USB3370 - Enhanced Single Supply Hi

USB3370 - Enhanced Single Supply Hi
USB3370
Enhanced Single Supply Hi-Speed
USB ULPI Transceiver
PRODUCT FEATURES
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Datasheet
USB-IF Battery Charging 1.1 Specification Compliant
Link Power Management (LPM) Specification
Compliant
Integrated ESD protection circuits
— Up to ±25kV IEC Air Discharge without external
devices
Over-Voltage Protection circuit (OVP) protects the
VBUS pin from continuous DC voltages up to 30V
SMSC RapidCharge Anywhere™ Provides:
— 3-times the charging current through a USB port
over traditional solutions
— USB-IF Battery Charging 1.1 compliance to any
portable device
— Charging current up to 1.5Amps via compatible
USB host or dedicated charger
— Dedicated Charging Port (DCP), Charging (CDP)
& Standard (SDP) Downstream Port support
flexPWR® Technology
— Extremely low current design ideal for battery
powered applications
— “Sleep” mode tri-states all ULPI pins and places
the part in a low current state
— 1.8V to 3.3V IO Voltage
Single Power Supply Operation
— Integrated 1.8V regulator
— Integrated 3.3V regulator
– 100mV dropout voltage
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PHYBoost
— Programmable USB transceiver drive strength for
recovering signal integrity
VariSenseTM
— Programmable USB receiver sensitivity
“Wrapper-less” design for optimal timing performance
and design ease
— Low Latency Hi-Speed Receiver (43 Hi-Speed
clocks Max) allows use of legacy UTMI Links with
a ULPI bridge
SMSC USB3370B
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External Reference Clock operation available
— ULPI Clock Input Mode (60MHz sourced by Link)
— 0 to 3.6V input drive tolerant
— Able to accept “noisy” clock sources as reference
to internal, low-jitter PLL
— Crystal support available
Smart detection circuits allow identification of USB
charger, headset, or data cable insertion
Includes full support for the optional On-The-Go
(OTG) protocol detailed in the On-The-Go
Supplement Revision 2.0 specification
Supports the OTG Host Negotiation Protocol (HNP)
and Session Request Protocol (SRP)
UART mode for non-USB serial data transfers
Internal 5V cable short-circuit protection of ID, DP
and DM lines to VBUS or ground
Industrial Operating Temperature -40°C to +85°C
32 pin, QFN lead-free RoHS Compliant package
(5 x 5x 0.90 mm height)
Applications
The USB3370 is the solution of choice for any
application where a Hi-Speed USB connection is desired
and when board space, power, and interface pins must
be minimized.
„ Cell Phones
„ PDAs
„ MP3 Players
„ GPS Personal Navigation
„ Scanners
„ External Hard Drives
„ Digital Still and Video Cameras
„ Portable Media Players
„ Entertainment Devices
„ Printers
„ Set Top Boxes
„ Video Record/Playback Systems
„ IP and Video Phones
„ Gaming Consoles
DATASHEET
Revision 1.0 (10-08-12)
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
Order Number(s):
ORDER NUMBER
REFCLK
FREQUENCY
USB3370B-EZK-TR
19.2 MHz
PACKAGE TYPE
REEL SIZE
32 Pin, QFN Lead-Free RoHS
Compliant Package (tape and reel)
4,000 pieces
This product meets the halogen maximum concentration values per IEC61249-2-21
For RoHS compliance and environmental information, please visit www.smsc.com/rohs
Please contact your SMSC sales representative for additional documentation related to this product
such as application notes, anomaly sheets, and design guidelines.
Copyright © 2012 SMSC or its subsidiaries. All rights reserved.
Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for
construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC
reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications
before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent
rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated
version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not
designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property
damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of
this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at http://www.smsc.com. SMSC is a registered
trademark of Standard Microsystems Corporation (“SMSC”). Product names and company names are the trademarks of their respective holders.
The Microchip name and logo, and the Microchip logo are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE
OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL
DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT;
TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD
TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Revision 1.0 (10-08-12)
2
DATASHEET
SMSC USB3370B
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
0.1
Reference Documents
UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1
Universal Serial Bus Specification, Revision 2.0
On-The-Go Supplement to the USB2.0 Specification, Revision 1.3
On-The-Go Supplement to the USB2.0 Specification, Revision 2.0
USB Battery Charging Specification, Revision 1.1
SMSC USB3370B
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DATASHEET
Revision 1.0 (10-08-12)
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
Table of Contents
0.1
Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Chapter 1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chapter 2 USB3370 Pin Locations and Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
USB3370 Pin Locations and Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.1
USB3370 Pin Diagram and Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chapter 3 Limiting Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.1
3.2
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Chapter 4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
Operating Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ULPI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital IO Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Characteristics: Analog I/O Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Dynamic Characteristics: Analog I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VBUS Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ID Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB Charger Detection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Regulator Output Voltages and Capacitor Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Piezoelectric Resonator for Internal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD and Latch-Up Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Chapter 5 Architecture Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
ULPI Digital Operation and Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB 2.0 Hi-Speed Transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.1
USB Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2.2
Termination Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bias Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Crystal Reference Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Integrated Low Jitter PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.1
REFCLK Frequency Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.2
REFCLK Amplitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.3
REFCLK Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5.4
REFCLK Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Regulators and POR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.1
Integrated Low Dropout Regulators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.2
Power On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.3
Recommended Power Supply Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.6.4
Start-Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB On-The-Go (OTG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.1
ID Resistor Detection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.2
VBUS Monitoring and VBUS Pulsing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.3
Driving External VBUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.7.4
External Vbus Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB UART Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB Charger Detection Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.9.1
Active Analog Charger Detection (USB-IF Battery Charging 1.1) . . . . . . . . . . . . . . . . . .
5.9.2
Resistive Charger Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision 1.0 (10-08-12)
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DATASHEET
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SMSC USB3370B
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
Chapter 6 ULPI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
ULPI Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.1
ULPI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.1.2
ULPI Interface Timing in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ULPI Register Access. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.1
Transmit Command Byte (TX CMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.2
ULPI Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.2.3
ULPI Register Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB3370 Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.1
ULPI Receive Command (RX CMD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.3.2
USB Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB3370 Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.1
USB3370 Host Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.4.2
Typical USB Transmit with ULPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.1
Entering Low Power/Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.2
Exiting Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.3
Link Power Management (LPM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.4
Interface Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.5.5
Minimizing Current in Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Full Speed/Low Speed Serial Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Carkit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6.7.1
Entering USB UART Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
RID Converter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
43
44
45
45
46
46
48
49
49
53
54
54
55
56
57
58
58
59
60
60
61
62
63
Chapter 7 ULPI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
7.1
ULPI Register Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.1
ULPI Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.2
Carkit Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.1.3
Vendor Register Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
64
65
70
72
Chapter 8 Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8.1
8.2
8.3
8.4
Application Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB Charger Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ESD Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4.1
Human Body Model (HBM) Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8.4.2
EN/IEC 61000-4-2 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
76
79
79
79
79
80
Chapter 9 Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Chapter 10 Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
SMSC USB3370B
5
DATASHEET
Revision 1.0 (10-08-12)
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
List of Figures
Figure 1.1
Figure 2.1
Figure 5.1
Figure 5.2
Figure 5.3
Figure 5.4
Figure 5.5
Figure 5.6
Figure 5.7
Figure 5.8
Figure 5.1
Figure 6.1
Figure 6.2
Figure 6.3
Figure 6.4
Figure 6.5
Figure 6.6
Figure 6.7
Figure 6.8
Figure 6.9
Figure 6.10
Figure 6.11
Figure 6.12
Figure 8.1
Figure 8.2
Figure 9.1
Figure 9.2
Figure 9.3
Figure 9.5
Figure 9.4
Block Diagram USB3370 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
USB3370 Pin Locations - Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
USB3370 System Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Configuring the USB3370 for ULPI Clock Input Mode (60 MHz) . . . . . . . . . . . . . . . . . . . . . . 28
Configuring the USB3370 for ULPI Clock Output Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Example of Circuit Used to Shift a Reference Clock Common-mode Voltage Level . . . . . . . 29
ULPI Start-up Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
USB3370 ID Resistor Detection Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
USB3370 OTG VBUS Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
USB3370 Drives Control Signal (CPEN_N) to External Vbus Switch . . . . . . . . . . . . . . . . . . 38
USB Charger Detection Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
ULPI Digital Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
ULPI Single Data Rate Timing Diagram in Synchronous Mode. . . . . . . . . . . . . . . . . . . . . . . 45
ULPI Register Write in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
ULPI Extended Register Write in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
ULPI Register Read in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
ULPI Extended Register Read in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
ULPI RXCMD Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
ULPI Receive in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
ULPI Transmit in Synchronous Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
LPM Token Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Entering Low Power Mode from Synchronous Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Exiting Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
USB3370 Application Diagram (Host configured for ULPI Clock Input Mode). . . . . . . . . . . . 77
USB3370 Application Diagram (Device configured for ULPI Clock Output Mode) . . . . . . . . 78
USB3370 32-pin QFN, 5x5mm Body, 0.5mm Pitch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
32QFN, 5x5 Tape and Reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
32QFN, 5x5 Reel Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
32QFN, 5x5 Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
32QFN Tape Length and Part Quantity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Revision 1.0 (10-08-12)
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DATASHEET
SMSC USB3370B
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
List of Tables
Table 2.1 USB3370 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3.2 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4.1 Operating Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4.2 Clock Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4.3 ULPI Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4.4 Digital IO Characteristics: RESETB, STP, DIR, NXT, DATA[7:0], and REFCLK Pins. . . . . . .
Table 4.5 DC Characteristics: Analog I/O Pins (DP/DM). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4.6 Dynamic Characteristics: Analog I/O Pins (DP/DM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4.7 VBUS Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4.8 ID Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4.9 USB Charger Detection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4.10 Regulator Output Voltages and Capacitor Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4.11 USB3370 Quartz Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4.12 ESD and Latch-Up Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5.1 DP/DM Termination vs. Signaling Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5.2 Operating Mode vs. Power Supply Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5.3 Valid Values of ID Resistance to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5.4 IdGnd and IdFloat vs. ID Resistance to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5.5 External VBUS Indicator Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5.6 Required RVBUS Resistor Value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5.7 External Vbus Indicator Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5.8 USB Charger Setting vs. Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5.9 USB Weak Pull-up Enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6.1 ULPI Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6.2 ULPI TX CMD Byte Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6.3 ULPI RX CMD Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6.4 USB Linestate Decoding in FS and LS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6.5 USB Linestate Decoding in HS Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6.6 USB Linestate Decoding in HS Chirp Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6.7 Interface Signal Mapping During Low Power Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6.8 Pin Definitions in 3 pin Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6.9 Pin Definitions in 6 pin Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6.10 Pin Definitions in Carkit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6.11 ULPI Register Programming Example to Enter UART Mode . . . . . . . . . . . . . . . . . . . . . . . . .
Table 7.1 ULPI Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8.1 Component Values in Application Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8.2 Capacitance Values at VBUS of USB Connector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 10.1 Customer Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMSC USB3370B
7
DATASHEET
10
13
13
15
16
16
17
17
19
20
20
21
21
22
22
25
31
33
33
36
37
38
41
42
44
46
51
52
52
52
57
60
61
62
62
64
76
76
85
Revision 1.0 (10-08-12)
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
Chapter 1 General Description
SMSC’s USB3370 is a family of Hi-Speed USB 2.0 Transceivers that provide a physical layer (PHY)
solution well-suited for portable electronic devices. Both commercial and industrial temperature
applications are supported.
Several advanced features make the USB3370 the transceiver of choice by reducing both eBOM part
count and printed circuit board (PCB) area. Outstanding ESD robustness eliminates the need for
external ESD protection devices in typical applications. The internal Over-Voltage Protection circuit
(OVP) protects the USB3370 from voltages up to 30V on the VBUS pin. By using a reference clock
from the Link, the USB3370 removes the cost of a dedicated crystal reference from the design. The
USB3370 includes integrated 3.3V and 1.8V regulators, making it possible to operate the device from
a single power supply.
The USB3370 is optimized for use in portable applications where a low operating current and standby
currents are essential. The USB3370 operates from a single supply and includes integrated regulators
for its supplies. The USB3370 also supports the USB Link Power Management protocol (LPM) to
further reduce USB operating currents.
The USB3370 also includes family is enabled with SMSC's RapidCharge AnywhereTM which supports
USB-IF Battery Charging 1.1 for any portable device. RapidCharge AnywhereTM provides three times
the charging current through a USB port over traditional solutions which translate up to 1.5Amps via
compatible USB host or dedicated charger. In addition, this provides a complete USB charging
ecosystem between device and host ports such as Dedicated Charging Port (DCP), Charging (CDP)
and Standard (SDP) Downstream Ports. Section 5.9 describes this is further detail.
The USB3370 meets all of the electrical requirements for a Hi-Speed USB Host, Device, or an On-theGo (OTG) transceiver. In addition to the supporting USB signaling, the USB3370 also provides USB
UART mode.
USB3370 uses the industry standard UTMI+ Low Pin Interface (ULPI) to connect the USB transceiver
to the Link. ULPI uses a method of in-band signaling and status byte transfers between the Link and
PHY to facilitate a USB session with only twelve pins.
The USB3370 uses SMSC’s “wrapper-less” technology to implement the ULPI interface. This “wrapperless” technology allows the PHY to achieve a low latency transmit and receive time. SMSC’s low
latency transceiver allows an existing UTMI Link to be reused by adding a UTMI to ULPI bridge. By
adding a bridge to the ASIC the existing and proven UTMI Link IP can be reused.
Revision 1.0 (10-08-12)
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DATASHEET
SMSC USB3370B
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
XO
REFCLK / XI
Datasheet
EXTVBUS
CPEN_N
OVP
ESD Protection
VBUS
ID
DP
DM
Low Jitter
Integrated
PLL
OTG
BC 1.1
Hi-Speed
USB
Transceiver
ULPI
Registers
and State
Machine
BIAS
Integrated
Power
Management
RBIAS
RESETB
VBAT
VDD33
VDD18
VDDIO
ULPI
Interface
STP
NXT
DIR
CLKOUT
DATA[7:0]
Figure 1.1 Block Diagram USB3370
The USB3370 includes an integrated 3.3V LDO regulator that is used to generate 3.3V from power
applied to the VBAT pin. The voltage on the VBAT pin can range from 3.0 to 5.5V. The regulator
dropout voltage is less than 100mV which allows the PHY to continue USB signaling when the voltage
on VBAT drops to 3.0V. The USB transceiver will continue to operate at lower voltages, although some
parameters may be outside the limits of the USB specifications. The VBAT and VDD33 pins should
never be connected together.
In USB UART mode, the USB3370 DP and DM pins are redefined to enable pass-through of
asynchronous serial data. The USB3370 will enter UART mode when programmed, as described in
Section 6.7.1.
SMSC USB3370B
9
DATASHEET
Revision 1.0 (10-08-12)
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
Chapter 2 USB3370 Pin Locations and Definitions
2.1
2.1.1
USB3370 Pin Locations and Descriptions
USB3370 Pin Diagram and Pin Definitions
DATA1
DATA2
VDDIO
NC
DATA3
CLKOUT
DATA4
DATA5
32
31
30
29
28
27
26
25
The illustration below is viewed from the top of the package.
DATA0
1
24
DATA6
VDDIO
2
23
DATA7
RBIAS
3
22
VDDIO
DM
4
21
NXT
DP
5
20
STP
EXTVBUS
6
19
DIR
ID
7
18
VDD18
17
RESETB
USB3300
32 Pin QFN
Hi-Speed
USB2
5x5 mm
ULPI
PHY
32 Pin QFN
GND FLAG
16
XO
13
VBUS
15
12
CPEN_N
REFCLK
11
VBAT
14
10
NC
VDD33
9
8
NC
GND
Figure 2.1 USB3370 Pin Locations - Top View
The following table details the pin definitions for the figure above.
Table 2.1 USB3370 Pin Descriptions
DIRECTION/
TYPE
ACTIVE
LEVEL
CLKOUT
Output,
CMOS
N/A
ULPI Clock Out Mode:
60MHz ULPI clock output. All ULPI signals are
driven synchronous to the rising edge of this clock.
ULPI Clock In Mode:
Connect this pin to VDDIO to configure 60MHz ULPI
Clock IN mode as described in Section 5.5.1.
NXT
Output,
CMOS
High
The PHY asserts NXT to throttle the data. When the
Link is sending data to the PHY, NXT indicates when
the current byte has been accepted by the PHY.
PIN
NAME
27
21
Revision 1.0 (10-08-12)
10
DESCRIPTION
DATASHEET
SMSC USB3370B
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
Table 2.1 USB3370 Pin Descriptions (continued)
DIRECTION/
TYPE
ACTIVE
LEVEL
DATA[0]
I/O,
CMOS
N/A
ULPI bi-directional data bus. DATA[0] is the LSB.
32
DATA[1]
I/O,
CMOS
N/A
ULPI bi-directional data bus.
31
DATA[2]
I/O,
CMOS
N/A
ULPI bi-directional data bus.
28
DATA[3]
I/O,
CMOS
N/A
ULPI bi-directional data bus.
26
DATA[4]
I/O,
CMOS
N/A
ULPI bi-directional data bus.
6
EXTVBUS
Input, CMOS
High
External Vbus Detect. Connect to fault output of an
external USB power switch or an external Vbus Valid
comparator. See Section 5.7.4, "External Vbus
Indicator," on page 38 for details. This pin has a pull
down resistor to prevent it from floating when the
ULPI bit UseExternalVbusIndicator is set to 0.
25
DATA[5]
I/O,
CMOS
N/A
ULPI bi-directional data bus.
24
DATA[6]
I/O,
CMOS
N/A
ULPI bi-directional data bus.
9
10
29
NC
N/A
N/A
No connect. Leave pin floating.
23
DATA[7]
I/O,
CMOS
N/A
ULPI bi-directional data bus. DATA[7] is the MSB.
12
CPEN_N
Output,
Open Drain
Low
External 5 volt supply enable. This pin is used to
enable the external Vbus power supply. The
CPEN_N pin is tri-stated on POR.
5
DP
I/O,
Analog
N/A
D+ pin of the USB cable.
4
DM
I/O,
Analog
N/A
D- pin of the USB cable.
14
VDD33
Power
N/A
3.3V Regulator Output. A 1.0uF (<1 ohm ESR)
bypass capacitor to ground is required for regulator
stability. The bypass capacitor should be placed as
close as possible to the USB3370.
11
VBAT
Power
N/A
Regulator input. The regulator supply can be from
5.5V to 3.0V.
13
VBUS
I/O,
Analog
N/A
This pin is used for the VBUS comparator inputs and
for VBUS pulsing during session request protocol.
An external resistor, RVBUS, is required between this
pin and the USB connector.
7
ID
Input,
Analog
N/A
For device applications the ID pin is connected to
VDD33. For Host applications ID is grounded. For
OTG applications the ID pin is connected to the USB
connector.
PIN
NAME
1
SMSC USB3370B
11
DESCRIPTION
DATASHEET
Revision 1.0 (10-08-12)
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
Table 2.1 USB3370 Pin Descriptions (continued)
DIRECTION/
TYPE
ACTIVE
LEVEL
RBIAS
Analog,
CMOS
N/A
Bias Resistor pin. This pin requires an 10kΩ (±1%)
resistor to ground, placed as close as possible to the
USB3370. Nominal voltage during ULPI operation is
0.8V.
XO
Output,
Analog
N/A
Crystal pin. If using an external clock on XI this pin
should be floated.
15
REFCLK
Input,
CMOS
N/A
ULPI Clock Out Mode:
Reference clock or XI (crystal in) pin.
ULPI Clock In Mode:
60MHz ULPI clock input.
17
RESETB
Input,
CMOS,
Low
When low, the part is suspended and the 3.3V and
1.8V regulators are disabled. When high, the
USB3370 will operate as a normal ULPI device, as
described in Section 5.6.2. The state of this pin may
be changed asynchronously to the clock signals.
When asserted for a minimum of 1 microsecond and
then de-asserted, the ULPI registers are reset to
their default state and all internal state machines are
reset.
18
VDD18
Power
N/A
1.8V Regulator Output. A 1.0uF (<1 ohm ESR)
bypass capacitor to ground is required for regulator
stability. The bypass capacitor should be placed as
close as possible to the USB3370.
20
STP
Input,
CMOS
High
The Link asserts STP for one clock cycle to stop the
data stream currently on the bus. If the Link is
sending data to the PHY, STP indicates the last byte
of data was on the bus in the previous cycle.
19
DIR
Output,
CMOS
N/A
Controls the direction of the data bus. When the PHY
has data to transfer to the Link, it drives DIR high to
take ownership of the bus. When the PHY has no
data to transfer it drives DIR low and monitors the
bus for commands from the Link.
Power
N/A
1.8V to 3.3V ULPI interface supply voltage.
Ground
N/A
Ground.
PIN
NAME
3
16
2
22
30
FLAG
8
DESCRIPTION
VDDIO
GND
Revision 1.0 (10-08-12)
12
DATASHEET
SMSC USB3370B
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
Chapter 3 Limiting Values
3.1
Absolute Maximum Ratings
Table 3.1 Absolute Maximum Ratings
PARAMETER
SYMBOL
VBUS, VBAT, and ID,
voltage to GND
VMAX_USB
DP and DM voltage to
GND
CONDITIONS
Voltage measured at pin.
VBUS tolerant to 30V with
external RVBUS.
MIN
TYP
MAX
UNITS
-0.5
6.0
V
VMAX_DPDM
-0.5
5.0
V
Maximum VDD18 voltage
to Ground
VMAX_18V
-0.5
2.5
V
Maximum VDD33 voltage
to Ground
VMAX_33V
-0.5
4.0
V
Maximum VDDIO voltage
to Ground
VMAX_IOV
-0.5
4.0
Maximum I/O voltage to
Ground
VMAX_IN
-0.5
VDDIO + 0.7
Maximum I/O voltage to
Ground (EXTVBUS,
CPEN_N)
VMAX_IN
-0.5
5.5V
Operating Temperature
TMAX_OP
-40
85
C
Storage Temperature
TMAX_STG
-55
150
C
Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. Exposure to absolute maximum rating conditions for extended periods
may affect device reliability.
3.2
Recommended Operating Conditions
Table 3.2 Recommended Operating Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
VBAT to GND
VBAT
3.0
VDD33 to GND
VDD33
3.0
VDD18 to GND
VDD18
VDDIO to GND
TYP
MAX
UNITS
5.5
V
3.3
3.6
V
1.6
1.8
2.0
V
VDDIO
1.6
1.8-3.3
3.6
V
Input Voltage on Digital
Pins (RESETB, STP,
DIR, NXT, DATA[7:0])
VI
0.0
VDDIO
V
Input Voltage on Digital
Pins (EXTVBUS,
CPEN_N)
VI
0.0
5.0
V
SMSC USB3370B
13
DATASHEET
Revision 1.0 (10-08-12)
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
Table 3.2 Recommended Operating Conditions (continued)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
Voltage on Analog I/O
Pins (DP, DM, ID)
VI(I/O)
0.0
VDD33
VBUS to GND
VVMAX
0.0
5.5
Ambient Temperature
TA
-40
85
Revision 1.0 (10-08-12)
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DATASHEET
C
SMSC USB3370B
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
Chapter 4 Electrical Characteristics
The following conditions are assumed unless otherwise specified:
VDD33 = 3.0 to 3.6V; VDD18 = 1.6 to 2.0V; VSS = 0V; TA = -40C to +85C
4.1
Operating Current
Table 4.1 Operating Current
PARAMETER
SYMBOL
Synchronous Mode Current
(Default Configuration)
Synchronous Mode Current
(HS USB operation)
Synchronous Mode Current
(FS/LS USB operation)
Serial Mode Current
(FS/LS USB)
Note 4.1
USB UART Current
Note 4.1
MIN
TYP
MAX
24
27
29
mA
2
3
7
mA
33
35
37
mA
5
6
14
mA
25
28.5
30
mA
IVIO(FS)
4
5
13
mA
IVBAT(FS_S)
7
8
9
mA
IVIO(FS_S)
0
0.1
0.7
mA
IVBAT(UART)
7
8
9
mA
IVIO(UART)
0
0.1
0.7
mA
VVBAT = 4.2V
VVDDIO = 1.8V
29
32
83
uA
0
0
2
uA
RESETB = 0
VVBAT = 4.2V
VVDDIO = 1.8V
0.1
1
12
uA
0
0
7
uA
IVBAT(SYNC)
CONDITIONS
USB Idle
IVIO(SYNC)
IVBAT(HS)
Active USB Transfer
IVIO(HS)
IVBAT(FS)
Low Power Mode
Note 4.2
Note 4.3
IVBAT(SUSPEND)
RESET Mode
Note 4.3
IVBAT(RSTB)
IVIO(SUSPEND)
IVIO(RSTB)
Active USB Transfer
UNITS
Note 4.1
ClockSuspendM bit = 0.
Note 4.2
SessEnd, VbusVld, and IdFloat comparators disabled. STP Interface protection disabled.
Note 4.3
REFCLK is OFF
SMSC USB3370B
15
DATASHEET
Revision 1.0 (10-08-12)
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
4.2
Clock Specifications
The model number for each frequency of REFCLK is provided in on page 2.
Table 4.2 Clock Specifications
PARAMETER
SYMBOL
Suspend Recovery Time
CONDITIONS
MIN
TYP
MAX
UNITS
1.1
1.32
ms
150
uS
1.32
ms
TSTART
LPM Enable = 0
1.0
TSTART_LPM
LPM Enable = 1
125
PHY Preparation Time
60MHz REFCLK
TPREP
LPM Enable = 0
1.0
TPREP_LPM
LPM Enable = 1
125
150
uS
CLKOUT Duty Cycle
DCCLKOUT
ULPI Clock Input Mode
45
55
%
REFCLK Duty Cycle
DCREFCLK
20
80
%
REFCLK Frequency Accuracy
FREFCLK
-500
+500
1.1
PPM
Note: TSTART and TPREP are measured from the time when REFCLK and RESETB are both valid to
when the USB3370 de-asserts DIR.
Note: The USB3370 uses the AutoResume feature, Section 6.4.1.4, to allow a host start-up time of
less than 1ms.
4.3
Note 4.4
REFCLK with oscillator Input
Note 4.5
Crystal Input
ULPI Interface Timing
Table 4.3 ULPI Interface Timing
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Setup time (STP, data in)
TSC, TSD
Model-specific REFCLK
5.0
ns
Hold time (STP, data in)
THC, THD
Model-specific REFCLK
0.0
ns
Output delay (control out, 8-bit data out)
TDC, TDD
Model-specific REFCLK
1.5
Setup time (STP, data in)
TSC, TSD
60MHz REFCLK
3
ns
Hold time (STP, data in)
THC, THD
60MHz REFCLK
0
ns
Output delay (control out, 8-bit data out)
TDC, TDD
60Mhz REFCLK
0.5
60MHz ULPI Output Clock Note 4.6
6
ns
60MHz ULPI Input Clock
6.0
ns
Note: CLoad = 10pF.
Note 4.6
Revision 1.0 (10-08-12)
REFCLK does not need to be aligned in any way to the ULPI signals.
16
DATASHEET
SMSC USB3370B
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
4.4
Digital IO Pins
Table 4.4 Digital IO Characteristics: RESETB, STP, DIR, NXT, DATA[7:0], and REFCLK Pins
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Low-Level Input Voltage
VIL
VSS
0.8
V
High-Level Input Voltage
VIH
0.68 *
VDDIO
VDDIO
V
High-Level Input Voltage
REFCLK and RESETB
VIH_REF
0.68 *
VDDIO
VDD33
V
Low-Level Output Voltage
VOL
IOL = 8mA
0.4
V
High-Level Output Voltage
VOH
IOH = -8mA
Output rise time
TIORISE
CLOAD = 10pF
1.19
nS
Output fall time
TIOFALL
CLOAD = 10pF
1.56
nS
Input Leakage Current
ILI
Pin Capacitance
Cpin
STP pull-up resistance
RSTP
InterfaceProtectDisable =
0
55
DATA[7:0] pull-down
resistance
RDATA_PD
ULPI Synchronous Mode
55
CLKOUT External Drive
VIH_ED
At start-up or following
reset
4.5
VDDIO 0.4
V
±10
uA
4
pF
67
80
kΩ
67
77
kΩ
0.4 *
VDDIO
V
MAX
UNITS
DC Characteristics: Analog I/O Pins
Table 4.5 DC Characteristics: Analog I/O Pins (DP/DM)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
LS/FS FUNCTIONALITY
Input levels
Differential Receiver Input
Sensitivity
VDIFS
Differential Receiver
Common-Mode Voltage
VCMFS
Single-Ended Receiver Low
Level Input Voltage
VILSE
Note 4.8
Single-Ended Receiver High
Level Input Voltage
VIHSE
Note 4.8
Single-Ended Receiver
Hysteresis
VHYSSE
| V(DP) - V(DM) |
0.2
0.8
V
2.5
V
0.8
V
2.0
0.050
V
0.150
V
Output Levels
SMSC USB3370B
17
DATASHEET
Revision 1.0 (10-08-12)
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
Table 4.5 DC Characteristics: Analog I/O Pins (DP/DM) (continued)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Low Level Output Voltage
VFSOL
Pull-up resistor on DP;
RL = 1.5kΩ to VDD33
0.3
V
High Level Output Voltage
VFSOH
Pull-down resistor on DP,
DM; Note 4.8
RL = 15kΩ to GND
2.8
3.6
V
Driver Output Impedance for
HS
ZHSDRV
Steady state drive
40.5
49.5
Ω
Input Impedance
ZINP
RX, RPU, RPD disabled
1.0
Pull-up Resistor Impedance
RPU
Bus Idle, Note 4.7
0.900
1.24
1.575
kΩ
Pull-up Resistor Impedance
RPU
Device Receiving,
Note 4.7
1.425
2.26
3.09
kΩ
Pull-dn Resistor Impedance
RPD
Note 4.7
14.25
16.9
20
kΩ
HS Differential Input
Sensitivity
VDIHS
| V(DP) - V(DM) |
100
HS Data Signaling Common
Mode Voltage Range
VCMHS
HS Squelch Detection
Threshold (Differential)
VHSSQ
HS Disconnect Threshold
VHSDSC
Termination
45
MΩ
HS FUNCTIONALITY
Input levels
VariSense[1:0] = 00b
Note 4.9
mV
-50
500
mV
100
150
mV
525
625
mV
Output Levels
High Speed Low Level
Output Voltage (DP/DM
referenced to GND)
VHSOL
45Ω load
-10
10
mV
High Speed High Level
Output Voltage (DP/DM
referenced to GND)
VHSOH
45Ω load
360
440
mV
High Speed IDLE Level
Output Voltage (DP/DM
referenced to GND)
VOLHS
45Ω load
-10
10
mV
Chirp-J Output Voltage
(Differential)
VCHIRPJ
HS termination resistor
disabled, pull-up resistor
connected. 45Ω load.
700
1100
mV
Chirp-K Output Voltage
(Differential)
VCHIRPK
HS termination resistor
disabled, pull-up resistor
connected. 45Ω load.
-900
-500
mV
±10
uA
Leakage Current
OFF-State Leakage Current
Revision 1.0 (10-08-12)
ILZ
18
DATASHEET
SMSC USB3370B
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
Table 4.5 DC Characteristics: Analog I/O Pins (DP/DM) (continued)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Port Capacitance
Transceiver Input
Capacitance
4.6
CIN
Pin to GND
5
10
pF
Note 4.7
The resistor value follows the 27% Resistor ECN published by the USB-IF.
Note 4.8
The values shown are valid when the USB RegOutput bits in the USB IO & Power
Management register are set to the default value.
Note 4.9
An automatic waiver up to 200mV is granted to accommodate system-level elements such
as measurement/test fixtures, captive cables, EMI components, and ESD suppression.
This parameter can be tuned using VariSense technology, as defined in Section 7.1.3.1of
Chapter 7.
Dynamic Characteristics: Analog I/O Pins
Table 4.6 Dynamic Characteristics: Analog I/O Pins (DP/DM)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
FS Output Driver Timing
FS Rise Time
TFR
CL = 50pF; 10 to 90% of
|VOH - VOL|
4
20
ns
FS Fall Time
TFF
CL = 50pF; 10 to 90% of
|VOH - VOL|
4
20
ns
Output Signal Crossover
Voltage
VCRS
Excluding the first
transition from IDLE state
1.3
2.0
V
Differential Rise/Fall Time
Matching
TFRFM
Excluding the first
transition from IDLE state
90
111.1
%
LS Rise Time
TLR
CL = 50-600pF;
10 to 90% of
|VOH - VOL|
75
300
ns
LS Fall Time
TLF
CL = 50-600pF;
10 to 90% of
|VOH - VOL|
75
300
ns
Differential Rise/Fall Time
Matching
TLRFM
Excluding the first
transition from IDLE state
80
125
%
LS Output Driver Timing
HS Output Driver Timing
Differential Rise Time
THSR
500
ps
Differential Fall Time
THSF
500
ps
Driver Waveform
Requirements
SMSC USB3370B
Eye pattern of Template 1
in USB 2.0 specification
19
DATASHEET
Revision 1.0 (10-08-12)
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
Table 4.6 Dynamic Characteristics: Analog I/O Pins (DP/DM) (continued)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
UNITS
High Speed Mode Timing
Receiver Waveform
Requirements
Eye pattern of Template 4
in USB 2.0 specification
Data Source Jitter and
Receiver Jitter Tolerance
Eye pattern of Template 4
in USB 2.0 specification
4.7
VBUS Electrical Characteristics
Table 4.7 VBUS Electrical Characteristics
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
SessEnd trip point
VSessEnd
0.2
0.5
0.8
V
SessVld trip point
VSessVld
0.8
1.4
2.0
V
VbusVld trip point
VVbusVld
4.4
4.58
4.75
V
VBUS Pull-Up
RVPU
VBUS to VDD33 Note 4.10
(ChargeVbus = 1)
1.29
1.34
1.45
kΩ
VBUS Pull-down
RVPD
VBUS to GND Note 4.10
(DisChargeVbus = 1)
1.55
1.7
1.85
kΩ
VBUS Impedance
RVB
VBUS to GND
40
75
100
kΩ
A-Device Impedance to
ground
RIdGnd
Maximum Impedance to
ground on ID pin
100
kΩ
Note 4.10 The RVPD and RVPU values include the required 1kΩ external RVBUS resistor.
4.8
ID Electrical Characteristics
Table 4.8 ID Electrical Characteristics
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ID Ground Trip Point
VIdGnd
0.4
0.7
0.9
V
ID Float Trip Point
VIdFloat
1.6
2.2
2.5
V
ID pull-up resistance
RID
IdPullup = 1
80
100
120
kΩ
ID weak pull-up resistance
RIDW
IdPullup = 0
1
ID pull-dn resistance
RIDPD
IdGndDrv = 1
Revision 1.0 (10-08-12)
20
DATASHEET
MΩ
1000
Ω
SMSC USB3370B
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
4.9
USB Charger Detection Characteristics
Table 4.9 USB Charger Detection Characteristics
PARAMETER
SYMBOL
Data Source Voltage
VDAT_SRC
Data Detect Voltage
CONDITIONS
TYP
MAX
UNITS
0.5
0.7
V
VDAT_REF
0.25
0.4
V
Data Source Current
IDAT_SRC
250
Data Sink Current
IDAT_SINK
50
150
uA
Data Connect Current
IDP_SRC
7
13
uA
Weak Pull-up Resistor
Impedance
RCD
4.10
IDAT_SRC < 250uA
MIN
Configured by bits 4 and 5
in USB IO & Power
Management register.
128
uA
170
212
kΩ
Regulator Output Voltages and Capacitor Requirement
Table 4.10 Regulator Output Voltages and Capacitor Requirement
PARAMETER
Regulator Output Voltage
SYMBOL
VDD33
Regulator Bypass Capacitor
COUT33
Bypass Capacitor ESR
CESR33
Regulator Output Voltage
VDD18
Regulator Bypass Capacitor
COUT18
Bypass Capacitor ESR
CESR18
SMSC USB3370B
CONDITIONS
MIN
TYP
MAX
5.5V > VBAT > 3.0V
2.8
3.3
3.6
V
USB UART Mode & UART
RegOutput[1:0] = 01
6V > VBAT > 3.0V
2.7
3.0
3.3
V
USB UART Mode & UART
RegOutput[1:0] = 10
6V > VBAT > 3.0V
2.47
2.75
3.03
V
USB UART Mode & UART
RegOutput[1:0] = 11
6V > VBAT > 3.0V
2.25
2.5
2.75
V
1.0
3.6V > VDD33 > 2.25V
1.6
uF
1.8
1
Ω
2.0
V
1.0
uF
1
21
DATASHEET
UNITS
Ω
Revision 1.0 (10-08-12)
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
4.11
Piezoelectric Resonator for Internal Oscillator
The internal oscillator may be used with an external quartz crystal or ceramic resonator as described
in Section 5.4. See Table 4.11 for the recommended crystal specifications.
Table 4.11 USB3370 Quartz Crystal Specifications
PARAMETER
SYMBOL
MIN
NOM
Crystal Cut
MAX
UNITS
NOTES
AT, typ
Crystal Oscillation Mode
Fundamental Mode
Crystal Calibration Mode
Parallel Resonant Mode
Frequency
Ffund
Total Allowable PPM Budget
-
See on
page 2
-
MHz
-
-
±500
PPM
Note 4.11
Shunt Capacitance
CO
-
7 typ
-
pF
Load Capacitance
CL
-
20 typ
-
pF
Drive Level
PW
0.1
-
-
mW
Equivalent Series Resistance
R1
-
-
30
Ohm
USB3370 REFCLK Pin
Capacitance
-
3 typ
-
pF
Note 4.12
USB3370 XO Pin Capacitance
-
3 typ
-
pF
Note 4.12
1M
-
-
Ohm
Note 4.13
Recommended Resistance
between XI and XO
Note 4.11 The required bit rate accuracy for Hi-Speed USB applications is ±500 ppm as provided in
the USB 2.0 Specification. This takes into account the effect of voltage, temperature, aging,
etc.
Note 4.12 This number includes the pad, the bond wire and the lead frame. Printed Circuit Board
(PCB) capacitance is not included in this value. The PCB capacitance value and the
capacitance value of the XO and REFCLK pins are required to accurately calculate the
value of the two external load capacitors.
Note 4.13 Refer to Section 5.4 and Figure 8.1 for more information.
4.12
ESD and Latch-Up Performance
Table 4.12 ESD and Latch-Up Performance
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
COMMENTS
ESD PERFORMANCE
Note 4.14
Human Body Model
±8
kV
Device
System
EN/IEC 61000-4-2 Contact
Discharge
±25
kV
3rd party system test
System
EN/IEC 61000-4-2 Air-gap
Discharge
±25
kV
3rd party system test
Revision 1.0 (10-08-12)
22
DATASHEET
SMSC USB3370B
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
Table 4.12 ESD and Latch-Up Performance (continued)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
COMMENTS
LATCH-UP PERFORMANCE
All Pins
EIA/JESD 78, Class II
150
mA
Note 4.14 REFCLK, XO, ID, and RESETB pins: ±5kV Human Body Model.
SMSC USB3370B
23
DATASHEET
Revision 1.0 (10-08-12)
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
Chapter 5 Architecture Overview
The USB3370 consists of the blocks shown in the diagram below.
EXTVBUS
CPEN_N
VDD33
RID
VDD33
TX Data
RVPU
RVB
RVPD
VbusValid
LDO
RPU
VDD33
RCD
VDD18
SessEnd
SessValid
LDO
RCD
VDD33
ESD Protection
VBAT
OVP
RPU
VBUS
ULPI
Digitial
RX Data
Rid Value
Digital IO
IdFloat
ID
OTG Module
RIDW
IdGnd
TX
DP
HS/FS/LS
TX Encoding
Integrated
Low Jitter
PLL
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
STP
NXT
DIR
CLKOUT
RESETB
VDDIO
REFCLK / XI
XO
RPD
RPD
DM
RX
HS/FS/LS
RX Decoding
BIAS
RBIAS
Figure 5.1 USB3370 System Diagram
5.1
ULPI Digital Operation and Interface
This section of the USB3370 is covered in detail in Chapter 6, ULPI Operation.
5.2
USB 2.0 Hi-Speed Transceiver
The blocks in the lower left-hand corner of interface to the DP/DM pins.
5.2.1
USB Transceiver
The USB3370 transceiver includes a Universal Serial Bus Specification Rev 2.0 compliant receiver and
transmitter. The DP/DM signals in the USB cable connect directly to the receivers and transmitters.
The receiver consists of receivers for HS and FS/LS mode. Depending on the mode, the selected
receiver provides the serial data stream through the multiplexer to the RX Logic block. For HS mode
support, the HS RX block contains a squelch circuit to insure that noise is not interpreted as data. The
RX block also includes a single-ended receiver on each of the data lines to determine the correct FS
linestate.
Revision 1.0 (10-08-12)
24
DATASHEET
SMSC USB3370B
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
Data from the Link is encoded, bit stuffed, serialized and transmitted onto the USB cable by the
transmitter. Separate differential FS/LS and HS transmitters are included to support all modes.
The USB3370 TX block meets the HS signalling level requirements in the USB 2.0 Specification when
the PCB traces from the DP and DM pins to the USB connector are correctly designed. In some
systems the proper 90 ohm differential impedance can not be maintained and it may be desirable to
compensate for loss by adjusting the HS transmitter amplitude and this HS squelch threshold. The
PHYBoost bits in the HS Compensation Register may be configured to adjust the HS transmitter
amplitude at the DP and DM pins. The VariSense bits in the HS Compensation Register can also be
used to lower the squelch threshold to compensate for losses on the PCB.
To ensure proper operation of the USB transceiver the settings of Table 5.1 must be followed.
5.2.2
Termination Resistors
The USB3370 transceiver fully integrates all of the USB termination resistors on both DP and DM. This
includes 1.5kΩ pull-up resistors, 15kΩ pull-down resistors and the 45Ω High Speed termination
resistors. These resistors require no tuning or trimming by the Link. The state of the resistors is
determined by the operating mode of the transceiver when operating in synchronous mode.
The XcvrSelect[1:0], TermSelect and OpMode[1:0] bits in the Function Control register, and the
DpPulldown and DmPulldown bits in the OTG Control register control the configuration of the
termination resistors. All possible valid resistor combinations are shown in Table 5.1, and operation is
guaranteed in only the configurations shown. If a ULPI Register Setting is configured that does not
match a setting in the table, the transceiver operation is not guaranteed and the settings in the last
row of Table 5.1 will be used.
„
RPU_DP_EN activates the 1.5kΩ DP pull-up resistor
„
RPU_DM_EN activates the 1.5kΩ DM pull-up resistor
„
RPD_DP_EN activates the 15kΩ DP pull-down resistor
„
RPD_DM_EN activates the 15kΩ DM pull-down resistor
„
HSTERM_EN activates the 45Ω DP and DM High Speed termination resistors
Table 5.1 DP/DM Termination vs. Signaling Mode
RPD_DP_EN
RPD_DM_EN
HSTERM_EN
Xb
01b
Xb
Xb
0b
0b
0b
0b
0b
Power-up or VBUS < VSESSEND
01b
0b
00b
1b
1b
0b
0b
1b
1b
0b
Host Chirp
00b
0b
10b
1b
1b
0b
0b
1b
1b
1b
Host High Speed
00b
0b
00b
1b
1b
0b
0b
1b
1b
1b
Host Full Speed
X1b
1b
00b
1b
1b
0b
0b
1b
1b
0b
TermSelect
DmPulldown
XXb
DpPulldown
Tri-State Drivers, Note 5.1
SIGNALING MODE
OpMode[1:0]
RPU_DM_EN
USB3370 TERMINATION
RESISTOR SETTINGS
RPU_DP_EN
XcvrSelect[1:0]
ULPI REGISTER SETTINGS
General Settings
Host Settings
SMSC USB3370B
25
DATASHEET
Revision 1.0 (10-08-12)
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
Table 5.1 DP/DM Termination vs. Signaling Mode (continued)
RPD_DP_EN
RPD_DM_EN
HSTERM_EN
1b
00b
1b
1b
0b
0b
1b
1b
0b
Host HS/FS Resume
01b
1b
10b
1b
1b
0b
0b
1b
1b
0b
Host Low Speed
10b
1b
00b
1b
1b
0b
0b
1b
1b
0b
Host LS Suspend
10b
1b
00b
1b
1b
0b
0b
1b
1b
0b
Host LS Resume
10b
1b
10b
1b
1b
0b
0b
1b
1b
0b
Host Test J/Test_K
00b
0b
10b
1b
1b
0b
0b
1b
1b
1b
Peripheral Chirp
00b
1b
10b
0b
0b
1b
0b
0b
0b
0b
Peripheral HS
00b
0b
00b
0b
0b
0b
0b
0b
0b
1b
Peripheral FS
01b
1b
00b
0b
0b
1b
0b
0b
0b
0b
Peripheral HS/FS Suspend
01b
1b
00b
0b
0b
1b
0b
0b
0b
0b
Peripheral HS/FS Resume
01b
1b
10b
0b
0b
1b
0b
0b
0b
0b
Peripheral LS
10b
1b
00b
0b
0b
0b
1b
0b
0b
0b
Peripheral LS Suspend
10b
1b
00b
0b
0b
0b
1b
0b
0b
0b
Peripheral LS Resume
10b
1b
10b
0b
0b
0b
1b
0b
0b
0b
Peripheral Test J/Test K
00b
0b
10b
0b
0b
0b
0b
0b
0b
1b
OTG device, Peripheral Chirp
00b
1b
10b
0b
1b
1b
0b
0b
1b
0b
OTG device, Peripheral HS
00b
0b
00b
0b
1b
0b
0b
0b
1b
1b
OTG device, Peripheral FS
01b
1b
00b
0b
1b
1b
0b
0b
1b
0b
OTG device, Peripheral HS/FS Suspend
01b
1b
00b
0b
1b
1b
0b
0b
1b
0b
OTG device, Peripheral HS/FS Resume
01b
1b
10b
0b
1b
1b
0b
0b
1b
0b
OTG device, Peripheral Test J/Test K
00b
0b
10b
0b
1b
0b
0b
0b
1b
1b
01b
0b
00b
0b
1b
0b
0b
0b
1b
0b
0b
0b
1b
1b
0b
TermSelect
DmPulldown
01b
DpPulldown
Host HS/FS Suspend
SIGNALING MODE
OpMode[1:0]
RPU_DM_EN
USB3370 TERMINATION
RESISTOR SETTINGS
RPU_DP_EN
XcvrSelect[1:0]
ULPI REGISTER SETTINGS
Peripheral Settings
Charger Detection
Connect Detect
Any combination not defined above,
Note 5.2
Note: This is equivalent to Table 40, Section 4.4 of the ULPI 1.1 specification.
Note: USB3370 does not support operation as an upstream hub port. See Chapter 6.4.1.3.
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Datasheet
Note 5.1
When RESETB = 0 The HS termination will tri-state the USB drivers
Note 5.2
The transceiver operation is not guaranteed in a combination that is not defined.
The USB3370 uses the 27% resistor ECN resistor tolerances. The resistor values are shown in
Table 4.5.
5.3
Bias Generator
This block consists of an internal bandgap reference circuit used for generating the driver current and
the biasing of the analog circuits. This block requires an external 10KΩ, 1% tolerance, reference
resistor connected from RBIAS to ground. This resistor should be placed as close as possible to the
USB3370 to minimize the trace length. The nominal voltage at RBIAS is 0.8V +/- 10% and therefore
the resistor will dissipate approximately 80μW of power.
5.4
Crystal Reference Support
The USB3370 provides support for a crystal to provide the reference frequency required by the device
in place of a clock oscillator. The crystal should be connected to the REFCLK/XI and XO pins. If a
clock oscillator is used in place of a crystal, it should be driven into the REFCLK/XI pin, and the XO
pin should be left floating. Proper care should be taken to ensure that a crystal is selected with
appropriate power dissipation characteristics.
5.5
Integrated Low Jitter PLL
The USB3370 uses an integrated low jitter phase locked loop (PLL) to provide a clean 480MHz clock
required for HS USB signal quality. This clock is used by the PHY during both transmit and receive.
The USB3370 PLL requires an accurate frequency reference to be driven on the REFCLK pin.
5.5.1
REFCLK Frequency Selection
The USB3370 PLL is designed to operate in one of two reference clock modes. In the first mode, the
60MHz ULPI clock is driven on the REFCLK pin. In the second mode a reference clock is driven on
the REFCLK pin. The Link is driving the ULPI clock, in the first mode, and this is referred to as ULPI
Clock Input Mode. In the second mode, the USB3370 generates the ULPI clock, and this is referred
to as ULPI Clock Output Mode.
During start-up, the USB3370 monitors the CLKOUT pin. If a connection to VDDIO is detected, the
USB3370 is configured for a 60MHz ULPI reference clock driven on the REFCLK pin. Section 5.5.1.1
and Section 5.5.1.2 describe how to configure the USB3370 for either ULPI Clock Input Mode or ULPI
Clock Output Mode.
5.5.1.1
ULPI Clock Input Mode (60MHz REFCLK Mode)
When using ULPI Clock Input Mode, the Link must supply the 60MHz ULPI clock to the USB3370. In
this mode the 60MHz ULPI Clock is connected to the REFCLK pin, and the CLKOUT pin is tied high
to VDDIO.
After the PLL has locked to the correct frequency, the USB3370 will de-assert DIR and the Link can
begin using the ULPI interface. The USB3370 is guaranteed to start the clock within the time specified
in Table 4.2. For Host applications, the ULPI AutoResume bit should be enabled. This is described in
Section 6.4.1.4.
For the USB3370, the REF pins should be tied to ground.
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VDD18/
VDDIO
~~
CLKOUT
REFCLK
ULPI Clk Out
To PLL
Link
Reference Clk In
~~
Clock
Source
SMSC PHY
Figure 5.2 Configuring the USB3370 for ULPI Clock Input Mode (60 MHz)
5.5.1.2
ULPI Clock Output Mode
When using ULPI Clock Output Mode, the USB3370 generates the 60MHz ULPI clock used by the
Link. In this mode, the REFCLK pin must be driven with the model-specific frequency, and the
CLKOUT pin sources the 60MHz ULPI clock to the Link. When using ULPI Clock Output Mode, the
system must not drive the CLKOUT pin following POR or hardware reset with a voltage that exceeds
the value of VIH_ED provided in Table 4.3. An example of ULPI Clock Output Mode is shown in
Figure 8.1
After the PLL has locked to the correct frequency, the USB3370 generates the 60MHz ULPI clock on
the CLKOUT pin, and de-asserts DIR to indicate that the PLL is locked. The USB3370 is guaranteed
to start the clock within the time specified in Table 4.2, and it will be accurate to within ±500ppm. For
Host applications the ULPI AutoResume bit should be enabled. This is described in Section 6.4.1.4.
When using ULPI Clock Output Mode, the edges of the reference clock do not need to be aligned in
any way to the ULPI interface signals. There is no need to align the phase of the REFCLK and the
CLKOUT.
~~
ULPI Clk In
CLKOUT
From PLL
Link
Clock
Source
REFCLK
To PLL
SMSC PHY
~~
Figure 5.3 Configuring the USB3370 for ULPI Clock Output Mode
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Enhanced Single Supply Hi-Speed USB ULPI Transceiver
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5.5.2
REFCLK Amplitude
The reference clock should be connected to the REFCLK pin as shown in the application diagrams,
Figure 8.1. The REFCLK pin is designed to be driven with a square wave from 0V to VDDIO, but can
be driven with a square wave from 0V to as high as 3.6V. The USB3370 uses only the positive edge
of the REFCLK.
If a digital reference is not available, the REFCLK pin can be driven by an analog sine wave that is
AC coupled into the REFCLK pin. If using an analog clock the DC bias should be set at the mid-point
of the VDD18 supply using a bias circuit as shown in Figure 5.4. The amplitude must be greater than
300mV peak to peak. The component values provided in Figure 5.4 are for example only. The actual
values should be selected to satisfy system requirements.
The REFCLK amplitude must comply with the signal amplitudes shown in Table 4.4 and the duty cycle
in Table 4.2.
47k
1.8V Supply
To REFCLK pin
0.1uF
47k
Clock
Figure 5.4 Example of Circuit Used to Shift a Reference Clock Common-mode Voltage Level
5.5.3
REFCLK Jitter
The USB3370 is tolerant to jitter on the reference clock. The REFCLK jitter should be limited to a peak
to peak jitter of less than 1nS over a 10uS time interval. If this level of jitter is exceeded when
configured for either ULPI Clock Input Mode or ULPI Clock Output Mode, the USB3370 High Speed
eye diagram may be degraded.
The frequency accuracy of the REFCLK must meet the +/- 500ppm requirement as shown in Table 4.2.
5.5.4
REFCLK Enable/Disable
The REFCLK should be enabled when the RESETB pin is brought high. The ULPI interface will start
running after the time specified in Table 4.2. If the reference clock enable is delayed relative to the
RESETB pin, the ULPI interface will start operation delayed by the same amount. The reference clock
can be run at anytime the RESETB pin is low without causing the USB3370 to start-up or draw current.
When the USB3370 is placed in Low Power Mode or Carkit Mode, the reference clock can be stopped
after the final ULPI register write is complete. The STP pin is asserted to bring the USB3370 out of
Low Power Mode. The reference clock should be started at the same time STP is asserted to minimize
the USB3370 start-up time.
If the reference clock is stopped while in ULPI Synchronous mode the PLL will come out of lock and
the frequency of oscillation will decrease to the minimum allowed by the PLL design. If the reference
clock is stopped during a USB session, the session may drop.
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5.6
Internal Regulators and POR
The USB3370 includes integrated power management functions, including a Low-Dropout regulator
that can be used to generate the 3.3V USB supply, an integrated 1.8V regulator, and a POR generator
described in Section 5.6.2.
5.6.1
Integrated Low Dropout Regulators
The USB3370 includes two integrated linear regulators. Power sourced at the VBAT pin is regulated
to 3.3V and 1.8V output on the VDD33 and VDD18 pins. To ensure stability, both regulators require
an external bypass capacitor as specified in Table 4.10 placed as close to the pin as possible.
The USB3370 regulators are designed to generate the 3.3 Volt and 1.8 Volt supplies for the USB3370
only. Using the regulators to provide current for other circuits is not recommended and SMSC does
not guarantee USB performance or regulator stability.
During USB UART mode the 3.3V regulator output voltage can be changed to allow the USB3370 to
work with UARTs operating at different operating voltages. The 3.3V regulator output is configured to
the voltages shown in Table 4.10 with the UART RegOutput[1:0] bits in the USB IO & Power
Management register.
The regulators are enabled by the RESETB pin. When RESETB pin is low both regulators are disabled
and the regulator outputs are pulled low by weak pull-down. The RESETB pin must be brought high
to enable the regulators.
For peripheral-only or host-only bus-powered applications, the input to VBAT may be derived from the
VBUS pin of the USB connector. In this configuration, the supply must be capable of withstanding any
transient voltage present at the VBUS pin of the USB connector. SMSC does not recommend
connecting the VBAT pin to the VBUS terminal of the USB connector.
5.6.2
Power On Reset (POR)
The USB3370 provides a POR circuit that generates an internal reset pulse after the VDD18 supply
is stable. After the internal POR goes high the USB3370 will release from reset and begin normal ULPI
operation as described in Section 5.6.4.
The ULPI registers will power up in their default state summarized in Table 7.1 when the 1.8V supply
comes up. Cycling the RESETB pin can also be used to reset the ULPI registers to their default state
(and reset all internal state machines) by bringing the pin low for a minimum of 1 microsecond and
then high. It is not necessary to wait for the VDD33 and VDD18 pins to discharge to 0 volts to reset
the part.
The RESETB pin must be pulled high to enable the 3.3V and 1.8V regulators. A pull-down resistor is
not present on the RESETB pin and therefore the system should drive the RESETB pin to the desired
state at all times. If the system does not need to place the USB3370 into reset mode the RESETB pin
can be connected to a supply between 1.8V and 3.3V.
5.6.3
Recommended Power Supply Sequence
For USB operation, the USB3370 requires a valid voltage on the VBAT and VDDIO pins. The VDD33
and VDD18 regulators are automatically enabled when the RESETB pin is brought high. For the
USB3343, Table 5.2 presents the power supply configurations in more detail.
The RESETB pin can be held low until the VBAT supply is stable. If the Link is not ready to interface
the USB3370, the Link may choose to hold the RESETB pin low until it is ready to control the ULPI
interface.
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Table 5.2 Operating Mode vs. Power Supply Configuration
VBAT
VDDIO
RESETB
0
0
0
Powered Off
1
X
0
RESET Mode. (Note 5.3)
1
1
1
Full USB operation as described in Chapter 6.
Note 5.3
5.6.4
OPERATING MODES AVAILABLE
VDDIO must be present for ULPI pins to tri-state.
Start-Up
The power on default state of the USB3370 is ULPI Synchronous mode. The USB3370 requires the
following conditions to begin operation: the power supplies must be stable, the REFCLK must be
present and the RESETB pin must be high. After these conditions are met, the USB3370 will begin
ULPI operation that is described in Chapter 6.
Figure 5.5 below shows a timing diagram to illustrate the start-up of the USB3370. At T0, the supplies
are stable and the USB3370 is held in reset mode. At T1, the Link drives RESETB high after the
REFCLK has started. The RESETB pin may be brought high asynchronously to REFCLK. Once, the
3.3V and 1.8V internal supplies become stable the USB3370 will apply the 15Kohm pull downs to the
data bus and assert DIR until the internal PLL has locked. After the PLL has locked, the USB3370 will
check that the Link has de-asserted STP and at T2 it will de-assert DIR and begin ULPI operation.
The ULPI bus will be available as shown in Figure 5.5 in the time defined as TSTART given in Table 4.2.
If the REFCLK signal starts after the RESETB pin is brought high, then time T0 will begin when
REFCLK starts. TSTART also assumes that the Link has de-asserted STP. If the Link has held STP
high the USB3370 will hold DIR high until STP is de-asserted. When the LINK de-asserts STP, it must
be ready drive the ULPI data bus to idle (00h) for a minimum of one clock cycle after DIR de-asserts.
T0
SUPPLIES
STABLE
REFCLK
T1
T2
REFCLK valid
RESETB
DATA[7:0]
PHY Tri-States
PHY Drives Idle
DIR
PHY Tri-States
PHY Drives High
STP
IDLE
RXCMD
IDLE
LINK Drives Low
TSTART
Figure 5.5 ULPI Start-up Timing
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5.7
USB On-The-Go (OTG)
The USB3370 provides support for the USB OTG protocol. OTG allows the USB3370 to be
dynamically configured as a host or peripheral depending on the type of cable inserted into the MicroAB receptacle. When the Micro-A plug of a cable is inserted into the Micro-AB receptacle, the USB
device becomes the A-device. When a Micro-B plug is inserted, the device becomes the B-device. The
OTG A-device behaves similar to a Host while the B-device behaves similar to a peripheral. The
differences are covered in the “On-The-Go Supplement to the USB 2.0 Specification”. In applications
where only USB Host or USB Peripheral is required, the OTG Module is unused.
5.7.1
ID Resistor Detection
The ID pin of the USB connector is monitored by the ID pin of the USB3370 to detect the attachment
of different types of USB devices and cables. For device only applications that do not use the ID signal
the ID pin should be connected to VDD33. The block diagram of the ID detection circuitry is shown in
Figure 5.6 and the related parameters are given in Table 4.8.
~~
VDD33
ID
To USB Con.
RID=100K
RIDW>1M
IdPullup
IdGnd
Vref IdGnd
en
IdGndDrv
IdGnd Rise or
IdGnd Fall
IdFloat
Vref IdFloat
en
Rid ADC
IdFloatRise or
IdFloatFall
RidValue
OTG Module
~~
Figure 5.6 USB3370 ID Resistor Detection Circuitry
5.7.1.1
USB OTG Operation
The USB3370 can detect ID grounded and ID floating to determine if an A or B cable has been
inserted. The A plug will ground the ID pin while the B plug will float the ID pin. These are the only
two valid states allowed in the OTG Protocol.
To monitor the status of the ID pin, the Link activates the IdPullup bit in the OTG Control register, waits
50mS and then reads the status of the IdGnd bit in the USB Interrupt Status register. If an A cable has
been inserted the IdGnd bit will read 0. If a B cable is inserted, the ID pin is floating and the IdGnd bit
will read 1.
The USB3370 provides an integrated weak pull-up resistor on the ID pin, RIDW. This resistor is present
to keep the ID pin in a known state when the IdPullup bit is disabled and the ID pin is floated. In
addition to keeping the ID pin in a known state, it enables the USB3370 to generate an interrupt to
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inform the link when a cable with a resistor to ground has been attached to the ID pin. The weak pullup is small enough that the largest valid RID resistor pulls the ID pin low and causes the IdGnd
comparator to go low.
After the link has detected an ID pin state change, the RID converter can be used to determine the
resistor value as described in Section 5.7.1.2.
5.7.1.2
Measuring ID Resistance to Ground
The Link can use the integrated resistance measurement capabilities of the USB3370 to determine the
value of an ID resistance to ground. The following table details the valid values of resistance to ground
that the USB3370 can detect.
Table 5.3 Valid Values of ID Resistance to Ground
ID RESISTANCE TO GROUND
RID VALUE
Ground
000
75Ω +/-1%
001
102kΩ +/-1%
010
200kΩ+/-1%
011
Floating
101
Note: IdPullUp = 0
The ID resistance to ground can be read while the USB3370 is in Synchronous Mode. When a resistor
to ground is attached to the ID pin, the state of the IdGnd comparator will change. After the Link has
detected ID transition to ground, it can use the methods described in Section 6.8 to operate the Rid
converter.
5.7.1.3
Using IdFloat Comparator (not recommended)
Note: The ULPI specification details a method to detect a 102kΩ resistance to ground using the
IdFloat comparator. This method can only detect 0ohms, 102kΩ, and floating terminations of
the ID pin. Due to this limitation it is recommended to use the RID Converter as described in
Section 5.7.1.2.
The ID pin can be either grounded, floated, or connected to ground with a 102kΩ external resistor. To
detect the 102K resistor, set the idPullup bit in the OTG Control register, causing the USB3370 to apply
the 100K internal pull-up connected between the ID pin and VDD33. Set the idFloatRise and idFloatFall
bits in the Carkit Interrupt Enable register to enable the IdFloat comparator to generate an RXCMD to
the Link when the state of the IdFloat changes. As described in Figure 6.3, the alt_int bit of the RXCMD
will be set. The values of IdGnd and IdFloat are shown for the three types cables that can attach to
the USB Connector in Table 5.4.
Table 5.4 IdGnd and IdFloat vs. ID Resistance to Ground
SMSC USB3370B
ID RESISTANCE
IDGND
IDFLOAT
Float
1
1
102K
1
0
GND
0
0
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Datasheet
Note: The ULPI register bits IdPullUp, IdFloatRise, and IdFloatFall should be enabled.
To save current when an A Plug is inserted, the internal 102kΩ pull-up resistor can be disabled by
clearing the IdPullUp bit in the OTG Control register and the IdFloatRise and IdFloatFall bits in both
the USB Interrupt Enable Rising and USB Interrupt Enable Falling registers. If the cable is removed
the weak RIDW will pull the ID pin high.
The IdGnd value can be read using the ULPI USB Interrupt Status register, bit 4. In host mode, it can
be set to generate an interrupt when IdGnd changes by setting the appropriate bits in the USB Interrupt
Enable Rising and USB Interrupt Enable Falling registers. The IdFloat value can be read by reading
the ULPI Carkit Interrupt Status register bit 0.
Note: The IdGnd switch has been provided to ground the ID pin for future applications.
5.7.2
VBUS Monitoring and VBUS Pulsing
The USB3370 includes all of the VBUS comparators required for OTG. The VBUSVld, SessVld, and
SessEnd comparators shown in Figure 5.7 are fully integrated into the USB3370. These comparators
are used to monitor changes in the VBUS voltage, and the state of each comparator can be read from
the USB Interrupt Status register.
The VbusVld comparator is used by the Link, when configured as an A device, to ensure that the
VBUS voltage on the cable is valid. The SessVld comparator is used by the Link when configured as
both an A or B device to indicate a session is requested or valid. Finally the SessEnd comparator is
used by the B-device to indicate a USB session has ended.
Also included in the VBUS Monitor and Pulsing block are the resistors used for VBUS pulsing in SRP.
The resistors used for VBUS pulsing include a pull-down to ground and a pull-up to VDD33.
In some applications, voltages much greater than 5.5V may be present at the VBUS pin of the USB
connector. The USB3370 includes an over voltage protection circuit that protects the VBUS pin of the
USB3370 from excessive voltages as shown in Figure 5.7.
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Datasheet
~~
VDD33
ChrgVbus
0.5V
SessEnd
VBUS
Overvoltage
Protection
RVB
RVBUS
SessEnd Rise or
SessEnd Fall
SessValid
1.4V
RVPD
VBUS
To USB Con.
RVPU
en
VbusValid
4.575V
DischrgVbus
en
VbusValid Rise or
VbusValid Fall
[0, X]
[1, 0]
EXTVBUS
IndicatorComplement
RXCMD VbusValid
[1, 1]
[UseExternalVbusindicator, IndicatorPassThru]
SMSC PHY
~~
Figure 5.7 USB3370 OTG VBUS Block
5.7.2.1
SessEnd Comparator
The SessEnd comparator is used during the Session Request Protocol (SRP). The comparator is used
by the B-device to detect when a USB session has ended and it is safe to start Vbus Pulsing to request
a USB session from the A-device. When VBUS goes below the threshold in Table 4.7, the USB session
is considered to be ended, and SessEnd will transition from 0 to 1. The SessEnd comparator can be
disabled by clearing this bit in both the USB Interrupt Enable Rising and USB Interrupt Enable Falling
registers. When disabled, the SessEnd bit in the USB Interrupt Status register will read 0.
The SessEnd Comparator is only used when configured as an OTG device. If the USB3370 is used
as a Host or Device only the SessEnd Comparator should be disabled, using the method described
above.
5.7.2.2
SessVld Comparator
The SessVld comparator is used when the PHY is configured as both an A and B device. When
configured as an A device, the SessVld is used to detect Session Request protocol (SRP). When
configured as a B device, SessVld is used to detect the presence of VBUS. The SessVld comparator
output can also be read from the USB Interrupt Status register. The SessVld comparator will also
generate an RX CMD, as detailed in Section 6.3.1, anytime the comparator changes state. The
SessVld interrupts can be disabled by clearing this bit in both the USB Interrupt Enable Rising and
USB Interrupt Enable Falling registers. When the interrupts are disabled, the SessVld comparator is
still operational and will generate RX CMD’s. The SessVld comparator trip point is detailed in Table 4.8.
Note: The OTG Supplement specifies a voltage range for A-Device Session Valid and B-Device
Session Valid comparator. The USB3370 PHY combines the two comparators into one and
uses the narrower threshold range.
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5.7.2.3
VbusVld Comparator
The VbusVld comparator is only used when the USB3370 is configured as a host that can supply less
than 100mA VBUS current. In the USB protocol, the A-device supplies the VBUS voltage and is
responsible to ensure it remains within a specified voltage range. The VbusVld comparator can be
disabled by clearing this bit in both the USB Interrupt Enable Rising and USB Interrupt Enable Falling
registers. When disabled, bit 1 of the USB Interrupt Status register will return a 0. The VbusVld
comparator threshold values are detailed in Table 4.8.
If the USB3370 is used as a Device only the VbusValid Comparator should be disabled, using the
method described above.
The USB3370 includes the external VbusVld indicator logic as detailed in the ULPI Specification. The
external VbusVld indicator is tied to a logic one. The decoding of this logic is shown in Table 5.5 below.
By default this logic is disabled.
Table 5.5 External VBUS Indicator Logic
TYPICAL
APPLICATION
USE
EXTERNAL
VBUS
INDICATOR
INDICATOR
PASS THRU
INDICATOR
COMPLEMENT
OTG Device
0
X
X
Internal VbusVld comparator (Default)
1
1
0
Fixed 1
1
1
1
Fixed 0
1
0
0
Internal VbusVld comparator.
1
0
1
Fixed 0
1
1
0
Fixed 1
1
1
1
Fixed 0
0
X
X
Internal VbusVld comparator. This
information should not be used by the
Link. (Note 5.4)
Standard Host
Standard
Peripheral
Note 5.4
5.7.2.4
RXCMD VBUS VALID
ENCODING SOURCE
A peripheral should not use VbusVld to begin operation. The peripheral should use
SessVld to detect the presence of VBUS on the USB connector. VbusVld should only be
used for USB Host and OTG A-device applications.
VBUS Pulsing with Pull-up and Pull-down Resistors
In addition to the internal VBUS comparators, the USB3370 also includes the integrated VBUS pull-up
and pull-down resistors used for VBUS Pulsing during OTG Session Request Protocol. To discharge
the VBUS voltage so that a Session Request can begin, the USB3370 provides a pull-down resistor
from VBUS to GND. This resistor is controlled by the DischargeVbus bit 3 of the OTG Control register.
The pull-up resistor is connected between VBUS and VDD33. This resistor is used to pull VBUS above
2.1 volts so that the A-Device knows that a USB session has been requested. The state of the pullup resistor is controlled by the bit 4 ChargeVbus of the OTG Control register. The Pull-Up and PullDown resistor values are detailed in Table 4.8.
The internal VBUS Pull-up and Pull-down resistors are designed to include the RVBUS external resistor
in series. This external resistor is used by the VBUS Over voltage protection described below.
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Datasheet
5.7.2.5
VBUS Input Impedance
The OTG Supplement requires an A-Device that supports Session Request Protocol to have a VBUS
input impedance less than 100kΩ and greater the 40kΩ to ground. The USB3370 provides a 75kΩ
resistance to ground, RVB. The RVB resistor tolerance is detailed in Table 4.8.
5.7.2.6
VBUS Over Voltage Protection (OVP)
The USB3370 provides an integrated over voltage protection circuit to protect the VBUS pin from
excessive voltages that may be present at the USB connector. The over voltage protection circuit works
with an external resistor (RVBUS) by drawing current across the resistor to reduce the voltage at the
VBUS pin.
When voltage at the VBUS pin exceeds 5.5V, the Over voltage Protection block will sink current to
ground until VBUS is below 5.5V. The current drops the excess voltage across RVBUS and protects the
USB3370 VBUS pin. The required RVBUS value is dependent on the operating mode of the USB3370
as shown in Table 5.6.
Table 5.6 Required RVBUS Resistor Value
OPERATING MODE
RVBUS
Device only
20kΩ ±5%
OTG Host Capable of less than 100mA
of current on VBUS
1kΩ ±5%
Host or OTG Host capable of >100mA
UseExternalVbusIndicator = 1
20kΩ ±5%
The Over voltage Protection circuit is designed to protect the USB3370 from continuous voltages up
to 30V on the RVBUS resistor.
The RVBUS resistor must be sized to handle the power dissipated across the resistor. The resistor
power can be found using the equation below:
2
( Vprotect – 5.0 )
P RVBUS = -------------------------------------------R VBUS
Where:
„
Vprotect is the VBUS protection required.
„
RVBUS is the resistor value, 1kΩ or 20kΩ.
„
PRVBUS is the required power rating of RVBUS.
For example, protecting a peripheral or device only application to 15V would require a 20kΩ RVBUS
resistor with a power rating of 0.05W. To protect an OTG product to 15V would require a 1kΩ RVBUS
resistor with a power rating of 0.1W.
5.7.3
Driving External VBUS
The USB3370 monitors VBUS as described in VBUS Monitoring and VBUS Pulsing. For OTG and Host
applications, the system is required to source 5 Volts on VBUS. The USB3370 fully supports VBUS
power control using an external VBUS switch. The USB3370 provides an open drain active low control
signal, CPEN_N, that is dedicated to controlling the Vbus supply when configured as an A-Device.
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CPEN_N is driven by setting the DrvVbus or DrvVbusExternal bit of the OTG Control register. To be
compatible with Link designs that support both internal and external Vbus supplies, the DrvVbus and
DrvVbusExternal bits in the OTG Control Register are NOR’d together. This enables the Link to set
either bit to access the external Vbus enable (CPEN_N). This logic is shown in Figure 5.8. DrvVbus
and DrvVbusExternal are set to 0 on Power On Reset (POR) as shown in Section 7.1.1.7.
USB Transceiver
RPU
CPEN_N
VBUS
Switch
EN
5V IN
+5V
VBUS
Supply
RVBUS
OUT
Link
Controller
DrvVbus
DrvVbusExternal
VBUS
ULPI
CPEN_N Logic
USB
Connector
VBUS
DM
DP
DM
DP
Figure 5.8 USB3370 Drives Control Signal (CPEN_N) to External Vbus Switch
5.7.4
External Vbus Indicator
The USB3370 has fully implemented the External Vbus detection described in the ULPI 1.1
specification. The block diagram of the External Vbus detection is shown in Figure 5.7 and in Table 5.5.
Table 5.7 External Vbus Indicator Logic
TYPICAL
APPLICATION
USE
EXTERNAL
VBUS
INDICATOR
INDICATOR
PASS THRU
INDICATOR
COMPLEMENT
OTG Device
0
X
X
Internal VbusVld comparator (Default)
1
1
0
External active high VbusVld signal
1
1
1
External active low VbusVld signal
1
0
0
External active high power fault signal
qualified with internal VbusVld
comparator. (Note 5.5)
1
0
1
External active low power fault signal
qualified with internal VbusVld
comparator. (Note 5.5)
1
1
0
External active high power fault signal
1
1
1
External active low power fault signal
0
X
X
Internal VbusVld comparator. This should
not be used by the Link. (Note 5.6)
Standard Host
Standard
Peripheral
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ENCODING SOURCE
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Note 5.5
SMSC does not recommend using the ExternalVbus signal qualified with the internal
VbusVld comparator.
Note 5.6
A peripheral should not use VbusVld to begin operation. The peripheral should use
SessVld because the internal VbusVld threshold can be above the Vbus voltage required
for USB peripheral operation.
A host PHY may use an active high or low fault by setting the IndicatorComplement bit [5] in the
Interface Control register. Also this implementation supports the IndicatorPassThru bit [6] in the
Interface Control register, which allows a choice of having the External Vbus input qualified (and’ed)
w i t h t h e e x t e r n a l v b u s c o m p a r a t o r o u t p u t . To u s e t h e E x t e r n a l V b u s I n p u t t h e
UseExternalVbusIndicator bit [7] must be set in the OTG control register. The default is not to use this
input.
The EXTVBUS pin has a built in pull down resistor that is controlled by the UseExternalVbusIndicator
bit [7] of the OTG control register. When UseExternalVbusIndicator is set to 0 (default) the pull down
resistor is activated to prevent the pin from floating when it is unused. When UseExternalVbusIndicator
is set to 1 the pull down resistor is disconnected.
5.8
USB UART Support
The USB3370 provides support for the USB UART interface as detailed in the ULPI specification and
the former CEA-936A specification. The USB3370 can be placed in UART Mode using the method
described in Section 6.7, and the regulator output will automatically switch to the value configured by
the UART RegOutput bits in the USB IO & Power Management register. While in UART mode, the
Linestate signals cannot be monitored on the DATA[0] and DATA[1] pins.
5.9
USB Charger Detection Support
The following blocks allow the USB3370 to detect when a Battery Charger, Charging Host Port, or a
USB Host is attached to the USB connector. The USB3370 can also be configured to appear as a
Charging Host Port, all according to the USB-IF Battery Charging 1.1 specification. The charger
detection circuitry should be disabled during USB operation.
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~~
V D D 33
C hargerP ullupE nD P
RCD
RCD
C hargerP ullupE nD M
C ontactD etectE n
en
I D P _S R C
DP
V D A T _S R C
T o U S B C on .
V D atS rcE n
H ostC hrgE n
DM
V datD et
V DAT_REF
RPD
RPD
T o U S B C on .
en
ID atS inkE n
en
I D A T _S IN K
D pP ulldow n
D m P ulldow n
SMSC PHY
~~
Figure 5.1 USB Charger Detection Block Diagram
Note: The italic names in the Figure 5.1 correspond to bits in the ULPI register set.
The charger detection circuitry runs from the VDD33 supply and requires that the VDD33 supply to be
present to run the charger detection circuitry. The VDD33 supply is present anytime the RESETB pin
is pulled high and VBAT is present. The charger detection circuits are fully functional while in Low
Power Mode (Suspendm = 0). The status of the VdatDet can be relayed back to the Link through the
ULPI interrupts in both Synchronous mode and Low Power Mode.
5.9.1
Active Analog Charger Detection (USB-IF Battery Charging 1.1)
The USB3370 includes the active analog charger detection specified in the USB-IF Battery Charging
Specification. The additional analog circuitry will allow the USB3370 to:
1. Detect a Dedicated Charging Port (DCP) with the DP and DM pins shorted together.
2. Detect a Standard Downstream Port (SDP) which has no battery charging circuitry.
3. Detect a Charging Downstream Port (CDP) which actively supplies voltage to the DM pin when
connected to a USB-IF BC 1.1 compatible device.
4. Behave as a Charging Downstream Port by enabling the voltage source on the DM pin.
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The charger detection circuitry is shown in Figure 5.1.
The VdatDet output is qualified with the Linestate[1:0] value. If the Linestate is not equal to 00 the
VdatDet signal will not assert.
The proper detection process flows through different modes of detection and uses the linestate and
VdatDet signals values to determine the connection. Table 5.8 describes the bit values that need to be
set to enter each mode.
DMPULLDOWN
DPPULLDOWN
HOSTCHRGEN
CONTACTDETEN
CHARGER DETECTION MODES
IDATSINKEN
VDATSRCEN
Table 5.8 USB Charger Setting vs. Modes
Device Connect Detect
(The Connect Detect setting in Table 5.1 must be followed)
0
0
1
0
0
1
Device Charger Detection
1
1
0
0
0
0
Device Enhanced Charger Detection
1
1
0
1
0
0
Device USB Operation
0
0
0
0
0
0
Charging Host Port, no charging device attached and SE0
(VdatDet = 0)
0
1
0
1
1
1
Charging Host Port, charging device attached (VdatDet = 1)
1
1
0
1
1
1
Charging Host Port USB Operation
0
0
0
1
1
1
5.9.1.1
Example Charger Detection Flow - Dedicated Charging Port
The USB-IF Battery Charging 1.1 specification describes in detail the flow for each charger type, but
below is an example of the flow used to detect a Dedicated Charger (DCP).
1. Device detects Vbus voltage is present from RXCMD, (SESS_VLD is 1)
2. Device enters the Device Connect Detect mode.
If the linestate still equals 10 after a specified timeout, the charger is an unknown charger and there
will be no attempted USB enumeration.
If the linestate equals 00 or 11, the device will go to the next mode:
3. Device enters Device Charger Detection mode.
If the VdatDet bit is 0 then the host is a Standard Downstream Port (SDP) and the device will draw
the standard 500mA of current and enter the Device USB Operation mode.
If the VdatDet bit is 1 then the host is a charger that can supply at least 1.5A of current, the device
will go to the next mode.
4. Device enters Device Enhanced Charger Detection mode.
If the VdatDet bit is 0 then the device is connected to a Charging Downstream Port (CDP) and the
device will enter the Device USB Operation mode.
If the VdatDet bit is 1 then the device is connected to a Dedicated Charging Port (DCP) and the
device will not try to enumerate.
5. The charger detection is complete.
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5.9.2
Resistive Charger Detection
Note: The Resistive Charger Detection has been superseded by the Active Analog Charger Detection
(USB-IF Battery Charging 1.1) detailed above. It is recommended that new designs use the
Active Analog Charger Detection (USB-IF Battery Charging 1.1).
To support the detection and identification of different types of USB chargers the USB3370 provides
integrated pull-up resistors, RCD, on both DP and DM. These pull-up resistors along with the single
ended receivers can be used to determine the type of USB charger attached. Reference information
on implementing charger detection is provided in Section 8.2.
Table 5.9 USB Weak Pull-up Enable
RESETB
DP PULLUP ENABLE
DM PULLUP ENABLE
0
0
0
1
ChargerPullupEnableDP
ChargerPullupEnableDM
Note: ChargerPullupEnableDP and ChargerPullupEnableDM are enabled in the USB IO & Power
Management register.
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Chapter 6 ULPI Operation
6.1
ULPI Introduction
The USB3370 uses the industry standard ULPI digital interface for communication between the
transceiver and Link (device controller). The ULPI interface is designed to reduce the number of pins
required to connect a discrete USB transceiver to an ASIC or digital controller. For example, a full
UTMI+ Level 3 OTG interface requires 54 signals while a ULPI interface requires only 12 signals.
The ULPI interface is documented completely in the “UTMI+ Low Pin Interface (ULPI) Specification
Revision 1.1”. The following sections describe the operating modes of the USB3370 digital interface.
Figure 6.1 illustrates the block diagram of the ULPI digital functions. It should be noted that this
USB3370 does not use a “ULPI wrapper” around a UTMI+ PHY core as the ULPI specification implies.
USB Transmit and Receive Logic
High Speed TX
Full Speed TX
Low Speed TX
NOTE:
The ULPI interface
is a wrapperless
design.
ULPI Protocol
Block
High Speed Data
Recovery
Full / Low Speed
Data Recovery
HS RX Data
To
OTG
Analog
To USB
Analog
Interface Protect Disable
UseExternal Vbus Indicator
Indicator Complement
Indicator Pass Thru
DischrgVbus
ChrgVbus
IdGndDrv
IdPullUp
RidCon...Done
VbusValid
SessionValid
SessionEnd
IdGnd
IdFloat
Rid State
Machine
Linestates[1:0]
HostDisconnect
ULPI Interupt
XcvrSelect[1:0]
TermSelect
OpMode[1:0]
Reset
DpPulldown
DmPulldown
SwapDP/DM
RegOutput[1:0]
TxdEn
RxdEn
To RX
Analog
FS/LS Data
RidValue[2:0]
RidCon...Start
Rx Data
ULPI Register Access
STP
To TX
Analog
FS/LS Tx Data
Transceiver Control
NXT
SuspendM
6pinSerial Mode
3pinSerial Mode
ClockSuspendM
AutoResume
CarkitMode
DIR
HS Tx Data
ChargerPullupEnDP
ChargerPullupEnDM
Tx Data
Data[7:0]
Interrupt Control
RESETB
POR
ULPI Register Array
Figure 6.1 ULPI Digital Block Diagram
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The advantage of a “wrapper-less” architecture is that the USB3370 has a lower USB latency than a
design which must first register signals into the PHY’s wrapper before the transfer to the transceiver
core. A low latency PHY allows a wrapper around a UTMI Link to be used and still make the required
USB turn-around timing required by the USB 2.0 specification.
RxEndDelay maximum allowed by the UTMI+/ULPI for 8-bit data is 63 Hi-Speed clocks. USB3370 uses
a low latency Hi-Speed receiver path to lower the RxEndDelay to 43 Hi-Speed clocks. This low latency
design gives the Link more cycles to make decisions and reduces the Link complexity. This is the result
of the “wrapper less” architecture of the USB3370. This low RxEndDelay should allow legacy UTMI
Links to use a “wrapper” to convert the UTMI+ interface to a ULPI interface.
In Figure 6.1, a single ULPI Protocol Block decodes the ULPI 8-bit bi-directional bus when the Link
addresses the PHY. The Link must use the DIR output to determine direction of the ULPI data bus.
The USB3370 is the “bus arbitrator”. The ULPI Protocol Block will route data/commands to the
transmitter or the ULPI register array.
6.1.1
ULPI Interface Signals
The UTMI+ Low Pin Interface (ULPI) uses a 12-pin interface to connect a USB Transceiver to an
external Link. The reduction of external pins, relative to UTMI+, is accomplished implementing the
relatively static configuration pins (i.e. xcvrselect[1:0], termselect, opmode[1:0], and DpPullDown
DmPulldown) as an internal register array.
An 8-bit bi-directional data bus clocked at 60MHz allows the Link to access this internal register array
and transfer USB packets to and from the PHY. The remaining 3 pins function to control the data flow
and arbitrate the data bus.
Direction of the 8-bit data bus is controlled by the DIR output from the PHY. Another output, NXT, is
used to control data flow into and out of the device. Finally, STP, which is in input to the PHY,
terminates transfers and is used to start up and resume from Low Power Mode.
The ULPI Interface signals are described below in Table 6.1.
Table 6.1 ULPI Interface Signals
SIGNAL
DIRECTION
DESCRIPTION
CLK
I/O
60MHz ULPI clock. All ULPI signals are driven synchronous to the rising edge of
this clock. This clock can be either driven by the PHY or the Link as described in
Section 5.5.1
DATA[7:0]
I/O
8-bit bi-directional data bus. Bus ownership is determined by DIR. The Link and
PHY initiate data transfers by driving a non-zero pattern onto the data bus. ULPI
defines interface timing for a single-edge data transfers with respect to rising edge
of the ULPI clock.
DIR
OUT
Controls the direction of the data bus. When the PHY has data to transfer to the
Link, it drives DIR high to take ownership of the bus. When the PHY has no data
to transfer it drives DIR low and monitors the bus for commands from the Link. The
PHY will pull DIR high whenever the interface cannot accept data from the Link,
such as during PLL start-up.
STP
IN
The Link asserts STP for one clock cycle to stop the data stream currently on the
bus. If the Link is sending data to the PHY, STP indicates the last byte of data was
on the bus in the previous cycle.
NXT
OUT
The PHY asserts NXT to throttle the data. When the Link is sending data to the
PHY, NXT indicates when the current byte has been accepted by the PHY. The
Link places the next byte on the data bus in the following clock cycle.
USB3370 implements a Single Data Rate (SDR) ULPI interface with all data transfers happening on
the rising edge of the 60MHz ULPI Clock while operating in Synchronous Mode. The direction of the
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data bus is determined by the state of DIR. When DIR is high, the PHY is driving DATA[7:0]. When
DIR is low, the Link is driving DATA[7:0].
Each time DIR changes, a “turn-around” cycle occurs where neither the Link nor PHY drive the data
bus for one clock cycle. During the “turn-around“cycle, the state of DATA[7:0] is unknown and the PHY
will not read the data bus.
Because USB uses a bit-stuffing encoding, some means of allowing the PHY to throttle the USB
transmit data is needed. The ULPI signal NXT is used to request the next byte to be placed on the
data bus by the Link.
The ULPI interface supports the two basic modes of operation: Synchronous Mode and Asynchronous
Mode. Asynchronous Mode includes Low Power Mode, the Serial Modes, and Carkit Mode. In
Synchronous Mode, all signals change synchronously with the 60MHz ULPI clock. In asynchronous
modes the clock is off and the ULPI bus is redefined to bring out the signals required for that particular
mode of operations. The description of synchronous Mode is described in the following sections while
the descriptions of the asynchronous modes are described in Section 6.5, Section 6.6, and Section 6.7.
6.1.2
ULPI Interface Timing in Synchronous Mode
The control and data timing relationships are given in Figure 6.2 and Table 4.3. All timing is relative to
the rising clock edge of the 60MHz ULPI Clock.
60MHz ULPI CLK
TSC
THC
Control In STP
TSD
THD
Data In DATA[7:0]
TDC
TDC
Control Out DIR, NXT
TDD
Data Out DATA[7:0]
Figure 6.2 ULPI Single Data Rate Timing Diagram in Synchronous Mode
6.2
ULPI Register Access
The following section details the steps required to access registers through the ULPI interface. At any
time DIR is low the Link may access the ULPI registers set using the Transmit Command byte. The
ULPI registers retain their contents when the PHY is in Low Power Mode, Full Speed/Low Speed Serial
Mode, or Carkit Mode.
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6.2.1
Transmit Command Byte (TX CMD)
A command from the Link begins a ULPI transfer from the Link to the USB3370. Before reading a
ULPI register, the Link must wait until DIR is low, and then send a Transmit Command Byte (TX CMD)
byte. The TX CMD byte informs the USB3370 of the type of data being sent. The TX CMD is followed
by a data transfer to or from the USB3370. Table 6.2 gives the TX command byte (TX CMD) encoding
for the USB3370. The upper two bits of the TX CMD instruct the PHY as to what type of packet the
Link is transmitting.
Table 6.2 ULPI TX CMD Byte Encoding
COMMAND NAME
CMD
BITS[7:6]
CMD BITS[5:0]
Idle
00b
000000b
ULPI Idle
Transmit
01b
000000b
USB Transmit Packet with No Packet Identifier
(NOPID)
00XXXXb
USB Transmit Packet Identifier (PID) where DATA[3:0]
is equal to the 4-bit PID. P3P2P1P0 where P3 is the
MSB.
XXXXXXb
Immediate Register Write Command where:
DATA[5:0] = 6-bit register address
Register Write
10b
101111b
Register Read
11b
Extended Register Write Command where the 8-bit
register address is available on the next cycle.
XXXXXXb
Immediate Register Read Command where:
DATA[5:0] = 6-bit register address
101111b
6.2.2
COMMAND DESCRIPTION
Extended Register Read Command where the 8-bit
register address is available on the next cycle.
ULPI Register Write
A ULPI register write operation is given in Figure 6.3. The TX command with a register write DATA[7:6]
= 10b is driven by the Link at T0. The register address is encoded into DATA[5:0] of the TX CMD byte.
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T0
T1
T2
T3
T4
T5
T6
CLK
DATA[7:0]
Idle
TXD CMD
(reg write)
Reg Data[n]
Idle
DIR
STP
NXT
ULPI Register
Reg Data [n-1]
Reg Data [n]
Figure 6.3 ULPI Register Write in Synchronous Mode
To write a register, the Link will wait until DIR is low, and at T0, drive the TX CMD on the data bus. At
T2 the PHY will drive NXT high. On the next rising clock edge, T3, the Link will write the register data.
At T4, the PHY will accept the register data and drive NXT low. The Link will drive an Idle on the bus
and drive STP high to signal the end of the data packet. Finally, at T5, the PHY will latch the data into
the register and the Link will pull STP low.
NXT is used to throttle when the Link drives the register data on the bus. DIR is low throughout this
transaction since the PHY is receiving data from the Link. STP is used to end the transaction and data
is registered after the de-assertion of STP. After the write operation completes, the Link must drive a
ULPI Idle (00h) on the data bus. If the databus is not driven to idle the USB3370 may decode the nonzero bus value as an RX Command.
A ULPI extended register write operation is shown in Figure 6.4. To write an extended register, the Link
will wait until DIR is low, and at T0, drive the TX CMD on the data bus. At T2 the PHY will drive NXT
high. On the next clock T3 the Link will drive the extended address. On the next rising clock edge, T4,
the Link will write the register data. At T5, the PHY will accept the register data and drive NXT low.
The Link will drive an Idle on the bus and drive STP high to signal the end of the data packet. At T5,
the PHY will latch the data into the register. Finally, at T6, the Link will drive STP low.
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T0
T1
T2
T3
T4
T5
T6
T7
CLK
DATA[7:0]
TXD CMD
(extended reg write)
Idle
Extended
address
Reg Data[n]
Idle
DIR
STP
NXT
ULPI Register
Reg Data [n-1]
Reg Data [n]
Figure 6.4 ULPI Extended Register Write in Synchronous Mode
6.2.3
ULPI Register Read
A ULPI register read operation is given in Figure 6.5. The Link drives a TX CMD byte with DATA[7:6]
= 11h for a register read. DATA[5:0] of the ULPI TX command bye contain the register address.
T0
T1
T2
T3
T4
T5
T6
CLK
DATA[7:0]
Idle
TXD CMD
reg read
Turn around
Reg Data
Turn around
Idle
DIR
STP
NXT
Figure 6.5 ULPI Register Read in Synchronous Mode
At T0, the Link will place the TX CMD on the data bus. At T2, the PHY will bring NXT high, signaling
the Link it is ready to accept the data transfer. At T3, the PHY reads the TX CMD, determines it is a
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register read, and asserts DIR to gain control of the bus. The PHY will also de-assert NXT. At T4, the
bus ownership has transferred back to the PHY and the PHY drives the requested register onto the
data bus. At T5, the Link will read the data bus and the PHY will drop DIR low returning control of the
bus back to the Link. After the turn around cycle, the Link must drive a ULPI Idle command at T6.
A ULPI extended register read operation is shown in Figure 6.6.To read an extended register, the Link
writes the TX CMD with the address set to 2Fh. At T2, the PHY will assert NXT, signaling the Link it
is ready to accept the extended address. At T3, the Link places the extended register address on the
bus. At T4, the PHY reads the extended address, and asserts DIR to gain control of the bus. The PHY
will also de-assert NXT. At T5, the bus ownership has transferred back to the PHY and the PHY drives
the requested register onto the data bus. At T6, the Link will read the data bus and the PHY will deassert DIR returning control of the bus back to the Link. After the turn around cycle, the Link must
drive a ULPI Idle command at T6.
T0
T1
T2
T3
T4
T5
T6
T7
CLK
DATA[7:0]
Idle
TXD CMD
extended reg read
Extended
address
Turn around
Reg Data
Turn around
Idle
DIR
STP
NXT
Figure 6.6 ULPI Extended Register Read in Synchronous Mode
6.3
USB3370 Receiver
The following section describes how the USB3370 uses the ULPI interface to receive USB signaling
and transfer status information to the Link. This information is communicated to the Link using RX
Commands to relay bus status and received USB packets.
6.3.1
ULPI Receive Command (RX CMD)
The ULPI Link needs information which was provided by the following pins in a UTMI implementation:
linestate[1:0], rxactive, rxvalid, rxerror, and VbusValid. When implementing the OTG functions, the
VBUS and ID pin states must also be transferred to the Link. ULPI defines a Receive Command Byte
(RXCMD) that contains this information.
An RXCMD can be sent a any time the bus is idle. The RXCMD is initiated when the USB3370 asserts
DIR to take control of the bus. The timing of RXCMD is shown in the figure below. The USB3370 can
send single or back to back RXCMD’s as required. The Encoding of the RXCMD byte is given in the
Table 6.3.
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T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
DATA[7:0]
Idle
Turn around
RXCMD
Turn around
Idle
Turn around
RXCMD
RXCMD
Turn around
Idle
DIR
STP
NXT
Figure 6.7 ULPI RXCMD Timing
Transfer of the RXCMD byte occurs in Synchronous Mode when the PHY has control of the bus. The
ULPI Protocol Block shown in Figure 6.1 determines when to send an RXCMD. A RXCMD will occur:
„
When a linestate change occurs.
„
When VBUS or ID comparators change state.
„
During a USB receive when NXT is low.
„
After the USB3370 deasserts DIR and STP is low during start-up
„
After the USB3370 exits Low Power Mode, Serial Modes, or Carkit Mode after detecting that the
Link has de-asserted STP, and DIR is low.
When a USB Receive is occurring, RXCMD’s are sent whenever NXT = 0 and DIR = 1. During a USB
Transmit, the RXCMD’s are returned to the Link after STP is asserted.
If an RXCMD event occurs during a Hi-Speed USB transmit, the RXCMD is blocked until STP deasserts at the end of the transmit. The RXCMD contains the status that is current at the time the
RXCMD is sent.
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Table 6.3 ULPI RX CMD Encoding
DATA[7:0]
NAME
DESCRIPTION AND VALUE
[1:0]
Linestate
UTMI Linestate Signals. See Section 6.3.1.1
[3:2]
Encoded
VBUS
State
ENCODED VBUS VOLTAGE STATES
[5:4]
Rx Event
Encoding
[6]
State of
ID pin
[7]
alt_int
VALUE
VBUS VOLTAGE
SESSEND
SESSVLD
VBUSVLD2
00
VVBUS < VSESS_END
1
0
0
01
VSESS_END < VVBUS <
VSESS_VLD
0
0
0
10
VSESS_VLD < VVBUS <
VVBUS_VLD
X
1
0
11
VVBUS_VLD < VVBUS
X
X
1
ENCODED UTMI EVENT SIGNALS
VALUE
RXACTIVE
RXERROR
HOSTDISCONNECT
00
0
0
0
01
1
0
0
11
1
1
0
10
X
X
1
Set to the logic state of the ID pin. A logic low indicates an A device. A logic high
indicates a B device.
Asserted when a non-USB interrupt occurs. This bit is set when an unmasked event
occurs on any bit in the Carkit Interrupt Latch register. The Link must read the Carkit
Interrupt Latch register to determine the source of the interrupt. Section 6.8 describes
how an interrupt can be generated when the RidConversionDone bit is set.
Notes:
1. An ‘X’ is a do not care and can be either a logic 0 or 1.
2. The value of VbusValid is defined in Table 5.5.
6.3.1.1
Definition of Linestate
The Linestate information is used to relay information back to the Link on the current status of the USB
data lines, DP and DM. The definition of Linestate changes as the USB3370 transitions between LS/FS
mode, HS mode, and HS Chirp.
6.3.1.1.1
LS/FS LINESTATE DEFINITIONS
In LS and FS operating modes the Linestate is defined by the outputs of the LS/FS Single Ended
Receivers (SE RX). The logic thresholds for single ended receivers, VILSE and VILSE are shown in
Table 4.5.
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Table 6.4 USB Linestate Decoding in FS and LS Mode
LINESTATE[1:0]
DP SE RX
DM SE RX
STATE
00
SE0
0
0
USB Reset
01
J (FS idle)
1
0
J State
10
K (LS Idle)
0
1
K State
11
SE1
1
1
SE1
Low Speed uses the same Linestate decoding threshold as Full Speed. Low Speed re-defines the Idle
state as an inversion of the Full Speed idle to account for the inversion which occurs in the hub
repeater path. Linestates are decoded exactly as in Table 6.4 with the idle as a K state.
6.3.1.1.2
HS LINESTATE DEFINITION
In HS mode the data transmission is too fast for Linestate to be transmitted with each transition in the
data packet. In HS operation the Linestate is redefined to indicate activity on the USB interface. The
Linestate will signal the assertion and de-assertion of squelch in HS mode.
Table 6.5 USB Linestate Decoding in HS Mode
LINESTATE[1:0]
DP SE RX
DM SE RX
STATE
00
SE0
0
0
HS Squelch asserted
01
J
1
0
HS Squelch de-asserted
10
K
0
1
Invalid State
11
SE1
1
1
Invalid State
6.3.1.1.3
HS CHIRP LINESTATE DEFINITION
There is also a third use of Linestate in HS Chirp where when the Host and Peripheral negotiate the
from FS mode to HS mode. While the transitions from K to J or SE0 are communicated to the Link
through the Linestate information.
Table 6.6 USB Linestate Decoding in HS Chirp Mode
LINESTATE[1:0]
DP SE RX
DM SE RX
STATE
00
SE0
0
0
HS Squelch asserted
01
J
1
0
HS Squelch de-asserted & HS
differential Receiver = 1
10
K
0
1
HS Squelch de-asserted & HS
differential Receiver = 0
11
SE1
1
1
Invalid State
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6.3.2
USB Receiver
The USB3370 ULPI receiver fully supports HS, FS, and LS transmit operations. In all three modes the
receiver detects the start of packet and synchronizes to the incoming data packet. In the ULPI protocol,
a received packet has the priority and will immediately follow register reads and RXCMD transfers.
Figure 6.8 shows a basic USB packet received by the USB3370 over the ULPI interface.
CLK
DATA[7:0]
Idle
Turn
around
Rxd
Cmd
PID
D1
Rxd
Cmd
D2
Turn
around
DIR
STP
NXT
Figure 6.8 ULPI Receive in Synchronous Mode
In Figure 6.8 the PHY asserts DIR to take control of the data bus from the Link. The assertion of DIR
and NXT in the same cycle contains additional information that Rxactive has been asserted. When
NXT is de-asserted and DIR is asserted, the RXCMD data is transferred to the Link. After the last byte
of the USB receive packet is transferred to the PHY, the linestate will return to idle.
The ULPI Full Speed receiver operates according to the UTMI / ULPI specification. In the Full Speed
case, the NXT signal will assert only when the Data bus has a valid received data byte. When NXT is
low with DIR high, the RXCMD is driven on the data bus.
In Full Speed, the USB3370 will not issue a Rxactive de-assertion in the RXCMD until the DP/DM
linestate transitions to idle. This prevents the Link from violating the two Full Speed bit times minimum
turn around time.
6.3.2.1
Disconnect Detection
A Hi-Speed host must detect a disconnect by sampling the transmitter outputs during the long EOP
transmitted during a SOF packet. The USB3370 only looks for a Hi-Speed disconnect during the long
EOP where the period is long enough for the disconnect reflection to return to the host PHY. When a
Hi-Speed disconnect occurs, the USB3370 will return a RXCMD and set the host disconnect bit in the
USB Interrupt Status register.
When in FS or LS modes, the Link is expected to handle all disconnect detection.
6.3.2.2
Link Power Management (LPM) Token Receive
The USB3370 is fully capable of receiving the Extended PID in the LPM token. When the LPM 0000b
PID is received, this information is passed to the Link as a normal receive packet. If the Link chooses
to enter LPM suspend, the procedure detailed in 6.5.3 can be followed.
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6.4
USB3370 Transmitter
The USB3370 ULPI transmitter fully supports HS, FS, and LS transmit operations. Figure 6.1 shows
the Hi-Speed, Full Speed, and Low Speed transmitter block controlled by ULPI Protocol Block.
Encoding of the USB packet follows the bit-stuffing and NRZI outlined in the USB 2.0 specification.
Many of these functions are reused between the HS and FS/LS transmitters. When using the
USB3370, Table 5.1 should always be used as a guideline on how to configure for various modes of
operation. The transmitter decodes the inputs of XcvrSelect[1:0], TermSelect, OpMode[1:0],
DpPulldown, and DmPulldown to determine what operation is expected. Users must strictly adhere to
the modes of operation given in Table 5.1.
Several important functions for a device and host are designed into the transmitter blocks.
The USB3370 transmitter will transmit a 32-bit long Hi-Speed sync before every Hi-Speed packet. In
Full and Low Speed modes a 8-bit sync is transmitted.
When the device or host needs to chirp for Hi-Speed port negotiation, the OpMode = 10 setting will
turn off the bit-stuffing and NRZI encoding in the transmitter. At the end of a chirp, the USB3370
OpMode register bits should be changed only after the RXCMD linestate encoding indicates that the
transmitter has completed transmitting. Should the opmode be switched to normal bit-stuffing and NRZI
encoding before the transmit pipeline is empty, the remaining data in the pipeline may be transmitted
in an bit-stuff encoding format.
Please refer to the ULPI specification for a detailed discussion of USB reset and HS chirp.
6.4.1
USB3370 Host Features
The USB3370 can also support USB Host operation and includes the following features that are
required for Host operation.
6.4.1.1
Hi-Speed Long EOP
When operating as a Hi-Speed host, the USB3370 will automatically generate a 40 bit long End of
Packet (EOP) after a SOF PID (A5h). The USB3370 determines when to send the 40-bit long EOP by
decoding the ULPI TX CMD bits [3:0] for the SOF. The 40-bit long EOP is only transmitted when the
DpPulldown and DmPulldown bits in the OTG Control register are asserted. The Hi-Speed 40-bit long
EOP is used to detect a disconnect in mode.
In device mode, the USB3370 will not send a long EOP after a SOF PID.
6.4.1.2
Low Speed Keep-Alive
Low Speed keep alive is supported by the USB3370. When in Low Speed mode, the USB3370 will
send out two Low Speed bit times of SE0 when a SOF PID is received.
6.4.1.3
UTMI+ Level 3
Pre-amble is supported for UTMI+ Level 3 compatibility. When XcvrSelect is set to (11b) in host mode,
(DpPulldown and DmPulldown both asserted) the USB3370 will pre-pend a Full Speed pre-amble
before the Low Speed packet. Full Speed rise and fall times are used in this mode. The pre-amble
consists of the following: Full Speed sync, the encoded pre-PID (C3h) and then Full Speed idle (DP=1
and DM = 0). A Low Speed packet follows with a sync, data and a LS EOP.
The USB3370 will only support UTMI+ Level 3 as a host. The USB3370 does not support UTMI+ Level
3 as a peripheral. A UTMI+ Level 3 peripheral is an upstream hub port. The USB3370 will not decode
a pre-amble packet intended for a LS device when the USB3370 is configured as the upstream port
of a FS hub, XcvrSelect = 11b, DpPulldown = 0b, DmPulldown =0b.
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6.4.1.4
Host Resume K
Resume K generation is supported by the USB3370. At the end of a USB Suspend the PHY will drive
a K back to the downstream device. When the USB3370 exits from Low Power Mode, when operating
as a host, it will automatically transmit a Resume K on DP/DM. The transmitters will end the K with
SE0 for two Low Speed bit times. If the USB3370 was operating in Hi-Speed mode before the suspend,
the host must change to Hi-Speed mode before the SE0 ends. SE0 is two Low Speed bit times which
is about 1.2 us. For more details please see sections 7.1.77 and 7.9 of the USB Specification.
In device mode, the resume K will not append an SE0, but release the bus to the correct idle state,
depending upon the operational mode as shown in Table 5.1.
The ULPI specification includes a detailed discussion of the resume sequence and the order of
operations required. To support Host start-up of less than 1mS the USB3370 implements the ULPI
AutoResume bit in the Interface Control register. The default AutoResume state is 0 and this bit should
be enabled for Host applications.
6.4.1.5
No SYNC and EOP Generation (OpMode = 11)
UTMI+ defines OpMode = 11 where no sync and EOP generation occurs in Hi-Speed operation. This
is an option to the ULPI specification and not implemented in the USB3370.
6.4.2
Typical USB Transmit with ULPI
Figure 6.9 shows a typical USB transmit sequence. A transmit sequence starts by the Link sending a
TX CMD where DATA[7:6] = 01b, DATA[5:4] = 00b, and Data[3:0] = PID. The TX CMD with the PID
is followed by transmit data.
CLK
DATA[7:0]
TXD CMD
(USB tx)
Idle
D0
D1
D2
D3
IDLE
Turn
Around
RXD
CMD
Turn
Around
DIR
NXT
STP
DP/DM
SE0
!SQUELCH
SE0
Figure 6.9 ULPI Transmit in Synchronous Mode
During transmit the PHY will use NXT to control the rate of data flow into the PHY. If the USB3370
pipeline is full or bit-stuffing causes the data pipeline to overfill NXT is de-asserted and the Link will
hold the value on Data until NXT is asserted. The USB Transmit ends when the Link asserts STP while
NXT is asserted.
Note: The Link cannot assert STP with NXT de-asserted since the USB3370 is expecting to fetch
another byte from the Link.
After the USB3370 completes transmitting, the DP and DM lines return to idle and a RXCMD is
returned to the Link so the inter-packet timers may be updated by linestate.
While operating in Full Speed or Low Speed, an End-of-Packet (EOP) is defined as SE0 for
approximately two bit times, followed by J for one bit time. The transceiver drives a J state for one bit
time following the SE0 to complete the EOP. The Link must wait for one bit time following line state
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indication of the SE0 to J transition to allow the transceiver to complete the one bit time J state. All bit
times are relative to the speed of transmission.
In the case of Full Speed or Low Speed, after STP is asserted each FS/LS bit transition will generate
a RXCMD since the bit times are relatively slow.
6.4.2.1
Link Power Management Token Transmit
A Host Link can send a LPM command using the USB3370. When sending the LPM token the normal
transmit method is not used. Sending a LPM token requires the USB3370 to send a 0000b or ‘F0’ PID.
When the ULPI specification was defined the ‘F0’ PID was not defined. The ULPI specification used
the “Reserved” ‘F0’ PID to signal chirp and resume signaling while using OpMode 10b. While in
OpMode 00b the USB3370 is able to generate the ‘F0’ PID as shown below.
CLK
DATA[7:0]
Idle
TXD CMD
(40h TX NOPID )
PID
(F0h)
D0
D1
Turn
Around
IDLE
Turn
Around
RXD
CMD
IDLE
DIR
NXT
STP
DP/DM
SE0
!SQUELCH
SE0
Figure 6.10 LPM Token Transmit
To send the ‘F0’ PID, the link will be required to use the TX CMD with NOPID to initiate the transmit
and then follow up the TX CMD with the ‘F0’ PID. The data bytes follow as in a normal transmit, in
OpMode 00b. The key difference is in that the link will have to send the PID the same as it would send
a data packet. The USB3370 is able to recognize the LPM transmit and correctly send the PID
information.
6.5
Low Power Mode
Low Power Mode is a power down state to save current when the USB session is suspended. The
Link controls when the PHY is placed into or out of Low Power Mode. In Low Power Mode all of the
circuits are powered down except the interface pins, Full Speed receiver, VBUS comparators, and
IdGnd comparator. The VBUS and ID comparators can optionally be powered down to save current as
shown in Section 6.5.5.
Before entering Low Power Mode, the USB3370 must be configured to set the desired state of the
USB transceiver. The XcvrSelect[1:0], TermSelect and OpMode[1:0] bits in the Function Control
register, and the DpPulldown and DmPulldown bits in the OTG Control register control the
configuration as shown in Table 5.1. The DP and DM pins are configured to a high impedance state
by configuring OpMode[1:0] = 01 as shown in the programming example in Table 6.8. Pull-down
resistors with a value of approximately 2MΩ are present on the DP and DM pins to avoid false linestate
indications that could result if the pins were allowed to float.
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6.5.1
Entering Low Power/Suspend Mode
To enter Low Power Mode, the Link will write a 0 or clear the SuspendM bit in the Function Control
register. After this write is complete, the PHY will assert DIR high and after a minimum of five rising
edges of CLKOUT, drive the clock low. After the clock is stopped, the PHY will enter a low power state
to conserve current. Placing the PHY in Suspend Mode is not related to USB Suspend. To clarify this
point, USB Suspend is initiated when a USB host stops data transmissions and enters Full-Speed
mode with 15KΩ pull-down resistors on DP and DM. The suspended device goes to Full-Speed mode
with a pull-up on DP. Both the host and device remain in this state until one of them drives DM high
(this is called a resume).
T0
T1
T2
T3
T4
T5
T6
CLK
DATA[7:0]
TXD CMD
(reg write)
Idle
Reg Data[n]
Idle
Turn
Around
...
T10
Low Power Mode
DIR
STP
NXT
SUSPENDM
(ULPI Register Bit)
Figure 6.11 Entering Low Power Mode from Synchronous Mode
While in Low Power Mode, the Data interface is redefined so that the Link can monitor Linestate and
the VBUS voltage. In Low Power Mode DATA[3:0] are redefined as shown in Table 6.7. Linestate[1:0]
is the combinational output of the Single-Ended Receivers. The “int” or interrupt signal indicates an
unmasked interrupt has occurred. When an unmasked interrupt or linestate change has occurred, the
Link is notified and can determine if it should wake-up the PHY.
Table 6.7 Interface Signal Mapping During Low Power Mode
SIGNAL
MAPS TO
DIRECTION
DESCRIPTION
linestate[0]
DATA[0]
OUT
Combinatorial LineState[0] driven directly by the Full-Speed single
ended receiver. Note 6.1
linestate[1]
DATA[1]
OUT
Combinatorial LineState[1] driven directly by the Full-Speed single
ended receiver. Note 6.1
reserved
DATA[2]
OUT
Driven Low
int
DATA[3]
OUT
Active high interrupt indication. Must be asserted whenever any
unmasked interrupt occurs.
reserved
DATA[7:4]
OUT
Driven Low
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Note 6.1
LineState: These signals reflect the current state of the Full-Speed single ended receivers.
LineState[0] directly reflects the current state of DP. LineState[1] directly reflects the current
state of DM. When DP=DM=0 this is called "Single Ended Zero" (SE0). When DP=DM=1,
this is called "Single Ended One" (SE1).
An unmasked interrupt can be caused by the following comparators changing state: VbusVld, SessVld,
SessEnd, and IdGnd. If any of these signals change state during Low Power Mode and the bits are
enabled in either the USB Interrupt Enable Rising or USB Interrupt Enable Falling registers, DATA[3]
will assert. During Low Power Mode, the VbusVld and SessEnd comparators can have their interrupts
masked to lower the suspend current as described in Section 6.5.5.
While in Low Power Mode, the Data bus is driven asynchronously because all of the PHY clocks are
stopped during Low Power Mode.
6.5.2
Exiting Low Power Mode
To exit Low Power Mode, the Link will assert STP. Upon the assertion of STP, the USB3370 will begin
its start-up procedure. After the PHY start-up is complete, the PHY will start the clock on CLKOUT and
de-assert DIR. After DIR has been de-asserted, the Link can de-assert STP when ready and start
operating in Synchronous Mode. The PHY will automatically set the SuspendM bit to a 1 in the
Function Control register.
T0
...
CLK
LOW
POWER MODE
DATA[7:0]
T1
T2
TURN
AROUND
T3
DATA BUS IGNORED (SLOW LINK)
IDLE (FAST LINK)
Fast Link Drives Bus
Idle and STP low
DIR
T4
T5
IDLE
Slow Link Drives Bus
Idle and STP low
STP
Note: Not to Scale
TSTART
Figure 6.12 Exiting Low Power Mode
The value for TSTART is given in Table 4.2.
Should the Link de-assert STP before DIR is de-asserted, the USB3370 will detect this as a false
resume request and return to Low Power Mode. This is detailed in Section 3.9.4 of the UTMI+ Low
Pin Interface (ULPI) Specification Revision 1.1.
6.5.3
Link Power Management (LPM)
When the USB3370 is operating with a Link capable of Link Power Management, the Link will place
the USB3370 in and out of suspend rapidly to conserve power. The USB3370 provides a fast suspend
recovery that allows the USB3370 to meet the suspend recovery time detailed in the Link Power
Management ECN to the USB 2.0 specification.
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When the Link places the USB3370 into suspend during Link Power Management, the LPM Enable
bit of the HS Compensation Register must be set to 1. This allows the USB3370 to start-up in the time
specified in Table 4.2.
6.5.4
Interface Protection
ULPI protocol assumes that both the Link and PHY will keep the ULPI data bus driven by either the
Link when DIR is low or the PHY when DIR is high. The only exception is when DIR has changed
state and a turn around cycle occurs for 1 clock period.
In the design of a USB system, there can be cases where the Link may not be driving the ULPI bus
to a known state while DIR is low. Two examples where this can happen is because of a slow Link
start-up or a hardware reset.
6.5.4.1
Start up Protection
Upon start-up, when the PHY de-asserts DIR, the Link must be ready to receive commands and drive
Idle on the data bus. If the Link is not ready to receive commands or drive Idle, it must assert STP
before DIR is de-asserted. The Link can then de-assert STP when it has completed its start-up. If the
Link doesn’t assert STP before it can receive commands, the PHY may interpret the data bus state as
a TX CMD and transmit invalid data onto the USB bus, or make invalid register writes.
When the USB3370 sends a RXCMD the Link is required to drive the data bus back to idle at the end
of the turn around cycle. If the Link does not drive the databus to idle the USB3370 may take the
information on the data bus as a TXCMD and transmit data on DP and DM until the Link asserts stop.
If the ID pin is floated the last RXCMD from the USB3370 will remain on the bus after DIR is deasserted and the USB3370 will take this in as a TXCMD.
A Link should be designed to have the default POR state of the STP output high and the data bus tristated. The USB3370 has weak pull-downs on the data bus to prevent these inputs from floating when
not driven. These resistors are only used to prevent the ULPI interface from floating during events
when the link ULPI pins may be tri-stated. The strength of the pull down resistors can be found in
Table 4.4. The pull downs are not strong enough to pull the data bus low after a ULPI RXCMD, the
Link must drive the data bus to idle after DIR is de-asserted.
In some cases, a Link may be software configured and not have control of its STP pin until after the
PHY has started. In this case, the USB3370 has in internal pull-up on the STP input pad which will
pull STP high while the Link’s STP output is tri-stated. The STP pull-up resistor is enabled on POR
and can be disabled by setting the InterfaceProtectDisable bit 7 of the Interface Control register.
The STP pull-up resistor will pull-up the Link’s STP input high until the Link configures and drives STP
high. After the Link completes its start-up, STP can be synchronously driven low.
A Link design which drives STP high during POR can disable the pull-up resistor on STP by setting
InterfaceProtectDisable bit to 1. A motivation for this is to reduce the suspend current. In Low Power
Mode, STP is held low, which would draw current through the pull-up resistor on STP.
6.5.4.2
Warm Reset
Designers should also consider the case of a warm restart of a Link with a PHY in Low Power Mode.
After the PHY enters Low Power Mode, DIR is asserted and the clock is stopped. The USB3370 looks
for STP to be asserted to re-start the clock and then resume normal synchronous operation.
Should the USB3370 be suspended in Low Power Mode, and the Link receives a hardware reset, the
PHY must be able to recover from Low Power Mode and start its clock. If the Link asserts STP on
reset, the PHY will exit Low Power Mode and start its clock.
If the Link does not assert STP on reset, the interface protection pull-up can be used. When the Link
is reset, its STP output will tri-state and the pull-up resistor will pull STP high, signaling the PHY to
restart its clock.
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6.5.5
Minimizing Current in Low Power Mode
In order to minimize the suspend current in Low Power Mode, the VBUS and ID comparators can be
disabled to reduce suspend current. In Low Power Mode, the VbusVld and SessEnd comparators are
not needed and can be disabled by clearing the associated bits in both the USB Interrupt Enable Rising
and USB Interrupt Enable Falling registers. By disabling the interrupt in BOTH the rise and fall
registers, the SessEnd and VbusVld comparators are turned off. The IdFloatRise and IdFloatFall bits
in Carkit Interrupt Enable register should also be disabled if they were set. When exiting Low Power
Mode, the Link should immediately re-enable the VbusVld and SessEnd comparators if host or OTG
functionality is required.
In addition to disabling the OTG comparators in Low Power Mode, the Link may choose to disable the
Interface Protect Circuit. By setting the InterfaceProtectDisable bit high in the Interface Control register,
the Link can disable the pull-up resistor on STP. When RESETB is low the Interface Protect Circuit
will be disabled.
6.6
Full Speed/Low Speed Serial Modes
The USB3370 includes two serial modes to support legacy Links which use either the 3pin or 6pin
serial format. To enter either serial mode, the Link will need to write a 1 to the 6-pin FsLsSerialMode
or the 3-pin FsLsSerialMode bits in the Interface control register. Serial Mode may be used to conserve
power when attached to a device that is not capable of operating in Hi-Speed.
The serial modes are entered in the same manner as the entry into Low Power Mode. The Link writes
the Interface Control register bit for the specific serial mode. The USB3370 will assert DIR and shut
off the clock after at least five clock cycles. Then the data bus goes to the format of the serial mode
selected. Before entering Serial Mode the Link must set the ULPI transceiver to the appropriate mode
as defined in Table 5.1.
In ULPI Clock Output Mode, the PHY will shut off the 60MHz clock to conserve power. Should the Link
need the 60MHz clock to continue during the serial mode of operation, the ClockSuspendM bit[3] of
the Interface Control Register should be set before entering a serial mode. If set, the 60 MHz clock
will be present during serial modes.
In serial mode, interrupts are possible from unmasked sources. The state of each interrupt source is
sampled prior to the assertion of DIR and this is compared against the asynchronous level from
interrupt source.
Exiting the serial modes is the same as exiting Low Power Mode. The Link must assert STP to signal
the PHY to exit serial mode. When the PHY can accept a command, DIR is de-asserted and the PHY
will wait until the Link de-asserts STP to resume synchronous ULPI operation. The RESETB pin can
also be pulsed low to reset the USB3370 and return it to Synchronous Mode.
6.6.0.1
3-Pin FS/LS Serial Mode
Three pin serial mode utilizes the data bus pins for the serial functions shown in Table 6.8.
Table 6.8 Pin Definitions in 3 pin Serial Mode
SIGNAL
CONNECTED
TO
DIRECTION
tx_enable
DATA[0]
IN
Active High transmit enable.
data
DATA[1]
I/O
TX differential data on DP/DM when tx_enable is high.
RX differential data from DP/DM when tx_enable is low.
SE0
DATA[2]
I/O
TX SE0 on DP/DM when tx_enable is high.
RX SE0_b from DP/DM when tx_enable is low.
Revision 1.0 (10-08-12)
DESCRIPTION
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Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
Table 6.8 Pin Definitions in 3 pin Serial Mode (continued)
SIGNAL
CONNECTED
TO
DIRECTION
interrupt
DATA[3]
OUT
Asserted when any unmasked interrupt occurs. Active high.
Reserved
DATA[7:4]
OUT
Driven Low.
6.6.0.2
DESCRIPTION
6-Pin FS/LS Serial Mode
Six pin serial mode utilizes the data bus pins for the serial functions shown in Table 6.9.
Table 6.9 Pin Definitions in 6 pin Serial Mode
SIGNAL
CONNECTED
TO
DIRECTION
tx_enable
DATA[0]
IN
Active High transmit enable.
tx_data
DATA[1]
IN
Tx differential data on DP/DM when tx_enable is high.
tx_se0
DATA[2]
IN
Tx SE0 on DP/DM when tx_enable is high.
interrupt
DATA[3]
OUT
Asserted when any unmasked interrupt occurs. Active high.
rx_dp
DATA[4]
OUT
Single ended receive data on DP.
rx_dm
DATA[5]
OUT
Single ended receive data on DM.
rx_rcv
DATA[6]
OUT
Differential receive data from DP and DM.
Reserved
DATA[7]
OUT
Driven Low.
6.7
DESCRIPTION
Carkit Mode
The USB3370 includes Carkit Mode to support a USB UART Mode.
By entering Carkit Mode, the USB3370 current drain is minimized. The internal PLL is disabled and
the 60MHz ULPI CLKOUT will be stopped to conserve power by default. The Link may configure the
60MHz clock to continue by setting the ClockSuspendM bit of the Interface Control register before
entering Carkit Mode. If set, the 60 MHz clock will continue during the Carkit Mode of operation.
In Carkit Mode, interrupts are possible if they have been enabled in the Carkit Interrupt Enable register.
The state of each interrupt source is sampled prior to the assertion of DIR and this is compared against
the asynchronous level from interrupt source. In Carkit Mode, the Linestate signals are not available
per the ULPI specification.
The ULPI interface is redefined to the following when Carkit Mode is entered.
SMSC USB3370B
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Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
Table 6.10 Pin Definitions in Carkit Mode
CONNECTED
TO
SIGNAL
DIRECTION
DESCRIPTION
txd
DATA[0]
IN
UART TXD signal that is routed to the DM pin if the TxdEn
is set in the Carkit Control register.
rxd
DATA[1]
OUT
UART RXD signal that is routed to the DP pin if the RxdEn
bit is set in the Carkit Control register.
reserved
DATA[2]
OUT
Driven Low (CarkitDataMC = 0, default)
IN
Tri-state (CarkitDataMC = 1)
int
DATA[3]
OUT
Asserted when any unmasked interrupt occurs. Active high.
reserved
DATA[4:7]
OUT
Driven Low.
Exiting Carkit Mode is the same as exiting Low Power Mode as described in Section 6.5.2. The Link
must assert STP to signal the PHY to exit serial mode. When the PHY can accept a command, DIR
is de-asserted and the PHY will wait until the Link de-asserts STP to resume synchronous ULPI
operation. The RESETB pin can also be pulsed low to reset the USB3370 and return it to Synchronous
Mode.
6.7.1
Entering USB UART Mode
The USB3370 can be placed into UART Mode by first setting the TxdEn and RxdEn bits in the Carkit
Control register. Then the Link can set the CarkitMode bit in the Interface Control register. The TxdEn
and RxdEn bits must be written before the CarkitMode bit.
Table 6.11 ULPI Register Programming Example to Enter UART Mode
R/W
ADDRESS
(HEX)
VALUE
(HEX)
W
04
W
DESCRIPTION
RESULT
49
Configure Non-Driving mode
Select FS transmit edge rates
OpMode=01
XcvrSelect=01
39
00
Set regulator to 3.3V
UART RegOutput=00
W
19
0C
Enable UART connections
RxdEn=1
TxdEn=1
W
07
04
Enable carkit mode
CarkitMode=1
After the CarkitMode bit is set, the ULPI interface will become redefined as described in Table 6.10,
and the USB3370 will transmit data through the DATA[0] to DM of the USB connector and receive
data on DP and pass the information the Link on DATA[1].
When entering UART mode, the regulator output will automatically switch to the value configured by
the UART RegOutput bits in the USB IO & Power Management register and the RCD pull-up resistors
will be applied internally to DP and DM. This will hold the UART in its default operating state.
While in UART mode, the transmit edge rates can be set to either the Full Speed USB or Low Speed
USB edge rates by using the XcvrSelect[1:0] bits in the Function Control register.
Revision 1.0 (10-08-12)
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Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
6.8
RID Converter Operation
The RID converter is designed to read the value of the ID resistance to ground and report back its
value through the ULPI interface.
When a resistor to ground is applied to the ID pin the state of the IdGnd comparator will change from
a 1 to a 0 as described in Section 5.7.1. If the USB3370 is in ULPI mode, an RXCMD will be generated
with bit 6 low. If the USB3370 is in Low Power Mode (or one of the other non-ULPI modes), the
DATA[3] interrupt signal will go high.
After the USB3370 has detected the change of state on the ID pin, the RID converter can be used to
determine the value of ID resistance. To start a ID resistance measurement, the RidConversionStart
bit is set in the Vendor Rid Conversion register.
The Link can use one of two methods to determine when the RID Conversion is complete. One method
is polling the RidConversionStart bit as described in Section 7.1.3.3. The preferred method is to set
the RidIntEn bit in the Vendor Rid Conversion register. When RidIntEn is set, an RXCMD will be
generated after the RID conversion is complete. As described in Table 6.3, the alt_int bit of the RXCMD
will be set.
After the RID Conversion is complete, the Link can read RidValue from the Vendor Rid Conversion
register.
SMSC USB3370B
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DATASHEET
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Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
Chapter 7 ULPI Register Map
7.1
ULPI Register Array
The USB3370 PHY implements all of the ULPI registers detailed in the ULPI revision 1.1 specification.
The complete USB3370 ULPI register set is shown in Table 7.1. All registers are 8 bits. This table also
includes the default state of each register upon POR or de-assertion of RESETB, as described in
Section 5.6.2. The RESET bit in the Function Control Register does not reset the bits of the ULPI
register array. The Link should not read or write to any registers not listed in this table.
The USB3370 supports extended register access. The immediate register set (00-3Fh) can be
accessed through either a immediate address or an extended register address.
Table 7.1 ULPI Register Map
ADDRESS (6BIT)
DEFAULT
STATE
READ
WRITE
SET
CLEAR
Vendor ID Low
24h
00h
-
-
-
Vendor ID High
04h
01h
-
-
-
Product ID Low
0Dh
02h
-
-
-
Product ID High
00h
03h
-
-
-
Function Control
41h
04-06h
04h
05h
06h
Interface Control
00h
07-09h
07h
08h
09h
OTG Control
06h
0A-0Ch
0Ah
0Bh
0Ch
USB Interrupt Enable Rising
1Fh
0D-0Fh
0Dh
0Eh
0Fh
USB Interrupt Enable Falling
1Fh
10-12h
10h
11h
12h
USB Interrupt Status (Note 7.1)
00h
13h
-
-
-
USB Interrupt Latch
00h
14h
-
-
-
Debug
00h
15h
-
-
-
Scratch Register
00h
16-18h
16h
17h
18h
Carkit Control
00h
19-1Bh
19h
1Ah
1Bh
Reserved
00h
Carkit Interrupt Enable
00h
1D-1Fh
1Dh
1Eh
1Fh
Carkit Interrupt Status
00h
20h
-
-
-
Carkit Interrupt Latch
00h
21h
-
-
-
Reserved
00h
HS Compensation Register
00h
31h
31h
-
-
USB-IF Charger Detection
00h
32h
32h
-
-
Reserved
00h
REGISTER NAME
Revision 1.0 (10-08-12)
64
1Ch
DATASHEET
22-30h
33-35h
SMSC USB3370B
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
Table 7.1 ULPI Register Map (continued)
ADDRESS (6BIT)
DEFAULT
STATE
READ
WRITE
SET
CLEAR
Vendor Rid Conversion
00h
36-38h
36h
37h
38h
USB IO & Power Management
04h
39-3Bh
39h
3Ah
3Bh
Reserved
00h
REGISTER NAME
Note 7.1
7.1.1
3C-3Fh
Dynamically updates to reflect current status of interrupt sources.
ULPI Register Set
The following registers are used for the ULPI interface.
7.1.1.1
Vendor ID Low
Address = 00h (read only)
FIELD NAME
BIT
ACCESS
DEFAULT
Vendor ID Low
7:0
rd
24h
7.1.1.2
DESCRIPTION
SMSC Vendor ID
Vendor ID High
Address = 01h (read only)
FIELD NAME
BIT
ACCESS
DEFAULT
Vendor ID High
7:0
rd
04h
7.1.1.3
DESCRIPTION
SMSC Vendor ID
Product ID Low
Address = 02h (read only)
FIELD NAME
BIT
ACCESS
DEFAULT
Product ID Low
7:0
rd
0Dh
7.1.1.4
DESCRIPTION
SMSC Product ID
Product ID High
Address = 03h (read only)
FIELD NAME
BIT
ACCESS
DEFAULT
Product ID High
7:0
rd
00h
SMSC USB3370B
DESCRIPTION
SMSC Product ID
65
DATASHEET
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Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
7.1.1.5
Function Control
Address = 04-06h (read), 04h (write), 05h (set), 06h (clear)
FIELD NAME
BIT
ACCESS
DEFAULT
XcvrSelect[1:0]
1:0
rd/w/s/c
01b
Selects the required transceiver speed.
00b: Enables HS transceiver
01b: Enables FS transceiver
10b: Enables LS transceiver
11b: Enables FS transceiver for LS packets (FS
preamble automatically pre-pended)
2
rd/w/s/c
0b
Controls the DP and DM termination depending on
XcvrSelect, OpMode, DpPulldown, and DmPulldown.
The DP and DM termination is detailed in Table 5.1.
4:3
rd/w/s/c
00b
Selects the required bit encoding style during
transmit.
00b: Normal Operation
01b: Non-Driving
10b: Disable bit-stuff and NRZI encoding
11b: Reserved
Reset
5
rd/w/s/c
0b
Active high transceiver reset. This reset does not
reset the ULPI interface or register set. Automatically
clears after reset is complete.
SuspendM
6
rd/w/s/c
1b
Active low PHY suspend. When cleared the PHY will
enter Low Power Mode as detailed in 6.5.
Automatically set when exiting Low Power Mode.
LPM Enable
7
rd/w/s/c
0b
When enabled the PLL start-up time is shortened to
allow fast start-up for LPM. The reduced PLL start-up
time is achieved by bypassing the VCO process
compensation which was done on initial start-up.
TermSelect
OpMode[1:0]
7.1.1.6
DESCRIPTION
Interface Control
Address = 07-09h (read), 07h (write), 08h (set), 09h (clear)
FIELD NAME
BIT
ACCESS
DEFAULT
6-pin FsLsSerialMode
0
rd/w/s/c
0b
When asserted the ULPI interface is redefined to the
6-pin Serial Mode. The PHY will automatically clear
this bit when exiting serial mode.
3-pin FsLsSerialMode
1
rd/w/s/c
0b
When asserted the ULPI interface is redefined to the
3-pin Serial Mode. The PHY will automatically clear
this bit when exiting serial mode.
CarkitMode
2
rd/w/s/c
0b
When asserted the ULPI interface is redefined to the
Carkit interface. The PHY will automatically clear this
bit when exiting Carkit Mode.
Revision 1.0 (10-08-12)
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DESCRIPTION
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Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
FIELD NAME
BIT
ACCESS
DEFAULT
ClockSuspendM
3
rd/w/s/c
0b
Enables Link to turn on 60MHz CLKOUT in Serial
Mode or Carkit Mode.
0b: Disable clock in serial or Carkit Mode.
1b: Enable clock in serial or Carkit Mode.
AutoResume
4
rd/w/s/c
0b
Only applicable in Host mode. Enables the PHY to
automatically transmit resume signaling. This
function is detailed in Section 6.4.1.4.
IndicatorComplement
5
rd/w/s/c
0b
Inverts the EXTVBUS signal. This function is detailed
in Section 5.7.2.
IndicatorPassThru
6
rd/w/s/c
0b
Disables and’ing the internal VBUS comparator with
the EXTVBUS signal when asserted. This function is
detailed in Section 5.7.2.
InterfaceProtectDisable
7
rd/w/s/c
0b
Used to disable the integrated STP pull-up resistor
used for interface protection. This function is detailed
in Section 6.5.4.
7.1.1.7
DESCRIPTION
OTG Control
Address = 0A-0Ch (read), 0Ah (write), 0Bh (set), 0Ch (clear)
FIELD NAME
BIT
ACCESS
DEFAULT
IdPullup
0
rd/w/s/c
0b
Connects a 100kΩ pull-up resistor from the ID pin to
VDD33
0b: Disables the pull-up resistor
1b: Enables the pull-up resistor
DpPulldown
1
rd/w/s/c
1b
Enables the 15k Ohm pull-down resistor on DP.
0b: Pull-down resistor not connected
1b: Pull-down resistor connected
DmPulldown
2
rd/w/s/c
1b
Enables the 15k Ohm pull-down resistor on DM.
0b: Pull-down resistor not connected
1b: Pull-down resistor connected
DischrgVbus
3
rd/w/s/c
0b
This bit is only used during SRP. Connects a resistor
from VBUS to ground to discharge VBUS.
0b: disconnect resistor from VBUS to ground
1b: connect resistor from VBUS to ground
ChrgVbus
4
rd/w/s/c
0b
This bit is only used during SRP. Connects a resistor
from VBUS to VDD33 to charge VBUS above the
SessValid threshold.
0b: disconnect resistor from VBUS to VDD33
1b: connect resistor from VBUS to VDD33
DrvVbus
5
rd/w/s/c
0b
Enables external 5 volt supply to drive 5 volts on
VBUS. This signal is or’ed with DrvVbusExternal.
0b: Do not drive Vbus, CPEN_N tri-stated.
1b: Drive Vbus, CPEN_N driven low.
SMSC USB3370B
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DESCRIPTION
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Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
FIELD NAME
BIT
ACCESS
DEFAULT
DrvVbusExternal
6
rd/w/s/c
0b
Enables external 5 volt supply to drive 5 volts on
VBUS. This signal is or’ed with DrvVbus.
0b: Do not drive Vbus, CPEN_N tri-stated.
1b: Drive Vbus, CPEN_N driven low.
UseExternalVbus
Indicator
7
rd/w/s/c
0b
Tells the PHY to use an external VBUS over-current
or voltage indicator. This function is detailed in
Section 5.7.2.
0b: Use the internal VbusValid comparator
1b: Use the EXTVBUS input as for VbusValid signal.
7.1.1.8
DESCRIPTION
USB Interrupt Enable Rising
Address = 0D-0Fh (read), 0Dh (write), 0Eh (set), 0Fh (clear)
FIELD NAME
BIT
ACCESS
DEFAULT
HostDisconnect Rise
0
rd/w/s/c
1b
Generate an interrupt event notification when
Hostdisconnect changes from low to high. Applicable
only in host mode.
VbusValid Rise
1
rd/w/s/c
1b
Generate an interrupt event notification when
Vbusvalid changes from low to high.
SessValid Rise
2
rd/w/s/c
1b
Generate an interrupt event notification when
SessValid changes from low to high.
SessEnd Rise
3
rd/w/s/c
1b
Generate an interrupt event notification when
SessEnd changes from low to high.
IdGnd Rise
4
rd/w/s/c
1b
Generate an interrupt event notification when IdGnd
changes from low to high.
7:5
rd
0h
Read only, 0.
Reserved
7.1.1.9
DESCRIPTION
USB Interrupt Enable Falling
Address = 10-12h (read), 10h (write), 11h (set), 12h (clear)
FIELD NAME
BIT
ACCESS
DEFAULT
HostDisconnect Fall
0
rd/w/s/c
1b
Generate an interrupt event notification when
Hostdisconnect changes from high to low. Applicable
only in host mode.
VbusValid Fall
1
rd/w/s/c
1b
Generate an interrupt event notification when
Vbusvalid changes from high to low.
SessValid Fall
2
rd/w/s/c
1b
Generate an interrupt event notification when
SessValid changes from high to low.
SessEnd Fall
3
rd/w/s/c
1b
Generate an interrupt event notification when
SessEnd changes from high to low.
IdGnd Fall
4
rd/w/s/c
1b
Generate an interrupt event notification when IdGnd
changes from high to low.
Reserved
7:5
rd
0h
Read only, 0.
Revision 1.0 (10-08-12)
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DESCRIPTION
DATASHEET
SMSC USB3370B
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
7.1.1.10
USB Interrupt Status
Address = 13h (read only)
This register dynamically updates to reflect current status of interrupt sources.
FIELD NAME
BIT
ACCESS
DEFAULT
DESCRIPTION
HostDisconnect
0
0b
Current value of the UTMI+ HS Hostdisconnect
output. Applicable only in host mode.
VbusValid
1
0b
Current value of the UTMI+ Vbusvalid output. If
VbusValid Rise and VbusValid Fall are set this
register will read 0.
SessValid
2
0b
Current value of the UTMI+ SessValid output. This
register will always read the current status of the
Session Valid comparator regardless of the
SessValid Rise and SessValid Fall settings.
SessEnd
3
0b
Current value of the UTMI+ SessEnd output. If
SessEnd Rise and SessEnd Fall are set this register
will read 0.
IdGnd
4
0b
Current value of the UTMI+ IdGnd output.
7:5
0h
Read only, 0.
Reserved
rd
(read
only)
Note: The default value is only valid after POR. When the register is read it will match the current
status of the comparators at the moment the register is read.
7.1.1.11
USB Interrupt Latch
Address = 14h (read only with auto clear)
FIELD NAME
BIT
ACCESS
DEFAULT
DESCRIPTION
HostDisconnect Latch
0
0b
Set to 1b by the PHY when an unmasked event
occurs on Hostdisconnect. Cleared when this register
is read. Applicable only in host mode.
VbusValid Latch
1
0b
Set to 1b by the PHY when an unmasked event
occurs on VbusValid. Cleared when this register is
read.
SessValid Latch
2
0b
Set to 1b by the PHY when an unmasked event
occurs on SessValid. Cleared when this register is
read.
SessEnd Latch
3
0b
Set to 1b by the PHY when an unmasked event
occurs on SessEnd. Cleared when this register is
read.
IdGnd Latch
4
0b
Set to 1b by the PHY when an unmasked event
occurs on IdGnd. Cleared when this register is read.
0h
Read only, 0.
Reserved
7:5
Note 7.2
SMSC USB3370B
rd
(Note 7.2)
rd
rd: Read Only with auto clear.
69
DATASHEET
Revision 1.0 (10-08-12)
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
7.1.1.12
Debug
Address = 15h (read only)
FIELD NAME
BIT
ACCESS
DEFAULT
Linestate[1:0]
1:0
rd
00b
Reserved
7:2
rd
000000b
7.1.1.13
DESCRIPTION
Contains the current value of Linestate[1:0].
Read only, 0.
Scratch Register
Address = 16-18h (read), 16h (write), 17h (set), 18h (clear)
FIELD NAME
BIT
ACCESS
DEFAULT
Scratch
7:0
rd/w/s/c
00h
7.1.2
DESCRIPTION
Empty register byte for testing purposes. Software
can read, write, set, and clear this register and the
PHY functionality will not be affected.
Carkit Control Registers
The following registers are used to set-up and enable the USB UART functions.
7.1.2.1
Carkit Control
Address = 19-1Bh (read), 19h (write), 1Ah (set), 1Bh (clear)
This register is used to program the USB3370 into and out of the Carkit Mode. When entering the
UART mode the Link must first set the desired TxdEn and the RxdEn bits and then transition to Carkit
Mode by setting the CarkitMode bit in the Interface Control Register. When RxdEn is not set then the
DATA[1] pin is held to a logic high.
FIELD NAME
BIT
ACCESS
DEFAULT
CarkitPwr
0
rd
0b
Read only, 0.
IdGndDrv
1
rd/w/s/c
0b
Drives ID pin to ground
TxdEn
2
rd/w/s/c
0b
Connects UART TXD (DATA[0]) to DM
RxdEn
3
rd/w/s/c
0b
Connects UART RXD (DATA[1]) to DP
Reserved
4
rd/w/s/c
0b
Reserved
5
rd/w/s/c
0b
Reserved
6
rd/w/s/c
0b
CarkitDataMC
7
rd/w/s/c
0b
7.1.2.2
DESCRIPTION
When set the UPLI DATA[2] pin is changed from a
driven 0 to tri-state, when carkit mode is entered.
Carkit Interrupt Enable
Address = 1D-1Fh (read), 1Dh (write), 1Eh (set), 1Fh (clear)
Revision 1.0 (10-08-12)
70
DATASHEET
SMSC USB3370B
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
FIELD NAME
BIT
ACCESS
DEFAULT
DESCRIPTION
IdFloatRise
0
rd/w/s/c
0b
When enabled an interrupt will be generated on the
alt_int of the RXCMD byte when the ID pin transitions
from non-floating to floating. The IdPullup bit in the
OTG Control register should be set.
IdFloatFall
1
rd/w/s/c
0b
When enabled an interrupt will be generated on the
alt_int of the RXCMD byte when the ID pin transitions
from floating to non-floating. The IdPullup bit in the
OTG Control register should be set.
VdatDetIntEn
2
rd/w/s/c
0b
When enabled an interrupt will be generated on the
alt_int of the RXCMD byte when the VDAT_DET
Comparator changes state.
CarDpRise
3
rd
0b
Not Implemented. Reads as 0b.
CarDpFall
4
rd
0b
Not Implemented. Reads as 0b.
RidIntEn
5
rd/w/s/c
0b
When enabled an interrupt will be generated on the
alt_int of the RXCMD byte when RidConversionDone
bit is asserted.
Note:
This register bit is or’ed with the RidIntEn bit
of the Vendor Rid Conversion register
described in Section 7.1.3.3.
Reserved
6
rd
0b
Read only, 0.
Reserved
7
rd
0b
Read only, 0.
7.1.2.3
Carkit Interrupt Status
Address = 20h (read only)
FIELD NAME
BIT
ACCESS
DEFAULT
DESCRIPTION
IdFloat
0
rd
0b
Asserted when the ID pin is floating. IdPullup must be
enabled.
VdatDet
1
rd
0b
VDAT_DET Comparator output
0b: No voltage is detected on DP
1b: Voltage detected on DP, IdatSinkEn must be set
to 1.
Note:
CarDp
SMSC USB3370B
2
rd
0b
VdatDet can also be read from the USB-IF
Charger Detection register described in
Section 7.1.3.3.
Not Implemented. Reads as 0b.
71
DATASHEET
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Datasheet
FIELD NAME
BIT
ACCESS
DEFAULT
RidValue
5:3
rd
000b
DESCRIPTION
Conversion value of Rid resistor
000: 0 ohms
001: 75 ohms
010: 102K ohms
011: 200K ohms
100: Reserved
101: ID floating
111: Error
Note:
RidConversionDone
6
rd
0b
Automatically asserted by the USB3370 when the
Rid Conversion is finished. The conversion will take
282uS. This bit will auto clear when the RidValue is
read from the Rid Conversion Register. Reading the
RidValue from the Carkit Interrupt Status register will
not clear either RidConversionDone status bit.
Note:
Reserved
7.1.2.4
7
rd
RidValue can also be read from the Vendor
Rid Conversion register described in
Section 7.1.3.3.
0b
RidConversionDone can also be read from
the Vendor Rid Conversion register
described in Section 7.1.3.3.
Read only, 0.
Carkit Interrupt Latch
Address = 21h (read only with auto-clear)
FIELD NAME
BIT
ACCESS
DEFAULT
IdFloat Latch
0
rd
(Note 7.3)
0b
Asserted if the state of the ID pin changes from nonfloating to floating while the IdFloatRise bit is enabled
or if the state of the ID pin changes from floating to
non-floating while the IdFloatFall bit is enabled.
VdatDet Latch
1
rd
0b
If VdatDetIntEn is set and the VdatDet bit changes
state, this bit will be asserted.
CarDp Latch
2
rd
0b
Not Implemented. Reads as 0b.
RidConversionLatch
3
rd
(Note 7.3)
0b
If RidIntEn is set and the state of the
RidConversionDone bit changes from a 0 to 1 this bit
will be asserted.
7:4
rd
0000b
Reserved
Note 7.3
7.1.3
DESCRIPTION
Read only, 0.
rd: Read Only with auto clear
Vendor Register Access
The vendor specific registers include the range from 30h to 3Fh. These can be accessed by the ULPI
immediate register read / write.
7.1.3.1
HS Compensation Register
Address = 31h (read / write)
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SMSC USB3370B
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
The USB3370 is designed to meet the USB specifications and requirements when the DP and DM
signals are properly designed on the PCB. The DP and DM trace impedance should be 45ohm single
ended and 90ohm differential. In cases where the DP and DM traces are not able to meet these
requirements the HS Compensation register can be used to compensate for the losses in signal
amplitude.
FIELD NAME
BIT
ACCESS
DEFAULT
VariSense
1:0
rd/w
00b
Used to lower the threshold of the squelch detector.
00: 100% (default)
01: 83%
10: 66.7%
11: 50%
Reserved
2
rd
0b
Read only, 0.
Reserved
3
rd
0b
Read only, 0.
PHYBoost
6:4
rd/w
000b
Reserved
7
rd
0b
7.1.3.2
DESCRIPTION
Used to change the output voltage of the Hi-Speed
transmitter
000: Nominal
001: +3.7%
010: +7.4%
011: +11.0%
100: +14.7%
101: +18.3%
110: +22.0%
111: +25.7%
Read only, 0.
USB-IF Charger Detection
Address = 32h (read / write)
FIELD NAME
BIT
ACCESS
DEFAULT
VDatSrcEn
0
rd/w
0
VDAT_SRC voltage enable
0b: Disabled
1b: Enabled
IDatSinkEn
1
rd/w
0
IDAT_SINK current sink and VDAT_DET comparator
enable
0b: Disabled, VDAT_DET = 0.
1b: Enabled
ContactDetectEn
2
rd/w
0
IDP_SRC Enable
0b: Disabled
1b: Enabled
HostChrgEn
3
rd/w
0
Enable Charging Host Port Mode.
0b: Portable Device
1b: Charging Host Port. When the charging host port
bit is set the connections of VDAT_SRC, IDAT_SINK,
IDP_SRC, and VDAT_DET are reversed between DP
and DM.
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Revision 1.0 (10-08-12)
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
FIELD NAME
VdatDet
BIT
ACCESS
DEFAULT
4
rd
0
DESCRIPTION
VDAT_DET Comparator output. IdatSinkEn must be set
to 1 to enable the comparator.
0b: No voltage is detected on DP or Linestate[1:0] is
not equal to 00b.
1b: Voltage detected on DP, and Linestate[1:0] = 00b.
Note:
Reserved
5-7
rd
VdatDet can also be read from the Carkit
Interrupt Status register described in
Section 7.1.2.3.
Read only, 0.
Note: The charger detection should be turned off before beginning USB operation. USB-IF Charger
Detection Bits 2:0 should be set to 000b.
7.1.3.3
Vendor Rid Conversion
Address = 36-38h (read), 36h (write), 37h (set), 38h (clear)
FIELD NAME
BIT
ACCESS
DEFAULT
RidValue
2:0
rd/w
000b
DESCRIPTION
Conversion value of Rid resistor
000: 0 ohms
001: 75 ohms
010: 100K ohms
011: 200K ohms
100: 440K ohms
101: ID floating
111: Error
Note:
RidConversionDone
3
rd
(Note 7.4)
0b
RidValue can also be read from the Carkit
Interrupt Status Register.
Automatically asserted by the USB3370 when the
Rid Conversion is finished. The conversion will take
282uS. This bit will auto clear when the RidValue is
read from the Rid Conversion Register. Reading the
RidValue from the Carkit Interrupt Status Register will
not clear either RidConversionDone status bit.
Note:
RidConversionDone can also be read from
the Carkit Interrupt Status Register.
RidConversionStart
4
rd/w/s/c
0b
When this bit is asserted either through a register
write or set, the Rid converter will read the value of
the ID resistor. When the conversion is complete this
bit will auto clear.
Reserved
5
rd/w/s/c
0b
This bit must remain at 0.
RidIntEn
6
rd/w/s/c
0b
When enabled an interrupt will be generated on the
alt_int of the RXCMD byte when RidConversionDone
bit is asserted.
Note:
Reserved
7
Note 7.4
Revision 1.0 (10-08-12)
rd
0b
This register bit is or’ed with the RidIntEn bit
of the Carkit Interrupt Status register.
Read only, 0.
rd: Read Only with auto clear.
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SMSC USB3370B
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
7.1.3.4
USB IO & Power Management
Address = 39-3Bh (read), 39h (write), 3Ah (set), 3Bh (clear)
FIELD NAME
BIT
ACCESS
DEFAULT
Reserved
0
rd/w/s/c
0b
Read only, 0.
SwapDP/DM
1
rd/w/s/c
0b
When asserted, the DP and DM pins of the USB
transceiver are swapped. This bit can be used to
prevent crossing the DP/DM traces on the board. In
UART mode, it swaps the routing to the DP and DM
pins.
3:2
rd/w/s/c
01b
Controls the output voltage of the VBAT to VDD33
regulator in UART mode. When the PHY is switched
from USB mode to UART mode regulator output will
automatically change to the value specified in this
register when TxdEn is asserted.
00: 3.3V
01: 3.0V (default)
10: 2.75V
11: 2.5V
ChargerPullupEnDP
4
rd/w/s/c
0b
Enables the RCD Pull-up resistor on the DP pin. (The
pull-up is automatically enabled in UART mode)
ChargerPullupEnDM
5
rd/w/s/c
0b
Enables the RCD Pull-up resistor on the DM pin. (The
pull-up is automatically enabled in UART mode)
7:6
rd/w/s/c
00b
Controls the output voltage of the VBAT to VDD33
regulator in USB mode. When the PHY is in
Synchronous Mode, Serial Mode, or Low Power
Mode, the regulator output will be the value specified
in this register.
00: 3.3V (default)
01: 3.0V
10: 2.75V
11: 2.5V
UART RegOutput
USB RegOutput
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Revision 1.0 (10-08-12)
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
Chapter 8 Application Notes
8.1
Application Diagrams
The USB3370 requires few external components as shown in the application diagrams. The USB 2.0
Specification restricts the voltage at the VBUS pin to a maximum value of 5.25V. In some applications,
the voltage will exceed this limit, so the USB3370 provides an integrated over voltage protection circuit.
The over voltage protection circuit works with an external resistor (RVBUS) to lower the voltage at the
VBUS pin.
Table 8.1 Component Values in Application Diagrams
REFERENCE
DESIGNATOR
VALUE
DESCRIPTION
NOTES
COUT
See Table 4.10
Bypass capacitor to ground (<1Ω ESR)
for regulator stability.
Place as close as possible to the
PHY.
CVBUS
See Table 8.2
Capacitor to ground required by the USB
Specification. SMSC recommends <1Ω
ESR.
Place near the USB connector.
CBYP
System
dependent.
Bypass capacitor to ground. Typical
values used are 0.1 or 0.01 μF.
Place as close as possible to the
PHY.
CDC_LOAD
System
dependent.
The USB connector housing may be ACcoupled to the device ground.
Industry convention is to ground
only the host side of the cable
shield.
RVBUS
1kΩ or 20kΩ
Series resistor to work with internal over
voltage protection.
See Section 5.7.2.6 for
information regarding power
dissipation.
RBIAS
10kΩ (±1%)
Series resistor to establish reference
voltage.
See Section 5.3 for information
regarding power dissipation.
Table 8.2 Capacitance Values at VBUS of USB Connector
MODE
MIN VALUE
Host
120μF
Device
1μF
10μF
OTG
1μF
6.5μF
Revision 1.0 (10-08-12)
MAX VALUE
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DATASHEET
SMSC USB3370B
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
Link Controller
VBUS Switch
EN
5V
IN
FAULT
CPEN_N
EXTVBUS
RVBUS must be
installed to enable
overvoltage
protection of the
VBUS pin.
RVBUS
VBUS
OUT
The capacitor CVBUS
must be installed on
this side of RVBUS.
RESETB
RESETB
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
STP
NXT
DIR
CLKOUT
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
STP
NXT
DIR
CLKIN
3.0-5.5V
Supply
XO
Resonator
VBAT
CBYP
USB
Receptacle
VDD33
CVBUS
- or -
REFCLK
COUT
VBUS
ID
ID
DM
DM
DP
SHIELD
GND
Crystal
and Caps
CLOAD
VDDIO Supply
VDDIO
DP
CBYP
VDD18
For Host applications (nonOTG), the ID pin should be
connected to GND.
COUT
RBIAS
GND
RBIAS
Figure 8.1 USB3370 Application Diagram (Host configured for ULPI Clock Input Mode)
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Revision 1.0 (10-08-12)
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
RVBUS must be installed to
enable overvoltage
protection of the VBUS pin.
Link Controller
CPEN_N
EXTVBUS
RVBUS
VBUS
3.0-5.5V
Supply
The capacitor CVBUS
must be installed on
this side of RVBUS.
USB
Receptacle
VBAT
CBYP
VDD33
CVBUS
COUT
RESETB
RESETB
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
STP
NXT
DIR
CLKOUT
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
STP
NXT
DIR
CLKIN
REFCLK
XO
REFCLK
ID
VBUS
DM
DM
DP
DP
VDDIO Supply
VDDIO
GND
CBYP
VDD18
SHIELD
COUT
CDC_BLOCK
GND
RBIAS
RBIAS
Figure 8.2 USB3370 Application Diagram (Device configured for ULPI Clock Output Mode)
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SMSC USB3370B
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
RVBUS must be installed to
enable overvoltage
protection of the VBUS pin.
VBUS Switch
5V
EN OUT
IN
RVBUS
VBUS
3.0-5.5V
Supply
The capacitor CVBUS
must be installed on
this side of RVBUS.
USB
Receptacle
Link Controller
CPEN_N
EXTVBUS
VBAT
CBYP
VDD33
CVBUS
COUT
ID
VBUS
DM
DM
DP
DP
RESETB
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
STP
NXT
DIR
CLKOUT
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
STP
NXT
DIR
CLKIN
REFCLK
XO
REFCLK
VDDIO Supply
VDDIO
CBYP
VDD18
SHIELD
GND
RESETB
COUT
CDC_BLOCK
GND
RBIAS
RBIAS
USB3370 Application Diagram (Host configured for ULPI Clock Output Mode)
8.2
USB Charger Detection
The USB3370 provides the hardware described in the USB Battery Charging Specification. SMSC
provides an Application Note which describes how to use the USB3370 in a battery charging
application.
8.3
Reference Designs
SMSC has generated reference designs for connecting the USB3370 to SoCs with a ULPI port. Please
contact the SMSC sales office for more details.
8.4
ESD Performance
The USB3370 is protected from ESD strikes. By eliminating the requirement for external ESD
protection devices, board space is conserved, and the board manufacturer is enabled to reduce cost.
The advanced ESD structures integrated into the USB3370 protect the device whether or not it is
powered up.
8.4.1
Human Body Model (HBM) Performance
HBM testing verifies the ability to withstand the ESD strikes like those that occur during handling and
manufacturing, and is done without power applied to the IC. To pass the test, the device must have
no change in operation or performance due to the event. The USB3370 HBM performance is detailed
in Table 4.12.
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Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
8.4.2
EN/IEC 61000-4-2 Performance
The EN/IEC 61000-4-2 ESD specification is an international standard that addresses system-level
immunity to ESD strikes while the end equipment is operational. In contrast, the HBM ESD tests are
performed at the device level with the device powered down.
SMSC contracts with Independent laboratories to test the USB3370 to EN/IEC 61000-4-2 in a working
system. Reports are available upon request. Please contact your SMSC representative, and request
information on 3rd party ESD test results. The reports show that systems designed with the USB3370
can safely provide the ESD performance shown in Table 4.12 without additional board level protection.
In addition to defining the ESD tests, EN/IEC 61000-4-2 also categorizes the impact to equipment
operation when the strike occurs (ESD Result Classification). The USB3370 maintains an ESD Result
Classification 1 or 2 when subjected to an EN/IEC 61000-4-2 (level 4) ESD strike.
Both air discharge and contact discharge test techniques for applying stress conditions are defined by
the EN/IEC 61000-4-2 ESD document.
8.4.2.1
Air Discharge
To perform this test, a charged electrode is moved close to the system being tested until a spark is
generated. This test is difficult to reproduce because the discharge is influenced by such factors as
humidity, the speed of approach of the electrode, and construction of the test equipment.
8.4.2.2
Contact Discharge
The uncharged electrode first contacts the USB connector to prepare this test, and then the probe tip
is energized. This yields more repeatable results, and is the preferred test method. The independent
test laboratories contracted by SMSC provide test results for both types of discharge methods.
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Datasheet
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Figure 9.1 USB3370 32-pin QFN, 5x5mm Body, 0.5mm Pitch
SMSC USB3370B
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DATASHEET
Revision 1.0 (10-08-12)
Chapter 9 Package Outline
Revision 1.0 (10-08-12)
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Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
SMSC USB3370B
Figure 9.2 32QFN, 5x5 Tape and Reel
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
Figure 9.3 32QFN, 5x5 Reel Dimensions
SMSC USB3370B
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DATASHEET
Revision 1.0 (10-08-12)
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
Figure 9.4 32QFN Tape Length and Part Quantity
Figure 9.5 32QFN, 5x5 Package Marking
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SMSC USB3370B
Enhanced Single Supply Hi-Speed USB ULPI Transceiver
Datasheet
Chapter 10 Datasheet Revision History
Table 10.1 Customer Revision History
REVISION LEVEL & DATE
Rev. 1.0 (10-08-12)
SMSC USB3370B
SECTION/FIGURE/ENTRY
CORRECTION
Initial datasheet release
85
DATASHEET
Revision 1.0 (10-08-12)
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