Altera Arria GX EP1AGX20C, EP1AGX35C, EP1AGX35D, EP1AGX50C, EP1AGX50D, EP1AGX60C, EP1AGX60D, EP1AGX60E, EP1AGX90E FPGA Device Handbook
Below you will find brief information for Arria GX EP1AGX20C, Arria GX EP1AGX35C, Arria GX EP1AGX35D, Arria GX EP1AGX50C, Arria GX EP1AGX50D, Arria GX EP1AGX60C, Arria GX EP1AGX60D, Arria GX EP1AGX60E, Arria GX EP1AGX90E. Arria GX family of devices combines 3.125 Gbps serial transceivers with reliable packaging technology and a proven logic array. Arria GX devices include 4 to 12 high-speed transceiver channels, each incorporating clock data recovery (CDR) technology and embedded SERDES circuitry designed to support PCI-Express, Gigabit Ethernet, SDI, SerialLite II, XAUI, and Serial RapidIO protocols.
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Arria GX Device Handbook,
Volume 1
101 Innovation Drive
San Jose, CA 95134 www.altera.com
Software Version:
Document Version:
Document Date:
9.1
2.0
© December 2009
Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services
.
AGX5V1-2.0
Contents
Chapter Revision Dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .vii
Section I. Arria GX Device Data Sheet
Chapter 1. Arria GX Device Family Overview
Chapter 2. Arria GX Architecture
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
iv Contents
On-Chip Differential Termination (R
D
OCT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-96
OCT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-97
Chapter 3. Configuration and Testing
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Contents
Chapter 4. DC and Switching Characteristics
v
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
vi Contents
Chapter 5. Reference and Ordering Information
Additional Information
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter Revision Dates
The chapters in this book,
Arria GX Device Handbook, Volume 1
, were revised on the following dates. Where chapters or groups of chapters are available separately, part numbers are listed.
Chapter 1 Arria GX Device Family Overview
Chapter 2 Arria GX Architecture
Chapter 3 Configuration and Testing
Chapter 4 DC and Switching Characteristics
Chapter 5 Reference and Ordering Information
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
viii Chapter Revision Dates
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Section I. Arria GX Device Data Sheet
■
■
■
This section provides designers with the data sheet specifications for Arria
®
GX devices. They contain feature definitions of the transceivers, internal architecture, configuration, and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power consumption, and ordering information for Arria GX devices.
■
■
This section includes the following chapters:
Chapter 1, Arria GX Device Family Overview
Chapter 2, Arria GX Architecture
Chapter 3, Configuration and Testing
Chapter 4, DC and Switching Characteristics
Chapter 5, Reference and Ordering Information
Revision History
Refer to each chapter for its own specific revision history. For information about when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook.
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
I–2 Section I: Arria GX Device Data Sheet
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
1. Arria GX Device Family Overview
AGX51001-2.0
Introduction
The Arria ® GX family of devices combines 3.125 Gbps serial transceivers with reliable packaging technology and a proven logic array. Arria GX devices include 4 to 12 high-speed transceiver channels, each incorporating clock data recovery (CDR) technology and embedded SERDES circuitry designed to support PCI-Express,
Gigabit Ethernet, SDI, SerialLite II, XAUI, and Serial RapidIO protocols, along with the ability to develop proprietary, serial-based IP using its Basic mode. The transceivers build upon the success of the Stratix ® II GX family. The Arria GX FPGA technology offers a 1.2-V logic array with the right level of performance and dependability needed to support these mainstream protocols.
Features
The key features of Arria GX devices include:
■ Transceiver block features
■
■
■
High-speed serial transceiver channels with CDR support up to 3.125 Gbps.
Devices available with 4, 8, or 12 high-speed full-duplex serial transceiver channels
Support for the following CDR-based bus standards—PCI Express, Gigabit
Ethernet, SDI, SerialLite II, XAUI, and Serial RapidIO, along with the ability to develop proprietary, serial-based IP using its Basic mode
■
■
■
■
■
■
■
■
Individual transmitter and receiver channel power-down capability for reduced power consumption during non-operation
1.2- and 1.5-V pseudo current mode logic (PCML) support on transmitter output buffers
Receiver indicator for loss of signal (available only in PCI Express [PIPE] mode)
Hot socketing feature for hot plug-in or hot swap and power sequencing support without the use of external devices
Dedicated circuitry that is compliant with PIPE, XAUI, Gigabit Ethernet, Serial
Digital Interface (SDI), and Serial RapidIO
8B/10B encoder/decoder performs 8-bit to 10-bit encoding and 10-bit to 8-bit decoding
Phase compensation FIFO buffer performs clock domain translation between the transceiver block and the logic array
Channel aligner compliant with XAUI
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
1–2 Chapter 1: Arria GX Device Family Overview
Features
■ Main device features:
■
TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers with performance up to
380 MHz
■
■
■
■
■
Up to 16 global clock networks with up to 32 regional clock networks per device
High-speed DSP blocks provide dedicated implementation of multipliers, multiply-accumulate functions, and finite impulse response (FIR) filters
Up to four enhanced phase-locked loops (PLLs) per device provide spread spectrum, programmable bandwidth, clock switch-over, and advanced multiplication and phase shifting
Support for numerous single-ended and differential I/O standards
High-speed source-synchronous differential I/O support on up to 47 channels
■
■
■
Support for source-synchronous bus standards, including SPI-4 Phase 2
(POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1
Support for high-speed external memory including DDR and DDR2 SDRAM, and SDR SDRAM
Support for multiple intellectual property megafunctions from Altera
®
MegaCore ® functions and Altera Megafunction Partners Program (AMPP SM )
■
Support for remote configuration updates
Table 1–1 lists Arria GX device features for FineLine BGA (FBGA) with flip chip
packages.
Table 1–1. Arria GX Device Features (Part 1 of 2)
EP1AGX20C EP1AGX35C/D
Feature
Package
C
484-pin,
780-pin
(Flip chip)
C
484-pin
(Flip chip)
D
780-pin
(Flip chip)
8,632 13,408
EP1AGX50C/D
C
484-pin
D
780-pin,
(Flip chip) 1152-pin
(Flip chip)
20,064 ALMs
Equivalent logic elements
(LEs)
Transceiver channels
Transceiver data rate
21,580
4
600 Mbps to 3.125
Gbps
4
33,520
8
600 Mbps to 3.125
Gbps
4
50,160
600 Mbps to 3.125
Gbps
8
Sourcesynchronous receive channels
31 31 31 31 31, 42
EP1AGX60C/D/E EP1AGX90E
C
484-pin
(Flip chip)
D
780-pin
(Flip chip)
E
1152-pin
(Flip chip)
E
1152-pin
(Flip chip)
4
31
24,040
60,100
8
31
12
600 Mbps to 3.125 Gbps
42
36,088
90,220
12
600 Mbps to 3.125
Gbps
47
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 1: Arria GX Device Family Overview
Features
1–3
Table 1–1. Arria GX Device Features (Part 2 of 2)
EP1AGX20C EP1AGX35C/D
Feature
C C D
Sourcesynchronous transmit channels
M512 RAM blocks
(32 × 18 bits)
M4K RAM blocks
(128 × 36 bits)
M-RAM blocks
(4096 × 144 bits)
Total RAM bits
Embedded multipliers
(18 × 18)
DSP blocks
PLLs
Maximum user I/O pins
29
166
118
1
1,229,184
40
10
4
230, 341
29
230
197
140
1
1,348,416
56
14
4
29
341
EP1AGX50C/D
C D
29
313
242
2
29, 42
2,475,072
104
4
229
26
4, 8
350, 514
C
EP1AGX60C/D/E
D E
29
229
4
29
326
252
2
2,528,640
128
32
350
42
8
514
EP1AGX90E
E
4,477,824
Arria GX devices are available in space-saving FBGA packages (refer to
Arria GX devices support vertical migration within the same package. With vertical migration support, designers can migrate to devices whose dedicated pins, configuration pins, and power pins are the same for a given package across device densities. For I/O pin migration across densities, the designer must cross-reference the available I/O pins with the device pin-outs for all planned densities of a given package type to identify which I/O pins are migratable.
45
478
400
4
176
44
8
538
Table 1–2. Arria GX Package Options (Pin Counts and Transceiver Channels) (Part 1 of 2)
Source-Synchronous Channels Maximum User I/O Pin Count
Device
Transceiver
Channels
Receive Transmit
484-Pin FBGA
(23 mm)
780-Pin FBGA
(29 mm)
EP1AGX20C
EP1AGX35C
EP1AGX50C
EP1AGX60C
EP1AGX35D
EP1AGX50D
4
4
8
4
4
8
31
31
31
31
31
31, 42
29
29
29
29
29
29, 42
230
230
229
229
—
—
341
—
—
—
341
350
1152-Pin
FBGA
(35 mm)
—
—
—
—
—
514
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
1–4 Chapter 1: Arria GX Device Family Overview
Document Revision History
Table 1–2. Arria GX Package Options (Pin Counts and Transceiver Channels) (Part 2 of 2)
Source-Synchronous Channels Maximum User I/O Pin Count
Device
Transceiver
Channels
Receive Transmit
484-Pin FBGA
(23 mm)
780-Pin FBGA
(29 mm)
EP1AGX60D
EP1AGX60E
EP1AGX90E
8
12
12
31
42
47
29
42
45
—
—
—
350
—
—
1152-Pin
FBGA
(35 mm)
—
514
538
Table 1–3 lists the Arria GX device package sizes.
Table 1–3. Arria GX FBGA Package Sizes
Dimension
Pitch (mm)
Area (mm
2
)
Length × width
(mm × mm)
484 Pins
1.00
529
23 × 23
780 Pins
1.00
841
29 × 29
1152 Pins
1.00
1225
35 × 35
Document Revision History
Table 1–4 lists the revision history for this chapter.
Table 1–4. Document Revision History
Date and Document Version
December 2009, v2.0
May 2008, v1.2
June 2007, v1.1
May 2007, v1.0
Changes Made
■
Document template update.
■
Minor text edits.
Included support for SDI,
SerialLite II, and XAUI.
Included GIGE information.
Initial Release
Summary of Changes
—
—
—
—
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
2. Arria GX Architecture
AGX51002-2.0
Transceivers
■
■
■
■
■
Arria ® GX devices incorporate up to 12 high-speed serial transceiver channels that build on the success of the Stratix ® II GX device family. Arria GX transceivers are structured into full-duplex (transmitter and receiver) four-channel groups called transceiver blocks located on the right side of the device. You can configure the transceiver blocks to support the following serial connectivity protocols
(functional modes):
PCI Express (PIPE)
Gigabit Ethernet (GIGE)
XAUI
Basic (600 Mbps to 3.125 Gbps)
SDI (HD, 3G)
■ Serial RapidIO (1.25 Gbps, 2.5 Gbps, 3.125 Gbps)
Transceivers within each block are independent and have their own set of dividers.
Therefore, each transceiver can operate at different frequencies. Each block can select from two reference clocks to provide two clock domains that each transceiver can select from.
Table 2–1 lists the number of transceiver channels for each member of the Arria GX
family.
Table 2–1. Arria GX Transceiver Channels
Device
EP1AGX20C
EP1AGX35C
EP1AGX35D
EP1AGX50C
EP1AGX50D
EP1AGX60C
EP1AGX60D
EP1AGX60E
EP1AGX90E
Number of Transceiver Channels
8
4
8
12
8
4
4
4
12
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–2 Chapter 2: Arria GX Architecture
Transceivers
shows a high-level diagram of the transceiver block architecture divided into four channels.
Figure 2–1. Transceiver Block
Transceiver Block
Arria GX
Logic Array
Channel 1
Channel 0
Supporting Blocks
(PLLs, State Machines,
Programming)
Channel 2
Channel 3
RX1
TX1
RX0
TX0
REFCLK_1
REFCLK_0
RX2
TX2
RX3
TX3
Each transceiver block has:
■
Four transceiver channels with dedicated physical coding sublayer (PCS) and physical media attachment (PMA) circuitry
■
■
One transmitter PLL that takes in a reference clock and generates high-speed serial clock depending on the functional mode
Four receiver PLLs and clock recovery unit (CRU) to recover clock and data from the received serial data stream
■ State machines and other logic to implement special features required to support each protocol
shows functional blocks that make up a transceiver channel.
Figure 2–2. Arria GX Transceiver Channel Block Diagram
PMA Analog Section
Deserializer n
(1)
Clock
Recovery
Unit
PCS Digital Section
Word
Aligner
XAUI
Lane
Deskew
Reference
Clock
Receiver
PLL
Reference
Clock
Transmitter
PLL
Serializer n
(1)
8B/10B
Encoder
Rate
Matcher
8B/10B
Decoder
Byte
Serializer
Byte
Deserializer
Phase
Compensation
FIFO Buffer m
(2)
Phase
Compensation
FIFO Buffer
FPGA Fabric
m
(2)
:
(1) “n” represents the number of bits in each word that must be serialized by the transmitter portion of the PMA. n = 8 or 10.
(2) “m” represents the number of bits in the word that passes between the FPGA logic and the PCS portion of the transceiver. m = 8, 10, 16, or 20.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
Transceivers
2–3
Each transceiver channel is full-duplex and consists of a transmitter channel and a receiver channel.
The transmitter channel contains the following sub-blocks:
■
■
■
■
■
Transmitter phase compensation first-in first-out (FIFO) buffer
Byte serializer (optional)
8B/10B encoder (optional)
Serializer (parallel-to-serial converter)
Transmitter differential output buffer
The receiver channel contains the following:
■
■
■
■
■
■
■
■
■
■
■
Receiver differential input buffer
Receiver lock detector and run length checker
CRU
Deserializer
Pattern detector
Word aligner
Lane deskew
Rate matcher (optional)
8B/10B decoder (optional)
Byte deserializer (optional)
Receiver phase compensation FIFO buffer
You can configure the transceiver channels to the desired functional modes using the
ALT2GXB MegaCore instance in the Quartus
®
II MegaWizard
™
Plug-in Manager for the Arria GX device family. Depending on the selected functional mode, the
Quartus II software automatically configures the transceiver channels to employ a subset of the sub-blocks listed above.
Transmitter Path
This section describes the data path through the Arria GX transmitter. The sub-blocks are described in order from the PLD-transmitter parallel interface to the serial transmitter buffer.
Clock Multiplier Unit
Each transceiver block has a clock multiplier unit (CMU) that takes in a reference clock and synthesizes two clocks: a high-speed serial clock to serialize the data and a low-speed parallel clock to clock the transmitter digital logic (PCS).
■
■
■
The CMU is further divided into three sub-blocks:
One transmitter PLL
One central clock divider block
Four local clock divider blocks (one per channel)
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–4 Chapter 2: Arria GX Architecture
Transceivers
shows the block diagram of the clock multiplier unit.
Figure 2–3. Clock Multiplier Unit
CMU Block
Transmitter Channels [3:2]
Transmitter High-Speed Serial and Low-Speed Parallel Clocks
TX Clock
Divider Block
Gen Block
Reference Clock from REFCLKs,
Global Clock (1),
Inter-Transceiver
Lines
Transmitter
PLL
Central Clock
Divider
Block
Transmitter High-Speed Serial and Low-Speed Parallel Clocks
TX Clock
Divider Block
Gen Block
Transmitter Channels [1:0]
The transmitter PLL multiplies the input reference clock to generate the high-speed serial clock required to support the intended protocol. It implements a half-rate voltage controlled oscillator (VCO) that generates a clock at half the frequency of the serial data rate for which it is configured.
shows the block diagram of the transmitter PLL.
Figure 2–4. Transmitter PLL
Transmitter PLL
/M
(1)
To
Inter-Transceiver Lines
Dedicated
REFCLK0
/2
Dedicated
REFCLK1
/2
Inter-Transceiver Lines[2:0]
Global Clock
(2)
INCLK
Phase
Frequency
Detector up down
Charge
Pump + Loop
Filter
Voltage
Controlled
Oscillator
/L
(1)
High Speed
Serial Clock
:
(1) You only need to select the protocol and the available input reference clock frequency in the ALTGXB MegaWizard Plug-In Manager. Based on your selections, the MegaWizard Plug-In Manager automatically selects the necessary /M and /L dividers (clock multiplication factors).
(2) The global clock line must be driven from an input pin only.
The reference clock input to the transmitter PLL can be derived from:
■
One of two available dedicated reference clock input pins (REFCLK0 or REFCLK1) of the associated transceiver block
■ PLD global clock network (must be driven directly from an input clock pin and cannot be driven by user logic or enhanced PLL)
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
Transceivers
2–5
■ Inter-transceiver block lines driven by reference clock input pins of other transceiver blocks
1
Altera ® recommends using the dedicated reference clock input pins (REFCLK0 or
REFCLK1
) to provide reference clock for the transmitter PLL.
Table 2–2 lists the adjustable parameters in the transmitter PLL.
Table 2–2. Transmitter PLL Specifications
Parameter
Input reference frequency range
Data rate support
Bandwidth
Specifications
50 MHz to 622.08 MHz
600 Mbps to 3.125 Gbps
Low, medium, or high
The transmitter PLL output feeds the central clock divider block and the local clock divider blocks. These clock divider blocks divide the high-speed serial clock to generate the low-speed parallel clock for the transceiver PCS logic and
PLD-transceiver interface clock.
Transmitter Phase Compensation FIFO Buffer
A transmitter phase compensation FIFO is located at each transmitter channel’s logic array interface. It compensates for the phase difference between the transmitter PCS clock and the local PLD clock. The transmitter phase compensation FIFO is used in all supported functional modes. The transmitter phase compensation FIFO buffer is eight words deep in PCI Express (PIPE) mode and four words deep in all other modes.
f
For more information about architecture and clocking, refer to the
Arria GX Transceiver
Architecture
chapter.
Byte Serializer
The byte serializer takes in two-byte wide data from the transmitter phase compensation FIFO buffer and serializes it into a one-byte wide data at twice the speed. The transmit data path after the byte serializer is 8 or 10 bits. This allows clocking the PLD-transceiver interface at half the speed when compared with the transmitter PCS logic. The byte serializer is bypassed in GIGE mode. After serialization, the byte serializer transmits the least significant byte (LSByte) first and the most significant byte (MSByte) last.
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–6 Chapter 2: Arria GX Architecture
Transceivers
shows byte serializer input and output. datain[15:0] is the input to the byte serializer from the transmitter phase compensation FIFO; dataout[7:0] is the output of the byte serializer.
Figure 2–5. Byte Serializer Operation
datain[15:0]
D1
{8'h00,8'h01} dataout[7:0]
xxxxxxxxxx xxxxxxxxxx
Note to
(1) datain may be 16 or 20 bits. dataout may be 8 or 10 bits.
D2
{8'h02,8'h03}
D1
LSByte
8'h01
D1
MSByte
8'h00
D2
LSByte
8'h03
D3 xxxx
D2
MSByte
8'h02
8B/10B Encoder
The 8B/10B encoder block is used in all supported functional modes. The 8B/10B encoder block takes in 8-bit data from the byte serializer or the transmitter phase compensation FIFO buffer. It generates a 10-bit code group with proper running disparity from the 8-bit character and a 1-bit control identifier (tx_ctrlenable).
When tx_ctrlenable is low, the 8-bit character is encoded as data code group
(Dx.y). When tx_ctrlenable is high, the 8-bit character is encoded as a control code group (Kx.y). The 10-bit code group is fed to the serializer. The 8B/10B encoder conforms to the IEEE 802.3 1998 edition standard.
f
For additional information regarding 8B/10B encoding rules, refer to the
Specifications and Additional Information
chapter.
shows the 8B/10B conversion format.
Figure 2–6. 8B/10B Encoder
7
H
6
G
5
F
4
E
3
D
2
C
1
B
0
A
Ctrl
MSB
8B-10B Conversion j
9 h
8 g
7 f
6 i
5 e
4 d
3 c
2 b
1 a
0
LSB
During reset (tx_digitalreset), the running disparity and data registers are cleared and the 8B/10B encoder continously outputs a K28.5 pattern from the
RD-column. After out of reset, the 8B/10B encoder starts with a negative disparity
(RD-) and transmits three K28.5 code groups for synchronizing before it starts encoding the input data or control character.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
Transceivers
2–7
Transmit State Machine
The transmit state machine operates in either PCI Express (PIPE) mode, XAUI mode, or GIGE mode, depending on the protocol used.
GIGE Mode
In GIGE mode, the transmit state machine converts all idle ordered sets (/K28.5/,
/Dx.y/) to either /I1/ or /I2/ ordered sets. The /I1/ set consists of a negative-ending disparity /K28.5/ (denoted by /K28.5/-), followed by a neutral /D5.6/. The /I2/ set consists of a positive-ending disparity /K28.5/ (denoted by /K28.5/+) and a negative-ending disparity /D16.2/ (denoted by /D16.2/-). The transmit state machines do not convert any of the ordered sets to match /C1/ or /C2/, which are the configuration ordered sets. (/C1/ and /C2/ are defined by [/K28.5/, /D21.5/] and [/K28.5/, /D2.2/], respectively). Both the /I1/ and /I2/ ordered sets guarantee a negative-ending disparity after each ordered set.
XAUI Mode
The transmit state machine translates the XAUI XGMII code group to the XAUI PCS code group.
lists the code conversion.
Table 2–3. On-Chip Termination Support by I/O Banks
XGMII TXC
1
1
1
1
0
1
1
1
1
9C
FB
FD
FE
00 through FF
07
07
XGMII TXD
Refer to IEEE 802.3 reserved code groups
Other value
PCS Code-Group
Dxx.y
K28.0 or K28.3 or K28.5
K28.5
K28.4
K27.7
K29.7
K30.7
Refer to IEEE 802.3 reserved code groups
K30.7
Description
Normal data
Idle in ||I||
Idle in ||T||
Sequence
Start
Terminate
Error
Reserved code groups
Invalid XGMII character
The XAUI PCS idle code groups, /K28.0/ (/R/) and /K28.5/ (/K/), are automatically randomized based on a PRBS7 pattern with an ×7 + ×6 + 1 polynomial. The /K28.3/
(/A/) code group is automatically generated between 16 and 31 idle code groups. The idle randomization on the /A/, /K/, and /R/ code groups is automatically done by the transmit state machine.
Serializer (Parallel-to-Serial Converter)
The serializer block clocks in 8- or 10-bit encoded data from the 8B/10B encoder using the low-speed parallel clock and clocks out serial data using the high-speed serial clock from the central or local clock divider blocks. The serializer feeds the data LSB to
MSB to the transmitter output buffer.
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–8 Chapter 2: Arria GX Architecture
Transceivers
shows the serializer block diagram.
Figure 2–7. Serializer
10
From 8B/10B
Encoder
D6
D5
D4
D3
D9
D8
D7
D2
D1
D0
CMU
Central /
Local Clock
Divider
Low-speed parallel clock
High-speed serial clock
D5
D4
D3
D2
D9
D8
D7
D6
D1
D0
To Transmitter
Output Buffer
Transmitter Buffer
The Arria GX transceiver buffers support the 1.2- and 1.5-V PCML I/O standard at rates up to 3.125 Gbps. The common mode voltage (V
CM
) of the output driver may be set to 600 or 700 mV.
f
For more information about the Arria GX transceiver buffers, refer to the
Arria GX
Transceiver Architecture
chapter.
The output buffer, as shown in Figure 2–8
, is directly driven by the high-speed data serializer and consists of a programmable output driver, a programmable pre-emphasis circuit, and OCT circuitry.
Arria GX Device Handbook, Volume 1
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Chapter 2: Arria GX Architecture
Transceivers
Figure 2–8. Output Buffer
Serializer
Output Buffer
Programmable
Output
Driver
Programmable
Pre-Emphasis
Output
Pins
2–9
Programmable Output Driver
The programmable output driver can be set to drive out differentially from 400 to
1200 mV. The differential output voltage (V
OD
) can be statically set by using the
ALTGXB megafunction.
You can configure the output driver with 100- OCT or external OCT.
Differential signaling conventions are shown in Figure 2–9
. The differential amplitude represents the value of the voltage between the true and complement signals.
Peak-to-peak differential voltage is defined as 2 (V
HIGH
– V
LOW
) = 2 single-ended voltage swing. The common mode voltage is the average of V
HIGH
and V
LOW
.
Figure 2–9. Differential Signaling
Single-Ended Waveform
V high
True
OD
Complement
V low
Differential Waveform
+400
+V
OD
V
OD
(Differential)
= V high
−
V low
2 * V
OD
0-V Differential
-V
OD
−400
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Transceivers
Programmable Pre-Emphasis
The programmable pre-emphasis module controls the output driver to boost high frequency components and compensate for losses in the transmission medium, as
shown in Figure 2–10 . Pre-emphasis is set statically using the ALTGXB megafunction.
Figure 2–10. Pre-Emphasis Signaling
V
MAX
V
MIN
Pre-Emphasis % = (
V
MAX
V
MIN
− 1) × 100
Pre-emphasis percentage is defined as (V
MAX
/V
MIN
– 1) × 100, where V
M AX
is the differential emphasized voltage (peak-to-peak) and V
MIN
is the differential steady-state voltage (peak-to-peak).
PCI Express (PIPE) Receiver Detect
The Arria GX transmitter buffer has a built-in receiver detection circuit for use in PCI
Express (PIPE) mode. This circuit provides the ability to detect if there is a receiver downstream by sending out a pulse on the channel and monitoring the reflection.
This mode requires a tri-stated transmitter buffer (in electrical idle mode).
PCI Express (PIPE) Electric Idles (or Individual Transmitter Tri-State)
The Arria GX transmitter buffer supports PCI Express (PIPE) electrical idles. This feature is only active in PCI Express (PIPE) mode. The tx_forceelecidle port puts the transmitter buffer in electrical idle mode. This port is available in all PCI Express
(PIPE) power-down modes and has specific usage in each mode.
Receiver Path
This section describes the data path through the Arria GX receiver. The sub-blocks are described in order from the receiver buffer to the PLD-receiver parallel interface.
Receiver Buffer
The Arria GX receiver input buffer supports the 1.2-V and 1.5-V PCML I/O standards at rates up to 3.125 Gbps. The common mode voltage of the receiver input buffer is programmable between 0.85 V and 1.2 V. You must select the 0.85 V common mode voltage for AC- and DC-coupled PCML links and 1.2 V common mode voltage for
DC-coupled LVDS links.
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2–11
The receiver has 100- on-chip differential termination (R
D
OCT) for different protocols, as shown in
Figure 2–11 . You can disable the receiver’s internal termination
if external terminations and biasing are provided. The receiver and transmitter differential termination method can be set independently of each other.
Figure 2–11. Receiver Input Buffer
100-
Ω
Termination
Input
Pins
Programmable
Equalizer
Differential
Input
Buffer
If a design uses external termination, the receiver must be externally terminated and biased to 0.85 V or 1.2 V.
Figure 2–12 shows an example of an external termination and
biasing circuit.
Figure 2–12. External Termination and Biasing Circuit
Receiver External Termination and Biasing
V
DD
Arria GX Device
50-
W
Termination
Resistance
C1
R1
R1/R2 = 1K
V
DD
´ {R2/(R1 + R 2)} = 0.85/1.2 V
R2
RXIP
Receiver
RXIN
Receiver External Termination and Biasing
Transmission
Line
Programmable Equalizer
The Arria GX receivers provide a programmable receiver equalization feature to compensate for the effects of channel attenuation for high-speed signaling. PCB traces carrying these high-speed signals have low-pass filter characteristics. Impedance mismatch boundaries can also cause signal degradation. Equalization in the receiver diminishes the lossy attenuation effects of the PCB at high frequencies.
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Transceivers
The receiver equalization circuit is comprised of a programmable amplifier. Each stage is a peaking equalizer with a different center frequency and programmable gain.
This allows varying amounts of gain to be applied, depending on the overall frequency response of the channel loss. Channel loss is defined as the summation of all losses through the PCB traces, vias, connectors, and cables present in the physical link. The Quartus II software allows five equalization settings for Arria GX devices.
Receiver PLL and Clock Recovery Unit (CRU)
Each transceiver block has four receiver PLLs and CRU units, each of which is dedicated to a receiver channel. The receiver PLL is fed by an input reference clock.
The receiver PLL, in conjunction with the CRU, generates two clocks: a high-speed serial recovered clock that clocks the deserializer and a low-speed parallel recovered clock that clocks the receiver's digital logic.
Figure 2–13 shows a block diagram of the receiver PLL and CRU circuits.
Figure 2–13. Receiver PLL and Clock Recovery Unit
/M
Dedicated
REFCLK0
/2
Dedicated
REFCLK1
/2
Inter-Transceiver Lines
[2:0]
Global Clock (2) rx_cruclk
PFD up dn up dn rx_pll_locked
CP+ LF VCO /L rx_locktorefclk rx_locktodata rx_datain
Clock Recovery Unit (CRU) Control rx_freqlocked
High-speed serial recovered clk
Low-speed parallel recovered clk
:
(1) You only need to select the protocol and the available input reference clock frequency in the ALTGXB MegaWizard Plug-In Manager. Based on your selections, the ALTGXB MegaWizard Plug-In Manager automatically selects the necessary /M and /L dividers.
(2) The global clock line must be driven from an input pin only.
■
■
■
■
The reference clock input to the receiver PLL can be derived from:
■ One of the two available dedicated reference clock input pins (REFCLK0 or
REFCLK1
) of the associated transceiver block
■
■
PLD global clock network (must be driven directly from an input clock pin and cannot be driven by user logic or enhanced PLL)
Inter-transceiver block lines driven by reference clock input pins of other transceiver blocks
All the parameters listed are programmable in the Quartus II software. The receiver
PLL has the following features:
Operates from 600 Mbps to 3.125 Gbps.
Uses a reference clock between 50 MHz and 622.08 MHz.
Programmable bandwidth settings: low, medium, and high.
Programmable rx_locktorefclk (forces the receiver PLL to lock to reference clock) and rx_locktodata (forces the receiver PLL to lock to data).
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Transceivers
2–13
■
■
The voltage-controlled oscillator (V
CO
) operates at half rate.
Programmable frequency multiplication W of 1, 4, 5, 8, 10, 16, 20, and 25. Not all settings are supported for any particular frequency.
■ Two lock indication signals are provided. They are found in PFD mode
(lock-to-reference clock), and PD (lock-to-data).
The CRU controls whether the receiver PLL locks to the input reference clock
(lock-to-reference mode) or the incoming serial data (lock-to data mode). You can set the CRU to switch between lock-to-data and lock-to-reference modes automatically or manually. In automatic lock mode, the phase detector and dedicated parts per million
(PPM) detector within each receiver channel control the switch between lock-to-data and lock-to-reference modes based on some pre-set conditions. In manual lock mode, you can control the switch manually using the rx_locktorefclk and rx_locktodata signals. f
For more information, refer to the “Clock Recovery Unit” section in the
Arria GX
Transceiver Protocol Support and Additional Features
chapter.
Table 2–4 lists the behavior of the CRU block with respect to the rx_locktorefclk
and rx_locktodata signals.
Table 2–4. CRU Manual Lock Signals
rx_locktorefclk
1 x
0
rx_locktodata
0
1
0
CRU Mode
Lock-to-reference clock
Lock-to-data
Automatic
If the rx_locktorefclk and rx_locktodata ports are not used, the default setting is automatic lock mode.
Deserializer
The deserializer block clocks in serial input data from the receiver buffer using the high-speed serial recovered clock and deserializes into 8- or 10-bit parallel data using the low-speed parallel recovered clock. The serial data is assumed to be received with
LSB first, followed by MSB. It feeds the deserialized 8- or 10-bit data to the word aligner, as shown in
.
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Arria GX Device Handbook, Volume 1
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Transceivers
Received Data
D6
D5
D4
D3
D9
D8
D7
D2
D1
D0
Clock
Recovery
Unit
High-speed serial recovered clock
Low -speed parallel recovered clock
Note to
:
(1) This is a 10-bit deserializer. The deserializer can also convert 8 bits of data.
D6
D5
D4
D3
D9
D8
D7
D2
D1
D0
10
To Word
Aligner
Word Aligner
The deserializer block creates 8- or 10-bit parallel data. The deserializer ignores protocol symbol boundaries when converting this data. Therefore, the boundaries of the transferred words are arbitrary. The word aligner aligns the incoming data based on specific byte or word boundaries. The word alignment module is clocked by the local receiver recovered clock during normal operation. All the data and programmed patterns are defined as “big-endian” (most significant word followed by least significant word). Most-significant-bit-first protocols should reverse the bit order of word align patterns programmed.
This module detects word boundaries for 8B/10B-based protocols. This module is also used to align to specific programmable patterns in PRBS7/23 test mode.
Pattern Detection
The programmable pattern detection logic can be programmed to align word boundaries using a single 7- or 10-bit pattern. The pattern detector can either do an exact match, or match the exact pattern and the complement of a given pattern. Once the programmed pattern is found, the data stream is aligned to have the pattern on the LSB portion of the data output bus.
XAUI, GIGE, PCI Express (PIPE), and Serial RapidIO standards have embedded state machines for symbol boundary synchronization. These standards use K28.5 as their
10-bit programmed comma pattern. Each of these standards uses different algorithms before signaling symbol boundary acquisition to the FPGA.
Pattern detection logic searches from the LSB to the MSB. If multiple patterns are found within the search window, the pattern in the lower portion of the data stream
(corresponding to the pattern received earlier) is aligned and the rest of the matching patterns are ignored.
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2–15
Once a pattern is detected and the data bus is aligned, the word boundary is locked.
The two detection status signals (rx_syncstatus and rx_patterndetect) indicate that an alignment is complete.
Figure 2–15 is a block diagram of the word aligner.
Figure 2–15. Word Aligner datain bitslip
Word
Aligner enapatternalign dataout syncstatus patterndetect clock
Control and Status Signals
The rx_enapatternalign signal is the FPGA control signal that enables word alignment in non-automatic modes. The rx_enapatternalign signal is not used in automatic modes (PCI Express [PIPE], XAUI, GIGE, and Serial RapidIO).
In manual alignment mode, after the rx_enapatternalign signal is activated, the rx_syncstatus
signal goes high for one parallel clock cycle to indicate that the alignment pattern has been detected and the word boundary has been locked. If rx_enapatternalign
is deactivated, the rx_syncstatus signal acts as a re-synchronization signal to signify that the alignment pattern has been detected but not locked on a different word boundary.
When using the synchronization state machine, the rx_syncstatus signal indicates the link status. If the rx_syncstatus signal is high, link synchronization is achieved. If the rx_syncstatus signal is low, link synchronization has not yet been achieved, or there were enough code group errors to lose synchronization. f
For more information about manual alignment modes, refer to the
Arria GX Device
Handbook
.
The rx_patterndetect signal pulses high during a new alignment and whenever the alignment pattern occurs on the current word boundary.
Programmable Run Length Violation
The word aligner supports a programmable run length violation counter. Whenever the number of the continuous ‘0’ (or ‘1’) exceeds a user programmable value, the rx_rlv
signal goes high for a minimum pulse width of two recovered clock cycles.
The maximum run values supported are 128 UI for 8-bit serialization or 160 UI for
10-bit serialization.
Running Disparity Check
The running disparity error rx_disperr and running disparity value rx_runningdisp
are sent along with aligned data from the 8B/10B decoder to the
FPGA. You can ignore or act on the reported running disparity value and running disparity error signals.
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Transceivers
Bit-Slip Mode
The word aligner can operate in either pattern detection mode or in bit-slip mode.
The bit-slip mode provides the option to manually shift the word boundary through the FPGA. This feature is useful for:
■
■
Longer synchronization patterns than the pattern detector can accommodate
Scrambled data stream
■ Input stream consisting of over-sampled data
The word aligner outputs a word boundary as it is received from the analog receiver after reset. You can examine the word and search its boundary in the FPGA. To do so, assert the rx_bitslip signal. The rx_bitslip signal should be toggled and held constant for at least two FPGA clock cycles.
For every rising edge of the rx_bitslip signal, the current word boundary is slipped by one bit. Every time a bit is slipped, the bit received earliest is lost. If bit slipping shifts a complete round of bus width, the word boundary is back to the original boundary.
The rx_syncstatus signal is not available in bit-slipping mode.
Channel Aligner
The channel aligner is available only in XAUI mode and aligns the signals of all four channels within a transceiver. The channel aligner follows the IEEE 802.3ae, clause 48 specification for channel bonding.
The channel aligner is a 16-word FIFO buffer with a state machine controlling the channel bonding process. The state machine looks for an /A/ (/K28.3/) in each channel and aligns all the /A/ code groups in the transceiver. When four columns of
/A/ (denoted by //A//) are detected, the rx_channelaligned signal goes high, signifying that all the channels in the transceiver have been aligned. The reception of four consecutive misaligned /A/ code groups restarts the channel alignment sequence and sends the rx_channelaligned signal low.
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Chapter 2: Arria GX Architecture
Transceivers
2–17
Figure 2–16 shows misaligned channels before the channel aligner and the aligned
channels after the channel aligner.
Figure 2–16. Before and After the Channel Aligner
Lane 3
K K R A K R R K K R K R
Lane 2
K K R A K R R K K R K R
Lane 1
K K R A K R R K K R K R
Lane 0
K K R A K R R K K R K R
Lane 3
K K R A K R R K K R K R
K K R A K R R K K R K R
Lane 2
Lane 1
Lane 0
K K R A K R R K K R K R
K K R A K R R K K R K R
Rate Matcher
In asynchronous systems, the upstream transmitter and local receiver can be clocked with independent reference clock sources. Frequency differences in the order of a few hundred PPM can potentially corrupt the data at the receiver.
The rate matcher compensates for small clock frequency differences between the upstream transmitter and the local receiver clocks by inserting or removing skip characters from the inter packet gap (IPG) or idle streams. It inserts a skip character if the local receiver is running a faster clock than the upstream transmitter. It deletes a skip character if the local receiver is running a slower clock than the upstream transmitter. The Quartus II software automatically configures the appropriate skip character as specified in the IEEE 802.3 for GIGE mode and PCI-Express Base
Specification for PCI Express (PIPE) mode. The rate matcher is bypassed in Serial
RapidIO and must be implemented in the PLD logic array or external circuits depending on your system design.
Table 2–5 lists the maximum frequency difference that the rate matcher can tolerate in
XAUI, PCI Express (PIPE), GIGE, and Basic functional modes.
Table 2–5. Rate Matcher PPM Tolerance
Function Mode
XAUI
PCI Express (PIPE)
GIGE
Basic
PPM
± 100
± 300
± 100
± 300
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Transceivers
XAUI Mode
In XAUI mode, the rate matcher adheres to clause 48 of the IEEE 802.3ae specification for clock rate compensation. The rate matcher performs clock compensation on columns of /R/ (/K28.0/), denoted by //R//. An //R// is added or deleted automatically based on the number of words in the FIFO buffer.
PCI Express (PIPE) Mode Rate Matcher
In PCI Express (PIPE) mode, the rate matcher can compensate up to ± 300 PPM
(600 PPM total) frequency difference between the upstream transmitter and the receiver. The rate matcher logic looks for skip ordered sets (SOS), which contains a
/K28.5/ comma followed by three /K28.0/ skip characters. The rate matcher logic deletes or inserts /K28.0/ skip characters as necessary from/to the rate matcher FIFO.
The rate matcher in PCI Express (PIPE) mode has a FIFO buffer overflow and underflow protection. In the event of a FIFO buffer overflow, the rate matcher deletes any data after detecting the overflow condition to prevent FIFO pointer corruption until the rate matcher is not full. In an underflow condition, the rate matcher inserts
9'h1FE (/K30.7/) until the FIFO buffer is not empty. These measures ensure that the
FIFO buffer can gracefully exit the overflow and underflow condition without requiring a FIFO reset. The rate matcher FIFO overflow and underflow condition is indicated on the pipestatus port.
You can bypass the rate matcher in PCI Express (PIPE) mode if you have a synchronous system where the upstream transmitter and local receiver derive their reference clocks from the same source.
GIGE Mode Rate Matcher
In GIGE mode, the rate matcher can compensate up to ± 100 PPM (200 PPM total) frequency difference between the upstream transmitter and the receiver. The rate matcher logic inserts or deletes /I2/ idle ordered sets to/from the rate matcher FIFO during the inter-frame or inter-packet gap (IFG or IPG). /I2/ is selected as the rate matching ordered set because it maintains the running disparity, unlike /I1/ that alters the running disparity. Because the /I2/ ordered-set contains two 10-bit code groups (/K28.5/, /D16.2/), 20 bits are inserted or deleted at a time for rate matching.
1
The rate matcher logic has the capability to insert or delete /C1/ or /C2/ configuration ordered sets when ‘GIGE Enhanced’ mode is chosen as the sub-protocol in the MegaWizard Plug-In Manager.
If the frequency PPM difference between the upstream transmitter and the local receiver is high, or if the packet size is too large, the rate matcher FIFO buffer can face an overflow or underflow situation.
Basic Mode
In basic mode, you can program the skip and control pattern for rate matching. There is no restriction on the deletion of a skip character in a cluster. The rate matcher deletes the skip characters as long as they are available. For insertion, the rate matcher inserts skip characters such that the number of skip characters at the output of rate matcher does not exceed five.
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8B/10B Decoder
The 8B/10B decoder is used in all supported functional modes. The 8B/10B decoder takes in 10-bit data from the rate matcher and decodes it into 8-bit data + 1-bit control identifier, thereby restoring the original transmitted data at the receiver. The 8B/10B decoder indicates whether the received 10-bit character is a data or control code through the rx_ctrldetect port. If the received 10-bit code group is a control character (Kx.y), the rx_ctrldetect signal is driven high and if it is a data character (Dx.y), the rx_ctrldetect signal is driven low.
Figure 2–17 shows a 10-bit code group decoded to an 8-bit data and a 1-bit control
indicator.
Figure 2–17. 10-Bit to 8-Bit Conversion j
9 h
8 g
7 f
6 i
5 e
4 d
3 c
2 b
1 a
0
MSB Received Last
LSB Received First
8B/10B Conversion ctrl 7
H
6
G
5
F
4
E
3
D
2
C
1
B
0
A
Parallel Data
If the received 10-bit code is not a part of valid Dx.y or Kx.y code groups, the 8B/10B decoder block asserts an error flag on the rx_errdetect port. If the received 10-bit code is detected with incorrect running disparity, the 8B/10B decoder block asserts an error flag on the rx_disperr and rx_errdetect ports. The error flag signals
(rx_errdetect and rx_disperr) have the same data path delay from the 8B/10B decoder to the PLD-transceiver interface as the bad code group.
Receiver State Machine
The receiver state machine operates in Basic, GIGE, PCI Express (PIPE), and XAUI modes. In GIGE mode, the receiver state machine replaces invalid code groups with
K30.7. In XAUI mode, the receiver state machine translates the XAUI PCS code group to the XAUI XGMII code group.
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Byte Deserializer
Byte deserializer takes in one-byte wide data from the 8B/10B decoder and deserializes it into a two-byte wide data at half the speed. This allows clocking the
PLD-receiver interface at half the speed as compared to the receiver PCS logic. The byte deserializer is bypassed in GIGE mode.
The byte ordering at the receiver output might be different than what was transmitted. This is a non-deterministic swap, because it depends on PLL lock times and link delay. If required, you must implement byte ordering logic in the PLD to correct this situation.
f
For more information about byte serializer, refer to the
Arria GX Transceiver
Architecture
chapter.
Receiver Phase Compensation FIFO Buffer
A receiver phase compensation FIFO buffer is located at each receiver channel’s logic array interface. It compensates for the phase difference between the receiver PCS clock and the local PLD receiver clock. The receiver phase compensation FIFO is used in all supported functional modes. The receiver phase compensation FIFO buffer is eight words deep in PCI Express (PIPE) mode and four words deep in all other modes. f
For more information about architecture and clocking, refer to the
Arria GX Transceiver
Architecture
chapter.
Loopback Modes
■
■
■
■
Arria GX transceivers support the following loopback configurations for diagnostic purposes:
Serial loopback
Reverse serial loopback
Reverse serial loopback (pre-CDR)
PCI Express (PIPE) reverse parallel loopback (available only in [PIPE] mode)
Serial Loopback
Figure 2–18 shows the transceiver data path in serial loopback.
Figure 2–18. Transceiver Data Path in Serial Loopback
TX Phase
Compensation
FIFO
Byte
Serializer
8B/10B
Encoder
Transmitter PCS Transmitter PMA
Serializer
PLD
Logic
Array
RX Phase
Compensation
FIFO
Byte
De-
Serializer
8B/10B
Decoder
Rate
Match
FIFO
Receiver PCS
Word
Aligner
Serial Loopback
Receiver PMA
De-
Serializer
Clock
Recovery
Unit
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Transceivers
2–21
In GIGE and Serial RapidIO modes, you can dynamically put each transceiver channel individually in serial loopback by controlling the rx_seriallpbken port. A high on the rx_seriallpbken port puts the transceiver into serial loopback and a low takes the transceiver out of serial loopback.
As seen in Figure 2–18 , the serial data output from the transmitter serializer is looped
back to the receiver CRU in serial loopback. The transmitter data path from the PLD interface to the serializer in serial loopback is the same as in non-loopback mode. The receiver data path from the clock recovery unit to the PLD interface in serial loopback is the same as in non-loopback mode. Because the entire transceiver data path is available in serial loopback, this option is often used to diagnose the data path as a probable cause of link errors.
1
When serial loopback is enabled, the transmitter output buffer is still active and drives the serial data out on the tx_dataout port.
Reverse Serial Loopback
Reverse serial loopback mode uses the analog portion of the transceiver. An external source (pattern generator or transceiver) generates the source data. The high-speed serial source data arrives at the high-speed differential receiver input buffer, passes through the CRU unit and the retimed serial data is looped back, and is transmitted though the high-speed differential transmitter output buffer.
Figure 2–19 shows the data path in reverse serial loopback mode.
Figure 2–19. Arria GX Block in Reverse Serial Loopback Mode
Transmitter Digital Logic
BIST
Incremental
Generator
BIST
PRBS
Generator
Analog Receiver and
Transmitter Logic
TX Phase
Compensation
FIFO
Byte
Serializer
20
8B/10B
Encoder
Serializer
FPGA
Logic
Array
BIST
Incremental
Verify
RX Phase
Compensation
FIFO
Byte
Deserializer
8B/10B
Decoder
Rate
Match
FIFO
Reverse
Serial
Loopback
Deskew
FIFO
BIST
PRBS
Verify
Word
Aligner
Deserializer
Clock
Recovery
Unit
Receiver Digital Logic
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Transceivers
Reverse Serial Pre-CDR Loopback
Reverse serial pre-CDR loopback mode uses the analog portion of the transceiver. An external source (pattern generator or transceiver) generates the source data. The high-speed serial source data arrives at the high-speed differential receiver input buffer, loops back before the CRU unit, and is transmitted though the high-speed differential transmitter output buffer. It is for test or verification use only to verify the signal being received after the gain and equalization improvements of the input buffer. The signal at the output is not exactly what is received because the signal goes through the output buffer and the V
O D
is changed to the V
OD
setting level.
Pre-emphasis settings have no effect.
Figure 2–20 shows the Arria GX block in reverse serial pre-CDR loopback mode.
Figure 2–20. Arria GX Block in Reverse Serial Pre-CDR Loopback Mode
Transmitter Digital Logic
BIST
Incremental
Generator
BIST
PRBS
Generator
Analog Receiver and
Transmitter Logic
TX Phase
Compensation
FIFO
Byte
Serializer
20
8B/10B
Encoder
Serializer
FPGA
Logic
Array
BIST
Incremental
Verify
RX Phase
Compensation
FIFO
Byte
Deserializer
8B/10B
Decoder
Rate
Match
FIFO
Reverse
Serial
Pre-CDR
Loopback
Deskew
FIFO
BIST
PRBS
Verify
Word
Aligner
Deserializer
Clock
Recovery
Unit
Receiver Digital Logic
PCI Express (PIPE) Reverse Parallel Loopback
Figure 2–21 shows the data path for PCI Express (PIPE) reverse parallel loopback. The
reverse parallel loopback configuration is compliant with the PCI Express (PIPE) specification and is available only on PCI Express (PIPE) mode.
Figure 2–21. PCI Express (PIPE) Reverse Parallel Loopback
TX Phase
Compensation
FIFO
Byte
Serializer
8B/10B
Encoder
Transmitter PCS Transmitter PMA
Serializer
PIPE
Interface
RX Phase
Compensation
FIFO
Byte
De-
Serializer
8B/10B
Decoder
PIPE Reverse
Parallel Loopback
Receiver PCS
Rate
Match
FIFO
Word
Aligner
Receiver PMA
De-
Serializer
Clock
Recovery
Unit
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Transceivers
2–23
You can dynamically put the PCI Express (PIPE) mode transceiver in reverse parallel loopback by controlling the tx_detectrxloopback port instantiated in the
MegaWizard Plug-In Manager. A high on the tx_detectrxloopback port in P0 power state puts the transceiver in reverse parallel loopback. A high on the tx_detectrxloopback
port in any other power state does not put the transceiver in reverse parallel loopback.
As seen in
Figure 2–21 , the serial data received on the rx_datain port in reverse
parallel loopback goes through the CRU, deserializer, word aligner, and the rate matcher blocks. The parallel data at the output of the receiver rate matcher block is looped back to the input of the transmitter serializer block. The serializer converts the parallel data to serial data and feeds it to the transmitter output buffer that drives the data out on the tx_dataout port. The data at the output of the rate matcher also goes through the 8B/10B decoder, byte deserializer, and receiver phase compensation
FIFO before being fed to the PLD on the rx_dataout port.
Reset and Powerdown
Arria GX transceivers offer a power saving advantage with their ability to shut off functions that are not needed.
■
■
■
The following three reset signals are available per transceiver channel and can be used to individually reset the digital and analog portions within each channel: tx_digitalreset rx_analogreset rx_digitalreset
■
■
The following two powerdown signals are available per transceiver block and can be used to shut down an entire transceiver block that is not being used: gxb_powerdown gxb_enable
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Transceivers
Table 2–6 lists the reset signals available in Arria GX devices and the transceiver
circuitry affected by each signal.
Table 2–6. Reset Signal Map to Arria GX Blocks
Reset Signal
rx_digitalreset
— — — — — — — — v
— v v v
— v v
— rx_analogreset
— — — — — — — v
— — — — — v
— — v tx_digitalreset v v
— — — v v
— — — — — — — — — — gxb_powerdown gxb_enable v v v v v v v v v
— v v v v v v v v v v v v v v v v
— v v v v v v v
Calibration Block
Arria GX devices use the calibration block to calibrate OCT for the PLLs, and their associated output buffers, and the terminating resistors on the transceivers. The calibration block counters the effects of process, voltage, and temperature (PVT). The calibration block references a derived voltage across an external reference resistor to calibrate the OCT resistors on Arria GX devices. You can power down the calibration block. However, powering down the calibration block during operations can yield transmit and receive data errors.
Transceiver Clocking
This section describes the clock distribution in an Arria GX transceiver channel and the PLD clock resource utilization by the transceiver blocks.
Transceiver Channel Clock Distribution
Each transceiver block has one transmitter PLL and four receiver PLLs.
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Chapter 2: Arria GX Architecture
Transceivers
2–25
The transmitter PLL multiplies the input reference clock to generate a high-speed serial clock at a frequency that is half the data rate of the configured functional mode.
This high-speed serial clock (or its divide-by-two version if the functional mode uses byte serializer) is fed to the CMU clock divider block. Depending on the configured functional mode, the CMU clock divider block divides the high-speed serial clock to generate the low-speed parallel clock that clocks the transceiver PCS logic in the associated channel. The low-speed parallel clock is also forwarded to the PLD logic array on the tx_clkout or coreclkout ports.
The receiver PLL in each channel is also fed by an input reference clock. The receiver
PLL along with the clock recovery unit generates a high-speed serial recovered clock and a low-speed parallel recovered clock. The low-speed parallel recovered clock feeds the receiver PCS logic until the rate matcher. The CMU low-speed parallel clock clocks the rest of the logic from the rate matcher until the receiver phase compensation FIFO. In modes that do not use a rate matcher, the receiver PCS logic is clocked by the recovered clock until the receiver phase compensation FIFO.
The input reference clock to the transmitter and receiver PLLs can be derived from:
■
■
One of two available dedicated reference clock input pins (REFCLK0 or REFCLK1) of the associated transceiver block
PLD clock network (must be driven directly from an input clock pin and cannot be driven by user logic or enhanced PLL)
■ Inter-transceiver block lines driven by reference clock input pins of other transceiver blocks
Figure 2–22 shows the input reference clock sources for the transmitter and receiver
PLL.
Figure 2–22. Input Reference Clock Sources
Inter-Transceiver Lines [2]
Transceiver Block 2
Inter-Transceiver Lines [1]
Transceiver Block 1
Transceiver Block 0
Inter-Transceiver Lines [0]
Dedicated
REFCLK0
/2
Dedicated
REFCLK1
/2
Inter-Transceiver Lines [2:0]
Global Clock (1)
Transmitter
PLL
Four
Receiver
PLLs
Global Clock (1)
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Transceivers f
For more information about transceiver clocking in all supported functional modes, refer to the
Arria GX Transceiver Architecture
chapter.
PLD Clock Utilization by Transceiver Blocks
Arria GX devices have up to 16 global clock (GCLK) lines and 16 regional clock
(RCLK) lines that are used to route the transceiver clocks. The following transceiver clocks use the available global and regional clock resources:
■
■
■
■
■
■ pll_inclk rx_cruclk
(if driven from an FPGA input pin)
(if driven from an FPGA input pin) tx_clkout/coreclkout
(CMU low-speed parallel clock forwarded to the PLD)
Recovered clock from each channel (rx_clkout) in non-rate matcher mode
Calibration clock (cal_blk_clk)
Fixed clock (fixedclk used for receiver detect circuitry in PCI Express [PIPE] mode only)
show the available GCLK and RCLK resources in Arria
GX devices.
Figure 2–23. Global Clock Resources in Arria GX Devices
CLK[15..12]
11 5
7
GCLK[15..12]
Arria GX
Transceiver
Block
GCLK[11..8]
CLK[3..0]
1
2
GCLK[3..0]
GCLK[4..7]
Arria GX
Transceiver
Block
8
12 6
CLK[7..4]
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Chapter 2: Arria GX Architecture
Transceivers
2–27
Figure 2–24. Regional Clock Resources in Arria GX Devices
7
RCLK
[31..28]
CLK[15..12]
11 5
RCLK
[27..24]
CLK[3..0]
1
2
RCLK
[3..0]
RCLK
[7..4]
RCLK
[23..20]
Arria GX
Transceiver
Block
RCLK
[19..16]
Arria GX
Transceiver
Block
8
RCLK
[11..8]
12 6
CLK[7..4]
RCLK
[15..12]
For the RCLK or GCLK network to route into the transceiver, a local route input output (LRIO) channel is required. Each LRIO clock region has up to eight clock paths and each transceiver block has a maximum of eight clock paths for connecting with
LRIO clocks. These resources are limited and determine the number of clocks that can be used between the PLD and transceiver blocks.
Table 2–7 and Table 2–8 list the
number of LRIO resources available for Arria GX devices with different numbers of transceiver blocks.
Table 2–7. Available Clocking Connections for Transceivers in EP1AGX35D, EP1AGX50D, and EP1AGX60D
Clock Resource Transceiver
Source
Region0 8 LRIO clock
Region1 8 LRIO clock
Global Clock
v v
Regional Clock
RCLK 20-27
RCLK 12-19
Bank13
8 Clock I/O
v
—
Bank14
8 Clock I/O
— v
Table 2–8. Available Clocking Connections for Transceivers in EP1AGX60E and EP1AGX90E
Clock Resource Transceiver
Source
Region0 8 LRIO clock
Region1 8 LRIO clock
Region2 8 LRIO clock
Region3 8 LRIO clock
Global Clock
v v v v
Regional Clock
RCLK 20-27
RCLK 20-27
RCLK 12-19
RCLK 12-19
Bank13
8 Clock I/O
v v
—
—
Bank14
8 Clock I/O
— v v
—
Bank15
8 Clock I/O
—
— v v
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Logic Array Blocks
Logic Array Blocks
Each logic array block (LAB) consists of eight adaptive logic modules (ALMs), carry chains, shared arithmetic chains, LAB control signals, local interconnects, and register chain connection lines. The local interconnect transfers signals between ALMs in the same LAB. Register chain connections transfer the output of an ALM register to the adjacent ALM register in a LAB. The Quartus II Compiler places associated logic in a
LAB or adjacent LABs, allowing the use of local, shared arithmetic chain, and register chain connections for performance and area efficiency.
lists Arria GX device resources.
shows the Arria GX LAB structure.
Table 2–9. Arria GX Device Resources
Device
EP1AGX20
EP1AGX35
EP1AGX50
EP1AGX60
EP1AGX90
M512 RAM
Columns/Blocks
166
197
313
326
478
M4K RAM
Columns/Blocks
118
140
242
252
400
M-RAM Blocks
1
1
2
2
4
DSP Block
Columns/Blocks
10
14
26
32
44
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Chapter 2: Arria GX Architecture
Logic Array Blocks
Figure 2–25. Arria GX LAB Structure
2–29
Row Interconnects of
Variable Speed & Length
ALMs
Direct link interconnect from adjacent block
Direct link interconnect from adjacent block
Direct link interconnect to adjacent block
Direct link interconnect to adjacent block
Local Interconnect LAB
Local Interconnect is Driven from Either Side by Columns & LABs,
& from Above by Rows
Column Interconnects of
Variable Speed & Length
LAB Interconnects
The LAB local interconnect can drive all eight ALMs in the same LAB. It is driven by column and row interconnects and ALM outputs in the same LAB. Neighboring
LABs, M512 RAM blocks, M4K RAM blocks, M-RAM blocks, or digital signal processing (DSP) blocks from the left and right can also drive the local interconnect of a LAB through the direct link connection. The direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility. Each ALM can drive 24 ALMs through fast local and direct link interconnects.
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Logic Array Blocks
Figure 2–26 shows the direct link connection.
Figure 2–26. Direct Link Connection
Direct link interconnect from left LAB, TriMatrix
TM
memory block, DSP block, or input/output element (IOE)
Direct link interconnect from right LAB, TriMatrix memory block, DSP block, or IOE output
ALMs
Direct link interconnect to left
Local
Interconnect
Direct link interconnect to right
LAB
LAB Control Signals
Each LAB contains dedicated logic for driving control signals to its ALMs. The control signals include three clocks, three clock enables, two asynchronous clears, synchronous clear, asynchronous preset or load, and synchronous load control signals, providing a maximum of 11 control signals at a time. Although synchronous load and clear signals are generally used when implementing counters, they can also be used with other functions.
Each LAB can use three clocks and three clock enable signals. However, there can only be up to two unique clocks per LAB, as shown in the LAB control signal generation
circuit in Figure 2–27 . Each LAB’s clock and clock enable signals are linked. For
example, any ALM in a particular LAB using the labclk1 signal also uses labclkena1
. If the LAB uses both the rising and falling edges of a clock, it also uses two LAB-wide clock signals. De-asserting the clock enable signal turns off the corresponding LAB-wide clock. Each LAB can use two asynchronous clear signals and an asynchronous load/preset signal. The asynchronous load acts as a preset when the asynchronous load data input is tied high. When the asynchronous load/preset signal is used, the labclkena0 signal is no longer available.
The LAB row clocks [5..0] and LAB local interconnect generate the LAB-wide control signals. The MultiTrack interconnects have inherently low skew. This low skew allows the MultiTrack interconnects to distribute clock and control signals in addition to data.
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Chapter 2: Arria GX Architecture
Adaptive Logic Modules
Figure 2–27 shows the LAB control signal generation circuit.
Figure 2–27. LAB-Wide Control Signals
There are two unique clock signals per LAB.
6
Dedicated Row LAB Clocks
6
6
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
2–31
labclk0 labclkena0 or asyncload or labpreset labclk1 labclkena1 labclk2 labclkena2 syncload labclr0 labclr1 synclr
Adaptive Logic Modules
The basic building block of logic in the Arria GX architecture is the ALM. The ALM provides advanced features with efficient logic utilization. Each ALM contains a variety of look-up table (LUT)-based resources that can be divided between two adaptive LUTs (ALUTs). With up to eight inputs to the two ALUTs, one ALM can implement various combinations of two functions. This adaptability allows the ALM to be completely backward-compatible with four-input LUT architectures. One ALM can also implement any function of up to six inputs and certain seven-input functions.
In addition to the adaptive LUT-based resources, each ALM contains two programmable registers, two dedicated full adders, a carry chain, a shared arithmetic chain, and a register chain. Through these dedicated resources, the ALM can efficiently implement various arithmetic functions and shift registers. Each ALM drives all types of interconnects: local, row, column, carry chain, shared arithmetic chain, register chain, and direct link interconnects.
shows a high-level block diagram of the Arria GX ALM while
Figure 2–29 shows a detailed view of all
the connections in the ALM.
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Adaptive Logic Modules
Figure 2–28. High-Level Block Diagram of the Arria GX ALM carry_in shared_arith_in reg_chain_in dataf0 datae0 dataa datab datac datad datae1 dataf1
Combinational
Logic adder0 adder1
D reg0
Q
D reg1
Q carry_out shared_arith_out reg_chain_out
To general or local routing
To general or local routing
To general or local routing
To general or local routing
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Chapter 2: Arria GX Architecture
Adaptive Logic Modules
Figure 2–29. Arria GX ALM Details
2–33
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Adaptive Logic Modules
One ALM contains two programmable registers. Each register has data, clock, clock enable, synchronous and asynchronous clear, asynchronous load data, and synchronous and asynchronous load/preset inputs.
Global signals, general-purpose I/O pins, or any internal logic can drive the register's clock and clear control signals. Either general-purpose I/O pins or internal logic can drive the clock enable, preset, asynchronous load, and asynchronous load data. The asynchronous load data input comes from the datae or dataf input of the ALM, which are the same inputs that can be used for register packing. For combinational functions, the register is bypassed and the output of the LUT drives directly to the outputs of the ALM.
Each ALM has two sets of outputs that drive the local, row, and column routing resources. The LUT, adder, or register output can drive these output drivers independently (refer to
Figure 2–29 ). For each set of output drivers, two ALM outputs
can drive column, row, or direct link routing connections. One of these ALM outputs can also drive local interconnect resources. This allows the LUT or adder to drive one output while the register drives another output. This feature, called register packing, improves device utilization because the device can use the register and combinational logic for unrelated functions. Another special packing mode allows the register output to feed back into the LUT of the same ALM so that the register is packed with its own fan-out LUT. This feature provides another mechanism for improved fitting.
The ALM can also drive out registered and unregistered versions of the LUT or adder output.
ALM Operating Modes
The Arria GX ALM can operate in one of the following modes:
■
■
■
■
Normal mode
Extended LUT mode
Arithmetic mode
Shared arithmetic mode
Each mode uses ALM resources differently. Each mode has 11 available inputs to the
ALM (refer to Figure 2–28 )the eight data inputs from the LAB local interconnect;
carry-in from the previous ALM or LAB; the shared arithmetic chain connection from the previous ALM or LAB; and the register chain connectionare directed to different destinations to implement the desired logic function. LAB-wide signals provide clock, asynchronous clear, asynchronous preset/load, synchronous clear, synchronous load, and clock enable control for the register. These LAB-wide signals are available in all
ALM modes. For more information about LAB-wide control signals, refer to “LAB
Control Signals” on page 2–30 .
The Quartus II software and supported third-party synthesis tools, in conjunction with parameterized functions such as library of parameterized modules (LPM) functions, automatically choose the appropriate mode for common functions such as counters, adders, subtractors, and arithmetic functions. If required, you can also create special-purpose functions that specify which ALM operating mode to use for optimal performance.
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Adaptive Logic Modules
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Normal Mode
Normal mode is suitable for general logic applications and combinational functions.
In this mode, up to eight data inputs from the LAB local interconnect are inputs to the combinational logic. Normal mode allows two functions to be implemented in one
Arria GX ALM, or an ALM to implement a single function of up to six inputs. The
ALM can support certain combinations of completely independent functions and various combinations of functions which have common inputs.
shows the supported LUT combinations in normal mode.
Figure 2–30. ALM in Normal Mode
dataf0 datae0 datac dataa datab datad datae1 dataf1
4-Input
LUT
4-Input
LUT combout0 dataf0 datae0 datac dataa datab combout1 datad datae1 dataf1
5-Input
LUT
5-Input
LUT combout0 combout1 dataf0 datae0 datac dataa datab datad datae1 dataf1
5-Input
LUT
3-Input
LUT combout0 combout1 dataf0 datae0 dataa datab datac datad
6-Input
LUT combout0
5-Input
LUT combout0 dataf0 datae0 dataa datab datac datad
6-Input
LUT combout0 dataf0 datae0 datac dataa datab
4-Input
LUT combout1 datae1 dataf1
6-Input
LUT combout1 datad datae1 dataf1
Note to
:
(1) Combinations of functions with less inputs than those shown are also supported. For example, combinations of functions with the following number of inputs are supported: 4 and 3, 3 and 3, 3 and 2, 5 and 2, and so on.
Normal mode provides complete backward compatibility with four-input LUT architectures. Two independent functions of four inputs or less can be implemented in one Arria GX ALM. In addition, a five-input function and an independent three-input function can be implemented without sharing inputs.
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Adaptive Logic Modules
To pack two five-input functions into one ALM, the functions must have at least two common inputs. The common inputs are dataa and datab. The combination of a four-input function with a five-input function requires one common input
(either dataa or datab).
To implement two six-input functions in one ALM, four inputs must be shared and the combinational function must be the same. For example, a 4 × 2 crossbar switch
(two 4-to-1 multiplexers with common inputs and unique select lines) can be implemented in one ALM, as shown in
. The shared inputs are dataa, datab
, datac, and datad, while the unique select lines are datae0 and dataf0 for function0
, and datae1 and dataf1 for function1. This crossbar switch consumes four LUTs in a four-input LUT-based architecture.
Figure 2–31. 4 × 2 Crossbar Switch Example
4
´ 2 Crossbar Switch sel0[1..0] inputa inputb inputc inputd out0 out1 sel1[1..0] dataf0 datae0 dataa datab datac datad
Implementation in 1 ALM
Six-Input
LUT
(Function0) combout0 datae1 dataf1
Six-Input
LUT
(Function1) combout1
In a sparsely used device, functions that can be placed into one ALM can be implemented in separate ALMs. The Quartus II Compiler spreads a design out to achieve the best possible performance. As a device begins to fill up, the Quartus II software automatically uses the full potential of the Arria GX ALM. The Quartus II
Compiler automatically searches for functions of common inputs or completely independent functions to be placed into one ALM and to make efficient use of the device resources. In addition, you can manually control resource usage by setting location assignments. Any six-input function can be implemented utilizing inputs dataa
, datab, datac, datad, and either datae0 and dataf0 or datae1 and dataf1
. If datae0 and dataf0 are used, the output is driven to register0, and/or register0 is bypassed and the data drives out to the interconnect using the top set of output drivers (refer to
Figure 2–32 ). If datae1 and dataf1 are used, the
output drives to register1 and/or bypasses register1 and drives to the interconnect using the bottom set of output drivers. The Quartus II Compiler automatically selects the inputs to the LUT. Asynchronous load data for the register comes from the datae or dataf input of the ALM. ALMs in normal mode support register packing.
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Adaptive Logic Modules
2–37
Figure 2–32. Six-Input Function in Normal Mode
dataf0 datae0 dataa datab datac datad
6-Input
LUT datae1 dataf1
(2)
These inputs are available for register packing.
D reg0
Q
D reg1
Q
To general or local routing
To general or local routing
To general or local routing
:
(1) If datae1 and dataf1 are used as inputs to the six-input function, datae0 and dataf0 are available for register packing.
(2) The dataf1 input is available for register packing only if the six-input function is un-registered.
Extended LUT Mode
Extended LUT mode is used to implement a specific set of seven-input functions. The set must be a 2-to-1 multiplexer fed by two arbitrary five-input functions sharing four inputs.
Figure 2–33 shows the template of supported seven-input functions utilizing
extended LUT mode. In this mode, if the seven-input function is unregistered, the unused eighth input is available for register packing. Functions that fit into the
occur naturally in designs. These functions often appear in designs as “if-else” statements in Verilog HDL or VHDL code.
Figure 2–33. Template for Supported Seven-Input Functions in Extended LUT Mode datae0 datac dataa datab datad dataf0
5-Input
LUT combout0
To general or local routing
To general or local routing
5-Input
LUT
D reg0
Q datae1 dataf1
(1)
This input is available for register packing.
Note to
:
(1) If the seven-input function is unregistered, the unused eighth input is available for register packing. The second register, reg1, is not available.
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Adaptive Logic Modules
Arithmetic Mode
Arithmetic mode is ideal for implementing adders, counters, accumulators, wide parity functions, and comparators. An ALM in arithmetic mode uses two sets of 2 four-input LUTs along with two dedicated full adders. The dedicated adders allow the LUTs to be available to perform pre-adder logic; therefore, each adder can add the output of two four-input functions. The four LUTs share the dataa and datab inputs. As shown in
, the carry-in signal feeds to adder0, and the carry-out from adder0 feeds to carry-in of adder1. The carry-out from adder1 drives to adder0 of the next ALM in the LAB. ALMs in arithmetic mode can drive out registered and/or unregistered versions of the adder outputs.
Figure 2–34. ALM in Arithmetic Mode carry_in datae0
adder0
4-Input
LUT
To general or local routing
To general or local routing dataf0 datac datab dataa
4-Input
LUT
D reg0
Q
adder1
datad datae1
4-Input
LUT
4-Input
LUT
D reg1
Q
To general or local routing
To general or local routing dataf1 carry_out
While operating in arithmetic mode, the ALM can support simultaneous use of the adder’s carry output along with combinational logic outputs. In this operation, adder output is ignored. This usage of the adder with the combinational logic output provides resource savings of up to 50% for functions that can use this ability. An example of such functionality is a conditional operation, such as the one shown in
Figure 2–35 . The equation for this example is:
Equation 2–1.
R = (X < Y) ? Y : X
To implement this function, the adder is used to subtract ‘Y’ from ‘X.’ If ‘X’ is less than
‘Y,’ the carry_out signal is ‘1.’ The carry_out signal is fed to an adder where it drives out to the LAB local interconnect. It then feeds to the LAB-wide syncload signal. When asserted, syncload selects the syncdata input. In this case, the data
‘Y’ drives the syncdata inputs to the registers. If ‘X’ is greater than or equal to ‘Y,’ the syncload
signal is deasserted and ‘X’ drives the data port of the registers.
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Chapter 2: Arria GX Architecture
Adaptive Logic Modules
Figure 2–35. Conditional Operation Example
Adder output is not used.
ALM 1
X[0]
Y[0]
Comb &
Adder
Logic
X[0]
syncdata
X[1]
Y[1]
Comb &
Adder
Logic
X[1] syncload
Carry Chain
syncload
ALM 2
D reg0
Q
R[0]
D reg1
Q
R[1]
X[2]
Y[2]
Comb &
Adder
Logic
X[2] syncload
D reg0
Q
R[2]
Comb &
Adder
Logic carry_out
To general or local routing
To general or local routing
To general or local routing
To local routing & then to LAB-wide syncload
2–39
Arithmetic mode also offers clock enable, counter enable, synchronous up/down control, add/subtract control, synchronous clear, and synchronous load. The LAB local interconnect data inputs generate the clock enable, counter enable, synchronous up/down and add/subtract control signals. These control signals can be used for the inputs that are shared between the four LUTs in the ALM. The synchronous clear and synchronous load options are LAB-wide signals that affect all registers in the LAB.
The Quartus II software automatically places any registers that are not used by the counter into other LABs.
Carry Chain
Carry chain provides a fast carry function between the dedicated adders in arithmetic or shared arithmetic mode. Carry chains can begin in either the first ALM or the fifth
ALM in a LAB. The final carry-out signal is routed to an ALM, where it is fed to local, row, or column interconnects.
The Quartus II Compiler automatically creates carry chain logic during compilation, or you can create it manually during design entry. Parameterized functions such as
LPM functions automatically take advantage of carry chains for the appropriate functions. The Quartus II Compiler creates carry chains longer than 16 (8 ALMs in arithmetic or shared arithmetic mode) by linking LABs together automatically. For enhanced fitting, a long carry chain runs vertically allowing fast horizontal connections to TriMatrix memory and DSP blocks. A carry chain can continue as far as a full column. To avoid routing congestion in one small area of the device when a high fan-in arithmetic function is implemented, the LAB can support carry chains that only use either the top half or bottom half of the LAB before connecting to the next LAB.
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Adaptive Logic Modules
The other half of the ALMs in the LAB is available for implementing narrower fan-in functions in normal mode. Carry chains that use the top four ALMs in the first LAB carries into the top half of the ALMs in the next LAB within the column. Carry chains that use the bottom four ALMs in the first LAB carries into the bottom half of the
ALMs in the next LAB within the column. Every other column of the LABs are top-half bypassable, while the other LAB columns are bottom-half bypassable. For
more information about carry chain interconnect, refer to “MultiTrack Interconnect” on page 2–44
.
Shared Arithmetic Mode
In shared arithmetic mode, the ALM can implement a three-input add. In this mode, the ALM is configured with four 4-input LUTs. Each LUT either computes the sum of three inputs or the carry of three inputs. The output of the carry computation is fed to the next adder (either to adder1 in the same ALM or to adder0 of the next ALM in the LAB) using a dedicated connection called the shared arithmetic chain. This shared arithmetic chain can significantly improve the performance of an adder tree by reducing the number of summation stages required to implement an adder tree.
Figure 2–36 shows the ALM in shared arithmetic mode.
Figure 2–36. ALM in Shared Arithmetic Mode shared_arith_in carry_in
4-Input
LUT datae0 datac datab dataa
4-Input
LUT
D reg0
Q datad datae1
4-Input
LUT
4-Input
LUT
D reg1
Q shared_arith_out carry_out
Note to
:
(1) Inputs dataf0 and dataf1 are available for register packing in shared arithmetic mode.
To general or local routing
To general or local routing
To general or local routing
To general or local routing
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Adaptive Logic Modules
2–41
Adder trees are used in many different applications. For example, the summation of partial products in a logic-based multiplier can be implemented in a tree structure.
Another example is a correlator function that can use a large adder tree to sum filtered data samples in a given time frame to recover or to de-spread data which was transmitted utilizing spread spectrum technology. An example of a three-bit add operation utilizing the shared arithmetic mode is shown in
sum (S[2..0]) and the partial carry (C[2..0]) is obtained using LUTs, while the result (R[2..0]) is computed using dedicated adders.
Figure 2–37. Example of a 3-Bit Add Utilizing Shared Arithmetic Mode
3-Bit Add Example
1st stage add is implemented in LUTs.
2nd stage add is implemented in adders.
+
X2 X1 X0
Y2 Y1 Y0
Z2 Z1 Z0
+
S2 S1 S0
C2 C1 C0
R3 R2 R1 R0
X0
Y0
Z0 shared_arith_in = '0' carry_in = '0'
ALM Implementation
ALM 1
3-Input
LUT
S0
R0
3-Input
LUT
C0
Binary Add
+
1 1 0
1 0 1
0 1 0
+
0 0 1
1 1 0
1 1 0 1
Decimal
Equivalents
+
6
5
2
+
1
2 x 6
13
X1
Y1
Z1
ALM 2
3-Input
LUT
S1
3-Input
LUT
C1
R1
3-Input
LUT
S2
R2
X2
Y2
Z2
3-Input
LUT
C2
3-Input
LUT
'0'
R3
3-Input
LUT
Shared Arithmetic Chain
In addition to dedicated carry chain routing, the shared arithmetic chain available in shared arithmetic mode allows the ALM to implement a three-input add, which significantly reduces the resources necessary to implement large adder trees or correlator functions. Shared arithmetic chains can begin in either the first or fifth ALM in a LAB. The Quartus II Compiler automatically links LABs to create shared arithmetic chains longer than 16 (eight ALMs in arithmetic or shared arithmetic mode). For enhanced fitting, a long shared arithmetic chain runs vertically allowing fast horizontal connections to TriMatrix memory and DSP blocks. A shared arithmetic chain can continue as far as a full column. Similar to carry chains, shared arithmetic
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–42 Chapter 2: Arria GX Architecture
Adaptive Logic Modules chains are also top- or bottom-half bypassable. This capability allows the shared arithmetic chain to cascade through half of the ALMs in a LAB while leaving the other half available for narrower fan-in functionality. Every other LAB column is top-half bypassable, while the other LAB columns are bottom-half bypassable. For more information about shared arithmetic chain interconnect, refer to
.
Register Chain
In addition to the general routing outputs, the ALMs in a LAB have register chain outputs. Register chain routing allows registers in the same LAB to be cascaded together. The register chain interconnect allows a LAB to use LUTs for a single combinational function and the registers to be used for an unrelated shift register implementation. These resources speed up connections between ALMs while saving local interconnect resources (refer to
Figure 2–38 ). The Quartus II Compiler
automatically takes advantage of these resources to improve utilization and performance. For more information about register chain interconnect, refer to
“MultiTrack Interconnect” on page 2–44 .
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
Adaptive Logic Modules
2–43
Figure 2–38. Register Chain within a LAB
From Previous ALM
Within The LAB
reg_chain_in adder0
To general or local routing
To general or local routing
D reg0
Q
Combinational
Logic adder1
D reg1
Q
To general or local routing adder0
To general or local routing
To general or local routing
To general or local routing
D reg0
Q
Combinational
Logic adder1
D reg1
Q
To general or local routing
To general or local routing reg_chain_out
To Next ALM within the LAB
Note to
:
(1) The combinational or adder logic can be used to implement an unrelated, unregistered function.
Clear and Preset Logic Control
LAB-wide signals control the logic for the register ’s clear and load/preset signals. The
ALM directly supports an asynchronous clear and preset function. The register preset is achieved through the asynchronous load of a logic high. The direct asynchronous preset does not require a NOT gate push-back technique. Arria GX devices support simultaneous asynchronous load/preset and clear signals. An asynchronous clear signal takes precedence if both signals are asserted simultaneously. Each LAB supports up to two clears and one load/preset signal.
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–44 Chapter 2: Arria GX Architecture
MultiTrack Interconnect
In addition to the clear and load/preset ports, Arria GX devices provide a device-wide reset pin (DEV_CLRn) that resets all registers in the device. An option set before compilation in the Quartus II software controls this pin. This device-wide reset overrides all other control signals.
MultiTrack Interconnect
In Arria GX architecture, the MultiTrack interconnect structure with DirectDrive technology provides connections between ALMs, TriMatrix memory, DSP blocks, and device I/O pins. The MultiTrack interconnect consists of continuous, performance-optimized routing lines of different lengths and speeds used for inter- and intra-design block connectivity. The Quartus II Compiler automatically places critical design paths on faster interconnects to improve design performance.
DirectDrive technology is a deterministic routing technology that ensures identical routing resource usage for any function regardless of placement in the device. The
MultiTrack interconnect and DirectDrive technology simplify the integration stage of block-based designing by eliminating the re-optimization cycles that typically follow design changes and additions.
The MultiTrack interconnect consists of row and column interconnects that span fixed distances. A routing structure with fixed length resources for all devices allows predictable and repeatable performance when migrating through different device densities. Dedicated row interconnects route signals to and from LABs, DSP blocks, and TriMatrix memory in the same row.
These row resources include:
■
■
■
Direct link interconnects between LABs and adjacent blocks
R4 interconnects traversing four blocks to the right or left
R24 row interconnects for high-speed access across the length of the device
The direct link interconnect allows a LAB, DSP block, or TriMatrix memory block to drive into the local interconnect of its left and right neighbors and then back into itself, providing fast communication between adjacent LABs and/or blocks without using row interconnect resources.
The R4 interconnects span four LABs, three LABs and one M512 RAM block, two
LABs and one M4K RAM block, or two LABs and one DSP block to the right or left of a source LAB. These resources are used for fast row connections in a four-LAB region.
Every LAB has its own set of R4 interconnects to drive either left or right.
shows R4 interconnect connections from a LAB.
R4 interconnects can drive and be driven by DSP blocks and RAM blocks and row
IOEs. For LAB interfacing, a primary LAB or LAB neighbor can drive a given R4 interconnect. For R4 interconnects that drive to the right, the primary LAB and right neighbor can drive onto the interconnect. For R4 interconnects that drive to the left, the primary LAB and its left neighbor can drive onto the interconnect. R4 interconnects can drive other R4 interconnects to extend the range of LABs they can drive. R4 interconnects can also drive C4 and C16 interconnects for connections from one row to another. Additionally, R4 interconnects can drive R24 interconnects.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
MultiTrack Interconnect
Figure 2–39. R4 Interconnect Connections
Adjacent LAB can
Drive onto Another
LAB's R4 Interconnect
R4 Interconnect
Driving Left
C4 and C16
Column Interconnects (1)
R4 Interconnect
Driving Right
2–45
LAB
Neighbor
Primary
LAB (2)
:
(1) C4 and C16 interconnects can drive R4 interconnects.
(2) This pattern is repeated for every LAB in the LAB row.
(3) The LABs in
show the 16 possible logical outputs per LAB.
LAB
Neighbor
R24 row interconnects span 24 LABs and provide the fastest resource for long row connections between LABs, TriMatrix memory, DSP blocks, and row IOEs. The R24 row interconnects can cross M-RAM blocks. R24 row interconnects drive to other row or column interconnects at every fourth LAB and do not drive directly to LAB local interconnects. R24 row interconnects drive LAB local interconnects via R4 and C4 interconnects. R24 interconnects can drive R24, R4, C16, and C4 interconnects. The column interconnect operates similarly to the row interconnect and vertically routes signals to and from LABs, TriMatrix memory, DSP blocks, and IOEs. Each column of
LABs is served by a dedicated column interconnect.
These column resources include:
■
■
■
■
■
Shared arithmetic chain interconnects in a LAB
Carry chain interconnects in a LAB and from LAB to LAB
Register chain interconnects in a LAB
C4 interconnects traversing a distance of four blocks in up and down direction
C16 column interconnects for high-speed vertical routing through the device
Arria GX devices include an enhanced interconnect structure in LABs for routing shared arithmetic chains and carry chains for efficient arithmetic functions. The register chain connection allows the register output of one ALM to connect directly to the register input of the next ALM in the LAB for fast shift registers. These
ALM-to-ALM connections bypass the local interconnect. The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance.
Figure 2–40 shows shared arithmetic chain, carry chain, and register
chain interconnects.
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–46 Chapter 2: Arria GX Architecture
MultiTrack Interconnect
Figure 2–40. Shared Arithmetic Chain, Carry Chain and Register Chain Interconnects
Local Interconnect
Routing Among ALMs in the LAB
ALM 1
Carry Chain & Shared
Arithmetic Chain
Routing to Adjacent ALM
Register Chain
Routing to Adjacent
ALM's Register Input
Local
Interconnect
ALM 2
ALM 3
ALM 4
ALM 5
ALM 6
ALM 7
ALM 8
C4 interconnects span four LABs, M512, or M4K blocks up or down from a source
LAB. Every LAB has its own set of C4 interconnects to drive either up or down.
Figure 2–41 shows the C4 interconnect connections from a LAB in a column. C4
interconnects can drive and be driven by all types of architecture blocks, including
DSP blocks, TriMatrix memory blocks, and column and row IOEs. For LAB interconnection, a primary LAB or its LAB neighbor can drive a given C4 interconnect. C4 interconnects can drive each other to extend their range as well as drive row interconnects for column-to-column connections.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
MultiTrack Interconnect
Figure 2–41. C4 Interconnect Connections
2–47
C4 Interconnect
Drives Local and R4
Interconnects up to Four Rows
C4 Interconnect
Driving Up
LAB
Row
Interconnect
Adjacent LAB can drive onto neighboring
LAB's C4 interconnect
Local
Interconnect
C4 Interconnect
Driving Down
Note to
:
(1) Each C4 interconnect can drive either up or down four rows.
C16 column interconnects span a length of 16 LABs and provide the fastest resource for long column connections between LABs, TriMatrix memory blocks, DSP blocks, and IOEs. C16 interconnects can cross M-RAM blocks and also drive to row and column interconnects at every fourth LAB. C16 interconnects drive LAB local interconnects via C4 and R4 interconnects and do not drive LAB local interconnects directly. All embedded blocks communicate with the logic array similar to
LAB-to-LAB interfaces. Each block (that is, TriMatrix memory and DSP blocks) connects to row and column interconnects and has local interconnect regions driven by row and column interconnects. These blocks also have direct link interconnects for fast connections to and from a neighboring LAB. All blocks are fed by the row LAB clocks, labclk[5..0].
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–48
lists the routing scheme for Arria GX device.
Table 2–10. Arria GX Device Routing Scheme
Destination
Chapter 2: Arria GX Architecture
TriMatrix Memory
Source
Shared arithmetic chain
Carry chain
Register chain
Local interconnect
Direct link interconnect
R4 interconnect
R24 interconnect
C4 interconnect
C16 interconnect
ALM
M512 RAM block
M4K RAM block
M-RAM block
DSP blocks
Column IOE
Row IOE
— — — — — — — — — v
— — — — — —
— — — — — — — — — v
— — — — — —
— — — — — — — — — v
— — — — — —
— — — — — — — — — v v v v v v v
— — — v
— — — — — — — — — — — —
— — — v
— v v v v
— — — — — — —
— — — — — v v v v
— — — — — — —
— — — v
— v
— v
— — — — — — — —
— — — — — v v v v
— — — — — — — v v v v v v
— v
— — — — — — — —
— — — v v v
— v
— — — — — — — —
— — — v v v
— v
— — — — — — — —
— — — — v v v v
— — — — — — — —
— — — — v v
— v
— — — — — — — —
— — — — v
— — v v
— — — — — — —
— — — — v v v v
— — — — — — — —
TriMatrix Memory
TriMatrix memory consists of three types of RAM blocks: M512, M4K, and M-RAM.
Although these memory blocks are different, they can all implement various types of memory with or without parity, including true dual-port, simple dual-port, and single-port RAM, ROM, and FIFO buffers.
lists the size and features of the different RAM blocks.
Table 2–11. TriMatrix Memory Features (Part 1 of 2)
Maximum performance
True dual-port memory
Simple dual-port memory
Single-port memory
Shift register
Memory Feature
M512 RAM Block
(32 × 18 Bits)
345 MHz
— v v v
M4K RAM Block
(128 × 36 Bits)
380 MHz v v v v
M-RAM Block
(4K × 144 Bits)
290 MHz v v v
—
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
TriMatrix Memory
2–49
Table 2–11. TriMatrix Memory Features (Part 2 of 2)
ROM
FIFO buffer
Pack mode
Memory Feature
Byte enable
Address clock enable
Parity bits
Mixed clock mode
Memory initialization file (.mif)
Simple dual-port memory mixed width support
True dual-port memory mixed width support
Power-up conditions
Register clears
Mixed-port read-during-write
M512 RAM Block
(32 × 18 Bits)
v v
— v
— v v v v
—
Outputs cleared
Output registers
Unknown output/old data
Configurations
512 × 1
256 × 2
128 × 4
64 × 8
64 × 9
32 × 16
32 × 18
M4K RAM Block
(128 × 36 Bits)
v v v v v v v v v v
Outputs cleared
Output registers
Unknown output/old data
4K × 1
2K × 2
1K × 4
512 × 8
512 × 9
256 × 16
256 × 18
128 × 32
128 × 36
M-RAM Block
(4K × 144 Bits)
— v v v v v v
— v v
Outputs unknown
Output registers
Unknown output
64K × 8
64K × 9
32K × 16
32K × 18
16K × 32
16K × 36
8K × 64
8K × 72
4K × 128
4K × 144
TriMatrix memory provides three different memory sizes for efficient application support. The Quartus II software automatically partitions the user-defined memory into the embedded memory blocks using the most efficient size combinations. You can also manually assign the memory to a specific block size or a mixture of block sizes.
M512 RAM Block
■
■
■
■
■
The M512 RAM block is a simple dual-port memory block and is useful for implementing small FIFO buffers, DSP, and clock domain transfer applications. Each block contains 576 RAM bits (including parity bits). M512 RAM blocks can be configured in the following modes:
Simple dual-port RAM
Single-port RAM
FIFO
ROM
Shift register
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–50 Chapter 2: Arria GX Architecture
TriMatrix Memory
When configured as RAM or ROM, you can use an initialization file to pre-load the memory contents.
M512 RAM blocks can have different clocks on its inputs and outputs. The wren, datain
, and write address registers are all clocked together from one of the two clocks feeding the block. The read address, rden, and output registers can be clocked by either of the two clocks driving the block, allowing the RAM block to operate in read and write or input and output clock modes. Only the output register can be bypassed. The six labclk signals or local interconnect can drive the inclock, outclock
, wren, rden, and outclr signals. Because of the advanced interconnect between the LAB and M512 RAM blocks, ALMs can also control the wren and rden signals and the RAM clock, clock enable, and asynchronous clear signals.
shows the M512 RAM block control signal generation logic.
Figure 2–42. M512 RAM Block Control Signals
Dedicated
Row LAB
Clocks
Local
Interconnect
6
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect inclock inclocken outclock outclocken rden wren outclr
The RAM blocks in Arria GX devices have local interconnects to allow ALMs and interconnects to drive into RAM blocks. The M512 RAM block local interconnect is driven by the R4, C4, and direct link interconnects from adjacent LABs. The M512
RAM blocks can communicate with LABs on either the left or right side through these row interconnects or with LAB columns on the left or right side with the column interconnects. The M512 RAM block has up to 16 direct link input connections from the left adjacent LABs and another 16 from the right adjacent LAB. M512 RAM outputs can also connect to left and right LABs through direct link interconnect. The
M512 RAM block has equal opportunity for access and performance to and from
LABs on either its left or right side.
shows the M512 RAM block to logic array interface.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
TriMatrix Memory
Figure 2–43. M512 RAM Block LAB Row Interface
C4 Interconnect
16
Direct link interconnect to adjacent LAB
Direct link interconnect from adjacent LAB dataout
36
M4K RAM
Block datain control signals clocks byte enable address
R4 Interconnect
Direct link interconnect to adjacent LAB
Direct link interconnect from adjacent LAB
2–51
6
M4K RAM Block Local
Interconnect Region
LAB Row Clocks
M4K RAM Blocks
■
■
■
■
■
The M4K RAM block includes support for true dual-port RAM. The M4K RAM block is used to implement buffers for a wide variety of applications such as storing processor code, implementing lookup schemes, and implementing larger memory applications. Each block contains 4,608 RAM bits (including parity bits). M4K RAM blocks can be configured in the following modes:
True dual-port RAM
Simple dual-port RAM
Single-port RAM
FIFO
ROM
■ Shift register
When configured as RAM or ROM, you can use an initialization file to pre-load the memory contents.
M4K RAM blocks allow for different clocks on their inputs and outputs. Either of the two clocks feeding the block can clock M4K RAM block registers (renwe, address, byte enable
, datain, and output registers). Only the output register can be bypassed. The six labclk signals or local interconnects can drive the control signals for the A and B ports of the M4K RAM block. ALMs can also control the clock_a, clock_b
, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b signals, as shown in
.
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–52 Chapter 2: Arria GX Architecture
TriMatrix Memory
Figure 2–44. M4K RAM Block Control Signals
Dedicated
Row LAB
Clocks
Local
Interconnect
6
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect clock_a clock_b clocken_a clocken_b renwe_a renwe_b aclr_a aclr_b
The R4, C4, and direct link interconnects from adjacent LABs drive the M4K RAM block local interconnect. The M4K RAM blocks can communicate with LABs on either the left or right side through these row resources or with LAB columns on either the right or left with the column resources. Up to 16 direct link input connections to the
M4K RAM block are possible from the left adjacent LABs and another 16 are possible from the right adjacent LAB. M4K RAM block outputs can also connect to left and right LABs through direct link interconnect.
Figure 2–45 shows the M4K RAM block
to logic array interface.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
TriMatrix Memory
Figure 2–45. M4K RAM Block LAB Row Interface
C4 Interconnect
16
Direct link interconnect to adjacent LAB
Direct link interconnect from adjacent LAB dataout
36
M4K RAM
Block datain control signals clocks byte enable address
R4 Interconnect
Direct link interconnect to adjacent LAB
Direct link interconnect from adjacent LAB
2–53
6
M4K RAM Block Local
Interconnect Region
LAB Row Clocks
M-RAM Block
■
■
The largest TriMatrix memory block, the M-RAM block, is useful for applications where a large volume of data must be stored on-chip. Each block contains 589,824
RAM bits (including parity bits). The M-RAM block can be configured in the following modes:
True dual-port RAM
Simple dual-port RAM
■
■
Single-port RAM
FIFO
You cannot use an initialization file to initialize the contents of a M-RAM block. All
M-RAM block contents power up to an undefined value. Only synchronous operation is supported in the M-RAM block, so all inputs are registered. Output registers can be bypassed.
Similar to all RAM blocks, M-RAM blocks can have different clocks on their inputs and outputs. Either of the two clocks feeding the block can clock M-RAM block registers (renwe, address, byte enable, datain, and output registers). You can bypass the output register. The six labclk signals or local interconnect can drive the control signals for the A and B ports of the M-RAM block. ALMs can also control the clock_a, clock_b
, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b
signals, as shown in
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–54 Chapter 2: Arria GX Architecture
TriMatrix Memory
Figure 2–46. M-RAM Block Control Signals
Dedicated
Row LAB
Clocks
Local
Interconnect
6
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect clocken_a clock_a aclr_a renwe_a renwe_b aclr_b clocken_b clock_b
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
The R4, R24, C4, and direct link interconnects from adjacent LABs on either the right or left side drive the M-RAM block local interconnect. Up to 16 direct link input connections to the M-RAM block are possible from the left adjacent LABs and another
16 are possible from the right adjacent LAB. M-RAM block outputs can also connect to
left and right LABs through direct link interconnect. Figure 2–47 shows an example
floorplan for the EP1AGX90 device and the location of the M-RAM interfaces.
Figure 2–49 show the interface between the M-RAM block and the
logic array.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
TriMatrix Memory
Figure 2–47. EP1AGX90 Device with M-RAM Interface Locations
M-RAM blocks interface to
LABs on right and left sides for easy access to horizontal I/O pins
M-RAM
Block
M-RAM
Block
2–55
M-RAM
Block
M-RAM
Block
M4K
Blocks
M512
Blocks
DSP
Blocks
LABs
Note to
:
(1) The device shown is an EP1AGX90 device. The number and position of M-RAM blocks vary in other devices.
DSP
Blocks
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–56
Figure 2–48. M-RAM Block LAB Row Interface
Row Unit Interface Allows LAB
Rows to Drive Port A Datain,
Dataout, Address and Control
Signals to and from M-RAM Block
Chapter 2: Arria GX Architecture
TriMatrix Memory
Row Unit Interface Allows LAB
Rows to Drive Port B Datain,
Dataout, Address and Control
Signals to and from M-RAM Block
L0
L1
L4
L5
L2
Port A
L3
M-RAM Block
LAB Interface
Blocks
LABs in Row
M-RAM Boundary
Note to
:
(1) Only R24 and C16 interconnects cross the M-RAM block boundaries.
Port B
R2
R3
R4
R5
R0
R1
LABs in Row
M-RAM Boundary
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
TriMatrix Memory
Figure 2–49. M-RAM Row Unit Interface to Interconnect
C4 Interconnect R4 and R24 Interconnects
M-RAM Block
2–57
LAB
Up to 16 dataout_a[ ]
16
Direct Link
Interconnects
Up to 28 datain_a[ ] addressa[ ] addr_ena_a renwe_a byteena
A
[ ] clocken_a clock_a aclr_a
Row Interface Block
M-RAM Block to
LAB Row Interface
Block Interconnect Region
lists the input and output data signal connections along with the address and control signal input connections to the row unit interfaces (L0 to L5 and R0 to R5).
Table 2–12. M-RAM Row Interface Unit Signals (Part 1 of 2)
Unit Interface Block
L0
L1
L2
L3
Input Signals
datain_a[14..0] byteena_a[1..0] datain_a[29..15] byteena_a[3..2] datain_a[35..30] addressa[4..0] addr_ena_a clock_a clocken_a renwe_a aclr_a addressa[15..5] datain_a[41..36]
Output Signals
dataout_a[11..0] dataout_a[23..12] dataout_a[35..24] dataout_a[47..36]
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–58 Chapter 2: Arria GX Architecture
Digital Signal Processing Block
Table 2–12. M-RAM Row Interface Unit Signals (Part 2 of 2)
Unit Interface Block
L4
L5
R0
R1
R2
R3
R4
R5
Input Signals
datain_a[56..42] byteena_a[5..4] datain_a[71..57] byteena_a[7..6] datain_b[14..0] byteena_b[1..0] datain_b[29..15] byteena_b[3..2] datain_b[35..30] addressb[4..0] addr_ena_b clock_b clocken_b renwe_b aclr_b addressb[15..5] datain_b[41..36] datain_b[56..42] byteena_b[5..4] datain_b[71..57] byteena_b[7..6]
Output Signals
dataout_a[59..48] dataout_a[71..60] dataout_b[11..0] dataout_b[23..12] dataout_b[35..24] dataout_b[47..36] dataout_b[59..48] dataout_b[71..60] f
For more information about TriMatrix memory, refer to the
TriMatrix Embedded
Memory Blocks in Arria GX Devices
chapter.
Digital Signal Processing Block
The most commonly used DSP functions are finite impulse response (FIR) filters, complex FIR filters, infinite impulse response (IIR) filters, fast Fourier transform (FFT) functions, direct cosine transform (DCT) functions, and correlators. All of these use the multiplier as the fundamental building block. Additionally, some applications need specialized operations such as multiply-add and multiply-accumulate operations. Arria GX devices provide DSP blocks to meet the arithmetic requirements of these functions.
■
■
■
Each Arria GX device has two to four columns of DSP blocks to efficiently implement
DSP functions faster than ALM-based implementations. Each DSP block can be configured to support up to:
Eight 9 × 9-bit multipliers
Four 18 × 18-bit multipliers
One 36 × 36-bit multiplier
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
Digital Signal Processing Block
2–59
As indicated, the Arria GX DSP block can support one 36 × 36-bit multiplier in a single DSP block and is true for any combination of signed, unsigned, or mixed sign multiplications.
Figure 2–50 shows one of the columns with surrounding LAB rows.
Figure 2–50. DSP Blocks Arranged in Columns
DSP Block
Column
4 LAB
Rows
DSP Block
lists the number of DSP blocks in each Arria GX device. DSP block multipliers can optionally feed an adder/subtractor or accumulator in the block depending on the configuration, which makes routing to ALMs easier, saves ALM routing resources, and increases performance because all connections and blocks are in the DSP block.
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–60 Chapter 2: Arria GX Architecture
Digital Signal Processing Block
Table 2–13. DSP Blocks in Arria GX Devices
Device
EP1AGX20
EP1AGX35
EP1AGX50
EP1AGX60
EP1AGX90
DSP Blocks
10
14
26
32
44
Total 9 × 9
Multipliers
80
112
208
256
352
Total 18 × 18
Multipliers
40
56
104
128
176
Total 36 × 36
Multipliers
10
14
26
32
44
Note to
(1) This list only shows functions that can fit into a single DSP block. Multiple DSP blocks can support larger multiplication functions.
Additionally, DSP block input registers can efficiently implement shift registers for
FIR filter applications. DSP blocks support Q1.15 format rounding and saturation.
Figure 2–51 shows a top-level diagram of the DSP block configured for 18 × 18-bit
multiplier mode.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
Digital Signal Processing Block
Figure 2–51. DSP Block Diagram for 18 × 18-Bit Configuration
Optional Serial Shift Register
Inputs from Previous
DSP Block
Multiplier Stage
D Q
ENA
CLRN
Optional Stage Configurable as Accumulator or Dynamic
Adder/Subtractor
D Q
ENA
CLRN
D Q
ENA
CLRN
1
D Q
ENA
CLRN
D Q
ENA
CLRN
D Q
ENA
CLRN
Summation
Output Selection
Multiplexer
D Q
ENA
CLRN
D Q
ENA
CLRN
D Q
ENA
CLRN
Summation Stage for Adding Four
Multipliers Together
Optional Output
Register Stage
Adder/
Subtractor/
Accumulator
2
Optional Serial
Shift Register
Outputs to
Next DSP Block in the Column
D Q
ENA
CLRN
D Q
ENA
CLRN
D Q
ENA
CLRN
Optional Pipeline
Register Stage
Optional Input Register
Stage with Parallel Input or
Shift Register Configuration
to MultiTrack
Interconnect
2–61
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–62 Chapter 2: Arria GX Architecture
Digital Signal Processing Block
Modes of Operation
■
■
The adder, subtractor, and accumulate functions of a DSP block have four modes of operation:
Simple multiplier
Multiply-accumulator
■ Two-multipliers adder
■ Four-multipliers adder
shows the different number of multipliers possible in each DSP block mode according to size. These modes allow the DSP blocks to implement numerous applications for DSP including FFTs, complex FIR, FIR, 2D FIR filters, equalizers, IIR, correlators, matrix multiplication, and many other functions. DSP blocks also support mixed modes and mixed multiplier sizes in the same block. For example, half of one
DSP block can implement one 18 × 18-bit multiplier in multiply-accumulator mode, while the other half of the DSP block implements four 9 × 9-bit multipliers in simple multiplier mode.
Table 2–14. Multiplier Size and Configurations per DSP Block
DSP Block Mode
Multiplier
Multiply-accumulator
9 × 9
Eight multipliers with eight product outputs
—
Two-multipliers adder Four two-multiplier adder (two
9 × 9 complex multiply)
Four-multipliers adder Two four-multiplier adder
18 × 18
Four multipliers with four product outputs
Two 52-bit multiply-accumulate blocks
Two two-multiplier adder (one
18 × 18 complex multiply)
One four-multiplier adder
36 × 36
One multiplier with one product output
—
—
—
DSP Block Interface
The Arria GX device DSP block input registers can generate a shift register that can cascade down in the same DSP block column. Dedicated connections between DSP blocks provide fast connections between shift register inputs to cascade shift register chains. You can cascade registers within multiple DSP blocks for 9 × 9- or 18 × 18-bit
FIR filters larger than four taps, with additional adder stages implemented in ALMs.
If the DSP block is configured as 36 × 36 bits, the adder, subtractor, or accumulator stages are implemented in ALMs. Each DSP block can route the shift register chain out of the block to cascade multiple columns of DSP blocks.
The DSP block is divided into four block units that interface with four LAB rows on the left and right. Each block unit can be considered one complete 18 × 18-bit multiplier with 36 inputs and 36 outputs. A local interconnect region is associated with each DSP block. Like an LAB, this interconnect region can be fed with 16 direct link interconnects from the LAB to the left or right of the DSP block in the same row.
R4 and C4 routing resources can access the DSP block’s local interconnect region.
The outputs also work similarly to LAB outputs. Eighteen outputs from the DSP block can drive to the left LAB through direct link interconnects and 18 can drive to the right LAB though direct link interconnects. All 36 outputs can drive to R4 and C4 routing interconnects. Outputs can drive right- or left-column routing.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
Digital Signal Processing Block
show the DSP block interfaces to LAB rows.
Figure 2–52. DSP Block Interconnect Interface
DSP Block
R4, C4 & Direct
Link Interconnects
OA[17..0]
OB[17..0]
A1[17..0]
B1[17..0]
R4, C4 & Direct
Link Interconnects
OC[17..0]
OD[17..0]
A2[17..0]
B2[17..0]
OE[17..0]
OF[17..0]
A3[17..0]
B3[17..0]
OG[17..0]
OH[17..0]
A4[17..0]
B4[17..0]
2–63
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–64
Figure 2–53. DSP Block Interface to Interconnect
C4 Interconnect
Direct Link Interconnect from Adjacent LAB
R4 Interconnect
Chapter 2: Arria GX Architecture
Digital Signal Processing Block
Direct Link Outputs to Adjacent LABs
Direct Link Interconnect from Adjacent LAB
DSP Block
Row Structure
36
LAB LAB
18
36
16
16
12
36
Control
A[17..0]
B[17..0]
OA[17..0]
OB[17..0]
36
Row Interface
Block
36 Inputs per Row DSP Block to
LAB Row Interface
Block Interconnect Region
36 Outputs per Row
A bus of 44 control signals feeds the entire DSP block. These signals include clocks, asynchronous clears, clock enables, signed and unsigned control signals, addition and subtraction control signals, rounding and saturation control signals, and accumulator synchronous loads. The clock signals are routed from LAB row clocks and are generated from specific LAB rows at the DSP block interface. The LAB row source for
control signals, data inputs, and outputs is shown in Table 2–15
.
f
For more information about DSP blocks, refer to the
DSP Blocks in Arria GX Devices
chapter.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
Digital Signal Processing Block
Table 2–15. DSP Block Signal Sources and Destinations
LAB Row at Interface
0
1
2
3
Control Signals Generated
clock0 aclr0 ena0 mult01_saturate addnsub1_round/ accum_round addnsub1 signa sourcea sourceb clock1 aclr1 ena1 accum_saturate mult01_round accum_sload sourcea sourceb mode0 clock2 aclr2 ena2 mult23_saturate addnsub3_round/ accum_round addnsub3 sign_b sourcea sourceb clock3 aclr3 ena3 accum_saturate mult23_round accum_sload sourcea sourceb mode1
Data Inputs
A1[17..0]
B1[17..0]
A2[17..0]
B2[17..0]
A3[17..0]
B3[17..0]
A4[17..0]
B4[17..0]
© December 2009 Altera Corporation
Data Outputs
OA[17..0]
OB[17..0]
OC[17..0]
OD[17..0]
OE[17..0]
OF[17..0]
OG[17..0]
OH[17..0]
2–65
Arria GX Device Handbook, Volume 1
2–66 Chapter 2: Arria GX Architecture
PLLs and Clock Networks
PLLs and Clock Networks
Arria GX devices provide a hierarchical clock structure and multiple PLLs with advanced features. The large number of clocking resources in combination with the clock synthesis precision provided by enhanced and fast PLLs provides a complete clock management solution.
Global and Hierarchical Clocking
Arria GX devices provide 16 dedicated global clock networks and 32 regional clock networks (eight per device quadrant). These clocks are organized into a hierarchical clock structure that allows for up to 24 clocks per device region with low skew and delay. This hierarchical clocking scheme provides up to 48 unique clock domains in
Arria GX devices.
There are 12 dedicated clock pins (CLK[15..12] and CLK[7..0]) to drive either the global or regional clock networks. Four clock pins drive each side of the device except the right side, as shown in
and Figure 2–55 . Internal logic and enhanced
and fast PLL outputs can also drive the global and regional clock networks. Each global and regional clock has a clock control block, which controls the selection of the clock source and dynamically enables or disables the clock to reduce power consumption.
Table 2–16 lists the global and regional clock features.
Table 2–16. Global and Regional Clock Features
Feature
Number per device
Number available per quadrant
Sources
Global Clocks
16
16
Clock pins, PLL outputs, core routings, inter-transceiver clocks
Dynamic clock source selection
Dynamic enable/disable v v
Regional Clocks
32
8
Clock pins, PLL outputs, core routings, inter-transceiver clocks
— v
Global Clock Network
These clocks drive throughout the entire device, feeding all device quadrants. GCLK networks can be used as clock sources for all resources in the device IOEs, ALMs, DSP blocks, and all memory blocks. These resources can also be used for control signals, such as clock enables and synchronous or asynchronous clears fed from the external pin. The global clock networks can also be driven by internal logic for internally generated global clocks and asynchronous clears, clock enables, or other control
signals with large fanout. Figure 2–54 shows the 12 dedicated CLK pins driving global
clock networks.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
PLLs and Clock Networks
Figure 2–54. Global Clocking
CLK[3..0]
Global Clock [15..0]
CLK[15..12]
Global Clock [15..0]
2–67
CLK[7..4]
Regional Clock Network
There are eight RCLK networks (RCLK[7..0]) in each quadrant of the Arria GX device that are driven by the dedicated CLK[15..12]and CLK[7..0] input pins, by
PLL outputs, or by internal logic. The regional clock networks provide the lowest clock delay and skew for logic contained in a single quadrant. The CLK pins symmetrically drive the RCLK networks in a particular quadrant, as shown in
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–68 Chapter 2: Arria GX Architecture
PLLs and Clock Networks
Figure 2–55. Regional Clocks
7
RCLK
[31..28]
CLK[15..12]
11 5
RCLK
[27..24]
CLK[3..0]
1
2
RCLK
[3..0]
RCLK
[7..4]
RCLK
[23..20]
Arria GX
Transceiver
Block
RCLK
[19..16]
Arria GX
Transceiver
Block
8
RCLK
[11..8]
12 6
CLK[7..4]
RCLK
[15..12]
Dual-Regional Clock Network
A single source (CLK pin or PLL output) can generate a dual-RCLK by driving two
RCLK network lines in adjacent quadrants (one from each quadrant), which allows logic that spans multiple quadrants to use the same low skew clock. The routing of this clock signal on an entire side has approximately the same speed but slightly higher clock skew when compared with a clock signal that drives a single quadrant.
Internal logic-array routing can also drive a dual-regional clock. Clock pins and enhanced PLL outputs on the top and bottom can drive horizontal dual-regional clocks. Clock pins and fast PLL outputs on the left and right can drive vertical dual-regional clocks, as shown in
Figure 2–56 . Corner PLLs cannot drive
dual-regional clocks.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
PLLs and Clock Networks
Figure 2–56. Dual-Regional Clocks
Clock Pins or PLL Clock Outputs
Can Drive Dual-Regional Network
CLK[15..12]
Clock Pins or PLL Clock
Outputs Can Drive
Dual-Regional Network
CLK[15..12]
2–69
CLK[3..0]
PLLs
CLK[3..0]
PLLs
CLK[7..4] CLK[7..4]
Combined Resources
Within each quadrant, there are 24 distinct dedicated clocking resources consisting of
16 global clock lines and eight regional clock lines. Multiplexers are used with these clocks to form buses to drive LAB row clocks, column IOE clocks, or row IOE clocks.
Another multiplexer is used at the LAB level to select three of the six row clocks to feed the ALM registers in the LAB (refer to
Figure 2–57. Hierarchical Clock Networks Per Quadrant
Clocks Available to a Quadrant or Half-Quadrant
Column I/O Cell
IO_CLK[7..0]
Global Clock Network [15..0]
Clock [23..0]
Lab Row Clock [5..0]
Regional Clock Network [7..0]
Row I/O Cell
IO_CLK[7..0]
You can use the Quartus II software to control whether a clock input pin drives either a GCLK, RCLK, or dual-RCLK network. The Quartus II software automatically selects the clocking resources if not specified.
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–70 Chapter 2: Arria GX Architecture
PLLs and Clock Networks
Clock Control Block
Each GCLK, RCLK, and PLL external clock output has its own clock control block.
The control block has two functions:
■ Clock source selection (dynamic selection for global clocks)
■ Clock power-down (dynamic clock enable or disable)
Figure 2–60 show the clock control block for the global clock,
regional clock, and PLL external clock output, respectively.
Figure 2–58. Global Clock Control Blocks
PLL Counter
Outputs
2
CLKp
Pins
2
CLKn
Pin
CLKSELECT[1..0]
(1)
2
Internal
Logic
Static Clock Select
(2)
This multiplexer supports
User-Controllable
Dynamic Switching
Enable/
Disable
Internal
Logic
GCLK
:
(1) These clock select signals can be dynamically controlled through internal logic when the device is operating in user mode.
(2) These clock select signals can only be set through a configuration file (SRAM Object File [.sof] or Programmer Object File [.pof]) and cannot be dynamically controlled during user mode operation.
Figure 2–59. Regional Clock Control Blocks
PLL Counter
Outputs
2
CLKp
Pin
CLKn
Pin
(2)
Internal
Logic
Static Clock Select (1)
Enable/
Disable
Internal
Logic
RCLK
:
(1) These clock select signals can only be set through a configuration file (.sof or .pof) and cannot be dynamically controlled during user mode operation.
(2) Only the CLKn pins on the top and bottom of the device feed to regional clock select.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
PLLs and Clock Networks
2–71
Figure 2–60. External PLL Output Clock Control Blocks
PLL Counter
Outputs (c[5..0])
6
Static Clock Select
(1)
Enable/
Disable
Internal
Logic
IOE
(2)
Internal
Logic
Static Clock
Select (1)
PLL_OUT
Pin
:
(1) These clock select signals can only be set through a configuration file (.sof or .pof) and cannot be dynamically controlled during user mode operation.
(2) The clock control block feeds to a multiplexer within the PLL_OUT pin’s IOE. The PLL_OUT pin is a dual-purpose pin. Therefore, this multiplexer selects either an internal signal or the output of the clock control block.
For the global clock control block, clock source selection can be controlled either statically or dynamically. You have the option of statically selecting the clock source by using the Quartus II software to set specific configuration bits in the configuration file (.sof or .pof) or controlling the selection dynamically by using internal logic to drive the multiplexer select inputs. When selecting statically, the clock source can be set to any of the inputs to the select multiplexer. When selecting the clock source dynamically, you can either select between two PLL outputs (such as the C0 or C1 outputs from one PLL), between two PLLs (such as the C0/C1 clock output of one
PLL or the C0/C1 c1ock output of the other PLL), between two clock pins (such as
CLK0
or CLK1), or between a combination of clock pins or PLL outputs.
For the regional and PLL_OUT clock control block, clock source selection can only be controlled statically using configuration bits. Any of the inputs to the clock select multiplexer can be set as the clock source.
Arria GX clock networks can be disabled (powered down) by both static and dynamic approaches. When a clock net is powered down, all logic fed by the clock net is in an off-state thereby reducing the overall power consumption of the device. GCLK and
RCLK networks can be powered down statically through a setting in the configuration file (.sof or .pof). Clock networks that are not used are automatically powered down through configuration bit settings in the configuration file generated by the Quartus II software. The dynamic clock enable or disable feature allows the internal logic to control power up/down synchronously on GCLK and RCLK nets and
PLL_OUT
pins. This function is independent of the PLL and is applied directly on the
clock network or PLL_OUT pin, as shown in Figure 2–58
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–72 Chapter 2: Arria GX Architecture
PLLs and Clock Networks
Enhanced and Fast PLLs
Arria GX devices provide robust clock management and synthesis using up to four enhanced PLLs and four fast PLLs. These PLLs increase performance and provide advanced clock interfacing and clock frequency synthesis. With features such as clock switchover, spread spectrum clocking, reconfigurable bandwidth, phase control, and reconfigurable phase shifting, the Arria GX device’s enhanced PLLs provide you with complete control of your clocks and system timing. The fast PLLs provide general purpose clocking with multiplication and phase shifting as well as high-speed outputs for high-speed differential I/O support. Enhanced and fast PLLs work together with the Arria GX high-speed I/O and advanced clock architecture to provide significant improvements in system performance and bandwidth.
The Quartus II software enables the PLLs and their features without requiring any external devices.
lists the PLLs available for each Arria GX device and their type.
Table 2–17. Arria GX Device PLL Availability
,
Fast PLLs Enhanced PLLs
Device
1 2 3
4
7 8 9
10
5 6 11 12
EP1AGX20
EP1AGX35
EP1AGX60
EP1AGX90
v v v v v v v v v v
—
—
—
—
—
—
—
—
—
—
—
— v v v
—
— v v v
—
—
—
—
—
—
—
—
—
— v v v v v v v v v v
—
— v v v
—
— v v v
(1) The global or regional clocks in a fast PLL's transceiver block can drive the fast PLL input. A pin or other PLL must drive the global or regional source. The source cannot be driven by internally generated logic before driving the fast PLL.
(2) EP1AGX20C, EP1AGX35C/D, EP1AGX50C and EP1AGX60C/D devices only have two fast PLLs (PLLs 1 and 2), but the connectivity from these two PLLs to the global and regional clock networks remains the same as shown in this table.
(3) PLLs 3, 4, 9, and 10 are not available in Arria GX devices.
(4) 4 or 8 PLLs are available depending on C or D device and the package option.
(5) 4or 8 PLLs are available depending on C, D, or E device option.
Table 2–18 lists the enhanced PLL and fast PLL features in Arria GX devices.
Table 2–18. Arria GX PLL Features (Part 1 of 2)
Feature
Clock multiplication and division
Phase shift
Clock switchover
PLL reconfiguration
Reconfigurable bandwidth
Spread spectrum clocking
Programmable duty cycle
Number of internal clock outputs
Number of external clock outputs
Enhanced PLL
Down to 125-ps increments
,
v v v v v
6
Three differential/six single-ended
Fast PLL
Down to 125-ps increments
,
v
v v
— v
4
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
PLLs and Clock Networks
2–73
Table 2–18. Arria GX PLL Features (Part 2 of 2)
Feature Enhanced PLL Fast PLL
Number of feedback clock inputs One single-ended or differential
—
(1) For enhanced PLLs, m, n range from 1 to 256 and post-scale counters range from 1 to 512 with 50% duty cycle.
(2) For fast PLLs, m, and post-scale counters range from 1 to 32. The n counter ranges from 1 to 4.
(3) The smallest phase shift is determined by the voltage controlled oscillator (V
CO
) period divided by 8.
(4) For degree increments, Arria GX devices can shift all output frequencies in increments of at least 45. Smaller degree increments are possible depending on the frequency and divide parameters.
(5) Arria GX fast PLLs only support manual clock switchover.
(6) Fast PLLs can drive to any I/O pin as an external clock. For high-speed differential I/O pins, the device uses a data channel to generate txclkout
.
(7) If the feedback input is used, you lose one (or two, if f
BIN
is differential) external clock output pin.
(8) Every Arria GX device has at least two enhanced PLLs with one single-ended or differential external feedback input per PLL.
Figure 2–61 shows a top-level diagram of the Arria GX device and PLL floorplan.
Figure 2–61. PLL Locations
CLK[15..12]
11 5
FPLL7CLK
7
CLK[3..0]
1
2
PLLs
FPLL8CLK 8
12 6
CLK[7..4]
shows global and regional clocking from the fast PLL outputs and side clock pins. The connections to the global and regional clocks from the fast PLL outputs, internal drivers, and CLK pins on the left side of the device are
.
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–74 Chapter 2: Arria GX Architecture
PLLs and Clock Networks
Figure 2–62. Global and Regional Clock Connections from Center Clock Pins and Fast PLL Outputs
CLK0
CLK1
Fast
PLL 1
C0
C1
C2
C3
Logic Array
Signal Input
To Clock
Network
CLK2
CLK3
Fast
PLL 2
C0
C1
C2
C3
RCLK0
RCLK1
RCLK2
RCLK3
RCLK4
RCLK5
RCLK6
RCLK7
GCLK0
GCLK1
GCLK2
GCLK3
Note to
:
(1) The global or regional clocks in a fast PLL's quadrant can drive the fast PLL input. A dedicated clock input pin or other PLL must drive the global or regional source. The source cannot be driven by internally generated logic before driving the fast PLL.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
PLLs and Clock Networks
Figure 2–63. Global and Regional Clock Connections from Corner Clock Pins and Fast PLL Outputs
RCLK0
RCLK1
RCLK2
RCLK3
Fast
PLL 7
C0
C1
C2
C3
2–75
Fast
PLL 8
C0
C1
C2
C3
RCLK4
RCLK5
RCLK6
RCLK7
GCLK0
GCLK1
GCLK2
GCLK3
Note to
:
(1) The GCLK or RCLK in a fast PLL's quadrant can drive the fast PLL input. A dedicated clock input pin or other PLL must drive the global or regional source. The source cannot be driven by internally generated logic before driving the fast PLL.
Table 2–19. Global and Regional Clock Connections from Left Side Clock Pins and Fast PLL Outputs (Part 1 of 2)
Left Side Global & Regional
Clock Network Connectivity
Clock Pins
CLK0p
CLK1p
CLK2p
CLK3p
Drivers from Internal Logic
GCLKDRV0
GCLKDRV1
GCLKDRV2
GCLKDRV3
RCLKDRV0
RCLKDRV1
RCLKDRV2
RCLKDRV3
RCLKDRV4
RCLKDRV5
RCLKDRV6 v v
— — v
— — — v
— — — v v
— — — v
— —
— — v v
—
— — v v
— v v
— — —
—
— v
—
— v
—
—
— v
—
—
— v
—
—
— v v v
— — —
— — v v
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— — v v
—
— —
— — — — — — —
— — v
— — — v
— — —
—
—
—
—
—
—
—
—
—
—
—
—
— — — — — — —
— — — v
— —
— — — — v
—
— v
— —
— — v
—
— — — — — v
— — — v
— — v
— — — v
— — —
— — — v
— —
— — — — v
—
— v
— —
— — v
—
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–76 Chapter 2: Arria GX Architecture
PLLs and Clock Networks
Table 2–19. Global and Regional Clock Connections from Left Side Clock Pins and Fast PLL Outputs (Part 2 of 2)
Left Side Global & Regional
Clock Network Connectivity
RCLKDRV7
PLL 1 Outputs
c0 c1 c2 c3
PLL 2 Outputs
c0 c1 c2 c3
PLL 7 Outputs
c0 c1 c2 c3
PLL 8 Outputs
c0 c1 c2 c3
— v v v
—
—
—
— v v
— v v v
—
—
—
— v v
—
—
—
— v v v v
—
—
—
—
—
— v v v v
—
—
— v
— v
— v
—
—
—
—
—
— v
— v
—
—
—
— v
— v
— v
—
— v
— v
— v
—
—
—
— v
— v
— v v
—
— v
— v
—
—
— v
— v
— v v v
— v v
— — — v
— v v
— v
— — v v v
— v
— v
— v
—
— — v v
— v
— v
— v
— v v
— v
—
— — v v
— v
— v
— — — —
— — v v v
— v
— — — — — v v
— — — v
— v
— — — — v v
— — v
— v
— — — — —
—
— v
— v
— — — v
— v
—
— — — — v
— v
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
PLLs and Clock Networks
2–77
Figure 2–64 shows the global and regional clocking from enhanced PLL outputs and
top and bottom CLK pins.
PLL11_FB
CLK12
CLK13
CLK14
CLK15
PLL5_FB
PLL11_OUT[2..0]p
PLL11_OUT[2..0]n
Regional
Clocks
RCLK27
RCLK26
RCLK25
RCLK24
Global
Clocks
Regional
Clocks
RCLK8
RCLK9
RCLK10
RCLK11
PLL12_OUT[2..0]p
PLL12_OUT[2..0]n
PLL 11
PLL 5 c0 c1 c2 c3 c4 c5 c0 c1 c2 c3 c4 c5
PLL5_OUT[2..0]p
PLL5_OUT[2..0]n
RCLK31
RCLK30
RCLK29
RCLK28
G4
G5
G6
G7
G15
G14
G13
G12 c0 c1 c2 c3 c4 c5 c0 c1 c2 c3 c4 c5
PLL 12
PLL 6
RCLK12
RCLK13
RCLK14
RCLK15
PLL6_OUT[2..0]p
PLL6_OUT[2..0]n
PLL12_FB
CLK4
CLK5
CLK6
CLK7
PLL6_FB
Note to
:
(1) If the design uses the feedback input, you might lose one (or two if FBIN is differential) external clock output pin.
The connections to the global and regional clocks from the top clock pins and enhanced PLL outputs are shown in
. The connections to the clocks from the bottom clock pins are shown in
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–78 Chapter 2: Arria GX Architecture
PLLs and Clock Networks
Table 2–20. Global and Regional Clock Connections from Top Clock Pins and Enhanced PLL Outputs
Top Side Global and
Regional Clock Network
Connectivity
Clock pins
CLK12p
CLK13p
CLK14p
CLK15p
CLK12n
CLK13n
CLK14n
CLK15n
Drivers from internal logic
GCLKDRV0
GCLKDRV1
GCLKDRV2
GCLKDRV3
RCLKDRV0
RCLKDRV1
RCLKDRV2
RCLKDRV3
RCLKDRV4
RCLKDRV5
RCLKDRV6
RCLKDRV7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— v v v v
—
Enhanced PLL5 outputs
c3 c4 c5 c0 c1 c2
Enhanced PLL 11 outputs
c0 c1 c2 c3 c4 c5 v v v v v v
—
—
—
—
—
—
— v
— v v v v
— —
—
—
— v
—
—
—
—
—
—
—
—
—
—
— v v v v
—
—
—
— v v v v
—
—
—
—
— v
—
—
— v
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— v v v v
—
— v
—
—
— v
—
—
—
—
—
—
—
—
—
—
— v v v v
—
—
—
— — v v v v
—
—
—
—
—
—
— v
—
—
— v
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— v
—
—
— v
—
—
—
—
—
—
— v
—
—
— v
—
—
— v
—
—
— v
— v
—
—
— v
—
— v
—
— v
—
— v
—
— v
—
—
—
—
—
— v
— v
— v
—
—
—
—
—
—
—
—
—
—
— v
— —
—
—
— v
— —
—
—
— v
— —
— v v
— v
—
—
—
— v
—
— v
— v
—
—
—
—
—
— v
—
—
— v
—
—
—
—
— v
—
—
— v
—
—
— v
— v
—
—
— v
— v v
—
—
— v
—
—
—
—
— v
—
—
— v
—
—
—
— v
—
—
— v
—
— v
—
—
— v
—
— — v
—
— v
— —
— — v
—
— v
— —
—
—
—
—
— — v
—
— v
— —
— — v
—
— v
— —
—
—
—
—
— — v
—
— v
— —
— v v
—
— — v
—
— v
— —
— v v
—
—
—
— v
— v
—
—
— v
— v
—
—
— v
—
—
— v
—
—
— v
—
—
— v
—
—
—
—
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
PLLs and Clock Networks
2–79
Table 2–21. Global and Regional Clock Connections from Bottom Clock Pins and Enhanced PLL Outputs
Bottom Side Global and
Regional Clock Network
Connectivity
Clock pins
CLK4p
CLK5p
CLK6p
CLK7p
CLK4n
CLK5n
CLK6n
CLK7n
Drivers from internal logic
GCLKDRV0
GCLKDRV1
GCLKDRV2
GCLKDRV3
RCLKDRV0
RCLKDRV1
RCLKDRV2
RCLKDRV3
RCLKDRV4
RCLKDRV5
RCLKDRV6
RCLKDRV7
—
—
—
—
—
—
—
—
—
—
—
—
—
—
— v v v v
—
Enhanced PLL 6 outputs
c3 c4 c5 c0 c1 c2
Enhanced PLL 12 outputs
c0 c1 c2 c3 c4 c5 v v v v v v
—
—
—
—
—
—
— v
— v v v v
— —
—
—
— v
—
—
—
—
—
—
—
—
—
—
— v v v v
—
—
—
—
—
—
—
—
— v
—
—
— v
—
—
—
—
—
—
—
—
—
—
—
—
—
— v v v v
—
—
—
—
—
—
—
— v
—
— — — v v v v v
—
—
—
— v
—
—
—
— v v
—
—
— v
—
—
—
—
—
—
—
—
—
—
—
—
—
— v
—
—
—
—
—
—
—
—
—
— v
— —
— v
—
—
— v
—
—
—
—
—
—
— v
—
—
— v
— — —
— —
— v
—
—
— v v v
— v v v v
—
— v v
—
—
— v
—
—
—
— v
—
—
—
—
—
—
—
—
— v
—
—
— v
—
—
— v
—
—
— v
—
— v
—
—
— v
—
—
—
—
—
—
— v
—
—
— v
—
—
— v
— v
—
—
— v
— v
—
—
—
— v
—
—
— v
—
—
—
—
—
—
— v
—
—
— v
—
—
— v
— v
—
—
— v
— v v
— —
— v
—
—
— v
— — — v
— —
— v
—
—
— v
— — —
—
—
—
—
—
—
—
—
—
— — — v
—
— v
—
—
—
— v
— — — v
—
— v
—
—
—
— v
— — — v
—
—
— v
—
— v
— — — v
— v
— v
— v
—
— v
—
—
—
— v
— — — v
— v
— v
—
—
— v
— v
—
—
— v
— v
—
—
— v
—
—
— v
—
—
— v
—
—
— v
—
—
—
—
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–80 Chapter 2: Arria GX Architecture
PLLs and Clock Networks
Enhanced PLLs
Arria GX devices contain up to four enhanced PLLs with advanced clock management features. These features include support for external clock feedback
mode, spread-spectrum clocking, and counter cascading. Figure 2–65 shows a
diagram of the enhanced PLL.
Figure 2–65. Arria GX Enhanced PLL
V
CO
Phase Selection
Selectable at Each
PLL Output Port
Post-Scale
Counters
From Adjacent PLL
Clock
Switchover
Circuitry
Phase Frequency
Detector
Spread
Spectrum
/c0
INCLK[3..0]
4
/c1
4
Global or
Regional
Clock
/n
PFD
Charge
Pump
Loop
Filter
VCO
8
/c2
6
/c3
8
6
Global
Clocks
Regional
Clocks
I/O Buffers (3)
/c4
/m
(2)
/c5
FBIN
Lock Detect
& Filter to I/O or general routing
Shaded Portions of the
PLL are Reconfigurable
VCO Phase Selection
Affecting All Outputs
:
(1) Each clock source can come from any of the four clock pins that are physically located on the same side of the device as the PLL.
(2) If the feedback input is used, you will lose one (or two, if FBIN is differential) external clock output pin.
(3) Each enhanced PLL has three differential external clock outputs or six single-ended external clock outputs.
(4) The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a clock control block provided the clock control block is fed by an output from another PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
Fast PLLs
Arria GX devices contain up to four fast PLLs with high-speed serial interfacing ability. Fast PLLs offer high-speed outputs to manage the high-speed differential I/O
interfaces. Figure 2–66 shows a diagram of the fast PLL.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
I/O Structure
2–81
Figure 2–66. Arria GX Device Fast PLL
Post-Scale
Counters
Clock
Switchover
Circuitry (4)
VCO Phase Selection
Selectable at each PLL
Output Port
Global or regional clock (1)
Phase
Frequency
Detector
diffioclk0
(2)
load_en0
(3)
÷c0
Clock
Input
4
÷n PFD
Charge
Pump
Loop
Filter
VCO
÷k
8
÷c1
4 load_en1
(3)
diffioclk1
(2)
Global clocks
÷c2
Global or regional clock (1)
4
8
Regional clocks
÷c3
÷m
8 to DPA block
Shaded Portions of the
PLL are Reconfigurable
:
(1) The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a clock control block provided the clock control block is fed by an output from another PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
(2) In high-speed differential I/O support mode, this high-speed PLL clock feeds the serializer/deserializer (SERDES) circuitry. Arria GX devices only support one rate of data transfer per fast PLL in high-speed differential I/O support mode.
(3) This signal is a differential I/O SERDES control signal.
(4) Arria GX fast PLLs only support manual clock switchover.
f
For more information about enhanced and fast PLLs, refer to the
PLLs in Arria GX
Devices
chapter. For more information about high-speed differential I/O support, refer to
“High-Speed Differential I/O with DPA Support” on page 2–99 .
I/O Structure
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
Arria GX IOEs provide many features, including:
Dedicated differential and single-ended I/O buffers
3.3-V, 64-bit, 66-MHz PCI compliance
3.3-V, 64-bit, 133-MHz PCI-X 1.0 compliance
JTAG boundary-scan test (BST) support
On-chip driver series termination
OCT for differential standards
Programmable pull-up during configuration
Output drive strength control
Tri-state buffers
Bus-hold circuitry
Programmable pull-up resistors
Programmable input and output delays
Open-drain outputs
DQ and DQS I/O pins
DDR registers
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–82 Chapter 2: Arria GX Architecture
I/O Structure
The IOE in Arria GX devices contains a bidirectional I/O buffer, six registers, and a latch for a complete embedded bidirectional single data rate or DDR transfer.
Figure 2–67 shows the Arria GX IOE structure. The IOE contains two input registers
(plus a latch), two output registers, and two output enable registers. The design can use both input registers and the latch to capture DDR input and both output registers to drive DDR outputs. Additionally, the design can use the output enable (OE) register for fast clock-to-output enable timing. The negative edge-clocked OE register is used for DDR SDRAM interfacing. The Quartus II software automatically duplicates a single OE register that controls multiple output or bidirectional pins.
Figure 2–67. Arria GX IOE Structure
Logic Array
OE
OE Register
D Q
OE Register
D Q
Output A
Output Register
D Q
Output B
Output Register
D Q
CLK
Input A
Input B
Input Register
D Q
Input Register
Input Latch
D Q
D
ENA
Q
The IOEs are located in I/O blocks around the periphery of the Arria GX device.
There are up to four IOEs per row I/O block and four IOEs per column I/O block.
Row I/O blocks drive row, column, or direct link interconnects. Column I/O blocks drive column interconnects.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
I/O Structure
Figure 2–68 shows how a row I/O block connects to the logic array.
Figure 2–68. Row I/O Block Connection to the Interconnect
R4 & R24
Interconnects
C4 Interconnect
I/O Block Local
Interconnect
2–83
LAB
32
Horizontal
I/O Block
32 Data & Control
Signals from
Logic Array (1)
io_dataina[3..0] io_datainb[3..0]
LAB Local
Interconnect
Direct Link
Interconnect to Adjacent LAB
Direct Link
Interconnect to Adjacent LAB
io_clk[7:0]
Horizontal I/O
Block Contains up to Four IOEs
Note to
:
(1) The 32 data and control signals consist of eight data out lines: four lines each for DDR applications io_dataouta[3..0] and io_dataoutb[3..0]
, four output enables io_oe[3..0], four input clock enables io_ce_in[3..0], four output clock enables io_ce_out[3..0]
, four clocks io_clk[3..0], four asynchronous clear and preset signals io_aclr/apreset[3..0], and four synchronous clear and preset signals io_sclr/spreset[3..0].
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–84 Chapter 2: Arria GX Architecture
I/O Structure
Figure 2–69 shows how a column I/O block connects to the logic array.
Figure 2–69. Column I/O Block Connection to the Interconnect
32 Data &
Control Signals from Logic Array (1)
Vertical I/O Block
Vertical I/O
Block Contains up to Four IOEs
32
IO_dataina[3..0]
IO_datainb[3..0]
io_clk[7..0]
I/O Block
Local Interconnect
R4 & R24
Interconnects
LAB LAB LAB
LAB Local
Interconnect
C4 & C16
Interconnects
Note to
:
(1) The 32 data and control signals consist of eight data out lines: four lines each for DDR applications io_dataouta[3..0] and io_dataoutb[3..0]
, four output enables io_oe[3..0], four input clock enables io_ce_in[3..0], four output clock enables io_ce_out[3..0]
, four clocks io_clk[3..0], four asynchronous clear and preset signals io_aclr/apreset[3..0], and four synchronous clear and preset signals io_sclr/spreset[3..0].
There are 32 control and data signals that feed each row or column I/O block. These control and data signals are driven from the logic array. The row or column IOE clocks, io_clk[7..0], provide a dedicated routing resource for low-skew, high-speed clocks. I/O clocks are generated from global or regional clocks (refer to
“PLLs and Clock Networks” on page 2–66 ).
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
I/O Structure
Figure 2–70 shows the signal paths through the I/O block.
Figure 2–70. Signal Path Through the I/O Block
Row or Column io_clk[7..0]
To Other
IOEs
To Logic
Array
io_dataina io_datainb
From Logic
Array
io_oe io_ce_in io_ce_out io_aclr io_sclr io_clk io_dataouta io_dataoutb
Control
Signal
Selection oe ce_in ce_out aclr/apreset sclr/spreset clk_in clk_out
IOE
2–85
Each IOE contains its own control signal selection for the following control signals: oe
, ce_in, ce_out, aclr/apreset, sclr/spreset, clk_in, and clk_out.
Figure 2–71 shows the control signal selection.
Figure 2–71. Control Signal Selection per IOE
Dedicated I/O
Clock [7..0]
Local
Interconnect io_oe io_sclr
Local
Interconnect io_aclr
Local
Interconnect
Local
Interconnect io_ce_out
Local
Interconnect io_ce_in
Local
Interconnect io_clk clk_out ce_out sclr/spreset clk_in ce_in aclr/apreset oe
:
(1) Control signals ce_in, ce_out, aclr/apreset, sclr/spreset, and oe can be global signals even though their control selection multiplexers are not directly fed by the ioe_clk[7..0] signals. The ioe_clk signals can drive the I/O local interconnect, which then drives the control selection multiplexers.
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–86 Chapter 2: Arria GX Architecture
I/O Structure
In normal bidirectional operation, you can use the input register for input data requiring fast setup times. The input register can have its own clock input and clock enable separate from the OE and output registers. The output register can be used for data requiring fast clock-to-output performance. You can use the OE register for fast clock-to-output enable timing. The OE and output register share the same clock source and the same clock enable source from the local interconnect in the associated
LAB, dedicated I/O clocks, and the column and row interconnects.
shows the IOE in bidirectional configuration.
Figure 2–72. Arria GX IOE in Bidirectional I/O Configuration
ioe_clk[7..0]
Column, Row, or Local
Interconnect oe clkout ce_out aclr/apreset
Chip-Wide Reset sclr/spreset clkin ce_in
OE Register
D Q
ENA
CLRN/PRN
Output Register
D Q
Output
Pin Delay
ENA
CLRN/PRN
Drive Strength Control
Open-Drain Output
Input Pin to
Logic Array Delay
Input Pin to
Input Register Delay
Input Register
D Q
OE Register t
CO
Delay
V
CCIO
PCI Clamp (2)
V
CCIO
Programmable
Pull-Up
Resistor
On-Chip
Termination
Bus-Hold
Circuit
ENA
CLRN/PRN
:
(1) All input signals to the IOE can be inverted at the IOE.
(2) The optional PCI clamp is only available on column I/O pins.
The Arria GX device IOE includes programmable delays that can be activated to ensure input IOE register-to-logic array register transfers, input pin-to-logic array register transfers, or output IOE register-to-pin transfers.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
I/O Structure
2–87
A path in which a pin directly drives a register can require the delay to ensure zero hold time, whereas a path in which a pin drives a register through combinational logic may not require the delay. Programmable delays exist for decreasing input-pin-to-logic-array and IOE input register delays. The Quartus II Compiler can program these delays to automatically minimize setup time while providing a zero hold time. Programmable delays can increase the register-to-pin delays for output and/or output enable registers. Programmable delays are no longer required to ensure zero hold times for logic array register-to-IOE register transfers. The Quartus II
Compiler can create zero hold time for these transfers. Table 2–22
shows the programmable delays for Arria GX devices.
Table 2–22. Arria GX Devices Programmable Delay Chain
Programmable Delays
Input pin to logic array delay
Input pin to input register delay
Output pin delay
Output enable register t
CO
delay
Quartus II Logic Option
Input delay from pin to internal cells
Input delay from pin to input register
Delay from output register to output pin
Delay to output enable pin
IOE registers in Arria GX devices share the same source for clear or preset. You can program preset or clear for each individual IOE. You can also program the registers to power up high or low after configuration is complete. If programmed to power up low, an asynchronous clear can control the registers. If programmed to power up high, an asynchronous preset can control the registers. This feature prevents the inadvertent activation of another device’s active-low input upon power-up. If one register in an IOE uses a preset or clear signal, all registers in the IOE must use that same signal if they require preset or clear. Additionally, a synchronous reset signal is available for the IOE registers.
Double Data Rate I/O Pins
Arria GX devices have six registers in the IOE, which support DDR interfacing by clocking data on both positive and negative clock edges. The IOEs in Arria GX devices support DDR inputs, DDR outputs, and bidirectional DDR modes. When using the
IOE for DDR inputs, the two input registers clock double rate input data on alternating edges. An input latch is also used in the IOE for DDR input acquisition.
The latch holds the data that is present during the clock high times, allowing both bits of data to be synchronous with the same clock edge (either rising or falling).
Figure 2–73 shows an IOE configured for DDR input. Figure 2–74
shows the DDR input timing diagram.
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–88 Chapter 2: Arria GX Architecture
I/O Structure
Figure 2–73. Arria GX IOE in DDR Input I/O Configuration
ioe_clk[7..0]
Column, Row, or Local
Interconnect
DQS Local
Bus (2) sclr/spreset
I nput Pin to
Input RegisterDelay
Input Register
D Q
To DQS Logic
Block (3)
VCCIO
PCI Clamp (4)
VCCIO
Programmable
Pull-Up
Resistor
On-Chip
Termination clkin ce_in aclr/apreset
ENA
CLRN/PRN
Bus-Hold
Circuit
Chip-Wide Reset
Input Register
D Q D
Latch
Q
ENA
CLRN/PRN
ENA
CLRN/PRN
:
(1) All input signals to the IOE can be inverted at the IOE.
(2) This signal connection is only allowed on dedicated DQ function pins.
(3) This signal is for dedicated DQS function pins only.
(4) The optional PCI clamp is only available on column I/O pins.
Figure 2–74. Input Timing Diagram in DDR Mode
Data at input pin
B0 A0 B1 A1 B2 A2 B3 A3 B4
CLK
Input To
Logic Array
A0 A1 A2 A3
B0 B1 B2 B3
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
I/O Structure
2–89
When using the IOE for DDR outputs, the two output registers are configured to clock two data paths from ALMs on rising clock edges. These output registers are multiplexed by the clock to drive the output pin at a ×2 rate. One output register clocks the first bit out on the clock high time, while the other output register clocks the second bit out on the clock low time.
shows the IOE configured for DDR output.
Figure 2–76 shows the DDR output timing diagram.
Figure 2–75. Arria GX IOE in DDR Output I/O Configuration
ioe_clk[7..0]
Column, Row, or Local
Interconnect oe clkout ce_out
OE Register
D Q
ENA
CLRN/PRN
OE Register tCO Delay aclr/apreset sclr/spreset
Chip-Wide Reset
OE Register
D Q
ENA
CLRN/PRN
Used for
DDR, DDR2
SDRAM
Output Register
D Q
ENA
CLRN/PRN
Output
Pin Delay clk
Drive Strength
Control
Open-Drain Output
Output Register
D Q
VCCIO
PCI Clamp (3)
VCCIO
Programmable
Pull-Up
Resistor
On-Chip
Termination
ENA
CLRN/PRN
Bus-Hold
Circuit
:
(1) All input signals to the IOE can be inverted at the IOE.
(2) The tri-state buffer is active low. The DDIO megafunction represents the tri-state buffer as active-high with an inverter at the OE register data port.
(3) The optional PCI clamp is only available on column I/O pins.
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–90 Chapter 2: Arria GX Architecture
I/O Structure
Figure 2–76. Output Timing Diagram in DDR Mode
CLK
A1 A2 A3 A4
From Internal
Registers
B1 B2 B3 B4
DDR output
B1 A1 B2 A2 B3 A3 B4 A4
The Arria GX IOE operates in bidirectional DDR mode by combining the DDR input and DDR output configurations. The negative-edge-clocked OE register holds the OE signal inactive until the falling edge of the clock to meet DDR SDRAM timing requirements.
External RAM Interfacing
In addition to the six I/O registers in each IOE, Arria GX devices also have dedicated phase-shift circuitry for interfacing with external memory interfaces, including DDR,
DDR2 SDRAM, and SDR SDRAM. In every Arria GX device, the I/O banks at the top
(Banks 3 and 4) and bottom (Banks 7 and 8) of the device support DQ and DQS signals with DQ bus modes of ×4, ×8/×9, ×16/×18, or ×32/×36.
of DQ and DQS buses that are supported per device.
Table 2–23. DQS and DQ Bus Mode Support
Device Package
EP1AGX20
EP1AGX35
EP1AGX50/60
484-pin FineLine BGA
484-pin FineLine BGA
780-pin FineLine BGA
484-pin FineLine BGA
780-pin FineLine BGA
1,152-pin FineLine
BGA
EP1AGX90
1,152-pin FineLine
BGA
Note to
(1) Numbers are preliminary until devices are available.
Number of
×4 Groups
2
2
18
2
18
36
36
Number of
×8/×9 Groups
0
0
8
0
8
18
18
Number of
×16/×18 Groups
0
0
4
0
4
8
Number of
×32/×36 Groups
0
0
0
0
0
4
8 4
A compensated delay element on each DQS pin automatically aligns input DQS synchronization signals with the data window of their corresponding DQ data signals. The DQS signals drive a local DQS bus in the top and bottom I/O banks. This
DQS bus is an additional resource to the I/O clocks and is used to clock DQ input registers with the DQS signal.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
I/O Structure
2–91
The Arria GX device has two phase-shifting reference circuits, one on the top and one on the bottom of the device. The circuit on the top controls the compensated delay elements for all DQS pins on the top. The circuit on the bottom controls the compensated delay elements for all DQS pins on the bottom.
Each phase-shifting reference circuit is driven by a system reference clock, which must have the same frequency as the DQS signal. Clock pins CLK[15..12]p feed phase circuitry on the top of the device and clock pins CLK[7..4]p feed phase circuitry on the bottom of the device. In addition, PLL clock outputs can also feed the phase-shifting reference circuits.
Figure 2–77 shows the phase-shift reference circuit
control of each DQS delay shift on the top of the device. This same circuit is duplicated on the bottom of the device.
Figure 2–77. DQS Phase-Shift Circuitry
DQS
Pin
DQS
Pin
CLK[15..12]p (3)
From PLL 5 (4)
DQS
Pin
DQS
Pin
Dt Dt
DQS
Phase-Shift
Circuitry
Dt Dt to IOE to IOE to IOE to IOE
:
(1) There are up to 18 pairs of DQS pins available on the top or bottom of the Arria GX device. There are up to 10 pairs on the right side and 8 pairs on the left side of the DQS phase-shift circuitry.
(2) The “t” module represents the DQS logic block.
(3) Clock pins CLK[15..12]p feed phase-shift circuitry on the top of the device and clock pins CLK[7..4]p feed the phase circuitry on the bottom of the device. You can also use a PLL clock output as a reference clock to phase shift circuitry.
(4) You can only use PLL 5 to feed the DQS phase-shift circuitry on the top of the device and PLL 6 to feed the DQS phase-shift circuitry on the bottom of the device.
These dedicated circuits combined with enhanced PLL clocking and phase-shift ability provide a complete hardware solution for interfacing to high-speed memory.
f
For more information about external memory interfaces, refer to the
External Memory
Interfaces in Arria GX Devices
chapter.
Programmable Drive Strength
The output buffer for each Arria GX device I/O pin has a programmable drive strength control for certain I/O standards. The LVTTL, LVCMOS, SSTL, and HSTL standards have several levels of drive strength that you can control. The default setting used in the Quartus II software is the maximum current strength setting that is used to achieve maximum I/O performance. For all I/O standards, the minimum setting is the lowest drive strength that guarantees the I
OH
/I
OL
of the standard. Using minimum settings provides signal slew rate control to reduce system noise and signal overshoot.
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–92 Chapter 2: Arria GX Architecture
I/O Structure
shows the possible settings for I/O standards with drive strength control.
Table 2–24. Programmable Drive Strength
I/O Standard
I
OH
/ I
OL
Current Strength
Setting (mA) for Column
I/O Pins
I
OH
/ I
OL
Current Strength
Setting (mA) for Row I/O
Pins
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
24, 20, 16, 12, 8, 4
24, 20, 16, 12, 8, 4
16, 12, 8, 4
12, 10, 8, 6, 4, 2
8, 6, 4, 2
12, 8
24, 20, 16
12, 8, 4
8, 4
12, 8, 4
8, 6, 4, 2
4, 2
12, 8
16
SSTL-18 Class I
SSTL-18 Class II
HSTL-18 Class I
HSTL-18 Class II
12, 10, 8, 6, 4
20, 18, 16, 8
12, 10, 8, 6, 4
20, 18, 16
10, 8, 6, 4
—
12, 10, 8, 6, 4
—
HSTL-15 Class I
HSTL-15 Class II
12, 10, 8, 6, 4
20, 18, 16
8, 6, 4
—
Note to
(1) The Quartus II software default current setting is the maximum setting for each I/O standard.
Open-Drain Output
Arria GX devices provide an optional open-drain (equivalent to an open collector) output for each I/O pin. This open-drain output enables the device to provide system-level control signals (for example, interrupt and write enable signals) that can be asserted by any of several devices.
Bus Hold
Each Arria GX device I/O pin provides an optional bus-hold feature. Bus-hold circuitry can hold the signal on an I/O pin at its last-driven state. Because the bus-hold feature holds the last-driven state of the pin until the next input signal is present, an external pull-up or pull-down resistor is not needed to hold a signal level when the bus is tri-stated.
Bus-hold circuitry also pulls undriven pins away from the input threshold voltage where noise can cause unintended high-frequency switching. You can select this feature individually for each I/O pin. The bus-hold output drives no higher than
V
CCIO
to prevent overdriving signals. If the bus-hold feature is enabled, the programmable pull-up option cannot be used. Disable the bus-hold feature when the
I/O pin has been configured for differential signals.
Bus-hold circuitry uses a resistor with a nominal resistance (RBH) of approximately
7 k to pull the signal level to the last-driven state. This information is provided for each V
CCIO
voltage level. Bus-hold circuitry is active only after configuration. When going into user mode, the bus-hold circuit captures the value on the pin present at the end of configuration.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
I/O Structure
2–93
f
For the specific sustaining current driven through this resistor and overdrive current used to identify the next-driven input level, refer to the
DC & Switching Characteristics
chapter.
Programmable Pull-Up Resistor
Each Arria GX device I/O pin provides an optional programmable pull-up resistor during user mode. If you enable this feature for an I/O pin, the pull-up resistor
(typically 25 k) holds the output to the V
CCIO
level of the output pin’s bank.
Advanced I/O Standard Support
Arria GX device IOEs support the following I/O standards:
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
3.3-V PCI
3.3-V PCI-X mode 1
LVDS
LVPECL (on input and output clocks only)
Differential 1.5-V HSTL class I and II
Differential 1.8-V HSTL class I and II
Differential SSTL-18 class I and II
Differential SSTL-2 class I and II
1.2-V HSTL class I and II
1.5-V HSTL class I and II
1.8-V HSTL class I and II
SSTL-2 class I and II
SSTL-18 class I and II
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–94 Chapter 2: Arria GX Architecture
I/O Structure
describes the I/O standards supported by Arria GX devices.
Table 2–25. Arria GX Devices Supported I/O Standards
I/O Standard Type
LVTTL
LVCMOS
2.5 V
1.8 V
1.5-V LVCMOS
3.3-V PCI
3.3-V PCI-X mode 1
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
Single-ended
LVDS
LVPECL
Differential
Differential
HyperTransport technology Differential
Differential 1.5-V HSTL class I and II
Differential
Differential 1.8-V HSTL class I and II
Differential
Differential SSTL-18 class I and II
Differential
Differential SSTL-2 class I and II
Differential
Voltage-referenced
1.5-V HSTL class I and II
1.8-V HSTL class I and II
SSTL-18 class I and II
SSTL-2 class I and II
Voltage-referenced
Voltage-referenced
Voltage-referenced
Voltage-referenced
Input Reference
Voltage
(V
REF
) (V)
—
—
—
—
—
—
—
—
—
—
0.75 1.5
0.90 1.8
0.90 1.8
1.25
0.6
0.75
0.9
0.90
1.25
Output Supply
Voltage
(V
CCIO
) (V)
3.3
3.3
2.5
1.8
1.5
3.3
3.3
2.5
3.3
2.5
1.2
1.5
1.8
1.8
2.5
(1) This I/O standard is only available on input and output column clock pins.
(2) This I/O standard is only available on input clock pins and DQS pins in I/O banks 3, 4, 7, and 8, and output clock pins in I/O banks 9, 10, 11, and 12.
(3) V
CCIO
is 3.3 V when using this I/O standard in input and output column clock pins (in I/O banks 3, 4, 7, 8, 9, 10, 11, and 12).
(4) 1.2-V HSTL is only supported in I/O banks 4, 7, and 8.
Board
Termination
Voltage (V
TT
) (V)
—
—
—
—
—
—
—
0.75
0.9
0.90
1.25
—
—
—
0.75
0.90
0.90
1.25
0.6
f
For more information about the I/O standards supported by Arria GX I/O banks, refer to the
Selectable I/O Standards in Arria GX Devices
chapter.
Arria GX devices contain six I/O banks and four enhanced PLL external clock output banks, as shown in
. The two I/O banks on the left of the device contain circuitry to support source-synchronous, high-speed differential I/O for LVDS inputs and outputs. These banks support all Arria GX I/O standards except PCI or PCI-X
I/O pins, and SSTL-18 class II and HSTL outputs. The top and bottom I/O banks support all single-ended I/O standards. Additionally, enhanced PLL external clock output banks allow clock output capabilities such as differential support for SSTL and
HSTL.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
I/O Structure
2–95
Figure 2–78. Arria GX I/O Banks
PLL7
DQS
×8
DQS
×8
DQS
×8
DQS
×8
VREF0B3 VREF1B3 VREF2B3 VREF3B3 VREF4B3
Bank 3
PLL11
Bank 11
PLL5
Bank 9
DQS
×8
DQS
×8
DQS
×8
DQS
×8
DQS
×8
VREF0B4 VREF1B4 VREF2B4 VREF3B4 VREF4B4
Bank 4
PLL1
PLL2
This I/O bank supports LVDS and LVPECL standards for input clock operations. Differential HSTL and differential SSTL standards are supported for both input and output operations. (3)
I/O Banks 3, 4, 9, and 11 support all single-ended
I/O standards for both input and output operations.
All differential I/O standards are supported for both input and output operations at I/O banks 9 and 11.
I/O banks 1 & 2 support LVTTL, LVCMOS,
2.5 V, 1.8 V, 1.5 V, SSTL-2, SSTL-18 class I,
LVDS, pseudo-differential SSTL-2 and pseudo-differential
SSTL-18 class I standards for both input and output operations. HSTL, SSTL-18 class II, pseudo-differential HSTL and pseudo-differential
SSTL-18 class II standards are only supported for input operations. (4)
This I/O bank supports LVDS and LVPECL standards for input clock operation. Differential HSTL and differential SSTL standards are supported for both input and output operations. (3)
SSTL standards are supported for both input and output operations. (3)
I/O banks 7, 8, 10 and 12 support all single-ended I/O standards for both input and output operations. All differential
I/O standards are supported for both input and output operations at I/O banks 10 and 12.
This I/O bank supports LVDS and LVPECL standards for input clock operation.
Differential HSTL and differential
This I/O bank supports LVDS and LVPECL standards for input clock operation. Differential HSTL and differential
SSTL standards are supported for both input and output operations. (3)
Transmitter: Bank 13
Receiver: Bank 13
REFCLK: Bank 13
Transmitter: Bank 14
Receiver: Bank 14
REFCLK: Bank 14
Transmitter: Bank 15
Receiver: Bank 15
REFCLK: Bank 15
PLL8
Bank 8
VREF4B8 VREF3B8 VREF2B8 VREF1B8 VREF0B8
DQS
×8
DQS
×8
DQS
×8
DQS
×8
Bank 12
PLL12
Bank 10
PLL6
Bank 7
VREF4B7 VREF3B7 VREF2B7 VREF1B7 VREF0B7
DQS
×8
DQS
×8
DQS
×8
DQS
×8
DQS
×8
:
(1)
is a top view of the silicon die that corresponds to a reverse view for flip chip packages. It is a graphical representation only.
(2) Depending on the size of the device, different device members have different numbers of V
REF and the Quartus II software.
groups. For the exact locations, refer to the pin list
(3) Banks 9 through 12 are enhanced PLL external clock output banks.
(4) Horizontal I/O banks feature SERDES and DPA circuitry for high-speed differential I/O standards. For more information about differential I/O standards, refer to the
High-Speed Differential I/O Interfaces in Arria GX Devices
chapter.
Each I/O bank has its own VCCIO pins. A single device can support
1.5-, 1.8-, 2.5-, and 3.3-V interfaces; each bank can support a different V
CCIO level independently. Each bank also has dedicated VREF pins to support the voltage-referenced standards (such as SSTL-2).
Each I/O bank can support multiple standards with the same V
CCIO
for input and output pins. Each bank can support one V
REF
voltage level. For example, when V
CCIO
is
3.3 V, a bank can support LVTTL, LVCMOS, and 3.3-V PCI for inputs and outputs.
On-Chip Termination
Arria GX devices provide differential (for the LVDS technology I/O standard) and on-chip series termination to reduce reflections and maintain signal integrity. There is no calibration support for these on-chip termination resistors. On-chip termination simplifies board design by minimizing the number of external termination resistors required. Termination can be placed inside the package, eliminating small stubs that can still lead to reflections.
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–96 Chapter 2: Arria GX Architecture
I/O Structure
Arria GX devices provide two types of termination:
■
■
On-chip differential termination (R
D
OCT)
On-chip series termination (R
S
OCT)
lists the Arria GX OCT support per I/O bank.
Table 2–26. On-Chip Termination Support by I/O Banks
On-Chip Termination Support
Series termination
Differential termination
I/O Standard Support
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL
2.5-V LVCMOS
1.8-V LVTTL
1.8-V LVCMOS
1.5-V LVTTL
1.5-V LVCMOS
SSTL-2 class I and II
SSTL-18 class I
SSTL-18 class II
1.8-V HSTL class I
1.8-V HSTL class II
1.5-V HSTL class I
1.2-V HSTL
LVDS
HyperTransport technology
Top and Bottom Banks
(3, 4, 7, 8)
v v v v v v v v v v v v v v v
—
—
Left Bank (1, 2)
v v v v v v v v v v
— v
— v
— v v
Note to
(1) Clock pins CLK1 and CLK3, and pins FPLL[7..8]CLK do not support differential on-chip termination. Clock pins CLK0 and
CLK2
, do support differential on-chip termination. Clock pins in the top and bottom banks (CLK[4..7, 12..15]) do not support differential on-chip termination.
On-Chip Differential Termination (R
D
OCT)
Arria GX devices support internal differential termination with a nominal resistance value of 100 for LVDS input receiver buffers. LVPECL input signals (supported on clock pins only) require an external termination resistor. R
D
OCT is supported across the full range of supported differential data rates as shown in the High-Speed I/O
Specifications section of the
DC & Switching Characteristics
chapter.
f
For more information about R
D
OCT, refer to the
High-Speed Differential I/O Interfaces with DPA in Arria GX Devices
chapter.
f
For more information about tolerance specifications for R
D
OCT, refer to the
DC &
Switching Characteristics
chapter.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
I/O Structure
2–97
On-Chip Series Termination (R
S
OCT)
Arria GX devices support driver impedance matching to provide the I/O driver with controlled output impedance that closely matches the impedance of the transmission line. As a result, reflections can be significantly reduced. Arria GX devices support
R
S
OCT for single-ended I/O standards with typical R
S
values of 25 and 50 Once matching impedance is selected, current drive strength is no longer selectable.
shows the list of output standards that support R
S
OCT.
f
For more information about R
S
OCT supported by Arria GX devices, refer to the
Selectable I/O Standards in Arria GX Devices
chapter.
f
For more information about tolerance specifications for OCT without calibration, refer to the
DC & Switching Characteristics
chapter.
MultiVolt I/O Interface
The Arria GX architecture supports the MultiVolt I/O interface feature that allows
Arria GX devices in all packages to interface with systems of different supply voltages. Arria GX VCCINT pins must always be connected to a 1.2-V power supply.
With a 1.2-V V
CCINT
level, input pins are 1.2-, 1.5-, 1.8-, 2.5-, and 3.3-V tolerant. The
VCCIO
pins can be connected to either a 1.2-, 1.5-, 1.8-, 2.5-, or 3.3-V power supply, depending on the output requirements. The output levels are compatible with systems of the same voltage as the power supply (for example, when VCCIO pins are connected to a 1.5-V power supply, the output levels are compatible with 1.5-V systems). Arria GX VCCPD power pins must be connected to a 3.3-V power supply.
These power pins are used to supply the pre-driver power to the output buffers, which increases the performance of the output pins. The VCCPD pins also power configuration input pins and JTAG input pins.
lists Arria GX MultiVolt I/O support.
Table 2–27. Arria GX MultiVolt I/O Support
Input Signal (V) Output Signal (V)
V
CCIO
(V)
1.2
1.5
1.8
2.5
3.3
1.2
1.5
1.8
2.5
3.3
5.0
1.2
1.5
1.8
2.5
3.3
v
v
v
v
v
v v
—
— v v
—
— v v v v
v v
v v v v v
v v
— v
—
— v v
—
—
— v v
v
v
v
—
—
—
— v
—
—
—
— v
(1) To drive inputs higher than V
C C IO
but less than 4.0 V, disable the PCI clamping diode and select the Allow LVTTL and LVCMOS input levels to
overdrive input buffer option in the Quartus II software.
(2) The pin current may be slightly higher than the default value. You must verify that the driving device’s V
O L not violate the applicable Arria GX V
I L
maximum and V
I H
minimum voltage specifications.
maximum and V
O H
minimum voltages do
(3) Although V
CC I O
specifies the voltage necessary for the Arria GX device to drive out, a receiving device powered at a different level can still interface with the Arria GX device if it has inputs that tolerate the V
C C I O
value.
(4) Arria GX devices support 1.2-V HSTL. They do not support 1.2-V LVTTL and 1.2-V LVCMOS.
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–98 Chapter 2: Arria GX Architecture
I/O Structure
The TDO and nCEO pins are powered by V
CCIO
of the bank that they reside. TDO is in
I/O bank 4 and nCEO is in I/O Bank 7. Ideally, the V
CC
supplies for the I/O buffers of any two connected pins are at the same voltage level. This may not always be possible depending on the V
CCIO
level of TDO and nCEO pins on master devices and the configuration voltage level chosen by V
CCSEL
on slave devices. Master and slave devices can be in any position in the chain. The master device indicates that it is driving out TDO or nCEO to a slave device. For multi-device passive configuration schemes, the nCEO pin of the master device drives the nCE pin of the slave device. The
VCCSEL
pin on the slave device selects which input buffer is used for nCE. When
V
CCSEL
is logic high, it selects the 1.8-V/1.5-V buffer powered by V
CCIO
. When V
CCSEL
is logic low, it selects the 3.3-V/2.5-V input buffer powered by V
CCPD
. The ideal case is to have the V
CC IO
of the nCEO bank in a master device match the V
CCSEL
settings for the nCE
input buffer of the slave device it is connected to, but that may not be possible depending on the application.
Table 2–28 contains board design recommendations to ensure that nCEO can
successfully drive nCE for all power supply combinations.
Table 2–28. Board Design Recommendations for nCEO and nCE Input Buffer Power
nCE Input Buffer Power in I/O Bank 3
VCCSEL
high
(V
CC I O
Bank 3 = 1.5 V)
VCCSEL
high
(V
CC I O
Bank 3 = 1.8 V)
VCCSEL
low (nCE powered by
V
C C P D
= 3.3 V)
V
C C I O
= 3.3 V
v v
v
V
Arria GX nCEO V
CCIO
Voltage Level in I/O Bank 7
C C I O
v v v
= 2.5 V
,
V
C C I O
v v
= 1.8 V
v
V
C C I O
= 1.5 V
v
Level shifter required v
(1) Input buffer is 3.3-V tolerant.
(2) The nCEO output buffer meets V
O H
(MIN) = 2.4 V.
(3) Input buffer is 2.5-V tolerant.
(4) The nCEO output buffer meets V
O H
(MIN) = 2.0 V.
(5) Input buffer is 1.8-V tolerant.
(6) An external 250-
pull-up resistor is not required, but recommended if signal levels on the board are not optimal.
V
C C I O
= 1.2 V
v
Level shifter required
Level shifter required
For JTAG chains, the TDO pin of the first device drives the TDI pin of the second device in the chain. The V
CCSEL
input on JTAG input I/O cells (TCK, TMS, TDI, and
TRST
) is internally hardwired to GND selecting the 3.3-V/2.5-V input buffer powered by V
CCPD
. The ideal case is to have the V
CCIO
of the TDO bank from the first device to match the V
CCSEL
settings for TDI on the second device, but that may not be possible depending on the application.
Table 2–29 contains board design recommendations to
ensure proper JTAG chain operation.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
High-Speed Differential I/O with DPA Support
2–99
Table 2–29. Supported TDO/TDI Voltage Combinations
Arria GX TDO V
C C I O
Voltage Level in I/O Bank 4
Device
Arria GX
Non-Arria GX
TDI Input
Buffer Power
Always V
C C P D
(3.3 V)
VCC = 3.3 V
VCC = 2.5 V
VCC = 1.8 V
VCC = 1.5 V
V
C C I O
= 3.3 V V
C C I O
= 2.5 V V
C C I O
= 1.8 V V
C C I O
= 1.5 V V
C C I O
= 1.2 V
v
v
v
Level shifter required
Level shifter required v
v
v
Level shifter required
Level shifter required v
v
v
Level shifter required
Level shifter required v
v
v v
v
v
Level shifter required v
Level shifter required v
(1) The TDO output buffer meets V
OH
(MIN) = 2.4 V.
(2) The TDO output buffer meets V
OH
(MIN) = 2.0 V.
(3) An external 250-
pull-up resistor is not required, but recommended if signal levels on the board are not optimal.
(4) Input buffer must be 3.3-V tolerant.
(5) Input buffer must be 2.5-V tolerant.
(6) Input buffer must be 1.8-V tolerant.
High-Speed Differential I/O with DPA Support
■
■
Arria GX devices contain dedicated circuitry for supporting differential standards at speeds up to 840 Mbps. LVDS differential I/O standards are supported in the Arria
GX device. In addition, the LVPECL I/O standard is supported on input and output clock pins on the top and bottom I/O banks.
The high-speed differential I/O circuitry supports the following high-speed I/O interconnect standards and applications:
SPI-4 Phase 2 (POS-PHY Level 4)
SFI-4
■ Parallel RapidIO standard
There are two dedicated high-speed PLLs (PLL1 and PLL2) in the EP1AGX20 and
EP1AGX35 devices and up to four dedicated high-speed PLLs (PLL1, PLL2, PLL7, and PLL8) in the EP1AGX50, EP1AGX60, and EP1AGX90 devices to multiply reference clocks and drive high-speed differential SERDES channels in I/O banks 1 and 2.
through
list the number of channels that each fast PLL can clock
in each of the Arria GX devices. In Table 2–30
through Table 2–34 the first row for each
transmitter or receiver provides the maximum number of channels that each fast PLL can drive in its adjacent I/O bank (I/O Bank 1 or I/O Bank 2). The second row shows the maximum number of channels that each fast PLL can drive in both I/O banks
(I/O Bank 1 and I/O Bank 2). For example, in the 780-pin FineLine BGA EP1AGX20
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–100 Chapter 2: Arria GX Architecture
High-Speed Differential I/O with DPA Support device, PLL 1 can drive a maximum of 16 transmitter channels in I/O Bank 2 or a maximum of 29 transmitter channels in I/O Banks 1 and 2. The Quartus II software can also merge receiver and transmitter PLLs when a receiver is driving a transmitter.
In this case, one fast PLL can drive both the maximum numbers of receiver and transmitter channels.
1
For more information, refer to the “Differential Pin Placement Guidelines” section in the
High-Speed Differential I/O Interfaces with DPA in Arria GX Devices
chapter.
Table 2–30. EP1AGX20 Device Differential Channels
Center Fast PLLs
Package Transmitter/Receiver Total Channels
PLL1 PLL2
Transmitter 29
16
13
13
16
484-pin FineLine BGA
Receiver
Transmitter
31
29
17
14
16
13
780-pin FineLine GBA
Receiver 31
17
14
14
17
Note to
(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels.
14
17
13
16
Table 2–31. EP1AGX35 Device Differential Channels
Center Fast PLLs
Package Transmitter/Receiver Total Channels
484-pin FineLine BGA
780-pin FineLine BGA
Transmitter
Receiver
Transmitter
Receiver
29
31
29
31
PLL1
16
13
17
14
16
13
17
14
PLL2
Note to
(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels.
13
16
14
17
13
16
14
17
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
High-Speed Differential I/O with DPA Support
Table 2–32. EP1AGX50 Device Differential Channels
Package
Transmitter/
Receiver
Total Channels
Center Fast PLLs Corner Fast PLLs
PLL1 PLL2 PLL7 PLL8
484-pin
FineLine BGA
780-pin
FineLine BGA
Transmitter
Receiver
Transmitter
Receiver
29
31
29
31
14
16
13
17
16
13
17
17
13
16
14
13
16
14
—
—
—
—
—
—
—
1,152-pin
FineLine BGA
Transmitter
Receiver
42
42
14
21
21
21
17
21
21
21
—
21
—
21
21 21 —
Note to
(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels.
—
—
21
—
21
—
—
—
—
—
—
—
Table 2–33. EP1AGX60 Device Differential Channels
Package
484-pin
FineLine BGA
780-pin
FineLine BGA
Transmitter/
Receiver
Total Channels
Center Fast PLLs Corner Fast PLLs
Transmitter
Receiver
Transmitter
Receiver
29
31
29
31
PLL1
16
13
17
14
21
13
17
14
16
PLL2
13
16
14
17
21
16
14
17
13
PLL7
—
—
—
—
21
—
—
—
—
Transmitter 42
1,152-pin
FineLine BGA
Receiver 42
21
21
21
21
21
21
—
21
—
Note to
(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels.
—
21
—
PLL8
—
—
—
—
21
—
—
—
—
2–101
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–102 Chapter 2: Arria GX Architecture
High-Speed Differential I/O with DPA Support
Table 2–34. EP1AGX90 Device Differential Channels
Center Fast PLLs
Corner Fast
PLLs
Package Transmitter/Receiver Total Channels
1,152-pin FineLine
BGA
Transmitter
Receiver
45
47
PLL1
23
22
23
24
PLL2
22
23
24
23
PLL7
Note to
(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels.
23
—
23
—
Dedicated Circuitry with DPA Support
Arria GX devices support source-synchronous interfacing with LVDS signaling at up to 840 Mbps. Arria GX devices can transmit or receive serial channels along with a low-speed or high-speed clock.
The receiving device PLL multiplies the clock by an integer factor W = 1 through 32.
The SERDES factor J determines the parallel data width to deserialize from receivers or to serialize for transmitters. The SERDES factor J can be set to 4, 5, 6, 7, 8, 9, or 10 and does not have to equal the PLL clock-multiplication W value. A design using the dynamic phase aligner also supports all of these J factor values. For a J factor of 1, the
Arria GX device bypasses the SERDES block. For a J factor of 2, the Arria GX device bypasses the SERDES block, and the DDR input and output registers are used in the
IOE.
shows the block diagram of the Arria GX transmitter channel.
Figure 2–79. Arria GX Transmitter Channel
Data from R4, R24, C4, or direct link interconnect
+
–
Up to 840 Mbps
10
10
Local
Interconnect
Dedicated
Transmitter
Interface
refclk
Fast
PLL diffioclk load_en
Regional or global clock
Each Arria GX receiver channel features a DPA block for phase detection and selection, a SERDES, a synchronizer, and a data realigner circuit. You can bypass the dynamic phase aligner without affecting the basic source-synchronous operation of the channel. In addition, you can dynamically switch between using the DPA block or bypassing the block via a control signal from the logic array.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
High-Speed Differential I/O with DPA Support
2–103
Figure 2–80 shows the block diagram of the Arria GX receiver channel.
Figure 2–80. GX Receiver Channel
Data to R4, R24, C4, or direct link interconnect
Up to 840 Mbps
+
–
D Q
Data Realignment
Circuitry
10
Eight Phase Clocks
data retimed_data
DPA
DPA_clk
8 refclk
Fast
PLL
Synchronizer diffioclk load_en
Dedicated
Receiver
Interface
Regional or global clock
An external pin or global or regional clock can drive the fast PLLs, which can output up to three clocks: two multiplied high-speed clocks to drive the SERDES block and/or external pin, and a low-speed clock to drive the logic array. In addition, eight phase-shifted clocks from the V
CO
can feed to the DPA circuitry. f
For more information about fast PLL, refer to the PLLs in Arria GX Devices chapter.
The eight phase-shifted clocks from the fast PLL feed to the DPA block. The DPA block selects the closest phase to the center of the serial data eye to sample the incoming data. This allows the source-synchronous circuitry to capture incoming data correctly regardless of channel-to-channel or clock-to-channel skew. The DPA block locks to a phase closest to the serial data phase. The phase-aligned DPA clock is used to write the data into the synchronizer.
The synchronizer sits between the DPA block and the data realignment and SERDES circuitry. Because every channel using the DPA block can have a different phase selected to sample the data, the synchronizer is needed to synchronize the data to the high-speed clock domain of the data realignment and the SERDES circuitry.
For high-speed source-synchronous interfaces such as POS-PHY 4 and the Parallel
RapidIO standard, the source synchronous clock rate is not a byte- or SERDES-rate multiple of the data rate. Byte alignment is necessary for these protocols because the source synchronous clock does not provide a byte or word boundary as the clock is one half the data rate, not one eighth. The Arria GX device’s high-speed differential
I/O circuitry provides dedicated data realignment circuitry for user-controlled byte boundary shifting. This simplifies designs while saving ALM resources. You can use an ALM-based state machine to signal the shift of receiver byte boundaries until a specified pattern is detected to indicate byte alignment.
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–104 Chapter 2: Arria GX Architecture
High-Speed Differential I/O with DPA Support
Fast PLL and Channel Layout
The receiver and transmitter channels are interleaved as such that each I/O bank on the left side of the device has one receiver channel and one transmitter channel per
LAB row. Figure 2–81 shows the fast PLL and channel layout in the EP1AGX20C,
EP1AGX35C/D, EP1AGX50C/D and EP1AGX60C/D devices. Figure 2–82 shows the
fast PLL and channel layout in EP1AGX60E and EP1AGX90E devices.
Figure 2–81. Fast PLL and Channel Layout in EP1AGX20C, EP1AGX35C/D, EP1AGX50C/D, EP1AGX60C/D Devices
4
LVDS
Clock
DPA
Clock
Quadrant Quadrant
4
2
Fast
PLL 1
Fast
PLL 2
2
LVDS
Clock
DPA
Clock
4
Note to
:
(1) For the number of channels each device supports, refer to Table 2–30 .
Quadrant Quadrant
Figure 2–82. Fast PLL and Channel Layout in EP1AGX60E and EP1AGX90E Devices
Fast
PLL 7
2
4
LVDS
Clock
DPA
Clock
Quadrant Quadrant
4
2
Fast
PLL 1
Fast
PLL 2
2
4
LVDS
Clock
DPA
Clock
Quadrant
2
Fast
PLL 8
Note to
:
(1) For the number of channels each device supports, refer to Table 2–30
.
Quadrant
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 2: Arria GX Architecture
Document Revision History
Document Revision History
shows the revision history for this chapter.
Table 2–35. Document Revision History
Date and Document Version
December 2009, v2.0
May 2008, v1.3
August 2007, v1.2
June 2007, v1.1
May 2007 v1.0
Changes Made
■
Document template update.
■
Minor text edits.
Added “Reverse Serial Pre-CDR Loopback” and “Calibration Block” sub-sections to
“Transmitter Path” section.
Added “Referenced Documents” section.
Added GIGE information.
Initial release.
Summary of Changes
—
—
—
—
—
2–105
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
2–106 Chapter 2: Arria GX Architecture
Document Revision History
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
3. Configuration and Testing
AGX51003-2.0
Introduction
All Arria
®
GX devices provide JTAG boundary-scan test (BST) circuitry that complies with the IEEE Std. 1149.1. You can perform JTAG boundary-scan testing either before or after, but not during configuration. Arria GX devices can also use the JTAG port for configuration with the Quartus
®
II software or hardware using either jam files (.jam) or jam byte-code files (.jbc).
■
■
■
■
This chapter contains the following sections:
“IEEE Std. 1149.1 JTAG Boundary-Scan Support”
“SignalTap II Embedded Logic Analyzer” on page 3–3
“Automated Single Event Upset (SEU) Detection” on page 3–8
IEEE Std. 1149.1 JTAG Boundary-Scan Support
Arria GX devices support I/O element (IOE) standard setting reconfiguration through the JTAG BST chain. The JTAG chain can update the I/O standard for all input and output pins any time before or during user-mode through the CONFIG_IO instruction. You can use this capability for JTAG testing before configuration when some of the Arria GX pins drive or receive from other devices on the board using voltage-referenced standards. Because the Arria GX device may not be configured before JTAG testing, the I/O pins may not be configured for appropriate electrical standards for chip-to-chip communication. Programming these I/O standards via
JTAG allows you to fully test the I/O connections to other devices.
A device operating in JTAG mode uses four required pins, TDI, TDO, TMS, and TCK, and one optional pin, TRST. The TCK pin has an internal weak pull-down resistor, while the TDI, TMS, and TRST pins have weak internal pull-up resistors. The JTAG input pins are powered by the 3.3-V V
CCPD
pins. The TDO output pin is powered by the
V
CCIO
power supply in I/O bank 4.
Arria GX devices also use the JTAG port to monitor the logic operation of the device with the SignalTap
®
II embedded logic analyzer. Arria GX devices support the JTAG instructions shown in
1
Arria GX, Cyclone ® II, Cyclone, Stratix ® , Stratix II, Stratix GX , and Stratix II GX devices must be within the first 17 devices in a JTAG chain. All of these devices have the same JTAG controller. If any of the Stratix, Arria GX, Cyclone, and Cyclone II devices are in the 18th or further position, they will fail configuration. This does not affect the functionality of the SignalTap ® II embedded logic analyzer.
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
3–2 Chapter 3: Configuration and Testing
IEEE Std. 1149.1 JTAG Boundary-Scan Support
Table 3–1. Arria GX JTAG Instructions
JTAG Instruction Instruction Code Description
SAMPLE/PRELOAD
EXTEST
BYPASS
USERCODE
IDCODE
00 0000 0101
00 0000 1111
11 1111 1111
00 0000 0111
00 0000 0110
Allows a snapshot of signals at the device pins to be captured and examined during normal device operation and permits an initial data pattern to be output at the device pins. Also used by the SignalTap II embedded logic analyzer.
Allows external circuitry and board-level interconnects to be tested by forcing a test pattern at the output pins and capturing test results at the input pins.
Places the 1-bit bypass register between the
TDI
and
TDO
pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation.
Selects the 32-bit
USERCODE
register and places it between the
TDI
and
TDO
pins, allowing the
USERCODE
to be serially shifted out of
TDO
.
Selects the
IDCODE
register and places it between
TDI
and
TDO
, allowing
IDCODE
to be serially shifted out of
TDO
.
ICR instructions
PULSE_NCONFIG
CONFIG_IO
00 0000 1011
00 0000 1010
—
00 0000 0001
00 0000 1101
Places the 1-bit bypass register between the
TDI
and
TDO
pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation, while tri-stating all of the I/O pins.
Places the 1-bit bypass register between the
TDI
and
TDO
pins, which allows the BST data to pass synchronously through selected devices to adjacent devices during normal device operation while holding I/O pins to a state defined by the data in the boundary-scan register.
Used when configuring an Arria GX device via the JTAG port with a USB-Blaster
TM
, MasterBlaster
TM
, ByteBlasterMV
TM
,
EthernetBlaster
TM
, or ByteBlaster II download cable, or when using a .jam or .jbc via an embedded processor or JRunner
TM
.
Emulates pulsing the nCONFIG pin low to trigger reconfiguration even though the physical pin is unaffected.
Allows configuration of I/O standards through the JTAG chain for
JTAG testing. Can be executed before, during, or after configuration. Stops configuration if executed during configuration. Once issued, the CONFIG_IO instruction holds nSTATUS
low to reset the configuration device. nSTATUS is held low until the IOE configuration register is loaded and the
TAP controller state machine transitions to the UPDATE_DR state.
(1) Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.
(2) For more information about using the CONFIG_IO instruction, refer to the
MorphIO: An I/O Reconfiguration Solution for Altera Devices
White Paper.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 3: Configuration and Testing
SignalTap II Embedded Logic Analyzer
3–3
The Arria GX device instruction register length is 10 bits and the USERCODE register
length is 32 bits. Table 3–2 and Table 3–3
show the boundary-scan register length and device IDCODE information for Arria GX devices.
Table 3–2. Arria GX Boundary-Scan Register Length
Device Boundary-Scan Register Length
EP1AGX20 1320
EP1AGX35 1320
EP1AGX50 1668
EP1AGX60
EP1AGX90
1668
2016
Table 3–3. 2-Bit Arria GX Device IDCODE
Device
EP1AGX20
EP1AGX35
EP1AGX50
EP1AGX60
EP1AGX90
Version (4 Bits)
0000
0000
0000
0000
0000
IDCODE (32 Bits)
Part Number (16 Bits)
0010 0001 0010 0001
0010 0001 0010 0001
0010 0001 0010 0010
0010 0001 0010 0010
0010 0001 0010 0011
Manufacturer Identity
(11 Bits)
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
000 0110 1110
LSB (1 Bit)
1
1
1
1
1
SignalTap II Embedded Logic Analyzer
Arria GX devices feature the SignalTap II embedded logic analyzer, which monitors design operation over a period of time through the IEEE Std. 1149.1 (JTAG) circuitry.
You can analyze internal logic at speed without bringing internal signals to the I/O pins. This feature is particularly important for advanced packages, such as FineLine
BGA (FBGA) packages, because it can be difficult to add a connection to a pin during the debugging process after a board is designed and manufactured.
Configuration
The logic, circuitry, and interconnects in the Arria GX architecture are configured with
CMOS SRAM elements. Altera ® FPGAs are reconfigurable and every device is tested with a high coverage production test program so you do not have to perform fault testing and can instead focus on simulation and design verification.
Arria GX devices are configured at system power up with data stored in an Altera configuration device or provided by an external controller (for example, a MAX ® II device or microprocessor). You can configure Arria GX devices using the fast passive parallel (FPP), active serial (AS), passive serial (PS), passive parallel asynchronous
(PPA), and JTAG configuration schemes. Each Arria GX device has an optimized interface that allows microprocessors to configure it serially or in parallel, and synchronously or asynchronously. The interface also enables microprocessors to treat
Arria GX devices as memory and configure them by writing to a virtual memory location, making reconfiguration easy.
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
3–4 Chapter 3: Configuration and Testing
Configuration
In addition to the number of configuration methods supported, Arria GX devices also offer decompression and remote system upgrade features. The decompression feature allows Arria GX FPGAs to receive a compressed configuration bitstream and decompress this data in real-time, reducing storage requirements and configuration time. The remote system upgrade feature allows real-time system upgrades from remote locations of Arria GX designs. For more information, refer to
.
Operating Modes
The Arria GX architecture uses SRAM configuration elements that require configuration data to be loaded each time the circuit powers up. The process of physically loading the SRAM data into the device is called configuration. During initialization, which occurs immediately after configuration, the device resets registers, enables I/O pins, and begins to operate as a logic device. The I/O pins are tri-stated during power up, and before and during configuration. Together, the configuration and initialization processes are called command mode. Normal device operation is called user mode.
SRAM configuration elements allow you to reconfigure Arria GX devices in-circuit by loading new configuration data into the device. With real-time reconfiguration, the device is forced into command mode with a device pin. The configuration process loads different configuration data, re-initializes the device, and resumes user-mode operation. You can perform in-field upgrades by distributing new configuration files either within the system or remotely.
PORSEL
is a dedicated input pin used to select power-on reset (POR) delay times of
12 ms or 100 ms during power up. When the PORSEL pin is connected to ground, the
POR time is 100 ms. When the PORSEL pin is connected to V
CC
, the POR time is 12 ms.
The nIO_PULLUP pin is a dedicated input that chooses whether the internal pull-up resistors on the user I/O pins and dual-purpose configuration I/O pins (nCSO, ASDO,
DATA[7..0]
, nWS, nRS, RDYnBSY, nCS, CS, RUnLU, PGM[2..0], CLKUSR,
INIT_DONE
, DEV_OE, DEV_CLR) are on or off before and during configuration. A logic high (1.5, 1.8, 2.5, 3.3 V) turns off the weak internal pull-up resistors, while a logic low turns them on.
Arria GX devices also offer a new power supply, V
C CPD
, which must be connected to
3.3 V in order to power the 3.3-V/2.5-V buffer available on the configuration input pins and JTAG pins. V
CCPD
applies to all the JTAG input pins (TCK, TMS, TDI, and
TRST
) and the following configuration pins: nCONFIG, DCLK (when used as an input), nIO_PULLUP
, DATA[7..0], RUnLU, nCE, nWS, nRS, CS, nCS, and CLKUSR. The V
CCSEL pin allows the V
CCIO
setting (of the banks where the configuration inputs reside) to be independent of the voltage required by the configuration inputs. Therefore, when selecting the V
CCIO
voltage, you do not have to take the VIL and VIH levels driven to the configuration inputs into consideration. The configuration input pins, nCONFIG,
DCLK
(when used as an input), nIO_PULLUP, RUnLU, nCE, nWS, nRS, CS, nCS, and
CLKUSR
, have a dual buffer design: a 3.3-V/2.5-V input buffer and a 1.8-V/1.5-V input buffer. The V
CCSEL
input pin selects which input buffer is used. The 3.3-V/2.5-V input buffer is powered by V
CCPD
, while the 1.8-V/1.5-V input buffer is powered by
V
CCIO
.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 3: Configuration and Testing
Configuration
3–5
V
CCSEL
is sampled during power up. Therefore, the V
CCSEL
setting cannot change on-the-fly or during a reconfiguration. The V
CCSEL
input buffer is powered by V
CCINT and must be hard-wired to V
C CPD
or ground. A logic high V
CC SEL
connection selects the
1.8-V/1.5-V input buffer, and a logic low selects the 3.3-V/2.5-V input buffer. V
CCSEL should be set to comply with the logic levels driven out of the configuration device or
MAX II microprocessor.
If the design must support configuration input voltages of 3.3 V/2.5 V, set V
CCSEL
to a logic low. You can set the V
CCIO
voltage of the I/O bank that contains the configuration inputs to any supported voltage. If the design must support configuration input voltages of 1.8 V/1.5 V, set V
CCSEL
to a logic high and the V
CCIO contains the configuration inputs to 1.8 V/1.5 V.
of the bank that f
For more information about multi-volt support, including information about using
TDO
and nCEO in multi-volt systems, refer to the
Arria GX Architecture
chapter.
Configuration Schemes
You can load the configuration data for an Arria GX device with one of five
configuration schemes (refer to Table 3–4 ), chosen on the basis of the target
application. You can use a configuration device, intelligent controller, or the JTAG port to configure an Arria GX device. A configuration device can automatically configure an Arria GX device at system power up.
You can configure multiple Arria GX devices in any of the five configuration schemes by connecting the configuration enable (nCE) and configuration enable output (nCEO) pins on each device. Arria GX FPGAs offer the following:
■
■
Configuration data decompression to reduce configuration file storage
Remote system upgrades for remotely updating Arria GX designs
Table 3–4 lists which configuration features can be used in each configuration scheme.
f
For more information about configuration schemes in Arria GX devices, refer to the
Configuring Arria GX Devices
chapter.
Table 3–4. Arria GX Configuration Features (Part 1 of 2)
Configuration Scheme
FPP
AS
PS
PPA
Configuration Method
MAX II device or microprocessor and flash device
Enhanced configuration device
Serial configuration device
MAX II device or microprocessor and flash device
Enhanced configuration device
Download cable
MAX II device or microprocessor and flash device
Decompression
v
v v v v
—
Remote System Upgrade
v v v
v v
— v
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
3–6 Chapter 3: Configuration and Testing
Configuration
Table 3–4. Arria GX Configuration Features (Part 2 of 2)
Configuration Scheme Configuration Method Decompression Remote System Upgrade
JTAG
Download cable
MAX II device or microprocessor and flash device
—
—
—
—
(1) In these modes, the host system must send a
DCLK
that is 4× the data rate.
(2) The enhanced configuration device decompression feature is available, while the Arria GX decompression feature is not available.
(3) Only remote update mode is supported when using the AS configuration scheme. Local update mode is not supported.
(4) The supported download cables include the Altera USB-Blaster universal serial bus (USB) port download cable, MasterBlaster
™
serial/USB communications cable, ByteBlaster II parallel port download cable, ByteBlasterMV parallel port download cable, and the EthernetBlaster download cable.
Device Configuration Data Decompression
Arria GX FPGAs support decompression of configuration data, which saves configuration memory space and time. This feature allows you to store compressed configuration data in configuration devices or other memory and transmit this compressed bitstream to Arria GX FPGAs. During configuration, the Arria GX FPGA decompresses the bitstream in real time and programs its SRAM cells. Arria GX
FPGAs support decompression in the FPP (when using a MAX II device or microprocessor and flash memory), AS, and PS configuration schemes.
Decompression is not supported in the PPA configuration scheme nor in JTAG-based configuration.
Remote System Upgrades
Shortened design cycles, evolving standards, and system deployments in remote locations are difficult challenges faced by system designers. Arria GX devices can help effectively deal with these challenges with their inherent re programmability and dedicated circuitry to perform remote system updates. Remote system updates help deliver feature enhancements and bug fixes without costly recalls, reduce time to market, and extend product life.
Arria GX FPGAs feature dedicated remote system upgrade circuitry to facilitate remote system updates. Soft logic (Nios ® processor or user logic) implemented in the
Arria GX device can download a new configuration image from a remote location, store it in configuration memory, and direct the dedicated remote system upgrade circuitry to initiate a reconfiguration cycle. The dedicated circuitry performs error detection during and after the configuration process, recovers from any error condition by reverting back to a safe configuration image, and provides error status information. This dedicated remote system upgrade circuitry avoids system downtime and is the critical component for successful remote system upgrades.
Remote system configuration is supported in the following Arria GX configuration schemes: FPP, AS, PS, and PPA. You can also implement remote system configuration in conjunction with Arria GX features such as real-time decompression of configuration data for efficient field upgrades.
f
For more information about remote configuration in Arria GX devices, refer to the
Remote System Upgrades with Arria GX Devices
chapter.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 3: Configuration and Testing
Configuration
3–7
Configuring Arria GX FPGAs with JRunner
The JRunner software driver configures Altera FPGAs, including Arria GX FPGAs, through the ByteBlaster
™
II or ByteBlasterMV cables in JTAG mode. The programming input file supported is in Raw Binary File (.rbf) format. JRunner also requires a Chain Description File (.cdf) generated by the Quartus II software. JRunner is targeted for embedded JTAG configuration. The source code is developed for the
Windows NT operating system (OS), but can be customized to run on other platforms. f
For more information about the JRunner software driver, refer to the
AN414: JRunner
Software Driver: An Embedded Solution for PLD JTAG Configuration
and the source files on the Altera website .
Programming Serial Configuration Devices with SRunner
You can program a serial configuration device in-system by an external microprocessor using SRunner TM . SRunner is a software driver developed for embedded serial configuration device programming that can be easily customized to fit into different embedded systems. SRunner software driver reads a raw programming data file (.rpd) and writes to serial configuration devices. The serial configuration device programming time using SRunner software driver is comparable to the programming time when using the Quartus II software.
f
For more information about SRunner, refer to the
AN418: SRunner: An Embedded
Solution for Serial Configuration Device Programming
and the source code on the Altera website .
f
For more information about programming serial configuration devices, refer to the
Serial Configuration Devices (EPCS1, EPCS4, EPCS64, and EPCS128) Data Sheet
in the
Configuration Handbook.
Configuring Arria GX FPGAs with the MicroBlaster Driver
The MicroBlaster ™ software driver supports a raw binary file (RBF) programming input file and is ideal for embedded FPP or PS configuration. The source code is developed for the Windows NT operating system, although it can be customized to run on other operating systems. f
For more information about the MicroBlaster software driver, refer to the
Configuring the MicroBlaster Fast Passive Parallel Software Driver
White Paper or the
AN423:
Configuring the MicroBlaster Passive Serial Software Driver
.
PLL Reconfiguration
The phase-locked loops (PLLs) in the Arria GX device family support reconfiguration of their multiply, divide, VCO-phase selection, and bandwidth selection settings without reconfiguring the entire device. You can use either serial data from the logic array or regular I/O pins to program the PLL’s counter settings in a serial chain. This option provides considerable flexibility for frequency synthesis, allowing real-time variation of the PLL frequency and delay. The rest of the device is functional while reconfiguring the PLL.
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
3–8 Chapter 3: Configuration and Testing
Automated Single Event Upset (SEU) Detection f
For more information about Arria GX PLLs, refer to the
PLLs in Arria GX Devices
chapter.
Automated Single Event Upset (SEU) Detection
Arria GX devices offer on-chip circuitry for automated checking of single event upset
(SEU) detection. Some applications that require the device to operate error free at high elevations or in close proximity to Earth’s North or South Pole requires periodic checks to ensure continued data integrity. The error detection cyclic redundancy check (CRC) feature controlled by the Device and Pin Options dialog box in the
Quartus II software uses a 32-bit CRC circuit to ensure data reliability and is one of the best options for mitigating SEU.
You can implement the error detection CRC feature with existing circuitry in Arria GX devices, eliminating the need for external logic. Arria GX devices compute CRC during configuration. The Arria GX device checks the computed-CRC against an automatically computed CRC during normal operation. The CRC_ERROR pin reports a soft error when configuration SRAM data is corrupted, triggering device reconfiguration.
Custom-Built Circuitry
Dedicated circuitry is built into Arria GX devices to automatically perform error detection. This circuitry constantly checks for errors in the configuration SRAM cells while the device is in user mode. You can monitor one external pin for the error and use it to trigger a reconfiguration cycle. You can select the desired time between checks by adjusting a built-in clock divider.
Software Interface
Beginning with version 7.1 of the Quartus II software, you can turn on the automated error detection CRC feature in the Device and Pin Options dialog box. This dialog box allows you to enable the feature and set the internal frequency of the CRC between 400 kHz to 50 MHz. This controls the rate that the CRC circuitry verifies the internal configuration SRAM bits in the Arria GX FPGA.
f
For more information about CRC, refer to
AN 357: Error Detection Using CRC in Altera
FPGAs
.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 3: Configuration and Testing
Document Revision History
Document Revision History
Table 3–5 lists the revision history for this chapter.
Table 3–5. Document Revision History
Date and Document Version
December 2009, v2.0
May 2009 v1.4
May 2008 v1.3
Changes Made
■
■
Document template update.
Minor text edits.
■
Removed “Temperature Sensing
Diode” section.
■
Updated Table 3–1 and Table 3–4.
Updated note in “Introduction” section.
Minor text edits.
Added the “Referenced Documents” section.
August 2007 v1.2
June 2007 v1.1
May 2007 v1.0
Deleted Signal Tap II information from Table 3–1.
Initial Release
Summary of Changes
—
—
—
—
—
—
3–9
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
3–10 Chapter 3: Configuration and Testing
Document Revision History
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
4. DC and Switching Characteristics
AGX51004-2.0
Operating Conditions
Arria ® GX devices are offered in both commercial and industrial grades. Both commercial and industrial devices are offered in –6 speed grade only.
■
■
■
■
■
■
■
■
■
■
■
■
This chapter contains the following sections:
“Power Consumption” on page 4–25
“I/O Timing Model” on page 4–26
“Typical Design Performance” on page 4–32
“Block Performance” on page 4–84
“IOE Programmable Delay” on page 4–86
“Maximum Input and Output Clock Toggle Rate” on page 4–87
“Duty Cycle Distortion” on page 4–95
“High-Speed I/O Specifications” on page 4–100
“PLL Timing Specifications” on page 4–103
“External Memory Interface Specifications” on page 4–105
“JTAG Timing Specifications” on page 4–106
through Table 4–42 on page 4–25
provide information on absolute maximum ratings, recommended operating conditions, DC electrical characteristics, and other specifications for Arria GX devices.
Absolute Maximum Ratings
Table 4–1 contains the absolute maximum ratings for the Arria GX device family.
Table 4–1. Arria GX Device Absolute Maximum Ratings
,
,
(Part 1 of 2)
V
CCINT
V
CCIO
V
CCPD
V
I
I
OUT
T
STG
Symbol Parameter
Supply voltage
Supply voltage
Supply voltage
DC output current, per pin
Storage temperature No bias
Conditions
With respect to ground
With respect to ground
With respect to ground
—
—
Minimum
–0.5
–0.5
–0.5
–0.5
–25
–65
Maximum
1.8
4.6
4.6
4.6
40
150
Units
V
V
V
V mA
C
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–2 Chapter 4: DC and Switching Characteristics
Operating Conditions
Table 4–1. Arria GX Device Absolute Maximum Ratings
(Note 1)
,
(2)
,
(3)
(Part 2 of 2)
Symbol Parameter Conditions Minimum Maximum Units
T
J
Junction temperature BGA packages under bias –55 125 C
(1) For more information about operating requirements for Altera
®
devices, refer to the
Arria GX Device Family Data Sheet
chapter.
(2) Conditions beyond those listed in
ratings for extended periods of time may have adverse affects on the device.
(3) Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply.
(4) During transitions, the inputs may overshoot to the voltage shown in
Table 4–2 based upon the input duty cycle. The DC case is equivalent to
100% duty cycle. During transitions, the inputs may undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns.
Table 4–2. Maximum Duty Cycles in Voltage Transitions
Symbol Parameter Condition Maximum Duty Cycles (%)
V
I
Maximum duty cycles in voltage transitions
V
I
= 4.0 V
V
I
= 4.1 V
V
I
= 4.2 V
V
I
= 4.3 V
V
I
= 4.4 V
V
I
= 4.5 V
100
90
50
30
17
10
Note to
(1) During transition, the inputs may overshoot to the voltages shown based on the input duty cycle. The DC case is equivalent to 100% duty cycle.
Recommended Operating Conditions
Table 4–3 lists the recommended operating conditions for the Arria GX device family.
Table 4–3. Arria GX Device Recommended Operating Conditions (Part 1 of 2)
V
V
V
V
V
I
CCINT
CCIO
O
Symbol
CCPD
Parameter
Supply voltage for internal logic and input buffers
Supply voltage for output buffers, 3.3-V operation
Supply voltage for output buffers, 2.5-V operation
Supply voltage for output buffers, 1.8-V operation
Supply voltage for output buffers, 1.5-V operation
Supply voltage for output buffers, 1.2-V operation
Supply voltage for pre-drivers as well as configuration and
JTAG I/O buffers.
Input voltage
(refer to
Output voltage
Conditions
Rise time
100 ms
Rise time
Rise time
Rise time
Rise time
Rise time
100
100 ms
100 ms
100 ms
100 ms
100 ms
—
,
s rise time 100 ms
(Part 1 of 2)
Minimum
1.15
3.135
(3.00)
2.375
1.71
1.425
1.15
3.135
–0.5
0
Maximum
1.25
3.465
(3.60)
2.625
1.89
1.575
1.25
3.465
V
4.0
CCIO
Units
V
V
V
V
V
V
V
V
V
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Operating Conditions
4–3
Table 4–3. Arria GX Device Recommended Operating Conditions (Part 2 of 2)
(Note 1)
(Part 2 of 2)
Symbol Parameter Conditions Minimum Maximum Units
T
J
Operating junction temperature
For commercial use
For industrial use
0
–40
85
100
C
C
(1) Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply.
(2) During transitions, the inputs may overshoot to the voltage shown in Table 4–2
based upon the input duty cycle. The DC case is equivalent to
100% duty cycle. During transitions, the inputs may undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns.
(3) Maximum V
CC
rise time is 100 ms, and V
CC
must rise monotonically from ground to V
CC
.
(4) V
CCPD
must ramp-up from 0 V to 3.3 V within 100
s to 100 ms. If V not configure successfully. If the system does not allow for a V
CCPD
is not ramped up within this specified time, the Arria GX device will
CCPD
ramp-up time of 100 ms or less, hold nCONFIG low until all power supplies are reliable.
(5) All pins, including dedicated inputs, clock, I/O, and JTAG pins, can be driven before V
CCINT
, V
CCPD
, and V
CCIO
are powered.
(6) V
CCIO
maximum and minimum conditions for PCI and PCI-X are shown in parentheses.
Transceiver Block Characteristics
contain transceiver block specifications.
Table 4–4. Arria GX Transceiver Block Absolute Maximum Ratings
Symbol Parameter Conditions Minimum Maximum Units
V
CCA
V
CCP
V
CCR
V
CCT_B
Transceiver block supply voltage
Transceiver block supply voltage
Transceiver block supply voltage
Transceiver block supply voltage
Commercial and industrial
Commercial and industrial
Commercial and industrial
Commercial and industrial
–0.5
–0.5
–0.5
–0.5
4.6
1.8
1.8
1.8
V
CCL_B
V
CCH_B
Transceiver block supply voltage
Transceiver block supply voltage
Commercial and industrial
Commercial and industrial
–0.5
–0.5
1.8
2.4
Note to
(1) The device can tolerate prolonged operation at this absolute maximum, as long as the maximum specification is not violated.
V
V
V
V
V
V
Table 4–5. Arria GX Transceiver Block Operating Conditions
Symbol
V
CCA
V
CCP
V
CCR
V
CCT_B
V
CCL_B
Parameter
Transceiver block supply voltage
Transceiver block supply voltage
Transceiver block supply voltage
Transceiver block supply voltage
Transceiver block supply voltage
Conditions
Commercial and industrial
Commercial and industrial
Commercial and industrial
Commercial and industrial
Commercial and industrial
Minimum Typical Maximum Units
3.135
1.15
1.15
1.15
1.15
V
CCH_B
Transceiver block supply voltage Commercial and industrial
1.15
1.425
R
REFB
Reference resistor Commercial and industrial 2K - 1%
Note to
(1) The DC signal on this pin must be as clean as possible. Ensure that no noise is coupled to this pin.
3.3
1.2
1.2
1.2
1.2
1.2
1.5
2K
3.465
1.25
1.25
1.25
1.25
1.25
1.575
2K +1%
V
V
V
V
V
V
V
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–4 Chapter 4: DC and Switching Characteristics
Operating Conditions
Table 4–6. Arria GX Transceiver Block AC Specification (Part 1 of 3)
Symbol / Description Conditions
–6 Speed Grade Commercial and
Industrial
Min Typ Max
Reference clock
Input reference clock frequency
Absolute V
M A X
for a
REFCLK
Pin
Absolute V
MIN
for a
REFCLK
Pin
Rise/Fall time
Duty cycle
Peak to peak differential input voltage V
ID
(diff p-p)
Spread spectrum clocking
On-chip termination resistors
V
ICM
(AC coupled)
V
ICM
(DC coupled)
—
—
—
—
—
—
0 to –0.5%
—
—
PCI Express
(PIPE) mode
—
50
—
–0.3
—
45
200
30
0.25
—
—
—
0.2
—
—
—
115 ± 20%
1200 ± 5%
—
2000 +/-1%
622.08
3.3
—
—
55
2000
33
0.55
RREFB
Transceiver Clocks
Calibration block clock frequency
Calibration block minimum power-down pulse width fixedclk
clock frequency
reconfig
clock frequency
Transceiver block minimum power-down pulse width
Receiver
Data rate
Absolute V
MAX
for a receiver pin
Absolute V
MIN
for a receiver pin
Maximum peak-to-peak differential input voltage V
ID
(diff p-p)
Minimum peak-to-peak differential input voltage V
ID
(diff p-p)
On-chip termination resistors
—
—
—
SDI mode
—
—
—
—
Vicm = 0.85 V
DC Gain = 3 dB
10
30
2.5
100
600
—
–0.4
—
160
—
—
125 ±10%
—
—
—
—
—
—
—
125
—
50
—
3125
2.0
—
3.3
—
V
ICM
Bandwidth at 3.125 Gbps
—
Vicm = 0.85 V setting
Vicm = 1.2 V setting
BW = Low
BW = Med
BW = High
100±15%
850 ± 10% 850 ± 10% 850 ± 10%
1200 ±
10%
—
—
—
1200 ±
10%
30
40
50
1200 ±
10%
—
—
—
Units
MHz
MHz ns
MHz
MHz ns
Mbps
V
V
V mV
mV mV kHz
mV
V
MHz
V
V
UI
% mV
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Operating Conditions
4–5
Table 4–6. Arria GX Transceiver Block AC Specification (Part 2 of 3)
–6 Speed Grade Commercial and
Industrial
Symbol / Description Conditions
Bandwidth at 2.5 Gbps
Return loss differential mode
Return loss common mode
BW = Low
BW = Med
BW = High
50 MHz to 1.25
GHz
(PCI Express)
100 MHz to 2.5
GHz (XAUI)
50 MHz to 1.25
GHz
(PCI Express)
100 MHz to 2.5
GHz (XAUI)
—
Min
—
—
—
Typ
35
50
60
–10
–6
Max
—
—
—
Programmable PPM detector
Run length
Programmable equalization
CDR Minimum T1b
Data lock time from rx_freqlocked
,
Programmable DC gain
Transmitter Buffer
Output Common Mode voltage (V ocm
)
On-chip termination resistors
Return loss differential mode
—
—
—
—
—
—
—
—
—
—
50 MHz to 1.25
GHz (PCI Express)
312 MHz to 625
MHz (XAUI)
625 MHz to
3.125GHz (XAUI)
± 62.5, 100, 125, 200, 250, 300, 500,
1000
80
— —
65 —
—
15
—
—
0 100
5
175
75
—
4000
— —
0, 3, 6
580 ± 10%
108±10%
–10
–10
4
Units
MHz dB dB
PPM
UI dB mV us us ns us dB mV
dB
decade slope
Return loss common mode
Rise time
Fall time
Intra differential pair skew
Intra-transceiver block skew (×4)
50 MHz to 1.25
GHz (PCI Express)
—
—
V
OD
= 800 mV
—
35
35
—
—
–6
—
—
—
—
65
65
15
100 dB ps ps ps ps
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–6 Chapter 4: DC and Switching Characteristics
Operating Conditions
Table 4–6. Arria GX Transceiver Block AC Specification (Part 3 of 3)
Symbol / Description Conditions
–6 Speed Grade Commercial and
Industrial
Min Typ Max
Units
Transmitter PLL
VCO frequency range
Bandwidth at 3.125 Gbps
Bandwidth at 2.5 Gbps
—
BW = Low
BW = Med
BW = High
BW = Low
BW = Med
BW = High
500
—
—
—
—
—
—
2
4
9
1
—
3
5
1562.5
—
—
—
—
—
—
MHz
MHz
MHz
TX PLL lock time from gxb_powerdown de-assertion
— — — 100 us
PCS
Interface speed per mode
Digital Reset Pulse Width
—
—
25 — 156.25
Minimum is 2 parallel clock cycles
MHz
—
(1) Spread spectrum clocking is allowed only in PCI Express (PIPE) mode if the upstream transmitter and the receiver share the same clock source.
(2) The reference clock DC coupling option is only available in PCI Express (PIPE) mode for the HCSL I/O standard.
(3) The fixedclk is used in PIPE mode receiver detect circuitry.
(4) The device cannot tolerate prolonged operation at this absolute maximum.
(5) The rate matcher supports only up to ± 300 PPM for PIPE mode and ± 100 PPM for GIGE mode.
(6) This parameter is measured by embedding the run length data in a PRBS sequence.
(7) Signal detect threshold detector circuitry is available only in PCI Express (PIPE mode).
(8) Time taken for rx_pll_locked to go high from rx_analogreset deassertion. Refer to Figure 4–1 .
(9) For lock times specific to the protocols, refer to protocol characterization documents.
(10) Time for which the CDR needs to stay in LTR mode after rx_pll_locked is asserted and before rx_locktodata is asserted in manual mode. Refer to
(11) Time taken to recover valid data from GXB after the rx_locktodata signal is asserted in manual mode. Measurement results are based on
PRBS31, for native data rates only. Refer to
(12) Time taken to recover valid data from GXB after the rx_freqlocked signal goes high in automatic mode. Measurement results are based on PRBS31, for native data rates only. Refer to
(13) This is applicable only to PCI Express (PIPE) ×4 and XAUI ×4 mode.
(14) Time taken to lock TX PLL from gxb_powerdown deassertion.
(15) The 1.2 V RX VICM settings is intended for DC-coupled LVDS links.
shows the lock time parameters in manual mode.
lock time parameters in automatic mode.
1
LTD = Lock to data
LTR = Lock to reference clock
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Operating Conditions
Figure 4–1. Lock Time Parameters for Manual Mode r x_analogreset
CDR status r x_pll_locked
4–7
LTR LTD r x_locktodata r x_dataout
Invalid Data
CDR LTR Time LTD lock time
CDR Minimum T1b
Valid data
Figure 4–2. Lock Time Parameters for Automatic Mode
CDR status
LTR LTD r x_freqlocked r x_dataout
Invalid data
Valid data
Data lock time from rx_freqlocked
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–8 Chapter 4: DC and Switching Characteristics
Operating Conditions
and
show differential receiver input and transmitter output waveforms, respectively.
Figure 4–3. Receiver Input Waveform
Single-Ended Waveform
V
CM
V
ID
Positive Channel (p)
Negative Channel (n)
Ground
Differential Waveform
V
ID
VID (diff peak-peak) = 2 x VID (single-ended)
V
ID p
− n = 0 V
Figure 4–4. Transmitter Output Waveform
Single-Ended Waveform
V
CM
V
OD
Positive Channel (p)
Negative Channel (n)
Ground
Differential Waveform
V
OD
VOD (diff peak-peak) = 2 x VOD (single-ended)
V
OD p
− n = 0 V
Table 4–7 lists the Arria GX transceiver block AC specification.
Table 4–7. Arria GX Transceiver Block AC Specification
(Part 1 of 4)
Description Condition
–6 Speed Grade
Commercial &
Industrial
Units
XAUI Transmit Jitter Generation
Total jitter at 3.125 Gbps
REFCLK
= 156.25 MHz
Pattern = CJPAT
V
OD
= 1200 mV
No Pre-emphasis
0.3
UI
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Operating Conditions
Table 4–7. Arria GX Transceiver Block AC Specification
(Note 1)
,
(2)
,
(3)
(Part 2 of 4)
Description Condition
Deterministic jitter at 3.125 Gbps
REFCLK
= 156.25 MHz
Pattern = CJPAT
V
OD
= 1200 mV
No Pre-emphasis
XAUI Receiver Jitter Tolerance
Total jitter
Deterministic jitter
Peak-to-peak jitter
Peak-to-peak jitter
Peak-to-peak jitter
Pattern = CJPAT
No Equalization
DC Gain = 3 dB
Pattern = CJPAT
No Equalization
DC Gain = 3 dB
Jitter frequency = 22.1 KHz
Jitter frequency = 1.875 MHz
Jitter frequency = 20 MHz
PCI Express (PIPE) Transmitter Jitter Generation
Total Transmitter Jitter Generation
Compliance Pattern; V
OD
Pre-emphasis = 49%
= 800 mV;
PCI Express (PIPE) Receiver Jitter Tolerance
Total Receiver Jitter Tolerance
Compliance Pattern;
DC Gain = 3 db
Gigabit Ethernet (GIGE) Transmitter Jitter Generation
Total Transmitter Jitter Generation (TJ)
Deterministic Transmitter Jitter
Generation (DJ)
CRPAT: V
OD
= 800 mV;
Pre-emphasis = 0%
CRPAT; V
OD
= 800 mV;
Pre-emphasis = 0%
Gigabit Ethernet (GIGE) Receiver Jitter Tolerance
Total Jitter Tolerance
Deterministic Jitter Tolerance
CJPAT Compliance Pattern;
DC Gain = 0 dB
CJPAT Compliance Pattern;
DC Gain = 0 dB
Serial RapidIO (1.25 Gbps, 2.5 Gbps, and 3.125 Gbps) Transmitter Jitter Generation
Total Transmitter Jitter Generation (TJ)
Deterministic Transmitter Jitter
Generation (DJ)
CJPAT Compliance Pattern;
V
OD
= 800 mV;
Pre-emphasis = 0%
CJPAT Compliance Pattern;
V
OD
= 800 mV;
Pre-emphasis = 0%
–6 Speed Grade
Commercial &
Industrial
Units
0.17
UI
> 0.65
> 0.37
> 8.5
> 0.1
> 0.1
UI
UI
UI
UI
< 0.25
UI p-p
> 0.6
< 0.279
< 0.14
> 0.66
> 0.4
< 0.35
< 0.17
UI
4–9
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–10 Chapter 4: DC and Switching Characteristics
Operating Conditions
Table 4–7. Arria GX Transceiver Block AC Specification
(Note 1)
,
(2)
,
(3)
(Part 3 of 4)
Description Condition
Serial RapidIO (1.25 Gbps, 2.5 Gbps, and 3.125 Gbps) Receiver Jitter Tolerance
CJPAT Compliance Pattern;
Total Jitter Tolerance
Combined Deterministic and Random
Jitter Tolerance (J
DR
)
Deterministic Jitter Tolerance (J
D
)
DC Gain = 0 dB
CJPAT Compliance Pattern;
DC Gain = 0 dB
CJPAT Compliance Pattern;
Sinusoidal Jitter Tolerance
DC Gain = 0 dB
Jitter Frequency = 22.1 KHz
Jitter Frequency = 200 KHz
Jitter Frequency = 1.875 MHz
Jitter Frequency = 20 MHz
SDI Transmitter Jitter Generation
Alignment Jitter (peak-to-peak)
Data Rate = 1.485 Gbps (HD)
REFCLK
= 74.25 MHz
Pattern = Color Bar
Vod = 800 mV
No Pre-emphasis
Low-Frequency Roll-Off = 100 KHz
Data Rate = 2.97 Gbps (3G)
REFCLK
= 148.5 MHz
Pattern = Color Bar
Vod = 800 mV
No Pre-emphasis
Low-Frequency Roll-Off = 100 KHz
–6 Speed Grade
Commercial &
Industrial
> 0.65
> 0.55
> 0.37
> 8.5
> 1.0
> 0.1
> 0.1
0.2
0.3
Units
UIv
UI
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Operating Conditions
4–11
Table 4–7. Arria GX Transceiver Block AC Specification
(Note 1)
,
(2)
,
(3)
(Part 4 of 4)
Description Condition
Sinusoidal Jitter Tolerance
(peak-to-peak)
Sinusoidal Jitter Tolerance
(peak-to-peak)
Jitter Frequency = 15 KHz
Data Rate = 2.97 Gbps (3G)
REFCLK
= 148.5 MHz
Pattern = Single Line
Scramble Color Bar
No Equalization
DC Gain = 0 dB
Jitter Frequency = 100 KHz
Data Rate = 2.97 Gbps (3G)
REFCLK
= 148.5 MHz
Pattern = Single Line Scramble Color Bar
No Equalization
DC Gain = 0 dB
Jitter Frequency = 148.5 MHz
Data Rate = 2.97 Gbps (3G)
REFCLK
= 148.5 MHz
Pattern = Single Line
Scramble Color Bar
No Equalization
DC Gain = 0 dB
Jitter Frequency = 20 KHz
Data Rate = 1.485 Gbps (HD)
REFCLK
= 74.25 MHz
Pattern = 75% Color Bar
No Equalization
DC Gain = 0 dB
Jitter Frequency = 100 KHz
Data Rate = 1.485 Gbps (HD)
REFCLK
= 74.25 MHz
Pattern = 75% Color Bar
No Equalization
DC Gain = 0 dB
(1) Dedicated REFCLK pins were used to drive the input reference clocks.
(2) Jitter numbers specified are valid for the stated conditions only.
(3) Refer to the protocol characterization documents for detailed information.
(4) The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification.
(5) The jitter numbers for PCI Express are compliant to the PCIe Base Specification 2.0.
(6) The jitter numbers for Serial RapidIO are compliant to the RapidIO Specification 1.3.
(7) The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.
(8) The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M specifications.
–6 Speed Grade
Commercial &
Industrial
Units
> 2
> 0.3
> 0.3
> 1
> 0.2
UI
UI
UI
UI
UI
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–12 Chapter 4: DC and Switching Characteristics
Operating Conditions
list the transmitter and receiver PCS latency for each mode, respectively.
Functional Mode Configuration
TX PIPE
TX Phase
Comp FIFO
XAUI
PIPE
GIGE
Serial RapidIO
—
×1, ×4, ×8
8-bit channel width
×1, ×4, ×8
16-bit channel width
—
1.25 Gbps, 2.5 Gbps,
3.125 Gbps
HD10-bit channel width
HD, 3G 20-bit channel width
—
1
1
—
—
2–3
3–4
3–4
2–3
2–3
SDI
—
—
2–3
2–3
BASIC Single
Width
8-bit/10-bit channel width
16-bit/20-bit channel width
—
—
2–3
2–3
(1) The latency numbers are with respect to the PLD-transceiver interface clock cycles.
(2) The total latency number is rounded off in the Sum column.
Transmitter PCS Latency
Byte
Serializer
1
1
1
1
1
1
1
1
1
TX State
Machine
0.5
—
—
—
—
—
—
—
—
8B/10B
Encoder
0.5
1
0.5
1
0.5
1
0.5
1
0.5
4–5
6–7
6–7
4–5
4–5
4–5
4–5
4–5
4–5
Table 4–9. PCS Latency (Part 1 of 2) (Part 1 of 2)
Receiver PCS Latency
XAUI
PIPE
GIGE
Serial
RapidIO
SDI
—
×1, ×4
8-bit channel width
×1, ×4
16-bit channel width
—
1.25 Gbps, 2.5 Gbps,
3.125 Gbps
HD 10-bit channel width
HD, 3G 20-bit channel width
2–2.5
2–2.5
5.5–6.5
0.5
4–5
2–2.5
4–5
2–2.5
5
2.5
—
—
—
—
—
—
11–13
5.5–6.5
11–13
—
—
—
1
0.5
1
0.5
1
0.5
1
—
—
—
—
—
—
1
1
1
1
1
1
1
1 1–2
1 2–3
1 2–3
1 1–2
1 1–2
1 1–2
1 1–2
—
1
14–17
21–25
1
—
—
—
—
13–16
19–23
6–7
9–10
6–7
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Operating Conditions
Table 4–9. PCS Latency (Part 2 of 2) (Part 2 of 2)
Receiver PCS Latency
4–13
BASIC
Single
Width
8/10-bit channel width; with Rate Matcher
8/10-bit channel width; without Rate Matcher
16/20-bit channel width; with Rate Matcher
4–5
4–5
2–2.5
—
—
—
11–13
—
5.5–6.5
1
1
0.5
—
—
—
1
1
1
1
1
1
1–2
1–2
1–2
1
—
—
19–23
8–10
11–14
16/20-bit channel width; without Rate Matcher
2–2.5
— — 0.5
— 1 1 1–2 — 6–7
(1) The latency numbers are with respect to the PLD-transceiver interface clock cycles.
(2) The total latency number is rounded off in the Sum column.
(3) The rate matcher latency shown is the steady state latency. Actual latency may vary depending on the skip ordered set gap allowed by the protocol, actual PPM difference between the reference clocks, and so forth.
through Table 4–13 show the typical V
OD
for data rates from 600 Mbps to
3.125 Gbps. The specification is for measurement at the package ball.
Table 4–10. Typical V
OD
Setting, TX Term = 100
V cc
HTX = 1.5 V
V
OD
Typical (mV)
400
430
600
625
V
OD
Setting (mV)
800
830
1000
1020
1200
1200
Table 4–11. Typical V
OD
Setting, TX Term = 100
V cc
HTX = 1.2 V
V
OD
Typical (mV)
320
344
480
500
V
OD
Setting (mV)
640
664
800
816
960
960
Table 4–12. Typical Pre-Emphasis (First Post-Tap),
V cc
HTX = 1.5 V
V
OD
Setting (mV) 1
First Post Tap Pre-Emphasis Level
2 4
400
600
800
24%
—
—
62%
31%
20%
3
TX Term = 100
112%
56%
35%
184%
86%
53%
5
—
122%
73%
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–14 Chapter 4: DC and Switching Characteristics
Operating Conditions
Table 4–12. Typical Pre-Emphasis (First Post-Tap),
(Note 1)
V cc
HTX = 1.5 V First Post Tap Pre-Emphasis Level
V
OD
Setting (mV)
1000
1200
1
—
—
2
—
—
3
23%
17%
4
36%
25%
5
49%
35%
Note to
(1) Applicable to data rates from 600 Mbps to 3.125 Gbps. Specification is for measurement at the package ball.
Table 4–13. Typical Pre-Emphasis (First Post-Tap),
V cc
HTX = 1.2 V First Post Tap Pre-Emphasis Level
V
OD
Setting (mV) 1 2 3 4 5
320
480
640
800
960
24%
—
—
—
—
61%
31%
20%
—
—
TX Term = 100
114%
55%
35%
23%
18%
—
86%
54%
36%
25%
—
121%
72%
49%
35%
Note to
(1) Applicable to data rates from 600 Mbps to 3.125 Gbps. Specification is for measurement at the package ball.
DC Electrical Characteristics
lists the Arria GX device family DC electrical characteristics.
Table 4–14. Arria GX Device DC Operating Conditions (Part 1 of 2)
I
I
I
I
I
I
OZ
Symbol
CCINT0
CCPD0
CCI00
Parameter Conditions
Input pin leakage current V
I
= V
CCIOmax
to 0 V
Tri-stated I/O pin leakage current
V
O
= V
CCIOmax
to 0 V
V
CCINT
supply current
(standby)
V
I
= ground, no load, no toggling inputs
T
J
= 25 °C
V
CCPD
supply current
(standby)
V
CCIO
supply current
(standby)
V
I
= ground, no load, no toggling inputs
T
J
= 25 °C,
V
CCPD
= 3.3V
V
I
= ground, no load, no toggling inputs
T
J
= 25 °C
All
All
Device
EP1AGX20/35
EP1AGX50/60
EP1AGX90
EP1AGX20/35
EP1AGX50/60
EP1AGX90
EP1AGX20/35
EP1AGX50/60
EP1AGX90
—
—
—
—
—
—
—
—
—
Min
–10
–10
Typ
—
—
0.30
0.50
0.62
2.7
3.6
4.3
4.0
4.0
4.0
Max
10
10
Units
A
A
A
A
A mA mA mA mA mA mA
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Operating Conditions
4–15
Table 4–14. Arria GX Device DC Operating Conditions (Part 2 of 2)
(Note 1)
R
Symbol
CONF
Parameter
Value of I/O pin pull-up resistor before and during configuration
Conditions
V i
= 0, V
CCIO
= 3.3 V
V i
= 0, V
CCIO
= 2.5 V
V i
= 0, V
CCIO
= 1.8 V
V i
= 0, V
CCIO
= 1.5 V
V i
= 0, V
CCIO
= 1.2 V
Device
—
—
—
—
—
Min
10
15
30
40
50
Typ
25
35
50
75
90
Max
50
70
100
150
170
Recommended value of
I/O pin external pull-down resistor before and during configuration
— — — 1 2 k
(1) Typical values are for T
A
= 25 °C, V
CCINT
= 1.2 V, and V
CCIO
= 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V.
(2) This value is specified for normal device operation. The value may vary during power-up. This applies for all V
CCIO
settings (3.3, 2.5, 1.8, 1.5, and 1.2 V).
(3) Maximum values depend on the actual TJ and design utilization. For maximum values, refer to the Excel-based PowerPlay Early Power Estimator
(available at PowerPlay Early Power Estimators (EPE) and Power Analyzer ) or the Quartus
®
II PowerPlay Power Analyzer feature for maximum values. For more information, refer to
“Power Consumption” on page 4–25
.
(4) Pin pull-up resistance values will be lower if an external source drives the pin higher than V
CCIO
.
Units
k
k
k
k
k
I/O Standard Specifications
through Table 4–38 show the Arria GX device family I/O standard
specifications.
Table 4–15. LVTTL Specifications
Symbol Parameter Conditions Minimum Maximum
V
CCIO
V
IH
V
IL
Output supply voltage
High-level input voltage
Low-level input voltage
—
—
—
3.135
1.7
–0.3
3.465
4.0
0.8
V
OH
V
OL
High-level output voltage I
OH
Low-level output voltage I
OL
= 4 mA
2.4
—
—
0.45
(1) Arria GX devices comply to the narrow range for the supply voltage as specified in the EIA/JEDEC Standard, JESD8-B.
(2) This specification is supported across all the programmable drive strength settings available for this I/O standard.
Units
V
V
V
V
V
Table 4–16. LVCMOS Specifications
Symbol Parameter Conditions Minimum Maximum
V
CCIO
V
IH
V
IL
V
V
OH
OL
Output supply voltage
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
—
—
—
V
CCIO
= 3.0, I
OH
= –0.1 mA
V
CCIO
= 3.0, I
OL
3.135
1.7
–0.3
V
CCIO
– 0.2
—
(1) Arria GX devices comply to the narrow range for the supply voltage as specified in the EIA/JEDEC Standard, JESD8-B.
(2) This specification is supported across all the programmable drive strength available for this I/O standard.
3.465
4.0
0.8
—
0.2
Units
V
V
V
V
V
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–16 Chapter 4: DC and Switching Characteristics
Operating Conditions
Table 4–17. 2.5-V I/O Specifications
Symbol Parameter Conditions Minimum Maximum Units
V
CCIO
V
IH
V
IL
V
V
OH
OL
Output supply voltage
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
—
—
—
I
OH
I
OL
= 1 mA
2.375
1.7
–0.3
2.0
—
2.625
4.0
0.7
—
0.4
(1) The Arria GX device V
CCIO
voltage level support of 2.5 to 5% is narrower than defined in the normal range of the EIA/JEDEC standard.
(2) This specification is supported across all the programmable drive settings available for this I/O standard.
V
V
V
V
V
Table 4–18. 1.8-V I/O Specifications
Symbol Parameter Conditions Minimum Maximum Units
V
CCIO
V
V
IH
IL
V
OH
V
OL
Output supply voltage
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
—
—
—
1.71
0.65 × V
CCIO
–0.3
I
OH
V
CCIO
– 0.45
I
OL
—
1.89
2.25
0.35 × V
CCIO
—
0.45
V
V
V
V
V
(1) The Arria GX device V
CCIO
voltage level support of 1.8 to 5% is narrower than defined in the normal range of the EIA/JEDEC standard.
(2) This specification is supported across all the programmable drive settings available for this I/O standard, as shown in
Arria GX Architecture
chapter.
Table 4–19. 1.5-V I/O Specifications
Symbol Parameter Conditions Minimum Maximum Units
V
CCIO
V
V
IH
IL
V
OH
V
OL
Output supply voltage
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
—
—
—
I
OH
I
OL
= 2 mA
1.425
0.65 V
CCIO
–0.3
0.75 V
—
CCIO
V
1.575
CCIO
+ 0.3
0.35 V
CCIO
—
0.25 V
CCIO
(1) The Arria GX device V
CCIO
voltage level support of 1.5 to 5% is narrower than defined in the normal range of the EIA/JEDEC standard.
(2) This specification is supported across all the programmable drive settings available for this I/O standard, as shown in the
Arria GX
Architecture
chapter.
V
V
V
V
V
and
show receiver input and transmitter output waveforms, respectively, for all differential I/O standards (LVDS and LVPECL).
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Operating Conditions
Figure 4–5. Receiver Input Waveforms for Differential I/O Standards
Single-Ended Waveform
Positive Channel (p) = V
IH
V
ID
Negative Channel (n) = V
IL
V
CM
Ground
4–17
Differential Waveform
V
ID
V
ID (Peak-to-Peak)
V
ID p
− n = 0 V
Figure 4–6. Transmitter Output Waveforms for Differential I/O Standards
Single-Ended Waveform
Positive Channel (p) = V
OH
V
OD
Negative Channel (n) = V
OL
V
CM
Ground
Differential Waveform
V
OD
V
OD p
− n = 0 V
Table 4–20. 2.5-V LVDS I/O Specifications
Symbol
V
CCIO
V
V
V
V
R
ID
ICM
OD
OCM
L
Parameter Conditions
I/O supply voltage for left and right I/O banks (1, 2, 5, and 6)
—
Input differential voltage swing
(single-ended)
—
Input common mode voltage —
Output differential voltage (single-ended) R
L
= 100
Output common mode voltage R
L
= 100
Receiver differential input discrete resistor (external to Arria GX devices)
—
Minimum
2.375
100
200
250
1.125
90
Typical
2.5
Maximum Units
2.625
V
350
1,250
—
—
100
900
1,800
450
1.375
110 mV mV mV
V
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–18 Chapter 4: DC and Switching Characteristics
Operating Conditions
Table 4–21. 3.3-V LVDS I/O Specifications
Symbol Parameter Conditions Minimum Typical Maximum Units
V
V
ID
I/O supply voltage for top and bottom
PLL banks (9, 10, 11, and 12)
Input differential voltage swing
(single-ended)
—
—
3.135
100
3.3
350
3.465
900
V mV
V
ICM
V
OD
V
OCM
R
L
Input common mode voltage —
Output differential voltage (single-ended) R
L
= 100
Output common mode voltage R
L
= 100
Receiver differential input discrete resistor (external to Arria GX devices)
—
200
250
840
90
1,250
—
—
100
1,800
710
1,570
110 mV mV mV
Note to
(1) The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by V
CCINT
, not V
CCIO
. The PLL clock output/feedback differential buffers are powered by VCC_PLL_OUT. For differential clock output/feedback operation, connect VCC_PLL_OUT to 3.3 V.
V
T
R
1
R
2
V
ICM
V
OD
V
OD
V
OCM
V
OCM
Table 4–22. 3.3-V PCML Specifications
V
V
CCIO
ID
Symbol Parameter
I/O supply voltage
Input differential voltage swing
(single-ended)
Input common mode voltage
Output differential voltage (single-ended)
Change in V
O D
between high and low
Output common mode voltage
Change in V
O C M
between high and low
Output termination voltage
Output external pull-up resistors
Output external pull-up resistors
Minimum
3.135
300
1.5
300
—
2.5
—
—
45
45
Typical
3.3
—
—
370
—
2.85
—
V
C C I O
50
50
Maximum
3.465
600
3.465
500
50
3.3
50
—
55
55
Table 4–23. LVPECL Specifications
Parameter Conditions Minimum Typical Maximum Units Parameter
V
V
CCIO
ID
I/O supply voltage
Input differential voltage swing
(single-ended)
—
—
3.135
300
3.3
600
3.465
1,000
V mV
V
V
ICM
OD
Input common mode voltage
Output differential voltage
(single-ended)
Output common mode voltage
R
L
—
= 100
1.0
525
—
—
2.5
970
V mV
V
OCM
R
L
Receiver differential input resistor
R
L
= 100
—
1,650
90
—
100
2,250
110 mV
Note to
(1) The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by V
CCINT
, not V
CCIO
. The PLL clock output/feedback differential buffers are powered by VCC_PLL_OUT. For differential clock output/feedback operation, connect VCC_PLL_OUT to 3.3 V.
Units
V mV
V mV mV
V mV
V
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Operating Conditions
V
CCIO
V
IH
V
IL
V
OH
V
OL
Table 4–24. 3.3-V PCI Specifications
Symbol Parameter
Output supply voltage
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Conditions Minimum Typical Maximum Units
— 3.0
— 0.5 V
CCIO
— –0.3
I
OUT
= –500
A
0.9 V
CCIO
I
OUT
= 1,500
A
—
3.3
—
—
—
—
3.6
V
CCIO
+ 0.5
0.3 V
CCIO
—
0.1 V
CCIO
V
V
V
V
V
Table 4–25. PCI-X Mode 1 Specifications
V
CCIO
V
IH
V
IL
V
IPU
V
OH
V
OL
Symbol Parameter
Output supply voltage
High-level input voltage
Low-level input voltage
Input pull-up voltage
High-level output voltage
Low-level output voltage
Conditions
—
—
—
—
I
OUT
= –500
A
I
OUT
= 1,500
A
Minimum
3.0
0.5 V
CCIO
–0.3
0.7 V
CCIO
0.9 V
CCIO
—
Maximum
3.6
V
CCIO
+ 0.5
0.35 V
CCIO
—
—
0.1 V
CCIO
Units
V
Table 4–26. SSTL-18 Class I Specifications
Symbol Parameter Conditions Minimum Typical Maximum Units
V
CCIO
V
REF
V
TT
V
IH
(DC)
V
IL
(DC)
V
IH
(AC)
V
IL
(AC)
V
V
OH
OL
Output supply voltage
Reference voltage
Termination voltage
High-level DC input voltage
Low-level DC input voltage
High-level AC input voltage
Low-level AC input voltage
High-level output voltage
Low-level output voltage
—
—
—
—
—
—
—
V
REF
– 0.04
V
REF
+ 0.125
V
REF
1.71
0.855
—
+ 0.25
—
I
OH
= –6.7 mA
V
TT
+ 0.475
I
OL
= 6.7 mA
—
1.8
0.9
V
REF
—
—
—
—
—
—
V
V
REF
+ 0.04
V
V
REF
0.945
REF
TT
1.89
—
– 0.125
—
– 0.25
—
– 0.475
Note to
(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the
Arria GX
Architecture
chapter.
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Table 4–27. SSTL-18 Class II Specifications
Symbol
V
CCIO
V
REF
V
TT
V
IH
(DC)
V
I L
(DC)
V
IH
(AC)
V
IL
(AC)
Parameter
Output supply voltage
Reference voltage
Termination voltage
High-level DC input voltage
Low-level DC input voltage
High-level AC input voltage
Low-level AC input voltage
Conditions
—
—
—
—
—
—
—
Minimum
1.71
0.855
V
REF
– 0.04
V
REF
+ 0.125
—
V
REF
+ 0.25
—
Typical
1.8
0.9
V
REF
—
—
—
—
Maximum
1.89
0.945
V
REF
+ 0.04
—
V
REF
– 0.125
—
V
REF
– 0.25
Units
V
V
V
V
V
V
V
4–19
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–20 Chapter 4: DC and Switching Characteristics
Operating Conditions
Table 4–27. SSTL-18 Class II Specifications
Symbol Parameter Conditions Minimum Typical Maximum Units
V
OH
V
OL
High-level output voltage
Low-level output voltage I
I
OH
OL
= –13.4 mA
V
CCIO
= 13.4 mA
– 0.28
—
—
—
—
0.28
Note to
(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the
Arria GX
Architecture
chapter.
V
V
Table 4–28. SSTL-18 Class I & II Differential Specifications
Symbol Parameter
V
CCIO
V
X
(AC)
Output supply voltage
V
SWING
(DC) DC differential input voltage
AC differential input cross point voltage
V
SWING
(AC) AC differential input voltage
V
ISO
V
ISO
Input clock signal offset voltage
Input clock signal offset voltage variation
V
OX
(AC) AC differential cross point voltage
Minimum
1.71
0.25
(V
CCIO
/2) – 0.175
(V
CCIO
0.5
—
—
/2) – 0.125
Typical
1.8
—
—
—
0.5 V
CC IO
200
—
Maximum
1.89
—
(V
CCIO
/2) + 0.175
(V
CCIO
—
—
—
/2) + 0.125
Units
V
V
V
V
V mV
V
Table 4–29. SSTL-2 Class I Specifications
Symbol Parameter Conditions Minimum Typical Maximum Units
V
CCIO
V
TT
V
REF
V
IH
(DC)
V
IL
(DC)
V
IH
(AC)
V
IL
(AC)
V
OH
Output supply voltage
Termination voltage
Reference voltage
High-level DC input voltage
Low-level DC input voltage
High-level AC input voltage
Low-level AC input voltage
High-level output voltage
—
—
—
—
—
—
—
I
OH
= –8.1 mA
2.375
V
REF
– 0.04
1.188
V
REF
+ 0.18
–0.3
V
REF
+ 0.35
—
V
TT
+ 0.57
2.5
V
REF
1.25
—
—
—
—
—
2.625
V
REF
+ 0.04
1.313
3.0
V
V
REF
REF
– 0.18
—
– 0.35
V
V
V
V
V
V
V
V
V
OL
Low-level output voltage I
OL
= 8.1 mA
— — V
TT
– 0.57
V
Note to
(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the
Arria GX Architecture
chapter.
Table 4–30. SSTL-2 Class II Specifications (Part 1 of 2)
Symbol
V
CC IO
V
TT
V
REF
V
IH
(DC)
Parameter
Output supply voltage
Termination voltage
Reference voltage
High-level DC input voltage
Conditions
—
—
—
—
Minimum
2.375
V
REF
– 0.04
1.188
V
REF
+ 0.18
Typical
2.5
V
REF
1.25
—
Maximum
2.625
V
REF
+ 0.04
1.313
V
CCIO
+ 0.3
Units
V
V
V
V
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Operating Conditions
4–21
Table 4–30. SSTL-2 Class II Specifications (Part 2 of 2)
Symbol Parameter Conditions Minimum Typical Maximum Units
V
V
IL
IH
(DC)
(AC)
Low-level DC input voltage
High-level AC input voltage
—
— V
REF
–0.3
+ 0.35
—
—
V
REF
– 0.18
—
V
V
V
IL
V
OH
V
OL
(AC) Low-level AC input voltage
High-level output voltage I
OH
Low-level output voltage I
OL
—
= –16.4 mA
V
TT
—
+ 0.76
—
—
—
—
V
REF
V
TT
– 0.35
—
– 0.76
V
V
V
Note to
(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the
Arria GX Architecture
chapter.
Table 4–31. SSTL-2 Class I & II Differential Specifications
V
CCIO
Symbol
V
SWING
(DC)
V
X
(AC)
V
SWING
(AC)
V
ISO
V
ISO
V
OX
(AC)
Parameter
Output supply voltage
DC differential input voltage
AC differential input cross point voltage
AC differential input voltage
Input clock signal offset voltage
Input clock signal offset voltage variation
AC differential output cross point voltage
(V
CCIO
/2) – 0.2
0.7
(V
Minimum
2.375
CCIO
0.36
—
—
/2) – 0.2
Typical
2.5
—
—
—
0.5 V
CCIO
200
— (V
Maximum
2.625
CCIO
—
(V
CCIO
/2) + 0.2
—
—
—
/2) + 0.2
V
Note to
(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the
Arria GX Architecture
chapter.
Units
V
V
V
V
V mV
Table 4–32. 1.2-V HSTL Specifications
Symbol
V
CCIO
V
REF
V
IH
(DC)
V
IL
(DC)
V
IH
(AC)
V
IL
(AC)
V
OH
V
OL
Parameter
Output supply voltage
Reference voltage
High-level DC input voltage
Low-level DC input voltage
High-level AC input voltage
Low-level AC input voltage
High-level output voltage
Low-level output voltage
Minimum
1.14
0.48 V
CCIO
V
REF
+ 0.08
–0.15
V
REF
+ 0.15
–0.24
V
REF
+ 0.15
–0.15
Typical
1.2
0.5 V
CCIO
—
—
—
—
—
—
Maximum
1.26
0.52 V
CCIO
V
CCIO
+ 0.15
V
REF
– 0.08
V
CCIO
+ 0.24
V
REF
– 0.15
V
CCIO
+ 0.15
V
REF
– 0.15
Units
V
V
V
V
V
V
V
V
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–22 Chapter 4: DC and Switching Characteristics
Operating Conditions
Table 4–33. 1.5-V HSTL Class I Specifications
Symbol Parameter Conditions Minimum Typical Maximum Units
V
CCIO
V
REF
V
TT
V
IH
(DC)
V
IL
(DC)
V
IH
V
IL
V
V
OH
OL
(AC)
(AC)
Output supply voltage
Input reference voltage
Termination voltage
DC high-level input voltage
DC low-level input voltage
AC high-level input voltage
AC low-level input voltage
High-level output voltage
Low-level output voltage
—
—
—
—
—
—
—
I
OH
I
OH
= –8 mA
V
V
REF
+ 0.2
V
1.425
0.713
0.713
REF
–0.3
CCIO
+ 0.1
—
– 0.4
—
1.5
0.75
0.75
—
—
—
—
—
—
V
1.575
0.788
0.788
REF
V
REF
—
– 0.1
—
– 0.2
—
0.4
V
V
V
V
V
V
V
V
V
Note to
(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the
Arria GX Architecture
chapter.
Table 4–34. 1.5-V HSTL Class II Specifications
Symbol Parameter Conditions Minimum Typical Maximum Units
V
CCIO
V
REF
V
TT
V
IH
(DC)
V
IL
(DC)
V
IH
(AC)
V
IL
V
V
OH
OL
(AC)
Output supply voltage
Input reference voltage
Termination voltage
DC high-level input voltage
DC low-level input voltage
AC high-level input voltage
AC low-level input voltage
High-level output voltage
Low-level output voltage
—
—
—
—
—
—
—
I
OH
= 16 mA
I
OH
V
REF
+ 0.1
V
REF
+ 0.2
V
1.425
0.713
0.713
–0.3
—
CCIO
– 0.4
—
1.50
0.75
0.75
—
—
—
—
—
—
V
1.575
0.788
0.788
REF
V
REF
—
– 0.1
—
– 0.2
—
0.4
V
V
V
V
V
V
V
V
V
Note to
(1) This specification is supported across all the programmable drive settings available for this I/O standard, as shown in the
Arria GX Architecture
chapter.
Table 4–35. 1.5-V HSTL Class I & II Differential Specifications
Symbol
V
CCIO
V
DIF
(DC)
V
CM
(DC)
V
DIF
(AC)
V
OX
(AC)
Parameter
I/O supply voltage
DC input differential voltage
DC common mode input voltage
AC differential input voltage
AC differential cross point voltage
Minimum
1.425
0.2
0.68
0.4
0.68
Typical
1.5
—
—
—
—
Maximum
1.575
—
0.9
—
0.9
Units
V
V
V
V
V
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Operating Conditions
4–23
Table 4–36. 1.8-V HSTL Class I Specifications
Symbol Parameter Conditions Minimum Typical Maximum Units
V
CCIO
V
REF
V
TT
V
IH
(DC)
V
IL
(DC)
Output supply voltage
Input reference voltage
Termination voltage
DC high-level input voltage
DC low-level input voltage
V
IH
(AC) AC high-level input voltage
V
IL
(AC) AC low-level input voltage
V
OH
V
OL
High-level output voltage
Low-level output voltage
—
—
—
—
—
—
—
I
OH
= 8 mA
I
OH
V
REF
+ 0.1
V
REF
+ 0.2
V
1.71
0.85
0.85
–0.3
CCIO
—
– 0.4
—
1.80
0.90
0.90
—
—
—
—
—
—
V
1.89
0.95
0.95
REF
V
REF
—
– 0.1
—
– 0.2
—
0.4
V
V
V
V
V
V
V
V
V
Note to
(1) This specification is supported across all the programmable drive settings available for this I/O standard, as shown in the
Arria GX Architecture
chapter.
Table 4–37. 1.8-V HSTL Class II Specifications
Symbol Parameter Conditions Minimum Typical Maximum Units
V
CCIO
V
REF
V
TT
V
IH
(DC)
V
IL
(DC)
V
IH
(AC)
V
IL
V
V
OH
OL
(AC)
Output supply voltage
Input reference voltage
Termination voltage
DC high-level input voltage
DC low-level input voltage
AC high-level input voltage
AC low-level input voltage
High-level output voltage
Low-level output voltage
—
—
—
—
—
—
—
1.71
0.85
0.85
V
REF
+ 0.1
–0.3
V
REF
+ 0.2
—
I
OH
V
CCIO
– 0.4
I
OH
= –16 mA
—
1.80
0.90
0.90
—
—
—
—
—
—
V
1.89
0.95
0.95
REF
V
REF
—
– 0.1
—
– 0.2
—
0.4
V
V
V
V
V
V
V
V
V
Note to
(1) This specification is supported across all the programmable drive settings available for this I/O standard, as shown in the
Arria GX Architecture
chapter in volume 1 of the Arria GX Device Handbook.
Table 4–38. 1.8-V HSTL Class I & II Differential Specifications
Symbol
V
CCIO
V
DIF
(DC)
V
CM
(DC)
V
DIF
(AC)
V
OX
(AC)
Parameter
I/O supply voltage
DC input differential voltage
DC common mode input voltage
AC differential input voltage
AC differential cross point voltage
Minimum
1.71
0.2
0.78
0.4
0.68
Typical
1.80
—
—
—
—
Maximum
1.89
—
1.12
—
0.9
Units
V
V
V
V
V
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–24 Chapter 4: DC and Switching Characteristics
Operating Conditions
Bus Hold Specifications
shows the Arria GX device family bus hold specifications.
Table 4–39. Bus Hold Parameters
Parameter Conditions
V
IN
> V
IL
(maximum)
1.2 V 1.5 V
V
C CIO
Level
1.8 V 2.5 V 3.3 V
Min Max Min Max Min Max Min Max Min Max
22.5
— 25 — 30 — 50 — 70 — Low sustaining current
High sustaining current
Low overdrive current
High overdrive current
Bus-hold trip point
V
IN
(minimum)
<V
IN
V
IN
< V
0 V
—
IH
< V
CCIO
0 V <
< V
CCIO
–22.5
—
—
0.45
—
120
–120
0.95
–25 —
—
—
0.5
160
–30
—
–160 —
1.0
0.68
—
200
–200
1.07
–50
—
—
0.7
—
300
–300
1.7
–70
—
—
0.8
—
500
–500
2.0
Units
A
A
A
A
V
On-Chip Termination Specifications
and
define the specification for internal termination resistance tolerance when using series or differential on-chip termination.
Table 4–40. Series On-Chip Termination Specification for Top and Bottom I/O Banks
Symbol Description
V
Conditions
CCIO
= 3.3/2.5V
Resistance Tolerance
Commercial
Max
±30
Industrial
Max
±30
Units
% 25-
R
S
3.3/2.5
Internal series termination without calibration (25-
setting
50-
R
S
3.3/2.5
Internal series termination without calibration (50-
setting
25-
R
S
1.8
Internal series termination without calibration (25-
setting
50-
R
S
1.8
Internal series termination without calibration (50-
setting
50-
R
S
1.5
Internal series termination without calibration (50-
setting
50-
R
S
1.2
Internal series termination without calibration (50-
setting
V
CCIO
V
V
V
V
= 3.3/2.5V
CCIO
CCIO
CCIO
CCIO
= 1.8V
= 1.8V
= 1.5V
= 1.2V
±30
±30
±30
±36
±50
± 30
±30
±30
±36
±50
%
%
%
%
%
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Power Consumption
4–25
Table 4–41. Series On-Chip Termination Specification for Left I/O Banks
25-
R
S
50-
R
S
3.3/2.5/1.8
50-
R
S
1.5
R
D
Symbol Description
3.3/2.5
Internal series termination without calibration (25-
setting
Internal series termination without calibration (50-
setting
Internal series termination without calibration (50-
setting
Internal differential termination for
LVDS (100-
setting)
Conditions
V
CCIO
= 3.3/2.5V
V
CCIO
= 3.3/2.5/1.8V
Resistance Tolerance
Commercial
Max
±30
Industrial
Max
±30
Units
%
±30 ±30 %
V
V
CCIO
CCIO
= 1.5V
= 2.5V
±36
±20
±36
±25
%
%
Pin Capacitance
shows the Arria GX device family pin capacitance.
Table 4–42. Arria GX Device Capacitance
Symbol Parameter Typical Units
C
C
IOTB
IOL
Input capacitance on I/O pins in I/O banks 3, 4, 7, and 8.
Input capacitance on I/O pins in I/O banks 1 and 2, including high-speed differential receiver and transmitter pins.
5.0
6.1
pF pF
C
CLKTB
C
CLKL
C
CLKL+
C
OUTFB
Input capacitance on top/bottom clock input pins:
Input capacitance on left clock inputs:
Input capacitance on left clock inputs:
CLK0
CLK1
and
and
CLK[4..7]
CLK2
CLK3
.
.
and
CLK[12..15]
.
Input capacitance on dual-purpose clock output/feedback pins in PLL banks 11 and 12.
6.0
6.1
3.3
6.7
pF pF pF pF
Note to
(1) Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement accuracy is within ±0.5 pF.
Power Consumption
Altera offers two ways to calculate power for a design: the Excel-based PowerPlay early power estimator power calculator and the Quartus II PowerPlay power analyzer feature.
The interactive Excel-based PowerPlay Early Power Estimator is typically used prior to designing the FPGA in order to get an estimate of device power. The Quartus II
PowerPlay Power Analyzer provides better quality estimates based on the specifics of the design after place-and-route is complete. The power analyzer can apply a combination of user-entered, simulation-derived and estimated signal activities which, combined with detailed circuit models, can yield very accurate power estimates.
In both cases, these calculations should only be used as an estimation of power, not as a specification.
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–26 Chapter 4: DC and Switching Characteristics
I/O Timing Model f
For more information about PowerPlay tools, refer to the
PowerPlay Early Power
Estimator and PowerPlay Power Analyzer
page and the
PowerPlay Power Analysis
chapter in volume 3 of the Quartus II Handbook.
For typical I
CC
standby specifications, refer to
I/O Timing Model
The DirectDrive technology and MultiTrack interconnect ensures predictable performance, accurate simulation, and accurate timing analysis across all Arria GX device densities and speed grades. This section describes and specifies the performance of I/Os.
All specifications are representative of worst-case supply voltage and junction temperature conditions.
1
The timing numbers listed in the tables of this section are extracted from the
Quartus II software version 7.1.
Preliminary, Correlated, and Final Timing
Timing models can have either preliminary, correlated, or final status. The Quartus II software issues an informational message during design compilation if the timing models are preliminary.
Table 4–43 lists the status of the Arria GX device timing
models.
■
Preliminary
status means the timing model is subject to change. Initially, timing numbers are created using simulation results, process data, and other known parameters. These tests are used to make the preliminary numbers as close to the actual timing parameters as possible.
■
■
Correlated
numbers are based on actual device operation and testing. These numbers reflect the actual performance of the device under worst-case voltage and junction temperature conditions.
Final timing
numbers are based on complete correlation to actual devices and addressing any minor deviations from the correlated timing model. When the timing models are final, all or most of the Arria GX family devices have been completely characterized and no further changes to the timing model are expected.
Table 4–43. Arria GX Device Timing Model Status
Device
EP1AGX20
EP1AGX35
EP1AGX50
EP1AGX60
EP1AGX90
Preliminary
—
—
—
—
—
Correlated
—
—
—
—
—
Final
v v v v v
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
I/O Timing Model
4–27
I/O Timing Measurement Methodology
Different I/O standards require different baseline loading techniques for reporting timing delays. Altera characterizes timing delays with the required termination for each I/O standard and with 0 pF (except for PCI and PCI-X which use 10 pF) loading and the timing is specified up to the output pin of the FPGA device. The Quartus II software calculates the I/O timing for each I/O standard with a default baseline loading as specified by the I/O standards.
The following measurements are made during device characterization. Altera measures clock-to-output delays (t
CO
) at worst-case process, minimum voltage, and maximum temperature (PVT) for default loading conditions shown in
Use the following equations to calculate clock pin to output pin timing for Arria GX devices:
Equation 4–1.
t
CO from clock pin to I/O pin = delay from clock pad to I/O output register + IOE output register clock-to-output delay + delay from output register to output pin + I/O output delay t xz
/t zx
from clock pin to I/O pin = delay from clock pad to I/O output register + IOE output register clock-to-output delay + delay from output register to output pin + I/O output delay + output enable pin delay
Simulation using IBIS models is required to determine the delays on the PCB traces in addition to the output pin delay timing reported by the Quartus II software and the timing model in the device handbook.
1. Simulate the output driver of choice into the generalized test setup, using values from
2. Record the time to V
MEAS
.
3. Simulate the output driver of choice into the actual PCB trace and load, using the appropriate IBIS model or capacitance value to represent the load.
4. Record the time to V
MEAS
.
5. Compare the results of steps
2 and 4 . The increase or decrease in delay should be
added to or subtracted from the I/O Standard Output Adder delays to yield the actual worst-case propagation delay (clock-to-output) of the PCB trace.
The Quartus II software reports the timing with the conditions shown in Table 4–44
using the above equation.
Figure 4–7 shows the model of the circuit that is
represented by the output timing of the Quartus II software.
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–28 Chapter 4: DC and Switching Characteristics
I/O Timing Model
Figure 4–7. Output Delay Timing Reporting Setup Modeled by Quartus II
V
TT
V
CCIO
Output
Buffer
Output
V
MEAS
R
S
R
T
C
L
Output p
Output n
R
D
GND GND
:
(1) Output pin timing is reported at the output pin of the FPGA device. Additional delays for loading and board trace delay need to be accounted for with IBIS model simulations.
(2) V
CCPD
is 3.085 V unless otherwise specified.
(3) V
CCINT
is 1.12 V unless otherwise specified.
Table 4–44. Output Timing Measurement Methodology for Output Pins
,
,
Loading and Termination
I/O Standard
LVTTL
PCI-X
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL with OCT
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
Differential SSTL-18 Class II
1.5-V differential HSTL Class I
1.5-V differential HSTL Class II
1.8-V differential HSTL Class I
R
S
(
—
—
—
—
25
25
25
—
—
—
—
25
—
—
—
—
—
—
—
25
25
50
25
) R
D
(
) R
T
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(
)
25
50
25
—
25
50
25
50
—
—
—
50
—
—
—
—
50
25
50
25
50
25
50
V
CCIO
(V)
V
TT
(V) C
3.135
3.135
2.375
1.710
—
—
—
—
1.425
2.970
—
—
2.970
—
2.325
1.123
2.325
1.123
1.660
0.790
1.660
0.790
1.660
0.790
1.660
0.790
1.375
0.648
1.375
0.648
1.140
—
2.325
1.123
2.325
1.123
1.660
0.790
1.660
0.790
1.375
0.648
1.375
0.648
1.660
0.790
L
(pF)
0
0
0
0
0
0
0
0
0
10
10
0
0
0
0
0
0
0
0
0
0
0
0
Measurement
Point
V
MEAS
(V)
1.1625
0.83
0.83
0.83
0.83
0.6875
0.6875
0.570
1.5675
1.5675
1.1875
0.855
0.7125
1.485
1.485
1.1625
1.1625
1.1625
0.83
0.83
0.6875
0.6875
0.83
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
I/O Timing Model
4–29
Table 4–44. Output Timing Measurement Methodology for Output Pins
(Note 1) , (2) , (3)
Loading and Termination
I/O Standard
R
S
(
)
R
D
(
) R
T
(
)
V
CCIO
(V)
V
TT
(V) C
1.660
0.790
L
(pF)
0 1.8-V differential HSTL Class II —
LVDS —
LVPECL —
—
100
100
25
—
—
2.325
3.135
—
—
(1) Input measurement point at internal node is 0.5 V
CCINT
.
(2) Output measuring point for V
MEAS
at buffer output is 0.5 V
CCIO
.
(3) Input stimulus edge rate is 0 to V
CC
in 0.2 ns (internal signal) from the driver preceding the I/O buffer.
(4) Less than 50-mV ripple on V
CCIO
and V
CCPD
, V
CCINT
= 1.15 V with less than 30-mV ripple.
(5) V
CCPD
= 2.97 V, less than 50-mV ripple on V
CCIO
and V
CCPD
, V
CCINT
= 1.15 V.
0
0
Measurement
Point
V
MEAS
(V)
0.83
1.1625
1.5675
and
show the measurement setup for output disable and output enable timing.
Figure 4–8. Measurement Setup for t xz
OE
Din
t
XZ
, Driving High to Tristate
Enable Disable
OE
Dout
½ V
CCINT
Din
100
Ω
Dout t hz
“1”
100 mv
GND
OE
Din
t
XZ
, Driving Low to Tristate
Enable Disable
OE
½ V
CCINT
100
Ω
Dout
Din t lz
Dout
“0”
V
CCIO
100 mv
Note to
(1) V
CCINT
is 1.12 V for this measurement.
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–30 Chapter 4: DC and Switching Characteristics
I/O Timing Model
Figure 4–9. Measurement Setup for t zx
OE
t
ZX
, Tristate to Driving High
OE
Disable Enable
½ V
CCINT
Dout
Din
1 M
Ω
Din
Dout t zh
“1”
½ V
CCIO
OE
Din
t
ZX
, Tristate to Driving Low
OE
Disable Enable
½ V
CCINT
1 M
Ω
Dout
Din
Dout t zl
“0”
½ V
CCIO
specifies the input timing measurement setup.
Table 4–45. Timing Measurement Methodology for Input Pins
(Part 1 of 2)
Measurement Conditions Measurement Point
I/O Standard
LVTTL
PCI-X
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL with OCT
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
2.325
2.325
1.660
1.660
1.660
1.660
1.375
1.375
V
CCIO
(V)
3.135
3.135
2.375
1.710
1.425
2.970
2.970
1.140
2.325
2.325
1.660
1.163
1.163
0.830
0.830
0.830
0.830
0.688
0.688
V
REF
(V)
—
—
—
—
—
—
—
0.570
1.163
1.163
0.830
Edge Rate (ns)
2.325
2.325
1.660
1.660
1.660
1.660
1.375
1.375
3.135
3.135
2.375
1.710
1.425
2.970
2.970
1.140
2.325
2.325
1.660
VMEAS (V)
1.1625
1.1625
0.83
0.83
0.83
0.83
0.6875
0.6875
1.5675
1.5675
1.1875
0.855
0.7125
1.485
1.485
0.570
1.1625
1.1625
0.83
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
I/O Timing Model
4–31
Table 4–45. Timing Measurement Methodology for Input Pins
(Note 1)
,
(2)
,
(3)
,
(4)
(Part 2 of 2)
I/O Standard
Differential SSTL-18 Class II
1.5-V differential HSTL Class I
1.5-V differential HSTL Class II
V
CCIO
(V)
1.660
1.375
1.375
1.8-V differential HSTL Class I
1.8-V differential HSTL Class II
1.660
1.660
LVDS 2.325
LVPECL 3.135
Measurement Conditions
V
REF
(V)
0.830
0.688
0.688
0.830
0.830
—
—
(1) Input buffer sees no load at buffer input.
(2) Input measuring point at buffer input is 0.5 V
CCIO
.
(3) Output measuring point is 0.5 V
CC
at internal node.
(4) Input edge rate is 1 V/ns.
(5) Less than 50-mV ripple on V
CCIO
and V
CCPD
, V
CCINT
= 1.15 V with less than 30-mV ripple.
(6) V
CCPD
= 2.97 V, less than 50-mV ripple on V
CCIO and V
CCPD
, V
CCINT
= 1.15 V.
Edge Rate (ns)
1.660
1.375
1.375
1.660
1.660
0.100
0.100
Measurement Point
VMEAS (V)
0.83
0.6875
0.6875
0.83
0.83
1.1625
1.5675
Clock Network Skew Adders
The Quartus II software models skew within dedicated clock networks such as global and regional clocks. Therefore, the intra-clock network skew adder is not specified.
specifies the intra clock skew between any two clock networks driving any registers in the Arria GX device.
Table 4–46. Clock Network Specifications
Name Description Min Typ
Clock skew adder
EP1AGX20/35
EP1AGX50/60
Clock skew adder
EP1AGX90
Clock skew adder
Inter-clock network, same side
Inter-clock network, entire chip
Inter-clock network, same side
Inter-clock network, entire chip
Inter-clock network, same side
Inter-clock network, entire chip
—
—
—
—
—
—
Note to
(1) This is in addition to intra-clock network skew, which is modeled in the Quartus II software.
—
—
—
—
—
—
Max
± 50
± 100
± 50
± 100
± 55
± 110
Units
ps ps ps ps ps ps
Default Capacitive Loading of Different I/O Standards
See
Table 4–47 for default capacitive loading of different I/O standards.
Table 4–47. Default Loading of Different I/O Standards for Arria GX Devices (Part 1 of 2)
I/O Standard Capacitive Load Units
2.5 V 0 pF
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–32 Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–47. Default Loading of Different I/O Standards for Arria GX Devices (Part 2 of 2)
1.8 V
1.5 V
I/O Standard Capacitive Load
0
0
Units
pF pF
PCI-X
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
Differential SSTL-18 Class II
1.5-V differential HSTL Class I
1.5-V differential HSTL Class II
1.8-V differential HSTL Class I
1.8-V differential HSTL Class II
LVDS 0
0
0
0
0
0
0
0
0
0
0
0
0
10 pF
0
0
0
0 pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF pF
Typical Design Performance
The following section describes the typical design performance for the Arria GX device family.
User I/O Pin Timing
through Table 4–77 show user I/O pin timing for Arria GX devices. I/O
buffer t
SU
, t
H
, and t
CO
are reported for the cases when I/O clock is driven by a non-PLL global clock (GCLK) and a PLL driven global clock (GCLK-PLL). For t and t
SU
, t
H
,
CO
using regional clock, add the value from the adder tables listed for each device to the GCLK/GCLK-PLL values for the device.
EP1AGX20 I/O Timing Parameters
through Table 4–51 show the maximum I/O timing parameters for
EP1AGX20 devices for I/O standards which support general purpose I/O pins.
Table 4–48 describes the row pin delay adders when using the regional clock in
Arria GX devices.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–48. EP1AGX20 Row Pin Delay Adders for Regional Clock
Fast Corner
Parameter
–6 Speed
Grade
Industrial
0.117
Commercial
0.117
0.273
RCLK
input adder
RCLK
PLL input adder
RCLK output adder
RCLK
PLL output adder
0.011
–0.117
–0.011
0.011
–0.117
–0.011
0.019
–0.273
–0.019
describes I/O timing specifications.
Table 4–49. EP1AGX20 Column Pins Input Timing Parameters (Part 1 of 3)
Fast Corner
I/O Standard
Clock Parameter
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5 V
SSTL-2 CLASS I
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL t t t t t t
SU t t
H
SU
H t
SU t
SU
H t
SU t
H t
SU
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
H
SU
H t
SU t
H
–1.225
2.772
–2.667
1.075
–0.970
2.517
–2.412
–1.156
2.703
–2.598
1.327
–1.222
2.769
–2.664
1.330
Industrial
1.251
–1.146
2.693
–2.588
1.251
–1.146
2.693
–2.588
1.261
–1.225
2.772
–2.667
1.075
–0.970
2.517
–2.412
–1.156
2.703
–2.598
1.327
–1.222
2.769
–2.664
1.330
Commercial
1.251
–1.146
2.693
–2.588
1.251
–1.146
2.693
–2.588
1.261
Units
ns ns ns ns
–6 Speed
Grade
–2.830
6.213
–5.936
3.200
–2.923
6.306
–6.029
2.372
–2.095
5.480
–5.203
2.915
–2.638
6.021
–5.744
2.915
–2.638
6.021
–5.744
2.897
–2.620
6.003
–5.726
3.107
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
4–33
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–34 Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–49. EP1AGX20 Column Pins Input Timing Parameters (Part 2 of 3)
Fast Corner
I/O Standard
Clock Parameter
SSTL-2 CLASS II
SSTL-18 CLASS I
SSTL-18 CLASS II
1.8-V HSTL CLASS I
1.8-V HSTL CLASS II
1.5-V HSTL CLASS I
1.5-V HSTL CLASS II
3.3-V PCI
3.3-V PCI-X
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
Industrial
–2.468
1.132
–1.027
2.574
–2.469
1.256
–1.151
2.698
–2.450
1.114
–1.009
2.556
–2.451
1.131
–1.026
2.573
–2.450
1.114
–1.009
2.556
–2.451
1.113
–1.008
2.555
1.075
–0.970
2.517
–2.412
1.113
–1.008
2.555
–2.593
1.256
–1.151
2.698
–2.593
Commercial
–2.468
1.132
–1.027
2.574
–2.469
1.256
–1.151
2.698
–2.450
1.114
–1.009
2.556
–2.451
1.131
–1.026
2.573
–2.450
1.114
–1.009
2.556
–2.451
1.113
–1.008
2.555
1.075
–0.970
2.517
–2.412
1.113
–1.008
2.555
–2.593
1.256
–1.151
2.698
–2.593
t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H
–6 Speed
Grade
–5.436
2.607
–2.330
5.715
–5.438
2.903
–2.626
6.009
–5.308
2.479
–2.202
5.587
–5.310
2.607
–2.330
5.713
–5.308
2.479
–2.202
5.587
–5.310
2.479
–2.202
5.585
2.372
–2.095
5.480
–5.203
2.479
–2.202
5.585
–5.732
2.903
–2.626
6.009
–5.732
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–49. EP1AGX20 Column Pins Input Timing Parameters (Part 3 of 3)
Fast Corner
I/O Standard
Clock Parameter
LVDS
GCLK
GCLK PLL t t
SU t t
H
SU
H
Industrial
1.106
–1.001
2.530
–2.425
Commercial
1.106
–1.001
2.530
–2.425
describes I/O timing specifications.
Table 4–50. EP1AGX20 Row Pins output Timing Parameters (Part 1 of 2)
Fast Model
I/O Standard
Drive
Strength
Clock Parameter
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V
LVCMOS
3.3-V
LVCMOS
2.5 V
2.5 V
2.5 V
1.8 V
1.8 V
1.8 V
1.8 V
1.5 V
1.5 V
4 mA
8 mA
12 mA
4 mA
8 mA
4 mA
8 mA
12 mA
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL t t t t t t t t t t
CO
CO t
CO t
CO t
CO
CO t
CO t
CO t
CO
CO t
CO t
CO t
CO
CO t
CO t
CO t
CO
CO t
CO t
CO
CO
CO t
CO t
CO
CO
CO t
CO t
CO
1.410
2.818
1.399
2.707
1.288
2.676
1.257
2.789
1.251
2.759
1.340
2.656
1.237
2.637
1.218
2.829
1.370
2.682
1.263
Industrial Commercial
2.904
2.904
1.485
2.776
1.357
2.720
1.301
2.776
1.357
2.670
1.485
2.776
1.357
2.720
1.301
2.776
1.357
2.670
1.410
2.818
1.399
2.707
1.288
2.676
1.257
2.789
1.251
2.759
1.340
2.656
1.237
2.637
1.218
2.829
1.370
2.682
1.263
–6 Speed
Grade
2.489
–2.212
5.564
–5.287
–6 Speed
Grade
2.900
5.858
2.786
6.551
3.479
5.950
2.878
2.703
5.661
2.589
7.052
3.980
6.273
3.201
5.972
6.699
3.627
6.059
2.987
6.022
2.950
6.059
2.987
5.753
2.681
6.033
2.961
5.775
Units
ns ns ns ns
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
4–35
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–36 Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–50. EP1AGX20 Row Pins output Timing Parameters (Part 2 of 2)
Fast Model
I/O Standard
Drive
Strength
Clock Parameter
SSTL-2
CLASS I
SSTL-2
CLASS I
SSTL-2
CLASS II
SSTL-18
CLASS I
SSTL-18
CLASS I
SSTL-18
CLASS I
SSTL-18
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
LVDS
8 mA
12 mA
16 mA
4 mA
6 mA
8 mA
10 mA
4 mA
6 mA
8 mA
10 mA
12 mA
4 mA
6 mA
8 mA
—
Industrial Commercial
1.156
2.594
1.175
2.597
1.178
2.582
1.163
2.654
1.226
1.176
2.598
1.179
2.580
1.161
2.584
1.165
2.575
1.195
2.618
1.199
2.594
1.175
2.597
1.178
2.595
2.626
1.207
2.602
1.183
2.568
1.149
2.614
1.156
2.594
1.175
2.597
1.178
2.582
1.163
2.654
1.226
1.176
2.598
1.179
2.580
1.161
2.584
1.165
2.575
1.195
2.618
1.199
2.594
1.175
2.597
1.178
2.595
2.626
1.207
2.602
1.183
2.568
1.149
2.614
t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
–6 Speed
Grade
2.342
5.443
2.371
5.429
2.357
5.421
2.349
5.613
2.530
2.394
5.430
2.358
5.426
2.354
5.415
2.343
5.414
2.484
5.485
2.413
5.468
2.396
5.447
2.375
5.466
5.614
2.542
5.538
2.466
5.407
2.335
5.556
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
describes I/O timing specifications.
Table 4–51. EP1AGX20 Column Pins Output Timing Parameters (Part 1 of 4)
Fast Corner
I/O Standard
Drive
Strength
Clock Parameter
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V
LVCMOS
3.3-V
LVCMOS
3.3-V
LVCMOS
3.3-V
LVCMOS
3.3-V
LVCMOS
3.3-V
LVCMOS
2.5 V
2.5 V
2.5 V
2.5 V
1.8 V
1.8 V
4 mA
8 mA
12 mA
16 mA
20 mA
24 mA
4 mA
8 mA
12 mA
16 mA
20 mA
24 mA
4 mA
8 mA
12 mA
16 mA
2 mA
4 mA
Industrial Commercial
2.726
1.284
2.674
1.232
2.653
1.211
2.635
1.193
2.644
1.202
2.651
1.209
2.638
1.196
2.627
1.185
2.766
1.324
2.771
1.329
2.649
1.207
2.642
1.200
2.764
1.322
2.672
1.230
2.909
1.467
2.764
1.322
2.697
1.255
2.671
1.229
2.726
1.284
2.674
1.232
2.653
1.211
2.635
1.193
2.644
1.202
2.651
1.209
2.638
1.196
2.627
1.185
2.766
1.324
2.771
1.329
2.649
1.207
2.642
1.200
2.764
1.322
2.672
1.230
2.909
1.467
2.764
1.322
2.697
1.255
2.671
1.229
t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
–6 Speed
Grade
6.201
3.095
5.939
2.833
5.822
2.716
5.748
2.642
5.796
2.690
5.764
2.658
5.746
2.640
5.724
2.618
7.193
4.087
6.419
3.313
5.875
2.769
5.877
2.771
6.169
3.063
5.874
2.768
6.541
3.435
6.169
3.063
6.169
3.063
6.000
2.894
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
4–37
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–38 Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–51. EP1AGX20 Column Pins Output Timing Parameters (Part 2 of 4)
Fast Corner
I/O Standard
Drive
Strength
Clock Parameter
1.8 V
1.8 V
1.8 V
1.8 V
1.5 V
1.5 V
1.5 V
1.5 V
SSTL-2
CLASS I
SSTL-2
CLASS I
SSTL-2
CLASS II
SSTL-2
CLASS II
SSTL-2
CLASS II
SSTL-18
CLASS I
SSTL-18
CLASS I
SSTL-18
CLASS I
SSTL-18
CLASS I
SSTL-18
CLASS I
SSTL-18
CLASS II
6 mA
8 mA
10 mA
12 mA
2 mA
4 mA
6 mA
8 mA
8 mA
12 mA
16 mA
20 mA
24 mA
4 mA
6 mA
8 mA
10 mA
12 mA
8 mA
Industrial Commercial
1.146
2.587
1.142
2.626
1.184
2.630
1.185
2.609
1.202
2.629
1.184
2.612
1.167
2.590
1.145
2.591
1.164
2.614
1.169
2.608
1.163
2.597
1.152
1.210
2.746
1.304
2.682
1.240
2.685
1.243
2.644
2.695
1.253
2.697
1.255
2.651
1.209
2.652
1.146
2.587
1.142
2.626
1.184
2.630
1.185
2.609
1.202
2.629
1.184
2.612
1.167
2.590
1.145
2.591
1.164
2.614
1.169
2.608
1.163
2.597
1.152
1.210
2.746
1.304
2.682
1.240
2.685
1.243
2.644
2.695
1.253
2.697
1.255
2.651
1.209
2.652
t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
–6 Speed
Grade
2.514
5.624
2.512
5.733
2.627
5.694
2.582
5.675
2.877
5.762
2.650
5.712
2.600
5.639
2.527
5.626
2.563
5.673
2.561
5.659
2.547
5.625
2.513
2.824
6.723
3.617
6.154
3.048
6.036
2.930
5.983
6.155
3.049
6.064
2.958
5.987
2.881
5.930
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–51. EP1AGX20 Column Pins Output Timing Parameters (Part 3 of 4)
Fast Corner
I/O Standard
Drive
Strength
Clock Parameter
SSTL-18
CLASS II
SSTL-18
CLASS II
SSTL-18
CLASS II
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS II
1.8-V HSTL
CLASS II
1.8-V HSTL
CLASS II
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS II
1.5-V HSTL
CLASS II
1.5-V HSTL
CLASS II
16 mA
18 mA
20 mA
4 mA
6 mA
8 mA
10 mA
12 mA
16 mA
18 mA
20 mA
4 mA
6 mA
8 mA
10 mA
12 mA
16 mA
18 mA
20 mA
Industrial Commercial
1.187
2.633
1.188
2.615
1.170
2.615
1.170
2.609
1.163
2.591
1.146
2.593
1.148
2.593
1.148
2.629
1.164
2.596
1.151
2.599
1.154
2.601
1.156
1.187
2.634
1.189
2.612
1.167
2.616
1.171
2.608
2.609
1.164
2.605
1.160
2.605
1.160
2.629
1.187
2.633
1.188
2.615
1.170
2.615
1.170
2.609
1.163
2.591
1.146
2.593
1.148
2.593
1.148
2.629
1.164
2.596
1.151
2.599
1.154
2.601
1.156
1.187
2.634
1.189
2.612
1.167
2.616
1.171
2.608
2.609
1.164
2.605
1.160
2.605
1.160
2.629
t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
–6 Speed
Grade
2.557
5.641
2.529
5.643
2.531
5.645
2.533
5.643
2.525
5.401
2.289
5.412
2.300
5.421
2.309
5.663
2.531
5.455
2.343
5.465
2.353
5.478
2.366
2.558
5.649
2.537
5.638
2.526
5.644
2.532
5.637
5.603
2.491
5.611
2.499
5.609
2.497
5.664
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
4–39
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–40 Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–51. EP1AGX20 Column Pins Output Timing Parameters (Part 4 of 4)
Fast Corner
I/O Standard
Drive
Strength
Clock Parameter
3.3-V PCI
3.3-V PCI-X
LVDS
—
—
—
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL t t t
CO t
CO
CO
CO t
CO t
CO
Industrial Commercial
2.755
1.313
2.755
1.313
3.621
2.190
2.755
1.313
2.755
1.313
3.621
2.190
–6 Speed
Grade
5.791
2.685
5.791
2.685
6.969
3.880
Units
ns ns ns ns ns ns
Table 4–52 through Table 4–53 list EP1AGX20 regional clock (RCLK) adder values that
should be added to GCLK values. These adder values are used to determine I/O timing when the I/O pin is driven using the regional clock. This applies for all I/O standards supported by Arria GX with general purpose I/O pins.
Table 4–52 describes row pin delay adders when using the regional clock in Arria GX
devices.
Table 4–52. EP1AGX20 Row Pin Delay Adders for Regional Clock
Fast Corner
Parameter –6 Speed Grade
RCLK
RCLK
RCLK
RCLK
input adder
PLL input adder
output adder
PLL output adder
Industrial
0.117
0.011
–0.117
–0.011
Commercial
0.117
0.011
–0.117
–0.011
0.273
0.019
–0.273
–0.019
Units
ns ns ns ns
Table 4–53 lists column pin delay adders when using the regional clock in Arria GX
devices.
Table 4–53. EP1AGX20 Column Pin Delay Adders for Regional Clock
Fast Corner
Parameter –6 Speed Grade
RCLK adder
input adder
RCLK
PLL input
RCLK
output adder
RCLK
PLL output adder
Industrial
0.081
–0.012
–0.081
1.11
Commercial
0.081
–0.012
–0.081
1.11
0.223
–0.008
–0.224
2.658
Units
ns ns ns ns
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
EP1AGX35 I/O Timing Parameters
through Table 4–57 list the maximum I/O timing parameters for
EP1AGX35 devices for I/O standards which support general purpose I/O pins.
Table 4–54 lists I/O timing specifications.
Table 4–54. EP1AGX35 Row Pins Input Timing Parameters (Part 1 of 2)
Fast Model
I/O Standard Clock Parameter
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5 V
SSTL-2 CLASS I
SSTL-2 CLASS II
SSTL-18 CLASS I
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL t t t t t t t t t
SU t
H t
SU t
H
SU t
H t
SU t
H
SU t
H t
SU t
H
SU t
H t
SU t
H
SU t
H t
SU t
H
SU t
H t
SU t
H
SU t
H t
SU
H
SU t
H t
SU t
H
Industrial
1.385
–1.280
2.804
–2.699
1.417
–1.312
2.836
–2.731
1.642
–1.537
3.061
–2.956
1.385
–1.280
2.804
–2.699
1.573
–1.468
2.992
–2.887
1.639
–1.534
3.058
–2.953
1.561
–1.456
2.980
–2.875
1.561
–1.456
2.980
–2.875
Commercial
1.385
–1.280
2.804
–2.699
1.417
–1.312
2.836
–2.731
1.642
–1.537
3.061
–2.956
1.385
–1.280
2.804
–2.699
1.573
–1.468
2.992
–2.887
1.639
–1.534
3.058
–2.953
1.561
–1.456
2.980
–2.875
1.561
–1.456
2.980
–2.875
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
–6 Speed
Grade
3.009
–2.732
6.081
–5.804
3.118
–2.841
6.190
–5.913
3.839
–3.562
6.911
–6.634
3.009
–2.732
6.081
–5.804
3.537
–3.260
6.609
–6.332
3.744
–3.467
6.816
–6.539
3.556
–3.279
6.628
–6.351
3.556
–3.279
6.628
–6.351
4–41
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–42 Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–54. EP1AGX35 Row Pins Input Timing Parameters (Part 2 of 2)
Fast Model
I/O Standard Clock Parameter
SSTL-18 CLASS II
1.8-V HSTL CLASS I
1.8-V HSTL CLASS II
1.5-V HSTL CLASS I
1.5-V HSTL CLASS II
LVDS
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL t t t
SU t t t t
H t
SU
H t
SU t t
H t
SU
H t
SU t t
H t
SU
H t
SU t t
H t
SU
H t
SU t
H t
SU t
H
SU
H
SU
H
Industrial
–2.731
1.417
–1.312
2.836
–2.731
1.443
–1.338
2.862
1.417
–1.312
2.836
–2.731
1.417
–1.312
2.836
–2.757
1.443
–1.338
2.862
–2.757
1.341
–1.236
2.769
–2.664
Commercial
–2.731
1.417
–1.312
2.836
–2.731
1.443
–1.338
2.862
1.417
–1.312
2.836
–2.731
1.417
–1.312
2.836
–2.757
1.443
–1.338
2.862
–2.757
1.341
–1.236
2.769
–2.664
lists I/O timing specifications.
Table 4–55. EP1AGX35 Column Pins Input Timing Parameters (Part 1 of 3)
Fast Corner
I/O Standard Clock Parameter
3.3-V LVTTL
3.3-V LVCMOS
GCLK
GCLK PLL
GCLK
GCLK PLL t t t t
SU
H t
SU t
H t
SU t
H
SU
H
Industrial
1.251
–1.146
2.693
–2.588
1.251
–1.146
2.693
–2.588
Commercial
1.251
–1.146
2.693
–2.588
1.251
–1.146
2.693
–2.588
–6 Speed
Grade
–5.913
3.118
–2.841
6.190
–5.913
3.246
–2.969
6.318
3.118
–2.841
6.190
–5.913
3.118
–2.841
6.190
–6.041
3.246
–2.969
6.318
–6.041
3.088
–2.811
6.171
–5.894
–6 Speed
Grade
2.915
–2.638
6.021
–5.744
2.915
–2.638
6.021
–5.744
Units
ns ns ns ns ns ns ns ns
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–55. EP1AGX35 Column Pins Input Timing Parameters (Part 2 of 3)
Fast Corner
I/O Standard Clock Parameter
2.5 V
1.8 V
1.5 V
SSTL-2 CLASS I
SSTL-2 CLASS II
SSTL-18 CLASS I
SSTL-18 CLASS II
1.8-V HSTL CLASS I
1.8-V HSTL CLASS II
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
Industrial
–2.450
1.114
–1.009
2.556
–2.451
1.113
–1.008
2.555
–2.412
1.075
–0.970
2.517
–2.412
1.113
–1.008
2.555
–2.664
1.330
–1.225
2.772
–2.667
1.075
–0.970
2.517
1.261
–1.156
2.703
–2.598
1.327
–1.222
2.769
–2.450
1.114
–1.009
2.556
–2.451
Commercial
–2.450
1.114
–1.009
2.556
–2.451
1.113
–1.008
2.555
–2.412
1.075
–0.970
2.517
–2.412
1.113
–1.008
2.555
–2.664
1.330
–1.225
2.772
–2.667
1.075
–0.970
2.517
1.261
–1.156
2.703
–2.598
1.327
–1.222
2.769
–2.450
1.114
–1.009
2.556
–2.451
t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H
–6 Speed
Grade
–5.308
2.479
–2.202
5.587
–5.310
2.479
–2.202
5.585
–5.203
2.372
–2.095
5.480
–5.203
2.479
–2.202
5.585
–5.936
3.200
–2.923
6.306
–6.029
2.372
–2.095
5.480
2.897
–2.620
6.003
–5.726
3.107
–2.830
6.213
–5.308
2.479
–2.202
5.587
–5.310
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
4–43
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–44 Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–55. EP1AGX35 Column Pins Input Timing Parameters (Part 3 of 3)
Fast Corner
I/O Standard Clock Parameter
1.5-V HSTL CLASS I
1.5-V HSTL CLASS II
3.3-V PCI
3.3-V PCI-X
LVDS
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL t t t t t t
H t
SU t
H t
SU t
SU t
H t
SU t
H t
SU t
H t
SU
H t
SU t
H t
SU t
H
SU
H
SU
H
Industrial
–2.469
1.256
–1.151
2.698
–2.593
1.256
–1.151
2.698
1.131
–1.026
2.573
–2.468
1.132
–1.027
2.574
–2.593
1.106
–1.001
2.530
–2.425
Commercial
–2.469
1.256
–1.151
2.698
–2.593
1.256
–1.151
2.698
1.131
–1.026
2.573
–2.468
1.132
–1.027
2.574
–2.593
1.106
–1.001
2.530
–2.425
lists I/O timing specifications.
Table 4–56. EP1AGX35 Row Pins Output Timing Parameters (Part 1 of 3)
Fast Model
I/O Standard
Drive
Strength
Clock Parameter
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V
LVCMOS
3.3-V
LVCMOS
2.5 V
4 mA
8 mA
12 mA
4 mA
8 mA
4 mA
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL t t t t t
CO
CO t
CO t
CO t
CO
CO t
CO t
CO
CO
CO t
CO t
CO
Industrial Commercial
2.904
2.904
1.485
2.776
1.357
2.720
1.301
2.776
1.357
2.670
1.251
2.759
1.340
1.251
2.759
1.340
1.485
2.776
1.357
2.720
1.301
2.776
1.357
2.670
–6 Speed
Grade
–5.438
2.903
–2.626
6.009
–5.732
2.903
–2.626
6.009
2.607
–2.330
5.713
–5.436
2.607
–2.330
5.715
–5.732
2.489
–2.212
5.564
–5.287
–6 Speed
Grade
6.699
3.627
6.059
2.987
6.022
2.950
6.059
2.987
5.753
2.681
6.033
2.961
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Units
ns ns ns ns ns ns ns ns ns ns ns ns
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–56. EP1AGX35 Row Pins Output Timing Parameters (Part 2 of 3)
Fast Model
I/O Standard
Drive
Strength
Clock Parameter
2.5 V
2.5 V
1.8 V
1.8 V
1.8 V
1.8 V
1.5 V
1.5 V
SSTL-2
CLASS I
SSTL-2
CLASS I
SSTL-2
CLASS II
SSTL-18
CLASS I
SSTL-18
CLASS I
SSTL-18
CLASS I
SSTL-18
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
8 mA
12 mA
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
8 mA
12 mA
16 mA
4 mA
6 mA
8 mA
10 mA
4 mA
6 mA
8 mA
10 mA
Industrial Commercial
1.195
2.618
1.199
2.594
1.175
2.597
1.178
2.595
1.263
2.626
1.207
2.602
1.183
2.568
1.149
2.614
1.176
2.598
1.179
2.580
1.161
2.584
1.165
1.399
2.707
1.288
2.676
1.257
2.789
1.370
2.682
2.656
1.237
2.637
1.218
2.829
1.410
2.818
1.195
2.618
1.199
2.594
1.175
2.597
1.178
2.595
1.263
2.626
1.207
2.602
1.183
2.568
1.149
2.614
1.176
2.598
1.179
2.580
1.161
2.584
1.165
1.399
2.707
1.288
2.676
1.257
2.789
1.370
2.682
2.656
1.237
2.637
1.218
2.829
1.410
2.818
t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
–6 Speed
Grade
2.484
5.485
2.413
5.468
2.396
5.447
2.375
5.466
2.878
5.614
2.542
5.538
2.466
5.407
2.335
5.556
2.394
5.430
2.358
5.426
2.354
5.415
2.343
3.201
5.972
2.900
5.858
2.786
6.551
3.479
5.950
5.775
2.703
5.661
2.589
7.052
3.980
6.273
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
4–45
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–46 Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–56. EP1AGX35 Row Pins Output Timing Parameters (Part 3 of 3)
Fast Model
I/O Standard
Drive
Strength
Clock Parameter
1.8-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
LVDS
12 mA
4 mA
6 mA
8 mA
—
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL t t t t t
CO t
CO
CO
CO t
CO t
CO
CO
CO t
CO t
CO
Industrial Commercial
2.575
1.156
2.594
1.175
2.597
1.178
2.582
1.163
2.654
1.226
2.575
1.156
2.594
1.175
2.597
1.178
2.582
1.163
2.654
1.226
lists I/O timing specifications.
Table 4–57. EP1AGX35 Column Pins Output Timing Parameters (Part 1 of 4)
Fast Corner
I/O Standard
Drive
Strength
Clock Parameter
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V
LVCMOS
3.3-V
LVCMOS
3.3-V
LVCMOS
3.3-V
LVCMOS
3.3-V
LVCMOS
4 mA
8 mA
12 mA
16 mA
20 mA
24 mA
4 mA
8 mA
12 mA
16 mA
20 mA
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL t t t t t t t t
CO t
CO t
CO
CO t
CO t
CO t
CO
CO t
CO t
CO t
CO
CO t
CO t
CO
CO
CO t
CO t
CO
CO
CO t
CO t
CO
Industrial Commercial
1.229
2.649
1.207
2.642
1.200
2.764
1.322
2.672
2.909
1.467
2.764
1.322
2.697
1.255
2.671
1.230
2.644
1.202
2.651
1.209
2.638
1.196
1.229
2.649
1.207
2.642
1.200
2.764
1.322
2.672
2.909
1.467
2.764
1.322
2.697
1.255
2.671
1.230
2.644
1.202
2.651
1.209
2.638
1.196
–6 Speed
Grade
5.414
2.342
5.443
2.371
5.429
2.357
5.421
2.349
5.613
2.530
–6 Speed
Grade
2.894
5.875
2.769
5.877
2.771
6.169
3.063
5.874
6.541
3.435
6.169
3.063
6.169
3.063
6.000
2.768
5.796
2.690
5.764
2.658
5.746
2.640
Units
ns ns ns ns ns ns ns ns ns ns
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–57. EP1AGX35 Column Pins Output Timing Parameters (Part 2 of 4)
Fast Corner
I/O Standard
Drive
Strength
Clock Parameter
3.3-V
LVCMOS
2.5 V
2.5 V
2.5 V
2.5 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.5 V
1.5 V
1.5 V
1.5 V
SSTL-2
CLASS I
SSTL-2
CLASS I
SSTL-2
CLASS II
SSTL-2
CLASS II
24 mA
4 mA
8 mA
12 mA
16 mA
2 mA
4 mA
6 mA
8 mA
10 mA
12 mA
2 mA
4 mA
6 mA
8 mA
8 mA
12 mA
16 mA
20 mA
Industrial Commercial
1.304
2.682
1.240
2.685
1.243
2.644
1.202
2.629
1.253
2.697
1.255
2.651
1.209
2.652
1.210
2.746
1.184
2.612
1.167
2.590
1.145
2.591
1.146
1.211
2.635
1.193
2.766
1.324
2.771
1.329
2.695
2.627
1.185
2.726
1.284
2.674
1.232
2.653
1.304
2.682
1.240
2.685
1.243
2.644
1.202
2.629
1.253
2.697
1.255
2.651
1.209
2.652
1.210
2.746
1.184
2.612
1.167
2.590
1.145
2.591
1.146
1.211
2.635
1.193
2.766
1.324
2.771
1.329
2.695
2.627
1.185
2.726
1.284
2.674
1.232
2.653
t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
–6 Speed
Grade
3.617
6.154
3.048
6.036
2.930
5.983
2.877
5.762
3.049
6.064
2.958
5.987
2.881
5.930
2.824
6.723
2.650
5.712
2.600
5.639
2.527
5.626
2.514
2.716
5.748
2.642
7.193
4.087
6.419
3.313
6.155
5.724
2.618
6.201
3.095
5.939
2.833
5.822
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
4–47
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–48 Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–57. EP1AGX35 Column Pins Output Timing Parameters (Part 3 of 4)
Fast Corner
I/O Standard
Drive
Strength
Clock Parameter
SSTL-2
CLASS II
SSTL-18
CLASS I
SSTL-18
CLASS I
SSTL-18
CLASS I
SSTL-18
CLASS I
SSTL-18
CLASS I
SSTL-18
CLASS II
SSTL-18
CLASS II
SSTL-18
CLASS II
SSTL-18
CLASS II
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS II
1.8-V HSTL
CLASS II
1.8-V HSTL
CLASS II
1.5-V HSTL
CLASS I
24 mA
4 mA
6 mA
8 mA
10 mA
12 mA
8 mA
16 mA
18 mA
20 mA
4 mA
6 mA
8 mA
10 mA
12 mA
16 mA
18 mA
20 mA
4 mA
Industrial Commercial
1.189
2.612
1.167
2.616
1.171
2.608
1.163
2.591
1.164
2.605
1.160
2.605
1.160
2.629
1.187
2.634
1.146
2.593
1.148
2.593
1.148
2.629
1.187
1.164
2.614
1.169
2.608
1.163
2.597
1.152
2.609
2.587
1.142
2.626
1.184
2.630
1.185
2.609
1.189
2.612
1.167
2.616
1.171
2.608
1.163
2.591
1.164
2.605
1.160
2.605
1.160
2.629
1.187
2.634
1.146
2.593
1.148
2.593
1.148
2.629
1.187
1.164
2.614
1.169
2.608
1.163
2.597
1.152
2.609
2.587
1.142
2.626
1.184
2.630
1.185
2.609
t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
–6 Speed
Grade
2.537
5.638
2.526
5.644
2.532
5.637
2.525
5.401
2.491
5.611
2.499
5.609
2.497
5.664
2.558
5.649
2.289
5.412
2.300
5.421
2.309
5.663
2.557
2.563
5.673
2.561
5.659
2.547
5.625
2.513
5.603
5.624
2.512
5.733
2.627
5.694
2.582
5.675
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–49
Table 4–57. EP1AGX35 Column Pins Output Timing Parameters (Part 4 of 4)
Fast Corner
I/O Standard
Drive
Strength
Clock Parameter
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS II
1.5-V HSTL
CLASS II
1.5-V HSTL
CLASS II
3.3-V PCI
3.3-V PCI-X
LVDS
6 mA
8 mA
10 mA
12 mA
16 mA
18 mA
20 mA
—
—
—
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL t t t t t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO
CO t
CO t
CO t
CO
CO t
CO t
CO
CO
CO
Industrial Commercial
1.164
2.596
1.151
2.599
1.154
2.601
1.156
2.755
2.633
1.188
2.615
1.170
2.615
1.170
2.609
1.313
2.755
1.313
3.621
2.190
1.164
2.596
1.151
2.599
1.154
2.601
1.156
2.755
2.633
1.188
2.615
1.170
2.615
1.170
2.609
1.313
2.755
1.313
3.621
2.190
Units
through Table 4–59 list EP1AGX35 regional clock (RCLK) adder values that
should be added to GCLK values. These adder values are used to determine I/O timing when the I/O pin is driven using the regional clock. This applies for all I/O standards supported by Arria GX with general purpose I/O pins.
Table 4–58 describes row pin delay adders when using the regional clock in Arria GX
devices.
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
–6 Speed
Grade
2.531
5.455
2.343
5.465
2.353
5.478
2.366
5.791
5.641
2.529
5.643
2.531
5.645
2.533
5.643
2.685
5.791
2.685
6.969
3.880
Table 4–58. EP1AGX35 Row Pin Delay Adders for Regional Clock
Fast Corner
Parameter –6 Speed Grade
RCLK adder
input adder
RCLK
PLL input
RCLK
output adder
RCLK
PLL output adder
Industrial
0.126
0.011
–0.126
–0.011
Commercial
0.126
0.011
–0.126
–0.011
0.281
0.018
–0.281
–0.018
Units
ns ns ns ns
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–50 Chapter 4: DC and Switching Characteristics
Typical Design Performance
lists column pin delay adders when using the regional clock in Arria GX devices.
Table 4–59. EP1AGX35 Column Pin Delay Adders for Regional Clock
Fast Corner
Parameter –6 Speed Grade
RCLK
input adder
RCLK
PLL input adder
RCLK
output adder
RCLK
PLL output adder
Industrial
0.099
–0.012
–0.086
1.253
Commercial
0.099
–0.012
–0.086
1.253
0.254
–0.01
–0.244
3.133
Units
ns ns ns ns
EP1AGX50 I/O Timing Parameters
through Table 4–63 list the maximum I/O timing parameters for
EP1AGX50 devices for I/O standards which support general purpose I/O pins.
Table 4–60 lists I/O timing specifications.
Table 4–60. EP1AGX50 Row Pins Input Timing Parameters (Part 1 of 2)
Fast Model
I/O Standard Clock Parameter
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5 V
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL t t t t t t t t
SU
H t
SU t
H t
SU
H t
SU t t
H t
SU
H t
SU t
SU t t t
H
H
SU
H
SU
H
SU
H
–1.457
2.990
–2.885
1.628
–1.523
3.056
–2.951
1.631
–1.526
3.059
–2.954
Industrial
1.550
–1.445
2.978
–2.873
1.550
–1.445
2.978
–2.873
1.562
–1.457
2.990
–2.885
1.628
–1.523
3.056
–2.951
1.631
–1.526
3.059
–2.954
Commercial
1.550
–1.445
2.978
–2.873
1.550
–1.445
2.978
–2.873
1.562
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
–6 Speed
Grade
3.542
–3.265
6.626
–6.349
3.542
–3.265
6.626
–6.349
3.523
–3.246
6.607
–6.330
3.730
–3.453
6.814
–6.537
3.825
–3.548
6.909
–6.632
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–60. EP1AGX50 Row Pins Input Timing Parameters (Part 2 of 2)
Fast Model
I/O Standard Clock Parameter
I
SSTL-2 CLASS
SSTL-2 CLASS
II
SSTL-18
CLASS I
SSTL-18
CLASS II
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS II
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS II
LVDS
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
Industrial
–2.729
1.432
–1.327
2.860
–2.755
1.433
–1.328
2.860
–2.729
1.406
–1.301
2.834
–2.729
1.407
–1.302
2.834
–2.697
1.406
–1.301
2.834
–2.729
1.407
–1.302
2.834
1.375
–1.270
2.802
–2.697
1.375
–1.270
2.802
–2.755
1.341
–1.236
2.769
–2.664
Commercial
–2.729
1.432
–1.327
2.860
–2.755
1.433
–1.328
2.860
–2.729
1.406
–1.301
2.834
–2.729
1.407
–1.302
2.834
–2.697
1.406
–1.301
2.834
–2.729
1.407
–1.302
2.834
1.375
–1.270
2.802
–2.697
1.375
–1.270
2.802
–2.755
1.341
–1.236
2.769
–2.664
t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H
–6 Speed
Grade
–5.911
3.232
–2.955
6.316
–6.039
3.234
–2.957
6.316
–5.911
3.104
–2.827
6.188
–5.911
3.106
–2.829
6.188
–5.802
3.104
–2.827
6.188
–5.911
3.106
–2.829
6.188
2.997
–2.720
6.079
–5.802
2.997
–2.720
6.079
–6.039
3.088
–2.811
6.171
–5.894
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
4–51
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–52 Chapter 4: DC and Switching Characteristics
Typical Design Performance
lists I/O timing specifications.
Table 4–61. EP1AGX50 Column Pins Input Timing Parameters (Part 1 of 2)
Fast Corner
I/O Standard Clock Parameter
3.3-V LVTTL
3.3-V
LVCMOS
2.5 V
1.8 V
1.5 V
SSTL-2
CLASS I
SSTL-2
CLASS II
SSTL-18
CLASS I
SSTL-18
CLASS II
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
Industrial
1.034
–0.929
2.500
–2.395
1.104
–0.999
2.546
–2.441
1.321
–1.216
2.763
–2.658
1.034
–0.929
2.500
–2.395
1.074
–0.969
2.539
–2.434
1.252
–1.147
2.694
–2.589
1.318
–1.213
2.760
–2.655
1.242
–1.137
2.684
–2.579
1.242
–1.137
2.684
–2.579
Commercial
1.034
–0.929
2.500
–2.395
1.104
–0.999
2.546
–2.441
1.321
–1.216
2.763
–2.658
1.034
–0.929
2.500
–2.395
1.074
–0.969
2.539
–2.434
1.252
–1.147
2.694
–2.589
1.318
–1.213
2.760
–2.655
1.242
–1.137
2.684
–2.579
1.242
–1.137
2.684
–2.579
t
H t
SU t
H t
SU t
H t
SU t
H t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
SU t
H t
SU t
H t
SU
–6 Speed
Grade
2.314
–2.037
5.457
–5.180
2.466
–2.189
5.573
–5.296
3.187
–2.910
6.294
–6.017
2.314
–2.037
5.457
–5.180
2.424
–2.147
5.564
–5.287
2.884
–2.607
5.991
–5.714
3.094
–2.817
6.201
–5.924
2.902
–2.625
6.009
–5.732
2.902
–2.625
6.009
–5.732
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–61. EP1AGX50 Column Pins Input Timing Parameters (Part 2 of 2)
Fast Corner
I/O Standard Clock Parameter
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS II
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS II
3.3-V PCI
3.3-V PCI-X
LVDS
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL t t t t
H t
SU t
H t
SU t
SU t
H t
SU t
H t
H t
SU t
H t
SU t
SU t
H t
SU t
H t
SU t
H t
SU
H t
SU t
H t
SU t
H t
SU t
H
SU
H
Industrial
–2.452
1.247
–1.142
2.689
–2.584
1.247
–1.142
2.689
–2.584
1.106
–1.001
2.530
–2.425
–2.434
1.122
–1.017
2.564
–2.459
1.094
–0.989
2.557
1.104
–0.999
2.546
–2.441
1.074
–0.969
2.539
Commercial
–2.452
1.247
–1.142
2.689
–2.584
1.247
–1.142
2.689
–2.584
1.106
–1.001
2.530
–2.425
–2.434
1.122
–1.017
2.564
–2.459
1.094
–0.989
2.557
1.104
–0.999
2.546
–2.441
1.074
–0.969
2.539
lists I/O timing specifications.
Table 4–62. EP1AGX50 Row Pins Output Timing Parameters (Part 1 of 3)
Fast Model
I/O Standard
Drive
Strength
Clock Parameter
3.3-V LVTTL
3.3-V LVTTL
4 mA
8 mA
GCLK
GCLK PLL
GCLK
GCLK PLL t t t t
CO
CO
CO
CO
Industrial Commercial
2.915
2.915
1.487
2.787
1.359
1.487
2.787
1.359
–6 Speed
Grade
–5.415
2.890
–2.613
5.997
–5.720
2.890
–2.613
5.997
–5.720
2.489
–2.212
5.564
–5.287
–5.287
2.594
–2.317
5.701
–5.424
2.557
–2.280
5.692
2.466
–2.189
5.573
–5.296
2.424
–2.147
5.564
–6 Speed
Grade
6.713
3.629
6.073
2.989
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Units
ns ns ns ns
4–53
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–54 Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–62. EP1AGX50 Row Pins Output Timing Parameters (Part 2 of 3)
Fast Model
I/O Standard
Drive
Strength
Clock Parameter
3.3-V LVTTL
3.3-V
LVCMOS
3.3-V
LVCMOS
2.5 V
2.5 V
2.5 V
1.8 V
1.8 V
1.8 V
1.8 V
1.5 V
1.5 V
SSTL-2
CLASS I
SSTL-2
CLASS I
SSTL-2
CLASS II
SSTL-18
CLASS I
SSTL-18
CLASS I
SSTL-18
CLASS I
SSTL-18
CLASS I
12 mA
4 mA
8 mA
4 mA
8 mA
12 mA
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
8 mA
12 mA
16 mA
4 mA
6 mA
8 mA
10 mA
Industrial Commercial
1.265
2.636
1.209
2.612
1.185
2.578
1.151
2.625
1.401
2.718
1.290
2.687
1.259
2.800
1.372
2.693
1.197
2.628
1.201
2.604
1.177
2.607
1.180
1.342
2.667
1.239
2.648
1.220
2.840
1.412
2.829
2.731
1.303
2.787
1.359
2.681
1.253
2.770
1.265
2.636
1.209
2.612
1.185
2.578
1.151
2.625
1.401
2.718
1.290
2.687
1.259
2.800
1.372
2.693
1.197
2.628
1.201
2.604
1.177
2.607
1.180
1.342
2.667
1.239
2.648
1.220
2.840
1.412
2.829
2.731
1.303
2.787
1.359
2.681
1.253
2.770
t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
–6 Speed
Grade
2.880
5.626
2.544
5.550
2.468
5.419
2.337
5.570
3.203
5.986
2.902
5.872
2.788
6.565
3.481
5.964
2.486
5.497
2.415
5.480
2.398
5.459
2.377
2.963
5.789
2.705
5.675
2.591
7.066
3.982
6.287
6.036
2.952
6.073
2.989
5.767
2.683
6.047
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–62. EP1AGX50 Row Pins Output Timing Parameters (Part 3 of 3)
Fast Model
I/O Standard
Drive
Strength
Clock Parameter
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
LVDS
4 mA
6 mA
8 mA
10 mA
12 mA
4 mA
6 mA
8 mA
—
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL t t t t t t t
CO t
CO t
CO
CO t
CO t
CO t
CO
CO t
CO t
CO
CO
CO t
CO t
CO
CO
CO t
CO t
CO
Industrial Commercial
1.167
2.585
1.158
2.605
1.177
2.607
1.180
2.592
2.606
1.178
2.608
1.181
2.590
1.163
2.594
1.165
2.654
1.226
1.167
2.585
1.158
2.605
1.177
2.607
1.180
2.592
2.606
1.178
2.608
1.181
2.590
1.163
2.594
1.165
2.654
1.226
lists I/O timing specifications.
Table 4–63. EP1AGX50 Column Pins Output Timing Parameters (Part 1 of 4)
Fast Corner
I/O Standard
Drive
Strength
Clock Parameter
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V
LVCMOS
4 mA
8 mA
12 mA
16 mA
20 mA
24 mA
4 mA
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL t t t t t t
CO t
CO t
CO
CO t
CO t
CO
CO
CO t
CO t
CO
CO
CO t
CO t
CO
Industrial Commercial
1.238
2.670
1.216
2.660
1.209
2.797
1.331
2.948
1.476
2.797
1.331
2.722
1.264
2.694
1.238
2.670
1.216
2.660
1.209
2.797
1.331
2.948
1.476
2.797
1.331
2.722
1.264
2.694
–6 Speed
Grade
2.345
5.426
2.344
5.457
2.373
5.441
2.359
5.433
5.480
2.396
5.442
2.360
5.438
2.356
5.427
2.351
5.613
2.530
–6 Speed
Grade
2.906
5.896
2.781
5.895
2.783
6.203
3.075
6.608
3.447
6.203
3.075
6.204
3.075
6.024
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
4–55
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–56 Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–63. EP1AGX50 Column Pins Output Timing Parameters (Part 2 of 4)
Fast Corner
I/O Standard
Drive
Strength
Clock Parameter
3.3-V
LVCMOS
3.3-V
LVCMOS
3.3-V
LVCMOS
3.3-V
LVCMOS
3.3-V
LVCMOS
2.5 V
2.5 V
2.5 V
2.5 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.5 V
1.5 V
1.5 V
1.5 V
8 mA
12 mA
16 mA
20 mA
24 mA
4 mA
8 mA
12 mA
16 mA
2 mA
4 mA
6 mA
8 mA
10 mA
12 mA
2 mA
4 mA
6 mA
8 mA
Industrial Commercial
1.262
2.719
1.264
2.671
1.218
2.671
1.219
2.779
1.220
2.654
1.202
2.804
1.333
2.808
1.338
2.717
1.313
2.703
1.249
2.705
1.252
2.660
1.211
1.205
2.638
1.194
2.754
1.293
2.697
1.241
2.672
2.695
1.239
2.663
1.211
2.666
1.218
2.651
1.262
2.719
1.264
2.671
1.218
2.671
1.219
2.779
1.220
2.654
1.202
2.804
1.333
2.808
1.338
2.717
1.313
2.703
1.249
2.705
1.252
2.660
1.211
1.205
2.638
1.194
2.754
1.293
2.697
1.241
2.672
2.695
1.239
2.663
1.211
2.666
1.218
2.651
t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
–6 Speed
Grade
3.061
6.098
2.970
6.012
2.893
5.953
2.836
6.815
2.728
5.760
2.654
7.295
4.099
6.479
3.325
6.195
3.629
6.210
3.060
6.118
2.942
6.014
2.889
2.652
5.736
2.630
6.240
3.107
5.963
2.845
5.837
5.893
2.780
5.809
2.702
5.776
2.670
5.758
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–63. EP1AGX50 Column Pins Output Timing Parameters (Part 3 of 4)
Fast Corner
I/O Standard
Drive
Strength
Clock Parameter
SSTL-2
CLASS I
SSTL-2
CLASS I
SSTL-2
CLASS II
SSTL-2
CLASS II
SSTL-2
CLASS II
SSTL-18
CLASS I
SSTL-18
CLASS I
SSTL-18
CLASS I
SSTL-18
CLASS I
SSTL-18
CLASS I
SSTL-18
CLASS II
SSTL-18
CLASS II
SSTL-18
CLASS II
SSTL-18
CLASS II
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
8 mA
12 mA
16 mA
20 mA
24 mA
4 mA
6 mA
8 mA
10 mA
12 mA
8 mA
16 mA
18 mA
20 mA
4 mA
6 mA
8 mA
10 mA
12 mA
Industrial Commercial
1.182
2.616
1.178
2.616
1.178
2.637
1.196
2.645
1.182
2.630
1.187
2.625
1.181
2.614
1.170
2.623
1.207
2.623
1.185
2.627
1.189
2.619
1.181
1.164
2.601
1.160
2.643
1.193
2.649
1.203
2.626
2.648
1.202
2.628
1.185
2.606
1.163
2.606
1.182
2.616
1.178
2.616
1.178
2.637
1.196
2.645
1.182
2.630
1.187
2.625
1.181
2.614
1.170
2.623
1.207
2.623
1.185
2.627
1.189
2.619
1.181
1.164
2.601
1.160
2.643
1.193
2.649
1.203
2.626
2.648
1.202
2.628
1.185
2.606
1.163
2.606
t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
–6 Speed
Grade
2.516
5.621
2.524
5.619
2.522
5.676
2.570
5.659
2.588
5.685
2.586
5.669
2.572
5.635
2.538
5.613
2.562
5.648
2.551
5.654
2.557
5.647
2.550
2.539
5.634
2.537
5.749
2.639
5.708
2.607
5.686
5.777
2.675
5.722
2.625
5.649
2.552
5.636
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
4–57
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–58 Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–63. EP1AGX50 Column Pins Output Timing Parameters (Part 4 of 4)
Fast Corner
I/O Standard
Drive
Strength
Clock Parameter
1.8-V HSTL
CLASS II
1.8-V HSTL
CLASS II
1.8-V HSTL
CLASS II
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS II
1.5-V HSTL
CLASS II
1.5-V HSTL
CLASS II
3.3-V PCI
3.3-V PCI-X
LVDS
16 mA
18 mA
20 mA
4 mA
6 mA
8 mA
10 mA
12 mA
16 mA
18 mA
20 mA
—
—
—
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL t t t t t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO
CO t
CO t
CO t
CO
CO t
CO t
CO
CO
CO
Industrial Commercial
1.182
2.607
1.169
2.610
1.172
2.612
1.174
2.786
1.322
2.786
1.322
3.621
2.190
1.196
2.644
1.206
2.626
1.188
2.626
1.188
2.620
2.602
1.164
2.604
1.166
2.604
1.166
2.637
1.182
2.607
1.169
2.610
1.172
2.612
1.174
2.786
1.322
2.786
1.322
3.621
2.190
1.196
2.644
1.206
2.626
1.188
2.626
1.188
2.620
2.602
1.164
2.604
1.166
2.604
1.166
2.637
Units
Table 4–64 through Table 4–65 list EP1AGX50 regional clock (RCLK) adder values that
should be added to the GCLK values. These adder values are used to determine I/O timing when the I/O pin is driven using the regional clock. This applies for all I/O standards supported by Arria GX with general purpose I/O pins.
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
–6 Speed
Grade
2.556
5.573
2.368
5.571
2.378
5.581
2.391
5.803
2.697
5.803
2.697
6.969
3.880
2.569
5.651
2.554
5.653
2.556
5.655
2.558
5.653
5.574
2.314
5.578
2.325
5.577
2.334
5.675
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–59
lists row pin delay adders when using the regional clock in Arria GX devices.
Table 4–64. EP1AGX50 Row Pin Delay Adders for Regional Clock
Fast Corner
Parameter
RCLK
input adder
RCLK
PLL input adder
RCLK
output adder
RCLK
PLL output adder
Industrial
0.151
0.011
–0.151
–0.011
Commercial
0.151
0.011
–0.151
–0.011
–6 Speed Grade
0.329
0.016
–0.329
–0.016
Units
ns ns ns ns
lists column pin delay adders when using the regional clock in Arria GX devices.
Table 4–65. EP1AGX50 Column Pin Delay Adders for Regional Clock
Fast Corner
Parameter
RCLK
RCLK
RCLK
RCLK
input adder
PLL input adder
output adder
PLL output adder
Industrial
0.146
–1.713
–0.146
1.716
Commercial
0.146
–1.713
–0.146
1.716
–6 Speed Grade
0.334
–3.645
–0.336
4.488
Units
ns ns ns ns
EP1AGX60 I/O Timing Parameters
through Table 4–69 list the maximum I/O timing parameters for
EP1AGX60 devices for I/O standards which support general purpose I/O pins.
Table 4–66 lists I/O timing specifications.
Table 4–66. EP1AGX60 Row Pins Input Timing Parameters (Part 1 of 3)
Fast Model
I/O Standard Clock Parameter
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL t t t t t t
SU t t t t
SU t
H t
H
SU
H
SU
H
SU
H
SU
H
Industrial Commercial
1.413
–1.308
2.975
–2.870
1.413
–1.308
2.975
–2.870
1.425
–1.320
2.987
–2.882
1.413
–1.308
2.975
–2.870
1.413
–1.308
2.975
–2.870
1.425
–1.320
2.987
–2.882
–6 Speed
Grade
3.113
–2.836
6.536
–6.259
3.113
–2.836
6.536
–6.259
3.094
–2.817
6.517
–6.240
Units
ns ns ns ns ns ns ns ns ns ns ns ns
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–60 Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–66. EP1AGX60 Row Pins Input Timing Parameters (Part 2 of 3)
Fast Model
I/O Standard Clock Parameter
1.8 V
1.5 V
SSTL-2 CLASS I
SSTL-2 CLASS II
SSTL-18 CLASS I
SSTL-18 CLASS II
1.8-V HSTL CLASS I
1.8-V HSTL CLASS II
1.5-V HSTL CLASS I
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
Industrial Commercial
–2.722
1.255
–1.150
2.827
–2.722
1.255
–1.150
2.827
–2.695
1.255
–1.150
2.827
–2.722
1.255
–1.150
2.827
–2.947
1.237
–1.132
2.800
–2.695
1.237
–1.132
2.800
1.477
–1.372
3.049
–2.944
1.480
–1.375
3.052
–2.722
1.281
–1.176
2.853
–2.748
–2.722
1.255
–1.150
2.827
–2.722
1.255
–1.150
2.827
–2.695
1.255
–1.150
2.827
–2.722
1.255
–1.150
2.827
–2.947
1.237
–1.132
2.800
–2.695
1.237
–1.132
2.800
1.477
–1.372
3.049
–2.944
1.480
–1.375
3.052
–2.722
1.281
–1.176
2.853
–2.748
t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H
–6 Speed
Grade
–5.815
2.649
–2.372
6.092
–5.815
2.649
–2.372
6.092
–5.713
2.649
–2.372
6.092
–5.815
2.649
–2.372
6.092
–6.536
2.566
–2.289
5.990
–5.713
2.566
–2.289
5.990
3.275
–2.998
6.718
–6.441
3.370
–3.093
6.813
–5.815
2.777
–2.500
6.220
–5.943
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–66. EP1AGX60 Row Pins Input Timing Parameters (Part 3 of 3)
Fast Model
I/O Standard Clock Parameter
1.5-V HSTL CLASS II
LVDS
GCLK
GCLK PLL
GCLK
GCLK PLL t t
SU t
H t
SU t t
H t
SU t
H
SU
H
Industrial Commercial
1.281
–1.176
2.853
–2.748
1.208
–1.103
2.767
–2.662
1.281
–1.176
2.853
–2.748
1.208
–1.103
2.767
–2.662
lists I/O timing specifications.
Table 4–67. EP1AGX60 Column Pins Input Timing Parameters (Part 1 of 3)
Fast Corner
I/O Standard Clock Parameter
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5 V
SSTL-2 CLASS I
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL t t t t t t
SU t t
H
SU
H t
SU t
SU
H t
SU t
H t
SU
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
H
SU
H t
SU t
H
–1.098
2.773
–2.668
0.948
–0.843
2.519
–2.414
–1.029
2.704
–2.599
1.200
–1.095
2.770
–2.665
1.203
Industrial Commercial
1.124
1.124
–1.019
2.694
–2.589
1.124
–1.019
2.694
–2.589
1.134
–1.019
2.694
–2.589
1.124
–1.019
2.694
–2.589
1.134
–1.098
2.773
–2.668
0.948
–0.843
2.519
–2.414
–1.029
2.704
–2.599
1.200
–1.095
2.770
–2.665
1.203
–6 Speed
Grade
-2.408
6.120
-5.843
2.778
-2.501
6.213
-5.936
1.951
-1.674
5.388
-5.111
2.493
-2.216
5.928
-5.651
2.493
-2.216
5.928
-5.651
2.475
-2.198
5.910
-5.633
2.685
–6 Speed
Grade
2.777
–2.500
6.220
–5.943
2.664
–2.387
6.083
–5.806
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Units
ns ns ns ns ns ns ns ns
4–61
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–62 Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–67. EP1AGX60 Column Pins Input Timing Parameters (Part 2 of 3)
Fast Corner
I/O Standard Clock Parameter
SSTL-2 CLASS II
SSTL-18 CLASS I
SSTL-18 CLASS II
1.8-V HSTL CLASS I
1.8-V HSTL CLASS II
1.5-V HSTL CLASS I
1.5-V HSTL CLASS II
3.3-V PCI
3.3-V PCI-X
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
Industrial Commercial
–2.469
1.005
–0.900
2.576
–2.471
1.129
–1.024
2.699
–2.451
0.987
–0.882
2.558
–2.453
1.004
–0.899
2.574
–2.451
0.987
–0.882
2.558
–2.453
0.986
–0.881
2.556
0.948
–0.843
2.519
–2.414
0.986
–0.881
2.556
–2.594
1.129
–1.024
2.699
–2.594
–2.469
1.005
–0.900
2.576
–2.471
1.129
–1.024
2.699
–2.451
0.987
–0.882
2.558
–2.453
1.004
–0.899
2.574
–2.451
0.987
–0.882
2.558
–2.453
0.986
–0.881
2.556
0.948
–0.843
2.519
–2.414
0.986
–0.881
2.556
–2.594
1.129
–1.024
2.699
–2.594
t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H
–6 Speed
Grade
–5.343
2.186
–1.909
5.623
–5.346
2.481
–2.204
5.916
–5.215
2.058
–1.781
5.495
–5.218
2.185
–1.908
5.620
–5.215
2.058
–1.781
5.495
–5.218
2.057
–1.780
5.492
1.951
–1.674
5.388
–5.111
2.057
–1.780
5.492
–5.639
2.481
–2.204
5.916
–5.639
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–67. EP1AGX60 Column Pins Input Timing Parameters (Part 3 of 3)
Fast Corner
I/O Standard Clock Parameter
LVDS
GCLK
GCLK PLL t t
SU t t
H
SU
H
Industrial Commercial
0.980
–0.875
2.557
–2.452
0.980
–0.875
2.557
–2.452
lists I/O timing specifications.
Table 4–68. EP1AGX60 Row Pins Output Timing Parameters (Part 1 of 2)
Fast Model
I/O Standard
Drive
Strength
Clock Parameter
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V
LVCMOS
3.3-V
LVCMOS
2.5 V
2.5 V
2.5 V
1.8 V
1.8 V
1.8 V
1.8 V
1.5 V
1.5 V
4 mA
8 mA
12 mA
4 mA
8 mA
4 mA
8 mA
12 mA
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL t t t t t t t t t t
CO
CO t
CO t
CO t
CO
CO t
CO t
CO t
CO
CO t
CO t
CO t
CO
CO t
CO t
CO t
CO
CO t
CO t
CO
CO
CO t
CO t
CO
CO
CO t
CO t
CO
1.419
2.980
1.408
2.869
1.297
2.838
1.266
2.951
1.256
2.907
1.345
2.804
1.242
2.785
1.223
2.991
1.379
2.844
1.272
Industrial Commercial
3.052
3.052
1.490
2.924
1.362
2.868
1.306
2.924
1.362
2.818
1.490
2.924
1.362
2.868
1.306
2.924
1.362
2.818
1.419
2.980
1.408
2.869
1.297
2.838
1.266
2.951
1.256
2.907
1.345
2.804
1.242
2.785
1.223
2.991
1.379
2.844
1.272
–6 Speed
Grade
2.062
–1.785
5.512
–5.235
–6 Speed
Grade
2.998
6.327
2.884
7.020
3.577
6.419
2.976
2.795
6.104
2.681
7.521
4.078
6.742
3.299
6.441
7.142
3.719
6.502
3.079
6.465
3.042
6.502
3.079
6.196
2.773
6.476
3.053
6.218
Units
ns ns ns ns
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
4–63
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–64 Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–68. EP1AGX60 Row Pins Output Timing Parameters (Part 2 of 2)
Fast Model
I/O Standard
Drive
Strength
Clock Parameter
SSTL-2
CLASS I
SSTL-2
CLASS I
SSTL-2
CLASS II
SSTL-18
CLASS I
SSTL-18
CLASS I
SSTL-18
CLASS I
SSTL-18
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
LVDS
8 mA
12 mA
16 mA
4 mA
6 mA
8 mA
10 mA
4 mA
6 mA
8 mA
10 mA
12 mA
4 mA
6 mA
8 mA
—
Industrial Commercial
1.165
2.756
1.184
2.759
1.187
2.744
1.172
2.787
1.228
1.185
2.760
1.188
2.742
1.170
2.746
1.174
2.737
1.204
2.780
1.208
2.756
1.184
2.759
1.187
2.757
2.774
1.211
2.750
1.187
2.716
1.153
2.776
1.165
2.756
1.184
2.759
1.187
2.744
1.172
2.787
1.228
1.185
2.760
1.188
2.742
1.170
2.746
1.174
2.737
1.204
2.780
1.208
2.756
1.184
2.759
1.187
2.757
2.774
1.211
2.750
1.187
2.716
1.153
2.776
t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
–6 Speed
Grade
2.440
5.912
2.469
5.898
2.455
5.890
2.447
6.037
2.618
2.492
5.899
2.456
5.895
2.452
5.884
2.441
5.883
2.582
5.954
2.511
5.937
2.494
5.916
2.473
5.935
6.057
2.633
5.981
2.557
5.850
2.426
6.025
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
lists I/O timing specifications.
Table 4–69. EP1AGX60 Column Pins Output Timing Parameters (Part 1 of 4)
Fast Corner
I/O Standard
Drive
Strength
Clock Parameter
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V
LVCMOS
3.3-V
LVCMOS
3.3-V
LVCMOS
3.3-V
LVCMOS
3.3-V
LVCMOS
3.3-V
LVCMOS
2.5 V
2.5 V
2.5 V
2.5 V
1.8 V
1.8 V
4 mA
8 mA
12 mA
16 mA
20 mA
24 mA
4 mA
8 mA
12 mA
16 mA
20 mA
24 mA
4 mA
8 mA
12 mA
16 mA
2 mA
4 mA
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO
Industrial Commercial
2.853
1.283
2.801
1.231
2.780
1.210
2.762
1.192
2.771
1.201
2.778
1.208
2.765
1.195
2.754
1.184
2.893
1.323
2.898
1.328
2.776
1.206
2.769
1.199
2.891
1.321
2.799
1.229
3.036
1.466
2.891
1.321
2.824
1.254
2.798
1.228
2.853
1.283
2.801
1.231
2.780
1.210
2.762
1.192
2.771
1.201
2.778
1.208
2.765
1.195
2.754
1.184
2.893
1.323
2.898
1.328
2.776
1.206
2.769
1.199
2.891
1.321
2.799
1.229
3.036
1.466
2.891
1.321
2.824
1.254
2.798
1.228
–6 Speed
Grade
6.623
3.188
6.361
2.926
6.244
2.809
6.170
2.735
6.218
2.783
6.186
2.751
6.168
2.733
6.146
2.711
7.615
4.180
6.841
3.406
6.297
2.862
6.299
2.864
6.591
3.156
6.296
2.861
6.963
3.528
6.591
3.156
6.591
3.156
6.422
2.987
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
4–65
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–66 Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–69. EP1AGX60 Column Pins Output Timing Parameters (Part 2 of 4)
Fast Corner
I/O Standard
Drive
Strength
Clock Parameter
1.8 V
1.8 V
1.8 V
1.8 V
1.5 V
1.5 V
1.5 V
1.5 V
SSTL-2
CLASS I
SSTL-2
CLASS I
SSTL-2
CLASS II
SSTL-2
CLASS II
SSTL-2
CLASS II
SSTL-18
CLASS I
SSTL-18
CLASS I
SSTL-18
CLASS I
SSTL-18
CLASS I
SSTL-18
CLASS I
SSTL-18
CLASS II
6 mA
8 mA
10 mA
12 mA
2 mA
4 mA
6 mA
8 mA
8 mA
12 mA
16 mA
20 mA
24 mA
4 mA
6 mA
8 mA
10 mA
12 mA
8 mA
Industrial Commercial
1.146
2.715
1.142
2.753
1.183
2.758
1.185
2.737
1.201
2.757
1.184
2.740
1.167
2.718
1.145
2.719
1.164
2.742
1.169
2.736
1.163
2.725
1.152
1.209
2.873
1.303
2.809
1.239
2.812
1.242
2.771
2.822
1.252
2.824
1.254
2.778
1.208
2.779
1.146
2.715
1.142
2.753
1.183
2.758
1.185
2.737
1.201
2.757
1.184
2.740
1.167
2.718
1.145
2.719
1.164
2.742
1.169
2.736
1.163
2.725
1.152
1.209
2.873
1.303
2.809
1.239
2.812
1.242
2.771
2.822
1.252
2.824
1.254
2.778
1.208
2.779
t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
–6 Speed
Grade
2.608
6.046
2.606
6.155
2.720
6.116
2.676
6.097
2.970
6.184
2.744
6.134
2.694
6.061
2.621
6.048
2.657
6.095
2.655
6.081
2.641
6.047
2.607
2.917
7.145
3.710
6.576
3.141
6.458
3.023
6.405
6.577
3.142
6.486
3.051
6.409
2.974
6.352
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–69. EP1AGX60 Column Pins Output Timing Parameters (Part 3 of 4)
Fast Corner
I/O Standard
Drive
Strength
Clock Parameter
SSTL-18
CLASS II
SSTL-18
CLASS II
SSTL-18
CLASS II
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS II
1.8-V HSTL
CLASS II
1.8-V HSTL
CLASS II
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS II
1.5-V HSTL
CLASS II
1.5-V HSTL
CLASS II
16 mA
18 mA
20 mA
4 mA
6 mA
8 mA
10 mA
12 mA
16 mA
18 mA
20 mA
4 mA
6 mA
8 mA
10 mA
12 mA
16 mA
18 mA
20 mA
Industrial Commercial
1.186
2.761
1.188
2.743
1.170
2.743
1.170
2.737
1.163
2.719
1.146
2.721
1.148
2.721
1.148
2.756
1.164
2.724
1.151
2.727
1.154
2.729
1.156
1.186
2.762
1.189
2.740
1.167
2.744
1.171
2.736
2.737
1.164
2.733
1.160
2.733
1.160
2.756
1.186
2.761
1.188
2.743
1.170
2.743
1.170
2.737
1.163
2.719
1.146
2.721
1.148
2.721
1.148
2.756
1.164
2.724
1.151
2.727
1.154
2.729
1.156
1.186
2.762
1.189
2.740
1.167
2.744
1.171
2.736
2.737
1.164
2.733
1.160
2.733
1.160
2.756
t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
–6 Speed
Grade
2.650
6.063
2.623
6.065
2.625
6.067
2.627
6.065
2.619
5.823
2.383
5.834
2.394
5.843
2.403
6.085
2.625
5.877
2.437
5.887
2.447
5.900
2.460
2.651
6.071
2.631
6.060
2.620
6.066
2.626
6.059
6.025
2.585
6.033
2.593
6.031
2.591
6.086
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
4–67
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–68 Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–69. EP1AGX60 Column Pins Output Timing Parameters (Part 4 of 4)
Fast Corner
I/O Standard
Drive
Strength
Clock Parameter
3.3-V PCI
3.3-V PCI-X
LVDS
—
—
—
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL t t t
CO t
CO
CO
CO t
CO t
CO
Industrial Commercial
2.882
1.312
2.882
1.312
3.746
2.185
2.882
1.312
2.882
1.312
3.746
2.185
–6 Speed
Grade
6.213
2.778
6.213
2.778
7.396
3.973
Units
ns ns ns ns ns ns
Table 4–70 through Table 4–71 list EP1AGX60 regional clock (RCLK) adder values that
should be added to the GCLK values. These adder values are used to determine I/O timing when the I/O pin is driven using the regional clock. This applies for all I/O standards supported by Arria GX with general purpose I/O pins.
Table 4–70 describes row pin delay adders when using the regional clock in Arria GX
devices.
Table 4–70. EP1AGX60 Row Pin Delay Adders for Regional Clock
Fast Corner
Parameter
RCLK
RCLK
RCLK
RCLK
input adder
PLL input adder
output adder
PLL output adder
Industrial
0.138
–0.003
–0.138
0.003
Commercial
0.138
–0.003
–0.138
0.003
–6 Speed Grade
0.311
–0.006
–0.311
0.006
Units
ns ns ns ns
Table 4–71 lists column pin delay adders when using the regional clock in Arria GX
devices.
Table 4–71. EP1AGX60 Column Pin Delay Adders for Regional Clock
Fast Corner
Parameter
RCLK
input adder
RCLK
PLL input adder
RCLK
RCLK
output adder
PLL output adder
Industrial
0.153
–1.066
–0.153
1.721
Commercial
0.153
–1.066
–0.153
1.721
–6 Speed Grade Units
0.344
–2.338
–0.343
4.486
ns ns ns ns
EP1AGX90 I/O Timing Parameters
through Table 4–75 list the maximum I/O timing parameters for
EP1AGX90 devices for I/O standards which support general purpose I/O pins.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
lists I/O timing specifications.
Table 4–72. EP1AGX90 Row Pins Input Timing Parameters (Part 1 of 2)
Fast Model
I/O Standard Clock Parameter
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5 V
SSTL-2 CLASS I
SSTL-2 CLASS II
SSTL-18 CLASS I
SSTL-18 CLASS II
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
Industrial Commercial
1.121
–1.016
3.187
–3.082
1.159
–1.054
3.212
–3.107
1.384
–1.279
3.437
–3.332
1.121
–1.016
3.187
–3.082
1.157
–1.052
3.235
–3.130
1.307
–1.202
3.378
–3.273
1.381
–1.276
3.434
–3.329
1.295
–1.190
3.366
–3.261
1.295
–1.190
3.366
–3.261
1.121
–1.016
3.187
–3.082
1.159
–1.054
3.212
–3.107
1.384
–1.279
3.437
–3.332
1.121
–1.016
3.187
–3.082
1.157
–1.052
3.235
–3.130
1.307
–1.202
3.378
–3.273
1.381
–1.276
3.434
–3.329
1.295
–1.190
3.366
–3.261
1.295
–1.190
3.366
–3.261
t
H t
SU t
H t
SU t
H t
SU t
H t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
SU t
H t
SU t
H t
SU
–6 Speed
Grade
2.329
–2.052
6.466
–6.189
2.447
–2.170
6.565
–6.288
3.168
–2.891
7.286
–7.009
2.329
–2.052
6.466
–6.189
2.441
–2.164
6.597
–6.320
2.854
–2.577
6.998
–6.721
3.073
–2.796
7.191
–6.914
2.873
–2.596
7.017
–6.740
2.873
–2.596
7.017
–6.740
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
4–69
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–70 Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–72. EP1AGX90 Row Pins Input Timing Parameters (Part 2 of 2)
Fast Model
I/O Standard Clock Parameter
1.8-V HSTL CLASS I
1.8-V HSTL CLASS II
1.5-V HSTL CLASS I
1.5-V HSTL CLASS II
LVDS
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL t t t t
H t
SU t
H t
SU t
SU t
H t
SU t
H t
SU t
H t
SU
H t
SU t
H t
SU t
H t
SU t
H
SU
H
Industrial Commercial
–3.130
1.185
–1.080
3.238
–3.133
1.183
–1.078
3.261
1.159
–1.054
3.212
–3.107
1.157
–1.052
3.235
–3.156
1.098
–0.993
3.160
–3.055
–3.130
1.185
–1.080
3.238
–3.133
1.183
–1.078
3.261
1.159
–1.054
3.212
–3.107
1.157
–1.052
3.235
–3.156
1.098
–0.993
3.160
–3.055
–6 Speed
Grade
–6.320
2.575
–2.298
6.693
–6.416
2.569
–2.292
6.725
2.447
–2.170
6.565
–6.288
2.441
–2.164
6.597
–6.448
2.439
–2.162
6.566
–6.289
lists I/O timing specifications.
\
Table 4–73. EP1AGX90 Column Pins Input Timing Parameters (Part 1 of 3)
Fast Corner
I/O Standard Clock Parameter
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL t
SU t
H t
SU t
H t
SU t
H t
H t
SU t
H t
SU t
H t
SU
Industrial Commercial
1.018
1.018
–0.913
3.082
–2.977
1.018
–0.913
3.082
–2.977
1.028
–0.923
3.092
–2.987
–0.913
3.082
–2.977
1.018
–0.913
3.082
–2.977
1.028
–0.923
3.092
–2.987
–6 Speed
Grade
2.290
–2.013
6.425
–6.148
2.290
–2.013
6.425
–6.148
2.272
–1.995
6.407
–6.130
Units
ns ns ns ns ns ns ns ns ns ns ns ns
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–73. EP1AGX90 Column Pins Input Timing Parameters (Part 2 of 3)
Fast Corner
I/O Standard Clock Parameter
1.8 V
1.5 V
SSTL-2 CLASS I
SSTL-2 CLASS II
SSTL-18 CLASS I
SSTL-18 CLASS II
1.8-V HSTL CLASS I
1.8-V HSTL CLASS II
1.5-V HSTL CLASS I
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
Industrial Commercial
–2.842
0.880
–0.775
2.944
–2.839
0.883
–0.778
2.947
–2.803
0.880
–0.775
2.944
–2.839
0.883
–0.778
2.947
–3.056
0.844
–0.739
2.908
–2.803
0.844
–0.739
2.908
1.094
–0.989
3.158
–3.053
1.097
–0.992
3.161
–2.842
0.898
–0.793
2.962
–2.857
–2.842
0.880
–0.775
2.944
–2.839
0.883
–0.778
2.947
–2.803
0.880
–0.775
2.944
–2.839
0.883
–0.778
2.947
–3.056
0.844
–0.739
2.908
–2.803
0.844
–0.739
2.908
1.094
–0.989
3.158
–3.053
1.097
–0.992
3.161
–2.842
0.898
–0.793
2.962
–2.857
t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H
–6 Speed
Grade
–5.716
1.854
–1.577
5.989
–5.712
1.858
–1.581
5.993
–5.609
1.854
–1.577
5.989
–5.712
1.858
–1.581
5.993
–6.433
1.751
–1.474
5.886
–5.609
1.751
–1.474
5.886
2.482
–2.205
6.617
–6.340
2.575
–2.298
6.710
–5.716
1.982
–1.705
6.117
–5.840
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
4–71
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–72 Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–73. EP1AGX90 Column Pins Input Timing Parameters (Part 3 of 3)
Fast Corner
I/O Standard Clock Parameter
1.5-V HSTL CLASS II
3.3-V PCI
3.3-V PCI-X
LVDS
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL t t
SU t
H t
SU t t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H t
SU t
H
SU
H
Industrial Commercial
–2.982
1.023
–0.918
3.087
–2.982
0.891
–0.786
2.963
–2.858
0.901
–0.796
2.965
–2.860
1.023
–0.918
3.087
–2.982
1.023
–0.918
3.087
–2.982
0.891
–0.786
2.963
–2.858
0.901
–0.796
2.965
–2.860
1.023
–0.918
3.087
lists I/O timing specifications.
Table 4–74. EP1AGX90 Row Pins Output Timing Parameters (Part 1 of 3)
Fast Model
I/O Standard
Drive
Strength
Clock Parameter
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V
LVCMOS
3.3-V
LVCMOS
2.5 V
2.5 V
2.5 V
4 mA
8 mA
12 mA
4 mA
8 mA
4 mA
8 mA
12 mA
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL t t t t t t t
CO
CO t
CO t
CO t
CO
CO t
CO t
CO
CO
CO t
CO t
CO
CO
CO t
CO t
CO
0.865
3.025
0.954
2.922
0.851
2.903
0.832
Industrial Commercial
3.170
3.170
1.099
3.042
0.971
2.986
0.915
3.042
0.971
2.936
1.099
3.042
0.971
2.986
0.915
3.042
0.971
2.936
0.865
3.025
0.954
2.922
0.851
2.903
0.832
–6 Speed
Grade
–6.136
2.278
–2.001
6.413
–6.136
1.920
–1.643
6.066
–5.789
1.986
–1.709
6.121
–5.844
2.278
–2.001
6.413
–6 Speed
Grade
7.382
3.238
6.742
2.598
6.705
2.561
6.742
2.598
6.436
2.292
6.716
2.572
6.458
2.314
6.344
2.200
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–74. EP1AGX90 Row Pins Output Timing Parameters (Part 2 of 3)
Fast Model
I/O Standard
Drive
Strength
Clock Parameter
1.8 V
1.8 V
1.8 V
1.8 V
1.5 V
1.5 V
SSTL-2
CLASS I
SSTL-2
CLASS I
SSTL-2
CLASS II
SSTL-18
CLASS I
SSTL-18
CLASS I
SSTL-18
CLASS I
SSTL-18
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.5-V HSTL
CLASS I
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
8 mA
12 mA
16 mA
4 mA
6 mA
8 mA
10 mA
4 mA
6 mA
8 mA
10 mA
12 mA
4 mA
Industrial Commercial
0.776
2.857
0.779
2.853
0.800
2.858
0.780
2.840
0.800
2.832
0.766
2.872
0.819
2.878
0.800
2.854
0.762
2.844
0.766
2.835
0.757
2.852
0.799
0.881
3.047
0.994
2.940
0.887
2.890
0.824
2.866
3.087
1.034
3.076
1.023
2.965
0.912
2.934
0.776
2.857
0.779
2.853
0.800
2.858
0.780
2.840
0.800
2.832
0.766
2.872
0.819
2.878
0.800
2.854
0.762
2.844
0.766
2.835
0.757
2.852
0.799
0.881
3.047
0.994
2.940
0.887
2.890
0.824
2.866
3.087
1.034
3.076
1.023
2.965
0.912
2.934
t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
–6 Speed
Grade
1.989
6.124
1.968
6.137
2.019
6.107
1.951
6.103
2.081
6.087
1.950
6.227
2.109
6.162
2.006
6.145
1.947
6.092
1.936
6.091
1.935
6.114
1.996
2.411
7.222
3.104
6.621
2.503
6.294
2.157
6.218
7.723
3.605
6.944
2.826
6.643
2.525
6.529
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
4–73
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–74 Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–74. EP1AGX90 Row Pins Output Timing Parameters (Part 3 of 3)
Fast Model
I/O Standard
Drive
Strength
Clock Parameter
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
LVDS
6 mA
8 mA
—
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL t t t
CO t
CO
CO
CO t
CO t
CO
Industrial Commercial
2.857
0.779
2.842
0.764
2.898
0.831
2.857
0.779
2.842
0.764
2.898
0.831
lists I/O timing specifications.
Table 4–75. EP1AGX90 Column Pins Output Timing Parameters (Part 1 of 4)
Fast Corner
I/O Standard
Drive
Strength
Clock Parameter
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V
LVCMOS
3.3-V
LVCMOS
3.3-V
LVCMOS
3.3-V
LVCMOS
3.3-V
LVCMOS
3.3-V
LVCMOS
2.5 V
4 mA
8 mA
12 mA
16 mA
20 mA
24 mA
4 mA
8 mA
12 mA
16 mA
20 mA
24 mA
4 mA
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL t t t t t t t t t
CO t
CO t
CO
CO t
CO t
CO t
CO
CO t
CO t
CO t
CO
CO t
CO t
CO t
CO
CO t
CO t
CO
CO
CO t
CO t
CO
CO
CO t
CO t
CO
Industrial Commercial
0.840
2.876
0.812
2.883
0.819
2.870
0.806
2.859
0.795
2.958
0.894
0.839
2.881
0.817
2.874
0.810
2.996
0.932
2.904
3.141
1.077
2.996
0.932
2.929
0.865
2.903
0.840
2.876
0.812
2.883
0.819
2.870
0.806
2.859
0.795
2.958
0.894
0.839
2.881
0.817
2.874
0.810
2.996
0.932
2.904
3.141
1.077
2.996
0.932
2.929
0.865
2.903
–6 Speed
Grade
6.106
1.950
6.098
1.942
6.265
2.129
–6 Speed
Grade
2.362
6.419
2.284
6.387
2.252
6.369
2.234
6.347
2.212
6.824
2.689
2.488
6.498
2.363
6.500
2.365
6.792
2.657
6.497
7.164
3.029
6.792
2.657
6.792
2.657
6.623
Units
ns ns ns ns ns ns
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–75. EP1AGX90 Column Pins Output Timing Parameters (Part 2 of 4)
Fast Corner
I/O Standard
Drive
Strength
Clock Parameter
2.5 V
2.5 V
2.5 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.5 V
1.5 V
1.5 V
1.5 V
SSTL-2
CLASS I
SSTL-2
CLASS I
SSTL-2
CLASS II
SSTL-2
CLASS II
SSTL-2
CLASS II
SSTL-18
CLASS I
8 mA
12 mA
16 mA
2 mA
4 mA
6 mA
8 mA
10 mA
12 mA
2 mA
4 mA
6 mA
8 mA
8 mA
12 mA
16 mA
20 mA
24 mA
4 mA
Industrial Commercial
0.853
2.876
0.812
2.859
0.797
2.842
0.780
2.820
0.819
2.884
0.820
2.978
0.914
2.914
0.850
2.917
0.758
2.821
0.759
2.817
0.755
2.858
0.794
0.934
3.003
0.939
2.927
0.863
2.929
0.865
2.883
2.906
0.842
2.885
0.821
2.867
0.803
2.998
0.853
2.876
0.812
2.859
0.797
2.842
0.780
2.820
0.819
2.884
0.820
2.978
0.914
2.914
0.850
2.917
0.758
2.821
0.759
2.817
0.755
2.858
0.794
0.934
3.003
0.939
2.927
0.863
2.929
0.865
2.883
2.906
0.842
2.885
0.821
2.867
0.803
2.998
t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
–6 Speed
Grade
2.524
6.606
2.471
6.381
2.250
6.331
2.200
6.258
2.475
6.553
2.418
7.346
3.211
6.777
2.642
6.659
2.127
6.245
2.114
6.243
2.112
6.356
2.221
3.681
7.042
2.907
6.778
2.643
6.687
2.552
6.610
6.562
2.427
6.445
2.310
6.371
2.236
7.816
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
4–75
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–76 Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–75. EP1AGX90 Column Pins Output Timing Parameters (Part 3 of 4)
Fast Corner
I/O Standard
Drive
Strength
Clock Parameter
SSTL-18
CLASS I
SSTL-18
CLASS I
SSTL-18
CLASS I
SSTL-18
CLASS I
SSTL-18
CLASS II
SSTL-18
CLASS II
SSTL-18
CLASS II
SSTL-18
CLASS II
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS I
1.8-V HSTL
CLASS II
1.8-V HSTL
CLASS II
1.8-V HSTL
CLASS II
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
6 mA
8 mA
10 mA
12 mA
8 mA
16 mA
18 mA
20 mA
4 mA
6 mA
8 mA
10 mA
12 mA
16 mA
18 mA
20 mA
4 mA
6 mA
8 mA
Industrial Commercial
0.784
2.838
0.776
2.821
0.759
2.823
0.761
2.823
0.773
2.861
0.797
2.864
0.802
2.842
0.780
2.846
0.761
2.861
0.797
2.863
0.801
2.845
0.783
0.776
2.827
0.765
2.839
0.777
2.835
0.773
2.835
2.860
0.798
2.839
0.777
2.844
0.782
2.838
0.784
2.838
0.776
2.821
0.759
2.823
0.761
2.823
0.773
2.861
0.797
2.864
0.802
2.842
0.780
2.846
0.761
2.861
0.797
2.863
0.801
2.845
0.783
0.776
2.827
0.765
2.839
0.777
2.835
0.773
2.835
2.860
0.798
2.839
0.777
2.844
0.782
2.838
t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO t
CO
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
–6 Speed
Grade
2.132
6.256
2.125
6.020
1.889
6.031
1.900
6.040
2.097
6.287
2.152
6.268
2.137
6.257
2.126
6.263
1.909
6.286
2.151
6.260
2.129
6.262
2.131
2.147
6.244
2.113
6.222
2.091
6.230
2.099
6.228
6.313
2.182
6.294
2.163
6.292
2.161
6.278
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–77
Table 4–75. EP1AGX90 Column Pins Output Timing Parameters (Part 4 of 4)
Fast Corner
I/O Standard
Drive
Strength
Clock Parameter
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS I
1.5-V HSTL
CLASS II
1.5-V HSTL
CLASS II
1.5-V HSTL
CLASS II
3.3-V PCI
3.3-V PCI-X
LVDS
10 mA
12 mA
16 mA
18 mA
20 mA
—
—
—
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL
GCLK
GCLK PLL t t t t t t
CO t
CO t
CO
CO t
CO t
CO t
CO
CO t
CO t
CO t
CO
CO t
CO t
CO
CO
CO
Industrial Commercial
0.767
2.831
0.769
2.987
0.923
2.987
0.923
3.835
1.769
2.845
0.783
2.839
0.777
2.826
0.764
2.829
0.767
2.831
0.769
2.987
0.923
2.987
0.923
3.835
1.769
2.845
0.783
2.839
0.777
2.826
0.764
2.829
–6 Speed
Grade
1.953
6.097
1.966
6.414
2.279
6.414
2.279
7.541
3.404
6.264
2.133
6.262
2.131
6.074
1.943
6.084
through Table 4–77 list the EP1AGX90 regional clock (RCLK) adder values
that should be added to the GCLK values. These adder values are used to determine
I/O timing when the I/O pin is driven using the regional clock. This applies for all
I/O standards supported by Arria GX with general purpose I/O pins.
lists row pin delay adders when using the regional clock in Arria GX devices.
Table 4–76. EP1AGX90 Row Pin Delay Adders for Regional Clock
Fast Corner
Parameter
RCLK
RCLK
RCLK
RCLK
input adder
PLL input adder
output adder
PLL output adder
Industrial
0.175
0.007
–0.175
–0.007
Commercial
0.175
0.007
–0.175
–0.007
–6 Speed Grade
0.418
0.015
–0.418
–0.015
Units
ns ns ns ns
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–78 Chapter 4: DC and Switching Characteristics
Typical Design Performance
lists column pin delay adders when using the regional clock in Arria GX devices.
Table 4–77. EP1AGX90 Column Pin Delay Adders for Regional Clock
Fast Corner
Parameter
RCLK
input adder
RCLK
PLL input adder
RCLK
output adder
RCLK
PLL output adder
Industrial
0.138
–1.697
–0.138
1.966
Commercial
0.138
–1.697
–0.138
1.966
–6 Speed Grade
0.354
–3.607
–0.353
5.188
Units
ns ns ns ns
Dedicated Clock Pin Timing
through Table 4–98 list clock pin timing for Arria GX devices when the
clock is driven by the global clock, regional clock, periphery clock, and a PLL.
Table 4–78 lists Arria GX clock timing parameters.
Table 4–78. Arria GX Clock Timing Parameters
Symbol
t
CIN t
COUT t
PLLCIN t
PLLCOUT
Parameter
Delay from clock pad to I/O input register
Delay from clock pad to I/O output register
Delay from PLL inclk pad to I/O input register
Delay from PLL inclk pad to I/O output register
EP1AGX20 Clock Timing Parameters
through Table 4–80 list the GCLK clock timing parameters for EP1AGX20
devices.
Table 4–79 lists clock timing specifications.
Table 4–79. EP1AGX20 Row Pins Global Clock Timing Parameters
Fast Model
Parameter –6 Speed Grade
tcin tcout tpllcin tpllcout
Industrial
1.394
1.399
–0.027
–0.022
Commercial
1.394
1.399
–0.027
–0.022
3.161
3.155
0.091
0.085
Units
ns ns ns ns
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–79
lists clock timing specifications.
Table 4–80. EP1AGX20 Row Pins Global Clock Timing Parameters
Fast Model
Parameter –6 Speed Grade
t
CIN t
COUT t
PLLCIN t
PLLCOUT
Industrial
1.655
1.655
0.236
0.236
Commercial
1.655
1.655
0.236
0.236
3.726
3.726
0.655
0.655
Units
ns ns ns ns
Table 4–81 through Table 4–82 list the RCLK clock timing parameters for EP1AGX20
devices.
Table 4–81 lists clock timing specifications.
Table 4–81. EP1AGX20 Row Pins Regional Clock Timing Parameters
Fast Model
Parameter –6 Speed Grade
t
CIN t
COUT t
PLLCIN t
PLLCOUT
Industrial
1.283
1.288
–0.034
–0.029
Commercial
1.283
1.288
–0.034
–0.029
2.901
2.895
0.077
0.071
Table 4–82 lists clock timing specifications.
Table 4–82. EP1AGX20 Row Pins Regional Clock Timing Parameters
Fast Model
Parameter –6 Speed Grade
t
CIN t
COUT t t
PLLCIN
PLLCOUT
Industrial
1.569
1.569
0.278
0.278
Commercial
1.569
1.569
0.278
0.278
3.487
3.487
0.706
0.706
Units
ns ns ns ns ns ns ns ns
Units
EP1AGX35 Clock Timing Parameters
through Table 4–84 list the GCLK clock timing parameters for EP1AGX35
devices.
Table 4–83 lists clock timing specifications.
Table 4–83. EP1AGX35 Row Pins Global Clock Timing Parameters (Part 1 of 2)
Fast Model
Parameter –6 Speed Grade
t t
CIN
COUT
Industrial
1.394
1.399
Commercial
1.394
1.399
3.161
3.155
Units
ns ns
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–80 Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–83. EP1AGX35 Row Pins Global Clock Timing Parameters (Part 2 of 2)
Fast Model
Parameter –6 Speed Grade
t t
PLLCIN
PLLCOUT
Industrial
–0.027
–0.022
Commercial
–0.027
–0.022
0.091
0.085
lists clock timing specifications.
Table 4–85. EP1AGX35 Row Pins Regional Clock Timing Parameters
Fast Model
Parameter –6 Speed Grade
t t t t
CIN
COUT
PLLCIN
PLLCOUT
Industrial
1.283
1.288
–0.034
–0.029
Commercial
1.283
1.288
–0.034
–0.029
2.901
2.895
0.077
0.071
Units
ns ns
Table 4–84. EP1AGX35 Row Pins Global Clock Timing Parameters
Fast Model
Parameter –6 Speed Grade
t t t t
CIN
COUT
PLLCIN
PLLCOUT
Industrial
1.655
1.655
0.236
0.236
Commercial
1.655
1.655
0.236
0.236
3.726
3.726
0.655
0.655
Units
ns ns ns ns
Table 4–85 through Table 4–86 list the RCLK clock timing parameters for EP1AGX35
devices.
Table 4–85 lists clock timing specifications.
Units
ns ns ns ns
Table 4–86 lists clock timing specifications.
Table 4–86. EP1AGX35 Row Pins Regional Clock Timing Parameters
Fast Model
Parameter –6 Speed Grade
t t t t
CIN
COUT
PLLCIN
PLLCOUT
Industrial
1.569
1.569
0.278
0.278
Commercial
1.569
1.569
0.278
0.278
3.487
3.487
0.706
0.706
Units
ns ns ns ns
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–81
EP1AGX50 Clock Timing Parameters
Table 4–87 through Table 4–88 list the GCLK clock timing parameters for EP1AGX50
devices.
Table 4–87 lists clock timing specifications.
Table 4–87. EP1AGX50 Row Pins Global Clock Timing Parameters
Fast Model
Parameter –6 Speed Grade
t
CIN t
COUT t
PLLCIN t
PLLCOUT
Industrial
1.529
1.534
–0.024
–0.019
Commercial
1.529
1.534
–0.024
–0.019
3.587
3.581
0.181
0.175
Table 4–88 lists clock timing specifications.
Table 4–89. EP1AGX50 Row Pins Regional Clock Timing Parameters
Fast Model
Parameter –6 Speed Grade
t
CIN t
COUT t t
PLLCIN
PLLCOUT
Industrial
1.396
1.401
–0.017
–0.012
Commercial
1.396
1.401
–0.017
–0.012
3.287
3.281
0.195
0.189
Units
ns ns ns ns ns ns ns ns
Table 4–88. EP1AGX50 Row Pins Global Clock Timing Parameters
Fast Model
Parameter –6 Speed Grade
t
CIN t
COUT t t
PLLCIN
PLLCOUT
Industrial
1.793
1.793
0.238
0.238
Commercial
1.793
1.793
0.238
0.238
4.165
4.165
0.758
0.758
Units
ns ns ns ns
through Table 4–90 list the RCLK clock timing parameters for EP1AGX50
devices.
Table 4–89 lists clock timing specifications.
Units
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–82 Chapter 4: DC and Switching Characteristics
Typical Design Performance
lists clock timing specifications.
Table 4–90. EP1AGX50 Row Pins Regional Clock Timing Parameters
Fast Model
Parameter –6 Speed Grade
t
CIN t
COUT t
PLLCIN t
PLLCOUT
Industrial
1.653
1.651
0.245
0.245
Commercial
1.653
1.651
0.245
0.245
3.841
3.839
0.755
0.755
Units
EP1AGX60 Clock Timing Parameters
Table 4–91 to Table 4–92 on page 4–82
list the GCLK clock timing parameters for
EP1AGX60 devices.
Table 4–91 lists clock timing specifications.
Table 4–91. EP1AGX60 Row Pins Global Clock Timing Parameters
Fast Model
Parameter –6 Speed Grade
t
CIN t
COUT t
PLLCIN t
PLLCOUT
Industrial
1.531
1.536
–0.023
–0.018
Commercial
1.531
1.536
–0.023
–0.018
3.593
3.587
0.188
0.182
Table 4–92 lists clock timing specifications.
Table 4–92. EP1AGX60 Row Pins Global Clock Timing Parameters
Fast Model
Parameter –6 Speed Grade
t
CIN t
COUT t t
PLLCIN
PLLCOUT
Industrial
1.792
1.792
0.238
0.238
Commercial
1.792
1.792
0.238
0.238
4.165
4.165
0.758
0.758
Units
Units
ns ns ns ns ns ns ns ns ns ns ns ns
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–83
Table 4–93 through Table 4–94 list the RCLK clock timing parameters for EP1AGX60
devices.
Table 4–93 lists clock timing specifications.
Table 4–93. EP1AGX60 Row Pins Regional Clock Timing Parameters
Fast Model
Parameter –6 Speed Grade
t
CIN t
COUT t t
PLLCIN
PLLCOUT
Industrial
1.382
1.387
–0.031
–0.026
Commercial
1.382
1.387
–0.031
–0.026
3.268
3.262
0.174
0.168
Table 4–94 lists clock timing specifications.
Table 4–94. EP1AGX60 Row Pins Regional Clock Timing Parameters
Fast Model
Parameter –6 Speed Grade
t
CIN t
COUT t
PLLCIN t
PLLCOUT
Industrial
1.649
1.651
0.245
0.245
Commercial
1.649
1.651
0.245
0.245
3.835
3.839
0.755
0.755
Units
ns ns ns ns
Units
ns ns ns ns
EP1AGX90 Clock Timing Parameters
through Table 4–96 list the GCLK clock timing parameters for EP1AGX90
devices.
Table 4–95 lists clock timing specifications.
Table 4–95. EP1AGX90 Row Pins Global Clock Timing Parameters
Fast Model
Parameter –6 Speed Grade
t
CIN t
COUT t
PLLCIN t
PLLCOUT
Industrial
1.630
1.635
–0.422
–0.417
Commercial
1.630
1.635
–0.422
–0.417
3.799
3.793
–0.310
–0.316
Units
ns ns ns ns
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–84 Chapter 4: DC and Switching Characteristics
Block Performance
lists clock timing specifications.
Table 4–96. EP1AGX90 Row Pins Global Clock Timing Parameters
Fast Model
Parameter –6 Speed Grade
t
CIN t
COUT t
PLLCIN t
PLLCOUT
Industrial
1.904
1.904
–0.153
–0.153
Commercial
1.904
1.904
–0.153
–0.153
4.376
4.376
0.254
0.254
Units
ns ns ns ns
Table 4–97 through Table 4–98 list the RCLK clock timing parameters for EP1AGX90
devices.
Table 4–97 lists clock timing specifications.
Table 4–97. EP1AGX90 Row Pins Regional Clock Timing Parameters
Fast Model
Parameter –6 Speed Grade
t
CIN t
COUT t
PLLCIN t
PLLCOUT
Industrial
1.462
1.467
–0.430
–0.425
Commercial
1.462
1.467
–0.430
–0.425
3.407
3.401
–0.322
–0.328
Table 4–98 lists clock timing specifications.
Table 4–98. EP1AGX90 Row Pins Regional Clock Timing Parameters
Fast Model
Parameter –6 Speed Grade
t
CIN t
COUT t t
PLLCIN
PLLCOUT
Industrial
1.760
1.760
–0.118
–0.118
Commercial
1.760
1.760
–0.118
–0.118
4.011
4.011
0.303
0.303
Units
ns ns ns ns ns ns ns ns
Units
Block Performance
shows the Arria GX performance for some common designs. All performance values were obtained with the Quartus II software compilation of library of parameterized modules (LPM) or MegaCore functions for finite impulse response
(FIR) and fast Fourier transform (FFT) designs.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Block Performance
lists performance notes.
Table 4–99. Arria GX Performance Notes
Applications
LE
TriMatrix Memory
M512 block
TriMatrix Memory
M4K block
TriMatrix Memory
MegaRAM block
16-to-1 multiplexer
32-to-1 multiplexer
16-bit counter
64-bit counter
Simple dual-port
RAM 32 x 18 bit
FIFO 32 x 18 bit
Simple dual-port
RAM 128 x 36 bit
True dual-port
RAM 128 x 18 bit
Single port RAM
4K x 144 bit
Simple dual-port
RAM 4K x 144 bit
True dual-port
RAM 4K x 144 bit
Single port RAM
8K x 72 bit
Simple dual-port
RAM 8K x 72 bit
Single port RAM
16K x 36 bit
Simple dual-port
RAM 16K x 36 bit
True dual-port
RAM 16K x 36 bit
Single port RAM
32K x 18 bit
Simple dual-port
RAM 32K x 18 bit
True dual-port
RAM 32K x 18 bit
Single port RAM
64K x 9 bit
Simple dual-port
RAM 64K x 9 bit
True dual-port
RAM 64K x 9 bit
ALUTs
5
11
0
0
16
64
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Resources Used
TriMatrix
Memory Blocks
0
0
0
0
1
1
1
1
2
1
2
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
DSP Blocks
0
0
0
0
0
0
0
0
0
0
0
0
0
0
292.0
254.0
292.0
251.0
244.0
292.0
244.0
247.0
Performance
–6 Speed Grade
168.41
334.11
374.0
168.41
348.0
333.22
344.71
348.0
317.36
292.0
251.0
254.0
292.0
251.0
4–85
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–86 Chapter 4: DC and Switching Characteristics
IOE Programmable Delay
Table 4–99. Arria GX Performance Notes
DSP block
Applications
Larger Designs
9 x 9-bit multiplier
18 x 18-bit multiplier
18 x 18-bit multiplier
36 x 36-bit multiplier
36 x 36-bit multiplier
18-bit 4-tap FIR filter
8-bit 16-tap parallel FIR filter
0
0
0
0
0
ALUTs
0
0
Resources Used
TriMatrix
Memory Blocks
0
0
0
0
0
0
0
DSP Blocks
1
2
8
8
4
8
4
Performance
–6 Speed Grade
335.35
285.0
335.35
174.4
285.0
163.0
163.0
IOE Programmable Delay
For IOE programmable delay, refer to
Table 4–100 lists IOE programmable delays.
Table 4–100. Arria GX IOE Programmable Delay on Row Pins
Parameter Paths Affected
Available
Settings
8
Fast Model
Industrial
Min
Offset
0
Max
Offset
1.782
Commercial
Min
Offset
0
Max
Offset
1.782
Input delay from pin to internal cells
Input delay from pin to input register
Delay from output register to output pin
Output enable pin delay
Pad to I/O dataout to core
Pad to I/O input register
I/O output register to pad txz/tzx
64
2
2
0
0
0
2.054
0.332
0.32
0
0
0
2.054
0.332
0.32
–6 Speed Grade
Min
Offset
0
0
0
0
Max
Offset
4.124
4.689
0.717
0.693
Units
ns ns ns ns
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Maximum Input and Output Clock Toggle Rate
4–87
Table 4–101 lists IOE programmable delays.
Table 4–101. Arria GX IOE Programmable Delay on Column Pins
Parameter Paths Affected
Available
Settings
Industrial
Fast Model
Commercial
8
Min
Offset
0
Max
Offset
1.781
Min
Offset
0
Max
Offset
1.781
Input delay from pin to internal cells
Input delay from pin to input register
Delay from output register to output pin
Output enable pin delay
Pad to I/O dataout to core
Pad to I/O input register
I/O output register to pad txz/tzx
64
2
2
0
0
0
2.053
0.332
0.32
0
0
0
2.053
0.332
0.32
–6 Speed Grade
Min
Offset
0
0
0
0
Max
Offset
4.132
4.697
0.717
0.693
Units
ns ns ns ns
Maximum Input and Output Clock Toggle Rate
Maximum clock toggle rate is defined as the maximum frequency achievable for a clock type signal at an I/O pin. The I/O pin can be a regular I/O pin or a dedicated clock I/O pin.
The maximum clock toggle rate is different from the maximum data bit rate. If the maximum clock toggle rate on a regular I/O pin is 300 MHz, the maximum data bit rate for dual data rate (DDR) could be potentially as high as 600 Mbps on the same
I/O pin.
provide output toggle rates at the default capacitive loading. Use the Quartus II software to obtain output toggle rates at loads different from the default capacitive loading.
Table 4–102 shows the maximum input clock toggle rates for Arria GX device column
I/O pins.
Table 4–102. Arria GX Maximum Input Toggle Rate for Column I/O Pins
I/O Standards
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5 V
SSTL-2 CLASS I
SSTL-2 CLASS II
SSTL-18 CLASS I
–6 Speed Grade
420
420
420
420
420
467
467
467
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–88 Chapter 4: DC and Switching Characteristics
Maximum Input and Output Clock Toggle Rate
Table 4–102. Arria GX Maximum Input Toggle Rate for Column I/O Pins
I/O Standards
SSTL-18 CLASS II
1.8-V HSTL CLASS I
1.8-V HSTL CLASS II
1.5-V HSTL CLASS I
1.5-V HSTL CLASS II
3.3-V PCI
3.3-V PCI-X
–6 Speed Grade
467
467
467
467
467
420
420
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Table 4–103 shows the maximum input clock toggle rates for Arria GX device row I/O
pins.
Table 4–103. Arria GX Maximum Input Toggle Rate for Row I/O Pins
I/O Standards
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5 V
SSTL-2 CLASS I
SSTL-2 CLASS II
SSTL-18 CLASS I
SSTL-18 CLASS II
1.8-V HSTL CLASS I
1.8-V HSTL CLASS II
1.5-V HSTL CLASS I
1.5-V HSTL CLASS II
LVDS
–6 Speed Grade
420
420
420
420
420
467
467
467
467
467
467
467
467
392
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Table 4–104 shows the maximum input clock toggle rates for Arria GX device
dedicated clock pins.
Table 4–104. Arria GX Maximum Input Clock Rate for Dedicated Clock Pins (Part 1 of 2)
I/O Standards
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5 V
SSTL-2 CLASS I
SSTL-2 CLASS II
3.3-V PCI
–6 Speed Grade
373
373
373
373
373
467
467
373
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Maximum Input and Output Clock Toggle Rate
Table 4–104. Arria GX Maximum Input Clock Rate for Dedicated Clock Pins (Part 2 of 2)
I/O Standards –6 Speed Grade
3.3-V PCI-X
SSTL-18 CLASS I
SSTL-18 CLASS II
1.8-V HSTL CLASS I
1.8-V HSTL CLASS II
1.5-V HSTL CLASS I
1.5-V HSTL CLASS II
1.2-V HSTL
373
467
467
467
467
467
467
233
DIFFERENTAL SSTL-2
DIFFERENTIAL 2.5-V
SSTL CLASS II
DIFFERENTIAL 1.8-V
SSTL CLASS I
DIFFERENTIAL 1.8-V
SSTL CLASS II
DIFFERENTIAL 1.8-V
HSTL CLASS I
DIFFERENTIAL 1.8-V
HSTL CLASS II
DIFFERENTIAL 1.5-V
HSTL CLASS I
DIFFERENTIAL 1.5-V
HSTL CLASS II
DIFFERENTIAL 1.2-V
HSTL
LVDS
LVDS
467
467
467
467
467
467
467
467
233
640
373
Note to
(1) This set of numbers refers to the VIO dedicated input clock pins.
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Table 4–105 shows the maximum output clock toggle rates for Arria GX device
column I/O pins.
Table 4–105. Arria GX Maximum Output Toggle Rate for Column I/O Pins (Part 1 of 3)
I/O Standards
3.3-V LVTTL
Drive Strength
4 mA
8 mA
12 mA
16 mA
20 mA
24 mA
–6 Speed Grade
196
303
393
486
570
626
Units
MHz
MHz
MHz
MHz
MHz
MHz
4–89
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–90 Chapter 4: DC and Switching Characteristics
Maximum Input and Output Clock Toggle Rate
Table 4–105. Arria GX Maximum Output Toggle Rate for Column I/O Pins (Part 2 of 3)
I/O Standards
3.3-V LVCMOS
2.5 V
1.8 V
1.5 V
SSTL-2 CLASS I
SSTL-2 CLASS II
SSTL-18 CLASS I
SSTL-18 CLASS II
1.8-V HSTL CLASS I
Drive Strength
373
373
140
327
327
140
186
280
280
327
280
327
168
303
350
392
373
420
280
420
561
561
607
336
486
706
925
514
766
97
215
874
934
168
355
215
411
626
819
24 mA
4 mA
6 mA
8 mA
10 mA
12 mA
8 mA
16 mA
2 mA
4 mA
6 mA
8 mA
8 mA
12 mA
16 mA
20 mA
18 mA
20 mA
4 mA
6 mA
8 mA
10 mA
12 mA
12 mA
16 mA
2 mA
4 mA
6 mA
8 mA
10 mA
12 mA
4 mA
8 mA
12 mA
16 mA
20 mA
24 mA
4 mA
8 mA
–6 Speed Grade Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Maximum Input and Output Clock Toggle Rate
4–91
Table 4–105. Arria GX Maximum Output Toggle Rate for Column I/O Pins (Part 3 of 3)
1.8-V HSTL CLASS II
1.5-V HSTL CLASS I
1.5-V HSTL CLASS II
3.3-V PCI
I/O Standards
3.3-V PCI-X
Drive Strength
16 mA
18 mA
20 mA
4 mA
6 mA
8 mA
10 mA
12 mA
16 mA
18 mA
20 mA
—
—
–6 Speed Grade
514
561
561
626
626
420
561
607
654
420
467
514
280
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Table 4–106 shows the maximum output clock toggle rates for Arria GX device row
I/O pins.
Table 4–106. Arria GX Maximum Output Toggle Rate for Row I/O Pins
2.5 V
1.8 V
1.5 V
I/O Standards
3.3-V LVTTL
3.3-V LVCMOS
SSTL-2 CLASS I
SSTL-2 CLASS II
SSTL-18 CLASS I
Drive Strength
486
168
303
280
514
97
215
336
196
303
393
215
411
168
355
327
280
140
186
280
373
12 mA
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
8 mA
4 mA
8 mA
12 mA
4 mA
8 mA
4 mA
8 mA
12 mA
16 mA
4 mA
6 mA
8 mA
10 mA
–6 Speed Grade Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–92 Chapter 4: DC and Switching Characteristics
Maximum Input and Output Clock Toggle Rate
Table 4–106. Arria GX Maximum Output Toggle Rate for Row I/O Pins
LVDS
I/O Standards
1.8-V HSTL CLASS I
1.5-V HSTL CLASS I
Drive Strength
4 mA
6 mA
8 mA
10 mA
12 mA
4 mA
6 mA
8 mA
—
–6 Speed Grade
607
280
420
561
280
420
561
561
598
Table 4–107 lists maximum output clock rate for dedicated clock pins.
Table 4–107. Arria GX Maximum Output Clock Rate for Dedicated Clock Pins (Part 1 of 4)
2.5 V
1.8 V
1.5 V
I/O Standards
3.3-V LVTTL
3.3-V LVCMOS
Drive Strength
12 mA
16 mA
2 mA
4 mA
6 mA
8 mA
10 mA
12 mA
2 mA
4 mA
6 mA
8 mA
4 mA
8 mA
12 mA
16 mA
20 mA
24 mA
4 mA
8 mA
4 mA
8 mA
12 mA
16 mA
20 mA
24 mA
–6 Speed Grade
336
486
706
925
514
766
97
215
168
303
350
392
874
934
168
355
215
411
626
819
196
303
393
486
570
626
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Maximum Input and Output Clock Toggle Rate
Table 4–107. Arria GX Maximum Output Clock Rate for Dedicated Clock Pins (Part 2 of 4)
I/O Standards
SSTL-2 CLASS I
SSTL-2 CLASS II
SSTL-18 CLASS I
SSTL-18 CLASS II
1.8-V HSTL CLASS I
1.8-V HSTL CLASS II
1.5-V HSTL CLASS I
1.5-V HSTL CLASS II
DIFFERENTIAL SSTL-2
DIFFERENTIAL 2.5-V
SSTL CLASS II
Drive Strength
8 mA
10mA
12 mA
16 mA
18 mA
20 mA
24 mA
8 mA
8 mA
10 mA
12 mA
16 mA
18 mA
20 mA
4 mA
6 mA
12 mA
16 mA
20 mA
24 mA
10 mA
12 mA
8 mA
16 mA
18 mA
20 mA
4 mA
6 mA
8 mA
12 mA
16 mA
20 mA
24 mA
4 mA
6 mA
8 mA
–6 Speed Grade
561
561
278
280
561
607
654
514
327
280
327
327
467
514
280
420
561
561
607
420
373
420
280
420
373
373
140
327
327
140
186
280
280
327
280
327
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
4–93
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–94 Chapter 4: DC and Switching Characteristics
Maximum Input and Output Clock Toggle Rate
Table 4–107. Arria GX Maximum Output Clock Rate for Dedicated Clock Pins (Part 3 of 4)
DIFFERENTIAL 1.8-V
SSTL CLASS I
DIFFERENTIAL 1.8-V
SSTL CLASS II
DIFFERENTIAL 1.8-V
HSTL CLASS I
DIFFERENTIAL 1.8-V
HSTL CLASS II
DIFFERENTIAL 1.5-V
HSTL CLASS I
DIFFERENTIAL 1.5-V
HSTL CLASS II
3.3-V PCI
3.3-V PCI-X
LVDS
HYPERTRANSPORT
LVPECL
3.3-V LVTTL
2.5 V
1.8 V
I/O Standards
3.3-V LVCMOS
Drive Strength
20 mA
4 mA
6 mA
8 mA
10 mA
12 mA
16 mA
18 mA
20 mA
24 mA
—
—
—
—
—
SERIES_25_OHMS
20 mA
4 mA
6 mA
8 mA
10 mA
12 mA
16 mA
18 mA
4 mA
6 mA
8 mA
10 mA
12 mA
8 mA
16 mA
18 mA
SERIES_50_OHMS
SERIES_25_OHMS
SERIES_50_OHMS
SERIES_25_OHMS
SERIES_50_OHMS
SERIES_25_OHMS
SERIES_50_OHMS
–6 Speed Grade
280
116
280
327
561
278
626
626
607
654
514
561
514
280
420
561
327
280
280
280
280
420
420
561
607
420
467
420
280
420
561
373
140
327
373
140
186
280
373
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Duty Cycle Distortion
4–95
Table 4–107. Arria GX Maximum Output Clock Rate for Dedicated Clock Pins (Part 4 of 4)
I/O Standards
1.5 V
SSTL-2 CLASS I
SSTL-2 CLASS II
SSTL-18 CLASS I
SSTL-18 CLASS II
1.8-V HSTL CLASS I
1.8-V HSTL CLASS II
1.5-V HSTL CLASS I
1.2-V HSTL
DIFFERENTIAL SSTL-2
DIFFERENTIAL 2.5-V
SSTL CLASS II
DIFFERENTIAL 1.8-V
SSTL CLASS I
DIFFERENTIAL 1.8-V
SSTL CLASS II
DIFFERENTIAL 1.8-V
HSTL CLASS I
DIFFERENTIAL 1.8-V
HSTL CLASS II
DIFFERENTIAL 1.5-V
HSTL CLASS I
DIFFERENTIAL 1.2-V
HSTL
Drive Strength
SERIES_50_OHMS
SERIES_50_OHMS
SERIES_25_OHMS
SERIES_50_OHMS
SERIES_25_OHMS
SERIES_50_OHMS
SERIES_25_OHMS
SERIES_50_OHMS
SERIES_50_OHMS
SERIES_50_OHMS
SERIES_25_OHMS
SERIES_50_OHMS
SERIES_25_OHMS
SERIES_50_OHMS
SERIES_25_OHMS
SERIES_50_OHMS
SERIES_50_OHMS
–6 Speed Grade
420
561
420
467
373
467
467
327
233
467
467
327
420
561
420
467
233
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Duty Cycle Distortion
Duty cycle distortion (DCD) describes how much the falling edge of a clock is off from its ideal position. The ideal position is when both the clock high time (CLKH) and the clock low time (CLKL) equal half of the clock period (T), as shown in
.
DCD is the deviation of the non-ideal falling edge from the ideal falling edge, such as
D1 for the falling edge A and D2 for the falling edge B (refer to Figure 4–10 ). The
maximum DCD for a clock is the larger value of D1 and D2.
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–96 Chapter 4: DC and Switching Characteristics
Duty Cycle Distortion
Figure 4–10. Duty Cycle Distortion
CLKH = T/2
Ideal Falling Edge
CLKL = T/2
D1 D2
Falling Edge A Falling Edge B
Clock Period (T)
DCD expressed in absolution derivation, for example, D1 or D2 in
clock-period independent. DCD can also be expressed as a percentage, and the percentage number is clock-period dependent. DCD as a percentage is defined as:
(T/2 – D1) / T (the low percentage boundary)
(T/2 + D2) / T (the high percentage boundary)
DCD Measurement Techniques
DCD is measured at an FPGA output pin driven by registers inside the corresponding
I/O element (IOE) block. When the output is a single data rate signal (non-DDIO), only one edge of the register input clock (positive or negative) triggers output transitions (
Figure 4–11 ). Therefore, any DCD present on the input clock signal or
caused by the clock input buffer or different input I/O standard does not transfer to the output signal.
Figure 4–11. DCD Measurement Technique for Non-DDIO (Single-Data Rate) Outputs
However, when the output is a double data rate input/output (DDIO) signal, both edges of the input clock signal (positive and negative) trigger output transitions
(
Figure 4–12 ). Therefore, any distortion on the input clock and the input clock buffer
affect the output DCD.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Duty Cycle Distortion
Figure 4–12. DCD Measurement Technique for DDIO (Double-Data Rate) Outputs
4–97
When an FPGA PLL generates the internal clock, the PLL output clocks the IOE block.
As the PLL only monitors the positive edge of the reference clock input and internally re-creates the output clock signal, any DCD present on the reference clock is filtered out. Therefore, the DCD for a DDIO output with PLL in the clock path is better than the DCD for a DDIO output without PLL in the clock path.
show the maximum DCD in absolution derivation for different I/O standards on Arria GX devices. Examples are also provided that show how to calculate DCD as a percentage.
Table 4–108. Maximum DCD for Non-DDIO Output on Row I/O Pins
Maximum DCD (ps) for Non-DDIO Output
Row I/O Output Standard
3.3-V LVTTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
1.8-V HSTL Class I
1.5-V HSTL Class I
LVDS
–6 Speed Grade
275
155
135
180
195
145
125
85
100
115
80
Units
ps ps ps ps ps ps ps ps ps ps ps
Here is an example for calculating the DCD as a percentage for a non-DDIO output on a row I/O:
If the non-DDIO output I/O standard is SSTL-2 Class II, the maximum DCD is 125 ps
(see Table 4–109 ). If the clock frequency is 267 MHz, the clock period T is:
T = 1/ f = 1 / 267 MHz = 3.745 ns = 3,745 ps
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–98 Chapter 4: DC and Switching Characteristics
Duty Cycle Distortion
To calculate the DCD as a percentage:
(T/2 – DCD) / T = (3,745 ps/2 – 125 ps) / 3,745 ps = 46.66% (for low boundary)
(T/2 + DCD) / T = (3,745 ps/2 + 125 ps) / 3,745 ps = 53.33% (for high boundary)
Therefore, the DCD percentage for the output clock at 267 MHz is from 46.66% to
53.33%.
Table 4–109. Maximum DCD for Non-DDIO Output on Column I/O Pins
Column I/O Output Standard I/O Standard
Maximum DCD (ps) for Non-DDIO Output
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL-12
LVPECL
–6 Speed Grade
220
135
130
115
100
175
155
110
215
110
110
115
80
200
80
Units
ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Table 4–110. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path
Note (1)
Input I/O Standard (No PLL in the Clock Path)
Maximum DCD (ps) for
Row DDIO Output I/O
Standard
TTL/CMOS SSTL-2 SSTL/HSTL LVDS
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
1.8-V HSTL Class I
1.5-V HSTL Class I
3.3/2.5V
440
390
375
325
430
355
350
335
330
330
1.8/1.5V
495
450
430
385
490
410
405
390
385
390
2.5V
170
120
105
90
160
85
80
65
60
60
1.8/1.5V
160
110
95
100
155
75
70
65
70
70
3.3V
105
75
90
135
100
85
90
105
110
105
Units
ps ps ps ps ps ps ps ps ps ps
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
Duty Cycle Distortion
Table 4–110. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path
Note (1)
Maximum DCD (ps) for
Row DDIO Output I/O
Standard
Input I/O Standard (No PLL in the Clock Path)
TTL/CMOS
3.3/2.5V
1.8/1.5V
LVDS 180
Note to
(1)
Table 4–110 assumes the input clock has zero DCD.
180
SSTL-2
2.5V
180
SSTL/HSTL
1.8/1.5V
180
LVDS
3.3V
180
Units
ps
Table 4–111. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path
Maximum DCD (ps) for
DDIO Column Output I/O
Standard
Input IO Standard (No PLL in the Clock Path)
TTL/CMOS
3.3/2.5V
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
LVPECL
Note to
(1)
Table 4–111 assumes the input clock has zero DCD.
330
330
330
180
350
335
320
330
440
390
375
325
430
355
1.8/1.5V
385
390
360
180
405
390
375
385
495
450
430
385
490
410
SSTL-2
2.5V
60
60
90
180
80
65
70
60
170
120
105
90
160
85
SSTL/HSTL
1.8/1.5V
70
70
100
180
70
65
80
70
160
110
95
100
155
75
Units
ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Table 4–112. Maximum DCD for DDIO Output on Row I/O Pins With PLL in the Clock Path
Maximum DCD (ps) for Row DDIO Output I/O Standard
Arria GX Devices (PLL Output
Feeding DDIO)
3.3-V LVTTL
3.3-V LVCMOS
2.5V
1.8V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
–6 Speed Grade
105
75
90
100
100
75
70
Units
ps ps ps ps ps ps ps
4–99
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–100 Chapter 4: DC and Switching Characteristics
High-Speed I/O Specifications
Table 4–112. Maximum DCD for DDIO Output on Row I/O Pins With PLL in the Clock Path
Maximum DCD (ps) for Row DDIO Output I/O Standard
Arria GX Devices (PLL Output
Feeding DDIO)
SSTL-18 Class I
1.8-V HSTL Class I
1.5-V HSTL Class I
LVDS
–6 Speed Grade
65
70
70
180
Units
ps ps ps ps
Table 4–113. Maximum DCD for DDIO Output on Column I/O Pins With PLL in the Clock Path
Maximum DCD (ps) for Column
DDIO Output I/O Standard
Arria GX Devices (PLL Output
Feeding DDIO)
Units
3.3-V LVTTL
3.3-V LVCMOS
2.5V
1.8V
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.2-V HSTL
LVPECL
–6 Speed Grade
70
70
100
155
70
65
80
70
180
160
110
95
100
155
75 ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
High-Speed I/O Specifications
Table 4–114 lists high-speed timing specifications definitions.
Table 4–114. High-Speed Timing Specifications and Definitions (Part 1 of 2)
High-Speed Timing Specifications
t
C f
H S C L K
J
W t
R I S E t
F A L L
Definitions
High-speed receiver/transmitter input and output clock period.
High-speed receiver/transmitter input and output clock frequency.
Deserialization factor (width of parallel data bus).
PLL multiplication factor.
Low-to-high transmission time.
High-to-low transmission time.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
High-Speed I/O Specifications
4–101
Table 4–114. High-Speed Timing Specifications and Definitions (Part 2 of 2) t t f f
High-Speed Timing Specifications
Timing unit interval (TUI)
H S D R
H S D R D PA
Channel-to-channel skew (TCCS)
Sampling window (SW)
Input jitter
Output jitter
D U T Y
L O CK
Definitions
The timing budget allowed for skew, propagation delays, and data sampling window.
(TUI = 1/(Receiver Input Clock Frequency × Multiplication Factor) = t
C
/w).
Maximum/minimum LVDS data transfer rate (f
H S D R
= 1/TUI), non-DPA.
Maximum/minimum LVDS data transfer rate (f
H S D R D P A
= 1/TUI), DPA.
The timing difference between the fastest and slowest output edges, including t
C O variation and clock skew. The clock is included in the TCCS measurement.
The period of time during which the data must be valid in order to capture it correctly. The setup and hold times determine the ideal strobe position within the sampling window.
Peak-to-peak input jitter on high-speed PLLs.
Peak-to-peak output jitter on high-speed PLLs.
Duty cycle on high-speed transmitter output clock.
Lock time for high-speed transmitter and receiver PLLs.
Table 4–115 shows the high-speed I/O timing specifications.
Table 4–115. High-Speed I/O Specifications (Part 1 of 2)
Symbol Conditions
W = 2 to 32 (LVDS, HyperTransport technology)
f
H S C L K f
H S C L K
(clock frequency)
= f
H S D R
/ W
W = 1 (SERDES bypass, LVDS only)
W = 1 (SERDES used, LVDS only) f
H S D R
(data rate)
J = 4 to 10 (LVDS, HyperTransport technology)
J = 2 (LVDS, HyperTransport technology)
J = 1 (LVDS only) f
H S D R D PA
(DPA data rate) J = 4 to 10 (LVDS, HyperTransport technology)
TCCS All differential I/O standards
SW All differential I/O standards
Output jitter
Output t
R I SE
Output t
F AL L t
D U T Y
DPA run length
DPA jitter tolerance
—
All differential I/O standards
All differential I/O standards
—
—
Data channel peak-to-peak jitter
Min
16
150
—
440
16
150
150
—
—
—
–6 Speed Grade
Typ
—
—
—
—
—
—
—
—
—
—
—
—
45 50
Units
Max
420
500
840
200
—
500
640
840
700
190
290 ps ps
290 ps
55 %
Mbps
Mbps ps ps
MHz
MHz
MHz
Mbps
Mbps
—
0.44
—
—
6,400
—
UI
UI
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–102 Chapter 4: DC and Switching Characteristics
High-Speed I/O Specifications
Table 4–115. High-Speed I/O Specifications (Part 2 of 2)
Note (1), (2)
–6 Speed Grade
Symbol Conditions Units
Min Typ Max
Standard Training Pattern Transition
Density
10%
— —
DPA lock time
SPI-4
Parallel Rapid
I/O
Miscellaneous
000000000011
11111111
00001111
10010000
10101010
25%
50%
100%
256
256
256
256
—
—
—
—
—
—
—
—
Number of repetitions
01010101 — 256 — —
(1) When J = 4 to 10, the SERDES block is used.
(2) When J = 1 or 2, the SERDES block is bypassed.
(3) The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150
input clock frequency × W 1,040.
(4) The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and the clock routing resource
(global, regional, or local) used. The I/O differential buffer and input register do not have a minimum toggle rate.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
PLL Timing Specifications
4–103
PLL Timing Specifications
and Table 4–117 describe the Arria GX PLL specifications when operating
in both the commercial junction temperature range (0 to 85 C) and the industrial junction temperature range (–40 to 100 C), except for the clock switchover and phase-shift stepping features. These two features are only supported from the 0 to
100 C junction temperature range.
Table 4–116. Enhanced PLL Specifications (Part 1 of 2) f f f f f t t t t f f t f t t t f f t f
IN f
INPFD
INDUTY
ENDUTY
INJITTER
OUTJITTER
FCOMP
OUT
SCANCLK
OUT_EXT
OUTDUTY
CLBW
VCO
SS
PLL_PSERR
ARESET
Name
CONFIGEPLL
LOCK
DLOCK
SWITCHOVER
% spread
ARESET_RECONFIG
Description
Input clock frequency
Input frequency to the PFD
Input clock duty cycle
External feedback input clock duty cycle
Input or external feedback clock input jitter tolerance in terms of period jitter.
Bandwidth 0.85 MHz
Input or external feedback clock input jitter tolerance in terms of period jitter.
Bandwidth
0.85 MHz
Dedicated clock output period jitter
External feedback compensation time
Output frequency for internal global or regional clock
Scanclk frequency
Time required to reconfigure scan chains for
EPLLs
PLL external clock output frequency
Duty cycle for external clock output
Time required for the PLL to lock from the time it is enabled or the end of device configuration
Time required for the PLL to lock dynamically after automatic clock switchover between two identical clock frequencies
Frequency range where the clock switchover performs properly
PLL closed-loop bandwidth
PLL VCO operating range
Spread-spectrum modulation frequency
Percent down spread for a given clock frequency
Accuracy of PLL phase shift
Minimum pulse width on areset signal.
Minimum pulse width on the areset signal when using PLL reconfiguration. Reset the PLL after scandone goes high.
Min
2
2
40
40
—
—
50
—
—
—
45
—
—
1.5
0.13
300
100
0.4
—
10
500
Typ
—
—
—
—
0.5
1.0
100
—
—
—
174/f
SCANCLK
50
0.03
—
1
1.2
—
—
0.5
—
—
—
Max
500
420
60
60
—
—
250
10
550
100
—
55
1
1
500
16.9
840
500
0.6
±30
—
—
Units
MHz
MHz
%
% ns (peak-to-peak) ns (peak-to-peak) ps (p-p) ns
MHz
MHz ns
MHz
% ms ms
MHz
MHz
MHz kHz
% ps ns ns
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–104 Chapter 4: DC and Switching Characteristics
PLL Timing Specifications
Table 4–116. Enhanced PLL Specifications (Part 2 of 2)
Name Description Min Typ
t
RECONFIGWAIT
The time required for the wait after the reconfiguration is done and the areset is applied.
—
(1) This is limited by the I/O f
MAX
.
(2) If the counter cascading feature of the PLL is used, there is no minimum output clock frequency.
—
Table 4–117. Fast PLL Specifications (Part 1 of 2) t t t f t f f f t f f f
IN
INPFD
INDUTY
INJITTER
VCO
OUT
OUT_EXT
CONFIGPLL
CLBW
LOCK
PLL_PSERR
ARESET
Name Description
Input clock frequency
Input frequency to the
PFD
Input clock duty cycle
Input clock jitter tolerance in terms of period jitter.
Bandwidth 2 MHz
Input clock jitter tolerance in terms of period jitter.
Bandwidth
0.2 MHz
Upper VCO frequency range
Lower VCO frequency range
PLL output frequency to
GCLK
or
RCLK
PLL output frequency to LVDS or DPA clock
PLL clock output frequency to regular
I/O
Time required to reconfigure scan chains for fast PLLs
PLL closed-loop bandwidth
Time required for the
PLL to lock from the time it is enabled or the end of the device configuration
Accuracy of PLL phase shift
Minimum pulse width on areset
signal.
Min
16.08
16.08
40
—
—
300
150
4.6875
150
4.6875
—
1.16
—
—
10
75/f
Typ
—
—
—
0.5
1.0
—
—
—
—
—
SCANCLK
5
0.03
—
—
Max
640
500
60
—
—
840
420
550
840
—
28
1
Max
Units
MHz
MHz
%
±30 ps
—
2 ns (p-p) ns (p-p)
MHz
MHz
MHz
MHz
MHz ns
MHz ms ns
Units
us
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
External Memory Interface Specifications
4–105
Table 4–117. Fast PLL Specifications (Part 2 of 2)
Name Description
t
ARESET_RECONFIG
Minimum pulse width on the areset
signal when using PLL reconfiguration. Reset the PLL after scandone
goes high.
Note to
(1) This is limited by the I/O f
MAX
.
Min
500
Typ
—
Max
—
Units
ns
External Memory Interface Specifications
list Arria GX device specifications for the dedicated circuitry used for interfacing with external memory devices.
Table 4–118. DLL Frequency Range Specifications
Frequency Mode
0
1
2
Frequency Range (MHz)
100 to 175
150 to 230
200 to 310
Table 4–119. DQS Jitter Specifications for DLL-Delayed Clock (tDQS_JITTER) ,
Number of DQS Delay Buffer Stages
Commercial (ps) Industrial (ps)
3
4
1
2
80
110
130
160
110
130
180
210
(1) Peak-to-peak period jitter on the phase-shifted DQS clock. For example, jitter on two delay stages under commercial conditions is 200 ps peak-to-peak or 100 ps.
(2) Delay stages used for requested DQS phase shift are reported in a project’s Compilation Report in the Quartus II software.
Table 4–120. DQS Phase-Shift Error Specifications for DLL-Delayed Clock (t
DQS_PSERR
)
Number of DQS Delay Buffer Stages
1
2
3
4
–6 Speed Grade (ps)
35
70
105
140
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–106 Chapter 4: DC and Switching Characteristics
JTAG Timing Specifications
Table 4–121. DQS Bus Clock Skew Adder Specifications (t
DQS_CLOCK_SKEW_A DDER
)
Mode
4 DQ per DQS
9 DQ per DQS
18 DQ per DQS
36 DQ per DQS
DQS Clock Skew Adder (ps)
40
70
75
95
Table 4–122. DQS Phase Offset Delay Per Stage (ps)
Positive Offset
Speed Grade
–6
Min
10
Max
16
(1) The delay settings are linear.
(2) The valid settings for phase offset are –32 to +31.
(3) The typical value equals the average of the minimum and maximum values.
Min
8
Negative Offset
Max
12
JTAG Timing Specifications
Figure 4–13 shows the timing requirements for the JTAG signals
Figure 4–13. Arria GX JTAG Waveforms.
TMS
TDI
t
JCH
t
JCP
t
JCL
t
JPSU t
JPH
TCK
t
JPZX t
JSSU t
JSH t
JPCO t
JPXZ
TDO
Signal to be
Captured
Signal to be
Driven
t
JSZX t
JSCO t
JSXZ
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter 4: DC and Switching Characteristics
JTAG Timing Specifications
Table 4–123 lists the JTAG timing parameters and values for Arria GX devices.
Table 4–123. Arria GX JTAG Timing Parameters and Values t t
Symbol
t
JCP t
JCH t
JCL t
JPSU t
JPH t
JPCO t
JPZX t
JPXZ t
JSSU t
JSH t
JSCO
JSZX
JSXZ
TCK clock period
Parameter
TCK clock high time
TCK clock low time
JTAG port setup time
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
Min
30
—
—
—
4
12
12
4
5
5
—
—
—
Max
—
9
9
9
—
—
—
—
—
—
12
12
12 ns
Units
ns ns ns ns ns ns ns ns ns ns ns ns
4–107
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
4–108 Chapter 4: DC and Switching Characteristics
Document Revision History
Document Revision History
lists the revision history for this chapter.
Table 4–124. Document Revision History
Date and Document Version
December 2009, v2.0
April 2009 v1.4
May 2008 v1.3
August 2007 v1.2
June 2007 v1.1
May 2007 v1.0
Changes Made
■
Updated
,
and
■
Document template update.
■
Minor text edits.
■
Updated Table 4–6 and Table 4–7.
■
Updated “Maximum Input and Output
Clock Toggle Rate” section.
Updated:
■
Table 4–5
■
Table 4–7
■
Table 4–8
■
Table 4–9
■
Table 4–10
■
Table 4–11
■
Table 4–12
■
Table 4–13
■
Table 4–14
■
Table 4–15
■
Table 4–16
■
Table 4–17
■
Table 4–43
■
Table 4–116
■
Table 4–117
Updated:
■
Figure 4–4
Minor text edits.
Removed “Preliminary” from each page.
Removed “Preliminary” note from
Tables 4–44, 4–45, and 4–47.
Added “Referenced Documents” section.
Updated Table 4–99.
Added GIGE information.
Initial release.
Summary of Changes
—
—
—
—
—
—
—
—
—
—
—
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
5. Reference and Ordering Information
AGX51005-2.0
Software
Arria ® GX devices are supported by the Altera ® Quartus ® II design software, which provides a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus II software includes HDL and schematic design entry, compilation and logic synthesis, full simulation and advanced timing analysis,
SignalTap
®
II logic analyzer, and device configuration. f
For more information about the Quartus II software features, refer to the
Quartus II
Development Software Handbook
.
The Quartus II software supports the Windows XP/2000/NT, Sun Solaris 8/9, Linux
Red Hat v7.3, Linux Red Hat Enterprise 3, and HP-UX operating systems. It also supports seamless integration with industry-leading EDA tools through the
NativeLink interface.
Device Pin-Outs
f
Arria GX device pin-outs are available on the Altera web site at www.altera.com
.
Ordering Information
describes the ordering codes for Arria GX devices. f
For more information on a specific package, refer to the
Package Information for Arria
GX Devices
chapter.
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
5–2 Chapter 5: Reference and Ordering Information
Document Revision History
Figure 5–1. Arria GX Device Packaging Ordering Information
EP1AGX 20 C F 484 C
Family Signature
EP1AGX : Arria GX
6
20
35
50
60
90
Device Type
Number of
Transceiver
Channels
C: 4
D: 8
E: 12
N
Optional Suffix
Indicates specific device options or shipment method.
N: Lead-free devices
Package Type
F: FineLine BGA (FBGA)
6
Speed Grade
Operating Temperature
C: Commercial temperature (T
J
= 0
I: Industrial temperature (T
J
= -40
˚
C to 85
˚
C)
˚
C to 100
˚
C)
Pin Count
484
780
1152
Document Revision History
Table 5–1 shows the revision history for this chapter.
Table 5–1. Document Revision History
Date and Document
Version
Changes Made
December 2009, v2.0
■
Document template update.
■
Minor text edits.
August 2007, v1.1
Added the “Referenced Documents” section.
May 2007, v1.0
Initial Release.
Summary of Changes
—
—
—
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Additional Information
About this Handbook
This handbook provides comprehensive information about the Altera ® Arria ® GX family of devices.
How to Contact Altera
For the most up-to-date information about Altera products, see the following table.
Contact
Technical support
Technical training
Product literature
Non-technical support (General)
(Software Licensing)
Contact
Method
Website
Website
Address
www.altera.com/support www.altera.com/training [email protected]
www.altera.com/literature [email protected]
Note:
(1) You can also contact your local Altera sales office or sales representative.
Typographic Conventions
The following table shows the typographic conventions that this document uses.
Visual Cue Meaning
Bold Type with Initial Capital
Letters bold type
Indicates command names and dialog box titles. For example, Save As dialog box.
Indicates directory names, project names, disk drive names, file names, file name extensions, dialog box options, software utility names, and other GUI labels. For example, \qdesigns directory, d: drive, and chiptrip.gdf file.
Italic Type with Initial Capital Letters Indicates document titles. For example, AN 519: Stratix IV Design Guidelines.
Italic type Indicates variables. For example, n + 1.
Initial Capital Letters
“Subheading Title”
Variable names are enclosed in angle brackets (< >). For example, <file name> and
<project name>.pof file.
Indicates keyboard keys and menu names. For example, Delete key and the Options menu.
Quotation marks indicate references to sections within a document and titles of
Quartus II Help topics. For example, “Typographic Conventions.”
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
Info–2
Visual Cue
Courier type
1., 2., 3., and a., b., c., and so on.
■
■
1 c w r f
Additional Information
Meaning
Indicates signal, port, register, bit, block, and primitive names. For example, data1, tdi
, and input. Active-low signals are denoted by suffix n. For example, resetn
.
Indicates command line commands and anything that must be typed exactly as it appears. For example, c:\qdesigns\tutorial\chiptrip.gdf.
Also indicates sections of an actual file, such as a Report File, references to parts of files (for example, the AHDL keyword SUBDESIGN), and logic function names (for example, TRI).
Numbered steps indicate a list of items when the sequence of the items is important, such as the steps listed in a procedure.
Bullets indicate a list of items when the sequence of the items is not important.
The hand points to information that requires special attention.
A caution calls attention to a condition or possible situation that can damage or destroy the product or your work.
A warning calls attention to a condition or possible situation that can cause you injury.
The angled arrow instructs you to press Enter.
The feet direct you to more information about a particular topic.
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 2
101 Innovation Drive
San Jose, CA 95134 www.altera.com
AGX5V2-2.0
ii
Copyright © 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services
.
Altera Corporation
Chapter Revision Dates
The chapters in this book, Arria GX Device Handbook, Volume 2, were revised on the following dates.
Where chapters or groups of chapters are available separately, part numbers are listed.
Chapter 1. Arria GX Transceiver Architecture
Chapter 2. Arria GX Transceiver Protocol Support and Additional Features
Chapter 3. Arria GX ALT2GXB Megafunction User Guide
Chapter 4. Specifications and Additional Information
Chapter 5. PLLs in Arria GX Devices
Chapter 6. TriMatrix Embedded Memory Blocks in Arria GX Devices
Chapter 7. External Memory Interfaces in Arria GX Devices
Chapter 8. Selectable I/O Standards in Arria GX Devices
Chapter 9. High-Speed Differential I/O Interfaces with DPA in Arria GX Devices
Altera Corporation iii
Chapter Revision Dates Arria GX Device Handbook, Volume 2
Chapter 10. DSP Blocks in Arria GX Devices
Chapter 11. Configuring Arria GX Devices
Chapter 12. Remote System Upgrades with Arria GX Devices
Chapter 13. IEEE 1149.1 (JTAG) Boundary-Scan Testing for Arria GX Devices
Chapter 14. Package Information for Arria GX Devices
iv
Contents
Chapter Revision Dates .......................................................................... iii
About this Handbook ............................................................................. xiii
Section I. Arria GX Transceiver User Guide
Chapter 1. Arria GX Transceiver Architecture
Altera Corporation v
Contents Arria GX Device Handbook, Volume 2
Chapter 2. Arria GX Transceiver Protocol Support and Additional Features
Recommended Reset Sequence for GIGE and Serial RapidIO in CRU Automatic Lock Mode ..
2–85
Recommended Reset Sequence for GIGE, Serial RapidIO, XAUI, SDI, and Basic Modes in CRU
Chapter 3. Arria GX ALT2GXB Megafunction User Guide
vi
Contents Contents
Chapter 4. Specifications and Additional Information
Section II. Clock Management
Chapter 5. PLLs in Arria GX Devices
and GNDA ............................................................................................................................ 5–54
56
Altera Corporation vii
Contents Arria GX Device Handbook, Volume 2
Section III. Memory
Chapter 6. TriMatrix Embedded Memory Blocks in Arria GX Devices
viii
Contents Contents
Chapter 7. External Memory Interfaces in Arria GX Devices
Section IV. I/O Standards
Chapter 8. Selectable I/O Standards in Arria GX Devices
Chapter 9. High-Speed Differential I/O Interfaces with DPA in Arria GX Devices
Altera Corporation ix
Contents Arria GX Device Handbook, Volume 2
Section V. Digital Signal Processing (DSP)
Chapter 10. DSP Blocks in Arria GX Devices
x
Section VI. Configuration& Remote System Upgrades
Chapter 11. Configuring Arria GX Devices
Contents Contents
Pins ....................................................................................................................................... 11–9
Chapter 12. Remote System Upgrades with Arria GX Devices
Interface Signals between Remote System Upgrade Circuitry & FPGA Logic Array ....... 12–20
Remote System Upgrade With a MAX II Device or Microprocessor & Flash Device ........ 12–28
Altera Corporation xi
Contents Arria GX Device Handbook, Volume 2
Chapter 13. IEEE 1149.1 (JTAG) Boundary-Scan Testing for Arria GX Devices
Section VII. PCB Layout Guidelines
Chapter 14. Package Information for Arria GX Devices
xii
About this Handbook
This handbook provides comprehensive information about the Altera
®
Arria
™
GX family of devices.
How to Contact
Altera
For the most up-to-date information about Altera products, refer to the following table.
Contact
Method
Technical support Website
Website
Technical training
Product literature
Non-technical support
(General)
Website
(Software Licensing) Email
Address
www.altera.com/support www.altera.com/training [email protected]
www.altera.com/literature [email protected]
Note to table:
(1) You can also contact your local Altera sales office or sales representative.
Typographic
Conventions
This document uses the typographic conventions shown below.
Visual Cue Meaning
Bold Type with Initial
Capital Letters
bold type External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and software utility names are shown in bold type. Examples: f
MAX
, \qdesigns directory, d: drive, chiptrip.gdf file.
Italic Type with Initial Capital
Letters
Document titles are shown in italic type with initial capital letters. Example: AN 75:
High-Speed Board Design.
Italic type
Command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. Example: Save As dialog box.
Internal timing parameters and variables are shown in italic type.
Examples: t
PIA
, n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type.
Example: <file name>, <project name>.pof file.
Altera Corporation xiii
Preliminary
Typographic Conventions
Visual Cue
Initial Capital Letters
“Subheading Title”
Courier type
1., 2., 3., and a., b., c., etc.
■
● • v
1 c w r f
Arria GX Device Handbook, Volume 2
Meaning
Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
References to sections within a document and titles of on-line help topics are shown in quotation marks. Example: “Typographic Conventions.”
Signal and port names are shown in lowercase Courier type. Examples: data1
, tdi , input.
Active-low signals are denoted by suffix n , e.g., resetn .
Anything that must be typed exactly as it appears is shown in Courier type. For example: c:\qdesigns\tutorial\chiptrip.gdf
. Also, sections of an actual file, such as a Report File, references to parts of files (e.g., the AHDL keyword
SUBDESIGN
), as well as logic function names (e.g.,
TRI
) are shown in
Courier.
Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure.
Bullets are used in a list of items when the sequence of the items is not important.
The checkmark indicates a procedure that consists of one step only.
The hand points to information that requires special attention.
A caution calls attention to a condition or possible situation that can damage or destory the product or the user’s work.
The warning calls attention to a condition or possible situation that could cause injury to the user.
The angled arrow indicates you should press the Enter key.
The feet direct you to more information on a particular topic.
xiv
Preliminary
Section I. Arria GX
Transceiver User Guide
This section provides information on the configuration modes for
Arria™ GX devices. It also includes information on testing, Arria GX port and parameter information, and pin constraint information.
■
■
This section includes the following chapters:
■
■
Chapter 1, Arria GX Transceiver Architecture
Chapter 2, Arria GX Transceiver Protocol Support and Additional
Chapter 3, Arria GX ALT2GXB Megafunction User Guide
Chapter 4, Specifications and Additional Information
Revision History
Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook.
Altera Corporation Section I–1
Preliminary
Arria GX Transceiver User Guide Arria GX Device Handbook, Volume 2
Section I–2
Preliminary
Altera Corporation
1. Arria GX Transceiver
Architecture
AGX52001-2.0
Introduction
■
■
■
■
■
■
Arria™ GX is a protocol-optimized FPGA family that leverages Altera’s advanced multi-gigabit transceivers. The Arria GX transceiver blocks build on the success of the Stratix
®
II GX family and are optimally designed to support the following serial connectivity protocols
(functional modes):
XAUI
PCI Express (PIPE)
Gigabit Ethernet (GIGE)
SDI
Serial RapidIO
Basic Mode
®
Building Blocks
Arria GX transceivers are structured into full duplex (transmitter and receiver) four-channel groups called transceiver blocks. The Arria GX device family offers up to 12 transceiver channels (three transceiver blocks) per device. You can configure each transceiver block to one of the supported functional modes; for example, four GIGE ports or one four-lane (×4) PCI Express (PIPE) port. In Arria GX devices that offer more than one transceiver block, you can configure each transceiver block to a different functional mode; for example, one transceiver block configured as a four-lane (×4) PCI Express (PIPE) port and the other transceiver block can be configured as four GIGE ports.
shows the Arria GX transceiver block diagram divided into transmitter and receiver circuits.
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May 2008
1–1
Arria GX Transceiver Architecture
Figure 1–1. Arria GX Gigabit Transceiver Block Diagram
alt2gxb
Input rx_datain rx_seriallpbken rx_bitslip rx_enapatternalign rx_analogreset rx_digitalreset rx_cruclk rx_locktorefclk rx_locktodata rx_invpolarity rx_revbitorderwa rx_revbyteorderwa pipe8b10binvpolarity refclk
SIPO
Clock
Recovery
Unit
Receiver
PLL
Word
Aligner
Channel
Aligner
Byte
Deserializer
Rate
Matcher
Phase
Compensation
FIFO
8B/10B
Decoder
Receiver
tx_forceelecidle tx_forcedispcompliance powerdn tx_detectrxloopback tx_datain tx_ctrlenable tx_digitalreset tx_forcedisp tx_invpolarity tx_dispval fixedclk cal_blk_clk cal_blk_powerdown pll_inclk gxb_powerdown gxb_enable
PIPE
Interface
Transmitter
Central
Block
Phase
Compensation
FIFO
Byte
Serializer
High-Speed
Clock
Transmitter
Clock
Divider
Central
Control
Unit
Reset
Logic
8B/10B
Encoder
PISO
XAUI, PCIe, and GIGE
State Machines
PIPE
Interface
Output rx_dataout rx_signaldetect rx_syncstatus rx_patterndetect debug_rx_phase_comp_fifo_error pipephydonestatus pipeelecidle pipestatus rxvalid rx_errdetect rx_ctrldetect rx_disperr rx_bisterr rx_bistdone tx_dataout tx_clkout coreclkout debug_tx_phase_comp_fifo_error pll_locked rx_channelaligned
1–2
Arria GX Device Handbook, Volume 1 May 2008
Port List
Port List
You instantiate the Arria GX transceivers using the ALT2GXB MegaCore
® instance provided in the Quartus
®
II MegaWizard
®
Plug-In Manager. The
ALT2GXB instance allows you to configure the transceivers for your intended protocol and select optional control and status ports to and from the instantiated transceiver channels.
Table 1–1. Arria GX ALT2GXB Ports (Part 1 of 6)
Port Name
Input/
Output
Description
Receiver Physical Coding Sublayer (PCS) Ports
rx_dataout rx_clkout
Output Receiver parallel data output. The bus width depends on the channel width multiplied by the number of channels per instance.
Output Recovered clock from the receiver channel. rx_coreclk rx_enapatternalign rx_bitslip rx_rlv pipe8b10binvpolarity
Input Optional read clock port for the receiver phase compensation first-in first-out (FIFO). If not selected, the Quartus II software automatically selects rx_clkout/tx_clkout as the read clock for receiver phase compensation
FIFO. If selected, you must drive this port with a clock that is frequency locked to rx_clkout/tx_clkout
.
Input
Input
Enables word aligner to align to the comma.
This port can be either edge or level sensitive based on the word aligner mode.
Word aligner bit slip control. The word aligner slips a bit of the current word boundary every rising edge of this signal.
Output Run-length violation indicator. A high signal is driven when the run length (consecutive '1's or
'0's) of the received data exceeds the configured limit.
Input Physical Interface for PCI Express (PIPE) polarity inversion at the 8B/10B decoder input.
This port inverts the data at the input to the
8B/10B decoder.
Scope
—
Channel
Channel
Channel
Channel
Channel
Channel
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Arria GX Device Handbook, Volume 1
Arria GX Transceiver Architecture
Table 1–1. Arria GX ALT2GXB Ports (Part 2 of 6)
Port Name
pipestatus pipephydonestatus rx_pipedatavalid pipeelecidle rx_digitalreset rx_bisterr rx_bistdone rx_ctrldetect rx_errdetect
Input/
Output
Description
Output PIPE receiver status port. In case of multiple status signals, the lower number signal takes precedence.
000 - Received data OK
001 - 1 skip added (not supported)
010 - 1 skip removed (not supported)
011 - Receiver detected
100 - 8B/10B decoder error
101 - Elastic buffer overflow
110 - Elastic buffer underflow
111 - Received disparity error
Output PIPE indicates a mode transition completion-power transition and rx_detect
.
A pulse is given.
Output PIPE valid data indicator on the rx_dataout port.
Output PIPE signal detect for PCI Express.
Input Reset port for the receiver PCS block. This port resets all the digital logic in the receiver channel. The minimum pulse width is two parallel clock cycles.
Output Built-in self test (BIST) block error flag. This port latches high if an error is detected.
Assertion of rx_digitalreset resets the
BIST verifier, which clears the error flag.
Output Built-in self test verifier done flag. This port goes high if the receiver finishes reception of the test sequence.
Output Receiver control code indicator port. Indicates whether the data at the output of rx_dataout
is a control or data word. Used with the 8B/10B decoder.
Output 8B/10B code group violation signal. Indicates that the data at the output of rx_dataout has a code violation or a disparity error. Used with disparity error signal to differentiate between a code group error and/or a disparity error. In addition, in XAUI mode, rx_errdetect
is asserted in the corresponding byte position when ALT2GXB substitutes the received data with 9'b1FE because of XAUI protocol violations.
Scope
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
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Arria GX Device Handbook, Volume 1 May 2008
Port List
Table 1–1. Arria GX ALT2GXB Ports (Part 3 of 6)
Port Name
Input/
Output
Description
rx_syncstatus rx_disperr rx_patterndetect rx_invpolarity rx_revbitorderwa
Output Indicates when the word aligner either aligns to a new word boundary (in single width mode the rx_patterndetect
port is level sensitive), indicates that a resynchronization is needed
(the rx_patterndetect
is edge sensitive), or indicates if synchronization is achieved or not (the dedicated synchronization state machine is used).
Output 8B/10B disparity error indicator port. Indicates that the data at the output of rx_dataout has a disparity error.
Output Indicates when the word aligner detects the alignment pattern in the current word boundary.
Input Inverts the polarity of the received data at the input of the word aligner
Input Available in Basic mode with bit-slip word alignment enabled. Reverses the bit-order of the received data at a byte level at the output of the word aligner.
Output Indicates receiver phase compensation FIFO overrun or underrun situation debug_rx_phase_comp_ fifo_error
Receiver Physical Media Attachment (PMA)
rx_pll_locked rx_analogreset
Output Receiver PLL locked signal. Indicates if the receiver PLL is phase locked to the CRU reference clock.
Input Receiver analog reset. Resets all analog circuits in the receiver PMA.
rx_freqlocked rx_signaldetect
Output CRU mode indicator port. Indicates if the CRU is locked to data mode or locked to the reference clock mode.
0 – Receiver CRU is in lock-to-reference clock mode
1 – Receiver CRU is in lock-to-data mode
Output Signal detect port. In PIPE mode, indicates if a signal that meets the specified range is present at the input of the receiver buffer. In all other modes, rx_signaldetect
is forced high and must not be used as an indication of a valid signal at receiver input.
Scope
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
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May 2008
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Arria GX Transceiver Architecture
Table 1–1. Arria GX ALT2GXB Ports (Part 4 of 6)
Port Name
rx_seriallpbken rx_locktodata rx_locktorefclk
Input/
Output
Input
Input
Input
Input
Description
Serial loopback control port.
0 – normal data path, no serial loopback
1 – serial loopback
Lock-to-data control for the CRU. Use with rx_locktorefclk
.
Lock-to-reference lock mode for the CRU. Use with rx_locktodata
.
rx_locktodata
/ rx
_ locktorefclk
0/0 – CRU is in automatic mode
0/1 – CRU is in lock-to-reference clock
1/0 – CRU is in lock-to-data mode
1/1 – CRU is in lock-to-data mode
Receiver PLL/CRU reference clock.
rx_cruclk
Transmitter PCS
tx_datain tx_clkout tx_coreclk tx_detectrxloopback tx_forceelecidle tx_forcedispcompliance
Input Transmitter parallel data input. The bus width depends on the channel width for the selected functional mode multiplied by the number of channels in the instance.
Output PLD logic array clock from the transceiver to the PLD. In an individual-channel mode, there is one tx_clkout
per channel.
Input
Input
Input
Input
Optional write clock port for the transmitter phase compensation FIFO. If not selected, the
Quartus II software automatically selects tx_clkout as the write clock for transmitter phase compensation FIFO. If selected, you must drive this port with a clock that is frequency locked to tx_clkout
.
PIPE receiver detect / loopback pin.
Depending on the power-down state ( P0 or
P1
), the signal either activates receiver detect or loopback.
PIPE Electrical Idle mode.
PIPE forced negative disparity port for transmission of the compliance pattern. The pattern requires starting at a negative disparity.
Assertion of this port at the first byte ensures that the first byte has a negative disparity. This port must be deasserted after the first byte.
Scope
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
Channel
1–6
Arria GX Device Handbook, Volume 1 May 2008
Port List
Table 1–1. Arria GX ALT2GXB Ports (Part 5 of 6)
powerdn
Port Name
tx_digitalreset tx_ctrlenable tx_invpolarity debug_tx_phase_comp_ fifo_error
Transmitter PMA
fixedclk
Input/
Output
Description
Input
Input
PIPE power mode port. This port sets the power mode of the associated PCI Express channel. The power modes are as follows:
2'b00: P0 – Normal operation
2'b01: P0s – Low recovery time latency, power saving state
2'b10: P1 – Longer recovery time (64
μs max) latency, lower power state
2'b11: P2 – Lowest power state
Reset port for the transmitter PCS block. This port resets all the digital logic in the transmit channel. The minimum pulse width is two parallel clock cycles.
Input Transmitter control code indicator port.
Indicates whether the data at the tx_datain port is a control or data word. This port is used with the 8B/10B encoder.
Input Available in all modes. Inverts the polarity of the data to be transmitted at the transmitter
PCS-PMA interface (input to the serializer).
Output Indicates transmitter phase compensation
FIFO overrun or underrun situation.
Input 125-MHz clock for receiver detect circuitry in
PCI Express (PIPE) mode.
Scope
Channel
Channel
Channel
Channel
Channel
Channel
CMU PMA
gxb_powerdown pll_locked pll_inclk
Calibration Block
cal_blk_clk
Input Transceiver block reset and power down. This resets and powers down all circuits in the transceiver block. This does not affect the
REFCLK buffers and reference clock lines.
Output PLL locked indicator for the transmitter PLLs.
Input Reference clocks for the transmitter PLLs.
Transceiver block
Transceiver block
Transceiver block
Device Input Calibration clock for the transceiver termination blocks. This clock supports frequencies from 10 MHz to 125 MHz.
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May 2008
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Arria GX Device Handbook, Volume 1
Arria GX Transceiver Architecture
Table 1–1. Arria GX ALT2GXB Ports (Part 6 of 6)
Port Name
cal_blk_powerdown
(active low)
Input/
Output
Input
Description
Power-down signal for the calibration block.
Assertion of this signal may interrupt data transmission and reception. Use this signal to re-calibrate the termination resistors if temperature and/or voltage changes warrant it.
Scope
Device
External Signals
tx_dataout rx_datain
gxb_enable
Output Transmitter serial output port.
Input Receiver serial input port.
Output Reference resistor port. This port is always used and must be tied to a 2K-
Ω resistor to ground. This port is highly sensitive to noise.
There must be no noise coupled to this port.
Input Dedicated reference clock inputs (two per transceiver block) for the transceiver. The buffer structure is similar to the receiver buffer, but the termination is not calibrated.
Input Dedicated transceiver block enable pin. If instantiated, this port must be tied to the pll_ena
input pin. A high level on this signal enables the transceiver block; a low level disables it.
(1) These are dedicated pins for the transceiver and do not appear in the MegaWizard Plug-In Manager.
Channel
Channel
Device
Transceiver block
Transceiver block
Transmitter
Channel
Architecture
This section provides a brief description about sub-blocks within the transmitter channel (shown in
Figure 1–2 ). The sub-blocks are described
in order from the PLD-transmitter parallel interface to the serial transmitter buffer.
Figure 1–2. Arria GX Transmitter Channel Block Diagram
Transmitter PCS
PLD
Logic
Array
PIPE
Interface
TX Phase
Compensation
FIFO
Byte
Serializer
8B/10B
Encoder
Transmitter PMA
Serializer
CMU
Reference
Clock
1–8
Arria GX Device Handbook, Volume 1 May 2008
Transmitter Channel Architecture
Clock Multiplier Unit
Each transceiver block has a clock multiplier unit (CMU) that takes in a reference clock and synthesizes two clocks: a high-speed serial clock to serialize the data and a low-speed parallel clock used to clock the transmitter digital logic (PCS) and the PLD-transceiver interface.
The CMU is further divided into three sub-blocks
■
■
■
Transmitter PLL
Central clock divider block
Local clock divider block
Each transceiver block has one transmitter PLL, one central clock divider and four local clock dividers. One local clock divider is located in each transmitter channel of the transceiver block.
shows a block diagram of the CMU block within each transceiver block.
Figure 1–3. Clock Multiplier Unit Block Diagram
CMU Block
Transmitter Channels [3:2]
Transmitter High-Speed Serial and Low-Speed Parallel Clocks
TX Clock
Gen Block
Reference clock from REFCLKs,
Global Clock (1)
Inter-Transceiver
Lines
Transmitter
PLL
Central Clock
Divider
Block
Transmitter High-Speed Serial and Low-Speed Parallel Clocks
Transmitter Channels[1:0]
:
(1) The global clock line must be driven from an input pin only.
TX Clock
Gen Block
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Arria GX Transceiver Architecture
Transmitter PLL
The transmitter PLL multiplies the input reference clock to generate the high-speed serial clock required to support the intended protocol. It synthesizes a half-rate high-speed serial clock that runs at half the frequency of the serial data rate for which it is configured; for example, the transmitter PLL runs at 625 MHz when configured in 1.25-Gbps GIGE functional mode.
The transmitter PLL output feeds the central clock divider block and the local clock divider blocks. These clock divider blocks divide the high-speed serial clock to generate the low-speed parallel clock for the transceiver PCS logic and the PLD-transceiver interface clock. Depending on the functional mode for which the transceiver block is configured, either the central clock divider block or the local clock divider block is used to generate the low-speed parallel clock.
shows a block diagram of the transmitter PLL.
Figure 1–4. Transmitter PLL
Transmitter PLL
/M (1)
To
Inter-Transceiver Block Lines
Dedicated
REFCLK0
/2
Dedicated
REFCLK1
/2
Inter-Transceiver Block Lines [2:0]
Global Clock (2)
INCLK up
Phase
Frequency
Detector down
Charge
Pump + Loop
Filter
Voltage
Controlled
Oscillator
/L (1)
High Speed
Serial Clock
Notes to
(1) You only need to select the protocol and the available input reference clock frequency in the Quartus II MegaWizard
Plug-In Manager. Based on your selections, the MegaWizard Plug-In Manager automatically selects the necessary
/M and /L dividers (clock multiplication factors).
(2) The global clock line must be driven from an input pin only.
The reference clock input to the transmitter PLL can be derived from:
■
■
■
One of the two available dedicated reference clock input pins
(REFCLK0 or REFCLK1) of the associated transceiver block
PLD global clock network (must be driven directly from an input clock pin and cannot be driven by user logic or enhanced PLL)
Inter-transceiver block lines driven by reference clock input pins of other transceiver blocks
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Arria GX Device Handbook, Volume 1 May 2008
Altera Corporation
May 2008
Transmitter Channel Architecture
1
Altera recommends using the dedicated reference clock input pins (REFCLK0 or REFCLK1) to provide the reference clock for the transmitter PLL.
Transmitter PLL Bandwidth Setting
The Arria GX transmitter PLLs in the transceiver offer a programmable bandwidth setting. The bandwidth of a PLL is the measure of its ability to track the input clock and jitter. It is determined by the -3dB frequency of the closed-loop gain of the PLL.
There are three bandwidth settings: high, medium, and low. The high bandwidth setting filters out internal noise from the V
CO
because it tracks the input clock above the frequency of the internal V
CO
noise. With the low bandwidth setting, if the noise on the input reference clock is greater than the internal noise of the V
CO
, the PLL filters out the noise above the
-3dB frequency of the closed-loop gain of the PLL. The medium bandwidth setting is a compromise between the high and low settings.
The -3dB frequencies for these settings can vary because of the non-linear nature and frequency dependencies of the circuit.
■
■
Dedicated Reference Clock Input Pins
Each transceiver block has two dedicated reference clock input pins
(REFCLK0 and REFCLK1). The clock route from REFCLK0 and REFCLK1 pins in each transceiver block has an optional pre-divider that divides the reference clock by two before feeding it to the transmitter PLL (shown in
). The refclk pre-divider is required if one of the following conditions is satisfied:
If the input clock frequency is greater than 325 MHz.
For functional modes with a data rate less than 3.125 Gbps (the data rate is specified in the what is the data rate? option in the General tab of the ALT2GXB MegaWizard):
●
●
If the input clock frequency is greater than or equal to 100 MHz
AND
If the ratio of data rate to input clock frequency is 4, 5, or 25
Reference Clock From PLD Global Clock Network
You can drive the reference clock to the transmitter PLL from a PLD global clock network. If you choose this option, you must drive the global
PLD reference clock line from a non-REFCLK FPGA input pin. You cannot use a clock generated by PLD logic or an enhanced PLL to drive the reference clock input to the transmitter PLL.
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Arria GX Device Handbook, Volume 1
Arria GX Transceiver Architecture
1
The Quartus II software requires the following setting for the non-REFCLK FPGA input pin used to drive the reference clock input:
Assignment name: Stratix II GX/Arria GX REFCLK coupling and
termination setting
Value: Use as regular IO.
Inter-Transceiver Block Line Routing
The inter-transceiver block lines allow the dedicated reference clock input pins of one transceiver block to drive the transmitter and receiver PLL of other transceiver blocks. There are a maximum of three inter-transceiver block routing lines available in the Arria GX device family. Each transceiver block can drive one inter-transceiver block line from either one of its associated reference clock pins. The inter-transceiver block lines can drive any or all of the transmitter and receiver PLLs in the device. The inter-transceiver block lines offer flexibility when multiple channels in separate transceiver blocks share a common reference clock frequency.
The inter-transceiver block lines also drive the reference clock from the
REFCLK
pins into the PLD fabric, which reduces the need to drive multiple clocks of the same frequency into the device. If a divide-by-two reference clock pre-divider is used, the inter-transceiver block line driven by the corresponding REFCLK pin cannot be used to clock PLD logic.
The Quartus II software automatically uses the appropriate inter-transceiver line if the transceiver block is being clocked by the dedicated reference clock (REFCLK) pin of another transceiver block.
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Arria GX Device Handbook, Volume 1 May 2008
Transmitter Channel Architecture
shows the inter-transceiver block line interface to the transceivers in the gigabit transceiver blocks and to the PLD.
Figure 1–5. Inter-Transceiver Block Line Routing
Inter-Transceiver Block Line[2]
Transceiver Block 2
Inter-Transceiver Block Line[1]
Transceiver Block 1
Transceiver Block 0
Inter-Transceiver Block Line[0]
Inter-Transceiver Block Lines[2:0]
Dedicated
REFCLK0
Dedicated
REFCLK1
Global Clock
(1)
/2
/2
:
(1) The global clock line must be driven from an input pin only.
Transmitter
PLL
1
Depending on the functional mode, the Quartus II software automatically selects the appropriate transmitter PLL bandwidth.
Central Clock Divider Block
The central clock divider block is located in the central block of the transceiver block (refer to
Figure 1–6 ). This block provides the high-speed
clock for the serializer and the low-speed clock for the transceiver’s PCS logic within the transceiver block in a four-lane mode.
shows the central clock divider block. The /4 and /5 block generates the slow-speed clock based on the serialization factor. The high-speed clock goes directly into each channel’s serializer.
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May 2008
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Arria GX Device Handbook, Volume 1
Arria GX Transceiver Architecture
Figure 1–6. Central Clock Divider Block
High-Speed
Serial Clock from
Transmitter PLL
/4 or /5
High-Speed Serial Clock (1)
Low-Speed Parallel Clock
Notes to
(1) This feeds the PCS logic.
The central clock divider block feeds all the channels in the transceiver block when in PIPE ×4 mode. This ensures that the serializer in each channel outputs the same bit number at the same time and minimizes the channel-to-channel skew.
Transmitter Local Clock Divider Block
The Tx local clock divider blocks are located in each transmitter channel of the transceiver block. The purpose of this block is to provide the high-speed clock for the serializer and the low-speed clock for the transmitter data path and the PLD for all the transmitters within the transceiver block. This allows for each of the transmitter channels to run at different rates. The /n divider offers /1, /2, and /4 factors to provide capability to reduce base frequency of the driving PLL to half or a quarter rate. This allows each transmitter channel to run at /1, /2, or /4 of the original data rate.
shows the transmitter local clock divider block.
Figure 1–7. Transmitter Local Clock Divider Block
High-Speed Clock
From Transmitter PLL0
High-Speed Clock
From Transmitter PLL1
÷ n
÷
1, 2, or 4
÷
4, 5
High-Speed
Clock to Transmitter
Slow-Speed
Clock to Transmitter
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May 2008
Transmitter Channel Architecture
Each transmitter local clock divider block is operated independently so there is no guarantee that each channel sends out the same bit at the same time.
■
■
Clock Synthesis
Each PLL in a transceiver block receives a reference clock and generates a high-speed clock that is forwarded to the clock generator blocks. There are two types of clock generators:
Transmitter local clock divider block
Central clock divider block
The transmitter local clock divider block resides in the transmit channel and synthesizes the high-speed serial clock (used by the serializer) and slow-speed clock (used by the transmitter’s PCS logic). The central clock divider block resides in the transceiver block outside the transmit or receive channels. This block synthesizes the high-speed serial clock (used by the serializer) and slow-speed clock (used by the transceiver block PCS logic—transmitter and receiver (if the rate matcher is used)). The PLD clock is also supplied by the central clock divider block and goes through the divide-by-two block (located in the central block of the transceiver block) if the byte serializer/deserializer is used.
The PLLs in the transceiver have half rate voltage-controlled oscillators
(VCOs) that run at half the rate of the data stream. When in the individual channel mode, the slow-speed clocks for the transmitter logic and the serializer need only be a /4, or a /5 divider to support a ×8 and ×10
serialization factor. Table 1–2
shows the divider settings for achieving the available serialization factor.
Table 1–2. Serialization Factor and Divider Settings
Serialization Factor
×8
×10
Divider Setting
/4
/5
In the four-lane mode, the central clock divider block supplies all the necessary clocks for the entire transceiver block.
The reference clock ranges from 50 MHz to 622.08 MHz. The phase frequency detector (PFD) has a minimum frequency limit of 50 MHz and a maximum frequency limit of 325 MHz.
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■
■
The refclk pre-divider (/2 ) is available if you use the dedicated refclk
pins for the input reference clock. The refclk pre-divider is required if one of the following conditions is satisfied:
If the input clock frequency is greater than 325 MHz.
For functional modes with a data rate less than 3.125 Gbps (the data rate is specified in the what is the data rate? option in the General tab of the ALT2GXB MegaWizard):
●
If the input clock frequency is greater than or equal to 100 MHz
●
AND
If the ratio of data rate to input clock frequency is 4, 5, or 25
Transceiver Clock Distribution
This section describes single lane and four-lane configurations for the high speed and low speed transceiver clocks. All protocol support falls in the single lane configuration except for the four-lane PIPE mode and
XAUI. The four-lane PIPE mode uses the four-lane configuration.
Single Lane
In a single lane configuration, the PLLs in the central block supply the high speed clock. Then the clock generation blocks in each transmitter channel divides down the high speed clock to the frequency needed to support its particular data rate. In this configuration, two separate clocks can be supplied through the central block to provide support for two separate base frequencies. The transmitter clock generation blocks can divide those down to create additional frequencies for specific data rate requirements. Each of the four transmitter channels can operate at a different data rate with the use of the individual transmitter local clock dividers and both Transmitter PLL0 and Transmitter PLL1.
1
If you instantiate four channels and are not in PIPE ×4, XAUI, or
Basic single-width mode with ×4 clocking, the Quartus II software automatically chooses the single lane configuration.
shows clock distribution for individual channel configuration.
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Transmitter Channel Architecture
Figure 1–8. Clock Distribution for Individual Channel Configuration
TX Channel 3
TX Channel 2
TX Local Clk
Div Block refclk 0 refclk 1
TXPLL 0
TXPLL 1
TXPLL Block
TX Channel 1
TX Channel 0
High Speed TXPLL 0 Clock
High Speed TXPLL 1 Clock
Central Block
TX Local Clk
Div Block
Four-Lane Mode
In a four-lane configuration (shown in
), the central block generates the parallel and serial clocks that feed the transmitter channels within the transceiver. All channels in a transceiver must operate at the same data rate. This configuration is only supported in PIPE ×4, XAUI and Basic mode with ×4 clocking.
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May 2008
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Arria GX Transceiver Architecture
Figure 1–9. Clock Distribution for a Four-Lane Configuration
Transmitter Channel 3
Transmitter Channel 2
Reference clocks (refclks,
Global Clock (1),
IQ Lines)
Transmitter PLL0
Transmitter PLL1
Transmitter PLL Block
Central
Clock Divider
Block
÷2
Central Block coreclk_out
To PLD
Transmitter Channel 1
Transmitter Channel 0
:
(1) The global clock line must be driven by an input pin.
Figure 1–10 shows how single transceiver block devices EP1AGX20CF,
EP1AGX35CF, EP1AGX50CF and EP1AGX60CF devices are configured for PCI-E ×4 mode. When ArriaGX devices are used in ×4 bonded mode for PCI-E, physical Lane 0 of the transmitter should be connected to physical Lane 0 of the receiver and vice versa.
Figure 1–10. Two Transceiver Block Device with One ×4 PCI-E Link
EP1AGX20C
EP1AGX35C
EP1AGX50C
EP1AGX60C
Bank 14 (Slave)
GXB_TX/RX1
GXB_TX/RX0
GXB_TX/RX2
GXB_TX/RX3
PCIe Lane 1
PCIe Lane 0
PCIe Lane 2
PCIe Lane 3
The two transceiver block devices EP1AGX35DF, EP1AGX50DF, and
EP1AGX60DF support only two PCI-E ×4 links. Fig Figure 1–11
shows the
PCI-E ×4 configuration.
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Transmitter Channel Architecture
Figure 1–11. Two Transceiver Block Device with Two ×4 PCI-E Links
EP1AGX35DF
EP1AGX50DF
EP1AGX60DF
Bank 13
GXB_TX/RX1
GXB_TX/RX0
GXB_TX/RX2
GXB_TX/RX3
Bank 14
GXB_TX/RX5
GXB_TX/RX4
GXB_TX/RX6
GXB_TX/RX7
PCIe Lane 5
PCIe Lane 4
PCIe Lane 6
PCIe Lane 7
PCIe Lane 1
PCIe Lane 0
PCIe Lane 2
PCIe Lane 3
The three transceiver block devices EP1AGX60EF and EP1AGX90EF
support up to three PCI-E ×4 links. Figure 1–12 shows the PCI-E ×4
configuration.
Figure 1–12. Three Transceiver Block Device with Three ×4 PCI-E Links
EP1AGX60EF
EP1AGX90EF
Bank 13
GXB_TX/RX1
GXB_TX/RX0
GXB_TX/RX2
GXB_TX/RX3
Bank 14
GXB_TX/RX5
GXB_TX/RX4
GXB_TX/RX6
GXB_TX/RX7
PCIe Lane 1
PCIe Lane 0
PCIe Lane 2
PCIe Lane 3
PCIe Lane 1
PCIe Lane 0
PCIe Lane 2
PCIe Lane 3
Bank 15
GXB_TX/RX9
GXB_TX/RX8
GXB_TX/RX10
GXB_TX/RX11
PCIe Lane 1
PCIe Lane 0
PCIe Lane 2
PCIe Lane 3
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May 2008
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Arria GX Transceiver Architecture
Channel Clock Distribution
This section describes clocking within each channel for:
■
■
Individual channels in Basic (without ×4 clocking enabled), PIPE ×1,
GIGE, Serial RapidIO, and SDI modes
Bonded channels in XAUI, PIPE ×4, and Basic (with ×4 clocking enabled) modes
Individual Channels Clocking
In individual channel modes, the transmitter logic is clocked by the slow speed clock from the clock divider block. The transmitter phase compensation FIFO buffer and the PIPE interface (in PIPE mode) are clocked by the tx_clkout clock of the channel that is fed back to the transmitter channel from the PLD logic.
routing for the transmitter channel.
Figure 1–13. Individual Channel Transmitter Logic Clocking
PLD
Logic
Array
XCVR
PIPE
Interface
Transmitter
Digital
Logic
TX
Phase
Compensation
FIFO
Byte
Serializer
÷1, 2
8B/10B
Encoder tx_clkout
Transmitter Analog Circuits
Serializer
Central Block Reference
Clocks
The receiver logic clocking has two clocking methods: one when rate matching is used and the other when rate matching is not used.
If rate matching is used (PIPE, GIGE, and Basic modes), the receiver logic from the serializer to the rate matcher is clocked by the recovered clock from its associated channel. The rest of the logic is clocked by the slow clock from the clock divider block of its associated channel. The read side of the phase compensation FIFO buffer and the PIPE interface (for PIPE mode) is clocked by the tx_clkout fed back through the PLD logic.
Figure 1–14 shows the clocking of the receiver logic with the rate matcher.
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Transmitter Channel Architecture
Figure 1–14. Individual Channel Receiver Logic Clocking with Rate Matching
PLD XCVR Receiver Digital Logic
PIPE
Interface
RX Phase
Compensation
FIFO
Byte
Deserializer
8B/10B
Decoder
Receiver Analog Circuits
Rate
Match
FIFO
Word
Aligner
Deserializer
Clock
Recovery
Unit
÷1, 2
Central
Block
Reference
Clocks tx_clkout
If rate matching is not used (Basic, SDI, and Serial RapidIO modes), then the receiver logic is clocked by the recovered clock of its associated channel (
). The receiver phase compensation FIFO buffer's read port is clocked by the recovered clock that is fed back from the PLD logic array as rx_clkout.
Figure 1–15. Individual Channel Receiver Logic Clocking Without Rate Matching
PLD XCVR Receiver Digital Logic
Receiver Analog Circuits
PIPE
RX Phase
Compensation
FIFO
÷1, 2
Byte
Deserializer
8B/10B
Decoder
Word
Aligner
Deserializer
Clock
Recovery
Unit rx_clkout
Transmitter Clocking (Bonded Channels)
The clocking in bonded channel modes ( Figure 1–16 ) is different from
that of the individual channel. All the transmitters are synchronized to the same transmitter PLL and clock divider from the central block. In ×4 bonded channel modes, the central clock divider of the transceiver block clocks all four channels.
The transmitter logic up to the read port of the transmitter phase compensation FIFO buffer is clocked by the slow speed clock from the central block. The PIPE interface and the write port of the transmitter phase compensation FIFO buffer is clocked by the coreclkout signal routed from the PLD.
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May 2008
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Figure 1–16. Transmitter Channel Clocking in Transceiver Mode
PLD
Logic
Array
XCVR
PIPE
Interface
Transmitter
Digital
Logic
TX
Phase
Compensation
FIFO
Byte
Serializer
÷1, 2
8B/10B
Encoder coreclkout
Transmitter Analog Circuits
Serializer
Central Block Reference
Clocks
For the receiver logic, in XAUI mode (
), the local recovered clock feeds the logic up to the write clock of the deskew FIFO buffer. The recovered clock from Channel 0 feeds the read clock of the deskew FIFO buffer and the write port of the rate matcher. The slow clock from the central block feeds the rest of the logic up to the write port of the phase compensation FIFO buffer. The coreclkout signal routed through the
PLD from the central block feeds the read side of the phase compensation
FIFO buffer.
Figure 1–17. Receiver Channel Clocking in XAUI Mode
PLD
XCVR
Receiver Digital Logic Receiver Analog Circuits
RX Phase
Compensation
FIFO
Byte
Deserializer
8B/10B
Decoder
Rate
Match
FIFO
Word
Aligner
Deserializer
Clock
Recovery
Unit
÷1, 2 coreclkout
Central Block Reference
Clocks
In the PIPE ×4 mode ( Figure 1–18
), the local recovered clock feeds the logic up to the write port of the rate matcher FIFO buffer. The slow clock from the central block feeds the rest of the logic up to the write port of the phase compensation FIFO buffer. The coreclkout signal routed through the PLD from the central block feeds the read side of the phase compensation FIFO buffer.
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Transmitter Channel Architecture
Figure 1–18. Receiver Channel PIPE 4 Mode
PLD
XCVR
Receiver Digital Logic
RX Phase
Compensation
FIFO
Byte
Deserializer
÷1, 2 coreclkout
8B/10B
Decoder
Receiver Analog Circuits
Rate
Match
FIFO
Word
Aligner
Deserializer
Clock
Recovery
Unit
Central Block Reference
Clocks
Altera Corporation
May 2008
Transmitter Phase Compensation FIFO
A transmitter phase compensation FIFO (
Figure 1–19 ) is located at each
transmitter channel's logic array interface. It compensates for the phase difference between the transmitter PCS clock and the local PLD clock.
In individual channel mode (for example, GIGE and Serial RapidIO), the low-speed parallel clock (or its divide-by-two version if the byte serializer is used) from the local clock divider block of each channel clocks the read port of its transmitter phase compensation FIFO buffer. This clock is also forwarded to the logic array on tx_clkout port of its associated channel. If the tx_coreclk port is not instantiated, the clock signal on the tx_clkout port of Channel 0 is automatically fed back to clock the write port of the transmitter phase compensation FIFOs in all channels within the transceiver block. If the tx_coreclk port is instantiated, the clock signal driven on the tx_coreclk port clocks the write port of the transmitter phase compensation FIFO of its associated channel. You must ensure that the clock on the tx_coreclk port is frequency locked to the read clock of the transmitter phase compensation FIFO. For more information about using the PLD core clock (tx_coreclk), refer to
“PLD-Transceiver Interface Clocking” on page 1–68 .
In bonded channel mode (for example, ×4 PCI Express (PIPE)), the low speed parallel clock from the central clock divider block is divided by two. This divide-by-two clock clocks the read port of the transmitter phase compensation FIFO. This clock is also forwarded to the logic array on the coreclkout port. If the tx_coreclk port is not instantiated, the clock signal on the coreclkout port is automatically fed back to clock the write port of transmitter phase compensation FIFO buffers in all channels within the transceiver block. If the tx_coreclk port is instantiated, the clock signal driven on the tx_coreclk port clocks the write port of the transmitter phase compensation FIFO of its associated channel. You must ensure that the clock on the tx_coreclk port is
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frequency locked to the read clock of the transmitter phase compensation
FIFO. For more information about using the PLD core clock
(tx_coreclk), refer to
“PLD-Transceiver Interface Clocking” on page 1–68
.
Figure 1–19. Transmitter Phase Compensation FIFO
Transmitter Channel datain[]
From PLD or PIPE
Interface tx_coreclk
Transmitter
Phase
Compensation
FIFO wrclk rdclk dataout[]
To Byte Serializer or 8B/10B
Encoder
/2
CMU
Local/Central Clock
Divider Block tx_clkout or coreclkout
Transmitter Phase Compensation FIFO Error Flag
The write port of the transmitter phase compensation FIFO can be clocked by either the CMU output clock or its divide-by-two version
(tx_clkout or coreclkout) or a PLD clock. The read port is always clocked by the CMU output clock or its divide-by-two version. In all configurations, the write clock and the read clock must have 0 parts per million (PPM) difference to avoid overrun/underflow of the phase compensation FIFO.
An optional debug_tx_phase_comp_fifo_error port is available in all modes to indicate transmitter phase compensation FIFO overrun/underflow condition. This feature should be used for debug purposes only if link errors are observed.
Byte Serializer
The byte serializer (
Figure 1–20 ) takes in 16- or 20-bit wide data from the
transmitter phase compensation FIFO buffer and serializes it into 8- or
10-bit wide data at twice the speed. This allows clocking the
PLD-transceiver interface at half the speed as compared to the transmitter
PCS logic. The byte serializer is bypassed in GIGE mode.
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Transmitter Channel Architecture
datain[15:0]
Byte Serializer
From Transmitter
Phase Compensation
FIFO wrclk rdclk
To 8B/10B
Encoder dataout[7:0]
/2
Divide-By-Two Version of Low-Speed
Parallel Clock
Low-Speed Parallel
Clock
:
(1) datain
and dataout may also be 20 bits and 10 bits wide, respectively.
CMU
Local/Central Clock
Divider Block
Figure 1–21. Byte Serializer Operation
datain[15:0]
D1
{8'h00, 8'h01} dataout[7:0]
After serialization, the byte serializer transmits the least significant byte
(LSByte) first and the most significant byte (MSByte) last.
Figure 1–21 shows byte serializer input and output. datain[15:0] is
the input to the byte serializer from the transmitter phase compensation
FIFO and dataout[7:0] is the output of the byte serializer. datain may also be 20 bits wide and dataout may be 10 bits wide depending on implementation.
xxxxxxxxxx xxxxxxxxxx
D2
{8'h02, 8'h03}
D1
LSByte
8'h01
D1
MSByte
8'h00
D2
LSByte
8'h03
D3 xxxx
D
2
MSByte
8'h02
In
Figure 1–21 , the LSByte is transmitted before the MSByte from the
transmitter byte serializer. For input data D1, the output data is D1
LSByte and then D1
MSByte
.
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May 2008
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Arria GX Transceiver Architecture
f
Figure 1–22. 8B/10B Encoder
8B/10B Encoder
The 8B/10B encoder block takes in 8-bit data from the byte serializer or transmitter phase compensation FIFO buffer (if the byte serializer is not used). It generates a 10-bit code group with proper running disparity from the 8-bit character and a 1-bit control identifier (tx_ctrlenable).
The 10-bit code group is fed to the serializer. The 8B/10B encoder conforms to the IEEE 802.3 1998 edition standard.
Figure 1–22 shows the 8B/10B conversion format.
For additional information about 8B/10B encoding rules, refer to the
Specifications and Additional Information
chapter in volume 2 of the
Arria GX Device Handbook.
7 6 5 4 3 2 1 0
H G F E D C B A
Ctrl
8B-10B Conversion j h g f i e d c b a
9 8 7 6 5 4 3 2 1 0
MSB
LSB
The 10-bit encoded data output from the 8B/10B encoder is fed to the serializer that transmits the data from LSB to MSB.
Reset Behavior
The transmitter digital reset (tx_digitalreset) signal resets the
8B/10B encoder. During reset, the running disparity and data registers are cleared and the 8B/10B encoder outputs a K28.5 pattern from the
RD- column continuously. Once out of reset, the 8B/10B encoder starts with a negative disparity (RD-) and transmits three K28.5 code groups for synchronizing before it starts encoding the input data or control character.
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Transmitter Channel Architecture
Figure 1–23 shows the 8B/10B encoder's reset behavior. When in reset
(tx_digitalreset is high), a K28.5- (K28.5 10-bit code group from the
RD- column) is sent continuously until tx_digitalreset is low. The transmitter channel pipelining causes some "don't cares (10'hxxx)" until the first of three K28.5 is sent. User data follows the third K28.5.
Figure 1–23. 8B/10B Encoder Output During Reset
clock tx_digitalreset dataout[9:0]
K28.5K28.5K28.5xxx ...
xxx K28.5K28.5+ K28.5Dx.y+
Control Code Group Encoding
A control identifier (tx_ctrlenable) input signal specifies whether the
8-bit input character is to be encoded as a control word (Kx.y) or data word (Dx.y). When tx_ctrlenable is low, the input character is encoded as data (Dx.y). When tx_ctrlenable is high, the input character is encoded as a control word (Kx.y). The waveform in
Figure 1–24 shows that the second 0xBC character is encoded as a control
word (K28.5). The rest of the characters are encoded as data (Dx.y).
Figure 1–24. Control Code Group Identification
clock datain[7..0] tx_ctrlenable
Code Group
83 78 BC BC 0F 00 BF 3C
D3.4
D24.3
D28.5
K28.5
D15.0
D0.0
D31.5
D28.1
1
The 8B/10B encoder does not check whether the code group word entered is one of the 12 valid codes. If you enter an invalid control code, the resultant 10-bit code group may be encoded as an invalid code (does not map to a valid Dx.y or Kx.y code group), or unintended valid Dx.y code group, depending on the value entered.
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Transmitter Force Disparity
Upon power on or reset, the 8B/10B encoder has a negative disparity and chooses the 10-bit code from the RD- column. The Transmitter Force
Disparity feature allows altering the running disparity via the tx_forcedisp
and tx_dispval ports.
Two optional ports, tx_forcedisp and tx_dispval, are available in
8B/10B enabled Basic mode. A high value on the tx_forcedisp bit will change the disparity value of the data to the value indicated by the associated tx_dispval bit. If the tx_forcedisp bit is low, then tx_dispval
is ignored and the current running disparity is not altered.
Forcing disparity can either maintain the current running disparity calculations if the forced disparity value (on the tx_dispval bit) happens to match the current running disparity, or flip the current running disparity calculations if it does not. If the forced disparity flips the current running disparity, the downstream 8B/10B decoder may detect a disparity error that should be tolerated by the downstream device.
Figure 1–25 shows the current running disparity being altered in Basic
mode by forcing a positive disparity on a negative disparity K28.5. In this example, a series of K28.5 code groups are continuously being sent. The stream alternates between a positive ending running disparity (RD+)
K28.5 and a negative ending running disparity (RD-) K28.5 as governed by the 8B/10B encoder to maintain a neutral overall disparity. The current running disparity at time n+3 indicates that the K28.5 in time n+4 should be encoded with a negative disparity. Since the tx_forcedisp is high at time n+4, and tx_dispval is also high, the K28.5 at time n+4 is encoded as a positive disparity code group. As the tx_forcedisp is low at n+5, the K28.5 will take the current running disparity of n+4 and encode the
K28.5 in time n+5 with a negative disparity. If the tx_forcedisp were driven high at time n+5, that K28.5 would also be encoded with positive disparity.
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Transmitter Channel Architecture
Figure 1–25. Transmitter Force Disparity Feature in Basic Mode
n n+1 n+2 n+3 n+4 n+5 n+6 n+7 clock tx_in[7:0] tx_ctrlenable tx_forcedisp tx_dispval
Current Disparity tx_out
BC BC BC BC BC BC BC BC
RD-
17C
RD+
283
RD-
17C
RD+
283
RD+
283
RD-
17C
RD+
283
RD-
17C
Transmitter Polarity Inversion
The positive and negative signals of a serial differential link might accidentally be swapped during board layout. Solutions such as a board re-spin or major updates to the PLD logic can prove expensive. The transmitter polarity inversion feature is provided to correct this situation.
An optional tx_invpolarity port is available in all modes to dynamically enable the transmitter polarity inversion feature. A high on the tx_invpolarity port inverts the polarity of every bit of the 8- or
10-bit input data word to the serializer in the transmitter data path. Since inverting the polarity of each bit has the same effect as swapping the positive and negative signals of the differential link, correct data is seen by the receiver. The tx_invpolarity is a dynamic signal and may cause initial disparity errors at the receiver of an 8B/10B encoded link.
The downstream system must be able to tolerate these disparity errors.
Figure 1–26 illustrates the transmitter polarity inversion feature in a
10-bit wide data path configuration.
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Figure 1–26. Transmitter Polarity Inversion
0
1
0
1
0
0
1
1
1
1 tx_invpolarity = HIGH
0
0
0
0
1
1
1
0
1
0
To Serializer
Output from transmitter PCS
Input to transmitter PMA
Transmitter Bit Reversal
By default, the Arria GX transmitted bit order is LSBit to MSBit. In Basic mode, the least significant bit of the 8/10-bit data word is transmitted first and the most significant bit is transmitted last. The Transmitter Bit
Reversal feature allows reversing the transmitted bit order as MSBit to
LSBit.
If the Transmitter Bit Reversal feature is enabled in Basic mode, the 8-bit
D[7:0]
or 10-bit D[9:0] data at the input of the serializer gets rewired to D[0:7] or D[0:9], respectively. Flipping the parallel data using this feature and transmitting LSBit to MSBit effectively provides MSBit to
LSBit transmission.
Figure 1–27 illustrates the transmitter bit reversal feature in a Basic mode
10-bit wide data path configuration.
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Transmitter Channel Architecture
Figure 1–27. Transmitter Bit Reversal in Basic Mode
D[9]
D[8]
D[7]
D[6]
D[5]
TX Bit Reversal = Enabled
D[4]
D[3]
D[2]
D[1]
D[0]
Output from transmitter PCS
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
To Serializer
Input to transmitter PMA
Serializer
The serializer block clocks in 8- or 10-bit data using the low-speed parallel clock and clocks out serial data using the high-speed serial clock from the central or local clock divider blocks. The serializer natively feeds the data
LSB to MSB to the transmitter output buffer.
Figure 1–28 shows the serializer block diagram.
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Figure 1–28. Serializer
10
From 8B/10B
Encoder
D 9
D 8
D 7
D 6
D
5
D 4
D 3
D 2
D 1
D 0
D 9
D 8
D 7
D 6
D 5
D 4
D 3
D 2
D 1
D 0
To Transmitter
Output Buffer
CMU
Central/
Local Clock
Divider
Low-Speed Parallel Clock
High-Speed Serial Clock
Figure 1–29 shows the serial bit order at the serializer output. In this
example, 10'b17C data is serialized and transmitted from LSB to MSB.
Figure 1–29. Serializer Bit Order
Low Speed Parallel Clock
High Speed Serial Clock datain[9:0]
0101111100
1010000011 dataout[0]
0 0 1 1 1 1 1 0 1 0 1 1 0 0 0 0 0 1 0 1
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Transmitter Buffer
The Arria GX transmitter buffers support 1.2-V and 1.5-V pseudo current mode logic (PCML) up to 3.125 Gbps and can drive 40 inches of FR4 trace
across two connectors. The transmitter buffer (refer to Figure 1–30
) has additional circuitry to improve signal integrity-programmable output voltage, programmable pre-emphasis circuit, and internal termination circuitry-and the capability to detect the presence of a downstream receiver. The Arria GX transmitter buffer supports a common mode of
600 or 700 mV.
Figure 1–30. Transmitter Buffer
Programmable
Pre-emphasis and VOD
50
Ω
+VTT-
50
Ω
Transmitter
Output Pins
RX Detect
Programmable Voltage Output Differential
Arria GX devices allow you to customize the differential output voltage
(VOD) to handle different trace lengths, various backplanes, and receiver
requirements (refer to Figure 1–31
). You select the VOD from a range between 400 and 1200 mV, as shown in
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Figure 1–31. VOD (Differential) Signal Level
Single-Ended Waveform
V
OD
(Differential)
= V
A
Differential Waveform
+V
OD
-
OD
V
OD
V
A
V
B
+600
0-V Differential
-V
OD
-600
shows the VOD setting per supply voltage for an on-chip termination value of 100
Ω .
Table 1–3. VOD Differential Peak to Peak
1.2-V V
CC
100-
Ω (mV)
—
480
640
800
960
1.5-V V
CC
100-
Ω (mV)
400
600
800
1000
1200
You set the VOD values in the MegaWizard Plug-In Manager.
The transmitter buffer is powered by either a 1.2-V or a 1.5-V power supply. You choose the transmitter buffer power (V
CCH
) of 1.2 V or 1.5 V through the ALT2GXB MegaWizard Plug-In Manager (the What is the
transmit buffer power (V
CCH
)?
option). The transmitter buffer power supply in Arria GX devices is transceiver-based. The 1.2 V power supply supports the 1.2-V PCML standard.
You specify the static VOD settings through the ALT2GXB MegaWizard
Plug-In Manager.
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Transmitter Channel Architecture
Programmable Pre-Emphasis
The programmable pre-emphasis module in each transmit buffer boosts the high frequencies in the transmit data signal, which may be attenuated in the transmission media. Using pre-emphasis can maximize the data eye opening at the far-end receiver.
The transmission line’s transfer function can be represented in the frequency domain as a low pass filter. Any frequency components below the -3dB frequency pass through with minimal losses. Frequency components greater than the -3dB frequency are attenuated. This variation in frequency response yields data dependent jitter and other ISI effects. By applying pre-emphasis, the high frequency components are boosted, that is, pre-emphasized. Pre-emphasis equalizes the frequency response at the receiver so the difference between the low frequency and high frequency components are reduced, which minimizes the ISI effects from the transmission medium.
The pre-emphasis requirements increase as data rates through legacy backplanes increase. The Arria GX transmitter buffer employs a pre-emphasis circuit with up to 184% of pre-emphasis to correct for losses in the transmission medium.
You set pre-emphasis settings through a slider menu in the ALT2GXB
MegaWizard Plug-In Manager. Arria GX devices support the first five settings for first post-tap pre-emphasis. Specify the first post-tap pre-emphasis settings through the MegaWizard Plug-In Manager.
Transmitter Termination
The Arria GX transmitter buffer includes on-chip differential termination of 100
Ω . The resistance is adjusted by the on-chip calibration circuit in
the calibration block (refer to “Calibration Blocks” on page 1–82
for more information), which compensates for temperature, voltage, and process changes. You can disable the on-chip termination to use external termination. If you select external termination, the transmitter common mode is also tri-stated.
You set the transmitter termination setting through a pull-down menu in the ALT2GXB MegaWizard Plug-In Manager.
PCI Express Receiver Detect
The Arria GX transmitter buffer has a built-in receiver detection circuit for use in the PIPE mode. This circuit detects if there is a receiver downstream by sending out a pulse on the common mode of the
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transmitter and monitoring the reflection. This mode requires the transmitter buffer to be tri-stated (in Electrical Idle mode) and the use of on-chip termination and a 125 MHz fixedclk signal.
This feature is only available in the PIPE mode. You enable it by setting the tx_forceelecidle and tx_detectrxloopback ports to 1'b1.
You must set the powerdn port to 2'b10 to place the transmitter in the
PCI-Express P1 power down state. The results of the receiver detect are encoded on the pipestatus port.
PCI Express Electrical Idle
The Arria GX transmitter buffer supports PCI Express Electrical Idle (or individual transmitter tri-state). This feature is only active in the PIPE mode. The tx_forceelecidle port puts the transmitter buffer in
Electrical Idle mode. This port is available in all PCI Express power-down
modes and has a specific use in each mode. Table 1–4 shows the usage in
each power mode.
Table 1–4. Power Mode Usage
Power Mode
P0
P1
P2
Usage
tx_forceelecidle
must be asserted. If this signal is deasserted, it indicates that there is valid data.
tx_forceelecidle
must be asserted.
When deasserted, the beacon signal must be transmitted.
Receiver
Channel
Architecture
This section provides a brief description about sub-blocks within the
receiver channel ( Figure 1–32
). The sub-blocks are described in order from the serial receiver input buffer to the receiver phase compensation
FIFO buffer at the transceiver-PLD interface.
Figure 1–32. Receiver Channel Block Diagram
Receiver Digital Logic
RX Phase
Compensation
FIFO
Byte
Deserializer
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
Receiver Analog Circuits
Deserializer
Clock
Recovery
Unit
Receiver
PLL
Reference
Clock
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Receiver Channel Architecture
Figure 1–33. Receiver Buffer
Receiver
Input Pins
50
Ω
+VTT-
50
Ω
Receiver Buffer
The Arria GX receiver buffers support 1.2-V, 1.5-V, 3.3-V PCML
(pseudo-current mode logic), differential LVPECL and LVDS I/O standards. The receiver buffers support data rates from 600 Mbps to
3.125 Gbps and are capable of compensating up to 40 inches of FR4 trace across two connectors. The receiver buffer (
circuitry to improve signal integrity, including a programmable equalization circuit and internal termination circuitry. Through a signal detect circuit, the receiver buffers can also detect if a signal of predefined amplitude exists at the receiver.
Programmable
Equalizer
To CRU
Signal
Detect
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May 2008
Receiver Termination
The Arria GX receiver buffer has an optional on-chip differential termination of 100
Ω . You can set the receiver termination resistance setting using one of these options:
■
Set receiver termination resistance by: a.
Set the receiver termination resistance option in the
MegaWizard Plug-In Manager if on-chip termination is used.
Arria GX supports 100
Ω termination. If the design requires external receive termination, turn on the Use External Receiver
Termination
option.
b.
You make the differential termination assignment per pin in the
Quartus II software. (On the Assignments menu, point to
Assignment Organizer
, and click Options for Individual
Nodes Only
. Then click Stratix II GX GXB Termination Value.)
■
Verify and set the receiver termination settings before compilation.
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Signal Threshold Detection Circuit
The signal detect feature is supported only in PIPE mode. The signal detect/loss threshold detector senses if the specified voltage level exists at the receiver buffer. This detector has a hysteresis response, that filters out any high frequency ringing caused by inter symbol interference or high frequency losses in the transmission medium. The rx_signaldetect
signal indicates if a signal conforms to the signal detection settings. A high level indicates that the signal conforms to the settings, a low level indicates that the signal does not conform to the settings.
The signal detect levels are to be determined by characterization. The signal detect levels may vary because of changing data patterns.
The signal/detect loss threshold detector also switches the receiver
PLL/CRU from lock-to-reference mode to lock-to-data mode. The lock-to-reference and lock-to-data modes dictate whether the VCO of the clock recovery unit (CRU) is trained by the reference clock or by the data stream.
You can bypass the signal/detect loss threshold detection circuit by choosing the Forced Signal Detect option in the MegaWizard Plug-In
Manager. This is useful in lossy environments where the voltage thresholds might not meet the lowest voltage threshold setting. Forcing this signal high enables the receiver PLL to switch from VCO training based on the reference clock to the incoming data without detecting a valid voltage threshold.
Receiver Common Mode
Arria GX transceivers support the receiver buffer common mode voltages of 0.85 V and 1.2 V. Altera recommends selecting 0.85 V as the receiver buffer common mode voltage.
Programmable Equalization
The Arria GX device offers an equalization circuit in each gigabit transceiver block receiver channel to increase noise margins and help reduce the effects of high frequency losses. The programmable equalizer compensates for the high frequency losses that distort the signal and reduces the noise margin of the transmission medium by equalizing the frequency response. There are five equalizer control settings allowed for an Arria GX device (including a setting with no equalization). In addition to equalization, Arria GX devices offer an equalizer DC gain option.
There are three legal settings for DC gain. You specify the equalizer settings (Equalization Settings and DC Gain) through the MegaWizard
Plug-In Manager.
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Receiver Channel Architecture
The transmission line's transfer function can be represented in the frequency domain as a low pass filter. Any frequency components below the -3dB frequency pass through with minimal losses. Frequency components that are greater than the -3dB frequency are attenuated. This variation in frequency response yields data-dependent jitter and other ISI effects. By applying equalization, the low frequency components are attenuated. This equalizes the frequency response such that the delta between the low frequency and high frequency components is reduced, which in return minimizes the ISI effects from the transmission medium.
Receiver PLL
Each transceiver channel has its own receiver PLL that is fed by an input reference clock. The reference clock frequency depends on the functional mode for which the transceiver channel is configured for. The clock recovery unit (CRU) controls whether the receiver PLL locks to the input reference clock (lock-to-reference mode) or the incoming serial data (lock-
to-data mode). Refer to “Clock Recovery Unit (CRU)” on page 1–41 for
more details on lock-to-reference and lock-to-data modes. The receiver
PLL, in conjunction with the clock recovery unit, generates two clocks: a high speed serial clock that clocks the deserializer and a low-speed parallel clock that clocks the receiver’s digital logic.
1
This section only discusses the receiver PLL operation in
lock-to-reference mode. For lock-to-data mode, refer to “Clock
Recovery Unit (CRU)” on page 1–41 .
Figure 1–34 shows the block diagram of the receiver PLL in
lock-to-reference mode.
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Figure 1–34. Receiver PLL Block Diagram
Dedicated
REFCLK0
/2
Dedicated
REFCLK1
/2
Inter-Transceiver Lines[2:0]
Global Clock (2) rx_locktorefclk rx_locktodata rx_datain rx_cruclk
/M (1)
PFD up dn up dn rx_pll_locked
Charge
Pump +
Loop
Filter
VCO
/L (1)
Clock Recovery Unit (CRU) Control rx_freqlocked
High-speed serial recovered clock
Low-speed parallel recovered clock inactive circuits active circuits
Notes to
(1) You only need to select the protocol and the available input reference clock frequency in the Quartus II MegaWizard
Plug-In Manager. Based on your selections, the MegaWizard Plug-In Manager automatically selects the necessary
/M and /L dividers.
(2) The global clock line must be driven from an input pin only.
The reference clock input to the receiver PLL can be derived from:
■
■
■
One of the two available dedicated reference clock input pins
(REFCLK0 or REFCLK1) of the associated transceiver block
PLD clock network (must be driven directly from an input clock pin and cannot be driven by user logic or enhanced PLL)
Inter-transceiver block lines driven by reference clock input pins of other transceiver blocks
Depending on the functional mode, the Quartus II software automatically selects the appropriate receiver PLL bandwidth.
Clock Synthesis
The maximum input frequency of the receiver PLL's phase frequency detector (PFD) is 325 MHz. To achieve a reference clock frequency above this limitation, the divide by 2 pre-divider on the dedicated local REFCLK path is automatically enabled by the Quartus II software. This divides the reference clock frequency by a factor of 2, and the /M PLL multiplier multiplies this pre-divided clock to yield the configured data rate. For example, in a situation with a data rate of 2500 Mbps and a reference clock of 500 MHz, the reference clock must be assigned to the REFCLK port where the 500 MHz reference clock can be divided by 2, yielding a
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Receiver Channel Architecture
250 MHz clock at the PFD. The VCO runs at half the data rate, so the selected multiplication factor should yield a 1250 MHz high speed clock.
The Quartus II software automatically selects a multiplication factor of ×5 in this case to generate a 1250 MHz clock from the pre-divided 250 MHz clock.
If the /2 pre-divider is used, the reference clock must be fed by a dedicated reference clock input (REFCLK) pin. Otherwise, the Quartus II compiler gives a Fitter error.
The pre-divider and the multiplication factors are automatically set by the
Quartus II software. The MegaWizard Plug-In Manager takes the data rate input and provides a list of the available reference clock frequencies that fall within the supported multiplication factors that you can select.
PPM Frequency Threshold Detector
The PPM frequency threshold detector senses whether the incoming reference clock to the clock recovery unit (CRU) and the PLL VCO of the
CRU are within a prescribed PPM tolerance range. Valid parameters are
62.5, 100, 125, 200, 250, 300, 500, or 1000 PPM. The default parameter, if no assignments are made, is 1000 PPM. The output of the PPM frequency threshold detector is one of the variables that assert the rx_freqlocked signal. Refer to
“Automatic Lock Mode” on page 1–42
for more details regarding the rx_freqlocked signal.
Receiver Bandwidth Type
The Arria GX receiver PLL in the CRU offers a programmable bandwidth setting. The PLL bandwidth is the measure of the PLL’s ability to track the input data and jitter. The bandwidth is determined by the -3dB frequency of the closed-loop gain of the PLL.
A higher bandwidth setting helps reject noise from the VCO and power supplies. A low bandwidth setting filters out more high frequency data input jitter.
Valid receiver bandwidth settings are low, medium, or high. The -3dB frequencies for these settings vary because of the non-linear nature and data dependencies of the circuit. You can vary the bandwidth to adjust and customize the performance on specific systems.
Clock Recovery Unit (CRU)
The CRU (
Figure 1–35 ) in each transceiver channel recovers the clock
from the received serial data stream. You can set the CRU to lock to the received serial data phase and frequency (lock-to-data mode) to eliminate
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any clock-to-data skew or to keep the receiver PLL locked to the reference clock (lock-to-reference mode). The switch between lock-to-data and lock-to-reference modes can be done automatically or manually. The
CRU, in conjunction with the receiver PLL, generates two clocks: a high-speed serial recovered clock that feeds the deserializer and a low-speed parallel recovered clock that feeds the receiver’s digital logic.
Figure 1–35. Clock Recovery Unit
/M
Dedicated
REFCLK0
/2
Dedicated
REFCLK1
/2
Inter-Transceiver Lines[2:0]
Global Clock (2) rx_cruclk
PFD up dn up dn rx_pll_locked
CP+LF
VCO
/L rx_locktorefclk rx_locktodata rx_datain
Clock Recovery Unit (CRU) Control rx_freqlocked
High-Speed Serial Recovered Clock
Low-Speed Parallel Recovered Clock inactive circuits active circuits
Notes to
(1) You only need to select the protocol and the available input reference clock frequency in the Quartus II MegaWizard
Plug-In Manager. Based on your selections, the MegaWizard Plug-In Manager automatically selects the necessary
/M and /L dividers.
(2) The global clock line must be driven from an input pin only.
Automatic Lock Mode
After coming out of reset in automatic lock mode, the CRU initially sets the receiver PLL to lock to the input reference clock (lock-to-reference mode). After the receiver PLL locks to the input reference clock, the CRU automatically sets it to lock to the incoming serial data (lock-to-data mode) when the following two conditions are met:
■
■
The receiver PLL output clock is within the configured PPM frequency threshold setting with respect to its reference clock
(frequency locked)
The reference clock and receiver PLL output clock are phase matched within approximately 0.08 UI (phase locked)
When the receiver PLL and CRU are in lock-to-reference mode, the PPM detector and the phase detector circuits monitor the relationship of the reference clock to the receiver PLL VCO output. If the frequency difference is within the configured PPM setting (as set in the MegaWizard
Plug-In Manager) and the phase difference is within 0.08 UI, the CRU
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switches to lock-to-data mode. The switch from lock-to-reference to lock-to-data mode is indicated by the assertion of the rx_freqlocked signal.
In lock-to-data mode, the receiver PLL uses a phase detector to keep the recovered clock phase-matched to the data. If the PLL does not stay locked to data due to frequency drift or severe amplitude attenuation, the
CRU switches back to lock-to-reference mode to lock the PLL to the reference clock. In automatic lock mode, the following condition forces the CRU to fall out of lock-to-data mode:
The CRU PLL is not within the configured PPM frequency threshold setting with respect to its reference clock.
The switch from lock-to-data to lock-to-reference mode is indicated by the de-assertion of rx_freqlocked signal.
When the CRU is in lock-to-data mode (rx_freqlocked is asserted), it tries to phase-match the PLL with the incoming data. As a result, the phase of the PLL output clock may differ from the reference clock due to which rx_pll_locked signal might get de-asserted. You should ignore the rx_pll_locked signal when the rx_freqlocked signal is asserted high.
Manual Lock Mode
Two optional input pins (rx_locktorefclk and rx_locktodata) allow you to control whether the CRU PLL automatically or manually switches between lock-to-reference mode and lock-to-data mode. This enables you to bypass the default automatic switchover circuitry if either rx_locktorefclk
or rx_locktodata is instantiated.
When the rx_locktorefclk signal is asserted, the CRU forces the receiver PLL to lock to the reference clock. When the rx_locktodata signal is asserted, the CRU forces the receiver PLL to lock-to-data. When both signals are asserted, the rx_locktodata signal takes precedence over the rx_locktorefclk signal, forcing the receiver PLL to lock-to-data.
The PPM threshold frequency detector and phase relationship detector reaction times may be too long for some applications. You can manually control the CRU to reduce PLL lock times using the rx_locktorefclk and rx_locktodata ports. Using the manual mode may reduce the time it takes for the CRU to switch from lock-to-reference mode to lock-to-data mode. You can assert the rx_locktorefclk to initially
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train the PLL to the reference clock. Once the receiver PLL locks to the reference clock, you can assert the rx_locktodata signal to force the
PLL to lock to the incoming data.
When the rx_locktorefclk signal is asserted high, the rx_freqlocked
signal does not have any significance and is always driven low, indicating that the CRU is in lock-to-reference mode. When the rx_locktodata signal is asserted high, the rx_freqlocked signal is always driven high, indicating that the CRU is in lock-to-data mode. If both signals are de-asserted, the CRU is in automatic lock mode.
shows a summary of the control signals.
Table 1–5. CRU User Control Lock Signals
rx_locktorefclk
1 x
0
rx_locktodata
0
1
0
CRU Mode
Lock-to-reference clock
Lock to data
Automatic
Deserializer
The deserializer block clocks in serial input data from the receiver buffer using the high-speed serial recovered clock and deserializes it into 8- or
10-bit parallel data using the low-speed parallel recovered clock. It feeds
the deserialized data to the word aligner as shown in Figure 1–36 .
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Figure 1–36. Deserializer
Received Data
D6
D5
D4
D3
D9
D8
D7
D2
D1
D0
Clock
Recovery
Unit
High-Speed Serial Recovered Clock
Low-Speed Parallel Recovered Clock
D6
D5
D4
D3
D9
D8
D7
D2
D1
D0
10
To Word
Aligner
Figure 1–37 shows the serial bit order of the deserializer block input and
the parallel data output of the deserializer block. A serial stream
(0101111100) is deserialized to a value 10'h17C. The serial data is assumed to be received LSB to MSB.
Figure 1–37. Deserializer Bit Order
Low-Speed Parallel Clock
High-Speed Serial Clock datain
0 0 1 1 1 1 1 0 1 0 1 1 0 0 0 0 0 1 0 1
dataout
0101111100 1010000011
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Receiver Polarity Inversion
The positive and negative signals of a serial differential link might be accidentally swapped during board layout. Solutions such as a board re-spin or major updates to the PLD logic can prove expensive. The receiver polarity inversion feature is provided to correct this situation.
An optional rx_invpolarity port is available in all modes to dynamically enable the receiver polarity inversion feature. A high on the rx_invpolarity
port inverts the polarity of every bit of the 8- or 10-bit input data word to the word aligner in the receiver data path. Since inverting the polarity of each bit has the same effect as swapping the positive and negative signals of the differential link, correct data is seen by the receiver. The rx_invpolarity is a dynamic signal and may cause initial disparity errors in an 8B/10B encoded link. The downstream system must be able to tolerate these disparity errors.
The receiver polarity inversion feature is different from the PCI Express
(PIPE) 8B/10B polarity inversion feature. The receiver polarity inversion feature inverts the polarity of the data bits at the input of the word aligner.
The PCI Express (PIPE) 8B/10B polarity inversion feature inverts the polarity of the data bits at the input of the 8B/10B decoder and is available only in PCI Express (PIPE) mode. Enabling the generic receiver polarity inversion and the PCI Express (PIPE) 8B/10B polarity inversion simultaneously is not allowed in PCI Express (PIPE) mode.
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Figure 1–38 illustrates the receiver polarity inversion feature.
Figure 1–38. Receiver Polarity Inversion
0
1
0
1
1
1
1
1
0
0 rx_invpolarity = High
Output from Deserializer
0
0
0
0
0
1
1
1
0
1
To Word Aligner
Input to Word Aligner
Figure 1–39. Word Aligner
Word Aligner
The word aligner (refer to Figure 1–39 ) clocks in received data from the
deserializer using the low-speed recovered clock. It restores the word boundary of the upstream transmitter based on the pre-defined word alignment character for the selected protocol. In addition to restoring the word boundary, the word aligner also implements a synchronization state machine in all functional modes to achieve lane synchronization.
Figure 1–39 shows the block diagram for the word aligner block.
datain bitslip
Word
Aligner enapatternalign dataout syncstatus patterndetect clock
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The word aligner consists of four sub-modules:
■
■
■
■
Aligner block
Pattern detect block
Manual bit-slip block
Run-length checker
There are two modes in which the word aligner works: basic mode and automatic synchronization state machine mode. The following sections explain each of the blocks in each mode of operation. The word aligner cannot be bypassed and must be used. However, you can use the rx_enapatternalign
port to set the word alignment to not align to the pattern.
■
■
■
Basic Mode
In basic mode, there are three blocks active in the word aligner:
Pattern detector
Manual word aligner
Automatic synchronization state machine
The pattern detector detects if the pattern exists in the current word boundary. The manual alignment identifies the alignment pattern across the byte boundaries and aligns to the correct byte boundary. The synchronization state machine detects the number of alignment patterns and good code groups for synchronization and goes out of synchronization if code group errors (bad code groups) are detected.
Figure 1–40 and Table 1–6 show the supported alignment modes when
basic mode is selected.
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Figure 1–40. Word Aligner Components in Basic Mode
10-Bit
Mode
Pattern Detector
7-Bit
Mode
Basic Mode
Manual
Alignment Mode
10-Bit
Mode
Synchronization
State Machines
Bit-Slip
Mode
7-Bit
Mode
Basic Mode PIPE Mode
Table 1–6. Word Alignment Modes
Word Alignment
Mode
Effective Mode Control Signals
Synchronization state machine
PCI Express, XAUI, GIGE, Serial
RapidIO, or Basic
Automatically controlled to adhere to the specified standard or by user entered parameter
Manual 7- and
10-bit alignment mode
Manual bit-slipping alignment mode
Alignment to detected pattern when allowed by the rx_enapatternalign
signal
Manual bit slip controlled by the
PLD logic array rx_enapatternalign rx_bitslip
Status Signals
rx_syncstatus rx_patterndetect rx_syncstatus rx_patterndetect rx_patterndetect
Pattern Detector Module
The pattern detector matches a pre-defined alignment pattern to the current byte boundary. When the pattern detector locates the alignment pattern, the optional rx_patterndetect signal is asserted for the duration of one clock cycle to signify that the alignment pattern exists in the current word boundary. The pattern detector module only indicates that the signal exists and does not modify the word boundary.
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Modification of the word boundary is discussed in the sections
and
“Synchronization State Machine
In the MegaWizard, you can program a 7-bit or a 10-bit pattern for the pattern detector to recognize. The pattern used for pattern matching is automatically derived from the word alignment pattern in the
MegaWizard. For the 7-bit and 10-bit patterns, the actual alignment pattern specified in the MegaWizard and its complement are checked.
shows the supported alignment patterns.
Table 1–7. Supported Alignment Patterns
Pattern Detect Mode
7 bit
10 bit
Supported Protocols Pattern Checked
Basic, GIGE (enhanced only)
Basic, XAUI, GIGE, Serial
RapidIO, and PIPE
Actual and complement
Actual and complement
In 8B/10B encoded data, actual and complement pattern indicates positive and negative disparities.
7-Bit Pattern Mode
In the 7-bit pattern detection mode (use this mode with 8B/10B code), the pattern detector matches the seven LSBs of the 10-bit alignment pattern, which you specified in your ALT2GXB custom megafunction variation, in the current word boundary. Both positive and negative disparities are also checked in this mode.
The 7-bit pattern mode can mask out the three MSBs of the data, which allows the pattern detector to recognize multiple alignment patterns. For example, in the 8B/10B encoded data, a /K28.5/ (b'0011111010), /K28.1/
(b'0011111001), and /K28.7/ (b'0011111000) share seven common LSBs.
Masking the three MSBs allows the pattern detector to resolve all three alignment patterns and indicate them on the rx_patterndetect port.
In 7-bit pattern mode, the word aligner still aligns to a 10 bit word boundary. The specified 7-bit pattern forms the least significant seven bits of the 10-bit word.
10-Bit Pattern Mode
In the 10-bit pattern detection mode (use this mode with 8B/10B code), the module matches the 10-bit alignment pattern you specified in your
ALT2GXB custom megafunction variation with the data and its complement in the current word boundary. Both positive and negative
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disparities are checked by the pattern checker in this mode. For example, if you specify a /K28.5/ (b'0011111010) pattern as the comma, rx_patterndetect
is asserted if b'0011111010 or b'1100000101 is detected in the incoming data.
Manual Alignment Modes
The word aligner has two manual alignment modes (7- and 10-bits) when the transceiver data path is in Basic mode.
7-bit Alignment Mode
In the 7-bit alignment mode (use the 8B/10B encoded data with this mode), the module looks for the 7-bit alignment pattern you specified in the MegaWizard Plug-In Manager in the incoming data stream. The 7-bit alignment mode is useful because it can mask out the three most significant bits of the data, which allows the word aligner to align to multiple alignment patterns. For example, in the 8B/10B encoded data, a
/K28.5/ (b'0011111010), /K28.1/ (b'0011111001), and /K28.7/
(b'0011111000) share seven common LSBs. Masking the three MSBs allows the word aligner to resolve all three alignment patterns synchronized to it. The word aligner places the boundary of the 7-bit pattern in the LSByte position with bit positions [0..7]. The true and complement of the patterns is checked.
Use the rx_enapatternalign port to enable the 7-bit manual word alignment mode. When the rx_enapatternalign signal is high, the word aligner detects the specified alignment patterns and realigns the byte boundary if needed. The rx_syncstatus port is asserted for one parallel clock cycle to signify that the word boundary was detected across the current word boundary and has synchronized to the new boundary, if a rising edge was detected previously on the rx_enapatternalign port. You must differentiate if the acquired byte boundary is correct, because the 7-bit pattern can appear between word boundaries. For example, in the standard 7-bit alignment pattern 7'b1111100, if a K28.7 is followed by a K28.5, the 7-bit alignment pattern appears on K28.7, between K28.7 and K28.5, and also again in K28.5 (refer to
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Figure 1–41. Cross Boundary 7-Bit Comma When /K28.7 is Followed by /K28.5
K28.7
K28.5
0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 1 0
7-bit comma-
7-bit comma-
7-bit comma+
Manual 10-Bit Alignment Mode
You can configure the word aligner to align to a 10-bit word boundary.
The internal word alignment circuitry shifts to the correct word boundary if the alignment pattern specified in the pattern detector is detected in the data stream.
The rx_enapatternalign port enables the word alignment in the manual 10-bit alignment mode. When the rx_enapatternalign signal is high, the word aligner detects the specified alignment pattern and realigns the byte boundary if necessary. The rx_syncstatus port is asserted for one parallel clock cycle to signify that the word boundary has been detected across the word boundary and has synchronized to the new boundary.
The rx_enapatternalign signal is held high if the alignment pattern is known to be unique and does not appear across the byte boundaries of other data. For example, if an 8B/10B encoding scheme guarantees that the /K28.5/ code group is a unique pattern in the data stream, the rx_enapatternalign
port is held at a constant high.
If the alignment pattern can exist between word boundaries, the rx_enapatternalign
port must be controlled by the user logic in the
PLD to avoid false word alignment. For example, assume that 8B/10B is used and a /+D19.1/ (b'110010 1001) character is specified as the alignment pattern. In this case, a false word boundary is detected if a
/-D15.1/ (b'010111 1001) is followed by a /+D18.1/ (b'010011 1001). Refer
.
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Figure 1–42. False Word Boundary Alignment if Alignment Pattern Exists Across Word Boundaries, Basic
Mode
…..
0 1 0 1
D15.1
1 1 1 0 0 1
+D19.1
0 1 0 0
+D18.1
1 1 1 0 0 1
…..
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May 2008
In this example, the rx_enapatternalign signal is deasserted after the word aligner locates the initial word alignment to prevent false word boundary alignment. When the rx_enapatternalign signal is deasserted, the current word boundary is locked even if the alignment pattern is detected across different boundaries. In this case, the rx_syncstatus
acts as a re-synchronization signal to signify that the alignment pattern was detected, but the boundary is different than the current boundary. You must monitor this signal and reassert the rx_enapatternalign
signal if realignment is desired.
Figure 1–43 shows an example of how the word aligner signals interact in
10-bit alignment mode. In this example, a /K28.5/ (10'b0011111010) is specified as the alignment pattern. The rx_enapatternalign signal is held high at time n, so alignment occurs whenever an alignment pattern exists in the pattern. The rx_patterndetect signal is asserted for one clock cycle to signify that the pattern exists on the re-aligned boundary.
The rx_syncstatus signal is also asserted for one clock cycle to signify that the boundary has been synchronized. At time n + 1, the rx_enapatternalign
signal is deasserted to instruct the word aligner to lock the current word boundary.
The alignment pattern is detected at time n + 2, but it exists on a different boundary than the current locked boundary. The bit orientation of the
Arria GX device is LSB to MSB, so the alignment pattern exists across time n + 2 and n + 3 (refer to
Figure 1–43 ). In this condition the
rx_patterndetect
remains low because the alignment pattern does not exist on the current word boundary, but the rx_syncstatus signal is asserted for one clock cycle to signify a resynchronization condition.
This means that the alignment pattern has been detected across another word boundary.
The user logic design in the PLD must decide whether or not to assert the rx_enapatternalign
to reinitiate the word alignment process. At time n + 5 the rx_patterndetect signal is asserted for one clock cycle to signify that the alignment pattern has been detected on the current word boundary.
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Figure 1–43. Word Aligner Symbol Interaction in 10-Bit Manual Alignment Mode
n n + 1 n + 2 n + 3 n + 4 rx_clkout rx_dataout[10..0] n + 5
111110000 0101111100 111110000 1111001010 1000000101 111110000 0101111100 rx_enapatternalign rx_patterndetect rx_syncstatus
Manual Bit-Slip Alignment Mode
You can also achieve word alignment by enabling the manual bit-slip option in the MegaWizard Plug-In Manager. With this option enabled, the transceiver shifts the word boundary MSB to LSB one bit every parallel clock cycle. The transceiver shifts the word boundary every time the bitslipping circuitry detects a rising edge of the rx_bitslip signal. At each rising edge of the rx_bitslip signal, the word boundary slips one bit.
The bit that arrives at the receiver first is skipped. When the word boundary matches the alignment pattern you specified in the
MegaWizard Plug-In Manager, the rx_patterndetect signal is asserted for one clock cycle. You must implement the logic in the PLD logic array to control the bit-slip circuitry.
The bit slipper is useful if the alignment pattern changes dynamically when the Arria GX device is in user mode. You can implement the controller in the logic array, so you can build a custom controller to dynamically change the alignment pattern without needing to reprogram the Arria GX device.
Figure 1–44 shows an example of how the word aligner signals interact in
the manual bit slip alignment mode. For this example, 8'b00111100 is specified as the alignment pattern and an 8'b11110000 value is held at the rx_datain
port.
Every rising edge on the rx_bitslip port causes the rx_dataout data to shift one bit from the MSB to the LSB by default. This is shown at time n + 2 where the 8'b11110000 data is shifted to a value of 8'b01111000. At this state the rx_patterndetect signal is held low because the specified alignment pattern does not exist in the current word boundary.
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The rx_bitslip is disabled at time n + 3 and re-enabled at time n + 4.
The output of the rx_dataout now matches the specified alignment pattern, thus the rx_patterndetect signal is asserted for one clock cycle. At time n + 5, the rx_patterndetect signal is still asserted because the alignment pattern still exists in the current word boundary.
Finally, at time n + 6 the rx_dataout boundary is shifted again and the rx_patterndetect
signal is deasserted to signify that the word boundary does not contain the alignment pattern.
Figure 1–44. Word Aligner Symbol Interaction in Manual Bit-Slip Mode
n n + 1 n + 2 n + 3 n + 4 rx_clkout rx_datain
00001111 n + 5 n + 6 rx_dataout[7..0] 11110000 01111000 00111100 00011110 rx_bitslip rx_patterndetect
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Synchronization State Machine Mode
You can choose to have the link synchronization handled by a state machine. Unlike the manual alignment mode where there is no built-in hysteresis to go into or fall out of synchronization, the synchronization state machine offers automatic detection of a valid number of alignment patterns and synchronization and detection of code group errors for automatically falling out of synchronization. The synchronization state machine is available in the Basic, XAUI, GIGE, and PIPE modes. For the
XAUI, GIGE, and PIPE modes, the number of alignment patterns, consecutive code groups, and bad code groups are fixed. You must use the 8B/10B code for the synchronization state machine. In XAUI, GIGE, and PIPE modes, the 8B/10B encoder/decoder is embedded in the transceiver data path. In Basic mode, you can configure the MegaWizard
Plug-In Manager to either use or bypass the 8B/10B encoder/decoder in the transceiver. If the synchronization state machine is enabled and the
8B/10B encoder/decoder is bypassed, the 8B/10B encoder/decoder logic must be implemented outside the transceiver as a requirement for using the synchronization state machine.
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In Basic mode, you can configure the state machine to suit a variety of standard and custom protocols. In the MegaWizard Plug-In Manager, you can program the number of alignment patterns to acquire link synchronization. You can program the number of bad code groups to fall out of synchronization. You can program the number of good code groups to negate a bad code group. You enter these values in the
MegaWizard Plug-In Manager. The rx_syncstatus port indicates the link status. A high level indicates link synchronization is achieved, a low level indicates that synchronization has not yet been achieved or that there were enough code group errors to fall out of synchronization.
Figure 1–45 shows a flowchart of the synchronization state machine.
Figure 1–45. Word Aligner Synchronization State Machine Flow Chart
Loss of Sync
Data= Comma
Data= !Valid
Comma Detect if Data == comma
kcntr++ else
kcntr=kcntr kcntr = 3
Data=valid; kcntr<3
Synchronized
Data=valid ecntr = 17
Data= !Valid
Synchronized Error
Detect if Data == !valid
ecntr++
gcntr=0 else if gcntr==16
ecntr- -
gcntr=0 else
gcntr++ ecntr = 0
The maximum value for the number of valid alignment patterns and good code groups is 256. The maximum value of invalid or bad code groups to fall out of synchronization is 8. For example, if 3 is set for the number of good code groups, then when 3 consecutive good code groups
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f are detected after a bad code group, the effect of the bad code group on synchronization is negated. This does not negate the bad code group that actually triggers the loss of synchronization. To negate a loss of synchronization, the protocol defined number of alignment patterns must be received.
When either XAUI or GIGE mode is used, the synchronization and word alignment is handled automatically by a built-in state machine that adheres to either the IEEE 802.3ae or IEEE 802.3 synchronization specifications, respectively. If you specify either standard, the alignment pattern is automatically defaulted to /K28.5/ (b'0011111010).
When you specify the XAUI protocol, code-group synchronization is achieved upon the reception of four /K28.5/ commas. Each comma can be followed by any number of valid code groups. Invalid code groups are not allowed during the synchronization stage. When code-group synchronization is achieved the optional rx_syncstatus signal is asserted.
For more information about the operation of the synchronization phase, refer to clause 47-48 of the IEEE P802.3ae standard or XAUI mode in the
Arria GX Transceiver Protocol Support and Additional Features
chapter in volume 2 of the Arria GX Device Handbook.
If you specify the GIGE protocol, code-group synchronization is achieved upon the reception of three consecutive ordered sets. An ordered set starts with the /K28.5/ comma and can be followed by an odd number of valid data code groups. Invalid code groups are not allowed during the reception of three ordered-sets. When code-group synchronization is achieved, the optional rx_syncstatus signal is asserted.
In PIPE mode, lane synchronization is achieved when the word aligner sees four good /K28.5/ commas and 16 good code groups. This is accomplished through the reception of four good PCI Express training sequences (TS1 or TS2). The PCI-Express fast training sequence (FTS) can also be used to achieve lane or link synchronization, but requires at least five of these training sequences. The rx_syncstatus signal is asserted when synchronization is achieved and is deasserted when the word aligner receives 23 code group errors.
Run Length Checker
The programmable run-length violation circuit resides in the word aligner block and detects consecutive 1s or 0s in the data. If the data stream exceeds the preset maximum number of consecutive 1s or 0s, the violation is signified by the assertion of the rx_rlv signal.
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This signal is not synchronized to the parallel data and appears in the logic array earlier than the run-length violation data. To ensure that the
PLD can latch this signal in systems where there are frequency variations between the recovered clock and the PLD logic array clock, the rx_rlv signal is asserted for a minimum of two clock cycles. The rx_rlv signal may be asserted longer, depending on the run-length of the received data.
The run-length violation circuit detects up to a run length of 128 (for an
8-bit deserialization factor) or 160 (for a 10-bit deserialization factor). The settings are in increments of 4 or 5 for the 8-bit or 10-bit deserialization factors, respectively.
Receiver Bit Reversal
By default, the Arria GX receiver assumes an LSB to MSB transmission. If the transmission order is MSB to LSB, then the receiver will put out the bit-flipped version of the data on the PLD interface. The Receiver Bit
Reversal feature is available to correct this situation.
The Receiver Bit Reversal feature is available only in Basic mode. If the
Receiver Bit Reversal feature is enabled, the 10-bit data D[9:0] at the output of the word aligner gets rewired to D[0:9]. Flipping the parallel data using this feature allows the receiver to put out the correctly bit-ordered data on the PLD interface in case of MSBit to LSBit transmission.
Because the receiver bit reversal is done at the output of the word aligner, a dynamic bit reversal would also require a reversal of word alignment pattern. As a result, the Receiver Bit Reversal feature is dynamic only if the receiver uses manual bit-slip alignment mode (no word alignment pattern). The Receiver Bit Reversal feature is static in all other Basic mode configurations and can be enabled through the MegaWizard Plug-In
Manager. In configurations where this feature is dynamic, an rx_revbitordwa
port is available to control the bit reversal dynamically. A high on the rx_revbitordwa port reverses the bit order at the input of the word aligner.
Figure 1–46 illustrates the receiver bit reversal feature in Basic 10-bit wide
data path configuration.
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Figure 1–46. Receiver Bit Reversal in Basic Mode
D
[9]
D[8]
D[7]
D[6]
D[5]
RX Bit Reversal = Enabled
D[4]
D[3]
D[2]
D[1]
D[0]
Output of Word Aligner before
RX bit reversal
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
Output of Word Aligner after RX bit reversal f
Channel Aligner (Deskew)
The channel aligner is automatically used when implementing the XAUI protocol to ensure that the channels are aligned with respect to each other.
The channel aligner uses a 16-word deep FIFO buffer and is available only in the XAUI mode.
For additional information about the Channel Aligner block, refer to the
Arria GX Transceiver Protocol Support and Additional Features
chapter in volume 2 of the Arria GX Device Handbook.
Rate Matcher
In asynchronous systems, the upstream transmitter and the local receiver may be clocked with independent reference clock sources. Frequency differences in the order of a few hundred PPM can potentially corrupt the data at the receiver. The rate matcher compensates for small clock frequency differences between the upstream transmitter and the local receiver clocks by inserting or removing skip characters or ordered-sets from the inter-packet gap (IPG) or idle streams. It inserts a skip character or ordered-set if the local receiver is running a faster clock than the upstream transmitter. It deletes a skip character or ordered-set if the local
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receiver is running a slower clock than the upstream transmitter. The rate matcher is available in PCI Express (PIPE), GIGE, XAUI, and Basic functional modes.
The rate matcher consists of a 20-word-deep FIFO buffer and necessary logic to detect and perform the insertion and deletion functions. The write port of the rate matcher FIFO is clocked by the low-speed parallel recovered clock. The read port is clocked by the low-speed parallel clock
from the CMU central or local clock divider block ( Figure 1–47
).
Figure 1–47. Rate Matcher
datain[9:0]
From Word Aligner
Rate Matcher wrclk rdclk
To 8B/10B
Decoder dataout[9:0]
Low-Speed Parallel
Recovered Clock from CRU
Low-Speed Parallel
CMU Clock
CMU
Local/Central Clock
Divider Block f
For information about the rate matcher in PIPE, GIGE, and XAUI modes, refer to the
Arria GX Transceiver Protocol Support and Additional Features
chapter in volume 2 of the Arria GX Device Handbook.
Basic Mode General Rate Matching
In Basic mode, the rate matcher supports up to 300 PPM differences between the upstream transmitter and the receiver. The rate matcher looks for the skip ordered set (SOS), which is a /K28.5/ comma followed by three programmable neutral disparity skip characters (for example,
/K28.0/). For general rate matching, you can customize the SOS to support a variety of protocols, including custom protocols. The SOS must contain a valid control code group (Kx.y), followed by any neutral disparity skip code group (any Kx.y or Dx.y of neutral disparity, for example, K28.0). The rate matcher deletes or inserts skip characters when necessary to prevent the rate matching FIFO buffer from overflowing or underflowing.
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The rate matcher in Basic mode can delete any number of skip characters as necessary in a cluster as long as there are skip characters to delete.
There are no restrictions regarding deleting more than one skip character in a cluster of skip characters.
Figure 1–48 shows an example of a Basic
mode rate matcher deletion of two skip characters. Although the skip characters are programmable, the /K28.0/ control group is used for illustration purposes.
Figure 1–48. Basic Mode Deletion of Two Skip Characters
clock
K28.5
K28.0
K28.0
K28.0
datain dataout K28.5
K28.0
Dx.y
Dx.y
K28.5
K28.0
K28.0
K28.5
K28.0
K28.0
Dx.y
Dx.y
Two Skips Deleted
The rate matcher inserts skip characters as required for rate matching. For a given skip ordered set, the rate matcher inserts skip characters so that the total number of consecutive skip characters does not exceed five at the
output of the rate matching FIFO buffer. Figure 1–49
shows an example where a skip character insertion is made on the second set of skip ordered sets because the first set has the maximum number of skip characters.
Figure 1–49. Basic Mode Insertion of a Skip Character
One Skip Inserted
clock datain dataout
K28.5
K28.0
K28.0
K28.0
K28.0
K28.0
K28.5
K28.0
K28.0
K28.0
K28.0
K28.0
One Skip Inserted
Dx.y
K28.5
K28.0
Dx.y
Dx.y
K28.5
K28.0
K28.0
The Arria GX rate matcher in Basic mode has FIFO buffer overflow and underflow protection. In the event of a FIFO buffer overflow the rate matcher deletes any data after the overflow condition to prevent FIFO buffer pointer corruption until the rate matcher is not full. In an underflow condition, the rate matcher inserts 9'h1FE (/K30.7) until the
FIFO buffer is not empty. These measures ensure that the FIFO buffer gracefully exits the overflow and underflow condition without requiring a FIFO buffer reset.
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8B/10B Decoder
The 8B/10B decoder takes in 10-bit data from the rate matcher and decodes it into 8-bit data + 1-bit control identifier, thereby restoring the original transmitted data at the receiver. The decoded data is fed to either the byte deserializer or the receiver phase compensation FIFO buffer
(depending on protocol). The 8B/10B decoder conforms to IEEE 802.3
1998 edition standards.
Figure 1–50 shows a 10-bit code group decoded to an 8-bit data and a 1-bit
control indicator.
Figure 1–50. 10-Bit to 8-Bit Conversion
j
9 h
8 g
7 f
6 i
5 e
4 d
3 c
2 b
1 a
0
MSB Received Last
LSB Received First
8B/10B Conversion ctrl 7
H
6
G
5
F
4
E
3
D
2
C
1
B
0
A
Parallel Data
Control Code Group Detection
The 8B/10B decoder differentiates between data and control codes through the rx_ctrldetect port. If the received 10-bit code group is a control code group (Kx.y), the rx_ctrldetect signal is driven high. If it is a data code group (Dx.y), the rx_ctrldetect signal is driven low.
Figure 1–51 shows an example waveform demonstrating the receipt of a
K28.5 code group (BC + ctrl). The rx_ctrldetect=1'b1 is aligned with
8'hbc, indicating that it is a control code group. The rest of the codes received are Dx.y code groups.
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Figure 1–51. Control Code Group Detection
clock dataout[7..0 ]
83 78 BC ctrldetect
Code Group
BC 0F 00
D3.4
D24.3
D28.5
K28.5
D15.0
D0.0
BF 3C
D31.5
D28.1
f
Code Group Error Detection
If the received 10-bit code group is not a part of valid Dx.y or Kx.y code groups, the 8B/10B decoder block asserts an error flag on the rx_errdetect
port. The error flag signal (rx_errdetect) has the same data path delay from the 8B/10B decoder to the PLD-transceiver interface as the invalid code group.
In GIGE, XAUI, and PIPE modes, the invalid code is replaced by a
/K30.7/ code (8'hFE on rx_dataout + 1'b1 on rx_ctrldetect). In all other modes, the value of the invalid code value can vary and should be ignored
Disparity Error Detection
If the received 10-bit code group is detected with incorrect running disparity, the 8B/10B decoder block asserts an error flag on the rx_disperr
and rx_errdetect ports.
Refer to the
Specifications and Additional Information
chapter in volume 2 of the Arria GX Device Handbook for information about the disparity calculation.
If negative disparity is calculated for the last 10-bit code group, a neutral or positive disparity 10-bit code group is expected. If the 8B/10B decoder does not receive a neutral or positive disparity 10-bit code group, the rx_disperr
signal goes high, indicating that the code group received has a disparity error. Similarly, if a neutral or negative disparity is expected and a 10-bit code group with positive disparity is received, the rx_disperr
signal goes high.
The detection of the disparity error might be delayed, depending on the data that follows the actual disparity error. The 8B/10B control codes terminate propagation of the disparity error. Any disparity errors propagated stop at the control code group, terminating that disparity error.
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Figure 1–52. Disparity Error Detection
n clock rx_dataout[7..0 ]
BC n+1
BC rx_disperr rx_errdetect rx_ctrldetect
Expected RD Code
RD Code Received rx_datain
RD-
RD-
17C
RD+
RD+
283
In GIGE and XAUI modes, the code that contains a disparity error is replaced by a /K30.7/ code (8'hFE on rx_dataout + rx_ctrldetect).
In all other modes, the code with incorrect disparity should be treated as an invalid code and ignored.
Figure 1–52 shows a case where the disparity is violated. A K28.5 code
group has an 8-bit value of 8'hbc and a 10-bit value that depends on the disparity calculation at the point of the generation of the K28.5 code group. The 10-bit value is 10'b0011111010 (10'h17c) for RD– or
10'b1100000101 (10'h283) for RD+. If the running disparity at time n - 1 is negative, the expected code group at time must be from the RD– column.
A K28.5 does not have a balanced 10-bit code group (equal number of 1s and 0s), so the expected RD code group must toggle back and forth between RD– and RD+. At time n + 3, the 8B/10B decoder received a RD+
K28.5 code group (10'h283), which makes the current running disparity negative. At time n + 4, because the current disparity is negative, a K28.5 from the RD– column is expected, but a K28.5 code group from the RD+ is received instead. This prompts rx_disperr to go high during time n + 4 to indicate that this particular K28.5 code group had a disparity error. The current running disparity at the end of time n + 4 is negative because a K28.5 from the RD+ column was received. Based on the current running disparity at the end of time n + 5, a positive disparity K28.5 code group (from the RD–) column is expected at time n + 5.
n+2
BC n+3
BC n+4 xx n+5
BC
RD-
RD-
17C
RD+
RD+
283
RD-
RD+
283
RD-
RD-
17C n+6
BC n+7
BC
RD+
RD+
283
RD-
RD-
17C
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Reset Condition
The reset for the 8B/10B decoder block is derived from the receiver digital reset (rx_digitalreset). When rx_digitalreset is asserted, the
8B/10B decoder block resets. In reset, the disparity registers are cleared and the outputs of the 8B/10B decoder block are driven low. After reset, the 8B/10B decoder starts with unknown disparity, depending on the disparity of the data it receives. The decoder calculates the initial running disparity based on the first valid code group received.
1
The receiver block must be word aligned after reset before the
8B/10B decoder can decode valid data or control codes. If word alignment has not been achieved, the data from the 8B/10B decoder should be considered invalid and discarded.
Polarity Inversion
The 8B/10B decoder has a PCI Express compatible polarity inversion on the data bus prior to 8B/10B decoding. This polarity inversion inverts the bits of the incoming data stream prior to the 8B/10B decoding block to fix potential P-N polarity inversion on the differential input buffer. You use the optional pipe8b10binvpolarity port to invert the inputs to the
8B/10B decoder dynamically from the PLD.
Byte Deserializer
The byte deserializer (
Figure 1–53 ) takes in 8- or 10-bit wide data from the
8B/10B decoder and deserializes it into 16- or 20-bit wide data at half the speed. This allows clocking the PLD-transceiver interface at half the speed as compared to the receiver PCS logic. The byte deserializer is bypassed in GIGE mode.
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Figure 1–53. Byte Deserializer
datain[7:0]
From 8B/10B
Decoder
Byte
Deserializer wrclk rdclk dataout[15:0]
To receiver phase compensation
FIFO
/2
Low -speed parallel recovered clock from CRU (1) or Low -speed parallel CMU clock (2)
Notes to
(1) Write port is clocked by low-speed parallel recovered clock if rate matcher is not used.
(2) Write port is clocked by low-speed parallel CMU clock if rate matcher is used.
If the byte deserializer is used, the byte ordering at the receiver output might be different than what was transmitted.
16-bit transmitted data pattern with A at the lower byte, followed by B at the upper byte. C and D follow in the next lower and upper bytes, respectively. At the byte deserializer, byte A arrives when it is stuffing the upper byte instead of stuffing the lower byte. This is a non-deterministic swap because it depends on PLL lock times and link delay. Implement byte-ordering logic in the PLD to correct this situation.
Figure 1–54. Intended Transmitted Pattern and Incorrect Byte Position at
Receiver After Byte Serializer
X
X
B
A
D
C
Intended Transmitted
Pattern
A
X
C
B
X
D
Incorrect Byte Position at Receiver
Receiver Phase Compensation FIFO Buffer
The receiver phase compensation FIFO buffer ( Figure 1–55
) is located at the FPGA logic array interface in the receiver block and is used to compensate for phase difference between the receiver clock and the clock from the PLD. The receiver phase compensation FIFO buffer operates in
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two modes: low latency and high latency. In low latency mode, the FIFO buffer is four words deep. The Quartus II software chooses the low latency mode automatically for every mode except the PCI-Express PIPE mode (which automatically uses high latency mode). In high latency mode, the FIFO buffer is eight words deep.
Figure 1–55. Receiver Phase Compensation FIFO Buffer
Receiver Channel rx_dataout[] datain[ ]
From Byte
Deserializer or
8B/10B Decoder
Receiver Phase
Compensation
FIFO wrclk rdclk
To PLD or PIPE interface
Low-Speed Parallel
Recovered Clock (1) or
Low-Speed Parallel
CMU Clock (2)
/2 rx_coreclk
Notes to
(1) Write port is clocked by low-speed parallel recovered clock when rate matcher is not used.
(2) Write port is clocked by low-speed parallel CMU clock when rate matcher is used.
rx_clkout or tx_clkout or coreclkout
In Basic mode, the write port is clocked by the recovered clock from the
CRU. This clock is half the rate if the byte deserializer is used. The read clock is clocked by the associated channel’s recovered clock.
1
The receiver phase compensation FIFO is always used and cannot be bypassed.
In four-channel (×4) bonding mode, all the read pointers are derived from a common source so that there is no need to synchronize the data of each channel in the PLD logic.
Receiver Phase Compensation FIFO Error Flag
Depending on the transceiver configuration, the write port of the receiver phase compensation FIFO can be clocked by either the recovered clock
(rx_clkout) or transmitter PLL output clock (tx_clkout or coreclkout
). The read port can be clocked by the recovered clock
(rx_clkout), transmitter PLL output clock (tx_clkout or
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coreclkout
) or a PLD clock. In all configurations, the write clock and the read clock must have 0 PPM difference to avoid overrun/underflow of the phase compensation FIFO.
An optional debug_rx_phase_comp_fifo_error port is available in all modes to indicate receiver phase compensation FIFO overrun/underflow condition. debug_rx_phase_comp_fifo_error is asserted high when the phase compensation FIFO gets either full or empty. This feature is useful to verify the phase compensation FIFO overrun/underflow condition as a probable cause of link errors.
PLD-Transceiver
Interface
Clocking
The transmitter phase compensation FIFO present at each channel’s
PLD-transmitter interface compensates for the phase difference between the PLD clock that produces the data to be transmitted and the transmitter PCS clock. The receiver phase compensation FIFO present at each channel’s PLD-receiver interface compensates for the phase difference between the PLD clock that processes the received data and the receiver PCS clock.
Depending on the functional mode, the Quartus II software automatically selects appropriate clocks to clock the read port of the transmitter phase compensation FIFO and the write port of the receiver phase compensation FIFO.
■
■
The write clock of the transmitter phase compensation FIFO and the read clock of the receiver phase compensation FIFO are part of the
PLD-transceiver interface clocks. Arria GX transceivers provide the following two options for selecting these PLD-transceiver interface clocks:
Automatic Phase Compensation FIFO clock selection
User Controlled Phase Compensation FIFO clock selection
The automatic phase compensation FIFO clock selection is a simpler option, but could lead to higher clock resource utilization as compared to user controlled phase compensation FIFO clock selection. This could be critical in designs with high clock resource requirements.
Automatic Phase Compensation FIFO Clock Selection
If you do not instantiate the tx_coreclk and rx_coreclk ports for the
Arria GX transceiver instance in the MegaWizard Plug-In Manager, the
Quartus II software automatically selects appropriate clocks to clock the write port of the transmitter phase compensation FIFO and the read clock of the receiver phase compensation FIFO.
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lists the clock sources that the Quartus II software automatically selects for the transmitter and receiver phase compensation FIFOs, depending on the functional mode.
Table 1–8. Clock Sources for the Transmitter and Receiver Phase Compensation FIFOs
Functional Mode
Write port clock selection for
Transmitter Phase Compensation
FIFO
Read port clock selection for
Receiver Phase Compensation
FIFO
Individual-channel mode with rate matcher
Individual-channel mode without rate matcher tx_clkout[0]
from channel 0 clocks the FIFO write port in all channels in the same transceiver block.
tx_clkout[0]
from channel 0 clocks the FIFO write port in all channels in the same transceiver block.
tx_clkout[0]
from channel 0 clocks the FIFO read port in all channels in the same transceiver block.
rx_clkout
from each channel clocks the FIFO read port of its associated channel.
Bonded-channel mode with/without rate matcher coreclkout clocks the FIFO write port in all channels in the same transceiver block.
coreclkout clocks the FIFO read port in all channels in the same transceiver block.
In an individual-channel mode without rate matcher (Serial RapidIO), a total of five global/regional clock resources per transceiver block are used by the PLD-transceiver interface clocks. Four clock resources are used by the rx_clkout signal of each channel being routed back to clock the read port of its receiver phase compensation FIFO. One clock resource is used by the tx_clkout[0] signal of Channel 0 being routed back to clock the write port of all transmitter phase compensation FIFOs in the transceiver block.
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Figure 1–56 shows the minimum PLD-Interface clock utilization per
transceiver block when configured in individual-channel mode without the rate matcher.
Figure 1–56. Minimum PLD-Interface Clock Utilization Per Transceiver Block Without the Rate Matcher
PLD XCVR
RX Phase
Comp FIFO
Channel 3
CRU rx_clkout[3] tx_clkout[0]
TX Phase
Comp FIFO
RX
TX CLK
Div Block
TX
RX Phase
Comp FIFO
Channel 2
CRU
RX rx_clkout[2] tx_clkout[0]
TX Phase
Comp FIFO
TX CLK
Div Block
TX
RX Phase
Comp FIFO
Channel 1
CRU
RX rx_clkout[1] tx_clkout[0] rx_clkout[0]
TX Phase
Comp FIFO
TX Phase
Comp FIFO
TX CLK
Div Block
TX
RX Phase
Comp FIFO
Channel 0
CRU
RX
TX CLK
Div Block
TX tx_clkout[0]
The PLD-transceiver clock utilization can be reduced by driving the transmitter and receiver phase compensation FIFOs with a single clock.
This is possible only if the driving clock is frequency-locked to the transceiver output clocks (tx_clkout, coreclkout, or rx_clkout).
To control the write and read clock selection for the transmitter and receiver phase compensation FIFO, you must instantiate the tx_coreclk
and rx_coreclk ports for the transceiver channels.
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User Controlled Phase Compensation FIFO Clock Selection
Instead of the Quartus II software automatically selecting the write and read clocks of the transmitter and receiver phase compensation FIFOs, respectively, you can manually connect appropriate clocks by instantiating the tx_coreclk and rx_coreclk ports in the
MegaWizard Plug-In Manager. For all like channels configured in the same functional mode and running off the same clock source, you can connect the tx_coreclk and rx_coreclk ports of all channels together and drive them using the same clock source. You can use a PLD clock input pin or a transceiver clock
(tx_clkout[0]/coreclkout/rx_clkout) to clock the tx_coreclk/rx_coreclk
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Figure 1–57. User Controlled Phase Compensation FIFO Clock
Channel 3
RX Phase
Comp FIFO
CRU rx_coreclk[3]
TX Phase
Comp FIFO
TX CLK
Div Block tx_coreclk[3]
Channel 2
RX Phase
Comp FIFO
CRU rx_coreclk[2]
RX
TX
RX
TX
TX Phase
Comp FIFO
TX CLK
Div Block tx_coreclk[2]
Channel 1
RX
RX Phase
Comp FIFO
CRU rx_coreclk[1]
TX
TX Phase
Comp FIFO
TX CLK
Div Block tx_coreclk[1]
Channel 0
RX
RX Phase
Comp FIFO
CRU rx_coreclk[0]
TX
To user logic tx_coreclk[0] tx _clkout[0]
TX Phase
Comp FIFO
TX CLK
Div Block
1
If the rx_clkout signal is used as a driver, it can only drive the rx_coreclk
ports. It cannot drive the tx_coreclk ports. If tx_coreclk
and rx_coreclk need to be driven with the same clock, you must use the tx_clkout signal as the clock driver.
If the clock signal on tx_coreclk is used to clock the write side of the transmitter phase compensation FIFO, you must make sure that it is frequency locked to the transmitter PCS clock reading from the FIFO. If the clock signal on rx_coreclk is used to clock the read side of the
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PLD-Transceiver Interface Clocking
receiver phase compensation FIFO, you must make sure that it is frequency locked to the receiver PCS clock writing into the FIFO. Any frequency differences may cause data corruption.
To help guard against incorrect usage, the use of the tx_coreclk and rx_coreclk
options requires clock assignments in the assignment organizer. If no assignments are used, the Quartus II software will issue a compilation error.
There are four settings to enable the PLD interface clocking options:
■
■
■
■
Stratix II GX/Arria GX GXB Shared Clock Group Setting
Stratix II GX/Arria GX GXB Shared Clock Group Driver Setting
Stratix II GX/Arria GX 0PPM Clock Group Setting
Stratix II GX/Arria GX 0PPM Clock Group Driver Setting
There are two main settings, Shared Clock and 0 PPM Clock, each with a driver and clock group setting. When specifying clock groups, an integer identifier is used as the group name to differentiate the different clock group settings from each another.
The Stratix II GX/Arria GX GXB Shared Clock Group Setting is the safest assignment. The Quartus II compiler analyzes the netlist during compilation to ensure transmitter channel members are derived from the same source. The Quartus II software gives a fitting error for incompatible assignments. The software cannot check for the output of the receiver frequency locked to the driving clock as the exact frequency is dictated by the upstream transmitter’s source clock. You must ensure that the rx_coreclk is derived from the same source clock as the upstream transmitter.
The Stratix II GX/Arria GX GXB Shared Clock Group Driver Setting assignment must be made to the source channel of the tx_clkout or coreclkout
. Specifying anything but the transmitter channels (the source for the tx_clkout or coreclkout) results in a Fitter error. If the source clock is not from tx_clkout or coreclkout (for example, the source is from rx_clkout or from a PLD clock input), the 0 PPM setting must be used instead.
For example, in a synchronous system, the transmitter and receiver are running off the same clock. To make tx_clkout[0] the clock driver, the
Stratix II GX/Arria GX GXB Shared Clock Group Driver Setting
is made in the assignment editor on the tx_dataout[0] name. You can use a group identifier value of “1” to identify the group that this driver feeds.
The Stratix II GX/Arria GX GXB Shared Clock Group Setting is made to all the rx_datain channels that the tx_dataout[0] output clock drives.
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1
The other tx_dataout channels do not need an assignment because the Quartus II software automatically groups the like transmitters in a transceiver block. A group identifier value of
“1” is also made to the rx_datain assignments.
The assignments in the Assignment Editor are shown in Table 1–9 .
Table 1–9. Assignment Editor
To:
Assignment name:
Value:
To:
Assignment name:
Value: tx_dataout[0]
Stratix II GX/Arria GX GXB Shared Clock Group Driver
Setting
1 rx_datain[] (note that the [] signifies the entire rx_datain
group)
Stratix II GX/Arria GX GXB Shared Clock Group Setting
1
The Stratix II GX/Arria GX 0PPM Clock Group Setting is for more advanced users that know the clocking configuration of the entire system and want to reduce the PLD global clock resource and PLD interface clock resource utilization. The Quartus II compiler does not perform any checking on the clock source. It is up to you to ensure that there is no frequency difference from the associated transceiver clock of the group and the driving clock to the tx_coreclk and rx_coreclk ports.
The Stratix II GX/Arria GX 0PPM Clock Group Driver Setting can be used with any of the transceiver output clocks (tx_clkout, rx_clkout, and coreclkout) as well as any PLD clock input pins, transceiver dedicated REFCLK pin, or PLD PLL output. User logic cannot be used as a driver. As with the shared clock group setting, the driver setting for the transceiver output clocks is made to the associated channel. For example, for tx_clkout or coreclkout, the transmitter channel name is specified. When the rx_clkout is the driver, the receiver channel name of the associated rx_clkout is specified. For the PLD input clock pins and the transceiver REFCLK pins, the name of the clock pin can be specified. For the PLL output, the PLL clock output port of the PLL can be found in the Node Finder and entered as the driver name. An integer value is specified for the group identification.
The Stratix II GX/Arria GX 0PPM Clock Group Setting is made to the transmitter or receiver channel names.
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The assignments in the Assignment Editor are shown in Table 1–10
.
f
Table 1–10. Assignment Editor
To:
Assignment name:
Value:
To:
Assignment name:
Value: tx_dataout[0], pld_clk_pin_name, refclk_pin,
and pll_outclk
Stratix II GX/Arria GX GXB 0PPM Clock Group Driver
Setting
1 rx_datain[]
and tx_dataout[]
Stratix II GX/Arria GX GXB 0PPM Clock Group Setting
1
For a complete set of features supported in each protocol, refer to the
Arria GX Transceiver Protocol Support and Additional Features
chapter in volume 2 of the Arria GX Device Handbook.
Loopback Modes
There are several loopback modes available on the Arria GX transceiver block that allow you to isolate portions of the circuit. All paths are designed to run up to full speed. The available loopback paths are:
■
■
■
■
Serial loopback available in all functional modes except PCI Express
(PIPE)
Reverse serial loopback available in Basic mode with 8B/10B
PCI Express PIPE reverse parallel loopback available in PCI Express protocol
Reverse serial pre-CDR loopback available in Basic mode with
8B/10B Reverse serial loopback available in Basic mode with 8B/10B
Serial Loopback
Figure 1–58 shows the data path for serial loopback. A data stream is fed
to the transmitter from the FPGA logic array and has the option of utilizing all the blocks in the transmitter. The data, in serial form, then traverses from the transmitter to the receiver. The serial data is the data that is transmitted from the Arria GX device. Once the data enters the receiver in serial form, it can use any of the receiver blocks and is then fed into the FPGA logic array.
Use the rx_seriallpbken port to dynamically enable serial loopback on a channel by channel basis. When rx_seriallpbken is high, all blocks that are active when the signal is low are still active. When the serial loopback is enabled, the tx_dataout port is still active and drives out the output pins.
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Serial loopback is often used to check the entire path of the transceiver.
The data is retimed through different clock domains and an alignment pattern is still necessary for the word aligner.
Figure 1–58. Arria GX Block in Serial Loopback Mode
Transmitter Digital Logic
BIST
Incremental
Generator
BIST
PRBS
Generator
TX Phase
Compensation
FIFO
Byte
Serializer
20
8B/10B
Encoder
FPGA
Logic
Array
BIST
Incremental
Verify
RX Phase
Compensation
FIFO
Byte
Ordering
Byte
Deserializer
8B/10B
Decoder
Rate
Match
FIFO
Analog Receiver and
Transmitter Logic
Serializer
Serial
Loopback
Deskew
FIFO
BIST
PRBS
Verify
Word
Aligner
Deserializer
Clock
Recovery
Unit
Receiver Digital Logic
PCI Express PIPE Reverse Parallel Loopback
Figure 1–59 shows the data path for the PCI Express PIPE reverse parallel
loopback. This data path is not flexible because it must be compliant with the PCI Express PIPE specification. The data comes in from the rx_datain
ports. The receiver uses the CRU, deserializer, word aligner, and rate matching FIFO buffer, loops back to the transmitter serializer, and then goes out the transmitter tx_dataout ports. The data also goes to the PLD fabric on the receiver side to the tx_dataout port. The deskew FIFO buffer is not enabled in this loopback mode. This loopback mode is optionally controlled dynamically through the tx_detectrxloopback
port.
1
This is the only loopback allowed in the PIPE mode.
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Figure 1–59. Arria GX Block in PCI Express PIPE Reverse Parallel Loopback Mode
Transmitter Digital Logic
BIST
Incremental
Generator
BIST
PRBS
Generator
Analog Receiver and
Transmitter Logic
FPGA
Logic
Array
TX Phase
Compensation
FIFO
Byte
Serializer
20
8B/10B
Encoder
PCI Express PIPE
Reverse Parallel
Loopback
Serializer
BIST
Incremental
Verify
RX Phase
Compensation
FIFO
Byte
Deserializer
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
BIST
PRBS
Verify
Word
Aligner
Deserializer
Clock
Recovery
Unit
Receiver Digital Logic
Reverse Serial Loopback
Reverse serial loopback is a subprotocol in Basic mode. It requires
8B/10B, and the word aligner pattern of K28.5. No dynamic pin control is available to select or deselect reverse serial loopback. The active block of the transmitter is only the buffer. The data sent to the receiver is retimed with the recovered clock and sent out to the transmitter.
The data path for reverse serial loopback is shown in
comes in from the rx_datain ports in the receiver. The data is then fed through the CDR block in serial form directly to the tx_dataout ports in the transmitter block.
You can enable reverse serial loopback for all channels through the
MegaWizard Plug-In Manager. Any pre-emphasis setting on the transmitter buffer is ignored in reverse serial loopback. The data flows through the active blocks of the receiver and into the logic array.
Reverse serial loopback is often implemented when using a bit error rate tester (BERT).
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Figure 1–60. Arria GX Block in Reverse Serial Loopback Mode
Transmitter Digital Logic
BIST
Incremental
Generator
BIST
PRBS
Generator
TX Phase
Compensation
FIFO
Byte
Serializer
FPGA
Logic
Array
BIST
Incremental
Verify
RX Phase
Compensation
FIFO
20
8B/10B
Encoder
Byte
Deserializer
8B/10B
Decoder
Rate
Match
FIFO
Receiver Digital Logic
Analog Receiver and
Transmitter Logic
Serializer
Reverse
Serial
Loopback
Deskew
FIFO
BIST
PRBS
Verify
Word
Aligner
Deserializer
Clock
Recovery
Unit
Reverse Serial Pre-CDR Loopback
The reverse serial pre-CDR loopback uses the analog portion of the transceiver. An external source (pattern generator or transceiver) generates the source data. The high-speed serial source data arrives at the high-speed differential receiver input buffer, loops back before the CRU unit, and is transmitted though the high-speed differential transmitter output buffer. This loopback mode is for test or verification use only to verify the signal being received after the gain and equalization improvements of the input buffer. The signal at the output is not exactly what is received, because the signal goes through the output buffer and the VOD is changed to the VOD setting level. The pre-emphasis settings have no effect.
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Figure 1–61. Arria GX Block in Reverse Serial Pre-CDR Loopback Mode
Transmitter Digital Logic
BIST
Incremental
Generator
BIST
PRBS
Generator
TX Phase
Compensation
FIFO
Byte
Serializer
FPGA
Logic
Array
BIST
Incremental
Verify
RX Phase
Compensation
FIFO
20
8B/10B
Encoder
Byte
Deserializer
8B/10B
Decoder
Rate
Match
FIFO
Analog Receiver and
Transmitter Logic
Serializer
Reverse
Serial
Loopback
Pre-CDR
Deskew
FIFO
BIST
PRBS
Verify
Word
Aligner
Deserializer
Clock
Recovery
Unit
Receiver Digital Logic
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May 2008
Incremental Pattern Generator
The incremental data generator sweeps through all the valid 8B/10B data and control characters. This mode is only available in Basic mode with the
BIST/parallel loopback subprotocol in the Quartus II software. You can also enable the incremental BIST verifier to perform a quick verification of the 8B/10B encoder/decoder paths.
In incremental mode, the BIST generator sends out the data pattern in the following sequence: K28.5 (comma), K27.7 (start of frame, SOF), Data
(00 FF incremental), K28.0, K28.1, K28.2, K28.3, K28.4, K28.6, K28.7, K23.7,
K30.7, K29.7 (end of frame, EOF), and then repeats. You must enable the
8B/10B encoder for proper operation. No dynamic control pin is available to enable or disable the loopback. Test result pins are rx_bistdone and rx_bisterr
. The rx_bistdone signal goes high at the end of the sequence. If the verifier detects an error before it is finished, rx_bisterr pulses high as long as the data is in error.
Built-In Self Test Modes
In addition to the regular data flow blocks, each transceiver channel contains an embedded built-in self test (BIST) generator and corresponding verifier block that you can use for quick device and setup verification (
Figure 1–62 ). The generators reside in the transmitter block
and the verifier in the receiver block. The generators can generate PRBS patterns. The verifiers are only available for the PRBS patterns. The BIST modes are only available as subprotocols under Basic mode.
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Figure 1–62. Built-In Self Test Mode
rx_datain[] tx_digitalreset[] rx_digitalreset[] rx_seriallpbken[]
(1)
pll_inclk[]
Buit-In Self Test
(BIST)
tx_dataout rx_bisterr
(2)
rx_bistdone
(2)
Notes to
(1) rx_seriallpbken[]
is required in PRBS.
(2) rx_bisterr[]
and rx_bistdone[] are only available in PRBS and BIST modes.
Figure 1–63 shows the PRBS blocks with loopback used in the transceiver
channel.
Figure 1–63. PRBS Blocks With Loopback in Transceiver Channel
Transmitter Digital Logic
BIST
Incremental
Generator
BIST
PRBS
Generator
TX Phase
Compensation
FIFO
Byte
Serializer
20
8B/10B
Encoder
FPGA
Logic
Array
BIST
Incremental
Verify
RX Phase
Compensation
FIFO
Byte
Deserializer
8B/10B
Decoder
Rate
Match
FIFO
Analog Receiver and
Transmitter Logic
Serializer
Serial
Loopback
Deskew
FIFO
BIST
PRBS
Verify
Word
Aligner
Deserializer
Clock
Recovery
Unit
Receiver Digital Logic
BIST in Basic Mode
Basic mode supports PRBS10 pattern generation and verification. PRBS10 is supported with or without serial loopback.
1
The PRBS10 pattern is only available when the SERDES factor is
10 bits.
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shows the BIST patterns for Basic mode.
Table 1–11. Available BIST Patterns in Basic Mode
Pattern
PRBS10
Word Aligner
Alignment Pattern
Byte Order Align
Pattern
10’h3FF N/A
Description
X
10
+ X
7
+ 1
8 Bit
—
Basic Mode
10 Bit
v
PRBS10
Pseudo-Random Bit Sequences (PRBS) are commonly used in systems to verify the integrity and robustness of the data transmission paths. When the SERDES factor is 10, use the PRBS10 pattern. The PRBS generator yields 2^10-1 unique patterns. You can use PRBS with or without serial loopback. In PRBS/ serial loopback mode, the rx_seriallpbken signal is available. In the PRBS/no loopback mode, this control signal is not available.
You enable PRBS mode in the Quartus II ALT2GXB MegaWizard Plug-In
Manager. PRBS10 does not use the 8B/10B encoder and decoder. The
8B/10B encoder and decoder are bypassed automatically in the PRBS mode.
The advantage of using a PRBS data stream is that the randomness yields an environment that stresses the transmission medium. In the data stream, you can observe both random jitter and deterministic jitter using a time interval analyzer, bit error rate tester, or oscilloscope.
The PRBS verifier can provide a quick check through the non-8B/10B path of the transceiver block. The PRBS verifier is active once the receiver channel is synchronized. Set the alignment pattern to 10'h3FF for the
10-bit SERDES modes.
The verifier stops checking the patterns after receiving all the PRBS patterns (1023 patterns for 10-bit mode). The rx_bistdone signal goes high, indicating that the verifier has completed. If the verifier detects an error before it is finished, rx_bisterr pulses high for the time the data is incorrect. Use the rx_digitalreset signal to re-start the PRBS verification.
The 8B/10B encoder is enabled, so the data stream is DC balanced.
8B/10B encoding guarantees a run length of less than 5 UI, which yields a less stressful pattern versus the PRBS data. However, since the PRBS generator bypasses the 8B/10B paths, the incremental BIST can test this path.
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Calibration
Blocks
The Arria GX gigabit transceiver block contains calibration circuits to calibrate the on-chip termination, the PLLs, and the output buffers. The calibration circuits are divided into two main blocks: the PLL and output buffer calibration block and the termination resistor calibration block
(refer to
Figure 1–64 ). Each transceiver block contains a PLL and output
buffer calibration block that calibrates the PLLs and output buffers within that particular transceiver block. Each device contains one termination resistor calibration block that calibrates all the termination resistors in the transceiver channels of the entire device.
Figure 1–64. Calibration Block
rref
PLL and Output
Buffer Calibration Block cal_blk_powerdown calibration_clk
Reference
Signal
Termination Resistor
Calibration Block
PLL and Output Buffer Calibration Block
Each Arria GX transceiver block contains a PLL and output buffer calibration circuit to counter the effects of PVT (process, voltage, and temperature) on the PLL and output buffer. Each transceiver block's calibration circuit uses a voltage reference derived from an external reference resistor. There is one reference resistor required for each active transceiver block in Arria GX devices. Unused transceiver blocks (except the transceiver blocks feeding the termination resistor calibration block) can be left unconnected or be tied to the 3.3 V transceiver analog V
CC
(if the transceiver block’s 3.3 V analog supply is connected to 3.3 V).
Termination Resistor Calibration Block
The Arria GX transceiver's on-chip termination resistors in the transceiver channels of the entire device are calibrated by a single calibration block. This block ensures that process, voltage, and temperature variations do not have an impact on the termination resistor value. There is only one termination resistor calibration block per device.
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May 2008
Calibration Blocks
The calibration block uses the reference resistor of transceiver block 0 or transceiver block 1, depending on the device and package. The calibration block uses the reference resistor in transceiver block 0 for EP1AGX20/35 and EP1AGX50/60 devices (except in the F484 package). The reference resistor in transceiver block 1 is used for EP1AGX20/35 and
EP1AGX50/60 devices in the F484 package, and for the EP1AGX90 device. A reference resistor must be connected to either transceiver block
0 or transceiver block 1 to ensure proper operation of the calibration block, whether or not the transceiver block is in use. Failing to connect the reference resistor of the transceiver block feeding the calibration block results in incorrect termination values for all the termination resistors in the transceivers of the entire device.
The termination resistor calibration circuit requires a calibration clock.
You can use a global clock line if the REFCLK pins are used for the reference clock. You can instantiate a calibration clock port in the
MegaWizard Plug-In Manager to supply your own clock through the cal_blk_clk
port.
The frequency range of the cal_blk_clk is 10 MHz to 125 MHz. If there are no slow speed clocks available, use a divide down circuit (for example, a ripple counter) to divide the available clock to a frequency in that range. The quality of the calibration clock is not an issue, so PLD local routing is sufficient to route the calibration clock.
For multiple ALT2GXB instances in the same device, if all the instances are the same, the calibration block must be active and the cal_blk_clk port of all instances must be tied to a common clock. Physically, there is one cal_blk_clk port per device. The Quartus II software provides an error message if the cal_blk_clk port is tied to different clock sources, because this would be impossible to fit into a device. If there are different configurations of the ALT2GXB instance, only one must have the calibration block instantiated. If multiple instances of the ALT2GXB custom megafunction variation have the calibration block instantiated, then all the cal_blk_clk ports must be tied to the same clock source.
The calibration block can be powered down through the optional cal_blk_powerdown
port (this is an active low input). Powering down the calibration block during operations may yield transmit and receive data errors. Only use this port to reset the calibration block to initiate a recalibration of the termination resistors to account for variations in temperature or voltage. The minimum pulse duration for this port is determined by characterization. If external termination is used on all signals, the calibration block in ALT2GXB need not be used.
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Referenced
Documents
This chapter references the following documents:
■
■
Arria GX Transceiver Protocol Support and Additional Features
Specifications and Additional Information
1–84
Arria GX Device Handbook, Volume 1 May 2008
Document Revision History
Document
Revision History
Table 1–12 shows the revision history for this chapter.
Table 1–12. Document Revision History
Date and Document
Version
May 2008, v2.0
August 2007, v1.2
June 2007 v1.1
May 2007 v1.0
Changes Made
●
●
Added sections
“Transmitter PLL Bandwidth Setting” ,
,
,
Clock Distribution” , “Individual Channels Clocking” ,
“Transmitter Clocking (Bonded Channels)”
,
Termination” , “PCI Express Receiver Detect”
,
,
“Signal Threshold Detection Circuit” ,
“Receiver Common Mode” , “Programmable
,
,
“Synchronization State Machine Mode” ,
, “Basic Mode General Rate Matching”
,
,
“Reverse Serial Pre-CDR Loopback” ,
,
Blocks” , “PLL and Output Buffer Calibration Block”
, and
“Termination Resistor Calibration Block”
Updated sections
,
“Dedicated Reference Clock Input Pins” ,
,
Detection” , “Disparity Error Detection”
,
“Receiver Phase Compensation FIFO
Added the
section.
Minor text edits.
Added GIGE information.
Initial release.
Summary of Changes
Major update. Addition of new material.
—
—
—
—
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May 2008
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Arria GX Device Handbook, Volume 1
Arria GX Transceiver Architecture
1–86
Arria GX Device Handbook, Volume 1 May 2008
2. Arria GX Transceiver
Protocol Support and
Additional Features
AGX52002-2.0
Introduction
Arria™ GX transceivers have a dedicated physical coding sublayer (PCS) and physical media attachment (PMA) circuitry to support PCI Express
(PIPE), Gigabit Ethernet (GIGE), and Serial RapidIO
®
protocols.
lists the Arria GX transceiver datapath modules employed in each mode.
Table 2–1. Arria GX Transceiver Datapath Modules
Functional
Mode
PCI Express
(PIPE)
GIGE
Serial
RapidIO
(1.25Gbps)
Serial
RapidIO
(2.5Gbps)
Serial
RapidIO
(3.125Gbps)
SDI - HD
(1.483Gbps)
SDI - HD
(1.485Gbps)
SDI - 3G
(2.967Gbps)
SDI - 3G
(2.97Gbps)
XAUI
(3.125Gbps)
Transmitter
/Receiver
Phase
Compensation
FIFO
v
Byte
Serializer/
Deserializer
v v v v v v v v v v
— v v v
—
—
—
— v
8B/10B
Encoder/
Decoder
Word
Aligner
Rate
Matcher
v v v v v
—
—
—
— v v v v v v
Bit-Slip
Bit-Slip
Bit-Slip
Bit-Slip v v
v
—
—
—
—
—
—
— v
PLD-
Transceiver
Interface
Width (bits)
16
8
16
16
16
10/20
10/20
20
20
16
(1) The rate matcher can be bypassed in low-latency (synchronous) PCI Express (PIPE) mode.
PLD-
Transceiver
Interface
Frequency
(MHz)
125
PCS
Frequency
(MHz)
250
125
62.5
125
156.25
148.3
148.5
148.35
148.5
156.25
125
125
250
312.5
148.3/296.
6
148.5/297
296.7
297
312.5
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Arria GX Transceiver Protocol Support and Additional Features
PCI Express
(PIPE) Mode
f
PCI Express is an evolution of peripheral component interconnect (PCI).
PCI is bandwidth-limited for today’s applications because it relies on synchronous single-ended type signaling with a wide multi-drop data bus. Clock and data-trace matching is required with PCI. PCI Express uses differential serial signaling with an embedded clock to enable an effective data rate of 2 Gbps per lane to overcome the limitations of PCI.
Arria GX transceivers support ×1 (single-lane) and ×4 (four-lane) link widths when configured in PCI Express (PIPE) mode. The Arria GX family supports up to twelve duplex (transmitter and receiver) ×1 links and up to three ×4 links per device. Transceiver channels configured in ×4
PCI Express (PIPE) mode must be physically located in the same transceiver block with logical Lane 0 assigned to physical Channel 0, logical Lane 1 assigned to physical Channel 1 and so on.
In addition to providing the transceiver PCS and PMA circuitry, Arria GX transceivers support the following protocol-specific features:
■
■
■
■
■
■
1
PCI Express synchronization state machine
Receiver detection
Electrical idle generation/detection
Beacon transmission
Polarity inversion
Power state management
This section is organized into transmitter and receiver data path modules when configured for PCI Express (PIPE) mode. The description for each module only covers details specific to PCI
Express (PIPE) functional mode support. Familiarity of PCI
Express protocol and PCI Express (PIPE) specifications is assumed.
For a general description of each module, refer to the
Arria GX
Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook.
PCI Express (PIPE) Mode Transmitter Architecture
This section lists sub-blocks within the transmitter channel configured in
PCI Express (PIPE) mode ( Figure 2–1 ). The sub-blocks are described in
order from the PLD transceiver parallel interface to the serial transmitter buffer.
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PCI Express (PIPE) Mode
Figure 2–1. PCI Express (PIPE) Transmitter Architecture
PLD
Logic
Array
PIPE
Interface
TX Phase
Compensation
FIFO
Byte
Serializer
8B/10B
Encoder
Transmitter PCS Transmitter PMA
Serializer
CMU
Reference
Clock f
Clock Multiplier Unit
The clock multiplier unit (CMU) takes in a reference clock and synthesizes the clocks that are used to clock the transmitter digital logic
(PCS), the serializer, and the PLD-transceiver interface.
For more details about CMU architecture, refer to the Clock Multiplier
Unit section in the
Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device Handbook.
■
■
In ×1 PCI Express (PIPE) mode, the CMU block consists of the following components:
Transmitter PLL that generates high-speed serial clock for the serializer
Local clock divider block that generates low-speed parallel clock for transmitter digital logic and PLD-transceiver interface
■
■
In ×4 PCI Express (PIPE) mode, the CMU block consists of the following components:
Transmitter PLL that generates high-speed serial clock for the serializer
Central clock divider block that generates low-speed parallel clock for transmitter digital logic and PLD-transceiver interface of each channel in the transceiver block
Input Reference Clock
In PCI Express (PIPE) mode, the only supported input reference clock frequency is 100 MHz.
The reference clock input to the transmitter PLL can be derived from the following pins:
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Arria GX Transceiver Protocol Support and Additional Features
■
■
1
One of the two available dedicated reference clock input pins
(REFCLK0 or REFCLK1) of the associated transceiver block
Inter-transceiver block lines driven by reference clock input pins of other transceiver blocks
Altera recommends using the dedicated reference clock input pins (REFCLK0 or REFCLK1) to provide a reference clock for the transmitter PLL.
specifies the input reference clock options available in PCI
Express (PIPE) mode.
Table 2–2. PCI Express (PIPE) Mode Input Reference Clock Specifications
Frequency
100 MHz
I/O Standard
1.2V PCML, 1.5V PCML, 3.3V PCML, Differential LVPECL, LVDS
HCSL
Coupling
AC
Termination
On-chip
Off-chip
Notes to
:
(1) In PCI Express (PIPE) mode, you have the option of selecting the HCSL standard for the reference clock if compliance to PCI Express is required. The Quartus
®
II software automatically selects DC coupling with external termination for the signal if configured as HCSL.
(2) Refer to
Figure 2–2 for an example termination scheme.
shows an example termination scheme for the reference clock signal when configured as HCSL.
Figure 2–2. DC Coupling and External Termination Scheme for PCI Express Reference Clock
Rs
(1)
Arria GX
REFCLK +
PCI Express
(HCSL)
REFCLK
Source
Rs
(1)
REFCLK -
Rp
=
50
Ω
Rp
=
50
Ω
:
(1) Select resistor values as recommended by the PCI Express clock source vendor.
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PCI Express (PIPE) Mode
Clock Synthesis
In PCI Express (PIPE) mode, the reference clock pre-divider divides the
100-MHz input reference clock by two. The resulting 50-MHz clock is fed to the transmitter PLL. Because the transmitter PLL implements a half-rate VCO, it multiplies the 50 MHz input clock by 25 to generate a
1250-MHz high-speed serial clock. This high-speed serial clock feeds the central clock divider and four local clock dividers of the transceiver block.
In ×4 PCI Express (PIPE) mode, the central clock divider in the transceiver block divides the 1250-MHz clock from the transmitter PLL by five to generate a 250-MHz parallel clock. This low-speed parallel clock output from the central clock divider block is used to clock the transmitter digital logic (PCS) in all channels of the transceiver block. The central clock divider block also forwards the high-speed serial clock from the transmitter PLL to the serializer within each channel. Because all four channels in the transceiver block are clocked with the same clock, the channel-to-channel skew is minimized.
In ×1 PCI Express (PIPE) mode, the local clock divider in each channel of the transceiver block divides the 1250-MHz clock from the transmitter
PLL by five to generate a 250-MHz parallel clock. This low-speed parallel clock output from the local clock divider block is used to clock the transmitter digital logic (PCS) of the associated channel. The local clock divider block also forwards the high-speed serial clock from the transmitter PLL to the serializer within its associated channel.
1
The Quartus II software automatically selects the appropriate transmitter PLL bandwidth suited for the PCI Express (PIPE) data rate.
shows the CMU implemented in PCI Express (PIPE) mode.
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Arria GX Transceiver Protocol Support and Additional Features
Figure 2–3. PCI Express (PIPE) Mode CMU
CMU Block
Transmitter Channels [3:2]
1250 MHz
Local Clock
TX Clock
Reference
Clock
100 MHz
/2 pre-divider
50 MHz
Transmitter
PLL
(x25)
1250 MHz
Central Clock
Divider Block
(/5)
1250 MHz
Transmitter Channels [1:0]
Local Clock
TX Clock
Gen Block
Transmitter High-Speed
Serial (1250 MHz) and
Low-Speed Parallel (250 MHz)
Clock
Transmitter High-Speed
Serial (1250 MHz) and
Low-Speed Parallel (250 MHz)
Clocks f
Transmitter Phase Compensation FIFO Buffer
The transmitter phase compensation FIFO buffer compensates for the phase difference between the PLD clock that clocks in parallel data into the transmitter and the PCS clock that clocks the rest of the transmitter digital logic.
Refer to the Transmitter Phase Compensation FIFO section in the
Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX
Device Handbook for more details about transmitter phase compensation
FIFO buffer architecture.
In PCI Express (PIPE) mode, the 250-MHz clock generated by the CMU clock divider block is divided by two. The resulting 125-MHz clock is used to clock the read port of the FIFO buffer. This 125-MHz clock is also forwarded to the PLD logic array (on the tx_clkout port in ×1 PCI
Express (PIPE) mode or the coreclkout port in ×4 PCI Express (PIPE) mode). If the tx_coreclk port is not instantiated, the clock signal on the tx_clkout
port of channel 0 is routed back to clock the write side of the transmitter phase compensation FIFO buffer in all channels with the transceiver block. The 16-bit PLD-transceiver interface clocked at
125-MHz results in an effective PCI Express (PIPE) data rate of 2 Gbps.
In PCI Express (PIPE) mode, the transmitter phase compensation FIFO is eight words deep. The latency through the FIFO is three to four
PLD-transceiver interface clock cycles.
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PCI Express (PIPE) Mode
shows the block diagram of transmitter phase compensation
FIFO in PCI Express (PIPE) mode.
Figure 2–4. TX Phase Compensation FIFO in PCI Express (PIPE) Mode
Transmitter Channel tx_datain[15:0]
From
PLD
Transmitter
Phase
Compensation
FIFO wrclk rdclk dataout[15:0]
To Byte Serializer tx_coreclk
125 MHz
125 MHz
/2
250 MHz
CMU
Local/Central Clock
Divider Block tx_clkout or coreclkout f
Byte Serializer
In PCI Express (PIPE) mode, the PLD-transceiver interface data is 16-bits wide and is clocked into the transmitter phase compensation FIFO at
125 MHz. The byte serializer clocks in the 16-bit wide data from the transmitter phase compensation FIFO at 125 MHz and clocks out 8-bit data to the 8B/10B encoder at 250 MHz. This allows clocking the
PLD-transceiver interface at half the speed.
For more details about byte serializer architecture, refer to the Byte
Serializer section in the
Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device Handbook.
The write port of the byte serializer is clocked by the divide-by-two version of the low-speed parallel clock from the CMU. The read port is clocked by the low-speed parallel clock from the CMU. The byte serializer clocks out the least significant byte (LSByte) of the 16-bit data first and the most significant byte (MSByte) last.
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Arria GX Transceiver Protocol Support and Additional Features
shows the block diagram of the byte serializer in PCI Express
(PIPE) mode.
Figure 2–5. Byte Serializer in PCI Express (PIPE) Mode
datain
From Transmitter
Phase Compensation
FIFO
125 MHz
Byte Serializer wrclk rdclk
250 MHz
To 8B/10B
Encoder dataout
125 MHz
Divide-by-Two
Version of
Low-Speed
Parallel Clock
/2
250 MHz
Low-Speed
Parallel Clock
CMU
Local/Central Clock
Divider Block f
8B/10B Encoder
In PCI Express (PIPE) mode, the 8B/10B encoder clocks in 8-bit data and
1-bit control identifier from the byte serializer and generates 10-bit encoded data. The 10-bit encoded data is fed to the serializer.
For more details about the 8B/10B encoder functionality, refer to the
8B/10B Encoder section in the
Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device Handbook.
Compliance Pattern Transmission Support
PCI Express has an option to transmit a compliance pattern for testing purposes. The compliance pattern must be transmitted beginning with a negative disparity. In PCI Express (PIPE) mode, you set the negative disparity with the tx_forcedispcompliance port.
Asserting the tx_forcedispcompliance port sets the LSByte of the
16-bit PLD-transmitter interface data to be encoded with a negative disparity. The tx_forcedispcompliance port must be de-asserted after the first word of the compliance pattern is clocked into the transceiver.
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Arria GX Device Handbook, Volume 2 May 2008
PCI Express (PIPE) Mode
f
1
The compliance pattern generator is not part of the Arria GX transceiver and must be designed using the PLD logic. This feature allows you to begin the compliance pattern only with a negative disparity.
Serializer
In PCI Express (PIPE) mode, the 10-bit encoded data from the 8B/10B encoder is clocked into the 10:1 serializer with the low-speed parallel clock at 250 MHz. The 10-bit data is clocked out of the serializer LSByte to
MSByte at both edges of the high-speed serial clock at 1250 MHz. The resulting 2.5 Gbps serial data output of the serializer is fed into the transmitter output buffer.
Refer to the Serializer section in the Arria GX Transceiver Architecture chapter in volume 2 of the Arria GX Device Handbook for more details about the serializer architecture.
Transmitter Buffer
shows the transmitter buffer settings when configured in PCI
Express (PIPE) mode.
Table 2–3. Transmitter Buffer Settings in PCI Express (PIPE) Mode
Settings
I/O Standard
Programmable Differential Output
Voltage (V
OD
)
Common Mode Voltage (V
CM
)
Differential Termination
Programmable Transmitter
Pre-Emphasis
V
CCH
(Transmitter Buffer Power)
1.2-V PCML
320-960 mV
600 mV
100
Ω
1.2 V
Value
Notes to
:
(1) The common mode voltage (V
CM
) is fixed in the MegaWizard
®
Plug-In Manager and cannot be changed.
(2) The I/O standard and differential termination settings are defaulted to 1.2-V
PCML and 100
Ω, respectively. If you select any other setting for the I/O standard or differential termination in the Assignment Editor, the Quartus II compiler will issue an error message.
(3) The transmitter buffer has five programmable first post-tap pre-emphasis settings.
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Arria GX Transceiver Protocol Support and Additional Features
Transmitter Electrical Idle
In PCI Express (PIPE) mode, you can force the transmitter into electrical idle condition during P0 and P2 power state by asserting the tx_forceelecidle
signal high. In electrical idle state, the transmitter buffer is tri-stated. The tx_forceelecidle signal must always be
asserted high in P0 and P1 power states. Refer to “Power State
for more details about PCI Express (PIPE) mode power states.
Receiver Detect
PCI Express Base Specification requires the transmitter to be capable of detecting a far-end receiver before beginning link training. Arria GX transceivers have dedicated receiver detect circuitry that is activated in
PCI Express (PIPE) mode.
The receiver detect circuitry is available only in the P1 power state, and is set through the tx_detectrxloopback port, and requires a 125 MHz fixedclk
signal. Refer to
“Power State Management” on page 2–22
for more details about PCI Express (PIPE) mode power states.
In P1 power state, the transmitter output buffer is tri-stated, because the transmitter is in electrical idle. A high on the tx_detectrxloopback port triggers the receiver detect circuitry to alter the transmitter buffer common mode voltage. The sudden change in common mode voltage appears as a step voltage at the tri-stated transmitter buffer output. If a receiver (that complies with PCI Express input impedance requirements) is present at the far end, the time constant of the step voltage is higher. If a receiver is not present or is powered down, the time constant of the step voltage is lower. The receiver detect circuitry snoops the transmitter buffer output for the time constant of the step voltage to detect the presence of the receiver at the far end.
A high pulse is driven on the pipephydonestatus port and 3'b011 is driven on the pipestatus port (refer to
“Receiver Status” on page 2–21 )
to indicate that a receiver has been detected. There is some latency after asserting the tx_detectrxloopback signal, before the receiver detection is indicated on the pipephydonestatus port.
1
The tx_forceelecidle port must be asserted at least 10 parallel clock cycles prior to the tx_detectrxloopback port to ensure that the transmitter buffer is tri-stated.
Beacon Transmission
The beacon is an optional 30-kHz to 500-MHz in-band signal that wakes the receiver from a P2 power state. This signal is optional; the Arria GX device does not have dedicated beacon transmission circuitry. The
Arria GX device supports the transmission of the beacon signal through
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Arria GX Device Handbook, Volume 2 May 2008
PCI Express (PIPE) Mode
a 10-bit encoded code group that has a five 1’s pulse (for example, K28.5)
(10'b0101111100). Because the beacon signal is a pulse that ranges from
2 ns to 500 ns, sending out a K28.5 at 2.5 Gbps meets the lower requirement with its five 1's pulse. (Though other 8B/10B code groups might meet the beacon requirement, this document uses the K28.5 control code group as the beacon signal.) The beacon transmission takes place only in the P2 power state. The tx_forceelecidle port controls when the transmitter is in Electrical Idle or not. This port must be de-asserted in order to transmit the K28.5 code group for beacon transmission.
PCI Express (PIPE) Mode Receiver Architecture
This section lists sub-blocks within the receiver channel configured in PCI
Express (PIPE) mode (
Figure 2–6 ). The sub-blocks are described in order
from the serial receiver input buffer to the receiver phase compensation
FIFO buffer at the transceiver-PLD interface.
Figure 2–6. PCI Express (PIPE) Mode Receiver Architecture
PLD
Logic
Array
PIPE
Interface
RX Phase
Compensation
FIFO
Byte
De-Serializer
8B/10B
Decoder
Rate
Match
FIFO
Receiver PCS
Word
Aligner
Receiver PMA
Clock
Recovery
Unit
De-
Serializer
Receiver
PLL
Reference
Clocks
Receiver Buffer
shows the receiver buffer settings when configured in PCI
Express (PIPE) mode.
Table 2–4. Receiver Buffer Settings in PCI Express (PIPE) Mode
(Part 1 of 2)
Settings Value
I/O Standard 1.2-V PCML, 1.5-V PCML,
3.3-V PCML, Differential LVPECL,
LVDS
Input Common Mode Voltage (Rx V
CM
Differential Termination 100
Ω
Programmable equalization
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Arria GX Transceiver Protocol Support and Additional Features
Table 2–4. Receiver Buffer Settings in PCI Express (PIPE) Mode
(Part 2 of 2)
Settings Value
Coupling AC
Notes to
:
(1) The common mode voltage (Rx V
CM
) is selectable in the MegaWizard
®
Plug-In
Manager.
(2) The differential termination setting is defaulted to 100
Ω. If you select any other setting for differential termination in the Assignment Editor, the Quartus II compiler issues an error message.
(3) The receiver buffer has five programmable equalization settings.
Signal Detect Threshold Circuitry
In PCI Express (PIPE) mode, the receiver buffer incorporates a signal detect threshold circuitry. The signal detect threshold circuitry senses whether the specified threshold voltage level exists at the receiver buffer.
This detector has a hysteresis response that filters out any high frequency ringing caused by inter symbol interference or high frequency losses in the transmission medium.
The rx_signaldetect signal indicates whether the signal at the receiver buffer conforms to the signal detection settings. A high level on the rx_signaldetect port indicates that the signal conforms to the settings and a low level indicates that the signal does not conform to the settings. The Quartus II software automatically defaults to the appropriate signal detect threshold based on the PCI Express electrical idle specifications.
Receiver PLL and Clock Recovery Unit (CRU)
In PCI Express (PIPE) mode, the receiver PLL in each transceiver channel is fed by a 100 MHz input reference clock. The receiver PLL in conjunction with the clock recovery unit generates two clocks: a high-speed serial recovered clock at 1250 MHz (half-rate VCO) that feeds the deserializer, and a low-speed parallel recovered clock at 250 MHz that feeds the receiver’s digital logic.
You can set the clock recovery unit in either automatic lock mode or manual lock mode. In automatic lock mode, the PPM detector and the phase detector within the receiver channel automatically switches the receiver PLL between lock-to-reference and lock-to-data modes. In manual lock mode, you can control the receiver PLL switch between lock-to-reference and lock-to-data modes via the rx_locktorefclk and rx_locktodata signals.
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PCI Express (PIPE) Mode
f f f
Refer to the Receiver PLL section in the
Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device Handbook for more details on the CRU lock modes.
■
■
The reference clock input to the receiver PLL can be derived from the following pins:
One of the two available dedicated reference clock input pins
(REFCLK0 or REFCLK1) of the associated transceiver block
Inter-transceiver block lines driven by reference clock input pins of other transceiver blocks
Deserializer
The 1:10 deserializer clocks in serial data from the receiver buffer using the high-speed recovered clock. The 10-bit deserialized data is clocked out to the word aligner using the low-speed recovered clock at 250 MHz.
The deserializer assumes that the transmission bit order is LSB to MSB; for example, the LSB of a data word is received earlier in time than its
MSB.
Refer to the Deserializer section in the Arria GX Transceiver Architecture chapter in volume 2 of the Arria GX Device Handbook for more details about the deserializer architecture.
Word Aligner
The word aligner clocks in the 10-bit data from the deserializer and restores the word boundary of the upstream transmitter. Besides restoring the word boundary, it also implements a synchronization state machine as specified in the PCI Express Base Specification to achieve lane synchronization.
Refer to the section “Word Aligner” on page 2–13 in the
Arria GX
Transceiver Architecture chapter in volume 2 of the Arria GX Device
Handbook for more details about the word aligner architecture.
■
■
■
In PCI Express (PIPE) mode, the word aligner consists of the following three modules:
Pattern detector module
Pattern aligner module
Run-length violation detector module
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Arria GX Transceiver Protocol Support and Additional Features
Pattern Detector
In PCI Express (PIPE) mode, the Quartus II software automatically configures 10-bit K28.5 (10'b0101111100) as the word alignment pattern.
After coming out of reset (rx_digitalreset), when the pattern detector detects either disparities of the K28.5 control word, it asserts the rx_patterndetect
signal for one parallel clock cycle. When the pattern aligner has aligned the incoming data to the desired word boundary, the pattern detector asserts the rx_patterndetect signal only if the word alignment pattern is found in the current word boundary.
Pattern Aligner
In PCI Express (PIPE) mode, the pattern aligner incorporates an automatic synchronization state machine. The Quartus II software automatically configures the synchronization state machine to indicate lane synchronization when the receiver receives four good /K28.5/ control code groups. Synchronization can be accomplished through the reception of four good PCI Express training sequences (TS1 or TS2) or four fast training sequences (FTS). Lane synchronization is indicated on the rx_syncstatus port of each channel. A high on the rx_syncstatus
port indicates that the lane is synchronized and a low indicates that it has fallen out of synchronization.
lists the synchronization state machine parameters when configured in PCI Express (PIPE) mode.
Table 2–5. Synchronization State Machine Parameters in PCI Express (PIPE)
Mode
4 Number of valid /K28.5/ code groups received to achieve synchronization (kcntr)
Number of errors received to lose synchronization (ecntr)
Number of continuous good code groups received to reduce the error count by 1 (gcntr)
17
16
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PCI Express (PIPE) Mode
shows a state diagram of the PCI Express (PIPE) synchronization.
Figure 2–7. PCI-Express (PIPE) Synchronization State Machine
Loss of Sync
Data = Comma
Data = !Valid
Comma Detect if Data == Comma kcntr++ else kcntr=kcntr kcntr = 3
Data = valid; kcntr <3 ecntr = 17
Synchronized
Data=Valid
Data = !Valid
Synchronized Error
Detect if Data == !valid
ecntr++ gcntr=0 else if gcntr==16 ecntr-gcntr=0 else gcntr++ ecntr = 0
2–7 list the TS1 and TS2 training sequences, respectively.
A PCI Express fast training sequence consists of a /K28.5/, followed by three /K28.1/ code groups.
Table 2–6. PCI Express TS1 Ordered Set (Part 1 of 2)
Symbol
Number
0
1
2
Allowed Values
—
0–255
0–31
Encoded Values Description
K28.5
Comma code group for symbol alignment
D0.0–D31.7, and K23.7
Link number with component
D0.0–D31.0, and K23.7
Lane number within port
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Table 2–6. PCI Express TS1 Ordered Set (Part 2 of 2)
Symbol
Number
3
Allowed Values
0–255
Encoded Values
4
5
2
Bit 0 = 0, 1
Bit 1 = 0, 1
Bit 2 = 0, 1
Bit 3 = 0, 1
Bit 4..7 = 0
Description
D0.0–D31.7
D2.0
D0.0, D1.0, D2.0, D4.0, and D8.0
N_FTS
. The number of fast training ordered sets required by the receiver to obtain reliable bit and symbol lock.
Data rate identifier
Bit 0–Reserved, set to 0
Bit 1 = 1, generation 1 (2.5Gbps) data rate supported
Bit 2..7–Reserved, set to 0
Training control
Bit 0 – Hot reset
Bit 0 = 0, de-assert
Bit 0 = 1, assert
6–15 — D10.2
Bit 1 – Disable link
Bit 1 = 0, de-assert
Bit 1 = 1, assert
Bit 1 – Loopback
Bit 2 = 0, de-assert
Bit 2 = 1, assert
Bit 3 – Disable scrambling
Bit 3 = 0, de-assert
Bit 3 = 1, assert
Bit 4..7 – Reserved
Bit 0 = 0, de-assert
Set to 0
TS1 identifier
Table 2–7. PCI Express TS2 Ordered Set (Part 1 of 2)
Symbol
Number
0
1
2
Allowed Values
—
0–255
0–31
Encoded Values Description
K28.5
Comma code group for symbol alignment.
D0.0–D31.7, and K23.7 Link number with component.
D0.0–D31.0, and K23.7 Lane number within port.
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PCI Express (PIPE) Mode
Table 2–7. PCI Express TS2 Ordered Set (Part 2 of 2)
Symbol
Number
3
Allowed Values
0–255
Encoded Values
4
5
2
Bit 0 = 0, 1
Bit 1 = 0, 1
Bit 2 = 0, 1
Bit 3 = 0, 1
Bit 4..7 = 0
Description
D0.0–D31.7
N_FTS . The number of fast training ordered sets required by the receiver to obtain reliable bit and symbol lock.
D2.0
Data rate identifier
Bit 0–Reserved, set to 0
Bit 1 = 1, generation 1 (2.5Gbps) data rate supported
Bit 2..7–Reserved, set to 0
D0.0, D1.0, D2.0, D4.0, and D8.0
Training control
Bit 0 – Hot reset
Bit 0 = 0, de-assert
Bit 0 = 1, assert
6–15 — D5.2
Bit 1 – Disable link
Bit 1 = 0, de-assert
Bit 1 = 1, assert
Bit 1 – Loopback
Bit 2 = 0, de-assert
Bit 2 = 1, assert
Bit 3 – Disable scrambling
Bit 3 = 0, de-assert
Bit 3 = 1, assert
Bit 4..7 – Reserved
Bit 0 = 0, de-assert
Set to 0
TS2 identifier
Rate Matcher
In PCI Express (PIPE) mode, the rate matcher can compensate up to
± 300 parts per million (PPM) (600 PPM total) frequency difference between the upstream transmitter and the receiver. In ×1 and ×4 PCI
Express (PIPE) mode, the write port of the rate matcher FIFO in each receiver channel is clocked by its low-speed parallel recovered clock. In
×1 PCI Express (PIPE) mode, the read port is clocked by the low-speed parallel clock output of the CMU local clock divider block. In ×4 PCI
Express (PIPE) mode, the read port is clocked by the low-speed parallel clock output of the CMU central clock divider block.
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
The rate matcher logic looks for skip ordered sets (SKP), which contains a /K28.5/ comma followed by three /K28.0/ skip characters. It deletes or inserts /K28.0/ skip characters as necessary from or to the rate matcher
FIFO. The rate matcher can delete only one skip character in a consecutive cluster of skip characters and can insert only one skip character per skip cluster.
shows an example of a PCI Express (PIPE) mode rate matcher deletion of two skip characters.
Figure 2–8. PCI Express (PIPE) Mode Rate Matcher Deletion
datain dataout
K28.5
K28.0
K28.0
K28.0
Dx.y
K28.5
K28.0
K28.0
K28.5
K28.0
K28.0
Dx.y
K28.5
K28.0
Dx.y
Dx.y
Two Skips Deleted
f
The rate matcher in PCI Express (PIPE) mode has FIFO buffer overflow and underflow protection. In the event of a FIFO buffer overflow, the rate matcher deletes any data after detecting the overflow condition to prevent FIFO pointer corruption until the rate matcher is not full. In an underflow condition, the rate matcher inserts 9'h1FE (/K30.7/) until the
FIFO buffer is not empty. These measures ensure that the FIFO buffer can gracefully exit the overflow/underflow condition without requiring a
FIFO reset. The rate matcher FIFO overflow and underflow condition is indicated on the pipestatus port.
8B/10B Decoder
In PCI Express (PIPE) mode, the 8B/10B decoder clocks in 10-bit data from the rate matcher and decodes it into 8-bit data + 1-bit control identifier. The 8-bit decoded data is fed to the byte deserializer.
For more details about the 8B/10B decoder functionality, refer to the
8B/10B Encoder section in the
Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device Handbook.
If the received 10-bit code is not a part of valid Dx.y or Kx.y code groups, the 8B/10B decoder block asserts an error flag on rx_errdetect port.
The 8B/10B decoder replaces the invalid code group with /K30.7/ code
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Arria GX Device Handbook, Volume 2 May 2008
PCI Express (PIPE) Mode
f
(8'hFE + 1'b1 after decoding). The error flag signal (rx_errdetect) has the same data path delay from the 8B/10B decoder to the PLD-transceiver interface as the invalid code group.
If the received 10-bit code is detected with incorrect running disparity, the
8B/10B decoder block asserts an error flag on the rx_disperr and rx_errdetect
ports. The error flag signal (rx_disperr) has the same delay from the 8B/10B decoder to the PLD-transceiver interface as the received data.
Polarity Inversion
The 8B/10B decoder supports the PCI Express (PIPE) compatible polarity inversion feature. This polarity inversion feature inverts the bits of the incoming data stream prior to the 8B/10B decoding block to fix accidental
P-N polarity inversion on the differential input buffer. You use the pipe8b10binvpolarity
port to invert the inputs to the 8B/10B decoder dynamically from the PLD.
1
You must not enable the receiver polarity inversion feature if you enable the PCI Express polarity inversion.
Byte Deserializer
In PCI Express (PIPE) mode, the PLD-receiver interface data is 16-bits wide and is clocked out of the receiver phase compensation FIFO at
125 MHz. The byte deserializer clocks in the 8-bit wide data from the
8B/10B decoder at 250 MHz and clocks out 16-bit wide data to the receiver phase compensation FIFO at 125 MHz. This allows clocking the
PLD-transceiver interface at half the speed.
For more details about byte deserializer architecture, refer to the Byte
Deserializer section in the
Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device Handbook.
In ×1 PCI Express (PIPE) mode, the write port of the byte deserializer is clocked by the low-speed parallel clock output from the CMU local clock divider block (tx_clkout) and the read port is clocked by divide-by-two version of this clock. In ×4 PCI Express (PIPE) mode, the write port of the byte deserializer is clocked by the low-speed parallel clock output from the CMU central clock divider block (coreclkout) and the read port is clocked by divide-by-two version of this clock.
Due to 8-bit to 16-bit byte deserialization, the byte ordering at the
PLD-receiver interface might be incorrect. You implement the byte ordering logic in the PLD core to correct for this situation.
Altera Corporation
May 2008
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Arria GX Transceiver Protocol Support and Additional Features
shows the block diagram of the byte serializer in PCI Express
(PIPE) mode.
Figure 2–9. Byte Deserializer in PCI Express (PIPE) Mode
datain[7:0]
From 8B/10B
Decoder wrclk
Byte
Deserializer rdclk dataout[15:0]
To Receiver Phase
Compensation
FIFO
125 MHz
250 MHz
Low-Speed Parallel CMU Clock
/2 f
Receiver Phase Compensation FIFO Buffer
The receiver phase compensation FIFO buffer compensates for the phase difference between the local receiver PLD clock and the receiver PCS clock.
For more details about receiver phase compensation FIFO buffer architecture, refer to the Receiver Phase Compensation FIFO Buffer section in the
Arria GX Transceiver Architecture
chapter in volume 2 of the
Arria GX Device Handbook.
In PCI Express (PIPE) mode, the 250-MHz clock generated by the CMU clock divider block is divided by two. The resulting 125-MHz clock is used to clock the write port of the FIFO buffer. This 125-MHz clock is also forwarded to the PLD logic array (on the tx_clkout port in ×1 PCI
Express (PIPE) mode or the coreclkout port in ×4 PCI Express (PIPE) mode). If the rx_coreclk port is not instantiated, the clock signal on the tx_clkout/coreclkout
port is routed back to clock the read side of the receiver phase compensation FIFO buffer. The 16-bit PLD-receiver interface, clocked at 125 MHz, results in an effective PCI Express (PIPE) data rate of 2 Gbps.
In PCI Express (PIPE) mode, the receiver phase compensation FIFO is eight words deep. The latency through the FIFO is two to three
PLD-transceiver interface clock cycles.
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PCI Express (PIPE) Mode
Figure 2–10 shows the block diagram of transmitter phase compensation
FIFO in PCI Express (PIPE) mode.
Figure 2–10. Receiver Phase Compensation FIFO in PCI Express (PIPE) Mode
Receiver Channel datain[15:0]
From Byte
Deserializer
125 MHz
Receiver Phase
Compensation
FIFO wrclk rdclk
125 MHz
Low-Speed
Parallel CMU Clock
250 MHz
/2 rx_dataout[15:0]
To PLD rx_coreclk tx_clkout or coreclkout
Altera Corporation
May 2008
Receiver Status
PCI Express (PIPE) specifies a receiver status indicator that reports the status of the PHY (PCS and PMA). In PCI Express (PIPE) mode, the receiver status is communicated to the PLD logic by the three-bit pipestatus
port. This port reports the status, as shown in
more than one event occurs at the same time, the signal is resolved with the higher priority status. The skip character added and removed flags
(3'b001 and 3'b010) are not supported. The pipestatus port may be encoded to 3b'001 and 3'b010, which should be ignored. It does not indicate that a skip has been added or removed and should be considered the same as 3'b000—received data. If the upper MAC layer must know when a skip character was added or removed, Altera recommends monitoring the number of skip characters received. The transmitter should send three skip characters in a standard skip-ordered set.
Table 2–8. pipestatus Description and Priority (Part 1 of 2)
pipestatus
3'b000
3'b001
3'b010
3'b011
3'b100
3'b101
Description
Received data
One skip character added (not supported)
One skip character removed (not supported)
Receiver detected
8B/10B decoder error
Elastic buffer overflow
Priority
6
N/A
N/A
1
2
3
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Arria GX Transceiver Protocol Support and Additional Features
Table 2–8. pipestatus Description and Priority (Part 2 of 2)
pipestatus
3'b110
3'b111
Description
Elastic buffer underflow
Received disparity error
Priority
4
5
Power State Management
The four supported power states in Arria GX when configured in PIPE mode are:
■
■
■
■
PO — normal power state
POs — low recovery time
P1 — lower than PO
P2 — lowest power state
There are four supported power states in Arria GX transceivers when configured in PIPE mode: P0, P0s, P1, and P2. P0 is the normal power state. P0s is a low recovery time power state that is lower than P0. P1 is a lower power state than P0s and has higher latency to come out of this state. P2 is the lowest power state.
The powerdn port transitions the transceiver into different power states.
The encoded value is shown in
Table 2–9 . The pipephydonestatus
signal reacts to the powerdn request and pulses high for one parallel clock cycle.
There are specific functions that are performed at each of the power states. The power-down states are for PCI Express (PIPE) emulation. The transceiver does not go into actual power saving mode, with the exception of the transmitter buffer for Electrical Idle.
shows each power state and its function.
Table 2–9. Power State Functions and Descriptions
Power State powerdn
P0 2'b00
P0s
P1
P2
2'b01
2'b10
2'b11
Function Description
Transmits normal data, transmits Electrical Idle, or enters into loopback mode.
Only transmits Electrical Idle.
Normal operation mode
Transmits Electrical Idle or a beacon to wake up the downstream receiver.
Low recovery time power saving state
Transmitter buffer is powered down and can do a receiver detect while in this state.
High recovery time power saving state
Lowest power saving state
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Altera Corporation
May 2008
PCI Express (PIPE) Mode
The two signals associated with the power states are: tx_detectrxloopback
and tx_forceelecidle. The tx_detectrxloopback
signal controls whether the channel goes into loopback when the power state is in P0 or receiver detect when in P1 state.
This signal does not have any affect in any other power states. The tx_forceelecidle
signal governs when the transmitter goes into an electrical idle state. The tx_forceelecidle signal is asserted in P0s and P1 states and de-asserted in P0 state. In P2 state, under normal conditions, the tx_forceelecidle signal is asserted and then de-asserted when the beacon signal must be sent out, signifying the intent to exit the P2 power-down state.
Table 2–10 shows the behavior of the tx_detectrxloopback and
tx_forceelecidle
signals in the power states.
Table 2–10. Power States and Functions Allowed in Each Power State
Power State
P0
P0s
P1
P2
tx_detectrxloopback
0: normal mode
1: data path in loopback mode
Don’t care
0: Electrical Idle
1: receiver detect
Don't care
tx_forceelecidle
0: Must be de-asserted.
1: Illegal mode
0: Illegal mode
1: Must be asserted in this state
0: Illegal mode
1: Must be asserted in this state
De-asserted in this state for sending beacon.
Otherwise asserted.
NFTS Fast Recovery IP (NFRI)
The PCI Express fast training sequences (FTS) are used for bit and byte synchronization to transition from P0s state to P0 state. The PCI Express standard specifies the required time period for this transition to be between 16 ns and 4
μs. The default PCI Express (PIPE) settings do not meet this requirement. You must enable the NFTS fast recovery IP (NFRI) for the receiver to transition from P0s to P0 within 4
μs by selecting the
Enable fast recovery mode
option in the MegaWizard Plug-In Manager.
PCI Express (PIPE) Mode Default Settings
In the PCI Express (PIPE) mode default settings (without NFRI enabled), the receiver PLL is in automatic lock mode. The PLL moves from lock-to-reference mode to lock-to-data mode based on the rx_freqlocked
being asserted. For the rx_freqlocked signal to be asserted, the CRU clock should be within the PPM threshold settings of the receiver PLL reference clock. The PPM detector checks the PPM
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Arria GX Transceiver Protocol Support and Additional Features
threshold settings by comparing the CRU PLL clock output with the reference clock for approximately 32768 clock cycles. For a 250 MHz PLD interface clock frequency, this comparison time period exceeds 4
μs, which violates the PCI Express specification.
The NFRI, if enabled, controls the rx_locktorefclk and rx_locktodata
signals to meet the 4
μs transition time from P0s to P0 power state.
1
If you select the rx_locktorefclk and rx_locktodata signals in the MegaWizard Plug-In Manager (CRU Manual Lock mode), the Enable fast recovery mode option cannot be selected.
■
■
■
When you select the Enable fast recovery mode option, you must consider the following:
NFRI is created in the PLD side for each PCI Express (PIPE) channel
NFRI is a soft IP, so it consumes logic resources
This block is self-contained, so no input/output ports are available to access the soft IP
Low-Latency (Synchronous) PCI Express (PIPE) Mode
The Arria GX receiver data path employs a rate match FIFO in PCI
Express (PIPE) mode to compensate up to ±300 PPM difference between the upstream transmitter and the local receiver reference clock. The low-latency (synchronous) PCI Express (PIPE) mode allows bypassing the rate match FIFO in synchronous systems that derive the transmitter and receiver reference clocks from the same source. You can bypass the rate match FIFO by not selecting the Enable Rate Match FIFO option in the ALT2GXB MegaWizard Plug-In Manager.
The rate match FIFO can be bypassed in both ×1 and ×4 PCI Express
(PIPE) modes. In normal PCI Express (PIPE) mode, the receiver blocks following the rate match FIFO are clocked by tx_clkout (×1 mode) or coreclkout
(×4 mode) of the local port. In low-latency (synchronous)
PCI Express (PIPE) mode, because the rate match FIFO is bypassed, these receiver blocks are clocked by the recovered clocks of the respective channels.
Except for the rate match FIFO being bypassed and the resulting changes in transceiver internal clocking, the low-latency (synchronous) PCI
Express (PIPE) mode shares the same data path and state machines as the normal PCI Express (PIPE) mode. However, some features supported in normal PCI Express (PIPE) mode are not supported in low-latency
(synchronous) PCI Express (PIPE) mode.
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Altera Corporation
May 2008
PCI Express (PIPE) Mode
PCI Express (PIPE) Reverse Parallel Loopback
In normal PCI Express (PIPE) mode, if the transceiver is in P0 power state, a high value on the tx_rxdetectloop signal forces a reverse parallel loopback, as discussed in PCI Express (PIPE) Reverse Parallel Loopback section. Parallel data at the output of the receiver rate match FIFO gets looped back to the input of the transmitter serializer.
In low-latency (synchronous) PCI Express (PIPE) mode, since the rate match FIFO is bypassed, this feature is not supported. A high value on the tx_rxdetectloop
signal when the transceiver is in P1 power state will not force it to perform reverse parallel loopback.
Link Width Negotiation
In normal ×4 PCI Express (PIPE) configuration, the receiver phase compensation FIFO control signals (write/read enable, and so forth) are shared among all lanes within the link. As a result, all lanes are truly bonded and the lane-lane skew meets the PCI Express specification.
In low-latency (synchronous) PCI Express (PIPE) configuration, the receiver phase compensation FIFO of individual lanes do not share control signals. The write port of the receiver phase compensation FIFO of each lane is clocked by its recovered clock. As a result, the lanes within a link are not bonded. You should perform external lane de-skewing to ensure proper link width negotiation.
Receiver Status
Because the rate match FIFO is bypassed in low-latency (synchronous)
PCI Express (PIPE) mode, status signal combinations related to the rate match FIFO on the pipestatus[2:0] port become irrelevant and must not be interpreted (
Table 2–11. pipestatus Signal (Part 1 of 2)
pipestatus[2:0]
000
001
010
011
100
101
Normal PIPE
Received Data OK
Not supported
Not supported
Receiver Detected
8B/10B Decoder Error
Elastic Buffer Overflow
Synchronous PIPE
Received Data OK
Not supported
Not supported
Receiver Detected
8B/10B Decoder Error
Not supported
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Table 2–11. pipestatus Signal (Part 2 of 2)
pipestatus[2:0]
110
111
Normal PIPE
Elastic Buffer Underflow
Received Disparity Error
Synchronous PIPE
Not supported
Received Disparity Error
Gigabit Ethernet
(GIGE) mode
■
■
■
IEEE 802.3 defines the 1000 Base-X PHY as an intermediate, or transition, layer that interfaces various physical media with the media access control
(MAC) in a gigabit ethernet system. It shields the MAC layer from the specific nature of the underlying medium. The 1000 Base-X PHY is divided into three sub-layers:
Physical coding sublayer (PCS)
Physical media attachment (PMA)
Physical medium dependent (PMD)
The PCS sublayer interfaces to the MAC through the gigabit medium independent interface (GMII). The 1000 Base-X PHY defines a physical interface data rate of 1 Gbps.
shows the 1000 Base-X PHY position in a Gigabit Ethernet
OSI reference model.
Figure 2–11. GIGE OSI Reference Model
OSI
Reference
Model Layers
Application
Presentation
Session
Transport
Network
Data Link
Physical
GMII
LAN
CSMA/CD Layers
Higher Layers
LLC
MAC (Optional)
MAC
Reconciliation
PCS
PMA
PMD
1000 Base-X
PHY
Medium
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Arria GX Device Handbook, Volume 2 May 2008
Gigabit Ethernet (GIGE) mode
f f
When Arria GX transceivers are configured in GIGE functional mode, they provide many of the PCS and PMA functions defined in the IEEE
802.3 specification; for example:
■
■
■
■
■
1
8B/10B encoding/decoding
Synchronization
Upstream transmitter and local receiver clock frequency compensation (rate matching)
Clock recovery from the encoded data forwarded by the receiver
PMD
Serialization/deserialization
Arria GX transceivers do not have built-in support for other PCS functions, such as auto-negotiation, collision-detect, and carrier-sense. If required, you must implement these functions in PLD logic array or external circuits.
For more information about additional features available in the Arria GX transceiver, refer to the GIGE-Enhanced sub-protocol in the
Arria GX
Megafunction User Guide
.
This section is organized into transmitter and receiver data path modules when configured for GIGE mode. The description for each module only covers details specific to GIGE functional mode support. This docuent assumes that you are familiar with the IEEE 802.3 Ethernet specification.
For a general description of each module, refer to the
Arria GX
Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook.
GIGE Mode Transmitter Architecture
This section lists sub-blocks within the transmitter channel configured in
). The sub-blocks are described in order from the
PLD-Transceiver parallel interface to the serial transmitter buffer.
Figure 2–12. GIGE Transmitter Architecture
PLD
Logic
Array
TX Phase
Compensation
FIFO
8B/10B
Encoder
Transmitter PCS Transmitter PMA
Serializer
CMU
Reference
Clock
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May 2008
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
f
Clock Multiplier Unit (CMU)
The clock multiplier unit takes in a reference clock and synthesizes the clocks that are used to clock the transmitter digital logic (PCS), the serializer, and the PLD-transceiver interface.
For more details about CMU architecture, refer to the Clock Multiplier
Unit section in the
Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device Handbook.
In GIGE mode, the CMU block consists of:
■
■
Transmitter PLL that generates high-speed serial clock for the serializer
Local clock divider block that generates low-speed parallel clock for transmitter digital logic and PLD-transceiver interface
Input Reference Clock
You can select either a 62.5 MHz or 125 MHz input reference clock frequency while configuring the transceiver in GIGE mode using the
Quartus II MegaWizard Plug-In Manager.
The reference clock input to the transmitter PLL can be derived from one of three components:
■
■
■
1
One of the two available dedicated reference clock input pins
(REFCLK0 or REFCLK1) of the associated transceiver block
PLD global clock network (must be driven directly from an input clock pin and cannot be driven by user logic or enhanced PLL)
Inter-transceiver block lines driven by reference clock input pins of other transceiver blocks
Altera recommends using the dedicated reference clock input pins (REFCLK0 or REFCLK1) to provide reference clock for the transmitter PLL.
The reference clock divide-by-two pre-divider is bypassed in GIGE mode.
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Gigabit Ethernet (GIGE) mode
Table 2–12 specifies the input reference clock options available in GIGE
mode.
Table 2–12. GIGE Mode Input Reference Clock Specification
Frequency
62.5 MHz
125 MHz
I/O Standard
1.2 V PCML,
1.5 V PCML,
3.3 V PCML, Differential LVPECL, LVDS
Coupling Termination
AC On-chip
Clock Synthesis
In GIGE mode, the input reference clock of 125 MHz (or 62.5 MHz) is fed to the transmitter PLL. Because the transmitter PLL implements a halfrate VCO, it multiplies the 125 MHz (or 62.5 MHz) input clock by 5 (or 10) to generate a 625 MHz high-speed serial clock. This high-speed serial clock feeds the local clock divider block in each GIGE channel instantiated within the transceiver block.
The local clock divider in each channel of the transceiver block divides the 625 MHz clock from the transmitter PLL by 5 to generate a 125 MHz parallel clock. This low-speed parallel clock output from the local clock divider block is used to clock the transmitter digital logic (PCS) of the associated channel. The local clock divider block also forwards the high-speed serial clock from the transmitter PLL to the serializer within its associated channel.
1
The Quartus II software automatically selects the appropriate transmitter PLL bandwidth suited for GIGE data rate.
Altera Corporation
May 2008
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Figure 2–13 shows the CMU implemented in GIGE mode.
Figure 2–13. GIGE Mode CMU
CMU Block
Transmitter Channels [3:2]
625 MHz
Transmitter High-Speed
Serial (625 MHz) and Low-Speed
Parallel (125 MHz) Clocks
Reference
Clock
125 MHz (62.5 MHz)
Transmitter
PLL x5 (x10)
625 MHz
625 MHz
Transmitter Channels [1:0]
Local Clock
TX Clock
Gen Block
Transmitter High-Speed
Serial (625 MHz) and Low-Speed
Parallel (125 MHz) Clocks f
Transmitter Phase Compensation FIFO Buffer
The transmitter phase compensation FIFO buffer compensates for the phase difference between the PLD clock that clocks in parallel data into the transmitter and the PCS clock that clocks the rest of the transmitter digital logic.
For more details about the transmitter phase compensation FIFO buffer architecture, refer to the Transmitter Phase Compensation FIFO Buffer section in the
Arria GX Transceiver Architecture
chapter in volume 2 of the
Arria GX Device Handbook.
In GIGE mode, the 125 MHz clock generated by the CMU local clock divider is used to clock the read port of the FIFO buffer. This 125 MHz clock is also forwarded to the PLD logic array (on the tx_clkout port).
If the tx_coreclk port is not instantiated, the clock signal on the tx_clkout
port is automatically routed back to clock the write side of the transmitter phase compensation FIFO buffer. The 8-bit
PLD-transceiver interface clocked at 125 MHz results into an effective
GIGE data rate of 1 Gbps.
In GIGE mode, the transmitter phase compensation FIFO is four words deep. The latency through the FIFO is two to three PLD-transceiver interface clock cycles.
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Gigabit Ethernet (GIGE) mode
Figure 2–14 shows the block diagram of transmitter phase compensation
FIFO in GIGE mode.
Figure 2–14. Transmitter Phase Compensation FIFO in GIGE Mode
Transmitter Channel tx_datain[7:0]
From
PLD tx_coreclk
125 MHz
Transmitter
Phase
Compensation
FIFO wrclk rdclk
125 MHz
To 8B/10B
Encoder dataout[7:0]
125 MHz
/2 tx_clkout
CMU
Local Clock Divider
Block f
8B/10B Encoder
In GIGE mode, the 8B/10B encoder clocks in 8-bit data and 1-bit control identifier from the transmitter phase compensation FIFO and generates a
10-bit encoded data. The 10-bit encoded data is fed to the serializer.
For more details about the 8B/10B encoder functionality, refer to the
8B/10B Encoder section in the
Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device Handbook.
GIGE Protocol — Ordered Sets and Special Code Groups
Table 2–13 lists ordered sets and special code groups used in the GIGE
functional mode.
Table 2–13. GIGE Ordered Sets (Part 1 of 2)
Code
Group
/C/
/C1/
/C2/
Ordered Set
Configuration
Configuration 1
Configuration 2
Number of
Code
Groups
—
4
4
Encoding
Alternating /C1/ and /C2/
/K28.5/D21.5/
Config_Reg
/K28.5/D2.2/
Config_Reg
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May 2008
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Table 2–13. GIGE Ordered Sets (Part 2 of 2)
Code
Group
Ordered Set
Number of
Code
Groups
—
Encoding
/I/
/I1/
/I2/
/R/
/S/
/T/
/V/
IDLE
IDLE 1
IDLE 2
Encapsulation
Carrier_Extend
Start_of_Packet
End_of_Packet
Error_Propagation
—
1
2
2
1
1
1
Correcting /I1/, Preserving
/I2/
/K28.5/D5.6
/K28.5/D16.2
—
/K23.7/
/K27.7/
/K29.7/
/K30.7/
(1) Two data code groups representing the Config_Reg value.
Idle Ordered-Set Generation
IEEE 802.3 requires the GIGE PHY to transmit idle ordered sets (/I/) continuously and repetitively whenever the GMII is idle. This ensures that the receiver maintains bit and word synchronization whenever there is no active data to be transmitted.
In GIGE functional mode, any /Dx.y/ following a /K28.5/ comma is replaced by the transmitter with either a /D5.6/ (/I1/ ordered set) or a
/D16.2/ (/I2/ ordered set), depending on the current running disparity.
The exception is when the data following the /K28.5/ is /D21.5/ (/C1/ ordered set) or /D2.2/ (/C2/) ordered set. If the running disparity before the /K28.5/ is positive, a /I1/ ordered set is generated. If the running disparity is negative, a /I2/ ordered set is generated. The disparity at the end of a /I1/ is the opposite of that at the beginning of the /I1/. The disparity at the end of a /I2/ is the same as the beginning running disparity (right before the idle code group). This ensures a negative running disparity at the end of an idle ordered set. A /Kx.y/ following a
/K28.5/ is not replaced.
Figure 2–15 shows the automatic idle ordered set generation. Note that
/D14.3/, /D24.0/, and /D15.8/ are replaced by /D5.6/ or /D16.2/ (for
/I1/, /I2/ ordered sets). /D21.5/ (part of the /C1/ order set) is not replaced.
2–32
Arria GX Device Handbook, Volume 2 May 2008
Gigabit Ethernet (GIGE) mode
Figure 2–15. Idle Ordered Set Generation in GIGE Mode
clock tx_datain [ ]
K28.5
D14.3
K28.5
D24.0
K28.5
D15.8
tx_dataout
Ordered Set
Dx.y
K28.5
/I1/
D5.6
K28.5
D21.5
Dx.y
K28.5
D16.2
K28.5
/I2/ /I2/
D16.2
K28.5
/C2/
D21.5
Reset Condition
After power-up or reset, the GIGE transmitter outputs three /K28.5/ commas before user data can be sent. This affects the synchronization ordered set transmission.
After reset (tx_digitalreset), the 8B/10B encoder automatically sends three /K28.5/ commas. Depending on when you start outputting the synchronization sequence, there could be an even or odd number of
/Dx.y/ sent as the transmitter before the synchronization sequence. The last of the three automatically sent /K28.5/and the first user-sent /Dx.y/ are treated as one idle ordered set. This can be a problem if there are an even number of /Dx.y/ transmitted before the start of the synchronization sequence.
Figure 2–16 shows an example of even numbers of /Dx.y/ between the
last automatically sent /K28.5/ and the first user-sent /K28.5/. The first user-sent ordered set is ignored, so three additional ordered sets are
required for proper synchronization. Figure 2–16
shows one don’t care data between the tx_digitalreset signal going low and the first of three automatic K28.5, but there could be more.
Figure 2–16. GIGE Synchronization Ordered Set Considerations After Reset
clock tx_digitalreset tx_dataout
K28.5
xxx
K28.5
K28.5
K28.5
Dx.y
Dx.y
K28.5