Arria GX Device Handbook

Arria GX Device Handbook
Arria GX Device Handbook,
Volume 1
101 Innovation Drive
San Jose, CA 95134
www.altera.com
Software Version:
Document Version:
Document Date:
9.1
2.0
© December 2009
Copyright © 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and service marks of Altera Corporation in the U.S. and other
countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of its semiconductor products to current specifications in accordance with Altera's standard warranty,
but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of
any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of
device specifications before relying on any published information and before placing orders for products or services.
AGX5V1-2.0
Contents
Chapter Revision Dates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .vii
Section I. Arria GX Device Data Sheet
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I-1
Chapter 1. Arria GX Device Family Overview
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Chapter 2. Arria GX Architecture
Transceivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Transmitter Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Clock Multiplier Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Transmitter Phase Compensation FIFO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
Byte Serializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
8B/10B Encoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Transmit State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Serializer (Parallel-to-Serial Converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
Transmitter Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
Receiver Path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Receiver Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Programmable Equalizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
Receiver PLL and Clock Recovery Unit (CRU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-12
Deserializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13
Word Aligner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Channel Aligner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Rate Matcher . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
8B/10B Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Receiver State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Byte Deserializer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Receiver Phase Compensation FIFO Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Loopback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Serial Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20
Reverse Serial Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21
Reverse Serial Pre-CDR Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
PCI Express (PIPE) Reverse Parallel Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22
Reset and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
Calibration Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
Transceiver Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
Transceiver Channel Clock Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24
PLD Clock Utilization by Transceiver Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26
Logic Array Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28
LAB Interconnects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29
LAB Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
iv
Contents
Adaptive Logic Modules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31
ALM Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34
Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35
Extended LUT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37
Arithmetic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38
Carry Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39
Shared Arithmetic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40
Shared Arithmetic Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41
Register Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42
Clear and Preset Logic Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43
MultiTrack Interconnect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44
TriMatrix Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48
M512 RAM Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49
M4K RAM Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51
M-RAM Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-53
Digital Signal Processing Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-58
Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62
DSP Block Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-62
PLLs and Clock Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-66
Global and Hierarchical Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-66
Global Clock Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-66
Regional Clock Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-67
Dual-Regional Clock Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-68
Combined Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-69
Clock Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-70
Enhanced and Fast PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-72
Enhanced PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-80
Fast PLLs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-80
I/O Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-81
Double Data Rate I/O Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-87
External RAM Interfacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-90
Programmable Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-91
Open-Drain Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-92
Bus Hold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-92
Programmable Pull-Up Resistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-93
Advanced I/O Standard Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-93
On-Chip Termination . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-95
On-Chip Differential Termination (R D OCT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-96
On-Chip Series Termination (RS OCT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-97
MultiVolt I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-97
High-Speed Differential I/O with DPA Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-99
Dedicated Circuitry with DPA Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-102
Fast PLL and Channel Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-104
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-105
Chapter 3. Configuration and Testing
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
IEEE Std. 1149.1 JTAG Boundary-Scan Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
SignalTap II Embedded Logic Analyzer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Contents
v
Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuration Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Configuration Data Decompression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Remote System Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuring Arria GX FPGAs with JRunner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Programming Serial Configuration Devices with SRunner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Configuring Arria GX FPGAs with the MicroBlaster Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Reconfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Automated Single Event Upset (SEU) Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Custom-Built Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3-3
3-4
3-5
3-6
3-6
3-7
3-7
3-7
3-7
3-8
3-8
3-8
3-9
Chapter 4. DC and Switching Characteristics
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Transceiver Block Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
I/O Standard Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15
Bus Hold Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
On-Chip Termination Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-24
Pin Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25
Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-25
I/O Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26
Preliminary, Correlated, and Final Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-26
I/O Timing Measurement Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-27
Clock Network Skew Adders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
Default Capacitive Loading of Different I/O Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-31
Typical Design Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
User I/O Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
EP1AGX20 I/O Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-32
EP1AGX35 I/O Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-41
EP1AGX50 I/O Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-50
EP1AGX60 I/O Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-59
EP1AGX90 I/O Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-68
Dedicated Clock Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-78
EP1AGX20 Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-78
EP1AGX35 Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-79
EP1AGX50 Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-81
EP1AGX60 Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-82
EP1AGX90 Clock Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-83
Block Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-84
IOE Programmable Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-86
Maximum Input and Output Clock Toggle Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-87
Duty Cycle Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-95
DCD Measurement Techniques . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-96
High-Speed I/O Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-100
PLL Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-103
External Memory Interface Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-105
JTAG Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-106
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-108
© December 2009 Altera Corporation
Arria GX Device Handbook, Volume 1
vi
Contents
Chapter 5. Reference and Ordering Information
Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Device Pin-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5-1
5-1
5-1
5-2
Additional Information
About this Handbook . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info-1
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info-1
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Info-1
Arria GX Device Handbook, Volume 1
© December 2009 Altera Corporation
Chapter Revision Dates
The chapters in this book, Arria GX Device Handbook, Volume 1, were revised on the
following dates. Where chapters or groups of chapters are available separately, part
numbers are listed.
Chapter 1
Arria GX Device Family Overview
Revised:
December 2009
Part Number: AGX51001-2.0
Chapter 2
Arria GX Architecture
Revised:
December 2009
Part Number: AGX51002-2.0
Chapter 3
Configuration and Testing
Revised:
December 2009
Part Number: AGX51003-2.0
Chapter 4
DC and Switching Characteristics
Revised:
December 2009
Part Number: AGX51004-2.0
Chapter 5
Reference and Ordering Information
Revised:
December 2009
Part Number: AGX51005-2.0
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
viii
Arria GX Device Handbook, Volume 1
Chapter Revision Dates
© December 2009
Altera Corporation
Section I. Arria GX Device Data Sheet
This section provides designers with the data sheet specifications for Arria® GX
devices. They contain feature definitions of the transceivers, internal architecture,
configuration, and JTAG boundary-scan testing information, DC operating
conditions, AC timing parameters, a reference to power consumption, and ordering
information for Arria GX devices.
This section includes the following chapters:
■
Chapter 1, Arria GX Device Family Overview
■
Chapter 2, Arria GX Architecture
■
Chapter 3, Configuration and Testing
■
Chapter 4, DC and Switching Characteristics
■
Chapter 5, Reference and Ordering Information
Revision History
Refer to each chapter for its own specific revision history. For information about when
each chapter was updated, refer to the Chapter Revision Dates section, which appears
in the full handbook.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
I–2
Section I: Arria GX Device Data Sheet
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
1. Arria GX Device Family Overview
AGX51001-2.0
Introduction
The Arria® GX family of devices combines 3.125 Gbps serial transceivers with reliable
packaging technology and a proven logic array. Arria GX devices include 4 to 12
high-speed transceiver channels, each incorporating clock data recovery (CDR)
technology and embedded SERDES circuitry designed to support PCI-Express,
Gigabit Ethernet, SDI, SerialLite II, XAUI, and Serial RapidIO protocols, along with
the ability to develop proprietary, serial-based IP using its Basic mode. The
transceivers build upon the success of the Stratix ® II GX family. The Arria GX FPGA
technology offers a 1.2-V logic array with the right level of performance and
dependability needed to support these mainstream protocols.
Features
The key features of Arria GX devices include:
■
© December 2009
Transceiver block features
■
High-speed serial transceiver channels with CDR support up to 3.125 Gbps.
■
Devices available with 4, 8, or 12 high-speed full-duplex serial transceiver
channels
■
Support for the following CDR-based bus standards—PCI Express, Gigabit
Ethernet, SDI, SerialLite II, XAUI, and Serial RapidIO, along with the ability to
develop proprietary, serial-based IP using its Basic mode
■
Individual transmitter and receiver channel power-down capability for
reduced power consumption during non-operation
■
1.2- and 1.5-V pseudo current mode logic (PCML) support on transmitter
output buffers
■
Receiver indicator for loss of signal (available only in PCI Express [PIPE]
mode)
■
Hot socketing feature for hot plug-in or hot swap and power sequencing
support without the use of external devices
■
Dedicated circuitry that is compliant with PIPE, XAUI, Gigabit Ethernet, Serial
Digital Interface (SDI), and Serial RapidIO
■
8B/10B encoder/decoder performs 8-bit to 10-bit encoding and 10-bit to 8-bit
decoding
■
Phase compensation FIFO buffer performs clock domain translation between
the transceiver block and the logic array
■
Channel aligner compliant with XAUI
Altera Corporation
Arria GX Device Handbook, Volume 1
1–2
Chapter 1: Arria GX Device Family Overview
Features
■
Main device features:
■
TriMatrix memory consisting of three RAM block sizes to implement true
dual-port memory and first-in first-out (FIFO) buffers with performance up to
380 MHz
■
Up to 16 global clock networks with up to 32 regional clock networks per
device
■
High-speed DSP blocks provide dedicated implementation of multipliers,
multiply-accumulate functions, and finite impulse response (FIR) filters
■
Up to four enhanced phase-locked loops (PLLs) per device provide spread
spectrum, programmable bandwidth, clock switch-over, and advanced
multiplication and phase shifting
■
Support for numerous single-ended and differential I/O standards
■
High-speed source-synchronous differential I/O support on up to 47 channels
■
Support for source-synchronous bus standards, including SPI-4 Phase 2
(POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1
■
Support for high-speed external memory including DDR and DDR2 SDRAM,
and SDR SDRAM
■
Support for multiple intellectual property megafunctions from Altera®
MegaCore® functions and Altera Megafunction Partners Program (AMPPSM )
■
Support for remote configuration updates
Table 1–1 lists Arria GX device features for FineLine BGA (FBGA) with flip chip
packages.
Table 1–1. Arria GX Device Features (Part 1 of 2)
EP1AGX20C
EP1AGX35C/D
EP1AGX50C/D
C
C
EP1AGX60C/D/E
EP1AGX90E
Feature
C
Package
484-pin,
780-pin
(Flip chip)
D
D
484-pin
780-pin
484-pin
780-pin,
(Flip chip)
(Flip chip)
(Flip chip)
1152-pin
C
484-pin
D
E
780-pin
1152-pin
(Flip chip) (Flip chip) (Flip chip)
E
1152-pin
(Flip chip)
(Flip chip)
ALMs
8,632
13,408
20,064
24,040
36,088
Equivalent
logic
elements
(LEs)
21,580
33,520
50,160
60,100
90,220
Transceiver
channels
4
Transceiver
data rate
Sourcesynchronous
receive
channels
600 Mbps
to 3.125
Gbps
31
Arria GX Device Handbook, Volume 1
4
8
600 Mbps to 3.125
Gbps
31
31
4
8
600 Mbps to 3.125
Gbps
31
31, 42
4
8
12
600 Mbps to 3.125 Gbps
31
31
© December 2009
12
600 Mbps
to 3.125
Gbps
42
Altera Corporation
47
Chapter 1: Arria GX Device Family Overview
Features
1–3
Table 1–1. Arria GX Device Features (Part 2 of 2)
EP1AGX20C
EP1AGX35C/D
EP1AGX50C/D
EP1AGX60C/D/E
EP1AGX90E
C
C
D
C
D
C
D
E
E
Sourcesynchronous
transmit
channels
29
29
29
29
29, 42
29
29
42
45
M512 RAM
blocks
(32 × 18 bits)
166
197
313
326
478
M4K RAM
blocks
(128 × 36
bits)
118
140
242
252
400
1
1
2
2
4
Total RAM
bits
1,229,184
1,348,416
2,475,072
2,528,640
4,477,824
Embedded
multipliers
(18 × 18)
40
56
104
128
176
DSP blocks
10
14
26
32
44
PLLs
4
4
Feature
M-RAM
blocks
(4096 × 144
bits)
Maximum
user I/O pins
230, 341
230
341
4
4, 8
4
229
350, 514
229
350
8
8
514
538
Arria GX devices are available in space-saving FBGA packages (refer to Table 1–2). All
Arria GX devices support vertical migration within the same package. With vertical
migration support, designers can migrate to devices whose dedicated pins,
configuration pins, and power pins are the same for a given package across device
densities. For I/O pin migration across densities, the designer must cross-reference
the available I/O pins with the device pin-outs for all planned densities of a given
package type to identify which I/O pins are migratable.
Table 1–2. Arria GX Package Options (Pin Counts and Transceiver Channels) (Part 1 of 2)
Source-Synchronous Channels
Maximum User I/O Pin Count
Transceiver
Channels
Receive
Transmit
484-Pin FBGA
(23 mm)
780-Pin FBGA
(29 mm)
1152-Pin
FBGA
(35 mm)
EP1AGX20C
4
31
29
230
341
—
EP1AGX35C
4
31
29
230
—
—
EP1AGX50C
4
31
29
229
—
—
EP1AGX60C
4
31
29
229
—
—
EP1AGX35D
8
31
29
—
341
—
EP1AGX50D
8
31, 42
29, 42
—
350
514
Device
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
1–4
Chapter 1: Arria GX Device Family Overview
Document Revision History
Table 1–2. Arria GX Package Options (Pin Counts and Transceiver Channels) (Part 2 of 2)
Source-Synchronous Channels
Maximum User I/O Pin Count
Transceiver
Channels
Receive
Transmit
484-Pin FBGA
(23 mm)
780-Pin FBGA
(29 mm)
1152-Pin
FBGA
(35 mm)
EP1AGX60D
8
31
29
—
350
—
EP1AGX60E
12
42
42
—
—
514
EP1AGX90E
12
47
45
—
—
538
Device
Table 1–3 lists the Arria GX device package sizes.
Table 1–3. Arria GX FBGA Package Sizes
Dimension
484 Pins
780 Pins
1152 Pins
Pitch (mm)
1.00
1.00
1.00
Area (mm2 )
529
841
1225
23 × 23
29 × 29
35 × 35
Length × width
(mm × mm)
Document Revision History
Table 1–4 lists the revision history for this chapter.
Table 1–4. Document Revision History
Date and Document Version
December 2009, v2.0
Changes Made
■
Document template update.
■
Minor text edits.
Summary of Changes
—
May 2008, v1.2
Included support for SDI,
SerialLite II, and XAUI.
—
June 2007, v1.1
Included GIGE information.
—
May 2007, v1.0
Initial Release
—
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
2. Arria GX Architecture
AGX51002-2.0
Transceivers
Arria® GX devices incorporate up to 12 high-speed serial transceiver channels that
build on the success of the Stratix ® II GX device family. Arria GX transceivers are
structured into full-duplex (transmitter and receiver) four-channel groups called
transceiver blocks located on the right side of the device. You can configure the
transceiver blocks to support the following serial connectivity protocols
(functional modes):
■
PCI Express (PIPE)
■
Gigabit Ethernet (GIGE)
■
XAUI
■
Basic (600 Mbps to 3.125 Gbps)
■
SDI (HD, 3G)
■
Serial RapidIO (1.25 Gbps, 2.5 Gbps, 3.125 Gbps)
Transceivers within each block are independent and have their own set of dividers.
Therefore, each transceiver can operate at different frequencies. Each block can select
from two reference clocks to provide two clock domains that each transceiver can
select from.
Table 2–1 lists the number of transceiver channels for each member of the Arria GX
family.
Table 2–1. Arria GX Transceiver Channels
© December 2009
Device
Number of Transceiver Channels
EP1AGX20C
4
EP1AGX35C
4
EP1AGX35D
8
EP1AGX50C
4
EP1AGX50D
8
EP1AGX60C
4
EP1AGX60D
8
EP1AGX60E
12
EP1AGX90E
12
Altera Corporation
Arria GX Device Handbook, Volume 1
2–2
Chapter 2: Arria GX Architecture
Transceivers
Figure 2–1 shows a high-level diagram of the transceiver block architecture divided
into four channels.
Figure 2–1. Transceiver Block
Transceiver Block
RX1
Channel 1
TX1
RX0
Channel 0
Arria GX
Logic Array
TX0
Supporting Blocks
(PLLs, State Machines,
Programming)
REFCLK_1
REFCLK_0
RX2
Channel 2
TX2
RX3
Channel 3
TX3
Each transceiver block has:
■
Four transceiver channels with dedicated physical coding sublayer (PCS) and
physical media attachment (PMA) circuitry
■
One transmitter PLL that takes in a reference clock and generates high-speed serial
clock depending on the functional mode
■
Four receiver PLLs and clock recovery unit (CRU) to recover clock and data from
the received serial data stream
■
State machines and other logic to implement special features required to support
each protocol
Figure 2–2 shows functional blocks that make up a transceiver channel.
Figure 2–2. Arria GX Transceiver Channel Block Diagram
PMA Analog Section
PCS Digital Section
n
Deserializer
(1)
Rate
Matcher
Clock
Recovery
Unit
Reference
Clock
Receiver
PLL
Reference
Clock
Transmitter
PLL
FPGA Fabric
Word
Aligner
XAUI
Lane
Deskew
8B/10B
Decoder
Byte
Deserializer
Phase
Compensation
FIFO Buffer
m
(2)
n
Serializer
(1)
8B/10B
Encoder
Byte
Serializer
Phase
Compensation
FIFO Buffer
m
(2)
Notes to Figure 2–2:
(1) “n” represents the number of bits in each word that must be serialized by the transmitter portion of the PMA.
n = 8 or 10.
(2) “m” represents the number of bits in the word that passes between the FPGA logic and the PCS portion of the transceiver. m = 8, 10, 16, or 20.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
Transceivers
2–3
Each transceiver channel is full-duplex and consists of a transmitter channel and a
receiver channel.
The transmitter channel contains the following sub-blocks:
■
Transmitter phase compensation first-in first-out (FIFO) buffer
■
Byte serializer (optional)
■
8B/10B encoder (optional)
■
Serializer (parallel-to-serial converter)
■
Transmitter differential output buffer
The receiver channel contains the following:
■
Receiver differential input buffer
■
Receiver lock detector and run length checker
■
CRU
■
Deserializer
■
Pattern detector
■
Word aligner
■
Lane deskew
■
Rate matcher (optional)
■
8B/10B decoder (optional)
■
Byte deserializer (optional)
■
Receiver phase compensation FIFO buffer
You can configure the transceiver channels to the desired functional modes using the
ALT2GXB MegaCore instance in the Quartus® II MegaWizard ™ Plug-in Manager for
the Arria GX device family. Depending on the selected functional mode, the
Quartus II software automatically configures the transceiver channels to employ a
subset of the sub-blocks listed above.
Transmitter Path
This section describes the data path through the Arria GX transmitter. The sub-blocks
are described in order from the PLD-transmitter parallel interface to the serial
transmitter buffer.
Clock Multiplier Unit
Each transceiver block has a clock multiplier unit (CMU) that takes in a reference
clock and synthesizes two clocks: a high-speed serial clock to serialize the data and a
low-speed parallel clock to clock the transmitter digital logic (PCS).
The CMU is further divided into three sub-blocks:
© December 2009
■
One transmitter PLL
■
One central clock divider block
■
Four local clock divider blocks (one per channel)
Altera Corporation
Arria GX Device Handbook, Volume 1
2–4
Chapter 2: Arria GX Architecture
Transceivers
Figure 2–3 shows the block diagram of the clock multiplier unit.
Figure 2–3. Clock Multiplier Unit
CMU Block
Transmitter High-Speed Serial
and Low-Speed Parallel Clocks
Transmitter Channels [3:2]
Local
Clock
TX Clock
Divider Block
Gen Block
Reference Clock
from REFCLKs,
Global Clock (1),
Inter-Transceiver
Lines
Central Clock
Divider
Block
Transmitter
PLL
Transmitter High-Speed Serial
and Low-Speed Parallel Clocks
Local
Clock
TX Clock
Divider Block
Gen Block
Transmitter Channels [1:0]
The transmitter PLL multiplies the input reference clock to generate the high-speed
serial clock required to support the intended protocol. It implements a half-rate
voltage controlled oscillator (VCO) that generates a clock at half the frequency of the
serial data rate for which it is configured.
Figure 2–4 shows the block diagram of the transmitter PLL.
Figure 2–4. Transmitter PLL
Transmitter PLL
/M
To
Inter-Transceiver Lines
Dedicated
REFCLK0
Dedicated
REFCLK1
/2
Phase
Frequency
INCLK Detector
/2
(1)
up
down
Charge
Pump + Loop
Filter
Voltage
Controlled
Oscillator
/L(1)
High Speed
Serial Clock
Inter-Transceiver Lines[2:0]
Global Clock (2)
Notes to Figure 2–4:
(1) You only need to select the protocol and the available input reference clock frequency in the ALTGXB MegaWizard Plug-In Manager. Based on your
selections, the MegaWizard Plug-In Manager automatically selects the necessary /M and /L dividers (clock multiplication factors).
(2) The global clock line must be driven from an input pin only.
The reference clock input to the transmitter PLL can be derived from:
■
One of two available dedicated reference clock input pins (REFCLK0 or REFCLK1)
of the associated transceiver block
■
PLD global clock network (must be driven directly from an input clock pin and
cannot be driven by user logic or enhanced PLL)
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
Transceivers
■
1
2–5
Inter-transceiver block lines driven by reference clock input pins of other
transceiver blocks
Altera® recommends using the dedicated reference clock input pins (REFCLK0 or
REFCLK1) to provide reference clock for the transmitter PLL.
Table 2–2 lists the adjustable parameters in the transmitter PLL.
Table 2–2. Transmitter PLL Specifications
Parameter
Specifications
Input reference frequency range
Data rate support
50 MHz to 622.08 MHz
600 Mbps to 3.125 Gbps
Bandwidth
Low, medium, or high
The transmitter PLL output feeds the central clock divider block and the local clock
divider blocks. These clock divider blocks divide the high-speed serial clock to
generate the low-speed parallel clock for the transceiver PCS logic and
PLD-transceiver interface clock.
Transmitter Phase Compensation FIFO Buffer
A transmitter phase compensation FIFO is located at each transmitter channel’s logic
array interface. It compensates for the phase difference between the transmitter PCS
clock and the local PLD clock. The transmitter phase compensation FIFO is used in all
supported functional modes. The transmitter phase compensation FIFO buffer is eight
words deep in PCI Express (PIPE) mode and four words deep in all other modes.
f
For more information about architecture and clocking, refer to the Arria GX Transceiver
Architecture chapter.
Byte Serializer
The byte serializer takes in two-byte wide data from the transmitter phase
compensation FIFO buffer and serializes it into a one-byte wide data at twice the
speed. The transmit data path after the byte serializer is 8 or 10 bits. This allows
clocking the PLD-transceiver interface at half the speed when compared with the
transmitter PCS logic. The byte serializer is bypassed in GIGE mode. After
serialization, the byte serializer transmits the least significant byte (LSByte) first and
the most significant byte (MSByte) last.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–6
Chapter 2: Arria GX Architecture
Transceivers
Figure 2–5 shows byte serializer input and output. datain[15:0] is the input to the
byte serializer from the transmitter phase compensation FIFO; dataout[7:0] is the
output of the byte serializer.
Figure 2–5. Byte Serializer Operation (Note 1)
D1
datain[15:0]
D2
{8'h00,8'h01}
{8'h02,8'h03}
D1LSByte
dataout[7:0]
xxxxxxxxxx
D3
8'h01
xxxxxxxxxx
xxxx
D1MSByte
8'h00
D2LSByte
D2MSByte
8'h03
8'h02
Note to Figure 2–5:
(1) datain may be 16 or 20 bits. dataout may be 8 or 10 bits.
8B/10B Encoder
The 8B/10B encoder block is used in all supported functional modes. The 8B/10B
encoder block takes in 8-bit data from the byte serializer or the transmitter phase
compensation FIFO buffer. It generates a 10-bit code group with proper running
disparity from the 8-bit character and a 1-bit control identifier (tx_ctrlenable).
When tx_ctrlenable is low, the 8-bit character is encoded as data code group
(Dx.y). When tx_ctrlenable is high, the 8-bit character is encoded as a control
code group (Kx.y). The 10-bit code group is fed to the serializer. The 8B/10B encoder
conforms to the IEEE 802.3 1998 edition standard.
f
For additional information regarding 8B/10B encoding rules, refer to the Specifications
and Additional Information chapter.
Figure 2–6 shows the 8B/10B conversion format.
Figure 2–6. 8B/10B Encoder
7
6
5
4
3
2
1
0
H
G
F
E
D
C
B
A
Ctrl
8B-10B Conversion
j
h
g
f
i
e
d
c
b
a
9
8
7
6
5
4
3
2
1
0
MSB
LSB
During reset (tx_digitalreset), the running disparity and data registers are
cleared and the 8B/10B encoder continously outputs a K28.5 pattern from the
RD-column. After out of reset, the 8B/10B encoder starts with a negative disparity
(RD-) and transmits three K28.5 code groups for synchronizing before it starts
encoding the input data or control character.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
Transceivers
2–7
Transmit State Machine
The transmit state machine operates in either PCI Express (PIPE) mode, XAUI mode,
or GIGE mode, depending on the protocol used.
GIGE Mode
In GIGE mode, the transmit state machine converts all idle ordered sets (/K28.5/,
/Dx.y/) to either /I1/ or /I2/ ordered sets. The /I1/ set consists of a negative-ending
disparity /K28.5/ (denoted by /K28.5/-), followed by a neutral /D5.6/. The /I2/ set
consists of a positive-ending disparity /K28.5/ (denoted by /K28.5/+) and a
negative-ending disparity /D16.2/ (denoted by /D16.2/-). The transmit state
machines do not convert any of the ordered sets to match /C1/ or /C2/, which are
the configuration ordered sets. (/C1/ and /C2/ are defined by [/K28.5/, /D21.5/]
and [/K28.5/, /D2.2/], respectively). Both the /I1/ and /I2/ ordered sets guarantee a
negative-ending disparity after each ordered set.
XAUI Mode
The transmit state machine translates the XAUI XGMII code group to the XAUI PCS
code group. Table 2–3 lists the code conversion.
Table 2–3. On-Chip Termination Support by I/O Banks
XGMII TXC
XGMII TXD
PCS Code-Group
Description
0
00 through FF
Dxx.y
Normal data
1
07
K28.0 or K28.3 or K28.5
Idle in ||I||
1
07
K28.5
Idle in ||T||
1
9C
K28.4
Sequence
1
FB
K27.7
Start
1
FD
K29.7
Terminate
1
FE
K30.7
Error
1
Refer to IEEE 802.3 reserved code
groups
Refer to IEEE 802.3 reserved code
groups
Reserved code groups
1
Other value
K30.7
Invalid XGMII character
The XAUI PCS idle code groups, /K28.0/ (/R/) and /K28.5/ (/K/), are automatically
randomized based on a PRBS7 pattern with an ×7 + ×6 + 1 polynomial. The /K28.3/
(/A/) code group is automatically generated between 16 and 31 idle code groups. The
idle randomization on the /A/, /K/, and /R/ code groups is automatically done by
the transmit state machine.
Serializer (Parallel-to-Serial Converter)
The serializer block clocks in 8- or 10-bit encoded data from the 8B/10B encoder using
the low-speed parallel clock and clocks out serial data using the high-speed serial
clock from the central or local clock divider blocks. The serializer feeds the data LSB to
MSB to the transmitter output buffer.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–8
Chapter 2: Arria GX Architecture
Transceivers
Figure 2–7 shows the serializer block diagram.
Figure 2–7. Serializer
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
10
From 8B/10B
Encoder
To Transmitter
Output Buffer
Low-speed parallel clock
CMU
Central /
Local Clock
High-speed serial clock
Divider
Transmitter Buffer
The Arria GX transceiver buffers support the 1.2- and 1.5-V PCML I/O standard at
rates up to 3.125 Gbps. The common mode voltage (VCM ) of the output driver may be
set to 600 or 700 mV.
f
For more information about the Arria GX transceiver buffers, refer to the Arria GX
Transceiver Architecture chapter.
The output buffer, as shown in Figure 2–8, is directly driven by the high-speed data
serializer and consists of a programmable output driver, a programmable
pre-emphasis circuit, and OCT circuitry.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
Transceivers
2–9
Figure 2–8. Output Buffer
Serializer
Output Buffer
Programmable
Pre-Emphasis
Output
Pins
Programmable
Output
Driver
Programmable Output Driver
The programmable output driver can be set to drive out differentially from 400 to
1200 mV. The differential output voltage (VOD ) can be statically set by using the
ALTGXB megafunction.
You can configure the output driver with 100- OCT or external OCT.
Differential signaling conventions are shown in Figure 2–9. The differential amplitude
represents the value of the voltage between the true and complement signals.
Peak-to-peak differential voltage is defined as 2 (VHIGH – VLOW ) = 2 single-ended
voltage swing. The common mode voltage is the average of V HIGH and VLOW.
Figure 2–9. Differential Signaling
Single-Ended Waveform
Vhigh
True
+VOD
Complement
Vlow
Differential Waveform
+400
+VOD
0-V Differential
VOD (Differential)
= Vhigh − Vlow
© December 2009
Altera Corporation
2 * VOD
-VOD
−400
Arria GX Device Handbook, Volume 1
2–10
Chapter 2: Arria GX Architecture
Transceivers
Programmable Pre-Emphasis
The programmable pre-emphasis module controls the output driver to boost high
frequency components and compensate for losses in the transmission medium, as
shown in Figure 2–10. Pre-emphasis is set statically using the ALTGXB megafunction.
Figure 2–10. Pre-Emphasis Signaling
VMAX
Pre-Emphasis % = (
VMIN
VMAX
− 1) × 100
VMIN
Pre-emphasis percentage is defined as (VMAX /VMIN – 1) × 100, where VM AX is the
differential emphasized voltage (peak-to-peak) and VMIN is the differential
steady-state voltage (peak-to-peak).
PCI Express (PIPE) Receiver Detect
The Arria GX transmitter buffer has a built-in receiver detection circuit for use in PCI
Express (PIPE) mode. This circuit provides the ability to detect if there is a receiver
downstream by sending out a pulse on the channel and monitoring the reflection.
This mode requires a tri-stated transmitter buffer (in electrical idle mode).
PCI Express (PIPE) Electric Idles (or Individual Transmitter Tri-State)
The Arria GX transmitter buffer supports PCI Express (PIPE) electrical idles. This
feature is only active in PCI Express (PIPE) mode. The tx_forceelecidle port puts
the transmitter buffer in electrical idle mode. This port is available in all PCI Express
(PIPE) power-down modes and has specific usage in each mode.
Receiver Path
This section describes the data path through the Arria GX receiver. The sub-blocks are
described in order from the receiver buffer to the PLD-receiver parallel interface.
Receiver Buffer
The Arria GX receiver input buffer supports the 1.2-V and 1.5-V PCML I/O standards
at rates up to 3.125 Gbps. The common mode voltage of the receiver input buffer is
programmable between 0.85 V and 1.2 V. You must select the 0.85 V common mode
voltage for AC- and DC-coupled PCML links and 1.2 V common mode voltage for
DC-coupled LVDS links.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
Transceivers
2–11
The receiver has 100- on-chip differential termination (R D OCT) for different
protocols, as shown in Figure 2–11. You can disable the receiver’s internal termination
if external terminations and biasing are provided. The receiver and transmitter
differential termination method can be set independently of each other.
Figure 2–11. Receiver Input Buffer
100-Ω
Termination
Input
Pins
Programmable
Equalizer
Differential
Input
Buffer
If a design uses external termination, the receiver must be externally terminated and
biased to 0.85 V or 1.2 V. Figure 2–12 shows an example of an external termination and
biasing circuit.
Figure 2–12. External Termination and Biasing Circuit
Receiver External Termination
and Biasing
Arria GX Device
VDD
50-W
Termination
Resistance
R1
C1
Receiver
R1/R2 = 1K
VDD ´ {R2/(R1 + R 2)} = 0.85/1.2 V
RXIP
R2
RXIN
Receiver External Termination
and Biasing
Transmission
Line
Programmable Equalizer
The Arria GX receivers provide a programmable receiver equalization feature to
compensate for the effects of channel attenuation for high-speed signaling. PCB traces
carrying these high-speed signals have low-pass filter characteristics. Impedance
mismatch boundaries can also cause signal degradation. Equalization in the receiver
diminishes the lossy attenuation effects of the PCB at high frequencies.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–12
Chapter 2: Arria GX Architecture
Transceivers
The receiver equalization circuit is comprised of a programmable amplifier. Each
stage is a peaking equalizer with a different center frequency and programmable gain.
This allows varying amounts of gain to be applied, depending on the overall
frequency response of the channel loss. Channel loss is defined as the summation of
all losses through the PCB traces, vias, connectors, and cables present in the physical
link. The Quartus II software allows five equalization settings for Arria GX devices.
Receiver PLL and Clock Recovery Unit (CRU)
Each transceiver block has four receiver PLLs and CRU units, each of which is
dedicated to a receiver channel. The receiver PLL is fed by an input reference clock.
The receiver PLL, in conjunction with the CRU, generates two clocks: a high-speed
serial recovered clock that clocks the deserializer and a low-speed parallel recovered
clock that clocks the receiver's digital logic.
Figure 2–13 shows a block diagram of the receiver PLL and CRU circuits.
Figure 2–13. Receiver PLL and Clock Recovery Unit
/M
Dedicated
REFCLK0
rx_pll_locked
/2
PFD
Dedicated
/2
REFCLK1
Inter-Transceiver Lines [2:0]
rx_cruclk
up
dn
up
dn
CP+ LF
VCO
/L
Global Clock (2)
rx_locktorefclk
rx_locktodata
rx_freqlocked
Clock Recovery Unit (CRU) Control
High-speed serial recovered clk
Low-speed parallel recovered clk
rx_datain
Notes to Figure 2–13:
(1) You only need to select the protocol and the available input reference clock frequency in the ALTGXB MegaWizard Plug-In Manager. Based on your
selections, the ALTGXB MegaWizard Plug-In Manager automatically selects the necessary /M and /L dividers.
(2) The global clock line must be driven from an input pin only.
The reference clock input to the receiver PLL can be derived from:
■
One of the two available dedicated reference clock input pins (REFCLK0 or
REFCLK1) of the associated transceiver block
■
PLD global clock network (must be driven directly from an input clock pin and
cannot be driven by user logic or enhanced PLL)
■
Inter-transceiver block lines driven by reference clock input pins of other
transceiver blocks
All the parameters listed are programmable in the Quartus II software. The receiver
PLL has the following features:
■
Operates from 600 Mbps to 3.125 Gbps.
■
Uses a reference clock between 50 MHz and 622.08 MHz.
■
Programmable bandwidth settings: low, medium, and high.
■
Programmable rx_locktorefclk (forces the receiver PLL to lock to reference
clock) and rx_locktodata (forces the receiver PLL to lock to data).
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
Transceivers
2–13
■
The voltage-controlled oscillator (VCO) operates at half rate.
■
Programmable frequency multiplication W of 1, 4, 5, 8, 10, 16, 20, and 25. Not all
settings are supported for any particular frequency.
■
Two lock indication signals are provided. They are found in PFD mode
(lock-to-reference clock), and PD (lock-to-data).
The CRU controls whether the receiver PLL locks to the input reference clock
(lock-to-reference mode) or the incoming serial data (lock-to data mode). You can set
the CRU to switch between lock-to-data and lock-to-reference modes automatically or
manually. In automatic lock mode, the phase detector and dedicated parts per million
(PPM) detector within each receiver channel control the switch between lock-to-data
and lock-to-reference modes based on some pre-set conditions. In manual lock mode,
you can control the switch manually using the rx_locktorefclk and
rx_locktodata signals.
f
For more information, refer to the “Clock Recovery Unit” section in the Arria GX
Transceiver Protocol Support and Additional Features chapter.
Table 2–4 lists the behavior of the CRU block with respect to the rx_locktorefclk
and rx_locktodata signals.
Table 2–4. CRU Manual Lock Signals
rx_locktorefclk
rx_locktodata
CRU Mode
1
0
Lock-to-reference clock
x
1
Lock-to-data
0
0
Automatic
If the rx_locktorefclk and rx_locktodata ports are not used, the default
setting is automatic lock mode.
Deserializer
The deserializer block clocks in serial input data from the receiver buffer using the
high-speed serial recovered clock and deserializes into 8- or 10-bit parallel data using
the low-speed parallel recovered clock. The serial data is assumed to be received with
LSB first, followed by MSB. It feeds the deserialized 8- or 10-bit data to the word
aligner, as shown in Figure 2–14.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–14
Chapter 2: Arria GX Architecture
Transceivers
Figure 2–14. Deserializer (Note 1)
Received Data
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
10
To Word
Aligner
Clock
High-speed serial recovered clock
Recovery
Unit
Low -speed parallel recovered clock
Note to Figure 2–14:
(1) This is a 10-bit deserializer. The deserializer can also convert 8 bits of data.
Word Aligner
The deserializer block creates 8- or 10-bit parallel data. The deserializer ignores
protocol symbol boundaries when converting this data. Therefore, the boundaries of
the transferred words are arbitrary. The word aligner aligns the incoming data based
on specific byte or word boundaries. The word alignment module is clocked by the
local receiver recovered clock during normal operation. All the data and programmed
patterns are defined as “big-endian” (most significant word followed by least
significant word). Most-significant-bit-first protocols should reverse the bit order of
word align patterns programmed.
This module detects word boundaries for 8B/10B-based protocols. This module is
also used to align to specific programmable patterns in PRBS7/23 test mode.
Pattern Detection
The programmable pattern detection logic can be programmed to align word
boundaries using a single 7- or 10-bit pattern. The pattern detector can either do an
exact match, or match the exact pattern and the complement of a given pattern. Once
the programmed pattern is found, the data stream is aligned to have the pattern on
the LSB portion of the data output bus.
XAUI, GIGE, PCI Express (PIPE), and Serial RapidIO standards have embedded state
machines for symbol boundary synchronization. These standards use K28.5 as their
10-bit programmed comma pattern. Each of these standards uses different algorithms
before signaling symbol boundary acquisition to the FPGA.
Pattern detection logic searches from the LSB to the MSB. If multiple patterns are
found within the search window, the pattern in the lower portion of the data stream
(corresponding to the pattern received earlier) is aligned and the rest of the matching
patterns are ignored.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
Transceivers
2–15
Once a pattern is detected and the data bus is aligned, the word boundary is locked.
The two detection status signals (rx_syncstatus and rx_patterndetect)
indicate that an alignment is complete.
Figure 2–15 is a block diagram of the word aligner.
Figure 2–15. Word Aligner
datain
bitslip
Word
Aligner
enapatternalign
dataout
syncstatus
patterndetect
clock
Control and Status Signals
The rx_enapatternalign signal is the FPGA control signal that enables word
alignment in non-automatic modes. The rx_enapatternalign signal is not used in
automatic modes (PCI Express [PIPE], XAUI, GIGE, and Serial RapidIO).
In manual alignment mode, after the rx_enapatternalign signal is activated, the
rx_syncstatus signal goes high for one parallel clock cycle to indicate that the
alignment pattern has been detected and the word boundary has been locked. If
rx_enapatternalign is deactivated, the rx_syncstatus signal acts as a
re-synchronization signal to signify that the alignment pattern has been detected but
not locked on a different word boundary.
When using the synchronization state machine, the rx_syncstatus signal indicates
the link status. If the rx_syncstatus signal is high, link synchronization is
achieved. If the rx_syncstatus signal is low, link synchronization has not yet been
achieved, or there were enough code group errors to lose synchronization.
f
For more information about manual alignment modes, refer to the Arria GX Device
Handbook.
The rx_patterndetect signal pulses high during a new alignment and whenever
the alignment pattern occurs on the current word boundary.
Programmable Run Length Violation
The word aligner supports a programmable run length violation counter. Whenever
the number of the continuous ‘0’ (or ‘1’) exceeds a user programmable value, the
rx_rlv signal goes high for a minimum pulse width of two recovered clock cycles.
The maximum run values supported are 128 UI for 8-bit serialization or 160 UI for
10-bit serialization.
Running Disparity Check
The running disparity error rx_disperr and running disparity value
rx_runningdisp are sent along with aligned data from the 8B/10B decoder to the
FPGA. You can ignore or act on the reported running disparity value and running
disparity error signals.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–16
Chapter 2: Arria GX Architecture
Transceivers
Bit-Slip Mode
The word aligner can operate in either pattern detection mode or in bit-slip mode.
The bit-slip mode provides the option to manually shift the word boundary through
the FPGA. This feature is useful for:
■
Longer synchronization patterns than the pattern detector can accommodate
■
Scrambled data stream
■
Input stream consisting of over-sampled data
The word aligner outputs a word boundary as it is received from the analog receiver
after reset. You can examine the word and search its boundary in the FPGA. To do so,
assert the rx_bitslip signal. The rx_bitslip signal should be toggled and held
constant for at least two FPGA clock cycles.
For every rising edge of the rx_bitslip signal, the current word boundary is
slipped by one bit. Every time a bit is slipped, the bit received earliest is lost. If bit
slipping shifts a complete round of bus width, the word boundary is back to the
original boundary.
The rx_syncstatus signal is not available in bit-slipping mode.
Channel Aligner
The channel aligner is available only in XAUI mode and aligns the signals of all four
channels within a transceiver. The channel aligner follows the IEEE 802.3ae, clause 48
specification for channel bonding.
The channel aligner is a 16-word FIFO buffer with a state machine controlling the
channel bonding process. The state machine looks for an /A/ (/K28.3/) in each
channel and aligns all the /A/ code groups in the transceiver. When four columns of
/A/ (denoted by //A//) are detected, the rx_channelaligned signal goes high,
signifying that all the channels in the transceiver have been aligned. The reception of
four consecutive misaligned /A/ code groups restarts the channel alignment
sequence and sends the rx_channelaligned signal low.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
Transceivers
2–17
Figure 2–16 shows misaligned channels before the channel aligner and the aligned
channels after the channel aligner.
Figure 2–16. Before and After the Channel Aligner
Lane 3
Before
K
K
A
K
R
R
K
K
R
K
R
K
K
R
A
K
R
R
K
K
R
K
K
R
A
K
R
R
K
K
R
K
R
Lane 2
Lane 1
K
Lane 0
After
R
K
K
R
A
K
R
R
K
K
R
K
Lane 3
K
K
R
A
K
R
R
K
K
R
K
R
Lane 2
K
K
R
A
K
R
R
K
K
R
K
R
Lane 1
K
K
R
A
K
R
R
K
K
R
K
R
Lane 0
K
K
R
A
K
R
R
K
K
R
K
R
R
R
Rate Matcher
In asynchronous systems, the upstream transmitter and local receiver can be clocked
with independent reference clock sources. Frequency differences in the order of a few
hundred PPM can potentially corrupt the data at the receiver.
The rate matcher compensates for small clock frequency differences between the
upstream transmitter and the local receiver clocks by inserting or removing skip
characters from the inter packet gap (IPG) or idle streams. It inserts a skip character if
the local receiver is running a faster clock than the upstream transmitter. It deletes a
skip character if the local receiver is running a slower clock than the upstream
transmitter. The Quartus II software automatically configures the appropriate skip
character as specified in the IEEE 802.3 for GIGE mode and PCI-Express Base
Specification for PCI Express (PIPE) mode. The rate matcher is bypassed in Serial
RapidIO and must be implemented in the PLD logic array or external circuits
depending on your system design.
Table 2–5 lists the maximum frequency difference that the rate matcher can tolerate in
XAUI, PCI Express (PIPE), GIGE, and Basic functional modes.
Table 2–5. Rate Matcher PPM Tolerance
© December 2009
Altera Corporation
Function Mode
PPM
XAUI
± 100
PCI Express (PIPE)
± 300
GIGE
± 100
Basic
± 300
Arria GX Device Handbook, Volume 1
2–18
Chapter 2: Arria GX Architecture
Transceivers
XAUI Mode
In XAUI mode, the rate matcher adheres to clause 48 of the IEEE 802.3ae specification
for clock rate compensation. The rate matcher performs clock compensation on
columns of /R/ (/K28.0/), denoted by //R//. An //R// is added or deleted
automatically based on the number of words in the FIFO buffer.
PCI Express (PIPE) Mode Rate Matcher
In PCI Express (PIPE) mode, the rate matcher can compensate up to ± 300 PPM
(600 PPM total) frequency difference between the upstream transmitter and the
receiver. The rate matcher logic looks for skip ordered sets (SOS), which contains a
/K28.5/ comma followed by three /K28.0/ skip characters. The rate matcher logic
deletes or inserts /K28.0/ skip characters as necessary from/to the rate matcher FIFO.
The rate matcher in PCI Express (PIPE) mode has a FIFO buffer overflow and
underflow protection. In the event of a FIFO buffer overflow, the rate matcher deletes
any data after detecting the overflow condition to prevent FIFO pointer corruption
until the rate matcher is not full. In an underflow condition, the rate matcher inserts
9'h1FE (/K30.7/) until the FIFO buffer is not empty. These measures ensure that the
FIFO buffer can gracefully exit the overflow and underflow condition without
requiring a FIFO reset. The rate matcher FIFO overflow and underflow condition is
indicated on the pipestatus port.
You can bypass the rate matcher in PCI Express (PIPE) mode if you have a
synchronous system where the upstream transmitter and local receiver derive their
reference clocks from the same source.
GIGE Mode Rate Matcher
In GIGE mode, the rate matcher can compensate up to ± 100 PPM (200 PPM total)
frequency difference between the upstream transmitter and the receiver. The rate
matcher logic inserts or deletes /I2/ idle ordered sets to/from the rate matcher FIFO
during the inter-frame or inter-packet gap (IFG or IPG). /I2/ is selected as the rate
matching ordered set because it maintains the running disparity, unlike /I1/ that
alters the running disparity. Because the /I2/ ordered-set contains two 10-bit code
groups (/K28.5/, /D16.2/), 20 bits are inserted or deleted at a time for rate matching.
1
The rate matcher logic has the capability to insert or delete /C1/ or /C2/
configuration ordered sets when ‘GIGE Enhanced’ mode is chosen as the sub-protocol
in the MegaWizard Plug-In Manager.
If the frequency PPM difference between the upstream transmitter and the local
receiver is high, or if the packet size is too large, the rate matcher FIFO buffer can face
an overflow or underflow situation.
Basic Mode
In basic mode, you can program the skip and control pattern for rate matching. There
is no restriction on the deletion of a skip character in a cluster. The rate matcher
deletes the skip characters as long as they are available. For insertion, the rate matcher
inserts skip characters such that the number of skip characters at the output of rate
matcher does not exceed five.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
Transceivers
2–19
8B/10B Decoder
The 8B/10B decoder is used in all supported functional modes. The 8B/10B decoder
takes in 10-bit data from the rate matcher and decodes it into 8-bit data + 1-bit control
identifier, thereby restoring the original transmitted data at the receiver. The 8B/10B
decoder indicates whether the received 10-bit character is a data or control code
through the rx_ctrldetect port. If the received 10-bit code group is a control
character (Kx.y), the rx_ctrldetect signal is driven high and if it is a data
character (Dx.y), the rx_ctrldetect signal is driven low.
Figure 2–17 shows a 10-bit code group decoded to an 8-bit data and a 1-bit control
indicator.
Figure 2–17. 10-Bit to 8-Bit Conversion
j
h
g
f
i
e
d
c
b
a
9
8
7
6
5
4
3
2
1
0
MSB Received Last
LSB Received First
8B/10B Conversion
ctrl
7
6
5
4
3
2
1
0
H
G
F
E
D
C
B
A
Parallel Data
If the received 10-bit code is not a part of valid Dx.y or Kx.y code groups, the 8B/10B
decoder block asserts an error flag on the rx_errdetect port. If the received 10-bit
code is detected with incorrect running disparity, the 8B/10B decoder block asserts an
error flag on the rx_disperr and rx_errdetect ports. The error flag signals
(rx_errdetect and rx_disperr) have the same data path delay from the 8B/10B
decoder to the PLD-transceiver interface as the bad code group.
Receiver State Machine
The receiver state machine operates in Basic, GIGE, PCI Express (PIPE), and XAUI
modes. In GIGE mode, the receiver state machine replaces invalid code groups with
K30.7. In XAUI mode, the receiver state machine translates the XAUI PCS code group
to the XAUI XGMII code group.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–20
Chapter 2: Arria GX Architecture
Transceivers
Byte Deserializer
Byte deserializer takes in one-byte wide data from the 8B/10B decoder and
deserializes it into a two-byte wide data at half the speed. This allows clocking the
PLD-receiver interface at half the speed as compared to the receiver PCS logic. The
byte deserializer is bypassed in GIGE mode.
The byte ordering at the receiver output might be different than what was
transmitted. This is a non-deterministic swap, because it depends on PLL lock times
and link delay. If required, you must implement byte ordering logic in the PLD to
correct this situation.
f
For more information about byte serializer, refer to the Arria GX Transceiver
Architecture chapter.
Receiver Phase Compensation FIFO Buffer
A receiver phase compensation FIFO buffer is located at each receiver channel’s logic
array interface. It compensates for the phase difference between the receiver PCS
clock and the local PLD receiver clock. The receiver phase compensation FIFO is used
in all supported functional modes. The receiver phase compensation FIFO buffer is
eight words deep in PCI Express (PIPE) mode and four words deep in all other
modes.
f
For more information about architecture and clocking, refer to the Arria GX Transceiver
Architecture chapter.
Loopback Modes
Arria GX transceivers support the following loopback configurations for diagnostic
purposes:
■
Serial loopback
■
Reverse serial loopback
■
Reverse serial loopback (pre-CDR)
■
PCI Express (PIPE) reverse parallel loopback (available only in [PIPE] mode)
Serial Loopback
Figure 2–18 shows the transceiver data path in serial loopback.
Figure 2–18. Transceiver Data Path in Serial Loopback
Transmitter PCS
TX Phase
Compensation
FIFO
Byte
Serializer
Transmitter PMA
8B/10B
Encoder
Serializer
PLD
Logic
Array
Serial Loopback
Receiver PCS
RX Phase
Compensation
FIFO
Arria GX Device Handbook, Volume 1
Byte
DeSerializer
8B/10B
Decoder
Rate
Match
FIFO
Word
Aligner
Receiver PMA
DeSerializer
Clock
Recovery
Unit
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
Transceivers
2–21
In GIGE and Serial RapidIO modes, you can dynamically put each transceiver
channel individually in serial loopback by controlling the rx_seriallpbken port. A
high on the rx_seriallpbken port puts the transceiver into serial loopback and a
low takes the transceiver out of serial loopback.
As seen in Figure 2–18, the serial data output from the transmitter serializer is looped
back to the receiver CRU in serial loopback. The transmitter data path from the PLD
interface to the serializer in serial loopback is the same as in non-loopback mode. The
receiver data path from the clock recovery unit to the PLD interface in serial loopback
is the same as in non-loopback mode. Because the entire transceiver data path is
available in serial loopback, this option is often used to diagnose the data path as a
probable cause of link errors.
1
When serial loopback is enabled, the transmitter output buffer is still active and
drives the serial data out on the tx_dataout port.
Reverse Serial Loopback
Reverse serial loopback mode uses the analog portion of the transceiver. An external
source (pattern generator or transceiver) generates the source data. The high-speed
serial source data arrives at the high-speed differential receiver input buffer, passes
through the CRU unit and the retimed serial data is looped back, and is transmitted
though the high-speed differential transmitter output buffer.
Figure 2–19 shows the data path in reverse serial loopback mode.
Figure 2–19. Arria GX Block in Reverse Serial Loopback Mode
Transmitter Digital Logic
BIST
PRBS
Generator
BIST
Incremental
Generator
TX Phase
Compensation
FIFO
Analog Receiver and
Transmitter Logic
Byte
Serializer
8B/10B
20 Encoder
Serializer
FPGA
Logic
Array
Reverse
Serial
Loopback
BIST
Incremental
Verify
RX Phase
Compensation
FIFO
BIST
PRBS
Verify
Byte
Deserializer
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
Deserializer
Clock
Recovery
Unit
Receiver Digital Logic
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–22
Chapter 2: Arria GX Architecture
Transceivers
Reverse Serial Pre-CDR Loopback
Reverse serial pre-CDR loopback mode uses the analog portion of the transceiver. An
external source (pattern generator or transceiver) generates the source data. The
high-speed serial source data arrives at the high-speed differential receiver input
buffer, loops back before the CRU unit, and is transmitted though the high-speed
differential transmitter output buffer. It is for test or verification use only to verify the
signal being received after the gain and equalization improvements of the input
buffer. The signal at the output is not exactly what is received because the signal goes
through the output buffer and the VO D is changed to the VOD setting level.
Pre-emphasis settings have no effect.
Figure 2–20 shows the Arria GX block in reverse serial pre-CDR loopback mode.
Figure 2–20. Arria GX Block in Reverse Serial Pre-CDR Loopback Mode
Transmitter Digital Logic
Analog Receiver and
Transmitter Logic
BIST
PRBS
Generator
BIST
Incremental
Generator
TX Phase
Compensation
FIFO
Byte
Serializer
8B/10B
20 Encoder
Serializer
FPGA
Logic
Array
BIST
Incremental
Verify
Reverse
Serial
Pre-CDR
Loopback
BIST
PRBS
Verify
Byte
Deserializer
RX Phase
Compensation
FIFO
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
Deserializer
Clock
Recovery
Unit
Receiver Digital Logic
PCI Express (PIPE) Reverse Parallel Loopback
Figure 2–21 shows the data path for PCI Express (PIPE) reverse parallel loopback. The
reverse parallel loopback configuration is compliant with the PCI Express (PIPE)
specification and is available only on PCI Express (PIPE) mode.
Figure 2–21. PCI Express (PIPE) Reverse Parallel Loopback
Transmitter PCS
TX Phase
Compensation
FIFO
Byte
Serializer
Transmitter PMA
8B/10B
Encoder
PIPE
Interface
Serializer
PIPE Reverse
Parallel Loopback
Receiver PCS
RX Phase
Compensation
FIFO
Arria GX Device Handbook, Volume 1
Byte
DeSerializer
8B/10B
Decoder
Rate
Match
FIFO
Word
Aligner
Receiver PMA
DeSerializer
Clock
Recovery
Unit
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
Transceivers
2–23
You can dynamically put the PCI Express (PIPE) mode transceiver in reverse parallel
loopback by controlling the tx_detectrxloopback port instantiated in the
MegaWizard Plug-In Manager. A high on the tx_detectrxloopback port in P0
power state puts the transceiver in reverse parallel loopback. A high on the
tx_detectrxloopback port in any other power state does not put the transceiver
in reverse parallel loopback.
As seen in Figure 2–21, the serial data received on the rx_datain port in reverse
parallel loopback goes through the CRU, deserializer, word aligner, and the rate
matcher blocks. The parallel data at the output of the receiver rate matcher block is
looped back to the input of the transmitter serializer block. The serializer converts the
parallel data to serial data and feeds it to the transmitter output buffer that drives the
data out on the tx_dataout port. The data at the output of the rate matcher also
goes through the 8B/10B decoder, byte deserializer, and receiver phase compensation
FIFO before being fed to the PLD on the rx_dataout port.
Reset and Powerdown
Arria GX transceivers offer a power saving advantage with their ability to shut off
functions that are not needed.
The following three reset signals are available per transceiver channel and can be used
to individually reset the digital and analog portions within each channel:
■
tx_digitalreset
■
rx_analogreset
■
rx_digitalreset
The following two powerdown signals are available per transceiver block and can be
used to shut down an entire transceiver block that is not being used:
© December 2009
■
gxb_powerdown
■
gxb_enable
Altera Corporation
Arria GX Device Handbook, Volume 1
2–24
Chapter 2: Arria GX Architecture
Transceivers
Table 2–6 lists the reset signals available in Arria GX devices and the transceiver
circuitry affected by each signal.
Reset Signal
Transmitter Phase Compensation FIFO Module/ Byte Serializer
Transmitter 8B/10B Encoder
Transmitter Serializer
Transmitter Analog Circuits
Transmitter PLL
Transmitter XAUI State Machine
BIST Generators
Receiver Deserializer
Receiver Word Aligner
Receiver Deskew FIFO Module
Receiver Rate Matcher
Receiver 8B/10B Decoder
Receiver Phase Comp FIFO Module/ Byte Deserializer
Receiver PLL / CRU
Receiver XAUI State Machine
BIST Verifiers
Receiver Analog Circuits
Table 2–6. Reset Signal Map to Arria GX Blocks
rx_digitalreset
—
—
—
—
—
—
—
—
v
—
v
v
v
—
v
v
—
rx_analogreset
—
—
—
—
—
—
—
v
—
—
—
—
—
v
—
—
v
tx_digitalreset
v
v
—
—
—
v
v
—
—
—
—
—
—
—
—
—
—
gxb_powerdown
v
v
v
v
v
v
v
v
v
—
v
v
v
v
v
v
v
gxb_enable
v
v
v
v
v
v
v
v
v
—
v
v
v
v
v
v
v
Calibration Block
Arria GX devices use the calibration block to calibrate OCT for the PLLs, and their
associated output buffers, and the terminating resistors on the transceivers. The
calibration block counters the effects of process, voltage, and temperature (PVT). The
calibration block references a derived voltage across an external reference resistor to
calibrate the OCT resistors on Arria GX devices. You can power down the calibration
block. However, powering down the calibration block during operations can yield
transmit and receive data errors.
Transceiver Clocking
This section describes the clock distribution in an Arria GX transceiver channel and
the PLD clock resource utilization by the transceiver blocks.
Transceiver Channel Clock Distribution
Each transceiver block has one transmitter PLL and four receiver PLLs.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
Transceivers
2–25
The transmitter PLL multiplies the input reference clock to generate a high-speed
serial clock at a frequency that is half the data rate of the configured functional mode.
This high-speed serial clock (or its divide-by-two version if the functional mode uses
byte serializer) is fed to the CMU clock divider block. Depending on the configured
functional mode, the CMU clock divider block divides the high-speed serial clock to
generate the low-speed parallel clock that clocks the transceiver PCS logic in the
associated channel. The low-speed parallel clock is also forwarded to the PLD logic
array on the tx_clkout or coreclkout ports.
The receiver PLL in each channel is also fed by an input reference clock. The receiver
PLL along with the clock recovery unit generates a high-speed serial recovered clock
and a low-speed parallel recovered clock. The low-speed parallel recovered clock
feeds the receiver PCS logic until the rate matcher. The CMU low-speed parallel clock
clocks the rest of the logic from the rate matcher until the receiver phase
compensation FIFO. In modes that do not use a rate matcher, the receiver PCS logic is
clocked by the recovered clock until the receiver phase compensation FIFO.
The input reference clock to the transmitter and receiver PLLs can be derived from:
■
One of two available dedicated reference clock input pins (REFCLK0 or REFCLK1)
of the associated transceiver block
■
PLD clock network (must be driven directly from an input clock pin and cannot be
driven by user logic or enhanced PLL)
■
Inter-transceiver block lines driven by reference clock input pins of other
transceiver blocks
Figure 2–22 shows the input reference clock sources for the transmitter and receiver
PLL.
Figure 2–22. Input Reference Clock Sources
Inter-Transceiver Lines [2]
Transceiver Block 2
Inter-Transceiver Lines [1]
Transceiver Block 1
Transceiver Block 0
Inter-Transceiver Lines [0]
Dedicated
REFCLK0
/2
Dedicated
REFCLK1
/2
Transmitter
PLL
Inter-Transceiver Lines [2:0]
Global Clock (1)
Four
Receiver
PLLs
Global Clock (1)
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–26
Chapter 2: Arria GX Architecture
Transceivers
f
For more information about transceiver clocking in all supported functional modes,
refer to the Arria GX Transceiver Architecture chapter.
PLD Clock Utilization by Transceiver Blocks
Arria GX devices have up to 16 global clock (GCLK) lines and 16 regional clock
(RCLK) lines that are used to route the transceiver clocks. The following transceiver
clocks use the available global and regional clock resources:
■
pll_inclk (if driven from an FPGA input pin)
■
rx_cruclk (if driven from an FPGA input pin)
■
tx_clkout/coreclkout (CMU low-speed parallel clock forwarded to the PLD)
■
Recovered clock from each channel (rx_clkout) in non-rate matcher mode
■
Calibration clock (cal_blk_clk)
■
Fixed clock (fixedclk used for receiver detect circuitry in PCI Express [PIPE]
mode only)
Figure 2–23 and Figure 2–24 show the available GCLK and RCLK resources in Arria
GX devices.
Figure 2–23. Global Clock Resources in Arria GX Devices
CLK[15..12]
11 5
7
Arria GX
Transceiver
Block
GCLK[15..12]
CLK[3..0]
1
2
GCLK[11..8]
GCLK[3..0]
GCLK[4..7]
Arria GX
Transceiver
Block
8
12 6
CLK[7..4]
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
Transceivers
2–27
Figure 2–24. Regional Clock Resources in Arria GX Devices
CLK[15..12]
11 5
7
CLK[3..0]
RCLK
[31..28]
RCLK
[27..24]
RCLK
[3..0]
RCLK
[23..20]
RCLK
[7..4]
RCLK
[19..16]
Arria GX
Transceiver
Block
1
2
RCLK
[11..8]
8
Arria GX
Transceiver
Block
RCLK
[15..12]
12 6
CLK[7..4]
For the RCLK or GCLK network to route into the transceiver, a local route input
output (LRIO) channel is required. Each LRIO clock region has up to eight clock paths
and each transceiver block has a maximum of eight clock paths for connecting with
LRIO clocks. These resources are limited and determine the number of clocks that can
be used between the PLD and transceiver blocks. Table 2–7 and Table 2–8 list the
number of LRIO resources available for Arria GX devices with different numbers of
transceiver blocks.
Table 2–7. Available Clocking Connections for Transceivers in EP1AGX35D, EP1AGX50D, and EP1AGX60D
Clock Resource
Source
Transceiver
Global Clock
Regional Clock
Bank13
8 Clock I/O
Bank14
8 Clock I/O
Region0 8 LRIO clock
v
RCLK 20-27
v
—
Region1 8 LRIO clock
v
RCLK 12-19
—
v
Table 2–8. Available Clocking Connections for Transceivers in EP1AGX60E and EP1AGX90E
Clock Resource
Source
Transceiver
Global Clock
Regional Clock
Bank13
8 Clock I/O
Bank14
8 Clock I/O
Bank15
8 Clock I/O
Region0 8 LRIO clock
v
RCLK 20-27
v
—
—
Region1 8 LRIO clock
v
RCLK 20-27
v
v
—
Region2 8 LRIO clock
v
RCLK 12-19
—
v
v
Region3 8 LRIO clock
v
RCLK 12-19
—
—
v
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–28
Chapter 2: Arria GX Architecture
Logic Array Blocks
Logic Array Blocks
Each logic array block (LAB) consists of eight adaptive logic modules (ALMs), carry
chains, shared arithmetic chains, LAB control signals, local interconnects, and register
chain connection lines. The local interconnect transfers signals between ALMs in the
same LAB. Register chain connections transfer the output of an ALM register to the
adjacent ALM register in a LAB. The Quartus II Compiler places associated logic in a
LAB or adjacent LABs, allowing the use of local, shared arithmetic chain, and register
chain connections for performance and area efficiency. Table 2–9 lists Arria GX device
resources. Figure 2–25 shows the Arria GX LAB structure.
Table 2–9. Arria GX Device Resources
M512 RAM
Columns/Blocks
M4K RAM
Columns/Blocks
M-RAM Blocks
DSP Block
Columns/Blocks
EP1AGX20
166
118
1
10
EP1AGX35
197
140
1
14
EP1AGX50
313
242
2
26
EP1AGX60
326
252
2
32
EP1AGX90
478
400
4
44
Device
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
Logic Array Blocks
2–29
Figure 2–25. Arria GX LAB Structure
Row Interconnects of
Variable Speed & Length
ALMs
Direct link
interconnect from
adjacent block
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
Direct link
interconnect to
adjacent block
Local Interconnect
LAB
Local Interconnect is Driven
from Either Side by Columns & LABs,
& from Above by Rows
Column Interconnects of
Variable Speed & Length
LAB Interconnects
The LAB local interconnect can drive all eight ALMs in the same LAB. It is driven by
column and row interconnects and ALM outputs in the same LAB. Neighboring
LABs, M512 RAM blocks, M4K RAM blocks, M-RAM blocks, or digital signal
processing (DSP) blocks from the left and right can also drive the local interconnect of
a LAB through the direct link connection. The direct link connection feature
minimizes the use of row and column interconnects, providing higher performance
and flexibility. Each ALM can drive 24 ALMs through fast local and direct link
interconnects.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–30
Chapter 2: Arria GX Architecture
Logic Array Blocks
Figure 2–26 shows the direct link connection.
Figure 2–26. Direct Link Connection
Direct link interconnect from
left LAB, TriMatrixTM memory
block, DSP block, or
input/output element (IOE)
Direct link interconnect from
right LAB, TriMatrix memory
block, DSP block, or IOE output
ALMs
Direct link
interconnect
to right
Direct link
interconnect
to left
Local
Interconnect
LAB
LAB Control Signals
Each LAB contains dedicated logic for driving control signals to its ALMs. The control
signals include three clocks, three clock enables, two asynchronous clears,
synchronous clear, asynchronous preset or load, and synchronous load control
signals, providing a maximum of 11 control signals at a time. Although synchronous
load and clear signals are generally used when implementing counters, they can also
be used with other functions.
Each LAB can use three clocks and three clock enable signals. However, there can only
be up to two unique clocks per LAB, as shown in the LAB control signal generation
circuit in Figure 2–27. Each LAB’s clock and clock enable signals are linked. For
example, any ALM in a particular LAB using the labclk1 signal also uses
labclkena1. If the LAB uses both the rising and falling edges of a clock, it also uses
two LAB-wide clock signals. De-asserting the clock enable signal turns off the
corresponding LAB-wide clock. Each LAB can use two asynchronous clear signals
and an asynchronous load/preset signal. The asynchronous load acts as a preset
when the asynchronous load data input is tied high. When the asynchronous
load/preset signal is used, the labclkena0 signal is no longer available.
The LAB row clocks [5..0] and LAB local interconnect generate the LAB-wide
control signals. The MultiTrack interconnects have inherently low skew. This low
skew allows the MultiTrack interconnects to distribute clock and control signals in
addition to data.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
Adaptive Logic Modules
2–31
Figure 2–27 shows the LAB control signal generation circuit.
Figure 2–27. LAB-Wide Control Signals
There are two unique
clock signals per LAB.
6
Dedicated Row LAB Clocks
6
6
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
labclk0
labclk1
labclkena0
or asyncload
or labpreset
labclk2
labclkena1
labclkena2
labclr1
syncload
labclr0
synclr
Adaptive Logic Modules
The basic building block of logic in the Arria GX architecture is the ALM. The ALM
provides advanced features with efficient logic utilization. Each ALM contains a
variety of look-up table (LUT)-based resources that can be divided between two
adaptive LUTs (ALUTs). With up to eight inputs to the two ALUTs, one ALM can
implement various combinations of two functions. This adaptability allows the ALM
to be completely backward-compatible with four-input LUT architectures. One ALM
can also implement any function of up to six inputs and certain seven-input functions.
In addition to the adaptive LUT-based resources, each ALM contains two
programmable registers, two dedicated full adders, a carry chain, a shared arithmetic
chain, and a register chain. Through these dedicated resources, the ALM can
efficiently implement various arithmetic functions and shift registers. Each ALM
drives all types of interconnects: local, row, column, carry chain, shared arithmetic
chain, register chain, and direct link interconnects. Figure 2–28 shows a high-level
block diagram of the Arria GX ALM while Figure 2–29 shows a detailed view of all
the connections in the ALM.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–32
Chapter 2: Arria GX Architecture
Adaptive Logic Modules
Figure 2–28. High-Level Block Diagram of the Arria GX ALM
carry_in
shared_arith_in
reg_chain_in
To general or
local routing
dataf0
adder0
datae0
D
dataa
datab
datac
Q
To general or
local routing
reg0
Combinational
Logic
datad
adder1
D
Q
datae1
To general or
local routing
reg1
dataf1
To general or
local routing
carry_out
shared_arith_out
Arria GX Device Handbook, Volume 1
reg_chain_out
© December 2009
Altera Corporation
© December 2009
Altera Corporation
datac
dataa
datab
Local
Interconnect
Local
Interconnect
Local
datae1
dataf1
Local
Interconnect
Local
Interconnect
Local
Interconnect
datad
datae0
Local
Interconnect
Interconnect
dataf0
Local
Interconnect
3-Input
LUT
3-Input
LUT
4-Input
LUT
3-Input
LUT
3-Input
LUT
4-Input
LUT
shared_arith_out
shared_arith_in
carry_out
carry_in
VCC
sclr
syncload
reg_chain_out
reg_chain_in
clk[2..0]
aclr[1..0]
ENA
CLRN
PRN/ALD
D
Q
ADATA
ENA
CLRN
PRN/ALD
D
Q
ADATA
asyncload
ena[2..0]
Local
Interconnect
Row, column &
direct link routing
Row, column &
direct link routing
Local
Interconnect
Row, column &
direct link routing
Row, column &
direct link routing
Chapter 2: Arria GX Architecture
Adaptive Logic Modules
2–33
Figure 2–29. Arria GX ALM Details
Arria GX Device Handbook, Volume 1
2–34
Chapter 2: Arria GX Architecture
Adaptive Logic Modules
One ALM contains two programmable registers. Each register has data, clock, clock
enable, synchronous and asynchronous clear, asynchronous load data, and
synchronous and asynchronous load/preset inputs.
Global signals, general-purpose I/O pins, or any internal logic can drive the register's
clock and clear control signals. Either general-purpose I/O pins or internal logic can
drive the clock enable, preset, asynchronous load, and asynchronous load data. The
asynchronous load data input comes from the datae or dataf input of the ALM,
which are the same inputs that can be used for register packing. For combinational
functions, the register is bypassed and the output of the LUT drives directly to the
outputs of the ALM.
Each ALM has two sets of outputs that drive the local, row, and column routing
resources. The LUT, adder, or register output can drive these output drivers
independently (refer to Figure 2–29). For each set of output drivers, two ALM outputs
can drive column, row, or direct link routing connections. One of these ALM outputs
can also drive local interconnect resources. This allows the LUT or adder to drive one
output while the register drives another output. This feature, called register packing,
improves device utilization because the device can use the register and combinational
logic for unrelated functions. Another special packing mode allows the register
output to feed back into the LUT of the same ALM so that the register is packed with
its own fan-out LUT. This feature provides another mechanism for improved fitting.
The ALM can also drive out registered and unregistered versions of the LUT or adder
output.
ALM Operating Modes
The Arria GX ALM can operate in one of the following modes:
■
Normal mode
■
Extended LUT mode
■
Arithmetic mode
■
Shared arithmetic mode
Each mode uses ALM resources differently. Each mode has 11 available inputs to the
ALM (refer to Figure 2–28)the eight data inputs from the LAB local interconnect;
carry-in from the previous ALM or LAB; the shared arithmetic chain connection from
the previous ALM or LAB; and the register chain connectionare directed to different
destinations to implement the desired logic function. LAB-wide signals provide clock,
asynchronous clear, asynchronous preset/load, synchronous clear, synchronous load,
and clock enable control for the register. These LAB-wide signals are available in all
ALM modes. For more information about LAB-wide control signals, refer to “LAB
Control Signals” on page 2–30.
The Quartus II software and supported third-party synthesis tools, in conjunction
with parameterized functions such as library of parameterized modules (LPM)
functions, automatically choose the appropriate mode for common functions such as
counters, adders, subtractors, and arithmetic functions. If required, you can also
create special-purpose functions that specify which ALM operating mode to use for
optimal performance.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
Adaptive Logic Modules
2–35
Normal Mode
Normal mode is suitable for general logic applications and combinational functions.
In this mode, up to eight data inputs from the LAB local interconnect are inputs to the
combinational logic. Normal mode allows two functions to be implemented in one
Arria GX ALM, or an ALM to implement a single function of up to six inputs. The
ALM can support certain combinations of completely independent functions and
various combinations of functions which have common inputs. Figure 2–30 shows the
supported LUT combinations in normal mode.
Figure 2–30. ALM in Normal Mode
(Note 1)
dataf0
datae0
datac
dataa
4-Input
LUT
combout0
datab
datad
datae1
dataf1
4-Input
LUT
combout1
dataf0
datae0
datac
dataa
datab
5-Input
LUT
combout0
datad
datae1
dataf1
3-Input
LUT
dataf0
datae0
datac
dataa
datab
datad
datae1
dataf1
5-Input
LUT
4-Input
LUT
dataf0
datae0
datac
dataa
datab
5-Input
LUT
combout0
5-Input
LUT
combout1
dataf0
datae0
dataa
datab
datac
datad
6-Input
LUT
combout0
dataf0
datae0
dataa
datab
datac
datad
6-Input
LUT
combout0
6-Input
LUT
combout1
datad
datae1
dataf1
combout1
combout0
combout1
datae1
dataf1
Note to Figure 2–30:
(1) Combinations of functions with less inputs than those shown are also supported. For example, combinations of functions with the following
number of inputs are supported: 4 and 3, 3 and 3, 3 and 2, 5 and 2, and so on.
Normal mode provides complete backward compatibility with four-input LUT
architectures. Two independent functions of four inputs or less can be implemented in
one Arria GX ALM. In addition, a five-input function and an independent three-input
function can be implemented without sharing inputs.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–36
Chapter 2: Arria GX Architecture
Adaptive Logic Modules
To pack two five-input functions into one ALM, the functions must have at least two
common inputs. The common inputs are dataa and datab. The combination of a
four-input function with a five-input function requires one common input
(either dataa or datab).
To implement two six-input functions in one ALM, four inputs must be shared and
the combinational function must be the same. For example, a 4 × 2 crossbar switch
(two 4-to-1 multiplexers with common inputs and unique select lines) can be
implemented in one ALM, as shown in Figure 2–31. The shared inputs are dataa,
datab, datac, and datad, while the unique select lines are datae0 and dataf0 for
function0, and datae1 and dataf1 for function1. This crossbar switch
consumes four LUTs in a four-input LUT-based architecture.
Figure 2–31. 4 × 2 Crossbar Switch Example
4 ´ 2 Crossbar Switch
sel0[1..0]
inputa
inputb
out0
inputc
inputd
Implementation in 1 ALM
dataf0
datae0
dataa
datab
datac
datad
Six-Input
LUT
(Function0)
combout0
Six-Input
LUT
(Function1)
combout1
out1
sel1[1..0]
datae1
dataf1
In a sparsely used device, functions that can be placed into one ALM can be
implemented in separate ALMs. The Quartus II Compiler spreads a design out to
achieve the best possible performance. As a device begins to fill up, the Quartus II
software automatically uses the full potential of the Arria GX ALM. The Quartus II
Compiler automatically searches for functions of common inputs or completely
independent functions to be placed into one ALM and to make efficient use of the
device resources. In addition, you can manually control resource usage by setting
location assignments. Any six-input function can be implemented utilizing inputs
dataa, datab, datac, datad, and either datae0 and dataf0 or datae1 and
dataf1. If datae0 and dataf0 are used, the output is driven to register0,
and/or register0 is bypassed and the data drives out to the interconnect using the
top set of output drivers (refer to Figure 2–32). If datae1 and dataf1 are used, the
output drives to register1 and/or bypasses register1 and drives to the
interconnect using the bottom set of output drivers. The Quartus II Compiler
automatically selects the inputs to the LUT. Asynchronous load data for the register
comes from the datae or dataf input of the ALM. ALMs in normal mode support
register packing.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
Adaptive Logic Modules
2–37
Figure 2–32. Six-Input Function in Normal Mode Note (1), (2)
dataf0
datae0
dataa
datab
datac
datad
To general or
local routing
6-Input
LUT
D
Q
To general or
local routing
reg0
datae1
dataf1
(2)
D
These inputs are available for register packing.
Q
To general or
local routing
reg1
Notes to Figure 2–32:
(1) If datae1 and dataf1 are used as inputs to the six-input function, datae0 and dataf0 are available for register
packing.
(2) The dataf1 input is available for register packing only if the six-input function is un-registered.
Extended LUT Mode
Extended LUT mode is used to implement a specific set of seven-input functions. The
set must be a 2-to-1 multiplexer fed by two arbitrary five-input functions sharing four
inputs. Figure 2–33 shows the template of supported seven-input functions utilizing
extended LUT mode. In this mode, if the seven-input function is unregistered, the
unused eighth input is available for register packing. Functions that fit into the
template shown in Figure 2–33 occur naturally in designs. These functions often
appear in designs as “if-else” statements in Verilog HDL or VHDL code.
Figure 2–33. Template for Supported Seven-Input Functions in Extended LUT Mode
datae0
datac
dataa
datab
datad
dataf0
5-Input
LUT
To general or
local routing
combout0
D
5-Input
LUT
Q
To general or
local routing
reg0
datae1
dataf1
(1)
This input is available
for register packing.
Note to Figure 2–33:
(1) If the seven-input function is unregistered, the unused eighth input is available for register packing. The second register, reg1, is not available.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–38
Chapter 2: Arria GX Architecture
Adaptive Logic Modules
Arithmetic Mode
Arithmetic mode is ideal for implementing adders, counters, accumulators, wide
parity functions, and comparators. An ALM in arithmetic mode uses two sets of 2
four-input LUTs along with two dedicated full adders. The dedicated adders allow
the LUTs to be available to perform pre-adder logic; therefore, each adder can add the
output of two four-input functions. The four LUTs share the dataa and datab
inputs. As shown in Figure 2–34, the carry-in signal feeds to adder0, and the
carry-out from adder0 feeds to carry-in of adder1. The carry-out from adder1
drives to adder0 of the next ALM in the LAB. ALMs in arithmetic mode can drive
out registered and/or unregistered versions of the adder outputs.
Figure 2–34. ALM in Arithmetic Mode
carry_in
adder0
datae0
4-Input
LUT
To general or
local routing
D
dataf0
datac
datab
dataa
Q
To general or
local routing
reg0
4-Input
LUT
adder1
datad
datae1
4-Input
LUT
To general or
local routing
D
4-Input
LUT
Q
To general or
local routing
reg1
dataf1
carry_out
While operating in arithmetic mode, the ALM can support simultaneous use of the
adder’s carry output along with combinational logic outputs. In this operation, adder
output is ignored. This usage of the adder with the combinational logic output
provides resource savings of up to 50% for functions that can use this ability. An
example of such functionality is a conditional operation, such as the one shown in
Figure 2–35. The equation for this example is:
Equation 2–1.
R = (X < Y) ? Y : X
To implement this function, the adder is used to subtract ‘Y’ from ‘X.’ If ‘X’ is less than
‘Y,’ the carry_out signal is ‘1.’ The carry_out signal is fed to an adder where it
drives out to the LAB local interconnect. It then feeds to the LAB-wide syncload
signal. When asserted, syncload selects the syncdata input. In this case, the data
‘Y’ drives the syncdata inputs to the registers. If ‘X’ is greater than or equal to ‘Y,’ the
syncload signal is deasserted and ‘X’ drives the data port of the registers.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
Adaptive Logic Modules
2–39
Figure 2–35. Conditional Operation Example
Adder output
is not used.
ALM 1
X[0]
Comb &
Adder
Logic
Y[0]
X[0]
D
R[0]
To general or
local routing
R[1]
To general or
local routing
R[2]
To general or
local routing
Q
reg0
syncdata
syncload
X[1]
Comb &
Adder
Logic
Y[1]
X[1]
D
Q
reg1
syncload
Carry Chain
ALM 2
X[2]
Y[2]
Comb &
Adder
Logic
X[2]
D
Q
reg0
syncload
Comb &
Adder
Logic
carry_out
To local routing &
then to LAB-wide
syncload
Arithmetic mode also offers clock enable, counter enable, synchronous up/down
control, add/subtract control, synchronous clear, and synchronous load. The LAB
local interconnect data inputs generate the clock enable, counter enable, synchronous
up/down and add/subtract control signals. These control signals can be used for the
inputs that are shared between the four LUTs in the ALM. The synchronous clear and
synchronous load options are LAB-wide signals that affect all registers in the LAB.
The Quartus II software automatically places any registers that are not used by the
counter into other LABs.
Carry Chain
Carry chain provides a fast carry function between the dedicated adders in arithmetic
or shared arithmetic mode. Carry chains can begin in either the first ALM or the fifth
ALM in a LAB. The final carry-out signal is routed to an ALM, where it is fed to local,
row, or column interconnects.
The Quartus II Compiler automatically creates carry chain logic during compilation,
or you can create it manually during design entry. Parameterized functions such as
LPM functions automatically take advantage of carry chains for the appropriate
functions. The Quartus II Compiler creates carry chains longer than 16 (8 ALMs in
arithmetic or shared arithmetic mode) by linking LABs together automatically. For
enhanced fitting, a long carry chain runs vertically allowing fast horizontal
connections to TriMatrix memory and DSP blocks. A carry chain can continue as far as
a full column. To avoid routing congestion in one small area of the device when a high
fan-in arithmetic function is implemented, the LAB can support carry chains that only
use either the top half or bottom half of the LAB before connecting to the next LAB.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–40
Chapter 2: Arria GX Architecture
Adaptive Logic Modules
The other half of the ALMs in the LAB is available for implementing narrower fan-in
functions in normal mode. Carry chains that use the top four ALMs in the first LAB
carries into the top half of the ALMs in the next LAB within the column. Carry chains
that use the bottom four ALMs in the first LAB carries into the bottom half of the
ALMs in the next LAB within the column. Every other column of the LABs are
top-half bypassable, while the other LAB columns are bottom-half bypassable. For
more information about carry chain interconnect, refer to “MultiTrack Interconnect”
on page 2–44.
Shared Arithmetic Mode
In shared arithmetic mode, the ALM can implement a three-input add. In this mode,
the ALM is configured with four 4-input LUTs. Each LUT either computes the sum of
three inputs or the carry of three inputs. The output of the carry computation is fed to
the next adder (either to adder1 in the same ALM or to adder0 of the next ALM in
the LAB) using a dedicated connection called the shared arithmetic chain. This shared
arithmetic chain can significantly improve the performance of an adder tree by
reducing the number of summation stages required to implement an adder tree.
Figure 2–36 shows the ALM in shared arithmetic mode.
Figure 2–36. ALM in Shared Arithmetic Mode
shared_arith_in
carry_in
4-Input
LUT
To general or
local routing
D
datae0
datac
datab
dataa
datad
datae1
Q
To general or
local routing
reg0
4-Input
LUT
4-Input
LUT
To general or
local routing
D
4-Input
LUT
Q
To general or
local routing
reg1
carry_out
shared_arith_out
Note to Figure 2–36:
(1) Inputs dataf0 and dataf1 are available for register packing in shared arithmetic mode.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
Adaptive Logic Modules
2–41
Adder trees are used in many different applications. For example, the summation of
partial products in a logic-based multiplier can be implemented in a tree structure.
Another example is a correlator function that can use a large adder tree to sum filtered
data samples in a given time frame to recover or to de-spread data which was
transmitted utilizing spread spectrum technology. An example of a three-bit add
operation utilizing the shared arithmetic mode is shown in Figure 2–37. The partial
sum (S[2..0]) and the partial carry (C[2..0]) is obtained using LUTs, while the
result (R[2..0]) is computed using dedicated adders.
Figure 2–37. Example of a 3-Bit Add Utilizing Shared Arithmetic Mode
shared_arith_in = '0'
carry_in = '0'
3-Bit Add Example
ALM Implementation
ALM 1
1st stage add is
implemented in LUTs.
X2 X1 X0
Y2 Y1 Y0
+ Z2 Z1 Z0
2nd stage add is
implemented in adders.
S2 S1 S0
+ C2 C1 C0
R3 R2 R1 R0
Binary Add
Decimal
Equivalents
1 1 0
1 0 1
+ 0 1 0
6
5
+ 2
0 0 1
+ 1 1 0
1
+ 2x6
1 1 0 1
13
3-Input
LUT
S0
R0
X0
Y0
Z0
3-Input
LUT
C0
X1
Y1
Z1
3-Input
LUT
S1
R1
3-Input
LUT
C1
3-Input
LUT
S2
ALM 2
R2
X2
Y2
Z2
3-Input
LUT
C2
3-Input
LUT
'0'
R3
3-Input
LUT
Shared Arithmetic Chain
In addition to dedicated carry chain routing, the shared arithmetic chain available in
shared arithmetic mode allows the ALM to implement a three-input add, which
significantly reduces the resources necessary to implement large adder trees or
correlator functions. Shared arithmetic chains can begin in either the first or fifth ALM
in a LAB. The Quartus II Compiler automatically links LABs to create shared
arithmetic chains longer than 16 (eight ALMs in arithmetic or shared arithmetic
mode). For enhanced fitting, a long shared arithmetic chain runs vertically allowing
fast horizontal connections to TriMatrix memory and DSP blocks. A shared arithmetic
chain can continue as far as a full column. Similar to carry chains, shared arithmetic
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–42
Chapter 2: Arria GX Architecture
Adaptive Logic Modules
chains are also top- or bottom-half bypassable. This capability allows the shared
arithmetic chain to cascade through half of the ALMs in a LAB while leaving the other
half available for narrower fan-in functionality. Every other LAB column is top-half
bypassable, while the other LAB columns are bottom-half bypassable. For more
information about shared arithmetic chain interconnect, refer to “MultiTrack
Interconnect” on page 2–44.
Register Chain
In addition to the general routing outputs, the ALMs in a LAB have register chain
outputs. Register chain routing allows registers in the same LAB to be cascaded
together. The register chain interconnect allows a LAB to use LUTs for a single
combinational function and the registers to be used for an unrelated shift register
implementation. These resources speed up connections between ALMs while saving
local interconnect resources (refer to Figure 2–38). The Quartus II Compiler
automatically takes advantage of these resources to improve utilization and
performance. For more information about register chain interconnect, refer to
“MultiTrack Interconnect” on page 2–44.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
Adaptive Logic Modules
Figure 2–38. Register Chain within a LAB
2–43
(Note 1)
From Previous ALM
Within The LAB
reg_chain_in
To general or
local routing
adder0
D
Q
To general or
local routing
reg0
Combinational
Logic
adder1
D
Q
To general or
local routing
reg1
To general or
local routing
To general or
local routing
adder0
D
Q
To general or
local routing
reg0
Combinational
Logic
adder1
D
Q
To general or
local routing
reg1
To general or
local routing
reg_chain_out
To Next ALM
within the LAB
Note to Figure 2–38:
(1) The combinational or adder logic can be used to implement an unrelated, unregistered function.
Clear and Preset Logic Control
LAB-wide signals control the logic for the register ’s clear and load/preset signals. The
ALM directly supports an asynchronous clear and preset function. The register preset
is achieved through the asynchronous load of a logic high. The direct asynchronous
preset does not require a NOT gate push-back technique. Arria GX devices support
simultaneous asynchronous load/preset and clear signals. An asynchronous clear
signal takes precedence if both signals are asserted simultaneously. Each LAB
supports up to two clears and one load/preset signal.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–44
Chapter 2: Arria GX Architecture
MultiTrack Interconnect
In addition to the clear and load/preset ports, Arria GX devices provide a
device-wide reset pin (DEV_CLRn) that resets all registers in the device. An option set
before compilation in the Quartus II software controls this pin. This device-wide reset
overrides all other control signals.
MultiTrack Interconnect
In Arria GX architecture, the MultiTrack interconnect structure with DirectDrive
technology provides connections between ALMs, TriMatrix memory, DSP blocks, and
device I/O pins. The MultiTrack interconnect consists of continuous,
performance-optimized routing lines of different lengths and speeds used for interand intra-design block connectivity. The Quartus II Compiler automatically places
critical design paths on faster interconnects to improve design performance.
DirectDrive technology is a deterministic routing technology that ensures identical
routing resource usage for any function regardless of placement in the device. The
MultiTrack interconnect and DirectDrive technology simplify the integration stage of
block-based designing by eliminating the re-optimization cycles that typically follow
design changes and additions.
The MultiTrack interconnect consists of row and column interconnects that span fixed
distances. A routing structure with fixed length resources for all devices allows
predictable and repeatable performance when migrating through different device
densities. Dedicated row interconnects route signals to and from LABs, DSP blocks,
and TriMatrix memory in the same row.
These row resources include:
■
Direct link interconnects between LABs and adjacent blocks
■
R4 interconnects traversing four blocks to the right or left
■
R24 row interconnects for high-speed access across the length of the device
The direct link interconnect allows a LAB, DSP block, or TriMatrix memory block to
drive into the local interconnect of its left and right neighbors and then back into
itself, providing fast communication between adjacent LABs and/or blocks without
using row interconnect resources.
The R4 interconnects span four LABs, three LABs and one M512 RAM block, two
LABs and one M4K RAM block, or two LABs and one DSP block to the right or left of
a source LAB. These resources are used for fast row connections in a four-LAB region.
Every LAB has its own set of R4 interconnects to drive either left or right. Figure 2–39
shows R4 interconnect connections from a LAB.
R4 interconnects can drive and be driven by DSP blocks and RAM blocks and row
IOEs. For LAB interfacing, a primary LAB or LAB neighbor can drive a given R4
interconnect. For R4 interconnects that drive to the right, the primary LAB and right
neighbor can drive onto the interconnect. For R4 interconnects that drive to the left,
the primary LAB and its left neighbor can drive onto the interconnect. R4
interconnects can drive other R4 interconnects to extend the range of LABs they can
drive. R4 interconnects can also drive C4 and C16 interconnects for connections from
one row to another. Additionally, R4 interconnects can drive R24 interconnects.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
MultiTrack Interconnect
2–45
Figure 2–39. R4 Interconnect Connections
(Note 1), (2), (3)
Adjacent LAB can
Drive onto Another
LAB's R4 Interconnect
C4 and C16
Column Interconnects (1)
R4 Interconnect
Driving Right
R4 Interconnect
Driving Left
LAB
Neighbor
Primary
LAB (2)
LAB
Neighbor
Notes to Figure 2–39:
(1) C4 and C16 interconnects can drive R4 interconnects.
(2) This pattern is repeated for every LAB in the LAB row.
(3) The LABs in Figure 2–39 show the 16 possible logical outputs per LAB.
R24 row interconnects span 24 LABs and provide the fastest resource for long row
connections between LABs, TriMatrix memory, DSP blocks, and row IOEs. The R24
row interconnects can cross M-RAM blocks. R24 row interconnects drive to other row
or column interconnects at every fourth LAB and do not drive directly to LAB local
interconnects. R24 row interconnects drive LAB local interconnects via R4 and C4
interconnects. R24 interconnects can drive R24, R4, C16, and C4 interconnects. The
column interconnect operates similarly to the row interconnect and vertically routes
signals to and from LABs, TriMatrix memory, DSP blocks, and IOEs. Each column of
LABs is served by a dedicated column interconnect.
These column resources include:
■
Shared arithmetic chain interconnects in a LAB
■
Carry chain interconnects in a LAB and from LAB to LAB
■
Register chain interconnects in a LAB
■
C4 interconnects traversing a distance of four blocks in up and down direction
■
C16 column interconnects for high-speed vertical routing through the device
Arria GX devices include an enhanced interconnect structure in LABs for routing
shared arithmetic chains and carry chains for efficient arithmetic functions. The
register chain connection allows the register output of one ALM to connect directly to
the register input of the next ALM in the LAB for fast shift registers. These
ALM-to-ALM connections bypass the local interconnect. The Quartus II Compiler
automatically takes advantage of these resources to improve utilization and
performance. Figure 2–40 shows shared arithmetic chain, carry chain, and register
chain interconnects.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–46
Chapter 2: Arria GX Architecture
MultiTrack Interconnect
Figure 2–40. Shared Arithmetic Chain, Carry Chain and Register Chain Interconnects
Local Interconnect
Routing Among ALMs
in the LAB
Carry Chain & Shared
Arithmetic Chain
Routing to Adjacent ALM
ALM 1
Register Chain
Routing to Adjacent
ALM's Register Input
ALM 2
Local
Interconnect
ALM 3
ALM 4
ALM 5
ALM 6
ALM 7
ALM 8
C4 interconnects span four LABs, M512, or M4K blocks up or down from a source
LAB. Every LAB has its own set of C4 interconnects to drive either up or down.
Figure 2–41 shows the C4 interconnect connections from a LAB in a column. C4
interconnects can drive and be driven by all types of architecture blocks, including
DSP blocks, TriMatrix memory blocks, and column and row IOEs. For LAB
interconnection, a primary LAB or its LAB neighbor can drive a given C4
interconnect. C4 interconnects can drive each other to extend their range as well as
drive row interconnects for column-to-column connections.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
MultiTrack Interconnect
Figure 2–41. C4 Interconnect Connections
2–47
(Note 1)
C4 Interconnect
Drives Local and R4
Interconnects
up to Four Rows
C4 Interconnect
Driving Up
LAB
Row
Interconnect
Adjacent LAB can
drive onto neighboring
LAB's C4 interconnect
Local
Interconnect
C4 Interconnect
Driving Down
Note to Figure 2–41:
(1) Each C4 interconnect can drive either up or down four rows.
C16 column interconnects span a length of 16 LABs and provide the fastest resource
for long column connections between LABs, TriMatrix memory blocks, DSP blocks,
and IOEs. C16 interconnects can cross M-RAM blocks and also drive to row and
column interconnects at every fourth LAB. C16 interconnects drive LAB local
interconnects via C4 and R4 interconnects and do not drive LAB local interconnects
directly. All embedded blocks communicate with the logic array similar to
LAB-to-LAB interfaces. Each block (that is, TriMatrix memory and DSP blocks)
connects to row and column interconnects and has local interconnect regions driven
by row and column interconnects. These blocks also have direct link interconnects for
fast connections to and from a neighboring LAB. All blocks are fed by the row LAB
clocks, labclk[5..0].
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–48
Chapter 2: Arria GX Architecture
TriMatrix Memory
Table 2–10 lists the routing scheme for Arria GX device.
Table 2–10. Arria GX Device Routing Scheme
Shared Arithmetic Chain
Carry Chain
Register Chain
Local Interconnect
Direct Link Interconnect
R4 Interconnect
R24 Interconnect
C4 Interconnect
C16 Interconnect
ALM
M512 RAM Block
M4K RAM Block
M-RAM Block
DSP Blocks
Column IOE
Row IOE
Destination
Shared arithmetic chain
—
—
—
—
—
—
—
—
—
v
—
—
—
—
—
—
Carry chain
—
—
—
—
—
—
—
—
—
v
—
—
—
—
—
—
Register chain
—
—
—
—
—
—
—
—
—
v
—
—
—
—
—
—
Local interconnect
—
—
—
—
—
—
—
—
—
v
v
v
v
v
v
v
Direct link interconnect
—
—
—
v
—
—
—
—
—
—
—
—
—
—
—
—
R4 interconnect
—
—
—
v
—
v
v
v
v
—
—
—
—
—
—
—
R24 interconnect
—
—
—
—
—
v
v
v
v
—
—
—
—
—
—
—
C4 interconnect
—
—
—
v
—
v
—
v
—
—
—
—
—
—
—
—
C16 interconnect
—
—
—
—
—
v
v
v
v
—
—
—
—
—
—
—
ALM
v
v
v
v
v
v
—
v
—
—
—
—
—
—
—
—
M512 RAM block
—
—
—
v
v
v
—
v
—
—
—
—
—
—
—
—
M4K RAM block
—
—
—
v
v
v
—
v
—
—
—
—
—
—
—
—
M-RAM block
—
—
—
—
v
v
v
v
—
—
—
—
—
—
—
—
DSP blocks
—
—
—
—
v
v
—
v
—
—
—
—
—
—
—
—
Column IOE
—
—
—
—
v
—
—
v
v
—
—
—
—
—
—
—
Row IOE
—
—
—
—
v
v
v
v
—
—
—
—
—
—
—
—
Source
TriMatrix Memory
TriMatrix memory consists of three types of RAM blocks: M512, M4K, and M-RAM.
Although these memory blocks are different, they can all implement various types of
memory with or without parity, including true dual-port, simple dual-port, and
single-port RAM, ROM, and FIFO buffers. Table 2–11 lists the size and features of the
different RAM blocks.
Table 2–11. TriMatrix Memory Features (Part 1 of 2)
M512 RAM Block
(32 × 18 Bits)
M4K RAM Block
(128 × 36 Bits)
M-RAM Block
(4K × 144 Bits)
Maximum performance
345 MHz
380 MHz
290 MHz
True dual-port memory
—
v
v
Simple dual-port memory
v
v
v
Single-port memory
v
v
v
Shift register
v
v
—
Memory Feature
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
TriMatrix Memory
2–49
Table 2–11. TriMatrix Memory Features (Part 2 of 2)
Memory Feature
M512 RAM Block
(32 × 18 Bits)
M4K RAM Block
(128 × 36 Bits)
M-RAM Block
(4K × 144 Bits)
ROM
v
v
—
FIFO buffer
v
v
v
Pack mode
—
v
v
Byte enable
v
v
v
Address clock enable
—
v
v
Parity bits
v
v
v
Mixed clock mode
v
v
v
Memory initialization file (.mif)
v
v
—
Simple dual-port memory mixed width support
v
v
v
True dual-port memory mixed width support
—
v
v
Power-up conditions
Outputs cleared
Outputs cleared
Outputs unknown
Register clears
Output registers
Output registers
Output registers
Unknown output/old
data
Unknown output/old
data
Unknown output
Mixed-port read-during-write
4K × 1
Configurations
512 × 1
2K × 2
256 × 2
1K × 4
128 × 4
512 × 8
64 × 8
512 × 9
64 × 9
256 × 16
32 × 16
256 × 18
32 × 18
128 × 32
128 × 36
64K × 8
64K × 9
32K × 16
32K × 18
16K × 32
16K × 36
8K × 64
8K × 72
4K × 128
4K × 144
TriMatrix memory provides three different memory sizes for efficient application
support. The Quartus II software automatically partitions the user-defined memory
into the embedded memory blocks using the most efficient size combinations. You can
also manually assign the memory to a specific block size or a mixture of block sizes.
M512 RAM Block
The M512 RAM block is a simple dual-port memory block and is useful for
implementing small FIFO buffers, DSP, and clock domain transfer applications. Each
block contains 576 RAM bits (including parity bits). M512 RAM blocks can be
configured in the following modes:
© December 2009
■
Simple dual-port RAM
■
Single-port RAM
■
FIFO
■
ROM
■
Shift register
Altera Corporation
Arria GX Device Handbook, Volume 1
2–50
Chapter 2: Arria GX Architecture
TriMatrix Memory
When configured as RAM or ROM, you can use an initialization file to pre-load the
memory contents.
M512 RAM blocks can have different clocks on its inputs and outputs. The wren,
datain, and write address registers are all clocked together from one of the two
clocks feeding the block. The read address, rden, and output registers can be clocked
by either of the two clocks driving the block, allowing the RAM block to operate in
read and write or input and output clock modes. Only the output register can be
bypassed. The six labclk signals or local interconnect can drive the inclock,
outclock, wren, rden, and outclr signals. Because of the advanced interconnect
between the LAB and M512 RAM blocks, ALMs can also control the wren and rden
signals and the RAM clock, clock enable, and asynchronous clear signals. Figure 2–42
shows the M512 RAM block control signal generation logic.
Figure 2–42. M512 RAM Block Control Signals
Dedicated
Row LAB
Clocks
6
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
outclocken
inclocken
Local
Interconnect
inclock
outclock
wren
rden
outclr
The RAM blocks in Arria GX devices have local interconnects to allow ALMs and
interconnects to drive into RAM blocks. The M512 RAM block local interconnect is
driven by the R4, C4, and direct link interconnects from adjacent LABs. The M512
RAM blocks can communicate with LABs on either the left or right side through these
row interconnects or with LAB columns on the left or right side with the column
interconnects. The M512 RAM block has up to 16 direct link input connections from
the left adjacent LABs and another 16 from the right adjacent LAB. M512 RAM
outputs can also connect to left and right LABs through direct link interconnect. The
M512 RAM block has equal opportunity for access and performance to and from
LABs on either its left or right side. Figure 2–43 shows the M512 RAM block to logic
array interface.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
TriMatrix Memory
2–51
Figure 2–43. M512 RAM Block LAB Row Interface
C4 Interconnect
R4 Interconnect
16
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
to adjacent LAB
36
dataout
M4K RAM
Block
Direct link
interconnect
from adjacent LAB
Direct link
interconnect
from adjacent LAB
datain
control
signals
byte
enable
clocks
address
6
M4K RAM Block Local
Interconnect Region
LAB Row Clocks
M4K RAM Blocks
The M4K RAM block includes support for true dual-port RAM. The M4K RAM block
is used to implement buffers for a wide variety of applications such as storing
processor code, implementing lookup schemes, and implementing larger memory
applications. Each block contains 4,608 RAM bits (including parity bits). M4K RAM
blocks can be configured in the following modes:
■
True dual-port RAM
■
Simple dual-port RAM
■
Single-port RAM
■
FIFO
■
ROM
■
Shift register
When configured as RAM or ROM, you can use an initialization file to pre-load the
memory contents.
M4K RAM blocks allow for different clocks on their inputs and outputs. Either of the
two clocks feeding the block can clock M4K RAM block registers (renwe, address,
byte enable, datain, and output registers). Only the output register can be
bypassed. The six labclk signals or local interconnects can drive the control signals
for the A and B ports of the M4K RAM block. ALMs can also control the clock_a,
clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and clocken_b
signals, as shown in Figure 2–44.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–52
Chapter 2: Arria GX Architecture
TriMatrix Memory
Figure 2–44. M4K RAM Block Control Signals
Dedicated
Row LAB
Clocks
6
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
clocken_b
clock_b
Local
Interconnect
clock_a
clocken_a
renwe_b
renwe_a
aclr_b
aclr_a
The R4, C4, and direct link interconnects from adjacent LABs drive the M4K RAM
block local interconnect. The M4K RAM blocks can communicate with LABs on either
the left or right side through these row resources or with LAB columns on either the
right or left with the column resources. Up to 16 direct link input connections to the
M4K RAM block are possible from the left adjacent LABs and another 16 are possible
from the right adjacent LAB. M4K RAM block outputs can also connect to left and
right LABs through direct link interconnect. Figure 2–45 shows the M4K RAM block
to logic array interface.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
TriMatrix Memory
2–53
Figure 2–45. M4K RAM Block LAB Row Interface
C4 Interconnect
R4 Interconnect
16
Direct link
interconnect
to adjacent LAB
Direct link
interconnect
to adjacent LAB
36
dataout
M4K RAM
Block
Direct link
interconnect
from adjacent LAB
Direct link
interconnect
from adjacent LAB
datain
control
signals
byte
enable
clocks
address
6
M4K RAM Block Local
Interconnect Region
LAB Row Clocks
M-RAM Block
The largest TriMatrix memory block, the M-RAM block, is useful for applications
where a large volume of data must be stored on-chip. Each block contains 589,824
RAM bits (including parity bits). The M-RAM block can be configured in the
following modes:
■
True dual-port RAM
■
Simple dual-port RAM
■
Single-port RAM
■
FIFO
You cannot use an initialization file to initialize the contents of a M-RAM block. All
M-RAM block contents power up to an undefined value. Only synchronous operation
is supported in the M-RAM block, so all inputs are registered. Output registers can be
bypassed.
Similar to all RAM blocks, M-RAM blocks can have different clocks on their inputs
and outputs. Either of the two clocks feeding the block can clock M-RAM block
registers (renwe, address, byte enable, datain, and output registers). You can
bypass the output register. The six labclk signals or local interconnect can drive the
control signals for the A and B ports of the M-RAM block. ALMs can also control the
clock_a, clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, and
clocken_b signals, as shown in Figure 2–46.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–54
Chapter 2: Arria GX Architecture
TriMatrix Memory
Figure 2–46. M-RAM Block Control Signals
Dedicated
Row LAB
Clocks
6
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
Local
Interconnect
clocken_a
Local
Interconnect
clock_a
renwe_a
aclr_a
clock_b
aclr_b
renwe_b
Local
Interconnect
clocken_b
The R4, R24, C4, and direct link interconnects from adjacent LABs on either the right
or left side drive the M-RAM block local interconnect. Up to 16 direct link input
connections to the M-RAM block are possible from the left adjacent LABs and another
16 are possible from the right adjacent LAB. M-RAM block outputs can also connect to
left and right LABs through direct link interconnect. Figure 2–47 shows an example
floorplan for the EP1AGX90 device and the location of the M-RAM interfaces.
Figure 2–48 and Figure 2–49 show the interface between the M-RAM block and the
logic array.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
TriMatrix Memory
2–55
Figure 2–47. EP1AGX90 Device with M-RAM Interface Locations
(Note 1)
M-RAM blocks interface to
LABs on right and left sides for
easy access to horizontal I/O pins
M4K
Blocks
M-RAM
Block
M-RAM
Block
M-RAM
Block
M-RAM
Block
M512
Blocks
DSP
Blocks
LABs
DSP
Blocks
Note to Figure 2–47:
(1) The device shown is an EP1AGX90 device. The number and position of M-RAM blocks vary in other devices.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–56
Chapter 2: Arria GX Architecture
TriMatrix Memory
Figure 2–48. M-RAM Block LAB Row Interface (Note 1)
Row Unit Interface Allows LAB
Rows to Drive Port A Datain,
Dataout, Address and Control
Signals to and from M-RAM Block
Row Unit Interface Allows LAB
Rows to Drive Port B Datain,
Dataout, Address and Control
Signals to and from M-RAM Block
L0
R0
L1
R1
M-RAM Block
L2
Port A
Port B R2
L3
R3
L4
R4
L5
R5
LAB Interface
Blocks
LABs in Row
M-RAM Boundary
LABs in Row
M-RAM Boundary
Note to Figure 2–48:
(1) Only R24 and C16 interconnects cross the M-RAM block boundaries.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
TriMatrix Memory
2–57
Figure 2–49. M-RAM Row Unit Interface to Interconnect
C4 Interconnect
R4 and R24 Interconnects
M-RAM Block
LAB
Up to 16
dataout_a[ ]
16
Up to 28
Direct Link
Interconnects
datain_a[ ]
addressa[ ]
addr_ena_a
renwe_a
byteenaA[ ]
clocken_a
clock_a
aclr_a
Row Interface Block
M-RAM Block to
LAB Row Interface
Block Interconnect Region
Table 2–12 lists the input and output data signal connections along with the address
and control signal input connections to the row unit interfaces (L0 to L5 and R0 to R5).
Table 2–12. M-RAM Row Interface Unit Signals (Part 1 of 2)
Unit Interface Block
L0
Input Signals
datain_a[14..0]
Output Signals
dataout_a[11..0]
byteena_a[1..0]
L1
datain_a[29..15]
dataout_a[23..12]
byteena_a[3..2]
datain_a[35..30]
dataout_a[35..24]
addressa[4..0]
addr_ena_a
L2
clock_a
clocken_a
renwe_a
aclr_a
L3
addressa[15..5]
dataout_a[47..36]
datain_a[41..36]
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–58
Chapter 2: Arria GX Architecture
Digital Signal Processing Block
Table 2–12. M-RAM Row Interface Unit Signals (Part 2 of 2)
Unit Interface Block
L4
Input Signals
datain_a[56..42]
Output Signals
dataout_a[59..48]
byteena_a[5..4]
L5
datain_a[71..57]
dataout_a[71..60]
byteena_a[7..6]
R0
datain_b[14..0]
dataout_b[11..0]
byteena_b[1..0]
R1
datain_b[29..15]
dataout_b[23..12]
byteena_b[3..2]
datain_b[35..30]
dataout_b[35..24]
addressb[4..0]
addr_ena_b
R2
clock_b
clocken_b
renwe_b
aclr_b
R3
addressb[15..5]
dataout_b[47..36]
datain_b[41..36]
R4
datain_b[56..42]
dataout_b[59..48]
byteena_b[5..4]
R5
datain_b[71..57]
dataout_b[71..60]
byteena_b[7..6]
f
For more information about TriMatrix memory, refer to the TriMatrix Embedded
Memory Blocks in Arria GX Devices chapter.
Digital Signal Processing Block
The most commonly used DSP functions are finite impulse response (FIR) filters,
complex FIR filters, infinite impulse response (IIR) filters, fast Fourier transform (FFT)
functions, direct cosine transform (DCT) functions, and correlators. All of these use
the multiplier as the fundamental building block. Additionally, some applications
need specialized operations such as multiply-add and multiply-accumulate
operations. Arria GX devices provide DSP blocks to meet the arithmetic requirements
of these functions.
Each Arria GX device has two to four columns of DSP blocks to efficiently implement
DSP functions faster than ALM-based implementations. Each DSP block can be
configured to support up to:
■
Eight 9 × 9-bit multipliers
■
Four 18 × 18-bit multipliers
■
One 36 × 36-bit multiplier
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
Digital Signal Processing Block
2–59
As indicated, the Arria GX DSP block can support one 36 × 36-bit multiplier in a
single DSP block and is true for any combination of signed, unsigned, or mixed sign
multiplications.
Figure 2–50 shows one of the columns with surrounding LAB rows.
Figure 2–50. DSP Blocks Arranged in Columns
DSP Block
Column
4 LAB
Rows
DSP Block
Table 2–13 lists the number of DSP blocks in each Arria GX device. DSP block
multipliers can optionally feed an adder/subtractor or accumulator in the block
depending on the configuration, which makes routing to ALMs easier, saves ALM
routing resources, and increases performance because all connections and blocks are
in the DSP block.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–60
Chapter 2: Arria GX Architecture
Digital Signal Processing Block
Table 2–13. DSP Blocks in Arria GX Devices (Note 1)
DSP Blocks
Total 9 × 9
Multipliers
Total 18 × 18
Multipliers
Total 36 × 36
Multipliers
EP1AGX20
10
80
40
10
EP1AGX35
14
112
56
14
EP1AGX50
26
208
104
26
EP1AGX60
32
256
128
32
EP1AGX90
44
352
176
44
Device
Note to Table 2–13:
(1) This list only shows functions that can fit into a single DSP block. Multiple DSP blocks can support larger
multiplication functions.
Additionally, DSP block input registers can efficiently implement shift registers for
FIR filter applications. DSP blocks support Q1.15 format rounding and saturation.
Figure 2–51 shows a top-level diagram of the DSP block configured for 18 × 18-bit
multiplier mode.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
Digital Signal Processing Block
2–61
Figure 2–51. DSP Block Diagram for 18 × 18-Bit Configuration
Optional Serial Shift Register
Inputs from Previous
DSP Block
Multiplier Stage
D
ENA
CLRN
D
Optional Stage Configurable
as Accumulator or Dynamic
Adder/Subtractor
Q
Q
D
Output Selection
Multiplexer
Q
ENA
CLRN
ENA
CLRN
Adder/
Subtractor/
Accumulator
1
D
Q
ENA
CLRN
D
Q
D
Q
ENA
CLRN
ENA
CLRN
Summation
D
Q
ENA
CLRN
D
Q
D
Q
Summation Stage
for Adding Four
Multipliers Together
ENA
CLRN
Optional Output
Register Stage
ENA
CLRN
Adder/
Subtractor/
Accumulator
2
D
Optional Serial
Shift Register
Outputs to
Next DSP Block
in the Column
Q
ENA
CLRN
D
Q
ENA
CLRN
© December 2009
Altera Corporation
D
Q
ENA
CLRN
Optional Pipeline
Register Stage
Optional Input Register
Stage with Parallel Input or
Shift Register Configuration
to MultiTrack
Interconnect
Arria GX Device Handbook, Volume 1
2–62
Chapter 2: Arria GX Architecture
Digital Signal Processing Block
Modes of Operation
The adder, subtractor, and accumulate functions of a DSP block have four modes of
operation:
■
Simple multiplier
■
Multiply-accumulator
■
Two-multipliers adder
■
Four-multipliers adder
Table 2–14 shows the different number of multipliers possible in each DSP block
mode according to size. These modes allow the DSP blocks to implement numerous
applications for DSP including FFTs, complex FIR, FIR, 2D FIR filters, equalizers, IIR,
correlators, matrix multiplication, and many other functions. DSP blocks also support
mixed modes and mixed multiplier sizes in the same block. For example, half of one
DSP block can implement one 18 × 18-bit multiplier in multiply-accumulator mode,
while the other half of the DSP block implements four 9 × 9-bit multipliers in simple
multiplier mode.
Table 2–14. Multiplier Size and Configurations per DSP Block
DSP Block Mode
Multiplier
9×9
Eight multipliers with eight
product outputs
Multiply-accumulator
—
18 × 18
Four multipliers with four
product outputs
36 × 36
One multiplier with one
product output
Two 52-bit
multiply-accumulate blocks
—
Two-multipliers adder
Four two-multiplier adder (two
9 × 9 complex multiply)
Two two-multiplier adder (one
18 × 18 complex multiply)
—
Four-multipliers adder
Two four-multiplier adder
One four-multiplier adder
—
DSP Block Interface
The Arria GX device DSP block input registers can generate a shift register that can
cascade down in the same DSP block column. Dedicated connections between DSP
blocks provide fast connections between shift register inputs to cascade shift register
chains. You can cascade registers within multiple DSP blocks for 9 × 9- or 18 × 18-bit
FIR filters larger than four taps, with additional adder stages implemented in ALMs.
If the DSP block is configured as 36 × 36 bits, the adder, subtractor, or accumulator
stages are implemented in ALMs. Each DSP block can route the shift register chain
out of the block to cascade multiple columns of DSP blocks.
The DSP block is divided into four block units that interface with four LAB rows on
the left and right. Each block unit can be considered one complete 18 × 18-bit
multiplier with 36 inputs and 36 outputs. A local interconnect region is associated
with each DSP block. Like an LAB, this interconnect region can be fed with 16 direct
link interconnects from the LAB to the left or right of the DSP block in the same row.
R4 and C4 routing resources can access the DSP block’s local interconnect region.
The outputs also work similarly to LAB outputs. Eighteen outputs from the DSP block
can drive to the left LAB through direct link interconnects and 18 can drive to the
right LAB though direct link interconnects. All 36 outputs can drive to R4 and C4
routing interconnects. Outputs can drive right- or left-column routing.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
Digital Signal Processing Block
2–63
Figure 2–52 and Figure 2–53 show the DSP block interfaces to LAB rows.
Figure 2–52. DSP Block Interconnect Interface
DSP Block
R4, C4 & Direct
Link Interconnects
OA[17..0]
OB[17..0]
R4, C4 & Direct
Link Interconnects
A1[17..0]
B1[17..0]
OC[17..0]
OD[17..0]
A2[17..0]
B2[17..0]
OE[17..0]
OF[17..0]
A3[17..0]
B3[17..0]
OG[17..0]
OH[17..0]
A4[17..0]
B4[17..0]
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–64
Chapter 2: Arria GX Architecture
Digital Signal Processing Block
Figure 2–53. DSP Block Interface to Interconnect
Direct Link Interconnect
from Adjacent LAB
C4 Interconnect
R4 Interconnect
Direct Link Outputs
to Adjacent LABs
Direct Link Interconnect
from Adjacent LAB
36
DSP Block
Row Structure
36
LAB
LAB
18
16
16
12
Control
36
A[17..0]
B[17..0]
OA[17..0]
OB[17..0]
36
Row Interface
Block
DSP Block to
LAB Row Interface
Block Interconnect Region
36 Inputs per Row
36 Outputs per Row
A bus of 44 control signals feeds the entire DSP block. These signals include clocks,
asynchronous clears, clock enables, signed and unsigned control signals, addition and
subtraction control signals, rounding and saturation control signals, and accumulator
synchronous loads. The clock signals are routed from LAB row clocks and are
generated from specific LAB rows at the DSP block interface. The LAB row source for
control signals, data inputs, and outputs is shown in Table 2–15.
f
For more information about DSP blocks, refer to the DSP Blocks in Arria GX Devices
chapter.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
Digital Signal Processing Block
2–65
Table 2–15. DSP Block Signal Sources and Destinations
LAB Row at Interface
Control Signals Generated
Data Inputs
Data Outputs
A1[17..0]
OA[17..0]
B1[17..0]
OB[17..0]
A2[17..0]
OC[17..0]
B2[17..0]
OD[17..0]
A3[17..0]
OE[17..0]
B3[17..0]
OF[17..0]
A4[17..0]
OG[17..0]
B4[17..0]
OH[17..0]
clock0
aclr0
ena0
mult01_saturate
0
addnsub1_round/
accum_round
addnsub1
signa
sourcea
sourceb
clock1
aclr1
ena1
accum_saturate
1
mult01_round
accum_sload
sourcea
sourceb
mode0
clock2
aclr2
ena2
mult23_saturate
2
addnsub3_round/
accum_round
addnsub3
sign_b
sourcea
sourceb
clock3
aclr3
ena3
accum_saturate
3
mult23_round
accum_sload
sourcea
sourceb
mode1
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–66
Chapter 2: Arria GX Architecture
PLLs and Clock Networks
PLLs and Clock Networks
Arria GX devices provide a hierarchical clock structure and multiple PLLs with
advanced features. The large number of clocking resources in combination with the
clock synthesis precision provided by enhanced and fast PLLs provides a complete
clock management solution.
Global and Hierarchical Clocking
Arria GX devices provide 16 dedicated global clock networks and 32 regional clock
networks (eight per device quadrant). These clocks are organized into a hierarchical
clock structure that allows for up to 24 clocks per device region with low skew and
delay. This hierarchical clocking scheme provides up to 48 unique clock domains in
Arria GX devices.
There are 12 dedicated clock pins (CLK[15..12] and CLK[7..0]) to drive either the
global or regional clock networks. Four clock pins drive each side of the device except
the right side, as shown in Figure 2–54 and Figure 2–55. Internal logic and enhanced
and fast PLL outputs can also drive the global and regional clock networks. Each
global and regional clock has a clock control block, which controls the selection of the
clock source and dynamically enables or disables the clock to reduce power
consumption. Table 2–16 lists the global and regional clock features.
Table 2–16. Global and Regional Clock Features
Feature
Global Clocks
Regional Clocks
Number per device
16
32
Number available per
quadrant
16
8
Sources
Clock pins, PLL outputs, core routings,
inter-transceiver clocks
Clock pins, PLL outputs, core routings,
inter-transceiver clocks
Dynamic clock source
selection
v
—
Dynamic enable/disable
v
v
Global Clock Network
These clocks drive throughout the entire device, feeding all device quadrants. GCLK
networks can be used as clock sources for all resources in the device IOEs, ALMs, DSP
blocks, and all memory blocks. These resources can also be used for control signals,
such as clock enables and synchronous or asynchronous clears fed from the external
pin. The global clock networks can also be driven by internal logic for internally
generated global clocks and asynchronous clears, clock enables, or other control
signals with large fanout. Figure 2–54 shows the 12 dedicated CLK pins driving global
clock networks.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
PLLs and Clock Networks
2–67
Figure 2–54. Global Clocking
CLK[15..12]
Global Clock [15..0]
CLK[3..0]
Global Clock [15..0]
CLK[7..4]
Regional Clock Network
There are eight RCLK networks (RCLK[7..0]) in each quadrant of the Arria GX
device that are driven by the dedicated CLK[15..12]and CLK[7..0] input pins, by
PLL outputs, or by internal logic. The regional clock networks provide the lowest
clock delay and skew for logic contained in a single quadrant. The CLK pins
symmetrically drive the RCLK networks in a particular quadrant, as shown in
Figure 2–55.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–68
Chapter 2: Arria GX Architecture
PLLs and Clock Networks
Figure 2–55. Regional Clocks
CLK[15..12]
11 5
7
CLK[3..0]
RCLK
[31..28]
RCLK
[27..24]
RCLK
[3..0]
RCLK
[23..20]
RCLK
[7..4]
RCLK
[19..16]
Arria GX
Transceiver
Block
1
2
8
RCLK
[11..8]
Arria GX
Transceiver
Block
RCLK
[15..12]
12 6
CLK[7..4]
Dual-Regional Clock Network
A single source (CLK pin or PLL output) can generate a dual-RCLK by driving two
RCLK network lines in adjacent quadrants (one from each quadrant), which allows
logic that spans multiple quadrants to use the same low skew clock. The routing of
this clock signal on an entire side has approximately the same speed but slightly
higher clock skew when compared with a clock signal that drives a single quadrant.
Internal logic-array routing can also drive a dual-regional clock. Clock pins and
enhanced PLL outputs on the top and bottom can drive horizontal dual-regional
clocks. Clock pins and fast PLL outputs on the left and right can drive vertical
dual-regional clocks, as shown in Figure 2–56. Corner PLLs cannot drive
dual-regional clocks.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
PLLs and Clock Networks
2–69
Figure 2–56. Dual-Regional Clocks
Clock Pins or PLL Clock Outputs
Can Drive Dual-Regional Network
CLK[15..12]
Clock Pins or PLL Clock
Outputs Can Drive
Dual-Regional Network
CLK[3..0]
CLK[15..12]
CLK[3..0]
PLLs
PLLs
CLK[7..4]
CLK[7..4]
Combined Resources
Within each quadrant, there are 24 distinct dedicated clocking resources consisting of
16 global clock lines and eight regional clock lines. Multiplexers are used with these
clocks to form buses to drive LAB row clocks, column IOE clocks, or row IOE clocks.
Another multiplexer is used at the LAB level to select three of the six row clocks to
feed the ALM registers in the LAB (refer to Figure 2–57).
Figure 2–57. Hierarchical Clock Networks Per Quadrant
Clocks Available
to a Quadrant
or Half-Quadrant
Column I/O Cell
IO_CLK[7..0]
Global Clock Network [15..0]
Clock [23..0]
Lab Row Clock [5..0]
Regional Clock Network [7..0]
Row I/O Cell
IO_CLK[7..0]
You can use the Quartus II software to control whether a clock input pin drives either
a GCLK, RCLK, or dual-RCLK network. The Quartus II software automatically selects
the clocking resources if not specified.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–70
Chapter 2: Arria GX Architecture
PLLs and Clock Networks
Clock Control Block
Each GCLK, RCLK, and PLL external clock output has its own clock control block.
The control block has two functions:
■
Clock source selection (dynamic selection for global clocks)
■
Clock power-down (dynamic clock enable or disable)
Figure 2–58 through Figure 2–60 show the clock control block for the global clock,
regional clock, and PLL external clock output, respectively.
Figure 2–58. Global Clock Control Blocks
CLKp
Pins
PLL Counter
Outputs
CLKSELECT[1..0]
(1)
2
2
CLKn
Pin
2
Internal
Logic
Static Clock Select (2)
This multiplexer supports
User-Controllable
Dynamic Switching
Enable/
Disable
Internal
Logic
GCLK
Notes to Figure 2–58:
(1) These clock select signals can be dynamically controlled through internal logic when the device is operating in user mode.
(2) These clock select signals can only be set through a configuration file (SRAM Object File [.sof] or Programmer Object File [.pof]) and cannot be
dynamically controlled during user mode operation.
Figure 2–59. Regional Clock Control Blocks
CLKp
Pin
PLL Counter
Outputs
CLKn
Pin (2)
2
Internal
Logic
Static Clock Select (1)
Enable/
Disable
Internal
Logic
RCLK
Notes to Figure 2–59:
(1) These clock select signals can only be set through a configuration file (.sof or .pof) and cannot be dynamically controlled during user mode
operation.
(2) Only the CLKn pins on the top and bottom of the device feed to regional clock select.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
PLLs and Clock Networks
2–71
Figure 2–60. External PLL Output Clock Control Blocks
PLL Counter
Outputs (c[5..0])
6
Static Clock Select (1)
Enable/
Disable
Internal
Logic
IOE (2)
Internal
Logic
Static Clock
Select (1)
PLL_OUT
Pin
Notes to Figure 2–60:
(1) These clock select signals can only be set through a configuration file (.sof or .pof) and cannot be dynamically controlled during user mode
operation.
(2) The clock control block feeds to a multiplexer within the PLL_OUT pin’s IOE. The PLL_OUT pin is a dual-purpose pin. Therefore, this multiplexer
selects either an internal signal or the output of the clock control block.
For the global clock control block, clock source selection can be controlled either
statically or dynamically. You have the option of statically selecting the clock source
by using the Quartus II software to set specific configuration bits in the configuration
file (.sof or .pof) or controlling the selection dynamically by using internal logic to
drive the multiplexer select inputs. When selecting statically, the clock source can be
set to any of the inputs to the select multiplexer. When selecting the clock source
dynamically, you can either select between two PLL outputs (such as the C0 or C1
outputs from one PLL), between two PLLs (such as the C0/C1 clock output of one
PLL or the C0/C1 c1ock output of the other PLL), between two clock pins (such as
CLK0 or CLK1), or between a combination of clock pins or PLL outputs.
For the regional and PLL_OUT clock control block, clock source selection can only be
controlled statically using configuration bits. Any of the inputs to the clock select
multiplexer can be set as the clock source.
Arria GX clock networks can be disabled (powered down) by both static and dynamic
approaches. When a clock net is powered down, all logic fed by the clock net is in an
off-state thereby reducing the overall power consumption of the device. GCLK and
RCLK networks can be powered down statically through a setting in the
configuration file (.sof or .pof). Clock networks that are not used are automatically
powered down through configuration bit settings in the configuration file generated
by the Quartus II software. The dynamic clock enable or disable feature allows the
internal logic to control power up/down synchronously on GCLK and RCLK nets and
PLL_OUT pins. This function is independent of the PLL and is applied directly on the
clock network or PLL_OUT pin, as shown in Figure 2–58 through Figure 2–60.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–72
Chapter 2: Arria GX Architecture
PLLs and Clock Networks
Enhanced and Fast PLLs
Arria GX devices provide robust clock management and synthesis using up to four
enhanced PLLs and four fast PLLs. These PLLs increase performance and provide
advanced clock interfacing and clock frequency synthesis. With features such as clock
switchover, spread spectrum clocking, reconfigurable bandwidth, phase control, and
reconfigurable phase shifting, the Arria GX device’s enhanced PLLs provide you with
complete control of your clocks and system timing. The fast PLLs provide general
purpose clocking with multiplication and phase shifting as well as high-speed
outputs for high-speed differential I/O support. Enhanced and fast PLLs work
together with the Arria GX high-speed I/O and advanced clock architecture to
provide significant improvements in system performance and bandwidth.
The Quartus II software enables the PLLs and their features without requiring any
external devices. Table 2–17 lists the PLLs available for each Arria GX device and their
type.
Table 2–17. Arria GX Device PLL Availability (Note 1), (2)
Fast PLLs
Enhanced PLLs
Device
1
2
3 (3)
4 (3)
7
8
9 (3)
10 (3)
5
6
11
12
EP1AGX20
v
v
—
—
—
—
—
—
v
v
—
—
EP1AGX35
v
v
—
—
—
—
—
—
v
v
—
—
EP1AGX50 (4)
v
v
—
—
v
v
—
—
v
v
v
v
EP1AGX60 (5)
v
v
—
—
v
v
—
—
v
v
v
v
EP1AGX90
v
v
—
—
v
v
—
—
v
v
v
v
Notes to Table 2–17:
(1) The global or regional clocks in a fast PLL's transceiver block can drive the fast PLL input. A pin or other PLL must drive the global or regional
source. The source cannot be driven by internally generated logic before driving the fast PLL.
(2) EP1AGX20C, EP1AGX35C/D, EP1AGX50C and EP1AGX60C/D devices only have two fast PLLs (PLLs 1 and 2), but the connectivity from these
two PLLs to the global and regional clock networks remains the same as shown in this table.
(3) PLLs 3, 4, 9, and 10 are not available in Arria GX devices.
(4) 4 or 8 PLLs are available depending on C or D device and the package option.
(5) 4or 8 PLLs are available depending on C, D, or E device option.
Table 2–18 lists the enhanced PLL and fast PLL features in Arria GX devices.
Table 2–18. Arria GX PLL Features (Part 1 of 2)
Feature
Enhanced PLL
Fast PLL
m/(n × post-scale counter) (1)
m/(n × post-scale counter) (2)
Down to 125-ps increments (3), (4)
Down to 125-ps increments (3), (4)
Clock switchover
v
v (5)
PLL reconfiguration
v
v
Reconfigurable bandwidth
v
v
Spread spectrum clocking
v
—
Programmable duty cycle
v
v
Clock multiplication and division
Phase shift
Number of internal clock outputs
6
4
Number of external clock outputs
Three differential/six single-ended
(6)
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
PLLs and Clock Networks
2–73
Table 2–18. Arria GX PLL Features (Part 2 of 2)
Feature
Number of feedback clock inputs
Enhanced PLL
Fast PLL
One single-ended or differential (7), (8)
—
Notes to Table 2–18:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
For enhanced PLLs, m, n range from 1 to 256 and post-scale counters range from 1 to 512 with 50% duty cycle.
For fast PLLs, m, and post-scale counters range from 1 to 32. The n counter ranges from 1 to 4.
The smallest phase shift is determined by the voltage controlled oscillator (VCO ) period divided by 8.
For degree increments, Arria GX devices can shift all output frequencies in increments of at least 45. Smaller degree increments are possible
depending on the frequency and divide parameters.
Arria GX fast PLLs only support manual clock switchover.
Fast PLLs can drive to any I/O pin as an external clock. For high-speed differential I/O pins, the device uses a data channel to generate
txclkout.
If the feedback input is used, you lose one (or two, if fBIN is differential) external clock output pin.
Every Arria GX device has at least two enhanced PLLs with one single-ended or differential external feedback input per PLL.
Figure 2–61 shows a top-level diagram of the Arria GX device and PLL floorplan.
Figure 2–61. PLL Locations
CLK[15..12]
FPLL7CLK
7
CLK[3..0]
1
2
11
5
12
6
PLLs
FPLL8CLK
8
CLK[7..4]
Figure 2–62 and Figure 2–63 shows global and regional clocking from the fast PLL
outputs and side clock pins. The connections to the global and regional clocks from
the fast PLL outputs, internal drivers, and CLK pins on the left side of the device are
shown in Table 2–19.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–74
Chapter 2: Arria GX Architecture
PLLs and Clock Networks
Figure 2–62. Global and Regional Clock Connections from Center Clock Pins and Fast PLL Outputs (Note 1)
C0
CLK0
CLK1
Fast
PLL 1
C1
C2
C3
Logic Array
Signal Input
To Clock
Network
C0
CLK2
CLK3
Fast
PLL 2
C1
C2
C3
RCLK0
RCLK2
RCLK1
RCLK4
RCLK3
RCLK6
RCLK5
RCLK7
GCLK0
GCLK1
GCLK2
GCLK3
Note to Figure 2–62:
(1) The global or regional clocks in a fast PLL's quadrant can drive the fast PLL input. A dedicated clock input pin or other PLL must drive the global
or regional source. The source cannot be driven by internally generated logic before driving the fast PLL.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
PLLs and Clock Networks
2–75
Figure 2–63. Global and Regional Clock Connections from Corner Clock Pins and Fast PLL Outputs
RCLK1
(Note 1)
RCLK3
RCLK0
RCLK2
RCLK4
RCLK6
C0
Fast
PLL 7
C1
C2
C3
C0
Fast
PLL 8
C1
C2
C3
RCLK5
GCLK0
RCLK7
GCLK2
GCLK1
GCLK3
Note to Figure 2–63:
(1) The GCLK or RCLK in a fast PLL's quadrant can drive the fast PLL input. A dedicated clock input pin or other PLL must drive the global or regional
source. The source cannot be driven by internally generated logic before driving the fast PLL.
RCLK7
RCLK6
RCLK5
RCLK4
RCLK3
RCLK2
RCLK1
RCLK0
CLK3
CLK2
CLK1
Left Side Global & Regional
Clock Network Connectivity
CLK0
Table 2–19. Global and Regional Clock Connections from Left Side Clock Pins and Fast PLL Outputs (Part 1 of 2)
Clock Pins
CLK0p
v
v
—
—
v
—
—
—
v
—
—
—
CLK1p
v
v
—
—
—
v
—
—
—
v
—
—
CLK2p
—
—
v
v
—
—
v
—
—
—
v
—
CLK3p
—
—
v
v
—
—
—
v
—
—
—
v
GCLKDRV0
v
v
—
—
—
—
—
—
—
—
—
—
GCLKDRV1
v
v
—
—
—
—
—
—
—
—
—
—
GCLKDRV2
—
—
v
v
—
—
—
—
—
—
—
—
GCLKDRV3
—
—
v
v
—
—
—
—
—
—
—
—
RCLKDRV0
—
—
—
—
v
—
—
—
v
—
—
—
RCLKDRV1
—
—
—
—
—
v
—
—
—
v
—
—
RCLKDRV2
—
—
—
—
—
—
v
—
—
—
v
—
RCLKDRV3
—
—
—
—
—
—
—
v
—
—
—
v
RCLKDRV4
—
—
—
—
v
—
—
—
v
—
—
—
RCLKDRV5
—
—
—
—
—
v
—
—
—
v
—
—
RCLKDRV6
—
—
—
—
—
—
v
—
—
—
v
—
Drivers from Internal Logic
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–76
Chapter 2: Arria GX Architecture
PLLs and Clock Networks
RCLK7
RCLK6
RCLK5
RCLK4
RCLK3
RCLK2
RCLK1
RCLK0
CLK3
CLK2
CLK1
Left Side Global & Regional
Clock Network Connectivity
CLK0
Table 2–19. Global and Regional Clock Connections from Left Side Clock Pins and Fast PLL Outputs (Part 2 of 2)
—
—
—
—
—
—
—
v
—
—
—
v
c0
v
v
—
—
v
—
v
—
v
—
v
—
c1
v
v
—
—
—
v
—
v
v
—
v
c2
—
—
v
v
v
—
v
—
v
—
v
—
c3
—
—
v
v
—
v
—
v
—
v
—
v
c0
v
v
—
—
—
v
—
v
—
v
—
v
c1
v
v
—
—
v
—
v
—
v
—
v
—
c2
—
—
v
v
—
v
—
v
—
v
—
v
c3
—
—
v
v
v
—
v
—
v
—
v
—
c0
—
—
v
v
—
v
—
v
—
—
—
—
c1
—
—
v
v
v
—
v
—
—
—
—
—
c2
v
v
—
—
—
v
—
v
—
—
—
—
c3
v
v
—
—
v
—
v
—
—
—
—
—
c0
—
—
v
v
—
—
—
—
v
—
v
—
c1
—
—
v
v
—
—
—
—
—
v
—
v
c2
v
v
—
—
—
—
—
—
v
—
v
—
c3
v
v
—
—
—
—
—
—
—
v
—
v
RCLKDRV7
PLL 1 Outputs
PLL 2 Outputs
PLL 7 Outputs
PLL 8 Outputs
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
PLLs and Clock Networks
2–77
Figure 2–64 shows the global and regional clocking from enhanced PLL outputs and
top and bottom CLK pins.
Figure 2–64. Global and Regional Clock Connections from Top and Bottom Clock Pins and Enhanced PLL Outputs (Note 1)
CLK15
CLK13
CLK12
CLK14
PLL5_FB
PLL11_FB
PLL 11
PLL 5
c0 c1 c2 c3 c4 c5
c0 c1 c2 c3 c4 c5
PLL5_OUT[2..0]p
PLL5_OUT[2..0]n
RCLK31
RCLK30
RCLK29
RCLK28
PLL11_OUT[2..0]p
PLL11_OUT[2..0]n
RCLK27
RCLK26
RCLK25
RCLK24
Regional
Clocks
G15
G14
G13
G12
Global
Clocks
Regional
Clocks
G4
G5
G6
G7
RCLK8
RCLK9
RCLK10
RCLK11
RCLK12
RCLK13
RCLK14
RCLK15
PLL6_OUT[2..0]p
PLL6_OUT[2..0]n
PLL12_OUT[2..0]p
PLL12_OUT[2..0]n
c0 c1 c2 c3 c4 c5
c0 c1 c2 c3 c4 c5
PLL 12
PLL 6
PLL12_FB
PLL6_FB
CLK4
CLK6
CLK5
CLK7
Note to Figure 2–64:
(1) If the design uses the feedback input, you might lose one (or two if FBIN is differential) external clock output pin.
The connections to the global and regional clocks from the top clock pins and
enhanced PLL outputs are shown in Table 2–20. The connections to the clocks from
the bottom clock pins are shown in Table 2–21.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–78
Chapter 2: Arria GX Architecture
PLLs and Clock Networks
RCLK31
RCLK30
RCLK29
RCLK28
RCLK27
RCLK26
RCLK25
RCLK24
CLK15
CLK14
CLK13
DLLCLK
Top Side Global and
Regional Clock Network
Connectivity
CLK12
Table 2–20. Global and Regional Clock Connections from Top Clock Pins and Enhanced PLL Outputs
Clock pins
CLK12p
v
v
v
—
—
v
—
—
—
v
—
—
—
CLK13p
v
v
v
—
—
—
v
—
—
—
v
—
—
CLK14p
v
—
—
v
v
—
—
v
—
—
—
v
—
CLK15p
v
—
—
v
v
—
—
—
v
—
—
—
v
CLK12n
—
v
—
—
—
v
—
—
—
v
—
—
—
CLK13n
—
—
v
—
—
—
v
—
—
—
v
—
—
CLK14n
—
—
—
v
—
—
—
v
—
—
—
v
—
CLK15n
—
—
—
—
v
—
—
—
v
—
—
—
v
GCLKDRV0
—
v
—
—
—
—
—
—
—
—
—
—
—
GCLKDRV1
—
—
v
—
—
—
—
—
—
—
—
—
—
GCLKDRV2
—
—
—
v
—
—
—
—
—
—
—
—
—
GCLKDRV3
—
—
—
—
v
—
—
—
—
—
—
—
—
RCLKDRV0
—
—
—
—
—
v
—
—
—
v
—
—
—
RCLKDRV1
—
—
—
—
—
—
v
—
—
—
v
—
—
RCLKDRV2
—
—
—
—
—
—
—
v
—
—
—
v
—
Drivers from internal logic
RCLKDRV3
—
—
—
—
—
—
—
—
v
—
—
—
v
RCLKDRV4
—
—
—
—
—
v
—
—
—
v
—
—
—
RCLKDRV5
—
—
—
—
—
—
v
—
—
—
v
—
—
RCLKDRV6
—
—
—
—
—
—
—
v
—
—
—
v
—
RCLKDRV7
—
—
—
—
—
—
—
—
v
—
—
—
v
c0
v
v
v
—
—
v
—
—
—
v
—
—
—
c1
v
v
v
—
—
—
v
—
—
—
v
—
—
c2
v
—
—
v
v
—
—
v
—
—
—
v
—
c3
v
—
—
v
v
—
—
—
v
—
—
—
v
c4
v
—
—
—
—
v
—
v
—
v
—
v
—
c5
v
—
—
—
—
—
v
—
v
—
v
—
v
c0
—
v
v
—
—
v
—
—
—
v
—
—
—
c1
—
v
v
—
—
—
v
—
—
—
v
—
—
c2
—
—
—
v
v
—
—
v
—
—
—
v
—
Enhanced PLL5 outputs
Enhanced PLL 11 outputs
c3
—
—
—
v
v
—
—
—
v
—
—
—
v
c4
—
—
—
—
—
v
—
v
—
v
—
v
—
c5
—
—
—
—
—
—
v
—
v
—
v
—
v
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
PLLs and Clock Networks
2–79
RCLK15
RCLK14
RCLK13
RCLK12
RCLK11
RCLK10
RCLK9
RCLK8
CLK7
CLK6
CLK5
CLK4
Bottom Side Global and
Regional Clock Network
Connectivity
DLLCLK
Table 2–21. Global and Regional Clock Connections from Bottom Clock Pins and Enhanced PLL Outputs
Clock pins
CLK4p
v
v
v
—
—
v
—
—
—
v
—
—
—
CLK5p
v
v
v
—
—
—
v
—
—
—
v
—
—
CLK6p
v
—
—
v
v
—
—
v
—
—
—
v
—
CLK7p
v
—
—
v
v
—
—
—
v
—
—
—
v
CLK4n
—
v
—
—
—
v
—
—
—
v
—
—
—
CLK5n
—
—
v
—
—
—
v
—
—
—
v
—
—
CLK6n
—
—
—
v
—
—
—
v
—
—
—
v
—
CLK7n
—
—
—
—
v
—
—
—
v
—
—
—
v
GCLKDRV0
—
v
—
—
—
—
—
—
—
—
—
—
—
GCLKDRV1
—
—
v
—
—
—
—
—
—
—
—
—
—
GCLKDRV2
—
—
—
v
—
—
—
—
—
—
—
—
—
GCLKDRV3
—
—
—
—
v
—
—
—
—
—
—
—
—
RCLKDRV0
—
—
—
—
—
v
—
—
—
v
—
—
—
RCLKDRV1
—
—
—
—
—
—
v
—
—
—
v
—
—
RCLKDRV2
—
—
—
—
—
—
—
v
—
—
—
v
—
RCLKDRV3
—
—
—
—
—
—
—
—
v
—
—
—
v
RCLKDRV4
—
—
—
—
—
v
—
—
—
v
—
—
—
RCLKDRV5
—
—
—
—
—
—
v
—
—
—
v
—
—
RCLKDRV6
—
—
—
—
—
—
—
v
—
—
—
v
—
RCLKDRV7
—
—
—
—
—
—
—
—
v
—
—
—
v
c0
v
v
v
—
—
v
—
—
—
v
—
—
—
c1
v
v
v
—
—
—
v
—
—
—
v
—
—
c2
v
—
—
v
v
—
—
v
—
—
c3
v
—
—
v
v
—
—
—
v
—
—
—
v
c4
v
—
—
—
—
v
—
v
—
v
—
v
—
c5
v
—
—
—
—
—
v
—
v
—
v
—
v
c0
—
v
v
—
—
v
—
—
—
v
—
—
—
c1
—
v
v
—
—
—
v
—
—
—
v
—
—
c2
—
—
—
v
v
—
—
v
—
—
—
v
—
c3
—
—
—
v
v
—
—
—
v
—
—
—
v
c4
—
—
—
—
—
v
—
v
—
v
—
v
—
c5
—
—
—
—
—
—
v
—
v
—
v
—
v
Drivers from internal logic
Enhanced PLL 6 outputs
v
Enhanced PLL 12 outputs
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–80
Chapter 2: Arria GX Architecture
PLLs and Clock Networks
Enhanced PLLs
Arria GX devices contain up to four enhanced PLLs with advanced clock
management features. These features include support for external clock feedback
mode, spread-spectrum clocking, and counter cascading. Figure 2–65 shows a
diagram of the enhanced PLL.
Figure 2–65. Arria GX Enhanced PLL
(Note 1)
From Adjacent PLL
VCO Phase Selection
Selectable at Each
PLL Output Port
Clock
Switchover
Circuitry
Post-Scale
Counters
Spread
Spectrum
Phase Frequency
Detector
/c0
INCLK[3..0]
/c1
4
/n
PFD
Charge
Pump
Loop
Filter
8
VCO
Global or
Regional
Clock
4
Global
Clocks
8
Regional
Clocks
/c2
6
/c3
6
/m
I/O Buffers (3)
/c4
(2)
/c5
FBIN
Shaded Portions of the
PLL are Reconfigurable
to I/O or general
routing
Lock Detect
& Filter
VCO Phase Selection
Affecting All Outputs
Notes to Figure 2–65:
(1)
(2)
(3)
(4)
Each clock source can come from any of the four clock pins that are physically located on the same side of the device as the PLL.
If the feedback input is used, you will lose one (or two, if FBIN is differential) external clock output pin.
Each enhanced PLL has three differential external clock outputs or six single-ended external clock outputs.
The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a clock
control block provided the clock control block is fed by an output from another PLL or a pin-driven dedicated global or regional clock. An internally
generated global signal cannot drive the PLL.
Fast PLLs
Arria GX devices contain up to four fast PLLs with high-speed serial interfacing
ability. Fast PLLs offer high-speed outputs to manage the high-speed differential I/O
interfaces. Figure 2–66 shows a diagram of the fast PLL.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
I/O Structure
2–81
Figure 2–66. Arria GX Device Fast PLL
Clock
Switchover
Circuitry (4)
Global or
regional clock (1)
Phase
Frequency
Detector
Post-Scale
Counters
diffioclk0 (2)
load_en0 (3)
÷c0
÷n
4
Clock
Input
VCO Phase Selection
Selectable at each PLL
Output Port
PFD
Charge
Pump
Loop
Filter
VCO
÷k
8
load_en1 (3)
÷c1
diffioclk1 (2)
4
Global clocks
÷c2
4
Global or
regional clock (1)
8
Regional clocks
÷c3
÷m
8
to DPA block
Shaded Portions of the
PLL are Reconfigurable
Notes to Figure 2–66:
(1) The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or regional clock, or through a clock
control block provided the clock control block is fed by an output from another PLL or a pin-driven dedicated global or regional clock. An internally
generated global signal cannot drive the PLL.
(2) In high-speed differential I/O support mode, this high-speed PLL clock feeds the serializer/deserializer (SERDES) circuitry. Arria GX devices only
support one rate of data transfer per fast PLL in high-speed differential I/O support mode.
(3) This signal is a differential I/O SERDES control signal.
(4) Arria GX fast PLLs only support manual clock switchover.
f
For more information about enhanced and fast PLLs, refer to the PLLs in Arria GX
Devices chapter. For more information about high-speed differential I/O support,
refer to “High-Speed Differential I/O with DPA Support” on page 2–99.
I/O Structure
Arria GX IOEs provide many features, including:
© December 2009
■
Dedicated differential and single-ended I/O buffers
■
3.3-V, 64-bit, 66-MHz PCI compliance
■
3.3-V, 64-bit, 133-MHz PCI-X 1.0 compliance
■
JTAG boundary-scan test (BST) support
■
On-chip driver series termination
■
OCT for differential standards
■
Programmable pull-up during configuration
■
Output drive strength control
■
Tri-state buffers
■
Bus-hold circuitry
■
Programmable pull-up resistors
■
Programmable input and output delays
■
Open-drain outputs
■
DQ and DQS I/O pins
■
DDR registers
Altera Corporation
Arria GX Device Handbook, Volume 1
2–82
Chapter 2: Arria GX Architecture
I/O Structure
The IOE in Arria GX devices contains a bidirectional I/O buffer, six registers, and a
latch for a complete embedded bidirectional single data rate or DDR transfer.
Figure 2–67 shows the Arria GX IOE structure. The IOE contains two input registers
(plus a latch), two output registers, and two output enable registers. The design can
use both input registers and the latch to capture DDR input and both output registers
to drive DDR outputs. Additionally, the design can use the output enable (OE)
register for fast clock-to-output enable timing. The negative edge-clocked OE register
is used for DDR SDRAM interfacing. The Quartus II software automatically
duplicates a single OE register that controls multiple output or bidirectional pins.
Figure 2–67. Arria GX IOE Structure
Logic Array
OE Register
OE
D
Q
OE Register
D
Q
Output Register
Output A
D
Q
CLK
Output Register
Output B
D
Q
Input Register
D
Q
Input A
Input B
Input Register
D
Q
Input Latch
D
Q
ENA
The IOEs are located in I/O blocks around the periphery of the Arria GX device.
There are up to four IOEs per row I/O block and four IOEs per column I/O block.
Row I/O blocks drive row, column, or direct link interconnects. Column I/O blocks
drive column interconnects.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
I/O Structure
2–83
Figure 2–68 shows how a row I/O block connects to the logic array.
Figure 2–68. Row I/O Block Connection to the Interconnect
R4 & R24
Interconnects
C4 Interconnect
I/O Block Local
Interconnect
32 Data & Control
Signals from
Logic Array (1)
32
LAB
Horizontal
I/O Block
io_dataina[3..0]
io_datainb[3..0]
Direct Link
Interconnect
to Adjacent LAB
Direct Link
Interconnect
to Adjacent LAB
io_clk[7:0]
LAB Local
Interconnect
Horizontal I/O
Block Contains
up to Four IOEs
Note to Figure 2–68:
(1) The 32 data and control signals consist of eight data out lines: four lines each for DDR applications io_dataouta[3..0] and
io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables io_ce_in[3..0], four output clock enables
io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous clear and preset signals io_aclr/apreset[3..0], and four
synchronous clear and preset signals io_sclr/spreset[3..0].
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–84
Chapter 2: Arria GX Architecture
I/O Structure
Figure 2–69 shows how a column I/O block connects to the logic array.
Figure 2–69. Column I/O Block Connection to the Interconnect
32 Data &
Control Signals
from Logic Array (1)
Vertical I/O
Block Contains
up to Four IOEs
Vertical I/O Block
32
IO_dataina[3..0]
IO_datainb[3..0]
io_clk[7..0]
I/O Block
Local Interconnect
R4 & R24
Interconnects
LAB
LAB Local
Interconnect
LAB
LAB
C4 & C16
Interconnects
Note to Figure 2–69:
(1) The 32 data and control signals consist of eight data out lines: four lines each for DDR applications io_dataouta[3..0] and
io_dataoutb[3..0], four output enables io_oe[3..0], four input clock enables io_ce_in[3..0], four output clock enables
io_ce_out[3..0], four clocks io_clk[3..0], four asynchronous clear and preset signals io_aclr/apreset[3..0], and four
synchronous clear and preset signals io_sclr/spreset[3..0] .
There are 32 control and data signals that feed each row or column I/O block. These
control and data signals are driven from the logic array. The row or column IOE
clocks, io_clk[7..0], provide a dedicated routing resource for low-skew,
high-speed clocks. I/O clocks are generated from global or regional clocks (refer to
“PLLs and Clock Networks” on page 2–66).
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
I/O Structure
2–85
Figure 2–70 shows the signal paths through the I/O block.
Figure 2–70. Signal Path Through the I/O Block
Row or Column
io_clk[7..0]
To Logic
Array
To Other
IOEs
io_dataina
io_datainb
oe
ce_in
io_oe
ce_out
io_ce_in
Control
Signal
Selection
io_ce_out
IOE
aclr/apreset
sclr/spreset
io_aclr
From Logic
Array
clk_in
io_sclr
clk_out
io_clk
io_dataouta
io_dataoutb
Each IOE contains its own control signal selection for the following control signals:
oe, ce_in, ce_out, aclr/apreset, sclr/spreset, clk_in, and clk_out.
Figure 2–71 shows the control signal selection.
Figure 2–71. Control Signal Selection per IOE (Note 1)
Dedicated I/O
Clock [7..0]
Local
Interconnect
io_oe
Local
Interconnect
io_sclr
Local
Interconnect
io_aclr
Local
Interconnect
io_ce_out
Local
Interconnect
io_ce_in
Local
Interconnect
io_clk
ce_out
clk_out
clk_in
ce_in
sclr/spreset
aclr/apreset
oe
Notes to Figure 2–71:
(1) Control signals ce_in, ce_out, aclr/apreset, sclr/spreset, and oe can be global signals even though their control selection
multiplexers are not directly fed by the ioe_clk[7..0] signals. The ioe_clk signals can drive the I/O local interconnect, which then drives
the control selection multiplexers.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–86
Chapter 2: Arria GX Architecture
I/O Structure
In normal bidirectional operation, you can use the input register for input data
requiring fast setup times. The input register can have its own clock input and clock
enable separate from the OE and output registers. The output register can be used for
data requiring fast clock-to-output performance. You can use the OE register for fast
clock-to-output enable timing. The OE and output register share the same clock
source and the same clock enable source from the local interconnect in the associated
LAB, dedicated I/O clocks, and the column and row interconnects. Figure 2–72 shows
the IOE in bidirectional configuration.
Figure 2–72. Arria GX IOE in Bidirectional I/O Configuration (Note 1)
ioe_clk[7..0]
Column, Row,
or Local
Interconnect
oe
OE Register
D
Q
clkout
ce_out
ENA
CLRN/PRN
OE Register
tCO Delay
VCCIO
PCI Clamp (2)
VCCIO
Programmable
Pull-Up
Resistor
aclr/apreset
Chip-Wide Reset
Output Register
D
sclr/spreset
Q
Output
Pin Delay
On-Chip
Termination
Drive Strength Control
ENA
Open-Drain Output
CLRN/PRN
Input Pin to
Logic Array Delay
Input Register
clkin
ce_in
D
Input Pin to
Input Register Delay
Bus-Hold
Circuit
Q
ENA
CLRN/PRN
Notes to Figure 2–72:
(1) All input signals to the IOE can be inverted at the IOE.
(2) The optional PCI clamp is only available on column I/O pins.
The Arria GX device IOE includes programmable delays that can be activated to
ensure input IOE register-to-logic array register transfers, input pin-to-logic array
register transfers, or output IOE register-to-pin transfers.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
I/O Structure
2–87
A path in which a pin directly drives a register can require the delay to ensure zero
hold time, whereas a path in which a pin drives a register through combinational logic
may not require the delay. Programmable delays exist for decreasing
input-pin-to-logic-array and IOE input register delays. The Quartus II Compiler can
program these delays to automatically minimize setup time while providing a zero
hold time. Programmable delays can increase the register-to-pin delays for output
and/or output enable registers. Programmable delays are no longer required to
ensure zero hold times for logic array register-to-IOE register transfers. The Quartus II
Compiler can create zero hold time for these transfers. Table 2–22 shows the
programmable delays for Arria GX devices.
Table 2–22. Arria GX Devices Programmable Delay Chain
Programmable Delays
Quartus II Logic Option
Input pin to logic array delay
Input delay from pin to internal cells
Input pin to input register delay
Input delay from pin to input register
Output pin delay
Delay from output register to output pin
Output enable register t CO delay
Delay to output enable pin
IOE registers in Arria GX devices share the same source for clear or preset. You can
program preset or clear for each individual IOE. You can also program the registers to
power up high or low after configuration is complete. If programmed to power up
low, an asynchronous clear can control the registers. If programmed to power up
high, an asynchronous preset can control the registers. This feature prevents the
inadvertent activation of another device’s active-low input upon power-up. If one
register in an IOE uses a preset or clear signal, all registers in the IOE must use that
same signal if they require preset or clear. Additionally, a synchronous reset signal is
available for the IOE registers.
Double Data Rate I/O Pins
Arria GX devices have six registers in the IOE, which support DDR interfacing by
clocking data on both positive and negative clock edges. The IOEs in Arria GX devices
support DDR inputs, DDR outputs, and bidirectional DDR modes. When using the
IOE for DDR inputs, the two input registers clock double rate input data on
alternating edges. An input latch is also used in the IOE for DDR input acquisition.
The latch holds the data that is present during the clock high times, allowing both bits
of data to be synchronous with the same clock edge (either rising or falling).
Figure 2–73 shows an IOE configured for DDR input. Figure 2–74 shows the DDR
input timing diagram.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–88
Chapter 2: Arria GX Architecture
I/O Structure
Figure 2–73. Arria GX IOE in DDR Input I/O Configuration
(Note 1)
ioe_clk[7..0]
Column, Row,
or Local
Interconnect
VCCIO
To DQS Logic
Block (3)
DQS Local
Bus (2)
PCI Clamp (4)
VCCIO
Programmable
Pull-Up
Resistor
On-Chip
Termination
Input Pin to
Input RegisterDelay
sclr/spreset
Input Register
D
Q
clkin
ENA
CLRN/PRN
ce_in
Bus-Hold
Circuit
aclr/apreset
Chip-Wide Reset
Latch
Input Register
D
Q
D
Q
ENA
CLRN/PRN
ENA
CLRN/PRN
Notes to Figure 2–73:
(1)
(2)
(3)
(4)
All input signals to the IOE can be inverted at the IOE.
This signal connection is only allowed on dedicated DQ function pins.
This signal is for dedicated DQS function pins only.
The optional PCI clamp is only available on column I/O pins.
Figure 2–74. Input Timing Diagram in DDR Mode
Data at
input pin
B0
A0
B1
A1
B2
A2
B3
A3
B4
CLK
A0
A1
A2
A3
B0
B1
B2
B3
Input To
Logic Array
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
I/O Structure
2–89
When using the IOE for DDR outputs, the two output registers are configured to clock
two data paths from ALMs on rising clock edges. These output registers are
multiplexed by the clock to drive the output pin at a ×2 rate. One output register
clocks the first bit out on the clock high time, while the other output register clocks the
second bit out on the clock low time. Figure 2–75 shows the IOE configured for DDR
output. Figure 2–76 shows the DDR output timing diagram.
Figure 2–75. Arria GX IOE in DDR Output I/O Configuration Notes (1), (2)
ioe_clk[7..0]
Column, Row,
or Local
Interconnect
oe
OE Register
D
Q
clkout
ENA
CLRN/PRN
OE Register
tCO Delay
ce_out
aclr/apreset
VCCIO
PCI Clamp (3)
Chip-Wide Reset
OE Register
D
VCCIO
Q
sclr/spreset
ENA
CLRN/PRN
Used for
DDR, DDR2
SDRAM
Programmable
Pull-Up
Resistor
Output Register
D
Q
ENA
CLRN/PRN
Output Register
D
Output
Pin Delay
On-Chip
Termination
clk
Drive Strength
Control
Open-Drain Output
Q
ENA
CLRN/PRN
Bus-Hold
Circuit
Notes to Figure 2–75:
(1) All input signals to the IOE can be inverted at the IOE.
(2) The tri-state buffer is active low. The DDIO megafunction represents the tri-state buffer as active-high with an inverter at the OE register data port.
(3) The optional PCI clamp is only available on column I/O pins.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–90
Chapter 2: Arria GX Architecture
I/O Structure
Figure 2–76. Output Timing Diagram in DDR Mode
CLK
A1
A2
A3
A4
B1
B2
B3
B4
From Internal
Registers
DDR output
B1
A1
B2
A2
B3
A3
B4
A4
The Arria GX IOE operates in bidirectional DDR mode by combining the DDR input
and DDR output configurations. The negative-edge-clocked OE register holds the OE
signal inactive until the falling edge of the clock to meet DDR SDRAM timing
requirements.
External RAM Interfacing
In addition to the six I/O registers in each IOE, Arria GX devices also have dedicated
phase-shift circuitry for interfacing with external memory interfaces, including DDR,
DDR2 SDRAM, and SDR SDRAM. In every Arria GX device, the I/O banks at the top
(Banks 3 and 4) and bottom (Banks 7 and 8) of the device support DQ and DQS signals
with DQ bus modes of ×4, ×8/×9, ×16/×18, or ×32/×36. Table 2–23 shows the number
of DQ and DQS buses that are supported per device.
Table 2–23. DQS and DQ Bus Mode Support (Note 1)
Device
EP1AGX20
EP1AGX35
EP1AGX50/60
EP1AGX90
Number of
×4 Groups
Number of
×8/×9 Groups
Number of
×16/×18 Groups
Number of
×32/×36 Groups
484-pin FineLine BGA
2
0
0
0
484-pin FineLine BGA
2
0
0
0
780-pin FineLine BGA
18
8
4
0
484-pin FineLine BGA
2
0
0
0
780-pin FineLine BGA
18
8
4
0
1,152-pin FineLine
BGA
36
18
8
4
1,152-pin FineLine
BGA
36
18
8
4
Package
Note to Table 2–23:
(1) Numbers are preliminary until devices are available.
A compensated delay element on each DQS pin automatically aligns input DQS
synchronization signals with the data window of their corresponding DQ data
signals. The DQS signals drive a local DQS bus in the top and bottom I/O banks. This
DQS bus is an additional resource to the I/O clocks and is used to clock DQ input
registers with the DQS signal.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
I/O Structure
2–91
The Arria GX device has two phase-shifting reference circuits, one on the top and one
on the bottom of the device. The circuit on the top controls the compensated delay
elements for all DQS pins on the top. The circuit on the bottom controls the
compensated delay elements for all DQS pins on the bottom.
Each phase-shifting reference circuit is driven by a system reference clock, which must
have the same frequency as the DQS signal. Clock pins CLK[15..12]p feed phase
circuitry on the top of the device and clock pins CLK[7..4]p feed phase circuitry on
the bottom of the device. In addition, PLL clock outputs can also feed the
phase-shifting reference circuits. Figure 2–77 shows the phase-shift reference circuit
control of each DQS delay shift on the top of the device. This same circuit is
duplicated on the bottom of the device.
Figure 2–77. DQS Phase-Shift Circuitry (Note 1), (2)
From PLL 5 (4)
DQS
Pin
DQS
Pin
Dt
Dt
to IOE
to IOE
CLK[15..12]p (3)
DQS
Phase-Shift
Circuitry
DQS
Pin
DQS
Pin
Dt
Dt
to IOE
to IOE
Notes to Figure 2–77:
(1) There are up to 18 pairs of DQS pins available on the top or bottom of the Arria GX device. There are up to 10 pairs on the right side and 8 pairs
on the left side of the DQS phase-shift circuitry.
(2) The “t” module represents the DQS logic block.
(3) Clock pins CLK[15..12]p feed phase-shift circuitry on the top of the device and clock pins CLK[7..4]p feed the phase circuitry on the
bottom of the device. You can also use a PLL clock output as a reference clock to phase shift circuitry.
(4) You can only use PLL 5 to feed the DQS phase-shift circuitry on the top of the device and PLL 6 to feed the DQS phase-shift circuitry on the bottom
of the device.
These dedicated circuits combined with enhanced PLL clocking and phase-shift
ability provide a complete hardware solution for interfacing to high-speed memory.
f
For more information about external memory interfaces, refer to the External Memory
Interfaces in Arria GX Devices chapter.
Programmable Drive Strength
The output buffer for each Arria GX device I/O pin has a programmable drive
strength control for certain I/O standards. The LVTTL, LVCMOS, SSTL, and HSTL
standards have several levels of drive strength that you can control. The default
setting used in the Quartus II software is the maximum current strength setting that is
used to achieve maximum I/O performance. For all I/O standards, the minimum
setting is the lowest drive strength that guarantees the IOH/IOL of the standard. Using
minimum settings provides signal slew rate control to reduce system noise and signal
overshoot.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–92
Chapter 2: Arria GX Architecture
I/O Structure
Table 2–24 shows the possible settings for I/O standards with drive strength control.
Table 2–24. Programmable Drive Strength (Note 1)
I OH / IOL Current Strength
Setting (mA) for Column
I/O Pins
IOH / IOL Current Strength
Setting (mA) for Row I/O
Pins
3.3-V LVTTL
24, 20, 16, 12, 8, 4
12, 8, 4
3.3-V LVCMOS
24, 20, 16, 12, 8, 4
8, 4
2.5-V LVTTL/LVCMOS
16, 12, 8, 4
12, 8, 4
1.8-V LVTTL/LVCMOS
12, 10, 8, 6, 4, 2
8, 6, 4, 2
1.5-V LVCMOS
8, 6, 4, 2
4, 2
SSTL-2 Class I
12, 8
12, 8
I/O Standard
SSTL-2 Class II
24, 20, 16
16
SSTL-18 Class I
12, 10, 8, 6, 4
10, 8, 6, 4
SSTL-18 Class II
20, 18, 16, 8
—
HSTL-18 Class I
12, 10, 8, 6, 4
12, 10, 8, 6, 4
HSTL-18 Class II
20, 18, 16
—
HSTL-15 Class I
12, 10, 8, 6, 4
8, 6, 4
HSTL-15 Class II
20, 18, 16
—
Note to Table 2–24:
(1) The Quartus II software default current setting is the maximum setting for each I/O standard.
Open-Drain Output
Arria GX devices provide an optional open-drain (equivalent to an open collector)
output for each I/O pin. This open-drain output enables the device to provide
system-level control signals (for example, interrupt and write enable signals) that can
be asserted by any of several devices.
Bus Hold
Each Arria GX device I/O pin provides an optional bus-hold feature. Bus-hold
circuitry can hold the signal on an I/O pin at its last-driven state. Because the
bus-hold feature holds the last-driven state of the pin until the next input signal is
present, an external pull-up or pull-down resistor is not needed to hold a signal level
when the bus is tri-stated.
Bus-hold circuitry also pulls undriven pins away from the input threshold voltage
where noise can cause unintended high-frequency switching. You can select this
feature individually for each I/O pin. The bus-hold output drives no higher than
VCCIO to prevent overdriving signals. If the bus-hold feature is enabled, the
programmable pull-up option cannot be used. Disable the bus-hold feature when the
I/O pin has been configured for differential signals.
Bus-hold circuitry uses a resistor with a nominal resistance (RBH) of approximately
7 k to pull the signal level to the last-driven state. This information is provided for
each VCCIO voltage level. Bus-hold circuitry is active only after configuration. When
going into user mode, the bus-hold circuit captures the value on the pin present at the
end of configuration.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
I/O Structure
f
2–93
For the specific sustaining current driven through this resistor and overdrive current
used to identify the next-driven input level, refer to the DC & Switching Characteristics
chapter.
Programmable Pull-Up Resistor
Each Arria GX device I/O pin provides an optional programmable pull-up resistor
during user mode. If you enable this feature for an I/O pin, the pull-up resistor
(typically 25 k) holds the output to the VCCIO level of the output pin’s bank.
Advanced I/O Standard Support
Arria GX device IOEs support the following I/O standards:
© December 2009
■
3.3-V LVTTL/LVCMOS
■
2.5-V LVTTL/LVCMOS
■
1.8-V LVTTL/LVCMOS
■
1.5-V LVCMOS
■
3.3-V PCI
■
3.3-V PCI-X mode 1
■
LVDS
■
LVPECL (on input and output clocks only)
■
Differential 1.5-V HSTL class I and II
■
Differential 1.8-V HSTL class I and II
■
Differential SSTL-18 class I and II
■
Differential SSTL-2 class I and II
■
1.2-V HSTL class I and II
■
1.5-V HSTL class I and II
■
1.8-V HSTL class I and II
■
SSTL-2 class I and II
■
SSTL-18 class I and II
Altera Corporation
Arria GX Device Handbook, Volume 1
2–94
Chapter 2: Arria GX Architecture
I/O Structure
Table 2–25 describes the I/O standards supported by Arria GX devices.
Table 2–25. Arria GX Devices Supported I/O Standards
I/O Standard
Type
Input Reference
Voltage
(VREF ) (V)
Output Supply
Voltage
(VCCIO ) (V)
Board
Termination
Voltage (VTT ) (V)
LVTTL
Single-ended
—
3.3
—
LVCMOS
Single-ended
—
3.3
—
2.5 V
Single-ended
—
2.5
—
1.8 V
Single-ended
—
1.8
—
1.5-V LVCMOS
Single-ended
—
1.5
—
3.3-V PCI
Single-ended
—
3.3
—
3.3-V PCI-X mode 1
Single-ended
—
3.3
—
LVDS
Differential
—
2.5 (3)
—
LVPECL (1)
Differential
—
3.3
—
HyperTransport technology
Differential
—
2.5 (3)
—
Differential 1.5-V HSTL class I and II (2) Differential
0.75
1.5
0.75
Differential 1.8-V HSTL class I and II (2) Differential
0.90
1.8
0.90
Differential SSTL-18 class I and II (2)
Differential
0.90
1.8
0.90
Differential SSTL-2 class I and II (2)
Differential
1.25
2.5
1.25
1.2-V HSTL (4)
Voltage-referenced
0.6
1.2
0.6
1.5-V HSTL class I and II
Voltage-referenced
0.75
1.5
0.75
1.8-V HSTL class I and II
Voltage-referenced
0.9
1.8
0.9
SSTL-18 class I and II
Voltage-referenced
0.90
1.8
0.90
SSTL-2 class I and II
Voltage-referenced
1.25
2.5
1.25
Notes to Table 2–25:
(1) This I/O standard is only available on input and output column clock pins.
(2) This I/O standard is only available on input clock pins and DQS pins in I/O banks 3, 4, 7, and 8, and output clock pins in I/O banks 9, 10, 11,
and 12.
(3) VCCIO is 3.3 V when using this I/O standard in input and output column clock pins (in I/O banks 3, 4, 7, 8, 9, 10, 11, and 12).
(4) 1.2-V HSTL is only supported in I/O banks 4, 7, and 8.
f
For more information about the I/O standards supported by Arria GX I/O banks,
refer to the Selectable I/O Standards in Arria GX Devices chapter.
Arria GX devices contain six I/O banks and four enhanced PLL external clock output
banks, as shown in Figure 2–78. The two I/O banks on the left of the device contain
circuitry to support source-synchronous, high-speed differential I/O for LVDS inputs
and outputs. These banks support all Arria GX I/O standards except PCI or PCI-X
I/O pins, and SSTL-18 class II and HSTL outputs. The top and bottom I/O banks
support all single-ended I/O standards. Additionally, enhanced PLL external clock
output banks allow clock output capabilities such as differential support for SSTL and
HSTL.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
I/O Structure
2–95
Figure 2–78. Arria GX I/O Banks
DQS ×8
PLL7
DQS ×8
(Note 1), (2)
DQS ×8
DQS ×8
VREF0B3 VREF1B3 VREF2B3 VREF3B3 VREF4B3
Bank 11
Bank 2
VREF3B1 VREF4B1
PLL2
DQS ×8
DQS ×8
DQS ×8
DQS ×8
Bank 4
Bank 9
This I/O bank supports LVDS
and LVPECL standards for input clock
operation. Differential HSTL and
differential SSTL standards are
supported for both input and output
operations. (3)
Bank 1
Bank 8
VREF4B8 VREF3B8 VREF2B8 VREF1B8 VREF0B8
DQS ×8
DQS ×8
DQS ×8
DQS ×8
Bank 12
Bank 10
PLL12
PLL6
Transmitter: Bank 13
Receiver: Bank 13
REFCLK: Bank 13
Transmitter: Bank 14
Receiver: Bank 14
REFCLK: Bank 14
I/O banks 7, 8, 10 and 12 support all single-ended I/O
standards for both input and output operations. All differential
I/O standards are supported for both input and output operations
at I/O banks 10 and 12.
This I/O bank supports LVDS
This I/O bank supports LVDS
and LVPECL standards for input clock operation.
and LVPECL standards for input clock
Differential HSTL and differential
operation. Differential HSTL and differential
SSTL standards are supported
SSTL standards are supported
for both input and output operations. (3)
for both input and output operations. (3)
VREF0B1 VREF1B1
VREF2B1
DQS ×8
VREF0B4 VREF1B4 VREF2B4 VREF3B4 VREF4B4
I/O banks 1 & 2 support LVTTL, LVCMOS,
2.5 V, 1.8 V, 1.5 V, SSTL-2, SSTL-18 class I,
LVDS, pseudo-differential SSTL-2 and pseudo-differential
SSTL-18 class I standards for both input and output
operations. HSTL, SSTL-18 class II,
pseudo-differential HSTL and pseudo-differential
SSTL-18 class II standards are only supported for
input operations. (4)
PLL1
PLL8
PLL5
This I/O bank supports LVDS
and LVPECL standards
for input clock operations. Differential HSTL
and differential SSTL standards
are supported for both input
and output operations. (3)
I/O Banks 3, 4, 9, and 11 support all single-ended
I/O standards for both input and output operations.
All differential I/O standards are supported for both
input and output operations at I/O banks 9 and 11.
VREF0B2 VREF1B2
VREF2B2
VREF3B2 VREF4B2
Bank 3
PLL11
Transmitter: Bank 15
Receiver: Bank 15
REFCLK: Bank 15
Bank 7
VREF4B7 VREF3B7 VREF2B7 VREF1B7 VREF0B7
DQS ×8
DQS ×8
DQS ×8
DQS ×8
DQS ×8
Notes to Figure 2–78:
(1) Figure 2–78 is a top view of the silicon die that corresponds to a reverse view for flip chip packages. It is a graphical representation only.
(2) Depending on the size of the device, different device members have different numbers of VREF groups. For the exact locations, refer to the pin list
and the Quartus II software.
(3) Banks 9 through 12 are enhanced PLL external clock output banks.
(4) Horizontal I/O banks feature SERDES and DPA circuitry for high-speed differential I/O standards. For more information about differential I/O
standards, refer to the High-Speed Differential I/O Interfaces in Arria GX Devices chapter.
Each I/O bank has its own VCCIO pins. A single device can support
1.5-, 1.8-, 2.5-, and 3.3-V interfaces; each bank can support a different VCCIO level
independently. Each bank also has dedicated VREF pins to support the
voltage-referenced standards (such as SSTL-2).
Each I/O bank can support multiple standards with the same VCCIO for input and
output pins. Each bank can support one VREF voltage level. For example, when VCCIO is
3.3 V, a bank can support LVTTL, LVCMOS, and 3.3-V PCI for inputs and outputs.
On-Chip Termination
Arria GX devices provide differential (for the LVDS technology I/O standard) and
on-chip series termination to reduce reflections and maintain signal integrity. There is
no calibration support for these on-chip termination resistors. On-chip termination
simplifies board design by minimizing the number of external termination resistors
required. Termination can be placed inside the package, eliminating small stubs that
can still lead to reflections.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–96
Chapter 2: Arria GX Architecture
I/O Structure
Arria GX devices provide two types of termination:
■
On-chip differential termination (R D OCT)
■
On-chip series termination (RS OCT)
Table 2–26 lists the Arria GX OCT support per I/O bank.
Table 2–26. On-Chip Termination Support by I/O Banks
On-Chip Termination Support
Series termination
Differential termination (1)
I/O Standard Support
Top and Bottom Banks
(3, 4, 7, 8)
Left Bank (1, 2)
3.3-V LVTTL
v
v
3.3-V LVCMOS
v
v
2.5-V LVTTL
v
v
2.5-V LVCMOS
v
v
1.8-V LVTTL
v
v
1.8-V LVCMOS
v
v
1.5-V LVTTL
v
v
1.5-V LVCMOS
v
v
SSTL-2 class I and II
v
v
SSTL-18 class I
v
v
SSTL-18 class II
v
—
1.8-V HSTL class I
v
v
1.8-V HSTL class II
v
—
1.5-V HSTL class I
v
v
1.2-V HSTL
v
—
LVDS
—
v
HyperTransport
technology
—
v
Note to Table 2–26:
(1) Clock pins CLK1 and CLK3, and pins FPLL[7..8]CLK do not support differential on-chip termination. Clock pins CLK0 and
CLK2, do support differential on-chip termination. Clock pins in the top and bottom banks (CLK[4..7, 12..15]) do not
support differential on-chip termination.
On-Chip Differential Termination (RD OCT)
Arria GX devices support internal differential termination with a nominal resistance
value of 100  for LVDS input receiver buffers. LVPECL input signals (supported on
clock pins only) require an external termination resistor. RD OCT is supported across
the full range of supported differential data rates as shown in the High-Speed I/O
Specifications section of the DC & Switching Characteristics chapter.
f
For more information about RD OCT, refer to the High-Speed Differential I/O Interfaces
with DPA in Arria GX Devices chapter.
f
For more information about tolerance specifications for R D OCT, refer to the DC &
Switching Characteristics chapter.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
I/O Structure
2–97
On-Chip Series Termination (R S OCT)
Arria GX devices support driver impedance matching to provide the I/O driver with
controlled output impedance that closely matches the impedance of the transmission
line. As a result, reflections can be significantly reduced. Arria GX devices support
RS OCT for single-ended I/O standards with typical R S values of 25 and 50 Once
matching impedance is selected, current drive strength is no longer selectable.
Table 2–26 shows the list of output standards that support RS OCT.
f
For more information about RS OCT supported by Arria GX devices, refer to the
Selectable I/O Standards in Arria GX Devices chapter.
f
For more information about tolerance specifications for OCT without calibration, refer
to the DC & Switching Characteristics chapter.
MultiVolt I/O Interface
The Arria GX architecture supports the MultiVolt I/O interface feature that allows
Arria GX devices in all packages to interface with systems of different supply
voltages. Arria GX VCCINT pins must always be connected to a 1.2-V power supply.
With a 1.2-V VCCINT level, input pins are 1.2-, 1.5-, 1.8-, 2.5-, and 3.3-V tolerant. The
VCCIO pins can be connected to either a 1.2-, 1.5-, 1.8-, 2.5-, or 3.3-V power supply,
depending on the output requirements. The output levels are compatible with
systems of the same voltage as the power supply (for example, when VCCIO pins are
connected to a 1.5-V power supply, the output levels are compatible with 1.5-V
systems). Arria GX VCCPD power pins must be connected to a 3.3-V power supply.
These power pins are used to supply the pre-driver power to the output buffers,
which increases the performance of the output pins. The VCCPD pins also power
configuration input pins and JTAG input pins.
Table 2–27 lists Arria GX MultiVolt I/O support.
Table 2–27. Arria GX MultiVolt I/O Support
(Note 1)
Input Signal (V)
VCCIO (V)
Output Signal (V)
1.2
1.5
1.8
2.5
3.3
1.2
1.5
1.8
2.5
3.3
5.0
1.2
(4)
v (2)
v (2)
v (2)
v (2)
v (4)
—
—
—
—
—
1.5
(4)
v
v
v (2)
v (2)
v (3)
v
—
—
—
—
1.8
(4)
v
v
v (2)
v (2)
v (3)
v (3)
v
—
—
—
2.5
(4)
—
—
v
v
v (3)
v (3)
v (3)
v
—
—
3.3
(4)
—
—
v
v
v (3)
v (3)
v (3)
v (3)
v
v
Notes to Table 2–27:
(1) To drive inputs higher than VC C IO but less than 4.0 V, disable the PCI clamping diode and select the Allow LVTTL and LVCMOS input levels to
overdrive input buffer option in the Quartus II software.
(2) The pin current may be slightly higher than the default value. You must verify that the driving device’s VO L maximum and VO H minimum voltages do
not violate the applicable Arria GX V I L maximum and V I H minimum voltage specifications.
(3) Although VCC I O specifies the voltage necessary for the Arria GX device to drive out, a receiving device powered at a different level can still interface
with the Arria GX device if it has inputs that tolerate the VC C I O value.
(4) Arria GX devices support 1.2-V HSTL. They do not support 1.2-V LVTTL and 1.2-V LVCMOS.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–98
Chapter 2: Arria GX Architecture
I/O Structure
The TDO and nCEO pins are powered by VCCIO of the bank that they reside. TDO is in
I/O bank 4 and nCEO is in I/O Bank 7. Ideally, the VCC supplies for the I/O buffers of
any two connected pins are at the same voltage level. This may not always be possible
depending on the VCCIO level of TDO and nCEO pins on master devices and the
configuration voltage level chosen by VCCSEL on slave devices. Master and slave
devices can be in any position in the chain. The master device indicates that it is
driving out TDO or nCEO to a slave device. For multi-device passive configuration
schemes, the nCEO pin of the master device drives the nCE pin of the slave device. The
VCCSEL pin on the slave device selects which input buffer is used for nCE. When
VCCSEL is logic high, it selects the 1.8-V/1.5-V buffer powered by VCCIO. When VCCSEL is
logic low, it selects the 3.3-V/2.5-V input buffer powered by VCCPD . The ideal case is to
have the VCC IO of the nCEO bank in a master device match the VCCSEL settings for the
nCE input buffer of the slave device it is connected to, but that may not be possible
depending on the application.
Table 2–28 contains board design recommendations to ensure that nCEO can
successfully drive nCE for all power supply combinations.
Table 2–28. Board Design Recommendations for nCEO and nCE Input Buffer Power
nCE Input Buffer Power
in I/O Bank 3
VCCSEL high
Arria GX nCEO VCCIO Voltage Level in I/O Bank 7
VC C I O = 3.3 V
VC C I O = 2.5 V
VC C I O = 1.8 V
VC C I O = 1.5 V
VC C I O = 1.2 V
v (1), (2)
v (3), (4)
v (5)
v
v
v (1), (2)
v (3), (4)
v
v
v
v (4)
v (6)
(VCC I O Bank 3 = 1.5 V)
VCCSEL high
(VCC I O Bank 3 = 1.8 V)
VCCSEL low (nCE
powered by
VC C P D = 3.3 V)
Level shifter
required
Level shifter
required
Level shifter
required
Notes to Table 2–28:
(1)
(2)
(3)
(4)
(5)
(6)
Input buffer is 3.3-V tolerant.
The nCEO output buffer meets VO H (MIN) = 2.4 V.
Input buffer is 2.5-V tolerant.
The nCEO output buffer meets VO H (MIN) = 2.0 V.
Input buffer is 1.8-V tolerant.
An external 250- pull-up resistor is not required, but recommended if signal levels on the board are not optimal.
For JTAG chains, the TDO pin of the first device drives the TDI pin of the second
device in the chain. The VCCSEL input on JTAG input I/O cells (TCK, TMS, TDI, and
TRST) is internally hardwired to GND selecting the 3.3-V/2.5-V input buffer powered
by VCCPD. The ideal case is to have the VCCIO of the TDO bank from the first device to
match the VCCSEL settings for TDI on the second device, but that may not be possible
depending on the application. Table 2–29 contains board design recommendations to
ensure proper JTAG chain operation.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
High-Speed Differential I/O with DPA Support
2–99
Table 2–29. Supported TDO/TDI Voltage Combinations
Device
Arria GX
TDI Input
Buffer Power
Arria GX TDO VC C I O Voltage Level in I/O Bank 4
VC C I O = 3.3 V
VC C I O = 2.5 V
VC C I O = 1.8 V
VC C I O = 1.5 V
VC C I O = 1.2 V
Always VC C P D
(3.3 V)
v (1)
v (2)
v (3)
Level shifter
required
Level shifter
required
VCC = 3.3 V
v (1)
v (2)
v (3)
Level shifter
required
Level shifter
required
VCC = 2.5 V
v (1), (4)
v (2)
v (3)
Level shifter
required
Level shifter
required
VCC = 1.8 V
v (1), (4)
v (2), (5)
v
Level shifter
required
Level shifter
required
VCC = 1.5 V
v (1), (4)
v (2), (5)
v (6)
v
v
Non-Arria GX
Notes to Table 2–29:
(1)
(2)
(3)
(4)
(5)
(6)
The TDO output buffer meets VOH (MIN) = 2.4 V.
The TDO output buffer meets VOH (MIN) = 2.0 V.
An external 250- pull-up resistor is not required, but recommended if signal levels on the board are not optimal.
Input buffer must be 3.3-V tolerant.
Input buffer must be 2.5-V tolerant.
Input buffer must be 1.8-V tolerant.
High-Speed Differential I/O with DPA Support
Arria GX devices contain dedicated circuitry for supporting differential standards at
speeds up to 840 Mbps. LVDS differential I/O standards are supported in the Arria
GX device. In addition, the LVPECL I/O standard is supported on input and output
clock pins on the top and bottom I/O banks.
The high-speed differential I/O circuitry supports the following high-speed I/O
interconnect standards and applications:
■
SPI-4 Phase 2 (POS-PHY Level 4)
■
SFI-4
■
Parallel RapidIO standard
There are two dedicated high-speed PLLs (PLL1 and PLL2) in the EP1AGX20 and
EP1AGX35 devices and up to four dedicated high-speed PLLs (PLL1, PLL2, PLL7,
and PLL8) in the EP1AGX50, EP1AGX60, and EP1AGX90 devices to multiply
reference clocks and drive high-speed differential SERDES channels in I/O banks 1
and 2.
Table 2–30 through Table 2–34 list the number of channels that each fast PLL can clock
in each of the Arria GX devices. In Table 2–30 through Table 2–34 the first row for each
transmitter or receiver provides the maximum number of channels that each fast PLL
can drive in its adjacent I/O bank (I/O Bank 1 or I/O Bank 2). The second row shows
the maximum number of channels that each fast PLL can drive in both I/O banks
(I/O Bank 1 and I/O Bank 2). For example, in the 780-pin FineLine BGA EP1AGX20
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–100
Chapter 2: Arria GX Architecture
High-Speed Differential I/O with DPA Support
device, PLL 1 can drive a maximum of 16 transmitter channels in I/O Bank 2 or a
maximum of 29 transmitter channels in I/O Banks 1 and 2. The Quartus II software
can also merge receiver and transmitter PLLs when a receiver is driving a transmitter.
In this case, one fast PLL can drive both the maximum numbers of receiver and
transmitter channels.
1
For more information, refer to the “Differential Pin Placement Guidelines” section in
the High-Speed Differential I/O Interfaces with DPA in Arria GX Devices chapter.
Table 2–30. EP1AGX20 Device Differential Channels
(Note 1)
Center Fast PLLs
Package
Transmitter/Receiver
Total Channels
Transmitter
29
Receiver
31
Transmitter
29
Receiver
31
484-pin FineLine BGA
780-pin FineLine GBA
PLL1
PLL2
16
13
13
16
17
14
14
17
16
13
13
16
17
14
14
17
Note to Table 2–30:
(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels.
Table 2–31. EP1AGX35 Device Differential Channels (Note 1)
Center Fast PLLs
Package
Transmitter/Receiver
Transmitter
484-pin FineLine BGA
780-pin FineLine BGA
Total Channels
29
Receiver
31
Transmitter
29
Receiver
31
PLL1
PLL2
16
13
13
16
17
14
14
17
16
13
13
16
17
14
14
17
Note to Table 2–31:
(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
High-Speed Differential I/O with DPA Support
2–101
Table 2–32. EP1AGX50 Device Differential Channels (Note 1)
Transmitter/
Receiver
Package
Transmitter
484-pin
FineLine BGA
Receiver
Transmitter
780-pin
FineLine BGA
Receiver
Transmitter
1,152-pin
FineLine BGA
Receiver
Center Fast PLLs
Corner Fast PLLs
Total Channels
29
31
29
31
42
42
PLL1
PLL2
PLL7
PLL8
16
13
—
—
13
16
—
—
17
14
—
—
14
17
—
—
16
13
—
—
13
16
—
—
17
14
—
—
14
17
—
—
21
21
21
21
21
21
—
—
21
21
21
21
21
21
—
—
Note to Table 2–32:
(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels.
Table 2–33. EP1AGX60 Device Differential Channels
Transmitter/
Receiver
Package
Transmitter
484-pin
FineLine BGA
Receiver
Transmitter
780-pin
FineLine BGA
Receiver
Transmitter
1,152-pin
FineLine BGA
Receiver
(Note 1)
Center Fast PLLs
Corner Fast PLLs
Total Channels
PLL1
29
31
29
31
42
42
PLL2
PLL7
PLL8
16
13
—
—
13
16
—
—
17
14
—
—
14
17
—
—
16
13
—
—
13
16
—
—
17
14
—
—
14
17
—
—
21
21
21
21
21
21
—
—
21
21
21
21
21
21
—
—
Note to Table 2–33:
(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–102
Chapter 2: Arria GX Architecture
High-Speed Differential I/O with DPA Support
Table 2–34. EP1AGX90 Device Differential Channels
(Note 1)
Center Fast PLLs
Package
Transmitter/Receiver
Total Channels
Transmitter
45
Receiver
47
1,152-pin FineLine
BGA
Corner Fast
PLLs
PLL1
PLL2
PLL7
23
22
23
22
23
—
23
24
23
24
23
—
Note to Table 2–34:
(1) The total number of receiver channels includes the four non-dedicated clock channels that can be optionally used as data channels.
Dedicated Circuitry with DPA Support
Arria GX devices support source-synchronous interfacing with LVDS signaling at up
to 840 Mbps. Arria GX devices can transmit or receive serial channels along with a
low-speed or high-speed clock.
The receiving device PLL multiplies the clock by an integer factor W = 1 through 32.
The SERDES factor J determines the parallel data width to deserialize from receivers
or to serialize for transmitters. The SERDES factor J can be set to 4, 5, 6, 7, 8, 9, or 10
and does not have to equal the PLL clock-multiplication W value. A design using the
dynamic phase aligner also supports all of these J factor values. For a J factor of 1, the
Arria GX device bypasses the SERDES block. For a J factor of 2, the Arria GX device
bypasses the SERDES block, and the DDR input and output registers are used in the
IOE. Figure 2–79 shows the block diagram of the Arria GX transmitter channel.
Figure 2–79. Arria GX Transmitter Channel
Data from R4, R24, C4, or
direct link interconnect
+
–
10
Local
Interconnect
Up to 840 Mbps
10
Dedicated
Transmitter
Interface
diffioclk
refclk
Fast
PLL
load_en
Regional or
global clock
Each Arria GX receiver channel features a DPA block for phase detection and
selection, a SERDES, a synchronizer, and a data realigner circuit. You can bypass the
dynamic phase aligner without affecting the basic source-synchronous operation of
the channel. In addition, you can dynamically switch between using the DPA block or
bypassing the block via a control signal from the logic array.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
High-Speed Differential I/O with DPA Support
2–103
Figure 2–80 shows the block diagram of the Arria GX receiver channel.
Figure 2–80. GX Receiver Channel
Data to R4, R24, C4, or
direct link interconnect
Up to 840 Mbps
+
–
D
Q
Data Realignment
Circuitry
10
data
retimed_data
DPA
Synchronizer
Dedicated
Receiver
Interface
DPA_clk
Eight Phase Clocks
8
diffioclk
refclk
Fast
PLL
load_en
Regional or
global clock
An external pin or global or regional clock can drive the fast PLLs, which can output
up to three clocks: two multiplied high-speed clocks to drive the SERDES block
and/or external pin, and a low-speed clock to drive the logic array. In addition, eight
phase-shifted clocks from the VCO can feed to the DPA circuitry.
f
For more information about fast PLL, refer to the PLLs in Arria GX Devices chapter.
The eight phase-shifted clocks from the fast PLL feed to the DPA block. The DPA
block selects the closest phase to the center of the serial data eye to sample the
incoming data. This allows the source-synchronous circuitry to capture incoming data
correctly regardless of channel-to-channel or clock-to-channel skew. The DPA block
locks to a phase closest to the serial data phase. The phase-aligned DPA clock is used
to write the data into the synchronizer.
The synchronizer sits between the DPA block and the data realignment and SERDES
circuitry. Because every channel using the DPA block can have a different phase
selected to sample the data, the synchronizer is needed to synchronize the data to the
high-speed clock domain of the data realignment and the SERDES circuitry.
For high-speed source-synchronous interfaces such as POS-PHY 4 and the Parallel
RapidIO standard, the source synchronous clock rate is not a byte- or SERDES-rate
multiple of the data rate. Byte alignment is necessary for these protocols because the
source synchronous clock does not provide a byte or word boundary as the clock is
one half the data rate, not one eighth. The Arria GX device’s high-speed differential
I/O circuitry provides dedicated data realignment circuitry for user-controlled byte
boundary shifting. This simplifies designs while saving ALM resources. You can use
an ALM-based state machine to signal the shift of receiver byte boundaries until a
specified pattern is detected to indicate byte alignment.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–104
Chapter 2: Arria GX Architecture
High-Speed Differential I/O with DPA Support
Fast PLL and Channel Layout
The receiver and transmitter channels are interleaved as such that each I/O bank on
the left side of the device has one receiver channel and one transmitter channel per
LAB row. Figure 2–81 shows the fast PLL and channel layout in the EP1AGX20C,
EP1AGX35C/D, EP1AGX50C/D and EP1AGX60C/D devices. Figure 2–82 shows the
fast PLL and channel layout in EP1AGX60E and EP1AGX90E devices.
Figure 2–81. Fast PLL and Channel Layout in EP1AGX20C, EP1AGX35C/D, EP1AGX50C/D, EP1AGX60C/D Devices (Note 1)
4
LVDS
Clock
DPA
Clock
Quadrant
Quadrant
Quadrant
Quadrant
4
2
Fast
PLL 1
Fast
PLL 2
2
4
LVDS
Clock
DPA
Clock
Note to Figure 2–81:
(1) For the number of channels each device supports, refer to Table 2–30.
Figure 2–82. Fast PLL and Channel Layout in EP1AGX60E and EP1AGX90E Devices (Note 1)
Fast
PLL 7
2
4
LVDS
Clock
DPA
Clock
Quadrant
Quadrant
DPA
Clock
Quadrant
Quadrant
4
2
Fast
PLL 1
Fast
PLL 2
2
4
LVDS
Clock
2
Fast
PLL 8
Note to Figure 2–82:
(1) For the number of channels each device supports, refer to Table 2–30 through Table 2–34.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 2: Arria GX Architecture
Document Revision History
2–105
Document Revision History
Table 2–35 shows the revision history for this chapter.
Table 2–35. Document Revision History
Date and Document Version
December 2009, v2.0
May 2008, v1.3
Changes Made
■
Document template update.
■
Minor text edits.
Summary of Changes
—
Added “Reverse Serial Pre-CDR Loopback”
and “Calibration Block” sub-sections to
“Transmitter Path” section.
—
August 2007, v1.2
Added “Referenced Documents” section.
—
June 2007, v1.1
Added GIGE information.
—
May 2007 v1.0
Initial release.
—
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
2–106
Arria GX Device Handbook, Volume 1
Chapter 2: Arria GX Architecture
Document Revision History
© December 2009
Altera Corporation
3. Configuration and Testing
AGX51003-2.0
Introduction
All Arria® GX devices provide JTAG boundary-scan test (BST) circuitry that complies
with the IEEE Std. 1149.1. You can perform JTAG boundary-scan testing either before
or after, but not during configuration. Arria GX devices can also use the JTAG port for
configuration with the Quartus® II software or hardware using either jam files (.jam)
or jam byte-code files (.jbc).
This chapter contains the following sections:
■
“IEEE Std. 1149.1 JTAG Boundary-Scan Support”
■
“SignalTap II Embedded Logic Analyzer” on page 3–3
■
“Configuration” on page 3–3
■
“Automated Single Event Upset (SEU) Detection” on page 3–8
IEEE Std. 1149.1 JTAG Boundary-Scan Support
Arria GX devices support I/O element (IOE) standard setting reconfiguration through
the JTAG BST chain. The JTAG chain can update the I/O standard for all input and
output pins any time before or during user-mode through the CONFIG_IO
instruction. You can use this capability for JTAG testing before configuration when
some of the Arria GX pins drive or receive from other devices on the board using
voltage-referenced standards. Because the Arria GX device may not be configured
before JTAG testing, the I/O pins may not be configured for appropriate electrical
standards for chip-to-chip communication. Programming these I/O standards via
JTAG allows you to fully test the I/O connections to other devices.
A device operating in JTAG mode uses four required pins, TDI, TDO, TMS, and TCK,
and one optional pin, TRST. The TCK pin has an internal weak pull-down resistor,
while the TDI, TMS, and TRST pins have weak internal pull-up resistors. The JTAG
input pins are powered by the 3.3-V VCCPD pins. The TDO output pin is powered by the
VCCIO power supply in I/O bank 4.
Arria GX devices also use the JTAG port to monitor the logic operation of the device
with the SignalTap ® II embedded logic analyzer. Arria GX devices support the JTAG
instructions shown in Table 3–1.
1
© December 2009
Arria GX, Cyclone® II, Cyclone, Stratix® , Stratix II, Stratix GX , and Stratix II GX
devices must be within the first 17 devices in a JTAG chain. All of these devices have
the same JTAG controller. If any of the Stratix, Arria GX, Cyclone, and Cyclone II
devices are in the 18th or further position, they will fail configuration. This does not
affect the functionality of the SignalTap ® II embedded logic analyzer.
Altera Corporation
Arria GX Device Handbook, Volume 1
3–2
Chapter 3: Configuration and Testing
IEEE Std. 1149.1 JTAG Boundary-Scan Support
Table 3–1. Arria GX JTAG Instructions
JTAG Instruction
Instruction Code
Description
SAMPLE/PRELOAD
00 0000 0101
Allows a snapshot of signals at the device pins to be captured
and examined during normal device operation and permits an
initial data pattern to be output at the device pins. Also used by
the SignalTap II embedded logic analyzer.
EXTEST (1)
00 0000 1111
Allows external circuitry and board-level interconnects to be
tested by forcing a test pattern at the output pins and capturing
test results at the input pins.
BYPASS
11 1111 1111
Places the 1-bit bypass register between the TDI and TDO pins,
which allows the BST data to pass synchronously through
selected devices to adjacent devices during normal device
operation.
USERCODE
00 0000 0111
Selects the 32-bit USERCODE register and places it between the
TDI and TDO pins, allowing the USERCODE to be serially shifted
out of TDO.
IDCODE
00 0000 0110
Selects the IDCODE register and places it between TDI and TDO ,
allowing IDCODE to be serially shifted out of TDO.
HIGHZ (1)
00 0000 1011
Places the 1-bit bypass register between the TDI and TDO pins,
which allows the BST data to pass synchronously through
selected devices to adjacent devices during normal device
operation, while tri-stating all of the I/O pins.
CLAMP (1)
00 0000 1010
Places the 1-bit bypass register between the TDI and TDO pins,
which allows the BST data to pass synchronously through
selected devices to adjacent devices during normal device
operation while holding I/O pins to a state defined by the data in
the boundary-scan register.
—
Used when configuring an Arria GX device via the JTAG port with
a USB-Blaster TM , MasterBlaster TM , ByteBlasterMVTM,
EthernetBlaster TM , or ByteBlaster II download cable, or when
using a .jam or .jbc via an embedded processor or JRunnerTM .
ICR instructions
PULSE_NCONFIG
00 0000 0001
Emulates pulsing the nCONFIG pin low to trigger
reconfiguration even though the physical pin is unaffected.
CONFIG_IO (2)
00 0000 1101
Allows configuration of I/O standards through the JTAG chain for
JTAG testing. Can be executed before, during, or after
configuration. Stops configuration if executed during
configuration. Once issued, the CONFIG_IO instruction holds
nSTATUS low to reset the configuration device. nSTATUS is
held low until the IOE configuration register is loaded and the
TAP controller state machine transitions to the UPDATE_DR
state.
Notes to Table 3–1:
(1) Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.
(2) For more information about using the CONFIG_IO instruction, refer to the MorphIO: An I/O Reconfiguration Solution for Altera Devices
White Paper.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 3: Configuration and Testing
SignalTap II Embedded Logic Analyzer
3–3
The Arria GX device instruction register length is 10 bits and the USERCODE register
length is 32 bits. Table 3–2 and Table 3–3 show the boundary-scan register length and
device IDCODE information for Arria GX devices.
Table 3–2. Arria GX Boundary-Scan Register Length
Device
Boundary-Scan Register Length
EP1AGX20
1320
EP1AGX35
1320
EP1AGX50
1668
EP1AGX60
1668
EP1AGX90
2016
Table 3–3. 2-Bit Arria GX Device IDCODE
IDCODE (32 Bits)
Device
Version (4 Bits)
Part Number (16 Bits)
Manufacturer Identity
(11 Bits)
LSB (1 Bit)
EP1AGX20
0000
0010 0001 0010 0001
000 0110 1110
1
EP1AGX35
0000
0010 0001 0010 0001
000 0110 1110
1
EP1AGX50
0000
0010 0001 0010 0010
000 0110 1110
1
EP1AGX60
0000
0010 0001 0010 0010
000 0110 1110
1
EP1AGX90
0000
0010 0001 0010 0011
000 0110 1110
1
SignalTap II Embedded Logic Analyzer
Arria GX devices feature the SignalTap II embedded logic analyzer, which monitors
design operation over a period of time through the IEEE Std. 1149.1 (JTAG) circuitry.
You can analyze internal logic at speed without bringing internal signals to the I/O
pins. This feature is particularly important for advanced packages, such as FineLine
BGA (FBGA) packages, because it can be difficult to add a connection to a pin during
the debugging process after a board is designed and manufactured.
Configuration
The logic, circuitry, and interconnects in the Arria GX architecture are configured with
CMOS SRAM elements. Altera® FPGAs are reconfigurable and every device is tested
with a high coverage production test program so you do not have to perform fault
testing and can instead focus on simulation and design verification.
Arria GX devices are configured at system power up with data stored in an Altera
configuration device or provided by an external controller (for example, a MAX ® II
device or microprocessor). You can configure Arria GX devices using the fast passive
parallel (FPP), active serial (AS), passive serial (PS), passive parallel asynchronous
(PPA), and JTAG configuration schemes. Each Arria GX device has an optimized
interface that allows microprocessors to configure it serially or in parallel, and
synchronously or asynchronously. The interface also enables microprocessors to treat
Arria GX devices as memory and configure them by writing to a virtual memory
location, making reconfiguration easy.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
3–4
Chapter 3: Configuration and Testing
Configuration
In addition to the number of configuration methods supported, Arria GX devices also
offer decompression and remote system upgrade features. The decompression feature
allows Arria GX FPGAs to receive a compressed configuration bitstream and
decompress this data in real-time, reducing storage requirements and configuration
time. The remote system upgrade feature allows real-time system upgrades from
remote locations of Arria GX designs. For more information, refer to “Configuration
Schemes” on page 3–5.
Operating Modes
The Arria GX architecture uses SRAM configuration elements that require
configuration data to be loaded each time the circuit powers up. The process of
physically loading the SRAM data into the device is called configuration. During
initialization, which occurs immediately after configuration, the device resets
registers, enables I/O pins, and begins to operate as a logic device. The I/O pins are
tri-stated during power up, and before and during configuration. Together, the
configuration and initialization processes are called command mode. Normal device
operation is called user mode.
SRAM configuration elements allow you to reconfigure Arria GX devices in-circuit by
loading new configuration data into the device. With real-time reconfiguration, the
device is forced into command mode with a device pin. The configuration process
loads different configuration data, re-initializes the device, and resumes user-mode
operation. You can perform in-field upgrades by distributing new configuration files
either within the system or remotely.
PORSEL is a dedicated input pin used to select power-on reset (POR) delay times of
12 ms or 100 ms during power up. When the PORSEL pin is connected to ground, the
POR time is 100 ms. When the PORSEL pin is connected to VCC, the POR time is 12 ms.
The nIO_PULLUP pin is a dedicated input that chooses whether the internal pull-up
resistors on the user I/O pins and dual-purpose configuration I/O pins (nCSO, ASDO,
DATA[7..0], nWS, nRS, RDYnBSY, nCS, CS, RUnLU, PGM[2..0], CLKUSR,
INIT_DONE, DEV_OE, DEV_CLR) are on or off before and during configuration. A
logic high (1.5, 1.8, 2.5, 3.3 V) turns off the weak internal pull-up resistors, while a
logic low turns them on.
Arria GX devices also offer a new power supply, V C CPD, which must be connected to
3.3 V in order to power the 3.3-V/2.5-V buffer available on the configuration input
pins and JTAG pins. VCCPD applies to all the JTAG input pins (TCK, TMS, TDI, and
TRST) and the following configuration pins: nCONFIG, DCLK (when used as an input),
nIO_PULLUP, DATA[7..0], RUnLU, nCE, nWS, nRS, CS, nCS, and CLKUSR. The VCCSEL
pin allows the VCCIO setting (of the banks where the configuration inputs reside) to be
independent of the voltage required by the configuration inputs. Therefore, when
selecting the VCCIO voltage, you do not have to take the VIL and VIH levels driven to
the configuration inputs into consideration. The configuration input pins, nCONFIG,
DCLK (when used as an input), nIO_PULLUP, RUnLU, nCE, nWS, nRS, CS, nCS, and
CLKUSR, have a dual buffer design: a 3.3-V/2.5-V input buffer and a 1.8-V/1.5-V
input buffer. The VCCSEL input pin selects which input buffer is used. The 3.3-V/2.5-V
input buffer is powered by VCCPD , while the 1.8-V/1.5-V input buffer is powered by
VCCIO.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 3: Configuration and Testing
Configuration
3–5
VCCSEL is sampled during power up. Therefore, the V CCSEL setting cannot change
on-the-fly or during a reconfiguration. The V CCSEL input buffer is powered by VCCINT
and must be hard-wired to VC CPD or ground. A logic high VCC SEL connection selects the
1.8-V/1.5-V input buffer, and a logic low selects the 3.3-V/2.5-V input buffer. VCCSEL
should be set to comply with the logic levels driven out of the configuration device or
MAX II microprocessor.
If the design must support configuration input voltages of 3.3 V/2.5 V, set VCCSEL to a
logic low. You can set the VCCIO voltage of the I/O bank that contains the configuration
inputs to any supported voltage. If the design must support configuration input
voltages of 1.8 V/1.5 V, set VCCSEL to a logic high and the VCCIO of the bank that
contains the configuration inputs to 1.8 V/1.5 V.
f
For more information about multi-volt support, including information about using
TDO and nCEO in multi-volt systems, refer to the Arria GX Architecture chapter.
Configuration Schemes
You can load the configuration data for an Arria GX device with one of five
configuration schemes (refer to Table 3–4), chosen on the basis of the target
application. You can use a configuration device, intelligent controller, or the JTAG
port to configure an Arria GX device. A configuration device can automatically
configure an Arria GX device at system power up.
You can configure multiple Arria GX devices in any of the five configuration schemes
by connecting the configuration enable (nCE) and configuration enable output (nCEO)
pins on each device. Arria GX FPGAs offer the following:
■
Configuration data decompression to reduce configuration file storage
■
Remote system upgrades for remotely updating Arria GX designs
Table 3–4 lists which configuration features can be used in each configuration scheme.
f
For more information about configuration schemes in Arria GX devices, refer to the
Configuring Arria GX Devices chapter.
Table 3–4. Arria GX Configuration Features (Part 1 of 2)
Configuration Scheme
FPP
AS
PS
PPA
© December 2009
Configuration Method
Decompression
Remote System Upgrade
MAX II device or microprocessor
and flash device
v (1)
v
Enhanced configuration device
v (2)
v
Serial configuration device
v
v (3)
MAX II device or microprocessor
and flash device
v
v
Enhanced configuration device
v
v
Download cable (4)
v
—
MAX II device or microprocessor
and flash device
—
v
Altera Corporation
Arria GX Device Handbook, Volume 1
3–6
Chapter 3: Configuration and Testing
Configuration
Table 3–4. Arria GX Configuration Features (Part 2 of 2)
Configuration Scheme
JTAG
Configuration Method
Decompression
Remote System Upgrade
Download cable (4)
—
—
MAX II device or microprocessor
and flash device
—
—
Notes for Table 3–4:
(1)
(2)
(3)
(4)
In these modes, the host system must send a DCLK that is 4× the data rate.
The enhanced configuration device decompression feature is available, while the Arria GX decompression feature is not available.
Only remote update mode is supported when using the AS configuration scheme. Local update mode is not supported.
The supported download cables include the Altera USB-Blaster universal serial bus (USB) port download cable, MasterBlaster ™ serial/USB
communications cable, ByteBlaster II parallel port download cable, ByteBlasterMV parallel port download cable, and the EthernetBlaster
download cable.
Device Configuration Data Decompression
Arria GX FPGAs support decompression of configuration data, which saves
configuration memory space and time. This feature allows you to store compressed
configuration data in configuration devices or other memory and transmit this
compressed bitstream to Arria GX FPGAs. During configuration, the Arria GX FPGA
decompresses the bitstream in real time and programs its SRAM cells. Arria GX
FPGAs support decompression in the FPP (when using a MAX II device or
microprocessor and flash memory), AS, and PS configuration schemes.
Decompression is not supported in the PPA configuration scheme nor in JTAG-based
configuration.
Remote System Upgrades
Shortened design cycles, evolving standards, and system deployments in remote
locations are difficult challenges faced by system designers. Arria GX devices can help
effectively deal with these challenges with their inherent re programmability and
dedicated circuitry to perform remote system updates. Remote system updates help
deliver feature enhancements and bug fixes without costly recalls, reduce time to
market, and extend product life.
Arria GX FPGAs feature dedicated remote system upgrade circuitry to facilitate
remote system updates. Soft logic (Nios® processor or user logic) implemented in the
Arria GX device can download a new configuration image from a remote location,
store it in configuration memory, and direct the dedicated remote system upgrade
circuitry to initiate a reconfiguration cycle. The dedicated circuitry performs error
detection during and after the configuration process, recovers from any error
condition by reverting back to a safe configuration image, and provides error status
information. This dedicated remote system upgrade circuitry avoids system
downtime and is the critical component for successful remote system upgrades.
Remote system configuration is supported in the following Arria GX configuration
schemes: FPP, AS, PS, and PPA. You can also implement remote system configuration
in conjunction with Arria GX features such as real-time decompression of
configuration data for efficient field upgrades.
f
For more information about remote configuration in Arria GX devices, refer to the
Remote System Upgrades with Arria GX Devices chapter.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 3: Configuration and Testing
Configuration
3–7
Configuring Arria GX FPGAs with JRunner
The JRunner software driver configures Altera FPGAs, including Arria GX FPGAs,
through the ByteBlaster™ II or ByteBlasterMV cables in JTAG mode. The
programming input file supported is in Raw Binary File (.rbf) format. JRunner also
requires a Chain Description File (.cdf) generated by the Quartus II software. JRunner
is targeted for embedded JTAG configuration. The source code is developed for the
Windows NT operating system (OS), but can be customized to run on other platforms.
f
For more information about the JRunner software driver, refer to the AN414: JRunner
Software Driver: An Embedded Solution for PLD JTAG Configuration and the source files
on the Altera website.
Programming Serial Configuration Devices with SRunner
You can program a serial configuration device in-system by an external
microprocessor using SRunnerTM . SRunner is a software driver developed for
embedded serial configuration device programming that can be easily customized to
fit into different embedded systems. SRunner software driver reads a raw
programming data file (.rpd) and writes to serial configuration devices. The serial
configuration device programming time using SRunner software driver is comparable
to the programming time when using the Quartus II software.
f
For more information about SRunner, refer to the AN418: SRunner: An Embedded
Solution for Serial Configuration Device Programming and the source code on the Altera
website.
f
For more information about programming serial configuration devices, refer to the
Serial Configuration Devices (EPCS1, EPCS4, EPCS64, and EPCS128) Data Sheet in the
Configuration Handbook.
Configuring Arria GX FPGAs with the MicroBlaster Driver
The MicroBlaster™ software driver supports a raw binary file (RBF) programming
input file and is ideal for embedded FPP or PS configuration. The source code is
developed for the Windows NT operating system, although it can be customized to
run on other operating systems.
f
For more information about the MicroBlaster software driver, refer to the Configuring
the MicroBlaster Fast Passive Parallel Software Driver White Paper or the AN423:
Configuring the MicroBlaster Passive Serial Software Driver.
PLL Reconfiguration
The phase-locked loops (PLLs) in the Arria GX device family support reconfiguration
of their multiply, divide, VCO-phase selection, and bandwidth selection settings
without reconfiguring the entire device. You can use either serial data from the logic
array or regular I/O pins to program the PLL’s counter settings in a serial chain. This
option provides considerable flexibility for frequency synthesis, allowing real-time
variation of the PLL frequency and delay. The rest of the device is functional while
reconfiguring the PLL.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
3–8
Chapter 3: Configuration and Testing
Automated Single Event Upset (SEU) Detection
f
For more information about Arria GX PLLs, refer to the PLLs in Arria GX Devices
chapter.
Automated Single Event Upset (SEU) Detection
Arria GX devices offer on-chip circuitry for automated checking of single event upset
(SEU) detection. Some applications that require the device to operate error free at high
elevations or in close proximity to Earth’s North or South Pole requires periodic
checks to ensure continued data integrity. The error detection cyclic redundancy
check (CRC) feature controlled by the Device and Pin Options dialog box in the
Quartus II software uses a 32-bit CRC circuit to ensure data reliability and is one of
the best options for mitigating SEU.
You can implement the error detection CRC feature with existing circuitry in Arria GX
devices, eliminating the need for external logic. Arria GX devices compute CRC
during configuration. The Arria GX device checks the computed-CRC against an
automatically computed CRC during normal operation. The CRC_ERROR pin reports
a soft error when configuration SRAM data is corrupted, triggering device
reconfiguration.
Custom-Built Circuitry
Dedicated circuitry is built into Arria GX devices to automatically perform error
detection. This circuitry constantly checks for errors in the configuration SRAM cells
while the device is in user mode. You can monitor one external pin for the error and
use it to trigger a reconfiguration cycle. You can select the desired time between
checks by adjusting a built-in clock divider.
Software Interface
Beginning with version 7.1 of the Quartus II software, you can turn on the automated
error detection CRC feature in the Device and Pin Options dialog box. This dialog
box allows you to enable the feature and set the internal frequency of the CRC
between 400 kHz to 50 MHz. This controls the rate that the CRC circuitry verifies the
internal configuration SRAM bits in the Arria GX FPGA.
f
For more information about CRC, refer to AN 357: Error Detection Using CRC in Altera
FPGAs.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 3: Configuration and Testing
Document Revision History
3–9
Document Revision History
Table 3–5 lists the revision history for this chapter.
Table 3–5. Document Revision History
Date and Document Version
December 2009, v2.0
May 2009
v1.4
May 2008
Changes Made
■
Document template update.
■
Minor text edits.
■
Removed “Temperature Sensing
Diode” section.
■
Updated Table 3–1 and Table 3–4.
Summary of Changes
—
—
Updated note in “Introduction”
section.
v1.3
Minor text edits.
—
Added the “Referenced Documents”
section.
—
Deleted Signal Tap II information
from Table 3–1.
—
v1.1
May 2007
Initial Release
—
August 2007
v1.2
June 2007
v1.0
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
3–10
Chapter 3: Configuration and Testing
Document Revision History
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
4. DC and Switching Characteristics
AGX51004-2.0
Operating Conditions
Arria® GX devices are offered in both commercial and industrial grades. Both
commercial and industrial devices are offered in –6 speed grade only.
This chapter contains the following sections:
■
“Operating Conditions”
■
“Power Consumption” on page 4–25
■
“I/O Timing Model” on page 4–26
■
“Typical Design Performance” on page 4–32
■
“Block Performance” on page 4–84
■
“IOE Programmable Delay” on page 4–86
■
“Maximum Input and Output Clock Toggle Rate” on page 4–87
■
“Duty Cycle Distortion” on page 4–95
■
“High-Speed I/O Specifications” on page 4–100
■
“PLL Timing Specifications” on page 4–103
■
“External Memory Interface Specifications” on page 4–105
■
“JTAG Timing Specifications” on page 4–106
Table 4–1 through Table 4–42 on page 4–25 provide information on absolute
maximum ratings, recommended operating conditions, DC electrical characteristics,
and other specifications for Arria GX devices.
Absolute Maximum Ratings
Table 4–1 contains the absolute maximum ratings for the Arria GX device family.
Table 4–1. Arria GX Device Absolute Maximum Ratings
Symbol
Parameter
(Note 1), (2), (3) (Part 1 of 2)
Conditions
Minimum
Maximum
Units
VCCINT
Supply voltage
With respect to ground
–0.5
1.8
V
VCCIO
Supply voltage
With respect to ground
–0.5
4.6
V
VCCPD
Supply voltage
With respect to ground
–0.5
4.6
V
VI
DC input voltage (4)
–0.5
4.6
V
IOUT
DC output current, per pin
–25
40
mA
TSTG
Storage temperature
–65
150
C
© December 2009
Altera Corporation
—
—
No bias
Arria GX Device Handbook, Volume 1
4–2
Chapter 4: DC and Switching Characteristics
Operating Conditions
Table 4–1. Arria GX Device Absolute Maximum Ratings
Symbol
Parameter
TJ
(Note 1), (2), (3) (Part 2 of 2)
Conditions
Junction temperature
Minimum
Maximum
Units
–55
125
C
BGA packages under bias
Notes to Table 4–1:
(1) For more information about operating requirements for Altera® devices, refer to the Arria GX Device Family Data Sheet chapter.
(2) Conditions beyond those listed in Table 4–1 may cause permanent damage to a device. Additionally, device operation at the absolute maximum
ratings for extended periods of time may have adverse affects on the device.
(3) Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply.
(4) During transitions, the inputs may overshoot to the voltage shown in Table 4–2 based upon the input duty cycle. The DC case is equivalent to
100% duty cycle. During transitions, the inputs may undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns.
Table 4–2. Maximum Duty Cycles in Voltage Transitions
Symbol
VI
Parameter
Maximum duty cycles in
voltage transitions
(Note 1)
Condition
Maximum Duty Cycles (%)
VI = 4.0 V
100
VI = 4.1 V
90
VI = 4.2 V
50
VI = 4.3 V
30
VI = 4.4 V
17
VI = 4.5 V
10
Note to Table 4–2:
(1) During transition, the inputs may overshoot to the voltages shown based on the input duty cycle. The DC case is
equivalent to 100% duty cycle.
Recommended Operating Conditions
Table 4–3 lists the recommended operating conditions for the Arria GX device family.
Table 4–3. Arria GX Device Recommended Operating Conditions (Part 1 of 2)
Symbol
Parameter
Conditions
(Note 1) (Part 1 of 2)
Minimum
Maximum
Units
1.15
1.25
V
Supply voltage for internal
logic and input buffers
Rise time  100 ms (3)
Supply voltage for output
buffers, 3.3-V operation
Rise time  100 ms (3), (6)
3.135
(3.00)
3.465
(3.60)
V
Supply voltage for output
buffers, 2.5-V operation
Rise time  100 ms (3)
2.375
2.625
V
Supply voltage for output
buffers, 1.8-V operation
Rise time  100 ms (3)
1.71
1.89
V
Supply voltage for output
buffers, 1.5-V operation
Rise time  100 ms (3)
1.425
1.575
V
Supply voltage for output
buffers, 1.2-V operation
Rise time  100 ms (3)
1.15
1.25
V
Supply voltage for pre-drivers
as well as configuration and
JTAG I/O buffers.
100 s  rise time  100 ms (4)
3.135
3.465
V
VCCPD
VI
Input voltage
(refer to Table 4–2)
(2), (5)
–0.5
4.0
V
VO
Output voltage
0
VCCIO
V
VCCINT
VCCIO
Arria GX Device Handbook, Volume 1
—
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Operating Conditions
4–3
Table 4–3. Arria GX Device Recommended Operating Conditions (Part 2 of 2)
Symbol
Parameter
TJ
Operating junction temperature
(Note 1) (Part 2 of 2)
Conditions
Minimum
Maximum
Units
0
85
C
–40
100
C
For commercial use
For industrial use
Notes to Table 4–3:
(1) Supply voltage specifications apply to voltage readings taken at the device pins, not at the power supply.
(2) During transitions, the inputs may overshoot to the voltage shown in Table 4–2 based upon the input duty cycle. The DC case is equivalent to
100% duty cycle. During transitions, the inputs may undershoot to –2.0 V for input currents less than 100 mA and periods shorter than 20 ns.
(3) Maximum VCC rise time is 100 ms, and VCC must rise monotonically from ground to VCC .
(4) VCCPD must ramp-up from 0 V to 3.3 V within 100 s to 100 ms. If VCCPD is not ramped up within this specified time, the Arria GX device will
not configure successfully. If the system does not allow for a V CCPD ramp-up time of 100 ms or less, hold nCONFIG low until all power supplies
are reliable.
(5) All pins, including dedicated inputs, clock, I/O, and JTAG pins, can be driven before VCCINT, VCCPD, and VCCIO are powered.
(6) VCCIO maximum and minimum conditions for PCI and PCI-X are shown in parentheses.
Transceiver Block Characteristics
Table 4–4 through Table 4–6 on page 4–4 contain transceiver block specifications.
Table 4–4. Arria GX Transceiver Block Absolute Maximum Ratings
Symbol
Parameter
(Note 1)
Conditions
Minimum
Maximum
Units
VCCA
Transceiver block supply voltage
Commercial and industrial
–0.5
4.6
V
VCCP
Transceiver block supply voltage
Commercial and industrial
–0.5
1.8
V
VCCR
Transceiver block supply voltage
Commercial and industrial
–0.5
1.8
V
VCCT_B
Transceiver block supply voltage
Commercial and industrial
–0.5
1.8
V
VCCL_B
Transceiver block supply voltage
Commercial and industrial
–0.5
1.8
V
VCCH_B
Transceiver block supply voltage
Commercial and industrial
–0.5
2.4
V
Note to Table 4–4:
(1) The device can tolerate prolonged operation at this absolute maximum, as long as the maximum specification is not violated.
Table 4–5. Arria GX Transceiver Block Operating Conditions
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Units
VCCA
Transceiver block supply voltage
Commercial and industrial
3.135
3.3
3.465
V
VCCP
Transceiver block supply voltage
Commercial and industrial
1.15
1.2
1.25
V
VCCR
Transceiver block supply voltage
Commercial and industrial
1.15
1.2
1.25
V
VCCT_B
Transceiver block supply voltage
Commercial and industrial
1.15
1.2
1.25
V
VCCL_B
Transceiver block supply voltage
Commercial and industrial
1.15
1.2
1.25
V
1.15
1.2
1.25
V
1.425
1.5
1.575
V
2K - 1%
2K
2K +1%

VCCH_B
Transceiver block supply voltage
Commercial and industrial
RREFB (1)
Reference resistor
Commercial and industrial
Note to Table 4–5:
(1) The DC signal on this pin must be as clean as possible. Ensure that no noise is coupled to this pin.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
4–4
Chapter 4: DC and Switching Characteristics
Operating Conditions
Table 4–6. Arria GX Transceiver Block AC Specification (Part 1 of 3)
Symbol / Description
Conditions
–6 Speed Grade Commercial and
Industrial
Min
Typ
Max
Units
Reference clock
Input reference clock frequency
—
50
—
622.08
MHz
Absolute VM A X for a REFCLK Pin
—
—
—
3.3
V
Absolute VMIN for a REFCLK Pin
—
–0.3
—
—
V
Rise/Fall time
—
—
0.2
—
UI
Duty cycle
—
45
—
55
%
Peak to peak differential input voltage VID
(diff p-p)
—
200
—
2000
mV
Spread spectrum clocking (1)
0 to –0.5%
30
—
33
kHz
On-chip termination resistors
—
115 ± 20%

VICM (AC coupled)
—
1200 ± 5%
mV
VICM (DC coupled) (2)
RREFB
PCI Express
(PIPE) mode
0.25
—
—
0.55
V

2000 +/-1%
Transceiver Clocks
Calibration block clock frequency
—
10
—
125
MHz
Calibration block minimum power-down
pulse width
—
30
—
—
ns
fixedclk clock frequency (3)
reconfig clock frequency
—
125 ±10%
MHz
SDI mode
2.5
—
50
MHz
—
100
—
—
ns
Data rate
—
600
—
3125
Mbps
Absolute VMAX for a receiver pin (4)
—
—
—
2.0
V
Absolute VMIN for a receiver pin
—
–0.4
—
—
V
Maximum peak-to-peak differential input
voltage VID (diff p-p)
Vicm = 0.85 V
—
—
3.3
V
Minimum peak-to-peak differential input
voltage VID (diff p-p)
DC Gain = 3 dB
160
—
—
mV
Transceiver block minimum power-down
pulse width
Receiver
On-chip termination resistors
VICM (15)
Bandwidth at 3.125 Gbps
Arria GX Device Handbook, Volume 1
—
100±15%

Vicm = 0.85 V
setting
850 ± 10% 850 ± 10% 850 ± 10%
mV
Vicm = 1.2 V
setting
1200 ±
10%
1200 ±
10%
1200 ±
10%
BW = Low
—
30
—
BW = Med
—
40
—
BW = High
—
50
—
© December 2009
mV
MHz
Altera Corporation
Chapter 4: DC and Switching Characteristics
Operating Conditions
4–5
Table 4–6. Arria GX Transceiver Block AC Specification (Part 2 of 3)
Symbol / Description
Bandwidth at 2.5 Gbps
Return loss differential mode
Conditions
–6 Speed Grade Commercial and
Industrial
Min
Typ
Max
BW = Low
—
35
—
BW = Med
—
50
—
BW = High
—
60
—
50 MHz to 1.25
GHz
(PCI Express)
Units
MHz
–10
dB
–6
dB
100 MHz to 2.5
GHz (XAUI)
Return loss common mode
50 MHz to 1.25
GHz
(PCI Express)
100 MHz to 2.5
GHz (XAUI)
Programmable PPM detector (5)
—
± 62.5, 100, 125, 200, 250, 300, 500,
1000
PPM
Run length (6)
—
80
UI
Programmable equalization
—
—
—
5
dB
Signal detect/loss threshold (7)
—
65
—
175
mV
CDR LTR TIme (8), (9)
—
—
—
75
us
CDR Minimum T1b (9), (10)
—
15
—
—
us
LTD lock time (9), (11)
—
0
100
4000
ns
Data lock time from rx_freqlocked (9),
(12)
—
—
—
4
us
Programmable DC gain
—
0, 3, 6
dB
Output Common Mode voltage (Vocm)
—
580 ± 10%
mV
On-chip termination resistors
—
108±10%

Transmitter Buffer
50 MHz to 1.25
GHz (PCI Express)
Return loss differential mode
dB
–10
312 MHz to 625
MHz (XAUI)
625 MHz to
3.125GHz (XAUI)
Return loss common mode
50 MHz to 1.25
GHz (PCI Express)
–10
dB
-----------------------------------decade slope
–6
dB
Rise time
—
35
—
65
ps
Fall time
—
35
—
65
ps
VOD = 800 mV
—
—
15
ps
—
—
—
100
ps
Intra differential pair skew
Intra-transceiver block skew (×4) (13)
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
4–6
Chapter 4: DC and Switching Characteristics
Operating Conditions
Table 4–6. Arria GX Transceiver Block AC Specification (Part 3 of 3)
Symbol / Description
Conditions
–6 Speed Grade Commercial and
Industrial
Units
Min
Typ
Max
—
500
—
1562.5
BW = Low
—
3
—
BW = Med
—
5
—
BW = High
—
9
—
BW = Low
—
1
—
BW = Med
—
2
—
BW = High
—
4
—
—
—
—
100
us
Interface speed per mode
—
25
—
156.25
MHz
Digital Reset Pulse Width
—
Transmitter PLL
VCO frequency range
Bandwidth at 3.125 Gbps
Bandwidth at 2.5 Gbps
TX PLL lock time from gxb_powerdown
de-assertion (9), (14)
MHz
MHz
MHz
PCS
Minimum is 2 parallel clock cycles
—
Notes to Table 4–6:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
(13)
(14)
(15)
Spread spectrum clocking is allowed only in PCI Express (PIPE) mode if the upstream transmitter and the receiver share the same clock source.
The reference clock DC coupling option is only available in PCI Express (PIPE) mode for the HCSL I/O standard.
The fixedclk is used in PIPE mode receiver detect circuitry.
The device cannot tolerate prolonged operation at this absolute maximum.
The rate matcher supports only up to ± 300 PPM for PIPE mode and ± 100 PPM for GIGE mode.
This parameter is measured by embedding the run length data in a PRBS sequence.
Signal detect threshold detector circuitry is available only in PCI Express (PIPE mode).
Time taken for rx_pll_locked to go high from rx_analogreset deassertion. Refer to Figure 4–1.
For lock times specific to the protocols, refer to protocol characterization documents.
Time for which the CDR needs to stay in LTR mode after rx_pll_locked is asserted and before rx_locktodata is asserted in manual
mode. Refer to Figure 4–1.
Time taken to recover valid data from GXB after the rx_locktodata signal is asserted in manual mode. Measurement results are based on
PRBS31, for native data rates only. Refer to Figure 4–1.
Time taken to recover valid data from GXB after the rx_freqlocked signal goes high in automatic mode. Measurement results are based
on PRBS31, for native data rates only. Refer to Figure 4–2.
This is applicable only to PCI Express (PIPE) ×4 and XAUI ×4 mode.
Time taken to lock TX PLL from gxb_powerdown deassertion.
The 1.2 V RX VICM settings is intended for DC-coupled LVDS links.
Figure 4–1 shows the lock time parameters in manual mode. Figure 4–2 shows the
lock time parameters in automatic mode.
1
LTD = Lock to data
LTR = Lock to reference clock
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Operating Conditions
4–7
Figure 4–1. Lock Time Parameters for Manual Mode
r x_analogreset
CDR status
LTR
LTD
r x_pll_locked
r x_locktodata
Invalid Data
Valid data
r x_dataout
CDR LTR Time
LTD lock time
CDR Minimum T1b
Figure 4–2. Lock Time Parameters for Automatic Mode
CDR status
LTR
LTD
r x_freqlocked
r x_dataout
Invalid
Valid
data
data
Data lock time from rx_freqlocked
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
4–8
Chapter 4: DC and Switching Characteristics
Operating Conditions
Figure 4–3 and Figure 4–4 show differential receiver input and transmitter output
waveforms, respectively.
Figure 4–3. Receiver Input Waveform
Single-Ended Waveform
Positive Channel (p)
VID
Negative Channel (n)
VCM
Ground
Differential Waveform
VID (diff peak-peak) = 2 x VID (single-ended)
VID
p−n=0V
VID
Figure 4–4. Transmitter Output Waveform
Single-Ended Waveform
Positive Channel (p)
VOD
Negative Channel (n)
VCM
Ground
Differential Waveform
VOD (diff peak-peak) = 2 x VOD (single-ended)
VOD
p−n=0V
VOD
Table 4–7 lists the Arria GX transceiver block AC specification.
Table 4–7. Arria GX Transceiver Block AC Specification
(Note 1), (2), (3) (Part 1 of 4)
Description
Condition
–6 Speed Grade
Commercial & Units
Industrial
XAUI Transmit Jitter Generation (4)
REFCLK = 156.25 MHz
Total jitter at 3.125 Gbps
Pattern = CJPAT
VOD = 1200 mV
0.3
UI
No Pre-emphasis
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Operating Conditions
4–9
Table 4–7. Arria GX Transceiver Block AC Specification
(Note 1), (2), (3) (Part 2 of 4)
Description
Condition
–6 Speed Grade
Commercial & Units
Industrial
REFCLK = 156.25 MHz
Deterministic jitter at 3.125 Gbps
Pattern = CJPAT
VOD = 1200 mV
0.17
UI
> 0.65
UI
> 0.37
UI
No Pre-emphasis
XAUI Receiver Jitter Tolerance (4)
Pattern = CJPAT
Total jitter
No Equalization
DC Gain = 3 dB
Pattern = CJPAT
Deterministic jitter
No Equalization
DC Gain = 3 dB
Peak-to-peak jitter
Jitter frequency = 22.1 KHz
> 8.5
UI
Peak-to-peak jitter
Jitter frequency = 1.875 MHz
> 0.1
UI
Peak-to-peak jitter
Jitter frequency = 20 MHz
> 0.1
UI
< 0.25
UI p-p
> 0.6
UI p-p
< 0.279
UI p-p
< 0.14
UI p-p
> 0.66
UI p-p
> 0.4
UI p-p
< 0.35
UI p-p
< 0.17
UI p-p
PCI Express (PIPE) Transmitter Jitter Generation (5)
Total Transmitter Jitter Generation
Compliance Pattern; VOD = 800 mV;
Pre-emphasis = 49%
PCI Express (PIPE) Receiver Jitter Tolerance (5)
Total Receiver Jitter Tolerance
Compliance Pattern;
DC Gain = 3 db
Gigabit Ethernet (GIGE) Transmitter Jitter Generation (7)
Total Transmitter Jitter Generation (TJ)
Deterministic Transmitter Jitter
Generation (DJ)
CRPAT: VOD = 800 mV;
Pre-emphasis = 0%
CRPAT; VOD = 800 mV;
Pre-emphasis = 0%
Gigabit Ethernet (GIGE) Receiver Jitter Tolerance
Total Jitter Tolerance
Deterministic Jitter Tolerance
CJPAT Compliance Pattern;
DC Gain = 0 dB
CJPAT Compliance Pattern;
DC Gain = 0 dB
Serial RapidIO (1.25 Gbps, 2.5 Gbps, and 3.125 Gbps) Transmitter Jitter Generation (6)
CJPAT Compliance Pattern;
Total Transmitter Jitter Generation (TJ)
VOD = 800 mV;
Pre-emphasis = 0%
CJPAT Compliance Pattern;
Deterministic Transmitter Jitter
Generation (DJ)
VOD = 800 mV;
Pre-emphasis = 0%
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
4–10
Chapter 4: DC and Switching Characteristics
Operating Conditions
Table 4–7. Arria GX Transceiver Block AC Specification
(Note 1), (2), (3) (Part 3 of 4)
Description
Condition
–6 Speed Grade
Commercial & Units
Industrial
Serial RapidIO (1.25 Gbps, 2.5 Gbps, and 3.125 Gbps) Receiver Jitter Tolerance (6)
Total Jitter Tolerance
Combined Deterministic and Random
Jitter Tolerance (JDR)
Deterministic Jitter Tolerance (JD)
Sinusoidal Jitter Tolerance
CJPAT Compliance Pattern;
> 0.65
UI p-p
> 0.55
UI p-p
> 0.37
UI p-p
Jitter Frequency = 22.1 KHz
> 8.5
UI p-p
Jitter Frequency = 200 KHz
> 1.0
UI p-p
Jitter Frequency = 1.875 MHz
> 0.1
UI p-p
Jitter Frequency = 20 MHz
> 0.1
UI p-p
Data Rate = 1.485 Gbps (HD)
REFCLK = 74.25 MHz
Pattern = Color Bar
Vod = 800 mV
No Pre-emphasis
Low-Frequency Roll-Off = 100 KHz
0.2
UIv
Data Rate = 2.97 Gbps (3G)
REFCLK = 148.5 MHz
Pattern = Color Bar
Vod = 800 mV
No Pre-emphasis
Low-Frequency Roll-Off = 100 KHz
0.3
UI
DC Gain = 0 dB
CJPAT Compliance Pattern;
DC Gain = 0 dB
CJPAT Compliance Pattern;
DC Gain = 0 dB
SDI Transmitter Jitter Generation (8)
Alignment Jitter (peak-to-peak)
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Operating Conditions
4–11
Table 4–7. Arria GX Transceiver Block AC Specification
Description
(Note 1), (2), (3) (Part 4 of 4)
–6 Speed Grade
Commercial & Units
Industrial
Condition
SDI Receiver Jitter Tolerance (8)
Jitter Frequency = 15 KHz
Data Rate = 2.97 Gbps (3G)
REFCLK = 148.5 MHz
Pattern = Single Line
Scramble Color Bar
No Equalization
DC Gain = 0 dB
Sinusoidal Jitter Tolerance
(peak-to-peak)
Sinusoidal Jitter Tolerance
(peak-to-peak)
>2
UI
Jitter Frequency = 100 KHz
Data Rate = 2.97 Gbps (3G)
REFCLK = 148.5 MHz
Pattern = Single Line Scramble Color Bar
No Equalization
DC Gain = 0 dB
> 0.3
UI
Jitter Frequency = 148.5 MHz
Data Rate = 2.97 Gbps (3G)
REFCLK = 148.5 MHz
Pattern = Single Line
Scramble Color Bar
No Equalization
DC Gain = 0 dB
> 0.3
UI
Jitter Frequency = 20 KHz
Data Rate = 1.485 Gbps (HD)
REFCLK = 74.25 MHz
Pattern = 75% Color Bar
No Equalization
DC Gain = 0 dB
>1
UI
Jitter Frequency = 100 KHz
Data Rate = 1.485 Gbps (HD)
REFCLK = 74.25 MHz
Pattern = 75% Color Bar
No Equalization
DC Gain = 0 dB
> 0.2
UI
Notes to Table 4–7:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Dedicated REFCLK pins were used to drive the input reference clocks.
Jitter numbers specified are valid for the stated conditions only.
Refer to the protocol characterization documents for detailed information.
The jitter numbers for XAUI are compliant to the IEEE802.3ae-2002 Specification.
The jitter numbers for PCI Express are compliant to the PCIe Base Specification 2.0.
The jitter numbers for Serial RapidIO are compliant to the RapidIO Specification 1.3.
The jitter numbers for GIGE are compliant to the IEEE802.3-2002 Specification.
The HD-SDI and 3G-SDI jitter numbers are compliant to the SMPTE292M and SMPTE424M specifications.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
4–12
Chapter 4: DC and Switching Characteristics
Operating Conditions
Table 4–8 and Table 4–9 list the transmitter and receiver PCS latency for each mode,
respectively.
Table 4–8. PCS Latency (Note 1)
Transmitter PCS Latency
Functional Mode
Configuration
TX PIPE
TX Phase
Comp FIFO
Byte
Serializer
TX State
Machine
8B/10B
Encoder
Sum (2)
—
2–3
1
0.5
0.5
4–5
×1, ×4, ×8
8-bit channel width
1
3–4
1
—
1
6–7
×1, ×4, ×8
16-bit channel width
1
3–4
1
—
0.5
6–7
—
2–3
1
—
1
4–5
1.25 Gbps, 2.5 Gbps,
3.125 Gbps
—
2–3
1
—
0.5
4–5
HD10-bit channel width
—
2–3
1
—
1
4–5
XAUI
—
PIPE
GIGE
—
Serial RapidIO
SDI
BASIC Single
Width
HD, 3G 20-bit channel width
—
2–3
1
—
0.5
4–5
8-bit/10-bit channel width
—
2–3
1
—
1
4–5
16-bit/20-bit channel width
—
2–3
1
—
0.5
4–5
Notes to Table 4–8:
(1) The latency numbers are with respect to the PLD-transceiver interface clock cycles.
(2) The total latency number is rounded off in the Sum column.
Table 4–9. PCS Latency (Part 1 of 2) (Part 1 of 2)
8B/10B Decoder
Receiver State Machine
Byte Deserializer
Byte Order
Receiver Phase Comp FIFO
Receiver PIPE
Sum (2)
Serial
RapidIO
Rate Matcher (3)
GIGE
Deskew FIFO
PIPE
Word Aligner
XAUI
2–2.5
2–2.5
5.5–6.5
0.5
1
1
1
1–2
—
14–17
×1, ×4
8-bit channel width
4–5
—
11–13
1
—
1
1
2–3
1
21–25
×1, ×4
16-bit channel width
2–2.5
—
5.5–6.5
0.5
—
1
1
2–3
1
13–16
4–5
—
11–13
1
—
1
1
1–2
—
19–23
2–2.5
—
—
0.5
—
1
1
1–2
—
6–7
5
—
—
1
—
1
1
1–2
—
9–10
2.5
—
—
0.5
—
1
1
1–2
—
6–7
Configuration
Functional Mode
Receiver PCS Latency
—
—
1.25 Gbps, 2.5 Gbps,
3.125 Gbps
HD 10-bit channel width
SDI
HD, 3G 20-bit channel
width
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Operating Conditions
4–13
Table 4–9. PCS Latency (Part 2 of 2) (Part 2 of 2)
Deskew FIFO
Rate Matcher (3)
8B/10B Decoder
Receiver State Machine
Byte Deserializer
Byte Order
Receiver Phase Comp FIFO
Receiver PIPE
Sum (2)
8/10-bit channel width;
with Rate Matcher
4–5
—
11–13
1
—
1
1
1–2
1
19–23
8/10-bit channel width;
without Rate Matcher
4–5
—
—
1
—
1
1
1–2
—
8–10
16/20-bit channel width;
with Rate Matcher
2–2.5
—
5.5–6.5
0.5
—
1
1
1–2
—
11–14
16/20-bit channel width;
without Rate Matcher
2–2.5
—
—
0.5
—
1
1
1–2
—
6–7
BASIC
Single
Width
Configuration
Functional Mode
Word Aligner
Receiver PCS Latency
Notes to Table 4–9:
(1) The latency numbers are with respect to the PLD-transceiver interface clock cycles.
(2) The total latency number is rounded off in the Sum column.
(3) The rate matcher latency shown is the steady state latency. Actual latency may vary depending on the skip ordered set gap allowed by the
protocol, actual PPM difference between the reference clocks, and so forth.
Table 4–10 through Table 4–13 show the typical VOD for data rates from 600 Mbps to
3.125 Gbps. The specification is for measurement at the package ball.
Table 4–10. Typical VOD Setting, TX Term = 100 
Vcc HTX = 1.5 V
VOD Typical (mV)
VOD Setting (mV)
400
600
800
1000
1200
430
625
830
1020
1200
Table 4–11. Typical VOD Setting, TX Term = 100 
Vcc HTX = 1.2 V
VOD Typical (mV)
VOD Setting (mV)
320
480
640
800
960
344
500
664
816
960
Table 4–12. Typical Pre-Emphasis (First Post-Tap), (Note 1)
Vcc HTX = 1.5 V
VOD Setting (mV)
First Post Tap Pre-Emphasis Level
1
2
3
4
5
TX Term = 100 
© December 2009
400
24%
62%
112%
184%
—
600
—
31%
56%
86%
122%
800
—
20%
35%
53%
73%
Altera Corporation
Arria GX Device Handbook, Volume 1
4–14
Chapter 4: DC and Switching Characteristics
Operating Conditions
Table 4–12. Typical Pre-Emphasis (First Post-Tap), (Note 1)
Vcc HTX = 1.5 V
VOD Setting (mV)
First Post Tap Pre-Emphasis Level
1
2
3
4
5
1000
—
—
23%
36%
49%
1200
—
—
17%
25%
35%
Note to Table 4–12:
(1) Applicable to data rates from 600 Mbps to 3.125 Gbps. Specification is for measurement at the package ball.
Table 4–13. Typical Pre-Emphasis (First Post-Tap), (Note 1)
Vcc HTX = 1.2 V
VOD Setting (mV)
First Post Tap Pre-Emphasis Level
1
2
3
4
5
TX Term = 100 
320
24%
61%
114%
—
—
480
—
31%
55%
86%
121%
640
—
20%
35%
54%
72%
800
—
—
23%
36%
49%
960
—
—
18%
25%
35%
Note to Table 4–13:
(1) Applicable to data rates from 600 Mbps to 3.125 Gbps. Specification is for measurement at the package ball.
DC Electrical Characteristics
Table 4–14 lists the Arria GX device family DC electrical characteristics.
Table 4–14. Arria GX Device DC Operating Conditions (Part 1 of 2)
Symbol
Parameter
(Note 1)
Conditions
Device
Min
Typ
Max
Units
II
Input pin leakage current
VI = VCCIOmax to 0 V (2)
All
–10
—
10
A
IOZ
Tri-stated I/O pin leakage
current
VO = VCCIOmax to 0 V (2)
All
–10
—
10
A
—
0.30
(3)
A
ICCINT0
VI = ground, no load, no
toggling inputs
EP1AGX20/35
VCCINT supply current
(standby)
EP1AGX50/60
—
0.50
(3)
A
TJ = 25 °C
EP1AGX90
—
0.62
(3)
A
VI = ground, no load, no
toggling inputs
EP1AGX20/35
—
2.7
(3)
mA
EP1AGX50/60
—
3.6
(3)
mA
TJ = 25 °C,
VCCPD = 3.3V
EP1AGX90
—
4.3
(3)
mA
VI = ground, no load, no
toggling inputs
EP1AGX20/35
—
4.0
(3)
mA
EP1AGX50/60
—
4.0
(3)
mA
TJ = 25 °C
EP1AGX90
—
4.0
(3)
mA
ICCPD0
ICCI00
VCCPD supply current
(standby)
VCCIO supply current
(standby)
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Operating Conditions
4–15
Table 4–14. Arria GX Device DC Operating Conditions (Part 2 of 2)
Symbol
Parameter
Value of I/O pin pull-up
resistor before and during
configuration
RCONF (4)
Conditions
(Note 1)
Device
Min
Typ
Max
Units
Vi = 0, VCCIO = 3.3 V
—
10
25
50
k
Vi = 0, VCCIO = 2.5 V
—
15
35
70
k
Vi = 0, VCCIO = 1.8 V
—
30
50
100
k
Vi = 0, VCCIO = 1.5 V
—
40
75
150
k
Vi = 0, VCCIO = 1.2 V
—
50
90
170
k
—
—
1
2
k
Recommended value of
I/O pin external pull-down
resistor before and during
configuration
—
Notes to Table 4–14:
(1) Typical values are for TA = 25 °C, VCCINT = 1.2 V, and VCCIO = 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V.
(2) This value is specified for normal device operation. The value may vary during power-up. This applies for all VCCIO settings (3.3, 2.5, 1.8, 1.5,
and 1.2 V).
(3) Maximum values depend on the actual TJ and design utilization. For maximum values, refer to the Excel-based PowerPlay Early Power Estimator
(available at PowerPlay Early Power Estimators (EPE) and Power Analyzer) or the Quartus® II PowerPlay Power Analyzer feature for maximum
values. For more information, refer to “Power Consumption” on page 4–25.
(4) Pin pull-up resistance values will be lower if an external source drives the pin higher than VCCIO.
I/O Standard Specifications
Table 4–15 through Table 4–38 show the Arria GX device family I/O standard
specifications.
Table 4–15. LVTTL Specifications
Symbol
Parameter
Conditions
Minimum
Maximum
Units
—
3.135
3.465
V
VCCIO (1)
Output supply voltage
VIH
High-level input voltage
—
1.7
4.0
V
VIL
Low-level input voltage
—
–0.3
0.8
V
VOH
High-level output voltage
IOH = –4 mA (2)
2.4
—
V
VOL
Low-level output voltage
IOL = 4 mA (2)
—
0.45
V
Notes to Table 4–15:
(1) Arria GX devices comply to the narrow range for the supply voltage as specified in the EIA/JEDEC Standard, JESD8-B.
(2) This specification is supported across all the programmable drive strength settings available for this I/O standard.
Table 4–16. LVCMOS Specifications
Symbol
Parameter
Conditions
Minimum
Maximum
Units
VCCIO (1)
Output supply voltage
—
3.135
3.465
V
VIH
High-level input voltage
—
1.7
4.0
V
VIL
Low-level input voltage
—
–0.3
0.8
V
VOH
High-level output voltage
VCCIO = 3.0, IOH = –0.1 mA (2)
VCCIO – 0.2
—
V
VOL
Low-level output voltage
VCCIO = 3.0, IOL = 0.1 mA (2)
—
0.2
V
Notes to Table 4–16:
(1) Arria GX devices comply to the narrow range for the supply voltage as specified in the EIA/JEDEC Standard, JESD8-B.
(2) This specification is supported across all the programmable drive strength available for this I/O standard.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
4–16
Chapter 4: DC and Switching Characteristics
Operating Conditions
Table 4–17. 2.5-V I/O Specifications
Symbol
Parameter
Conditions
Minimum
Maximum
Units
VCCIO (1)
Output supply voltage
—
2.375
2.625
V
VIH
High-level input voltage
—
1.7
4.0
V
VIL
Low-level input voltage
—
–0.3
0.7
V
VOH
High-level output voltage
I OH = –1 mA (2)
2.0
—
V
VOL
Low-level output voltage
I OL = 1 mA (2)
—
0.4
V
Notes to Table 4–17:
(1) The Arria GX device VCCIO voltage level support of 2.5 to 5% is narrower than defined in the normal range of the EIA/JEDEC standard.
(2) This specification is supported across all the programmable drive settings available for this I/O standard.
Table 4–18. 1.8-V I/O Specifications
Symbol
Parameter
Conditions
Minimum
Maximum
Units
VCCIO (1)
Output supply voltage
—
1.71
1.89
V
VIH
High-level input voltage
—
0.65 × VCCIO
2.25
V
VIL
Low-level input voltage
—
–0.3
0.35 × VCCIO
V
VOH
High-level output voltage
I OH = –2 mA (2)
VCCIO – 0.45
—
V
VOL
Low-level output voltage
I OL = 2 mA (2)
—
0.45
V
Notes to Table 4–18:
(1) The Arria GX device VCCIO voltage level support of 1.8 to 5% is narrower than defined in the normal range of the EIA/JEDEC standard.
(2) This specification is supported across all the programmable drive settings available for this I/O standard, as shown in Arria GX Architecture
chapter.
Table 4–19. 1.5-V I/O Specifications
Symbol
Parameter
Conditions
Minimum
Maximum
Units
VCCIO (1)
Output supply voltage
—
1.425
1.575
V
VIH
High-level input voltage
—
0.65 VCCIO
VCCIO + 0.3
V
VIL
Low-level input voltage
—
–0.3
0.35 VCCIO
V
VOH
High-level output voltage
IOH = –2 mA (2)
0.75 VCCIO
—
V
VOL
Low-level output voltage
IOL = 2 mA (2)
—
0.25 VCCIO
V
Notes to Table 4–19:
(1) The Arria GX device VCCIO voltage level support of 1.5 to 5% is narrower than defined in the normal range of the EIA/JEDEC standard.
(2) This specification is supported across all the programmable drive settings available for this I/O standard, as shown in the Arria GX
Architecture chapter.
Figure 4–5 and Figure 4–6 show receiver input and transmitter output waveforms,
respectively, for all differential I/O standards (LVDS and LVPECL).
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Operating Conditions
4–17
Figure 4–5. Receiver Input Waveforms for Differential I/O Standards
Single-Ended Waveform
Positive Channel (p) = VIH
VID
Negative Channel (n) = VIL
VCM
Ground
Differential Waveform
VID
p−n=0V
VID
VID (Peak-to-Peak)
Figure 4–6. Transmitter Output Waveforms for Differential I/O Standards
Single-Ended Waveform
Positive Channel (p) = VOH
VOD
Negative Channel (n) = VOL
VCM
Ground
Differential Waveform
VOD
p−n=0V
VOD
Table 4–20. 2.5-V LVDS I/O Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Units
VCCIO
I/O supply voltage for left and right I/O
banks (1, 2, 5, and 6)
—
2.375
2.5
2.625
V
VID
Input differential voltage swing
(single-ended)
—
100
350
900
mV
VICM
Input common mode voltage
—
200
1,250
1,800
mV
VOD
Output differential voltage (single-ended)
RL = 100 
250
—
450
mV
VOCM
Output common mode voltage
RL = 100 
1.125
—
1.375
V
RL
Receiver differential input discrete
resistor (external to Arria GX devices)
—
90
100
110

© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
4–18
Chapter 4: DC and Switching Characteristics
Operating Conditions
Table 4–21. 3.3-V LVDS I/O Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Units
VCCIO (1)
I/O supply voltage for top and bottom
PLL banks (9, 10, 11, and 12)
—
3.135
3.3
3.465
V
VID
Input differential voltage swing
(single-ended)
—
100
350
900
mV
VICM
Input common mode voltage
—
200
1,250
1,800
mV
VOD
Output differential voltage (single-ended) RL = 100 
250
—
710
mV
VOCM
Output common mode voltage
RL = 100 
840
—
1,570
mV
RL
Receiver differential input discrete
resistor (external to Arria GX devices)
90
100
110

—
Note to Table 4–21:
(1) The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by V CCINT, not VCCIO. The PLL clock output/feedback
differential buffers are powered by VCC_PLL_OUT. For differential clock output/feedback operation, connect VCC_PLL_OUT to 3.3 V.
Table 4–22. 3.3-V PCML Specifications
Symbol
Parameter
Minimum
Typical
Maximum
Units
3.135
3.3
3.465
V
300
—
600
mV
VCCIO
I/O supply voltage
VID
Input differential voltage swing
(single-ended)
VICM
Input common mode voltage
1.5
—
3.465
V
VOD
Output differential voltage (single-ended)
300
370
500
mV
VOD
Change in VO D between high and low
—
—
50
mV
VOCM
Output common mode voltage
2.5
2.85
3.3
V
VOCM
Change in VO C M between high and low
—
—
50
mV
VT
Output termination voltage
—
VC C I O
—
V
R1
Output external pull-up resistors
45
50
55

R2
Output external pull-up resistors
45
50
55

Table 4–23. LVPECL Specifications
Parameter
Conditions
Minimum
Typical
Maximum
Units
Parameter
VCCIO (1)
I/O supply voltage
—
3.135
3.3
3.465
V
VID
Input differential voltage swing
(single-ended)
—
300
600
1,000
mV
VICM
Input common mode voltage
—
1.0
—
2.5
V
VOD
Output differential voltage
(single-ended)
RL = 100 
525
—
970
mV
VOCM
Output common mode voltage
RL = 100 
1,650
—
2,250
mV
RL
Receiver differential input resistor
—
90
100
110

Note to Table 4–23:
(1) The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by VCCINT, not VCCIO . The PLL clock output/feedback
differential buffers are powered by VCC_PLL_OUT. For differential clock output/feedback operation, connect VCC_PLL_OUT to 3.3 V.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Operating Conditions
4–19
Table 4–24. 3.3-V PCI Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Units
VCCIO
Output supply voltage
—
3.0
3.3
3.6
V
VIH
High-level input voltage
—
0.5 VCCIO
—
VCCIO + 0.5
V
VIL
Low-level input voltage
—
–0.3
—
0.3 VCCIO
V
VOH
High-level output voltage
IOUT = –500 A
0.9 VCCIO
—
—
V
VOL
Low-level output voltage
IOUT = 1,500 A
—
—
0.1 VCCIO
V
Table 4–25. PCI-X Mode 1 Specifications
Symbol
Parameter
Conditions
Minimum
Maximum
Units
VCCIO
Output supply voltage
—
3.0
3.6
V
VIH
High-level input voltage
—
0.5 VCCIO
VCCIO + 0.5
V
VIL
Low-level input voltage
—
–0.3
0.35 VCCIO
V
VIPU
Input pull-up voltage
—
0.7 VCCIO
—
V
VOH
High-level output voltage
I OUT = –500 A
0.9 VCCIO
—
V
VOL
Low-level output voltage
I OUT = 1,500 A
—
0.1 VCCIO
V
Table 4–26. SSTL-18 Class I Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Units
VCCIO
Output supply voltage
—
1.71
1.8
1.89
V
VREF
Reference voltage
—
0.855
0.9
0.945
V
VTT
Termination voltage
—
VREF – 0.04
VREF
VREF + 0.04
V
VIH (DC)
High-level DC input voltage
—
VREF + 0.125
—
—
V
VIL (DC)
Low-level DC input voltage
—
—
—
VREF – 0.125
V
VIH (AC)
High-level AC input voltage
—
VREF + 0.25
—
—
V
VIL (AC)
Low-level AC input voltage
—
—
—
VREF – 0.25
V
VOH
High-level output voltage
I OH = –6.7 mA (1)
VTT + 0.475
—
—
V
VOL
Low-level output voltage
I OL = 6.7 mA (1)
—
—
VTT – 0.475
V
Note to Table 4–26:
(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arria GX
Architecture chapter.
Table 4–27. SSTL-18 Class II Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Units
VCCIO
Output supply voltage
—
1.71
1.8
1.89
V
VREF
Reference voltage
—
0.855
0.9
0.945
V
VTT
Termination voltage
—
VREF – 0.04
VREF
VREF + 0.04
V
VIH (DC)
High-level DC input voltage
—
VREF + 0.125
—
—
V
VIL (DC)
Low-level DC input voltage
—
—
—
VREF – 0.125
V
VIH (AC)
High-level AC input voltage
—
VREF + 0.25
—
—
V
VIL (AC)
Low-level AC input voltage
—
—
—
VREF – 0.25
V
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
4–20
Chapter 4: DC and Switching Characteristics
Operating Conditions
Table 4–27. SSTL-18 Class II Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Units
VOH
High-level output voltage
I OH = –13.4 mA (1)
VCCIO – 0.28
—
—
V
VOL
Low-level output voltage
I OL = 13.4 mA (1)
—
—
0.28
V
Note to Table 4–27:
(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arria GX
Architecture chapter.
Table 4–28. SSTL-18 Class I & II Differential Specifications
Symbol
Parameter
Minimum
Typical
Maximum
Units
VCCIO
Output supply voltage
1.71
1.8
1.89
V
VSWING (DC)
DC differential input voltage
0.25
—
—
V
VX (AC)
AC differential input cross point
voltage
(VCCIO/2) – 0.175
—
(VCCIO/2) + 0.175
V
VSWING (AC)
AC differential input voltage
0.5
—
—
V
VISO
Input clock signal offset voltage
—
0.5 VCC IO
—
V
VISO
Input clock signal offset voltage
variation
—
200
—
mV
VOX (AC)
AC differential cross point voltage
(VCCIO/2) – 0.125
—
(VCCIO/2) + 0.125
V
Table 4–29. SSTL-2 Class I Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Units
VCCIO
Output supply voltage
—
2.375
2.5
2.625
V
VTT
Termination voltage
—
VREF – 0.04
VREF
VREF + 0.04
V
VREF
Reference voltage
—
1.188
1.25
1.313
V
VIH (DC)
High-level DC input voltage
—
VREF + 0.18
—
3.0
V
VIL (DC)
Low-level DC input voltage
—
–0.3
—
VREF – 0.18
V
VIH (AC)
High-level AC input voltage
—
VREF + 0.35
—
—
V
VIL (AC)
Low-level AC input voltage
—
—
—
VREF – 0.35
V
VOH
High-level output voltage
IOH = –8.1 mA
(1)
VTT + 0.57
—
VOL
Low-level output voltage
IOL = 8.1 mA (1)
—
—
V
VTT – 0.57
V
Note to Table 4–29:
(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arria GX Architecture
chapter.
Table 4–30. SSTL-2 Class II Specifications (Part 1 of 2)
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Units
VCC IO
Output supply voltage
—
2.375
2.5
2.625
V
VTT
Termination voltage
—
VREF – 0.04
VREF
VREF + 0.04
V
VREF
Reference voltage
—
1.188
1.25
1.313
V
VIH (DC)
High-level DC input
voltage
—
VREF + 0.18
—
VCCIO + 0.3
V
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Operating Conditions
4–21
Table 4–30. SSTL-2 Class II Specifications (Part 2 of 2)
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Units
VIL (DC)
Low-level DC input
voltage
—
–0.3
—
VREF – 0.18
V
VIH (AC)
High-level AC input
voltage
—
VREF + 0.35
—
—
V
VIL (AC)
Low-level AC input
voltage
—
—
—
VREF – 0.35
V
VOH
High-level output voltage
IOH = –16.4 mA (1)
VTT + 0.76
—
—
V
VOL
Low-level output voltage
I OL = 16.4 mA (1)
—
—
VTT – 0.76
V
Note to Table 4–30:
(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arria GX Architecture
chapter.
Table 4–31. SSTL-2 Class I & II Differential Specifications
Symbol
(Note 1)
Parameter
Minimum
Typical
Maximum
Units
VCCIO
Output supply voltage
2.375
2.5
2.625
V
VSWING (DC)
DC differential input voltage
0.36
—
—
V
VX (AC)
AC differential input cross point voltage
(VCCIO/2) – 0.2
—
(VCCIO /2) + 0.2
V
VSWING (AC)
AC differential input voltage
0.7
—
—
V
VISO
Input clock signal offset voltage
—
0.5 VCCIO
—
V
VISO
Input clock signal offset voltage
variation
—
200
—
mV
VOX (AC)
AC differential output cross point
voltage
(VCCIO/2) – 0.2
—
(VCCIO /2) + 0.2
V
Note to Table 4–31:
(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arria GX Architecture
chapter.
Table 4–32. 1.2-V HSTL Specifications
Symbol
Parameter
Minimum
Typical
Maximum
Units
1.14
1.2
1.26
V
VCCIO
Output supply voltage
VREF
Reference voltage
0.48 VCCIO
0.5 VCCIO
0.52 VCCIO
V
VIH (DC)
High-level DC input voltage
VREF + 0.08
—
VCCIO + 0.15
V
VIL (DC)
Low-level DC input voltage
–0.15
—
VREF – 0.08
V
VIH (AC)
High-level AC input voltage
VREF + 0.15
—
VCCIO + 0.24
V
VIL (AC)
Low-level AC input voltage
–0.24
—
VREF – 0.15
V
VOH
High-level output voltage
VREF + 0.15
—
VCCIO + 0.15
V
VOL
Low-level output voltage
–0.15
—
VREF – 0.15
V
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
4–22
Chapter 4: DC and Switching Characteristics
Operating Conditions
Table 4–33. 1.5-V HSTL Class I Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Units
VCCIO
Output supply voltage
—
1.425
1.5
1.575
V
VREF
Input reference voltage
—
0.713
0.75
0.788
V
VTT
Termination voltage
—
0.713
0.75
0.788
V
VIH (DC)
DC high-level input voltage
—
VREF + 0.1
—
—
V
VIL (DC)
DC low-level input voltage
—
–0.3
—
VREF – 0.1
V
VIH (AC)
AC high-level input voltage
—
VREF + 0.2
—
—
V
VIL (AC)
AC low-level input voltage
—
—
—
VREF – 0.2
V
VOH
High-level output voltage
IOH = 8 mA (1)
VCCIO – 0.4
—
—
V
VOL
Low-level output voltage
IOH = –8 mA (1)
—
—
0.4
V
Note to Table 4–33:
(1) This specification is supported across all the programmable drive settings available for this I/O standard as shown in the Arria GX Architecture
chapter.
Table 4–34. 1.5-V HSTL Class II Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Units
VCCIO
Output supply voltage
—
1.425
1.50
1.575
V
VREF
Input reference voltage
—
0.713
0.75
0.788
V
VTT
Termination voltage
—
0.713
0.75
0.788
V
VIH (DC)
DC high-level input voltage
—
VREF + 0.1
—
—
V
VIL (DC)
DC low-level input voltage
—
–0.3
—
VREF – 0.1
V
VIH (AC)
AC high-level input voltage
—
VREF + 0.2
—
—
V
VIL (AC)
AC low-level input voltage
—
—
—
VREF – 0.2
V
VOH
High-level output voltage
IOH = 16 mA (1)
VCCIO – 0.4
—
—
V
VOL
Low-level output voltage
I OH = –16 mA (1)
—
—
0.4
V
Note to Table 4–34:
(1) This specification is supported across all the programmable drive settings available for this I/O standard, as shown in the Arria GX Architecture
chapter.
Table 4–35. 1.5-V HSTL Class I & II Differential Specifications
Symbol
Parameter
Minimum
Typical
Maximum
Units
1.425
1.5
1.575
V
VCCIO
I/O supply voltage
VDIF (DC)
DC input differential voltage
0.2
—
—
V
VCM (DC)
DC common mode input voltage
0.68
—
0.9
V
VDIF (AC)
AC differential input voltage
0.4
—
—
V
VOX (AC)
AC differential cross point
voltage
0.68
—
0.9
V
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Operating Conditions
4–23
Table 4–36. 1.8-V HSTL Class I Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Units
VCCIO
Output supply voltage
—
1.71
1.80
1.89
V
VREF
Input reference voltage
—
0.85
0.90
0.95
V
VTT
Termination voltage
—
0.85
0.90
0.95
V
VIH (DC)
DC high-level input voltage
—
VREF + 0.1
—
—
V
VIL (DC)
DC low-level input voltage
—
–0.3
—
VREF – 0.1
V
VIH (AC)
AC high-level input voltage
—
VREF + 0.2
—
—
V
VIL (AC)
AC low-level input voltage
—
—
—
VREF – 0.2
V
VOH
High-level output voltage
IOH = 8 mA (1)
VCCIO – 0.4
—
—
V
VOL
Low-level output voltage
IOH = –8 mA (1)
—
—
0.4
V
Note to Table 4–36:
(1) This specification is supported across all the programmable drive settings available for this I/O standard, as shown in the Arria GX Architecture
chapter.
Table 4–37. 1.8-V HSTL Class II Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum
Units
VCCIO
Output supply voltage
—
1.71
1.80
1.89
V
VREF
Input reference voltage
—
0.85
0.90
0.95
V
VTT
Termination voltage
—
0.85
0.90
0.95
V
VIH (DC)
DC high-level input voltage
—
VREF + 0.1
—
—
V
VIL (DC)
DC low-level input voltage
—
–0.3
—
VREF – 0.1
V
VIH (AC)
AC high-level input voltage
—
VREF + 0.2
—
—
V
VIL (AC)
AC low-level input voltage
—
—
—
VREF – 0.2
V
VOH
High-level output voltage
I OH = 16 mA (1)
VCCIO – 0.4
—
—
V
VOL
Low-level output voltage
IOH = –16 mA (1)
—
—
0.4
V
Note to Table 4–37:
(1) This specification is supported across all the programmable drive settings available for this I/O standard, as shown in the Arria GX Architecture
chapter in volume 1 of the Arria GX Device Handbook.
Table 4–38. 1.8-V HSTL Class I & II Differential Specifications
Symbol
Parameter
Minimum
Typical
Maximum
Units
VCCIO
I/O supply voltage
1.71
1.80
1.89
V
VDIF (DC)
DC input differential voltage
0.2
—
—
V
VCM (DC)
DC common mode input voltage
0.78
—
1.12
V
VDIF (AC)
AC differential input voltage
0.4
—
—
V
VOX (AC)
AC differential cross point voltage
0.68
—
0.9
V
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
4–24
Chapter 4: DC and Switching Characteristics
Operating Conditions
Bus Hold Specifications
Table 4–39 shows the Arria GX device family bus hold specifications.
Table 4–39. Bus Hold Parameters
VC CIO Level
Parameter
1.2 V
Conditions
1.5 V
1.8 V
2.5 V
3.3 V
Units
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Low
sustaining
current
VIN > VIL
(maximum)
22.5
—
25
—
30
—
50
—
70
—
A
High
sustaining
current
VIN < VIH
(minimum)
–22.5
—
–25
—
–30
—
–50
—
–70
—
A
Low overdrive
current
0V
<VIN < VCCIO
—
120
—
160
—
200
—
300
—
500
A
High
overdrive
current
0V<
VIN < VCCIO
—
–120
—
–160
—
–200
—
–300
—
–500
A
—
0.45
0.95
0.5
1.0
0.68
1.07
0.7
1.7
0.8
2.0
V
Bus-hold trip
point
On-Chip Termination Specifications
Table 4–40 and Table 4–41 define the specification for internal termination resistance
tolerance when using series or differential on-chip termination.
Table 4–40. Series On-Chip Termination Specification for Top and Bottom I/O Banks
Resistance Tolerance
Symbol
Description
Conditions
Commercial
Max
Industrial
Max
Units
25- RS 3.3/2.5
Internal series termination without
calibration (25- setting
VCCIO = 3.3/2.5V
±30
±30
%
50- RS 3.3/2.5
Internal series termination without
calibration (50- setting
VCCIO = 3.3/2.5V
±30
± 30
%
25- RS 1.8
Internal series termination without
calibration (25- setting
VCCIO = 1.8V
±30
±30
%
50- RS 1.8
Internal series termination without
calibration (50- setting
VCCIO = 1.8V
±30
±30
%
50- RS 1.5
Internal series termination without
calibration (50- setting
VCCIO = 1.5V
±36
±36
%
50- RS 1.2
Internal series termination without
calibration (50- setting
VCCIO = 1.2V
±50
±50
%
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Power Consumption
4–25
Table 4–41. Series On-Chip Termination Specification for Left I/O Banks
Resistance Tolerance
Symbol
Description
Conditions
Commercial
Max
Industrial
Max
Units
25- RS 3.3/2.5
Internal series termination without
calibration (25- setting
VCCIO = 3.3/2.5V
±30
±30
%
50- RS
3.3/2.5/1.8
Internal series termination without
calibration (50- setting
VCCIO = 3.3/2.5/1.8V
±30
±30
%
50- RS 1.5
Internal series termination without
calibration (50- setting
VCCIO = 1.5V
±36
±36
%
RD
Internal differential termination for
LVDS (100- setting)
VCCIO = 2.5V
±20
±25
%
Pin Capacitance
Table 4–42 shows the Arria GX device family pin capacitance.
Table 4–42. Arria GX Device Capacitance
Symbol
(Note 1)
Parameter
Typical
Units
CIOTB
Input capacitance on I/O pins in I/O banks 3, 4, 7, and 8.
5.0
pF
CIOL
Input capacitance on I/O pins in I/O banks 1 and 2, including high-speed differential
receiver and transmitter pins.
6.1
pF
CCLKTB
Input capacitance on top/bottom clock input pins: CLK[4..7] and CLK[12..15] .
6.0
pF
CCLKL
Input capacitance on left clock inputs: CLK0 and CLK2.
6.1
pF
CCLKL+
Input capacitance on left clock inputs: CLK1 and CLK3.
3.3
pF
COUTFB
Input capacitance on dual-purpose clock output/feedback pins in PLL banks 11 and 12.
6.7
pF
Note to Table 4–42:
(1) Capacitance is sample-tested only. Capacitance is measured using time-domain reflections (TDR). Measurement accuracy is within ±0.5 pF.
Power Consumption
Altera offers two ways to calculate power for a design: the Excel-based PowerPlay
early power estimator power calculator and the Quartus II PowerPlay power analyzer
feature.
The interactive Excel-based PowerPlay Early Power Estimator is typically used prior
to designing the FPGA in order to get an estimate of device power. The Quartus II
PowerPlay Power Analyzer provides better quality estimates based on the specifics of
the design after place-and-route is complete. The power analyzer can apply a
combination of user-entered, simulation-derived and estimated signal activities
which, combined with detailed circuit models, can yield very accurate power
estimates.
In both cases, these calculations should only be used as an estimation of power, not as
a specification.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
4–26
Chapter 4: DC and Switching Characteristics
I/O Timing Model
f
For more information about PowerPlay tools, refer to the PowerPlay Early Power
Estimator and PowerPlay Power Analyzer page and the PowerPlay Power Analysis chapter
in volume 3 of the Quartus II Handbook.
For typical ICC standby specifications, refer to Table 4–14 on page 4–14 .
I/O Timing Model
The DirectDrive technology and MultiTrack interconnect ensures predictable
performance, accurate simulation, and accurate timing analysis across all Arria GX
device densities and speed grades. This section describes and specifies the
performance of I/Os.
All specifications are representative of worst-case supply voltage and junction
temperature conditions.
1
The timing numbers listed in the tables of this section are extracted from the
Quartus II software version 7.1.
Preliminary, Correlated, and Final Timing
Timing models can have either preliminary, correlated, or final status. The Quartus II
software issues an informational message during design compilation if the timing
models are preliminary. Table 4–43 lists the status of the Arria GX device timing
models.
■
Preliminary status means the timing model is subject to change. Initially, timing
numbers are created using simulation results, process data, and other known
parameters. These tests are used to make the preliminary numbers as close to the
actual timing parameters as possible.
■
Correlated numbers are based on actual device operation and testing. These
numbers reflect the actual performance of the device under worst-case voltage and
junction temperature conditions.
■
Final timing numbers are based on complete correlation to actual devices and
addressing any minor deviations from the correlated timing model. When the
timing models are final, all or most of the Arria GX family devices have been
completely characterized and no further changes to the timing model are
expected.
Table 4–43. Arria GX Device Timing Model Status
Device
Preliminary
Correlated
Final
EP1AGX20
—
—
v
EP1AGX35
—
—
v
EP1AGX50
—
—
v
EP1AGX60
—
—
v
EP1AGX90
—
—
v
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
I/O Timing Model
4–27
I/O Timing Measurement Methodology
Different I/O standards require different baseline loading techniques for reporting
timing delays. Altera characterizes timing delays with the required termination for
each I/O standard and with 0 pF (except for PCI and PCI-X which use 10 pF) loading
and the timing is specified up to the output pin of the FPGA device. The Quartus II
software calculates the I/O timing for each I/O standard with a default baseline
loading as specified by the I/O standards.
The following measurements are made during device characterization. Altera
measures clock-to-output delays (tCO) at worst-case process, minimum voltage, and
maximum temperature (PVT) for default loading conditions shown in Table 4–44.
Use the following equations to calculate clock pin to output pin timing for Arria GX
devices:
Equation 4–1.
tCO from clock pin to I/O pin = delay from clock pad to I/O output
register + IOE output register clock-to-output delay + delay
from output register to output pin + I/O output delay
txz/tzx from clock pin to I/O pin = delay from clock pad to I/O
output register + IOE output register clock-to-output delay +
delay from output register to output pin + I/O output delay +
output enable pin delay
Simulation using IBIS models is required to determine the delays on the PCB traces in
addition to the output pin delay timing reported by the Quartus II software and the
timing model in the device handbook.
1. Simulate the output driver of choice into the generalized test setup, using values
from Table 4–44.
2. Record the time to V MEAS.
3. Simulate the output driver of choice into the actual PCB trace and load, using the
appropriate IBIS model or capacitance value to represent the load.
4. Record the time to V MEAS.
5. Compare the results of steps 2 and 4. The increase or decrease in delay should be
added to or subtracted from the I/O Standard Output Adder delays to yield the
actual worst-case propagation delay (clock-to-output) of the PCB trace.
The Quartus II software reports the timing with the conditions shown in Table 4–44
using the above equation. Figure 4–7 shows the model of the circuit that is
represented by the output timing of the Quartus II software.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
4–28
Chapter 4: DC and Switching Characteristics
I/O Timing Model
Figure 4–7. Output Delay Timing Reporting Setup Modeled by Quartus II
VTT
VCCIO
Outputp
RT
Output
Buffer
RS
Output
VMEAS
Outputn
CL
GND
RD
GND
Notes to Figure 4–7:
(1) Output pin timing is reported at the output pin of the FPGA device. Additional delays for loading and board trace delay
need to be accounted for with IBIS model simulations.
(2) VCCPD is 3.085 V unless otherwise specified.
(3) VCCINT is 1.12 V unless otherwise specified.
Table 4–44. Output Timing Measurement Methodology for Output Pins (Note 1), (2), (3)
Measurement
Point
Loading and Termination
I/O Standard
RS ()
RD ( )
RT ( )
VCCIO
(V)
VTT (V)
CL (pF)
VMEAS (V)
LVTTL (4)
—
—
—
3.135
—
0
1.5675
LVCMOS (4)
—
—
—
3.135
—
0
1.5675
2.5 V (4)
—
—
—
2.375
—
0
1.1875
1.8 V (4)
—
—
—
1.710
—
0
0.855
1.5 V (4)
—
—
—
1.425
—
0
0.7125
PCI (5)
—
—
—
2.970
—
10
1.485
PCI-X (5)
—
—
—
2.970
—
10
1.485
SSTL-2 Class I
25
—
50
2.325
1.123
0
1.1625
SSTL-2 Class II
25
—
25
2.325
1.123
0
1.1625
SSTL-18 Class I
25
—
50
1.660
0.790
0
0.83
SSTL-18 Class II
25
—
25
1.660
0.790
0
0.83
1.8-V HSTL Class I
—
—
50
1.660
0.790
0
0.83
1.8-V HSTL Class II
—
—
25
1.660
0.790
0
0.83
1.5-V HSTL Class I
—
—
50
1.375
0.648
0
0.6875
1.5-V HSTL Class II
—
—
25
1.375
0.648
0
0.6875
1.2-V HSTL with OCT
—
—
—
1.140
—
0
0.570
Differential SSTL-2 Class I
25
—
50
2.325
1.123
0
1.1625
Differential SSTL-2 Class II
25
—
25
2.325
1.123
0
1.1625
Differential SSTL-18 Class I
50
—
50
1.660
0.790
0
0.83
Differential SSTL-18 Class II
25
—
25
1.660
0.790
0
0.83
1.5-V differential HSTL Class I
—
—
50
1.375
0.648
0
0.6875
1.5-V differential HSTL Class II
—
—
25
1.375
0.648
0
0.6875
1.8-V differential HSTL Class I
—
—
50
1.660
0.790
0
0.83
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
I/O Timing Model
4–29
Table 4–44. Output Timing Measurement Methodology for Output Pins (Note 1), (2), (3)
Measurement
Point
Loading and Termination
I/O Standard
RS ()
RD ( )
RT ( )
VCCIO
(V)
VTT (V)
CL (pF)
VMEAS (V)
1.8-V differential HSTL Class II
—
—
25
1.660
0.790
0
0.83
LVDS
—
100
—
2.325
—
0
1.1625
LVPECL
—
100
—
3.135
—
0
1.5675
Notes to Table 4–44:
(1)
(2)
(3)
(4)
(5)
Input measurement point at internal node is 0.5 VCCINT.
Output measuring point for VMEAS at buffer output is 0.5 VCCIO.
Input stimulus edge rate is 0 to VCC in 0.2 ns (internal signal) from the driver preceding the I/O buffer.
Less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V with less than 30-mV ripple.
VCCPD = 2.97 V, less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V.
Figure 4–8 and Figure 4–9 show the measurement setup for output disable and output
enable timing.
Figure 4–8. Measurement Setup for txz
(Note 1)
tXZ, Driving High to Tristate
Enable
OE
OE
½ VCCINT
Dout
Din
100 Ω
Disable
“1”
Din
100 mv
Dout
thz
GND
tXZ, Driving Low to Tristate
Enable
OE
100 Ω
Disable
½ VCCINT
OE
Dout
Din
Din
Dout
“0”
tlz
VCCIO
100 mv
Note to Figure 4–8:
(1) VCCINT is 1.12 V for this measurement.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
4–30
Chapter 4: DC and Switching Characteristics
I/O Timing Model
Figure 4–9. Measurement Setup for tzx
tZX, Tristate to Driving High
Disable
OE
Enable
½ VCCINT
OE
Dout
Din
“1”
Din
1 MΩ
tzh
Dout
½ VCCIO
tZX, Tristate to Driving Low
Disable
Enable
½ VCCINT
OE
1 MΩ
OE
Dout
Din
“0”
Din
½ VCCIO
tzl
Dout
Table 4–45 specifies the input timing measurement setup.
Table 4–45. Timing Measurement Methodology for Input Pins
(Note 1), (2), (3), (4) (Part 1 of 2)
Measurement Conditions
Measurement Point
VCCIO (V)
VREF (V)
Edge Rate (ns)
VMEAS (V)
LVTTL (5)
3.135
—
3.135
1.5675
LVCMOS (5)
3.135
—
3.135
1.5675
2.5 V (5)
2.375
—
2.375
1.1875
1.8 V (5)
1.710
—
1.710
0.855
1.5 V (5)
1.425
—
1.425
0.7125
PCI (6)
2.970
—
2.970
1.485
PCI-X (6)
2.970
—
2.970
1.485
SSTL-2 Class I
2.325
1.163
2.325
1.1625
SSTL-2 Class II
2.325
1.163
2.325
1.1625
SSTL-18 Class I
1.660
0.830
1.660
0.83
I/O Standard
SSTL-18 Class II
1.660
0.830
1.660
0.83
1.8-V HSTL Class I
1.660
0.830
1.660
0.83
1.8-V HSTL Class II
1.660
0.830
1.660
0.83
1.5-V HSTL Class I
1.375
0.688
1.375
0.6875
1.5-V HSTL Class II
1.375
0.688
1.375
0.6875
1.2-V HSTL with OCT
1.140
0.570
1.140
0.570
Differential SSTL-2 Class I
2.325
1.163
2.325
1.1625
Differential SSTL-2 Class II
2.325
1.163
2.325
1.1625
Differential SSTL-18 Class I
1.660
0.830
1.660
0.83
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
I/O Timing Model
4–31
Table 4–45. Timing Measurement Methodology for Input Pins
(Note 1), (2), (3), (4) (Part 2 of 2)
Measurement Conditions
Measurement Point
VCCIO (V)
VREF (V)
Edge Rate (ns)
VMEAS (V)
Differential SSTL-18 Class II
1.660
0.830
1.660
0.83
1.5-V differential HSTL Class I
1.375
0.688
1.375
0.6875
I/O Standard
1.5-V differential HSTL Class II
1.375
0.688
1.375
0.6875
1.8-V differential HSTL Class I
1.660
0.830
1.660
0.83
1.8-V differential HSTL Class II
1.660
0.830
1.660
0.83
LVDS
2.325
—
0.100
1.1625
LVPECL
3.135
—
0.100
1.5675
Notes to Table 4–45:
(1)
(2)
(3)
(4)
(5)
(6)
Input buffer sees no load at buffer input.
Input measuring point at buffer input is 0.5 VCCIO.
Output measuring point is 0.5 VCC at internal node.
Input edge rate is 1 V/ns.
Less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V with less than 30-mV ripple.
VCCPD = 2.97 V, less than 50-mV ripple on VCCIO and VCCPD, VCCINT = 1.15 V.
Clock Network Skew Adders
The Quartus II software models skew within dedicated clock networks such as global
and regional clocks. Therefore, the intra-clock network skew adder is not specified.
Table 4–46 specifies the intra clock skew between any two clock networks driving any
registers in the Arria GX device.
Table 4–46. Clock Network Specifications
Name
Description
Min
Typ
Max
Units
Clock skew adder
EP1AGX20/35 (1)
Inter-clock network, same side
—
—
± 50
ps
Inter-clock network, entire chip
—
—
± 100
ps
Clock skew adder
EP1AGX50/60 (1)
Inter-clock network, same side
—
—
± 50
ps
Inter-clock network, entire chip
—
—
± 100
ps
Clock skew adder
EP1AGX90 (1)
Inter-clock network, same side
—
—
± 55
ps
Inter-clock network, entire chip
—
—
± 110
ps
Note to Table 4–46:
(1) This is in addition to intra-clock network skew, which is modeled in the Quartus II software.
Default Capacitive Loading of Different I/O Standards
See Table 4–47 for default capacitive loading of different I/O standards.
Table 4–47. Default Loading of Different I/O Standards for Arria GX Devices (Part 1 of 2)
I/O Standard
© December 2009
Capacitive Load
Units
LVTTL
0
pF
LVCMOS
0
pF
2.5 V
0
pF
Altera Corporation
Arria GX Device Handbook, Volume 1
4–32
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–47. Default Loading of Different I/O Standards for Arria GX Devices (Part 2 of 2)
I/O Standard
Capacitive Load
Units
1.8 V
0
pF
1.5 V
0
pF
PCI
10
pF
PCI-X
10
pF
SSTL-2 Class I
0
pF
SSTL-2 Class II
0
pF
SSTL-18 Class I
0
pF
SSTL-18 Class II
0
pF
1.5-V HSTL Class I
0
pF
1.5-V HSTL Class II
0
pF
1.8-V HSTL Class I
0
pF
1.8-V HSTL Class II
0
pF
Differential SSTL-2 Class I
0
pF
Differential SSTL-2 Class II
0
pF
Differential SSTL-18 Class I
0
pF
Differential SSTL-18 Class II
0
pF
1.5-V differential HSTL Class I
0
pF
1.5-V differential HSTL Class II
0
pF
1.8-V differential HSTL Class I
0
pF
1.8-V differential HSTL Class II
0
pF
LVDS
0
pF
Typical Design Performance
The following section describes the typical design performance for the Arria GX
device family.
User I/O Pin Timing
Table 4–48 through Table 4–77 show user I/O pin timing for Arria GX devices. I/O
buffer tSU , tH , and tCO are reported for the cases when I/O clock is driven by a
non-PLL global clock (GCLK) and a PLL driven global clock (GCLK-PLL). For tSU, tH,
and tCO using regional clock, add the value from the adder tables listed for each device
to the GCLK/GCLK-PLL values for the device.
EP1AGX20 I/O Timing Parameters
Table 4–48 through Table 4–51 show the maximum I/O timing parameters for
EP1AGX20 devices for I/O standards which support general purpose I/O pins.
Table 4–48 describes the row pin delay adders when using the regional clock in
Arria GX devices.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–33
Table 4–48. EP1AGX20 Row Pin Delay Adders for Regional Clock
Fast Corner
Industrial
Commercial
–6 Speed
Grade
0.117
0.117
0.273
ns
RCLK PLL
input adder
0.011
0.011
0.019
ns
RCLK output
–0.117
–0.117
–0.273
ns
–0.011
–0.011
–0.019
ns
Parameter
RCLK input
Units
adder
adder
RCLK PLL
output adder
Table 4–49 describes I/O timing specifications.
Table 4–49. EP1AGX20 Column Pins Input Timing Parameters (Part 1 of 3)
I/O Standard
Fast Corner
Industrial
Commercial
–6 Speed
Grade
tSU
1.251
1.251
2.915
ns
tH
–1.146
–1.146
–2.638
ns
GCLK PLL
tSU
2.693
2.693
6.021
ns
tH
–2.588
–2.588
–5.744
ns
GCLK
tSU
1.251
1.251
2.915
ns
tH
–1.146
–1.146
–2.638
ns
tSU
2.693
2.693
6.021
ns
tH
–2.588
–2.588
–5.744
ns
tSU
1.261
1.261
2.897
ns
tH
–1.156
–1.156
–2.620
ns
GCLK PLL
tSU
2.703
2.703
6.003
ns
tH
–2.598
–2.598
–5.726
ns
GCLK
tSU
1.327
1.327
3.107
ns
tH
–1.222
–1.222
–2.830
ns
tSU
2.769
2.769
6.213
ns
tH
–2.664
–2.664
–5.936
ns
tSU
1.330
1.330
3.200
ns
tH
–1.225
–1.225
–2.923
ns
GCLK PLL
tSU
2.772
2.772
6.306
ns
tH
–2.667
–2.667
–6.029
ns
GCLK
tSU
1.075
1.075
2.372
ns
tH
–0.970
–0.970
–2.095
ns
tSU
2.517
2.517
5.480
ns
tH
–2.412
–2.412
–5.203
ns
Clock
GCLK
3.3-V LVTTL
3.3-V LVCMOS
GCLK PLL
GCLK
2.5 V
1.8 V
GCLK PLL
GCLK
1.5 V
SSTL-2 CLASS I
GCLK PLL
© December 2009
Altera Corporation
Parameter
Units
Arria GX Device Handbook, Volume 1
4–34
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–49. EP1AGX20 Column Pins Input Timing Parameters (Part 2 of 3)
I/O Standard
Fast Corner
Clock
GCLK
SSTL-2 CLASS II
GCLK PLL
GCLK
SSTL-18 CLASS I
GCLK PLL
GCLK
SSTL-18 CLASS II
GCLK PLL
GCLK
1.8-V HSTL CLASS I
GCLK PLL
GCLK
1.8-V HSTL CLASS II
GCLK PLL
GCLK
1.5-V HSTL CLASS I
GCLK PLL
GCLK
1.5-V HSTL CLASS II
GCLK PLL
GCLK
3.3-V PCI
GCLK PLL
GCLK
3.3-V PCI-X
GCLK PLL
Arria GX Device Handbook, Volume 1
Industrial
Commercial
–6 Speed
Grade
tSU
1.075
1.075
2.372
ns
tH
–0.970
–0.970
–2.095
ns
Parameter
Units
tSU
2.517
2.517
5.480
ns
tH
–2.412
–2.412
–5.203
ns
tSU
1.113
1.113
2.479
ns
tH
–1.008
–1.008
–2.202
ns
tSU
2.555
2.555
5.585
ns
tH
–2.450
–2.450
–5.308
ns
tSU
1.114
1.114
2.479
ns
tH
–1.009
–1.009
–2.202
ns
tSU
2.556
2.556
5.587
ns
tH
–2.451
–2.451
–5.310
ns
tSU
1.113
1.113
2.479
ns
tH
–1.008
–1.008
–2.202
ns
tSU
2.555
2.555
5.585
ns
tH
–2.450
–2.450
–5.308
ns
tSU
1.114
1.114
2.479
ns
tH
–1.009
–1.009
–2.202
ns
tSU
2.556
2.556
5.587
ns
tH
–2.451
–2.451
–5.310
ns
tSU
1.131
1.131
2.607
ns
tH
–1.026
–1.026
–2.330
ns
tSU
2.573
2.573
5.713
ns
tH
–2.468
–2.468
–5.436
ns
tSU
1.132
1.132
2.607
ns
tH
–1.027
–1.027
–2.330
ns
tSU
2.574
2.574
5.715
ns
tH
–2.469
–2.469
–5.438
ns
tSU
1.256
1.256
2.903
ns
tH
–1.151
–1.151
–2.626
ns
tSU
2.698
2.698
6.009
ns
tH
–2.593
–2.593
–5.732
ns
tSU
1.256
1.256
2.903
ns
tH
–1.151
–1.151
–2.626
ns
tSU
2.698
2.698
6.009
ns
tH
–2.593
–2.593
–5.732
ns
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–35
Table 4–49. EP1AGX20 Column Pins Input Timing Parameters (Part 3 of 3)
Fast Corner
I/O Standard
Clock
Industrial
Commercial
–6 Speed
Grade
tSU
1.106
1.106
2.489
ns
tH
–1.001
–1.001
–2.212
ns
Parameter
GCLK
LVDS
GCLK PLL
Units
tSU
2.530
2.530
5.564
ns
tH
–2.425
–2.425
–5.287
ns
Units
Table 4–50 describes I/O timing specifications.
Table 4–50. EP1AGX20 Row Pins output Timing Parameters (Part 1 of 2)
I/O Standard
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
Clock
4 mA
GCLK
3.3-V
LVCMOS
8 mA
2.5 V
4 mA
1.8 V
1.8 V
1.8 V
1.8 V
1.5 V
1.5 V
© December 2009
Commercial
tCO
2.904
2.904
6.699
ns
GCLK PLL
tCO
1.485
1.485
3.627
ns
GCLK
tCO
2.776
2.776
6.059
ns
GCLK PLL
tCO
1.357
1.357
2.987
ns
Parameter
GCLK
tCO
2.720
2.720
6.022
ns
GCLK PLL
tCO
1.301
1.301
2.950
ns
GCLK
tCO
2.776
2.776
6.059
ns
GCLK PLL
tCO
1.357
1.357
2.987
ns
GCLK
tCO
2.670
2.670
5.753
ns
GCLK PLL
tCO
1.251
1.251
2.681
ns
GCLK
tCO
2.759
2.759
6.033
ns
GCLK PLL
tCO
1.340
1.340
2.961
ns
12 mA
4 mA
2.5 V
Industrial
–6 Speed
Grade
8 mA
3.3-V
LVCMOS
2.5 V
Fast Model
Drive
Strength
GCLK
tCO
2.656
2.656
5.775
ns
GCLK PLL
tCO
1.237
1.237
2.703
ns
GCLK
tCO
2.637
2.637
5.661
ns
GCLK PLL
tCO
1.218
1.218
2.589
ns
GCLK
tCO
2.829
2.829
7.052
ns
GCLK PLL
tCO
1.410
1.410
3.980
ns
GCLK
tCO
2.818
2.818
6.273
ns
GCLK PLL
tCO
1.399
1.399
3.201
ns
8 mA
12 mA
2 mA
4 mA
GCLK
tCO
2.707
2.707
5.972
ns
GCLK PLL
tCO
1.288
1.288
2.900
ns
GCLK
tCO
2.676
2.676
5.858
ns
GCLK PLL
tCO
1.257
1.257
2.786
ns
GCLK
tCO
2.789
2.789
6.551
ns
GCLK PLL
tCO
1.370
1.370
3.479
ns
GCLK
tCO
2.682
2.682
5.950
ns
GCLK PLL
tCO
1.263
1.263
2.878
ns
6 mA
8 mA
2 mA
4 mA
Altera Corporation
Arria GX Device Handbook, Volume 1
4–36
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–50. EP1AGX20 Row Pins output Timing Parameters (Part 2 of 2)
Fast Model
Drive
Strength
Clock
SSTL-2
CLASS I
8 mA
GCLK
SSTL-2
CLASS I
12 mA
SSTL-2
CLASS II
16 mA
SSTL-18
CLASS I
4 mA
SSTL-18
CLASS I
6 mA
SSTL-18
CLASS I
8 mA
SSTL-18
CLASS I
10 mA
1.8-V HSTL
CLASS I
4 mA
1.8-V HSTL
CLASS I
6 mA
1.8-V HSTL
CLASS I
8 mA
1.8-V HSTL
CLASS I
10 mA
1.8-V HSTL
CLASS I
12 mA
1.5-V HSTL
CLASS I
4 mA
1.5-V HSTL
CLASS I
6 mA
1.5-V HSTL
CLASS I
8 mA
I/O Standard
LVDS
—
Arria GX Device Handbook, Volume 1
Industrial
Commercial
–6 Speed
Grade
tCO
2.626
2.626
5.614
ns
GCLK PLL
tCO
1.207
1.207
2.542
ns
Parameter
Units
GCLK
tCO
2.602
2.602
5.538
ns
GCLK PLL
tCO
1.183
1.183
2.466
ns
GCLK
tCO
2.568
2.568
5.407
ns
GCLK PLL
tCO
1.149
1.149
2.335
ns
GCLK
tCO
2.614
2.614
5.556
ns
GCLK PLL
tCO
1.195
1.195
2.484
ns
GCLK
tCO
2.618
2.618
5.485
ns
GCLK PLL
tCO
1.199
1.199
2.413
ns
GCLK
tCO
2.594
2.594
5.468
ns
GCLK PLL
tCO
1.175
1.175
2.396
ns
GCLK
tCO
2.597
2.597
5.447
ns
GCLK PLL
tCO
1.178
1.178
2.375
ns
GCLK
tCO
2.595
2.595
5.466
ns
GCLK PLL
tCO
1.176
1.176
2.394
ns
GCLK
tCO
2.598
2.598
5.430
ns
GCLK PLL
tCO
1.179
1.179
2.358
ns
GCLK
tCO
2.580
2.580
5.426
ns
GCLK PLL
tCO
1.161
1.161
2.354
ns
GCLK
tCO
2.584
2.584
5.415
ns
GCLK PLL
tCO
1.165
1.165
2.343
ns
GCLK
tCO
2.575
2.575
5.414
ns
GCLK PLL
tCO
1.156
1.156
2.342
ns
GCLK
tCO
2.594
2.594
5.443
ns
GCLK PLL
tCO
1.175
1.175
2.371
ns
GCLK
tCO
2.597
2.597
5.429
ns
GCLK PLL
tCO
1.178
1.178
2.357
ns
GCLK
tCO
2.582
2.582
5.421
ns
GCLK PLL
tCO
1.163
1.163
2.349
ns
GCLK
tCO
2.654
2.654
5.613
ns
GCLK PLL
tCO
1.226
1.226
2.530
ns
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–37
Table 4–51 describes I/O timing specifications.
Table 4–51. EP1AGX20 Column Pins Output Timing Parameters (Part 1 of 4)
I/O Standard
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V
LVCMOS
16 mA
3.3-V
LVCMOS
20 mA
3.3-V
LVCMOS
24 mA
2.5 V
4 mA
1.8 V
1.8 V
© December 2009
6.541
ns
GCLK PLL
tCO
1.467
1.467
3.435
ns
GCLK
tCO
2.764
2.764
6.169
ns
GCLK PLL
tCO
1.322
1.322
3.063
ns
GCLK
tCO
2.697
2.697
6.169
ns
GCLK PLL
tCO
1.255
1.255
3.063
ns
GCLK
tCO
2.671
2.671
6.000
ns
GCLK PLL
tCO
1.229
1.229
2.894
ns
GCLK
tCO
2.649
2.649
5.875
ns
GCLK PLL
tCO
1.207
1.207
2.769
ns
GCLK
tCO
2.642
2.642
5.877
ns
GCLK PLL
tCO
1.200
1.200
2.771
ns
GCLK
tCO
2.764
2.764
6.169
ns
GCLK PLL
tCO
1.322
1.322
3.063
ns
GCLK
tCO
2.672
2.672
5.874
ns
GCLK PLL
tCO
1.230
1.230
2.768
ns
GCLK
tCO
2.644
2.644
5.796
ns
GCLK PLL
tCO
1.202
1.202
2.690
ns
GCLK
tCO
2.651
2.651
5.764
ns
GCLK PLL
tCO
1.209
1.209
2.658
ns
GCLK
tCO
2.638
2.638
5.746
ns
GCLK PLL
tCO
1.196
1.196
2.640
ns
GCLK
tCO
2.627
2.627
5.724
ns
GCLK PLL
tCO
1.185
1.185
2.618
ns
GCLK
tCO
2.726
2.726
6.201
ns
GCLK PLL
tCO
1.284
1.284
3.095
ns
GCLK
tCO
2.674
2.674
5.939
ns
GCLK PLL
tCO
1.232
1.232
2.833
ns
GCLK
tCO
2.653
2.653
5.822
ns
GCLK PLL
tCO
1.211
1.211
2.716
ns
GCLK
tCO
2.635
2.635
5.748
ns
GCLK PLL
tCO
1.193
1.193
2.642
ns
GCLK
tCO
2.766
2.766
7.193
ns
GCLK PLL
tCO
1.324
1.324
4.087
ns
GCLK
tCO
2.771
2.771
6.419
ns
GCLK PLL
tCO
1.329
1.329
3.313
ns
24 mA
12 mA
2.5 V
2.909
20 mA
3.3-V
LVCMOS
Units
2.909
16 mA
8 mA
Commercial
tCO
12 mA
3.3-V
LVCMOS
Industrial
–6 Speed
Grade
Parameter
GCLK
8 mA
4 mA
2.5 V
Clock
4 mA
3.3-V
LVCMOS
2.5 V
Fast Corner
Drive
Strength
8 mA
12 mA
16 mA
2 mA
4 mA
Altera Corporation
Arria GX Device Handbook, Volume 1
4–38
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–51. EP1AGX20 Column Pins Output Timing Parameters (Part 2 of 4)
I/O Standard
1.8 V
1.8 V
1.8 V
1.8 V
1.5 V
1.5 V
1.5 V
1.5 V
SSTL-2
CLASS I
Drive
Strength
6 mA
8 mA
10 mA
12 mA
2 mA
4 mA
6 mA
8 mA
8 mA
SSTL-2
CLASS I
12 mA
SSTL-2
CLASS II
16 mA
SSTL-2
CLASS II
20 mA
SSTL-2
CLASS II
24 mA
SSTL-18
CLASS I
4 mA
SSTL-18
CLASS I
6 mA
SSTL-18
CLASS I
8 mA
SSTL-18
CLASS I
10 mA
SSTL-18
CLASS I
12 mA
SSTL-18
CLASS II
8 mA
Arria GX Device Handbook, Volume 1
Fast Corner
Clock
Industrial
Commercial
–6 Speed
Grade
Parameter
Units
GCLK
tCO
2.695
2.695
6.155
ns
GCLK PLL
tCO
1.253
1.253
3.049
ns
GCLK
tCO
2.697
2.697
6.064
ns
GCLK PLL
tCO
1.255
1.255
2.958
ns
GCLK
tCO
2.651
2.651
5.987
ns
GCLK PLL
tCO
1.209
1.209
2.881
ns
GCLK
tCO
2.652
2.652
5.930
ns
GCLK PLL
tCO
1.210
1.210
2.824
ns
GCLK
tCO
2.746
2.746
6.723
ns
GCLK PLL
tCO
1.304
1.304
3.617
ns
GCLK
tCO
2.682
2.682
6.154
ns
GCLK PLL
tCO
1.240
1.240
3.048
ns
GCLK
tCO
2.685
2.685
6.036
ns
GCLK PLL
tCO
1.243
1.243
2.930
ns
GCLK
tCO
2.644
2.644
5.983
ns
GCLK PLL
tCO
1.202
1.202
2.877
ns
GCLK
tCO
2.629
2.629
5.762
ns
GCLK PLL
tCO
1.184
1.184
2.650
ns
GCLK
tCO
2.612
2.612
5.712
ns
GCLK PLL
tCO
1.167
1.167
2.600
ns
GCLK
tCO
2.590
2.590
5.639
ns
GCLK PLL
tCO
1.145
1.145
2.527
ns
GCLK
tCO
2.591
2.591
5.626
ns
GCLK PLL
tCO
1.146
1.146
2.514
ns
GCLK
tCO
2.587
2.587
5.624
ns
GCLK PLL
tCO
1.142
1.142
2.512
ns
GCLK
tCO
2.626
2.626
5.733
ns
GCLK PLL
tCO
1.184
1.184
2.627
ns
GCLK
tCO
2.630
2.630
5.694
ns
GCLK PLL
tCO
1.185
1.185
2.582
ns
GCLK
tCO
2.609
2.609
5.675
ns
GCLK PLL
tCO
1.164
1.164
2.563
ns
GCLK
tCO
2.614
2.614
5.673
ns
GCLK PLL
tCO
1.169
1.169
2.561
ns
GCLK
tCO
2.608
2.608
5.659
ns
GCLK PLL
tCO
1.163
1.163
2.547
ns
GCLK
tCO
2.597
2.597
5.625
ns
GCLK PLL
tCO
1.152
1.152
2.513
ns
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–39
Table 4–51. EP1AGX20 Column Pins Output Timing Parameters (Part 3 of 4)
I/O Standard
SSTL-18
CLASS II
Clock
18 mA
SSTL-18
CLASS II
20 mA
1.8-V HSTL
CLASS I
4 mA
1.8-V HSTL
CLASS I
6 mA
1.8-V HSTL
CLASS I
8 mA
1.8-V HSTL
CLASS I
10 mA
1.8-V HSTL
CLASS I
12 mA
1.8-V HSTL
CLASS II
16 mA
1.8-V HSTL
CLASS II
18 mA
1.8-V HSTL
CLASS II
20 mA
1.5-V HSTL
CLASS I
4 mA
1.5-V HSTL
CLASS I
6 mA
1.5-V HSTL
CLASS I
8 mA
1.5-V HSTL
CLASS I
10 mA
1.5-V HSTL
CLASS I
12 mA
1.5-V HSTL
CLASS II
16 mA
1.5-V HSTL
CLASS II
18 mA
1.5-V HSTL
CLASS II
20 mA
Industrial
Commercial
–6 Speed
Grade
Parameter
Units
GCLK
tCO
2.609
2.609
5.603
ns
GCLK PLL
tCO
1.164
1.164
2.491
ns
GCLK
tCO
2.605
2.605
5.611
ns
GCLK PLL
tCO
1.160
1.160
2.499
ns
GCLK
tCO
2.605
2.605
5.609
ns
GCLK PLL
tCO
1.160
1.160
2.497
ns
GCLK
tCO
2.629
2.629
5.664
ns
GCLK PLL
tCO
1.187
1.187
2.558
ns
GCLK
tCO
2.634
2.634
5.649
ns
GCLK PLL
tCO
1.189
1.189
2.537
ns
GCLK
tCO
2.612
2.612
5.638
ns
GCLK PLL
tCO
1.167
1.167
2.526
ns
GCLK
tCO
2.616
2.616
5.644
ns
GCLK PLL
tCO
1.171
1.171
2.532
ns
GCLK
tCO
2.608
2.608
5.637
ns
GCLK PLL
tCO
1.163
1.163
2.525
ns
GCLK
tCO
2.591
2.591
5.401
ns
GCLK PLL
tCO
1.146
1.146
2.289
ns
GCLK
tCO
2.593
2.593
5.412
ns
GCLK PLL
tCO
1.148
1.148
2.300
ns
GCLK
tCO
2.593
2.593
5.421
ns
GCLK PLL
tCO
1.148
1.148
2.309
ns
GCLK
tCO
2.629
2.629
5.663
ns
GCLK PLL
tCO
1.187
1.187
2.557
ns
GCLK
tCO
2.633
2.633
5.641
ns
GCLK PLL
tCO
1.188
1.188
2.529
ns
GCLK
tCO
2.615
2.615
5.643
ns
GCLK PLL
tCO
1.170
1.170
2.531
ns
GCLK
tCO
2.615
2.615
5.645
ns
GCLK PLL
tCO
1.170
1.170
2.533
ns
GCLK
tCO
2.609
2.609
5.643
ns
GCLK PLL
tCO
1.164
1.164
2.531
ns
GCLK
tCO
2.596
2.596
5.455
ns
GCLK PLL
tCO
1.151
1.151
2.343
ns
GCLK
tCO
2.599
2.599
5.465
ns
GCLK PLL
tCO
1.154
1.154
2.353
ns
GCLK
tCO
2.601
2.601
5.478
ns
GCLK PLL
tCO
1.156
1.156
2.366
ns
16 mA
SSTL-18
CLASS II
© December 2009
Fast Corner
Drive
Strength
Altera Corporation
Arria GX Device Handbook, Volume 1
4–40
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–51. EP1AGX20 Column Pins Output Timing Parameters (Part 4 of 4)
I/O Standard
3.3-V PCI
3.3-V PCI-X
LVDS
Fast Corner
Drive
Strength
Clock
—
GCLK
—
—
Industrial
Commercial
–6 Speed
Grade
tCO
2.755
2.755
5.791
ns
GCLK PLL
tCO
1.313
1.313
2.685
ns
Parameter
Units
GCLK
tCO
2.755
2.755
5.791
ns
GCLK PLL
tCO
1.313
1.313
2.685
ns
GCLK
tCO
3.621
3.621
6.969
ns
GCLK PLL
tCO
2.190
2.190
3.880
ns
Table 4–52 through Table 4–53 list EP1AGX20 regional clock (RCLK) adder values that
should be added to GCLK values. These adder values are used to determine I/O
timing when the I/O pin is driven using the regional clock. This applies for all I/O
standards supported by Arria GX with general purpose I/O pins.
Table 4–52 describes row pin delay adders when using the regional clock in Arria GX
devices.
Table 4–52. EP1AGX20 Row Pin Delay Adders for Regional Clock
Fast Corner
Parameter
–6 Speed Grade
Units
0.117
0.273
ns
0.011
0.011
0.019
ns
RCLK output adder
–0.117
–0.117
–0.273
ns
RCLK PLL output adder
–0.011
–0.011
–0.019
ns
Industrial
Commercial
RCLK input adder
0.117
RCLK PLL input adder
Table 4–53 lists column pin delay adders when using the regional clock in Arria GX
devices.
Table 4–53. EP1AGX20 Column Pin Delay Adders for Regional Clock
Fast Corner
Parameter
–6 Speed Grade
Units
0.081
0.223
ns
–0.012
–0.012
–0.008
ns
–0.081
–0.081
–0.224
ns
1.11
1.11
2.658
ns
Industrial
Commercial
RCLK input adder
0.081
RCLK PLL input
adder
RCLK output
adder
RCLK PLL output
adder
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–41
EP1AGX35 I/O Timing Parameters
Table 4–54 through Table 4–57 list the maximum I/O timing parameters for
EP1AGX35 devices for I/O standards which support general purpose I/O pins.
Table 4–54 lists I/O timing specifications.
Table 4–54. EP1AGX35 Row Pins Input Timing Parameters (Part 1 of 2)
Fast Model
I/O Standard
Clock
GCLK
3.3-V LVTTL
GCLK PLL
GCLK
3.3-V LVCMOS
GCLK PLL
GCLK
2.5 V
GCLK PLL
GCLK
1.8 V
GCLK PLL
GCLK
1.5 V
GCLK PLL
GCLK
SSTL-2 CLASS I
GCLK PLL
GCLK
SSTL-2 CLASS II
GCLK PLL
GCLK
SSTL-18 CLASS I
GCLK PLL
© December 2009
Altera Corporation
Industrial
Commercial
–6 Speed
Grade
t SU
1.561
1.561
3.556
ns
tH
–1.456
–1.456
–3.279
ns
t SU
2.980
2.980
6.628
ns
Parameter
Units
tH
–2.875
–2.875
–6.351
ns
t SU
1.561
1.561
3.556
ns
tH
–1.456
–1.456
–3.279
ns
t SU
2.980
2.980
6.628
ns
tH
–2.875
–2.875
–6.351
ns
t SU
1.573
1.573
3.537
ns
tH
–1.468
–1.468
–3.260
ns
t SU
2.992
2.992
6.609
ns
tH
–2.887
–2.887
–6.332
ns
t SU
1.639
1.639
3.744
ns
tH
–1.534
–1.534
–3.467
ns
t SU
3.058
3.058
6.816
ns
tH
–2.953
–2.953
–6.539
ns
t SU
1.642
1.642
3.839
ns
tH
–1.537
–1.537
–3.562
ns
t SU
3.061
3.061
6.911
ns
tH
–2.956
–2.956
–6.634
ns
t SU
1.385
1.385
3.009
ns
tH
–1.280
–1.280
–2.732
ns
t SU
2.804
2.804
6.081
ns
tH
–2.699
–2.699
–5.804
ns
t SU
1.385
1.385
3.009
ns
tH
–1.280
–1.280
–2.732
ns
t SU
2.804
2.804
6.081
ns
tH
–2.699
–2.699
–5.804
ns
t SU
1.417
1.417
3.118
ns
tH
–1.312
–1.312
–2.841
ns
t SU
2.836
2.836
6.190
ns
tH
–2.731
–2.731
–5.913
ns
Arria GX Device Handbook, Volume 1
4–42
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–54. EP1AGX35 Row Pins Input Timing Parameters (Part 2 of 2)
Fast Model
I/O Standard
Clock
GCLK
SSTL-18 CLASS II
GCLK PLL
GCLK
1.8-V HSTL CLASS I
GCLK PLL
GCLK
1.8-V HSTL CLASS II
GCLK PLL
GCLK
1.5-V HSTL CLASS I
GCLK PLL
GCLK
1.5-V HSTL CLASS II
GCLK PLL
GCLK
LVDS
GCLK PLL
Industrial
Commercial
–6 Speed
Grade
t SU
1.417
1.417
3.118
ns
tH
–1.312
–1.312
–2.841
ns
Parameter
Units
t SU
2.836
2.836
6.190
ns
tH
–2.731
–2.731
–5.913
ns
t SU
1.417
1.417
3.118
ns
tH
–1.312
–1.312
–2.841
ns
t SU
2.836
2.836
6.190
ns
tH
–2.731
–2.731
–5.913
ns
t SU
1.417
1.417
3.118
ns
tH
–1.312
–1.312
–2.841
ns
t SU
2.836
2.836
6.190
ns
tH
–2.731
–2.731
–5.913
ns
t SU
1.443
1.443
3.246
ns
tH
–1.338
–1.338
–2.969
ns
t SU
2.862
2.862
6.318
ns
tH
–2.757
–2.757
–6.041
ns
t SU
1.443
1.443
3.246
ns
tH
–1.338
–1.338
–2.969
ns
t SU
2.862
2.862
6.318
ns
tH
–2.757
–2.757
–6.041
ns
t SU
1.341
1.341
3.088
ns
tH
–1.236
–1.236
–2.811
ns
t SU
2.769
2.769
6.171
ns
tH
–2.664
–2.664
–5.894
ns
–6 Speed
Grade
Units
Table 4–55 lists I/O timing specifications.
Table 4–55. EP1AGX35 Column Pins Input Timing Parameters (Part 1 of 3)
Fast Corner
I/O Standard
Clock
Parameter
Industrial
GCLK
3.3-V LVTTL
GCLK PLL
GCLK
3.3-V LVCMOS
GCLK PLL
Arria GX Device Handbook, Volume 1
Commercial
tSU
1.251
1.251
2.915
ns
tH
–1.146
–1.146
–2.638
ns
tSU
2.693
2.693
6.021
ns
tH
–2.588
–2.588
–5.744
ns
tSU
1.251
1.251
2.915
ns
tH
–1.146
–1.146
–2.638
ns
tSU
2.693
2.693
6.021
ns
tH
–2.588
–2.588
–5.744
ns
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–43
Table 4–55. EP1AGX35 Column Pins Input Timing Parameters (Part 2 of 3)
Fast Corner
I/O Standard
Clock
GCLK
2.5 V
GCLK PLL
GCLK
1.8 V
GCLK PLL
GCLK
1.5 V
GCLK PLL
GCLK
SSTL-2 CLASS I
GCLK PLL
GCLK
SSTL-2 CLASS II
GCLK PLL
GCLK
SSTL-18 CLASS I
GCLK PLL
GCLK
SSTL-18 CLASS II
GCLK PLL
GCLK
1.8-V HSTL CLASS I
GCLK PLL
GCLK
1.8-V HSTL CLASS II
GCLK PLL
© December 2009
Altera Corporation
Industrial
Commercial
–6 Speed
Grade
tSU
1.261
1.261
2.897
ns
tH
–1.156
–1.156
–2.620
ns
Parameter
Units
tSU
2.703
2.703
6.003
ns
tH
–2.598
–2.598
–5.726
ns
tSU
1.327
1.327
3.107
ns
tH
–1.222
–1.222
–2.830
ns
tSU
2.769
2.769
6.213
ns
tH
–2.664
–2.664
–5.936
ns
tSU
1.330
1.330
3.200
ns
tH
–1.225
–1.225
–2.923
ns
tSU
2.772
2.772
6.306
ns
tH
–2.667
–2.667
–6.029
ns
tSU
1.075
1.075
2.372
ns
tH
–0.970
–0.970
–2.095
ns
tSU
2.517
2.517
5.480
ns
tH
–2.412
–2.412
–5.203
ns
tSU
1.075
1.075
2.372
ns
tH
–0.970
–0.970
–2.095
ns
tSU
2.517
2.517
5.480
ns
tH
–2.412
–2.412
–5.203
ns
tSU
1.113
1.113
2.479
ns
tH
–1.008
–1.008
–2.202
ns
tSU
2.555
2.555
5.585
ns
tH
–2.450
–2.450
–5.308
ns
tSU
1.114
1.114
2.479
ns
tH
–1.009
–1.009
–2.202
ns
tSU
2.556
2.556
5.587
ns
tH
–2.451
–2.451
–5.310
ns
tSU
1.113
1.113
2.479
ns
tH
–1.008
–1.008
–2.202
ns
tSU
2.555
2.555
5.585
ns
tH
–2.450
–2.450
–5.308
ns
tSU
1.114
1.114
2.479
ns
tH
–1.009
–1.009
–2.202
ns
tSU
2.556
2.556
5.587
ns
tH
–2.451
–2.451
–5.310
ns
Arria GX Device Handbook, Volume 1
4–44
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–55. EP1AGX35 Column Pins Input Timing Parameters (Part 3 of 3)
Fast Corner
I/O Standard
Clock
Industrial
Commercial
–6 Speed
Grade
tSU
1.131
1.131
2.607
ns
tH
–1.026
–1.026
–2.330
ns
Parameter
GCLK
1.5-V HSTL CLASS I
GCLK PLL
GCLK
1.5-V HSTL CLASS II
GCLK PLL
GCLK
3.3-V PCI
GCLK PLL
GCLK
3.3-V PCI-X
GCLK PLL
GCLK
LVDS
GCLK PLL
Units
tSU
2.573
2.573
5.713
ns
tH
–2.468
–2.468
–5.436
ns
tSU
1.132
1.132
2.607
ns
tH
–1.027
–1.027
–2.330
ns
tSU
2.574
2.574
5.715
ns
tH
–2.469
–2.469
–5.438
ns
tSU
1.256
1.256
2.903
ns
tH
–1.151
–1.151
–2.626
ns
tSU
2.698
2.698
6.009
ns
tH
–2.593
–2.593
–5.732
ns
tSU
1.256
1.256
2.903
ns
tH
–1.151
–1.151
–2.626
ns
tSU
2.698
2.698
6.009
ns
tH
–2.593
–2.593
–5.732
ns
tSU
1.106
1.106
2.489
ns
tH
–1.001
–1.001
–2.212
ns
tSU
2.530
2.530
5.564
ns
tH
–2.425
–2.425
–5.287
ns
Table 4–56 lists I/O timing specifications.
Table 4–56. EP1AGX35 Row Pins Output Timing Parameters (Part 1 of 3)
I/O Standard
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
Fast Model
Drive
Strength
Clock
4 mA
GCLK
8 mA
12 mA
3.3-V
LVCMOS
4 mA
3.3-V
LVCMOS
8 mA
2.5 V
4 mA
Arria GX Device Handbook, Volume 1
Industrial
Commercial
–6 Speed
Grade
tCO
2.904
2.904
6.699
ns
GCLK PLL
tCO
1.485
1.485
3.627
ns
GCLK
tCO
2.776
2.776
6.059
ns
GCLK PLL
tCO
1.357
1.357
2.987
ns
Parameter
Units
GCLK
tCO
2.720
2.720
6.022
ns
GCLK PLL
tCO
1.301
1.301
2.950
ns
GCLK
tCO
2.776
2.776
6.059
ns
GCLK PLL
tCO
1.357
1.357
2.987
ns
GCLK
tCO
2.670
2.670
5.753
ns
GCLK PLL
tCO
1.251
1.251
2.681
ns
GCLK
tCO
2.759
2.759
6.033
ns
GCLK PLL
tCO
1.340
1.340
2.961
ns
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–45
Table 4–56. EP1AGX35 Row Pins Output Timing Parameters (Part 2 of 3)
I/O Standard
2.5 V
2.5 V
1.8 V
1.8 V
1.8 V
1.8 V
1.5 V
1.5 V
SSTL-2
CLASS I
Clock
2.656
5.775
ns
GCLK PLL
tCO
1.237
1.237
2.703
ns
GCLK
tCO
2.637
2.637
5.661
ns
GCLK PLL
tCO
1.218
1.218
2.589
ns
GCLK
tCO
2.829
2.829
7.052
ns
GCLK PLL
tCO
1.410
1.410
3.980
ns
GCLK
tCO
2.818
2.818
6.273
ns
GCLK PLL
tCO
1.399
1.399
3.201
ns
GCLK
tCO
2.707
2.707
5.972
ns
GCLK PLL
tCO
1.288
1.288
2.900
ns
4 mA
6 mA
GCLK
tCO
2.676
2.676
5.858
ns
GCLK PLL
tCO
1.257
1.257
2.786
ns
GCLK
tCO
2.789
2.789
6.551
ns
GCLK PLL
tCO
1.370
1.370
3.479
ns
GCLK
tCO
2.682
2.682
5.950
ns
GCLK PLL
tCO
1.263
1.263
2.878
ns
GCLK
tCO
2.626
2.626
5.614
ns
GCLK PLL
tCO
1.207
1.207
2.542
ns
GCLK
tCO
2.602
2.602
5.538
ns
GCLK PLL
tCO
1.183
1.183
2.466
ns
GCLK
tCO
2.568
2.568
5.407
ns
GCLK PLL
tCO
1.149
1.149
2.335
ns
GCLK
tCO
2.614
2.614
5.556
ns
GCLK PLL
tCO
1.195
1.195
2.484
ns
GCLK
tCO
2.618
2.618
5.485
ns
GCLK PLL
tCO
1.199
1.199
2.413
ns
GCLK
tCO
2.594
2.594
5.468
ns
GCLK PLL
tCO
1.175
1.175
2.396
ns
GCLK
tCO
2.597
2.597
5.447
ns
GCLK PLL
tCO
1.178
1.178
2.375
ns
GCLK
tCO
2.595
2.595
5.466
ns
GCLK PLL
tCO
1.176
1.176
2.394
ns
GCLK
tCO
2.598
2.598
5.430
ns
GCLK PLL
tCO
1.179
1.179
2.358
ns
GCLK
tCO
2.580
2.580
5.426
ns
GCLK PLL
tCO
1.161
1.161
2.354
ns
GCLK
tCO
2.584
2.584
5.415
ns
GCLK PLL
tCO
1.165
1.165
2.343
ns
8 mA
2 mA
4 mA
8 mA
16 mA
SSTL-18
CLASS I
4 mA
SSTL-18
CLASS I
6 mA
SSTL-18
CLASS I
8 mA
SSTL-18
CLASS I
10 mA
1.8-V HSTL
CLASS I
4 mA
1.8-V HSTL
CLASS I
6 mA
1.8-V HSTL
CLASS I
8 mA
1.8-V HSTL
CLASS I
10 mA
Units
2.656
2 mA
SSTL-2
CLASS II
Commercial
tCO
12 mA
12 mA
Industrial
–6 Speed
Grade
Parameter
GCLK
8 mA
SSTL-2
CLASS I
© December 2009
Fast Model
Drive
Strength
Altera Corporation
Arria GX Device Handbook, Volume 1
4–46
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–56. EP1AGX35 Row Pins Output Timing Parameters (Part 3 of 3)
I/O Standard
1.8-V HSTL
CLASS I
Drive
Strength
12 mA
1.5-V HSTL
CLASS I
4 mA
1.5-V HSTL
CLASS I
6 mA
1.5-V HSTL
CLASS I
8 mA
LVDS
—
Fast Model
Clock
Industrial
Commercial
–6 Speed
Grade
Parameter
Units
GCLK
tCO
2.575
2.575
5.414
ns
GCLK PLL
tCO
1.156
1.156
2.342
ns
GCLK
tCO
2.594
2.594
5.443
ns
GCLK PLL
tCO
1.175
1.175
2.371
ns
GCLK
tCO
2.597
2.597
5.429
ns
GCLK PLL
tCO
1.178
1.178
2.357
ns
GCLK
tCO
2.582
2.582
5.421
ns
GCLK PLL
tCO
1.163
1.163
2.349
ns
GCLK
tCO
2.654
2.654
5.613
ns
GCLK PLL
tCO
1.226
1.226
2.530
ns
Units
Table 4–57 lists I/O timing specifications.
Table 4–57. EP1AGX35 Column Pins Output Timing Parameters (Part 1 of 4)
I/O Standard
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
Fast Corner
Drive
Strength
Clock
4 mA
GCLK
8 mA
12 mA
16 mA
20 mA
24 mA
3.3-V
LVCMOS
4 mA
3.3-V
LVCMOS
8 mA
3.3-V
LVCMOS
12 mA
3.3-V
LVCMOS
16 mA
3.3-V
LVCMOS
20 mA
Arria GX Device Handbook, Volume 1
Industrial
Commercial
–6 Speed
Grade
tCO
2.909
2.909
6.541
ns
GCLK PLL
tCO
1.467
1.467
3.435
ns
GCLK
tCO
2.764
2.764
6.169
ns
GCLK PLL
tCO
1.322
1.322
3.063
ns
GCLK
tCO
2.697
2.697
6.169
ns
GCLK PLL
tCO
1.255
1.255
3.063
ns
Parameter
GCLK
tCO
2.671
2.671
6.000
ns
GCLK PLL
tCO
1.229
1.229
2.894
ns
GCLK
tCO
2.649
2.649
5.875
ns
GCLK PLL
tCO
1.207
1.207
2.769
ns
GCLK
tCO
2.642
2.642
5.877
ns
GCLK PLL
tCO
1.200
1.200
2.771
ns
GCLK
tCO
2.764
2.764
6.169
ns
GCLK PLL
tCO
1.322
1.322
3.063
ns
GCLK
tCO
2.672
2.672
5.874
ns
GCLK PLL
tCO
1.230
1.230
2.768
ns
GCLK
tCO
2.644
2.644
5.796
ns
GCLK PLL
tCO
1.202
1.202
2.690
ns
GCLK
tCO
2.651
2.651
5.764
ns
GCLK PLL
tCO
1.209
1.209
2.658
ns
GCLK
tCO
2.638
2.638
5.746
ns
GCLK PLL
tCO
1.196
1.196
2.640
ns
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–47
Table 4–57. EP1AGX35 Column Pins Output Timing Parameters (Part 2 of 4)
Fast Corner
Drive
Strength
Clock
3.3-V
LVCMOS
24 mA
GCLK
2.5 V
4 mA
I/O Standard
2.5 V
2.5 V
2.5 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.5 V
1.5 V
1.5 V
1.5 V
Commercial
tCO
2.627
2.627
5.724
ns
GCLK PLL
tCO
1.185
1.185
2.618
ns
GCLK
tCO
2.726
2.726
6.201
ns
tCO
1.284
1.284
3.095
ns
GCLK
tCO
2.674
2.674
5.939
ns
GCLK PLL
tCO
1.232
1.232
2.833
ns
GCLK
tCO
2.653
2.653
5.822
ns
GCLK PLL
tCO
1.211
1.211
2.716
ns
GCLK
tCO
2.635
2.635
5.748
ns
GCLK PLL
tCO
1.193
1.193
2.642
ns
12 mA
16 mA
GCLK
tCO
2.766
2.766
7.193
ns
GCLK PLL
tCO
1.324
1.324
4.087
ns
GCLK
tCO
2.771
2.771
6.419
ns
GCLK PLL
tCO
1.329
1.329
3.313
ns
GCLK
tCO
2.695
2.695
6.155
ns
GCLK PLL
tCO
1.253
1.253
3.049
ns
GCLK
tCO
2.697
2.697
6.064
ns
GCLK PLL
tCO
1.255
1.255
2.958
ns
2 mA
4 mA
6 mA
8 mA
GCLK
tCO
2.651
2.651
5.987
ns
GCLK PLL
tCO
1.209
1.209
2.881
ns
GCLK
tCO
2.652
2.652
5.930
ns
GCLK PLL
tCO
1.210
1.210
2.824
ns
GCLK
tCO
2.746
2.746
6.723
ns
GCLK PLL
tCO
1.304
1.304
3.617
ns
GCLK
tCO
2.682
2.682
6.154
ns
GCLK PLL
tCO
1.240
1.240
3.048
ns
10 mA
12 mA
2 mA
4 mA
GCLK
tCO
2.685
2.685
6.036
ns
GCLK PLL
tCO
1.243
1.243
2.930
ns
GCLK
tCO
2.644
2.644
5.983
ns
GCLK PLL
tCO
1.202
1.202
2.877
ns
GCLK
tCO
2.629
2.629
5.762
ns
GCLK PLL
tCO
1.184
1.184
2.650
ns
GCLK
tCO
2.612
2.612
5.712
ns
GCLK PLL
tCO
1.167
1.167
2.600
ns
6 mA
8 mA
8 mA
SSTL-2
CLASS I
12 mA
SSTL-2
CLASS II
16 mA
SSTL-2
CLASS II
20 mA
Units
GCLK PLL
8 mA
SSTL-2
CLASS I
© December 2009
Industrial
–6 Speed
Grade
Parameter
GCLK
tCO
2.590
2.590
5.639
ns
GCLK PLL
tCO
1.145
1.145
2.527
ns
GCLK
tCO
2.591
2.591
5.626
ns
GCLK PLL
tCO
1.146
1.146
2.514
ns
Altera Corporation
Arria GX Device Handbook, Volume 1
4–48
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–57. EP1AGX35 Column Pins Output Timing Parameters (Part 3 of 4)
Fast Corner
Drive
Strength
Clock
SSTL-2
CLASS II
24 mA
GCLK
SSTL-18
CLASS I
4 mA
SSTL-18
CLASS I
6 mA
SSTL-18
CLASS I
8 mA
SSTL-18
CLASS I
10 mA
SSTL-18
CLASS I
12 mA
SSTL-18
CLASS II
8 mA
SSTL-18
CLASS II
16 mA
SSTL-18
CLASS II
18 mA
SSTL-18
CLASS II
20 mA
1.8-V HSTL
CLASS I
4 mA
1.8-V HSTL
CLASS I
6 mA
1.8-V HSTL
CLASS I
8 mA
1.8-V HSTL
CLASS I
10 mA
1.8-V HSTL
CLASS I
12 mA
1.8-V HSTL
CLASS II
16 mA
1.8-V HSTL
CLASS II
18 mA
1.8-V HSTL
CLASS II
20 mA
1.5-V HSTL
CLASS I
4 mA
I/O Standard
Arria GX Device Handbook, Volume 1
Industrial
Commercial
–6 Speed
Grade
tCO
2.587
2.587
5.624
ns
GCLK PLL
tCO
1.142
1.142
2.512
ns
Parameter
Units
GCLK
tCO
2.626
2.626
5.733
ns
GCLK PLL
tCO
1.184
1.184
2.627
ns
GCLK
tCO
2.630
2.630
5.694
ns
GCLK PLL
tCO
1.185
1.185
2.582
ns
GCLK
tCO
2.609
2.609
5.675
ns
GCLK PLL
tCO
1.164
1.164
2.563
ns
GCLK
tCO
2.614
2.614
5.673
ns
GCLK PLL
tCO
1.169
1.169
2.561
ns
GCLK
tCO
2.608
2.608
5.659
ns
GCLK PLL
tCO
1.163
1.163
2.547
ns
GCLK
tCO
2.597
2.597
5.625
ns
GCLK PLL
tCO
1.152
1.152
2.513
ns
GCLK
tCO
2.609
2.609
5.603
ns
GCLK PLL
tCO
1.164
1.164
2.491
ns
GCLK
tCO
2.605
2.605
5.611
ns
GCLK PLL
tCO
1.160
1.160
2.499
ns
GCLK
tCO
2.605
2.605
5.609
ns
GCLK PLL
tCO
1.160
1.160
2.497
ns
GCLK
tCO
2.629
2.629
5.664
ns
GCLK PLL
tCO
1.187
1.187
2.558
ns
GCLK
tCO
2.634
2.634
5.649
ns
GCLK PLL
tCO
1.189
1.189
2.537
ns
GCLK
tCO
2.612
2.612
5.638
ns
GCLK PLL
tCO
1.167
1.167
2.526
ns
GCLK
tCO
2.616
2.616
5.644
ns
GCLK PLL
tCO
1.171
1.171
2.532
ns
GCLK
tCO
2.608
2.608
5.637
ns
GCLK PLL
tCO
1.163
1.163
2.525
ns
GCLK
tCO
2.591
2.591
5.401
ns
GCLK PLL
tCO
1.146
1.146
2.289
ns
GCLK
tCO
2.593
2.593
5.412
ns
GCLK PLL
tCO
1.148
1.148
2.300
ns
GCLK
tCO
2.593
2.593
5.421
ns
GCLK PLL
tCO
1.148
1.148
2.309
ns
GCLK
tCO
2.629
2.629
5.663
ns
GCLK PLL
tCO
1.187
1.187
2.557
ns
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–49
Table 4–57. EP1AGX35 Column Pins Output Timing Parameters (Part 4 of 4)
Fast Corner
Drive
Strength
Clock
1.5-V HSTL
CLASS I
6 mA
GCLK
1.5-V HSTL
CLASS I
8 mA
1.5-V HSTL
CLASS I
10 mA
1.5-V HSTL
CLASS I
12 mA
1.5-V HSTL
CLASS II
16 mA
1.5-V HSTL
CLASS II
18 mA
1.5-V HSTL
CLASS II
20 mA
I/O Standard
3.3-V PCI
3.3-V PCI-X
LVDS
Industrial
Commercial
–6 Speed
Grade
tCO
2.633
2.633
5.641
ns
GCLK PLL
tCO
1.188
1.188
2.529
ns
Parameter
Units
GCLK
tCO
2.615
2.615
5.643
ns
GCLK PLL
tCO
1.170
1.170
2.531
ns
GCLK
tCO
2.615
2.615
5.645
ns
GCLK PLL
tCO
1.170
1.170
2.533
ns
GCLK
tCO
2.609
2.609
5.643
ns
GCLK PLL
tCO
1.164
1.164
2.531
ns
GCLK
tCO
2.596
2.596
5.455
ns
GCLK PLL
tCO
1.151
1.151
2.343
ns
GCLK
tCO
2.599
2.599
5.465
ns
GCLK PLL
tCO
1.154
1.154
2.353
ns
GCLK
tCO
2.601
2.601
5.478
ns
GCLK PLL
tCO
1.156
1.156
2.366
ns
GCLK
tCO
2.755
2.755
5.791
ns
GCLK PLL
tCO
1.313
1.313
2.685
ns
GCLK
tCO
2.755
2.755
5.791
ns
GCLK PLL
tCO
1.313
1.313
2.685
ns
GCLK
tCO
3.621
3.621
6.969
ns
GCLK PLL
tCO
2.190
2.190
3.880
ns
—
—
—
Table 4–58 through Table 4–59 list EP1AGX35 regional clock (RCLK) adder values that
should be added to GCLK values. These adder values are used to determine I/O
timing when the I/O pin is driven using the regional clock. This applies for all I/O
standards supported by Arria GX with general purpose I/O pins.
Table 4–58 describes row pin delay adders when using the regional clock in Arria GX
devices.
Table 4–58. EP1AGX35 Row Pin Delay Adders for Regional Clock
Fast Corner
Parameter
© December 2009
–6 Speed Grade
Units
0.126
0.281
ns
0.011
0.011
0.018
ns
RCLK output adder
–0.126
–0.126
–0.281
ns
RCLK PLL output
adder
–0.011
–0.011
–0.018
ns
Industrial
Commercial
RCLK input adder
0.126
RCLK PLL input
adder
Altera Corporation
Arria GX Device Handbook, Volume 1
4–50
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–59 lists column pin delay adders when using the regional clock in Arria GX
devices.
Table 4–59. EP1AGX35 Column Pin Delay Adders for Regional Clock
Fast Corner
Parameter
–6 Speed Grade
Units
0.099
0.254
ns
–0.012
–0.012
–0.01
ns
RCLK output adder
–0.086
–0.086
–0.244
ns
RCLK PLL output adder
1.253
1.253
3.133
ns
Industrial
Commercial
RCLK input adder
0.099
RCLK PLL input adder
EP1AGX50 I/O Timing Parameters
Table 4–60 through Table 4–63 list the maximum I/O timing parameters for
EP1AGX50 devices for I/O standards which support general purpose I/O pins.
Table 4–60 lists I/O timing specifications.
Table 4–60. EP1AGX50 Row Pins Input Timing Parameters (Part 1 of 2)
Fast Model
I/O Standard
Clock
Parameter
Industrial
Commercial
–6 Speed
Grade
Units
t SU
1.550
1.550
3.542
ns
tH
–1.445
–1.445
–3.265
ns
t SU
2.978
2.978
6.626
ns
tH
–2.873
–2.873
–6.349
ns
t SU
1.550
1.550
3.542
ns
tH
–1.445
–1.445
–3.265
ns
GCLK PLL
t SU
2.978
2.978
6.626
ns
tH
–2.873
–2.873
–6.349
ns
GCLK
t SU
1.562
1.562
3.523
ns
tH
–1.457
–1.457
–3.246
ns
t SU
2.990
2.990
6.607
ns
tH
–2.885
–2.885
–6.330
ns
t SU
1.628
1.628
3.730
ns
tH
–1.523
–1.523
–3.453
ns
GCLK PLL
t SU
3.056
3.056
6.814
ns
tH
–2.951
–2.951
–6.537
ns
GCLK
t SU
1.631
1.631
3.825
ns
tH
–1.526
–1.526
–3.548
ns
t SU
3.059
3.059
6.909
ns
tH
–2.954
–2.954
–6.632
ns
GCLK
3.3-V LVTTL
GCLK PLL
GCLK
3.3-V LVCMOS
2.5 V
GCLK PLL
GCLK
1.8 V
1.5 V
GCLK PLL
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–51
Table 4–60. EP1AGX50 Row Pins Input Timing Parameters (Part 2 of 2)
Fast Model
I/O Standard
Clock
GCLK
SSTL-2 CLASS
I
GCLK PLL
GCLK
SSTL-2 CLASS
II
GCLK PLL
GCLK
SSTL-18
CLASS I
GCLK PLL
GCLK
SSTL-18
CLASS II
GCLK PLL
GCLK
1.8-V HSTL
CLASS I
GCLK PLL
GCLK
1.8-V HSTL
CLASS II
GCLK PLL
GCLK
1.5-V HSTL
CLASS I
GCLK PLL
GCLK
1.5-V HSTL
CLASS II
GCLK PLL
GCLK
LVDS
GCLK PLL
© December 2009
Altera Corporation
Industrial
Commercial
–6 Speed
Grade
t SU
1.375
1.375
2.997
ns
tH
–1.270
–1.270
–2.720
ns
Parameter
Units
t SU
2.802
2.802
6.079
ns
tH
–2.697
–2.697
–5.802
ns
t SU
1.375
1.375
2.997
ns
tH
–1.270
–1.270
–2.720
ns
t SU
2.802
2.802
6.079
ns
tH
–2.697
–2.697
–5.802
ns
t SU
1.406
1.406
3.104
ns
tH
–1.301
–1.301
–2.827
ns
t SU
2.834
2.834
6.188
ns
tH
–2.729
–2.729
–5.911
ns
t SU
1.407
1.407
3.106
ns
tH
–1.302
–1.302
–2.829
ns
t SU
2.834
2.834
6.188
ns
tH
–2.729
–2.729
–5.911
ns
t SU
1.406
1.406
3.104
ns
tH
–1.301
–1.301
–2.827
ns
t SU
2.834
2.834
6.188
ns
tH
–2.729
–2.729
–5.911
ns
t SU
1.407
1.407
3.106
ns
tH
–1.302
–1.302
–2.829
ns
t SU
2.834
2.834
6.188
ns
tH
–2.729
–2.729
–5.911
ns
t SU
1.432
1.432
3.232
ns
tH
–1.327
–1.327
–2.955
ns
t SU
2.860
2.860
6.316
ns
tH
–2.755
–2.755
–6.039
ns
t SU
1.433
1.433
3.234
ns
tH
–1.328
–1.328
–2.957
ns
t SU
2.860
2.860
6.316
ns
tH
–2.755
–2.755
–6.039
ns
t SU
1.341
1.341
3.088
ns
tH
–1.236
–1.236
–2.811
ns
t SU
2.769
2.769
6.171
ns
tH
–2.664
–2.664
–5.894
ns
Arria GX Device Handbook, Volume 1
4–52
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–61 lists I/O timing specifications.
Table 4–61. EP1AGX50 Column Pins Input Timing Parameters (Part 1 of 2)
Fast Corner
I/O Standard
Industrial
Commercial
–6 Speed
Grade
tSU
1.242
1.242
2.902
ns
tH
–1.137
–1.137
–2.625
ns
GCLK PLL
tSU
2.684
2.684
6.009
ns
tH
–2.579
–2.579
–5.732
ns
GCLK
tSU
1.242
1.242
2.902
ns
tH
–1.137
–1.137
–2.625
ns
tSU
2.684
2.684
6.009
ns
tH
–2.579
–2.579
–5.732
ns
tSU
1.252
1.252
2.884
ns
tH
–1.147
–1.147
–2.607
ns
GCLK PLL
tSU
2.694
2.694
5.991
ns
tH
–2.589
–2.589
–5.714
ns
GCLK
tSU
1.318
1.318
3.094
ns
tH
–1.213
–1.213
–2.817
ns
tSU
2.760
2.760
6.201
ns
tH
–2.655
–2.655
–5.924
ns
tSU
1.321
1.321
3.187
ns
tH
–1.216
–1.216
–2.910
ns
GCLK PLL
tSU
2.763
2.763
6.294
ns
tH
–2.658
–2.658
–6.017
ns
GCLK
tSU
1.034
1.034
2.314
ns
tH
–0.929
–0.929
–2.037
ns
tSU
2.500
2.500
5.457
ns
tH
–2.395
–2.395
–5.180
ns
tSU
1.034
1.034
2.314
ns
tH
–0.929
–0.929
–2.037
ns
GCLK PLL
tSU
2.500
2.500
5.457
ns
tH
–2.395
–2.395
–5.180
ns
GCLK
tSU
1.104
1.104
2.466
ns
tH
–0.999
–0.999
–2.189
ns
tSU
2.546
2.546
5.573
ns
tH
–2.441
–2.441
–5.296
ns
tSU
1.074
1.074
2.424
ns
tH
–0.969
–0.969
–2.147
ns
tSU
2.539
2.539
5.564
ns
tH
–2.434
–2.434
–5.287
ns
Clock
GCLK
3.3-V LVTTL
3.3-V
LVCMOS
GCLK PLL
GCLK
2.5 V
1.8 V
GCLK PLL
GCLK
1.5 V
SSTL-2
CLASS I
GCLK PLL
GCLK
SSTL-2
CLASS II
SSTL-18
CLASS I
GCLK PLL
GCLK
SSTL-18
CLASS II
GCLK PLL
Arria GX Device Handbook, Volume 1
Parameter
Units
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–53
Table 4–61. EP1AGX50 Column Pins Input Timing Parameters (Part 2 of 2)
Fast Corner
I/O Standard
Clock
GCLK
1.8-V HSTL
CLASS I
GCLK PLL
GCLK
1.8-V HSTL
CLASS II
GCLK PLL
GCLK
1.5-V HSTL
CLASS I
GCLK PLL
GCLK
1.5-V HSTL
CLASS II
Industrial
Commercial
–6 Speed
Grade
tSU
1.104
1.104
2.466
ns
tH
–0.999
–0.999
–2.189
ns
Parameter
GCLK PLL
GCLK
3.3-V PCI
GCLK PLL
GCLK
3.3-V PCI-X
GCLK PLL
GCLK
LVDS
GCLK PLL
Units
tSU
2.546
2.546
5.573
ns
tH
–2.441
–2.441
–5.296
ns
tSU
1.074
1.074
2.424
ns
tH
–0.969
–0.969
–2.147
ns
tSU
2.539
2.539
5.564
ns
tH
–2.434
–2.434
–5.287
ns
tSU
1.122
1.122
2.594
ns
tH
–1.017
–1.017
–2.317
ns
tSU
2.564
2.564
5.701
ns
tH
–2.459
–2.459
–5.424
ns
tSU
1.094
1.094
2.557
ns
tH
–0.989
–0.989
–2.280
ns
tSU
2.557
2.557
5.692
ns
tH
–2.452
–2.452
–5.415
ns
tSU
1.247
1.247
2.890
ns
tH
–1.142
–1.142
–2.613
ns
tSU
2.689
2.689
5.997
ns
tH
–2.584
–2.584
–5.720
ns
tSU
1.247
1.247
2.890
ns
tH
–1.142
–1.142
–2.613
ns
tSU
2.689
2.689
5.997
ns
tH
–2.584
–2.584
–5.720
ns
tSU
1.106
1.106
2.489
ns
tH
–1.001
–1.001
–2.212
ns
tSU
2.530
2.530
5.564
ns
tH
–2.425
–2.425
–5.287
ns
Table 4–62 lists I/O timing specifications.
Table 4–62. EP1AGX50 Row Pins Output Timing Parameters (Part 1 of 3)
I/O Standard
3.3-V LVTTL
3.3-V LVTTL
© December 2009
Fast Model
Drive
Strength
Clock
4 mA
GCLK
Industrial
Commercial
–6 Speed
Grade
tCO
2.915
2.915
6.713
ns
GCLK PLL
tCO
1.487
1.487
3.629
ns
GCLK
tCO
2.787
2.787
6.073
ns
GCLK PLL
tCO
1.359
1.359
2.989
ns
8 mA
Altera Corporation
Parameter
Units
Arria GX Device Handbook, Volume 1
4–54
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–62. EP1AGX50 Row Pins Output Timing Parameters (Part 2 of 3)
I/O Standard
3.3-V LVTTL
Clock
12 mA
GCLK
3.3-V
LVCMOS
4 mA
3.3-V
LVCMOS
8 mA
2.5 V
4 mA
2.5 V
2.5 V
1.8 V
1.8 V
1.8 V
1.8 V
1.5 V
1.5 V
Fast Model
Drive
Strength
8 mA
12 mA
2 mA
4 mA
6 mA
8 mA
2 mA
4 mA
SSTL-2
CLASS I
8 mA
SSTL-2
CLASS I
12 mA
SSTL-2
CLASS II
16 mA
SSTL-18
CLASS I
4 mA
SSTL-18
CLASS I
6 mA
SSTL-18
CLASS I
8 mA
SSTL-18
CLASS I
10 mA
Arria GX Device Handbook, Volume 1
Industrial
Commercial
–6 Speed
Grade
tCO
2.731
2.731
6.036
ns
GCLK PLL
tCO
1.303
1.303
2.952
ns
Parameter
Units
GCLK
tCO
2.787
2.787
6.073
ns
GCLK PLL
tCO
1.359
1.359
2.989
ns
GCLK
tCO
2.681
2.681
5.767
ns
GCLK PLL
tCO
1.253
1.253
2.683
ns
GCLK
tCO
2.770
2.770
6.047
ns
GCLK PLL
tCO
1.342
1.342
2.963
ns
GCLK
tCO
2.667
2.667
5.789
ns
GCLK PLL
tCO
1.239
1.239
2.705
ns
GCLK
tCO
2.648
2.648
5.675
ns
GCLK PLL
tCO
1.220
1.220
2.591
ns
GCLK
tCO
2.840
2.840
7.066
ns
GCLK PLL
tCO
1.412
1.412
3.982
ns
GCLK
tCO
2.829
2.829
6.287
ns
GCLK PLL
tCO
1.401
1.401
3.203
ns
GCLK
tCO
2.718
2.718
5.986
ns
GCLK PLL
tCO
1.290
1.290
2.902
ns
GCLK
tCO
2.687
2.687
5.872
ns
GCLK PLL
tCO
1.259
1.259
2.788
ns
GCLK
tCO
2.800
2.800
6.565
ns
GCLK PLL
tCO
1.372
1.372
3.481
ns
GCLK
tCO
2.693
2.693
5.964
ns
GCLK PLL
tCO
1.265
1.265
2.880
ns
GCLK
tCO
2.636
2.636
5.626
ns
GCLK PLL
tCO
1.209
1.209
2.544
ns
GCLK
tCO
2.612
2.612
5.550
ns
GCLK PLL
tCO
1.185
1.185
2.468
ns
GCLK
tCO
2.578
2.578
5.419
ns
GCLK PLL
tCO
1.151
1.151
2.337
ns
GCLK
tCO
2.625
2.625
5.570
ns
GCLK PLL
tCO
1.197
1.197
2.486
ns
GCLK
tCO
2.628
2.628
5.497
ns
GCLK PLL
tCO
1.201
1.201
2.415
ns
GCLK
tCO
2.604
2.604
5.480
ns
GCLK PLL
tCO
1.177
1.177
2.398
ns
GCLK
tCO
2.607
2.607
5.459
ns
GCLK PLL
tCO
1.180
1.180
2.377
ns
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–55
Table 4–62. EP1AGX50 Row Pins Output Timing Parameters (Part 3 of 3)
Fast Model
Drive
Strength
Clock
1.8-V HSTL
CLASS I
4 mA
GCLK
1.8-V HSTL
CLASS I
6 mA
1.8-V HSTL
CLASS I
8 mA
1.8-V HSTL
CLASS I
10 mA
1.8-V HSTL
CLASS I
12 mA
1.5-V HSTL
CLASS I
4 mA
1.5-V HSTL
CLASS I
6 mA
1.5-V HSTL
CLASS I
8 mA
I/O Standard
LVDS
Industrial
Commercial
–6 Speed
Grade
tCO
2.606
2.606
5.480
ns
GCLK PLL
tCO
1.178
1.178
2.396
ns
Parameter
Units
GCLK
tCO
2.608
2.608
5.442
ns
GCLK PLL
tCO
1.181
1.181
2.360
ns
GCLK
tCO
2.590
2.590
5.438
ns
GCLK PLL
tCO
1.163
1.163
2.356
ns
GCLK
tCO
2.594
2.594
5.427
ns
GCLK PLL
tCO
1.167
1.167
2.345
ns
GCLK
tCO
2.585
2.585
5.426
ns
GCLK PLL
tCO
1.158
1.158
2.344
ns
GCLK
tCO
2.605
2.605
5.457
ns
GCLK PLL
tCO
1.177
1.177
2.373
ns
GCLK
tCO
2.607
2.607
5.441
ns
GCLK PLL
tCO
1.180
1.180
2.359
ns
GCLK
tCO
2.592
2.592
5.433
ns
GCLK PLL
tCO
1.165
1.165
2.351
ns
GCLK
tCO
2.654
2.654
5.613
ns
GCLK PLL
tCO
1.226
1.226
2.530
ns
Units
—
Table 4–63 lists I/O timing specifications.
Table 4–63. EP1AGX50 Column Pins Output Timing Parameters (Part 1 of 4)
I/O Standard
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V
LVCMOS
© December 2009
Fast Corner
Drive
Strength
Clock
4 mA
GCLK
8 mA
12 mA
16 mA
20 mA
24 mA
4 mA
Altera Corporation
Industrial
Commercial
–6 Speed
Grade
tCO
2.948
2.948
6.608
ns
GCLK PLL
tCO
1.476
1.476
3.447
ns
GCLK
tCO
2.797
2.797
6.203
ns
GCLK PLL
tCO
1.331
1.331
3.075
ns
GCLK
tCO
2.722
2.722
6.204
ns
GCLK PLL
tCO
1.264
1.264
3.075
ns
Parameter
GCLK
tCO
2.694
2.694
6.024
ns
GCLK PLL
tCO
1.238
1.238
2.906
ns
GCLK
tCO
2.670
2.670
5.896
ns
GCLK PLL
tCO
1.216
1.216
2.781
ns
GCLK
tCO
2.660
2.660
5.895
ns
GCLK PLL
tCO
1.209
1.209
2.783
ns
GCLK
tCO
2.797
2.797
6.203
ns
GCLK PLL
tCO
1.331
1.331
3.075
ns
Arria GX Device Handbook, Volume 1
4–56
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–63. EP1AGX50 Column Pins Output Timing Parameters (Part 2 of 4)
Fast Corner
Drive
Strength
Clock
3.3-V
LVCMOS
8 mA
GCLK
3.3-V
LVCMOS
12 mA
3.3-V
LVCMOS
16 mA
3.3-V
LVCMOS
20 mA
3.3-V
LVCMOS
24 mA
2.5 V
4 mA
I/O Standard
2.5 V
2.5 V
2.5 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.5 V
1.5 V
1.5 V
1.5 V
8 mA
12 mA
16 mA
2 mA
4 mA
6 mA
8 mA
10 mA
12 mA
2 mA
4 mA
6 mA
8 mA
Arria GX Device Handbook, Volume 1
Industrial
Commercial
–6 Speed
Grade
tCO
2.695
2.695
5.893
ns
GCLK PLL
tCO
1.239
1.239
2.780
ns
Parameter
Units
GCLK
tCO
2.663
2.663
5.809
ns
GCLK PLL
tCO
1.211
1.211
2.702
ns
GCLK
tCO
2.666
2.666
5.776
ns
GCLK PLL
tCO
1.218
1.218
2.670
ns
GCLK
tCO
2.651
2.651
5.758
ns
GCLK PLL
tCO
1.205
1.205
2.652
ns
GCLK
tCO
2.638
2.638
5.736
ns
GCLK PLL
tCO
1.194
1.194
2.630
ns
GCLK
tCO
2.754
2.754
6.240
ns
GCLK PLL
tCO
1.293
1.293
3.107
ns
GCLK
tCO
2.697
2.697
5.963
ns
GCLK PLL
tCO
1.241
1.241
2.845
ns
GCLK
tCO
2.672
2.672
5.837
ns
GCLK PLL
tCO
1.220
1.220
2.728
ns
GCLK
tCO
2.654
2.654
5.760
ns
GCLK PLL
tCO
1.202
1.202
2.654
ns
GCLK
tCO
2.804
2.804
7.295
ns
GCLK PLL
tCO
1.333
1.333
4.099
ns
GCLK
tCO
2.808
2.808
6.479
ns
GCLK PLL
tCO
1.338
1.338
3.325
ns
GCLK
tCO
2.717
2.717
6.195
ns
GCLK PLL
tCO
1.262
1.262
3.061
ns
GCLK
tCO
2.719
2.719
6.098
ns
GCLK PLL
tCO
1.264
1.264
2.970
ns
GCLK
tCO
2.671
2.671
6.012
ns
GCLK PLL
tCO
1.218
1.218
2.893
ns
GCLK
tCO
2.671
2.671
5.953
ns
GCLK PLL
tCO
1.219
1.219
2.836
ns
GCLK
tCO
2.779
2.779
6.815
ns
GCLK PLL
tCO
1.313
1.313
3.629
ns
GCLK
tCO
2.703
2.703
6.210
ns
GCLK PLL
tCO
1.249
1.249
3.060
ns
GCLK
tCO
2.705
2.705
6.118
ns
GCLK PLL
tCO
1.252
1.252
2.942
ns
GCLK
tCO
2.660
2.660
6.014
ns
GCLK PLL
tCO
1.211
1.211
2.889
ns
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–57
Table 4–63. EP1AGX50 Column Pins Output Timing Parameters (Part 3 of 4)
Fast Corner
Drive
Strength
Clock
SSTL-2
CLASS I
8 mA
GCLK
SSTL-2
CLASS I
12 mA
SSTL-2
CLASS II
16 mA
SSTL-2
CLASS II
20 mA
SSTL-2
CLASS II
24 mA
SSTL-18
CLASS I
4 mA
SSTL-18
CLASS I
6 mA
SSTL-18
CLASS I
8 mA
SSTL-18
CLASS I
10 mA
SSTL-18
CLASS I
12 mA
SSTL-18
CLASS II
8 mA
SSTL-18
CLASS II
16 mA
SSTL-18
CLASS II
18 mA
SSTL-18
CLASS II
20 mA
1.8-V HSTL
CLASS I
4 mA
1.8-V HSTL
CLASS I
6 mA
1.8-V HSTL
CLASS I
8 mA
1.8-V HSTL
CLASS I
10 mA
1.8-V HSTL
CLASS I
12 mA
I/O Standard
© December 2009
Industrial
Commercial
–6 Speed
Grade
tCO
2.648
2.648
5.777
ns
GCLK PLL
tCO
1.202
1.202
2.675
ns
Parameter
Units
GCLK
tCO
2.628
2.628
5.722
ns
GCLK PLL
tCO
1.185
1.185
2.625
ns
GCLK
tCO
2.606
2.606
5.649
ns
GCLK PLL
tCO
1.163
1.163
2.552
ns
GCLK
tCO
2.606
2.606
5.636
ns
GCLK PLL
tCO
1.164
1.164
2.539
ns
GCLK
tCO
2.601
2.601
5.634
ns
GCLK PLL
tCO
1.160
1.160
2.537
ns
GCLK
tCO
2.643
2.643
5.749
ns
GCLK PLL
tCO
1.193
1.193
2.639
ns
GCLK
tCO
2.649
2.649
5.708
ns
GCLK PLL
tCO
1.203
1.203
2.607
ns
GCLK
tCO
2.626
2.626
5.686
ns
GCLK PLL
tCO
1.182
1.182
2.588
ns
GCLK
tCO
2.630
2.630
5.685
ns
GCLK PLL
tCO
1.187
1.187
2.586
ns
GCLK
tCO
2.625
2.625
5.669
ns
GCLK PLL
tCO
1.181
1.181
2.572
ns
GCLK
tCO
2.614
2.614
5.635
ns
GCLK PLL
tCO
1.170
1.170
2.538
ns
GCLK
tCO
2.623
2.623
5.613
ns
GCLK PLL
tCO
1.182
1.182
2.516
ns
GCLK
tCO
2.616
2.616
5.621
ns
GCLK PLL
tCO
1.178
1.178
2.524
ns
GCLK
tCO
2.616
2.616
5.619
ns
GCLK PLL
tCO
1.178
1.178
2.522
ns
GCLK
tCO
2.637
2.637
5.676
ns
GCLK PLL
tCO
1.196
1.196
2.570
ns
GCLK
tCO
2.645
2.645
5.659
ns
GCLK PLL
tCO
1.207
1.207
2.562
ns
GCLK
tCO
2.623
2.623
5.648
ns
GCLK PLL
tCO
1.185
1.185
2.551
ns
GCLK
tCO
2.627
2.627
5.654
ns
GCLK PLL
tCO
1.189
1.189
2.557
ns
GCLK
tCO
2.619
2.619
5.647
ns
GCLK PLL
tCO
1.181
1.181
2.550
ns
Altera Corporation
Arria GX Device Handbook, Volume 1
4–58
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–63. EP1AGX50 Column Pins Output Timing Parameters (Part 4 of 4)
Fast Corner
Drive
Strength
Clock
1.8-V HSTL
CLASS II
16 mA
GCLK
1.8-V HSTL
CLASS II
18 mA
1.8-V HSTL
CLASS II
20 mA
1.5-V HSTL
CLASS I
4 mA
1.5-V HSTL
CLASS I
6 mA
1.5-V HSTL
CLASS I
8 mA
1.5-V HSTL
CLASS I
10 mA
1.5-V HSTL
CLASS I
12 mA
1.5-V HSTL
CLASS II
16 mA
1.5-V HSTL
CLASS II
18 mA
1.5-V HSTL
CLASS II
20 mA
I/O Standard
3.3-V PCI
3.3-V PCI-X
LVDS
—
—
—
Industrial
Commercial
–6 Speed
Grade
tCO
2.602
2.602
5.574
ns
GCLK PLL
tCO
1.164
1.164
2.314
ns
Parameter
Units
GCLK
tCO
2.604
2.604
5.578
ns
GCLK PLL
tCO
1.166
1.166
2.325
ns
GCLK
tCO
2.604
2.604
5.577
ns
GCLK PLL
tCO
1.166
1.166
2.334
ns
GCLK
tCO
2.637
2.637
5.675
ns
GCLK PLL
tCO
1.196
1.196
2.569
ns
GCLK
tCO
2.644
2.644
5.651
ns
GCLK PLL
tCO
1.206
1.206
2.554
ns
GCLK
tCO
2.626
2.626
5.653
ns
GCLK PLL
tCO
1.188
1.188
2.556
ns
GCLK
tCO
2.626
2.626
5.655
ns
GCLK PLL
tCO
1.188
1.188
2.558
ns
GCLK
tCO
2.620
2.620
5.653
ns
GCLK PLL
tCO
1.182
1.182
2.556
ns
GCLK
tCO
2.607
2.607
5.573
ns
GCLK PLL
tCO
1.169
1.169
2.368
ns
GCLK
tCO
2.610
2.610
5.571
ns
GCLK PLL
tCO
1.172
1.172
2.378
ns
GCLK
tCO
2.612
2.612
5.581
ns
GCLK PLL
tCO
1.174
1.174
2.391
ns
GCLK
tCO
2.786
2.786
5.803
ns
GCLK PLL
tCO
1.322
1.322
2.697
ns
GCLK
tCO
2.786
2.786
5.803
ns
GCLK PLL
tCO
1.322
1.322
2.697
ns
GCLK
tCO
3.621
3.621
6.969
ns
GCLK PLL
tCO
2.190
2.190
3.880
ns
Table 4–64 through Table 4–65 list EP1AGX50 regional clock (RCLK) adder values that
should be added to the GCLK values. These adder values are used to determine I/O
timing when the I/O pin is driven using the regional clock. This applies for all I/O
standards supported by Arria GX with general purpose I/O pins.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–59
Table 4–64 lists row pin delay adders when using the regional clock in Arria GX
devices.
Table 4–64. EP1AGX50 Row Pin Delay Adders for Regional Clock
Fast Corner
Parameter
–6 Speed Grade
Units
0.151
0.329
ns
0.011
0.011
0.016
ns
RCLK output adder
–0.151
–0.151
–0.329
ns
RCLK PLL output adder
–0.011
–0.011
–0.016
ns
Industrial
Commercial
RCLK input adder
0.151
RCLK PLL input adder
Table 4–65 lists column pin delay adders when using the regional clock in Arria GX
devices.
Table 4–65. EP1AGX50 Column Pin Delay Adders for Regional Clock
Fast Corner
Parameter
–6 Speed Grade
Units
0.146
0.334
ns
–1.713
–1.713
–3.645
ns
RCLK output adder
–0.146
–0.146
–0.336
ns
RCLK PLL output adder
1.716
1.716
4.488
ns
Industrial
Commercial
RCLK input adder
0.146
RCLK PLL input adder
EP1AGX60 I/O Timing Parameters
Table 4–66 through Table 4–69 list the maximum I/O timing parameters for
EP1AGX60 devices for I/O standards which support general purpose I/O pins.
Table 4–66 lists I/O timing specifications.
Table 4–66. EP1AGX60 Row Pins Input Timing Parameters (Part 1 of 3)
Fast Model
I/O Standard
Industrial
Commercial
–6 Speed
Grade
t SU
1.413
1.413
3.113
ns
tH
–1.308
–1.308
–2.836
ns
GCLK PLL
t SU
2.975
2.975
6.536
ns
tH
–2.870
–2.870
–6.259
ns
GCLK
t SU
1.413
1.413
3.113
ns
tH
–1.308
–1.308
–2.836
ns
t SU
2.975
2.975
6.536
ns
tH
–2.870
–2.870
–6.259
ns
t SU
1.425
1.425
3.094
ns
tH
–1.320
–1.320
–2.817
ns
t SU
2.987
2.987
6.517
ns
tH
–2.882
–2.882
–6.240
ns
Clock
GCLK
3.3-V LVTTL
3.3-V LVCMOS
GCLK PLL
GCLK
2.5 V
GCLK PLL
© December 2009
Altera Corporation
Parameter
Units
Arria GX Device Handbook, Volume 1
4–60
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–66. EP1AGX60 Row Pins Input Timing Parameters (Part 2 of 3)
Fast Model
I/O Standard
Clock
GCLK
1.8 V
GCLK PLL
GCLK
1.5 V
GCLK PLL
GCLK
SSTL-2 CLASS I
GCLK PLL
GCLK
SSTL-2 CLASS II
GCLK PLL
GCLK
SSTL-18 CLASS I
GCLK PLL
GCLK
SSTL-18 CLASS II
GCLK PLL
GCLK
1.8-V HSTL CLASS I
GCLK PLL
GCLK
1.8-V HSTL CLASS II
GCLK PLL
GCLK
1.5-V HSTL CLASS I
GCLK PLL
Arria GX Device Handbook, Volume 1
Industrial
Commercial
–6 Speed
Grade
t SU
1.477
1.477
3.275
ns
tH
–1.372
–1.372
–2.998
ns
Parameter
Units
t SU
3.049
3.049
6.718
ns
tH
–2.944
–2.944
–6.441
ns
t SU
1.480
1.480
3.370
ns
tH
–1.375
–1.375
–3.093
ns
t SU
3.052
3.052
6.813
ns
tH
–2.947
–2.947
–6.536
ns
t SU
1.237
1.237
2.566
ns
tH
–1.132
–1.132
–2.289
ns
t SU
2.800
2.800
5.990
ns
tH
–2.695
–2.695
–5.713
ns
t SU
1.237
1.237
2.566
ns
tH
–1.132
–1.132
–2.289
ns
t SU
2.800
2.800
5.990
ns
tH
–2.695
–2.695
–5.713
ns
t SU
1.255
1.255
2.649
ns
tH
–1.150
–1.150
–2.372
ns
t SU
2.827
2.827
6.092
ns
tH
–2.722
–2.722
–5.815
ns
t SU
1.255
1.255
2.649
ns
tH
–1.150
–1.150
–2.372
ns
t SU
2.827
2.827
6.092
ns
tH
–2.722
–2.722
–5.815
ns
t SU
1.255
1.255
2.649
ns
tH
–1.150
–1.150
–2.372
ns
t SU
2.827
2.827
6.092
ns
tH
–2.722
–2.722
–5.815
ns
t SU
1.255
1.255
2.649
ns
tH
–1.150
–1.150
–2.372
ns
t SU
2.827
2.827
6.092
ns
tH
–2.722
–2.722
–5.815
ns
t SU
1.281
1.281
2.777
ns
tH
–1.176
–1.176
–2.500
ns
t SU
2.853
2.853
6.220
ns
tH
–2.748
–2.748
–5.943
ns
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–61
Table 4–66. EP1AGX60 Row Pins Input Timing Parameters (Part 3 of 3)
Fast Model
I/O Standard
Clock
GCLK
1.5-V HSTL CLASS II
GCLK PLL
GCLK
LVDS
GCLK PLL
Industrial
Commercial
–6 Speed
Grade
t SU
1.281
1.281
2.777
ns
tH
–1.176
–1.176
–2.500
ns
Parameter
Units
t SU
2.853
2.853
6.220
ns
tH
–2.748
–2.748
–5.943
ns
t SU
1.208
1.208
2.664
ns
tH
–1.103
–1.103
–2.387
ns
t SU
2.767
2.767
6.083
ns
tH
–2.662
–2.662
–5.806
ns
–6 Speed
Grade
Units
Table 4–67 lists I/O timing specifications.
Table 4–67. EP1AGX60 Column Pins Input Timing Parameters (Part 1 of 3)
Fast Corner
I/O Standard
Clock
Parameter
Industrial
tSU
1.124
1.124
2.493
ns
tH
–1.019
–1.019
-2.216
ns
tSU
2.694
2.694
5.928
ns
tH
–2.589
–2.589
-5.651
ns
tSU
1.124
1.124
2.493
ns
tH
–1.019
–1.019
-2.216
ns
GCLK PLL
tSU
2.694
2.694
5.928
ns
tH
–2.589
–2.589
-5.651
ns
GCLK
tSU
1.134
1.134
2.475
ns
tH
–1.029
–1.029
-2.198
ns
tSU
2.704
2.704
5.910
ns
tH
–2.599
–2.599
-5.633
ns
tSU
1.200
1.200
2.685
ns
tH
–1.095
–1.095
-2.408
ns
GCLK PLL
tSU
2.770
2.770
6.120
ns
tH
–2.665
–2.665
-5.843
ns
GCLK
tSU
1.203
1.203
2.778
ns
tH
–1.098
–1.098
-2.501
ns
tSU
2.773
2.773
6.213
ns
tH
–2.668
–2.668
-5.936
ns
tSU
0.948
0.948
1.951
ns
tH
–0.843
–0.843
-1.674
ns
tSU
2.519
2.519
5.388
ns
tH
–2.414
–2.414
-5.111
ns
GCLK
3.3-V LVTTL
GCLK PLL
GCLK
3.3-V LVCMOS
2.5 V
GCLK PLL
GCLK
1.8 V
1.5 V
GCLK PLL
GCLK
SSTL-2 CLASS I
GCLK PLL
© December 2009
Commercial
Altera Corporation
Arria GX Device Handbook, Volume 1
4–62
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–67. EP1AGX60 Column Pins Input Timing Parameters (Part 2 of 3)
Fast Corner
I/O Standard
Clock
GCLK
SSTL-2 CLASS II
GCLK PLL
GCLK
SSTL-18 CLASS I
GCLK PLL
GCLK
SSTL-18 CLASS II
GCLK PLL
GCLK
1.8-V HSTL CLASS I
GCLK PLL
GCLK
1.8-V HSTL CLASS II
GCLK PLL
GCLK
1.5-V HSTL CLASS I
GCLK PLL
GCLK
1.5-V HSTL CLASS II
GCLK PLL
GCLK
3.3-V PCI
GCLK PLL
GCLK
3.3-V PCI-X
GCLK PLL
Arria GX Device Handbook, Volume 1
Industrial
Commercial
–6 Speed
Grade
tSU
0.948
0.948
1.951
ns
tH
–0.843
–0.843
–1.674
ns
Parameter
Units
tSU
2.519
2.519
5.388
ns
tH
–2.414
–2.414
–5.111
ns
tSU
0.986
0.986
2.057
ns
tH
–0.881
–0.881
–1.780
ns
tSU
2.556
2.556
5.492
ns
tH
–2.451
–2.451
–5.215
ns
tSU
0.987
0.987
2.058
ns
tH
–0.882
–0.882
–1.781
ns
tSU
2.558
2.558
5.495
ns
tH
–2.453
–2.453
–5.218
ns
tSU
0.986
0.986
2.057
ns
tH
–0.881
–0.881
–1.780
ns
tSU
2.556
2.556
5.492
ns
tH
–2.451
–2.451
–5.215
ns
tSU
0.987
0.987
2.058
ns
tH
–0.882
–0.882
–1.781
ns
tSU
2.558
2.558
5.495
ns
tH
–2.453
–2.453
–5.218
ns
tSU
1.004
1.004
2.185
ns
tH
–0.899
–0.899
–1.908
ns
tSU
2.574
2.574
5.620
ns
tH
–2.469
–2.469
–5.343
ns
tSU
1.005
1.005
2.186
ns
tH
–0.900
–0.900
–1.909
ns
tSU
2.576
2.576
5.623
ns
tH
–2.471
–2.471
–5.346
ns
tSU
1.129
1.129
2.481
ns
tH
–1.024
–1.024
–2.204
ns
tSU
2.699
2.699
5.916
ns
tH
–2.594
–2.594
–5.639
ns
tSU
1.129
1.129
2.481
ns
tH
–1.024
–1.024
–2.204
ns
tSU
2.699
2.699
5.916
ns
tH
–2.594
–2.594
–5.639
ns
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–63
Table 4–67. EP1AGX60 Column Pins Input Timing Parameters (Part 3 of 3)
Fast Corner
I/O Standard
Clock
GCLK
LVDS
GCLK PLL
Industrial
Commercial
–6 Speed
Grade
tSU
0.980
0.980
2.062
ns
tH
–0.875
–0.875
–1.785
ns
Parameter
Units
tSU
2.557
2.557
5.512
ns
tH
–2.452
–2.452
–5.235
ns
Units
Table 4–68 lists I/O timing specifications.
Table 4–68. EP1AGX60 Row Pins Output Timing Parameters (Part 1 of 2)
I/O Standard
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
Clock
4 mA
GCLK
3.3-V
LVCMOS
8 mA
2.5 V
1.8 V
1.8 V
1.8 V
1.8 V
1.5 V
1.5 V
© December 2009
Commercial
tCO
3.052
3.052
7.142
ns
GCLK PLL
tCO
1.490
1.490
3.719
ns
GCLK
tCO
2.924
2.924
6.502
ns
GCLK PLL
tCO
1.362
1.362
3.079
ns
Parameter
GCLK
tCO
2.868
2.868
6.465
ns
GCLK PLL
tCO
1.306
1.306
3.042
ns
GCLK
tCO
2.924
2.924
6.502
ns
GCLK PLL
tCO
1.362
1.362
3.079
ns
GCLK
tCO
2.818
2.818
6.196
ns
GCLK PLL
tCO
1.256
1.256
2.773
ns
GCLK
tCO
2.907
2.907
6.476
ns
GCLK PLL
tCO
1.345
1.345
3.053
ns
12 mA
4 mA
2.5 V
Industrial
–6 Speed
Grade
8 mA
3.3-V
LVCMOS
2.5 V
Fast Model
Drive
Strength
4 mA
GCLK
tCO
2.804
2.804
6.218
ns
GCLK PLL
tCO
1.242
1.242
2.795
ns
GCLK
tCO
2.785
2.785
6.104
ns
GCLK PLL
tCO
1.223
1.223
2.681
ns
GCLK
tCO
2.991
2.991
7.521
ns
GCLK PLL
tCO
1.419
1.419
4.078
ns
GCLK
tCO
2.980
2.980
6.742
ns
GCLK PLL
tCO
1.408
1.408
3.299
ns
8 mA
12 mA
2 mA
4 mA
GCLK
tCO
2.869
2.869
6.441
ns
GCLK PLL
tCO
1.297
1.297
2.998
ns
GCLK
tCO
2.838
2.838
6.327
ns
GCLK PLL
tCO
1.266
1.266
2.884
ns
GCLK
tCO
2.951
2.951
7.020
ns
GCLK PLL
tCO
1.379
1.379
3.577
ns
GCLK
tCO
2.844
2.844
6.419
ns
GCLK PLL
tCO
1.272
1.272
2.976
ns
6 mA
8 mA
2 mA
4 mA
Altera Corporation
Arria GX Device Handbook, Volume 1
4–64
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–68. EP1AGX60 Row Pins Output Timing Parameters (Part 2 of 2)
Fast Model
Drive
Strength
Clock
SSTL-2
CLASS I
8 mA
GCLK
SSTL-2
CLASS I
12 mA
SSTL-2
CLASS II
16 mA
SSTL-18
CLASS I
4 mA
SSTL-18
CLASS I
6 mA
SSTL-18
CLASS I
8 mA
SSTL-18
CLASS I
10 mA
1.8-V HSTL
CLASS I
4 mA
1.8-V HSTL
CLASS I
6 mA
1.8-V HSTL
CLASS I
8 mA
1.8-V HSTL
CLASS I
10 mA
1.8-V HSTL
CLASS I
12 mA
1.5-V HSTL
CLASS I
4 mA
1.5-V HSTL
CLASS I
6 mA
1.5-V HSTL
CLASS I
8 mA
I/O Standard
LVDS
—
Arria GX Device Handbook, Volume 1
Industrial
Commercial
–6 Speed
Grade
tCO
2.774
2.774
6.057
ns
GCLK PLL
tCO
1.211
1.211
2.633
ns
GCLK
tCO
2.750
2.750
5.981
ns
GCLK PLL
tCO
1.187
1.187
2.557
ns
GCLK
tCO
2.716
2.716
5.850
ns
GCLK PLL
tCO
1.153
1.153
2.426
ns
GCLK
tCO
2.776
2.776
6.025
ns
GCLK PLL
tCO
1.204
1.204
2.582
ns
GCLK
tCO
2.780
2.780
5.954
ns
GCLK PLL
tCO
1.208
1.208
2.511
ns
GCLK
tCO
2.756
2.756
5.937
ns
GCLK PLL
tCO
1.184
1.184
2.494
ns
GCLK
tCO
2.759
2.759
5.916
ns
GCLK PLL
tCO
1.187
1.187
2.473
ns
GCLK
tCO
2.757
2.757
5.935
ns
GCLK PLL
tCO
1.185
1.185
2.492
ns
GCLK
tCO
2.760
2.760
5.899
ns
GCLK PLL
tCO
1.188
1.188
2.456
ns
GCLK
tCO
2.742
2.742
5.895
ns
GCLK PLL
tCO
1.170
1.170
2.452
ns
GCLK
tCO
2.746
2.746
5.884
ns
GCLK PLL
tCO
1.174
1.174
2.441
ns
GCLK
tCO
2.737
2.737
5.883
ns
GCLK PLL
tCO
1.165
1.165
2.440
ns
GCLK
tCO
2.756
2.756
5.912
ns
GCLK PLL
tCO
1.184
1.184
2.469
ns
GCLK
tCO
2.759
2.759
5.898
ns
GCLK PLL
tCO
1.187
1.187
2.455
ns
GCLK
tCO
2.744
2.744
5.890
ns
GCLK PLL
tCO
1.172
1.172
2.447
ns
GCLK
tCO
2.787
2.787
6.037
ns
GCLK PLL
tCO
1.228
1.228
2.618
ns
Parameter
© December 2009
Units
Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–65
Table 4–69 lists I/O timing specifications.
Table 4–69. EP1AGX60 Column Pins Output Timing Parameters (Part 1 of 4)
I/O Standard
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
Clock
4 mA
GCLK
3.036
3.036
6.963
ns
GCLK PLL
tCO
1.466
1.466
3.528
ns
GCLK
tCO
2.891
2.891
6.591
ns
GCLK PLL
tCO
1.321
1.321
3.156
ns
GCLK
tCO
2.824
2.824
6.591
ns
GCLK PLL
tCO
1.254
1.254
3.156
ns
GCLK
tCO
2.798
2.798
6.422
ns
GCLK PLL
tCO
1.228
1.228
2.987
ns
GCLK
tCO
2.776
2.776
6.297
ns
GCLK PLL
tCO
1.206
1.206
2.862
ns
GCLK
tCO
2.769
2.769
6.299
ns
GCLK PLL
tCO
1.199
1.199
2.864
ns
GCLK
tCO
2.891
2.891
6.591
ns
GCLK PLL
tCO
1.321
1.321
3.156
ns
GCLK
tCO
2.799
2.799
6.296
ns
GCLK PLL
tCO
1.229
1.229
2.861
ns
GCLK
tCO
2.771
2.771
6.218
ns
GCLK PLL
tCO
1.201
1.201
2.783
ns
GCLK
tCO
2.778
2.778
6.186
ns
GCLK PLL
tCO
1.208
1.208
2.751
ns
GCLK
tCO
2.765
2.765
6.168
ns
GCLK PLL
tCO
1.195
1.195
2.733
ns
GCLK
tCO
2.754
2.754
6.146
ns
GCLK PLL
tCO
1.184
1.184
2.711
ns
GCLK
tCO
2.853
2.853
6.623
ns
GCLK PLL
tCO
1.283
1.283
3.188
ns
GCLK
tCO
2.801
2.801
6.361
ns
GCLK PLL
tCO
1.231
1.231
2.926
ns
GCLK
tCO
2.780
2.780
6.244
ns
GCLK PLL
tCO
1.210
1.210
2.809
ns
GCLK
tCO
2.762
2.762
6.170
ns
GCLK PLL
tCO
1.192
1.192
2.735
ns
GCLK
tCO
2.893
2.893
7.615
ns
GCLK PLL
tCO
1.323
1.323
4.180
ns
GCLK
tCO
2.898
2.898
6.841
ns
GCLK PLL
tCO
1.328
1.328
3.406
ns
20 mA
24 mA
8 mA
3.3-V
LVCMOS
12 mA
3.3-V
LVCMOS
16 mA
3.3-V
LVCMOS
20 mA
3.3-V
LVCMOS
24 mA
2.5 V
4 mA
2.5 V
8 mA
2.5 V
12 mA
© December 2009
tCO
16 mA
3.3-V
LVCMOS
1.8 V
Commercial
12 mA
3.3-V
LVCMOS
1.8 V
Industrial
–6 Speed
Grade
8 mA
4 mA
2.5 V
Fast Corner
Drive
Strength
16 mA
2 mA
4 mA
Altera Corporation
Parameter
Units
Arria GX Device Handbook, Volume 1
4–66
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–69. EP1AGX60 Column Pins Output Timing Parameters (Part 2 of 4)
I/O Standard
1.8 V
1.8 V
1.8 V
1.8 V
1.5 V
1.5 V
1.5 V
1.5 V
Fast Corner
Drive
Strength
Clock
6 mA
GCLK
8 mA
10 mA
12 mA
2 mA
4 mA
6 mA
8 mA
SSTL-2
CLASS I
8 mA
SSTL-2
CLASS I
12 mA
SSTL-2
CLASS II
16 mA
SSTL-2
CLASS II
20 mA
SSTL-2
CLASS II
24 mA
SSTL-18
CLASS I
4 mA
SSTL-18
CLASS I
6 mA
SSTL-18
CLASS I
8 mA
SSTL-18
CLASS I
10 mA
SSTL-18
CLASS I
12 mA
SSTL-18
CLASS II
8 mA
Arria GX Device Handbook, Volume 1
Industrial
Commercial
–6 Speed
Grade
tCO
2.822
2.822
6.577
ns
GCLK PLL
tCO
1.252
1.252
3.142
ns
Parameter
Units
GCLK
tCO
2.824
2.824
6.486
ns
GCLK PLL
tCO
1.254
1.254
3.051
ns
GCLK
tCO
2.778
2.778
6.409
ns
GCLK PLL
tCO
1.208
1.208
2.974
ns
GCLK
tCO
2.779
2.779
6.352
ns
GCLK PLL
tCO
1.209
1.209
2.917
ns
GCLK
tCO
2.873
2.873
7.145
ns
GCLK PLL
tCO
1.303
1.303
3.710
ns
GCLK
tCO
2.809
2.809
6.576
ns
GCLK PLL
tCO
1.239
1.239
3.141
ns
GCLK
tCO
2.812
2.812
6.458
ns
GCLK PLL
tCO
1.242
1.242
3.023
ns
GCLK
tCO
2.771
2.771
6.405
ns
GCLK PLL
tCO
1.201
1.201
2.970
ns
GCLK
tCO
2.757
2.757
6.184
ns
GCLK PLL
tCO
1.184
1.184
2.744
ns
GCLK
tCO
2.740
2.740
6.134
ns
GCLK PLL
tCO
1.167
1.167
2.694
ns
GCLK
tCO
2.718
2.718
6.061
ns
GCLK PLL
tCO
1.145
1.145
2.621
ns
GCLK
tCO
2.719
2.719
6.048
ns
GCLK PLL
tCO
1.146
1.146
2.608
ns
GCLK
tCO
2.715
2.715
6.046
ns
GCLK PLL
tCO
1.142
1.142
2.606
ns
GCLK
tCO
2.753
2.753
6.155
ns
GCLK PLL
tCO
1.183
1.183
2.720
ns
GCLK
tCO
2.758
2.758
6.116
ns
GCLK PLL
tCO
1.185
1.185
2.676
ns
GCLK
tCO
2.737
2.737
6.097
ns
GCLK PLL
tCO
1.164
1.164
2.657
ns
GCLK
tCO
2.742
2.742
6.095
ns
GCLK PLL
tCO
1.169
1.169
2.655
ns
GCLK
tCO
2.736
2.736
6.081
ns
GCLK PLL
tCO
1.163
1.163
2.641
ns
GCLK
tCO
2.725
2.725
6.047
ns
GCLK PLL
tCO
1.152
1.152
2.607
ns
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–67
Table 4–69. EP1AGX60 Column Pins Output Timing Parameters (Part 3 of 4)
Fast Corner
Drive
Strength
Clock
SSTL-18
CLASS II
16 mA
GCLK
SSTL-18
CLASS II
18 mA
SSTL-18
CLASS II
20 mA
1.8-V HSTL
CLASS I
4 mA
1.8-V HSTL
CLASS I
6 mA
1.8-V HSTL
CLASS I
8 mA
1.8-V HSTL
CLASS I
10 mA
1.8-V HSTL
CLASS I
12 mA
1.8-V HSTL
CLASS II
16 mA
1.8-V HSTL
CLASS II
18 mA
1.8-V HSTL
CLASS II
20 mA
1.5-V HSTL
CLASS I
4 mA
1.5-V HSTL
CLASS I
6 mA
1.5-V HSTL
CLASS I
8 mA
1.5-V HSTL
CLASS I
10 mA
1.5-V HSTL
CLASS I
12 mA
1.5-V HSTL
CLASS II
16 mA
1.5-V HSTL
CLASS II
18 mA
1.5-V HSTL
CLASS II
20 mA
I/O Standard
© December 2009
Industrial
Commercial
–6 Speed
Grade
tCO
2.737
2.737
6.025
ns
GCLK PLL
tCO
1.164
1.164
2.585
ns
GCLK
tCO
2.733
2.733
6.033
ns
GCLK PLL
tCO
1.160
1.160
2.593
ns
GCLK
tCO
2.733
2.733
6.031
ns
GCLK PLL
tCO
1.160
1.160
2.591
ns
GCLK
tCO
2.756
2.756
6.086
ns
GCLK PLL
tCO
1.186
1.186
2.651
ns
GCLK
tCO
2.762
2.762
6.071
ns
GCLK PLL
tCO
1.189
1.189
2.631
ns
GCLK
tCO
2.740
2.740
6.060
ns
GCLK PLL
tCO
1.167
1.167
2.620
ns
GCLK
tCO
2.744
2.744
6.066
ns
GCLK PLL
tCO
1.171
1.171
2.626
ns
GCLK
tCO
2.736
2.736
6.059
ns
GCLK PLL
tCO
1.163
1.163
2.619
ns
GCLK
tCO
2.719
2.719
5.823
ns
GCLK PLL
tCO
1.146
1.146
2.383
ns
GCLK
tCO
2.721
2.721
5.834
ns
GCLK PLL
tCO
1.148
1.148
2.394
ns
GCLK
tCO
2.721
2.721
5.843
ns
GCLK PLL
tCO
1.148
1.148
2.403
ns
GCLK
tCO
2.756
2.756
6.085
ns
GCLK PLL
tCO
1.186
1.186
2.650
ns
GCLK
tCO
2.761
2.761
6.063
ns
GCLK PLL
tCO
1.188
1.188
2.623
ns
GCLK
tCO
2.743
2.743
6.065
ns
GCLK PLL
tCO
1.170
1.170
2.625
ns
GCLK
tCO
2.743
2.743
6.067
ns
GCLK PLL
tCO
1.170
1.170
2.627
ns
GCLK
tCO
2.737
2.737
6.065
ns
GCLK PLL
tCO
1.164
1.164
2.625
ns
GCLK
tCO
2.724
2.724
5.877
ns
GCLK PLL
tCO
1.151
1.151
2.437
ns
GCLK
tCO
2.727
2.727
5.887
ns
GCLK PLL
tCO
1.154
1.154
2.447
ns
GCLK
tCO
2.729
2.729
5.900
ns
GCLK PLL
tCO
1.156
1.156
2.460
ns
Altera Corporation
Parameter
Units
Arria GX Device Handbook, Volume 1
4–68
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–69. EP1AGX60 Column Pins Output Timing Parameters (Part 4 of 4)
I/O Standard
3.3-V PCI
3.3-V PCI-X
LVDS
Fast Corner
Drive
Strength
Clock
—
GCLK
—
—
Industrial
Commercial
–6 Speed
Grade
tCO
2.882
2.882
6.213
ns
GCLK PLL
tCO
1.312
1.312
2.778
ns
Parameter
Units
GCLK
tCO
2.882
2.882
6.213
ns
GCLK PLL
tCO
1.312
1.312
2.778
ns
GCLK
tCO
3.746
3.746
7.396
ns
GCLK PLL
tCO
2.185
2.185
3.973
ns
Table 4–70 through Table 4–71 list EP1AGX60 regional clock (RCLK) adder values that
should be added to the GCLK values. These adder values are used to determine I/O
timing when the I/O pin is driven using the regional clock. This applies for all I/O
standards supported by Arria GX with general purpose I/O pins.
Table 4–70 describes row pin delay adders when using the regional clock in Arria GX
devices.
Table 4–70. EP1AGX60 Row Pin Delay Adders for Regional Clock
Fast Corner
Parameter
–6 Speed Grade
Units
0.138
0.311
ns
–0.003
–0.003
–0.006
ns
RCLK output adder
–0.138
–0.138
–0.311
ns
RCLK PLL output adder
0.003
0.003
0.006
ns
Industrial
Commercial
RCLK input adder
0.138
RCLK PLL input adder
Table 4–71 lists column pin delay adders when using the regional clock in Arria GX
devices.
Table 4–71. EP1AGX60 Column Pin Delay Adders for Regional Clock
Fast Corner
Parameter
–6 Speed Grade
Units
0.153
0.344
ns
–1.066
–1.066
–2.338
ns
RCLK output adder
–0.153
–0.153
–0.343
ns
RCLK PLL output adder
1.721
1.721
4.486
ns
Industrial
Commercial
RCLK input adder
0.153
RCLK PLL input adder
EP1AGX90 I/O Timing Parameters
Table 4–72 through Table 4–75 list the maximum I/O timing parameters for
EP1AGX90 devices for I/O standards which support general purpose I/O pins.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–69
Table 4–72 lists I/O timing specifications.
Table 4–72. EP1AGX90 Row Pins Input Timing Parameters (Part 1 of 2)
Fast Model
I/O Standard
Industrial
Commercial
–6 Speed
Grade
t SU
1.295
1.295
2.873
ns
tH
–1.190
–1.190
–2.596
ns
GCLK PLL
t SU
3.366
3.366
7.017
ns
tH
–3.261
–3.261
–6.740
ns
GCLK
t SU
1.295
1.295
2.873
ns
tH
–1.190
–1.190
–2.596
ns
t SU
3.366
3.366
7.017
ns
tH
–3.261
–3.261
–6.740
ns
t SU
1.307
1.307
2.854
ns
tH
–1.202
–1.202
–2.577
ns
t SU
3.378
3.378
6.998
ns
Clock
GCLK
3.3-V LVTTL
3.3-V LVCMOS
GCLK PLL
GCLK
2.5 V
GCLK PLL
GCLK
1.8 V
GCLK PLL
GCLK
1.5 V
GCLK PLL
GCLK
SSTL-2 CLASS I
GCLK PLL
GCLK
SSTL-2 CLASS II
GCLK PLL
GCLK
SSTL-18 CLASS I
GCLK PLL
GCLK
SSTL-18 CLASS II
GCLK PLL
© December 2009
Altera Corporation
Parameter
Units
tH
–3.273
–3.273
–6.721
ns
t SU
1.381
1.381
3.073
ns
tH
–1.276
–1.276
–2.796
ns
t SU
3.434
3.434
7.191
ns
tH
–3.329
–3.329
–6.914
ns
t SU
1.384
1.384
3.168
ns
tH
–1.279
–1.279
–2.891
ns
t SU
3.437
3.437
7.286
ns
tH
–3.332
–3.332
–7.009
ns
t SU
1.121
1.121
2.329
ns
tH
–1.016
–1.016
–2.052
ns
t SU
3.187
3.187
6.466
ns
tH
–3.082
–3.082
–6.189
ns
t SU
1.121
1.121
2.329
ns
tH
–1.016
–1.016
–2.052
ns
t SU
3.187
3.187
6.466
ns
tH
–3.082
–3.082
–6.189
ns
t SU
1.159
1.159
2.447
ns
tH
–1.054
–1.054
–2.170
ns
t SU
3.212
3.212
6.565
ns
tH
–3.107
–3.107
–6.288
ns
t SU
1.157
1.157
2.441
ns
tH
–1.052
–1.052
–2.164
ns
t SU
3.235
3.235
6.597
ns
tH
–3.130
–3.130
–6.320
ns
Arria GX Device Handbook, Volume 1
4–70
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–72. EP1AGX90 Row Pins Input Timing Parameters (Part 2 of 2)
Fast Model
I/O Standard
Clock
GCLK
1.8-V HSTL CLASS I
GCLK PLL
GCLK
1.8-V HSTL CLASS II
GCLK PLL
GCLK
1.5-V HSTL CLASS I
GCLK PLL
GCLK
1.5-V HSTL CLASS II
GCLK PLL
GCLK
LVDS
GCLK PLL
Industrial
Commercial
–6 Speed
Grade
t SU
1.159
1.159
2.447
ns
tH
–1.054
–1.054
–2.170
ns
Parameter
Units
t SU
3.212
3.212
6.565
ns
tH
–3.107
–3.107
–6.288
ns
t SU
1.157
1.157
2.441
ns
tH
–1.052
–1.052
–2.164
ns
t SU
3.235
3.235
6.597
ns
tH
–3.130
–3.130
–6.320
ns
t SU
1.185
1.185
2.575
ns
tH
–1.080
–1.080
–2.298
ns
t SU
3.238
3.238
6.693
ns
tH
–3.133
–3.133
–6.416
ns
t SU
1.183
1.183
2.569
ns
tH
–1.078
–1.078
–2.292
ns
t SU
3.261
3.261
6.725
ns
tH
–3.156
–3.156
–6.448
ns
t SU
1.098
1.098
2.439
ns
tH
–0.993
–0.993
–2.162
ns
t SU
3.160
3.160
6.566
ns
tH
–3.055
–3.055
–6.289
ns
–6 Speed
Grade
Units
Table 4–73 lists I/O timing specifications.
\
Table 4–73. EP1AGX90 Column Pins Input Timing Parameters (Part 1 of 3)
Fast Corner
I/O Standard
Clock
Parameter
Industrial
Commercial
t SU
1.018
1.018
2.290
ns
tH
–0.913
–0.913
–2.013
ns
t SU
3.082
3.082
6.425
ns
tH
–2.977
–2.977
–6.148
ns
t SU
1.018
1.018
2.290
ns
tH
–0.913
–0.913
–2.013
ns
GCLK PLL
t SU
3.082
3.082
6.425
ns
tH
–2.977
–2.977
–6.148
ns
GCLK
t SU
1.028
1.028
2.272
ns
tH
–0.923
–0.923
–1.995
ns
t SU
3.092
3.092
6.407
ns
tH
–2.987
–2.987
–6.130
ns
GCLK
3.3-V LVTTL
GCLK PLL
GCLK
3.3-V LVCMOS
2.5 V
GCLK PLL
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–71
Table 4–73. EP1AGX90 Column Pins Input Timing Parameters (Part 2 of 3)
Fast Corner
I/O Standard
Clock
GCLK
1.8 V
GCLK PLL
GCLK
1.5 V
GCLK PLL
GCLK
SSTL-2 CLASS I
GCLK PLL
GCLK
SSTL-2 CLASS II
GCLK PLL
GCLK
SSTL-18 CLASS I
GCLK PLL
GCLK
SSTL-18 CLASS II
GCLK PLL
GCLK
1.8-V HSTL CLASS I
GCLK PLL
GCLK
1.8-V HSTL CLASS II
GCLK PLL
GCLK
1.5-V HSTL CLASS I
GCLK PLL
© December 2009
Altera Corporation
Industrial
Commercial
–6 Speed
Grade
t SU
1.094
1.094
2.482
ns
tH
–0.989
–0.989
–2.205
ns
Parameter
Units
t SU
3.158
3.158
6.617
ns
tH
–3.053
–3.053
–6.340
ns
t SU
1.097
1.097
2.575
ns
tH
–0.992
–0.992
–2.298
ns
t SU
3.161
3.161
6.710
ns
tH
–3.056
–3.056
–6.433
ns
t SU
0.844
0.844
1.751
ns
tH
–0.739
–0.739
–1.474
ns
t SU
2.908
2.908
5.886
ns
tH
–2.803
–2.803
–5.609
ns
t SU
0.844
0.844
1.751
ns
tH
–0.739
–0.739
–1.474
ns
t SU
2.908
2.908
5.886
ns
tH
–2.803
–2.803
–5.609
ns
t SU
0.880
0.880
1.854
ns
tH
–0.775
–0.775
–1.577
ns
t SU
2.944
2.944
5.989
ns
tH
–2.839
–2.839
–5.712
ns
t SU
0.883
0.883
1.858
ns
tH
–0.778
–0.778
–1.581
ns
t SU
2.947
2.947
5.993
ns
tH
–2.842
–2.842
–5.716
ns
t SU
0.880
0.880
1.854
ns
tH
–0.775
–0.775
–1.577
ns
t SU
2.944
2.944
5.989
ns
tH
–2.839
–2.839
–5.712
ns
t SU
0.883
0.883
1.858
ns
tH
–0.778
–0.778
–1.581
ns
t SU
2.947
2.947
5.993
ns
tH
–2.842
–2.842
–5.716
ns
t SU
0.898
0.898
1.982
ns
tH
–0.793
–0.793
–1.705
ns
t SU
2.962
2.962
6.117
ns
tH
–2.857
–2.857
–5.840
ns
Arria GX Device Handbook, Volume 1
4–72
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–73. EP1AGX90 Column Pins Input Timing Parameters (Part 3 of 3)
Fast Corner
I/O Standard
Clock
Industrial
Commercial
–6 Speed
Grade
t SU
0.901
0.901
1.986
ns
tH
–0.796
–0.796
–1.709
ns
Parameter
GCLK
1.5-V HSTL CLASS II
GCLK PLL
GCLK
3.3-V PCI
GCLK PLL
GCLK
3.3-V PCI-X
GCLK PLL
GCLK
LVDS
GCLK PLL
Units
t SU
2.965
2.965
6.121
ns
tH
–2.860
–2.860
–5.844
ns
t SU
1.023
1.023
2.278
ns
tH
–0.918
–0.918
–2.001
ns
t SU
3.087
3.087
6.413
ns
tH
–2.982
–2.982
–6.136
ns
t SU
1.023
1.023
2.278
ns
tH
–0.918
–0.918
–2.001
ns
t SU
3.087
3.087
6.413
ns
tH
–2.982
–2.982
–6.136
ns
t SU
0.891
0.891
1.920
ns
tH
–0.786
–0.786
–1.643
ns
t SU
2.963
2.963
6.066
ns
tH
–2.858
–2.858
–5.789
ns
Table 4–74 lists I/O timing specifications.
Table 4–74. EP1AGX90 Row Pins Output Timing Parameters (Part 1 of 3)
I/O Standard
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
Drive
Strength
4 mA
8 mA
12 mA
3.3-V
LVCMOS
4 mA
3.3-V
LVCMOS
8 mA
2.5 V
4 mA
2.5 V
2.5 V
8 mA
12 mA
Arria GX Device Handbook, Volume 1
Fast Model
Clock
Commercial
–6 Speed
Grade
Units
Industrial
Parameter
GCLK
tCO
3.170
3.170
7.382
ns
GCLK PLL
tCO
1.099
1.099
3.238
ns
GCLK
tCO
3.042
3.042
6.742
ns
GCLK PLL
tCO
0.971
0.971
2.598
ns
GCLK
tCO
2.986
2.986
6.705
ns
GCLK PLL
tCO
0.915
0.915
2.561
ns
GCLK
tCO
3.042
3.042
6.742
ns
GCLK PLL
tCO
0.971
0.971
2.598
ns
GCLK
tCO
2.936
2.936
6.436
ns
GCLK PLL
tCO
0.865
0.865
2.292
ns
GCLK
tCO
3.025
3.025
6.716
ns
GCLK PLL
tCO
0.954
0.954
2.572
ns
GCLK
tCO
2.922
2.922
6.458
ns
GCLK PLL
tCO
0.851
0.851
2.314
ns
GCLK
tCO
2.903
2.903
6.344
ns
GCLK PLL
tCO
0.832
0.832
2.200
ns
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–73
Table 4–74. EP1AGX90 Row Pins Output Timing Parameters (Part 2 of 3)
I/O Standard
1.8 V
1.8 V
1.8 V
1.8 V
1.5 V
1.5 V
Clock
2 mA
GCLK
Industrial
Commercial
–6 Speed
Grade
tCO
3.087
3.087
7.723
ns
GCLK PLL
tCO
1.034
1.034
3.605
ns
tCO
3.076
3.076
6.944
ns
tCO
1.023
1.023
2.826
ns
GCLK
tCO
2.965
2.965
6.643
ns
GCLK PLL
tCO
0.912
0.912
2.525
ns
GCLK
tCO
2.934
2.934
6.529
ns
GCLK PLL
tCO
0.881
0.881
2.411
ns
GCLK
tCO
3.047
3.047
7.222
ns
GCLK PLL
tCO
0.994
0.994
3.104
ns
8 mA
2 mA
GCLK
tCO
2.940
2.940
6.621
ns
GCLK PLL
tCO
0.887
0.887
2.503
ns
GCLK
tCO
2.890
2.890
6.294
ns
GCLK PLL
tCO
0.824
0.824
2.157
ns
GCLK
tCO
2.866
2.866
6.218
ns
GCLK PLL
tCO
0.800
0.800
2.081
ns
GCLK
tCO
2.832
2.832
6.087
ns
GCLK PLL
tCO
0.766
0.766
1.950
ns
4 mA
SSTL-2
CLASS I
12 mA
SSTL-2
CLASS II
16 mA
SSTL-18
CLASS I
4 mA
SSTL-18
CLASS I
6 mA
SSTL-18
CLASS I
8 mA
SSTL-18
CLASS I
10 mA
1.8-V HSTL
CLASS I
4 mA
1.8-V HSTL
CLASS I
6 mA
1.8-V HSTL
CLASS I
8 mA
1.8-V HSTL
CLASS I
10 mA
1.8-V HSTL
CLASS I
12 mA
1.5-V HSTL
CLASS I
4 mA
Units
GCLK
6 mA
8 mA
Parameter
GCLK PLL
4 mA
SSTL-2
CLASS I
© December 2009
Fast Model
Drive
Strength
GCLK
tCO
2.872
2.872
6.227
ns
GCLK PLL
tCO
0.819
0.819
2.109
ns
GCLK
tCO
2.878
2.878
6.162
ns
GCLK PLL
tCO
0.800
0.800
2.006
ns
GCLK
tCO
2.854
2.854
6.145
ns
GCLK PLL
tCO
0.776
0.776
1.989
ns
GCLK
tCO
2.857
2.857
6.124
ns
GCLK PLL
tCO
0.779
0.779
1.968
ns
GCLK
tCO
2.853
2.853
6.137
ns
GCLK PLL
tCO
0.800
0.800
2.019
ns
GCLK
tCO
2.858
2.858
6.107
ns
GCLK PLL
tCO
0.780
0.780
1.951
ns
GCLK
tCO
2.840
2.840
6.103
ns
GCLK PLL
tCO
0.762
0.762
1.947
ns
GCLK
tCO
2.844
2.844
6.092
ns
GCLK PLL
tCO
0.766
0.766
1.936
ns
GCLK
tCO
2.835
2.835
6.091
ns
GCLK PLL
tCO
0.757
0.757
1.935
ns
GCLK
tCO
2.852
2.852
6.114
ns
GCLK PLL
tCO
0.799
0.799
1.996
ns
Altera Corporation
Arria GX Device Handbook, Volume 1
4–74
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–74. EP1AGX90 Row Pins Output Timing Parameters (Part 3 of 3)
Fast Model
Drive
Strength
Clock
1.5-V HSTL
CLASS I
6 mA
GCLK
1.5-V HSTL
CLASS I
8 mA
I/O Standard
LVDS
—
Industrial
Commercial
–6 Speed
Grade
tCO
2.857
2.857
6.106
ns
GCLK PLL
tCO
0.779
0.779
1.950
ns
GCLK
tCO
2.842
2.842
6.098
ns
GCLK PLL
tCO
0.764
0.764
1.942
ns
GCLK
tCO
2.898
2.898
6.265
ns
GCLK PLL
tCO
0.831
0.831
2.129
ns
Units
Parameter
Units
Table 4–75 lists I/O timing specifications.
Table 4–75. EP1AGX90 Column Pins Output Timing Parameters (Part 1 of 4)
I/O Standard
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
3.3-V LVTTL
Fast Corner
Drive
Strength
Clock
4 mA
GCLK
8 mA
12 mA
16 mA
20 mA
24 mA
3.3-V
LVCMOS
4 mA
3.3-V
LVCMOS
8 mA
3.3-V
LVCMOS
12 mA
3.3-V
LVCMOS
16 mA
3.3-V
LVCMOS
20 mA
3.3-V
LVCMOS
24 mA
2.5 V
4 mA
Arria GX Device Handbook, Volume 1
Industrial
Commercial
–6 Speed
Grade
tCO
3.141
3.141
7.164
ns
GCLK PLL
tCO
1.077
1.077
3.029
ns
Parameter
GCLK
tCO
2.996
2.996
6.792
ns
GCLK PLL
tCO
0.932
0.932
2.657
ns
GCLK
tCO
2.929
2.929
6.792
ns
GCLK PLL
tCO
0.865
0.865
2.657
ns
GCLK
tCO
2.903
2.903
6.623
ns
GCLK PLL
tCO
0.839
0.839
2.488
ns
GCLK
tCO
2.881
2.881
6.498
ns
GCLK PLL
tCO
0.817
0.817
2.363
ns
GCLK
tCO
2.874
2.874
6.500
ns
GCLK PLL
tCO
0.810
0.810
2.365
ns
GCLK
tCO
2.996
2.996
6.792
ns
GCLK PLL
tCO
0.932
0.932
2.657
ns
GCLK
tCO
2.904
2.904
6.497
ns
GCLK PLL
tCO
0.840
0.840
2.362
ns
GCLK
tCO
2.876
2.876
6.419
ns
GCLK PLL
tCO
0.812
0.812
2.284
ns
GCLK
tCO
2.883
2.883
6.387
ns
GCLK PLL
tCO
0.819
0.819
2.252
ns
GCLK
tCO
2.870
2.870
6.369
ns
GCLK PLL
tCO
0.806
0.806
2.234
ns
GCLK
tCO
2.859
2.859
6.347
ns
GCLK PLL
tCO
0.795
0.795
2.212
ns
GCLK
tCO
2.958
2.958
6.824
ns
GCLK PLL
tCO
0.894
0.894
2.689
ns
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–75
Table 4–75. EP1AGX90 Column Pins Output Timing Parameters (Part 2 of 4)
I/O Standard
2.5 V
2.5 V
2.5 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.8 V
1.5 V
1.5 V
1.5 V
1.5 V
Clock
8 mA
GCLK
Industrial
Commercial
–6 Speed
Grade
tCO
2.906
2.906
6.562
ns
GCLK PLL
tCO
0.842
0.842
2.427
ns
tCO
2.885
2.885
6.445
ns
tCO
0.821
0.821
2.310
ns
GCLK
tCO
2.867
2.867
6.371
ns
GCLK PLL
tCO
0.803
0.803
2.236
ns
GCLK
tCO
2.998
2.998
7.816
ns
GCLK PLL
tCO
0.934
0.934
3.681
ns
GCLK
tCO
3.003
3.003
7.042
ns
GCLK PLL
tCO
0.939
0.939
2.907
ns
2 mA
4 mA
GCLK
tCO
2.927
2.927
6.778
ns
GCLK PLL
tCO
0.863
0.863
2.643
ns
GCLK
tCO
2.929
2.929
6.687
ns
GCLK PLL
tCO
0.865
0.865
2.552
ns
GCLK
tCO
2.883
2.883
6.610
ns
GCLK PLL
tCO
0.819
0.819
2.475
ns
GCLK
tCO
2.884
2.884
6.553
ns
GCLK PLL
tCO
0.820
0.820
2.418
ns
6 mA
8 mA
10 mA
12 mA
GCLK
tCO
2.978
2.978
7.346
ns
GCLK PLL
tCO
0.914
0.914
3.211
ns
GCLK
tCO
2.914
2.914
6.777
ns
GCLK PLL
tCO
0.850
0.850
2.642
ns
GCLK
tCO
2.917
2.917
6.659
ns
GCLK PLL
tCO
0.853
0.853
2.524
ns
GCLK
tCO
2.876
2.876
6.606
ns
GCLK PLL
tCO
0.812
0.812
2.471
ns
2 mA
4 mA
6 mA
8 mA
SSTL-2
CLASS I
12 mA
SSTL-2
CLASS II
16 mA
SSTL-2
CLASS II
20 mA
SSTL-2
CLASS II
24 mA
SSTL-18
CLASS I
4 mA
Units
GCLK
16 mA
8 mA
Parameter
GCLK PLL
12 mA
SSTL-2
CLASS I
© December 2009
Fast Corner
Drive
Strength
GCLK
tCO
2.859
2.859
6.381
ns
GCLK PLL
tCO
0.797
0.797
2.250
ns
GCLK
tCO
2.842
2.842
6.331
ns
GCLK PLL
tCO
0.780
0.780
2.200
ns
GCLK
tCO
2.820
2.820
6.258
ns
GCLK PLL
tCO
0.758
0.758
2.127
ns
GCLK
tCO
2.821
2.821
6.245
ns
GCLK PLL
tCO
0.759
0.759
2.114
ns
GCLK
tCO
2.817
2.817
6.243
ns
GCLK PLL
tCO
0.755
0.755
2.112
ns
GCLK
tCO
2.858
2.858
6.356
ns
GCLK PLL
tCO
0.794
0.794
2.221
ns
Altera Corporation
Arria GX Device Handbook, Volume 1
4–76
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–75. EP1AGX90 Column Pins Output Timing Parameters (Part 3 of 4)
Fast Corner
Drive
Strength
Clock
SSTL-18
CLASS I
6 mA
GCLK
SSTL-18
CLASS I
8 mA
SSTL-18
CLASS I
10 mA
SSTL-18
CLASS I
12 mA
SSTL-18
CLASS II
8 mA
SSTL-18
CLASS II
16 mA
SSTL-18
CLASS II
18 mA
SSTL-18
CLASS II
20 mA
1.8-V HSTL
CLASS I
4 mA
1.8-V HSTL
CLASS I
6 mA
1.8-V HSTL
CLASS I
8 mA
1.8-V HSTL
CLASS I
10 mA
1.8-V HSTL
CLASS I
12 mA
1.8-V HSTL
CLASS II
16 mA
1.8-V HSTL
CLASS II
18 mA
1.8-V HSTL
CLASS II
20 mA
1.5-V HSTL
CLASS I
4 mA
1.5-V HSTL
CLASS I
6 mA
1.5-V HSTL
CLASS I
8 mA
I/O Standard
Arria GX Device Handbook, Volume 1
Industrial
Commercial
–6 Speed
Grade
tCO
2.860
2.860
6.313
ns
GCLK PLL
tCO
0.798
0.798
2.182
ns
Parameter
Units
GCLK
tCO
2.839
2.839
6.294
ns
GCLK PLL
tCO
0.777
0.777
2.163
ns
GCLK
tCO
2.844
2.844
6.292
ns
GCLK PLL
tCO
0.782
0.782
2.161
ns
GCLK
tCO
2.838
2.838
6.278
ns
GCLK PLL
tCO
0.776
0.776
2.147
ns
GCLK
tCO
2.827
2.827
6.244
ns
GCLK PLL
tCO
0.765
0.765
2.113
ns
GCLK
tCO
2.839
2.839
6.222
ns
GCLK PLL
tCO
0.777
0.777
2.091
ns
GCLK
tCO
2.835
2.835
6.230
ns
GCLK PLL
tCO
0.773
0.773
2.099
ns
GCLK
tCO
2.835
2.835
6.228
ns
GCLK PLL
tCO
0.773
0.773
2.097
ns
GCLK
tCO
2.861
2.861
6.287
ns
GCLK PLL
tCO
0.797
0.797
2.152
ns
GCLK
tCO
2.864
2.864
6.268
ns
GCLK PLL
tCO
0.802
0.802
2.137
ns
GCLK
tCO
2.842
2.842
6.257
ns
GCLK PLL
tCO
0.780
0.780
2.126
ns
GCLK
tCO
2.846
2.846
6.263
ns
GCLK PLL
tCO
0.784
0.784
2.132
ns
GCLK
tCO
2.838
2.838
6.256
ns
GCLK PLL
tCO
0.776
0.776
2.125
ns
GCLK
tCO
2.821
2.821
6.020
ns
GCLK PLL
tCO
0.759
0.759
1.889
ns
GCLK
tCO
2.823
2.823
6.031
ns
GCLK PLL
tCO
0.761
0.761
1.900
ns
GCLK
tCO
2.823
2.823
6.040
ns
GCLK PLL
tCO
0.761
0.761
1.909
ns
GCLK
tCO
2.861
2.861
6.286
ns
GCLK PLL
tCO
0.797
0.797
2.151
ns
GCLK
tCO
2.863
2.863
6.260
ns
GCLK PLL
tCO
0.801
0.801
2.129
ns
GCLK
tCO
2.845
2.845
6.262
ns
GCLK PLL
tCO
0.783
0.783
2.131
ns
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–77
Table 4–75. EP1AGX90 Column Pins Output Timing Parameters (Part 4 of 4)
Fast Corner
Drive
Strength
Clock
1.5-V HSTL
CLASS I
10 mA
GCLK
1.5-V HSTL
CLASS I
12 mA
1.5-V HSTL
CLASS II
16 mA
1.5-V HSTL
CLASS II
18 mA
1.5-V HSTL
CLASS II
20 mA
I/O Standard
3.3-V PCI
3.3-V PCI-X
LVDS
Industrial
Commercial
–6 Speed
Grade
tCO
2.845
2.845
6.264
ns
GCLK PLL
tCO
0.783
0.783
2.133
ns
Parameter
Units
GCLK
tCO
2.839
2.839
6.262
ns
GCLK PLL
tCO
0.777
0.777
2.131
ns
GCLK
tCO
2.826
2.826
6.074
ns
GCLK PLL
tCO
0.764
0.764
1.943
ns
GCLK
tCO
2.829
2.829
6.084
ns
GCLK PLL
tCO
0.767
0.767
1.953
ns
GCLK
tCO
2.831
2.831
6.097
ns
GCLK PLL
tCO
0.769
0.769
1.966
ns
GCLK
tCO
2.987
2.987
6.414
ns
GCLK PLL
tCO
0.923
0.923
2.279
ns
GCLK
tCO
2.987
2.987
6.414
ns
GCLK PLL
tCO
0.923
0.923
2.279
ns
GCLK
tCO
3.835
3.835
7.541
ns
GCLK PLL
tCO
1.769
1.769
3.404
ns
—
—
—
Table 4–76 through Table 4–77 list the EP1AGX90 regional clock (RCLK) adder values
that should be added to the GCLK values. These adder values are used to determine
I/O timing when the I/O pin is driven using the regional clock. This applies for all
I/O standards supported by Arria GX with general purpose I/O pins.
Table 4–76 lists row pin delay adders when using the regional clock in Arria GX
devices.
Table 4–76. EP1AGX90 Row Pin Delay Adders for Regional Clock
Fast Corner
Parameter
© December 2009
–6 Speed Grade
Units
0.175
0.418
ns
0.007
0.007
0.015
ns
RCLK output adder
–0.175
–0.175
–0.418
ns
RCLK PLL output adder
–0.007
–0.007
–0.015
ns
Industrial
Commercial
RCLK input adder
0.175
RCLK PLL input adder
Altera Corporation
Arria GX Device Handbook, Volume 1
4–78
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–77 lists column pin delay adders when using the regional clock in Arria GX
devices.
Table 4–77. EP1AGX90 Column Pin Delay Adders for Regional Clock
Fast Corner
Parameter
–6 Speed Grade
Units
0.138
0.354
ns
–1.697
–1.697
–3.607
ns
RCLK output adder
–0.138
–0.138
–0.353
ns
RCLK PLL output adder
1.966
1.966
5.188
ns
Industrial
Commercial
RCLK input adder
0.138
RCLK PLL input adder
Dedicated Clock Pin Timing
Table 4–79 through Table 4–98 list clock pin timing for Arria GX devices when the
clock is driven by the global clock, regional clock, periphery clock, and a PLL.
Table 4–78 lists Arria GX clock timing parameters.
Table 4–78. Arria GX Clock Timing Parameters
Symbol
Parameter
tCIN
Delay from clock pad to I/O input register
tCOUT
Delay from clock pad to I/O output register
tPLLCIN
Delay from PLL inclk pad to I/O input register
tPLLCOUT
Delay from PLL inclk pad to I/O output register
EP1AGX20 Clock Timing Parameters
Table 4–79 through Table 4–80 list the GCLK clock timing parameters for EP1AGX20
devices.
Table 4–79 lists clock timing specifications.
Table 4–79. EP1AGX20 Row Pins Global Clock Timing Parameters
Fast Model
Parameter
–6 Speed Grade
Units
1.394
3.161
ns
1.399
1.399
3.155
ns
tpllcin
–0.027
–0.027
0.091
ns
tpllcout
–0.022
–0.022
0.085
ns
Industrial
Commercial
tcin
1.394
tcout
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–79
Table 4–80 lists clock timing specifications.
Table 4–80. EP1AGX20 Row Pins Global Clock Timing Parameters
Fast Model
Parameter
–6 Speed Grade
Units
1.655
3.726
ns
1.655
1.655
3.726
ns
tPLLCIN
0.236
0.236
0.655
ns
tPLLCOUT
0.236
0.236
0.655
ns
Industrial
Commercial
tCIN
1.655
tCOUT
Table 4–81 through Table 4–82 list the RCLK clock timing parameters for EP1AGX20
devices.
Table 4–81 lists clock timing specifications.
Table 4–81. EP1AGX20 Row Pins Regional Clock Timing Parameters
Fast Model
Parameter
–6 Speed Grade
Units
1.283
2.901
ns
1.288
1.288
2.895
ns
tPLLCIN
–0.034
–0.034
0.077
ns
tPLLCOUT
–0.029
–0.029
0.071
ns
Industrial
Commercial
tCIN
1.283
tCOUT
Table 4–82 lists clock timing specifications.
Table 4–82. EP1AGX20 Row Pins Regional Clock Timing Parameters
Fast Model
Parameter
–6 Speed Grade
Units
1.569
3.487
ns
1.569
1.569
3.487
ns
tPLLCIN
0.278
0.278
0.706
ns
tPLLCOUT
0.278
0.278
0.706
ns
Industrial
Commercial
tCIN
1.569
tCOUT
EP1AGX35 Clock Timing Parameters
Table 4–83 through Table 4–84 list the GCLK clock timing parameters for EP1AGX35
devices.
Table 4–83 lists clock timing specifications.
Table 4–83. EP1AGX35 Row Pins Global Clock Timing Parameters (Part 1 of 2)
Fast Model
Parameter
© December 2009
–6 Speed Grade
Units
1.394
3.161
ns
1.399
3.155
ns
Industrial
Commercial
tCIN
1.394
tCOUT
1.399
Altera Corporation
Arria GX Device Handbook, Volume 1
4–80
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–83. EP1AGX35 Row Pins Global Clock Timing Parameters (Part 2 of 2)
Fast Model
Parameter
–6 Speed Grade
Units
–0.027
0.091
ns
–0.022
0.085
ns
–6 Speed Grade
Units
Industrial
Commercial
tPLLCIN
–0.027
tPLLCOUT
–0.022
Table 4–84 lists clock timing specifications.
Table 4–84. EP1AGX35 Row Pins Global Clock Timing Parameters
Fast Model
Parameter
Industrial
Commercial
tCIN
1.655
1.655
3.726
ns
tCOUT
1.655
1.655
3.726
ns
tPLLCIN
0.236
0.236
0.655
ns
tPLLCOUT
0.236
0.236
0.655
ns
Table 4–85 through Table 4–86 list the RCLK clock timing parameters for EP1AGX35
devices.
Table 4–85 lists clock timing specifications.
Table 4–85. EP1AGX35 Row Pins Regional Clock Timing Parameters
Fast Model
Parameter
–6 Speed Grade
Units
1.283
2.901
ns
1.288
1.288
2.895
ns
tPLLCIN
–0.034
–0.034
0.077
ns
tPLLCOUT
–0.029
–0.029
0.071
ns
Industrial
Commercial
tCIN
1.283
tCOUT
Table 4–86 lists clock timing specifications.
Table 4–86. EP1AGX35 Row Pins Regional Clock Timing Parameters
Fast Model
Parameter
–6 Speed Grade
Units
1.569
3.487
ns
1.569
3.487
ns
0.278
0.278
0.706
ns
0.278
0.278
0.706
ns
Industrial
Commercial
tCIN
1.569
tCOUT
1.569
tPLLCIN
tPLLCOUT
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–81
EP1AGX50 Clock Timing Parameters
Table 4–87 through Table 4–88 list the GCLK clock timing parameters for EP1AGX50
devices.
Table 4–87 lists clock timing specifications.
Table 4–87. EP1AGX50 Row Pins Global Clock Timing Parameters
Fast Model
Parameter
–6 Speed Grade
Units
1.529
3.587
ns
1.534
1.534
3.581
ns
tPLLCIN
–0.024
–0.024
0.181
ns
tPLLCOUT
–0.019
–0.019
0.175
ns
–6 Speed Grade
Units
Industrial
Commercial
tCIN
1.529
tCOUT
Table 4–88 lists clock timing specifications.
Table 4–88. EP1AGX50 Row Pins Global Clock Timing Parameters
Fast Model
Parameter
Industrial
Commercial
tCIN
1.793
1.793
4.165
ns
tCOUT
1.793
1.793
4.165
ns
tPLLCIN
0.238
0.238
0.758
ns
tPLLCOUT
0.238
0.238
0.758
ns
Table 4–89 through Table 4–90 list the RCLK clock timing parameters for EP1AGX50
devices.
Table 4–89 lists clock timing specifications.
Table 4–89. EP1AGX50 Row Pins Regional Clock Timing Parameters
Fast Model
Parameter
© December 2009
–6 Speed Grade
Units
1.396
3.287
ns
1.401
1.401
3.281
ns
tPLLCIN
–0.017
–0.017
0.195
ns
tPLLCOUT
–0.012
–0.012
0.189
ns
Industrial
Commercial
tCIN
1.396
tCOUT
Altera Corporation
Arria GX Device Handbook, Volume 1
4–82
Chapter 4: DC and Switching Characteristics
Typical Design Performance
Table 4–90 lists clock timing specifications.
Table 4–90. EP1AGX50 Row Pins Regional Clock Timing Parameters
Fast Model
Parameter
–6 Speed Grade
Units
1.653
3.841
ns
1.651
1.651
3.839
ns
tPLLCIN
0.245
0.245
0.755
ns
tPLLCOUT
0.245
0.245
0.755
ns
Industrial
Commercial
tCIN
1.653
tCOUT
EP1AGX60 Clock Timing Parameters
Table 4–91 to Table 4–92 on page 4–82 list the GCLK clock timing parameters for
EP1AGX60 devices.
Table 4–91 lists clock timing specifications.
Table 4–91. EP1AGX60 Row Pins Global Clock Timing Parameters
Fast Model
Parameter
–6 Speed Grade
Units
1.531
3.593
ns
1.536
1.536
3.587
ns
tPLLCIN
–0.023
–0.023
0.188
ns
tPLLCOUT
–0.018
–0.018
0.182
ns
–6 Speed Grade
Units
Industrial
Commercial
tCIN
1.531
tCOUT
Table 4–92 lists clock timing specifications.
Table 4–92. EP1AGX60 Row Pins Global Clock Timing Parameters
Fast Model
Parameter
Industrial
Commercial
tCIN
1.792
1.792
4.165
ns
tCOUT
1.792
1.792
4.165
ns
tPLLCIN
0.238
0.238
0.758
ns
tPLLCOUT
0.238
0.238
0.758
ns
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Typical Design Performance
4–83
Table 4–93 through Table 4–94 list the RCLK clock timing parameters for EP1AGX60
devices.
Table 4–93 lists clock timing specifications.
Table 4–93. EP1AGX60 Row Pins Regional Clock Timing Parameters
Fast Model
Parameter
tCIN
Industrial
Commercial
1.382
1.382
–6 Speed Grade
Units
3.268
ns
tCOUT
1.387
1.387
3.262
ns
tPLLCIN
–0.031
–0.031
0.174
ns
tPLLCOUT
–0.026
–0.026
0.168
ns
Table 4–94 lists clock timing specifications.
Table 4–94. EP1AGX60 Row Pins Regional Clock Timing Parameters
Fast Model
Parameter
–6 Speed Grade
Units
1.649
3.835
ns
1.651
1.651
3.839
ns
tPLLCIN
0.245
0.245
0.755
ns
tPLLCOUT
0.245
0.245
0.755
ns
Industrial
Commercial
tCIN
1.649
tCOUT
EP1AGX90 Clock Timing Parameters
Table 4–95 through Table 4–96 list the GCLK clock timing parameters for EP1AGX90
devices.
Table 4–95 lists clock timing specifications.
Table 4–95. EP1AGX90 Row Pins Global Clock Timing Parameters
Fast Model
Parameter
© December 2009
–6 Speed Grade
Units
1.630
3.799
ns
1.635
1.635
3.793
ns
tPLLCIN
–0.422
–0.422
–0.310
ns
tPLLCOUT
–0.417
–0.417
–0.316
ns
Industrial
Commercial
tCIN
1.630
tCOUT
Altera Corporation
Arria GX Device Handbook, Volume 1
4–84
Chapter 4: DC and Switching Characteristics
Block Performance
Table 4–96 lists clock timing specifications.
Table 4–96. EP1AGX90 Row Pins Global Clock Timing Parameters
Fast Model
Parameter
–6 Speed Grade
Units
1.904
4.376
ns
1.904
1.904
4.376
ns
tPLLCIN
–0.153
–0.153
0.254
ns
tPLLCOUT
–0.153
–0.153
0.254
ns
Industrial
Commercial
tCIN
1.904
tCOUT
Table 4–97 through Table 4–98 list the RCLK clock timing parameters for EP1AGX90
devices.
Table 4–97 lists clock timing specifications.
Table 4–97. EP1AGX90 Row Pins Regional Clock Timing Parameters
Fast Model
Parameter
–6 Speed Grade
Units
1.462
3.407
ns
1.467
1.467
3.401
ns
tPLLCIN
–0.430
–0.430
–0.322
ns
tPLLCOUT
–0.425
–0.425
–0.328
ns
Industrial
Commercial
tCIN
1.462
tCOUT
Table 4–98 lists clock timing specifications.
Table 4–98. EP1AGX90 Row Pins Regional Clock Timing Parameters
Fast Model
Parameter
–6 Speed Grade
Units
1.760
4.011
ns
1.760
1.760
4.011
ns
tPLLCIN
–0.118
–0.118
0.303
ns
tPLLCOUT
–0.118
–0.118
0.303
ns
Industrial
Commercial
tCIN
1.760
tCOUT
Block Performance
Table 4–99 shows the Arria GX performance for some common designs. All
performance values were obtained with the Quartus II software compilation of library
of parameterized modules (LPM) or MegaCore functions for finite impulse response
(FIR) and fast Fourier transform (FFT) designs.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Block Performance
4–85
Table 4–99 lists performance notes.
Table 4–99. Arria GX Performance Notes
Resources Used
Applications
LE
TriMatrix Memory
M512 block
TriMatrix Memory
M4K block
TriMatrix Memory
MegaRAM block
© December 2009
Performance
ALUTs
TriMatrix
Memory Blocks
DSP Blocks
–6 Speed Grade
16-to-1
multiplexer
5
0
0
168.41
32-to-1
multiplexer
11
0
0
334.11
16-bit counter
16
0
0
374.0
64-bit counter
64
0
0
168.41
Simple dual-port
RAM 32 x 18 bit
0
1
0
348.0
FIFO 32 x 18 bit
0
1
0
333.22
Simple dual-port
RAM 128 x 36 bit
0
1
0
344.71
True dual-port
RAM 128 x 18 bit
0
1
0
348.0
Single port RAM
4K x 144 bit
0
2
0
244.0
Simple dual-port
RAM 4K x 144 bit
0
1
0
292.0
True dual-port
RAM 4K x 144 bit
0
2
0
244.0
Single port RAM
8K x 72 bit
0
1
0
247.0
Simple dual-port
RAM 8K x 72 bit
0
1
0
292.0
Single port RAM
16K x 36 bit
0
1
0
254.0
Simple dual-port
RAM 16K x 36 bit
0
1
0
292.0
True dual-port
RAM 16K x 36 bit
0
1
0
251.0
Single port RAM
32K x 18 bit
0
1
0
317.36
Simple dual-port
RAM 32K x 18 bit
0
1
0
292.0
True dual-port
RAM 32K x 18 bit
0
1
0
251.0
Single port RAM
64K x 9 bit
0
1
0
254.0
Simple dual-port
RAM 64K x 9 bit
0
1
0
292.0
True dual-port
RAM 64K x 9 bit
0
1
0
251.0
Altera Corporation
Arria GX Device Handbook, Volume 1
4–86
Chapter 4: DC and Switching Characteristics
IOE Programmable Delay
Table 4–99. Arria GX Performance Notes
Resources Used
Applications
DSP block
Larger Designs
Performance
ALUTs
TriMatrix
Memory Blocks
DSP Blocks
–6 Speed Grade
9 x 9-bit
multiplier
0
0
1
335.35
18 x 18-bit
multiplier
0
0
2
285.0
18 x 18-bit
multiplier
0
0
4
335.35
36 x 36-bit
multiplier
0
0
8
174.4
36 x 36-bit
multiplier
0
0
8
285.0
18-bit 4-tap FIR
filter
0
0
8
163.0
8-bit 16-tap
parallel FIR filter
0
0
4
163.0
IOE Programmable Delay
For IOE programmable delay, refer to Table 4–100 through Table 4–101.
Table 4–100 lists IOE programmable delays.
Table 4–100. Arria GX IOE Programmable Delay on Row Pins
Fast Model
–6 Speed Grade
Parameter
Paths Affected
Available
Settings
Industrial
Commercial
Units
Min
Offset
Max
Offset
Min
Offset
Max
Offset
Min
Offset
Max
Offset
Input delay
from pin to
internal cells
Pad to I/O dataout
to core
8
0
1.782
0
1.782
0
4.124
ns
Input delay
from pin to
input register
Pad to I/O input
register
64
0
2.054
0
2.054
0
4.689
ns
Delay from
output
register to
output pin
I/O output register
to pad
2
0
0.332
0
0.332
0
0.717
ns
Output
enable pin
delay
txz/tzx
2
0
0.32
0
0.32
0
0.693
ns
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Maximum Input and Output Clock Toggle Rate
4–87
Table 4–101 lists IOE programmable delays.
Table 4–101. Arria GX IOE Programmable Delay on Column Pins
Fast Model
–6 Speed Grade
Parameter
Input delay
from pin to
internal cells
Paths Affected
Available
Settings
Pad to I/O dataout to
core
Pad to I/O input register
Input delay
from pin to
input register
Industrial
Commercial
Units
Min
Offset
Max
Offset
Min
Offset
Max
Offset
Min
Offset
Max
Offset
8
0
1.781
0
1.781
0
4.132
ns
64
0
2.053
0
2.053
0
4.697
ns
Delay from
output
register to
output pin
I/O output register to
pad
2
0
0.332
0
0.332
0
0.717
ns
Output
enable pin
delay
txz/tzx
2
0
0.32
0
0.32
0
0.693
ns
Maximum Input and Output Clock Toggle Rate
Maximum clock toggle rate is defined as the maximum frequency achievable for a
clock type signal at an I/O pin. The I/O pin can be a regular I/O pin or a dedicated
clock I/O pin.
The maximum clock toggle rate is different from the maximum data bit rate. If the
maximum clock toggle rate on a regular I/O pin is 300 MHz, the maximum data bit
rate for dual data rate (DDR) could be potentially as high as 600 Mbps on the same
I/O pin.
Table 4–105, Table 4–106, and Table 4–107 provide output toggle rates at the default
capacitive loading. Use the Quartus II software to obtain output toggle rates at loads
different from the default capacitive loading.
Table 4–102 shows the maximum input clock toggle rates for Arria GX device column
I/O pins.
Table 4–102. Arria GX Maximum Input Toggle Rate for Column I/O Pins
I/O Standards
© December 2009
–6 Speed Grade
Units
3.3-V LVTTL
420
MHz
3.3-V LVCMOS
420
MHz
2.5 V
420
MHz
1.8 V
420
MHz
1.5 V
420
MHz
SSTL-2 CLASS I
467
MHz
SSTL-2 CLASS II
467
MHz
SSTL-18 CLASS I
467
MHz
Altera Corporation
Arria GX Device Handbook, Volume 1
4–88
Chapter 4: DC and Switching Characteristics
Maximum Input and Output Clock Toggle Rate
Table 4–102. Arria GX Maximum Input Toggle Rate for Column I/O Pins
I/O Standards
–6 Speed Grade
Units
SSTL-18 CLASS II
467
MHz
1.8-V HSTL CLASS I
467
MHz
1.8-V HSTL CLASS II
467
MHz
1.5-V HSTL CLASS I
467
MHz
1.5-V HSTL CLASS II
467
MHz
3.3-V PCI
420
MHz
3.3-V PCI-X
420
MHz
Table 4–103 shows the maximum input clock toggle rates for Arria GX device row I/O
pins.
Table 4–103. Arria GX Maximum Input Toggle Rate for Row I/O Pins
I/O Standards
–6 Speed Grade
Units
3.3-V LVTTL
420
MHz
3.3-V LVCMOS
420
MHz
2.5 V
420
MHz
1.8 V
420
MHz
1.5 V
420
MHz
SSTL-2 CLASS I
467
MHz
SSTL-2 CLASS II
467
MHz
SSTL-18 CLASS I
467
MHz
SSTL-18 CLASS II
467
MHz
1.8-V HSTL CLASS I
467
MHz
1.8-V HSTL CLASS II
467
MHz
1.5-V HSTL CLASS I
467
MHz
1.5-V HSTL CLASS II
467
MHz
LVDS
392
MHz
Table 4–104 shows the maximum input clock toggle rates for Arria GX device
dedicated clock pins.
Table 4–104. Arria GX Maximum Input Clock Rate for Dedicated Clock Pins (Part 1 of 2)
I/O Standards
–6 Speed Grade
Units
3.3-V LVTTL
373
MHz
3.3-V LVCMOS
373
MHz
2.5 V
373
MHz
1.8 V
373
MHz
1.5 V
373
MHz
SSTL-2 CLASS I
467
MHz
SSTL-2 CLASS II
467
MHz
3.3-V PCI
373
MHz
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Maximum Input and Output Clock Toggle Rate
4–89
Table 4–104. Arria GX Maximum Input Clock Rate for Dedicated Clock Pins (Part 2 of 2)
I/O Standards
–6 Speed Grade
Units
3.3-V PCI-X
373
MHz
SSTL-18 CLASS I
467
MHz
SSTL-18 CLASS II
467
MHz
1.8-V HSTL CLASS I
467
MHz
1.8-V HSTL CLASS II
467
MHz
1.5-V HSTL CLASS I
467
MHz
1.5-V HSTL CLASS II
467
MHz
1.2-V HSTL
233
MHz
DIFFERENTAL SSTL-2
467
MHz
DIFFERENTIAL 2.5-V
SSTL CLASS II
467
MHz
DIFFERENTIAL 1.8-V
SSTL CLASS I
467
MHz
DIFFERENTIAL 1.8-V
SSTL CLASS II
467
MHz
DIFFERENTIAL 1.8-V
HSTL CLASS I
467
MHz
DIFFERENTIAL 1.8-V
HSTL CLASS II
467
MHz
DIFFERENTIAL 1.5-V
HSTL CLASS I
467
MHz
DIFFERENTIAL 1.5-V
HSTL CLASS II
467
MHz
DIFFERENTIAL 1.2-V
HSTL
233
MHz
LVDS
640
MHz
LVDS (1)
373
MHz
Note to Table 4–104:
(1) This set of numbers refers to the VIO dedicated input clock pins.
Table 4–105 shows the maximum output clock toggle rates for Arria GX device
column I/O pins.
Table 4–105. Arria GX Maximum Output Toggle Rate for Column I/O Pins (Part 1 of 3)
I/O Standards
3.3-V LVTTL
© December 2009
Altera Corporation
Drive Strength
–6 Speed Grade
Units
4 mA
196
MHz
8 mA
303
MHz
12 mA
393
MHz
16 mA
486
MHz
20 mA
570
MHz
24 mA
626
MHz
Arria GX Device Handbook, Volume 1
4–90
Chapter 4: DC and Switching Characteristics
Maximum Input and Output Clock Toggle Rate
Table 4–105. Arria GX Maximum Output Toggle Rate for Column I/O Pins (Part 2 of 3)
I/O Standards
3.3-V LVCMOS
2.5 V
1.8 V
1.5 V
SSTL-2 CLASS I
SSTL-2 CLASS II
SSTL-18 CLASS I
SSTL-18 CLASS II
1.8-V HSTL CLASS I
Arria GX Device Handbook, Volume 1
Drive Strength
–6 Speed Grade
Units
4 mA
215
MHz
8 mA
411
MHz
12 mA
626
MHz
16 mA
819
MHz
20 mA
874
MHz
24 mA
934
MHz
4 mA
168
MHz
8 mA
355
MHz
12 mA
514
MHz
16 mA
766
MHz
2 mA
97
MHz
4 mA
215
MHz
6 mA
336
MHz
8 mA
486
MHz
10 mA
706
MHz
12 mA
925
MHz
2 mA
168
MHz
4 mA
303
MHz
6 mA
350
MHz
8 mA
392
MHz
8 mA
280
MHz
12 mA
327
MHz
16 mA
280
MHz
20 mA
327
MHz
24 mA
327
MHz
4 mA
140
MHz
6 mA
186
MHz
8 mA
280
MHz
10 mA
373
MHz
12 mA
373
MHz
8 mA
140
MHz
16 mA
327
MHz
18 mA
373
MHz
20 mA
420
MHz
4 mA
280
MHz
6 mA
420
MHz
8 mA
561
MHz
10 mA
561
MHz
12 mA
607
MHz
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Maximum Input and Output Clock Toggle Rate
4–91
Table 4–105. Arria GX Maximum Output Toggle Rate for Column I/O Pins (Part 3 of 3)
I/O Standards
Drive Strength
–6 Speed Grade
Units
16 mA
420
MHz
18 mA
467
MHz
20 mA
514
MHz
4 mA
280
MHz
6 mA
420
MHz
8 mA
561
MHz
10 mA
607
MHz
12 mA
654
MHz
16 mA
514
MHz
18 mA
561
MHz
20 mA
561
MHz
3.3-V PCI
—
626
MHz
3.3-V PCI-X
—
626
MHz
1.8-V HSTL CLASS II
1.5-V HSTL CLASS I
1.5-V HSTL CLASS II
Table 4–106 shows the maximum output clock toggle rates for Arria GX device row
I/O pins.
Table 4–106. Arria GX Maximum Output Toggle Rate for Row I/O Pins
I/O Standards
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5 V
SSTL-2 CLASS I
SSTL-2 CLASS II
SSTL-18 CLASS I
© December 2009
Altera Corporation
Drive Strength
–6 Speed Grade
Units
4 mA
196
MHz
8 mA
303
MHz
12 mA
393
MHz
4 mA
215
MHz
8 mA
411
MHz
4 mA
168
MHz
8 mA
355
MHz
12 mA
514
MHz
2 mA
97
MHz
4 mA
215
MHz
6 mA
336
MHz
8 mA
486
MHz
2 mA
168
MHz
4 mA
303
MHz
8 mA
280
MHz
12 mA
327
MHz
16 mA
280
MHz
4 mA
140
MHz
6 mA
186
MHz
8 mA
280
MHz
10 mA
373
MHz
Arria GX Device Handbook, Volume 1
4–92
Chapter 4: DC and Switching Characteristics
Maximum Input and Output Clock Toggle Rate
Table 4–106. Arria GX Maximum Output Toggle Rate for Row I/O Pins
I/O Standards
1.8-V HSTL CLASS I
1.5-V HSTL CLASS I
LVDS
Drive Strength
–6 Speed Grade
Units
4 mA
280
MHz
6 mA
420
MHz
8 mA
561
MHz
10 mA
561
MHz
12 mA
607
MHz
4 mA
280
MHz
6 mA
420
MHz
8 mA
561
MHz
—
598
MHz
Table 4–107 lists maximum output clock rate for dedicated clock pins.
Table 4–107. Arria GX Maximum Output Clock Rate for Dedicated Clock Pins (Part 1 of 4)
I/O Standards
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
1.5 V
Arria GX Device Handbook, Volume 1
Drive Strength
–6 Speed Grade
Units
4 mA
196
MHz
8 mA
303
MHz
12 mA
393
MHz
16 mA
486
MHz
20 mA
570
MHz
24 mA
626
MHz
4 mA
215
MHz
8 mA
411
MHz
12 mA
626
MHz
16 mA
819
MHz
20 mA
874
MHz
24 mA
934
MHz
4 mA
168
MHz
8 mA
355
MHz
12 mA
514
MHz
16 mA
766
MHz
2 mA
97
MHz
4 mA
215
MHz
6 mA
336
MHz
8 mA
486
MHz
10 mA
706
MHz
12 mA
925
MHz
2 mA
168
MHz
4 mA
303
MHz
6 mA
350
MHz
8 mA
392
MHz
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Maximum Input and Output Clock Toggle Rate
4–93
Table 4–107. Arria GX Maximum Output Clock Rate for Dedicated Clock Pins (Part 2 of 4)
I/O Standards
SSTL-2 CLASS I
SSTL-2 CLASS II
SSTL-18 CLASS I
SSTL-18 CLASS II
1.8-V HSTL CLASS I
1.8-V HSTL CLASS II
1.5-V HSTL CLASS I
1.5-V HSTL CLASS II
DIFFERENTIAL SSTL-2
DIFFERENTIAL 2.5-V
SSTL CLASS II
© December 2009
Altera Corporation
Drive Strength
–6 Speed Grade
Units
8 mA
280
MHz
12 mA
327
MHz
16 mA
280
MHz
20 mA
327
MHz
24 mA
327
MHz
4 mA
140
MHz
6 mA
186
MHz
8 mA
280
MHz
10 mA
373
MHz
12 mA
373
MHz
8 mA
140
MHz
16 mA
327
MHz
18 mA
373
MHz
20 mA
420
MHz
4 mA
280
MHz
6 mA
420
MHz
8 mA
561
MHz
10 mA
561
MHz
12 mA
607
MHz
16 mA
420
MHz
18 mA
467
MHz
20 mA
514
MHz
4 mA
280
MHz
6 mA
420
MHz
8 mA
561
MHz
10mA
607
MHz
12 mA
654
MHz
16 mA
514
MHz
18 mA
561
MHz
20 mA
561
MHz
24 mA
278
MHz
8 mA
280
MHz
12 mA
327
MHz
16 mA
280
MHz
20 mA
327
MHz
24 mA
327
MHz
Arria GX Device Handbook, Volume 1
4–94
Chapter 4: DC and Switching Characteristics
Maximum Input and Output Clock Toggle Rate
Table 4–107. Arria GX Maximum Output Clock Rate for Dedicated Clock Pins (Part 3 of 4)
I/O Standards
DIFFERENTIAL 1.8-V
SSTL CLASS I
DIFFERENTIAL 1.8-V
SSTL CLASS II
DIFFERENTIAL 1.8-V
HSTL CLASS I
DIFFERENTIAL 1.8-V
HSTL CLASS II
DIFFERENTIAL 1.5-V
HSTL CLASS I
DIFFERENTIAL 1.5-V
HSTL CLASS II
3.3-V PCI
Drive Strength
–6 Speed Grade
Units
4 mA
140
MHz
6 mA
186
MHz
8 mA
280
MHz
10 mA
373
MHz
12 mA
373
MHz
8 mA
140
MHz
16 mA
327
MHz
18 mA
373
MHz
20 mA
420
MHz
4 mA
280
MHz
6 mA
420
MHz
8 mA
561
MHz
10 mA
561
MHz
12 mA
607
MHz
16 mA
420
MHz
18 mA
467
MHz
20 mA
514
MHz
4 mA
280
MHz
6 mA
420
MHz
8 mA
561
MHz
10 mA
607
MHz
12 mA
654
MHz
16 mA
514
MHz
18 mA
561
MHz
20 mA
561
MHz
24 mA
278
MHz
—
626
MHz
3.3-V PCI-X
—
626
MHz
LVDS
—
280
MHz
HYPERTRANSPORT
—
116
MHz
LVPECL
—
280
MHz
SERIES_25_OHMS
327
MHz
SERIES_50_OHMS
327
MHz
SERIES_25_OHMS
280
MHz
SERIES_50_OHMS
280
MHz
SERIES_25_OHMS
280
MHz
SERIES_50_OHMS
280
MHz
SERIES_25_OHMS
420
MHz
SERIES_50_OHMS
420
MHz
3.3-V LVTTL
3.3-V LVCMOS
2.5 V
1.8 V
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Duty Cycle Distortion
4–95
Table 4–107. Arria GX Maximum Output Clock Rate for Dedicated Clock Pins (Part 4 of 4)
I/O Standards
Drive Strength
–6 Speed Grade
Units
1.5 V
SERIES_50_OHMS
373
MHz
SSTL-2 CLASS I
SERIES_50_OHMS
467
MHz
SSTL-2 CLASS II
SERIES_25_OHMS
467
MHz
SSTL-18 CLASS I
SERIES_50_OHMS
327
MHz
SSTL-18 CLASS II
SERIES_25_OHMS
420
MHz
1.8-V HSTL CLASS I
SERIES_50_OHMS
561
MHz
1.8-V HSTL CLASS II
SERIES_25_OHMS
420
MHz
1.5-V HSTL CLASS I
SERIES_50_OHMS
467
MHz
1.2-V HSTL
SERIES_50_OHMS
233
MHz
DIFFERENTIAL SSTL-2
SERIES_50_OHMS
467
MHz
DIFFERENTIAL 2.5-V
SSTL CLASS II
SERIES_25_OHMS
467
MHz
DIFFERENTIAL 1.8-V
SSTL CLASS I
SERIES_50_OHMS
327
MHz
DIFFERENTIAL 1.8-V
SSTL CLASS II
SERIES_25_OHMS
420
MHz
DIFFERENTIAL 1.8-V
HSTL CLASS I
SERIES_50_OHMS
561
MHz
DIFFERENTIAL 1.8-V
HSTL CLASS II
SERIES_25_OHMS
420
MHz
DIFFERENTIAL 1.5-V
HSTL CLASS I
SERIES_50_OHMS
467
MHz
DIFFERENTIAL 1.2-V
HSTL
SERIES_50_OHMS
233
MHz
Duty Cycle Distortion
Duty cycle distortion (DCD) describes how much the falling edge of a clock is off from
its ideal position. The ideal position is when both the clock high time (CLKH) and the
clock low time (CLKL) equal half of the clock period (T), as shown in Figure 4–10.
DCD is the deviation of the non-ideal falling edge from the ideal falling edge, such as
D1 for the falling edge A and D2 for the falling edge B (refer to Figure 4–10). The
maximum DCD for a clock is the larger value of D1 and D2.
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
4–96
Chapter 4: DC and Switching Characteristics
Duty Cycle Distortion
Figure 4–10. Duty Cycle Distortion
Ideal Falling Edge
CLKH = T/2
CLKL = T/2
D1
Falling Edge A
D2
Falling Edge B
Clock Period (T)
DCD expressed in absolution derivation, for example, D1 or D2 in Figure 4–10, is
clock-period independent. DCD can also be expressed as a percentage, and the
percentage number is clock-period dependent. DCD as a percentage is defined as:
(T/2 – D1) / T (the low percentage boundary)
(T/2 + D2) / T (the high percentage boundary)
DCD Measurement Techniques
DCD is measured at an FPGA output pin driven by registers inside the corresponding
I/O element (IOE) block. When the output is a single data rate signal (non-DDIO),
only one edge of the register input clock (positive or negative) triggers output
transitions (Figure 4–11). Therefore, any DCD present on the input clock signal or
caused by the clock input buffer or different input I/O standard does not transfer to
the output signal.
Figure 4–11. DCD Measurement Technique for Non-DDIO (Single-Data Rate) Outputs
However, when the output is a double data rate input/output (DDIO) signal, both
edges of the input clock signal (positive and negative) trigger output transitions
(Figure 4–12). Therefore, any distortion on the input clock and the input clock buffer
affect the output DCD.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Duty Cycle Distortion
4–97
Figure 4–12. DCD Measurement Technique for DDIO (Double-Data Rate) Outputs
When an FPGA PLL generates the internal clock, the PLL output clocks the IOE block.
As the PLL only monitors the positive edge of the reference clock input and internally
re-creates the output clock signal, any DCD present on the reference clock is filtered
out. Therefore, the DCD for a DDIO output with PLL in the clock path is better than
the DCD for a DDIO output without PLL in the clock path.
Table 4–108 through Table 4–113 show the maximum DCD in absolution derivation
for different I/O standards on Arria GX devices. Examples are also provided that
show how to calculate DCD as a percentage.
Table 4–108. Maximum DCD for Non-DDIO Output on Row I/O Pins
Maximum DCD (ps) for Non-DDIO Output
Row I/O Output Standard
–6 Speed Grade
Units
3.3-V LVTTTL
275
ps
3.3-V LVCMOS
155
ps
2.5 V
135
ps
1.8 V
180
ps
1.5-V LVCMOS
195
ps
SSTL-2 Class I
145
ps
SSTL-2 Class II
125
ps
SSTL-18 Class I
85
ps
1.8-V HSTL Class I
100
ps
1.5-V HSTL Class I
115
ps
LVDS
80
ps
Here is an example for calculating the DCD as a percentage for a non-DDIO output on
a row I/O:
If the non-DDIO output I/O standard is SSTL-2 Class II, the maximum DCD is 125 ps
(see Table 4–109). If the clock frequency is 267 MHz, the clock period T is:
T = 1/ f = 1 / 267 MHz = 3.745 ns = 3,745 ps
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
4–98
Chapter 4: DC and Switching Characteristics
Duty Cycle Distortion
To calculate the DCD as a percentage:
(T/2 – DCD) / T = (3,745 ps/2 – 125 ps) / 3,745 ps = 46.66% (for low boundary)
(T/2 + DCD) / T = (3,745 ps/2 + 125 ps) / 3,745 ps = 53.33% (for high boundary)
Therefore, the DCD percentage for the output clock at 267 MHz is from 46.66% to
53.33%.
Table 4–109. Maximum DCD for Non-DDIO Output on Column I/O Pins
Column I/O Output Standard I/O Standard
Maximum DCD (ps)
for Non-DDIO Output
Units
–6 Speed Grade
3.3-V LVTTL
220
ps
3.3-V LVCMOS
175
ps
2.5 V
155
ps
1.8 V
110
ps
1.5-V LVCMOS
215
ps
SSTL-2 Class I
135
ps
SSTL-2 Class II
130
ps
SSTL-18 Class I
115
ps
SSTL-18 Class II
100
ps
1.8-V HSTL Class I
110
ps
1.8-V HSTL Class II
110
ps
1.5-V HSTL Class I
115
ps
1.5-V HSTL Class II
80
ps
1.2-V HSTL-12
200
ps
LVPECL
80
ps
Table 4–110. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path Note (1)
Input I/O Standard (No PLL in the Clock Path)
Maximum DCD (ps) for
Row DDIO Output I/O
Standard
TTL/CMOS
SSTL-2
SSTL/HSTL
LVDS
Units
3.3/2.5V
1.8/1.5V
2.5V
1.8/1.5V
3.3V
3.3-V LVTTL
440
495
170
160
105
ps
3.3-V LVCMOS
390
450
120
110
75
ps
2.5 V
375
430
105
95
90
ps
1.8 V
325
385
90
100
135
ps
1.5-V LVCMOS
430
490
160
155
100
ps
SSTL-2 Class I
355
410
85
75
85
ps
SSTL-2 Class II
350
405
80
70
90
ps
SSTL-18 Class I
335
390
65
65
105
ps
1.8-V HSTL Class I
330
385
60
70
110
ps
1.5-V HSTL Class I
330
390
60
70
105
ps
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
Duty Cycle Distortion
4–99
Table 4–110. Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path Note (1)
Input I/O Standard (No PLL in the Clock Path)
Maximum DCD (ps) for
Row DDIO Output I/O
Standard
TTL/CMOS
SSTL-2
SSTL/HSTL
LVDS
3.3/2.5V
1.8/1.5V
2.5V
1.8/1.5V
3.3V
180
180
180
180
180
LVDS
Units
ps
Note to Table 4–110:
(1) Table 4–110 assumes the input clock has zero DCD.
Table 4–111. Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path
(Note 1)
Input IO Standard (No PLL in the Clock Path)
Maximum DCD (ps) for
DDIO Column Output I/O
Standard
TTL/CMOS
SSTL-2
SSTL/HSTL
Units
3.3/2.5V
1.8/1.5V
2.5V
1.8/1.5V
3.3-V LVTTL
440
495
170
160
ps
3.3-V LVCMOS
390
450
120
110
ps
2.5 V
375
430
105
95
ps
1.8 V
325
385
90
100
ps
1.5-V LVCMOS
430
490
160
155
ps
SSTL-2 Class I
355
410
85
75
ps
SSTL-2 Class II
350
405
80
70
ps
SSTL-18 Class I
335
390
65
65
ps
SSTL-18 Class II
320
375
70
80
ps
1.8-V HSTL Class I
330
385
60
70
ps
1.8-V HSTL Class II
330
385
60
70
ps
1.5-V HSTL Class I
330
390
60
70
ps
1.5-V HSTL Class II
330
360
90
100
ps
LVPECL
180
180
180
180
ps
Note to Table 4–111:
(1) Table 4–111 assumes the input clock has zero DCD.
Table 4–112. Maximum DCD for DDIO Output on Row I/O Pins With PLL in the Clock Path
Maximum DCD (ps) for Row DDIO Output I/O Standard
Arria GX Devices (PLL Output
Feeding DDIO)
Units
–6 Speed Grade
3.3-V LVTTL
105
ps
3.3-V LVCMOS
75
ps
2.5V
90
ps
1.8V
100
ps
1.5-V LVCMOS
100
ps
SSTL-2 Class I
75
ps
SSTL-2 Class II
70
ps
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
4–100
Chapter 4: DC and Switching Characteristics
High-Speed I/O Specifications
Table 4–112. Maximum DCD for DDIO Output on Row I/O Pins With PLL in the Clock Path
Maximum DCD (ps) for Row DDIO Output I/O Standard
Arria GX Devices (PLL Output
Feeding DDIO)
Units
–6 Speed Grade
SSTL-18 Class I
65
ps
1.8-V HSTL Class I
70
ps
1.5-V HSTL Class I
70
ps
LVDS
180
ps
Table 4–113. Maximum DCD for DDIO Output on Column I/O Pins With PLL in the Clock Path
Maximum DCD (ps) for Column
DDIO Output I/O Standard
Arria GX Devices (PLL Output
Feeding DDIO)
Units
–6 Speed Grade
3.3-V LVTTL
160
ps
3.3-V LVCMOS
110
ps
2.5V
95
ps
1.8V
100
ps
1.5-V LVCMOS
155
ps
SSTL-2 Class I
75
ps
SSTL-2 Class II
70
ps
SSTL-18 Class I
65
ps
SSTL-18 Class II
80
ps
1.8-V HSTL Class I
70
ps
1.8-V HSTL Class II
70
ps
1.5-V HSTL Class I
70
ps
1.5-V HSTL Class II
100
ps
1.2-V HSTL
155
ps
LVPECL
180
ps
High-Speed I/O Specifications
Table 4–114 lists high-speed timing specifications definitions.
Table 4–114. High-Speed Timing Specifications and Definitions (Part 1 of 2)
High-Speed Timing Specifications
Definitions
tC
High-speed receiver/transmitter input and output clock period.
fH S C L K
High-speed receiver/transmitter input and output clock frequency.
J
Deserialization factor (width of parallel data bus).
W
PLL multiplication factor.
tR I S E
Low-to-high transmission time.
tF A L L
High-to-low transmission time.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
High-Speed I/O Specifications
4–101
Table 4–114. High-Speed Timing Specifications and Definitions (Part 2 of 2)
High-Speed Timing Specifications
Definitions
Timing unit interval (TUI)
The timing budget allowed for skew, propagation delays, and data sampling window.
(TUI = 1/(Receiver Input Clock Frequency × Multiplication Factor) = tC /w).
fH S D R
Maximum/minimum LVDS data transfer rate (f H S D R = 1/TUI), non-DPA.
fH S D R D PA
Maximum/minimum LVDS data transfer rate (f H S D R D P A = 1/TUI), DPA.
Channel-to-channel skew (TCCS)
The timing difference between the fastest and slowest output edges, including tC O
variation and clock skew. The clock is included in the TCCS measurement.
Sampling window (SW)
The period of time during which the data must be valid in order to capture it
correctly. The setup and hold times determine the ideal strobe position within the
sampling window.
Input jitter
Peak-to-peak input jitter on high-speed PLLs.
Output jitter
Peak-to-peak output jitter on high-speed PLLs.
tD U T Y
Duty cycle on high-speed transmitter output clock.
tL O CK
Lock time for high-speed transmitter and receiver PLLs.
Table 4–115 shows the high-speed I/O timing specifications.
Table 4–115. High-Speed I/O Specifications (Part 1 of 2)Note (1), (2)
–6 Speed Grade
Symbol
Conditions
Units
Min
Typ
Max
W = 2 to 32 (LVDS, HyperTransport technology) (3)
16
—
420
MHz
W = 1 (SERDES bypass, LVDS only)
16
—
500
MHz
W = 1 (SERDES used, LVDS only)
150
—
640
MHz
J = 4 to 10 (LVDS, HyperTransport technology)
150
—
840
Mbps
J = 2 (LVDS, HyperTransport technology)
(4)
—
700
Mbps
J = 1 (LVDS only)
(4)
—
500
Mbps
fH S D R D PA (DPA data rate)
J = 4 to 10 (LVDS, HyperTransport technology)
150
—
840
Mbps
TCCS
All differential I/O standards
—
—
200
ps
SW
All differential I/O standards
440
—
—
ps
Output jitter
—
—
—
190
ps
Output t R I SE
All differential I/O standards
—
—
290
ps
Output t F AL L
All differential I/O standards
—
—
290
ps
tD U T Y
—
45
50
55
%
DPA run length
—
—
—
6,400
UI
0.44
—
—
UI
fH S C L K (clock frequency)
fH S C L K = f H S D R / W
fH S D R (data rate)
DPA jitter tolerance
© December 2009
Data channel peak-to-peak jitter
Altera Corporation
Arria GX Device Handbook, Volume 1
4–102
Chapter 4: DC and Switching Characteristics
High-Speed I/O Specifications
Table 4–115. High-Speed I/O Specifications (Part 2 of 2)Note (1), (2)
–6 Speed Grade
Symbol
Conditions
Units
Min
DPA lock time
Typ
Max
—
—
Standard
Training Pattern
Transition
Density
SPI-4
000000000011
11111111
10%
256
—
—
Parallel Rapid
I/O
00001111
25%
256
—
—
10010000
50%
256
—
—
Miscellaneous
10101010
100%
256
—
—
01010101
—
256
—
—
Number of
repetitions
Notes to Table 4–115:
(1)
(2)
(3)
(4)
When J = 4 to 10, the SERDES block is used.
When J = 1 or 2, the SERDES block is bypassed.
The input clock frequency and the W factor must satisfy the following fast PLL VCO specification: 150  input clock frequency × W  1,040.
The minimum specification is dependent on the clock source (fast PLL, enhanced PLL, clock pin, and so on) and the clock routing resource
(global, regional, or local) used. The I/O differential buffer and input register do not have a minimum toggle rate.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
PLL Timing Specifications
4–103
PLL Timing Specifications
Table 4–116 and Table 4–117 describe the Arria GX PLL specifications when operating
in both the commercial junction temperature range (0 to 85 C) and the industrial
junction temperature range (–40 to 100 C), except for the clock switchover and
phase-shift stepping features. These two features are only supported from the 0 to
100 C junction temperature range.
Table 4–116. Enhanced PLL Specifications (Part 1 of 2)
Name
Description
Min
Typ
Max
Units
fIN
Input clock frequency
2
—
500
MHz
fINPFD
Input frequency to the PFD
2
—
420
MHz
fINDUTY
Input clock duty cycle
40
—
60
%
fENDUTY
External feedback input clock duty cycle
40
—
60
%
Input or external feedback clock input jitter
tolerance in terms of period jitter.
—
0.5
—
ns (peak-to-peak)
—
1.0
—
ns (peak-to-peak)
tINJITTER
Bandwidth  0.85 MHz
Input or external feedback clock input jitter
tolerance in terms of period jitter.
Bandwidth  0.85 MHz
tOUTJITTER
Dedicated clock output period jitter
50
100
250
ps (p-p)
tFCOMP
External feedback compensation time
—
—
10
ns
fOUT
Output frequency for internal global or regional
clock
1.5 (2)
—
550
MHz
fSCANCLK
Scanclk frequency
—
—
100
MHz
tCONFIGEPLL
Time required to reconfigure scan chains for
EPLLs
—
174/fSCANCLK
—
ns
fOUT_EXT
PLL external clock output frequency
1.5 (2)
(1)
MHz
fOUTDUTY
Duty cycle for external clock output
45
50
55
%
tLOCK
Time required for the PLL to lock from the time
it is enabled or the end of device configuration
—
0.03
1
ms
tDLOCK
Time required for the PLL to lock dynamically
after automatic clock switchover between two
identical clock frequencies
—
—
1
ms
fSWITCHOVER
Frequency range where the clock switchover
performs properly
1.5
1
500
MHz
fCLBW
PLL closed-loop bandwidth
0.13
1.2
16.9
MHz
fVCO
PLL VCO operating range
300
—
840
MHz
fSS
Spread-spectrum modulation frequency
100
—
500
kHz
% spread
Percent down spread for a given clock
frequency
0.4
0.5
0.6
%
tPLL_PSERR
Accuracy of PLL phase shift
—
—
±30
ps
tARESET
Minimum pulse width on areset signal.
10
—
—
ns
tARESET_RECONFIG
Minimum pulse width on the areset signal
when using PLL reconfiguration. Reset the PLL
after scandone goes high.
500
—
—
ns
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
4–104
Chapter 4: DC and Switching Characteristics
PLL Timing Specifications
Table 4–116. Enhanced PLL Specifications (Part 2 of 2)
Name
tRECONFIGWAIT
Description
The time required for the wait after the
reconfiguration is done and the areset is
applied.
Min
Typ
Max
Units
—
—
2
us
Notes to Table 4–116:
(1) This is limited by the I/O f MAX.
(2) If the counter cascading feature of the PLL is used, there is no minimum output clock frequency.
Table 4–117. Fast PLL Specifications (Part 1 of 2)
Name
Description
Min
Typ
Max
Units
fIN
Input clock frequency
16.08
—
640
MHz
fINPFD
Input frequency to the
PFD
16.08
—
500
MHz
fINDUTY
Input clock duty cycle
40
—
60
%
Input clock jitter
tolerance in terms of
period jitter.
Bandwidth 2 MHz
—
0.5
—
ns (p-p)
Input clock jitter
tolerance in terms of
period jitter.
Bandwidth  0.2 MHz
—
1.0
—
ns (p-p)
Upper VCO frequency
range
300
—
840
MHz
Lower VCO frequency
range
150
—
420
MHz
PLL output frequency
to GCLK or RCLK
4.6875
—
550
MHz
PLL output frequency
to LVDS or DPA clock
150
—
840
MHz
fOUT_EXT
PLL clock output
frequency to regular
I/O
4.6875
—
(1)
MHz
tCONFIGPLL
Time required to
reconfigure scan
chains for fast PLLs
—
75/f SCANCLK
—
ns
fCLBW
PLL closed-loop
bandwidth
1.16
5
28
MHz
tLOCK
Time required for the
PLL to lock from the
time it is enabled or
the end of the device
configuration
—
0.03
1
ms
tPLL_PSERR
Accuracy of PLL phase
shift
—
—
±30
ps
tARESET
Minimum pulse width
on areset signal.
10
—
—
ns
tINJITTER
fVCO
fOUT
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
External Memory Interface Specifications
4–105
Table 4–117. Fast PLL Specifications (Part 2 of 2)
Name
tARESET_RECONFIG
Description
Min
Typ
Max
Units
Minimum pulse width
on the areset signal
when using PLL
reconfiguration. Reset
the PLL after
scandone goes high.
500
—
—
ns
Note to Table 4–117:
(1) This is limited by the I/O f MAX.
External Memory Interface Specifications
Table 4–118 through Table 4–122 list Arria GX device specifications for the dedicated
circuitry used for interfacing with external memory devices.
Table 4–118. DLL Frequency Range Specifications
Frequency Mode
Frequency Range (MHz)
0
100 to 175
1
150 to 230
2
200 to 310
Table 4–119. DQS Jitter Specifications for DLL-Delayed Clock (tDQS_JITTER) , (Note 1)
Number of DQS Delay Buffer Stages (2)
Commercial (ps)
Industrial (ps)
1
80
110
2
110
130
3
130
180
4
160
210
Notes to Table 4–119:
(1) Peak-to-peak period jitter on the phase-shifted DQS clock. For example, jitter on two delay stages under
commercial conditions is 200 ps peak-to-peak or 100 ps.
(2) Delay stages used for requested DQS phase shift are reported in a project’s Compilation Report in the Quartus II
software.
Table 4–120. DQS Phase-Shift Error Specifications for DLL-Delayed Clock (tDQS_PSERR )
© December 2009
Number of DQS Delay Buffer Stages
–6 Speed Grade (ps)
1
35
2
70
3
105
4
140
Altera Corporation
Arria GX Device Handbook, Volume 1
4–106
Chapter 4: DC and Switching Characteristics
JTAG Timing Specifications
Table 4–121. DQS Bus Clock Skew Adder Specifications (t DQS_CLOCK_SKEW_A DDER )
Mode
DQS Clock Skew Adder (ps)
4 DQ per DQS
40
9 DQ per DQS
70
18 DQ per DQS
75
36 DQ per DQS
95
Table 4–122. DQS Phase Offset Delay Per Stage (ps)
Note (1), (2), (3)
Positive Offset
Negative Offset
Speed Grade
–6
Min
Max
Min
Max
10
16
8
12
Notes to Table 4–122:
(1) The delay settings are linear.
(2) The valid settings for phase offset are –32 to +31.
(3) The typical value equals the average of the minimum and maximum values.
JTAG Timing Specifications
Figure 4–13 shows the timing requirements for the JTAG signals
Figure 4–13. Arria GX JTAG Waveforms.
TMS
TDI
t JCP
t JCH
t JCL
t JPSU
t JPH
TCK
tJPZX
t JPXZ
t JPCO
TDO
tJSSU
Signal
to be
Captured
Signal
to be
Driven
Arria GX Device Handbook, Volume 1
tJSZX
tJSH
tJSCO
tJSXZ
© December 2009
Altera Corporation
Chapter 4: DC and Switching Characteristics
JTAG Timing Specifications
4–107
Table 4–123 lists the JTAG timing parameters and values for Arria GX devices.
Table 4–123. Arria GX JTAG Timing Parameters and Values
Symbol
© December 2009
Parameter
Min
Max
Units
tJCP
TCK clock period
30
—
ns
tJCH
TCK clock high time
12
—
ns
tJCL
TCK clock low time
12
—
ns
tJPSU
JTAG port setup time
4
—
ns
tJPH
JTAG port hold time
5
—
ns
tJPCO
JTAG port clock to output
—
9
ns
tJPZX
JTAG port high impedance to valid output
—
9
ns
tJPXZ
JTAG port valid output to high impedance
—
9
ns
tJSSU
Capture register setup time
4
—
ns
tJSH
Capture register hold time
5
—
ns
tJSCO
Update register clock to output
—
12
ns
tJSZX
Update register high impedance to valid
output
—
12
ns
tJSXZ
Update register valid output to high
impedance
—
12
ns
Altera Corporation
Arria GX Device Handbook, Volume 1
4–108
Chapter 4: DC and Switching Characteristics
Document Revision History
Document Revision History
Table 4–124 lists the revision history for this chapter.
Table 4–124. Document Revision History
Date and Document Version
December 2009, v2.0
April 2009
v1.4
Changes Made
■
Updated Table 4–104, Table 4–105,
and Table 4–106.
■
Document template update.
■
Minor text edits.
■
Updated Table 4–6 and Table 4–7.
■
Updated “Maximum Input and Output
Clock Toggle Rate” section.
Summary of Changes
—
—
Updated:
May 2008
v1.3
■
Table 4–5
■
Table 4–7
■
Table 4–8
■
Table 4–9
■
Table 4–10
■
Table 4–11
■
Table 4–12
■
Table 4–13
■
Table 4–14
■
Table 4–15
■
Table 4–16
■
Table 4–17
■
Table 4–43
■
Table 4–116
■
Table 4–117
Updated:
■
Figure 4–4
—
—
Minor text edits.
—
Removed “Preliminary” from each page.
—
Removed “Preliminary” note from
Tables 4–44, 4–45, and 4–47.
—
Added “Referenced Documents” section.
—
June 2007
v1.1
Updated Table 4–99.
—
Added GIGE information.
—
May 2007
v1.0
Initial release.
August 2007 v1.2
Arria GX Device Handbook, Volume 1
—
© December 2009
Altera Corporation
5. Reference and Ordering Information
AGX51005-2.0
Software
Arria® GX devices are supported by the Altera® Quartus® II design software, which
provides a comprehensive environment for system-on-a-programmable-chip (SOPC)
design. The Quartus II software includes HDL and schematic design entry,
compilation and logic synthesis, full simulation and advanced timing analysis,
SignalTap® II logic analyzer, and device configuration.
f
For more information about the Quartus II software features, refer to the Quartus II
Development Software Handbook .
The Quartus II software supports the Windows XP/2000/NT, Sun Solaris 8/9, Linux
Red Hat v7.3, Linux Red Hat Enterprise 3, and HP-UX operating systems. It also
supports seamless integration with industry-leading EDA tools through the
NativeLink interface.
Device Pin-Outs
f
Arria GX device pin-outs are available on the Altera web site at www.altera.com.
Ordering Information
Figure 5–1 describes the ordering codes for Arria GX devices.
f
© December 2009
For more information on a specific package, refer to the Package Information for Arria
GX Devices chapter.
Altera Corporation
Arria GX Device Handbook, Volume 1
5–2
Chapter 5: Reference and Ordering Information
Document Revision History
Figure 5–1. Arria GX Device Packaging Ordering Information
EP1AGX
20
C
F
484
C
6
N
Family Signature
Optional Suffix
EP1AGX : Arria GX
Indicates specific device options or
shipment method.
N:
Lead-free devices
Device Type
20
35
50
60
90
Speed Grade
6
Operating Temperature
Number of
Transceiver
Channels
C: Commercial temperature (TJ = 0˚ C to 85˚ C)
I: Industrial temperature (TJ = -40˚ C to 100˚ C)
Pin Count
C: 4
D: 8
E: 12
Package Type
484
780
1152
F: FineLine BGA (FBGA)
Document Revision History
Table 5–1 shows the revision history for this chapter.
Table 5–1. Document Revision History
Date and Document
Version
December 2009, v2.0
Changes Made
■
Document template update.
■
Minor text edits.
Summary of Changes
—
August 2007, v1.1
Added the “Referenced Documents” section.
—
May 2007, v1.0
Initial Release.
—
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Additional Information
About this Handbook
This handbook provides comprehensive information about the Altera® Arria® GX
family of devices.
How to Contact Altera
For the most up-to-date information about Altera products, see the following table.
Contact (Note 1)
Contact
Method
Address
Technical support
Website
www.altera.com/support
Technical training
Website
www.altera.com/training
Email
[email protected]
Product literature
Email
www.altera.com/literature
Non-technical support (General)
Email
[email protected]
(Software Licensing)
Email
[email protected]
Note:
(1) You can also contact your local Altera sales office or sales representative.
Typographic Conventions
The following table shows the typographic conventions that this document uses.
Visual Cue
Meaning
Bold Type with Initial Capital
Letters
Indicates command names and dialog box titles. For example, Save As dialog box.
bold type
Indicates directory names, project names, disk drive names, file names, file name
extensions, dialog box options, software utility names, and other GUI labels. For
example, \qdesigns directory, d: drive, and chiptrip.gdf file.
Italic Type with Initial Capital Letters
Indicates document titles. For example, AN 519: Stratix IV Design Guidelines.
Italic type
Indicates variables. For example, n + 1.
Variable names are enclosed in angle brackets (< >). For example, <file name> and
<project name>.pof file.
Initial Capital Letters
Indicates keyboard keys and menu names. For example, Delete key and the Options
menu.
“Subheading Title”
Quotation marks indicate references to sections within a document and titles of
Quartus II Help topics. For example, “Typographic Conventions.”
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
Info–2
Additional Information
Visual Cue
Courier type
Meaning
Indicates signal, port, register, bit, block, and primitive names. For example, data1,
tdi, and input. Active-low signals are denoted by suffix n. For example,
resetn.
Indicates command line commands and anything that must be typed exactly as it
appears. For example, c:\qdesigns\tutorial\chiptrip.gdf.
Also indicates sections of an actual file, such as a Report File, references to parts of
files (for example, the AHDL keyword SUBDESIGN), and logic function names (for
example, TRI).
1., 2., 3., and
a., b., c., and so on.
Numbered steps indicate a list of items when the sequence of the items is important,
such as the steps listed in a procedure.
■ ■
Bullets indicate a list of items when the sequence of the items is not important.
1
The hand points to information that requires special attention.
c
A caution calls attention to a condition or possible situation that can damage or
destroy the product or your work.
w
A warning calls attention to a condition or possible situation that can cause you
injury.
r
The angled arrow instructs you to press Enter.
f
The feet direct you to more information about a particular topic.
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 2
101 Innovation Drive
San Jose, CA 95134
www.altera.com
AGX5V2-2.0
Copyright © 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and
service marks of Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Altera products are protected under numerous U.S. and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants
performance of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no
responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera Corporation. Altera customers are advised
to obtain the latest version of device specifications before relying on any published information and before
placing orders for products or services.
ii
Altera Corporation
Chapter Revision Dates
The chapters in this book, Arria GX Device Handbook, Volume 2, were revised on the following dates.
Where chapters or groups of chapters are available separately, part numbers are listed.
Chapter 1. Arria GX Transceiver Architecture
Revised:
May 2008
Part number: AGX52001-2.0
Chapter 2. Arria GX Transceiver Protocol Support and Additional Features
Revised:
May 2008
Part number: AGX52002-2.0
Chapter 3. Arria GX ALT2GXB Megafunction User Guide
Revised:
May 2008
Part number: AGX52003-2.0
Chapter 4. Specifications and Additional Information
Revised:
May 2007
Part number: AGX52004-1.0
Chapter 5. PLLs in Arria GX Devices
Revised:
May 2008
Part number: AGX52005-1.2
Chapter 6. TriMatrix Embedded Memory Blocks in Arria GX Devices
Revised:
May 2008
Part number: AGX52006-1.2
Chapter 7. External Memory Interfaces in Arria GX Devices
Revised:
May 2008
Part number: AGX52007-1.2
Chapter 8. Selectable I/O Standards in Arria GX Devices
Revised:
May 2008
Part number: AGX52008-1.2
Chapter 9. High-Speed Differential I/O Interfaces with DPA in Arria GX Devices
Revised:
May 2008
Part number: AGX52009-1.2
Altera Corporation
iii
Chapter Revision Dates
Arria GX Device Handbook, Volume 2
Chapter 10. DSP Blocks in Arria GX Devices
Revised:
May 2008
Part number: AGX52010-1.2
Chapter 11. Configuring Arria GX Devices
Revised:
May 2008
Part number: AGX52011-1.3
Chapter 12. Remote System Upgrades with Arria GX Devices
Revised:
May 2008
Part number: AGX52012-1.2
Chapter 13. IEEE 1149.1 (JTAG) Boundary-Scan Testing for Arria GX Devices
Revised:
May 2008
Part number: AGX52013-1.2
Chapter 14. Package Information for Arria GX Devices
Revised:
May 2008
Part number: AGX52014-1.1
iv
Altera Corporation
Contents
Chapter Revision Dates .......................................................................... iii
About this Handbook ............................................................................. xiii
How to Contact Altera .......................................................................................................................... xiii
Typographic Conventions .................................................................................................................... xiii
Section I. Arria GX Transceiver User Guide
Chapter 1. Arria GX Transceiver Architecture
Introduction ............................................................................................................................................ 1–1
Building Blocks ...................................................................................................................................... 1–1
Port List ................................................................................................................................................... 1–3
Transmitter Channel Architecture ...................................................................................................... 1–8
Clock Multiplier Unit ....................................................................................................................... 1–9
Transmitter Phase Compensation FIFO ...................................................................................... 1–23
Byte Serializer ................................................................................................................................. 1–24
8B/10B Encoder .............................................................................................................................. 1–26
Serializer .......................................................................................................................................... 1–31
Transmitter Buffer .......................................................................................................................... 1–33
Receiver Channel Architecture .......................................................................................................... 1–36
Receiver Buffer ................................................................................................................................ 1–37
Receiver PLL ................................................................................................................................... 1–39
Clock Recovery Unit (CRU) ............................................................................................................. 1–41
Deserializer ....................................................................................................................................... 1–44
Word Aligner .................................................................................................................................... 1–47
Channel Aligner (Deskew) ................................................................................................................ 1–59
Rate Matcher ..................................................................................................................................... 1–59
8B/10B Decoder .............................................................................................................................. 1–62
Byte Deserializer ............................................................................................................................. 1–65
Receiver Phase Compensation FIFO Buffer ............................................................................... 1–66
PLD-Transceiver Interface Clocking ................................................................................................. 1–68
Automatic Phase Compensation FIFO Clock Selection ............................................................ 1–68
User Controlled Phase Compensation FIFO Clock Selection .................................................. 1–71
Loopback Modes .................................................................................................................................. 1–75
Serial Loopback .............................................................................................................................. 1–75
PCI Express PIPE Reverse Parallel Loopback ............................................................................ 1–76
Reverse Serial Loopback ............................................................................................................... 1–77
Reverse Serial Pre-CDR Loopback ............................................................................................... 1–78
Altera Corporation
v
Contents
Arria GX Device Handbook, Volume 2
Built-In Self Test Modes ................................................................................................................
BIST in Basic Mode .........................................................................................................................
Calibration Blocks ................................................................................................................................
Referenced Documents .......................................................................................................................
Document Revision History ...............................................................................................................
1–79
1–80
1–82
1–84
1–85
Chapter 2. Arria GX Transceiver Protocol Support and Additional Features
Introduction ............................................................................................................................................ 2–1
PCI Express (PIPE) Mode ..................................................................................................................... 2–2
PCI Express (PIPE) Mode Transmitter Architecture ................................................................... 2–2
PCI Express (PIPE) Mode Receiver Architecture ...................................................................... 2–11
Receiver Status ................................................................................................................................ 2–21
Power State Management ............................................................................................................. 2–22
NFTS Fast Recovery IP (NFRI) ..................................................................................................... 2–23
Low-Latency (Synchronous) PCI Express (PIPE) Mode ........................................................... 2–24
Gigabit Ethernet (GIGE) mode .......................................................................................................... 2–26
GIGE Mode Transmitter Architecture ......................................................................................... 2–27
GIGE Mode Receiver Architecture .............................................................................................. 2–34
UNH-IOL Gigabit Ethernet Compliance .................................................................................... 2–42
Serial RapidIO Mode ........................................................................................................................... 2–43
Serial RapidIO Mode Transmitter Architecture ........................................................................ 2–43
Serial RapidIO Mode Receiver Architecture .............................................................................. 2–50
Basic Single-Width Mode ................................................................................................................... 2–57
XAUI Mode ........................................................................................................................................... 2–60
XAUI Mode Transmitter Architecture ........................................................................................ 2–64
XAUI Mode Receiver Architecture .............................................................................................. 2–71
Serial Digital Interface (SDI) Mode ................................................................................................... 2–81
Reset Control and Power-Down ........................................................................................................ 2–83
User Reset and Power-Down Signals .......................................................................................... 2–84
Recommended Reset Sequence for GIGE and Serial RapidIO in CRU Automatic Lock Mode ..
2–85
Recommended Reset Sequence for GIGE, Serial RapidIO, XAUI, SDI, and Basic Modes in CRU
Manual Lock Mode ........................................................................................................................ 2–86
Recommended Reset Sequence for PCI Express (PIPE) Mode ................................................ 2–88
Power-Down ................................................................................................................................... 2–90
TimeQuest Timing Analyzer ........................................................................................................ 2–90
Unconstrained Asynchronous ALT2GXB Ports ........................................................................ 2–98
Referenced Document ......................................................................................................................... 2–99
Document Revision History ............................................................................................................. 2–100
Chapter 3. Arria GX ALT2GXB Megafunction User Guide
Introduction ............................................................................................................................................ 3–1
Basic Mode .............................................................................................................................................. 3–3
PCI Express (PIPE) Mode ................................................................................................................... 3–25
XAUI Mode ........................................................................................................................................... 3–46
GIGE Mode ........................................................................................................................................... 3–64
SDI Mode .............................................................................................................................................. 3–86
vi
Altera Corporation
Contents
Contents
Serial RapidIO Mode ......................................................................................................................... 3–117
Referenced Documents ..................................................................................................................... 3–141
Document Revision History ............................................................................................................. 3–142
Chapter 4. Specifications and Additional Information
8B/10B Code .......................................................................................................................................... 4–1
Code Notation ................................................................................................................................... 4–1
Disparity Calculation ....................................................................................................................... 4–1
Supported Codes .............................................................................................................................. 4–3
Document Revision History ............................................................................................................... 4–11
Section II. Clock Management
Chapter 5. PLLs in Arria GX Devices
Introduction ............................................................................................................................................ 5–1
Enhanced PLLs ....................................................................................................................................... 5–5
Enhanced PLL Hardware Overview ............................................................................................. 5–5
Enhanced PLL Software Overview ................................................................................................ 5–8
Enhanced PLL Pins ........................................................................................................................ 5–11
Fast PLLs ............................................................................................................................................... 5–14
Fast PLL Hardware Overview ..................................................................................................... 5–14
Fast PLL Software Overview ........................................................................................................ 5–15
Fast PLL Pins ................................................................................................................................... 5–16
Clock Feedback Modes ....................................................................................................................... 5–18
Source-Synchronous Mode ........................................................................................................... 5–18
No Compensation Mode ............................................................................................................... 5–19
Normal Mode .................................................................................................................................. 5–20
Zero Delay Buffer Mode ................................................................................................................ 5–21
External Feedback Mode ............................................................................................................... 5–22
Hardware Features .............................................................................................................................. 5–23
Clock Multiplication and Division .............................................................................................. 5–24
Phase-Shift Implementation ......................................................................................................... 5–25
Programmable Duty Cycle ........................................................................................................... 5–26
Advanced Clear and Enable Control ........................................................................................... 5–27
Advanced Features .............................................................................................................................. 5–30
Counter Cascading ......................................................................................................................... 5–30
Clock Switchover ............................................................................................................................ 5–31
Reconfigurable Bandwidth ................................................................................................................ 5–42
PLL Reconfiguration ........................................................................................................................... 5–49
Spread-Spectrum Clocking ................................................................................................................ 5–49
Board Layout ........................................................................................................................................ 5–54
VCCA and GNDA ............................................................................................................................ 5–54
VCCD ................................................................................................................................................................................................................... 5–56
External Clock Output Power ...................................................................................................... 5–57
Guidelines ........................................................................................................................................ 5–58
Altera Corporation
vii
Contents
Arria GX Device Handbook, Volume 2
PLL Specifications ................................................................................................................................
Clocking ................................................................................................................................................
Global and Hierarchical Clocking ................................................................................................
Clock Sources Per Region ..............................................................................................................
Clock Input Connections ...............................................................................................................
Clock Source Control For Enhanced PLLs ..................................................................................
Clock Source Control for Fast PLLs .............................................................................................
Delay Compensation for Fast PLLs .............................................................................................
Clock Output Connections ............................................................................................................
Clock Control Block .............................................................................................................................
clkena Signals ..................................................................................................................................
Conclusion ............................................................................................................................................
Referenced Documents .......................................................................................................................
Document Revision History ...............................................................................................................
5–59
5–59
5–59
5–62
5–67
5–69
5–69
5–70
5–71
5–77
5–80
5–81
5–81
5–82
Section III. Memory
Chapter 6. TriMatrix Embedded Memory Blocks in Arria GX Devices
Introduction ............................................................................................................................................ 6–1
TriMatrix Memory Overview .............................................................................................................. 6–1
Parity Bit Support ............................................................................................................................. 6–3
Byte Enable Support ........................................................................................................................ 6–3
Pack Mode Support .......................................................................................................................... 6–7
Address Clock Enable Support ...................................................................................................... 6–7
Memory Modes ...................................................................................................................................... 6–9
Single-Port Mode ............................................................................................................................ 6–10
Simple Dual-Port Mode ................................................................................................................. 6–11
True Dual-Port Mode ..................................................................................................................... 6–14
Shift-Register Mode ....................................................................................................................... 6–17
ROM Mode ...................................................................................................................................... 6–19
FIFO Buffers Mode ......................................................................................................................... 6–19
Clock Modes ......................................................................................................................................... 6–19
Independent Clock Mode .............................................................................................................. 6–20
Input and Output Clock Mode ..................................................................................................... 6–22
Read and Write Clock Mode ......................................................................................................... 6–25
Single-Clock Mode ......................................................................................................................... 6–27
Designing With TriMatrix Memory .................................................................................................. 6–30
Selecting TriMatrix Memory Blocks ............................................................................................ 6–30
Synchronous and Pseudo-Asynchronous Modes ...................................................................... 6–31
Power-Up Conditions & Memory Initialization ........................................................................ 6–31
Read-During-Write Operation at the Same Address ..................................................................... 6–32
Same-Port Read-During-Write Mode .......................................................................................... 6–32
Mixed-Port Read-During-Write Mode ........................................................................................ 6–33
Conclusion ............................................................................................................................................ 6–34
Referenced Documents ....................................................................................................................... 6–35
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Contents
Contents
Document Revision History ............................................................................................................... 6–35
Chapter 7. External Memory Interfaces in Arria GX Devices
Introduction ............................................................................................................................................ 7–1
External Memory Standards ................................................................................................................ 7–3
DDR and DDR2 SDRAM ................................................................................................................. 7–3
Arria GX DDR Memory Support Overview ...................................................................................... 7–7
DDR Memory Interface Pins ........................................................................................................... 7–8
DQS Phase-Shift Circuitry ............................................................................................................ 7–11
DQS Logic Block ............................................................................................................................. 7–16
DDR Registers ................................................................................................................................. 7–19
PLL ................................................................................................................................................... 7–26
Conclusion ............................................................................................................................................ 7–26
Referenced Documents ....................................................................................................................... 7–26
Document Revision History ............................................................................................................... 7–26
Section IV. I/O Standards
Chapter 8. Selectable I/O Standards in Arria GX Devices
Introduction ............................................................................................................................................ 8–1
Arria GX I/O Features .......................................................................................................................... 8–1
Arria GX I/O Standards Support ........................................................................................................ 8–2
Single-Ended I/O Standards .......................................................................................................... 8–3
Differential I/O Standards ............................................................................................................ 8–10
Arria GX External Memory Interfaces .............................................................................................. 8–19
Arria GX I/O Banks ............................................................................................................................ 8–20
Programmable I/O Standards ...................................................................................................... 8–21
On-Chip Termination .......................................................................................................................... 8–25
On-Chip Series Termination without Calibration ..................................................................... 8–26
Design Considerations ........................................................................................................................ 8–28
I/O Termination ............................................................................................................................. 8–28
I/O Banks Restrictions .................................................................................................................. 8–29
I/O Placement Guidelines ............................................................................................................ 8–30
DC Guidelines ................................................................................................................................. 8–34
Conclusion ............................................................................................................................................ 8–37
References ............................................................................................................................................. 8–37
Referenced Documents ....................................................................................................................... 8–38
Document Revision History ............................................................................................................... 8–38
Chapter 9. High-Speed Differential I/O Interfaces with DPA in Arria GX Devices
Introduction ............................................................................................................................................
I/O Banks ................................................................................................................................................
Differential Transmitter ........................................................................................................................
Differential Receiver ..............................................................................................................................
Receiver Data Realignment Circuit ...............................................................................................
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9–6
9–7
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Contents
Arria GX Device Handbook, Volume 2
Dynamic Phase Aligner ................................................................................................................... 9–8
Synchronizer ..................................................................................................................................... 9–9
Differential I/O Termination ............................................................................................................. 9–10
Fast PLL ................................................................................................................................................ 9–10
Clocking ................................................................................................................................................ 9–11
Source Synchronous Timing Budget ........................................................................................... 9–13
Differential Data Orientation ........................................................................................................ 9–14
Differential I/O Bit Position ......................................................................................................... 9–14
Receiver Skew Margin for Non-DPA .......................................................................................... 9–16
Differential Pin Placement Guidelines ............................................................................................. 9–18
High-Speed Differential I/Os and Single-Ended I/Os ............................................................. 9–18
DPA Usage Guidelines .................................................................................................................. 9–19
Non-DPA Differential I/O Usage Guidelines ............................................................................ 9–22
Board Design Considerations ............................................................................................................ 9–23
Conclusion ............................................................................................................................................ 9–24
Referenced Documents ....................................................................................................................... 9–25
Document Revision History ............................................................................................................... 9–25
Section V. Digital Signal Processing (DSP)
Chapter 10. DSP Blocks in Arria GX Devices
Introduction .......................................................................................................................................... 10–1
DSP Block Overview ........................................................................................................................... 10–2
Architecture .......................................................................................................................................... 10–7
Multiplier Block .............................................................................................................................. 10–7
Adder/Output Block ................................................................................................................... 10–14
Accumulator ....................................................................................................................................... 10–16
Operational Modes ............................................................................................................................ 10–18
Simple Multiplier Mode .............................................................................................................. 10–20
Multiply Accumulate Mode ....................................................................................................... 10–23
Multiply Add Mode ..................................................................................................................... 10–24
Complex Multiply ............................................................................................................................. 10–26
FIR Filter .............................................................................................................................................. 10–29
Software Support ............................................................................................................................... 10–31
Conclusion .......................................................................................................................................... 10–31
Referenced Documents ..................................................................................................................... 10–32
Document Revision History ............................................................................................................. 10–32
Section VI. Configuration& Remote System Upgrades
Chapter 11. Configuring Arria GX Devices
Introduction .......................................................................................................................................... 11–1
Configuration Devices ................................................................................................................... 11–1
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Contents
Contents
Configuration Features ....................................................................................................................... 11–4
Configuration Data Decompression ............................................................................................ 11–5
Remote System Upgrade ............................................................................................................... 11–8
Power-On Reset Circuit ................................................................................................................. 11–8
VCCPD Pins ....................................................................................................................................... 11–9
VCCSEL Pin .................................................................................................................................... 11–9
Fast Passive Parallel Configuration ................................................................................................ 11–13
FPP Configuration Using a MAX II Device as an External Host .......................................... 11–13
FPP Configuration Using a Microprocessor ............................................................................. 11–24
FPP Configuration Using an Enhanced Configuration Device ............................................. 11–24
Active Serial Configuration (Serial Configuration Devices) ....................................................... 11–32
Estimating Active Serial Configuration Time .......................................................................... 11–41
Programming Serial Configuration Devices ............................................................................ 11–41
Passive Serial Configuration ............................................................................................................ 11–44
PS Configuration Using a MAX II Device as an External Host ............................................. 11–45
PS Configuration Using a Microprocessor ............................................................................... 11–52
PS Configuration Using a Configuration Device ..................................................................... 11–53
PS Configuration Using a Download Cable ............................................................................. 11–65
Passive Parallel Asynchronous Configuration .............................................................................. 11–71
JTAG Configuration .......................................................................................................................... 11–82
Jam STAPL .................................................................................................................................... 11–89
Device Configuration Pins ............................................................................................................... 11–90
Conclusion ........................................................................................................................................ 11–104
Referenced Documents ................................................................................................................... 11–104
Document Revision History ........................................................................................................... 11–105
Chapter 12. Remote System Upgrades with Arria GX Devices
Introduction .......................................................................................................................................... 12–1
Functional Description ........................................................................................................................ 12–2
Configuration Image Types & Pages ........................................................................................... 12–5
Remote System Upgrade Modes ....................................................................................................... 12–7
Overview ......................................................................................................................................... 12–7
Remote Update Mode .................................................................................................................... 12–9
Local Update Mode ...................................................................................................................... 12–11
Dedicated Remote System Upgrade Circuitry .............................................................................. 12–13
Remote System Upgrade Registers ............................................................................................ 12–15
Remote System Upgrade State Machine ................................................................................... 12–18
User Watchdog Timer .................................................................................................................. 12–19
Interface Signals between Remote System Upgrade Circuitry & FPGA Logic Array ....... 12–20
Remote System Upgrade Pin Descriptions ............................................................................... 12–23
Quartus II Software Support ............................................................................................................ 12–23
altremote_update Megafunction ................................................................................................ 12–24
Remote System Upgrade Atom .................................................................................................. 12–27
System Design Guidelines ................................................................................................................ 12–27
Remote System Upgrade With Serial Configuration Devices ............................................... 12–28
Remote System Upgrade With a MAX II Device or Microprocessor & Flash Device ........ 12–28
Remote System Upgrade with Enhanced Configuration Devices ........................................ 12–29
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Contents
Arria GX Device Handbook, Volume 2
Conclusion .......................................................................................................................................... 12–30
Referenced Documents ..................................................................................................................... 12–31
Document Revision History ............................................................................................................. 12–31
Chapter 13. IEEE 1149.1 (JTAG) Boundary-Scan Testing for Arria GX Devices
Introduction .......................................................................................................................................... 13–1
IEEE Std. 1149.1 BST Architecture .................................................................................................... 13–3
IEEE Std. 1149.1 Boundary-Scan Register ........................................................................................ 13–4
Boundary-Scan Cells of a Arria GX Device I/O Pin ................................................................. 13–5
IEEE Std. 1149.1 BST Operation Control .......................................................................................... 13–7
SAMPLE/PRELOAD Instruction Mode ................................................................................... 13–11
Capture Phase ............................................................................................................................... 13–12
Shift & Update Phases ................................................................................................................. 13–12
EXTEST Instruction Mode .......................................................................................................... 13–13
Capture Phase ............................................................................................................................... 13–14
Shift & Update Phases ................................................................................................................. 13–14
BYPASS Instruction Mode .......................................................................................................... 13–15
IDCODE Instruction Mode ......................................................................................................... 13–16
USERCODE Instruction Mode ................................................................................................... 13–16
CLAMP Instruction Mode .......................................................................................................... 13–17
HIGHZ Instruction Mode ........................................................................................................... 13–17
I/O Voltage Support in JTAG Chain .............................................................................................. 13–17
Using IEEE Std. 1149.1 BST Circuitry ............................................................................................. 13–19
BST for Configured Devices ............................................................................................................. 13–19
Disabling IEEE Std. 1149.1 BST Circuitry ....................................................................................... 13–20
Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing ............................................................. 13–20
Boundary-Scan Description Language (BSDL) Support .............................................................. 13–21
Conclusion .......................................................................................................................................... 13–22
References ........................................................................................................................................... 13–22
Referenced Documents ..................................................................................................................... 13–22
Document Revision History ............................................................................................................. 13–22
Section VII. PCB Layout Guidelines
Chapter 14. Package Information for Arria GX Devices
Introduction ..........................................................................................................................................
Thermal Resistance ........................................................................................................................
Package Outlines .................................................................................................................................
484-Pin FBGA - Flip Chip ..............................................................................................................
780-Pin FBGA - Flip Chip ..............................................................................................................
1,152-Pin FBGA - Flip Chip ...........................................................................................................
Document Revision History ...............................................................................................................
xii
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14–2
14–3
14–3
14–5
14–7
14–8
Altera Corporation
About this Handbook
This handbook provides comprehensive information about the Altera®
Arria™ GX family of devices.
How to Contact
Altera
For the most up-to-date information about Altera products, refer to the
following table.
Contact (1)
Technical support
Technical training
Contact
Method
Address
Website
www.altera.com/support
Website
www.altera.com/training
Email
[email protected]
Product literature
Website
www.altera.com/literature
Non-technical support
(General)
Email
[email protected]
(Software Licensing) Email
[email protected]
Note to table:
(1)
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Conventions
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You can also contact your local Altera sales office or sales representative.
This document uses the typographic conventions shown below.
Meaning
Bold Type with Initial
Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are
shown in bold, initial capital letters. Example: Save As dialog box.
bold type
External timing parameters, directory names, project names, disk drive names,
filenames, filename extensions, and software utility names are shown in bold
type. Examples: fMAX, \qdesigns directory, d: drive, chiptrip.gdf file.
Italic Type with Initial Capital
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Document titles are shown in italic type with initial capital letters. Example: AN 75:
High-Speed Board Design.
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Example: <file name>, <project name>.pof file.
Altera Corporation
xiii
Preliminary
Typographic Conventions
Visual Cue
Arria GX Device Handbook, Volume 2
Meaning
Initial Capital Letters
Keyboard keys and menu names are shown with initial capital letters. Examples:
Delete key, the Options menu.
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References to sections within a document and titles of on-line help topics are
shown in quotation marks. Example: “Typographic Conventions.”
Courier type
Signal and port names are shown in lowercase Courier type. Examples: data1,
tdi, input. Active-low signals are denoted by suffix n, e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For
example: c:\qdesigns\tutorial\chiptrip.gdf. Also, sections of an
actual file, such as a Report File, references to parts of files (e.g., the AHDL
keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in
Courier.
1., 2., 3., and
a., b., c., etc.
Numbered steps are used in a list of items when the sequence of the items is
important, such as the steps listed in a procedure.
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Bullets are used in a list of items when the sequence of the items is not important.
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The checkmark indicates a procedure that consists of one step only.
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xiv
Preliminary
Altera Corporation
Section I. Arria GX
Transceiver User Guide
This section provides information on the configuration modes for
Arria™ GX devices. It also includes information on testing, Arria GX port
and parameter information, and pin constraint information.
This section includes the following chapters:
Revision History
Altera Corporation
■
Chapter 1, Arria GX Transceiver Architecture
■
Chapter 2, Arria GX Transceiver Protocol Support and Additional
Features
■
Chapter 3, Arria GX ALT2GXB Megafunction User Guide
■
Chapter 4, Specifications and Additional Information
Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the full handbook.
Section I–1
Preliminary
Arria GX Transceiver User Guide
Section I–2
Preliminary
Arria GX Device Handbook, Volume 2
Altera Corporation
1. Arria GX Transceiver
Architecture
AGX52001-2.0
Introduction
Arria™ GX is a protocol-optimized FPGA family that leverages Altera’s
advanced multi-gigabit transceivers. The Arria GX transceiver blocks
build on the success of the Stratix® II GX family and are optimally
designed to support the following serial connectivity protocols
(functional modes):
■
■
■
■
■
■
Building Blocks
XAUI
PCI Express (PIPE)
Gigabit Ethernet (GIGE)
SDI
Serial RapidIO®
Basic Mode
Arria GX transceivers are structured into full duplex (transmitter and
receiver) four-channel groups called transceiver blocks. The Arria GX
device family offers up to 12 transceiver channels (three transceiver
blocks) per device. You can configure each transceiver block to one of the
supported functional modes; for example, four GIGE ports or one
four-lane (×4) PCI Express (PIPE) port. In Arria GX devices that offer
more than one transceiver block, you can configure each transceiver block
to a different functional mode; for example, one transceiver block
configured as a four-lane (×4) PCI Express (PIPE) port and the other
transceiver block can be configured as four GIGE ports.
Figure 1–1 shows the Arria GX transceiver block diagram divided into
transmitter and receiver circuits.
Altera Corporation
May 2008
1–1
Arria GX Transceiver Architecture
Figure 1–1. Arria GX Gigabit Transceiver Block Diagram
alt2gxb
Input
Output
rx_datain
rx_dataout
rx_seriallpbken
rx_signaldetect
rx_bitslip
rx_syncstatus
rx_enapatternalign
rx_patterndetect
rx_analogreset
rx_digitalreset
SIPO
Word
Aligner
Rate
Matcher
Channel
Aligner
8B/10B
Decoder
debug_rx_phase_comp_fifo_error
rx_cruclk
pipephydonestatus
rx_locktorefclk
pipeelecidle
Clock
Recovery
Unit
rx_locktodata
pipestatus
PIPE
Interface
rx_invpolarity
rx_revbitorderwa
rx_revbyteorderwa
refclk
rxvalid
rx_errdetect
Phase
Compensation
FIFO
Byte
Deserializer
Receiver
PLL
rx_ctrldetect
pipe8b10binvpolarity
rx_disperr
rx_bisterr
rx_bistdone
Receiver
tx_forceelecidle
tx_forcedispcompliance
powerdn
tx_detectrxloopback
tx_dataout
tx_datain
tx_clkout
tx_ctrlenable
coreclkout
tx_digitalreset
debug_tx_phase_comp_fifo_error
Phase
Compensation
FIFO
tx_forcedisp
tx_invpolarity
PIPE
Interface
Byte
Serializer
8B/10B
Encoder
PISO
pll_locked
rx_channelaligned
tx_dispval
fixedclk
cal_blk_clk
High-Speed
Clock
cal_blk_powerdown
pll_inclk
Transmitter
Clock
Divider
gxb_powerdown
gxb_enable
Transmitter
Central
Block
Central
Control
Unit
1–2
Arria GX Device Handbook, Volume 1
Reset
Logic
XAUI, PCIe,
and GIGE
State Machines
Altera Corporation
May 2008
Port List
Port List
You instantiate the Arria GX transceivers using the ALT2GXB MegaCore®
instance provided in the Quartus® II MegaWizard® Plug-In Manager. The
ALT2GXB instance allows you to configure the transceivers for your
intended protocol and select optional control and status ports to and from
the instantiated transceiver channels.
Table 1–1. Arria GX ALT2GXB Ports (Part 1 of 6)
Port Name
Input/
Output
Description
Scope
—
Receiver Physical Coding Sublayer (PCS) Ports
rx_dataout
Output
Receiver parallel data output. The bus width
depends on the channel width multiplied by the
number of channels per instance.
rx_clkout
Output
Recovered clock from the receiver channel.
Channel
rx_coreclk
Input
Optional read clock port for the receiver phase
compensation first-in first-out (FIFO). If not
selected, the Quartus II software automatically
selects rx_clkout/tx_clkout as the
read clock for receiver phase compensation
FIFO. If selected, you must drive this port with
a clock that is frequency locked to
rx_clkout/tx_clkout.
Channel
rx_enapatternalign
Input
Enables word aligner to align to the comma.
This port can be either edge or level sensitive
based on the word aligner mode.
Channel
rx_bitslip
Input
Word aligner bit slip control. The word aligner
slips a bit of the current word boundary every
rising edge of this signal.
Channel
rx_rlv
Output
Run-length violation indicator. A high signal is
driven when the run length (consecutive '1's or
'0's) of the received data exceeds the
configured limit.
Channel
pipe8b10binvpolarity
Input
Physical Interface for PCI Express (PIPE)
polarity inversion at the 8B/10B decoder input.
This port inverts the data at the input to the
8B/10B decoder.
Channel
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May 2008
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Arria GX Device Handbook, Volume 1
Arria GX Transceiver Architecture
Table 1–1. Arria GX ALT2GXB Ports (Part 2 of 6)
Port Name
Input/
Output
Description
Scope
pipestatus
Output
PIPE receiver status port. In case of multiple
status signals, the lower number signal takes
precedence.
000 - Received data OK
001 - 1 skip added (not supported)
010 - 1 skip removed (not supported)
011 - Receiver detected
100 - 8B/10B decoder error
101 - Elastic buffer overflow
110 - Elastic buffer underflow
111 - Received disparity error
Channel
pipephydonestatus
Output
PIPE indicates a mode transition
completion-power transition and rx_detect.
A pulse is given.
Channel
rx_pipedatavalid
Output
PIPE valid data indicator on the rx_dataout
port.
Channel
pipeelecidle
Output
PIPE signal detect for PCI Express.
Channel
rx_digitalreset
Input
Reset port for the receiver PCS block. This port
resets all the digital logic in the receiver
channel. The minimum pulse width is two
parallel clock cycles.
Channel
rx_bisterr
Output
Built-in self test (BIST) block error flag. This
port latches high if an error is detected.
Assertion of rx_digitalreset resets the
BIST verifier, which clears the error flag.
Channel
rx_bistdone
Output
Built-in self test verifier done flag. This port
goes high if the receiver finishes reception of
the test sequence.
Channel
rx_ctrldetect
Output
Receiver control code indicator port. Indicates
whether the data at the output of
rx_dataout is a control or data word. Used
with the 8B/10B decoder.
Channel
rx_errdetect
Output
8B/10B code group violation signal. Indicates
that the data at the output of rx_dataout
has a code violation or a disparity error. Used
with disparity error signal to differentiate
between a code group error and/or a disparity
error. In addition, in XAUI mode,
rx_errdetect is asserted in the
corresponding byte position when ALT2GXB
substitutes the received data with 9'b1FE
because of XAUI protocol violations.
Channel
1–4
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May 2008
Port List
Table 1–1. Arria GX ALT2GXB Ports (Part 3 of 6)
Port Name
Input/
Output
Description
Scope
rx_syncstatus
Output
Indicates when the word aligner either aligns to
a new word boundary (in single width mode the
rx_patterndetect port is level sensitive),
indicates that a resynchronization is needed
(the rx_patterndetect is edge sensitive),
or indicates if synchronization is achieved or
not (the dedicated synchronization state
machine is used).
Channel
rx_disperr
Output
8B/10B disparity error indicator port. Indicates
that the data at the output of rx_dataout
has a disparity error.
Channel
rx_patterndetect
Output
Indicates when the word aligner detects the
alignment pattern in the current word
boundary.
Channel
rx_invpolarity
Input
Inverts the polarity of the received data at the
input of the word aligner
Channel
rx_revbitorderwa
Input
Available in Basic mode with bit-slip word
alignment enabled. Reverses the bit-order of
the received data at a byte level at the output
of the word aligner.
Channel
debug_rx_phase_comp_
fifo_error
Output
Indicates receiver phase compensation FIFO
overrun or underrun situation
Channel
Receiver Physical Media Attachment (PMA)
rx_pll_locked
Output
Receiver PLL locked signal. Indicates if the
receiver PLL is phase locked to the CRU
reference clock.
Channel
rx_analogreset
Input
Receiver analog reset. Resets all analog
circuits in the receiver PMA.
Channel
rx_freqlocked
Output
CRU mode indicator port. Indicates if the CRU
is locked to data mode or locked to the
reference clock mode.
0 – Receiver CRU is in lock-to-reference clock
mode
1 – Receiver CRU is in lock-to-data mode
Channel
rx_signaldetect
Output
Signal detect port. In PIPE mode, indicates if a
signal that meets the specified range is present
at the input of the receiver buffer. In all other
modes, rx_signaldetect is forced high
and must not be used as an indication of a valid
signal at receiver input.
Channel
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May 2008
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Arria GX Device Handbook, Volume 1
Arria GX Transceiver Architecture
Table 1–1. Arria GX ALT2GXB Ports (Part 4 of 6)
Port Name
Input/
Output
rx_seriallpbken
Input
rx_locktodata
Input
Description
Scope
Serial loopback control port.
0 – normal data path, no serial loopback
1 – serial loopback
Channel
Lock-to-data control for the CRU. Use with
Channel
rx_locktorefclk.
rx_locktorefclk
Input
Lock-to-reference lock mode for the CRU. Use
with rx_locktodata.
rx_locktodata/rx_locktorefclk
0/0 – CRU is in automatic mode
0/1 – CRU is in lock-to-reference clock
1/0 – CRU is in lock-to-data mode
1/1 – CRU is in lock-to-data mode
Channel
rx_cruclk
Input
Receiver PLL/CRU reference clock.
Channel
tx_datain
Input
Transmitter parallel data input. The bus width
depends on the channel width for the selected
functional mode multiplied by the number of
channels in the instance.
Channel
tx_clkout
Output
PLD logic array clock from the transceiver to
the PLD. In an individual-channel mode, there
is one tx_clkout per channel.
Channel
tx_coreclk
Input
Optional write clock port for the transmitter
phase compensation FIFO. If not selected, the
Quartus II software automatically selects
tx_clkout as the write clock for transmitter
phase compensation FIFO. If selected, you
must drive this port with a clock that is
frequency locked to tx_clkout.
Channel
tx_detectrxloopback
Input
PIPE receiver detect / loopback pin.
Depending on the power-down state (P0 or
P1), the signal either activates receiver detect
or loopback.
Channel
tx_forceelecidle
Input
PIPE Electrical Idle mode.
Channel
tx_forcedispcompliance
Input
PIPE forced negative disparity port for
transmission of the compliance pattern. The
pattern requires starting at a negative disparity.
Assertion of this port at the first byte ensures
that the first byte has a negative disparity. This
port must be deasserted after the first byte.
Channel
Transmitter PCS
1–6
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
Port List
Table 1–1. Arria GX ALT2GXB Ports (Part 5 of 6)
Port Name
Input/
Output
Description
Scope
powerdn
Input
PIPE power mode port. This port sets the
power mode of the associated PCI Express
channel. The power modes are as follows:
2'b00: P0 – Normal operation
2'b01: P0s – Low recovery time latency, power
saving state
2'b10: P1 – Longer recovery time (64 μs max)
latency, lower power state
2'b11: P2 – Lowest power state
Channel
tx_digitalreset
Input
Reset port for the transmitter PCS block. This
port resets all the digital logic in the transmit
channel. The minimum pulse width is two
parallel clock cycles.
Channel
tx_ctrlenable
Input
Transmitter control code indicator port.
Indicates whether the data at the tx_datain
port is a control or data word. This port is used
with the 8B/10B encoder.
Channel
tx_invpolarity
Input
Available in all modes. Inverts the polarity of
the data to be transmitted at the transmitter
PCS-PMA interface (input to the serializer).
Channel
debug_tx_phase_comp_
fifo_error
Output
Indicates transmitter phase compensation
FIFO overrun or underrun situation.
Channel
Input
125-MHz clock for receiver detect circuitry in
PCI Express (PIPE) mode.
Channel
gxb_powerdown
Input
Transceiver block reset and power down. This
resets and powers down all circuits in the
transceiver block. This does not affect the
REFCLK buffers and reference clock lines.
Transceiver
block
pll_locked
Output
PLL locked indicator for the transmitter PLLs.
Transceiver
block
pll_inclk
Input
Reference clocks for the transmitter PLLs.
Transceiver
block
Input
Calibration clock for the transceiver
termination blocks. This clock supports
frequencies from 10 MHz to 125 MHz.
Transmitter PMA
fixedclk
CMU PMA
Calibration Block
cal_blk_clk
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May 2008
Device
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Arria GX Transceiver Architecture
Table 1–1. Arria GX ALT2GXB Ports (Part 6 of 6)
Input/
Output
Port Name
Description
Scope
Input
Power-down signal for the calibration block.
Assertion of this signal may interrupt data
transmission and reception. Use this signal to
re-calibrate the termination resistors if
temperature and/or voltage changes warrant it.
Device
tx_dataout
Output
Transmitter serial output port.
Channel
rx_datain
Input
Receiver serial input port.
Channel
rrefb (1)
Output
Reference resistor port. This port is always
used and must be tied to a 2K-Ω resistor to
ground. This port is highly sensitive to noise.
There must be no noise coupled to this port.
Device
refclk (1)
Input
Dedicated reference clock inputs (two per
transceiver block) for the transceiver. The
buffer structure is similar to the receiver buffer,
but the termination is not calibrated.
Transceiver
block
gxb_enable
Input
Dedicated transceiver block enable pin. If
instantiated, this port must be tied to the
pll_ena input pin. A high level on this signal
enables the transceiver block; a low level
disables it.
Transceiver
block
cal_blk_powerdown
(active low)
External Signals
Note to Table 1–1:
(1)
These are dedicated pins for the transceiver and do not appear in the MegaWizard Plug-In Manager.
Transmitter
Channel
Architecture
This section provides a brief description about sub-blocks within the
transmitter channel (shown in Figure 1–2). The sub-blocks are described
in order from the PLD-transmitter parallel interface to the serial
transmitter buffer.
Figure 1–2. Arria GX Transmitter Channel Block Diagram
Transmitter PCS
PLD
Logic
Array
PIPE
Interface
TX Phase
Compensation
FIFO
Byte
Serializer
8B/10B
Encoder
Transmitter PMA
Serializer
CMU
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Reference
Clock
Altera Corporation
May 2008
Transmitter Channel Architecture
Clock Multiplier Unit
Each transceiver block has a clock multiplier unit (CMU) that takes in a
reference clock and synthesizes two clocks: a high-speed serial clock to
serialize the data and a low-speed parallel clock used to clock the
transmitter digital logic (PCS) and the PLD-transceiver interface.
The CMU is further divided into three sub-blocks
■
■
■
Transmitter PLL
Central clock divider block
Local clock divider block
Each transceiver block has one transmitter PLL, one central clock divider
and four local clock dividers. One local clock divider is located in each
transmitter channel of the transceiver block.
Figure 1–3 shows a block diagram of the CMU block within each
transceiver block.
Figure 1–3. Clock Multiplier Unit Block Diagram
CMU Block
Transmitter High-Speed Serial
and Low-Speed Parallel Clocks
Transmitter Channels [3:2]
Local Clock
TX Clock
Gen Block
Divider Block
Reference clock
from REFCLKs,
Global Clock (1)
Inter-Transceiver
Lines
Transmitter
PLL
Central Clock
Divider
Block
Transmitter High-Speed Serial
and Low-Speed Parallel Clocks
Local Clock
TX Clock
Divider Block
Transmitter Channels[1:0]
Gen Block
Note to Figure 1–3:
(1)
The global clock line must be driven from an input pin only.
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May 2008
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Arria GX Transceiver Architecture
Transmitter PLL
The transmitter PLL multiplies the input reference clock to generate the
high-speed serial clock required to support the intended protocol. It
synthesizes a half-rate high-speed serial clock that runs at half the
frequency of the serial data rate for which it is configured; for example,
the transmitter PLL runs at 625 MHz when configured in 1.25-Gbps GIGE
functional mode.
The transmitter PLL output feeds the central clock divider block and the
local clock divider blocks. These clock divider blocks divide the
high-speed serial clock to generate the low-speed parallel clock for the
transceiver PCS logic and the PLD-transceiver interface clock. Depending
on the functional mode for which the transceiver block is configured,
either the central clock divider block or the local clock divider block is
used to generate the low-speed parallel clock.
Figure 1–4 shows a block diagram of the transmitter PLL.
Figure 1–4. Transmitter PLL
Transmitter PLL
/M (1)
To
Inter-Transceiver Block Lines
Dedicated
REFCLK0
up
/2
INCLK
Dedicated
/2
REFCLK1
Inter-Transceiver Block Lines [2:0]
Phase
Frequency
Detector
down
Charge
Pump + Loop
Filter
Voltage
Controlled
Oscillator
/L (1)
High Speed
Serial Clock
Global Clock (2)
Notes to Figure 1–4:
(1)
(2)
You only need to select the protocol and the available input reference clock frequency in the Quartus II MegaWizard
Plug-In Manager. Based on your selections, the MegaWizard Plug-In Manager automatically selects the necessary
/M and /L dividers (clock multiplication factors).
The global clock line must be driven from an input pin only.
The reference clock input to the transmitter PLL can be derived from:
■
■
■
One of the two available dedicated reference clock input pins
(REFCLK0 or REFCLK1) of the associated transceiver block
PLD global clock network (must be driven directly from an input
clock pin and cannot be driven by user logic or enhanced PLL)
Inter-transceiver block lines driven by reference clock input pins of
other transceiver blocks
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May 2008
Transmitter Channel Architecture
1
Altera recommends using the dedicated reference clock input
pins (REFCLK0 or REFCLK1) to provide the reference clock for
the transmitter PLL.
Transmitter PLL Bandwidth Setting
The Arria GX transmitter PLLs in the transceiver offer a programmable
bandwidth setting. The bandwidth of a PLL is the measure of its ability to
track the input clock and jitter. It is determined by the -3dB frequency of
the closed-loop gain of the PLL.
There are three bandwidth settings: high, medium, and low. The high
bandwidth setting filters out internal noise from the VCO because it tracks
the input clock above the frequency of the internal VCO noise. With the
low bandwidth setting, if the noise on the input reference clock is greater
than the internal noise of the VCO, the PLL filters out the noise above the
-3dB frequency of the closed-loop gain of the PLL. The medium
bandwidth setting is a compromise between the high and low settings.
The -3dB frequencies for these settings can vary because of the non-linear
nature and frequency dependencies of the circuit.
Dedicated Reference Clock Input Pins
Each transceiver block has two dedicated reference clock input pins
(REFCLK0 and REFCLK1). The clock route from REFCLK0 and REFCLK1
pins in each transceiver block has an optional pre-divider that divides the
reference clock by two before feeding it to the transmitter PLL (shown in
Figure 1–4). The refclk pre-divider is required if one of the following
conditions is satisfied:
■
■
If the input clock frequency is greater than 325 MHz.
For functional modes with a data rate less than 3.125 Gbps (the data
rate is specified in the what is the data rate? option in the General
tab of the ALT2GXB MegaWizard):
●
If the input clock frequency is greater than or equal to 100 MHz
AND
●
If the ratio of data rate to input clock frequency is 4, 5, or 25
Reference Clock From PLD Global Clock Network
You can drive the reference clock to the transmitter PLL from a PLD
global clock network. If you choose this option, you must drive the global
PLD reference clock line from a non-REFCLK FPGA input pin. You cannot
use a clock generated by PLD logic or an enhanced PLL to drive the
reference clock input to the transmitter PLL.
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May 2008
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Arria GX Transceiver Architecture
1
The Quartus II software requires the following setting for the
non-REFCLK FPGA input pin used to drive the reference clock
input:
Assignment name: Stratix II GX/Arria GX REFCLK coupling and
termination setting
Value: Use as regular IO.
Inter-Transceiver Block Line Routing
The inter-transceiver block lines allow the dedicated reference clock input
pins of one transceiver block to drive the transmitter and receiver PLL of
other transceiver blocks. There are a maximum of three inter-transceiver
block routing lines available in the Arria GX device family. Each
transceiver block can drive one inter-transceiver block line from either
one of its associated reference clock pins. The inter-transceiver block lines
can drive any or all of the transmitter and receiver PLLs in the device. The
inter-transceiver block lines offer flexibility when multiple channels in
separate transceiver blocks share a common reference clock frequency.
The inter-transceiver block lines also drive the reference clock from the
REFCLK pins into the PLD fabric, which reduces the need to drive
multiple clocks of the same frequency into the device. If a divide-by-two
reference clock pre-divider is used, the inter-transceiver block line driven
by the corresponding REFCLK pin cannot be used to clock PLD logic.
The Quartus II software automatically uses the appropriate
inter-transceiver line if the transceiver block is being clocked by the
dedicated reference clock (REFCLK) pin of another transceiver block.
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May 2008
Transmitter Channel Architecture
Figure 1–5 shows the inter-transceiver block line interface to the
transceivers in the gigabit transceiver blocks and to the PLD.
Figure 1–5. Inter-Transceiver Block Line Routing
Inter-Transceiver Block Line[2]
Transceiver Block 2
Inter-Transceiver Block Line[1]
Transceiver Block 1
Transceiver Block 0
Inter-Transceiver Block Line[0]
Inter-Transceiver Block Lines[2:0]
Dedicated
REFCLK0
/2
Dedicated
REFCLK1
/2
Transmitter
PLL
Global Clock (1)
Note to Figure 1–5:
(1)
The global clock line must be driven from an input pin only.
1
Depending on the functional mode, the Quartus II software
automatically selects the appropriate transmitter PLL
bandwidth.
Central Clock Divider Block
The central clock divider block is located in the central block of the
transceiver block (refer to Figure 1–6). This block provides the high-speed
clock for the serializer and the low-speed clock for the transceiver’s PCS
logic within the transceiver block in a four-lane mode.
Figure 1–6 shows the central clock divider block. The /4 and /5 block
generates the slow-speed clock based on the serialization factor. The
high-speed clock goes directly into each channel’s serializer.
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May 2008
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Arria GX Transceiver Architecture
Figure 1–6. Central Clock Divider Block
High-Speed Serial Clock (1)
High-Speed
Serial Clock from
Transmitter PLL
Low-Speed Parallel Clock
/4 or /5
Notes to Figure 1–6:
(1)
This feeds the PCS logic.
The central clock divider block feeds all the channels in the transceiver
block when in PIPE ×4 mode. This ensures that the serializer in each
channel outputs the same bit number at the same time and minimizes the
channel-to-channel skew.
Transmitter Local Clock Divider Block
The Tx local clock divider blocks are located in each transmitter channel
of the transceiver block. The purpose of this block is to provide the
high-speed clock for the serializer and the low-speed clock for the
transmitter data path and the PLD for all the transmitters within the
transceiver block. This allows for each of the transmitter channels to run
at different rates. The /n divider offers /1, /2, and /4 factors to provide
capability to reduce base frequency of the driving PLL to half or a quarter
rate. This allows each transmitter channel to run at /1, /2, or /4 of the
original data rate.
Figure 1–7 shows the transmitter local clock divider block.
Figure 1–7. Transmitter Local Clock Divider Block
High-Speed Clock
From Transmitter PLL0
High-Speed
Clock to Transmitter
÷n
High-Speed Clock
From Transmitter PLL1
÷ 4, 5
Slow-Speed
Clock to Transmitter
÷1, 2, or 4
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May 2008
Transmitter Channel Architecture
Each transmitter local clock divider block is operated independently so
there is no guarantee that each channel sends out the same bit at the same
time.
Clock Synthesis
Each PLL in a transceiver block receives a reference clock and generates a
high-speed clock that is forwarded to the clock generator blocks. There
are two types of clock generators:
■
■
Transmitter local clock divider block
Central clock divider block
The transmitter local clock divider block resides in the transmit channel
and synthesizes the high-speed serial clock (used by the serializer) and
slow-speed clock (used by the transmitter’s PCS logic). The central clock
divider block resides in the transceiver block outside the transmit or
receive channels. This block synthesizes the high-speed serial clock (used
by the serializer) and slow-speed clock (used by the transceiver block PCS
logic—transmitter and receiver (if the rate matcher is used)). The PLD
clock is also supplied by the central clock divider block and goes through
the divide-by-two block (located in the central block of the transceiver
block) if the byte serializer/deserializer is used.
The PLLs in the transceiver have half rate voltage-controlled oscillators
(VCOs) that run at half the rate of the data stream. When in the individual
channel mode, the slow-speed clocks for the transmitter logic and the
serializer need only be a /4, or a /5 divider to support a ×8 and ×10
serialization factor. Table 1–2 shows the divider settings for achieving the
available serialization factor.
Table 1–2. Serialization Factor and Divider Settings
Serialization Factor
Divider Setting
×8
/4
×10
/5
In the four-lane mode, the central clock divider block supplies all the
necessary clocks for the entire transceiver block.
The reference clock ranges from 50 MHz to 622.08 MHz. The phase
frequency detector (PFD) has a minimum frequency limit of 50 MHz and
a maximum frequency limit of 325 MHz.
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May 2008
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Arria GX Transceiver Architecture
The refclk pre-divider (/2 ) is available if you use the dedicated
refclk pins for the input reference clock. The refclk pre-divider is
required if one of the following conditions is satisfied:
■
■
If the input clock frequency is greater than 325 MHz.
For functional modes with a data rate less than 3.125 Gbps (the data
rate is specified in the what is the data rate? option in the General
tab of the ALT2GXB MegaWizard):
●
If the input clock frequency is greater than or equal to 100 MHz
AND
●
If the ratio of data rate to input clock frequency is 4, 5, or 25
Transceiver Clock Distribution
This section describes single lane and four-lane configurations for the
high speed and low speed transceiver clocks. All protocol support falls in
the single lane configuration except for the four-lane PIPE mode and
XAUI. The four-lane PIPE mode uses the four-lane configuration.
Single Lane
In a single lane configuration, the PLLs in the central block supply the
high speed clock. Then the clock generation blocks in each transmitter
channel divides down the high speed clock to the frequency needed to
support its particular data rate. In this configuration, two separate clocks
can be supplied through the central block to provide support for two
separate base frequencies. The transmitter clock generation blocks can
divide those down to create additional frequencies for specific data rate
requirements. Each of the four transmitter channels can operate at a
different data rate with the use of the individual transmitter local clock
dividers and both Transmitter PLL0 and Transmitter PLL1.
1
If you instantiate four channels and are not in PIPE ×4, XAUI, or
Basic single-width mode with ×4 clocking, the Quartus II
software automatically chooses the single lane configuration.
Figure 1–8 shows clock distribution for individual channel configuration.
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May 2008
Transmitter Channel Architecture
Figure 1–8. Clock Distribution for Individual Channel Configuration
TX Channel 3
TX Channel 2
TX Local Clk
Div Block
refclk 0
TXPLL 0
High Speed TXPLL 0 Clock
TXPLL 1
High Speed TXPLL 1 Clock
refclk 1
TXPLL Block
Central Block
TX Channel 1
TX Channel 0
TX Local Clk
Div Block
Four-Lane Mode
In a four-lane configuration (shown in Figure 1–9), the central block
generates the parallel and serial clocks that feed the transmitter channels
within the transceiver. All channels in a transceiver must operate at the
same data rate. This configuration is only supported in PIPE ×4, XAUI
and Basic mode with ×4 clocking.
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May 2008
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Arria GX Transceiver Architecture
Figure 1–9. Clock Distribution for a Four-Lane Configuration Note (1)
Transmitter Channel 3
Transmitter Channel 2
Transmitter PLL0
Reference
clocks (refclks,
Global Clock (1),
IQ Lines)
Transmitter PLL1
Central
Clock Divider
Block
coreclk_out
÷2
Transmitter PLL Block
To PLD
Central Block
Transmitter Channel 1
Transmitter Channel 0
Note to Figure 1–9:
(1)
The global clock line must be driven by an input pin.
Figure 1–10 shows how single transceiver block devices EP1AGX20CF,
EP1AGX35CF, EP1AGX50CF and EP1AGX60CF devices are configured
for PCI-E ×4 mode. When ArriaGX devices are used in ×4 bonded mode
for PCI-E, physical Lane 0 of the transmitter should be connected to
physical Lane 0 of the receiver and vice versa.
Figure 1–10. Two Transceiver Block Device with One ×4 PCI-E Link
Bank 14 (Slave)
EP1AGX20C
EP1AGX35C
EP1AGX50C
EP1AGX60C
GXB_TX/RX1
PCIe Lane 1
GXB_TX/RX0
PCIe Lane 0
GXB_TX/RX2
PCIe Lane 2
GXB_TX/RX3
PCIe Lane 3
The two transceiver block devices EP1AGX35DF, EP1AGX50DF, and
EP1AGX60DF support only two PCI-E ×4 links. Fig Figure 1–11shows the
PCI-E ×4 configuration.
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Transmitter Channel Architecture
Figure 1–11. Two Transceiver Block Device with Two ×4 PCI-E Links
Bank 13
EP1AGX35DF
EP1AGX50DF
EP1AGX60DF
GXB_TX/RX1
PCIe Lane 5
GXB_TX/RX0
PCIe Lane 4
GXB_TX/RX2
PCIe Lane 6
GXB_TX/RX3
PCIe Lane 7
Bank 14
GXB_TX/RX5
PCIe Lane 1
GXB_TX/RX4
PCIe Lane 0
GXB_TX/RX6
PCIe Lane 2
GXB_TX/RX7
PCIe Lane 3
The three transceiver block devices EP1AGX60EF and EP1AGX90EF
support up to three PCI-E ×4 links. Figure 1–12 shows the PCI-E ×4
configuration.
Figure 1–12. Three Transceiver Block Device with Three ×4 PCI-E Links
Bank 13
EP1AGX60EF
EP1AGX90EF
GXB_TX/RX1
PCIe Lane 1
GXB_TX/RX0
PCIe Lane 0
GXB_TX/RX2
PCIe Lane 2
GXB_TX/RX3
PCIe Lane 3
Bank 14
GXB_TX/RX5
PCIe Lane 1
GXB_TX/RX4
PCIe Lane 0
GXB_TX/RX6
PCIe Lane 2
GXB_TX/RX7
PCIe Lane 3
Bank 15
Altera Corporation
May 2008
GXB_TX/RX9
PCIe Lane 1
GXB_TX/RX8
PCIe Lane 0
GXB_TX/RX10
PCIe Lane 2
GXB_TX/RX11
PCIe Lane 3
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Channel Clock Distribution
This section describes clocking within each channel for:
■
■
Individual channels in Basic (without ×4 clocking enabled), PIPE ×1,
GIGE, Serial RapidIO, and SDI modes
Bonded channels in XAUI, PIPE ×4, and Basic (with ×4 clocking
enabled) modes
Individual Channels Clocking
In individual channel modes, the transmitter logic is clocked by the slow
speed clock from the clock divider block. The transmitter phase
compensation FIFO buffer and the PIPE interface (in PIPE mode) are
clocked by the tx_clkout clock of the channel that is fed back to the
transmitter channel from the PLD logic. Figure 1–13 shows the clock
routing for the transmitter channel.
Figure 1–13. Individual Channel Transmitter Logic Clocking
PLD
Logic
Array
XCVR
PIPE
Interface
Transmitter
Digital
TX
Logic
Phase
Compensation
FIFO
Transmitter Analog Circuits
Byte
Serializer
8B/10B
Encoder
Serializer
÷1, 2
tx_clkout
Central Block
Reference
Clocks
The receiver logic clocking has two clocking methods: one when rate
matching is used and the other when rate matching is not used.
If rate matching is used (PIPE, GIGE, and Basic modes), the receiver logic
from the serializer to the rate matcher is clocked by the recovered clock
from its associated channel. The rest of the logic is clocked by the slow
clock from the clock divider block of its associated channel. The read side
of the phase compensation FIFO buffer and the PIPE interface (for PIPE
mode) is clocked by the tx_clkout fed back through the PLD logic.
Figure 1–14 shows the clocking of the receiver logic with the rate matcher.
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Transmitter Channel Architecture
Figure 1–14. Individual Channel Receiver Logic Clocking with Rate Matching
PLD
XCVR
Receiver Analog Circuits
Receiver Digital Logic
PIPE
Interface
RX Phase
Compensation
FIFO
Byte
Deserializer
Rate
Match
FIFO
8B/10B
Decoder
Word
Aligner
Deserializer
Clock
Recovery
Unit
÷1, 2
Central
Block
tx_clkout
Reference
Clocks
If rate matching is not used (Basic, SDI, and Serial RapidIO modes), then
the receiver logic is clocked by the recovered clock of its associated
channel (Figure 1–15). The receiver phase compensation FIFO buffer's
read port is clocked by the recovered clock that is fed back from the PLD
logic array as rx_clkout.
Figure 1–15. Individual Channel Receiver Logic Clocking Without Rate Matching
PLD
XCVR
PIPE
rx_clkout
Receiver Analog Circuits
Receiver Digital Logic
RX Phase
Compensation
FIFO
Byte
Deserializer
8B/10B
Decoder
Word
Aligner
Deserializer
Clock
Recovery
Unit
÷1, 2
Transmitter Clocking (Bonded Channels)
The clocking in bonded channel modes (Figure 1–16) is different from
that of the individual channel. All the transmitters are synchronized to
the same transmitter PLL and clock divider from the central block. In ×4
bonded channel modes, the central clock divider of the transceiver block
clocks all four channels.
The transmitter logic up to the read port of the transmitter phase
compensation FIFO buffer is clocked by the slow speed clock from the
central block. The PIPE interface and the write port of the transmitter
phase compensation FIFO buffer is clocked by the coreclkout signal
routed from the PLD.
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May 2008
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Arria GX Transceiver Architecture
Figure 1–16. Transmitter Channel Clocking in Transceiver Mode
PLD
Logic
Array
Transmitter
Digital
Logic
XCVR
PIPE
Interface
Transmitter Analog Circuits
TX
Phase
Compensation
FIFO
Byte
Serializer
8B/10B
Encoder
Serializer
÷1, 2
coreclkout
Central Block
Reference
Clocks
For the receiver logic, in XAUI mode (Figure 1–17), the local recovered
clock feeds the logic up to the write clock of the deskew FIFO buffer. The
recovered clock from Channel 0 feeds the read clock of the deskew FIFO
buffer and the write port of the rate matcher. The slow clock from the
central block feeds the rest of the logic up to the write port of the phase
compensation FIFO buffer. The coreclkout signal routed through the
PLD from the central block feeds the read side of the phase compensation
FIFO buffer.
Figure 1–17. Receiver Channel Clocking in XAUI Mode
XCVR
PLD
Receiver Analog Circuits
Receiver Digital Logic
RX Phase
Compensation
FIFO
Byte
Deserializer
8B/10B
Decoder
Rate
Match
FIFO
Word
Aligner
Clock
Recovery
Unit
Deserializer
÷1, 2
Central Block
coreclkout
Reference
Clocks
In the PIPE ×4 mode (Figure 1–18), the local recovered clock feeds the
logic up to the write port of the rate matcher FIFO buffer. The slow clock
from the central block feeds the rest of the logic up to the write port of the
phase compensation FIFO buffer. The coreclkout signal routed
through the PLD from the central block feeds the read side of the phase
compensation FIFO buffer.
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Transmitter Channel Architecture
Figure 1–18. Receiver Channel PIPE 4 Mode
XCVR
PLD
Receiver Analog Circuits
Receiver Digital Logic
RX Phase
Compensation
FIFO
Byte
Deserializer
8B/10B
Decoder
Rate
Match
FIFO
Word
Aligner
Deserializer
Clock
Recovery
Unit
÷1, 2
Central Block
coreclkout
Reference
Clocks
Transmitter Phase Compensation FIFO
A transmitter phase compensation FIFO (Figure 1–19) is located at each
transmitter channel's logic array interface. It compensates for the phase
difference between the transmitter PCS clock and the local PLD clock.
In individual channel mode (for example, GIGE and Serial RapidIO), the
low-speed parallel clock (or its divide-by-two version if the byte serializer
is used) from the local clock divider block of each channel clocks the read
port of its transmitter phase compensation FIFO buffer. This clock is also
forwarded to the logic array on tx_clkout port of its associated
channel. If the tx_coreclk port is not instantiated, the clock signal on
the tx_clkout port of Channel 0 is automatically fed back to clock the
write port of the transmitter phase compensation FIFOs in all channels
within the transceiver block. If the tx_coreclk port is instantiated, the
clock signal driven on the tx_coreclk port clocks the write port of the
transmitter phase compensation FIFO of its associated channel. You must
ensure that the clock on the tx_coreclk port is frequency locked to the
read clock of the transmitter phase compensation FIFO. For more
information about using the PLD core clock (tx_coreclk), refer to
“PLD-Transceiver Interface Clocking” on page 1–68.
In bonded channel mode (for example, ×4 PCI Express (PIPE)), the low
speed parallel clock from the central clock divider block is divided by
two. This divide-by-two clock clocks the read port of the transmitter
phase compensation FIFO. This clock is also forwarded to the logic array
on the coreclkout port. If the tx_coreclk port is not instantiated, the
clock signal on the coreclkout port is automatically fed back to clock
the write port of transmitter phase compensation FIFO buffers in all
channels within the transceiver block. If the tx_coreclk port is
instantiated, the clock signal driven on the tx_coreclk port clocks the
write port of the transmitter phase compensation FIFO of its associated
channel. You must ensure that the clock on the tx_coreclk port is
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May 2008
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Arria GX Transceiver Architecture
frequency locked to the read clock of the transmitter phase compensation
FIFO. For more information about using the PLD core clock
(tx_coreclk), refer to “PLD-Transceiver Interface Clocking” on
page 1–68.
Figure 1–19. Transmitter Phase Compensation FIFO
Transmitter Channel
datain[]
From PLD
or PIPE
Interface
Transmitter
Phase
Compensation
FIFO
wrclk
rdclk
dataout[]
To Byte Serializer
or 8B/10B
Encoder
tx_coreclk
/2
CMU
Local/Central Clock
Divider Block
tx_clkout
or
coreclkout
Transmitter Phase Compensation FIFO Error Flag
The write port of the transmitter phase compensation FIFO can be
clocked by either the CMU output clock or its divide-by-two version
(tx_clkout or coreclkout) or a PLD clock. The read port is always
clocked by the CMU output clock or its divide-by-two version. In all
configurations, the write clock and the read clock must have 0 parts per
million (PPM) difference to avoid overrun/underflow of the phase
compensation FIFO.
An optional debug_tx_phase_comp_fifo_error port is available in
all modes to indicate transmitter phase compensation FIFO
overrun/underflow condition. This feature should be used for debug
purposes only if link errors are observed.
Byte Serializer
The byte serializer (Figure 1–20) takes in 16- or 20-bit wide data from the
transmitter phase compensation FIFO buffer and serializes it into 8- or
10-bit wide data at twice the speed. This allows clocking the
PLD-transceiver interface at half the speed as compared to the transmitter
PCS logic. The byte serializer is bypassed in GIGE mode.
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May 2008
Transmitter Channel Architecture
Figure 1–20. Byte Serializer Note (1)
datain[15:0]
dataout[7:0]
Byte Serializer
From Transmitter
Phase Compensation
FIFO
To 8B/10B
Encoder
wrclk
rdclk
CMU
Local/Central Clock
Divider Block
/2
Low-Speed Parallel
Clock
Divide-By-Two Version
of Low-Speed
Parallel Clock
Note to Figure 1–20:
(1)
datain and dataout may also be 20 bits and 10 bits wide, respectively.
After serialization, the byte serializer transmits the least significant byte
(LSByte) first and the most significant byte (MSByte) last.
Figure 1–21 shows byte serializer input and output. datain[15:0] is
the input to the byte serializer from the transmitter phase compensation
FIFO and dataout[7:0] is the output of the byte serializer. datain
may also be 20 bits wide and dataout may be 10 bits wide depending on
implementation.
Figure 1–21. Byte Serializer Operation
D1
datain[15:0]
{8'h02, 8'h03}
D1 LSByte
dataout[7:0]
xxxxxxxxxx
D3
D2
{8'h00, 8'h01}
xxxxxxxxxx
8'h01
xxxx
D1 MSByte
8'h00
D2LSByte
8'h03
D2MSByte
8'h02
In Figure 1–21, the LSByte is transmitted before the MSByte from the
transmitter byte serializer. For input data D1, the output data is D1LSByte
and then D1MSByte.
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Arria GX Transceiver Architecture
8B/10B Encoder
The 8B/10B encoder block takes in 8-bit data from the byte serializer or
transmitter phase compensation FIFO buffer (if the byte serializer is not
used). It generates a 10-bit code group with proper running disparity
from the 8-bit character and a 1-bit control identifier (tx_ctrlenable).
The 10-bit code group is fed to the serializer. The 8B/10B encoder
conforms to the IEEE 802.3 1998 edition standard.
Figure 1–22 shows the 8B/10B conversion format.
f
For additional information about 8B/10B encoding rules, refer to the
Specifications and Additional Information chapter in volume 2 of the
Arria GX Device Handbook.
Figure 1–22. 8B/10B Encoder
7 6 5 4 3 2 1 0
Ctrl
H G F E D C B A
8B-10B Conversion
j
h g f
i
e d c b a
9 8 7 6 5 4 3 2 1 0
MSB
LSB
The 10-bit encoded data output from the 8B/10B encoder is fed to the
serializer that transmits the data from LSB to MSB.
Reset Behavior
The transmitter digital reset (tx_digitalreset) signal resets the
8B/10B encoder. During reset, the running disparity and data registers
are cleared and the 8B/10B encoder outputs a K28.5 pattern from the
RD- column continuously. Once out of reset, the 8B/10B encoder starts
with a negative disparity (RD-) and transmits three K28.5 code groups for
synchronizing before it starts encoding the input data or control
character.
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Transmitter Channel Architecture
Figure 1–23 shows the 8B/10B encoder's reset behavior. When in reset
(tx_digitalreset is high), a K28.5- (K28.5 10-bit code group from the
RD- column) is sent continuously until tx_digitalreset is low. The
transmitter channel pipelining causes some "don't cares (10'hxxx)" until
the first of three K28.5 is sent. User data follows the third K28.5.
Figure 1–23. 8B/10B Encoder Output During Reset
clock
tx_digitalreset
dataout[9:0]
K28.5-
K28.5-
K28.5-
xxx
...
xxx
K28.5-
K28.5+
K28.5-
Dx.y+
Control Code Group Encoding
A control identifier (tx_ctrlenable) input signal specifies whether the
8-bit input character is to be encoded as a control word (Kx.y) or data
word (Dx.y). When tx_ctrlenable is low, the input character is
encoded as data (Dx.y). When tx_ctrlenable is high, the input
character is encoded as a control word (Kx.y). The waveform in
Figure 1–24 shows that the second 0xBC character is encoded as a control
word (K28.5). The rest of the characters are encoded as data (Dx.y).
Figure 1–24. Control Code Group Identification
clock
datain[7..0]
83
78
BC
BC
0F
00
BF
3C
D3.4
D24.3
D28.5
K28.5
D15.0
D0.0
D31.5
D28.1
tx_ctrlenable
Code Group
1
Altera Corporation
May 2008
The 8B/10B encoder does not check whether the code group
word entered is one of the 12 valid codes. If you enter an invalid
control code, the resultant 10-bit code group may be encoded as
an invalid code (does not map to a valid Dx.y or Kx.y code
group), or unintended valid Dx.y code group, depending on the
value entered.
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Arria GX Transceiver Architecture
Transmitter Force Disparity
Upon power on or reset, the 8B/10B encoder has a negative disparity and
chooses the 10-bit code from the RD- column. The Transmitter Force
Disparity feature allows altering the running disparity via the
tx_forcedisp and tx_dispval ports.
Two optional ports, tx_forcedisp and tx_dispval, are available in
8B/10B enabled Basic mode. A high value on the tx_forcedisp bit will
change the disparity value of the data to the value indicated by the
associated tx_dispval bit. If the tx_forcedisp bit is low, then
tx_dispval is ignored and the current running disparity is not altered.
Forcing disparity can either maintain the current running disparity
calculations if the forced disparity value (on the tx_dispval bit)
happens to match the current running disparity, or flip the current
running disparity calculations if it does not. If the forced disparity flips
the current running disparity, the downstream 8B/10B decoder may
detect a disparity error that should be tolerated by the downstream
device.
Figure 1–25 shows the current running disparity being altered in Basic
mode by forcing a positive disparity on a negative disparity K28.5. In this
example, a series of K28.5 code groups are continuously being sent. The
stream alternates between a positive ending running disparity (RD+)
K28.5 and a negative ending running disparity (RD-) K28.5 as governed
by the 8B/10B encoder to maintain a neutral overall disparity. The current
running disparity at time n+3 indicates that the K28.5 in time n+4 should
be encoded with a negative disparity. Since the tx_forcedisp is high at
time n+4, and tx_dispval is also high, the K28.5 at time n+4 is encoded
as a positive disparity code group. As the tx_forcedisp is low at n+5,
the K28.5 will take the current running disparity of n+4 and encode the
K28.5 in time n+5 with a negative disparity. If the tx_forcedisp were
driven high at time n+5, that K28.5 would also be encoded with positive
disparity.
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May 2008
Transmitter Channel Architecture
Figure 1–25. Transmitter Force Disparity Feature in Basic Mode
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
BC
BC
BC
BC
BC
BC
BC
BC
RD-
RD+
RD-
RD+
RD+
RD-
RD+
RD-
17C
283
283
17C
283
17C
clock
tx_in[7:0]
tx_ctrlenable
tx_forcedisp
tx_dispval
Current Disparity
tx_out
17C
283
Transmitter Polarity Inversion
The positive and negative signals of a serial differential link might
accidentally be swapped during board layout. Solutions such as a board
re-spin or major updates to the PLD logic can prove expensive. The
transmitter polarity inversion feature is provided to correct this situation.
An optional tx_invpolarity port is available in all modes to
dynamically enable the transmitter polarity inversion feature. A high on
the tx_invpolarity port inverts the polarity of every bit of the 8- or
10-bit input data word to the serializer in the transmitter data path. Since
inverting the polarity of each bit has the same effect as swapping the
positive and negative signals of the differential link, correct data is seen
by the receiver. The tx_invpolarity is a dynamic signal and may
cause initial disparity errors at the receiver of an 8B/10B encoded link.
The downstream system must be able to tolerate these disparity errors.
Figure 1–26 illustrates the transmitter polarity inversion feature in a
10-bit wide data path configuration.
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May 2008
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Arria GX Transceiver Architecture
Figure 1–26. Transmitter Polarity Inversion
0
1
1
0
0
1
1
0
1
tx_invpolarity = HIGH
0
1
0
1
0
1
0
0
1
0
1
Output from transmitter PCS
To Serializer
Input to transmitter PMA
Transmitter Bit Reversal
By default, the Arria GX transmitted bit order is LSBit to MSBit. In Basic
mode, the least significant bit of the 8/10-bit data word is transmitted first
and the most significant bit is transmitted last. The Transmitter Bit
Reversal feature allows reversing the transmitted bit order as MSBit to
LSBit.
If the Transmitter Bit Reversal feature is enabled in Basic mode, the 8-bit
D[7:0] or 10-bit D[9:0] data at the input of the serializer gets rewired
to D[0:7] or D[0:9], respectively. Flipping the parallel data using this
feature and transmitting LSBit to MSBit effectively provides MSBit to
LSBit transmission.
Figure 1–27 illustrates the transmitter bit reversal feature in a Basic mode
10-bit wide data path configuration.
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May 2008
Transmitter Channel Architecture
Figure 1–27. Transmitter Bit Reversal in Basic Mode
D[9]
D[0]
D[8]
D[1]
D[7]
D[2]
D[6]
D[3]
D[5] TX Bit Reversal = Enabled
D[4]
D[4]
D[5]
D[3]
D[6]
D[2]
D[7]
D[1]
D[8]
D[0]
D[9]
Output from transmitter PCS
To Serializer
Input to transmitter PMA
Serializer
The serializer block clocks in 8- or 10-bit data using the low-speed parallel
clock and clocks out serial data using the high-speed serial clock from the
central or local clock divider blocks. The serializer natively feeds the data
LSB to MSB to the transmitter output buffer.
Figure 1–28 shows the serializer block diagram.
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May 2008
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Arria GX Transceiver Architecture
Figure 1–28. Serializer
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
10
From 8B/10B
Encoder
CMU
Central/
Local Clock
Divider
To Transmitter
Output Buffer
Low-Speed Parallel Clock
High-Speed Serial Clock
Figure 1–29 shows the serial bit order at the serializer output. In this
example, 10'b17C data is serialized and transmitted from LSB to MSB.
Figure 1–29. Serializer Bit Order
Low Speed Parallel Clock
High Speed Serial Clock
datain[9:0]
0101111100
dataout[0]
0 0 1
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1
1010000011
1
1
1 0
1
0
1
1
0
0
0
0 0
1
0
1
Altera Corporation
May 2008
Transmitter Channel Architecture
Transmitter Buffer
The Arria GX transmitter buffers support 1.2-V and 1.5-V pseudo current
mode logic (PCML) up to 3.125 Gbps and can drive 40 inches of FR4 trace
across two connectors. The transmitter buffer (refer to Figure 1–30) has
additional circuitry to improve signal integrity-programmable output
voltage, programmable pre-emphasis circuit, and internal termination
circuitry-and the capability to detect the presence of a downstream
receiver. The Arria GX transmitter buffer supports a common mode of
600 or 700 mV.
Figure 1–30. Transmitter Buffer
50Ω
+VTT-
Programmable
Pre-emphasis
and VOD
Transmitter
Output Pins
50Ω
RX Detect
Programmable Voltage Output Differential
Arria GX devices allow you to customize the differential output voltage
(VOD) to handle different trace lengths, various backplanes, and receiver
requirements (refer to Figure 1–31). You select the VOD from a range
between 400 and 1200 mV, as shown in Table 1–3.
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May 2008
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Arria GX Transceiver Architecture
Figure 1–31. VOD (Differential) Signal Level
Single-Ended Waveform
VA
+VOD
VB
Differential Waveform
+600
+VOD
0-V Differential
VOD
VOD (Differential)
-VOD
-600
= VA – VB
Table 1–3 shows the VOD setting per supply voltage for an on-chip
termination value of 100 Ω .
Table 1–3. VOD Differential Peak to Peak
1.2-V VCC
1.5-V VCC
100-Ω (mV)
100-Ω (mV)
—
400
480
600
640
800
800
1000
960
1200
You set the VOD values in the MegaWizard Plug-In Manager.
The transmitter buffer is powered by either a 1.2-V or a 1.5-V power
supply. You choose the transmitter buffer power (VCCH) of 1.2 V or 1.5 V
through the ALT2GXB MegaWizard Plug-In Manager (the What is the
transmit buffer power (VCCH)? option). The transmitter buffer power
supply in Arria GX devices is transceiver-based. The 1.2 V power supply
supports the 1.2-V PCML standard.
You specify the static VOD settings through the ALT2GXB MegaWizard
Plug-In Manager.
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May 2008
Transmitter Channel Architecture
Programmable Pre-Emphasis
The programmable pre-emphasis module in each transmit buffer boosts
the high frequencies in the transmit data signal, which may be attenuated
in the transmission media. Using pre-emphasis can maximize the data
eye opening at the far-end receiver.
The transmission line’s transfer function can be represented in the
frequency domain as a low pass filter. Any frequency components below
the -3dB frequency pass through with minimal losses. Frequency
components greater than the -3dB frequency are attenuated. This
variation in frequency response yields data dependent jitter and other ISI
effects. By applying pre-emphasis, the high frequency components are
boosted, that is, pre-emphasized. Pre-emphasis equalizes the frequency
response at the receiver so the difference between the low frequency and
high frequency components are reduced, which minimizes the ISI effects
from the transmission medium.
The pre-emphasis requirements increase as data rates through legacy
backplanes increase. The Arria GX transmitter buffer employs a
pre-emphasis circuit with up to 184% of pre-emphasis to correct for losses
in the transmission medium.
You set pre-emphasis settings through a slider menu in the ALT2GXB
MegaWizard Plug-In Manager. Arria GX devices support the first five
settings for first post-tap pre-emphasis. Specify the first post-tap
pre-emphasis settings through the MegaWizard Plug-In Manager.
Transmitter Termination
The Arria GX transmitter buffer includes on-chip differential termination
of 100 Ω . The resistance is adjusted by the on-chip calibration circuit in
the calibration block (refer to “Calibration Blocks” on page 1–82 for more
information), which compensates for temperature, voltage, and process
changes. You can disable the on-chip termination to use external
termination. If you select external termination, the transmitter common
mode is also tri-stated.
You set the transmitter termination setting through a pull-down menu in
the ALT2GXB MegaWizard Plug-In Manager.
PCI Express Receiver Detect
The Arria GX transmitter buffer has a built-in receiver detection circuit
for use in the PIPE mode. This circuit detects if there is a receiver
downstream by sending out a pulse on the common mode of the
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May 2008
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Arria GX Transceiver Architecture
transmitter and monitoring the reflection. This mode requires the
transmitter buffer to be tri-stated (in Electrical Idle mode) and the use of
on-chip termination and a 125 MHz fixedclk signal.
This feature is only available in the PIPE mode. You enable it by setting
the tx_forceelecidle and tx_detectrxloopback ports to 1'b1.
You must set the powerdn port to 2'b10 to place the transmitter in the
PCI-Express P1 power down state. The results of the receiver detect are
encoded on the pipestatus port.
PCI Express Electrical Idle
The Arria GX transmitter buffer supports PCI Express Electrical Idle (or
individual transmitter tri-state). This feature is only active in the PIPE
mode. The tx_forceelecidle port puts the transmitter buffer in
Electrical Idle mode. This port is available in all PCI Express power-down
modes and has a specific use in each mode. Table 1–4 shows the usage in
each power mode.
Table 1–4. Power Mode Usage
Power Mode
P0
Usage
tx_forceelecidle must be asserted. If this signal is deasserted, it indicates that there is
valid data.
P1
tx_forceelecidle must be asserted.
P2
When deasserted, the beacon signal must be transmitted.
Receiver
Channel
Architecture
This section provides a brief description about sub-blocks within the
receiver channel (Figure 1–32). The sub-blocks are described in order
from the serial receiver input buffer to the receiver phase compensation
FIFO buffer at the transceiver-PLD interface.
Figure 1–32. Receiver Channel Block Diagram
Receiver Digital Logic
RX Phase
Compensation
FIFO
Receiver Analog Circuits
Byte
Deserializer
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
Deserializer
Clock
Recovery
Unit
Reference
Receiver Clock
PLL
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May 2008
Receiver Channel Architecture
Receiver Buffer
The Arria GX receiver buffers support 1.2-V, 1.5-V, 3.3-V PCML
(pseudo-current mode logic), differential LVPECL and LVDS I/O
standards. The receiver buffers support data rates from 600 Mbps to
3.125 Gbps and are capable of compensating up to 40 inches of FR4 trace
across two connectors. The receiver buffer (Figure 1–33) has additional
circuitry to improve signal integrity, including a programmable
equalization circuit and internal termination circuitry. Through a signal
detect circuit, the receiver buffers can also detect if a signal of predefined
amplitude exists at the receiver.
Figure 1–33. Receiver Buffer
50Ω
Receiver
Input Pins
Programmable
Equalizer
+VTT-
To CRU
50Ω
Signal
Detect
Receiver Termination
The Arria GX receiver buffer has an optional on-chip differential
termination of 100 Ω . You can set the receiver termination resistance
setting using one of these options:
■
Set receiver termination resistance by:
a. Set the receiver termination resistance option in the
MegaWizard Plug-In Manager if on-chip termination is used.
Arria GX supports 100 Ω termination. If the design requires
external receive termination, turn on the Use External Receiver
Termination option.
b.
■
Altera Corporation
May 2008
You make the differential termination assignment per pin in the
Quartus II software. (On the Assignments menu, point to
Assignment Organizer, and click Options for Individual
Nodes Only. Then click Stratix II GX GXB Termination Value.)
Verify and set the receiver termination settings before compilation.
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Arria GX Transceiver Architecture
Signal Threshold Detection Circuit
The signal detect feature is supported only in PIPE mode. The signal
detect/loss threshold detector senses if the specified voltage level exists
at the receiver buffer. This detector has a hysteresis response, that filters
out any high frequency ringing caused by inter symbol interference or
high frequency losses in the transmission medium. The
rx_signaldetect signal indicates if a signal conforms to the signal
detection settings. A high level indicates that the signal conforms to the
settings, a low level indicates that the signal does not conform to the
settings.
The signal detect levels are to be determined by characterization. The
signal detect levels may vary because of changing data patterns.
The signal/detect loss threshold detector also switches the receiver
PLL/CRU from lock-to-reference mode to lock-to-data mode. The
lock-to-reference and lock-to-data modes dictate whether the VCO of the
clock recovery unit (CRU) is trained by the reference clock or by the data
stream.
You can bypass the signal/detect loss threshold detection circuit by
choosing the Forced Signal Detect option in the MegaWizard Plug-In
Manager. This is useful in lossy environments where the voltage
thresholds might not meet the lowest voltage threshold setting. Forcing
this signal high enables the receiver PLL to switch from VCO training
based on the reference clock to the incoming data without detecting a
valid voltage threshold.
Receiver Common Mode
Arria GX transceivers support the receiver buffer common mode voltages
of 0.85 V and 1.2 V. Altera recommends selecting 0.85 V as the receiver
buffer common mode voltage.
Programmable Equalization
The Arria GX device offers an equalization circuit in each gigabit
transceiver block receiver channel to increase noise margins and help
reduce the effects of high frequency losses. The programmable equalizer
compensates for the high frequency losses that distort the signal and
reduces the noise margin of the transmission medium by equalizing the
frequency response. There are five equalizer control settings allowed for
an Arria GX device (including a setting with no equalization). In addition
to equalization, Arria GX devices offer an equalizer DC gain option.
There are three legal settings for DC gain. You specify the equalizer
settings (Equalization Settings and DC Gain) through the MegaWizard
Plug-In Manager.
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Receiver Channel Architecture
The transmission line's transfer function can be represented in the
frequency domain as a low pass filter. Any frequency components below
the -3dB frequency pass through with minimal losses. Frequency
components that are greater than the -3dB frequency are attenuated. This
variation in frequency response yields data-dependent jitter and other ISI
effects. By applying equalization, the low frequency components are
attenuated. This equalizes the frequency response such that the delta
between the low frequency and high frequency components is reduced,
which in return minimizes the ISI effects from the transmission medium.
Receiver PLL
Each transceiver channel has its own receiver PLL that is fed by an input
reference clock. The reference clock frequency depends on the functional
mode for which the transceiver channel is configured for. The clock
recovery unit (CRU) controls whether the receiver PLL locks to the input
reference clock (lock-to-reference mode) or the incoming serial data (lockto-data mode). Refer to “Clock Recovery Unit (CRU)” on page 1–41 for
more details on lock-to-reference and lock-to-data modes. The receiver
PLL, in conjunction with the clock recovery unit, generates two clocks: a
high speed serial clock that clocks the deserializer and a low-speed
parallel clock that clocks the receiver’s digital logic.
1
This section only discusses the receiver PLL operation in
lock-to-reference mode. For lock-to-data mode, refer to “Clock
Recovery Unit (CRU)” on page 1–41.
Figure 1–34 shows the block diagram of the receiver PLL in
lock-to-reference mode.
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May 2008
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Arria GX Transceiver Architecture
Figure 1–34. Receiver PLL Block Diagram
/M (1)
rx_pll_locked
Dedicated
REFCLK0
/2
Dedicated
REFCLK1
/2
PFD
rx_cruclk
up
dn
up
dn
Inter-Transceiver Lines[2:0]
Charge
Pump +
Loop
Filter
VCO
/L (1)
Global Clock (2)
rx_freqlocked
rx_locktorefclk
Clock Recovery Unit (CRU) Control
rx_locktodata
High-speed serial recovered clock
rx_datain
Low-speed parallel recovered clock
inactive circuits
active circuits
Notes to Figure 1–34:
(1)
(2)
You only need to select the protocol and the available input reference clock frequency in the Quartus II MegaWizard
Plug-In Manager. Based on your selections, the MegaWizard Plug-In Manager automatically selects the necessary
/M and /L dividers.
The global clock line must be driven from an input pin only.
The reference clock input to the receiver PLL can be derived from:
■
■
■
One of the two available dedicated reference clock input pins
(REFCLK0 or REFCLK1) of the associated transceiver block
PLD clock network (must be driven directly from an input clock pin
and cannot be driven by user logic or enhanced PLL)
Inter-transceiver block lines driven by reference clock input pins of
other transceiver blocks
Depending on the functional mode, the Quartus II software automatically
selects the appropriate receiver PLL bandwidth.
Clock Synthesis
The maximum input frequency of the receiver PLL's phase frequency
detector (PFD) is 325 MHz. To achieve a reference clock frequency above
this limitation, the divide by 2 pre-divider on the dedicated local REFCLK
path is automatically enabled by the Quartus II software. This divides the
reference clock frequency by a factor of 2, and the /M PLL multiplier
multiplies this pre-divided clock to yield the configured data rate. For
example, in a situation with a data rate of 2500 Mbps and a reference clock
of 500 MHz, the reference clock must be assigned to the REFCLK port
where the 500 MHz reference clock can be divided by 2, yielding a
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Receiver Channel Architecture
250 MHz clock at the PFD. The VCO runs at half the data rate, so the
selected multiplication factor should yield a 1250 MHz high speed clock.
The Quartus II software automatically selects a multiplication factor of ×5
in this case to generate a 1250 MHz clock from the pre-divided 250 MHz
clock.
If the /2 pre-divider is used, the reference clock must be fed by a
dedicated reference clock input (REFCLK) pin. Otherwise, the Quartus II
compiler gives a Fitter error.
The pre-divider and the multiplication factors are automatically set by the
Quartus II software. The MegaWizard Plug-In Manager takes the data
rate input and provides a list of the available reference clock frequencies
that fall within the supported multiplication factors that you can select.
PPM Frequency Threshold Detector
The PPM frequency threshold detector senses whether the incoming
reference clock to the clock recovery unit (CRU) and the PLL VCO of the
CRU are within a prescribed PPM tolerance range. Valid parameters are
62.5, 100, 125, 200, 250, 300, 500, or 1000 PPM. The default parameter, if no
assignments are made, is 1000 PPM. The output of the PPM frequency
threshold detector is one of the variables that assert the rx_freqlocked
signal. Refer to “Automatic Lock Mode” on page 1–42 for more details
regarding the rx_freqlocked signal.
Receiver Bandwidth Type
The Arria GX receiver PLL in the CRU offers a programmable bandwidth
setting. The PLL bandwidth is the measure of the PLL’s ability to track the
input data and jitter. The bandwidth is determined by the -3dB frequency
of the closed-loop gain of the PLL.
A higher bandwidth setting helps reject noise from the VCO and power
supplies. A low bandwidth setting filters out more high frequency data
input jitter.
Valid receiver bandwidth settings are low, medium, or high. The -3dB
frequencies for these settings vary because of the non-linear nature and
data dependencies of the circuit. You can vary the bandwidth to adjust
and customize the performance on specific systems.
Clock Recovery Unit (CRU)
The CRU (Figure 1–35) in each transceiver channel recovers the clock
from the received serial data stream. You can set the CRU to lock to the
received serial data phase and frequency (lock-to-data mode) to eliminate
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any clock-to-data skew or to keep the receiver PLL locked to the reference
clock (lock-to-reference mode). The switch between lock-to-data and
lock-to-reference modes can be done automatically or manually. The
CRU, in conjunction with the receiver PLL, generates two clocks: a
high-speed serial recovered clock that feeds the deserializer and a
low-speed parallel recovered clock that feeds the receiver’s digital logic.
Figure 1–35. Clock Recovery Unit
/M
rx_pll_locked
Dedicated
REFCLK0
/2
Dedicated
REFCLK1
/2
PFD
rx_cruclk
up
dn
up
dn
Inter-Transceiver Lines[2:0]
CP+LF
VCO
/L
Global Clock (2)
rx_freqlocked
rx_locktorefclk
Clock Recovery Unit (CRU) Control
rx_locktodata
High-Speed Serial Recovered Clock
rx_datain
Low-Speed Parallel Recovered Clock
inactive circuits
active circuits
Notes to Figure 1–35:
(1)
(2)
You only need to select the protocol and the available input reference clock frequency in the Quartus II MegaWizard
Plug-In Manager. Based on your selections, the MegaWizard Plug-In Manager automatically selects the necessary
/M and /L dividers.
The global clock line must be driven from an input pin only.
Automatic Lock Mode
After coming out of reset in automatic lock mode, the CRU initially sets
the receiver PLL to lock to the input reference clock (lock-to-reference
mode). After the receiver PLL locks to the input reference clock, the CRU
automatically sets it to lock to the incoming serial data (lock-to-data
mode) when the following two conditions are met:
■
■
The receiver PLL output clock is within the configured PPM
frequency threshold setting with respect to its reference clock
(frequency locked)
The reference clock and receiver PLL output clock are phase matched
within approximately 0.08 UI (phase locked)
When the receiver PLL and CRU are in lock-to-reference mode, the PPM
detector and the phase detector circuits monitor the relationship of the
reference clock to the receiver PLL VCO output. If the frequency
difference is within the configured PPM setting (as set in the MegaWizard
Plug-In Manager) and the phase difference is within 0.08 UI, the CRU
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switches to lock-to-data mode. The switch from lock-to-reference to
lock-to-data mode is indicated by the assertion of the rx_freqlocked
signal.
In lock-to-data mode, the receiver PLL uses a phase detector to keep the
recovered clock phase-matched to the data. If the PLL does not stay
locked to data due to frequency drift or severe amplitude attenuation, the
CRU switches back to lock-to-reference mode to lock the PLL to the
reference clock. In automatic lock mode, the following condition forces
the CRU to fall out of lock-to-data mode:
The CRU PLL is not within the configured PPM frequency threshold
setting with respect to its reference clock.
The switch from lock-to-data to lock-to-reference mode is indicated by the
de-assertion of rx_freqlocked signal.
When the CRU is in lock-to-data mode (rx_freqlocked is asserted), it
tries to phase-match the PLL with the incoming data. As a result, the
phase of the PLL output clock may differ from the reference clock due to
which rx_pll_locked signal might get de-asserted. You should ignore
the rx_pll_locked signal when the rx_freqlocked signal is asserted
high.
Manual Lock Mode
Two optional input pins (rx_locktorefclk and rx_locktodata)
allow you to control whether the CRU PLL automatically or manually
switches between lock-to-reference mode and lock-to-data mode. This
enables you to bypass the default automatic switchover circuitry if either
rx_locktorefclk or rx_locktodata is instantiated.
When the rx_locktorefclk signal is asserted, the CRU forces the
receiver PLL to lock to the reference clock. When the rx_locktodata
signal is asserted, the CRU forces the receiver PLL to lock-to-data. When
both signals are asserted, the rx_locktodata signal takes precedence
over the rx_locktorefclk signal, forcing the receiver PLL to
lock-to-data.
The PPM threshold frequency detector and phase relationship detector
reaction times may be too long for some applications. You can manually
control the CRU to reduce PLL lock times using the rx_locktorefclk
and rx_locktodata ports. Using the manual mode may reduce the
time it takes for the CRU to switch from lock-to-reference mode to
lock-to-data mode. You can assert the rx_locktorefclk to initially
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train the PLL to the reference clock. Once the receiver PLL locks to the
reference clock, you can assert the rx_locktodata signal to force the
PLL to lock to the incoming data.
When the rx_locktorefclk signal is asserted high, the
rx_freqlocked signal does not have any significance and is always
driven low, indicating that the CRU is in lock-to-reference mode. When
the rx_locktodata signal is asserted high, the rx_freqlocked signal
is always driven high, indicating that the CRU is in lock-to-data mode. If
both signals are de-asserted, the CRU is in automatic lock mode.
Table 1–5 shows a summary of the control signals.
Table 1–5. CRU User Control Lock Signals
rx_locktorefclk
rx_locktodata
CRU Mode
1
0
Lock-to-reference clock
x
1
Lock to data
0
0
Automatic
Deserializer
The deserializer block clocks in serial input data from the receiver buffer
using the high-speed serial recovered clock and deserializes it into 8- or
10-bit parallel data using the low-speed parallel recovered clock. It feeds
the deserialized data to the word aligner as shown in Figure 1–36.
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Figure 1–36. Deserializer
Received Data
D9
D9
D8
D8
D7
D7
D6
D6
D5
D5
D4
D4
D3
D3
D2
D2
D1
D1
D0
D0
10
Clock
Recovery
Unit
To Word
Aligner
High-Speed Serial Recovered Clock
Low-Speed Parallel Recovered Clock
Figure 1–37 shows the serial bit order of the deserializer block input and
the parallel data output of the deserializer block. A serial stream
(0101111100) is deserialized to a value 10'h17C. The serial data is assumed
to be received LSB to MSB.
Figure 1–37. Deserializer Bit Order
Low-Speed Parallel Clock
High-Speed Serial Clock
datain
dataout
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May 2008
0 0 1
1
1
1
1 0
1
0
1
1
0
0
0
0 0
0101111100
1
0
1
1010000011
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Receiver Polarity Inversion
The positive and negative signals of a serial differential link might be
accidentally swapped during board layout. Solutions such as a board
re-spin or major updates to the PLD logic can prove expensive. The
receiver polarity inversion feature is provided to correct this situation.
An optional rx_invpolarity port is available in all modes to
dynamically enable the receiver polarity inversion feature. A high on the
rx_invpolarity port inverts the polarity of every bit of the 8- or 10-bit
input data word to the word aligner in the receiver data path. Since
inverting the polarity of each bit has the same effect as swapping the
positive and negative signals of the differential link, correct data is seen
by the receiver. The rx_invpolarity is a dynamic signal and may
cause initial disparity errors in an 8B/10B encoded link. The downstream
system must be able to tolerate these disparity errors.
The receiver polarity inversion feature is different from the PCI Express
(PIPE) 8B/10B polarity inversion feature. The receiver polarity inversion
feature inverts the polarity of the data bits at the input of the word aligner.
The PCI Express (PIPE) 8B/10B polarity inversion feature inverts the
polarity of the data bits at the input of the 8B/10B decoder and is
available only in PCI Express (PIPE) mode. Enabling the generic receiver
polarity inversion and the PCI Express (PIPE) 8B/10B polarity inversion
simultaneously is not allowed in PCI Express (PIPE) mode.
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Figure 1–38 illustrates the receiver polarity inversion feature.
Figure 1–38. Receiver Polarity Inversion
0
1
1
0
0
1
1
0
1
rx_invpolarity = High
To Word Aligner
0
1
0
1
0
1
0
0
1
0
1
Input to Word Aligner
Output from Deserializer
Word Aligner
The word aligner (refer to Figure 1–39) clocks in received data from the
deserializer using the low-speed recovered clock. It restores the word
boundary of the upstream transmitter based on the pre-defined word
alignment character for the selected protocol. In addition to restoring the
word boundary, the word aligner also implements a synchronization
state machine in all functional modes to achieve lane synchronization.
Figure 1–39 shows the block diagram for the word aligner block.
Figure 1–39. Word Aligner
datain
bitslip
Word
Aligner
enapatternalign
dataout
syncstatus
patterndetect
clock
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The word aligner consists of four sub-modules:
■
■
■
■
Aligner block
Pattern detect block
Manual bit-slip block
Run-length checker
There are two modes in which the word aligner works: basic mode and
automatic synchronization state machine mode. The following sections
explain each of the blocks in each mode of operation. The word aligner
cannot be bypassed and must be used. However, you can use the
rx_enapatternalign port to set the word alignment to not align to the
pattern.
Basic Mode
In basic mode, there are three blocks active in the word aligner:
■
■
■
Pattern detector
Manual word aligner
Automatic synchronization state machine
The pattern detector detects if the pattern exists in the current word
boundary. The manual alignment identifies the alignment pattern across
the byte boundaries and aligns to the correct byte boundary. The
synchronization state machine detects the number of alignment patterns
and good code groups for synchronization and goes out of
synchronization if code group errors (bad code groups) are detected.
Figure 1–40 and Table 1–6 show the supported alignment modes when
basic mode is selected.
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Figure 1–40. Word Aligner Components in Basic Mode
Basic Mode
Manual
Alignment Mode
Pattern Detector
10-Bit
Mode
Bit-Slip
Mode
7-Bit
Mode
Synchronization
State Machines
7-Bit
Mode
10-Bit
Mode
Basic Mode
10-Bit
GIGE
Mode
PIPE Mode
16-Bit
XAUI
Mode
Table 1–6. Word Alignment Modes
Word Alignment
Mode
Effective Mode
Synchronization
state machine
PCI Express, XAUI, GIGE, Serial
RapidIO, or Basic
Automatically controlled to
adhere to the specified
standard or by user entered
parameter
rx_syncstatus
rx_patterndetect
Manual 7- and
10-bit alignment
mode
Alignment to detected pattern
when allowed by the
rx_enapatternalign signal
rx_enapatternalign
rx_syncstatus
rx_patterndetect
Manual
bit-slipping
alignment mode
Manual bit slip controlled by the
PLD logic array
rx_bitslip
rx_patterndetect
Control Signals
Status Signals
Pattern Detector Module
The pattern detector matches a pre-defined alignment pattern to the
current byte boundary. When the pattern detector locates the alignment
pattern, the optional rx_patterndetect signal is asserted for the
duration of one clock cycle to signify that the alignment pattern exists in
the current word boundary. The pattern detector module only indicates
that the signal exists and does not modify the word boundary.
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Modification of the word boundary is discussed in the sections “Manual
Alignment Modes” on page 1–51 and “Synchronization State Machine
Mode” on page 1–55.
In the MegaWizard, you can program a 7-bit or a 10-bit pattern for the
pattern detector to recognize. The pattern used for pattern matching is
automatically derived from the word alignment pattern in the
MegaWizard. For the 7-bit and 10-bit patterns, the actual alignment
pattern specified in the MegaWizard and its complement are checked.
Table 1–7 shows the supported alignment patterns.
Table 1–7. Supported Alignment Patterns
Pattern Detect Mode
Supported Protocols
Pattern Checked
7 bit
Basic, GIGE (enhanced
only)
Actual and complement
10 bit
Basic, XAUI, GIGE, Serial Actual and complement
RapidIO, and PIPE
In 8B/10B encoded data, actual and complement pattern indicates
positive and negative disparities.
7-Bit Pattern Mode
In the 7-bit pattern detection mode (use this mode with 8B/10B code), the
pattern detector matches the seven LSBs of the 10-bit alignment pattern,
which you specified in your ALT2GXB custom megafunction variation, in
the current word boundary. Both positive and negative disparities are
also checked in this mode.
The 7-bit pattern mode can mask out the three MSBs of the data, which
allows the pattern detector to recognize multiple alignment patterns. For
example, in the 8B/10B encoded data, a /K28.5/ (b'0011111010), /K28.1/
(b'0011111001), and /K28.7/ (b'0011111000) share seven common LSBs.
Masking the three MSBs allows the pattern detector to resolve all three
alignment patterns and indicate them on the rx_patterndetect port.
In 7-bit pattern mode, the word aligner still aligns to a 10 bit word
boundary. The specified 7-bit pattern forms the least significant seven bits
of the 10-bit word.
10-Bit Pattern Mode
In the 10-bit pattern detection mode (use this mode with 8B/10B code),
the module matches the 10-bit alignment pattern you specified in your
ALT2GXB custom megafunction variation with the data and its
complement in the current word boundary. Both positive and negative
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disparities are checked by the pattern checker in this mode. For example,
if you specify a /K28.5/ (b'0011111010) pattern as the comma,
rx_patterndetect is asserted if b'0011111010 or b'1100000101 is
detected in the incoming data.
Manual Alignment Modes
The word aligner has two manual alignment modes (7- and 10-bits) when
the transceiver data path is in Basic mode.
7-bit Alignment Mode
In the 7-bit alignment mode (use the 8B/10B encoded data with this
mode), the module looks for the 7-bit alignment pattern you specified in
the MegaWizard Plug-In Manager in the incoming data stream. The 7-bit
alignment mode is useful because it can mask out the three most
significant bits of the data, which allows the word aligner to align to
multiple alignment patterns. For example, in the 8B/10B encoded data, a
/K28.5/ (b'0011111010), /K28.1/ (b'0011111001), and /K28.7/
(b'0011111000) share seven common LSBs. Masking the three MSBs allows
the word aligner to resolve all three alignment patterns synchronized to
it. The word aligner places the boundary of the 7-bit pattern in the LSByte
position with bit positions [0..7]. The true and complement of the patterns
is checked.
Use the rx_enapatternalign port to enable the 7-bit manual word
alignment mode. When the rx_enapatternalign signal is high, the
word aligner detects the specified alignment patterns and realigns the
byte boundary if needed. The rx_syncstatus port is asserted for one
parallel clock cycle to signify that the word boundary was detected across
the current word boundary and has synchronized to the new boundary,
if a rising edge was detected previously on the rx_enapatternalign
port. You must differentiate if the acquired byte boundary is correct,
because the 7-bit pattern can appear between word boundaries. For
example, in the standard 7-bit alignment pattern 7'b1111100, if a K28.7 is
followed by a K28.5, the 7-bit alignment pattern appears on K28.7,
between K28.7 and K28.5, and also again in K28.5 (refer to Figure 1–41).
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Figure 1–41. Cross Boundary 7-Bit Comma When /K28.7 is Followed by /K28.5
K28.7
0
0
1
1
1
1
K28.5
1
0
0
0
7-bit comma-
0
0
1
1
1
1
1
0
1
0
7-bit comma7-bit comma+
Manual 10-Bit Alignment Mode
You can configure the word aligner to align to a 10-bit word boundary.
The internal word alignment circuitry shifts to the correct word boundary
if the alignment pattern specified in the pattern detector is detected in the
data stream.
The rx_enapatternalign port enables the word alignment in the
manual 10-bit alignment mode. When the rx_enapatternalign signal
is high, the word aligner detects the specified alignment pattern and
realigns the byte boundary if necessary. The rx_syncstatus port is
asserted for one parallel clock cycle to signify that the word boundary has
been detected across the word boundary and has synchronized to the
new boundary.
The rx_enapatternalign signal is held high if the alignment pattern
is known to be unique and does not appear across the byte boundaries of
other data. For example, if an 8B/10B encoding scheme guarantees that
the /K28.5/ code group is a unique pattern in the data stream, the
rx_enapatternalign port is held at a constant high.
If the alignment pattern can exist between word boundaries, the
rx_enapatternalign port must be controlled by the user logic in the
PLD to avoid false word alignment. For example, assume that 8B/10B is
used and a /+D19.1/ (b'110010 1001) character is specified as the
alignment pattern. In this case, a false word boundary is detected if a
/-D15.1/ (b'010111 1001) is followed by a /+D18.1/ (b'010011 1001). Refer
to Figure 1–42.
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Figure 1–42. False Word Boundary Alignment if Alignment Pattern Exists Across Word Boundaries, Basic
Mode
+D18.1
- D15.1
…..
0
1
0
1
1
1
1
0
0
1
0
1
0
0
1
1
1
0
0
1
…..
+D19.1
In this example, the rx_enapatternalign signal is deasserted after the
word aligner locates the initial word alignment to prevent false word
boundary alignment. When the rx_enapatternalign signal is
deasserted, the current word boundary is locked even if the alignment
pattern is detected across different boundaries. In this case, the
rx_syncstatus acts as a re-synchronization signal to signify that the
alignment pattern was detected, but the boundary is different than the
current boundary. You must monitor this signal and reassert the
rx_enapatternalign signal if realignment is desired.
Figure 1–43 shows an example of how the word aligner signals interact in
10-bit alignment mode. In this example, a /K28.5/ (10'b0011111010) is
specified as the alignment pattern. The rx_enapatternalign signal is
held high at time n, so alignment occurs whenever an alignment pattern
exists in the pattern. The rx_patterndetect signal is asserted for one
clock cycle to signify that the pattern exists on the re-aligned boundary.
The rx_syncstatus signal is also asserted for one clock cycle to signify
that the boundary has been synchronized. At time n + 1, the
rx_enapatternalign signal is deasserted to instruct the word aligner
to lock the current word boundary.
The alignment pattern is detected at time n + 2, but it exists on a different
boundary than the current locked boundary. The bit orientation of the
Arria GX device is LSB to MSB, so the alignment pattern exists across time
n + 2 and n + 3 (refer to Figure 1–43). In this condition the
rx_patterndetect remains low because the alignment pattern does
not exist on the current word boundary, but the rx_syncstatus signal
is asserted for one clock cycle to signify a resynchronization condition.
This means that the alignment pattern has been detected across another
word boundary.
The user logic design in the PLD must decide whether or not to assert the
rx_enapatternalign to reinitiate the word alignment process. At time
n + 5 the rx_patterndetect signal is asserted for one clock cycle to
signify that the alignment pattern has been detected on the current word
boundary.
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Figure 1–43. Word Aligner Symbol Interaction in 10-Bit Manual Alignment Mode
n
n+1
n+2
n+3
n+4
n+5
1111001010
1000000101
111110000
0101111100
rx_clkout
rx_dataout[10..0]
111110000
0101111100
111110000
rx_enapatternalign
rx_patterndetect
rx_syncstatus
Manual Bit-Slip Alignment Mode
You can also achieve word alignment by enabling the manual bit-slip
option in the MegaWizard Plug-In Manager. With this option enabled, the
transceiver shifts the word boundary MSB to LSB one bit every parallel
clock cycle. The transceiver shifts the word boundary every time the bitslipping circuitry detects a rising edge of the rx_bitslip signal. At each
rising edge of the rx_bitslip signal, the word boundary slips one bit.
The bit that arrives at the receiver first is skipped. When the word
boundary matches the alignment pattern you specified in the
MegaWizard Plug-In Manager, the rx_patterndetect signal is
asserted for one clock cycle. You must implement the logic in the PLD
logic array to control the bit-slip circuitry.
The bit slipper is useful if the alignment pattern changes dynamically
when the Arria GX device is in user mode. You can implement the
controller in the logic array, so you can build a custom controller to
dynamically change the alignment pattern without needing to reprogram
the Arria GX device.
Figure 1–44 shows an example of how the word aligner signals interact in
the manual bit slip alignment mode. For this example, 8'b00111100 is
specified as the alignment pattern and an 8'b11110000 value is held at the
rx_datain port.
Every rising edge on the rx_bitslip port causes the rx_dataout data
to shift one bit from the MSB to the LSB by default. This is shown at time
n + 2 where the 8'b11110000 data is shifted to a value of 8'b01111000. At
this state the rx_patterndetect signal is held low because the
specified alignment pattern does not exist in the current word boundary.
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The rx_bitslip is disabled at time n + 3 and re-enabled at time n + 4.
The output of the rx_dataout now matches the specified alignment
pattern, thus the rx_patterndetect signal is asserted for one clock
cycle. At time n + 5, the rx_patterndetect signal is still asserted
because the alignment pattern still exists in the current word boundary.
Finally, at time n + 6 the rx_dataout boundary is shifted again and the
rx_patterndetect signal is deasserted to signify that the word
boundary does not contain the alignment pattern.
Figure 1–44. Word Aligner Symbol Interaction in Manual Bit-Slip Mode
n
n+1
n+2
n+3
n+4
n+5
n+6
rx_clkout
00001111
rx_datain
rx_dataout[7..0]
11110000
01111000
00111100
00011110
rx_bitslip
rx_patterndetect
Synchronization State Machine Mode
You can choose to have the link synchronization handled by a state
machine. Unlike the manual alignment mode where there is no built-in
hysteresis to go into or fall out of synchronization, the synchronization
state machine offers automatic detection of a valid number of alignment
patterns and synchronization and detection of code group errors for
automatically falling out of synchronization. The synchronization state
machine is available in the Basic, XAUI, GIGE, and PIPE modes. For the
XAUI, GIGE, and PIPE modes, the number of alignment patterns,
consecutive code groups, and bad code groups are fixed. You must use
the 8B/10B code for the synchronization state machine. In XAUI, GIGE,
and PIPE modes, the 8B/10B encoder/decoder is embedded in the
transceiver data path. In Basic mode, you can configure the MegaWizard
Plug-In Manager to either use or bypass the 8B/10B encoder/decoder in
the transceiver. If the synchronization state machine is enabled and the
8B/10B encoder/decoder is bypassed, the 8B/10B encoder/decoder logic
must be implemented outside the transceiver as a requirement for using
the synchronization state machine.
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In Basic mode, you can configure the state machine to suit a variety of
standard and custom protocols. In the MegaWizard Plug-In Manager, you
can program the number of alignment patterns to acquire link
synchronization. You can program the number of bad code groups to fall
out of synchronization. You can program the number of good code
groups to negate a bad code group. You enter these values in the
MegaWizard Plug-In Manager. The rx_syncstatus port indicates the
link status. A high level indicates link synchronization is achieved, a low
level indicates that synchronization has not yet been achieved or that
there were enough code group errors to fall out of synchronization.
Figure 1–45 shows a flowchart of the synchronization state machine.
Figure 1–45. Word Aligner Synchronization State Machine Flow Chart
Loss of Sync
Data= Comma
Data= !Valid
Comma Detect
if Data == comma
kcntr++
else
kcntr=kcntr
Data=valid;
kcntr<3
kcntr = 3
Synchronized
Data=valid
Data= !Valid
ecntr = 17
Synchronized Error
Detect
if Data == !valid
ecntr++
gcntr=0
else if gcntr==16
ecntr- gcntr=0
else
gcntr++
ecntr = 0
The maximum value for the number of valid alignment patterns and
good code groups is 256. The maximum value of invalid or bad code
groups to fall out of synchronization is 8. For example, if 3 is set for the
number of good code groups, then when 3 consecutive good code groups
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are detected after a bad code group, the effect of the bad code group on
synchronization is negated. This does not negate the bad code group that
actually triggers the loss of synchronization. To negate a loss of
synchronization, the protocol defined number of alignment patterns
must be received.
When either XAUI or GIGE mode is used, the synchronization and word
alignment is handled automatically by a built-in state machine that
adheres to either the IEEE 802.3ae or IEEE 802.3 synchronization
specifications, respectively. If you specify either standard, the alignment
pattern is automatically defaulted to /K28.5/ (b'0011111010).
When you specify the XAUI protocol, code-group synchronization is
achieved upon the reception of four /K28.5/ commas. Each comma can
be followed by any number of valid code groups. Invalid code groups are
not allowed during the synchronization stage. When code-group
synchronization is achieved the optional rx_syncstatus signal is
asserted.
f
For more information about the operation of the synchronization phase,
refer to clause 47-48 of the IEEE P802.3ae standard or XAUI mode in the
Arria GX Transceiver Protocol Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook.
If you specify the GIGE protocol, code-group synchronization is achieved
upon the reception of three consecutive ordered sets. An ordered set
starts with the /K28.5/ comma and can be followed by an odd number of
valid data code groups. Invalid code groups are not allowed during the
reception of three ordered-sets. When code-group synchronization is
achieved, the optional rx_syncstatus signal is asserted.
In PIPE mode, lane synchronization is achieved when the word aligner
sees four good /K28.5/ commas and 16 good code groups. This is
accomplished through the reception of four good PCI Express training
sequences (TS1 or TS2). The PCI-Express fast training sequence (FTS) can
also be used to achieve lane or link synchronization, but requires at least
five of these training sequences. The rx_syncstatus signal is asserted
when synchronization is achieved and is deasserted when the word
aligner receives 23 code group errors.
Run Length Checker
The programmable run-length violation circuit resides in the word
aligner block and detects consecutive 1s or 0s in the data. If the data
stream exceeds the preset maximum number of consecutive 1s or 0s, the
violation is signified by the assertion of the rx_rlv signal.
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This signal is not synchronized to the parallel data and appears in the
logic array earlier than the run-length violation data. To ensure that the
PLD can latch this signal in systems where there are frequency variations
between the recovered clock and the PLD logic array clock, the rx_rlv
signal is asserted for a minimum of two clock cycles. The rx_rlv signal
may be asserted longer, depending on the run-length of the received data.
The run-length violation circuit detects up to a run length of 128 (for an
8-bit deserialization factor) or 160 (for a 10-bit deserialization factor). The
settings are in increments of 4 or 5 for the 8-bit or 10-bit deserialization
factors, respectively.
Receiver Bit Reversal
By default, the Arria GX receiver assumes an LSB to MSB transmission. If
the transmission order is MSB to LSB, then the receiver will put out the
bit-flipped version of the data on the PLD interface. The Receiver Bit
Reversal feature is available to correct this situation.
The Receiver Bit Reversal feature is available only in Basic mode. If the
Receiver Bit Reversal feature is enabled, the 10-bit data D[9:0] at the
output of the word aligner gets rewired to D[0:9]. Flipping the parallel
data using this feature allows the receiver to put out the correctly
bit-ordered data on the PLD interface in case of MSBit to LSBit
transmission.
Because the receiver bit reversal is done at the output of the word aligner,
a dynamic bit reversal would also require a reversal of word alignment
pattern. As a result, the Receiver Bit Reversal feature is dynamic only if
the receiver uses manual bit-slip alignment mode (no word alignment
pattern). The Receiver Bit Reversal feature is static in all other Basic mode
configurations and can be enabled through the MegaWizard Plug-In
Manager. In configurations where this feature is dynamic, an
rx_revbitordwa port is available to control the bit reversal
dynamically. A high on the rx_revbitordwa port reverses the bit order
at the input of the word aligner.
Figure 1–46 illustrates the receiver bit reversal feature in Basic 10-bit wide
data path configuration.
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Figure 1–46. Receiver Bit Reversal in Basic Mode
D[9]
D[0]
D[8]
D[1]
D[7]
D[2]
D[6]
D[3]
D[5]
RX Bit Reversal = Enabled
D[4]
D[4]
D[5]
D[3]
D[6]
D[2]
D[7]
D[1]
D[8]
D[0]
D[9]
Output of Word Aligner before
RX bit reversal
Output of Word Aligner after RX
bit reversal
Channel Aligner (Deskew)
The channel aligner is automatically used when implementing the XAUI
protocol to ensure that the channels are aligned with respect to each other.
The channel aligner uses a 16-word deep FIFO buffer and is available
only in the XAUI mode.
f
For additional information about the Channel Aligner block, refer to the
Arria GX Transceiver Protocol Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook.
Rate Matcher
In asynchronous systems, the upstream transmitter and the local receiver
may be clocked with independent reference clock sources. Frequency
differences in the order of a few hundred PPM can potentially corrupt the
data at the receiver. The rate matcher compensates for small clock
frequency differences between the upstream transmitter and the local
receiver clocks by inserting or removing skip characters or ordered-sets
from the inter-packet gap (IPG) or idle streams. It inserts a skip character
or ordered-set if the local receiver is running a faster clock than the
upstream transmitter. It deletes a skip character or ordered-set if the local
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receiver is running a slower clock than the upstream transmitter. The rate
matcher is available in PCI Express (PIPE), GIGE, XAUI, and Basic
functional modes.
The rate matcher consists of a 20-word-deep FIFO buffer and necessary
logic to detect and perform the insertion and deletion functions. The write
port of the rate matcher FIFO is clocked by the low-speed parallel
recovered clock. The read port is clocked by the low-speed parallel clock
from the CMU central or local clock divider block (Figure 1–47).
Figure 1–47. Rate Matcher
dataout[9:0]
datain[9:0]
Rate Matcher
To 8B/10B
Decoder
From Word Aligner
wrclk
Low-Speed Parallel
Recovered Clock
from CRU
f
rdclk
Low-Speed Parallel
CMU Clock
CMU
Local/Central Clock
Divider Block
For information about the rate matcher in PIPE, GIGE, and XAUI modes,
refer to the Arria GX Transceiver Protocol Support and Additional Features
chapter in volume 2 of the Arria GX Device Handbook.
Basic Mode General Rate Matching
In Basic mode, the rate matcher supports up to 300 PPM differences
between the upstream transmitter and the receiver. The rate matcher
looks for the skip ordered set (SOS), which is a /K28.5/ comma followed
by three programmable neutral disparity skip characters (for example,
/K28.0/). For general rate matching, you can customize the SOS to
support a variety of protocols, including custom protocols. The SOS must
contain a valid control code group (Kx.y), followed by any neutral
disparity skip code group (any Kx.y or Dx.y of neutral disparity, for
example, K28.0). The rate matcher deletes or inserts skip characters when
necessary to prevent the rate matching FIFO buffer from overflowing or
underflowing.
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The rate matcher in Basic mode can delete any number of skip characters
as necessary in a cluster as long as there are skip characters to delete.
There are no restrictions regarding deleting more than one skip character
in a cluster of skip characters. Figure 1–48 shows an example of a Basic
mode rate matcher deletion of two skip characters. Although the skip
characters are programmable, the /K28.0/ control group is used for
illustration purposes.
Figure 1–48. Basic Mode Deletion of Two Skip Characters
clock
datain
K28.5
K28.0
K28.0
K28.0
Dx.y
K28.5
K28.0
K28.0
dataout
K28.5
K28.0
Dx.y
K28.5
K28.0
K28.0
Dx.y
Dx.y
Two Skips Deleted
The rate matcher inserts skip characters as required for rate matching. For
a given skip ordered set, the rate matcher inserts skip characters so that
the total number of consecutive skip characters does not exceed five at the
output of the rate matching FIFO buffer. Figure 1–49 shows an example
where a skip character insertion is made on the second set of skip ordered
sets because the first set has the maximum number of skip characters.
Figure 1–49. Basic Mode Insertion of a Skip Character
One Skip Inserted
One Skip Inserted
clock
datain
K28.5
K28.0
K28.0
K28.0
K28.0
K28.0
Dx.y
K28.5
K28.0
Dx.y
dataout
K28.5
K28.0
K28.0
K28.0
K28.0
K28.0
Dx.y
K28.5
K28.0
K28.0
The Arria GX rate matcher in Basic mode has FIFO buffer overflow and
underflow protection. In the event of a FIFO buffer overflow the rate
matcher deletes any data after the overflow condition to prevent FIFO
buffer pointer corruption until the rate matcher is not full. In an
underflow condition, the rate matcher inserts 9'h1FE (/K30.7) until the
FIFO buffer is not empty. These measures ensure that the FIFO buffer
gracefully exits the overflow and underflow condition without requiring
a FIFO buffer reset.
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8B/10B Decoder
The 8B/10B decoder takes in 10-bit data from the rate matcher and
decodes it into 8-bit data + 1-bit control identifier, thereby restoring the
original transmitted data at the receiver. The decoded data is fed to either
the byte deserializer or the receiver phase compensation FIFO buffer
(depending on protocol). The 8B/10B decoder conforms to IEEE 802.3
1998 edition standards.
Figure 1–50 shows a 10-bit code group decoded to an 8-bit data and a 1-bit
control indicator.
Figure 1–50. 10-Bit to 8-Bit Conversion
j
h
g
f
i
e
d
c
b
a
9
8
7
6
5
4
3
2
1
0
MSB Received Last
LSB Received First
8B/10B Conversion
ctrl
7
6
5
4
3
2
1
0
H
G
F
E
D
C
B
A
Parallel Data
Control Code Group Detection
The 8B/10B decoder differentiates between data and control codes
through the rx_ctrldetect port. If the received 10-bit code group is a
control code group (Kx.y), the rx_ctrldetect signal is driven high. If
it is a data code group (Dx.y), the rx_ctrldetect signal is driven low.
Figure 1–51 shows an example waveform demonstrating the receipt of a
K28.5 code group (BC + ctrl). The rx_ctrldetect=1'b1 is aligned with
8'hbc, indicating that it is a control code group. The rest of the codes
received are Dx.y code groups.
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Receiver Channel Architecture
Figure 1–51. Control Code Group Detection
clock
dataout[7..0 ]
83
78
BC
BC
0F
00
BF
3C
D3.4
D24.3
D28.5
K28.5
D15.0
D0.0
D31.5
D28.1
ctrldetect
Code Group
Code Group Error Detection
If the received 10-bit code group is not a part of valid Dx.y or Kx.y code
groups, the 8B/10B decoder block asserts an error flag on the
rx_errdetect port. The error flag signal (rx_errdetect) has the
same data path delay from the 8B/10B decoder to the PLD-transceiver
interface as the invalid code group.
In GIGE, XAUI, and PIPE modes, the invalid code is replaced by a
/K30.7/ code (8'hFE on rx_dataout + 1'b1 on rx_ctrldetect). In all
other modes, the value of the invalid code value can vary and should be
ignored
Disparity Error Detection
If the received 10-bit code group is detected with incorrect running
disparity, the 8B/10B decoder block asserts an error flag on the
rx_disperr and rx_errdetect ports.
f
Refer to the Specifications and Additional Information chapter in volume 2
of the Arria GX Device Handbook for information about the disparity
calculation.
If negative disparity is calculated for the last 10-bit code group, a neutral
or positive disparity 10-bit code group is expected. If the 8B/10B decoder
does not receive a neutral or positive disparity 10-bit code group, the
rx_disperr signal goes high, indicating that the code group received
has a disparity error. Similarly, if a neutral or negative disparity is
expected and a 10-bit code group with positive disparity is received, the
rx_disperr signal goes high.
The detection of the disparity error might be delayed, depending on the
data that follows the actual disparity error. The 8B/10B control codes
terminate propagation of the disparity error. Any disparity errors
propagated stop at the control code group, terminating that disparity
error.
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In GIGE and XAUI modes, the code that contains a disparity error is
replaced by a /K30.7/ code (8'hFE on rx_dataout + rx_ctrldetect).
In all other modes, the code with incorrect disparity should be treated as
an invalid code and ignored.
Figure 1–52 shows a case where the disparity is violated. A K28.5 code
group has an 8-bit value of 8'hbc and a 10-bit value that depends on the
disparity calculation at the point of the generation of the K28.5 code
group. The 10-bit value is 10'b0011111010 (10'h17c) for RD– or
10'b1100000101 (10'h283) for RD+. If the running disparity at time n - 1 is
negative, the expected code group at time must be from the RD– column.
A K28.5 does not have a balanced 10-bit code group (equal number of 1s
and 0s), so the expected RD code group must toggle back and forth
between RD– and RD+. At time n + 3, the 8B/10B decoder received a RD+
K28.5 code group (10'h283), which makes the current running disparity
negative. At time n + 4, because the current disparity is negative, a K28.5
from the RD– column is expected, but a K28.5 code group from the RD+
is received instead. This prompts rx_disperr to go high during time
n + 4 to indicate that this particular K28.5 code group had a disparity
error. The current running disparity at the end of time n + 4 is negative
because a K28.5 from the RD+ column was received. Based on the current
running disparity at the end of time n + 5, a positive disparity K28.5 code
group (from the RD–) column is expected at time n + 5.
Figure 1–52. Disparity Error Detection
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
BC
BC
BC
BC
xx
BC
BC
BC
Expected RD Code
RD-
RD+
RD-
RD+
RD-
RD-
RD+
RD-
RD Code Received
RD-
RD+
RD-
RD+
RD+
RD-
RD+
RD-
rx_datain
17C
283
17C
283
283
17C
283
17C
clock
rx_dataout[7..0 ]
rx_disperr
rx_errdetect
rx_ctrldetect
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Reset Condition
The reset for the 8B/10B decoder block is derived from the receiver digital
reset (rx_digitalreset). When rx_digitalreset is asserted, the
8B/10B decoder block resets. In reset, the disparity registers are cleared
and the outputs of the 8B/10B decoder block are driven low. After reset,
the 8B/10B decoder starts with unknown disparity, depending on the
disparity of the data it receives. The decoder calculates the initial running
disparity based on the first valid code group received.
1
The receiver block must be word aligned after reset before the
8B/10B decoder can decode valid data or control codes. If word
alignment has not been achieved, the data from the 8B/10B
decoder should be considered invalid and discarded.
Polarity Inversion
The 8B/10B decoder has a PCI Express compatible polarity inversion on
the data bus prior to 8B/10B decoding. This polarity inversion inverts the
bits of the incoming data stream prior to the 8B/10B decoding block to fix
potential P-N polarity inversion on the differential input buffer. You use
the optional pipe8b10binvpolarity port to invert the inputs to the
8B/10B decoder dynamically from the PLD.
Byte Deserializer
The byte deserializer (Figure 1–53) takes in 8- or 10-bit wide data from the
8B/10B decoder and deserializes it into 16- or 20-bit wide data at half the
speed. This allows clocking the PLD-transceiver interface at half the
speed as compared to the receiver PCS logic. The byte deserializer is
bypassed in GIGE mode.
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Figure 1–53. Byte Deserializer
dataout[15:0]
datain[7:0]
Byte
Deserializer
From 8B/10B
Decoder
To receiver phase
compensation
wrclk
rdclk
FIFO
/2
Low -speed parallel recovered
clock from CRU (1) or Low -speed
parallel CMU clock (2)
Notes to Figure 1–53:
(1)
(2)
Write port is clocked by low-speed parallel recovered clock if rate matcher is not used.
Write port is clocked by low-speed parallel CMU clock if rate matcher is used.
If the byte deserializer is used, the byte ordering at the receiver output
might be different than what was transmitted. Figure 1–54 shows the
16-bit transmitted data pattern with A at the lower byte, followed by B at
the upper byte. C and D follow in the next lower and upper bytes,
respectively. At the byte deserializer, byte A arrives when it is stuffing the
upper byte instead of stuffing the lower byte. This is a non-deterministic
swap because it depends on PLL lock times and link delay. Implement
byte-ordering logic in the PLD to correct this situation.
Figure 1–54. Intended Transmitted Pattern and Incorrect Byte Position at
Receiver After Byte Serializer
X
B
D
A
C
X
X
A
C
X
B
D
Intended Transmitted
Pattern
Incorrect Byte Position
at Receiver
Receiver Phase Compensation FIFO Buffer
The receiver phase compensation FIFO buffer (Figure 1–55) is located at
the FPGA logic array interface in the receiver block and is used to
compensate for phase difference between the receiver clock and the clock
from the PLD. The receiver phase compensation FIFO buffer operates in
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two modes: low latency and high latency. In low latency mode, the FIFO
buffer is four words deep. The Quartus II software chooses the low
latency mode automatically for every mode except the PCI-Express PIPE
mode (which automatically uses high latency mode). In high latency
mode, the FIFO buffer is eight words deep.
Figure 1–55. Receiver Phase Compensation FIFO Buffer
Receiver Channel
rx_dataout[]
datain[ ]
From Byte
Deserializer or
8B/10B Decoder
Low-Speed Parallel
Recovered Clock (1) or
Low-Speed Parallel
CMU Clock (2)
Receiver Phase
Compensation
FIFO
wrclk
To PLD or PIPE
interface
rdclk
rx_coreclk
/2
rx_clkout or
tx_clkout or
coreclkout
Notes to Figure 1–55:
(1)
(2)
Write port is clocked by low-speed parallel recovered clock when rate matcher is not used.
Write port is clocked by low-speed parallel CMU clock when rate matcher is used.
In Basic mode, the write port is clocked by the recovered clock from the
CRU. This clock is half the rate if the byte deserializer is used. The read
clock is clocked by the associated channel’s recovered clock.
1
The receiver phase compensation FIFO is always used and
cannot be bypassed.
In four-channel (×4) bonding mode, all the read pointers are derived from
a common source so that there is no need to synchronize the data of each
channel in the PLD logic.
Receiver Phase Compensation FIFO Error Flag
Depending on the transceiver configuration, the write port of the receiver
phase compensation FIFO can be clocked by either the recovered clock
(rx_clkout) or transmitter PLL output clock (tx_clkout or
coreclkout). The read port can be clocked by the recovered clock
(rx_clkout), transmitter PLL output clock (tx_clkout or
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coreclkout) or a PLD clock. In all configurations, the write clock and
the read clock must have 0 PPM difference to avoid overrun/underflow
of the phase compensation FIFO.
An optional debug_rx_phase_comp_fifo_error port is available in
all modes to indicate receiver phase compensation FIFO
overrun/underflow condition. debug_rx_phase_comp_fifo_error
is asserted high when the phase compensation FIFO gets either full or
empty. This feature is useful to verify the phase compensation FIFO
overrun/underflow condition as a probable cause of link errors.
PLD-Transceiver
Interface
Clocking
The transmitter phase compensation FIFO present at each channel’s
PLD-transmitter interface compensates for the phase difference between
the PLD clock that produces the data to be transmitted and the
transmitter PCS clock. The receiver phase compensation FIFO present at
each channel’s PLD-receiver interface compensates for the phase
difference between the PLD clock that processes the received data and the
receiver PCS clock.
Depending on the functional mode, the Quartus II software automatically
selects appropriate clocks to clock the read port of the transmitter phase
compensation FIFO and the write port of the receiver phase
compensation FIFO.
The write clock of the transmitter phase compensation FIFO and the read
clock of the receiver phase compensation FIFO are part of the
PLD-transceiver interface clocks. Arria GX transceivers provide the
following two options for selecting these PLD-transceiver interface
clocks:
■
■
Automatic Phase Compensation FIFO clock selection
User Controlled Phase Compensation FIFO clock selection
The automatic phase compensation FIFO clock selection is a simpler
option, but could lead to higher clock resource utilization as compared to
user controlled phase compensation FIFO clock selection. This could be
critical in designs with high clock resource requirements.
Automatic Phase Compensation FIFO Clock Selection
If you do not instantiate the tx_coreclk and rx_coreclk ports for the
Arria GX transceiver instance in the MegaWizard Plug-In Manager, the
Quartus II software automatically selects appropriate clocks to clock the
write port of the transmitter phase compensation FIFO and the read clock
of the receiver phase compensation FIFO.
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Table 1–8 lists the clock sources that the Quartus II software automatically
selects for the transmitter and receiver phase compensation FIFOs,
depending on the functional mode.
Table 1–8. Clock Sources for the Transmitter and Receiver Phase Compensation FIFOs
Write port clock selection for
Transmitter Phase Compensation
FIFO
Functional Mode
Read port clock selection for
Receiver Phase Compensation
FIFO
Individual-channel mode with rate
matcher
tx_clkout[0] from channel 0
clocks the FIFO write port in all
channels in the same transceiver
block.
tx_clkout[0] from channel 0
clocks the FIFO read port in all
channels in the same transceiver
block.
Individual-channel mode without
rate matcher
tx_clkout[0] from channel 0
clocks the FIFO write port in all
channels in the same transceiver
block.
rx_clkout from each channel
clocks the FIFO read port of its
associated channel.
Bonded-channel mode with/without
rate matcher
coreclkout clocks the FIFO
coreclkout clocks the FIFO read
write port in all channels in the same port in all channels in the same
transceiver block.
transceiver block.
In an individual-channel mode without rate matcher (Serial RapidIO), a
total of five global/regional clock resources per transceiver block are used
by the PLD-transceiver interface clocks. Four clock resources are used by
the rx_clkout signal of each channel being routed back to clock the read
port of its receiver phase compensation FIFO. One clock resource is used
by the tx_clkout[0] signal of Channel 0 being routed back to clock the
write port of all transmitter phase compensation FIFOs in the transceiver
block.
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Figure 1–56 shows the minimum PLD-Interface clock utilization per
transceiver block when configured in individual-channel mode without
the rate matcher.
Figure 1–56. Minimum PLD-Interface Clock Utilization Per Transceiver Block Without the Rate Matcher
PLD
XCVR
Channel 3
RX Phase
Comp FIFO
rx_clkout[3]
TX Phase
Comp FIFO
tx_clkout[0]
RX
CRU
TX
TX CLK
Div Block
Channel 2
RX Phase
Comp FIFO
rx_clkout[2]
TX Phase
Comp FIFO
tx_clkout[0]
RX
CRU
TX
TX CLK
Div Block
Channel 1
RX Phase
Comp FIFO
rx_clkout[1]
TX Phase
Comp FIFO
tx_clkout[0]
RX
CRU
TX
TX CLK
Div Block
Channel 0
RX Phase
Comp FIFO
rx_clkout[0]
TX Phase
Comp FIFO
RX
CRU
TX
TX CLK
Div Block
tx_clkout[0]
The PLD-transceiver clock utilization can be reduced by driving the
transmitter and receiver phase compensation FIFOs with a single clock.
This is possible only if the driving clock is frequency-locked to the
transceiver output clocks (tx_clkout, coreclkout, or rx_clkout).
To control the write and read clock selection for the transmitter and
receiver phase compensation FIFO, you must instantiate the
tx_coreclk and rx_coreclk ports for the transceiver channels.
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User Controlled Phase Compensation FIFO Clock Selection
Instead of the Quartus II software automatically selecting the write and
read clocks of the transmitter and receiver phase compensation FIFOs,
respectively, you can manually connect appropriate clocks by
instantiating the tx_coreclk and rx_coreclk ports in the
MegaWizard Plug-In Manager. For all like channels configured in the
same functional mode and running off the same clock source, you can
connect the tx_coreclk and rx_coreclk ports of all channels together
and drive them using the same clock source. You can use a PLD clock
input pin or a transceiver clock
(tx_clkout[0]/coreclkout/rx_clkout) to clock the
tx_coreclk/rx_coreclk ports (Figure 1–57).
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Figure 1–57. User Controlled Phase Compensation FIFO Clock
Channel 3
RX Phase
Comp FIFO
RX
CRU
rx_coreclk[3]
TX Phase
Comp FIFO
TX
TX CLK
Div Block
tx_coreclk[3]
Channel 2
RX Phase
Comp FIFO
RX
CRU
rx_coreclk[2]
TX Phase
Comp FIFO
tx_coreclk[2]
TX
TX CLK
Div Block
Channel 1
RX Phase
Comp FIFO
RX
CRU
rx_coreclk[1]
TX Phase
Comp FIFO
TX
TX CLK
Div Block
tx_coreclk[1]
Channel 0
RX Phase
Comp FIFO
RX
CRU
rx_coreclk[0]
tx_coreclk[0]
To user
logic
TX Phase
Comp FIFO
TX
TX CLK
Div Block
tx _clkout[0]
1
If the rx_clkout signal is used as a driver, it can only drive the
rx_coreclk ports. It cannot drive the tx_coreclk ports. If
tx_coreclk and rx_coreclk need to be driven with the
same clock, you must use the tx_clkout signal as the clock
driver.
If the clock signal on tx_coreclk is used to clock the write side of the
transmitter phase compensation FIFO, you must make sure that it is
frequency locked to the transmitter PCS clock reading from the FIFO. If
the clock signal on rx_coreclk is used to clock the read side of the
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receiver phase compensation FIFO, you must make sure that it is
frequency locked to the receiver PCS clock writing into the FIFO. Any
frequency differences may cause data corruption.
To help guard against incorrect usage, the use of the tx_coreclk and
rx_coreclk options requires clock assignments in the assignment
organizer. If no assignments are used, the Quartus II software will issue a
compilation error.
There are four settings to enable the PLD interface clocking options:
■
■
■
■
Stratix II GX/Arria GX GXB Shared Clock Group Setting
Stratix II GX/Arria GX GXB Shared Clock Group Driver Setting
Stratix II GX/Arria GX 0PPM Clock Group Setting
Stratix II GX/Arria GX 0PPM Clock Group Driver Setting
There are two main settings, Shared Clock and 0 PPM Clock, each with a
driver and clock group setting. When specifying clock groups, an integer
identifier is used as the group name to differentiate the different clock
group settings from each another.
The Stratix II GX/Arria GX GXB Shared Clock Group Setting is the
safest assignment. The Quartus II compiler analyzes the netlist during
compilation to ensure transmitter channel members are derived from the
same source. The Quartus II software gives a fitting error for
incompatible assignments. The software cannot check for the output of
the receiver frequency locked to the driving clock as the exact frequency
is dictated by the upstream transmitter’s source clock. You must ensure
that the rx_coreclk is derived from the same source clock as the
upstream transmitter.
The Stratix II GX/Arria GX GXB Shared Clock Group Driver Setting
assignment must be made to the source channel of the tx_clkout or
coreclkout. Specifying anything but the transmitter channels (the
source for the tx_clkout or coreclkout) results in a Fitter error. If the
source clock is not from tx_clkout or coreclkout (for example, the
source is from rx_clkout or from a PLD clock input), the 0 PPM setting
must be used instead.
For example, in a synchronous system, the transmitter and receiver are
running off the same clock. To make tx_clkout[0] the clock driver, the
Stratix II GX/Arria GX GXB Shared Clock Group Driver Setting is made
in the assignment editor on the tx_dataout[0] name. You can use a
group identifier value of “1” to identify the group that this driver feeds.
The Stratix II GX/Arria GX GXB Shared Clock Group Setting is made to
all the rx_datain channels that the tx_dataout[0] output clock
drives.
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Arria GX Transceiver Architecture
1
The other tx_dataout channels do not need an assignment
because the Quartus II software automatically groups the like
transmitters in a transceiver block. A group identifier value of
“1” is also made to the rx_datain assignments.
The assignments in the Assignment Editor are shown in Table 1–9.
Table 1–9. Assignment Editor
To:
tx_dataout[0]
Assignment name:
Stratix II GX/Arria GX GXB Shared Clock Group Driver
Setting
Value:
1
To:
rx_datain[] (note that the [] signifies the entire
rx_datain group)
Assignment name:
Stratix II GX/Arria GX GXB Shared Clock Group Setting
Value:
1
The Stratix II GX/Arria GX 0PPM Clock Group Setting is for more
advanced users that know the clocking configuration of the entire system
and want to reduce the PLD global clock resource and PLD interface clock
resource utilization. The Quartus II compiler does not perform any
checking on the clock source. It is up to you to ensure that there is no
frequency difference from the associated transceiver clock of the group
and the driving clock to the tx_coreclk and rx_coreclk ports.
The Stratix II GX/Arria GX 0PPM Clock Group Driver Setting can be
used with any of the transceiver output clocks (tx_clkout, rx_clkout,
and coreclkout) as well as any PLD clock input pins, transceiver
dedicated REFCLK pin, or PLD PLL output. User logic cannot be used as
a driver. As with the shared clock group setting, the driver setting for the
transceiver output clocks is made to the associated channel. For example,
for tx_clkout or coreclkout, the transmitter channel name is
specified. When the rx_clkout is the driver, the receiver channel name
of the associated rx_clkout is specified. For the PLD input clock pins
and the transceiver REFCLK pins, the name of the clock pin can be
specified. For the PLL output, the PLL clock output port of the PLL can be
found in the Node Finder and entered as the driver name. An integer
value is specified for the group identification.
The Stratix II GX/Arria GX 0PPM Clock Group Setting is made to the
transmitter or receiver channel names.
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May 2008
Loopback Modes
The assignments in the Assignment Editor are shown in Table 1–10.
Table 1–10. Assignment Editor
f
Loopback Modes
To:
tx_dataout[0], pld_clk_pin_name,
refclk_pin, and pll_outclk
Assignment name:
Stratix II GX/Arria GX GXB 0PPM Clock Group Driver
Setting
Value:
1
To:
rx_datain[] and tx_dataout[]
Assignment name:
Stratix II GX/Arria GX GXB 0PPM Clock Group Setting
Value:
1
For a complete set of features supported in each protocol, refer to the
Arria GX Transceiver Protocol Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook.
There are several loopback modes available on the Arria GX transceiver
block that allow you to isolate portions of the circuit. All paths are
designed to run up to full speed. The available loopback paths are:
■
■
■
■
Serial loopback available in all functional modes except PCI Express
(PIPE)
Reverse serial loopback available in Basic mode with 8B/10B
PCI Express PIPE reverse parallel loopback available in PCI Express
protocol
Reverse serial pre-CDR loopback available in Basic mode with
8B/10B Reverse serial loopback available in Basic mode with 8B/10B
Serial Loopback
Figure 1–58 shows the data path for serial loopback. A data stream is fed
to the transmitter from the FPGA logic array and has the option of
utilizing all the blocks in the transmitter. The data, in serial form, then
traverses from the transmitter to the receiver. The serial data is the data
that is transmitted from the Arria GX device. Once the data enters the
receiver in serial form, it can use any of the receiver blocks and is then fed
into the FPGA logic array.
Use the rx_seriallpbken port to dynamically enable serial loopback
on a channel by channel basis. When rx_seriallpbken is high, all
blocks that are active when the signal is low are still active. When the
serial loopback is enabled, the tx_dataout port is still active and drives
out the output pins.
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May 2008
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Arria GX Transceiver Architecture
Serial loopback is often used to check the entire path of the transceiver.
The data is retimed through different clock domains and an alignment
pattern is still necessary for the word aligner.
Figure 1–58. Arria GX Block in Serial Loopback Mode
Transmitter Digital Logic
TX Phase
Compensation
FIFO
Analog Receiver and
Transmitter Logic
BIST
PRBS
Generator
BIST
Incremental
Generator
Byte
Serializer
20
8B/10B
Encoder
Serializer
FPGA
Logic
Array
Serial
Loopback
BIST
Incremental
Verify
RX Phase
Compensation
FIFO
BIST
PRBS
Verify
Byte
Deserializer
Byte
Ordering
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
Deserializer
Clock
Recovery
Unit
Receiver Digital Logic
PCI Express PIPE Reverse Parallel Loopback
Figure 1–59 shows the data path for the PCI Express PIPE reverse parallel
loopback. This data path is not flexible because it must be compliant with
the PCI Express PIPE specification. The data comes in from the
rx_datain ports. The receiver uses the CRU, deserializer, word aligner,
and rate matching FIFO buffer, loops back to the transmitter serializer,
and then goes out the transmitter tx_dataout ports. The data also goes
to the PLD fabric on the receiver side to the tx_dataout port. The
deskew FIFO buffer is not enabled in this loopback mode. This loopback
mode is optionally controlled dynamically through the
tx_detectrxloopback port.
1
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This is the only loopback allowed in the PIPE mode.
Altera Corporation
May 2008
Loopback Modes
Figure 1–59. Arria GX Block in PCI Express PIPE Reverse Parallel Loopback Mode
Transmitter Digital Logic
Analog Receiver and
Transmitter Logic
BIST
Incremental
Generator
TX Phase
Compensation
FIFO
BIST
PRBS
Generator
Byte
Serializer
8B/10B
Encoder
20
FPGA
Logic
Array
Serializer
PCI Express PIPE
Reverse Parallel
Loopback
BIST
Incremental
Verify
RX Phase
Compensation
FIFO
BIST
PRBS
Verify
Byte
Deserializer
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
Deserializer
Clock
Recovery
Unit
Receiver Digital Logic
Reverse Serial Loopback
Reverse serial loopback is a subprotocol in Basic mode. It requires
8B/10B, and the word aligner pattern of K28.5. No dynamic pin control is
available to select or deselect reverse serial loopback. The active block of
the transmitter is only the buffer. The data sent to the receiver is retimed
with the recovered clock and sent out to the transmitter.
The data path for reverse serial loopback is shown in Figure 1–60. Data
comes in from the rx_datain ports in the receiver. The data is then fed
through the CDR block in serial form directly to the tx_dataout ports
in the transmitter block.
You can enable reverse serial loopback for all channels through the
MegaWizard Plug-In Manager. Any pre-emphasis setting on the
transmitter buffer is ignored in reverse serial loopback. The data flows
through the active blocks of the receiver and into the logic array.
Reverse serial loopback is often implemented when using a bit error rate
tester (BERT).
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 1
Arria GX Transceiver Architecture
Figure 1–60. Arria GX Block in Reverse Serial Loopback Mode
Transmitter Digital Logic
Analog Receiver and
Transmitter Logic
BIST
PRBS
Generator
BIST
Incremental
Generator
TX Phase
Compensation
FIFO
Byte
Serializer
8B/10B
20 Encoder
Serializer
FPGA
Logic
Array
Reverse
Serial
Loopback
BIST
Incremental
Verify
RX Phase
Compensation
FIFO
BIST
PRBS
Verify
Byte
Deserializer
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
Deserializer
Clock
Recovery
Unit
Receiver Digital Logic
Reverse Serial Pre-CDR Loopback
The reverse serial pre-CDR loopback uses the analog portion of the
transceiver. An external source (pattern generator or transceiver)
generates the source data. The high-speed serial source data arrives at the
high-speed differential receiver input buffer, loops back before the CRU
unit, and is transmitted though the high-speed differential transmitter
output buffer. This loopback mode is for test or verification use only to
verify the signal being received after the gain and equalization
improvements of the input buffer. The signal at the output is not exactly
what is received, because the signal goes through the output buffer and
the VOD is changed to the VOD setting level. The pre-emphasis settings
have no effect.
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Altera Corporation
May 2008
Loopback Modes
Figure 1–61. Arria GX Block in Reverse Serial Pre-CDR Loopback Mode
Transmitter Digital Logic
Analog Receiver and
Transmitter Logic
BIST
PRBS
Generator
BIST
Incremental
Generator
TX Phase
Compensation
FIFO
Byte
Serializer
8B/10B
20 Encoder
Serializer
FPGA
Logic
Array
BIST
Incremental
Verify
RX Phase
Compensation
FIFO
Reverse
Serial
Loopback
Pre-CDR
BIST
PRBS
Verify
Byte
Deserializer
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
Deserializer
Clock
Recovery
Unit
Receiver Digital Logic
Incremental Pattern Generator
The incremental data generator sweeps through all the valid 8B/10B data
and control characters. This mode is only available in Basic mode with the
BIST/parallel loopback subprotocol in the Quartus II software. You can
also enable the incremental BIST verifier to perform a quick verification
of the 8B/10B encoder/decoder paths.
In incremental mode, the BIST generator sends out the data pattern in the
following sequence: K28.5 (comma), K27.7 (start of frame, SOF), Data
(00 FF incremental), K28.0, K28.1, K28.2, K28.3, K28.4, K28.6, K28.7, K23.7,
K30.7, K29.7 (end of frame, EOF), and then repeats. You must enable the
8B/10B encoder for proper operation. No dynamic control pin is available
to enable or disable the loopback. Test result pins are rx_bistdone and
rx_bisterr. The rx_bistdone signal goes high at the end of the
sequence. If the verifier detects an error before it is finished, rx_bisterr
pulses high as long as the data is in error.
Built-In Self Test Modes
In addition to the regular data flow blocks, each transceiver channel
contains an embedded built-in self test (BIST) generator and
corresponding verifier block that you can use for quick device and setup
verification ( Figure 1–62). The generators reside in the transmitter block
and the verifier in the receiver block. The generators can generate PRBS
patterns. The verifiers are only available for the PRBS patterns. The BIST
modes are only available as subprotocols under Basic mode.
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May 2008
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Arria GX Device Handbook, Volume 1
Arria GX Transceiver Architecture
Figure 1–62. Built-In Self Test Mode
rx_datain[]
tx_dataout
Buit-In Self Test
(BIST)
tx_digitalreset[]
rx_digitalreset[]
rx_bisterr(2)
rx_seriallpbken[](1)
rx_bistdone(2)
pll_inclk[]
Notes to Figure 1–62:
(1)
(2)
rx_seriallpbken[] is required in PRBS.
rx_bisterr[] and rx_bistdone[] are only available in PRBS and BIST modes.
Figure 1–63 shows the PRBS blocks with loopback used in the transceiver
channel.
Figure 1–63. PRBS Blocks With Loopback in Transceiver Channel
Transmitter Digital Logic
Analog Receiver and
Transmitter Logic
BIST
Incremental
Generator
TX Phase
Compensation
FIFO
BIST
PRBS
Generator
Byte
Serializer
20
8B/10B
Encoder
Serializer
FPGA
Logic
Array
Serial
Loopback
BIST
Incremental
Verify
BIST
PRBS
Verify
Byte
Deserializer
RX Phase
Compensation
FIFO
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
Deserializer
Clock
Recovery
Unit
Receiver Digital Logic
BIST in Basic Mode
Basic mode supports PRBS10 pattern generation and verification. PRBS10
is supported with or without serial loopback.
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The PRBS10 pattern is only available when the SERDES factor is
10 bits.
Altera Corporation
May 2008
Loopback Modes
Table 1–11 shows the BIST patterns for Basic mode.
Table 1–11. Available BIST Patterns in Basic Mode
Pattern
PRBS10
Basic Mode
Word Aligner
Alignment Pattern
Byte Order Align
Pattern
Description
10’h3FF
N/A
X10 + X7 + 1
8 Bit
10 Bit
—
v
PRBS10
Pseudo-Random Bit Sequences (PRBS) are commonly used in systems to
verify the integrity and robustness of the data transmission paths. When
the SERDES factor is 10, use the PRBS10 pattern. The PRBS generator
yields 2^10-1 unique patterns. You can use PRBS with or without serial
loopback. In PRBS/ serial loopback mode, the rx_seriallpbken signal
is available. In the PRBS/no loopback mode, this control signal is not
available.
You enable PRBS mode in the Quartus II ALT2GXB MegaWizard Plug-In
Manager. PRBS10 does not use the 8B/10B encoder and decoder. The
8B/10B encoder and decoder are bypassed automatically in the PRBS
mode.
The advantage of using a PRBS data stream is that the randomness yields
an environment that stresses the transmission medium. In the data
stream, you can observe both random jitter and deterministic jitter using
a time interval analyzer, bit error rate tester, or oscilloscope.
The PRBS verifier can provide a quick check through the non-8B/10B
path of the transceiver block. The PRBS verifier is active once the receiver
channel is synchronized. Set the alignment pattern to 10'h3FF for the
10-bit SERDES modes.
The verifier stops checking the patterns after receiving all the PRBS
patterns (1023 patterns for 10-bit mode). The rx_bistdone signal goes
high, indicating that the verifier has completed. If the verifier detects an
error before it is finished, rx_bisterr pulses high for the time the data
is incorrect. Use the rx_digitalreset signal to re-start the PRBS
verification.
The 8B/10B encoder is enabled, so the data stream is DC balanced.
8B/10B encoding guarantees a run length of less than 5 UI, which yields
a less stressful pattern versus the PRBS data. However, since the PRBS
generator bypasses the 8B/10B paths, the incremental BIST can test this
path.
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May 2008
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Arria GX Transceiver Architecture
Calibration
Blocks
The Arria GX gigabit transceiver block contains calibration circuits to
calibrate the on-chip termination, the PLLs, and the output buffers. The
calibration circuits are divided into two main blocks: the PLL and output
buffer calibration block and the termination resistor calibration block
(refer to Figure 1–64). Each transceiver block contains a PLL and output
buffer calibration block that calibrates the PLLs and output buffers within
that particular transceiver block. Each device contains one termination
resistor calibration block that calibrates all the termination resistors in the
transceiver channels of the entire device.
Figure 1–64. Calibration Block
rref
PLL and Output
Buffer Calibration Block
Reference
Signal
cal_blk_powerdown
calibration_clk
Termination Resistor
Calibration Block
PLL and Output Buffer Calibration Block
Each Arria GX transceiver block contains a PLL and output buffer
calibration circuit to counter the effects of PVT (process, voltage, and
temperature) on the PLL and output buffer. Each transceiver block's
calibration circuit uses a voltage reference derived from an external
reference resistor. There is one reference resistor required for each active
transceiver block in Arria GX devices. Unused transceiver blocks (except
the transceiver blocks feeding the termination resistor calibration block)
can be left unconnected or be tied to the 3.3 V transceiver analog VCC (if
the transceiver block’s 3.3 V analog supply is connected to 3.3 V).
Termination Resistor Calibration Block
The Arria GX transceiver's on-chip termination resistors in the
transceiver channels of the entire device are calibrated by a single
calibration block. This block ensures that process, voltage, and
temperature variations do not have an impact on the termination resistor
value. There is only one termination resistor calibration block per device.
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May 2008
Calibration Blocks
The calibration block uses the reference resistor of transceiver block 0 or
transceiver block 1, depending on the device and package. The calibration
block uses the reference resistor in transceiver block 0 for EP1AGX20/35
and EP1AGX50/60 devices (except in the F484 package). The reference
resistor in transceiver block 1 is used for EP1AGX20/35 and
EP1AGX50/60 devices in the F484 package, and for the EP1AGX90
device. A reference resistor must be connected to either transceiver block
0 or transceiver block 1 to ensure proper operation of the calibration
block, whether or not the transceiver block is in use. Failing to connect the
reference resistor of the transceiver block feeding the calibration block
results in incorrect termination values for all the termination resistors in
the transceivers of the entire device.
The termination resistor calibration circuit requires a calibration clock.
You can use a global clock line if the REFCLK pins are used for the
reference clock. You can instantiate a calibration clock port in the
MegaWizard Plug-In Manager to supply your own clock through the
cal_blk_clk port.
The frequency range of the cal_blk_clk is 10 MHz to 125 MHz. If there
are no slow speed clocks available, use a divide down circuit (for
example, a ripple counter) to divide the available clock to a frequency in
that range. The quality of the calibration clock is not an issue, so PLD local
routing is sufficient to route the calibration clock.
For multiple ALT2GXB instances in the same device, if all the instances
are the same, the calibration block must be active and the cal_blk_clk
port of all instances must be tied to a common clock. Physically, there is
one cal_blk_clk port per device. The Quartus II software provides an
error message if the cal_blk_clk port is tied to different clock sources,
because this would be impossible to fit into a device. If there are different
configurations of the ALT2GXB instance, only one must have the
calibration block instantiated. If multiple instances of the ALT2GXB
custom megafunction variation have the calibration block instantiated,
then all the cal_blk_clk ports must be tied to the same clock source.
The calibration block can be powered down through the optional
cal_blk_powerdown port (this is an active low input). Powering down
the calibration block during operations may yield transmit and receive
data errors. Only use this port to reset the calibration block to initiate a
recalibration of the termination resistors to account for variations in
temperature or voltage. The minimum pulse duration for this port is
determined by characterization. If external termination is used on all
signals, the calibration block in ALT2GXB need not be used.
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May 2008
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Arria GX Transceiver Architecture
Referenced
Documents
This chapter references the following documents:
■
■
Arria GX Transceiver Protocol Support and Additional Features
Specifications and Additional Information
1–84
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
Document Revision History
Document
Revision History
Table 1–12 shows the revision history for this chapter.
Table 1–12. Document Revision History
Date and Document
Version
May 2008, v2.0
Changes Made
●
●
August 2007, v1.2
Summary of Changes
Added sections “Transmitter PLL Bandwidth Setting”,
“Central Clock Divider Block”, “Transmitter Local Clock
Divider Block”, “Clock Synthesis”, “Transceiver Clock
Distribution”, “Single Lane”, “Four-Lane Mode”, “Channel
Clock Distribution”, “Individual Channels Clocking”,
“Transmitter Clocking (Bonded Channels)”, “Transmitter
Force Disparity”, “Transmitter Bit Reversal”, “Transmitter
Termination”, “PCI Express Receiver Detect”, “PCI
Express Electrical Idle”, “Receiver Buffer”, “Receiver
Termination”, “Signal Threshold Detection Circuit”,
“Receiver Common Mode”, “Programmable
Equalization”, “Clock Synthesis”, “PPM Frequency
Threshold Detector”, “Receiver Bandwidth Type”, “Basic
Mode”, “Pattern Detector Module”, “7-Bit Pattern Mode”,
“10-Bit Pattern Mode”, “7-bit Alignment Mode”, “Manual
10-Bit Alignment Mode”, “Manual Bit-Slip Alignment
Mode”, “Synchronization State Machine Mode”, “Run
Length Checker”, “Receiver Bit Reversal”, “Channel
Aligner (Deskew)”, “Basic Mode General Rate Matching”,
“Polarity Inversion”, “Receiver Phase Compensation
FIFO Error Flag”, “Serial Loopback”, “PCI Express PIPE
Reverse Parallel Loopback”, “Reverse Serial Loopback”,
“Reverse Serial Pre-CDR Loopback”, “Built-In Self Test
Modes”, “BIST in Basic Mode”, “PRBS10”, “Calibration
Blocks”, “PLL and Output Buffer Calibration Block”, and
“Termination Resistor Calibration Block”
Updated sections “Building Blocks”, “Port List”,
“Dedicated Reference Clock Input Pins”, “Byte
Serializer”, “8B/10B Encoder”, “Transmitter Polarity
Inversion”, “Serializer”, “Transmitter Buffer”, “Receiver
Channel Architecture”, “Code Group Error
Detection”,“Disparity Error Detection”, “Byte
Deserializer”, “Receiver Phase Compensation FIFO
Buffer”, and “Loopback Modes”
Major update. Addition of
new material.
Added the “Referenced Documents” section.
—
Minor text edits.
—
June 2007 v1.1
Added GIGE information.
—
May 2007 v1.0
Initial release.
—
Altera Corporation
May 2008
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Arria GX Transceiver Architecture
1–86
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
2. Arria GX Transceiver
Protocol Support and
Additional Features
AGX52002-2.0
Introduction
Arria™ GX transceivers have a dedicated physical coding sublayer (PCS)
and physical media attachment (PMA) circuitry to support PCI Express
(PIPE), Gigabit Ethernet (GIGE), and Serial RapidIO® protocols.
Table 2–1 lists the Arria GX transceiver datapath modules employed in
each mode.
Table 2–1. Arria GX Transceiver Datapath Modules
Functional
Mode
Transmitter
PLD/Receiver
Byte
8B/10B
Word
Rate
Transceiver
Phase
Serializer/ Encoder/
Aligner Matcher
Interface
Compensation Deserializer Decoder
Width (bits)
FIFO
PCI Express
(PIPE)
GIGE
Serial
RapidIO
(1.25Gbps)
Serial
RapidIO
(2.5Gbps)
v
v
v
v
v
v
v
v(1)
16
PLDTransceiver
Interface
Frequency
(MHz)
PCS
Frequency
(MHz)
125
250
—
v
v
v
8
125
125
v
v
v
—
16
62.5
125
v
v
v
—
16
125
250
Serial
RapidIO
(3.125Gbps)
v
v
v
v
—
16
156.25
312.5
SDI - HD
(1.483Gbps)
v
—
—
Bit-Slip
—
10/20
148.3
148.3/296.
6
SDI - HD
(1.485Gbps)
v
—
—
Bit-Slip
—
10/20
148.5
148.5/297
SDI - 3G
(2.967Gbps)
v
—
—
Bit-Slip
—
20
148.35
296.7
SDI - 3G
(2.97Gbps)
v
—
—
Bit-Slip
—
20
148.5
297
XAUI
(3.125Gbps)
v
v
v
v
v
16
156.25
312.5
Note to Table 2–1:
(1)
The rate matcher can be bypassed in low-latency (synchronous) PCI Express (PIPE) mode.
Altera Corporation
May 2008
2–1
Arria GX Transceiver Protocol Support and Additional Features
PCI Express
(PIPE) Mode
PCI Express is an evolution of peripheral component interconnect (PCI).
PCI is bandwidth-limited for today’s applications because it relies on
synchronous single-ended type signaling with a wide multi-drop data
bus. Clock and data-trace matching is required with PCI. PCI Express
uses differential serial signaling with an embedded clock to enable an
effective data rate of 2 Gbps per lane to overcome the limitations of PCI.
Arria GX transceivers support ×1 (single-lane) and ×4 (four-lane) link
widths when configured in PCI Express (PIPE) mode. The Arria GX
family supports up to twelve duplex (transmitter and receiver) ×1 links
and up to three ×4 links per device. Transceiver channels configured in ×4
PCI Express (PIPE) mode must be physically located in the same
transceiver block with logical Lane 0 assigned to physical Channel 0,
logical Lane 1 assigned to physical Channel 1 and so on.
In addition to providing the transceiver PCS and PMA circuitry, Arria GX
transceivers support the following protocol-specific features:
■
■
■
■
■
■
PCI Express synchronization state machine
Receiver detection
Electrical idle generation/detection
Beacon transmission
Polarity inversion
Power state management
1
f
This section is organized into transmitter and receiver data path
modules when configured for PCI Express (PIPE) mode. The
description for each module only covers details specific to PCI
Express (PIPE) functional mode support. Familiarity of PCI
Express protocol and PCI Express (PIPE) specifications is
assumed.
For a general description of each module, refer to the Arria GX
Transceiver Architecture chapter in volume 2 of the Arria GX Device
Handbook.
PCI Express (PIPE) Mode Transmitter Architecture
This section lists sub-blocks within the transmitter channel configured in
PCI Express (PIPE) mode (Figure 2–1). The sub-blocks are described in
order from the PLD transceiver parallel interface to the serial transmitter
buffer.
2–2
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
PCI Express (PIPE) Mode
Figure 2–1. PCI Express (PIPE) Transmitter Architecture
Transmitter PCS
PLD
Logic
Array
TX Phase
Compensation
FIFO
PIPE
Interface
Byte
Serializer
8B/10B
Encoder
Transmitter PMA
Serializer
CMU
Reference
Clock
Clock Multiplier Unit
The clock multiplier unit (CMU) takes in a reference clock and
synthesizes the clocks that are used to clock the transmitter digital logic
(PCS), the serializer, and the PLD-transceiver interface.
f
For more details about CMU architecture, refer to the Clock Multiplier
Unit section in the Arria GX Transceiver Architecture chapter in volume 2
of the Arria GX Device Handbook.
In ×1 PCI Express (PIPE) mode, the CMU block consists of the following
components:
■
■
Transmitter PLL that generates high-speed serial clock for the
serializer
Local clock divider block that generates low-speed parallel clock for
transmitter digital logic and PLD-transceiver interface
In ×4 PCI Express (PIPE) mode, the CMU block consists of the following
components:
■
■
Transmitter PLL that generates high-speed serial clock for the
serializer
Central clock divider block that generates low-speed parallel clock
for transmitter digital logic and PLD-transceiver interface of each
channel in the transceiver block
Input Reference Clock
In PCI Express (PIPE) mode, the only supported input reference clock
frequency is 100 MHz.
The reference clock input to the transmitter PLL can be derived from the
following pins:
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
■
■
One of the two available dedicated reference clock input pins
(REFCLK0 or REFCLK1) of the associated transceiver block
Inter-transceiver block lines driven by reference clock input pins of
other transceiver blocks
1
Altera recommends using the dedicated reference clock input
pins (REFCLK0 or REFCLK1) to provide a reference clock for the
transmitter PLL.
Table 2–2 specifies the input reference clock options available in PCI
Express (PIPE) mode.
Table 2–2. PCI Express (PIPE) Mode Input Reference Clock Specifications
Frequency
100 MHz
I/O Standard
Coupling
Termination
1.2V PCML, 1.5V PCML, 3.3V PCML, Differential LVPECL, LVDS
AC
On-chip
HCSL (1)
DC (2)
Off-chip
Notes to Table 2–2:
(1)
(2)
In PCI Express (PIPE) mode, you have the option of selecting the HCSL standard for the reference clock if
compliance to PCI Express is required. The Quartus® II software automatically selects DC coupling with external
termination for the signal if configured as HCSL.
Refer to Figure 2–2 for an example termination scheme.
Figure 2–2 shows an example termination scheme for the reference clock
signal when configured as HCSL.
Figure 2–2. DC Coupling and External Termination Scheme for PCI Express Reference Clock
PCI Express
(HCSL)
REFCLK
Source
Arria GX
REFCLK +
Rs (1)
Rs (1)
REFCLK -
Rp = 50 Ω
Rp = 50 Ω
Note to Figure 2–2:
(1)
Select resistor values as recommended by the PCI Express clock source vendor.
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May 2008
PCI Express (PIPE) Mode
Clock Synthesis
In PCI Express (PIPE) mode, the reference clock pre-divider divides the
100-MHz input reference clock by two. The resulting 50-MHz clock is fed
to the transmitter PLL. Because the transmitter PLL implements a
half-rate VCO, it multiplies the 50 MHz input clock by 25 to generate a
1250-MHz high-speed serial clock. This high-speed serial clock feeds the
central clock divider and four local clock dividers of the transceiver block.
In ×4 PCI Express (PIPE) mode, the central clock divider in the transceiver
block divides the 1250-MHz clock from the transmitter PLL by five to
generate a 250-MHz parallel clock. This low-speed parallel clock output
from the central clock divider block is used to clock the transmitter digital
logic (PCS) in all channels of the transceiver block. The central clock
divider block also forwards the high-speed serial clock from the
transmitter PLL to the serializer within each channel. Because all four
channels in the transceiver block are clocked with the same clock, the
channel-to-channel skew is minimized.
In ×1 PCI Express (PIPE) mode, the local clock divider in each channel of
the transceiver block divides the 1250-MHz clock from the transmitter
PLL by five to generate a 250-MHz parallel clock. This low-speed parallel
clock output from the local clock divider block is used to clock the
transmitter digital logic (PCS) of the associated channel. The local clock
divider block also forwards the high-speed serial clock from the
transmitter PLL to the serializer within its associated channel.
1
The Quartus II software automatically selects the appropriate
transmitter PLL bandwidth suited for the PCI Express (PIPE)
data rate.
Figure 2–3 shows the CMU implemented in PCI Express (PIPE) mode.
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
Figure 2–3. PCI Express (PIPE) Mode CMU
CMU Block
Transmitter Channels [3:2]
Local Clock
TX Clock
Divider
Block
(/5)Block
Gen
1250 MHz
Reference
Clock
100 MHz
/2
pre-divider
Transmitter
PLL
(x25)
50 MHz
1250 MHz
1250 MHz
Transmitter High-Speed
Serial (1250 MHz) and
Low-Speed Parallel (250 MHz)
Clock
Central Clock
Divider Block
(/5)
Local Clock
TX Clock
Divider
Block
(/5)Block
Gen
Transmitter Channels [1:0]
Transmitter High-Speed
Serial (1250 MHz) and
Low-Speed Parallel (250 MHz)
Clocks
Transmitter Phase Compensation FIFO Buffer
The transmitter phase compensation FIFO buffer compensates for the
phase difference between the PLD clock that clocks in parallel data into
the transmitter and the PCS clock that clocks the rest of the transmitter
digital logic.
f
Refer to the Transmitter Phase Compensation FIFO section in the
Arria GX Transceiver Architecture chapter in volume 2 of the Arria GX
Device Handbook for more details about transmitter phase compensation
FIFO buffer architecture.
In PCI Express (PIPE) mode, the 250-MHz clock generated by the CMU
clock divider block is divided by two. The resulting 125-MHz clock is
used to clock the read port of the FIFO buffer. This 125-MHz clock is also
forwarded to the PLD logic array (on the tx_clkout port in ×1 PCI
Express (PIPE) mode or the coreclkout port in ×4 PCI Express (PIPE)
mode). If the tx_coreclk port is not instantiated, the clock signal on the
tx_clkout port of channel 0 is routed back to clock the write side of the
transmitter phase compensation FIFO buffer in all channels with the
transceiver block. The 16-bit PLD-transceiver interface clocked at
125-MHz results in an effective PCI Express (PIPE) data rate of 2 Gbps.
In PCI Express (PIPE) mode, the transmitter phase compensation FIFO is
eight words deep. The latency through the FIFO is three to four
PLD-transceiver interface clock cycles.
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Altera Corporation
May 2008
PCI Express (PIPE) Mode
Figure 2–4 shows the block diagram of transmitter phase compensation
FIFO in PCI Express (PIPE) mode.
Figure 2–4. TX Phase Compensation FIFO in PCI Express (PIPE) Mode
Transmitter Channel
tx_datain[15:0]
Transmitter
Phase
Compensation
FIFO
From
PLD
wrclk
dataout[15:0]
To Byte Serializer
rdclk
250 MHz
tx_coreclk
125 MHz
125 MHz
/2
CMU
Local/Central Clock
Divider Block
tx_clkout or coreclkout
Byte Serializer
In PCI Express (PIPE) mode, the PLD-transceiver interface data is 16-bits
wide and is clocked into the transmitter phase compensation FIFO at
125 MHz. The byte serializer clocks in the 16-bit wide data from the
transmitter phase compensation FIFO at 125 MHz and clocks out 8-bit
data to the 8B/10B encoder at 250 MHz. This allows clocking the
PLD-transceiver interface at half the speed.
f
For more details about byte serializer architecture, refer to the Byte
Serializer section in the Arria GX Transceiver Architecture chapter in
volume 2 of the Arria GX Device Handbook.
The write port of the byte serializer is clocked by the divide-by-two
version of the low-speed parallel clock from the CMU. The read port is
clocked by the low-speed parallel clock from the CMU. The byte serializer
clocks out the least significant byte (LSByte) of the 16-bit data first and the
most significant byte (MSByte) last.
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
Figure 2–5 shows the block diagram of the byte serializer in PCI Express
(PIPE) mode.
Figure 2–5. Byte Serializer in PCI Express (PIPE) Mode
dataout
datain
From Transmitter
Phase Compensation
FIFO
Byte Serializer
To 8B/10B
Encoder
wrclk
rdclk
125 MHz
250 MHz
125 MHz
/2
Divide-by-Two
Version of
Low-Speed
Parallel Clock
250 MHz
Low-Speed
Parallel Clock
CMU
Local/Central Clock
Divider Block
8B/10B Encoder
In PCI Express (PIPE) mode, the 8B/10B encoder clocks in 8-bit data and
1-bit control identifier from the byte serializer and generates 10-bit
encoded data. The 10-bit encoded data is fed to the serializer.
f
For more details about the 8B/10B encoder functionality, refer to the
8B/10B Encoder section in the Arria GX Transceiver Architecture chapter
in volume 2 of the Arria GX Device Handbook.
Compliance Pattern Transmission Support
PCI Express has an option to transmit a compliance pattern for testing
purposes. The compliance pattern must be transmitted beginning with a
negative disparity. In PCI Express (PIPE) mode, you set the negative
disparity with the tx_forcedispcompliance port.
Asserting the tx_forcedispcompliance port sets the LSByte of the
16-bit PLD-transmitter interface data to be encoded with a negative
disparity. The tx_forcedispcompliance port must be de-asserted
after the first word of the compliance pattern is clocked into the
transceiver.
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Altera Corporation
May 2008
PCI Express (PIPE) Mode
1
The compliance pattern generator is not part of the Arria GX
transceiver and must be designed using the PLD logic. This
feature allows you to begin the compliance pattern only with a
negative disparity.
Serializer
In PCI Express (PIPE) mode, the 10-bit encoded data from the 8B/10B
encoder is clocked into the 10:1 serializer with the low-speed parallel
clock at 250 MHz. The 10-bit data is clocked out of the serializer LSByte to
MSByte at both edges of the high-speed serial clock at 1250 MHz. The
resulting 2.5 Gbps serial data output of the serializer is fed into the
transmitter output buffer.
f
Refer to the Serializer section in the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device Handbook for more details
about the serializer architecture.
Transmitter Buffer
Table 2–3 shows the transmitter buffer settings when configured in PCI
Express (PIPE) mode.
Table 2–3. Transmitter Buffer Settings in PCI Express (PIPE) Mode
Settings
Value
I/O Standard
1.2-V PCML (2)
Programmable Differential Output
Voltage (VOD)
320-960 mV
Common Mode Voltage (VCM)
600 mV (1)
Differential Termination
100 Ω (2)
Programmable Transmitter
Pre-Emphasis
Enabled (3)
VCCH (Transmitter Buffer Power)
1.2 V
Notes to Table 2–3:
(1)
(2)
(3)
Altera Corporation
May 2008
The common mode voltage (VCM) is fixed in the MegaWizard® Plug-In Manager
and cannot be changed.
The I/O standard and differential termination settings are defaulted to 1.2-V
PCML and 100 Ω , respectively. If you select any other setting for the I/O
standard or differential termination in the Assignment Editor, the Quartus II
compiler will issue an error message.
The transmitter buffer has five programmable first post-tap pre-emphasis
settings.
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Arria GX Transceiver Protocol Support and Additional Features
Transmitter Electrical Idle
In PCI Express (PIPE) mode, you can force the transmitter into electrical
idle condition during P0 and P2 power state by asserting the
tx_forceelecidle signal high. In electrical idle state, the transmitter
buffer is tri-stated. The tx_forceelecidle signal must always be
asserted high in P0 and P1 power states. Refer to “Power State
Management” on page 2–22 for more details about PCI Express (PIPE)
mode power states.
Receiver Detect
PCI Express Base Specification requires the transmitter to be capable of
detecting a far-end receiver before beginning link training. Arria GX
transceivers have dedicated receiver detect circuitry that is activated in
PCI Express (PIPE) mode.
The receiver detect circuitry is available only in the P1 power state, and is
set through the tx_detectrxloopback port, and requires a 125 MHz
fixedclk signal. Refer to “Power State Management” on page 2–22 for
more details about PCI Express (PIPE) mode power states.
In P1 power state, the transmitter output buffer is tri-stated, because the
transmitter is in electrical idle. A high on the tx_detectrxloopback
port triggers the receiver detect circuitry to alter the transmitter buffer
common mode voltage. The sudden change in common mode voltage
appears as a step voltage at the tri-stated transmitter buffer output. If a
receiver (that complies with PCI Express input impedance requirements)
is present at the far end, the time constant of the step voltage is higher. If
a receiver is not present or is powered down, the time constant of the step
voltage is lower. The receiver detect circuitry snoops the transmitter
buffer output for the time constant of the step voltage to detect the
presence of the receiver at the far end.
A high pulse is driven on the pipephydonestatus port and 3'b011 is
driven on the pipestatus port (refer to “Receiver Status” on page 2–21)
to indicate that a receiver has been detected. There is some latency after
asserting the tx_detectrxloopback signal, before the receiver
detection is indicated on the pipephydonestatus port.
1
The tx_forceelecidle port must be asserted at least 10
parallel clock cycles prior to the tx_detectrxloopback port
to ensure that the transmitter buffer is tri-stated.
Beacon Transmission
The beacon is an optional 30-kHz to 500-MHz in-band signal that wakes
the receiver from a P2 power state. This signal is optional; the Arria GX
device does not have dedicated beacon transmission circuitry. The
Arria GX device supports the transmission of the beacon signal through
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May 2008
PCI Express (PIPE) Mode
a 10-bit encoded code group that has a five 1’s pulse (for example, K28.5)
(10'b0101111100). Because the beacon signal is a pulse that ranges from
2 ns to 500 ns, sending out a K28.5 at 2.5 Gbps meets the lower
requirement with its five 1's pulse. (Though other 8B/10B code groups
might meet the beacon requirement, this document uses the K28.5 control
code group as the beacon signal.) The beacon transmission takes place
only in the P2 power state. The tx_forceelecidle port controls when
the transmitter is in Electrical Idle or not. This port must be de-asserted in
order to transmit the K28.5 code group for beacon transmission.
PCI Express (PIPE) Mode Receiver Architecture
This section lists sub-blocks within the receiver channel configured in PCI
Express (PIPE) mode (Figure 2–6). The sub-blocks are described in order
from the serial receiver input buffer to the receiver phase compensation
FIFO buffer at the transceiver-PLD interface.
Figure 2–6. PCI Express (PIPE) Mode Receiver Architecture
Receiver PCS
PLD
Logic
Array
PIPE
Interface
RX Phase
Compensation
FIFO
Byte
De-Serializer
8B/10B
Decoder
Rate
Match
FIFO
Receiver PMA
DeSerializer
Word
Aligner
Clock
Recovery
Unit
Receiver
PLL
Reference
Clocks
Receiver Buffer
Table 2–4 shows the receiver buffer settings when configured in PCI
Express (PIPE) mode.
Table 2–4. Receiver Buffer Settings in PCI Express (PIPE) Mode
(Part 1 of 2)
Settings
I/O Standard
Value
1.2-V PCML, 1.5-V PCML,
3.3-V PCML, Differential LVPECL,
LVDS
Input Common Mode Voltage (Rx VCM) 850 mV, 1200 mV (1)
Altera Corporation
May 2008
Differential Termination
100 Ω (2)
Programmable equalization
Enabled (3)
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Arria GX Transceiver Protocol Support and Additional Features
Table 2–4. Receiver Buffer Settings in PCI Express (PIPE) Mode
(Part 2 of 2)
Settings
Coupling
Value
AC
Notes to Table 2–4:
(1)
(2)
(3)
The common mode voltage (Rx VCM) is selectable in the MegaWizard® Plug-In
Manager.
The differential termination setting is defaulted to 100 Ω. If you select any other
setting for differential termination in the Assignment Editor, the Quartus II
compiler issues an error message.
The receiver buffer has five programmable equalization settings.
Signal Detect Threshold Circuitry
In PCI Express (PIPE) mode, the receiver buffer incorporates a signal
detect threshold circuitry. The signal detect threshold circuitry senses
whether the specified threshold voltage level exists at the receiver buffer.
This detector has a hysteresis response that filters out any high frequency
ringing caused by inter symbol interference or high frequency losses in
the transmission medium.
The rx_signaldetect signal indicates whether the signal at the
receiver buffer conforms to the signal detection settings. A high level on
the rx_signaldetect port indicates that the signal conforms to the
settings and a low level indicates that the signal does not conform to the
settings. The Quartus II software automatically defaults to the
appropriate signal detect threshold based on the PCI Express electrical
idle specifications.
Receiver PLL and Clock Recovery Unit (CRU)
In PCI Express (PIPE) mode, the receiver PLL in each transceiver channel
is fed by a 100 MHz input reference clock. The receiver PLL in
conjunction with the clock recovery unit generates two clocks: a
high-speed serial recovered clock at 1250 MHz (half-rate VCO) that feeds
the deserializer, and a low-speed parallel recovered clock at 250 MHz that
feeds the receiver’s digital logic.
You can set the clock recovery unit in either automatic lock mode or
manual lock mode. In automatic lock mode, the PPM detector and the
phase detector within the receiver channel automatically switches the
receiver PLL between lock-to-reference and lock-to-data modes. In
manual lock mode, you can control the receiver PLL switch between
lock-to-reference and lock-to-data modes via the rx_locktorefclk
and rx_locktodata signals.
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May 2008
PCI Express (PIPE) Mode
f
Refer to the Receiver PLL section in the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device Handbook for more details on
the CRU lock modes.
The reference clock input to the receiver PLL can be derived from the
following pins:
■
■
One of the two available dedicated reference clock input pins
(REFCLK0 or REFCLK1) of the associated transceiver block
Inter-transceiver block lines driven by reference clock input pins of
other transceiver blocks
Deserializer
The 1:10 deserializer clocks in serial data from the receiver buffer using
the high-speed recovered clock. The 10-bit deserialized data is clocked
out to the word aligner using the low-speed recovered clock at 250 MHz.
The deserializer assumes that the transmission bit order is LSB to MSB;
for example, the LSB of a data word is received earlier in time than its
MSB.
f
Refer to the Deserializer section in the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device Handbook for more details
about the deserializer architecture.
Word Aligner
The word aligner clocks in the 10-bit data from the deserializer and
restores the word boundary of the upstream transmitter. Besides
restoring the word boundary, it also implements a synchronization state
machine as specified in the PCI Express Base Specification to achieve lane
synchronization.
f
Refer to the section “Word Aligner” on page 2–13 in the Arria GX
Transceiver Architecture chapter in volume 2 of the Arria GX Device
Handbook for more details about the word aligner architecture.
In PCI Express (PIPE) mode, the word aligner consists of the following
three modules:
■
■
■
Altera Corporation
May 2008
Pattern detector module
Pattern aligner module
Run-length violation detector module
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Arria GX Transceiver Protocol Support and Additional Features
Pattern Detector
In PCI Express (PIPE) mode, the Quartus II software automatically
configures 10-bit K28.5 (10'b0101111100) as the word alignment pattern.
After coming out of reset (rx_digitalreset), when the pattern
detector detects either disparities of the K28.5 control word, it asserts the
rx_patterndetect signal for one parallel clock cycle. When the
pattern aligner has aligned the incoming data to the desired word
boundary, the pattern detector asserts the rx_patterndetect signal
only if the word alignment pattern is found in the current word boundary.
Pattern Aligner
In PCI Express (PIPE) mode, the pattern aligner incorporates an
automatic synchronization state machine. The Quartus II software
automatically configures the synchronization state machine to indicate
lane synchronization when the receiver receives four good /K28.5/
control code groups. Synchronization can be accomplished through the
reception of four good PCI Express training sequences (TS1 or TS2) or
four fast training sequences (FTS). Lane synchronization is indicated on
the rx_syncstatus port of each channel. A high on the
rx_syncstatus port indicates that the lane is synchronized and a low
indicates that it has fallen out of synchronization.
Table 2–5 lists the synchronization state machine parameters when
configured in PCI Express (PIPE) mode.
Table 2–5. Synchronization State Machine Parameters in PCI Express (PIPE)
Mode
Number of valid /K28.5/ code groups received to achieve
synchronization (kcntr)
4
Number of errors received to lose synchronization (ecntr)
17
Number of continuous good code groups received to reduce the
error count by 1 (gcntr)
16
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May 2008
PCI Express (PIPE) Mode
Figure 2–7 shows a state diagram of the PCI Express (PIPE)
synchronization.
Figure 2–7. PCI-Express (PIPE) Synchronization State Machine
Loss of Sync
Data = Comma
Data = !Valid
Comma Detect
if Data == Comma
kcntr++
else
kcntr=kcntr
Data = valid;
kcntr <3
kcntr = 3
Synchronized
Data=Valid
Data = !Valid
ecntr = 17
Synchronized Error
Detect
if Data == !valid
ecntr++
gcntr=0
else
if gcntr==16
ecntr-gcntr=0
else
gcntr++
ecntr = 0
Tables 2–6 and 2–7 list the TS1 and TS2 training sequences, respectively.
A PCI Express fast training sequence consists of a /K28.5/, followed by
three /K28.1/ code groups.
Table 2–6. PCI Express TS1 Ordered Set (Part 1 of 2)
Symbol
Number
Allowed Values
Encoded Values
0
—
K28.5
1
0–255
D0.0–D31.7, and K23.7
Link number with component
2
0–31
D0.0–D31.0, and K23.7
Lane number within port
Altera Corporation
May 2008
Description
Comma code group for symbol alignment
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Table 2–6. PCI Express TS1 Ordered Set (Part 2 of 2)
Symbol
Number
Allowed Values
Encoded Values
Description
3
0–255
D0.0–D31.7
N_FTS. The number of fast training ordered
sets required by the receiver to obtain
reliable bit and symbol lock.
4
2
D2.0
Data rate identifier
Bit 0–Reserved, set to 0
Bit 1 = 1, generation 1 (2.5Gbps) data rate
supported
Bit 2..7–Reserved, set to 0
5
Bit 0 = 0, 1
Bit 1 = 0, 1
Bit 2 = 0, 1
Bit 3 = 0, 1
Bit 4..7 = 0
D0.0, D1.0, D2.0, D4.0,
and D8.0
Training control
Bit 0 – Hot reset
Bit 0 = 0, de-assert
Bit 0 = 1, assert
Bit 1 – Disable link
Bit 1 = 0, de-assert
Bit 1 = 1, assert
Bit 1 – Loopback
Bit 2 = 0, de-assert
Bit 2 = 1, assert
Bit 3 – Disable scrambling
Bit 3 = 0, de-assert
Bit 3 = 1, assert
Bit 4..7 – Reserved
Bit 0 = 0, de-assert
Set to 0
6–15
—
D10.2
TS1 identifier
Table 2–7. PCI Express TS2 Ordered Set (Part 1 of 2)
Symbol
Number
Allowed Values
Encoded Values
K28.5
Description
0
—
1
0–255
D0.0–D31.7, and K23.7 Link number with component.
2
0–31
D0.0–D31.0, and K23.7 Lane number within port.
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Comma code group for symbol alignment.
Altera Corporation
May 2008
PCI Express (PIPE) Mode
Table 2–7. PCI Express TS2 Ordered Set (Part 2 of 2)
Symbol
Number
Allowed Values
Encoded Values
3
0–255
D0.0–D31.7
Description
N_FTS. The number of fast training ordered sets
required by the receiver to obtain reliable bit and
symbol lock.
4
2
D2.0
5
Bit 0 = 0, 1
Bit 1 = 0, 1
Bit 2 = 0, 1
Bit 3 = 0, 1
Bit 4..7 = 0
D0.0, D1.0, D2.0, D4.0,
and D8.0
Data rate identifier
Bit 0–Reserved, set to 0
Bit 1 = 1, generation 1 (2.5Gbps) data rate
supported
Bit 2..7–Reserved, set to 0
Training control
Bit 0 – Hot reset
Bit 0 = 0, de-assert
Bit 0 = 1, assert
Bit 1 – Disable link
Bit 1 = 0, de-assert
Bit 1 = 1, assert
Bit 1 – Loopback
Bit 2 = 0, de-assert
Bit 2 = 1, assert
Bit 3 – Disable scrambling
Bit 3 = 0, de-assert
Bit 3 = 1, assert
Bit 4..7 – Reserved
Bit 0 = 0, de-assert
Set to 0
6–15
—
D5.2
TS2 identifier
Rate Matcher
In PCI Express (PIPE) mode, the rate matcher can compensate up to
± 300 parts per million (PPM) (600 PPM total) frequency difference
between the upstream transmitter and the receiver. In ×1 and ×4 PCI
Express (PIPE) mode, the write port of the rate matcher FIFO in each
receiver channel is clocked by its low-speed parallel recovered clock. In
×1 PCI Express (PIPE) mode, the read port is clocked by the low-speed
parallel clock output of the CMU local clock divider block. In ×4 PCI
Express (PIPE) mode, the read port is clocked by the low-speed parallel
clock output of the CMU central clock divider block.
Altera Corporation
May 2008
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Arria GX Transceiver Protocol Support and Additional Features
The rate matcher logic looks for skip ordered sets (SKP), which contains
a /K28.5/ comma followed by three /K28.0/ skip characters. It deletes or
inserts /K28.0/ skip characters as necessary from or to the rate matcher
FIFO. The rate matcher can delete only one skip character in a consecutive
cluster of skip characters and can insert only one skip character per skip
cluster.
Figure 2–8 shows an example of a PCI Express (PIPE) mode rate matcher
deletion of two skip characters.
Figure 2–8. PCI Express (PIPE) Mode Rate Matcher Deletion
Skip Cluster
Skip Cluster
datain
K28.5
K28.0
K28.0
K28.0
Dx.y
K28.5
K28.0
K28.0
dataout
K28.5
K28.0
K28.0
Dx.y
K28.5
K28.0
Dx.y
Dx.y
Two Skips Deleted
The rate matcher in PCI Express (PIPE) mode has FIFO buffer overflow
and underflow protection. In the event of a FIFO buffer overflow, the rate
matcher deletes any data after detecting the overflow condition to
prevent FIFO pointer corruption until the rate matcher is not full. In an
underflow condition, the rate matcher inserts 9'h1FE (/K30.7/) until the
FIFO buffer is not empty. These measures ensure that the FIFO buffer can
gracefully exit the overflow/underflow condition without requiring a
FIFO reset. The rate matcher FIFO overflow and underflow condition is
indicated on the pipestatus port.
8B/10B Decoder
In PCI Express (PIPE) mode, the 8B/10B decoder clocks in 10-bit data
from the rate matcher and decodes it into 8-bit data + 1-bit control
identifier. The 8-bit decoded data is fed to the byte deserializer.
f
For more details about the 8B/10B decoder functionality, refer to the
8B/10B Encoder section in the Arria GX Transceiver Architecture chapter
in volume 2 of the Arria GX Device Handbook.
If the received 10-bit code is not a part of valid Dx.y or Kx.y code groups,
the 8B/10B decoder block asserts an error flag on rx_errdetect port.
The 8B/10B decoder replaces the invalid code group with /K30.7/ code
2–18
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
PCI Express (PIPE) Mode
(8'hFE + 1'b1 after decoding). The error flag signal (rx_errdetect) has
the same data path delay from the 8B/10B decoder to the PLD-transceiver
interface as the invalid code group.
If the received 10-bit code is detected with incorrect running disparity, the
8B/10B decoder block asserts an error flag on the rx_disperr and
rx_errdetect ports. The error flag signal (rx_disperr) has the same
delay from the 8B/10B decoder to the PLD-transceiver interface as the
received data.
Polarity Inversion
The 8B/10B decoder supports the PCI Express (PIPE) compatible polarity
inversion feature. This polarity inversion feature inverts the bits of the
incoming data stream prior to the 8B/10B decoding block to fix accidental
P-N polarity inversion on the differential input buffer. You use the
pipe8b10binvpolarity port to invert the inputs to the 8B/10B
decoder dynamically from the PLD.
1
You must not enable the receiver polarity inversion feature if
you enable the PCI Express polarity inversion.
Byte Deserializer
In PCI Express (PIPE) mode, the PLD-receiver interface data is 16-bits
wide and is clocked out of the receiver phase compensation FIFO at
125 MHz. The byte deserializer clocks in the 8-bit wide data from the
8B/10B decoder at 250 MHz and clocks out 16-bit wide data to the
receiver phase compensation FIFO at 125 MHz. This allows clocking the
PLD-transceiver interface at half the speed.
f
For more details about byte deserializer architecture, refer to the Byte
Deserializer section in the Arria GX Transceiver Architecture chapter in
volume 2 of the Arria GX Device Handbook.
In ×1 PCI Express (PIPE) mode, the write port of the byte deserializer is
clocked by the low-speed parallel clock output from the CMU local clock
divider block (tx_clkout) and the read port is clocked by divide-by-two
version of this clock. In ×4 PCI Express (PIPE) mode, the write port of the
byte deserializer is clocked by the low-speed parallel clock output from
the CMU central clock divider block (coreclkout) and the read port is
clocked by divide-by-two version of this clock.
Due to 8-bit to 16-bit byte deserialization, the byte ordering at the
PLD-receiver interface might be incorrect. You implement the byte
ordering logic in the PLD core to correct for this situation.
Altera Corporation
May 2008
2–19
Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
Figure 2–9 shows the block diagram of the byte serializer in PCI Express
(PIPE) mode.
Figure 2–9. Byte Deserializer in PCI Express (PIPE) Mode
dataout[15:0]
datain[7:0]
Byte
Deserializer
From 8B/10B
Decoder
wrclk
To Receiver Phase
Compensation
FIFO
rdclk
125 MHz
250 MHz
/2
Low-Speed Parallel CMU Clock
Receiver Phase Compensation FIFO Buffer
The receiver phase compensation FIFO buffer compensates for the phase
difference between the local receiver PLD clock and the receiver PCS
clock.
f
For more details about receiver phase compensation FIFO buffer
architecture, refer to the Receiver Phase Compensation FIFO Buffer
section in the Arria GX Transceiver Architecture chapter in volume 2 of the
Arria GX Device Handbook.
In PCI Express (PIPE) mode, the 250-MHz clock generated by the CMU
clock divider block is divided by two. The resulting 125-MHz clock is
used to clock the write port of the FIFO buffer. This 125-MHz clock is also
forwarded to the PLD logic array (on the tx_clkout port in ×1 PCI
Express (PIPE) mode or the coreclkout port in ×4 PCI Express (PIPE)
mode). If the rx_coreclk port is not instantiated, the clock signal on the
tx_clkout/coreclkout port is routed back to clock the read side of
the receiver phase compensation FIFO buffer. The 16-bit PLD-receiver
interface, clocked at 125 MHz, results in an effective PCI Express (PIPE)
data rate of 2 Gbps.
In PCI Express (PIPE) mode, the receiver phase compensation FIFO is
eight words deep. The latency through the FIFO is two to three
PLD-transceiver interface clock cycles.
2–20
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
PCI Express (PIPE) Mode
Figure 2–10 shows the block diagram of transmitter phase compensation
FIFO in PCI Express (PIPE) mode.
Figure 2–10. Receiver Phase Compensation FIFO in PCI Express (PIPE) Mode
Receiver Channel
datain[15:0]
From Byte
Deserializer
To PLD
wrclk
rdclk
125 MHz
250 MHz
rx_dataout[15:0]
Receiver Phase
Compensation
FIFO
125 MHz
/2
rx_coreclk
Low-Speed
Parallel CMU Clock
tx_clkout or
coreclkout
Receiver Status
PCI Express (PIPE) specifies a receiver status indicator that reports the
status of the PHY (PCS and PMA). In PCI Express (PIPE) mode, the
receiver status is communicated to the PLD logic by the three-bit
pipestatus port. This port reports the status, as shown in Table 2–8. If
more than one event occurs at the same time, the signal is resolved with
the higher priority status. The skip character added and removed flags
(3'b001 and 3'b010) are not supported. The pipestatus port may be
encoded to 3b'001 and 3'b010, which should be ignored. It does not
indicate that a skip has been added or removed and should be considered
the same as 3'b000—received data. If the upper MAC layer must know
when a skip character was added or removed, Altera recommends
monitoring the number of skip characters received. The transmitter
should send three skip characters in a standard skip-ordered set.
Table 2–8. pipestatus Description and Priority (Part 1 of 2)
pipestatus
Altera Corporation
May 2008
Description
Priority
3'b000
Received data
3'b001
One skip character added (not supported)
N/A
6
3'b010
One skip character removed (not supported)
N/A
3'b011
Receiver detected
1
3'b100
8B/10B decoder error
2
3'b101
Elastic buffer overflow
3
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
Table 2–8. pipestatus Description and Priority (Part 2 of 2)
pipestatus
Description
Priority
3'b110
Elastic buffer underflow
4
3'b111
Received disparity error
5
Power State Management
The four supported power states in Arria GX when configured in PIPE
mode are:
■
■
■
■
PO — normal power state
POs — low recovery time
P1 — lower than PO
P2 — lowest power state
There are four supported power states in Arria GX transceivers when
configured in PIPE mode: P0, P0s, P1, and P2. P0 is the normal power
state. P0s is a low recovery time power state that is lower than P0. P1 is a
lower power state than P0s and has higher latency to come out of this
state. P2 is the lowest power state.
The powerdn port transitions the transceiver into different power states.
The encoded value is shown in Table 2–9. The pipephydonestatus
signal reacts to the powerdn request and pulses high for one parallel
clock cycle.
There are specific functions that are performed at each of the power
states. The power-down states are for PCI Express (PIPE) emulation. The
transceiver does not go into actual power saving mode, with the
exception of the transmitter buffer for Electrical Idle.
Table 2–9 shows each power state and its function.
Table 2–9. Power State Functions and Descriptions
Power State
powerdn
Function
P0
2'b00
Transmits normal data,
transmits Electrical Idle, or enters into
loopback mode.
Normal operation mode
P0s
2'b01
Only transmits Electrical Idle.
Low recovery time power saving state
P1
2'b10
Transmitter buffer is powered down and
High recovery time power saving state
can do a receiver detect while in this state.
P2
2'b11
Transmits Electrical Idle or a beacon to
wake up the downstream receiver.
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Arria GX Device Handbook, Volume 2
Description
Lowest power saving state
Altera Corporation
May 2008
PCI Express (PIPE) Mode
The two signals associated with the power states are:
tx_detectrxloopback and tx_forceelecidle. The
tx_detectrxloopback signal controls whether the channel goes into
loopback when the power state is in P0 or receiver detect when in P1 state.
This signal does not have any affect in any other power states. The
tx_forceelecidle signal governs when the transmitter goes into an
electrical idle state. The tx_forceelecidle signal is asserted in P0s
and P1 states and de-asserted in P0 state. In P2 state, under normal
conditions, the tx_forceelecidle signal is asserted and then
de-asserted when the beacon signal must be sent out, signifying the intent
to exit the P2 power-down state.
Table 2–10 shows the behavior of the tx_detectrxloopback and
tx_forceelecidle signals in the power states.
Table 2–10. Power States and Functions Allowed in Each Power State
Power State
tx_detectrxloopback
tx_forceelecidle
P0
0: normal mode
1: data path in loopback mode
0: Must be de-asserted.
1: Illegal mode
P0s
Don’t care
0: Illegal mode
1: Must be asserted in this state
P1
0: Electrical Idle
1: receiver detect
0: Illegal mode
1: Must be asserted in this state
P2
Don't care
De-asserted in this state for
sending beacon.
Otherwise asserted.
NFTS Fast Recovery IP (NFRI)
The PCI Express fast training sequences (FTS) are used for bit and byte
synchronization to transition from P0s state to P0 state. The PCI Express
standard specifies the required time period for this transition to be
between 16 ns and 4 μs. The default PCI Express (PIPE) settings do not
meet this requirement. You must enable the NFTS fast recovery IP (NFRI)
for the receiver to transition from P0s to P0 within 4 μs by selecting the
Enable fast recovery mode option in the MegaWizard Plug-In Manager.
PCI Express (PIPE) Mode Default Settings
In the PCI Express (PIPE) mode default settings (without NFRI enabled),
the receiver PLL is in automatic lock mode. The PLL moves from
lock-to-reference mode to lock-to-data mode based on the
rx_freqlocked being asserted. For the rx_freqlocked signal to be
asserted, the CRU clock should be within the PPM threshold settings of
the receiver PLL reference clock. The PPM detector checks the PPM
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
threshold settings by comparing the CRU PLL clock output with the
reference clock for approximately 32768 clock cycles. For a 250 MHz PLD
interface clock frequency, this comparison time period exceeds 4 μs,
which violates the PCI Express specification.
The NFRI, if enabled, controls the rx_locktorefclk and
rx_locktodata signals to meet the 4 μs transition time from P0s to P0
power state.
1
If you select the rx_locktorefclk and rx_locktodata
signals in the MegaWizard Plug-In Manager (CRU Manual Lock
mode), the Enable fast recovery mode option cannot be
selected.
When you select the Enable fast recovery mode option, you must
consider the following:
■
■
■
NFRI is created in the PLD side for each PCI Express (PIPE) channel
NFRI is a soft IP, so it consumes logic resources
This block is self-contained, so no input/output ports are available to
access the soft IP
Low-Latency (Synchronous) PCI Express (PIPE) Mode
The Arria GX receiver data path employs a rate match FIFO in PCI
Express (PIPE) mode to compensate up to ±300 PPM difference between
the upstream transmitter and the local receiver reference clock. The
low-latency (synchronous) PCI Express (PIPE) mode allows bypassing
the rate match FIFO in synchronous systems that derive the transmitter
and receiver reference clocks from the same source. You can bypass the
rate match FIFO by not selecting the Enable Rate Match FIFO option in
the ALT2GXB MegaWizard Plug-In Manager.
The rate match FIFO can be bypassed in both ×1 and ×4 PCI Express
(PIPE) modes. In normal PCI Express (PIPE) mode, the receiver blocks
following the rate match FIFO are clocked by tx_clkout (×1 mode) or
coreclkout (×4 mode) of the local port. In low-latency (synchronous)
PCI Express (PIPE) mode, because the rate match FIFO is bypassed, these
receiver blocks are clocked by the recovered clocks of the respective
channels.
Except for the rate match FIFO being bypassed and the resulting changes
in transceiver internal clocking, the low-latency (synchronous) PCI
Express (PIPE) mode shares the same data path and state machines as the
normal PCI Express (PIPE) mode. However, some features supported in
normal PCI Express (PIPE) mode are not supported in low-latency
(synchronous) PCI Express (PIPE) mode.
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May 2008
PCI Express (PIPE) Mode
PCI Express (PIPE) Reverse Parallel Loopback
In normal PCI Express (PIPE) mode, if the transceiver is in P0 power state,
a high value on the tx_rxdetectloop signal forces a reverse parallel
loopback, as discussed in PCI Express (PIPE) Reverse Parallel Loopback
section. Parallel data at the output of the receiver rate match FIFO gets
looped back to the input of the transmitter serializer.
In low-latency (synchronous) PCI Express (PIPE) mode, since the rate
match FIFO is bypassed, this feature is not supported. A high value on the
tx_rxdetectloop signal when the transceiver is in P1 power state will
not force it to perform reverse parallel loopback.
Link Width Negotiation
In normal ×4 PCI Express (PIPE) configuration, the receiver phase
compensation FIFO control signals (write/read enable, and so forth) are
shared among all lanes within the link. As a result, all lanes are truly
bonded and the lane-lane skew meets the PCI Express specification.
In low-latency (synchronous) PCI Express (PIPE) configuration, the
receiver phase compensation FIFO of individual lanes do not share
control signals. The write port of the receiver phase compensation FIFO
of each lane is clocked by its recovered clock. As a result, the lanes within
a link are not bonded. You should perform external lane de-skewing to
ensure proper link width negotiation.
Receiver Status
Because the rate match FIFO is bypassed in low-latency (synchronous)
PCI Express (PIPE) mode, status signal combinations related to the rate
match FIFO on the pipestatus[2:0] port become irrelevant and must
not be interpreted (Table 2–11).
Table 2–11. pipestatus Signal (Part 1 of 2)
Altera Corporation
May 2008
pipestatus[2:0]
Normal PIPE
Synchronous PIPE
000
Received Data OK
Received Data OK
001
Not supported
Not supported
010
Not supported
Not supported
011
Receiver Detected
Receiver Detected
100
8B/10B Decoder Error
8B/10B Decoder Error
101
Elastic Buffer Overflow
Not supported
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
Table 2–11. pipestatus Signal (Part 2 of 2)
Gigabit Ethernet
(GIGE) mode
pipestatus[2:0]
Normal PIPE
Synchronous PIPE
110
Elastic Buffer Underflow
Not supported
111
Received Disparity Error
Received Disparity Error
IEEE 802.3 defines the 1000 Base-X PHY as an intermediate, or transition,
layer that interfaces various physical media with the media access control
(MAC) in a gigabit ethernet system. It shields the MAC layer from the
specific nature of the underlying medium. The 1000 Base-X PHY is
divided into three sub-layers:
■
■
■
Physical coding sublayer (PCS)
Physical media attachment (PMA)
Physical medium dependent (PMD)
The PCS sublayer interfaces to the MAC through the gigabit medium
independent interface (GMII). The 1000 Base-X PHY defines a physical
interface data rate of 1 Gbps.
Figure 2–11 shows the 1000 Base-X PHY position in a Gigabit Ethernet
OSI reference model.
Figure 2–11. GIGE OSI Reference Model
LAN
CSMA/CD Layers
OSI
Reference
Model Layers
Higher Layers
LLC
Application
MAC (Optional)
Presentation
MAC
Session
Transport
Network
Data Link
Reconciliation
GMII
PCS
PMA
PMD
1000 Base-X
PHY
Physical
Medium
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Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Gigabit Ethernet (GIGE) mode
When Arria GX transceivers are configured in GIGE functional mode,
they provide many of the PCS and PMA functions defined in the IEEE
802.3 specification; for example:
■
■
■
■
■
1
f
8B/10B encoding/decoding
Synchronization
Upstream transmitter and local receiver clock frequency
compensation (rate matching)
Clock recovery from the encoded data forwarded by the receiver
PMD
Serialization/deserialization
Arria GX transceivers do not have built-in support for other PCS
functions, such as auto-negotiation, collision-detect, and
carrier-sense. If required, you must implement these functions
in PLD logic array or external circuits.
For more information about additional features available in the Arria GX
transceiver, refer to the GIGE-Enhanced sub-protocol in the Arria GX
Megafunction User Guide.
This section is organized into transmitter and receiver data path modules
when configured for GIGE mode. The description for each module only
covers details specific to GIGE functional mode support. This docuent
assumes that you are familiar with the IEEE 802.3 Ethernet specification.
f
For a general description of each module, refer to the Arria GX
Transceiver Architecture chapter in volume 2 of the Arria GX Device
Handbook.
GIGE Mode Transmitter Architecture
This section lists sub-blocks within the transmitter channel configured in
GIGE mode (Figure 2–12). The sub-blocks are described in order from the
PLD-Transceiver parallel interface to the serial transmitter buffer.
Figure 2–12. GIGE Transmitter Architecture
Transmitter PCS
PLD
Logic
Array
TX Phase
Compensation
FIFO
8B/10B
Encoder
Transmitter PMA
Serializer
CMU
Altera Corporation
May 2008
Reference
Clock
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
Clock Multiplier Unit (CMU)
The clock multiplier unit takes in a reference clock and synthesizes the
clocks that are used to clock the transmitter digital logic (PCS), the
serializer, and the PLD-transceiver interface.
f
For more details about CMU architecture, refer to the Clock Multiplier
Unit section in the Arria GX Transceiver Architecture chapter in volume 2
of the Arria GX Device Handbook.
In GIGE mode, the CMU block consists of:
■
■
Transmitter PLL that generates high-speed serial clock for the
serializer
Local clock divider block that generates low-speed parallel clock for
transmitter digital logic and PLD-transceiver interface
Input Reference Clock
You can select either a 62.5 MHz or 125 MHz input reference clock
frequency while configuring the transceiver in GIGE mode using the
Quartus II MegaWizard Plug-In Manager.
The reference clock input to the transmitter PLL can be derived from one
of three components:
■
■
■
One of the two available dedicated reference clock input pins
(REFCLK0 or REFCLK1) of the associated transceiver block
PLD global clock network (must be driven directly from an input
clock pin and cannot be driven by user logic or enhanced PLL)
Inter-transceiver block lines driven by reference clock input pins of
other transceiver blocks
1
Altera recommends using the dedicated reference clock input
pins (REFCLK0 or REFCLK1) to provide reference clock for the
transmitter PLL.
The reference clock divide-by-two pre-divider is bypassed in GIGE mode.
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Altera Corporation
May 2008
Gigabit Ethernet (GIGE) mode
Table 2–12 specifies the input reference clock options available in GIGE
mode.
Table 2–12. GIGE Mode Input Reference Clock Specification
Frequency
62.5 MHz
125 MHz
I/O Standard
1.2 V PCML,
1.5 V PCML,
3.3 V PCML, Differential LVPECL, LVDS
Coupling Termination
AC
On-chip
Clock Synthesis
In GIGE mode, the input reference clock of 125 MHz (or 62.5 MHz) is fed
to the transmitter PLL. Because the transmitter PLL implements a halfrate VCO, it multiplies the 125 MHz (or 62.5 MHz) input clock by 5 (or 10)
to generate a 625 MHz high-speed serial clock. This high-speed serial
clock feeds the local clock divider block in each GIGE channel
instantiated within the transceiver block.
The local clock divider in each channel of the transceiver block divides
the 625 MHz clock from the transmitter PLL by 5 to generate a 125 MHz
parallel clock. This low-speed parallel clock output from the local clock
divider block is used to clock the transmitter digital logic (PCS) of the
associated channel. The local clock divider block also forwards the
high-speed serial clock from the transmitter PLL to the serializer within
its associated channel.
1
Altera Corporation
May 2008
The Quartus II software automatically selects the appropriate
transmitter PLL bandwidth suited for GIGE data rate.
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
Figure 2–13 shows the CMU implemented in GIGE mode.
Figure 2–13. GIGE Mode CMU
CMU Block
Transmitter Channels [3:2]
Local Clock
TX Clock
Divider
Block
Gen(/5)
Block
625 MHz
125 MHz (62.5 MHz)
Reference
Clock
Transmitter
PLL
x5 (x10)
625 MHz
Transmitter High-Speed
Serial (625 MHz) and Low-Speed
Parallel (125 MHz) Clocks
625 MHz
Local Clock
TX Clock
Divider
Block
Gen
(/5)Block
Transmitter High-Speed
Serial (625 MHz) and Low-Speed
Parallel (125 MHz) Clocks
Transmitter Channels [1:0]
Transmitter Phase Compensation FIFO Buffer
The transmitter phase compensation FIFO buffer compensates for the
phase difference between the PLD clock that clocks in parallel data into
the transmitter and the PCS clock that clocks the rest of the transmitter
digital logic.
f
For more details about the transmitter phase compensation FIFO buffer
architecture, refer to the Transmitter Phase Compensation FIFO Buffer
section in the Arria GX Transceiver Architecture chapter in volume 2 of the
Arria GX Device Handbook.
In GIGE mode, the 125 MHz clock generated by the CMU local clock
divider is used to clock the read port of the FIFO buffer. This 125 MHz
clock is also forwarded to the PLD logic array (on the tx_clkout port).
If the tx_coreclk port is not instantiated, the clock signal on the
tx_clkout port is automatically routed back to clock the write side of
the transmitter phase compensation FIFO buffer. The 8-bit
PLD-transceiver interface clocked at 125 MHz results into an effective
GIGE data rate of 1 Gbps.
In GIGE mode, the transmitter phase compensation FIFO is four words
deep. The latency through the FIFO is two to three PLD-transceiver
interface clock cycles.
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May 2008
Gigabit Ethernet (GIGE) mode
Figure 2–14 shows the block diagram of transmitter phase compensation
FIFO in GIGE mode.
Figure 2–14. Transmitter Phase Compensation FIFO in GIGE Mode
Transmitter Channel
tx_datain[7:0]
Transmitter
Phase
Compensation
FIFO
From
PLD
wrclk
dataout[7:0]
To 8B/10B
Encoder
rdclk
tx_coreclk
125 MHz
125 MHz
125 MHz
CMU
Local Clock Divider
Block
/2
tx_clkout
8B/10B Encoder
In GIGE mode, the 8B/10B encoder clocks in 8-bit data and 1-bit control
identifier from the transmitter phase compensation FIFO and generates a
10-bit encoded data. The 10-bit encoded data is fed to the serializer.
f
For more details about the 8B/10B encoder functionality, refer to the
8B/10B Encoder section in the Arria GX Transceiver Architecture chapter
in volume 2 of the Arria GX Device Handbook.
GIGE Protocol — Ordered Sets and Special Code Groups
Table 2–13 lists ordered sets and special code groups used in the GIGE
functional mode.
Table 2–13. GIGE Ordered Sets (Part 1 of 2)
Altera Corporation
May 2008
Code
Group
Ordered Set
Number of
Code
Groups
Encoding
/C/
Configuration
—
Alternating /C1/ and /C2/
/C1/
Configuration 1
4
/K28.5/D21.5/Config_Reg
(1)
/C2/
Configuration 2
4
/K28.5/D2.2/Config_Reg
(1)
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Arria GX Transceiver Protocol Support and Additional Features
Table 2–13. GIGE Ordered Sets (Part 2 of 2)
Code
Group
Ordered Set
Number of
Code
Groups
/I/
IDLE
—
/I1/
IDLE 1
2
/K28.5/D5.6
/I2/
IDLE 2
2
/K28.5/D16.2
Encapsulation
—
—
/R/
Carrier_Extend
1
/K23.7/
/S/
Start_of_Packet
1
/K27.7/
/T/
End_of_Packet
1
/K29.7/
/V/
Error_Propagation
1
/K30.7/
Encoding
Correcting /I1/, Preserving
/I2/
Note to Table 2–13:
(1)
Two data code groups representing the Config_Reg value.
Idle Ordered-Set Generation
IEEE 802.3 requires the GIGE PHY to transmit idle ordered sets (/I/)
continuously and repetitively whenever the GMII is idle. This ensures
that the receiver maintains bit and word synchronization whenever there
is no active data to be transmitted.
In GIGE functional mode, any /Dx.y/ following a /K28.5/ comma is
replaced by the transmitter with either a /D5.6/ (/I1/ ordered set) or a
/D16.2/ (/I2/ ordered set), depending on the current running disparity.
The exception is when the data following the /K28.5/ is /D21.5/ (/C1/
ordered set) or /D2.2/ (/C2/) ordered set. If the running disparity before
the /K28.5/ is positive, a /I1/ ordered set is generated. If the running
disparity is negative, a /I2/ ordered set is generated. The disparity at the
end of a /I1/ is the opposite of that at the beginning of the /I1/. The
disparity at the end of a /I2/ is the same as the beginning running
disparity (right before the idle code group). This ensures a negative
running disparity at the end of an idle ordered set. A /Kx.y/ following a
/K28.5/ is not replaced.
Figure 2–15 shows the automatic idle ordered set generation. Note that
/D14.3/, /D24.0/, and /D15.8/ are replaced by /D5.6/ or /D16.2/ (for
/I1/, /I2/ ordered sets). /D21.5/ (part of the /C1/ order set) is not
replaced.
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May 2008
Gigabit Ethernet (GIGE) mode
Figure 2–15. Idle Ordered Set Generation in GIGE Mode
clock
tx_datain [ ]
K28.5
D14.3
K28.5
D24.0
K28.5
D15.8
K28.5
D21.5
Dx.y
tx_dataout
Dx.y
K28.5
D5.6
K28.5
D16.2
K28.5
D16.2
K28.5
D21.5
/I1/
Ordered Set
/I2/
/I2/
/C2/
Reset Condition
After power-up or reset, the GIGE transmitter outputs three /K28.5/
commas before user data can be sent. This affects the synchronization
ordered set transmission.
After reset (tx_digitalreset), the 8B/10B encoder automatically
sends three /K28.5/ commas. Depending on when you start outputting
the synchronization sequence, there could be an even or odd number of
/Dx.y/ sent as the transmitter before the synchronization sequence. The
last of the three automatically sent /K28.5/and the first user-sent /Dx.y/
are treated as one idle ordered set. This can be a problem if there are an
even number of /Dx.y/ transmitted before the start of the
synchronization sequence.
Figure 2–16 shows an example of even numbers of /Dx.y/ between the
last automatically sent /K28.5/ and the first user-sent /K28.5/. The first
user-sent ordered set is ignored, so three additional ordered sets are
required for proper synchronization. Figure 2–16 shows one don’t care
data between the tx_digitalreset signal going low and the first of
three automatic K28.5, but there could be more.
Figure 2–16. GIGE Synchronization Ordered Set Considerations After Reset
clock
tx_digitalreset
tx_dataout
K28.5
Altera Corporation
May 2008
xxx
K28.5
K28.5
K28.5
Dx.y
Dx.y
K28.5
Dx.y
K28.5
Dx.y
K28.5
Dx.y
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Arria GX Transceiver Protocol Support and Additional Features
Serializer
In GIGE mode, the 10-bit encoded data from the 8B/10B encoder is
clocked into the 10:1 serializer with the low-speed parallel clock at
125 MHz. The 10-bit data is clocked out of the serializer LSB to MSB at the
high-speed effective serial clock rate at 1250 MHz. The serial data output
of the serializer is fed into the transmitter output buffer.
f
For more details about the serializer architecture, refer to the Serializer
section in the Arria GX Transceiver Architecture chapter in volume 2 of the
Arria GX Device Handbook.
Transmitter Buffer
Table 2–14 shows the transmitter buffer settings when configured in
GIGE mode.
Table 2–14. Transmitter Buffer Settings in GIGE Mode
Settings
Value
I/O Standard
1.5-V PCML (1)
Programmable Differential Output
Voltage (VOD)
400 — 1200 mV
Common Mode Voltage (VCM)
Differential Termination
600 mV, 700 mV (1)
100 Ω (2)
Programmable Transmitter PreEmphasis
Enabled (3)
VCCH (Transmitter Buffer Power)
1.5 V
Notes to Table 2–14:
(1)
(2)
(3)
The common mode voltage (VCM) setting is selectable in the MegaWizard
Plug-In Manager.
The I/O standard and differential termination settings are defaulted to 1.5-V
PCML and 100 Ω , respectively. If you select any other setting for I/O standard
or differential termination in the Assignment Editor, the Quartus II compiler
will issue an error message.
The transmitter buffer has five programmable first post-tap pre-emphasis
settings.
GIGE Mode Receiver Architecture
This section lists sub-blocks within the receiver channel configured in
GIGE mode (Figure 2–17). The sub-blocks are described in order from the
serial receiver input buffer to the receiver phase compensation FIFO
buffer at the transceiver-PLD interface.
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May 2008
Gigabit Ethernet (GIGE) mode
Figure 2–17. GIGE Mode Receiver Architecture
Receiver PMA
Receiver PCS
PLD
Logic
Array
RX Phase
Compensation
FIFO
8B/10B
Decoder
Rate
Match
FIFO
DeSerializer
Word
Aligner
Clock
Recovery
Unit
Receiver
PLL
Reference
Clocks
Receiver Buffer
Table 2–15 shows the receiver buffer settings when configured in GIGE
mode.
Table 2–15. Receiver Buffer Settings in GIGE Mode
Settings
I/O Standard
Input Common Mode Voltage (Rx VCM)
Differential Termination
Programmable Equalization
Coupling
Value
1.2-V PCML, 1.5-V PCML,
3.3-V PCML, Differential LVPECL,
LVDS
850 mV, 1200 mV (1)
100 Ω (2)
Enabled (3)
AC
Notes to Table 2–15:
(1)
(2)
(3)
The common mode voltage (Rx VCM) is selectable in the MegaWizard Plug-In
Manager.
The differential termination setting is defaulted to 100 Ω . If you select any other
setting for differential termination in the Assignment Editor, the Quartus II
compiler will issue an error message.
The receiver buffer has five programmable equalization settings.
Receiver PLL and Clock Recovery Unit
In GIGE mode, the receiver PLL in each transceiver channel is fed by a
125 MHz or a 62.5 MHz input reference clock. The receiver PLL in
conjunction with the CRU generates two clocks: a high-speed serial
recovered clock at 625 MHz (half-rate PLL) that feeds the deserializer and
a low-speed parallel recovered clock at 125 MHz that feeds the receiver’s
digital logic.
You can set the clock recovery unit in either automatic lock mode or
manual lock mode. In automatic lock mode, the PPM detector and the
phase detector within the receiver channel automatically switches the
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May 2008
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
receiver PLL between lock-to-reference and lock-to-data modes. In
manual lock mode, you can control the receiver PLL switch between
lock-to-reference and lock-to-data modes via the rx_locktorefclk
and rx_locktodata signals.
f
For more details about the CRU lock modes, refer to the Receiver PLL
and Clock Recovery Unit section in the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device Handbook.
The reference clock input to the receiver PLL can be derived from:
■
■
■
One of the two available dedicated reference clock input pins
(REFCLK0 or REFCLK1) of the associated transceiver block
PLD global clock network (must be driven directly from an input
clock pin and cannot be driven by user logic or enhanced PLL)
Inter-transceiver block lines driven by reference clock input pins of
other transceiver blocks
Table 2–16 specifies the input reference clock options available in GIGE
mode.
Table 2–16. GIGE Mode Input Reference Clock Specification
Frequency
125 MHz
62.5 MHz
I/O Standard
Coupling
Termination
1.2 V PCML,
1.5 V PCML,
3.3 V PCML, Differential LVPECL, LVDS
AC
On-chip
Deserializer
The 1:10 deserializer clocks in serial data from the receiver buffer using
the high-speed recovered clock. The 10-bit de-serialized data is clocked
out to the word aligner using the low-speed recovered clock at 125 MHz.
The deserializer assumes that the transmission bit order is LSB to MSB;
for example, the LSB of a data word is received earlier in time than its
MSB.
f
For more details about the deserializer architecture, refer to the
Deserializer section in the Arria GX Transceiver Architecture chapter in
volume 2 of the Arria GX Device Handbook.
2–36
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Altera Corporation
May 2008
Gigabit Ethernet (GIGE) mode
Word Aligner
The word aligner clocks in the 10-bit data from the deserializer and
restores the word boundary of the upstream transmitter. Besides
restoring the word boundary, it also implements a synchronization state
machine as specified in the IEEE 802.3 specification to achieve receiver
synchronization.
In GIGE mode, the word aligner is comprised of the following three
modules:
■
■
■
Pattern detector module
Pattern aligner module
Run-length violation detector module
Pattern Detector
In GIGE mode, the Quartus II software automatically configures 10-bit
K28.5 (10'b0101111100) as the word alignment pattern. After coming out
of reset (rx_digitalreset), when the pattern detector detects either
disparities of the K28.5 control word, it asserts the rx_patterndetect
signal for one parallel clock cycle. When the pattern aligner has aligned
the incoming data to the desired word boundary, the pattern detector
asserts the rx_patterndetect signal only if the word alignment
pattern is found in the current word boundary.
Pattern Aligner
In GIGE mode, the pattern aligner incorporates an automatic
synchronization state machine. The Quartus II software automatically
configures the synchronization state machine to indicate synchronization
when the receiver receives three consecutive synchronization ordered
sets. An ordered set defined for synchronization is a /K28.5/ code group
followed by an odd number of valid /Dx.y/ code groups. The fastest way
for the receiver to achieve synchronization is to receive three continuous
{/K28.5/, /Dx.y/} ordered sets.
Receiver synchronization is indicated on the rx_syncstatus port of
each channel. A high on the rx_syncstatus port indicates that the lane
is synchronized and a low indicates that it has fallen out of
synchronization. The receiver loses synchronization when it detects four
invalid code groups separated by less than three valid code groups or
when it is reset.
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May 2008
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
Table 2–17 lists the synchronization state machine parameters when
configured in GIGE mode.
Table 2–17. Synchronization State Machine Parameters in GIGE Mode
Number of valid {/K28.5/, /Dx,y/} ordered-sets received to achieve synchronization
3
Number of errors received to lose synchronization
4
Number of continuous good code groups received to reduce the error count by 1
4
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May 2008
Gigabit Ethernet (GIGE) mode
Figure 2–18 shows the synchronization state machine implemented in
GIGE mode.
Figure 2–18. GIGE Synchronization State Machine
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May 2008
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
The word aligner block asserts an error flag on the rx_disperr and
rx_errdetect ports if the received 10-bit code is detected with
incorrect running disparity. The error flag signal (rx_disperr) has the
same delay from the word aligner to the PLD-transceiver interface as the
received data.
Rate Matcher
In GIGE mode, the rate matcher can compensate up to ±100 PPM
(200 PPM total) frequency difference between the upstream transmitter
and the receiver. The write port of the rate matcher FIFO in each receiver
channel is clocked by its low-speed parallel recovered clock. The read
port is clocked by the low-speed parallel clock output of the CMU local
clock divider block.
The rate matcher logic inserts or deletes /I2/ idle ordered-sets to/from
the rate matcher FIFO during the inter-frame or inter-packet gap (IFG or
IPG). /I2/ is selected as the rate matching ordered-set since it maintains
the running disparity unlike /I1/ that alters the running disparity. Since
the /I2/ ordered-set contains two 10-bit code groups (/K28.5/, /D16.2/),
twenty bits are inserted or deleted at a time for rate matching.
1
f
The rate matcher logic has the capability to insert or delete /C1/
or /C2/ configuration ordered sets when GIGE-Enhanced mode
is chosen as the sub-protocol in the MegaWizard Plug-In
Manager.
Refer to the Arria GX ALT2GXB Megafunction User Guide for details on
GIGE-Enhanced mode.
Figure 2–19 shows an example of /I2/ deletion and Figure 2–20 shows an
example of /I2/ insertion in a GIGE mode rate matcher.
Figure 2–19. GIGE Rate Matcher /I2/ Deletion
/D/
/D/
/D/
From Rate Matcher
/D/
/D/
/D/
/S/
/D/
/I2/ /I2/
/D/
/D/
To Rate Matcher
/I1/
/D/
/D/
/S/
/I2/
/I1/
One /I2/ Code Removed
2–40
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Gigabit Ethernet (GIGE) mode
Figure 2–20. GIGE Rate Matcher /I2/ Insertion
/D/
/D/
From Rate Matcher
/D/
/D/
/D/
/D/
/S/
/D/
/I2/
/D/
/I2/
/D/
To Rate Matcher
/I1/
/D/
/D/
/S/
/I2/
/I2/
/I2/
/I1/
One /I2/ Code Added
If the frequency PPM difference between the upstream transmitter and
the local receiver is high or if the packet size is too large, the rate matcher
FIFO buffer can face an overflow or underflow situation.
8B/10B Decoder
In GIGE mode, the 8B/10B decoder clocks in 10-bit data from the rate
matcher and decodes it into 8-bit data + 1-bit control identifier. The 10-bit
decoded data is fed to the receiver phase compensation FIFO buffer.
f
For more details about the 8B/10B decoder functionality, refer to the
8B/10B Encoder section in the Arria GX Transceiver Architecture chapter
in volume 2 of the Arria GX Device Handbook.
If the received 10-bit code group is not a part of valid Dx.y or Kx.y code
groups, the 8B/10B decoder block asserts an error flag on the
rx_errdetect port. The error flag signal (rx_errdetect) has the
same data path delay from the 8B/10B decoder to the PLD-transceiver
interface as the invalid code group.
Receiver Phase Compensation FIFO
The receiver phase compensation FIFO buffer compensates for the phase
difference between the local receiver PLD clock and the receiver PCS
clock.
f
For more details about the receiver phase compensation FIFO buffer
architecture, refer to the Receiver Phase Compensation FIFO section in
the Arria GX Transceiver Architecture chapter in volume 2 of the Arria GX
Device Handbook.
In GIGE mode, the 125 MHz clock generated by the CMU local clock
divider block clocks the write port of the FIFO buffer. This 125 MHz clock
is also forwarded to the PLD logic array (on the corresponding
tx_clkout port). If the rx_coreclk port is not instantiated, the clock
signal on the tx_clkout port is automatically routed back to clock the
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May 2008
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
read side of the receiver phase compensation FIFO buffer. The 8-bit
PLD-receiver interface clocked at 125 MHz results in an effective GIGE
data rate of 1 Gbps.
In GIGE mode, the receiver phase compensation FIFO is four words deep.
The latency through the FIFO is one to two PLD-transceiver interface
clock cycles.
Figure 2–21 shows the block diagram of receiver phase compensation
FIFO in GIGE mode.
Figure 2–21. Receiver Phase Compensation FIFO in GIGE Mode
Receiver Channel
rx_dataout[7:0]
datain[7:0]
Receiver Phase
Compensation
FIFO
From 8B/10B
Decoder
To PLD
wrclk
Low-Speed Parallel
CMU Clock
125 MHz
125 MHz
/2
rdclk
rx_coreclk
125 MHz
tx_clkout
UNH-IOL Gigabit Ethernet Compliance
For UNH-IOL compliance in GIGE mode, the following architectural
features are available when GIGE-Enhanced sub-protocol is chosen in the
Megawizard Plug-In Manager.
■
■
f
7-bit word alignment using the synchronization state machine.
Insertion and deletion of /C1/ and /C2/configuration ordered sets
by the rate matcher during the Auto-negotiation phase.
Refer to the Arria GX ALT2GXB Megafunction User Guide for details
regarding additional ports generated for GIGE-Enhanced mode.
2–42
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Altera Corporation
May 2008
Serial RapidIO Mode
Serial RapidIO
Mode
The RapidIO standard is a high-performance, packet-switched
interconnect technology designed to pass data and control information
between microprocessors, digital signal, communications, and network
processors, system memories, and peripheral devices. Serial RapidIO
physical layer specification defines three line rates at 1.25 Gbps, 2.5 Gbps,
and 3.125 Gbps. It also supports two link widths — single-lane (×1) and
bonded four-lane (×4) at each line rate.
Arria GX transceivers support both single-lane (×1) and four-lane (×4)
Serial RapidIO link widths at 1.25 Gbps and 2.5 Gbps and single-lane link
widths at 3.125 Gbps. In ×4 Serial RapidIO mode, the four transceiver
channels are not bonded and are clocked independently, as four
individual channels.
When configured in Serial RapidIO functional mode, Arria GX
transceivers provide the following PCS and PMA functions:
■
■
■
■
■
1
8B/10B encoding/decoding
Word alignment
Lane Synchronization State Machine
Clock recovery from the encoded data
Serialization/deserialization
Arria GX transceivers do not have built-in support for other PCS
functions, such as clock frequency compensation between
upstream transmitter clock and local receiver clock (rate
matcher), idle sequence generation, and lane alignment in ×4
mode. Depending on your system requirements, you must
implement these functions in the logic array or external circuits.
This section is organized into transmitter and receiver data path modules
when configured for Serial RapidIO mode. The description for each
module only covers details specific to Serial RapidIO functional mode
support. This document assumes that you are familiar with the RapidIO
Interconnect Specification v1.3.
f
For a general description of each module, refer to the Arria GX
Transceiver Architecture chapter in volume 2 of the Arria GX Device
Handbook.
Serial RapidIO Mode Transmitter Architecture
This section lists sub-blocks within the transmitter channel configured in
Serial RapidIO mode (Figure 2–22). The sub-blocks are described from
the PLD-Transceiver parallel interface to the serial transmitter buffer.
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May 2008
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Arria GX Transceiver Protocol Support and Additional Features
Figure 2–22. Serial RapidIO Transmitter Architecture
Transmitter PCS
PLD
Logic
Array
TX Phase
Compensation
FIFO
Byte
Serializer
8B/10B
Encoder
Transmitter PMA
Serializer
CMU
Reference
Clock
Clock Multiplier Unit (CMU)
The clock multiplier unit takes in a reference clock and synthesizes the
clocks that are used to clock the transmitter digital logic (PCS), the
serializer, and the PLD-transceiver interface.
f
For more details about CMU architecture, refer to the Clock Multiplier
Unit section in the Arria GX Transceiver Architecture chapter in volume 2
of the Arria GX Device Handbook.
In Serial RapidIO mode, the CMU block consists of:
■
■
Transmitter PLL that generates high-speed serial clock for the
serializer
Local clock divider block that generates low-speed parallel clock for
transmitter digital logic and PLD-transceiver interface
Input Reference Clock
Table 2–18 lists the input reference clock frequencies allowed in Serial
RapidIO mode.
The reference clock input to the transmitter PLL can be derived from:
■
■
■
One of the two available dedicated reference clock input pins
(REFCLK0 or REFCLK1) of the associated transceiver block
PLD global clock network (must be driven directly from an input
clock pin and cannot be driven by user logic or enhanced PLL)
Inter-transceiver block lines driven by reference clock input pins of
other transceiver blocks
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Altera Corporation
May 2008
Serial RapidIO Mode
1
Altera recommends using the dedicated reference clock input
pins (REFCLK0 or REFCLK1) to provide reference clock for the
transmitter PLL.
Table 2–18. Serial RapidIO Mode Input Reference Clock Specifications
Data Rate
(Gbps)
Reference Clock Frequency (MHz)
I/O Standard
1.25
62.5, 78.125, 125, 156.25, 250, 312.5
2.5
50, 62.5, 78.125, 100, 125, 156.25, 250,
312.5, 500
3.125
Coupling Termination
1.2V PCML, 1.5V PCML, 3.3V
PCML, Differential LVPECL,
LVDS
AC
On-chip
62.5, 78.125, 97.6563, 125, 156.25,
195.3125, 312.5, 390.625
Clock Synthesis
In Serial RapidIO mode, the input reference clock is fed to the transmitter
PLL. Because the transmitter PLL implements a half-rate VCO, it
multiplies the input reference clock to generate a 625-MHz (1.25-Gbps
Serial RapidIO) or 1250-MHz (2.5 Gbps Serial RapidIO) or 1562.5-MHz
(3.125-Gbps Serial RapidIO) high-speed serial clock. This high-speed
serial clock feeds the local clock divider block in each Serial RapidIO
channel instantiated within the transceiver block. Table 2–19 lists the
transmitter PLL multiplication factors that the Quartus II software
automatically selects, depending on the Serial RapidIO data rate and
input reference clock frequency selection.
Table 2–19. Serial RapidIO Mode Transmitter PLL Multiplication Factors
(Part 1 of 2)
Data Rate
(Gbps)
1.25
Altera Corporation
May 2008
Reference Clock
Frequency (MHz)
Transmitter PLL Multiplication
Factor
62.5
10
78.125
8
125
5
156.25
4
250 (pre-divide by 2)
5
312.5
2
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Arria GX Transceiver Protocol Support and Additional Features
Table 2–19. Serial RapidIO Mode Transmitter PLL Multiplication Factors
(Part 2 of 2)
Data Rate
(Gbps)
2.5
3.125
Reference Clock
Frequency (MHz)
Transmitter PLL Multiplication
Factor
50
25
62.5
20
78.125
16
100 (pre-divide by 2)
25
125
10
156.25
8
250
5
312.5
4
500 (pre-divide by 2)
5
62.5
25
78.125
20
97.6563
16
125 (pre-divide by 2)
25
156.25
10
195.3125
8
312.5
5
390.625 (pre-divide by 2)
8
In Serial RapidIO 1.25-Gbps (2.5-Gbps, 3.125-Gbps) mode, the local clock
divider in each channel of the transceiver block divides the 625-MHz
(1250-MHz, 1562.5-MHz) clock from the transmitter PLL by five to
generate a 125-MHz (250-MHz, 312.5-MHz) parallel clock. This
low-speed parallel clock output from the local clock divider block is used
to clock the transmitter digital logic (PCS) of the associated channel. The
local clock divider block also forwards the high-speed serial clock from
the transmitter PLL to the serializer within its associated channel.
1
The Quartus II software automatically selects the appropriate
transmitter PLL bandwidth suited for Serial RapidIO data rate.
Transmitter Phase Compensation FIFO Buffer
The transmitter phase compensation FIFO buffer compensates for the
phase difference between the PLD clock that clocks in parallel data into
the transmitter and the PCS clock that clocks the rest of the transmitter
digital logic.
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Altera Corporation
May 2008
Serial RapidIO Mode
f
For more details about the transmitter phase compensation FIFO buffer
architecture, refer to the transmitter Phase Compensation FIFO section in
the Arria GX Transceiver Architecture chapter in volume 2 of the Arria GX
Device Handbook.
In Serial RapidIO 1.25-Gbps (2.5-Gbps, 3.125-Gbps) mode, the 125-MHz
(250-MHz, 312.5-MHz) clock generated by the CMU clock divider block
is divided by 2. The resulting 62.5-MHz (125-MHz, 156.25-MHz) clock is
used to clock the read port of the FIFO buffer. This divide-by-two clock is
also forwarded to the PLD logic array (on the tx_clkout port of its
associated channel). If the tx_coreclk port is not instantiated, the clock
signal on the tx_clkout port is automatically routed back to clock the
write side of the transmitter phase compensation FIFO buffer. The 16-bit
PLD-transceiver interface clocked at 62.5 MHz (125 MHz, 156.25 MHz)
results into an effective Serial RapidIO data rate of 1.25 Gbps (2.5 Gbps,
3.125 Gbps).
In Serial RapidIO mode, the transmitter phase compensation FIFO is four
words deep. The latency through the FIFO is two to three
PLD-transceiver interface clock cycles.
Figure 2–23 shows the block diagram of transmitter phase compensation
FIFO in Serial RapidIO mode.
Figure 2–23. Transmitter Phase Compensation FIFO in Serial RapidIO Mode Note (1)
Transmitter Channel
From
PLD
tx_coreclk
dataout[15:0]
Transmitter
Phase
Compensation
FIFO
tx_datain[15:0]
wrclk
62.5 MHz
(125 MHz, 156.25 MHz)
To 8B/10B
Encoder
rdclk
62.5 MHz
(125 MHz, 156.25 MHz)
125 MHz (250 MHz, 312.5)
/2
CMU
Local Clock Divider
Block
tx_clkout
Note to Figure 2–23:
(1)
The clock frequencies inside the parenthesis apply to 2.5 Gbps and 3.125 Gbps Serial RapidIO mode and the ones
outside apply to 1.25 Gbps Serial RapidIO mode.
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May 2008
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Arria GX Transceiver Protocol Support and Additional Features
Byte Serializer
In Serial RapidIO 1.25 Gbps (2.5 Gbps, 3.125 Gbps) mode, the
PLD-transceiver interface data is 16 bits wide and is clocked into the
transmitter phase compensation FIFO at 62.5 MHz (125 MHz,
156.25 MHz). The byte serializer clocks in the 16-bit wide data from the
transmitter phase compensation FIFO at 62.5 MHz (125 MHz,
156.25 MHz) and clocks out 8-bit data to the 8B/10B encoder at 125 MHz
(250 MHz, 312.5 MHz). This allows clocking the PLD-transceiver
interface at half the speed.
f
For more details about the byte serializer architecture, refer to the Byte
Serializer section in the Arria GX Transceiver Architecture chapter in
volume 2 of the Arria GX Device Handbook.
The write port of the byte serializer is clocked by the divide-by-two
version of the low-speed parallel clock from CMU. The read port is
clocked by the low-speed parallel clock from CMU. The byte serializer
clocks out the least significant byte of the 16-bit data first and the most
significant byte last.
Figure 2–24 shows the block diagram of the byte serializer in Serial
RapidIO mode.
Figure 2–24. Byte Serializer in Serial RapidIO Mode Note (1)
datain[15:0]
dataout[7:0]
Byte Serializer
From Transmitter
Phase Compensation
FIFO
To 8B/10B
Encoder
wrclk
rdclk
125 MHz (250 MHz, 312.5 MHz)
62.5 MHz (125 MHz, 156.25 MHz)
62.5 MHz
(125 MHz, 156.25 MHz)
Divide-by-Two Version
of Low-Speed
Parallel Clock
/2
125 MHz
(250 MHz, 312.5 MHz)
Low-Speed
Parallel Clock
CMU
Local/Central Clock
Divider Block
Note to Figure 2–24:
(1)
The clock frequencies inside the parenthesis apply to 2.5 Gbps and 3.125 Gbps Serial RapidIO mode and the ones
outside apply to 1.25 Gbps Serial RapidIO mode.
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May 2008
Serial RapidIO Mode
8B/10B Encoder
In Serial RapidIO mode, the 8B/10B encoder clocks in 8-bit data and 1-bit
control identifier from the transmitter phase compensation FIFO and
generates a 10-bit encoded data. The 10-bit encoded data is fed to the
serializer.
f
For more details about the 8B/10B encoder functionality, refer to the
8B/10B Encoder section in the Arria GX Transceiver Architecture chapter
in volume 2 of the Arria GX Device Handbook.
Serializer
In Serial RapidIO 1.25 Gbps (2.5 Gbps, 3.125 Gbps) mode, the 10-bit
encoded data from the 8B/10B encoder is clocked into the 10:1 serializer
with the low-speed parallel clock at 125 MHz (250 MHz, 312.5 MHz). The
10-bit data is clocked out of the serializer LSB to MSB at the high-speed
effective serial clock rate at 1250 MHz (2500 MHz, 3125 MHz). The serial
data output of the serializer is fed into the transmitter output buffer.
f
For more details about the serializer architecture, refer to the Serializer
section in the Arria GX Transceiver Architecture chapter in volume 2 of the
Arria GX Device Handbook.
Transmitter Buffer
Table 2–20 shows the transmitter buffer settings when configured in
Serial RapidIO mode.
Table 2–20. Transmitter Buffer Settings in Serial RapidIO Mode
(Part 1 of 2)
Settings
I/O Standard
1.5-V PCML (1)
Programmable Differential Output
Voltage (VOD)
400 - 1200 mV
Common Mode Voltage (VCM)
Differential Termination
Programmable pre-emphasis
Altera Corporation
May 2008
Value
600 mV, 700 mV (1)
100 Ω (2)
Enabled (3)
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
Table 2–20. Transmitter Buffer Settings in Serial RapidIO Mode
(Part 2 of 2)
Settings
Value
VCCH (Transmitter Buffer Power)
1.5 V
Notes to Table 2–20:
(1)
(2)
(3)
The common mode voltage (VCM) setting is selectable in the MegaWizard Plug-In
Manager.
The I/O standard and differential termination settings are defaulted to 1.5-V
PCML and 100 Ω , respectively. If you select any other setting for the I/O standard
or differential termination in the Assignment Editor, the Quartus II compiler
issues an error message.
The transmitter buffer has five programmable first post-tap pre-emphasis
settings.
Serial RapidIO Mode Receiver Architecture
This section lists sub-blocks within the receiver channel configured in
Serial RapidIO mode (Figure 2–25). The sub-blocks are described in order
from the serial receiver input buffer to the receiver phase compensation
FIFO buffer at the transceiver-PLD interface.
Figure 2–25. Serial RapidIO Mode Receiver Architecture
Receiver PCS
PLD
Logic
Array
RX Phase
Compensation FIFO
Byte
DeSerializer
8B/10B
Decoder
Word
Aligner
Receiver PMA
DeSerializer
Clock
Recovery
Unit
Receiver
PLL
Reference
Clocks
Receiver Buffer
Table 2–21 shows the receiver buffer settings when configured in Serial
RapidIO mode.
Table 2–21. Receiver Buffer Settings in Serial RapidIO Mode (Part 1 of 2)
Settings
I/O Standard
Input Common Mode Voltage (Rx VCM)
2–50
Arria GX Device Handbook, Volume 2
Value
1.2-V PCML, 1.5-V PCML,
3.3-V PCML, Differential LVPECL,
LVDS
850 mV, 1200 mV (1)
Altera Corporation
May 2008
Serial RapidIO Mode
Table 2–21. Receiver Buffer Settings in Serial RapidIO Mode (Part 2 of 2)
Settings
Value
100 Ω (2)
Differential Termination
Enabled (3)
Programmable Equalization
Coupling
AC
Notes to Table 2–21:
(1)
(2)
(3)
The common mode voltage (Rx VCM) is selectable in the MegaWizard Plug-In
Manager.
The differential termination setting is defaulted to 100 Ω . If you select any other
setting for differential termination in the Assignment Editor, the Quartus II
compiler issues an error message.
The receiver buffer has five programmable equalization settings.
Receiver PLL and Clock Recovery Unit
In Serial RapidIO 1.25 Gbps (2.5 Gbps, 3.125 Gbps) mode, the receiver
PLL in each transceiver channel is fed by an input reference clock. The
receiver PLL in conjunction with the clock recovery unit generates two
clocks: a half-rate high-speed serial recovered clock at 625 MHz
(1250 MHz, 1562.5 MHz) that feeds the deserializer and a low-speed
parallel recovered clock at 125 MHz (250 MHz, 312.5 MHz) that feeds the
receiver’s digital logic.
You can set the clock recovery unit in either automatic lock mode or
manual lock mode. In automatic lock mode, the PPM detector and the
phase detector within the receiver channel automatically switch the
receiver PLL between lock-to-reference and lock-to-data modes. In
manual lock mode, you can control the receiver PLL switch between
lock-to-reference and lock-to-data modes via the rx_locktorefclk
and rx_locktodata signals.
f
For more details about the CRU lock modes, refer to the Receiver PLL
section and Clock Recovery Unit (CRU) section in the Arria GX
Transceiver Architecture chapter in volume 2 of the Arria GX Device
Handbook.
The reference clock input to the receiver PLL can be derived from one of
the following components:
■
■
■
Altera Corporation
May 2008
One of the two available dedicated reference clock input pins
(REFCLK0 or REFCLK1) of the associated transceiver block
PLD global clock network (must be driven directly from an input
clock pin and cannot be driven by user logic or enhanced PLL)
Inter-transceiver block lines driven by reference clock input pins of
other transceiver blocks
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
Table 2–22 specifies the receiver input reference clock options available in
Serial RapidIO mode.
Table 2–22. Serial RapidIO Mode Input Reference Clock Specifications
Data Rate
(Gbps)
Reference Clock Frequency
(MHz)
1.25
62.5, 78.125,125, 156.25,
250, 312.5
2.5
50, 62.5, 78.125, 100, 125,
156.25, 250, 312.5, 500
3.125
62.5, 78.125, 97.6563, 125,
156.25, 195.3125, 312.5,
390.625
I/O Standard
1.2 V PCML, 1.5 V PCML, 3.3 V PCML,
Differential LVPECL, LVDS
Coupling Termination
AC
On-chip
Deserializer
In Serial RapidIO 1.25 Gbps (2.5 Gbps, 3.125 Gbps) mode, the 1:10
deserializer clocks in serial data from the receiver buffer using the
high-speed serial recovered clock. The 10-bit de-serialized data is clocked
out to the word aligner using the low-speed parallel recovered clock at
125 MHz (250 MHz, 312.5 MHz). The deserializer assumes that the
transmission bit order is LSB to MSB; that is, the LSB of a data word is
received earlier in time than its MSB.
f
For more details on the deserializer architecture, refer to the Deserializer
section in the Arria GX Transceiver Architecture chapter in volume 2 of the
Arria GX Device Handbook.
Word Aligner
The word aligner clocks in the 10-bit data from the deserializer and
restores the word boundary of the upstream transmitter.
f
For more details about the word aligner architecture, refer to the section
“Word Aligner” on page 2–13 in the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device Handbook.
In Serial RapidIO mode, the word aligner comprises of the following
three modules:
■
■
■
Pattern detector module
Pattern aligner module
Run-length violation detection module
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Altera Corporation
May 2008
Serial RapidIO Mode
Pattern Detector
In Serial RapidIO mode, the Quartus II software automatically configures
10-bit K28.5 (10'b0101111100) as the word alignment pattern. After
coming out of reset (rx_digitalreset), when the pattern detector
detects either disparities of the K28.5 control word, it asserts the
rx_patterndetect signal for one parallel clock cycle. When the
pattern aligner has aligned the incoming data to the desired word
boundary, the pattern detector asserts rx_patterndetect signal only
if the word alignment pattern is found in the current word boundary.
Pattern Aligner
In Serial RapidIO mode, the pattern aligner employs an automatic
synchronization state machine. The Quartus II software automatically
configures the synchronization state machine to indicate synchronization
when the receiver receives 127 K28.5 (10'b0101111100 or 10'b1010000011)
synchronization code groups without receiving an intermediate invalid
code group. Once synchronized, the state machine indicates loss of
synchronization when it detects three invalid code groups separated by
fewer than 255 valid code groups or when it is reset.
Receiver synchronization is indicated on the rx_syncstatus port of
each channel. A high on the rx_syncstatus port indicates that the lane
is synchronized and a low indicates that it has fallen out of
synchronization.
Table 2–23 lists the synchronization state machine parameters when
configured in Serial RapidIO mode.
Table 2–23. Synchronization State Machine Parameters in Serial RapidIO
Mode
Number of valid K28.5 code groups received to achieve
synchronization
Number of errors received to lose synchronization
Number of continuous good code groups received to reduce
the error count by 1
1
Altera Corporation
May 2008
127
3
255
In an 8B/10B encoded data stream, a /K28.7/ special code
group followed by any of the data code groups /D3.y/,
/D11.y/, /D12.y/, /D19.y/, /D20.y/, /D28.y/ or /K28.y/
(where y ranges from 0 to 7), may cause the /K28.5/ alignment
pattern to appear across the word boundary. Serial RapidIO
protocol allows /K28.7/ transmission only during test and
debug.
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Arria GX Transceiver Protocol Support and Additional Features
Figure 2–26 shows the synchronization state machine implemented in
Serial RapidIO functional mode.
Figure 2–26. Synchronization State Machine in Serial RapidIO Mode
Loss of Sync
Data = Comma
Data = !Valid
Comma Detect
if Data == Comma
kcntr++
else
kcntr=kcntr
Data = valid;
kcntr <3
kcntr = 127
Synchronized
Data=Valid
Data = !Valid
ecntr = 3
Synchronized Error
Detect
if Data == !valid
ecntr++
gcntr=0
else
if gcntr==255
ecntr-gcntr=0
else
gcntr++
ecntr = 0
The word aligner block asserts an error flag on the rx_disperr and
rx_errdetect ports if the received 10-bit code is detected with
incorrect running disparity. The error flag signal (rx_disperr) has the
same delay from the word aligner to the PLD-transceiver interface as the
received data.
8B/10B Decoder
In Serial RapidIO mode, the 8B/10B decoder clocks in 10-bit data from the
word aligner and decodes it into 8-bit data + 1-bit control identifier. The
8-bit decoded data is fed to the byte deserializer.
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May 2008
Serial RapidIO Mode
f
For more details about the 8B/10B decoder functionality, refer to the
8B/10B Decoder section in the Arria GX Transceiver Architecture chapter
in volume 2 of the Arria GX Device Handbook.
If the received 10-bit code group is not a part of valid Dx.y or Kx.y code
groups, the 8B/10B decoder block asserts an error flag on the
rx_errdetect port. The error flag signal (rx_errdetect) has the
same data path delay from the 8B/10B decoder to the PLD-transceiver
interface as the invalid code group.
Byte Deserializer
In Serial RapidIO 1.25 Gbps (2.5 Gbps, 3.125 Gbps) mode, the
PLD-receiver interface data is 16 bits wide and is clocked out of the
receiver phase compensation FIFO at 62.5 MHz (125 MHz, 156.25 MHz).
The byte deserializer clocks in the 8-bit wide data from the 8B/10B
decoder at 125 MHz (250 MHz, 312.5 MHz) and clocks out 16-bit wide
data to the receiver phase compensation FIFO at 62.5 MHz (125 MHz,
156.25 MHz). This allows clocking the PLD-transceiver interface at half
the speed.
f
For more details about byte deserializer architecture, refer to the Byte
Deserializer section in the Arria GX Transceiver Architecture chapter in
volume 2 of the Arria GX Device Handbook.
In Serial RapidIO mode, the write port of the byte deserializer is clocked
by the low-speed parallel recovered clock and the read port is clocked by
divide-by-two version of this clock.
Due to 8-bit to 16-bit byte deserialization, the byte ordering at the
PLD-receiver interface might be incorrect. If required, you must
implement the byte ordering logic in the PLD core to correct for this
situation.
Altera Corporation
May 2008
2–55
Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
Figure 2–27 shows the block diagram of the byte deserializer in Serial
RapidIO mode.
Figure 2–27. Byte Deserializer in Serial RapidIO Mode Note (1)
dataout[15:0]
datain[7:0]
Byte
Deserializer
To Receiver Phase
Compensation
FIFO
From 8B/10B
Decoder
wrclk
rdclk
62.5 MHz (125 MHz, 156.25 MHz)
125 MHz (250 MHz, 312.5 MHz)
/2
Low-Speed Parallel Recovered Clock
Note to Figure 2–27:
(1)
The clock frequencies inside the parenthesis apply to 2.5 Gbps and 3.125 Gbps Serial RapidIO mode and the ones
outside apply to 1.25 Gbps Serial RapidIO mode.
Receiver Phase Compensation FIFO Buffer
The receiver phase compensation FIFO buffer compensates for the phase
difference between the local receiver PLD clock and the receiver PCS
clock.
f
For more details about the receiver phase compensation FIFO buffer
architecture, refer to the Receiver Phase Compensation FIFO Buffer
section in the Arria GX Transceiver Architecture chapter in volume 2 of the
Arria GX Device Handbook.
In Serial RapidIO 1.25 Gbps (2.5 Gbps, 3.125 Gbps) mode, the 125 MHz
(250 MHz, 312.5 MHz) low-speed parallel recovered clock is divided by
2. The resulting 62.5 MHz (125 MHz, 156.25 MHz) clock is used to clock
the write port of the FIFO buffer. This divide-by-two clock is also
forwarded to the PLD logic array (on the rx_clkout port). If the
rx_coreclk port is not instantiated, the recovered clock signal on the
rx_clkout port is automatically routed back to clock the read side of the
receiver phase compensation FIFO buffer. The 16-bit PLD-receiver
interface clocked at 62.5 MHz (125 MHz, 156.25 MHz) results into an
effective Serial RapidIO data rate of 1 Gbps (2 Gbps, 3.125 Gbps).
In Serial RapidIO mode, the receiver phase compensation FIFO is four
words deep. The latency through the FIFO is one to two PLD-transceiver
interface clock cycles.
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May 2008
Basic Single-Width Mode
Figure 2–28 shows the block diagram of receiver phase compensation
FIFO in Serial RapidIO mode.
Figure 2–28. Receiver Phase Compensation FIFO in RapidIO Mode Note (1)
Receiver Channel
datain[15:0]
From Byte
Deserializer
wrclk
62.5 MHz (125 MHz, 156.25 MHz)
125 MHz (250 MHz, 312.5 MHz)
/2
rx_dataout[15:0]
Receiver Phase
Compensation
FIFO
To PLD
rdclk
rx_coreclk
62.5 MHz (125 MHz, 156.25 MHz)
Low -speed parallel
recovered clock
rx_clkout
Note to Figure 2–28:
(1)
The clock frequencies inside the parenthesis apply to 2.5 Gbps and 3.125 Gbps Serial RapidIO mode and the ones
outside apply to 1.25 Gbps Serial RapidIO mode.
Basic
Single-Width
Mode
Use the Basic single-width mode for custom protocols that are not part of
the pre-defined supported protocols; for example, PIPE. With some
restrictions, the following PCS blocks are available:
■
■
■
■
■
■
■
■
■
Transmitter phase compensation FIFO buffer
Transmitter byte serializer
8B/10B encoder
Word aligner
Rate matcher
8B/10B decoder
Byte deserializer
Byte ordering block
Receiver phase compensation FIFO buffer
The byte ordering block is available only in reverse serial loopback
configuration in Basic mode. The rate matcher is coupled with the 8B/10B
code groups, which requires the use of the 8B/10B encoder or decoder
either in the PCS or PLD logic array.
Basic Single-Width Mode with x4 Clocking
In Basic single-width mode, the ALT2GXB MegaWizard Plug-In Manager
provides a ×4 option under the Which subprotocol will you be using?
option. If you select this option, all four transmitter channels within the
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
transceiver block are clocked by clocks generated from the central clock
divider block. The low-speed clock from the central clock divider block
clocks the bonded transmitter PCS logic in all four channels. This reduces
the transmitter channel-to-channel skew within the transceiver block.
Each receiver channel within the transceiver block is clocked individually
by the recovered clock from its own CRU.
1
Configuring transceivers in this mode yields low transmitter
channel-to-channel skew within a transceiver block. It does not
provide skew reduction for channels placed across transceiver
blocks.
Figure 2–29 shows the data path in this mode.
Figure 2–29. Basic Single-Width Mode with ×4 Clocking
Transmitter Digital Logic
TX Phase
Compensation
FIFO
Byte
Serializer
Analog Receiver and
Transmitter Logic
8B/10B
Encoder
Serializer
FPGA
Logic
Array
RX Phase
Compensation
FIFO
Byte
Ordering
Byte
Deserializer
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
Deserializer
Clock
Recovery
Unit
Receiver Digital Logic
The transmitter data path consists of a 16-bit PLD-transceiver interface,
transmitter phase compensation FIFO, 16:8-bit byte serializer, and 8:1
serializer.
The receiver data path consists of the CRU, 1:8 deserializer, bit-slip word
aligner, 8:16 byte deserializer, receiver phase compensation FIFO, and 16bit Transceiver-PLD interface.
Transceiver Placement Limitations
If one or more channels in a transceiver block are configured to Basic
single-width mode with ×4 clocking option enabled, the remaining
channels in that transceiver block must either have the same
configuration or must be unused. All used channels within a transceiver
block configured to this mode must also run at the same data rate. All
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May 2008
Basic Single-Width Mode
channels within the transceiver block configured to this mode must be
instantiated using the same ALT2GXB MegaWizard Plug-In Manager
instance.
Figures 2–30 and 2–31 show examples of legal and illegal transceiver
placements with respect to the Basic single-width mode with ×4 clocking
enabled.
Figure 2–30. Examples of Legal Transceiver Placement
Ch0
Basic Single-Width mode with x4
clocking option enabled
Ch0
Ch1
Basic Single-Width mode with x4
clocking option enabled
Ch1
Basic Single-Width mode with x4
clocking option disabled
Ch2
Unused Channel
Ch2
Serial RapidIO
Ch3
Unused Channel
Ch3
Basic Single-Width mode with x4
clocking option disabled
Serial RapidIO
Figure 2–31. Examples of Illegal Transceiver Placement
Ch0
Basic Single-Width mode with x4
clocking option enabled
Ch0
Basic Single-Width mode with x4
clocking option enabled
Ch1
Basic Single-Width mode with x4
clocking option enabled
Ch1
Basic Single-Width mode with x4
clocking option enabled
Ch2
Serial RapidIO
Ch2
Basic Single-Width mode with x4
clocking option disabled
Ch3
Serial RapidIO
Ch3
Basic Single-Width mode with x4
clocking option disabled
Clocking and Reset Recommendations
To minimize the transmitter channel to channel skew across transceiver
blocks, Altera recommends that you follow the protocols listed below:
■
■
Altera Corporation
May 2008
Using the dedicated REFCLK pins of the centrally located transceiver
block in your design to provide the input reference clock for all
transceiver blocks. This reduces the skew on the input reference
clock driving the CMU PLL in each transceiver block. For example,
in a design with 12 channels placed across Banks 13, 14, and 15, use
the REFCLK pins of Bank 14 to provide the input reference clock.
De-asserting the tx_digitalreset signal of all used transceiver
blocks simultaneously after pll_locked signal from all active
transceiver blocks goes high.
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Arria GX Transceiver Protocol Support and Additional Features
Figure 2–32 shows the recommended clocking for 12 transceiver channels
across transceiver banks 13, 14, and 15 in the EP1AGX90EF1152 device.
Figure 2–32. Clocking Recommendations to Minimize Transmitter
Channel-To-Channel Skew
Bank13
Four Channels in
Basic x4 clocking
mode
Inter-transceiver
block (IQ) clock
pll_inclk
Bank14
Four Channels in
Basic x4 clocking
mode
pll_inclk
REFCLK_B14
Bank15
Four Channels in
Basic x4 clocking
mode
Inter-transceiver
block (IQ) clock
XAUI Mode
pll_inclk
This section briefly introduces the XAUI standard and the code groups
and ordered sets associated with this self-managed interface. For full
details about the XAUI standard, refer to clause 47 and 48 in the 10
Gigabit Ethernet standard (IEEE 802.3ae).
Arria GX devices contain embedded macros dedicated to the XAUI
protocol, including synchronization, channel deskew, rate matching,
XGMII Extender Sublayer (XGXS) to 10 Gigabit Media Independent
Interface (XGMII) and XGMII to XGXS code-group conversion macros.
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May 2008
XAUI Mode
The XAUI standard is an optional self-managed interface that is inserted
between the reconciliation sublayer and the PHY layer to transparently
extend the physical reach of XGMII.
This section is organized into transmitter and receiver data path modules
when configured for XAUI mode. The description for each module only
covers details specific to XAUI functional mode support.
f
For a general description of each module, refer to the Arria GX
Transceiver Architecture chapter in volume 2 of the Arria GX Device
Handbook.
XAUI addresses several physical limitations of XGMII. XGMII signaling
is based on the HSTL Class I single-ended I/O standard, which has an
electrical distance limitation of approximately 7 cm. XAUI uses a
low-voltage differential signaling method, so the electrical limitation is
increased to approximately 50 cm. Another advantage of XAUI is the
simplification of backplane and board trace routing. XGMII is composed
of 32 transmit channels, 32 receive channels, one transmit clock, one
receive clock, four transmitter control characters, and four receive control
characters for a total of a 74-pin wide interface. XAUI consists of four
differential transmitter channels and four differential receiver channels
for a total of a 16-pin wide interface. This reduction in pin count
significantly simplifies the routing process in the layout design.
Figure 2–33 shows the relationships between the XGMII and XAUI layers.
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
Figure 2–33. XGMII and XAUI Relationship
LAN
CSMA/CD Layers
Higher Layers
LLC
OSI
Reference
Model Layers
MAC (Optional)
MAC
Application
Reconciliation
Presentation
XGMII
XGXS
Session
XAUI
Transport
XGXS
Optional XGMII
Extender
XGMII
Network
PCS
Data Link
PMA
PHY
PMD
Physical
MDI
Medium
10 Gb/s
Media Access Control (MAC)
Medium Dependent Interface (MDI)
Physical Coding Sublayer (PCS)
Physical Layer Device (PHY)
Logical Link Control (LLC)
Physical Medium Attachment (PMA)
Physical Medium Dependent (PMD)
10 Gigabit Attachment Unit Interface (XAUI)
10 Gigabit Media Independent Interface (XGMII)
XGMII Extender Sublayer (XGXS)
The XGMII interface consists of four lanes of eight bits. At the transmit
side of the XAUI interface, the data and control characters are converted
within the XGXS into an 8B/10B encoded data stream. Each data stream
is then transmitted across a single differential pair running at 3.125 Gbps.
At the XAUI receiver, the incoming data is decoded and mapped back to
the 32-bit XGMII format. This provides a transparent extension of the
physical reach of the XGMII and also reduces the interface pin count.
XAUI functions as a self-managed interface because code group
synchronization, channel deskew, and clock domain decoupling is
handled with no upper layer support requirements. This functionality is
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May 2008
XAUI Mode
based on the PCS code groups that are used during the IPG time and idle
periods. PCS code groups are mapped by the XGXS to XGMII characters
specified in Table 2–24.
Table 2–24. XGMII Character to PCS Code-Group Mapping
XGMII TXC
XGMII TXD (1)
PCS Code Group
0
00 through FF
Dxx.y
1
07
K28.0, K28.3, or
K28.5
Description
Normal data
transmission
Idle in ||I||
1
07
K28.5
Idle in ||T||
1
9C
K28.4
Sequence
1
FB
K27.7
Start
1
FD
K29.7
Terminate
1
FE
K30.7
Error
1
Other value
—
1
Any other value
K30.7
Reserved XGMII
character
Deleted XGMII
character
Note to Table 2–24:
(1)
Values in TXD column are in hexadecimal.
Figure 2–34 shows an example of the mapping between XGMII characters
and the PCS code groups that are used in XAUI. The idle characters are
mapped to a pseudo random sequence of /A/, /R/, and /K/ code
groups.
Figure 2–34. XGMII Character to PCS Code-Group Mapping
XGMII
T/RxD<7:0>
|
|
S
Dp
D
D
D
---
D
D
D
D
|
|
|
|
|
|
T/RxD<15:8>
|
|
Dp
Dp
D
D
D
---
D
D
D
T
|
|
|
|
|
|
T/RxD<23:16>
|
|
Dp
Dp
D
D
D
---
D
D
D
|
|
|
|
|
|
|
T/RxD<31:24>
|
|
Dp
Dp
D
D
D
---
D
D
D
|
|
|
|
|
|
|
PCS
Lane 0
K
R
S
Dp
D
D
D
---
D
D
D
D
A
R
R
K
K
R
Lane 1
K
R
Dp
Dp
D
D
D
---
D
D
D
T
A
R
R
K
K
R
Lane 2
K
R
Dp
Dp
D
D
D
---
D
D
D
K
A
R
R
K
K
R
Lane 3
K
R
Dp
Dp
D
D
D
---
D
D
D
K
A
R
R
K
K
R
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May 2008
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Arria GX Transceiver Protocol Support and Additional Features
The PCS code-groups are sent via PCS ordered sets. PCS ordered sets
consist of combinations of special and data code groups defined as a
column of code groups. These ordered sets are composed of four code
groups beginning in Lane 0. Table 2–25 lists the defined idle ordered sets
(||I||) that are used for the self managed properties of XAUI.
Table 2–25. Defined Idle Ordered Set
Code
Ordered Set
||I||
Idle
||K||
Synchronization
column
Number of
Code Groups
4
Encoding
Substitute for XGMII Idle
/K28.5/K28.5/K28.5/K28.5
||R||
Skip column
4
/K28.0/K28.0/K28.0/K28.0
||A||
Align column
4
/K28.3/K28.3/K28.3/K28.3
XAUI Mode Transmitter Architecture
This section lists sub-blocks within the transmitter channel configured in
XAUI mode (Figure 2–35). The sub-blocks are described in order from the
PLD-Transceiver parallel interface to the serial transmitter buffer.
Figure 2–35. XAUI Transmitter Architecture
Transmitter PCS
TX Phase
Compensation
FIFO
PLD
Logic
Array
Byte
Serializer
8B/10B
Encoder
Transmitter PMA
Serializer
CMU
Reference
Clock
Clock Multiplier Unit (CMU)
The clock multiplier unit takes in a reference clock and synthesizes the
clocks that are used to clock the transmitter digital logic (PCS), the
serializer, and the PLD-transceiver interface.
f
For more details about CMU architecture, refer to the Clock Multiplier
Unit section in the Arria GX Transceiver Architecture chapter in volume 2
of the Arria GX Device Handbook.
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May 2008
XAUI Mode
In XAUI mode, the CMU block consists of the following components:
■
■
Transmitter PLL that generates high-speed serial clock for the
serializer
Local clock divider block that generates low-speed parallel clock for
transmitter digital logic and PLD-transceiver interface
Input Reference Clock
In XAUI mode for Arria GX devices, the only supported input reference
clock frequency is 156.25 MHz.
The reference clock input to the transmitter PLL can be derived from the
following components:
■
■
One of the two available dedicated reference clock input pins
(REFCLK0 or REFCLK1) of the associated transceiver block
Inter-transceiver block lines driven by reference clock input pins of
other transceiver blocks
Altera recommends using the dedicated reference clock input pins
(REFCLK0 or REFCLK1) to provide reference clock for the transmitter
PLL.
Dedicated Reference Clock Pin Specifications
Table 2–26 shows the I/O standards allowed for the reference clock pins.
Table 2–26. Xaui Mode Reference Clock Specifications
Frequency
156.25 MHz
I/O Standard
Coupling
Termination
1.2-V PCML,
1.5-V PCML,
3.3-V PCML,
Differential LVPECL,
LVDS
AC
On-chip
In ×4 mode for XAUI, the central clock divider in the transceiver block
divides the 1562.5 MHz clock from the transmitter PLL by 5 to generate a
312.5 MHz parallel clock. This low-speed parallel clock output from the
central clock divider block is used to clock the transmitter digital logic
(PCS) in all channels of the transceiver block. The central clock divider
block also forwards the high-speed serial clock from the transmitter PLL
to the serializer within each channel. Because all four channels in the
transceiver block are clocked with the same clock, the channel-to-channel
skew is minimized.
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May 2008
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
1
The Quartus II software automatically selects the appropriate
transmitter PLL bandwidth suited for the XAUI data rate.
Figure 2–36 shows the CMU implemented in XAUI mode.
Figure 2–36. XAUI Mode CMU
CMU Block
Transmitter Channels [3:2]
Local Clock
TX Clock
Divider
Block
(/5)Block
Gen
1562.5 MHz
Reference
Clock
Transmitter
PLL
(x10)
156.25 MHz
1562.5 MHz
1562.5 MHz
Transmitter High-Speed
Serial (1562.5 MHz) and
Low-Speed Parallel (312.5 MHz)
Clock
Central Clock
Divider Block
(/5)
Local Clock
TX Clock
Divider
Block
(/5)Block
Gen
Transmitter Channels [1:0]
Transmitter High-Speed
Serial (1562.5 MHz) and
Low-Speed Parallel (312.5 MHz)
Clocks
Clock Synthesis
In XAUI mode, the 156.25-input reference clock is fed to the transmitter
PLL. Since the transmitter PLL implements a half-rate VCO, it multiplies
the 156.25-MHz input clock by 10 to generate a 1562.5-MHz (3.125-Gbps)
high speed serial clock. This high-speed serial clock feeds the central
clock divider and four local clock dividers of the transceiver block.
Transmitter Phase Compensation FIFO Buffer
The transmitter phase compensation FIFO buffer compensates for the
phase difference between the PLD clock that clocks in parallel data into
the transmitter and the PCS clock that clocks the rest of the transmitter
digital logic.
f
For more details about the transmitter phase compensation FIFO buffer
architecture, refer to the Transmitter Phase Compensation FIFO section
in the Arria GX Transceiver Architecture chapter in volume 2 of the
Arria GX Device Handbook.
In XAUI 3.125 Gbps mode, the 312.5 MHz clock generated by the CMU
clock divider block is divided by two. The resulting 156.25 MHz clock is
used to clock the read port of the FIFO buffer. This divide-by-two clock is
also forwarded to the PLD logic array (on the tx_clkout port of its
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May 2008
XAUI Mode
associated channel). If the tx_coreclk port is not instantiated, the clock
signal on the tx_clkout port is automatically routed back to clock the
write side of the transmitter phase compensation FIFO buffer. The 16-bit
PLD-transceiver interface clocked at 156.25 MHz results in an effective
XAUI data rate of 3.125 Gbps.
In XAUI mode, the transmitter phase compensation FIFO is four words
deep. The latency through the FIFO is two to three PLD transceiver
interface clock cycles.
Figure 2–37 shows the block diagram of transmitter phase compensation
FIFO in XAUI mode.
Figure 2–37. Transmitter Phase Compensation FIFO in XAUI Mode
Transmitter Channel
tx_datain[7:0]
Transmitter
Phase
Compensation
FIFO
From
PLD
wrclk
tx_coreclk
156.25 MHz
dataout [7:0]
To 8B/10B
Encoder
rdclk
156.25 MHz
312.5 MHz
/2
CMU
Local Clock Divider
Block
tx_clkout
Byte Serializer
In XAUI 3.125 Gbps mode the PLD-transceiver interface data is 16 bits
wide and is clocked into the transmitter phase compensation FIFO at
156.25 MHz. The byte serializer clocks in the 16-bit wide data from the
transmitter phase compensation FIFO at 156.25 MHz and clocks out 8-bit
data to the 8B/10B encoder at 312.5 MHz. This allows clocking the
PLD-transceiver interface at half the speed.
f
Altera Corporation
May 2008
For more details about the byte serializer architecture, refer to the Byte
Serializer section in the Arria GX Transceiver Architecture chapter in
volume 2 of the Arria GX Device Handbook.
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Arria GX Transceiver Protocol Support and Additional Features
The write port of the byte serializer is clocked by the divide-by-two
version of the low-speed parallel clock from CMU. The read port is
clocked by the low-speed parallel clock from CMU. The byte serializer
clocks out the least significant byte of the 16-bit data first and the most
significant byte last.
Figure 2–38 shows the block diagram of the byte serializer in XAUI mode.
Figure 2–38. Byte Serializer in XAUI Mode
dataout
datain
Byte Serializer
From Transmitter
Phase Compensation
FIFO
To 8B/10B
Encoder
wrclk
rdclk
156.25 MHz
312.5 MHz
156.25 MHz
/2
Divide-by-Two
Version of
Low-Speed
Parallel Clock
312.5 MHz
Low-Speed
Parallel Clock
CMU
Local/Central Clock
Divider Block
8B/10B Encoder
In XAUI mode, the 8B/10B encoder clocks in 8-bit data and 1-bit control
identifier from the transmitter phase compensation FIFO and generates a
10-bit encoded data. The 10-bit encoded data is fed to the serializer.
f
For more details about the 8B/10B encoder functionality, refer to the
8B/10B Encoder section in the Arria GX Transceiver Architecture chapter
in volume 2 of the Arria GX Device Handbook.
XGMII Character to PCS Code-Group Mapping
In XAUI mode, the 8B/10B encoder in Arria GX devices is controlled by
a global transmitter state machine that maps various 8-bit XGMII codes
to 10-bit PCS code groups. This state machine complies with the IEEE
802.3ae PCS transmit specification. Figure 2–39 shows the PCS transmit
source state diagram specified in clause 48 of the IEEE P802.3ae.
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Altera Corporation
May 2008
XAUI Mode
Figure 2–39. IEEE 802.3ae PCS Transmit Source State Diagram
!reset
!(TX=||IDLE|| + TX=||Q||
SEND_Q
IF TX=||T|| THEN cvtx_terminate
tx_code_group<39:0> ⇐
ENCODE(TX)
PUDR
(next_ifg + A_CNT≠0)
next_ifg = A_CNT≠0
reset
SEND_A
SEND_K
tx_code_group<39:0> ⇐ ||A||
next_ifg ⇐ K
PUDR
Q_det
tx_code_group<39:0> ⇐ ||K||
next_ifg ⇐ A
PUDR
!Q_det
UCT
B
SEND_Q
tx_code_group<39:0> ⇐ TQMSG
Q_det ⇐ K
PUDR
A
A_CNT≠0 *
cod_sel=1
B
UCT
SEND_RANDOM_K
tx_code_group<39:0> ⇐ ||K||
PUDR
SEND_RANDOM_R
tx_code_group<39:0> ⇐ ||R||
A_CNT≠0 *
cod_sel=1
B
A_CNT≠0 *
cod_sel=1 A
A_CNT=0
A_CNT=0
A
SEND_RANDOM_A
A_CNT≠0 *
cod_sel=1
tx_code_group<39:0> ⇐ ||A||
PUDR
Q_det
B
!Q_det *
cod_sel=1
SEND_RANDOM_Q
tx_code_group<39:0> ⇐ TQMSG
Q_det ⇐ FALSE
PUDR
B
A
Altera Corporation
May 2008
A
!Q_det *
cod_set=1
cod_set=1
cod_set=1
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Arria GX Transceiver Protocol Support and Additional Features
Table 2–27 lists the XGMII character to PCS code-group mapping.
Table 2–27. XGMII Character to PCS Code-Group Mapping
XGMII TXC
XGMII TXD (1)
PCS Code Group
0
00 through FF
Dxx.y
1
07
K28.0, K28.3, or
K28.5
Description
Normal data
transmission
Idle in ||I||
1
07
K28.5
Idle in ||T||
1
9C
K28.4
Sequence
1
FB
K27.7
Start
1
FD
K29.7
Terminate
1
FE
K30.7
Error
1
Other value
1
Any other value
Reserved XGMII
character
K30.7
Invalid XGMII
character
Note to Table 2–27:
(1)
Values in TXD column are in hexadecimal.
Serializer
In XAUI 3.125 Gbps mode, the 10-bit encoded data from the 8B/10B
encoder is clocked into the 10:1 serializer with the low speed parallel
clock at 312.5 MHz. The 10-bit data is clocked out of the serializer LSB to
MSB at the high-speed effective serial clock rate at 3125 MHz. The serial
data output of the serializer is fed into the transmitter output buffer.
f
For more details about the serializer architecture, refer to the serializer
section in the Arria GX Transceiver Architecture chapter in volume 2 of the
Arria GX Device Handbook.
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May 2008
XAUI Mode
Transmitter Buffer
Table 2–28 shows the transmitter buffer settings when configured in
XAUI mode.
Table 2–28. Transmitter Buffer Settings in XAUI Mode
Settings
Value
I/O Standard
1.5-V PCML (1)
Programmable Differential Output
Voltage (VOD)
400 - 1200 mV
600 mV, 700 mV (1)
Common Mode Voltage (VCM)
100 Ω (2)
Differential Termination
Enabled (3)
Programmable pre-emphasis
VCCH (Transmitter Buffer Power)
1.5 V
Notes to Table 2–28:
(1)
(2)
(3)
The common mode voltage (VCM) settings are selectable in the MegaWizard
Plug-In Manager.
The I/O standard and differential termination settings are defaulted to 1.5-V
PCML and 100 Ω, respectively. If you select any other setting for the I/O standard
or differential termination in the Assignment Editor, the Quartus II compiler
issues an error message.
The transmitter buffer has five programmable first post-tap pre-emphasis
settings.
XAUI Mode Receiver Architecture
This section lists sub-blocks within the receiver channel configured in
XAUI mode (Figure 2–40). The sub-blocks are described in order from the
serial receiver input buffer to the receiver phase compensation FIFO
buffer at the transceiver-PLD interface.
Figure 2–40. XAUI Mode Receiver Architecture
FPGA
Logic
Array
RX Phase
Compensation
FIFO
Altera Corporation
May 2008
Byte
Ordering
Byte DeSerializer
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
Deserializer
Clock
Recovery
Unit
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Arria GX Transceiver Protocol Support and Additional Features
Receiver Buffer
Table 2–29 shows the receiver buffer settings when configured in XAUI
mode.
Table 2–29. Receiver Buffer Settings in XAUI Mode
Settings
Value
I/O Standard
1.2-V PCML,
1.5-V PCML,
3.3-V PCML,
Differential LVPECL,
LVDS
Input Common Mode Voltage (Rx VCM)
850 mV, 1200 mV (1)
Differential Termination
Programmable equalization
Coupling
100 Ω (2)
Enabled (3)
AC
Notes to Table 2–29:
(1)
(2)
(3)
The common mode voltage (Rx VCM) is selectable in the MegaWizard Plug-In
Manager.
The differential termination setting is defaulted to 100 Ω. If you select any other
setting for differential termination in the Assignment Editor, the Quartus II
compiler issues an error message.
The receiver buffer has five programmable equalization settings.
Receiver PLL and Clock Recovery Unit
In XAUI 3.125 Gpbs mode, the receiver PLL in each transceiver channel is
fed by an input reference clock. The receiver PLL in conjunction with the
clock recovery unit generates two clocks: a half-rate high-speed serial
recovered clock at 1562.5 MHz that feeds the deserializer and a low-speed
parallel recovered clock at 312.5 MHz that feeds the receiver's digital
logic.
You can set the clock recovery unit in either automatic lock mode or
manual lock mode. In automatic lock mode, the PPM detector and the
phase detector within the receiver channel automatically switch the
receiver PLL between lock-to-reference and lock-to-data modes. In
manual lock mode, you can control the receiver PLL switch between lock
to-reference and lock-to-data modes via the rx_locktorefclk and
rx_locktodata signals.
f
For more details about the CRU lock modes, refer to the Receiver PLL
section in the Arria GX Transceiver Architecture chapter in volume 2 of the
Arria GX Device Handbook.
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May 2008
XAUI Mode
The reference clock input to the receiver PLL can be derived from one of
the following pins:
■
■
■
One of the two available dedicated reference clock input pins
(REFCLK0 or REFCLK1) of the associated transceiver block
PLD global clock network (must be driven directly from an input
clock pin and cannot be driven by user logic or enhanced PLL)
Inter-transceiver block lines driven by reference clock input pins of
other transceiver blocks
Deserializer
In XAUI 3.125 Gbps mode, the 1:10 deserializer clocks in serial data from
the receiver buffer using the high-speed serial recovered clock. The 10-bit
deserialized data is clocked out to the word aligner using the low-speed
parallel recovered clock at 312.5 MHz. The deserializer assumes that the
transmission bit order is LSB to MSB; that is, the LSB of a data word is
received earlier in time than its MSB.
f
For more details about the deserializer architecture, refer to the
Deserializer section in the Arria GX Transceiver Architecture chapter in
volume 2 of the Arria GX Device Handbook.
Word Aligner
The word aligner clocks in 10-bit data from the deserializer and restores
the word boundary of the upstream transmitter.
f
For more details about the word aligner architecture, refer to the Word
Aligner section in the Arria GX Transceiver Architecture chapter in
volume 2 of the Arria GX Device Handbook.
In XAUI mode, the word aligner comprises of the following three
modules:
■
■
■
Pattern detector module
Pattern aligner module
Run-length violation detection module
Pattern Detector
In XAUI mode, the Quartus II software automatically configures 10-bit
K28.5 (10'b0101111100) as the word alignment pattern. After coming out
of reset (rx_digitalreset), when the pattern detector detects either
disparities of the K28.5 control word, it asserts the rx_patterndetect
signal for one parallel clock cycle. When the pattern aligner has aligned
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May 2008
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Arria GX Transceiver Protocol Support and Additional Features
the incoming data to the desired word boundary, the pattern detector
asserts rx_patterndetect signal only if the word alignment pattern is
found in the current word boundary.
Pattern Aligner
In XAUI mode, the pattern aligner employs an automatic synchronization
state machine. The Quartus II software automatically configures the
synchronization state machine to indicate synchronization when the
receiver receives 4 K28.5 (10'b0101111100 or 10'b1010000011)
synchronization code groups without receiving an intermediate invalid
code group. Once synchronized, the state machine indicates loss of
synchronization when it detects 4 invalid code groups separated by less
than 4 valid code groups or when it is reset.
Receiver synchronization is indicated on the rx_syncstatus port of
each channel. A high on the rx_syncstatus port indicates that the lane
is synchronized and a low indicates that it has fallen out of
synchronization.
Table 2–30 lists the synchronization state machine parameters when
configured in XAUI mode.
Table 2–30. Synchronization State Machine Parameters in XAUI Mode
Number of valid K28.5 code groups received to achieve synchronization
4
Number of errors received to lose synchronization
4
Number of continuous good code groups received to reduce the error count 4
by 1
Synchronization State Machine in XAUI Mode
When XAUI mode is used, the synchronization and word alignment is
handled automatically by a built-in state machine that adheres to either
the IEEE 802.3ae or IEEE 802.3 synchronization specifications,
respectively. If you specify either standard, the alignment pattern is
automatically defaulted to /K28.5/ (b'0011111010).
XAUI uses an embedded clocking scheme that re-times the data that
potentially can alter the code-group boundary. The boundaries of the
code groups are re-aligned through a synchronization process specified
in clause 48 of the IEEE P802.3ae standard, which states that
synchronization is achieved upon the reception of four /K28.5/ commas.
When you specify the XAUI protocol, code-group synchronization is
achieved upon the reception of four /K28.5/ commas. Each comma can
be followed by any number of valid code groups. Invalid code groups are
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May 2008
XAUI Mode
not allowed during the synchronization stage. When code-group
synchronization is achieved the optional rx_syncstatus signal is
asserted.
Refer to clause 47-48 of the IEEE P802.3ae standard or “XAUI Mode” on
page 2–60 for more information about the operation of the
synchronization phase.
When you configure Arria GX devices to the XAUI protocol, the built in
pattern detector, word aligner, and XAUI state machines adhere to the
PCS synchronization specification. After all the conditions for
synchronization have been met, the rx_syncstatus signal is asserted
and only de-asserts if synchronization is lost.
Figure 2–41 shows the PCS synchronization state diagram specified in
clause 48 of the IEEE P802.3ae.
Figure 2–41. IEEE 802.3ae PCS Synchronization State Diagram
reset +
(signal_detectCHANGE<n> *PUDI)
LOSS_OF_SYNC
PUDI * signal_detect<n>=FAIL)+
PUDI(![/COMMA/])
lane_sync_status<n> ⇐ FAIL
enable_cgalign ⇐TRUE
SUDI
(signal_detect<n>=OK)*
PUDI([/COMMA/]
COMMA_DETECT_1
PUDI([/COMMA/]
*∉[/INVALID/]
enable_cgalign ⇐ FALSE
SUDI
PUDI([/INVALID/])
PUDI([/COMMA/]
COMMA_DETECT_2
PUDI([/COMMA/]
*∉[/INVALID/]
SUDI
PUDI([/INVALID/])
PUDI([/COMMA/]
COMMA_DETECT_3
PUDI([/COMMA/]
*∉[/INVALID/]
SUDI
PUDI([/INVALID/])
PUDI([/COMMA/]
PUDI(∉[/INVALID/])
SYNC_ACQUIRED_1
lane_sync_status<n> ⇐ OK
SUDI
PUDI([/INVALID/])
1
PUDI(∉[/INVALID/])
SYNC_ACQUIRED_2
SYNC_ACQUIRED_2A
good_cgs ⇐ 0
SUDI
good_cgs ⇐ good_cgs + 1
SUDI
PUDI([/INVALID/])
PUDI(∉[/INVALID/])*good_cgs = 3
PUDI([/INVALID/])
2
PUDI(∉[/INVALID/])*
good_cgs ≠ 3
PUDI(∉[/INVALID/])
SYNC_ACQUIRED_3
SYNC_ACQUIRED_3A
good_cgs ⇐ 0
SUDI
good_cgs ⇐ good_cgs + 1
SUDI
PUDI([/INVALID/])
PUDI([/INVALID/])
1
PUDI(∉[/INVALID/])*
good_cgs ≠ 3
PUDI(∉[/INVALID/])*good_cgs = 3
PUDI(∉[/INVALID/])
SYNC_ACQUIRED_4
SYNC_ACQUIRED_4A
good_cgs ⇐ 0
SUDI
PUDI([/INVALID/])
good_cgs ⇐ good_cgs + 1
SUDI
PUDI([/INVALID/])
2
Altera Corporation
May 2008
PUDI(∉[/INVALID/])*
good_cgs ≠ 3
PUDI(∉[/INVALID/])*good_cgs = 3
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Arria GX Transceiver Protocol Support and Additional Features
The word aligner block asserts an error flag on the rx_disperr and
rx_errdetect ports if the received 10-bit code is detected with
incorrect running disparity. The error flag signal (rx_disperr) has the
same delay from the word aligner to the PLD-transceiver interface as the
received data.
Channel Aligner (Deskew)
It is possible for ordered sets to be misaligned with respect to one another
because of board skew or differences between the independent clock
recoveries per serial lane. Channel alignment, also referred to as deskew
or channel bonding, realigns the ordered sets by using the alignment code
group, referred to as /A/. The /A/ code group is transmitted
simultaneously on all four lanes, constituting an ||A|| ordered set,
during idles or IPG. XAUI receivers use these code groups to resolve any
lane to lane skew. Skew between the lanes can be up to 40 UI (12.8 ns) as
specified in the standard, which relaxes the board design constraints.
Figure 2–42 shows lane skew at the receiver input and how the deskew
circuitry uses the /A/ code group to deskew the channels.
Figure 2–42. Lane Deskew with the /A/ Code Group
Lane 0
K
Lane 2
K
R
A
K
R
R
K
K
R
K
R
Lane 1
K
K
R
A
K
R
R
K
K
R
K
K
R
A
K
R
R
K
K
R
K
R
K
K
R
A
K
R
R
K
K
R
K
K
Lane 3
R
Lanes Skew at
Receiver Input
R
Lane 0
K
K
R
A
K
R
R
K
K
R
K
R
Lane 1
K
K
R
A
K
R
R
K
K
R
K
R
Lane 2
K
K
R
A
K
R
R
K
K
R
K
R
Lane 3
K
K
R
A
K
R
R
K
K
R
K
R
Lanes are
Deskewed by
Lining up
the "Align"/A/,
Code Groups
Arria GX devices manage XAUI channel alignment with a dedicated
deskew macro that consists of a 16-word-deep FIFO buffer controlled by
a XAUI deskew state machine. The XAUI deskew state machine first
looks for the /A/ code group within each channel. When the XAUI
deskew state machine detects /A/ in each channel, the deskew FIFO
buffer is enabled. The deskew state machine now monitors the reception
of /A/ code groups. When four aligned /A/ code groups have been
received the rx_channelaligned is asserted. The deskew state
machine continues to monitor the reception of /A/ code groups and
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XAUI Mode
de-asserts the rx_channelaligned signal if alignment conditions are
lost. This built-in deskew macro is only enabled for the XAUI protocol.
Figure 2–43 shows the PCS deskew state diagram specified in clause 48 of
the IEEE P802.3ae.
Figure 2–43. IEEE 802.3ae PCS Deskew State Diagram
reset +
(sync_status=FAIL * SUDI)
LOSS_OF_ALIGNMENT
align_status ⇐ FAIL
enable_deskew ⇐TRUE
SUDI(![/||A||/])
AUDI
sync_status OK * SUDI(![/||A||/])
!deskew_error
* SUDI(![/||A||/])
ALIGN_DETECT_1
enable_deskew ⇐ FALSE
AUDI
deskew_error * SUDI
SUDI(![/||A||/])
ALIGN_DETECT_2
!deskew_error
* SUDI(![/||A||/])
AUDI
deskew_error * SUDI
SUDI(![/||A||/])
!deskew_error
* SUDI(![/||A||/])
ALIGN_DETECT_3
AUDI
deskew_error * SUDI
1
SUDI(![/||A||/])
!deskew_error
* SUDI(![/||A||/])
ALIGN_ACQUIRED_1
enable_deskew ⇐ FALSE
AUDI
deskew_error * SUDI
2
SUDI(![/||A||/])
ALIGN_ACQUIRED_2
!deskew_error
* SUDI(![/||A||/])
AUDI
deskew_error * SUDI
3
SUDI(![/||A||/])
1
!deskew_error
* SUDI(![/||A||/])
ALIGN_ACQUIRED_3
AUDI
deskew_error * SUDI
SUDI(![/||A||/])
2
!deskew_error
* SUDI(![/||A||/])
ALIGN_ACQUIRED_4
AUDI
deskew_error * SUDI
SUDI(![/||A||/])
3
Rate Matcher
XAUI can operate in multi-crystal environments, which can tolerate
frequency variations of 100 PPM between crystals. Arria GX devices
contain embedded circuitry to perform clock rate compensation, which is
achieved by inserting or removing the PCS SKIP code group (/R/) from
the IPG or idle stream. This process is called rate matching and is
sometimes referred to as clock rate compensation.
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May 2008
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Arria GX Transceiver Protocol Support and Additional Features
The rate matcher in Arria GX devices consists of a 12-word-deep FIFO
buffer, with control logic that you can configure to support XAUI, GIGE,
or custom modes. In XAUI mode the controller begins to write data into
the FIFO buffer whenever the rx_channelaligned signal is asserted.
Within the control logic there is a FIFO counter that keeps track of the
read and write executions. When the FIFO counter reaches a value of
greater than nine, the receivers delete the /R/ code-group
simultaneously across all channels during IPG or idle conditions. If the
FIFO counter is fewer than five, the receivers insert the /R/ code-group
simultaneously across all channels during IPG or idle conditions.
The rate matcher in XAUI mode operates in a synchronized four mode
and supports up to a 100 PPM clock difference between the upstream
transmitter and receiver. In this mode, the rate matcher can insert or
delete a column of /R/ characters as denoted by the ||R|| designation,
depending on whether the FIFO buffer is approaching an empty or full
condition. The rate matcher does not operate until the XAUI
synchronization state machine achieves word alignment and channel
alignment. Until that point, the rate matcher is not active (read and write
pointers do not move).
If the ||R|| code words are not received on all channels, rate matching
does not occur and may lead to over/underflow conditions in the
rate-matching FIFO buffer. If this situation occurs, the data output of the
receiver outputs a constant 9'h19C (8'h9C on the rx_dataout output
and 1'b1 on the rx_ctrldetect output) in Lane 0 (rest of the lane are
data 8'h00). The receiver digital reset must be asserted and the lanes
resynchronized before data can be received.
1
This circuitry compensates for 100 PPM frequency variations.
8B/10B Decoder
In XAUI mode, the 8B/10B decoder clocks in 10-bit data from the word
aligner and decodes it into 8-bit data + 1-bit control identifier. The 8-bit
decoded data is fed to the byte deserializer.
f
For more details about the 8B/10B decoder functionality, refer to the
8B/10B Encoder section in the Arria GX Transceiver Architecture chapter
in volume 2 of the Arria GX Device Handbook.
If the received 10-bit code group is not a part of valid Dx.y or Kx.y code
groups, the 8B/10B decoder block asserts an error flag on the
rx_errdetect port. The error flag signal (rx_errdetect) has the
same data path delay from the 8B/10B decoder to the PLD-transceiver
interface as the invalid code group.
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May 2008
XAUI Mode
If the received 10-bit code group is detected with incorrect running
disparity, the 8B/10B decoder block asserts an error flag on the
rx_disperr and rx_errdetect ports. The error flag signal
(rx_disperr) has the same delay from the 8B/10B decoder to the
PLD-transceiver interface as the received data.
PCS Code Group to XGMII Character Mapping
In XAUI mode, the 8B/10B decoder in Arria GX devices is controlled by
a global receiver state machine that maps various PCS code groups into
specific 8-bit XGMII codes. Table 2–31 lists the PCS code group to XGMII
character mapping.
Table 2–31. PCS Code Group to XGMII Character Mapping
XGMII RXC
XGMII RXD
PCS Code Group
Description
0
00 through FF
Dxx.y
Normal data transmission
1
07
K28.0, K28.3, or K28.5
Idle in [[I]]
1
07
K28.5
Idle in [[T]]
1
9C
K28.4
Sequence
1
FB
K27.7
Start
1
FD
K29.7
Terminate
1
FE
K30.7
Error
1
FE
Invalid code group
Received code group
Note to Table 2–31:
(1)
Values in RXD column are in hexadecimal.
Byte Deserializer
In XAUI 3.125 Gbps mode, the PLD-receiver interface data is 16 bits wide
and is clocked out of the receiver phase compensation FIFO at
156.25 MHz. The byte deserializer clocks in the 8-bit wide data from the
8B/10B decoder at 312.5 MHz and clocks out 16-bit wide data to the
receiver phase compensation FIFO at 156.25 MHz. This allows clocking
the PLD-transceiver interface at half the speed.
f
For more details about byte deserializer architecture, refer to the Byte
Deserializer section in the Arria GX Transceiver Architecture chapter in
volume 2 of the Arria GX Device Handbook.
In XAUI mode, the write port of the byte deserializer is clocked by the
low-speed parallel recovered clock and the read port is clocked by
divide-by-two version of this clock.
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May 2008
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Arria GX Transceiver Protocol Support and Additional Features
Due to 8- to 16-bit byte deserialization, the byte ordering at the PLD
receiver interface might be incorrect. If required, you must implement the
byte ordering logic in the PLD core to correct for this situation.
Figure 2–44 shows the block diagram of the byte deserializer in XAUI
mode.
Figure 2–44. Byte Deserializer in XAUI Mode
dataout
datain
Byte
Deserializer
From 8B/10B
Decoder
wrclk
To Receiver Phase
Compensation
FIFO
rdclk
156.25 MHz
312.5 MHz
/2
Low-Speed Parallel CMU Clock
Receiver Phase Compensation FIFO Buffer
The receiver phase compensation FIFO buffer compensates for the phase
difference between the local receiver PLD clock and the receiver PCS
clock.
f
For more details about the receiver phase compensation FIFO buffer
architecture, refer to the Receiver Phase Compensation FIFO Buffer
section in the Arria GX Transceiver Architecture chapter in volume 2 of the
Arria GX Device Handbook.
In XAUI 3.125 Gbps mode, the 312.5 MHz low-speed parallel recovered
clock is divided by 2. The resulting 156.25 MHz clock is used to clock the
write port of the FIFO buffer. This divide-by-two clock is also forwarded
to the PLD logic array (on the rx_clkout port). If the rx_coreclk port
is not instantiated, the recovered clock signal on the rx_clkout port is
automatically routed back to clock the read side of the receiver phase
compensation FIFO buffer. The 16-bit PLD-receiver interface clocked at
156.25 MHz results in an effective XAUI data rate of 3.125 Gbps.
In XAUI mode, the receiver phase compensation FIFO is four words deep.
The latency through the FIFO is one to two PLD-transceiver interface
clock cycles.
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May 2008
Serial Digital Interface (SDI) Mode
Figure 2–45 shows the block diagram of receiver phase compensation
FIFO in XAUI mode.
Figure 2–45. Receiver Phase Compensation FIFO in XAUI Mode
Receiver Channel
datain[15:0]
From Byte
Deserializer
Receiver Phase
Compensation
FIFO
To PLD
wrclk
156.25 MHz
312.5 MHz
rx_dataout[15:0]
rdclk
156.25 MHz
/2
rx_coreclk
Low-Speed
Parallel CMU Clock
tx_clkout or
coreclkout
Serial Digital
Interface (SDI)
Mode
The Society of Motion Picture and Television Engineers (SMPTE) defines
various Serial Digital Interface (SDI) standards for transmission of
uncompressed video.
The following three SMPTE standards are popular in video broadcasting
applications:
■
■
■
SMPTE 259M standard— more popularly known as the standard
definition (SD) SDI, is defined to carry video data at 270 Mbps.
SMPTE 292M standard— more popularly known as the high
definition (HD) SDI, is defined to carry video data at either
1485 Mbps or 1483.5 Mbps.
SMPTE 424M standard— more popularly known as the third
generation (3G) SDI, is defined to carry video data at either
2970 Mbps or 2967 Mbps.
You can configure Arria GX transceivers in HD SDI or 3G SDI
configuration using the ALT2GXB MegaWizard Plug-In Manager.
Figure 2–46 shows the ALT2GXB transceiver data path in SDI mode.
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Figure 2–46. SDI Mode Data Path
Transmitter Digital Logic
TX Phase
Compensation
FIFO
Analog Receiver and
Transmitter Logic
Byte
Serializer
8B/10B
Encoder
Serializer
FPGA
Logic
Array
RX Phase
Compensation
FIFO
Byte
Deserializer
Byte
Ordering
8B/10B
Decoder
Rate
Match
FIFO
Deskew
FIFO
Word
Aligner
Deserializer
Clock
Recovery
Unit
Receiver Digital Logic
Table 2–32 shows ALT2GXB configurations supported by the Arria GX
transceivers in SDI mode.
Table 2–32. ALT2GXB Configuration in SDI Mode
Configuration
Data Rate (Mbps)
REFCLK
Frequencies
(MHz)
74.25, 148.5
Channel Width
HD
1485
10 bit, 20 bit
1483.5
74.175, 148.35
10 bit, 20 bit
3G
2970
148.5, 297
Only 20-bit
interface allowed
in 3G
2967
148.35, 296.7
Only 20-bit
interface allowed
in 3G
Transmitter Data Path
In the 10-bit channel width SDI configuration, the transmitter data path
consists of the transmitter phase compensation FIFO and the 10:1
serializer. In the 20-bit channel width SDI configuration, the transmitter
data path also includes the byte serializer.
1
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In SDI mode, the transmitter is purely a parallel-to-serial
converter. SDI transmitter functions, such as scrambling and
cyclic redundancy check (CRC) code generation, must be
implemented in the FPGA logic array.
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May 2008
Reset Control and Power-Down
Receiver Data Path
In the 10-bit channel width SDI configuration, the receiver data path is
comprised of the CRU, the 1:10 deserializer, the word aligner in bit-slip
mode, and the receiver phase compensation FIFO. In the 20-bit channel
width SDI configuration, the receiver data path also includes the byte
deserializer.
1
SDI receiver functions, such as descrambling, framing, and CRC
checker, must be implemented in the FPGA logic array.
Receiver Word Alignment/Framing
In SDI systems, because the word alignment and framing happens after
descrambling, the word aligner in the receiver data path is not useful.
Altera recommends driving the ALT2GXB rx_bitslip signal low to
avoid the word aligner from inserting bits in the received data stream.
1
f
Reset Control
and
Power-Down
Altera offers SDI MegaCore® function that can be configured at
SD-SDI, HD-SDI, and 3G-SDI data rates. The SDI MegaCore
function implements system level functions such as scrambling
and de-scrambling and CRC generation and checking. It also
offers the capability of configuring the three SDI data rates (SD,
HD, and 3G) dynamically on the same transceiver channel.
For more information about the SDI MegaCore function, refer to the SDI
MegaCore Function User Guide.
Arria GX transceivers provide multiple reset signals to reset the analog
and digital circuits in the transceiver channels. Besides individual
channel resets, Arria GX transceivers also provide power-down signals
that you can assert to power-down the entire transceiver block to reduce
power consumption (Figure 2–47).
Figure 2–47. Reset Signals
tx_digitalreset
rx_digitalreset
rx_analogreset
Reset Control
gxb_powerdown
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May 2008
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Arria GX Transceiver Protocol Support and Additional Features
User Reset and Power-Down Signals
Each transceiver block and each channel in the transceiver block of the
Arria GX device has individual reset signals to reset the digital and
analog circuits in the channel. The tx_digitalreset,
rx_digitalreset, and rx_analogreset signals affect the channels
individually. The gxb_powerdown signal affects the entire transceiver
block.
1
■
■
■
■
All reset and power-down signals are optional. Altera strongly
recommends using the reset and power-down signals and
following the reset sequence detailed in this section.
tx_digitalreset—This signal resets all digital logic in the
transmitter. This signal operates independently from the other reset
signals. The minimum pulse width is two parallel cycles.
●
In Basic mode, Altera recommends de-asserting the
tx_digitalreset signal of all used transceiver blocks
simultaneously after the pll_locked signal from all active
transceiver blocks goes high.
rx_digitalreset—This signal resets all digital logic in the
receiver. This signal operates independently from the other reset
signals. The minimum pulse width is two parallel cycles.
rx_analogreset—This signal resets part of the analog portion of
the receiver CRU. This signal operates independently from the other
reset signals. The minimum pulse width is two parallel cycles.
gxb_powerdown—This signal powers down the entire transceiver
block, including the transmitter PLL. All digital and analog circuits
are also reset. This signal operates independently from the other reset
signals. The minimum pulse width is 100 ns.
Table 2–33 lists the transceiver modules that get affected by each reset and
power-down signal.
Table 2–33. Blocks Affected by Reset and Power-Down Signals (Part 1 of 2)
Transceiver Blocks
rx_digitalreset
rx_analogreset
tx_digitalreset
gxb_powerdown
Transmitter phase compensation
FIFO buffer and byte serializer
—
—
v
v
Transmitter 8B/10B encoder
—
—
v
v
Transmitter serializer
—
—
—
v
Transmitter analog circuits
—
—
—
v
Transmitter PLLs
—
—
—
v
Transmitter analog circuits
—
—
—
v
Receiver deserializer
—
—
—
v
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Reset Control and Power-Down
Table 2–33. Blocks Affected by Reset and Power-Down Signals (Part 2 of 2)
Transceiver Blocks
rx_digitalreset
rx_analogreset
tx_digitalreset
gxb_powerdown
Receiver word aligner
v
—
—
v
Receiver rate matcher
v
—
—
v
Receiver 8B/10B decoder
v
—
—
v
Receiver phase compensation
FIFO buffer and byte deserializer
v
—
—
v
Receiver PLL and CRU
—
v
—
v
Receiver analog circuits
—
—
—
v
The recommended reset sequence varies depending on whether the CRU
is configured in automatic lock mode or manual lock mode.
Recommended Reset Sequence for GIGE and Serial RapidIO in
CRU Automatic Lock Mode
Figure 2–48 shows a sample reset sequence for GIGE, Serial RapidIO,
XAUI, SDI, and Basic modes when the CRU is configured in automatic
lock mode.
Figure 2–48. Reset Sequence for GIGE, Serial RapidIO, XAUI, SDI and Basic in Automatic Mode
100 ns
Reset/Power Down Signals
1
2
gxb_powerdown
4
tx_digitalreset
4
rx_analogreset
7
rx_digitalreset
Output Status Signals
3
pll_locked
5
rx_pll_locked
6
rx_freqlocked
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May 2008
4 μs
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After power on, follow these steps:
1.
Assert the gxb_powerdown port for a minimum period of 100 ns
(time between markers 1 and 2).
2.
Keep the tx_digitalreset, rx_digitalreset, and
rx_analogreset asserted during this time period.
3.
After you de-assert the gxb_powerdown signal, the transmitter PLL
starts locking to the transmitter input reference clock. Once the
transmitter PLL locks (as indicated by the pll_locked signal
going high), you de-assert the tx_digitalreset signal.
4.
After you de-assert the rx_analogreset signal, the receiver PLL
starts locking to the receiver input reference clock (in automatic lock
mode).
5.
Once the receiver PLL locks to the input reference clock, the
rx_pll_locked signal goes high. The internal PPM detector takes
some time to calculate the PPM difference between the receiver PLL
output clock and the input reference clock.
6.
Once it calculates the PPM difference to be within the pre-defined
limits, the rx_freqlocked signal goes high. At this point the CRU
enters lock-to-data mode and the receiver PLL starts locking to the
received data.
7.
You de-assert the rx_digitalreset 4 μs after the
rx_freqlocked signal goes high.
Recommended Reset Sequence for GIGE, Serial RapidIO, XAUI,
SDI, and Basic Modes in CRU Manual Lock Mode
Figure 2–49 shows a sample reset sequence for GIGE, Serial RapidIO,
XAUI, SDI, and Basic modes when the CRU is configured in manual lock
mode.
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Reset Control and Power-Down
Figure 2–49. Reset Sequence for GIGE and Serial RapidIO in Manual Mode
100 ns
Reset/Power Down Signals
1
2
gxb_powerdown
4
tx_digitalreset
4
rx_analogreset
7
rx_digitalreset
4 μs
Output Status Signals
3
pll_locked
5
rx_pll_locked
CRU Control Signals
6
rx_locktorefclk
rx_locktodata
15 μs
After power-on, follow these steps:
Altera Corporation
May 2008
1.
Assert the gxb_powerdown port for a minimum period of 100 ns
(time between markers 1 and 2). Keep the tx_digitalreset,
rx_digitalreset, rx_analogreset, and rx_locktorefclk
signals asserted during this time period.
2.
After you de-assert the gxb_powerdown signal, the transmitter PLL
starts locking to the transmitter input reference clock.
3.
Once the transmitter PLL locks (as indicated by the pll_locked
signal going high), you de-assert the tx_digitalreset signal.
4.
After you de-assert the rx_analogreset signal, the receiver PLL
starts locking to the receiver input reference clock since
rx_locktorefclk is asserted.
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5.
Wait for at least 15 μs (time between markers 5 and 6) after the
rx_pll_locked signal goes high and then de-assert the
rx_locktorefclk signal.
6.
At the same time assert the rx_locktodata signal. At this point
the CRU enters lock-to-data mode and the receiver PLL starts
locking to the received data.
7.
You de-assert the rx_digitalreset at least 4 μs (time between
markers 6 and 7) after asserting the rx_locktodata signal.
Recommended Reset Sequence for PCI Express (PIPE) Mode
In PCI Express (PIPE) mode, the rx_freqlocked signal does not go
high during the PCI Express (PIPE) compliance testing phase because of
receiving Electrical Idle. For all other modes, the reset sequence looks for
the rx_freqlocked signal to de-assert rx_digitalreset.
Figure 2–50 shows the reset sequence for PCI Express (PIPE) mode.
Figure 2–50. Reset Sequence for PCI Express (PIPE) Mode
Initialization/PCI-E Compliance Phase
Normal Operation Phase
100 ns
1
2
gxb_powerdown
4
tx_digitalreset
4
rx_analogreset
6
10
11
rx_digitalreset
T3
3
pll_locked
5
rx_pll_locked
7
8
9
rx_freqlocked
T2
T1
Ignore Receive Data
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May 2008
Reset Control and Power-Down
Initialization and PCI Express Compliance Phase
After the device is powered up, a PCI Express-compliant device may
perform compliance testing. Because rx_digitalreset must be
de-asserted during compliance testing, waiting for the rx_freqlocked
signal to de-assert rx_digitalreset is not recommended.
De-assert the tx_digitalreset signal after the pll_locked signal
goes high. De-assert the rx_digitalreset when the rx_pll_locked
signal goes high (unlike GIGE and Serial RapidIO modes, where you wait
until rx_freqlocked goes high).
The parallel data sent to the PLD logic array in the receive side may not
be valid until 4 μs after rx_freqlocked goes high.
Normal Operation Phase
During normal operation, the receive data is valid and the
rx_freqlocked signal is high. In this situation, when rx_freqlocked
is de-asserted, (marker 8 in Figure 2–50), wait for the rx_freqlocked
signal to go high again and assert rx_digitalreset (marker 10 in
Figure 2–50) for two parallel receive clock cycles.
The data from the transceiver block is not valid between the time when
rx_freqlocked goes low until rx_digitalreset is de-asserted. The
PLD logic should ignore the data during this time period (the time period
between markers 8 and 11 in Figure 2–50).
1
Minimum T1 and T2 period is 4 μs. Minimum T3 period is two
parallel receive clock cycles.
Rate Matcher FIFO Buffer Overflow and Underflow Condition
During the normal operation phase, monitor the overflow and underflow
status of the rate matcher FIFO buffer. If there is overflow and underflow
on the rate matcher FIFO buffer, assert the rx_digitalreset signal for
two receive parallel clock cycles. You can monitor the rate matcher FIFO
buffer status through the pipestatus[2:0] signal from the PCI
Express (PIPE) interface. This condition is shown in Figure 2–51.
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May 2008
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Arria GX Transceiver Protocol Support and Additional Features
Figure 2–51. PCI Express (PIPE) Mode Reset During Rate Matcher FIFO Buffer Overflow & Underflow
Condition
tx_digitalreset
1
0
rx_analogreset
1
0
rx_digitalreset
1
0
T3
rx_freqlocked
T3
1
0
000
pipestatus
101
000
110
000
Notes to Figure 2–51:
(1)
(2)
Pipestatus = 101 represents elastic overflow (not available in Low-Latency [Synchronous] PCI Express [PIPE]
mode).
Pipestatus = 110 represents elastic overflow (not available in Low-Latency [Synchronous] PCI Express [PIPE] mode).
Power-Down
The Quartus II software automatically selects the power-down channel
feature, which takes effect when you configure the Arria GX device. All
unused transceiver channels and blocks in a design are powered down to
reduce the overall power consumption.
1
The gxb_powerdown port is optional. In simulation, if the
gxb_powerdown port is not instantiated, you must assert the
tx_digitalreset, rx_digitalreset and
rx_analogreset signals appropriately for correct simulation
behavior. If the gxb_powerdown port is instantiated and other
reset signals are not used, you must assert the gxb_powerdown
signal for at least one parallel clock cycle for correct simulation
behavior. In simulation, you can de-assert the
rx_digitalreset immediately after rx_freqlocked signal
goes high to reduce the simulation run time. It is not necessary
to wait for 4 µs (as suggested in the actual reset sequence).
1
In PCI Express (PIPE) mode simulation, you must assert the
tx_forceelecidle signal for at least one parallel clock cycle
before transmitting normal data for correct simulation behavior.
TimeQuest Timing Analyzer
Quartus II software designs targeted towards the Arria GX device family
use the TimeQuest Timing Analyzer for static timing analysis. Starting
with Quartus II software versions 7.1 and 7.1 sp1, the TimeQuest Timing
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Reset Control and Power-Down
Analyzer does not automatically constrain the transceiver reset ports and
asynchronous input/output ports. As a result, the TimeQuest Timing
Analyzer does not perform timing analysis on these paths.
The TimeQuest Timing Analyzer reports these unconstrained paths in
RED in the Timing Analyzer report. You must manually add the
constraints in the Synopsys Design Constraints (.sdc) file for the
TimeQuest Timing Analyzer to analyze these paths.
Unconstrained Reset Ports
In the Quartus II software versions 7.1 and 7.1 sp1, the TimeQuest Timing
Analyzer does not constrain the following transceiver reset ports:
■
■
■
■
gxb_powerdown
tx_digitalreset
rx_digitalreset
rx_analogreset
Identifying Unconstrained Reset Ports
To identify the unconstrained reset/powerdown ports, follow these
steps:
1.
After compiling your design, in the Tools drop-down menu, select
the TimeQuest Timing Analyzer. This opens up the Quartus II
TimeQuest Timing Analyzer window.
2.
In the Tasks pane, execute Report Unconstrained Paths. This
reports all unconstrained paths in RED in the Report pane.
3.
In the Report pane, expand the Unconstrained Paths option and
further expand the Setup Analysis or Hold Analysis option.
4.
Under Setup Analysis or Hold Analysis, appears Unconstrained
Input Port Paths, Unconstrained Output Port Paths, or both,
depending on how the reset/powerdown ports are driven.
5.
Altera Corporation
May 2008
a.
If a reset/powerdown port is driven by an input pin, it is listed
in the Unconstrained Input Port Paths report.
b.
If a reset/powerdown port is driven by synchronous logic, it is
listed in the Unconstrained Output Port Paths report.
In the Unconstrained Input Port Paths and Unconstrained Output
Port Paths reports, the unconstrained reset/powerdown ports of
your ALT2GXB instances are listed under the To column.
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Consider the design example in Figure 2–52.
Figure 2–52. Example Design for TimeQuest Timing Analyzer Constraints
top_tx_digitalreset
gxb_powerdown
Reset Controller
ALT2GXB
Channel 0
rx_digitalreset
rx_analogreset
ALT2GXB
Channel 1
In the design example in Figure 2–52, all reset/powerdown ports for the
two channels are driven by the reset controller (except the
tx_digitalreset port). The tx_digitalreset port is driven from
an input pin.
Figures 2–53 and 2–54 show the TimeQuest Timing Analyzer Report for
Unconstrained Input Port Paths and Unconstrained Output Port Paths,
respectively.
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May 2008
Reset Control and Power-Down
Figure 2–53. Unconstrained Input Port Paths
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Figure 2–54. Unconstrained Output Port Paths
Having identified the unconstrained reset/powerdown ports in the
design, the next step is to constrain these ports.
Setting Reset/Powerdown Port Timing Constraints
You must add the reset/powerdown port timing constraints either
directly in the .sdc file or through the TimeQuest Timing Analyzer GUI.
To add the timing constraints using the TimeQuest GUI, follow these
steps:
1.
In either the Unconstrained Input Port Paths or Unconstrained
Output Port Paths report, locate the reset/powerdown ports.
2.
In the To column, right-click the reset/powerdown port and select
Set Max Delay.
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Reset Control and Power-Down
3.
On the resulting window, enter an initial Delay Value of 4 ns.
4.
In the To column, right click on the reset/powerdown port again
and select Set Min Delay.
5.
On the resulting window, enter an initial Delay Value of 1.2 ns.
1
The difference between the maximum delay and minimum
delay is set to 2.8 ns, which is the maximum skew allowed on
reset/powerdown ports.
6.
Set the maximum and minimum delay for all transceiver
reset/powerdown ports in your design, according to steps 1-5.
7.
In the Tasks pane of the TimeQuest Timing Analyzer, double-click
Update Timing Netlist and Write SDC File. Double-clicking on
each of these causes them to execute.
8.
Confirm that the above timing constraints were added to the .sdc
file linked with your design.
9.
Run the Quartus II Fitter.
10. After the Quartus II Fitter operation completes, in the Tasks pane of
the TimeQuest Timing Analyzer window, double-click on Update
Timing Netlist. The Update Timing Netlist task then executes.
11. Execute Report Top Failing Paths by double-clicking this option in
the Tasks pane of the TimeQuest Timing Analyzer window.
12. Assuming all other paths in your design meet timing, one or more
of the paths involving reset/powerdown ports might report timing
violations. This is because the design is not able to meet the
preliminary timing constraints of 4 ns (maximum delay) and 1.2 ns
(minimum delay).
13. Note the slack in the timing report for all failing paths and adjust the
maximum delay and the minimum delay values in the file. Maintain
a difference of 2.8 ns between the maximum delay and the
minimum delay for each reset/powerdown port.
14. After adjusting the delay values, execute Update Timing Netlist
and run the Quartus II Fitter again.
15. After the Quartus II Fitter operation completes, execute Update
Timing Netlist.
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16. Execute Report Top Failing Paths once again. If there are any failing
paths involving the reset/powerdown ports, adjust the delay values
in the .sdc file and repeat the procedure until no failing paths are
reported.
Consider the previous design example in which all unconstrained ports
were identified. The following example shows how to set the constraints
for the gxb_powerdown port. The same procedure must be followed for
all other reset ports.
After setting the maximum and minimum delay for the gxb_powerdown
port, the .sdc file should have the constraints detailed in Example 2–1 and
Example 2–2:
Example 2–1. Settings for Maximum Delay in the gxb_powerdown Port
#****************************************************
# Set Maximum Delay
#****************************************************
set_max_delay -from [get_keepers
{reset_seq_tx_rx_rx_cruclk_rx_clkout:inst2|gxb_powerd
own}] -to [get_ports
{PIPE_DataGen_Ch:inst|alt2gxb:alt2gxb_component|chann
el_quad[0].cent_unit~OBSERVABLEQUADRESET}] 4.000
Example 2–2. Settings for Minimum Delay in the gxb_powerdown Port
#****************************************************
# Set Minimum Delay
#****************************************************
set_min_delay -from [get_keepers
{reset_seq_tx_rx_rx_cruclk_rx_clkout:inst2|gxb_powerd
own}] -to [get_ports
{PIPE_DataGen_Ch:inst|alt2gxb:alt2gxb_component|chann
el_quad[0].cent_unit~OBSERVABLEQUADRESET}] 1.200
After running the Quartus II fitter with the above timing constraints for
the gxb_powerdown port, the following slack is reported on this path
after executing Report Top Failing Paths (Figure 2–55).
2–96
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May 2008
Reset Control and Power-Down
Figure 2–55. Slack Reported for the gxb_powerdown Port
Because the data arrival time is later than the data required time by
0.798 ns, the maximum delay and minimum delay should both be
incremented by 0.8 ns in the .sdc file. The new .sdc file should have the
modified constraints for the gxb_powerdown port indicated in
Example 2–3 and Example 2–4.
Example 2–3. Modified Settings for Maximum Delay for the gxb_powerdown Port
#***************************************************
# Set Maximum Delay
#****************************************************
set_max_delay -from [get_keepers
{reset_seq_tx_rx_rx_cruclk_rx_clkout:inst2|gxb_powerd
own}] -to [get_ports
{PIPE_DataGen_Ch:inst|alt2gxb:alt2gxb_component|chann
el_quad[0].cent_unit~OBSERVABLEQUADRESET}] 4.8
Example 2–4. Modified Settings for Minimum Delay for the gxb_powerdown Port
#****************************************************
# Set Minimum Delay
#****************************************************
set_min_delay -from [get_keepers
{reset_seq_tx_rx_rx_cruclk_rx_clkout:inst2|gxb_powerd
own}] -to [get_ports
{PIPE_DataGen_Ch:inst|alt2gxb:alt2gxb_component|chann
el_quad[0].cent_unit~OBSERVABLEQUADRESET}] 2.000
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
After modifying the .sdc file and running the Quartus II Fitter, the Update
Timing Netlist option should be executed, followed by Report Top
Failing Paths. If the gxb_powerdown port still shows in the failing paths,
modify the slack appropriately in the .sdc file and repeat the procedure
until timing is met on this path.
Follow the same procedure to set timing constraints on all transceiver
reset/powerdown ports in your design.
1
You should set constraints and meet timing for both fast and
slow timing models. The same maximum and minimum delay
constraints might not be able to meet timing for both timing
models. This is acceptable as long as the skew is within the
specified period (2.8 ns) for each path in the .sdc file for each
timing model.
Unconstrained Asynchronous ALT2GXB Ports
In the Quartus II software versions 7.1 and 7.1 sp1, the TimeQuest Timing
Analyzer does not automatically constrain transceiver asynchronous
input/output ports. These ports are listed in Table 2–34.
Table 2–34. TImeQuest Timing Analyzer Port Names Versus ALT2GXB Port
Names
TimeQuest Timing Analyzer Port
Name
ALT2GXB Port Name
ala2size
rx_ala2size
enapatternalign
rx_enapatternalign
bitslip
rx_bitslip
rlv
rx_rlv
invpol
rx_invpolarity
enabyteord
rx_enabyteord
pipe8b10binvpolarity
pipe8b10binvpolarity
revbitorderwa
rx_revbitorderwa
bisterr
rx_bisterr
bistdone
rx_bitstdone
phaselockloss
rx_pll_locked
freqlock
rx_freqlocked
seriallpbkben
rx_seriallpbken
2–98
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May 2008
Referenced Document
You must add the timing constraints manually in the .sdc file or for the
TimeQuest Timing Analyzer to analyze these paths. For these
asynchronous ports, you only need to set a maximum delay constraint of
10 ns in the .sdc file.
To identify all unconstrained ALT2GXB asynchronous ports, execute
Report Unconstrained Paths in TimeQuest Timing Analyzer after
running the Quartus II Fitter. Set a maximum delay of 10 ns for all such
ports in the .sdc file.
For example, if the rx_invpolarity signal is driven by the signal
top_rx_invpolarity on an input pin, the .sdc file constraint for this
port should be set as shown in Example 2–5.
Example 2–5. Constraints for the rx_invpolarity Port
set_max_delay -from [get_ports {top_rx_invpolarity}]
-to [get_keepers
{xcvr_inst.receive~OBSERVABLEINVPOL}] 10.000
Follow the same procedure to constrain all asynchronous ALT2GXB ports
in your design before closing timing analysis for your design.
Referenced
Document
Altera Corporation
May 2008
This chapter references the following documents:
■
■
■
Arria GX ALT2GXB Megafunction User Guide
Arria GX Transceiver Architecture
SDI MegaCore Function User Guide
2–99
Arria GX Device Handbook, Volume 2
Arria GX Transceiver Protocol Support and Additional Features
Document
Revision History
Table 2–35 shows the revision history for this chapter.
Table 2–35. Document Revision History
Date and Document
Version
Changes Made
Summary of Changes
May 2008, v2.0
Added “Basic Single-Width Mode”, “Serial Digital Interface
(SDI) Mode”, “XAUI Mode” and “UNH-IOL Gigabit Ethernet
Compliance” sections.
Updated “Serial RapidIO Mode Transmitter Architecture”
section.
—
August 2007, v1.2
Added the “Referenced Document” section.
—
Minor text edits.
—
June 2007 v1.1
Added “TimeQuest Timing Analyzer” section.
—
Added GIGE information.
—
May 2007 v1.0
Initial release.
—
2–100
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
3. Arria GX ALT2GXB
Megafunction User Guide
AGX52003-2.0
Introduction
The MegaWizard® Plug-In Manager in the Quartus® II software creates or
modifies design files that contain custom megafunction variations that
can then be instantiated in a design file. The MegaWizard Plug-In
Manager provides a wizard that allows you to specify options for the
ALT2GXB megafunction. You can use the wizard to set the ALT2GXB
megafunction features in the design.
Start the MegaWizard Plug-In Manager using one of the following
methods:
■
■
■
Choose the MegaWizard Plug-In Manager command (Tools menu).
In the Block Editor, click MegaWizard Plug-In Manager in the
Symbol dialog box (Edit menu).
Start the stand-alone version of the MegaWizard Plug-In Manager by
typing the following command at the command prompt: qmegawiz.
The ALT2GXB MegaWizard Plug-In Manager allows you to configure
one or more transceiver channels.
This chapter contains the following sections:
■
■
■
■
■
■
“Basic Mode” on page 3–3
“PCI Express (PIPE) Mode” on page 3–25
“XAUI Mode” on page 3–46
“GIGE Mode” on page 3–64
“SDI Mode” on page 3–86
“Serial RapidIO Mode” on page 3–117
Figure 3–1 shows the first page of the MegaWizard Plug-In Manager. To
generate an ALT2GXB custom megafunction variation, select Create a
new custom megafunction variation and click Next.
Altera Corporation
May 2008
3–1
Preliminary
Arria GX ALT2GXB Megafunction User Guide
Figure 3–1. MegaWizard Plug-In Manager (Page 1)
Figure 3–2 shows the second page of the MegaWizard Plug-In Manager.
Select Arria GX as the device family.
Figure 3–2. MegaWizard Plug-In Manager (Page 2)
3–2
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Basic Mode
Basic Mode
This section provides descriptions of the options available on the
individual pages of the ALT2GXB MegaWizard Plug-In Manager for
Basic mode. The MegaWizard Plug-In Manager provides a warning if any
of the settings you choose are illegal.
Figure 3–3 shows page 3 of the ALT2GXB MegaWizard Plug-In Manager
in Basic mode.
Figure 3–3. MegaWizard Plug-In Manager - ALT2GXB (General)
Altera Corporation
May 2008
3–3
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–1 describes the available options on page 3 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–1. MegaWizard Plug-In Manager Options (Page 3 for Basic Mode) (Part 1 of 2)
ALT2GXB Setting
Description
Which protocol will you be
using?
Determines the specific protocol or modes under
which the transceiver operates. For Basic mode, you
must select the Basic protocol.
Which subprotocol will you
be using?
In Basic mode, the subprotocols are the diagnostic
modes. The available options are as follows:
● No loopback – This is the normal operation of the
transceiver.
● Serial loopback – This mode loops the user data
from the transmitter path back to the receiver path
right before the buffers. Serial loopback can be
controlled dynamically.
● Reverse serial loopback – This is a loopback after
the receiver’s CDR block to the transmitter buffer.
The RX path in the PCS is active but the TX side
is not.
● Reverse serial loopback (pre-CDR) – This is the
loopback before the receiver’s CDR block to the
transmitter buffer. The RX path in the PCS is
active but the TX side is not.
● PRBS/Serial loopback – This is another serial
loopback mode, but with the PRBS BIST block
active. The PRBS pattern depends on the
serializer/deserializer (SERDES) factor.
● ×4 – This mode can be used to implement the
SFI-5 interface. In this mode, all four channels
within the transceiver block are clocked from its
central clock divider block to minimize transmitter
channel-to-channel skew.
Enforce default settings for
this protocol
This selection is not active in Basic mode because
there is no pre-defined protocol.
Reference
Loopback Modes and
Built-In Self-Test Modes
sections in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
What is the operation mode? The available operation modes are receiver only,
transmitter only, and receiver and transmitter.
What is the number of
channels?
This option determines how many duplicate channels
this ALT2GXB instance contains.
What is the deserializer
block width?
This option sets the transceiver data path width and
defaults to single width mode.
Single width—In this mode, the transceiver operates
between 600 Mbps to 3.125 Gbps.
3–4
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Basic Mode
Table 3–1. MegaWizard Plug-In Manager Options (Page 3 for Basic Mode) (Part 2 of 2)
ALT2GXB Setting
What is the channel width?
Description
Reference
This option determines the transceiver-to-PLD
interface width.
In single-width mode, selecting 8 or 10 bits bypasses
the byte serializer/deserializer. If you select 16 or 20
bits, the byte serializer/deserializer is used.
What would you like to base
the setting on?
●
What is the data rate?
Determines the TX and RX PLL VCO frequency.
What is the input clock
frequency?
Determines the input clock frequency you want as a
reference clock for the transceiver.
Byte Serializer and
Deserializer sections in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
This option allows you to do one of following:
Enter a data rate and select an input clock
frequency through a pull-down menu (with the
data rate selection).
● Enter your input clock frequency through a
pull-down menu (with the data rate selection) or
enter your input clock frequency and select from
the available data rates for a clock frequency.
What is the data rate division This setting, in conjunction with the selected data
factor?
rate, determines the effective data rate for the
transceiver channel. Division factors of 1, 2, and 4 are
available. For example, a data rate setting of
3000 Mbps and at data rate division factor of 2 yields
an effective data rate of 1500 Mbps.
Altera Corporation
May 2008
3–5
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–4 shows page 4 of the ALT2GXB MegaWizard Plug-In Manager
for Basic mode.
Figure 3–4. MegaWizard Plug-In Manager - ALT2GXB (PLL/Ports)
3–6
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Basic Mode
Table 3–2 describes the available options on page 4 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–2. MegaWizard Plug-In Manager Options (Page 4 for Basic Mode) (Part 1 of 2)
ALT2GXB Setting
Train Receiver PLL clock
from PLL inclk
Description
Reference
If you turn this option on, your design uses the input
reference clock to the transmitter PLL to train the
receiver PLL. This reduces the need to supply a
separate receiver PLL reference clock.
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
What is the GXB Transmitter This option selects the transmitter PLL bandwidth and Clock Multiplier Unit
PLL bandwidth mode?
the allowed options are low, medium and high.
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
What is the Receiver PLL
bandwidth mode?
This option selects the receiver PLL bandwidth and the Clock Recovery Unit
allowed options are low, medium and high.
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
What is the acceptable PPM
threshold between the
Receiver PLL VCO and the
CRU clock?
This option determines the parts per million (PPM)
difference that affects the automatic receiver clock
recovery unit (CRU) switchover between lock-to-data
and lock-to-reference. There are additional factors that
affect the CRU’s transition.
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create gxb_powerdown
port to power down the
Quad
This signal can be used to reset and power down all
circuits in the transceiver block. It does not power
down the REFCLK buffers and reference clock lines.
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create gxb_enable port
to enable the Quad
This signal can be used to enable Arria GX transceiver Reset Control and Power
Down section in the
blocks. If instantiated, this port must be tied to the
Arria GX Transceiver
dedicated gigabit transceiver block enable input pin.
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create rx_analogreset
port
Receiver analog reset port.
Altera Corporation
May 2008
Reset Control and Power
Down” section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
3–7
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–2. MegaWizard Plug-In Manager Options (Page 4 for Basic Mode) (Part 2 of 2)
ALT2GXB Setting
Create
rx_digitalreset port
Create
tx_digitalreset port
Description
Reference
Receiver digital reset port. Resets the PCS portion of
the receiver. Altera® recommends using this port along
with logic to implement the recommended reset
sequence.
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Transmitter digital reset port. Resets the PCS portion
of the transmitter. Altera recommends using this port
along with logic to implement the recommended reset
sequence.
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create pll_locked port PLL locked indicator for the transmitter PLLs.
to indicate PLL is in lock with
the reference input clock
Clock Multiplier Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create
Lock-to-reference lock mode for the CRU. Use with
rx_locktorefclk port
rx_locktodata.
rx_locktodata/rx_locktorefclk
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
to lock the RX PLL to the
reference clock
Create rx_locktodata
port to lock the RX PLL to
the received data
0/0—CRU is in automatic mode
0/1—CRU is in lock-to-reference clock
1/0—CRU is in lock-to-data mode
1/1—CRU is in lock-to-data mode
Lock-to-data control for the CRU. Use with
rx_locktorefclk.
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Receiver PLL locked signal. Indicates if the receiver
Create rx_pll_locked
port to indicate RX PLL is in PLL is phase locked to the CRU reference clock.
lock with the reference clock
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
CRU mode indicator port. Indicates if the CRU is
locked to data mode or locked to the reference clock
mode.
0—Receiver CRU is in lock-to-reference clock
mode
1—Receiver CRU is in lock-to-data mode
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create rx_freqlocked
port to indicate RX PLL is in
lock with the received data
3–8
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Basic Mode
Figure 3–5 shows page 5 of the ALT2GXB MegaWizard Plug-In Manager
for Basic mode.
Figure 3–5. MegaWizard Plug-In Manager - ALT2GXB (Ports/Cal Blk)
Altera Corporation
May 2008
3–9
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–3 describes the available options on page 5 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–3. MegaWizard Plug-In Manager Options (Page 5 for Basic Mode) (Part 1 of 2)
ALT2GXB Setting
Description
Reference
to indicated data input
signal detection
Signal detect port. In PCI Express (PIPE) mode,
indicates if a signal that meets the specified range is
present at the input of the receiver buffer. In all other
modes, rx_signaldetect is forced high and must
not be used as an indication of a valid signal at
receiver input.
Receiver Phase
Compensation FIFO
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create
This optional output port indicates Receiver Phase
Receiver Phase
Create
rx_signaldetect port
Compensation FIFO
debug_rx_phase_comp Compensation FIFO overflow/under run condition.
_fifo_error output port Note that no PPM difference is allowed between FIFO section in the Arria GX
Create
read and write clocks. Use this port for debug
purposes only.
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
This optional output port indicates Transmitter Phase
Transmitter Phase
Compensation FIFO
debug_tx_phase_comp Compensation FIFO overflow/under run condition.
_fifo_error output port Note that no PPM difference is allowed between FIFO section in the Arria GX
Create rx_coreclk port
to connect to the read clock
of the RX phase
compensation FIFO
read and write clocks. Use this port for debug
purposes only.
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
This optional input port allows you to clock the read
side of the Receiver Phase Compensation FIFO with
a non-transceiver PLD clock.
Transceiver Clocking
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create tx_coreclk port This optional input port allows you to clock the write
to connect to the write clock side of the Transmitter Phase Compensation FIFO
with a non-transceiver PLD clock.
of the TX phase
compensation FIFO
3–10
Arria GX Device Handbook, Volume 2
Transceiver Clocking
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Altera Corporation
May 2008
Basic Mode
Table 3–3. MegaWizard Plug-In Manager Options (Page 5 for Basic Mode) (Part 2 of 2)
ALT2GXB Setting
Description
Reference
Use calibration block
This option allows you to select which instance of the
ALT2GXB megafunction instantiates the calibration
block. Only one instance of the ALT2GXB
megafunction is required to instantiate the calibration
block.
Calibration Blocks
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create active low
Power-down signal for the calibration block. Assertion
of this signal may interrupt data transmission and
reception. Use this signal to re-calibrate the
termination resistors if temperature and/or voltage
changes warrant it.
Calibration Blocks
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
cal_blk_powerdown to
power down the calibration
block
Altera Corporation
May 2008
3–11
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–6 shows page 6 of the ALT2GXB MegaWizard Plug-In Manager
for Basic mode.
Figure 3–6. MegaWizard Plug-In Manager - ALT2GXB (RX Analog)
3–12
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Basic Mode
Table 3–4 describes the available options on page 6 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–4. MegaWizard Plug-In Manager Options (Page 6 for Basic Mode) (Part 1 of 2)
ALT2GXB Setting
Description
Reference
Enable manual equalizer
control
This option enables the 0–4 setting options for manual Receiver Buffer section
equalizer control.
in the Arria GX
Transceiver
Architecture chapter in
volume 2 of the
Arria GX Device
Handbook.
What is the equalizer DC
gain?
This enables the DC gain option and the legal settings Receiver Buffer section
are 0, 1, 2, and 3.
in the Arria GX
Transceiver
Architecture chapter in
volume 2 of the
Arria GX Device
Handbook.
What is the Receiver
Common Mode Voltage
(RX VC M )?
The receiver common mode voltage is programmable. Receiver Buffer section
The selections available are 0.85 V and 1.2 V.
in the Arria GX
Transceiver
Architecture chapter in
volume 2 of the
Arria GX Device
Handbook.
Force signal detection
This option is not available in Basic mode.
Receiver Buffer Section
in the Arria GX
Transceiver
Architecture chapter in
volume 2 of the
Arria GX Device
Handbook.
What is the signal detect and
signal loss threshold?
This option is not available in Basic mode.
Receiver Buffer section
in the Arria GX
Transceiver
Architecture chapter in
volume 2 of the
Arria GX Device
Handbook.
Altera Corporation
May 2008
3–13
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–4. MegaWizard Plug-In Manager Options (Page 6 for Basic Mode) (Part 2 of 2)
ALT2GXB Setting
Description
Reference
Use external receiver
termination
This option is available if you use an external
termination resistor instead of the on-chip termination
(OCT). If checked, this option turns off the receiver
OCT.
Receiver Buffer section
in the Arria GX
Transceiver
Architecture chapter in
volume 2 of the
Arria GX Device
Handbook.
What is the receiver
termination resistance?
This option selects the receiver termination value. The Receiver Buffer section
only supported receiver termination resistance value in the Arria GX
Transceiver
is 100 Ω .
Architecture chapter in
volume 2 of the
Arria GX Device
Handbook.
3–14
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Basic Mode
Figure 3–7 shows page 7 of the ALT2GXB MegaWizard Plug-In Manager
for Basic mode.
Figure 3–7. MegaWizard Plug-In Manager - ALT2GXB (TX Analog)
Altera Corporation
May 2008
3–15
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–5 describes the available options on page 7 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–5. MegaWizard Plug-In Manager Options (Page 7 for Basic Mode)
ALT2GXB Setting
Description
Reference
What is the Transmitter
Buffer Power (VCCH)?
This setting is for information only and is used to
calculate the VOD from the buffer power supply (VCCH)
and the transmitter termination to derive the proper
VOD range. In Basic mode, this option is fixed at 1.5 V
Transmitter Buffer section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
What is the Transmitter
Common Mode Voltage
(VC M )?
The transmitter common mode voltage setting is
selectable between 0.6 V and 0.7 V.
Transmitter Buffer section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Use external Transmitter
termination
This option is available if you use an external
termination resistor instead of the OCT. Checking this
option turns off the transmitter OCT.
Transmitter Buffer section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Select the Transmitter
termination resistance
This option selects the transmitter termination value.
This option defaults to 100 Ω for Arria GX devices.
Transmitter Buffer section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
What is the Voltage Output
Differential (VOD) control
setting?
This option selects the VO D of the transmitter buffer.
The differential output voltage is programmable
between 400 mV and 1200 mV in steps of 200 mV. The
available VO D settings change based on VC C H .
Transmitter Buffer section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Pre-emphasis pre-tap
setting (% of VOD)
This option is not available in Arria GX devices and is
fixed at 0.
Pre-emphasis first post-tap
setting (% of VOD)
This option sets the amount of pre-emphasis on the
transmitter buffer using first post-tap. The options
available are 0, 1, 2, 3, 4, and 5.
Transmitter Buffer section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Pre-emphasis second
This option is not available in Arria GX devices and is
post-tap setting (% of VOD) fixed at 0.
3–16
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Basic Mode
Figure 3–8 shows page 8 of the MegaWizard Plug-In Manager for Basic
protocol mode set up.
Figure 3–8. MegaWizard Plug-In Manager - ALT2GXB (Basic 1)
Table 3–6 describes the available options on page 8 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–6. MegaWizard Plug-In Manager Options (Page 8 for Basic Mode) (Part 1 of 3)
ALT2GXB Setting
Description
Reference
Enable byte ordering block
This option is not available in Arria GX devices.
—
What do you want the byte
ordering to be based on?
This option is not available in Arria GX devices.
—
Altera Corporation
May 2008
3–17
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–6. MegaWizard Plug-In Manager Options (Page 8 for Basic Mode) (Part 2 of 3)
ALT2GXB Setting
Description
Reference
What is the byte ordering
pattern?
This option is not available in Arria GX devices.
—
What is the byte ordering
pad pattern?
This option is not available in Arria GX devices.
—
Enable 8B/10B
decoder/encoder
This option enables the 8B/10B encoder and
decoder. This option is only available if the
channel width is 8 or 16 bits.
—
Create tx_forcedisp to This option allows you to force positive or
enable Force disparity and negative disparity on transmitted data in 8B/10B
use tx_dispval to code configurations.
up the incoming word using
positive or negative
disparity
8B/10B Encoder section in the
Arria GX Transceiver
Architecture chapter in volume
2 of the Arria GX Device
Handbook.
Enable rate match FIFO
This option enables the rate matcher and is only
available with the 8B/10B decoder.
Rate Matcher section in the
Arria GX Transceiver
Architecture chapter in volume
2 of the Arria GX Device
Handbook.
What is the 20-bit rate
match pattern1? (usually
used for +ve disparity
pattern)
Enter the positive disparity rate matcher pattern
and control code pattern. The skip pattern is used
for insertion or deletion. The control pattern
identifies which group of skip patterns to use for
rate matching. If only one disparity is needed for
rate matching, enter the same pattern for both
rate matching patterns (pattern1 and pattern2).
Rate Matcher section in the
Arria GX Transceiver
Architecture chapter in volume
2 of the Arria GX Device
Handbook.
What is the 20-bit rate
match pattern2? (usually
used for -ve disparity
pattern)
Enter the negative disparity rate matcher pattern
and control code pattern. The skip pattern is used
for insertion or deletion. The control pattern
identifies which group of skip patterns to use for
rate matching. If only one disparity is needed for
rate matching, enter the same pattern for both
rate matching patterns (pattern1 and pattern2).
Rate Matcher section in the
Arria GX Transceiver
Architecture chapter in volume
2 of the Arria GX Device
Handbook.
Flip Receiver output data
bits
This option reverses the bit order of the data at
the receiver-PLD interface at a byte level to
support MSBit-to-LSBit transmission protocols.
The default transmission order is LSBit-to-MSBit.
Flip Transmitter input data
bits
This option reverses the bit order of the data bits
at the input of the transmitter at a byte level to
support MSBit-to-LSBit transmission protocols.
The default transmission order is LSBit-to-MSBit.
3–18
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Basic Mode
Table 3–6. MegaWizard Plug-In Manager Options (Page 8 for Basic Mode) (Part 3 of 3)
ALT2GXB Setting
Enable Transmitter bit
reversal
Description
Reference
This option inverts (flips) the bit order of the data
bits at the transmitter PCS-PMA interface at a
byte level to support MSBit-to-LSBit transmission
protocols. The default transmission is
LSBit-to-MSBit.
8B/10B encoder section in the
Arria GX Transceiver
Architecture chapter in volume
2 of the Arria GX Device
Handbook.
Create rx_invpolarity This optional port allows you to dynamically
reverse the polarity of the received data at the
to enable word aligner
input of the word aligner.
polarity inversion
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in volume
2 of the Arria GX Device
Handbook.
Create tx_invpolarity This optional port allows you to dynamically
to allow Transmitter polarity reverse the polarity of the data to be transmitted
at the transmitter PCS-PMA interface.
inversion
8B/10B Encoder section in the
Arria GX Transceiver
Architecture chapter in volume
2 of the Arria GX Device
Handbook.
Altera Corporation
May 2008
3–19
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–9 shows page 9 of the MegaWizard Plug-In Manager for Basic
protocol mode set up.
Figure 3–9. MegaWizard Plug-In Manager - ALT2GXB (Basic 2)
3–20
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Basic Mode
Table 3–7 describes the available options on page 9 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–7. MegaWizard Plug-In Manager Options (Page 9 for Basic Mode) (Part 1 of 3)
ALT2GXB Setting
Description
Reference
This option sets the word aligner in manual
alignment mode. (Manual alignment, bit-slipping,
and built-in state machine are mutually exclusive
options.)
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
When should the word aligner This option sets the behavior of the
realign?
rx_enapatternalign signal to either edge
or level sensitive. Altera recommends using edge
sensitive for scrambled data (non-8B/10B) traffic
and level sensitive for 8B/10B traffic.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Use manual bit slipping mode This option sets the word aligner to use the
bit-slip port to alter the byte boundary one bit at
a time.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Use manual word alignment
mode
Use the built-in
'synchronization state
machine'
This option sets the word aligner to use the
built-in synchronization state machine. The
behavior is similar to the PIPE synchronization
state machine with adjustable synchronization
thresholds.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Number of bad data words
before loss of synch state
Use this option with the built-in state machine to
transition from a synchronized state to an
unsynchronized state.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Number of consecutive valid
words before synch state is
reached
This option sets the word aligner to check for a
given number of good code groups. Use this
option with the built-in state machine in
conjunction with the Number of valid patterns
before synchronization state is reached
option to achieve synchronization.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Number of valid patterns
This option checks for the number of valid
before synch state is reached alignment patterns seen. Use this option with the
built-in state machine in conjunction with the
Number of consecutive valid words before
synch state is reached option to achieve
synchronization.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Altera Corporation
May 2008
3–21
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–7. MegaWizard Plug-In Manager Options (Page 9 for Basic Mode) (Part 2 of 3)
ALT2GXB Setting
Description
Reference
What is the word alignment
pattern length?
This option sets the word alignment length. The
available choices depend on whether 8B/10B is
used and which word alignment mode is used.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the word alignment
pattern?
Enter the word alignment pattern here. The
length of the alignment pattern is based on the
word alignment pattern length. In bit-slip mode,
this option triggers rx_patterndetect.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Flip word alignment pattern
bits
This option reverses the bit order of the
alignment pattern at a byte level to support
MSB-to-LSB transmission protocols. The default
transmission order is LSB-to-MSB.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Enable run-length violation
checking with a run length of
This option activates the run-length violation
circuit. You can program the run length at which
the circuit triggers the rx_rlv signal.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Enable word aligner output
reverse bit ordering
In manual bit-slip mode, this option creates an
input port rx_revbitorderwa to dynamically
reverse the bit order at the output of the receiver
word aligner. In Basic mode, this option statically
configures the receiver to always reverse the bit
order of the data at the output of the word aligner.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create rx_syncstatus
output port for pattern
detector and word aligner
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create
Refer to the Arria GX Transceiver Architecture
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
rx_patterndetect port to chapter in volume 2 of the Arria GX Device
indicate pattern detected
Handbook for information about this port.
Create rx_ctrldetect
port to indicate 8B/10B
decoder has detected a
control code
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
3–22
Arria GX Device Handbook, Volume 2
8B/10B Decoder section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Altera Corporation
May 2008
Basic Mode
Table 3–7. MegaWizard Plug-In Manager Options (Page 9 for Basic Mode) (Part 3 of 3)
ALT2GXB Setting
Description
Reference
Create rx_errdetect port
to indicate 8B/10B decoder
has detected an error code
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
8B/10B Decoder section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create rx_disperr port to
indicate 8B/10B decoder has
detected a disparity code
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
8B/10B Decoder section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create
This option is not available for Arria GX devices. Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
rx_revbyteorderwa to
enable receiver symbol swap
Altera Corporation
May 2008
3–23
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–10 shows page 10 of the MegaWizard Plug-In Manager for Basic
protocol mode set up. The Generate simulation model creates a
behavioral model (.vo or .vho) of the transceiver instance for third-party
simulators. The Generate Netlist option generates a netlist for the third
party EDA synthesis tool to estimate timing and resource utilization for
the ALT2GXB instance.
Figure 3–10. MegaWizard Plug-In Manager - ALT2GXB (EDA)
3–24
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
PCI Express (PIPE) Mode
Figure 3–11 shows page 11 (last page) of the MegaWizard Plug-In
Manager for Basic protocol mode set up. You can select optional files on
this page. After you make your selections, click Finish to generate the
files.
Figure 3–11. MegaWizard Plug-In Manager - ALT2GXB (Summary)
PCI Express
(PIPE) Mode
This section provides descriptions of the options available on the
individual pages of the ALT2GXB MegaWizard Plug-In Manager for the
PCI Express (PIPE) mode. The MegaWizard Plug-In Manager provides a
warning if any of the settings you choose are illegal.
Altera Corporation
May 2008
3–25
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–12 shows page 3 of the ALT2GXB MegaWizard Plug-In Manager
for PCI Express (PIPE) mode.
Figure 3–12. MegaWizard Plug-In Manager - ALT2GXB (General)
3–26
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
PCI Express (PIPE) Mode
Table 3–8 describes the available options on page 3 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–8. MegaWizard Plug-In Manager Options (Page 3 for PCI Express [PIPE] Mode) (Part 1 of 2)
ALT2GXB Setting
Description
Reference
—
Which protocol will you be
using?
Determines the specific protocol or modes under
which the transceiver operates. For PCI Express
(PIPE) mode, you must select the PCI Express
(PIPE) protocol.
Which subprotocol will you
be using?
In PCI Express (PIPE) mode, the subprotocols are
the supported link widths: 1 or 4.
PCI Express (PIPE) Mode
section in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in volume
2 of the Arria GX Device
Handbook.
Enforce default settings for
this protocol
Selecting this option skips the PCI screen in the
PCI Express (PIPE) MegaWizard Plug-In Manager.
The PCI screen allows you to select the PCI
Express (PIPE) specific ports for your design. If you
select this option, all PCI Express (PIPE) specific
ports are used.
—
What is the operation mode? Only the receiver and transmitter (full duplex) mode
is allowed in the PCI Express (PIPE) mode.
Receiver-only and transmitter only modes are not
allowed.
—
What is the number of
channels?
—
This determines how many duplicate channels this
ALT2GXB instance contains. In a x4 subprotocol,
the number of channels increments by 4.
What is the deserializer block This option is unavailable in PCI Express (PIPE)
width?
mode.
—
Byte Serializer and Byte
Deserializer sections in the
Arria GX Architecture
chapter in volume 1 of the
Arria GX Device Handbook
What is the channel width?
This option determines the PLD-transceiver
interface width. Only 16-bit interface width is
supported.
What would you like to base
the setting on?
This option is unavailable because the data rate is
fixed at 2500 Mbps for PCI Express (PIPE) mode.
—
What is the data rate?
This option is unavailable because the data rate is
fixed at 2500 Mbps for PCI Express (PIPE) mode.
—
Altera Corporation
May 2008
3–27
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–8. MegaWizard Plug-In Manager Options (Page 3 for PCI Express [PIPE] Mode) (Part 2 of 2)
ALT2GXB Setting
What is the input clock
frequency?
Description
Reference
Determines the input reference clock frequency for PCI Express (PIPE) Mode
the transceiver. In PCI Express (PIPE) mode, only section in the Arria GX
Architecture chapter in
100 MHz is allowed.
volume 1 of the Arria GX
Device Handbook
What is the data rate division This option is unavailable in PCI Express (PIPE)
factor?
mode.
—
Figure 3–13 shows page 4 of the ALT2GXB MegaWizard Plug-In Manager
for PCI Express (PIPE) mode.
Figure 3–13. MegaWizard Plug-In Manager - ALT2GXB (PLL/Ports)
3–28
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
PCI Express (PIPE) Mode
Table 3–9 describes the available options on page 4 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–9. MegaWizard Plug-In Manager Options (Page 4 for PCI Express [PIPE] Mode) (Part 1 of 2)
ALT2GXB Setting
Description
Reference
If you select this option, the transmitter input
reference clock (pll_inclk) drives the
receiver PLL input reference clock also.
If you do not select this option, the signal on the
rx_cruclk port drives the receiver PLL input
reference clock.
—
What is the GXB Transmitter
PLL bandwidth mode?
This option is not available in PCI Express
(PIPE) mode because the transmitter PLL
bandwidth is fixed at high.
—
What is the Receiver PLL
bandwidth mode?
This option is not available in PCI Express
(PIPE) mode because the receiver PLL
bandwidth is fixed at medium.
—
Train Receiver PLL clock from
PLL_inclk
This option determines the PPM difference that
What is the acceptable PPM
threshold between the Receiver affects the automatic receiver clock recovery
PLL VCO and the CRU clock? unit (CRU) switchover between lock-to-data
and lock-to-reference. (There are additional
factors that affect the CRU’s transition.)
Clock Recovery Unit (CRU)
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device Handbook
Create gxb_powerdown port This signal can be used to reset and power
down all circuits in the transceiver block. It
to power down the Quad
does not power down the REFCLK buffers and
reference clock lines.
Reset Control and Power
Down section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device Handbook.
Create gxb_enable port to
enable the Quad
This signal can be used to enable Arria GX
transceiver blocks. If instantiated, this port
must be tied to the dedicated gigabit
transceiver block enable input pin.
Receiver analog reset port.
Create rx_analogreset
port for the analog portion of the
receiver
Create rx_digitalreset
port for the digital portion of the
receiver
Altera Corporation
May 2008
Reset Control and Power
Down section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device Handbook.
Reset Control and Power
Down section in the Arria GX
Transceiver Protocol Support
and Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Receiver digital reset port. Resets the PCS
logic of the receiver. Altera recommends using
this port to implement the recommended reset
sequence.
Reset Control and Power
Down section in the Arria GX
Transceiver Protocol Support
and Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
3–29
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–9. MegaWizard Plug-In Manager Options (Page 4 for PCI Express [PIPE] Mode) (Part 2 of 2)
ALT2GXB Setting
Description
Reference
Create tx_digitalreset
port for the digital portion of the
transmitter
Transmitter digital reset port. Resets the PCS
logic of the transmitter. Altera recommends
using this port to implement the recommended
reset sequence.
Reset Control and Power
Down section in the Arria GX
Transceiver Protocol Support
and Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Create pll_locked port to
indicate PLL is in lock with the
reference input clock
PLL locked indicator for the transmitter PLLs.
Reset Control and Power
Down section in the Arria GX
Transceiver Protocol Support
and Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Create rx_locktorefclk
port to lock the RX PLL to the
reference clock
Lock-to-reference lock mode for the CRU. Use
with rx_locktodata.
rx_locktodata/rx_locktorefclk
0/0—CRU is in automatic mode
0/1—CRU is in lock-to-reference clock
1/0—CRU is in lock-to-data mode
1/1—CRU is in lock-to-data mode
Clock Recovery Unit (CRU)
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device Handbook
Create rx_locktodata port
to lock the RX PLL to the
received data
Lock-to-data control for the CRU. Use with
rx_locktorefclk.
Clock Recovery Unit (CRU)
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device Handbook
Create rx_pll_locked port Receiver PLL locked signal. Indicates if the
to indicate RX PLL is in lock with receiver PLL is phase locked to the CRU
reference clock.
the reference clock
Reset Control and Power
Down section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device Handbook
Create rx_freqlocked port CRU mode indicator port. Indicates if the CRU
to indicate RX PLL is in lock with is locked to data mode or locked to the
reference clock mode.
the received data
0—Receiver CRU is in lock-to-reference clock
mode
1—Receiver CRU is in lock-to-data mode
Clock Recovery Unit (CRU)
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device Handbook
3–30
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
PCI Express (PIPE) Mode
Figure 3–14 shows page 5 of the ALT2GXB MegaWizard Plug-In Manager
for PCI Express (PIPE) mode.
Figure 3–14. MegaWizard Plug-In Manager - ALT2GXB (Ports/Cal Blk)
Altera Corporation
May 2008
3–31
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–10 describes the available options on page 5 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–10. MegaWizard Plug-In Manager Options (Page 5 for PCI Express [PIPE] Mode) (Part 1 of 2)
ALT2GXB Setting
Description
Reference
Signal detect port. In PCI Express (PIPE)
Create rx_signaldetect
port to indicate data input signal mode, indicates if a signal that meets the
specified range is present at the input of the
detection
receiver buffer. In all other modes,
rx_signaldetect is forced high and must
not be used as an indication of a valid signal at
receiver input.
Receiver Buffer section
under PCI Express (PIPE)
mode in the Arria GX
Transceiver Protocol Support
and Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Create
This optional output port indicates Receiver
Phase Compensation FIFO overflow/under run
condition. Note that no PPM difference is
allowed between FIFO read and write clocks.
Use this port for debugging purposes only.
Receiver Phase
Compensation FIFO section
in the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
This optional output port indicates Transmitter
Phase Compensation FIFO overflow/under run
condition. Note that no PPM difference is
allowed between FIFO read and write clocks.
Use this port for debug purposes only.
Transmitter Phase
Compensation FIFO section
in the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
Create rx_coreclk port to
connect to the read clock of the
RX phase compensation FIFO
This optional input port allows you to clock the
read side of the Receiver Phase
Compensation FIFO with a non-transceiver
PLD clock.
PLD-Transceiver Interface
Clocking section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
Create tx_coreclk port to
connect to the write clock of the
TX phase compensation FIFO
This optional input port allows you to clock the
write side of the Transmitter Phase
Compensation FIFO with a non-transceiver
PLD clock.
PLD-Transceiver Interface
Clocking section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
debug_rx_phase_comp_
fifo_error output port
Create
debug_tx_phase_comp_
fifo_error output port
3–32
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
PCI Express (PIPE) Mode
Table 3–10. MegaWizard Plug-In Manager Options (Page 5 for PCI Express [PIPE] Mode) (Part 2 of 2)
ALT2GXB Setting
Description
Reference
Use calibration block
This option allows you to select which instance
of the ALT2GXB megafunction instantiates the
calibration block. Only one instance of the
ALT2GXB megafunction is required to
instantiate the calibration block.
Calibration Block section in
the Arria GX Transceiver
Protocol Support and
Additional Features chapter
in volume 2 of the Arria GX
Device Handbook
Create active low
Power-down signal for the calibration block.
Calibration Block section in
the Arria GX Transceiver
powerdown the calibration block transmission and reception. Use this signal to Protocol Support and
Additional Features chapter
re-calibrate the termination resistors if
temperature and/or voltage changes warrant it. in volume 2 of the Arria GX
Device Handbook
cal_blk_powerdown port to Assertion of this signal may interrupt data
Altera Corporation
May 2008
3–33
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–12 shows page 6 of the ALT2GXB MegaWizard Plug-In Manager
for PCI Express (PIPE) mode.
Figure 3–15. MegaWizard Plug-In Manager - ALT2GXB (RX Analog)
3–34
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
PCI Express (PIPE) Mode
Table 3–11 describes the available options on page 6 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–11. MegaWizard Plug-In Manager Options (Page 6 for PCI Express [PIPE] Mode)
ALT2GXB Setting
Description
Reference
Enable manual equalizer
control
This option enables the 0–4 setting options for
manual equalizer control.
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the equalizer DC
gain?
In PIPE mode, a DC gain setting of 1 is forced.
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the Receiver
Common Mode Voltage (RX
VC M )?
The receiver common mode voltage is
programmable. The options available are 0.85 V
and 1.2 V.
Receiver Buffer section
under PCI Express (PIPE)
mode in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in volume
2 of the Arria GX Device
Handbook
Force signal detection
This option disables the signal detect circuit. You
must not select this option as signal detect circuitry
is required for electrical idle detection at the
receiver.
Receiver Buffer section
under PCI Express (PIPE)
mode in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in volume
2 of the Arria GX Device
Handbook
What is the signal detect and This option sets the trip point of the signal detect
signal loss threshold?
circuit. You must select a threshold level of 2 in PCI
Express (PIPE) mode.
Receiver Buffer section
under PCI Express (PIPE)
mode in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in volume
2 of the Arria GX Device
Handbook
Altera Corporation
May 2008
3–35
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–11. MegaWizard Plug-In Manager Options (Page 6 for PCI Express [PIPE] Mode)
ALT2GXB Setting
Description
Reference
Use external receiver
termination
This option is available if you use an external
termination resistor instead of the OCT. If checked,
this option turns off the receiver OCT.
—
What is the receiver
termination resistance?
In PCI Express (PIPE) mode, the only supported
receiver termination resistance is 100 Ω.
3–36
Arria GX Device Handbook, Volume 2
Receiver Buffer section
under PCI Express (PIPE)
mode in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in volume
2 of the Arria GX Device
Handbook
Altera Corporation
May 2008
PCI Express (PIPE) Mode
Figure 3–16 shows page 7 of the ALT2GXB MegaWizard Plug-In Manager
for PCI Express (PIPE) mode.
Figure 3–16. MegaWizard Plug-In Manager - ALT2GXB (TX Analog)
Altera Corporation
May 2008
3–37
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–12 describes the available options on page 7 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–12. MegaWizard Plug-In Manager Options (Page 7 for PCI Express [PIPE] Mode)
ALT2GXB Setting
What is the Transmitter Buffer
Power (VCCH)?
Description
In PCI Express (PIPE) mode, the transmitter
buffer power is fixed at 1.2 V. You must connect
the VC C H power pins of a PCI Express (PIPE)
transceiver bank to a 1.2 V power supply. You
must select 1.2 V PCML I/O standard for the
transmitter data output pins.
What is the Transmitter Common In PCI Express (PIPE) mode, the transmitter
Mode Voltage (VCM)?
common mode voltage is fixed at 0.6 V.
Reference
Transmitter Buffer section
under PCI Express
(PIPE) Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
Transmitter Buffer section
under PCI Express
(PIPE) Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
Use external Transmitter
termination
This option is available if you want to use an
external termination resistor instead of the OCT.
Checking this option turns off the transmitter
OCT.
—
Select the Transmitter
termination resistance
In PCI Express (PIPE) mode, the only supported
receiver termination resistance is 100 Ω.
Transmitter Buffer section
under PCI Express
(PIPE) Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
What is the Voltage Output
Differential (VOD) control
setting?
This option selects the VO D of the transmitter
buffer. The differential output voltage is
programmable between 400 mV and 1200 mV in
steps of 200 mV. The available VO D settings
change based on VC C H .
Transmitter Buffer section
under PCI Express
(PIPE) Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
Pre-emphasis pre-tap setting (%
of VOD)
This option is not available in Arria GX devices
and is fixed at 0.
3–38
Arria GX Device Handbook, Volume 2
—
Altera Corporation
May 2008
PCI Express (PIPE) Mode
Table 3–12. MegaWizard Plug-In Manager Options (Page 7 for PCI Express [PIPE] Mode)
ALT2GXB Setting
Description
Reference
Pre-emphasis first post-tap
setting (% of VOD)
This option sets the amount of pre-emphasis on
the transmitter buffer using first post-tap. The
options available are 0, 1, 2, 3, 4, and 5.
Transmitter Buffer section
under PCI Express
(PIPE) Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
Pre-emphasis second post-tap
setting (% of VOD)
This option is not available in Arria GX devices
and is fixed at 0.
—
Altera Corporation
May 2008
3–39
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–17 shows page 8 of the ALT2GXB MegaWizard Plug-In Manager
for PCI Express (PIPE) mode. If the Enforce default settings for this
protocol option is selected, this page does not appear in the MegaWizard
Plug-In Manager.
Figure 3–17. MegaWizard Plug-In Manager - ALT2GXB (PCI Express [PIPE] 1)
3–40
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
PCI Express (PIPE) Mode
Table 3–13 describes the available options on page 8 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–13. MegaWizard Plug-In Manager Options (Page 8 for PCI Express [PIPE] Mode) (Part 1 of 2)
ALT2GXB Setting
Description
Reference
Enable Rate match FIFO
This option enables bypassing of the rate match Low-latency
(Synchronous) PCI
FIFO in the receiver data path (Low-latency
Express (PIPE) Mode in
[Synchronous] PCI Express [PIPE] mode).
the Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Enable run-length violation
checking with a run length of
This option activates the run length violation
Word Aligner section in the
circuit. You can program the run length at which Arria GX Transceiver
Architecture chapter in
the circuit triggers the rx_rlv signal.
volume 2 of the Arria GX
Device Handbook
Enable fast recovery mode
This option creates the NFTS fast recovery IP
required to meet the PCI Express (PIPE)
specification in the PLD logic array.
NFTS Fast Recovery IP
(NFRI) section in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Create rx_syncstatus output Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
port for pattern detector and
volume 2 of the Arria GX Device Handbook for
word aligner
information about this port.
Word Aligner section under
PCI Express (PIPE) Mode
in the Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
information about this port.
Word Aligner section under
PCI Express (PIPE) Mode
in the Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Create rx_ctrldetect output Refer to the Arria GX Transceiver Protocol
port to indicate 8B/10B decoder Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
has detected a control code
information about this port.
8B/10B Decoder section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
Create rx_patterndetect
output port to indicate pattern
detected
Altera Corporation
May 2008
3–41
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–13. MegaWizard Plug-In Manager Options (Page 8 for PCI Express [PIPE] Mode) (Part 2 of 2)
ALT2GXB Setting
Description
Reference
Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
information about this port.
PCI Express (PIPE) Mode
section in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
Refer to the Arria GX Transceiver Protocol
Create tx_forceelecidle
input port to force the transmitter Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
to send Electrical Idle signals
information about this port.
PCI Express (PIPE) Mode
section in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
Create
PCI Express (PIPE) Mode
section in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
Create tx_detectrxloop
input port as receiver detect or
loopback enable, depending on
the power state
tx_forcedispcompliance
input port to force negative
running disparity
Create tx_invpolarity to
allow Transmitter polarity
inversion
Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook 2
for information about this port.
8B/10B Encoder section in
This optional port allows you to dynamically
reverse the polarity of the data to be transmitted the Arria GX Transceiver
Architecture chapter in
at the transmitter PCS-PMA interface.
volume 2 of the Arria GX
Device Handbook\
3–42
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
PCI Express (PIPE) Mode
Figure 3–18 shows page 9 of the ALT2GXB MegaWizard Plug-In Manager
for PCI Express (PIPE) mode. If the Enforce default settings for this
protocol option is selected, this page does not appear in the MegaWizard
Plug-In Manager.
Figure 3–18. MegaWizard Plug-In Manager - ALT2GXB (PCI Express [PIPE] 2)
Altera Corporation
May 2008
3–43
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–13 describes the available options on page 9 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–14. MegaWizard Plug-In Manager Options (Page 9 for PCI Express [PIPE] Mode)
ALT2GXB Setting
Create pipestatus output
port for PIPE interface status
signal
Description
Reference
Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
information about this port.
Receiver Status section in
the Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Create pipedatavalid output Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
port to indicate valid data from
volume 2 of the Arria GX Device Handbook for
the receiver
information about this port.
PCI Express (PIPE) Mode
section Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
Create pipeelecidle output
port for Electrical Idle detect
status signal
Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
information about this port.
PCI Express (PIPE) Mode
section in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
Create pipephydonestatus
output port to indicate PIPE
completed power state
transitions
Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
information about this port.
PCI Express (PIPE) Mode
section in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
Create
Refer to the Arria GX Transceiver Protocol
PCI Express (PIPE) Mode
section in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
pipe8b/10binvpolarity to Support and Additional Features chapter in
enable polarity inversion in PIPE volume 2 of the Arria GX Device Handbook for
information about this port.
Create powerdn input port for
PIPE powerdown directive
Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
information about this port.
3–44
Arria GX Device Handbook, Volume 2
PCI Express (PIPE) Mode
section in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
Altera Corporation
May 2008
PCI Express (PIPE) Mode
Figure 3–19 shows page 10 of the MegaWizard Plug-In Manager for the
PCI Express (PIPE) protocol selection. The Generate simulation model
option creates a behavioral model (.vo or .vho) of the transceiver instance
for third-party simulators. The Generate a netlist for synthesis area and
timing estimation option creates a netlist file (.syn) for third-party
synthesis tools.
Figure 3–19. MegaWizard Plug-In Manager - ALT2GXB (EDA)
Altera Corporation
May 2008
3–45
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–20 shows page 11 (the last page) of the MegaWizard Plug-In
Manager for the PCI Express (PIPE) protocol set up. You can select
optional files on this page. After you make your selections, click Finish to
generate the files.
Figure 3–20. MegaWizard Plug-In Manager - ALT2GXB (Summary)
XAUI Mode
This section provides descriptions of the options available on the
individual pages of the ALT2GXB MegaWizard Plug-In Manager for
XAUI mode. The MegaWizard Plug-In Manager provides a warning if
any of the settings you choose are illegal.
1
3–46
Arria GX Device Handbook, Volume 2
The word aligner and rate matcher operations and patterns are
pre-configured for XAUI mode and cannot be altered.
Altera Corporation
May 2008
XAUI Mode
Figure 3–21 shows page 3 of the ALT2GXB MegaWizard Plug-In Manager
for XAUI mode.
Figure 3–21. MegaWizard Plug-In Manager - ALT2GXB (General)
Table 3–15 describes the available options on page 3 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–15. MegaWizard Plug-In Manager Options (Page 3 for XAUI Mode) (Part 1 of 2)
ALT2GXB Setting
Description
Reference
Which protocol will you be
using?
Determines the specific protocol or modes under
which the transceiver operates. For XAUI mode you
must select the XAUI.
—
Which subprotocol will you
be using?
Not applicable to XAUI mode.
—
Altera Corporation
May 2008
3–47
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–15. MegaWizard Plug-In Manager Options (Page 3 for XAUI Mode) (Part 2 of 2)
ALT2GXB Setting
Description
Reference
Selecting this option skips the XAUI screen of the
XAUI MegaWizard Plug-In Manager. The XAUI
screen allows you to select the XAUI-specific ports
for your design. If you select this option, all
XAUI-specific ports are used.
—
What is the operation mode? Only receiver and transmitter (full duplex) is allowed
in the XAUI protocol. Receiver only and transmitter
only modes are not allowed.
—
What is the number of
channels?
—
Enforce default settings for
this protocol
This selects how many duplicate channels this
ALT2GXB instance contains. In XAUI mode, the
number of channels increments by 4.
What is the deserializer block XAUI mode only operates in a single-width mode.
width?
—
What is the channel width?
Byte Serializer and Byte
This option determines the transceiver-to-PLD
interface width. Only 16-bit channel width is allowed Deserializer sections in the
Arria GX Transceiver
in XAUI mode.
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What would you like to base
the setting on?
This option is not available in XAUI mode.
—
What is the data rate?
The data rate is fixed at 3.125 Gbps for the XAUI
protocol.
—
What is the input clock
frequency?
Determines the input reference clock frequency for
the transceiver. The Quartus II software
automatically selects the input reference clock
frequency based on the entered data rate.
—
What is the data rate division This option is not available in XAUI mode.
factor?
3–48
Arria GX Device Handbook, Volume 2
—
Altera Corporation
May 2008
XAUI Mode
Figure 3–22 shows page 4 of the ALT2GXB MegaWizard Plug-In Manager
for XAUI mode.
Figure 3–22. MegaWizard Plug-In Manager - ALT2GXB (PLL/Ports)
Altera Corporation
May 2008
3–49
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–16 describes the available options on page 4 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–16. MegaWizard Plug-In Manager Options (Page 4 for XAUI Mode) (Part 1 of 2)
ALT2GXB Setting
Description
Reference
Train Receiver PLL clock from
PLL inclk
If you turn this option on, your design uses the
input reference clock to the transmitter PLL to train
the receiver PLL. This reduces the need to supply
a separate receiver PLL reference clock.
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
What is the GXB Transmitter
PLL bandwidth mode?
In XAUI mode, only high bandwidth is supported
for the transmitter PLL.
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
What is the Receiver PLL
bandwidth mode?
In XAUI mode, only medium bandwidth is
supported for the receiver PLL and VCO.
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
This option determines the PPM difference that
What is the acceptable PPM
threshold between the Receiver affects the automatic receiver CRU switchover
PLL VCO and the CRU clock? between lock-to-data and lock-to-reference.
(There are additional factors that affect CRU’s
transition.)
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create gxb_powerdown port This signal can be used to reset and power down
all circuits in the transceiver block. It does not
to power down the Quad
power down the REFCLK buffers and reference
clock lines.
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
This signal can be used to enable Arria GX
transceiver blocks. If instantiated, this port must be
tied to the dedicated gigabit transceiver block
enable input pin.
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create gxb_enable port to
enable the Quad
Receiver analog reset port.
Create rx_analogreset
port for the analog portion of the
receiver
3–50
Arria GX Device Handbook, Volume 2
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Altera Corporation
May 2008
XAUI Mode
Table 3–16. MegaWizard Plug-In Manager Options (Page 4 for XAUI Mode) (Part 2 of 2)
ALT2GXB Setting
Description
Reference
Create rx_digitalreset
port for the digital portion of the
receiver
Receiver digital reset port. Resets the PCS portion
of the receiver. Altera recommends using this port
along with logic to implement the recommended
reset sequence.
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create tx_digitalreset
port for the digital portion of the
transmitter
Transmitter digital reset port. Resets the PCS
portion of the transmitter. Altera recommends
using this port along with logic to implement the
recommended reset sequence.
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create pll_locked port to
indicate PLL is in lock with the
reference input clock
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
Clock Multiplier Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create rx_locktorefclk
port to lock the RX PLL to the
reference clock
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create rx_locktodata port
to lock the RX PLL to the
received data
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create rx_pll_locked port Refer to the Arria GX Transceiver Architecture
to indicate RX PLL is in lock with chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
the reference clock
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create rx_freqlocked port Refer to the Arria GX Transceiver Architecture
to indicate RX PLL is in lock with chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
the received data
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Altera Corporation
May 2008
3–51
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–22 shows page 5 of the ALT2GXB MegaWizard Plug-In Manager
for XAUI mode.
Figure 3–23. MegaWizard Plug-In Manager - ALT2GXB (Ports/Cal Blk)
3–52
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
XAUI Mode
Table 3–17 describes the available options on page 5 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–17. MegaWizard Plug-In Manager Options (Page 5 for XAUI Mode) (Part 1 of 2)
ALT2GXB Setting
Description
Reference
Refer to the Arria GX Transceiver Architecture
Create rx_signaldetect
port to indicate data input signal chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
detection
Create
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
This optional output port indicates Receiver Phase Receiver Phase
debug_rx_phase_comp_fi Compensation FIFO overflow/under run condition. Compensation FIFO
Note that no PPM difference is allowed between section in the Arria GX
fo_error output port
Create
FIFO read and write clocks. Use this port for
debug purpose only.
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
This optional output port indicates Transmitter
Transmitter Phase
Compensation FIFO
debug_tx_phase_comp_fi Phase Compensation FIFO overflow/under run
condition. Note that no PPM difference is allowed section in the Arria GX
fo_error output port
between FIFO read and write clocks. Use this port Transceiver Architecture
chapter in volume 2 of the
for debug purposes only.
Arria GX Device
Handbook.
Transceiver Clocking
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create rx_coreclk port to
connect to the read clock of the
RX phase compensation FIFO
This optional input port allows you to clock the
read side of the Receiver Phase Compensation
FIFO with a non-transceiver PLD clock.
Create tx_coreclk port to
connect to the write clock of the
TX phase compensation FIFO
Transmitter Phase
This optional input port allows you to clock the
write side of the Transmitter Phase Compensation Compensation FIFO
section in the Arria GX
FIFO with a non-transceiver PLD clock.
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Altera Corporation
May 2008
3–53
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–17. MegaWizard Plug-In Manager Options (Page 5 for XAUI Mode) (Part 2 of 2)
ALT2GXB Setting
Use calibration block
Description
Reference
This option allows you to select which instance of
the ALT2GXB megafunction instantiates the
calibration block. Only one instance of the
ALT2GXB megafunction is required to instantiate
the calibration block.
Calibration Blocks
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create cal_blk_powerdown Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
to power down the calibration
Handbook. for information about this port.
block
3–54
Arria GX Device Handbook, Volume 2
Calibration Blocks
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Altera Corporation
May 2008
XAUI Mode
Figure 3–24 shows page 6 of the ALT2GXB MegaWizard Plug-In Manager
for XAUI mode.
Figure 3–24. MegaWizard Plug-In Manager - ALT2GXB (RX Analog)
Altera Corporation
May 2008
3–55
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–18 describes the available options on page 6 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–18. MegaWizard Plug-In Manager Options (Page 6 for XAUI Mode)
ALT2GXB Setting
Description
Reference
Enable static equalizer
control
This option enables the 0–4 setting options for
manual equalizer control.
What is the Receiver
Common Mode Voltage (RX
VCM)?
Receiver Buffer section in
The receiver common mode voltage is
programmable. The selections available are 0.85 V the Arria GX Transceiver
Architecture chapter in
or 1.2 V.
volume 2 of the Arria GX
Device Handbook.
Force signal detection
This option is available only in PCI Express (PIPE)
mode.
Receiver Buffer Section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the signal detect and This option is available only in PCI Express (PIPE)
signal loss threshold?
mode.
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Use external receiver
termination
This option is available if you use an external
termination resistor instead of the on-chip
termination OCT. If checked, this option turns off the
receiver OCT.
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the Receiver
termination resistance?
This option selects the receiver termination value.
In Arria GX devices, the receiver termination value
is fixed at 100 Ω.
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
3–56
Arria GX Device Handbook, Volume 2
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Altera Corporation
May 2008
XAUI Mode
Figure 3–25 shows page 7 of the ALT2GXB MegaWizard Plug-In Manager
for XAUI mode.
Figure 3–25. MegaWizard Plug-In Manager - ALT2GXB (TX Analog)
Altera Corporation
May 2008
3–57
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–19 describes the available options on page 7 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–19. MegaWizard Plug-In Manager Options (Page 7 for XAUI Mode)
ALT2GXB Setting
Description
Reference
This setting is for information only and is used
to calculate the VO D from the buffer power
supply (VC C H ) and the transmitter termination
to derive the proper VO D range. In XAUI mode,
this option is fixed at 1.5 V
Transmitter Buffer section
in the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the Transmitter Common The transmitter common mode voltage setting
Mode Voltage (VCM)?
is selectable between 0.6 V and 0.7 V.
Transmitter Buffer section
in the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Use external Transmitter
termination
This option is available if you use an external
termination resistor instead of the on-chip
termination OCT. Checking this option turns off
the transmitter OCT.
Transmitter Buffer section
in the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Select the Transmitter
termination resistance
This option selects the transmitter termination Transmitter Buffer section
value. This option is also used in the calculation in the Arria GX Transceiver
of the available VOD.
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the Voltage Output
Differential (VOD) control
setting?
This option selects the VO D of the transmitter
buffer. The differential output voltage is
programmable between 400 mV and 1200 mV
in steps of 200 mV. The available VO D settings
change based on VC C H .
Transmitter Buffer section
in the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Pre-emphasis pre-tap setting (%
of VOD)
This option is not available in Arria GX devices
and is fixed at 0.
Transmitter Buffer section
in the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Pre-emphasis first post-tap
setting (% of VOD)
This option sets the amount of pre-emphasis on Transmitter Buffer section
in the Arria GX Transceiver
the transmitter buffer using first post-tap. The
Architecture chapter in
options available are 0, 1, 2, 3, 4, and 5.
volume 2 of the Arria GX
Device Handbook.
Pre-emphasis second post-tap
setting (% of VOD)
This option is not available in Arria GX devices
and is fixed at 0.
What is the Transmitter Buffer
Power (VCCH)?
3–58
Arria GX Device Handbook, Volume 2
—
Altera Corporation
May 2008
XAUI Mode
Figure 3–26 shows page 8 of the ALT2GXB MegaWizard Plug-In Manager
for XAUI mode.
Figure 3–26. MegaWizard Plug-In Manager - ALT2GXB (Loopback)
Altera Corporation
May 2008
3–59
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–20 describes the available options on page 8 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–20. MegaWizard Plug-In Manager Options (Page 8 for XAUI Mode)
ALT2GXB Setting
Description
Reference
Which loopback option would
you like?
There are two option available in XAUI mode:
no loopback and serial loopback.
● No loopback - this is the default mode.
● Serial loopback - if you select serial
loopback, the rx_seriallpbken port is
available to control the serial loopback
feature dynamically. A 1'b1 enables serial
loopback and a 1'b0 disables loopback on a
channel-by-channel basis. Altera
recommends controlling all four channels
simultaneously. A digital reset must be
asserted for the transceiver.
Loopback Modes section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
Which reverse loopback option
would you like?
This option is not available in XAUI mode.
Loopback Modes section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
3–60
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
XAUI Mode
Figure 3–27 shows page 9 of the ALT2GXB MegaWizard Plug-In Manager
for XAUI mode. If the Enforce default settings for this protocol option is
selected, this page does not appear in the MegaWizard Plug-In Manager.
Figure 3–27. MegaWizard Plug-In Manager - ALT2GXB (XAUI)
Altera Corporation
May 2008
3–61
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–21 describes the available options on page 9 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–21. MegaWizard Plug-In Manager Options (Page 9 for XAUI Mode)
ALT2GXB Setting
Enable run-length violation
checking with a run length of
Description
Reference
Word Aligner section in the
This option activates the run-length violation
circuit. You can program the run length at which Arria GX Transceiver
Architecture chapter in
the circuit triggers the rx_rlv signal.
volume 2 of the Arria GX
Device Handbook.
Create rx_syncstatus output Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
port for pattern detector and
Handbook for information about this port.
word aligner
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create rx_patterndetect
port to indicate pattern detected
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create rx_invpolarity to
enable word aligner polarity
inversion
This optional port allows you to dynamically
reverse the polarity of the received data at the
input of the word aligner.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create rx_ctrldetect port
to indicate 8B/10B decoder has
detected a control code
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
8B/10B Decoder section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create rx_errdetect port to
indicate 8B/10B decoder has
detected an error code
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
8B/10B Decoder section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create rx_disperr port to
indicate 8B/10B decoder has
detected a disparity error
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
8B/10B Decoder section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create tx_invpolarity to
allow Transmitter polarity
inversion
8B/10B Encoder section in
This optional port allows you to dynamically
reverse the polarity of the data to be transmitted the Arria GX Transceiver
Architecture chapter in
at the transmitter PCS-PMA interface.
volume 2 of the Arria GX
Device Handbook.
3–62
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
XAUI Mode
Figure 3–28 shows page 10 of the MegaWizard Plug-In Manager for the
XAUI protocol selection. The Generate simulation model option creates
a behavioral model (.vo or .vho) of the transceiver instance for third-party
simulators. The Generate Netlist option generates a netlist for the third
party EDA synthesis tool to be able to estimate timing and resource
utilization for the ALT2GXB instance.
Figure 3–28. MegaWizard Plug-In Manager - ALT2GXB (EDA)
Altera Corporation
May 2008
3–63
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–29 shows page 11 (the last page) of the MegaWizard Plug-In
Manager for the XAUI protocol set up. You can select optional files on this
page. After you make your selections, click Finish to generate the files.
Figure 3–29. MegaWizard Plug-In Manager - ALT2GXB (Summary)
GIGE Mode
This section provides descriptions of the options available on the
individual pages of the ALT2GXB MegaWizard Plug-In Manager for
GIGE mode. The MegaWizard Plug-In Manager provides a warning if
any of the settings you choose are illegal.
3–64
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
GIGE Mode
Figure 3–30 shows page 3 of the ALT2GXB MegaWizard Plug-In Manager
for GIGE mode.
Figure 3–30. MegaWizard Plug-In Manager - ALT2GXB (General)
Altera Corporation
May 2008
3–65
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–22 describes the available options on page 3 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–22. MegaWizard Plug-In Manager Options (Page 3 for GIGE Mode) (Part 1 of 2)
ALT2GXB Setting
Which protocol will you be
using?
Which subprotocol will you
be using?
Description
Reference
Determines the specific protocol or modes under
which the transceiver operates. For GIGE mode,
you must select the GIGE.
—
The options available here are:
None: Select this option for GIGE mode, when
UNH-IOL Compliance is not required.
● GIGE-Enhanced: Select this option when your
system implementation has Auto-Negotiation
phase or if either /K28.1/, /K28.7/ code group is
used in the synchronization ordered set /K/D/.
—
●
Selecting the GIGE-Enhanced mode enables
7-bit word alignment mode and Rate matcher
insertion/deletion of C1/C2 configuration
ordered sets as required by the Auto negotiation
test suite used for UNH-IOL compliance. Three
additional output ports: rx_runningdisp,
rx_rmfifodatainserted and
rx_rmfifodatadeleted are also enabled
automatically when this option is selected.
Enforce default settings for
this protocol
Selecting this option skips the GIGE screen of the
GIGE MegaWizard Plug-In Manager. The GIGE
screen allows you to select the GIGE-specific ports
for your design. If you select this option, all
GIGE-specific ports are used.
—
What is the operation mode? The transmitter only and receiver and transmitter
(full duplex) modes are allowed in GIGE protocol.
The receiver only mode is not available.
—
What is the number of
channels?
—
This selects how many duplicate channels this
ALT2GXB instance contains. In GIGE mode, the
number of channels increments by 1.
What is the deserializer block This option is unavailable in GIGE mode.
width?
What is the channel width?
This option determines the PLD-transceiver
interface width. Only 8-bit interface width is
supported.
What would you like to base
the setting on?
This option is unavailable because the data rate is
fixed at 1250 Mbps for GIGE mode.
3–66
Arria GX Device Handbook, Volume 2
—
Byte Serializer and Byte
Deserializer sections in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
—
Altera Corporation
May 2008
GIGE Mode
Table 3–22. MegaWizard Plug-In Manager Options (Page 3 for GIGE Mode) (Part 2 of 2)
ALT2GXB Setting
Description
Reference
What is the data rate?
This option is unavailable because the data rate is
fixed at 1250 Mbps for GIGE mode.
—
What is the input clock
frequency?
Determines the input reference clock frequency for
the transceiver. In GIGE mode, input reference
clock frequencies of 62.5 MHz and 125 MHz are
supported.
GIGE Mode section in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
What is the data rate division This option is unavailable in GIGE mode.
factor?
Altera Corporation
May 2008
—
3–67
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–31 shows page 4 of the ALT2GXB MegaWizard Plug-In Manager
for GIGE mode.
Figure 3–31. MegaWizard Plug-In Manager - ALT2GXB (PLL/Ports)
3–68
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
GIGE Mode
Table 3–23 describes the available options on page 4 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–23. MegaWizard Plug-In Manager Options (Page 4 for GIGE Mode) (Part 1 of 3)
ALT2GXB Setting
Description
Reference
If you select this option, the transmitter input
reference clock (pll_inclk) drives the receiver
PLL input reference clock also.
If you do not select this option, the signal on the
rx_cruclk port drives the receiver PLL input
reference clock.
—
What is the GXB Transmitter
PLL bandwidth mode?
This option is not available in GIGE mode because
the transmitter PLL bandwidth is fixed at high.
—
What is the Receiver PLL
bandwidth mode?
This option is not available in GIGE mode because
the receiver PLL bandwidth is fixed at medium.
—
Train Receiver PLL clock from
PLL_inclk
This option determines the PPM difference that
What is the acceptable PPM
threshold between the Receiver affects the automatic receiver CRU switchover
PLL VCO and the CRU clock? between lock-to-data and lock-to-reference.
(There are additional factors that affect the CRU’s
transition.)
Clock Recovery Unit
(CRU) section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
Create gxb_powerdown port This signal can be used to reset and power down
all circuits in the transceiver block. It does not
to power down the Quad
power down the REFCLK buffers and reference
clock lines.
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
This signal can be used to enable Arria GX
transceiver blocks. If instantiated, this port must be
tied to the dedicated gigabit transceiver block
enable input pin.
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create gxb_enable port to
enable the Quad
Receiver analog reset port.
Create rx_analogreset
port for the analog portion of the
receiver
Altera Corporation
May 2008
Reset Control and Power
Down section in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
3–69
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–23. MegaWizard Plug-In Manager Options (Page 4 for GIGE Mode) (Part 2 of 3)
ALT2GXB Setting
Description
Reference
Create rx_digitalreset
port for the digital portion of the
receiver
Receiver digital reset port. Resets the PCS logic of Reset Control and Power
the receiver. Altera recommends using this port to Down section in the
Arria GX Transceiver
implement the recommended reset sequence.
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
Create tx_digitalreset
port for the digital portion of the
transmitter
Transmitter digital reset port. Resets the PCS logic
of the transmitter. Altera recommends using this
port to implement the recommended reset
sequence.
Reset Control and Power
Down section in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
Create pll_locked port to
indicate PLL is in lock with the
reference input clock
Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
information about this port.
Reset Control and Power
Down section in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
Create rx_locktorefclk
port to lock the RX PLL to the
reference clock
Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
information about this port.
Clock Recovery Unit
(CRU) section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
Create rx_locktodata port
to lock the RX PLL to the
received data
Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
information about this port.
Clock Recovery Unit
(CRU) section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
Create rx_pll_locked port Refer to the Arria GX Transceiver Protocol
to indicate RX PLL is in lock with Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
the reference clock
information about this port.
Reset Control and Power
Down section in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
3–70
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
GIGE Mode
Table 3–23. MegaWizard Plug-In Manager Options (Page 4 for GIGE Mode) (Part 3 of 3)
ALT2GXB Setting
Description
Reference
Create rx_freqlocked port Refer to the Arria GX Transceiver Protocol
to indicate RX PLL is in lock with Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
the received data
information about this port.
This option is not available in GIGE mode.
Create rx_signaldetect
port to indicate data input signal
detection
Clock Recovery Unit
(CRU) section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
—
This optional output port indicates Receiver Phase
Compensation FIFO overflow/under run condition.
Note that no PPM difference is allowed between
FIFO read and write clocks. Use this port for
debug purposes only.
Receiver Phase
Compensation FIFO
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
This optional output port indicates Transmitter
Phase Compensation FIFO overflow/under run
condition. Note that no PPM difference is allowed
between FIFO read and write clocks. Use this port
for debug purposes only.
Transmitter Phase
Compensation FIFO
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
Create rx_coreclk port to
connect to the read clock of the
RX phase compensation FIFO
This optional input port allows you to clock the
read side of the Receiver Phase Compensation
FIFO with a non-transceiver PLD clock.
PLD-Transceiver
Interface Clocking
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
Create tx_coreclk port to
connect to the write clock of the
TX phase compensation FIFO
PLD-Transceiver
This optional input port allows you to clock the
write side of the Transmitter Phase Compensation Interface Clocking
section in the Arria GX
FIFO with a non-transceiver PLD clock.
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
Create
debug_rx_phase_comp_
fifo_error output port
Create
debug_tx_phase_comp_
fifo_error output port
Altera Corporation
May 2008
3–71
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–31 shows page 5 of the ALT2GXB MegaWizard Plug-In Manager
for GIGE mode.
Figure 3–32. MegaWizard Plug-In Manager - ALT2GXB (Ports/Cal Blk)
3–72
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
GIGE Mode
Table 3–23 describes the available options on page 5 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–24. MegaWizard Plug-In Manager Options (Page 5 for GIGE Mode) (Part 1 of 2)
ALT2GXB Setting
Description
Reference
This option is not available in GIGE mode.
Create rx_signaldetect
port to indicate data input signal
detection
—
This optional output port indicates Receiver Phase
Compensation FIFO overflow/under run condition.
Note that no PPM difference is allowed between
FIFO read and write clocks. Use this port for
debug purposes only.
Receiver Phase
Compensation FIFO
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
This optional output port indicates Transmitter
Phase Compensation FIFO overflow/under run
condition. Note that no PPM difference is allowed
between FIFO read and write clocks. Use this port
for debug purposes only.
Transmitter Phase
Compensation FIFO
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
Create rx_coreclk port to
connect to the read clock of the
RX phase compensation FIFO
This optional input port allows you to clock the
read side of the Receiver Phase Compensation
FIFO with a non-transceiver PLD clock.
PLD-Transceiver
Interface Clocking
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
Create tx_coreclk port to
connect to the write clock of the
TX phase compensation FIFO
PLD-Transceiver
This optional input port allows you to clock the
write side of the Transmitter Phase Compensation Interface Clocking
section in the Arria GX
FIFO with a non-transceiver PLD clock.
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
Create
debug_rx_phase_comp_
fifo_error output port
Create
debug_tx_phase_comp_
fifo_error output port
Altera Corporation
May 2008
3–73
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–24. MegaWizard Plug-In Manager Options (Page 5 for GIGE Mode) (Part 2 of 2)
ALT2GXB Setting
Description
Reference
Use calibration block
This option allows you to select which instance of
the ALT2GXB megafunction instantiates the
calibration block. Only one instance of the
ALT2GXB megafunction is required to instantiate
the calibration block.
Calibration Block section
in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
Create active low
Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
information about this port.
Calibration Block section
in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
cal_blk_powerdown to
power down the calibration
block
3–74
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
GIGE Mode
Figure 3–33 shows page 6 of the ALT2GXB MegaWizard Plug-In Manager
for GIGE mode.
Figure 3–33. MegaWizard Plug-In Manager - ALT2GXB (RX Analog)
Altera Corporation
May 2008
3–75
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–25 describes the available options on page 6 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–25. MegaWizard Plug-In Manager Options (Page 6 for GIGE Mode)
ALT2GXB Setting
Description
Reference
Enable manual equalizer
control
This option enables the 0–4 setting options for
manual equalizer control.
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the equalizer DC
gain?
This enables the DC gain option and the legal
settings are 0, 1, 2, and 3.
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the Receiver
Common Mode Voltage (RX
VCM)?
The receiver common mode voltage is
programmable. The selections available are 0.85 V
and 1.2 V.
Receiver Buffer section
under GIGE Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
Force signal detection
This option is unavailable in GIGE mode and is
always forced selected.
—
What is the signal detect and This option is unavailable in GIGE mode as signal
signal loss threshold?
detection is forced.
—
Use external receiver
termination
This option is available if you use an external
termination resistor instead of the on-chip termination
OCT. If checked, this option turns off the receiver
OCT.
—
What is the Receiver
termination resistance?
In GIGE mode, the only supported receiver
termination resistance is 100 Ω.
3–76
Arria GX Device Handbook, Volume 2
Receiver Buffer section
under GIGE Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
Altera Corporation
May 2008
GIGE Mode
Figure 3–34 shows page 7 of the ALT2GXB MegaWizard Plug-In Manager
for GIGE mode.
Figure 3–34. MegaWizard Plug-In Manager - ALT2GXB (TX Analog)
Altera Corporation
May 2008
3–77
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–26 describes the available options on page 7 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–26. MegaWizard Plug-In Manager Options (Page 7 for GIGE Mode)
ALT2GXB Setting
What is the Transmitter Buffer
Power (VCCH)?
Description
Reference
In GIGE mode, the transmitter buffer power can
be either 1.2 V or 1.5 V.
You must connect the VC C H power pins of a GIGE
transceiver bank to a 1.2 V or 1.5 V power supply.
You must select 1.2 V PCML or 1.5 V PCML I/O
standard for the transmitter data output pins.
Transmitter Buffer section
under GIGE Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
What is the Transmitter Common In GIGE mode, the transmitter common mode
Mode Voltage (VCM)?
voltage is selectable between 0.6 V and 0.7 V.
Transmitter Buffer section
under GIGE Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
—
Use external Transmitter
termination
This option is available if you use an external
termination resistor instead of the on-chip
termination OCT. Checking this option turns off
the transmitter OCT.
Select the Transmitter
termination resistance
In GIGE mode, the only supported receiver
termination resistance is 100 Ω.
Transmitter Buffer section
under GIGE Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
What is the Voltage Output
Differential (VOD) control
setting?
This option selects the VO D of the transmitter
buffer. The differential output voltage is
programmable between 400 mV to 1200 mV in
steps of 200 mV. The available VO D settings
change based on VC C H .
Transmitter Buffer section
under GIGE Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
Pre-emphasis pre-tap setting (%
of VOD)
This option is not available in Arria GX devices
and is fixed at 0.
—
3–78
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
GIGE Mode
Table 3–26. MegaWizard Plug-In Manager Options (Page 7 for GIGE Mode)
ALT2GXB Setting
Description
Reference
Pre-emphasis first post-tap
setting (% of VOD)
This option sets the amount of pre-emphasis on
the transmitter buffer using first post-tap. The
options available are 0, 1, 2, 3, 4, and 5.
Transmitter Buffer section
under GIGE Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
Pre-emphasis second post-tap
setting (% of VOD)
This option is not available in Arria GX devices
and is fixed at 0.
—
Altera Corporation
May 2008
3–79
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–35 shows page 8 of the ALT2GXB MegaWizard Plug-In Manager
for GIGE mode.
Figure 3–35. MegaWizard Plug-In Manager - ALT2GXB (Loopback)
3–80
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
GIGE Mode
Table 3–27 describes the available options on page 8 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–27. MegaWizard Plug-In Manager Options (Page 8 for GIGE Mode)
ALT2GXB Setting
Which loopback option would
you like?
Altera Corporation
May 2008
Description
Reference
No loopback and serial loopback options are
available in GIGE mode.
No loopback is the default mode. If you select
serial loopback, the rx_seriallpbken port is
available to control the serial loopback feature
dynamically. A 1'b1 enables serial loopback and
a 1'b0 disables loopback on a
channel-by-channel basis.
Loopback Modes section
in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
3–81
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–36 shows page 9 of the ALT2GXB MegaWizard Plug-In Manager
for GIGE mode. If the Enforce default settings for this protocol option is
selected, this page does not appear in the MegaWizard Plug-In Manager.
Figure 3–36. MegaWizard Plug-In Manager - ALT2GXB (GIGE)
3–82
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
GIGE Mode
Table 3–28 describes the available options on page 9 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–28. MegaWizard Plug-In Manager Options (Page 9 for GIGE Mode)
ALT2GXB Setting
Enable run-length violation
checking with a run length of
Description
Reference
Word Aligner section in the
This option activates the run-length violation
circuit. You can program the run length at which Arria GX Transceiver
Architecture chapter in
the circuit triggers the rx_rlv signal.
volume 2 of the Arria GX
Device Handbook
Create rx_syncstatus output Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
port for pattern detector and
volume 2 of the Arria GX Device Handbook for
word aligner
information about this port.
Word Aligner section under
GIGE mode in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in volume
2 of the Arria GX Device
Handbook
Create rx_patterndetect
output port to indicate pattern
detected
Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
information about this port.
Word Aligner section under
GIGE Mode in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in volume
2 of the Arria GX Device
Handbook
Create rx_invpolarity to
enable word aligner polarity
inversion
This optional port allows you to dynamically
reverse the polarity of the received data at the
input of the word aligner.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
Create rx_ctrldetect output Refer to the Arria GX Transceiver Architecture
port to indicate 8B/10B decoder chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
has detected a control code
8B/10B Decoder section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
8B/10B Decoder section in
the Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Create rx_errdetect port to
indicate 8B/10B decoder has
detected an error code
Altera Corporation
May 2008
3–83
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–28. MegaWizard Plug-In Manager Options (Page 9 for GIGE Mode)
ALT2GXB Setting
Description
Reference
Create rx_disperr port to
indicate 8B/10B decoder has
detected a disparity error
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
8B/10B Decoder section in
the Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Create tx_invpolarity to
allow Transmitter polarity
inversion
8B/10B Encoder section in
This optional port allows you to dynamically
reverse the polarity of the data to be transmitted the Arria GX Transceiver
Protocol Support and
at the transmitter PCS-PMA interface.
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
3–84
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
GIGE Mode
Figure 3–37 shows page 10 of the MegaWizard Plug-In Manager for the
GIGE protocol selection. The Generate simulation model option creates
a behavioral model (.vo or .vho) of the transceiver instance for third-party
simulators. The Generate a netlist for synthesis area and timing
estimation option creates a netlist file (.syn) for third-party synthesis
tools.
Figure 3–37. MegaWizard Plug-In Manager - ALT2GXB (EDA)
Altera Corporation
May 2008
3–85
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–38 shows page 11 (the last page) of the MegaWizard Plug-In
Manager for the GIGE protocol set up. You can select optional files on this
page. After you make your selections, click Finish to generate the files.
Figure 3–38. MegaWizard Plug-In Manager - ALT2GXB (Summary)
SDI Mode
This section provides descriptions of the options available on the
individual pages of the ALT2GXB MegaWizard Plug-In Manager for SDI
mode. The MegaWizard Plug-In Manager provides a warning if any of
the settings you choose are illegal.
3–86
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
SDI Mode
Figure 3–39 shows page 3 of the ALT2GXB MegaWizard Plug-In Manager
for SDI mode.
Figure 3–39. MegaWizard Plug-In Manager - ALT2GXB (General)
Altera Corporation
May 2008
3–87
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–29 describes the available options on page 3 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–29. MegaWizard Plug-In Manager Options (Page 3 for SDI Mode)
ALT2GXB Setting
Which protocol will you be
using?
Which subprotocol will you
be using?
Enforce default settings for
this protocol
Description
Reference
Determines the specific protocol or modes under
which the transceiver operates. For SDI mode, you
must select the SDI protocol.
—
In SDI mode, the two available subprotocols are:
3G: third-generation (3 Gbps) SDI at 2970 Mbps
or 2967 Mbps
● HD: high-definition SDI at 1485 Mbps or
1483.5 Mbps
—
This option is not available in SDI mode.
—
●
What is the operation mode? The transmitter only, receiver only, and receiver and
transmitter (full duplex) modes are allowed in SDI
protocol.
—
What is the number of
channels?
This selects how many duplicate channels this
ALT2GXB instance contains.
—
What is the deserializer block SDI mode only operates in single-width mode.
width?
Double-width mode is not supported.
—
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the channel width?
This option determines the transceiver-to-PLD
interface width. In SDI mode, 10-bit and 20-bit
channel widths are allowed. In 10-bit configuration,
the byte serializer is not used. In 20-bit
configuration, the byte serializer is used.
What would you like to base
the setting on?
This option not available in SDI mode.
—
What is the data rate?
This field is automatically set based on the
subprotocol (3G or HD) and the input clock
frequency selection.
—
What is the input clock
frequency?
Four input reference clock options are available,
depending on the subprotocol (3G or HD).
● For 3G subprotocol, the available options are:
148.5 MHz and 297 MHz for 2970 Mbps data
rate and 148.35 MHz and 296.7 MHz for
2967 Mbps data rate
● For HD subprotocol, the available option are:
74.25 MHz and 148.5 MHz for 1485 Mbps data
rate and 74.175 MHz and 148.35 MHz for
1483.5 Mbps data rate
—
What is the data rate division This option is not available in SDI Mode.
factor?
3–88
Arria GX Device Handbook, Volume 2
—
Altera Corporation
May 2008
SDI Mode
Figure 3–40 shows page 4 of the ALT2GXB MegaWizard Plug-In Manager
for SDI mode.
Figure 3–40. MegaWizard Plug-In Manager - ALT2GXB (PLL/Ports)
Altera Corporation
May 2008
3–89
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–30 describes the available options on page 4 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–30. MegaWizard Plug-In Manager Options (Page 4 for SDI Mode) (Part 1 of 3)
ALT2GXB Setting
Description
Reference
Train Receiver PLL clock from
PLL inclk
If you turn this option on, your design uses the
input reference clock to the transmitter PLL to train
the receiver PLL. This reduces the need to supply
a separate receiver PLL reference clock.
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
What is the GXB Transmitter
PLL bandwidth mode?
Three available bandwidth options are high,
medium, and low. The default transmitter PLL
bandwidth is high.
Clock Multiplier Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
What is the Receiver PLL
bandwidth mode?
Three available bandwidth options are high,
medium, and low. The default receiver PLL
bandwidth is medium.
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
This option determines the PPM difference that
What is the acceptable PPM
threshold between the Receiver affects the automatic receiver CRU switchover
PLL VCO and the CRU clock? between lock-to-data and lock-to-reference.
(There are additional factors that affect CRU’s
transition.)
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create gxb_powerdown port This signal can be used to reset and power down
all circuits in the transceiver block. It does not
to power down the Quad
power down the REFCLK buffers and reference
clock lines.
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
This signal can be used to enable Arria GX
transceiver blocks. If instantiated, this port must be
tied to the dedicated gigabit transceiver block
enable input pin.
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create gxb_enable port to
enable the Quad
Receiver analog reset port.
Create rx_analogreset
port for the analog portion of the
receiver
3–90
Arria GX Device Handbook, Volume 2
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Altera Corporation
May 2008
SDI Mode
Table 3–30. MegaWizard Plug-In Manager Options (Page 4 for SDI Mode) (Part 2 of 3)
ALT2GXB Setting
Description
Reference
Create rx_digitalreset
port for the digital portion of the
receiver
Receiver digital reset port. Resets the PCS portion
of the receiver. Altera recommends using this port
along with logic to implement the recommended
reset sequence.
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create tx_digitalreset
port for the digital portion of the
receiver
Transmitter digital reset port. Resets the PCS
portion of the transmitter. Altera recommends
using this port along with logic to implement the
recommended reset sequence.
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create pll_locked port to
indicate PLL is in lock with the
reference input clock
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
Clock Multiplier Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create rx_locktorefclk
port to lock the RX PLL to the
reference clock
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create rx_locktodata port
to lock the RX PLL to the
received data
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create rx_pll_locked port Refer to the Arria GX Transceiver Architecture
to indicate RX PLL is in lock with chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
the reference clock
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create rx_freqlocked port Refer to the Arria GX Transceiver Architecture
to indicate RX PLL is in lock with chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
the received data
Clock Recovery Unit
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Altera Corporation
May 2008
3–91
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–30. MegaWizard Plug-In Manager Options (Page 4 for SDI Mode) (Part 3 of 3)
ALT2GXB Setting
Description
Refer to the Arria GX Transceiver Architecture
Create rx_signaldetect
port to indicate data input signal chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
detection
Create
Reference
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
This optional output port indicates Receiver Phase Receiver Phase
debug_rx_phase_comp_fi Compensation FIFO overflow/under run condition. Compensation FIFO
Note that no PPM difference is allowed between section in the Arria GX
fo_error output port
Create
FIFO read and write clocks. Use this port for
debug purposes only.
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
This optional output port indicates Transmitter
Transmitter Phase
Compensation FIFO
debug_tx_phase_comp_fi Phase Compensation FIFO overflow/under run
condition. Note that no PPM difference is allowed section in the Arria GX
fo_error output port
between FIFO read and write clocks. Use this port Transceiver Architecture
chapter in volume 2 of the
for debug purposes only.
Arria GX Device
Handbook.
Transceiver Clocking
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create rx_coreclk port to
connect to the read clock of the
RX phase compensation FIFO
This optional input port allows you to clock the
read side of the Receiver Phase Compensation
FIFO with a non-transceiver PLD clock.
Create tx_coreclk port to
connect to the write clock of the
TX phase compensation FIFO
Transceiver Clocking
This optional input port allows you to clock the
write side of the Transmitter Phase Compensation section in the Arria GX
Transceiver Architecture
FIFO with a non-transceiver PLD clock.
chapter in volume 2 of the
Arria GX Device
Handbook.
3–92
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
SDI Mode
Figure 3–40 shows page 5 of the ALT2GXB MegaWizard Plug-In Manager
for SDI mode.
Figure 3–41. MegaWizard Plug-In Manager - ALT2GXB (Ports/Cal Blk)
Altera Corporation
May 2008
3–93
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–30 describes the available options on page 5 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–31. MegaWizard Plug-In Manager Options (Page 5 for SDI Mode) (Part 1 of 2)
ALT2GXB Setting
Description
Refer to the Arria GX Transceiver Architecture
Create rx_signaldetect
port to indicate data input signal chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
detection
Create
Reference
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
This optional output port indicates Receiver Phase Receiver Phase
debug_rx_phase_comp_fi Compensation FIFO overflow/under run condition. Compensation FIFO
Note that no PPM difference is allowed between section in the Arria GX
fo_error output port
Create
FIFO read and write clocks. Use this port for
debug purposes only.
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
This optional output port indicates Transmitter
Transmitter Phase
Compensation FIFO
debug_tx_phase_comp_fi Phase Compensation FIFO overflow/under run
condition. Note that no PPM difference is allowed section in the Arria GX
fo_error output port
between FIFO read and write clocks. Use this port Transceiver Architecture
chapter in volume 2 of the
for debug purposes only.
Arria GX Device
Handbook.
Transceiver Clocking
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create rx_coreclk port to
connect to the read clock of the
RX phase compensation FIFO
This optional input port allows you to clock the
read side of the Receiver Phase Compensation
FIFO with a non-transceiver PLD clock.
Create tx_coreclk port to
connect to the write clock of the
TX phase compensation FIFO
Transceiver Clocking
This optional input port allows you to clock the
write side of the Transmitter Phase Compensation section in the Arria GX
Transceiver Architecture
FIFO with a non-transceiver PLD clock.
chapter in volume 2 of the
Arria GX Device
Handbook.
3–94
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
SDI Mode
Table 3–31. MegaWizard Plug-In Manager Options (Page 5 for SDI Mode) (Part 2 of 2)
ALT2GXB Setting
Use calibration block
Description
Reference
This option allows you to select which instance of
the ALT2GXB megafunction instantiates the
calibration block. Only one instance of the
ALT2GXB megafunction is required to instantiate
the calibration block.
Calibration Blocks
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Create cal_blk_powerdown Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
to power down the calibration
Handbook for information about this port.
block
Altera Corporation
May 2008
Calibration Blocks
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
3–95
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–42 shows page 6 of the ALT2GXB MegaWizard Plug-In Manager
for SDI mode.
Figure 3–42. MegaWizard Plug-In Manager - ALT2GXB (RX Analog)
3–96
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
SDI Mode
Table 3–32 describes the available options on page 6 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–32. MegaWizard Plug-In Manager Options (Page 6 for SDI Mode)
ALT2GXB Setting
Description
Reference
Enable static equalizer
control
This option enables the 0–4 setting options for
manual equalizer control.
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the equalizer DC
gain?
This enables the DC gain option. The legal settings
are 0, 1, 2, 3.
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the Receiver
Common Mode Voltage (RX
VCM)?
The receiver common mode voltage is
programmable. The selections available are 0.85 V
and 1.2 V.
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Force signal detection
This option is not available in SDI mode.
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the signal detect and This option is not available in SDI mode.
signal loss threshold?
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Use external receiver
termination
This option is available if you want to use an external
termination resistor instead of the on-chip termination
OCT. If checked, this option turns off the receiver
OCT.
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the receiver
termination resistance?
This option selects the receiver termination value.
The receiver termination value is fixed at 100 Ω in
Arria GX devices.
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Altera Corporation
May 2008
3–97
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–43 shows page 7 of the ALT2GXB MegaWizard Plug-In Manager
for SDI mode.
Figure 3–43. MegaWizard Plug-In Manager - ALT2GXB (TX Analog)
3–98
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
SDI Mode
Table 3–33 describes the available options on page 7 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–33. MegaWizard Plug-In Manager Options (Page 7 for SDI Mode)
ALT2GXB Setting
Description
Reference
This setting is for information only and is used to
calculate the VO D from the buffer power supply
(VC C H ) and the transmitter termination to derive
the proper VO D range. In SDI mode, this option is
fixed at 1.5 V.
Transmitter Buffer section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
What is the Transmitter Common The transmitter common mode voltage setting is
Mode Voltage (VCM)?
selectable between 0.6 V and 0.7 V.
Transmitter Buffer section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Use external Transmitter
termination
This option is available if you use an external
termination resistor instead of the on-chip
termination OCT. Checking this option turns off
the transmitter OCT.
Transmitter Buffer section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Select the Transmitter
termination resistance
This option selects the transmitter termination
value. This option is also used in the calculation
of the available VOD.
Transmitter Buffer section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
What is the Voltage Output
Differential (VOD) control
setting?
This option selects the VO D of the transmitter
buffer. The differential output voltage is
programmable between 400 mV and 1200 mV in
steps of 200 mV. The available VO D settings
change based on VC C H .
Transmitter Buffer section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
Pre-emphasis pre-tap setting (%
of VOD)
This option is not available in Arria GX devices
and is fixed at 0.
Pre-emphasis first post-tap
setting (% of VOD)
This option sets the amount of pre-emphasis on
the transmitter buffer using first post-tap. The
options available are 0, 1, 2, 3, 4, and 5.
Pre-emphasis second post-tap
setting (% of VOD)
This option is not available in Arria GX devices
and is fixed at 0.
What is the Transmitter Buffer
Power (VCCH)?
Altera Corporation
May 2008
Transmitter Buffer section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook.
3–99
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–44 shows page 8 of the ALT2GXB MegaWizard Plug-In Manager
for SDI mode.
Figure 3–44. MegaWizard Plug-In Manager - ALT2GXB (Reconfig)
3–100
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
SDI Mode
Table 3–34 describes the available options on page 8 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–34. MegaWizard Plug-In Manager Options (Page 8 for SDI Mode)
Description
Reference
What do you want to be
able to dynamically
reconfigure in the
transceiver?
ALT2GXB Setting
Available options are:
● Analog controls: Dynamically reconfigures the
PMA control settings like Vod, Pre-emphasis,
Equalization, etc.
● Channel Internals: Enables MIF-based
reconfiguration among modes that have different
data paths within the channel but same PLD
interface signals. When this option is enabled,
two mutually exclusive options, Enable Channel
and Transmitter PLL Reconfiguration and
Use alternate reference clock, are available.
Stratix II GX Dynamic
Reconfiguration chapter in
volume 2 of the Stratix II GX
Device Handbook.
What is the starting
channel number?
The range for the dynamic reconfiguration starting
channel number setting is 0—156, in multiples of 4.
It is in multiples of 4 because the dynamic
reconfiguration interface is per transceiver block.
The range of 0—156 is the logical channel address,
based purely on the number of possible ALT2GXB
instances.
Stratix II GX Dynamic
Reconfiguration chapter in
volume 2 of the Stratix II GX
Device Handbook.
Figure 3–45 shows page 9 of the ALT2GXB MegaWizard Plug-In Manager
for SDI mode. This page appears only when the Enable Channel and
Transmitter PLL Reconfiguration option is selected in the Reconfig page
(Page 8).
Altera Corporation
May 2008
3–101
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–45. MegaWizard Plug-In Manager - ALT2GXB (Reconfig Alt PLL)
Table 3–35 describes the available options on page 9 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–35. MegaWizard Plug-In Manager Options (Page 9 for SDI Mode)
ALT2GXB Setting
Use alternate Transmitter
PLL and Receiver PLL
Description
Selecting this option sets up the transmitter
channel to listen to one of the two PLLs in its
transceiver block. The information regarding
which PLL it listens to is stored in the MIF.
3–102
Arria GX Device Handbook, Volume 2
Reference
Stratix II GX Dynamic
Reconfiguration chapter in
volume 2 of the Stratix II GX
Device Handbook.
Altera Corporation
May 2008
SDI Mode
Figure 3–46 shows page 10 of the ALT2GXB MegaWizard Plug-In
Manager for SDI mode. This page appears only when the Enable
Channel and Transmitter PLL Reconfiguration option is selected in the
Reconfig page (Page 8).
Figure 3–46. MegaWizard Plug-In Manager - ALT2GXB (Reconfig Clks 1)
Altera Corporation
May 2008
3–103
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–36 describes the available options on page 10 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–36. MegaWizard Plug-In Manager Options (Page 10 for SDI Mode)
ALT2GXB Setting
Description
Reference
This option allows you to select the logical index for the
PLL that you intend to use with the current configuration.
This option is meaningful only if you select the Use
alternate Transmitter PLL and Receiver PLL option on
the Reconfig Alt PLL page.
Stratix II GX Dynamic
Reconfiguration chapter in
volume 2 of the Stratix II GX
Device Handbook.
How many input clocks? This field allows you to select the number of reference
clock inputs needed to meet your CMU PLL
reconfiguration design goals. A maximum of five input
reference clocks are allowed.
Stratix II GX Dynamic
Reconfiguration chapter in
volume 2 of the Stratix II GX
Device Handbook.
What is the main PLL
logical reference clock
index?
What is the selected
input clock source for
the Transmitter PLL and
Receiver PLL?
If you select more than one input reference clock
sources for the transmitter and/or receiver PLL, this
option allows you to select the clock source for the
current configuration.
If you select the Use alternate Transmitter PLL and
What is the selected
Receiver PLL option, you can select the clock source for
input clock source for
the alternate Transmitter the alternate Transmitter PLL and the Receiver PLL.
PLL and Receiver PLL?
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Stratix II GX
Device Handbook.
Stratix II GX Dynamic
Reconfiguration chapter in
volume 2 of the Stratix II GX
Device Handbook.
What is the reconfig
protocol driven by clock
0?
If you select more than one input reference clock
sources for the transmitter and/or receiver PLL, these
options allow you to select the functional mode for the
respective reference clock source.
Stratix II GX Dynamic
Reconfiguration chapter in
volume 2 of the Stratix II GX
Device Handbook.
What is clock 0 input
frequency?
If you select more than one input reference clock
sources for the transmitter and/or receiver PLL, these
options allow you to select the reference clock
frequencies for each clock source.
Stratix II GX Dynamic
Reconfiguration chapter in
volume 2 of the Stratix II GX
Device Handbook.
Use clock 0 reference
clock divider
If you select more than one input reference clock source
for the transmitter and/or receiver PLL, these options
allow you to instruct the MegaWizard about the REFCLK
pre-divider on input reference clocks.
Stratix II GX Dynamic
Reconfiguration chapter in
volume 2 of the Stratix II GX
Device Handbook.
Figure 3–47 shows page 11 of the ALT2GXB MegaWizard Plug-In
Manager for SDI mode. This page appears only when the Enable
Channel and Transmitter PLL Reconfiguration option is selected in the
Reconfig page (Page 8).
3–104
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
SDI Mode
Figure 3–47. MegaWizard Plug-In Manager - ALT2GXB (Reconfig 2)
Altera Corporation
May 2008
3–105
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–37 describes the available options on page 11 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–37. MegaWizard Plug-In Manager Options (Page 11 for SDI Mode)
ALT2GXB Setting
Description
Reference
How should the receivers
be clocked?
Three options are available:
● Share a single transmitter core clock between
receivers
● Use the respective channel transmitter core clock
● Use the respective channel receiver core clocks
Stratix II GX Dynamic
Reconfiguration chapter in
volume 2 of the Stratix II GX
Device Handbook.
How should the
transmitters be clocked?
Two options are available:
● Share a single transmitter core clock between
transmitters
● Use the respective channel transmitter core clocks
Stratix II GX Dynamic
Reconfiguration chapter in
volume 2 of the Stratix II GX
Device Handbook.
Create
This optional input port allows you to dynamically
reverse the bit order at the output of the receiver word
aligner.
Word Aligner section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Stratix II GX
Device Handbook.
You can select various control and status signals
depending on what protocol(s) you intend to
dynamically reconfigure the transceiver to.
Stratix II GX Dynamic
Reconfiguration chapter in
volume 2 of the Stratix II GX
Device Handbook.
rx_revbitorderwa
input port to use receiver
enable bit reversal
Check a control box to use
the corresponding control
port
3–106
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
SDI Mode
Figure 3–48 shows page 12 of the ALT2GXB MegaWizard Plug-In
Manager for SDI mode.
Figure 3–48. MegaWizard Plug-In Manager - ALT2GXB (Loopback)
Altera Corporation
May 2008
3–107
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–38 describes the available options on page 12 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–38. MegaWizard Plug-In Manager Options (Page 12 for SDI Mode)
ALT2GXB Setting
Description
Reference
Which loopback option would
you like?
There are two options available in SDI mode: no
loopback and serial loopback.
● No loopback - this is the default mode.
● Serial loopback - if you select serial loopback,
the rx_seriallpbken port is available to
control the serial loopback feature
dynamically. A 1'b1 enables serial loopback
and a 1'b0 disables loopback on a
channel-by-channel basis. Altera
recommends controlling all four channels
simultaneously. A digital reset must be
asserted for the transceiver.
Loopback Modes section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Stratix II GX Device
Handbook.
Reverse Loopback option
This option is not available in SDI mode.
Loopback Modes section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Stratix II GX Device
Handbook.
3–108
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
SDI Mode
Figure 3–49 shows page 13 of the ALT2GXB MegaWizard Plug-In
Manager for SDI mode. If the Enforce default settings for this protocol
option is selected, this page does not appear in the MegaWizard.
Figure 3–49. MegaWizard Plug-In Manager - ALT2GXB (SDI 1)
Altera Corporation
May 2008
3–109
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–39 describes the available options on page 13 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–39. MegaWizard Plug-In Manager Options (Page 13 for SDI Mode) (Part 1 of 2)
ALT2GXB Setting
Enable byte ordering block
Description
This option is not available in Arria GX devices.
Enable 8B/10B decoder/encoder This option is force-selected in SDI mode since
8B/10B decoder/encoder is always used.
Reference
—
8B/10 Encoder section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the
Stratix II GX Device
Handbook.
8B/10 Encoder section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the
Stratix II GX Device
Handbook.
Create tx_forcedisp to
enable Force disparity and use
tx_dispval to code up the
incoming word using positive or
negative disparity
This option allows you to force positive or
negative disparity on transmitted data in 8B/10B
configurations.
Enable rate match FIFO
This option is not available in SDI mode since the Rate Matcher section in
rate match FIFO is always bypassed.
the Arria GX Transceiver
Architecture chapter in
volume 2 of the
Stratix II GX Device
Handbook.
Flip Receiver output data bits
This option reverses the bit order of the data at
the receiver-PLD interface at a byte level to
support MSBit-to-LSBit transmission protocols.
The default transmission order is LSBit-to-MSBit.
Flip Transmitter input data bits
This option reverses the bit order of the data bits
at the input of the transmitter at a byte level to
support MSBit-to-LSBit transmission protocols.
The default transmission order is LSBit-to-MSBit.
Enable Transmitter bit reversal
This option inverts (flips) the bit order of the data
bits at the transmitter PCS-PMA interface at a
byte level to support MSBit-to-LSBit transmission
protocols. The default transmission is
LSBit-to-MSBit.
3–110
Arria GX Device Handbook, Volume 2
8B/10B Encoder section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Stratix II GX Device
Handbook.
Altera Corporation
May 2008
SDI Mode
Table 3–39. MegaWizard Plug-In Manager Options (Page 13 for SDI Mode) (Part 2 of 2)
ALT2GXB Setting
Description
Reference
Create rx_invpolarity to
enable word aligner polarity
inversion
This optional port allows you to dynamically
reverse the polarity of the received data at the
input of the word aligner.
Word Aligner section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the
Stratix II GX Device
Handbook.
Create tx_invpolarity to
allow Transmitter polarity
inversion
This optional port allows you to dynamically
reverse the polarity of the data to be transmitted
at the transmitter PCS-PMA interface.
8B/10B Encoder section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Stratix II GX Device
Handbook.
Altera Corporation
May 2008
3–111
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–50 shows page 14 of the ALT2GXB MegaWizard Plug-In
Manager for SDI mode.
Figure 3–50. MegaWizard Plug-In Manager - ALT2GXB (SDI 2)
3–112
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
SDI Mode
Table 3–40 describes the available options on page 14 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–40. MegaWizard Plug-In Manager Options (Page 14 for SDI Mode) (Part 1 of 3)
ALT2GXB Setting
Description
Reference
Use manual word alignment
mode
Word Aligner section in
This option is not available in SDI mode as the
word aligner uses the bit-slip port to alter the byte the Arria GX Transceiver
Architecture chapter in
boundary one bit at a time.
volume 2 of the
Stratix II GX Device
Handbook.
Use manual bitslipping mode
Word Aligner section in
This option sets the word aligner to use the
bit-slip port to alter the byte boundary one bit at a the Arria GX Transceiver
time. This option is force selected in SDI mode. Architecture chapter in
volume 2 of the
Stratix II GX Device
Handbook.
Use the built-in 'synchronization
state machine'
Word Aligner section in
This option is not available in SDI mode as the
word aligner uses the bit-slip port to alter the byte the Arria GX Transceiver
Architecture chapter in
boundary one bit at a time.
volume 2 of the
Stratix II GX Device
Handbook.
Number of bad data words before This option is not available in SDI mode.
loss of synch state
Word Aligner section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the
Stratix II GX Device
Handbook.
Number of consecutive valid
words before synch state is
reached
This option is not available in SDI mode.
Word Aligner section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the
Stratix II GX Device
Handbook.
Number of valid patterns before
synch state is reached
This option is not available in SDI mode.
Word Aligner section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the
Stratix II GX Device
Handbook.
What is the word alignment
pattern length?
This option sets the word alignment length. The
available choices are 7 bit and 10 bit.
Word Aligner section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the
Stratix II GX Device
Handbook.
Altera Corporation
May 2008
3–113
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–40. MegaWizard Plug-In Manager Options (Page 14 for SDI Mode) (Part 2 of 3)
ALT2GXB Setting
Description
Reference
Word Aligner section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the
Stratix II GX Device
Handbook.
What is the word alignment
pattern?
Enter the word alignment pattern here. The
length of the alignment pattern is based on the
word alignment pattern length.
Flip word alignment pattern bits
This option reverses the bit order of the alignment
pattern at a byte level to support MSB-to-LSB
transmission protocols. The default transmission
order is LSB-to-MSB.
Enable run-length violation
checking with a run length of
This option activates the run-length violation
circuit. You can program the run length at which
the circuit triggers the rx_rlv signal.
Word Aligner section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the
Stratix II GX Device
Handbook.
Enable word aligner output
reverse bit ordering
This option statically configures the receiver to
reverse the bit order of the data at the output of
the word aligner.
Word Aligner section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the
Stratix II GX Device
Handbook.
Create rx_syncstatus output Refer to the Stratix II GX Transceiver Architecture Word Aligner section in
Overview chapter in volume 2 of the Stratix II GX the Arria GX Transceiver
port for pattern detector and
Device Handbook for information about this port. Architecture chapter in
word aligner
volume 2 of the
Stratix II GX Device
Handbook.
Create rx_patterndetect
port to indicate pattern detected
Refer to the Stratix II GX Transceiver Architecture Word Aligner section in
Overview chapter in volume 2 of the Stratix II GX the Arria GX Transceiver
Device Handbook for information about this port. Architecture chapter in
volume 2 of the
Stratix II GX Device
Handbook.
Create rx_ctrldetect port
to indicate 8B/10B decoder has
detected a control code
This option is not available in SDI mode.
Create rx_errdetect port to
indicate 8B/10B decoder has
detected an error code
This option is not available in SDI mode.
3–114
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
SDI Mode
Table 3–40. MegaWizard Plug-In Manager Options (Page 14 for SDI Mode) (Part 3 of 3)
ALT2GXB Setting
Description
Reference
Create rx_disperr port to
indicate 8B/10B decoder has
detected a disparity code
This option is not available in SDI mode.
Create rx_revbyteorderwa
to enable receiver symbol swap
This option is not available in SDI mode.
Altera Corporation
May 2008
3–115
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–51 shows page 15 of the MegaWizard Plug-In Manager for the
SDI protocol selection. The Generate simulation model option creates a
behavioral model (.vo or .vho) of the transceiver instance for third-party
simulators. The Generate Netlist option generates a netlist for third party
EDA synthesis tool to be able to estimate timing and resource utilization
for the ALT2GXB instance.
Figure 3–51. MegaWizard Plug-In Manager - ALT2GXB (EDA)
3–116
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Serial RapidIO Mode
Figure 3–52 shows page 16 (the last page) of the MegaWizard Plug-In
Manager for the SDI protocol set up. You can select optional files on this
page. After you make your selections, click Finish to generate the files.
Figure 3–52. MegaWizard Plug-In Manager - ALT2GXB (Summary)
Serial RapidIO
Mode
Altera Corporation
May 2008
This section provides descriptions of the options available on the
individual pages of the ALT2GXB MegaWizard Plug-In Manager for
Serial RapidIO mode. The MegaWizard Plug-In Manager provides a
warning if any of the settings you choose are illegal.
3–117
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–53 shows page 3 of the ALT2GXB MegaWizard Plug-In Manager
in Serial RapidIO mode.
Figure 3–53. MegaWizard Plug-In Manager - ALT2GXB (General)
3–118
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Serial RapidIO Mode
Table 3–41 describes the available options on page 3 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–41. MegaWizard Plug-In Manager Options (Page 3 for Serial RapidIO Mode)
ALT2GXB Setting
Description
Reference
Which protocol will you be
using?
Determines the specific protocol or modes under which
the transceiver operates. For Serial RapidIO mode, you
must select the Serial RapidIO.
—
Which subprotocol will you
be using?
Not applicable to Serial RapidIO mode.
—
Enforce default settings for
this protocol
Not applicable to Serial RapidIO mode.
—
What is the operation mode? The available operation modes are receiver only,
transmitter only, and receiver and transmitter.
—
What is the number of
channels?
This option determines how many duplicate channels
this ALT2GXB instance contains.
—
What is the deserializer
block width?
This option is unavailable in Serial RapidIO mode.
—
What is the channel width?
This option determines the PLD-transceiver interface
width. Only 16-bit interface width is supported.
What would you like to base
the setting on?
This option is unavailable in Serial RapidIO mode.
—
What is the data rate?
In Serial RapidIO mode, data rates of 1250 Mbps,
2500 Mbps, and 3125 Mbps are supported.
—
What is the input clock
frequency?
Determines the input reference clock frequency for the
transceiver. The following input reference clock
frequencies are supported for each data rate option:
● 1250 Mbps: 62.5 MHz, 78.125 MHz, 125 MHz,
156.25MHz, 250 MHz, 312.5 MHz
● 2500 Mbps: 50 MHz, 62.5 MHz, 78.125 MHz,
100 MHz, 125 MHz, 156.25MHz, 250 MHz,
312.5 MHz, 500 Mhz.
● 3125 Mbps: 62.5 MHz, 78.125 MHz, 97.6563 MHz,
125 MHz, 156.25MHz, 195.3125 MHz, 312.5 MHz,
390.625 MHz.
What is the data rate division This option is unavailable in Serial RapidIO mode.
factor?
Altera Corporation
May 2008
Byte Serializer and Byte
Deserializer sections in
the Arria GX
Transceiver
Architecture chapter in
volume 2 of the
Arria GX Device
Handbook
Serial RapidIO Mode
section in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the
Arria GX Device
Handbook
—
3–119
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–54 shows page 4 of the ALT2GXB MegaWizard Plug-In Manager
for Serial RapidIO mode.
Figure 3–54. MegaWizard Plug-In Manager - ALT2GXB (PLL/Ports)
3–120
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Serial RapidIO Mode
Table 3–42 describes the available options on page 4 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–42. MegaWizard Plug-In Manager Options (Page 4 for Serial RapidIO Mode)
ALT2GXB Setting
Description
Reference
Train Receiver PLL clock from
PLL inclk
If you select this option, the transmitter input
reference clock (pll_inclk) drives the receiver
PLL input reference clock also.
If you do not select this option, the signal on the
rx_cruclk port drives the receiver PLL input
reference clock.
—
What is the GXB Transmitter
PLL bandwidth mode?
This option is not available in Serial RapidIO mode
because the transmitter PLL bandwidth is fixed at
high.
—
What is the Receiver PLL
bandwidth mode?
This option is not available in Serial RapidIO mode
because the receiver PLL bandwidth is fixed at
medium.
—
This option determines the PPM difference that
What is the acceptable PPM
threshold between the Receiver affects the automatic receiver CRU switchover
PLL VCO and the CRU clock? between lock-to-data and lock-to-reference.
(There are additional factors that affect the CRU’s
transition.)
Clock Recovery Unit
(CRU) section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
Create gxb_powerdown port This signal can be used to reset and power down
all circuits in the transceiver block. It does not
to power down the Quad
power down the REFCLK buffers and reference
clock lines.
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
This signal can be used to enable Arria GX
transceiver blocks. If instantiated, this port must be
tied to the dedicated gigabit transceiver block
enable input pin.
Reset Control and Power
Down section in the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
Create gxb_enable port to
enable the Quad
Receiver analog reset port.
Create rx_analogreset
port for the analog portion of the
receiver
Altera Corporation
May 2008
Reset Control and Power
Down section in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
3–121
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–42. MegaWizard Plug-In Manager Options (Page 4 for Serial RapidIO Mode)
ALT2GXB Setting
Description
Reference
Create rx_digitalreset
port for the digital portion of the
receiver
Receiver digital reset port. Resets the PCS logic of Reset Control and Power
the receiver. Altera recommends using this port to Down section in the
Arria GX Transceiver
implement the recommended reset sequence.
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
Create tx_digitalreset
port for the digital portion of the
transmitter
Transmitter digital reset port. Resets the PCS logic
of the transmitter. Altera recommends using this
port to implement the recommended reset
sequence.
Reset Control and Power
Down section in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
Create pll_locked port to
indicate PLL is in lock with the
reference input clock
Refer to the Arria GX Transceiver Protocol
Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
information about this port.
Reset Control and Power
Down section in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
Create rx_locktorefclk
port to lock the RX PLL to the
reference clock
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
Clock Recovery Unit
(CRU) section in the Arria
GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
Create rx_locktodata port
to lock the RX PLL to the
received data
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
Clock Recovery Unit
(CRU) section in the Arria
GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
Create rx_pll_locked port Refer to the Arria GX Transceiver Protocol
to indicate RX PLL is in lock with Support and Additional Features chapter in
volume 2 of the Arria GX Device Handbook for
the reference clock
information about this port.
Reset Control and Power
Down section in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device
Handbook
3–122
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Serial RapidIO Mode
Table 3–42. MegaWizard Plug-In Manager Options (Page 4 for Serial RapidIO Mode)
ALT2GXB Setting
Description
Reference
Create rx_freqlocked port Refer to the Arria GX Transceiver Architecture
to indicate RX PLL is in lock with chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
the received data
This option is not available in Serial RapidIO
Create rx_signaldetect
port to indicate data input signal mode.
detection
Clock Recovery Unit
(CRU) section in the Arria
GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
—
This optional output port indicates Receiver Phase
Compensation FIFO overflow/under run condition.
Note that no PPM difference is allowed between
FIFO read and write clocks. Use this port for
debug purposes only.
Receiver Phase
Compensation FIFO
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
This optional output port indicates Transmitter
Phase Compensation FIFO overflow/under run
condition. Note that no PPM difference is allowed
between FIFO read and write clocks. Use this port
for debug purposes only.
Transmitter Phase
Compensation FIFO
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
Create rx_coreclk port to
connect to the read clock of the
RX phase compensation FIFO
This optional input port allows you to clock the
read side of the Receiver Phase Compensation
FIFO with a non-transceiver PLD clock.
PLD-Transceiver
Interface Clocking
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
Create tx_coreclk port to
connect to the write clock of the
TX phase compensation FIFO
PLD-Transceiver
This optional input port allows you to clock the
write side of the Transmitter Phase Compensation Interface Clocking
section in the Arria GX
FIFO with a non-transceiver PLD clock.
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
Create
debug_rx_phase_comp_
fifo_error output port
Create
debug_tx_phase_comp_
fifo_error output port
Altera Corporation
May 2008
3–123
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–54 shows page 5 of the ALT2GXB MegaWizard Plug-In Manager
for Serial RapidIO mode.
Figure 3–55. MegaWizard Plug-In Manager - ALT2GXB (Ports/Cal Blk)
3–124
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Serial RapidIO Mode
Table 3–42 describes the available options on page 5 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–43. MegaWizard Plug-In Manager Options (Page 5 for Serial RapidIO Mode)
ALT2GXB Setting
Description
Reference
This option is not available in Serial RapidIO
Create rx_signaldetect
port to indicate data input signal mode.
detection
—
This optional output port indicates Receiver Phase
Compensation FIFO overflow/under run condition.
Note that no PPM difference is allowed between
FIFO read and write clocks. Use this port for
debug purposes only.
Receiver Phase
Compensation FIFO
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
This optional output port indicates Transmitter
Phase Compensation FIFO overflow/under run
condition. Note that no PPM difference is allowed
between FIFO read and write clocks. Use this port
for debug purposes only.
Transmitter Phase
Compensation FIFO
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
Create rx_coreclk port to
connect to the read clock of the
RX phase compensation FIFO
This optional input port allows you to clock the
read side of the Receiver Phase Compensation
FIFO with a non-transceiver PLD clock.
PLD-Transceiver
Interface Clocking
section in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
Create tx_coreclk port to
connect to the write clock of the
TX phase compensation FIFO
PLD-Transceiver
This optional input port allows you to clock the
write side of the Transmitter Phase Compensation Interface Clocking
section in the Arria GX
FIFO with a non-transceiver PLD clock.
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
Create
debug_rx_phase_comp_
fifo_error output port
Create
debug_tx_phase_comp_
fifo_error output port
Altera Corporation
May 2008
3–125
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–43. MegaWizard Plug-In Manager Options (Page 5 for Serial RapidIO Mode)
ALT2GXB Setting
Description
Reference
Use calibration block
This option allows you to select which instance of
the ALT2GXB megafunction instantiates the
calibration block. Only one instance of the
ALT2GXB megafunction is required to instantiate
the calibration block.
Calibration Block section
in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
Create active low
Refer to the Arria GX Transceiver Protocol Support
and Additional Features chapter in volume 2 of the
Arria GX Device Handbook, for information about
this port.
Calibration Block section
in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
cal_blk_powerdown to
power down the calibration
block
3–126
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Serial RapidIO Mode
Figure 3–56 shows page 6 of the ALT2GXB MegaWizard Plug-In Manager
for Serial RapidIO mode.
Figure 3–56. MegaWizard Plug-In Manager - ALT2GXB (RX Analog)
Altera Corporation
May 2008
3–127
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–44 describes the available options on page 6 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–44. MegaWizard Plug-In Manager Options (Page 6 for Serial RapidIO Mode)
ALT2GXB Setting
Description
Reference
Enable manual equalizer
control
This option enables the 0–4 setting options for
manual equalizer control.
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the equalizer DC
gain?
This enables the DC gain option and the legal
settings are 0, 1, 2, and 3.
Receiver Buffer section in
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook.
What is the Receiver
Common Mode Voltage
(RX VCM)?
The receiver common mode voltage is
programmable, and the selections available are 0.85
V and 1.2 V.
Receiver Buffer section
under Serial RapidIO
Mode in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
Force signal detection
This option is not available in Serial RapidIO mode
and is always forced selected.
—
What is the signal detect and This option is not available in Serial RapidIO mode as
signal loss threshold?
signal detection is forced.
—
Use external receiver
termination
This option is available if you use an external
termination resistor instead of the on-chip termination
OCT. If checked, this option turns off the receiver
OCT.
—
What is the receiver
termination resistance?
In Serial RapidIO mode, the only supported receiver
termination resistance is 100 Ω.
Receiver Buffer section
under Serial RapidIO
Mode in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
3–128
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Serial RapidIO Mode
Figure 3–57 shows page 7 of the ALT2GXB MegaWizard Plug-In Manager
for Serial RapidIO mode.
Figure 3–57. MegaWizard Plug-In Manager - ALT2GXB (TX Analog)
Altera Corporation
May 2008
3–129
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–45 describes the available options on page 7 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–45. MegaWizard Plug-In Manager Options (Page 7 for Serial RapidIO Mode)
ALT2GXB Setting
What is the Transmitter Buffer
Power (VCCH)?
Description
Reference
This setting is for information only and is used
to calculate the VO D from the buffer power
supply (VC C H ) and the transmitter termination
to derive the proper VO D range. In serial
RapidIO mode, this option is fixed at 1.5 V
Transmitter Buffer section
under Serial RapidIO Mode
in the Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
What is the Transmitter Common In Serial RapidIO mode, the transmitter
Mode Voltage (VCM)?
common mode voltage is selectable between
0.6 V and 0.7 V.
Transmitter Buffer section
under Serial RapidIO mode
in the Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
—
Use external Transmitter
termination
This option is available if you want to use an
external termination resistor instead of the
on-chip termination OCT. Checking this option
turns off the transmitter OCT.
Select the Transmitter
termination resistance
In Serial RapidIO mode, the only supported
receiver termination resistance is 100 Ω.
Transmitter Buffer section
under Serial RapidIO mode
in the Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
What is the Voltage Output
Differential (VOD) control
setting?
This option selects the VO D of the transmitter
buffer. The differential output voltage is
programmable between 400 mV and 1200 mV
in steps of 200 mV. The available VO D settings
change based on VC C H .
Transmitter Buffer section
under Serial RapidIO Mode
in the Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Pre-emphasis pre-tap setting (%
of VOD)
This option is not available in Arria GX devices
and is fixed at 0.
—
3–130
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Serial RapidIO Mode
Table 3–45. MegaWizard Plug-In Manager Options (Page 7 for Serial RapidIO Mode)
ALT2GXB Setting
Description
Reference
Pre-emphasis first post-tap
setting (% of VOD)
This option sets the amount of pre-emphasis on Transmitter Buffer section
under Serial RapidIO Mode
the transmitter buffer using first post-tap. The
in the Arria GX Transceiver
options available are 0, 1, 2, 3, 4, and 5.
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Pre-emphasis second post-tap
setting (% of VOD)
This option is not available in Arria GX devices
and is fixed at 0.
Altera Corporation
May 2008
—
3–131
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–58 shows page 8 of the ALT2GXB MegaWizard Plug-In Manager
for Serial RapidIO mode.
Figure 3–58. MegaWizard Plug-In Manager - ALT2GXB (Loopback)
3–132
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Serial RapidIO Mode
Table 3–46 describes the available options on page 8 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–46. MegaWizard Plug-In Manager Options (Page 8 for Serial RapidIO Mode)
ALT2GXB Setting
Which loopback option would
you like?
Description
Reference
No loopback and serial loopback options are
available in Serial RapidIO mode.
● No loopback is the default mode.
● If you select serial loopback, the
rx_seriallpbken port is available to
control the serial loopback feature
dynamically. A 1'b1 enables serial loopback
and a 1'b0 disables loopback on a
channel-by-channel basis.
Loopback Modes section
in the Arria GX
Transceiver Protocol
Support and Additional
Features chapter in
volume 2 of the Arria GX
Device Handbook
Figure 3–59 shows page 9 of the ALT2GXB MegaWizard Plug-In Manager
for Serial RapidIO mode.
Altera Corporation
May 2008
3–133
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–59. MegaWizard Plug-In Manager - ALT2GXB (SR I/O 1)
Table 3–47 describes the available options on page 9 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–47. MegaWizard Plug-In Manager Options (Page 9 for Serial RapidIO Mode) (Part 1 of 2)
ALT2GXB Setting
Description
Reference
Enable byte ordering block
This option is not available in Arria GX devices.
—
Enable 8B/10B
decoder/encoder
This option is unavailable in Serial RapidIO mode and
is always forced selected to enable 8B/10B
decoder/encoder.
—
3–134
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Serial RapidIO Mode
Table 3–47. MegaWizard Plug-In Manager Options (Page 9 for Serial RapidIO Mode) (Part 2 of 2)
ALT2GXB Setting
Description
Reference
Create tx_forcedisp to This option is unavailable in Serial RapidIO mode.
enable Force disparity and
use tx_dispval to code
up the incoming word using
positive or negative
disparity
—
Enable rate match FIFO
This option is unavailable in Serial RapidIO mode as
the rate matcher is not supported.
—
Flip Receiver output data
bits
This option reverses the bit order of the data at the
receiver-PLD interface at a byte level.
—
Flip Transmitter input data
bits
This option reverses the bit order of the data bits at the
input of the transmitter at a byte level.
—
Enable Transmitter bit
reversal
This option is unavailable in Serial RapidIO mode.
—
Word Aligner section in
Create rx_invpolarity This optional port allows you to dynamically reverse
the polarity of the received data at the input of the word the Arria GX Transceiver
to enable word aligner
Architecture chapter in
aligner.
polarity inversion
volume 2 of the Arria GX
Device Handbook
Create tx_invpolarity This optional port allows you to dynamically reverse
to allow Transmitter polarity the polarity of the data to be transmitted at the
transmitter PCS-PMA interface.
inversion
Altera Corporation
May 2008
8B/10B Encoder section
in the Arria GX
Transceiver Architecture
chapter in volume 2 of the
Arria GX Device
Handbook
3–135
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–60 shows page 10 of the MegaWizard Plug-In Manager for Serial
RapidIO protocol set up.
Figure 3–60. MegaWizard Plug-In Manager - ALT2GXB (SR I/O 2)
Table 3–48 describes the available options on page 10 of the MegaWizard
Plug-In Manager for your ALT2GXB custom megafunction variation.
Table 3–48. MegaWizard Plug-In Manager Options (Page 10 for Serial RapidIO Mode) (Part 1 of 4)
ALT2GXB Setting
Description
Reference
This option is unavailable in Serial RapidIO mode.
—
Use manual bit slipping mode. This option is unavailable in Serial RapidIO mode.
—
Use manual word alignment
mode
3–136
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Serial RapidIO Mode
Table 3–48. MegaWizard Plug-In Manager Options (Page 10 for Serial RapidIO Mode) (Part 2 of 4)
ALT2GXB Setting
Description
Reference
Use the built-in
'synchronization state
machine'
This option is forced selected in Serial RapidIO
mode.
Word Aligner section under
Serial RapidIO Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Number of bad data words
before loss of synch state
Refer to the Arria GX Transceiver Protocol Support
and Additional Features chapter in volume 2 of the
Arria GX Device Handbook for information about
this port.
Word Aligner section under
Serial RapidIO Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Number of consecutive valid
words before synch state is
reached
Refer to the Arria GX Transceiver Protocol Support
and Additional Features chapter in volume 2 of the
Arria GX Device Handbook for information about
this port.
Word Aligner section under
Serial RapidIO mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Number of valid patterns
Refer to the Arria GX Transceiver Protocol Support
before synch state is reached and Additional Features chapter in volume 2 of the
Arria GX Device Handbook for information about
this port.
Word Aligner section under
Serial RapidIO Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
What is the word alignment
pattern length?
The word alignment pattern length is fixed to 10 in
Serial RapidIO mode.
Word Aligner section under
Serial RapidIO mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
What is the word alignment
pattern?
Enter the 10-bit word alignment pattern here.
Word Aligner section under
Serial RapidIO Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Altera Corporation
May 2008
3–137
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Table 3–48. MegaWizard Plug-In Manager Options (Page 10 for Serial RapidIO Mode) (Part 3 of 4)
ALT2GXB Setting
Description
Reference
Flip word alignment pattern
bits
This option reverses the bit order of the alignment
pattern at a byte level to support MSB-to-LSB
transmission protocols. The default transmission
order is LSB-to-MSB.
—
Enable run-length violation
checking with a run length of
This option activates the run-length violation
circuit. You can program the run length at which
the circuit triggers the rx_rlv signal.
Enable word aligner output
reverse bit ordering
This option is unavailable in Serial RapidIO mode.
—
Create rx_syncstatus
output port for pattern
detector and word aligner
Refer to the Arria GX Transceiver Protocol Support
and Additional Features chapter in volume 2 of the
Arria GX Device Handbook for information about
this port.
Word Aligner section under
Serial RapidIO Mode in the
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Create
Refer to the Arria GX Transceiver Protocol Support Word Aligner section under
Word Aligner section n the
Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
rx_patterndetect output and Additional Features chapter in volume 2 of the Serial RapidIO Mode in the
port to indicate pattern
detected
Arria GX Device Handbook for information about
this port.
Refer to the Arria GX Transceiver Architecture
Create rx_ctrldetect
output port to indicate 8B/10B chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
decoder has detected a
control code
Create rx_errdetect port
to indicate 8B/10B decoder
has detected an error code
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
3–138
Arria GX Device Handbook, Volume 2
Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
8B/10B Decoder section n
the Arria GX Transceiver
Architecture chapter in
volume 2 of the Arria GX
Device Handbook
8B/10B Decoder section in
the Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
Altera Corporation
May 2008
Serial RapidIO Mode
Table 3–48. MegaWizard Plug-In Manager Options (Page 10 for Serial RapidIO Mode) (Part 4 of 4)
ALT2GXB Setting
Description
Reference
Create rx_disperr port to
indicate 8B/10B decoder has
detected a disparity error
Refer to the Arria GX Transceiver Architecture
chapter in volume 2 of the Arria GX Device
Handbook for information about this port.
Create
This option is unavailable in Serial RapidIO mode.
8B/10B Decoder section in
the Arria GX Transceiver
Protocol Support and
Additional Features
chapter in volume 2 of the
Arria GX Device Handbook
—
rx_revbyteorderwa to
enable receiver symbol swap
Figure 3–61 shows page 11 of the MegaWizard Plug-In Manager for the
Serial RapidIO protocol selection. The Generate simulation model
option creates a behavioral model (.vo or .vho) of the transceiver instance
for third-party simulators. The Generate a netlist for synthesis area and
timing estimation option creates a netlist file (.syn) for third-party
synthesis tools.
Altera Corporation
May 2008
3–139
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
Figure 3–61. MegaWizard Plug-In Manager - ALT2GXB (EDA)
3–140
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2008
Referenced Documents
Figure 3–62 shows page 12 (last page) of the MegaWizard Plug-In
Manager for Serial RapidIO protocol set up. You can select optional files
on this page. After you make your selections, click Finish to generate the
files.
Figure 3–62. MegaWizard Plug-In Manager - ALT2GXB (Summary)
Referenced
Documents
This chapter references the following documents:
■
■
■
Altera Corporation
May 2008
Arria GX Architecture chapter in volume 1 of the Arria GX Device
Handbook
Arria GX Transceiver Architecture chapter in volume 2 of the Arria GX
Device Handbook
Arria GX Transceiver Protocol Support and Additional Features chapter
in volume 2 of the Arria GX Device Handbook
3–141
Arria GX Device Handbook, Volume 2
Arria GX ALT2GXB Megafunction User Guide
■
Document
Revision History
Stratix II GX Transceiver Architecture Overview chapter in volume 2 of
the Stratix II GX Device Handbook
Table 3–49 shows the revision history for this chapter.
Table 3–49. Document Revision History
Date and
Document
Version
Changes Made
Summary of Changes
August 2007,
v1.2
Added the “Referenced Documents” section.
—
Minor text edits.
—
June 2007,
v1.1
Added GIGE information.
—
May 2007, v1.0 Initial Release.
3–142
Arria GX Device Handbook, Volume 2
—
Altera Corporation
May 2008
4. Specifications and
Additional Information
AGX52004-1.0
8B/10B Code
This section provides information about the data and control codes for
Arria™ GX devices.
Code Notation
The 8B/10B data and control codes are referred to as Dx.y and Kx.y,
respectively. The 8-bit byte – H G F E D C B A, where H is the most
significant bit (MSB) and A is the significant bit (LSB) – is broken up into
two groups, x and y, where x is the five lower bits (E D C B A) and y is the
three upper bits (H G F). Figure 4–1 shows the designation for 3C hex.
Figure 4–1. Sample Notation for 3C hex
y=1
D28.1 =
(3C hex)
x = 28
0
0
1
1
1
1
0
0
H
G
F
E
D
C
B
A
There are 256 Dx.y and 12 Kx.y valid 8-bit codes. These codes have two
10-bit equivalent codes associated with each 8-bit code. The 10-bit codes
have either a neutral disparity or a non-neutral disparity. With neutral
disparity, two neutral disparity 10-bit codes are associated with an 8-bit
code. With non-neutral disparity 10-bit code, a positive and a negative
disparity code are associated with the 8-bit code.
The positive disparity 10-bit code is associated in the RD– column. The
negative disparity 10-bit code is associated in the RD+ column.
Disparity Calculation
Running disparity is calculated based on the sub-blocks of the 10-bit code.
The 10-bit code is divided into two sub-blocks, a 6-bit sub-block (abcdei)
and a 4-bit sub-block (fghj), as shown in Figure 4–2.
Altera Corporation
May 2007
4–1
8B/10B Code
Figure 4–2. 10-Bit Grouping of 6-bit & 4-Bit Sub-Blocks
10-Bit Code
D28.1 =
(3C hex)
j
h
g
f
i
e
d
c
b
a
0
0
1
1
1
1
1
0
0
0
4-Bit Block
6-Bit Block
The running disparity at the beginning of the 6-bit sub-block is the
running disparity at the end of the previous 10-bit code. The running
disparity of the 4-bit sub-block is the running disparity at the end of the
6-bit sub-block. The running disparity at the end of the 4-bit sub-block is
the running disparity of the 10-bit code (refer to Figure 4–3).
Figure 4–3. Running Disparity Between Sub-Blocks
10-Bit Code
D28.1 =
(3C hex)
j
h
g
f
i
e
d
c
b
a
0
0
1
1
1
1
1
0
0
0
4-Bit Block
6-Bit Block
The running disparity calculation rules are as follows:
■
The current running disparity at the end of a sub-block is positive if
any of the following is true:
●
The sub-block contains more ones than zeros
●
The 6-bit sub-block is 6'b000111
●
The 4-bit sub-block is 4'b0011
■
The current running disparity at the end of a sub-block is negative if
any of the following is true:
●
The sub-block contains more zeros than ones
●
The 6-bit sub-block is 6'b111000
●
The 4-bit sub-block is 4'b1100
If those conditions are not met, the running disparity at the end of the
sub-block is the same as at the beginning of the sub-block.
4–2
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2007
Specifications and Additional Information
Supported Codes
The 8B/10B scheme defines the 12 control codes listed in Table 4–1 for
synchronization, alignment, and general application purposes.
Table 4–1. Supported K Codes
8-Bit Code
K Code
10-Bit Code RD–
10-Bit Code RD+
Octal Value
HGF_EDCBA
abcdei_fghj
K28.0
1C
8'b000_11100
10'b001111_0100
10'b110000_1011
K28.1
3C
8'b001_11100
10'b001111_1001
10'b110000_0110
K28.2
5C
8'b010_11100
10'b001111_0101
10'b110000_1010
K28.3
7C
8'b011_11100
10'b001111_0011
10'b110000_1100
K28.4
9C
8'b100_11100
10'b001111_0010
10'b110000_1101
K28.5 (1)
BC
8'b101_11100
10'b001111_1010
10'b110000_0101
K28.6
DC
8'b110_11100
10'b001111_0110
10'b110000_1001
K28.7
FC
8'b111_11100
10'b001111_1000
10'b110000_0111
K23.7
F7
8'b111_10111
10'b111010_1000
10'b000101_0111
K27.7
FB
8'b111_11011
10'b110110_1000
10'b001001_0111
K29.7
FD
8'b111_11101
10'b101110_1000
10'b010001_0111
K30.7
FE
8'b111_11110
10'b011110_1000
10'b100001_0111
Note to Table 4–1:
(1)
K28.5 is a comma code used for word alignment and indicates an IDLE state.
Table 4–2 shows the valid data code-groups.
Table 4–2. Valid Data Code-Groups (Part 1 of 9)
Octet Bits
Code-Group Name
Current RD–
Current RD+
Octet Value
HGF EDCBA
abcdei fghj
D0.0
00
000 00000
100111 0100
011000 1011
D1.0
01
000 00001
011101 0100
100010 1011
D2.0
02
000 00010
101101 0100
010010 1011
D3.0
03
000 00011
110001 1011
110001 0100
D4.0
04
000 00100
110101 0100
001010 1011
D5.0
05
000 00101
101001 1011
101001 0100
D6.0
06
000 00110
011001 1011
011001 0100
D7.0
07
000 00111
111000 1011
000111 0100
Altera Corporation
May 2007
4–3
Arria GX Device Handbook, Volume 2
8B/10B Code
Table 4–2. Valid Data Code-Groups (Part 2 of 9)
Octet Bits
Code-Group Name
Current RD–
Current RD+
Octet Value
HGF EDCBA
abcdei fghj
D8.0
08
000 01000
111001 0100
000110 1011
D9.0
09
000 01001
100101 1011
100101 0100
D10.0
0A
000 01010
010101 1011
010101 0100
D11.0
0B
000 01011
110100 1011
110100 0100
D12.0
0C
000 01100
001101 1011
001101 0100
D13.0
0D
000 01101
101100 1011
101100 0100
D14.0
0E
000 01110
011100 1011
011100 0100
D15.0
0F
000 01111
010111 0100
101000 1011
D16.0
10
000 10000
011011 0100
100100 1011
D17.0
11
000 10001
100011 1011
100011 0100
D18.0
12
000 10010
010011 1011
010011 0100
D19.0
13
000 10011
110010 1011
110010 0100
D20.0
14
000 10100
001011 1011
001011 0100
D21.0
15
000 10101
101010 1011
101010 0100
D22.0
16
000 10110
011010 1011
011010 0100
D23.0
17
000 10111
111010 0100
000101 1011
D24.0
18
000 11000
110011 0100
001100 1011
D25.0
19
000 11001
100110 1011
100110 0100
D26.0
1A
000 11010
010110 1011
010110 0100
D27.0
1B
000 11011
110110 0100
001001 1011
D28.0
1C
000 11100
001110 1011
001110 0100
D29.0
1D
000 11101
101110 0100
010001 1011
D30.0
1E
000 11110
011110 0100
100001 1011
D31.0
1F
000 11111
101011 0100
010100 1011
D0.1
20
001 00000
100111 1001
011000 1001
D1.1
21
001 00001
011101 1001
100010 1001
D2.1
22
001 00010
101101 1001
010010 1001
D3.1
23
001 00011
110001 1001
110001 1001
D4.1
24
001 00100
110101 1001
001010 1001
D5.1
25
001 00101
101001 1001
101001 1001
D6.1
26
001 00110
011001 1001
011001 1001
D7.1
27
001 00111
111000 1001
000111 1001
D8.1
28
001 01000
111001 1001
000110 1001
4–4
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2007
Specifications and Additional Information
Table 4–2. Valid Data Code-Groups (Part 3 of 9)
Octet Bits
Code-Group Name
Current RD–
Current RD+
Octet Value
HGF EDCBA
abcdei fghj
D9.1
29
001 01001
100101 1001
100101 1001
D10.1
2A
001 01010
010101 1001
010101 1001
D11.1
2B
001 01011
110100 1001
110100 1001
D12.1
2C
001 01100
001101 1001
001101 1001
D13.1
2D
001 01101
101100 1001
101100 1001
D14.1
2E
001 01110
011100 1001
011100 1001
D15.1
2F
001 01111
010111 1001
101000 1001
D16.1
30
001 10000
011011 1001
100100 1001
D17.1
31
001 10001
100011 1001
100011 1001
D18.1
32
001 10010
010011 1001
010011 1001
D19.1
33
001 10011
110010 1001
110010 1001
D20.1
34
001 10100
001011 1001
001011 1001
D21.1
35
001 10101
101010 1001
101010 1001
D22.1
36
001 10110
011010 1001
011010 1001
D23.1
37
001 10111
111010 1001
000101 1001
D24.1
38
001 11000
110011 1001
001100 1001
D25.1
39
001 11001
100110 1001
100110 1001
D26.1
3A
001 11010
010110 1001
010110 1001
D27.1
3B
001 11011
110110 1001
001001 1001
D28.1
3C
001 11100
001110 1001
001110 1001
D29.1
3D
001 11101
101110 1001
010001 1001
D30.1
3E
001 11110
011110 1001
100001 1001
D31.1
3F
001 11111
101011 1001
010100 1001
D0.2
40
010 00000
100111 0101
011000 0101
D1.2
41
010 00001
011101 0101
100010 0101
D2.2
42
010 00010
101101 0101
010010 0101
D3.2
43
010 00011
110001 0101
110001 0101
D4.2
44
010 00100
110101 0101
001010 0101
D5.2
45
010 00101
101001 0101
101001 0101
D6.2
46
010 00110
011001 0101
011001 0101
D7.2
47
010 00111
111000 0101
000111 0101
D8.2
48
010 01000
111001 0101
000110 0101
D9.2
49
010 01001
100101 0101
100101 0101
Altera Corporation
May 2007
4–5
Arria GX Device Handbook, Volume 2
8B/10B Code
Table 4–2. Valid Data Code-Groups (Part 4 of 9)
Octet Bits
Code-Group Name
Current RD–
Current RD+
Octet Value
HGF EDCBA
abcdei fghj
D10.2
4A
010 01010
010101 0101
010101 0101
D11.2
4B
010 01011
110100 0101
110100 0101
D12.2
4C
010 01100
001101 0101
001101 0101
D13.2
4D
010 01101
101100 0101
101100 0101
D14.2
4E
010 01110
011100 0101
011100 0101
D15.2
4F
010 01111
010111 0101
101000 0101
D16.2
50
010 10000
011011 0101
100100 0101
D17.2
51
010 10001
100011 0101
100011 0101
D18.2
52
010 10010
010011 0101
010011 0101
D19.2
53
010 10011
110010 0101
110010 0101
D20.2
54
010 10100
001011 0101
001011 0101
D21.2
55
010 10101
101010 0101
101010 0101
D22.2
56
010 10110
011010 0101
011010 0101
D23.2
57
010 10111
111010 0101
000101 0101
D24.2
58
010 11000
110011 0101
001100 0101
D25.2
59
010 11001
100110 0101
100110 0101
D26.2
5A
010 11010
010110 0101
010110 0101
D27.2
5B
010 11011
110110 0101
001001 0101
D28.2
5C
010 11100
001110 0101
001110 0101
D29.2
5D
010 11101
101110 0101
010001 0101
D30.2
5E
010 11110
011110 0101
100001 0101
D31.2
5F
010 11111
101011 0101
010100 0101
D0.3
60
011 00000
100111 0011
011000 1100
D1.3
61
011 00001
011101 0011
100010 1100
D2.3
62
011 00010
101101 0011
010010 1100
D3.3
63
011 00011
110001 1100
110001 0011
D4.3
64
011 00100
110101 0011
001010 1100
D5.3
65
011 00101
101001 1100
101001 0011
D6.3
66
011 00110
011001 1100
011001 0011
D7.3
67
011 00111
111000 1100
000111 0011
D8.3
68
011 01000
111001 0011
000110 1100
D9.3
69
011 01001
100101 1100
100101 0011
D10.3
6A
011 01010
010101 1100
010101 0011
4–6
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2007
Specifications and Additional Information
Table 4–2. Valid Data Code-Groups (Part 5 of 9)
Octet Bits
Code-Group Name
Current RD–
Current RD+
Octet Value
HGF EDCBA
abcdei fghj
D11.3
6B
011 01011
110100 1100
110100 0011
D12.3
6C
011 01100
001101 1100
001101 0011
D13.3
6D
011 01101
101100 1100
101100 0011
D14.3
6E
011 01110
011100 1100
011100 0011
D15.3
6F
011 01111
010111 0011
101000 1100
D16.3
70
011 10000
011011 0011
100100 1100
D17.3
71
011 10001
100011 1100
100011 0011
D18.3
72
011 10010
010011 1100
010011 0011
D19.3
73
011 10011
110010 1100
110010 0011
D20.3
74
011 10100
001011 1100
001011 0011
D21.3
75
011 10101
101010 1100
101010 0011
D22.3
76
011 10110
011010 1100
011010 0011
D23.3
77
011 10111
111010 0011
000101 1100
D24.3
78
011 11000
110011 0011
001100 1100
D25.3
79
011 11001
100110 1100
100110 0011
D26.3
7A
011 11010
010110 1100
010110 0011
D27.3
7B
011 11011
110110 0011
001001 1100
D28.3
7C
011 11100
001110 1100
001110 0011
D29.3
7D
011 11101
101110 0011
010001 1100
D30.3
7E
011 11110
011110 0011
100001 1100
D31.3
7F
011 11111
101011 0011
010100 1100
D0.4
80
100 00000
100111 0010
011000 1101
D1.4
81
100 00001
011101 0010
100010 1101
D2.4
82
100 00010
101101 0010
010010 1101
D3.4
83
100 00011
110001 1101
110001 0010
D4.4
84
100 00100
110101 0010
001010 1101
D5.4
85
100 00101
101001 1101
101001 0010
D6.4
86
100 00110
011001 1101
011001 0010
D7.4
87
100 00111
111000 1101
000111 0010
D8.4
88
100 01000
111001 0010
000110 1101
D9.4
89
100 01001
100101 1101
100101 0010
D10.4
8A
100 01010
010101 1101
010101 0010
D11.4
8B
100 01011
110100 1101
110100 0010
Altera Corporation
May 2007
4–7
Arria GX Device Handbook, Volume 2
8B/10B Code
Table 4–2. Valid Data Code-Groups (Part 6 of 9)
Octet Bits
Code-Group Name
Current RD–
Current RD+
Octet Value
HGF EDCBA
abcdei fghj
D12.4
8C
100 01100
001101 1101
001101 0010
D13.4
8D
100 01101
101100 1101
101100 0010
D14.4
8E
100 01110
011100 1101
011100 0010
D15.4
8F
100 01111
010111 0010
101000 1101
D16.4
90
100 10000
011011 0010
100100 1101
D17.4
91
100 10001
100011 1101
100011 0010
D18.4
92
100 10010
010011 1101
010011 0010
D19.4
93
100 10011
110010 1101
110010 0010
D20.4
94
100 10100
001011 1101
001011 0010
D21.4
95
100 10101
101010 1101
101010 0010
D22.4
96
100 10110
011010 1101
011010 0010
D23.4
97
100 10111
111010 0010
000101 1101
D24.4
98
100 11000
110011 0010
001100 1101
D25.4
99
100 11001
100110 1101
100110 0010
D26.4
9A
100 11010
010110 1101
010110 0010
D27.4
9B
100 11011
110110 0010
001001 1101
D28.4
9C
100 11100
001110 1101
001110 0010
D29.4
9D
100 11101
101110 0010
010001 1101
D30.4
9E
100 11110
011110 0010
100001 1101
D31.4
9F
100 11111
101011 0010
010100 1101
D0.5
A0
101 00000
100111 1010
011000 1010
D1.5
A1
101 00001
011101 1010
100010 1010
D2.5
A2
101 00010
101101 1010
010010 1010
D3.5
A3
101 00011
110001 1010
110001 1010
D4.5
A4
101 00100
110101 1010
001010 1010
D5.5
A5
101 00101
101001 1010
101001 1010
D6.5
A6
101 00110
011001 1010
011001 1010
D7.5
A7
101 00111
111000 1010
000111 1010
D8.5
A8
101 01000
111001 1010
000110 1010
D9.5
A9
101 01001
100101 1010
100101 1010
D10.5
AA
101 01010
010101 1010
010101 1010
D11.5
AB
101 01011
110100 1010
110100 1010
D12.5
AC
101 01100
001101 1010
001101 1010
4–8
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2007
Specifications and Additional Information
Table 4–2. Valid Data Code-Groups (Part 7 of 9)
Octet Bits
Code-Group Name
Current RD–
Current RD+
Octet Value
HGF EDCBA
abcdei fghj
D13.5
AD
101 01101
101100 1010
101100 1010
D14.5
AE
101 01110
011100 1010
011100 1010
D15.5
AF
101 01111
010111 1010
101000 1010
D16.5
B0
101 10000
011011 1010
100100 1010
D17.5
B1
101 10001
100011 1010
100011 1010
D18.5
B2
101 10010
010011 1010
010011 1010
D19.5
B3
101 10011
110010 1010
110010 1010
D20.5
B4
101 10100
001011 1010
001011 1010
D21.5
B5
101 10101
101010 1010
101010 1010
D22.5
B6
101 10110
011010 1010
011010 1010
D23.5
B7
101 10111
111010 1010
000101 1010
D24.5
B8
101 11000
110011 1010
001100 1010
D25.5
B9
101 11001
100110 1010
100110 1010
D26.5
BA
101 11010
010110 1010
010110 1010
D27.5
BB
101 11011
110110 1010
001001 1010
D28.5
BC
101 11100
001110 1010
001110 1010
D29.5
BD
101 11101
101110 1010
010001 1010
D30.5
BE
101 11110
011110 1010
100001 1010
D31.5
BF
101 11111
101011 1010
010100 1010
D0.6
C0
110 00000
100111 0110
011000 0110
D1.6
C1
110 00001
011101 0110
100010 0110
D2.6
C2
110 00010
101101 0110
010010 0110
D3.6
C3
110 00011
110001 0110
110001 0110
D4.6
C4
110 00100
110101 0110
001010 0110
D5.6
C5
110 00101
101001 0110
101001 0110
D6.6
C6
110 00110
011001 0110
011001 0110
D7.6
C7
110 00111
111000 0110
000111 0110
D8.6
C8
110 01000
111001 0110
000110 0110
D9.6
C9
110 01001
100101 0110
100101 0110
D10.6
CA
110 01010
010101 0110
010101 0110
D11.6
CB
110 01011
110100 0110
110100 0110
D12.6
CC
110 01100
001101 0110
001101 0110
D13.6
CD
110 01101
101100 0110
101100 0110
Altera Corporation
May 2007
4–9
Arria GX Device Handbook, Volume 2
8B/10B Code
Table 4–2. Valid Data Code-Groups (Part 8 of 9)
Octet Bits
Code-Group Name
Current RD–
Current RD+
Octet Value
HGF EDCBA
abcdei fghj
D14.6
CE
110 01110
011100 0110
011100 0110
D15.6
CF
110 01111
010111 0110
101000 0110
D16.6
D0
110 10000
011011 0110
100100 0110
D17.6
D1
110 10001
100011 0110
100011 0110
D18.6
D2
110 10010
010011 0110
010011 0110
D19.6
D3
110 10011
110010 0110
110010 0110
D20.6
D4
110 10100
001011 0110
001011 0110
D21.6
D5
110 10101
101010 0110
101010 0110
D22.6
D6
110 10110
011010 0110
011010 0110
D23.6
D7
110 10111
111010 0110
000101 0110
D24.6
D8
110 11000
110011 0110
001100 0110
D25.6
D9
110 11001
100110 0110
100110 0110
D26.6
DA
110 11010
010110 0110
010110 0110
D27.6
DB
110 11011
110110 0110
001001 0110
D28.6
DC
110 11100
001110 0110
001110 0110
D29.6
DD
110 11101
101110 0110
010001 0110
D30.6
DE
110 11110
011110 0110
100001 0110
D31.6
DF
110 11111
101011 0110
010100 0110
D0.7
E0
111 00000
100111 0001
011000 1110
D1.7
E1
111 00001
011101 0001
100010 1110
D2.7
E2
111 00010
101101 0001
010010 1110
D3.7
E3
111 00011
110001 1110
110001 0001
D4.7
E4
111 00100
110101 0001
001010 1110
D5.7
E5
111 00101
101001 1110
101001 0001
D6.7
E6
111 00110
011001 1110
011001 0001
D7.7
E7
111 00111
111000 1110
000111 0001
D8.7
E8
111 01000
111001 0001
000110 1110
D9.7
E9
111 01001
100101 1110
100101 0001
D10.7
EA
111 01010
010101 1110
010101 0001
D11.7
EB
111 01011
110100 1110
110100 1000
D12.7
EC
111 01100
001101 1110
001101 0001
D13.7
ED
111 01101
101100 1110
101100 1000
D14.7
EE
111 01110
011100 1110
011100 1000
4–10
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2007
Specifications and Additional Information
Table 4–2. Valid Data Code-Groups (Part 9 of 9)
Octet Bits
Code-Group Name
Current RD–
Current RD+
Octet Value
HGF EDCBA
abcdei fghj
D15.7
EF
111 01111
010111 0001
101000 1110
D16.7
F0
111 10000
011011 0001
100100 1110
D17.7
F1
111 10001
100011 0111
100011 0001
D18.7
F2
111 10010
010011 0111
010011 0001
D19.7
F3
111 10011
110010 1110
110010 0001
D20.7
F4
111 10100
001011 0111
001011 0001
D21.7
F5
111 10101
101010 1110
101010 0001
D22.7
F6
111 10110
011010 1110
011010 0001
D23.7
F7
111 10111
111010 0001
000101 1110
D24.7
F8
111 11000
110011 0001
001100 1110
D25.7
F9
111 11001
100110 1110
100110 0001
D26.7
FA
111 11010
010110 1110
010110 0001
D27.7
FB
111 11011
110110 0001
001001 1110
D28.7
FC
111 11100
001110 1110
001110 0001
D29.7
FD
111 11101
101110 0001
010001 1110
D30.7
FE
111 11110
011110 0001
100001 1110
D31.7
FF
111 11111
101011 0001
010100 1110
Document
Revision History
Table 4–3 shows the revision history for this document.
Table 4–3. Document Revision History
Date and Document Version
May 2007 v1.0
Altera Corporation
May 2007
Changes Made
Initial Release
Summary of Changes
N/A
4–11
Arria GX Device Handbook, Volume 2
Document Revision History
4–12
Arria GX Device Handbook, Volume 2
Altera Corporation
May 2007
Section II. Clock
Management
This section provides information on clock management in Arria™ GX
devices. It describes the enhanced and fast phase-locked loops (PLLs) that
support clock management and synthesis for on-chip clock management,
external system clock management, and high-speed I/O interfaces.
This section includes the following chapter:
■
Revision History
Altera Corporation
Chapter 5, PLLs in Arria GX Devices
Refer to each chapter for its own specific revision history. For information
on when each chapter was updated, refer to the Chapter Revision Dates
section, which appears in the full handbook.
Section II–1
Preliminary
Clock Management
Section II–2
Preliminary
Arria GX Device Handbook, Volume 2
Altera Corporation
5. PLLs in Arria GX Devices
AGX52005-1.2
Introduction
ArriaTM GX device phase-locked loops (PLLs) provide robust clock
management and synthesis for device clock management, external
system clock management, and high-speed I/O interfaces. These PLLs
are highly versatile and can be used as a zero delay buffer, a jitter
attenuator, low skew fan out buffer, or a frequency synthesizer.
Arria GX devices feature up to four enhanced PLLs and up to four fast
PLLs. Both enhanced and fast PLLs are feature rich, supporting advanced
capabilities such as clock switchover, reconfigurable phase shift, PLL
reconfiguration, and reconfigurable bandwidth. You can use PLLs for
general-purpose clock management, supporting multiplication, phase
shifting, and programmable duty cycle. In addition, enhanced PLLs
support external clock feedback mode, spread-spectrum clocking, and
counter cascading. Fast PLLs offer high-speed outputs to manage
high-speed differential I/O interfaces.
Arria GX devices also support power-down mode where clock networks
that are not being used can easily be turned off, reducing overall power
consumption of the device. In addition, Arria GX PLLs support dynamic
selection of the PLL input clock from up to five possible sources, giving
you the flexibility to choose from multiple (up to four) clock sources to
feed the primary and secondary clock input ports.
The Altera® Quartus® II software enables the PLLs and their features
without requiring any external devices.
This chapter contains the following sections:
■
■
■
■
■
■
■
■
■
■
■
■
■
Altera Corporation
May 2008
“Enhanced PLLs” on page 5–5
“Fast PLLs” on page 5–14
“Clock Feedback Modes” on page 5–18
“Hardware Features” on page 5–23
“Advanced Features” on page 5–30
“Reconfigurable Bandwidth” on page 5–42
“PLL Reconfiguration” on page 5–49
“Spread-Spectrum Clocking” on page 5–49
“Board Layout” on page 5–54
“PLL Specifications” on page 5–59
“Clocking” on page 5–59
“Clock Control Block” on page 5–77
“Conclusion” on page 5–81
5–1
PLLs in Arria GX Devices
Table 5–1 shows the PLLs available for each Arria GX device.
Table 5–1. Arria GX Device PLL Availability Note (1)
Device
Fast PLLs
Enhanced PLLs
1
2
7
8
5
6
11
12
EP1AGX20 (2)
v
v
—
—
v
v
—
—
EP1AGX35 (2)
v
v
—
—
v
v
—
—
EP1AGX50 (2)
v
v
v
v
v
v
v
v
EP1AGX60 (3)
v
v
v
v
v
v
v
v
EP1AGX90
v
v
v
v
v
v
v
v
Notes for Table 5–1:
(1)
(2)
(3)
The global or regional clocks in a fast PLL’s transceiver block can drive the fast
PLL input. A pin or other PLL must drive the global or regional source. The
source cannot be driven by internally generated logic before driving the fast PLL.
EP1AGX20, EP1AGX35, EP1AGX50 and EP1AGX60 devices only have two fast
PLLs (PLLs 1 and 2).
EP1AGX60 devices in F484 and F780 devices have two fast PLLs (PLL 1 and 2)
and two enhanced PLLs. Arria GX devices in the F1152 package support all eight
PLLs.
Table 5–2 shows the enhanced PLL and fast PLL features in Arria GX
devices.
Table 5–2. Arria GX PLL Features (Part 1 of 2)
Feature
Clock multiplication and division
Enhanced PLL
Fast PLL
m/(n post-scale counter) (1)
m/(n post-scale counter) (2)
Down to 125-ps increments (3)
Down to 125-ps increments (3)
Clock switchover
v
v(4)
PLL reconfiguration
v
v
Reconfigurable bandwidth
v
v
Spread-spectrum clocking
v
—
Programmable duty cycle
v
v
Phase shift
Number of clock outputs per PLL (5)
Number of dedicated external clock outputs
per PLL
5–2
Arria GX Device Handbook, Volume 1
6
4
Three differential or six
single-ended
(6)
Altera Corporation
May 2008
Introduction
Table 5–2. Arria GX PLL Features (Part 2 of 2)
Feature
Number of feedback clock inputs per PLL
Enhanced PLL
Fast PLL
1 (7)
—
Notes to Table 5–2:
(1)
(2)
(3)
(4)
(5)
(6)
(7)
For enhanced PLLs, m and n range from 1 to 512 with a 50% duty cycle. Post-scale counters range from 1 to 512
with a 50% duty cycle. For non-50% duty-cycle clock outputs, post-scale counters range from 1 to 256.
Fast PLLs can range from 1 to 4. The post-scale and m counters range from 1 to 32. For non-50% duty-cycle clock
outputs, post-scale counters range from 1 to 16.
The smallest phase shift is determined by the voltage controlled oscillator (VCO) period divided by eight. The
supported phase-shift range is from 125 to 250 ps. Arria GX devices can shift all output frequencies in increments
of at least 45. Smaller degree increments are possible depending on the frequency and divide parameters. For
non-50% duty cycle clock outputs post-scale counters range from 1 to 256.
Arria GX fast PLLs only support manual clock switchover.
Clock outputs can be driven to internal clock networks or to a pin.
PLL clock outputs of the fast PLLs can drive to any I/O pin to be used as an external clock output. For high-speed
differential I/O pins, the device uses a data channel to generate the transmitter output clock (txclkout).
If the design uses external feedback input pins, you will lose one (or two, if fbin is differential) dedicated output
clock pins.
Altera Corporation
May 2008
5–3
Arria GX Device Handbook, Volume 1
PLLs in Arria GX Devices
Figure 5–1 shows a top-level diagram of the Arria GX device and PLL
locations. See “Clock Control Block” on page 5–77 for more information
about PLL connections to global and regional clocks networks.
Figure 5–1. Arria GX PLL Locations
CLK[15..12]
FPLL7CLK
7
CLK[3..0]
1
2
FPLL8CLK
8
11
5
12
6
CLK[7..4]
Notes to Figure 5–1:
(1)
(2)
(3)
(4)
(5)
EP1AGX20 and EP1AGX35 devices have two enhanced and two fast PLLs.
EP1AGX50 devices in the F484 package have two enhanced PLLs (5 and 6), two fast PLLs (1 and 2), two enhanced
and two fast PLLs (1 and 2) in the F780 package, and four enhanced, four fast PLLs in the F1152 package.
EP1AGX60 devices in the F484 and F780 packages have two enhanced and two fast PLLs, and four enhanced and
four fast PLLs in the F1152 package.
EP1AGX60 devices have four enhanced and four fast PLLs in the F1152 package.
The corner fast PLLs (7 and 8) are enabled only in the F1152 package offering.
5–4
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Altera Corporation
May 2008
Enhanced PLLs
Enhanced PLLs
Arria GX devices contain up to four enhanced PLLs with advanced clock
management features. The main goal of a PLL is to synchronize the phase
and frequency of an internal and external clock to an input reference
clock. There are a number of components that comprise a PLL to achieve
this phase alignment.
Enhanced PLL Hardware Overview
Arria GX PLLs align the rising edge of the reference input clock to a
feedback clock using the phase-frequency detector (PFD). The falling
edges are determined by duty-cycle specifications. The PFD produces an
up or down signal that determines whether the VCO needs to operate at
a higher or lower frequency.
PFD output is applied to the charge pump and loop filter, which produces
a control voltage for setting the VCO frequency. If the PFD produces an
up signal, the VCO frequency increases; a down signal decreases the VCO
frequency. The PFD outputs these up and down signals to a charge pump.
If the charge pump receives an up signal, current is driven into the loop
filter. Conversely, if the charge pump receives a down signal, current is
drawn from the loop filter.
The loop filter converts these up and down signals to a voltage that is
used to bias the VCO. The loop filter also removes glitches from the
charge pump and prevents voltage over-shoot, which filters the jitter on
the VCO.
The voltage from the loop filter determines how fast the VCO operates.
The VCO is implemented as a four-stage differential ring oscillator. A
divide counter (m) is inserted in the feedback loop to increase the VCO
frequency above the input reference frequency. VCO frequency (fVCO) is
equal to (m) times the input reference clock (fREF). The input reference
clock (fREF) to the PFD is equal to the input clock (fIN) divided by the
pre-scale counter (n). Therefore, the feedback clock (fFB) applied to one
input of the PFD is locked to the fREF that is applied to the other input of
the PFD.
The VCO output can feed up to six post-scale counters (C0, C1, C2, C3, C4,
and C5). These post-scale counters allow a number of harmonically
related frequencies to be produced within the PLL.
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 1
PLLs in Arria GX Devices
Figure 5–2 shows a simplified block diagram of the major components of
the Arria GX enhanced PLL. Figure 5–3 shows the enhanced PLL’s
outputs and dedicated clock outputs.
Figure 5–2. Arria GX Enhanced PLL Note (3), (4)
From Adjacent PLL
VCO Phase Selection
Selectable at Each
PLL Output Port
Clock
Switchover
Circuitry
Post-Scale
Counters
Spread
Spectrum
Phase Frequency
Detector
÷C0
inclk[3..0]
÷C1
4
÷n
PFD
Charge
Pump
Loop
Filter
Global or
Regional
Clock
8
VCO
4
Global
Clocks
8
Regional
Clocks
÷C2
6
÷C3
6
(1)
÷m
I/O Buffers (2)
÷C4
÷C5
fbin
Shaded Portions of the
PLL are Reconfigurable
Lock Detect
& Filter
to I/O or general
routing
VCO Phase Selection
Affecting All Outputs
Notes to Figure 5–2:
(1)
(2)
(3)
(4)
Each clock source can come from any of the four clock pins located on the same side of the device as the PLL.
PLLs 5, 6, 11, and 12 each have six single-ended dedicated clock outputs or three differential dedicated clock
outputs.
If the design uses external feedback input pins, you will lose one (or two, if fbin is differential) dedicated output
clock pin. Every Arria GX device has at least two enhanced PLLs with one single-ended or differential external
feedback input per PLL.
The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock. An internally generated global signal cannot drive the PLL.
5–6
Arria GX Device Handbook, Volume 1
Altera Corporation
May 2008
Enhanced PLLs
External Clock Outputs
Enhanced PLLs 5, 6, 11, and 12 each support up to six single-ended clock
outputs (or three differential pairs), as shown in Figure 5–3.
Figure 5–3. External Clock Outputs for Enhanced PLLs 5, 6, 11, and 12
C0
C1
Enhanced
PLL
C2
C3
C4
C5
extclken0
(3)
extclken2
(3)
extclken3
(3)
extclken1
(3)
PLL#_OUT0p
(1)
PLL#_OUT0n
(1)
extclken4
(3)
extclken5
(3)
PLL#_OUT1p
(1)
PLL#_OUT2p
(1), (2)
PLL#_OUT1n
(1)
PLL#_OUT2n
(1), (2)
Notes to Figure 5–3:
(1)
(2)
(3)
These clock output pins can be fed by any one of the C[5..0] counters.
These clock output pins are used as either external clock outputs or for external feedback. If the design uses external
feedback input pins, you will lose one (or two, if fbin is differential) dedicated output clock pin.
These external clock enable signals are available only when using the ALTCLKCTRL megafunction.
Any of the six output counters C[5..0] can feed the dedicated external
clock outputs, as shown in Figure 5–5. Therefore, one counter or
frequency can drive all output pins available from a given PLL. The
dedicated output clock pins (PLL#_OUT) from each enhanced PLL are
powered by a separate power pin (for example, VCC_PLL5_OUT,
VCC_PLL6_OUT, etc.), reducing the overall output jitter by providing
improved isolation from switching I/O pins.
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 1
PLLs in Arria GX Devices
Figure 5–4. External Clock Output Connectivity to PLL Output Counters for Enhanced PLLs 5, 6, 11, and 12
Note (1)
C0
C1
6
6
To I/O pins (1)
C3
C4
From internal logic
or IOE
C5
6
Multiplexer Selection
Set in Configuration File
C6
Note to Figure 5–4:
(1)
The design can use each external clock output pin as a general-purpose output pin from the logic array. These pins
are multiplexed with I/O element (IOE) outputs.
Each pin of a single-ended output pair can either be in phase or 180o out
of phase. The Quartus II software places the NOT gate in the design into
the IOE to implement 180o phase with respect to the other pin in the pair.
The clock output pin pairs support the same I/O standards as standard
output pins (in the top and bottom banks) as well as LVDS, LVPECL,
differential HSTL, and differential SSTL. See Table 5–5, under “Enhanced
PLL Pins” on page 5–11 to determine which I/O standards the enhanced
PLL clock pins support.
When in single-ended or differential mode, one power pin supports six
single-ended or three differential outputs. Both outputs use the same I/O
standard in single-ended mode to maintain performance. You can also
use the external clock output pins as user output pins if external
enhanced PLL clocking is not needed.
The enhanced PLL can also drive out to any regular I/O pin through the
global or regional clock network. For this case, jitter on the output clock
is pending characterization
Enhanced PLL Software Overview
Arria GX enhanced PLLs are enabled in the Quartus II software by using
the ALTPLL megafunction. Figure 5–5 shows the available ports (as they
are named in the Quartus II ALTPLL megafunction) of the Arria GX
enhanced PLL.
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Altera Corporation
May 2008
Enhanced PLLs
Figure 5–5. Enhanced PLL Ports
(1)
Physical Pin
pllena
(2), (3)
inclk0
(2), (3)
inclk1
C[5..0]
(4)
Signal Driven by Internal Logic
Signal Driven to Internal Logic
Internal Clock Signal
locked
scanwrite
clkloss
activeclock
scanread
scandataout
scandata
clkbad[1..0]
scanclk
scandone
fbin
clkswitch
areset
pfdena
(5)
pll#_out0p
pll#_out0n
(5)
pll#_out1p
(5)
pll#_out1n
(5)
pll#_out2p
(5)
pll#_out2n
(5)
Notes to Figure 5–5:
(1)
(2)
(3)
(4)
(5)
Enhanced and fast PLLs share this input pin.
These are either single-ended or differential pins.
The primary and secondary clock input can be fed from any one of four clock pins located on the same side of the
device as the PLL.
C[5..0] can drive to the global or regional clock networks or the dedicated external clock output pins.
These dedicated output clocks are fed by the C[5..0] counters.
Tables 5–3 and 5–4 describe all the enhanced PLL ports.
Table 5–3. Enhanced PLL Input Signals (Part 1 of 2)
Port
Description
Source
Destination
inclk0
Primary clock input to the PLL.
Pin or another PLL
counter
inclk1
Secondary clock input to the PLL.
Pin or another PLL
counter
fbin
External feedback input to the PLL.
Pin
PFD
pllena
Enable pin for enabling or disabling
all or a set of PLLs. Active high.
Pin
General PLL control
signal
clkswitch
Switch-over signal used to initiate
external clock switch-over control.
Active high.
Logic array
PLL switch-over circuit
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 1
PLLs in Arria GX Devices
Table 5–3. Enhanced PLL Input Signals (Part 2 of 2)
Port
Description
Source
Destination
areset
Signal used to reset the PLL which
resynchronizes all the counter
outputs. Active high.
Logic array
General PLL control
signal
pfdena
Enables the outputs from the phase
frequency detector. Active high.
Logic array
PFD
scanclk
Serial clock signal for the real-time
PLL reconfiguration feature.
Logic array
Reconfiguration circuit
scandata
Serial input data stream for the real- Logic array
time PLL reconfiguration feature.
Reconfiguration circuit
scanwrite
Enables writing the data in the scan
chain into the PLL. Active high.
Logic array
Reconfiguration circuit
scanread
Enables scan data to be written into
the scan chain. Active high.
Logic array
Reconfiguration circuit
Table 5–4. Enhanced PLL Output Signals (Part 1 of 2)
Port
Description
Source
Destination
C[5..0]
PLL output counters driving regional, PLL counter
global or external clocks.
Internal or external clock
pll#_out[2..0]p
pll#_out[2..0]n
PLL counter
These are three differential or six
single-ended external clock output
pins fed from the C[5..0]PLL
counters, and every output can be
driven by any counter. p and n are
the positive (p) and negative (n) pins
for differential pins.
Pin(s)
clkloss
Signal indicating the switch-over
circuit detected a switch-over
condition.
PLL switch-over
circuit
Logic array
clkbad[1..0]
PLL switch-over
Signals indicating which reference
circuit
clock is no longer toggling.
clkbad1 indicates inclk1 status,
clkbad0 indicates inclk0 status.
1= good; 0 = bad
Logic array
locked
Lock or gated lock output from lock
detect circuit. Active high.
Logic array
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PLL lock detect
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May 2008
Enhanced PLLs
Table 5–4. Enhanced PLL Output Signals (Part 2 of 2)
Port
Description
Source
Destination
activeclock
Signal to indicate which clock
PLL clock
multiplexer
(0 = inclk0 or 1 = inclk1) is
driving the PLL. If this signal is low,
inclk0 drives the PLL, If this signal
is high, inclk1 drives the PLL
Logic array
scandataout
Output of the last shift register in the PLL scan chain
scan chain.
Logic array
scandone
Signal indicating when the PLL has
completed reconfiguration. 1 to 0
transition indicates that the PLL has
been reconfigured.
PLL scan chain
Logic array
Enhanced PLL Pins
Table 5–5 lists the I/O standards support by enhanced PLL clock outputs.
Table 5–5. I/O Standards Supported for Enhanced PLL Pins Note (1)
(Part 1 of 2)
Input
inclk
fbin
Output
extclk
LVTTL
v
v
v
LVCMOS
v
v
v
2.5 V
v
v
v
1.8 V
v
v
v
1.5 V
v
v
v
3.3-V PCI
v
v
v
3.3-V PCI-X
v
v
v
SSTL-2 Class I
v
v
v
SSTL-2 Class II
v
v
v
SSTL-18 Class I
v
v
v
SSTL-18 Class II
v
v
v
1.8-V HSTL Class I
v
v
v
1.8-V HSTL Class II
v
v
v
1.5-V HSTL Class I
v
v
v
1.5-V HSTL Class II
v
v
v
Differential SSTL-2 Class I
v
v
v
Differential SSTL-2 Class II
v
v
v
I/O Standard
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 1
PLLs in Arria GX Devices
Table 5–5. I/O Standards Supported for Enhanced PLL Pins Note (1)
(Part 2 of 2)
Input
inclk
fbin
Output
extclk
Differential SSTL-18 Class I
v
v
v
Differential SSTL-18 Class II
v
v
v
1.8-V differential HSTL Class I
v
v
v
1.8-V differential HSTL Class II
v
v
v
1.5-V differential HSTL Class I
v
v
v
1.5-V differential HSTL Class II
v
v
v
LVDS
v
v
v
HyperTransport technology
—
—
—
Differential LVPECL
v
v
v
I/O Standard
Note to Table 5–5:
(1)
The enhanced PLL external clock output bank does not allow a mixture of both
single-ended and differential I/O standards.
Table 5–6 shows the physical pins and their purpose for Arria GX
enhanced PLLs. For inclk port connections to pins, see “Clock Control
Block” on page 5–77.
Table 5–6. Arria GX Enhanced PLL Pins Note (1) (Part 1 of 2)
Pin
Description
CLK4p/n
Single-ended or differential pins that can drive the inclk port for PLLs 6 or 12.
CLK5p/n
Single-ended or differential pins that can drive the inclk port for PLLs 6 or 12.
CLK6p/n
Single-ended or differential pins that can drive the inclk port for PLLs 6 or 12.
CLK7p/n
Single-ended or differential pins that can drive the inclk port for PLLs 6 or 12.
CLK12p/
Single-ended or differential pins that can drive the inclk port for PLLs 5 or 11.
CLK13p/
Single-ended or differential pins that can drive the inclk port for PLLs 5 or 11.
CLK14p/n
Single-ended or differential pins that can drive the inclk port for PLLs 5 or 11.
CLK15p/n
Single-ended or differential pins that can drive the inclk port for PLLs 5 or 11.
PLL5_FBp/n
Single-ended or differential pins that can drive the fbin port for PLL 5.
PLL6_FBp/n
Single-ended or differential pins that can drive the fbin port for PLL 6.
PLL11_FBp/n
Single-ended or differential pins that can drive the fbin port for PLL 11.
PLL12_FBp/n
Single-ended or differential pins that can drive the fbin port for PLL 12.
pllena
Dedicated input pin that drives the pllena port of all or a set of PLLs. If you do
not use this pin, connect it to ground.
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May 2008
Enhanced PLLs
Table 5–6. Arria GX Enhanced PLL Pins Note (1) (Part 2 of 2)
Pin
Description
PLL5_OUT[2..0]p/n
Single-ended or differential pins driven by C[5..0]ports from PLL 5.
PLL6_OUT[2..0]p/n
Single-ended or differential pins driven by C[5..0]ports from PLL 6.
PLL11_OUT[2..0]p/n
Single-ended or differential pins driven by C[5..0]ports from PLL 11.
PLL12_OUT[2..0]p/n
Single-ended or differential pins driven by C[5..0] ports from PLL 12.
VCCA_PLL5
Analog power for PLL 5. You must connect this pin to 1.2 V, even if the PLL is not
used.
GNDA_PLL5
Analog ground for PLL 5. You can connect this pin to the GND plane on the board.
VCCA_PLL6
Analog power for PLL 6. You must connect this pin to 1.2 V, even if the PLL is not
used.
GNDA_PLL6
Analog ground for PLL 6. You can connect this pin to the GND plane on the board.
VCCA_PLL11
Analog power for PLL 11. You must connect this pin to 1.2 V, even if the PLL is not
used.
GNDA_PLL11
Analog ground for PLL 11. You can connect this pin to the GND plane on the
board.
VCCA_PLL12
Analog power for PLL 12. You must connect this pin to 1.2 V, even if the PLL is not
used.
GNDA_PLL12
Analog ground for PLL 12. You can connect this pin to the GND plane on the
board.
VCCD_PLL
Digital power for PLLs. You must connect this pin to 1.2 V, even if the PLL is not
used.
VCC_PLL5_OUT
External clock output VCCIO power for PLL5_OUT0p, PLL5_OUT0n,
PLL5_OUT1p, PLL5_OUT1n, PLL5_OUT2p, and PLL5_OUT2n outputs from PLL
5.
VCC_PLL6_OUT
External clock output VCCIO power for PLL6_OUT0p, PLL6_OUT0n,
PLL6_OUT1p, PLL6_OUT1n and PLL6_OUT2p, PLL6_OUT2n outputs from PLL
6.
VCC_PLL11_OUT
External clock output VCCIO power for PLL11_OUT0p, PLL11_OUT0n,
PLL11_OUT1p, PLL11_OUT1n and PLL11_OUT2p, PLL11_OUT2n outputs from
PLL 11.
VCC_PLL12_OUT
External clock output VCCIO power for PLL12_OUT0p, PLL12_OUT0n,
PLL12_OUT1p, PLL12_OUT1n and PLL12_OUT2p, PLL12_OUT2n outputs from
PLL 12.
Note to Table 5–6:
(1)
The negative leg pins (CLKn, PLL_FBn, and PLL_OUTn) are only required with differential signaling.
Altera Corporation
May 2008
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Arria GX Device Handbook, Volume 1
PLLs in Arria GX Devices
Fast PLLs
Arria GX devices contain up to four fast PLLs. Fast PLLs have high-speed
differential I/O interface capability along with general purpose features.
Fast PLL Hardware Overview
Figure 5–6 shows a diagram of the fast PLL for Arria GX devices.
Figure 5–6. Arria GX Fast PLL Block Diagram
Global or
regional clock (2)
Clock (1)
Switchover
Circuitry
VCO Phase Selection
Selectable at each PLL
Output Port
Phase
Frequency
Detector
diffioclk0 (3)
Clock
Input
loaden0 (4)
÷c0
(5)
÷n
4
Post-Scale
Counters
PFD
Charge
Pump
Loop
Filter
VCO
÷k
diffioclk1 (3)
8
loaden1 (4)
÷c1
4
Global clocks
÷c2
4
Global or
regional clock (2)
8
Regional clocks
÷c3
÷m
8
Shaded Portions of the
PLL are Reconfigurable
to DPA block
Notes to Figure 5–6:
(1)
(2)
(3)
(4)
(5)
Arria GX fast PLLs only support manual clock switchover.
The global or regional clock input can be driven by an output from another PLL, a pin-driven dedicated global or
regional clock, or through a clock control block provided the clock control block is fed by an output from another
PLL or a pin-driven dedicated global or regional clock.
In high-speed differential I/O support mode, this high-speed PLL clock feeds SERDES. Arria GX devices only
support one rate of data transfer per fast PLL in high-speed differential I/O support mode.
This signal is a high-speed differential I/O support SERDES control signal.
If the design enables this ÷2 counter, the device can use a VCO frequency range of 150 to 520 MHz.
External Clock Outputs
Each fast PLL supports differential or single-ended outputs for
source-synchronous transmitters or general-purpose external clocks.
There are no dedicated external clock output pins. The fast PLL global or
regional outputs can drive any I/O pin as an external clock output pin.
The I/O standards supported by any particular bank determines what
standards are possible for an external clock output driven by the fast PLL
in that bank.
f
For more information, see the Selectable I/O Standards in Arria GX Devices
chapter in volume 2 of the Arria GX Device Handbook.
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Altera Corporation
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Fast PLLs
Fast PLL Software Overview
Arria GX fast PLLs are enabled in the Quartus II software by using the
ALTPLL megafunction. Figure 5–7 shows the available ports (as they are
named in the Quartus II ALTPLL megafunction) of the Arria GX fast PLL.
Figure 5–7. Arria GX Fast PLL Ports and Physical Destinations
Physical Pin
inclk0 (1)
C[3..0]
inclk1 (1)
Signal Driven by Internal Logic
Signal Driven to Internal Logic
pllena (2)
Internal Clock Signal
locked
areset
pfdena
scanclk
scandata
scanwrite
scandataout
scandone
scanread
Notes to Figure 5–7:
(1)
(2)
This input pin is either single-ended or differential.
This input pin is shared by all enhanced and fast PLLs.
Tables 5–7 and 5–8 show the description of all fast PLL ports.
Table 5–7. Fast PLL Input Signals
Name
Description
Source
Destination
inclk0
Primary clock input to the fast PLL.
Pin or another PLL
counter
inclk1
Secondary clock input to the fast PLL.
Pin or another PLL
counter
pllena
Enable pin for enabling or disabling all or a set
of PLLs. Active high.
Pin
PLL control signal
clkswitch
Switch-over signal used to initiate external clock Logic array
switch-over control. Active high.
Reconfiguration circuit
areset
Enables the up/down outputs from the
phase-frequency detector. Active high.
Logic array
PLL control signal
pfdena
Enables the up/down outputs from the
phase-frequency detector. Active high.
Logic array
PFD
scanclk
Serial clock signal for the real-time PLL control
feature.
Logic array
Reconfiguration circuit
scandata
Serial input data stream for the real-time PLL
control feature.
Logic array
Reconfiguration circuit
Altera Corporation
May 2008
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PLLs in Arria GX Devices
Tabl