ABOV MC96F7816, MC96C7816 microcontroller User’s Manual

MC96F7816/C7816

ABOV SEMICONDUCTOR Co., Ltd.

8-BIT MICROCONTROLLERS

MC96F7816/C7816

User’s Manual (Ver. 2.5)

April 20, 2012 Ver. 2.5 1

MC96F7816/C7816

REVISION HISTORY

VERSION 0.0 (April 9, 2010)

VERSION 1.0 (July 12, 2010)

Change all

LVR/LVI‟s Detection Min/Max Values at Low Voltage Reset and Low Voltage Indicator characteristics

Change „8/14μA (Typ/Max)‟ to “I

BL

@Both Enable” in Low Voltage Reset and Low Voltage Indicator characteristics

Change „6/12μA (Typ/Max)‟ to “I

BL

@One of two

Enable” in Low Voltage Reset and Low Voltage Indicator characteristics

Change „±1.5%/±2.5%/±3.5%‟(T

A

= 0°C

– +70°C/T

A

= -20°C

– +85°C/T

Tolerance ” in Internal RC Oscillator characteristics.

A

= -40°C

– +85°[email protected] – 5.5V) to “IRC‟s

Change „3/6/9 kHz (Min/Typ/Max)‟ to “f

WDTRC

” in INTERNAL WATCH-DOG RC OSCILLATION characteristics.

Change „LCD Voltage‟s Min/Typ/Max Values‟ to “VLC3” in LCD VOLTAGE characteristics.

Change

„3/6uA (Typ/Max)‟ to “I

LCD

” in LCD VOLTAGE characteristics.

Change „3.0/6.0mA (Typ/Max)‟ to “IDD1 @12MHz” in DC electrical characteristics.


Change „1.4/2.8mA (Typ/Max)‟ to “IDD1 @IRC 4MHz” in DC electrical characteristics.


Change „0.6/1.2mA (Typ/Max)‟ to “IDD2 @IRC 4MHz” in DC electrical characteristics.

Change „50.0/80.0μA (Typ/Max)‟ to “IDD3” in DC electrical characteristics.

Change „4.0/8.0μA (Typ/Max)‟ to “IDD4” in DC electrical characteristics.

Add a note at „T2ADRL Register description ‟.

Add a note at „T3ADRL Register description ‟.

Change „LCDCCR Register description ‟.

Change A/D Conversion timing information.

Change description at „LVRCR Register description ‟.

VERSION 1.1 (August 19, 2010)

Change „3.0μA (Max)‟ to “IDD5” in DC electrical characteristics.

Change RSTFR Register

‟s Initial value and note at „RSTFR Register description‟

VERSION 1.2 (September 15, 2010)

Change „1.60/1.75 (Typ/Max)‟ to “LVR/LVI level” in LVR/LVI electrical characteristics

.

Change „600/1200/2000 kΩ (Min/Typ/Max)‟ to “RX1” in DC electrical characteristics.

Add Figure11.9 PWM Output Waveforms in PWM Mode for Timer 0.

VERSION 1.3 (December 29, 2010)

Change „±4 (Max)‟ to “ILE” in ADC electrical characteristics

.

Add a note at „SCCR&OSCCR Register description ‟.

VERSION 2.0 (January 7, 2011)

Delete P91/P90 ‟s GPIO function. Only use XIN/XOUT pins.

Add MC96C7816

‟s specification(MC96F7816‟s Mask version)

VERSION 2.1 (April 12, 2011)

Add Figure7.21 and Figure 8.20 Recommended Circuit and Layout in Electrical Characteristics.

Add a Note at „LVRCR register description‟.

Add a Note 3 at

„DSDA and DSCL pins information‟.

Change contents and „LCD Voltage‟s Min/Typ/Max Values‟ to “VLC3” in LCD VOLTAGE characteristics.

VERSION 2.2 (July 4, 2011)

Change RSTFR Register ‟s Initial value and note at „RSTFR Register description‟

2 April 20, 2012 Ver. 2.5

MC96F7816/C7816

VERSION 2.3 (November 23, 2011)

Change description at „RXC function descriptions‟.

Change description at „T0EN function descriptions‟.

Change NOTE at

„LVRVS[3:0] bits description‟.

Add „Instructions on how to use the input port‟ descriptions.

VERSION 2.4 (December 6, 2011)

Add „VLC3 electrical characteristics‟ about 1/2 and 1/4 bias for MC96F7816(flash).

VERSION 2.5 (April 20, 2012) This book

Change „30V/mS (Max)‟ to “VDD Voltage Rising Time” in Power-on Reset Electrical characteristics.

Add a

“Table 12.21 LCD Frame Frequency” in LCD driver chapter.

Retype a typo at „EO Register description‟.

Version 2.5

Published by FAE Team



2012 ABOV Semiconductor Co.,Ltd. All rights reserved.

Additional information of this manual may be served by ABOV Semiconductor offices in Korea or Distributors.

ABOV Semiconductor reserves the right to make changes to any information here in at any time without notice.

The information, diagrams and other data in this manual are correct and reliable; however, ABOV

Semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.

April 20, 2012 Ver. 2.5 3

MC96F7816/C7816

Table of Contents

1. Overview ........................................................................................................................................................... 12

1.1 Description ................................................................................................................................................. 12

1.2 Comparison of MC96F7816 and MC96C7816 ........................................................................................... 12

1.3 Features ..................................................................................................................................................... 13

1.4 Ordering Information .................................................................................................................................. 14

1.5 Development Tools .................................................................................................................................... 15

2. Block Diagram ................................................................................................................................................... 17

3. Pin Assignment ................................................................................................................................................. 18

4. Package Diagram .............................................................................................................................................. 20

5. Pin Description .................................................................................................................................................. 22

6. Port Structures .................................................................................................................................................. 26

6.1 General Purpose I/O Port ........................................................................................................................... 26

6.2 External Interrupt I/O Port........................................................................................................................... 27

7. MC96F7816 Electrical Characteristics .............................................................................................................. 28

7.1 Absolute Maximum Ratings ........................................................................................................................ 28

7.2 Recommended Operating Conditions ........................................................................................................ 28

7.3 A/D Converter Characteristics .................................................................................................................... 29

7.4 Power-On Reset Characteristics ................................................................................................................ 29

7.5 Low Voltage Reset and Low Voltage Indicator Characteristics .................................................................. 30

7.6 Internal RC Oscillator Characteristics ......................................................................................................... 31

7.7 Internal Watch-Dog Timer RC Oscillator Characteristics ............................................................................ 31

7.8 LCD Voltage Characteristics ...................................................................................................................... 32

7.9 DC Characteristics ..................................................................................................................................... 34

7.10 AC Characteristics .................................................................................................................................... 35

7.11 Serial I/O Characteristics .......................................................................................................................... 36

7.12 UART Characteristics ............................................................................................................................... 37

7.13 Data Retention Voltage in Stop Mode ...................................................................................................... 38

7.14 Internal Flash Rom Characteristics .......................................................................................................... 39

7.15 Input/Output Capacitance ......................................................................................................................... 39

7.16 Main Clock Oscillator Characteristics ....................................................................................................... 40

7.17 Sub Clock Oscillator Characteristics ........................................................................................................ 41

7.18 Main Oscillation Stabilization Characteristics ........................................................................................... 42

7.19 Sub Oscillation Characteristics ................................................................................................................. 42

7.20 Operating Voltage Range ......................................................................................................................... 43

7.21 Recommended Circuit and Layout ........................................................................................................... 44

7.22 Typical Characteristics ............................................................................................................................. 45

8. MC96C7816 Electrical Characteristics(Mask Version) ...................................................................................... 48

8.1 Absolute Maximum Ratings ........................................................................................................................ 48

8.2 Recommended Operating Conditions ........................................................................................................ 48

8.3 A/D Converter Characteristics .................................................................................................................... 49

8.4 Power-On Reset Characteristics ................................................................................................................ 49

8.5 Low Voltage Reset and Low Voltage Indicator Characteristics .................................................................. 50

8.6 Internal RC Oscillator Characteristics ......................................................................................................... 51

8.7 Internal Watch-Dog Timer RC Oscillator Characteristics ............................................................................ 51

8.8 LCD Voltage Characteristics ...................................................................................................................... 52

8.9 DC Characteristics ..................................................................................................................................... 53

8.10 AC Characteristics .................................................................................................................................... 54

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MC96F7816/C7816

8.11 Serial I/O Characteristics .......................................................................................................................... 55

8.12 UART Characteristics ............................................................................................................................... 56

8.13 Data Retention Voltage in Stop Mode ...................................................................................................... 57

8.14 Input/Output Capacitance ......................................................................................................................... 58

8.15 Main Clock Oscillator Characteristics ....................................................................................................... 58

8.16 Sub Clock Oscillator Characteristics ........................................................................................................ 59

8.17 Main Oscillation Stabilization Characteristics ........................................................................................... 60

8.18 Sub Oscillation Characteristics ................................................................................................................. 60

8.19 Operating Voltage Range ......................................................................................................................... 61

8.20 Recommended Circuit and Layout ........................................................................................................... 62

8.21 Typical Characteristics ............................................................................................................................. 63

9. Memory ............................................................................................................................................................. 66

9.1 Program Memory ........................................................................................................................................ 66

9.2 Data Memory .............................................................................................................................................. 68

9.3 XRAM Memory ........................................................................................................................................... 70

9.4 SFR Map .................................................................................................................................................... 71

10. I/O Ports .......................................................................................................................................................... 78

10.1 I/O Ports ................................................................................................................................................... 78

10.2 Port Register ............................................................................................................................................ 78

10.3 P0 Port ..................................................................................................................................................... 81

10.4 P1 Port ..................................................................................................................................................... 83

10.5 P2 Port ..................................................................................................................................................... 85

10.6 P3 Port ..................................................................................................................................................... 86

10.7 P4 Port ..................................................................................................................................................... 87

10.8 P5 Port ..................................................................................................................................................... 88

10.9 P6 Port ..................................................................................................................................................... 89

10.10 P7 Port ................................................................................................................................................... 90

10.11 P8 Port ................................................................................................................................................... 91

10.12 P9 Port ................................................................................................................................................... 92

10.13 Port Function .......................................................................................................................................... 93

11. Interrupt Controller ........................................................................................................................................ 102

11.1 Overview ................................................................................................................................................ 102

11.2 External Interrupt .................................................................................................................................... 103

11.3 Block Diagram ........................................................................................................................................ 104

11.4 Interrupt Vector Table ............................................................................................................................. 105

11.5 Interrupt Sequence ................................................................................................................................. 105

11.6 Effective Timing after Controlling Interrupt Bit ........................................................................................ 107

11.7 Multi Interrupt ......................................................................................................................................... 108

11.8 Interrupt Enable Accept Timing .............................................................................................................. 109

11.9 Interrupt Service Routine Address .......................................................................................................... 109

11.10 Saving/Restore General-Purpose Registers ......................................................................................... 109

11.11 Interrupt Timing .................................................................................................................................... 110

11.12 Interrupt Register Overview .................................................................................................................. 110

11.13 Interrupt Register Description ............................................................................................................... 112

12. Peripheral Hardware ..................................................................................................................................... 117

12.1 Clock Generator ..................................................................................................................................... 117

12.2 Basic Interval Timer ................................................................................................................................ 121

12.3 Watch Dog Timer ................................................................................................................................... 123

12.4 Watch Timer ........................................................................................................................................... 126

12.5 Timer 0 ................................................................................................................................................... 129

12.6 Timer 1 ................................................................................................................................................... 139

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MC96F7816/C7816

12.7 Timer 2 ................................................................................................................................................... 148

12.8 Timer 3 ................................................................................................................................................... 159

12.9 Buzzer Driver .......................................................................................................................................... 170

12.10 SIO ....................................................................................................................................................... 172

12.11 12-Bit A/D Converter ............................................................................................................................ 177

12.12 UART.................................................................................................................................................... 182

12.13 LCD Driver ............................................................................................................................................ 196

13. Power Down Operation ................................................................................................................................. 210

13.1 Overview ................................................................................................................................................ 210

13.2 Peripheral Operation in IDLE/STOP Mode ............................................................................................. 210

13.3 IDLE Mode ............................................................................................................................................. 211

13.4 STOP Mode ............................................................................................................................................ 212

13.5 Release Operation of STOP Mode ......................................................................................................... 213

14. RESET .......................................................................................................................................................... 215

14.1 Overview ................................................................................................................................................ 215

14.2 Reset Source .......................................................................................................................................... 215

14.3 RESET Block Diagram ........................................................................................................................... 215

14.4 RESET Noise Canceller ......................................................................................................................... 216

14.5 Power On RESET .................................................................................................................................. 216

14.6 External RESETB Input .......................................................................................................................... 219

14.7 Brown Out Detector Processor ............................................................................................................... 220

14.8 LVI Block Diagram .................................................................................................................................. 221

15. On-chip Debug System ................................................................................................................................. 225

15.1 Overview ................................................................................................................................................ 225

15.2 Two-Pin External Interface ..................................................................................................................... 226

16. Flash Memory ............................................................................................................................................... 231

16.1 Overview ................................................................................................................................................ 231

17. Configure Option ........................................................................................................................................... 242

17.1 Configure Option Control Register ......................................................................................................... 242

18. APPENDIX .................................................................................................................................................... 243

6

List of Figures

Figure 1.1 OCD Debugger and Pin Description ...................................................................................... 15

Figure 1.2 PGMplusUSB (Single Writer) ................................................................................................. 16

Figure 1.3 StandAlone PGMplus (Single Writer) ..................................................................................... 16

Figure 1.4 StandAlone Gang8 (for Mass Production) ............................................................................. 16

Figure 2.1 MC96F7816 Block Diagram ................................................................................................... 17

Figure 3.1 MC96F7816 80MQFP-1420 Pin Assignment ......................................................................... 18

Figure 3.2 MC96F7816 80LQFP-1212 Pin Assignment .......................................................................... 19

Figure 4.1 80-Pin MQFP Package .......................................................................................................... 20

Figure 4.2 80-Pin LQFP Package ........................................................................................................... 21

Figure 6.1 General Purpose I/O Port ...................................................................................................... 26

Figure 6.2 External Interrupt I/O Port ...................................................................................................... 27

Figure 7.1 Input Timing for RESETB ...................................................................................................... 35

Figure 7.2 Input Timing for External Interrupts ........................................................................................ 35

Figure 7.3 Input Timing for EC0, EC2 ..................................................................................................... 35

Figure 7.4 Serial Interface Data Transfer Timing .................................................................................... 36

Figure 7.5 Waveform for UART Timing Characteristics .......................................................................... 37

April 20, 2012 Ver. 2.5

MC96F7816/C7816

Figure 7.6 Timing Waveform for the UART Module ................................................................................ 37

Figure 7.7 Stop Mode Release Timing when Initiated by an Interrupt .................................................... 38

Figure 7.8 Stop Mode Release Timing when Initiated by RESETB ........................................................ 38

Figure 7.9 Crystal/Ceramic Oscillator ..................................................................................................... 40

Figure 7.10 External Clock ...................................................................................................................... 40

Figure 7.11 Crystal Oscillator .................................................................................................................. 41


Figure 7.13 Clock Timing Measurement at XIN ...................................................................................... 42

Figure 7.14 Clock Timing Measurement at SXIN .................................................................................... 42

Figure 7.15 Operating Voltage Range .................................................................................................... 43

Figure 7.16 Recommended Circuit and Layout ....................................................................................... 44

Figure 7.17 RUN (IDD1) Currnet ............................................................................................................ 45

Figure 7.18 IDLE (IDD2) Current ............................................................................................................ 45

Figure 7.19 SUB RUN (IDD3) Current .................................................................................................... 46

Figure 7.20 SUB IDLE (IDD4) Currnet .................................................................................................... 46

Figure 7.21 STOP (IDD5) Current .......................................................................................................... 47

Figure 8.1 Input Timing for RESETB ...................................................................................................... 54

Figure 8.2 Input Timing for External Interrupts ........................................................................................ 54

Figure 8.3 Input Timing for EC0, EC2 ..................................................................................................... 54

Figure 8.4 Serial Interface Data Transfer Timing .................................................................................... 55

Figure 8.5 Waveform for UART Timing Characteristics .......................................................................... 56

Figure 8.6 Timing Waveform for the UART Module ................................................................................ 56

Figure 8.7 Stop Mode Release Timing when Initiated by an Interrupt .................................................... 57

Figure 8.8 Stop Mode Release Timing when Initiated by RESETB ........................................................ 57

Figure 8.9 Crystal/Ceramic Oscillator ..................................................................................................... 58


Figure 8.11 Crystal Oscillator .................................................................................................................. 59


Figure 8.13 Clock Timing Measurement at XIN ...................................................................................... 60

Figure 8.14 Clock Timing Measurement at SXIN .................................................................................... 60

Figure 8.15 Operating Voltage Range .................................................................................................... 61

Figure 8.16 Recommended Circuit and Layout ....................................................................................... 62

Figure 8.17 RUN (IDD1) Currnet ............................................................................................................ 63

Figure 8.18 IDLE (IDD2) Current ............................................................................................................ 63

Figure 8.19 SUB RUN (IDD3) Current .................................................................................................... 64

Figure 8.20 SUB IDLE (IDD4) Currnet .................................................................................................... 64

Figure 8.21 STOP (IDD5) Current .......................................................................................................... 65

Figure 9.1 Program Memory ................................................................................................................... 67

Figure 9.2 Data Memory Map ................................................................................................................. 68

Figure 9.3 Lower 128 Bytes RAM ........................................................................................................... 69

Figure 9.4 XDATA Memory Area ............................................................................................................ 70

Figure 11.1 External Interrupt Description ............................................................................................ 103

Figure 11.2 Block Diagram of Interrupt ................................................................................................. 104

Figure 11.3 Interrupt Vector Address Table .......................................................................................... 106

Figure 11.4 Effective Timing of Interrupt Enable Register.................................................................... 107

Figure 11.5 Effective Timing of Interrupt Flag Register ......................................................................... 107

Figure 11.6 Effective Timing of Interrupt ............................................................................................... 108

Figure 11.7 Interrupt Response Timing Diagram .................................................................................. 109

April 20, 2012 Ver. 2.5 7

MC96F7816/C7816

8

Figure 11.8 Correspondence between Vector Table Address and the Entry Address of ISP ............... 109

Figure 11.9 Saving/Restore Process Diagram and Sample Source ..................................................... 109

Figure 11.10 Timing Chart of Interrupt Acceptance and Interrupt Return Instruction ............................ 110

Figure 12.1 Clock Generator Block Diagram ........................................................................................ 117

Figure 12.2 Basic Interval Timer Block Diagram ................................................................................... 121

Figure 12.3 Watch Dog Timer Interrupt Timing Waveform.................................................................... 123

Figure 12.4 Watch Dog Timer Block Diagram ....................................................................................... 124

Figure 12.5 Watch Timer Block Diagram .............................................................................................. 126

Figure 12.6 8-Bit Timer/Counter Mode for Timer 0 ............................................................................... 130

Figure 12.7 8-Bit Timer/Counter 0 Example .......................................................................................... 131

Figure 12.8 8-Bit PWM Mode for Timer 0 ............................................................................................. 132

Figure 12.9 PWM Output Waveforms in PWM Mode for Timer 0 ......................................................... 133

Figure 12.10 8-Bit Capture Mode for Timer 0 ....................................................................................... 134

Figure 12.11 Input Capture Mode Operation for Timer 0 ...................................................................... 135

Figure 12.12 Express Timer Overflow in Capture Mode ....................................................................... 135

Figure 12.13 8-Bit Timer 0 Block Diagram ............................................................................................ 136

Figure 12.14 8-Bit Timer/Counter Mode for Timer 1 ............................................................................. 140

Figure 12.15 8-Bit Timer/Counter 1 Example ........................................................................................ 141

Figure 12.16 8-Bit Timer/Counter 1 Counter Operation ........................................................................ 141

Figure 12.17 Carrier Mode for Timer 1.................................................................................................. 142

Figure 12.18 Carrier Output Waveforms in Repeat Mode for Timer 1 .................................................. 144

Figure 12.19 8-Bit Timer 1 Block Diagram ............................................................................................ 145

Figure 12.20 16-Bit Timer/Counter Mode for Timer 2 ........................................................................... 149

Figure 12.21 16-Bit Timer/Counter 2 Example ...................................................................................... 150

Figure 12.22 16-Bit Capture Mode for Timer 2 ..................................................................................... 151



Figure 12.25 16-Bit PPG Mode for Timer 2 ........................................................................................... 153

Figure 12.26 16-Bit PPG Mode Timming chart for Timer 2 ................................................................... 154

Figure 12.27 16-Bit Timer/Counter Mode for Timer 2 and Block Diagram ............................................ 155

Figure 12.28 16-Bit Timer/Counter Mode for Timer 3 ........................................................................... 160

Figure 12.29 16-Bit Timer/Counter 3 Example ...................................................................................... 161

Figure 12.30 16-Bit Capture Mode for Timer 3 ..................................................................................... 162



Figure 12.33 16-Bit PPG Mode for Timer 3 ........................................................................................... 164

Figure 12.34 16-Bit PPG Mode Timming chart for Timer 3 ................................................................... 165

Figure 12.35 16-Bit Timer 3 Block Diagram .......................................................................................... 166

Figure 12.36 Buzzer Driver Block Diagram ........................................................................................... 170

Figure 12.37 SIO Block Diagram .......................................................................................................... 172

Figure 12.38 SIO Pre-Scaler Register (SIOPS) .................................................................................... 173

Figure 12.39 SIO Timing Diagram at SEDGE=0 ................................................................................... 174

Figure 12.40 SIO Timing Diagram at SEDGE=1 ................................................................................... 174

Figure 12.41 12-bit ADC Block Diagram ............................................................................................... 177

Figure 12.42 A/D Analog Input Pin with Capacitor ................................................................................ 178

Figure 12.43 A/D Power (AVDD) Pin with Capacitor............................................................................. 178

Figure 12.44 ADC Operation for Align Bit ............................................................................................. 178

Figure 12.45 A/D Converter Operation Flow ......................................................................................... 179

April 20, 2012 Ver. 2.5

MC96F7816/C7816

Figure 12.46 UART Block Diagram ....................................................................................................... 183

Figure 12.47 Clock Generation Block Diagram ..................................................................................... 184

Figure 12.48 Frame Format .................................................................................................................. 185

Figure 12.49 Start Bit Sampling ............................................................................................................ 189

Figure 12.50 Sampling of Data and Parity Bit ....................................................................................... 189

Figure 12.51 Stop Bit Sampling and Next Start Bit Sampling ............................................................... 190

Figure 12.52 LCD Circuit Block Diagram .............................................................................................. 197

Figure 12.53 LCD Signal Waveforms (Static) ....................................................................................... 198

Figure 12.54 LCD Signal Waveforms (1/2Duty, 1/2Bias) ...................................................................... 199




Figure 12.58 Internal Resistor Bias Connection .................................................................................... 203

Figure 12.59 External Resistor Bias Connection .................................................................................. 204

Figure 12.60 Capacitor Bias Connection .............................................................................................. 205

Figure 12.61 LCD Circuit Block Diagram .............................................................................................. 206

Figure 13.1 IDLE Mode Release Timing by External Interrupt .............................................................. 211

Figure 13.2 STOP Mode Release Timing by External Interrupt ............................................................ 212

Figure 13.3 STOP Mode Release Flow ................................................................................................ 213

Figure 14.1 RESET Block Diagram ...................................................................................................... 215

Figure 14.2 Reset noise canceller timer diagram .................................................................................. 216

Figure 14.3 Fast VDD Rising Time ....................................................................................................... 216

Figure 14.4 Internal RESET Release Timing On Power-Up ................................................................. 216

Figure 14.5 Configuration Timing when Power-on ................................................................................ 217

Figure 14.6 Boot Process Wave Form .................................................................................................. 217

Figure 14.7 Timing Diagram after RESET ............................................................................................ 219

Figure 14.8 Oscillator generating waveform example ........................................................................... 219

Figure 14.9 Block Diagram of BOD ....................................................................................................... 220

Figure 14.10 Internal Reset at the power fail situation .......................................................................... 220

Figure 14.11 Configuration timing when BOD RESET .......................................................................... 221

Figure 14.12 LVI Diagram ..................................................................................................................... 221

Figure 15.1 Block Diagram of On-Chip Debug System ......................................................................... 226

Figure 15.2 10-bit Transmission Packet................................................................................................ 227

Figure 15.3 Data Transfer on the Twin Bus .......................................................................................... 227

Figure 15.4 Bit Transfer on the Serial Bus ............................................................................................ 228

Figure 15.5 Start and Stop Condition .................................................................................................... 228

Figure 15.6 Acknowledge on the Serial Bus ......................................................................................... 229

Figure 15.7 Clock Synchronization during Wait Procedure ................................................................... 229

Figure 15.8 Connection of Transmission .............................................................................................. 230

Figure 16.1 Flash Program ROM Structure .......................................................................................... 232

List of Tables

Table 1-1 Ordering Information of MC96F7816/C7816 ........................................................................... 14

Table 5-1 Normal pin description ............................................................................................................ 22

Table 7-1 Absolute Maximum Ratings .................................................................................................... 28

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MC96F7816/C7816

10

Table 7-2 Recommended Operating Conditions ..................................................................................... 28

Table 7-3 A/D Converter Characteristics ................................................................................................ 29

Table 7-4 Power-On Reset Characteristics ............................................................................................. 29

Table 7-5 LVR and LVI Characteristics ................................................................................................... 30

Table 7-6 Internal RC Oscillator Characteristics ..................................................................................... 31

Table 7-7 Internal WDTRC Oscillator Characteristics ............................................................................. 31

Table 7-8 LCD Voltage Characteristics ................................................................................................... 32

Table 7-9 DC Characteristics .................................................................................................................. 34

Table 7-10 AC Characteristics ................................................................................................................ 35

Table 7-11 Serial I/O Characteristics ...................................................................................................... 36

Table 7-12 UART Characteristics ........................................................................................................... 37

Table 7-13 Data Retention Voltage in Stop Mode ................................................................................... 38

Table 7-14 Internal Flash Rom Characteristics ....................................................................................... 39

Table 7-15 Input/Output Capacitance ..................................................................................................... 39

Table 7-16 Main Clock Oscillator Characteristics ................................................................................... 40

Table 7-17 Sub Clock Oscillator Characteristics ..................................................................................... 41

Table 7-18 Main Oscillation Stabilization Characteristics........................................................................ 42

Table 7-19 Sub Oscillation Stabilization Characteristics ......................................................................... 42

Table 8-1 Absolute Maximum Ratings .................................................................................................... 48

Table 8-2 Recommended Operating Conditions ..................................................................................... 48

Table 8-3 A/D Converter Characteristics ................................................................................................ 49

Table 8-4 Power-On Reset Characteristics ............................................................................................. 49

Table 8-5 LVR and LVI Characteristics ................................................................................................... 50

Table 8-6 Internal RC Oscillator Characteristics ..................................................................................... 51

Table 8-7 Internal WDTRC Oscillator Characteristics ............................................................................. 51

Table 8-8 LCD Voltage Characteristics ................................................................................................... 52

Table 8-9 DC Characteristics .................................................................................................................. 53

Table 8-10 AC Characteristics ................................................................................................................ 54

Table 8-11 Serial I/O Characteristics ...................................................................................................... 55

Table 8-12 UART Characteristics ........................................................................................................... 56

Table 8-13 Data Retention Voltage in Stop Mode ................................................................................... 57

Table 8-14 Input/Output Capacitance ..................................................................................................... 58

Table 8-15 Main Clock Oscillator Characteristics ................................................................................... 58

Table 8-16 Sub Clock Oscillator Characteristics ..................................................................................... 59

Table 8-17 Main Oscillation Stabilization Characteristics........................................................................ 60

Table 8-18 Sub Oscillation Stabilization Characteristics ......................................................................... 60

Table 9-1 SFR Map Summary ................................................................................................................ 71

Table 9-2 SFR Map................................................................................................................................. 72

Table 10-1 Port Register Map ................................................................................................................. 79

Table 11-1 Interrupt Group Priority Level .............................................................................................. 102

Table 11-2 Interrupt Vector Address Table ........................................................................................... 105

Table 11-3 Interrupt Register Map ........................................................................................................ 112

Table 12-1 Clock Generator Register Map ........................................................................................... 118

Table 12-2 Basic Interval Timer Register Map ...................................................................................... 122

Table 12-3 Watch Dog Timer Register Map .......................................................................................... 124

Table 12-4 Watch Timer Register Map ................................................................................................. 127

Table 12-5 Timer 0 Operating Modes ................................................................................................... 129

Table 12-6 Timer 0 Register Map ......................................................................................................... 137

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Table 12-8 Timer 1 Register Map ......................................................................................................... 145


Table 12-10 Timer 2 Register Map ....................................................................................................... 155

Table 12-11 Timer 3 Operating Modes ................................................................................................. 159

Table 12-12 Timer 3 Register Map ....................................................................................................... 166

Table 12-13 Buzzer Frequency at 8 MHz ............................................................................................. 170

Table 12-14 Buzzer Driver Register Map .............................................................................................. 171

Table 12-15 SIO Register Map ............................................................................................................. 175

Table 12-16 ADC Register Map ............................................................................................................ 179

Table 12-17 Equations for Calculating Baud Rate Register Setting ...................................................... 184

Table 12-18 UART Register Map .......................................................................................................... 190

Table 12-19 Examples of UARTBD Settings for Commonly Used Oscillator Frequencies ................... 195

Table 12-20 LCD Register Map ............................................................................................................ 206

Table 12-21 LCD Frame Frequency ..................................................................................................... 208

Table 13-1 Peripheral Operation during Power Down Mode ................................................................. 210

Table 13-2 Power Down Operation Register Map ................................................................................ 214

Table 14-1 Reset State ......................................................................................................................... 215

Table 14-2 Boot Process Description.................................................................................................... 218

Table 14-3 Reset Operation Register Map ........................................................................................... 222

Table 16-1 Flash Memory Register Map ............................................................................................... 233

Table 16-2 Protection Area size ............................................................................................................ 236

April 20, 2012 Ver. 2.5 11

MC96F7816/C7816

MC96F7816/C7816

CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

WITH 12-BIT A/D CONVERTER

1. Overview

1.1 Description

The MC96F7816/C7816 is advanced CMOS 8-bit microcontroller with 16K bytes. This is powerful microcontroller which provides a highly flexible and cost effective solution to many embedded control applications.

This provides the following features : 16K bytes of FLASH, 256 bytes of IRAM, 256 bytes of XRAM , general purpose I/O, basic interval timer, watchdog timer, 8/16-bit timer/counter, carrier generation, programmable pulse generation, 8-bit PWM output, watch timer, buzzer driving port, SIO, UART, 12-bit A/D converter, LCD driver, onchip POR, LVR, LVI, on-chip oscillator and clock circuitry. The MC96F7816/C7816 also supports power saving modes to reduce power consumption.

FLASH MCU MASK MCU ROM XRAM IRAM ADC

I/O

PORT

Package

8ch 71 80 MQFP/LQFP MC96F7816 MC96C7816 16K bytes 256 bytes 256 bytes

1.2 Comparison of MC96F7816 and MC96C7816

Characteristic MC96F7816 MC96C7816

Program Memory

Operating Frequency

Characteristics

DC Characteristics: Sub

Operating Current(IDD3)

Internal RC Oscillator

Characteristics

16K byte Flash ROM

0.4~12MHz

50uA(typ)/80uA(max)

16K byte Mask ROM

0.4~10MHz

25uA(typ)/50uA(max)

4MHz ± 1.5% (T

A

= 0°C ~ +70°C)

4MHz ± 2.5% (T

A

= -20°C ~ +85°C)

4MHz ± 3.5% (T

A

= -40°C ~ +85°C)

4MHz ± 20% (T

A

= -40°C ~ +85°C)

LVR/LVI Characteristics 1.60V(LVR only)/ 2.00V/ 2.10V/

2.20V/ 2.32V/ 2.44V/ 2.59V/ 2.75V/

2.93V/ 3.14V/ 3.38V/ 3.67V/ 4.00V/

4.40V

VLC3 Characteristics In case of LCDCCR =

“000b”

- Spec: 0.9V/1.0V/1.1V(min/typ/max)

1.60V(LVR only)/ 2.05V/ 2.15V/ 2.25V/

2.37V/ 2.49V/ 2.64V/ 2.80V/ 2.98V/ 3.19V/

3.43V/ 3.77V/ 4.10V/ 4.50V

In case of LCDCCR =

“000b”

- Spec: 0.855V/0.95V/1.045V(min/typ/max)

NOTE) Refer to chapther 7/8

‟s electrical characteristics of MC96F7816/C7816 for detail contents, repectively.

12 April 20, 2012 Ver. 2.5

1.3 Features

• CPU

- 8 Bit CISC Core (8051 Compatible)

• ROM (FLASH) Capacity

- 16K bytes

- Flash with self read/write capability

- On chip debug and In-system programming (ISP)

- Endurance : 100,000 times

• 256 Bytes IRAM

• 256 Bytes XRAM

- (37 Bytes including LCD display RAM)

• General Purpose I/O (GPIO)

- Normal I/O : 27 Ports

(P0, P1, P2[7:4], P3[4:0], P9[3:2])

- LCD shared I/O : 44 Ports

(P2[3:0], P4, P5, P6, P7, P8)

• Basic Interval Timer (BIT)

- 8Bit × 1ch

• Watch Dog Timer (WDT)

- 8Bit × 1ch

- 6kHz internal RC oscillator

• Timer/ Counter

- 8Bit × 2ch (T0/T1), 16Bit x 2ch (T2/T3)

• Carrier Generation

- Carrier Generation (by T1), T3 Clock source

• Programmable Pulse Generation

- Pulse generation (by T2/T3)

• PWM

- 8Bit × 1ch (by T0)

• Watch Timer (WT)

- 3.91mS/0.25S/0.5S/1S/1M interval at 32.768kHz

• Buzzer

- 8Bit × 1ch

• SIO

- 8Bit × 1ch

• UART

- 8Bit × 1ch

• 12 Bit A/D Converter

- 8 Input channels

• LCD Driver

- 30 Segments and 8 Common terminals

- Internal or external resistor bias

- Capacitor bias (Voltage boost)

- 16-step contrast control

- Static, 2, 3, 4, 5, 6, and 8 duty selectable

- 1/2, 1/3, and 1/4 bias selectable

April 20, 2012 Ver. 2.5

MC96F7816/C7816

• Power On Reset

- Reset release level (1.4V)

• Low Voltage Reset

- 14 level detect

MC96F7816 (1.60V/ 2.00V/ 2.10V/ 2.20V/ 2.32V/

2.44V/ 2.59V/ 2.75V/ 2.93V/ 3.14V/

3.38V/ 3.67V/ 4.00V/ 4.40V)

MC96C7816 (1.60V/ 2.05V/ 2.15V/ 2.25V/ 2.37V/

2.49V/ 2.64V/ 2.80V/ 2.98V/ 3.19V/

3.43V/ 3.77V/ 4.10V/ 4.50V)

• Low Voltage Indicator

- 13 level detect

MC96F7816 (2.00V/ 2.10V/ 2.20V/ 2.32V/ 2.44V/

2.59V/ 2.75V/ 2.93V/ 3.14V/ 3.38V/

3.67V/ 4.00V/ 4.40V)

MC96C7816 (2.05V/ 2.15V/ 2.25V/ 2.37V/ 2.49V/

2.64V/ 2.80V/ 2.98V/ 3.19V/ 3.43V/

3.77V/ 4.10V/ 4.50V)

- External reference detect

• Interrupt Sources

- External Interrupts

(EXINT0~7, EINT8, EINT10, EINT12,

EINT13) (5)

- Timer( 0/1/2/3) (5)

- WDT (1)

- BIT (1)

- WT (1)

- SIO (1)

- UART(TX/RX) (2)

- ADC (1)

• Internal RC Oscillator

MC96F7816 Internal RC frequency

4MHz ± 1.5% (T

A

= 0°C ~ +70°C)

4MHz ± 2.5% (T

A

= -20°C ~ +85°C)

4MHz ± 3.5% (T

A

= -40°C ~ +85°C)

MC96C7816 Internal RC frequency

4MHz ± 20% (T

A

= -40°C ~ +85°C)

• Power Down Mode

- STOP, IDLE mode

• Operating Voltage and Frequency

MC96F7816 1.8V ~ 5.5V (@ 32 ~ 38kHz)

1.8V ~ 5.5V (@ 0.4 ~ 4.2MHz)

2.7V ~ 5.5V (@ 0.4 ~ 10.0MHz)

3.0V ~ 5.5V (@ 0.4 ~ 12.0MHz)

MC96C7816 1.8V ~ 5.5V (@ 32 ~ 38kHz)

1.8V ~ 5.5V (@ 0.4 ~ 4.2MHz)

2.7V ~ 5.5V (@ 0.4 ~ 10.0MHz)

- Voltage dropout converter included for core

13

MC96F7816/C7816

• Minimum Instruction Execution Time

MC96F7816 167nS (@ 12MHz main clock)

61

μS (@t 32.768kHz sub clock)

MC96C7816 200nS (@ 10MHz main clock)

61

μS (@t 32.768kHz sub clock)

• Operating Temperature: – 40 ~ + 85℃

• Oscillator Type

MC96F7816 0.4-12MHz crystal or ceramic for main clock

32.768kHz crystal for sub clock

MC96C7816 0.4-10MHz crystal or ceramic for main clock

32.768kHz crystal for sub clock

• Package Type

- 80 MQFP-1420

- 80 LQFP-1212

1.4 Ordering Information

Table 1-1 Ordering Information of MC96F7816/C7816

Device name

MC96F7816/C7816Q

MC96F7816/C7816L

ROM size

16K bytes

IRAM size

256 bytes

XRAM size

256 bytes

Package

80 MQFP

80 LQFP

14 April 20, 2012 Ver. 2.5

1.5 Development Tools

1.5.1 Compiler

MC96F7816/C7816

We do not provide the compiler. Please contact the third parties.

The core of MC96F7816 is Mentor 8051. And, device ROM size is smaller than 64K bytes. Developer can use all kinds of third party‟s standard 8051 compiler.

1.5.2 OCD emulator and debugger

The OCD (On Chip Debug) emulator supports ABOV Semiconductor‟s 8051 series MCU emulation.

The OCD interface uses two-wire interfacing between PC and MCU which i s attached to user‟s system. The

OCD can read or change the value of MCU internal memory and I/O peripherals. And the OCD also controls

MCU internal debugging logic, it means OCD controls emulation, step run, monitoring, etc.

The OCD Debugger program works on Microsoft-Windows NT, 2000, XP, Vista (32bit) operating system.

If you want to see more details, please refer to OCD debugger manual. You can download debugger S/W and manual from our web-site.

Connection:

- SCLK (MC96F7816 P23 port)

- SDATA (MC96F7816 P22 port)

OCD connector diagram: Connect OCD with user system

1

3

2

5

7

9

2

4

6

8

10

User VCC

User GND

SCLK

SDATA

Figure 1.1 OCD Debugger and Pin Description

April 20, 2012 Ver. 2.5 15

MC96F7816/C7816

1.5.3 Programmer

Single programmer:

PGMplus USB: It programs MCU device directly.

Figure 1.2 PGMplusUSB (Single Writer)

StandAlone PGMplus: It programs MCU device directly.

Figure 1.3 StandAlone PGMplus (Single Writer)

OCD emulator: It can write code in MCU device too, because OCD debugging supports ISP (In System

Programming).

It does not require additional H/W, except developer‟s target system.

Gang programmer:

It programs 8 MCU devices at once.

So, it is mainly used in mass production line.

Gang programmer is standalone type, it means it does not require host PC, after a program is downloaded from host PC to Gang programmer.

16

Figure 1.4 StandAlone Gang8 (for Mass Production)

April 20, 2012 Ver. 2.5

2. Block Diagram

AN0-AN3/P24-P27

AN4-AN7/P10-P13

AVREF

AVSS

T0O/PWM0O/P93

EINT10/P93

EC0/P92

REM/P07

T2O/PWM2O/P32

EINT12/P00

EC2/P02

T3O/PWM3O/P31

EINT13/P30

P00/EINT12

P01/EINT8

P02/EC2

P03/BUZO

P04/SCK

P05/SO

P06/SI

P07/REM

P10-P13/EINT0-EINT3/AN4-AN7

P14-P17/EINT4-EINT7

P20-P21/SEG33-SEG34

P22/SEG35/DSDA

P23/SEG36/DSCL

P24-P27/AN0-AN3

P30/EINT13/LVIREF

P31/T3O/PWM3O

P32/T2O/PWM2O

P33/TXD

P34/RXD

P40-P43/VLC0-VLC3

P44/CAPH

P45/CAPL

P46/COM0

P47/COM1/SEG0

DSDA DSCL

12 – Bit

A/D Converter

8 – Bit Timer 0

8 – Bit Timer 1

16 – Bit Timer 2

16 – Bit Timer 3

P0 Port

P1 Port

P2 Port

P3 Port

P4 Port

On-Chip Debug

M8051 Core

16K Bytes ROM

XRAM

(256 Bytes)

IRAM

(256 Bytes)

Basic Interval Timer

Power On Reset

Low Voltage Reset

Watchdog Timer

6kHz INT-RC OSC

INT-RC OSC

4MHz

Watch Timer

Voltage

Down

Converter

VDD VSS

Low Voltage

Indicator

Buzzer

SIO

UART

LCD Driver/

Controller

P9 Port

P8 Port

P7 Port

P6 Port

P5 Port

CLOCK/

SYSTEM

CONTROL

Figure 2.1 MC96F7816 Block Diagram

MC96F7816/C7816

LVIREF/P30

BUZO/P03

SCK/P04

SO/P05

SI/P06

TXD/P33

RXD/P34

COM0-COM1/P46-P47

COM2-COM7/P80-P85

SEG0/P47

SEG1-SEG8/P80-P87

SEG9-SEG16/P70-P77

SEG17-SEG24/P60-P67

SEG25-SEG32/P50-P57

SEG33-SEG36/P20-P23

VLC0-VLC3/P40-P43

P92/RESETB/EC0

P93/T0O/PWM0O/EINT10

P80-P85/COM2-COM7/SEG1-SEG6

P86-P87/SEG7-SEG8

P70-P77/SEG9-SEG16

P60-P67/SEG17-SEG24

P50-P57/SEG25-SEG32

RESETB/P92/EC0

VREG

SXOUT

SXIN

XIN

XOUT

April 20, 2012 Ver. 2.5 17

MC96F7816/C7816

3. Pin Assignment

P83/COM5/SEG4

P84/COM6/SEG5

P85/COM7/SEG6

P86/SEG7

P87/SEG8

P70/SEG9

P71/SEG10

P72/SEG11

P73/SEG12

P74/SEG13

P75/SEG14

P76/SEG15

P77/SEG16

P60/SEG17

P61/SEG18

P62/SEG19

P63/SEG20

P64/SEG21

P65/SEG22

P66/SEG23

P67/SEG24

P50/SEG25

P51/SEG26

P52/SEG27

7

8

9

5

6

3

4

1

2

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

MC96F7816Q

(80MQFP-1420)

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

64

63

62

61

60

59

43

42

41

XOUT

XIN

VDD

P07/REM

P06/SI

P05/SO

P04/SCK

P03/BUZO

P02/EC2

P01/EINT8

P00/EINT12

P34/RXD

P33/TXD

P32/T2O/PWM2O

P31/T3O/PWM3O

P17/EINT7

P16/EINT6

P15/EINT5

P14/EINT4

P13/EINT3/AN7

P12/EINT2/AN6

P11/EINT1/AN5

P10/EINT0/AN4

P30/EINT13/LVIREF

Figure 3.1 MC96F7816 80MQFP-1420 Pin Assignment

NOTE) On On-Chip Debugging, ISP uses P2[2:3] pin as DSDA, DSCL.

18 April 20, 2012 Ver. 2.5

MC96F7816/C7816

P85/COM7/SEG6

P86/SEG7

P87/SEG8

P70/SEG9

P71/SEG10

P72/SEG11

P73/SEG12

P74/SEG13

P75/SEG14

P76/SEG15

P77/SEG16

P60/SEG17

P61/SEG18

P62/SEG19

P63/SEG20

P64/SEG21

P65/SEG22

P66/SEG23

P67/SEG24

P50/SEG25

7

8

9

5

6

3

4

1

2

10

11

12

13

14

15

16

17

18

19

20

MC96F7816L

(80LQFP-1212)

56

55

54

53

52

60

59

58

57

46

45

44

43

42

41

51

50

49

48

47

VDD

P07/REM

P06/SI

P05/SO

P04/SCK

P03/BUZO

P02/EC2

P01/EINT8

P00/EINT12

P34/RXD

P33/TXD

P32/T2O/PWM2O

P31/T3O/PWM3O

P17/EINT7

P16/EINT6

P15/EINT5

P14/EINT4

P13/EINT3/AN7

P12/EINT2/AN6

P11/EINT1/AN5

Figure 3.2 MC96F7816 80LQFP-1212 Pin Assignment

NOTE) On On-Chip Debugging, ISP uses P2[2:3] pin as DSDA, DSCL.

April 20, 2012 Ver. 2.5 19

MC96F7816/C7816

4. Package Diagram

20

Figure 4.1 80-Pin MQFP Package

April 20, 2012 Ver. 2.5

MC96F7816/C7816

April 20, 2012 Ver. 2.5

Figure 4.2 80-Pin LQFP Package

21

MC96F7816/C7816

5. Pin Description

Table 5-1 Normal pin description

PIN

Name

I/O Function

P00 I/O Port 0 is a bit-programmable I/O port which can be

P01 configured as a schmitt-trigger input, a push-pull output, or an open-drain output.

P02

A pull-up resistor can be specified in 1-bit unit.

P03

P04

P05

P06

P07


P11 configured as a schmitt-trigger input, a push-pull output, or an open-drain output.

P12


P13

P14

P15

P16

P17


P21 configured as an input, a push-pull output, or an opendrain output.

P22


P23

P24

P25

P26

P27


P31 configured as an input (P30: Schmitt trigger input), a push-pull output, or an open-drain output.

P32


P33

P34

P40 I/O Port 4 is a bit-programmable I/O port which can be configured as an input, a push-pull output, or an open-

P41 drain output.

P42


P43

P44

P45

P46

P47

@RESET

Input

Input

Input

Input

Input

Shared with

EINT12

EINT8

EC2

BUZO

SCK

SO

SI

REM

EINT0/AN4

EINT1/AN5

EINT2/AN6

EINT3/AN7

EINT4

EINT5

EINT6

EINT7

SEG33

SEG34

SEG35/DSDA

SEG36/DSCL

AN0

AN1

AN2

AN3

EINT13/LVIREF

T3O/PWM3O

T2O/PWM2O

TXD

RXD

VLC0

VLC1

VLC2

VLC3

CAPH

CAPL

COM0

COM1/SEG0

22 April 20, 2012 Ver. 2.5

Table 5-1 Normal pin description (Continued)

PIN

Name

I/O Function



P52


P53

P54

P55

P56

P57



P62


P63

P64

P65

P66

P67


P71 configured as an input or a push-pull output.


P72

P73

P74

P75

P76

P77


P81 configured as an input or a push-pull output.


P82

P83

P84

P85

P86

P87



A pull-up resistor can be specified in 1-bit unit

MC96F7816/C7816

@RESET

Input

Input

Input

Input

Input

Shared with

SEG17

SEG18

SEG19

SEG20

SEG21

SEG22

SEG23

SEG24

SEG9

SEG10

SEG25

SEG26

SEG27

SEG28

SEG29

SEG30

SEG31

SEG32

SEG11

SEG12

SEG13

SEG14

SEG15

SEG16

COM2/SEG1

COM3/SEG2

COM4/SEG3

COM5/SEG4

COM6/SEG5

COM7/SEG6

SEG7

SEG8

RESETB/EC0

T0O/PWM0O/EINT10

April 20, 2012 Ver. 2.5 23

MC96F7816/C7816

LVIREF

VLC0 –

VLC3

CAPH

CAPL

COM0

COM1

COM2 –

COM7


PIN Name I/O

EINT10

Function

I/O External interrupt input and Timer 0 capture input

EINT12 I/O External interrupt input and Timer 2 capture input

EINT13

EINT0

EINT1

EINT2

I/O External interrupt input and Timer 3 capture input

I/O External interrupt inputs

EINT3

EINT4

EINT5

EINT6

EINT7

EINT8

T0O

I/O Timer 0 interval output

T2O

T3O

REM



I/O Carrier generation output

PWM0O I/O Timer 0 PWM output

PWM2O I/O Timer 2 pulse output

PWM3O I/O Timer 3 pulse output

EC0

EC2

BUZO

SCK

SO

SI

TXD

RXD

AN0 –AN3

I/O Timer 0 event count input

I/O Timer 2 event count input

I/O Buzzer signal output

I/O Serial clock input/output

I/O Serial data output

I/O Serial data input

I/O UART data output

I/O UART data input

I/O A/D converter analog input channels

AN4

–AN7

I/O Low Voltage Indicator reference voltage

I/O LCD bias voltage pins

I/O Capacitor terminals for voltage booster

I/O LCD common signal output

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

Input

@RESET

Input

Input

Input

Input

Input

Input

Shared with

P93/T0O/PWM0O

P00

P30/LVIREF

P10/AN4

P11/AN5

P12/AN6

P13/AN7

P14

P15

P16

P17

P01

P93/PWM0O/EINT10

P32/PWM2O

P31/PWM3O

P07

P93/T0O/EINT10

P32/T2O

P31/T3O

P92/RESETB

P02

P03

P04

P05

P06

P33

P34

P24

–P27

P10/EINT0 –

P13/EINT3

P30/EINT13

P40 –P43

Input

Input

P44

P45

P46

P47/SEG0

P80/SEG1 –

P85/SEG6

24 April 20, 2012 Ver. 2.5

MC96F7816/C7816


PIN

Name

SEG0

SEG1 –

SEG6

SEG7

–

SEG8

SEG9 –

SEG16

SEG17 –

SEG24

SEG25

–

SEG32

SEG33 –

SEG34

SEG35

I/O

I/O

Function

LCD segment signal output

SEG36

RESETB

I/O System reset pin with a pull-up resistor when it is selected as the RESETB by “CONFIGURE OPTION”

DSDA I/O On chip debugger data input/output

(NOTE2,3)

DSCL I/O On chip debugger clock input

(NOTE2,3)

XIN,

XOUT

I/O

Main oscillator pins

SXIN,

SXOUT

I/O

Sub oscillator pins

VREG

–

AVREF

AVSS

VDD,

VSS

–

–

–

Regulator voltage output for sub clock

0.1

μF capacitor needed

A/D converter reference voltage

A/D converter ground

Power input pins

@RESET

Input

Input

Input

Input

Input

Input

–

–

–

–

Shared with

P47/COM1

P80/COM2 –

P85/COM7

P86 –P87

P70

–P77

P60 –P67

P50

–P57

P20 –P21

P22/DSDA

P23/DSCL

P92/EC0

P22/SEG35

P23/SEG36

–

–

–

–

–

–

Notes) 1. The P92/RESETB/EC0 pin is configured as one of the P92/EC0 and the RESETB pin by the

“CONFIGURE OPTION”.

2. If the P22/SEG35/DSDA and P23/SEG36/DSCL pins are connected to an emulator during reset or

power-on reset, the pins are automatically configured as the debugger pins.

3. The P22/SEG35/DSDA and P23/SEG36/DSCL pins are configured as inputs with internal pull-up

resistor only during the reset or power-on reset.

April 20, 2012 Ver. 2.5 25

MC96F7816/C7816

6. Port Structures

6.1 General Purpose I/O Port

PULL-UP

REGISTER

OPEN DRAIN

REGISTER

DATA

REGISTER

SUB-FUNC DATA OUTPUT

SUB-FUNC ENABLE

SUB-FUNC DIRECTION

DIRECTION

REGISTER

1

MUX

0

0

MUX

1

Level Shift (1.8V to ExtVDD)

Level Shift (ExtVDD to 1.8V)

V DD

V DD V DD

PAD

CMOS or

Schmitt Level

Input

PORTx INPUT or

SUB-FUNC DATA INPUT

ANALOG CHANNEL

ENABLE

ANALOG INPUT

Figure 6.1 General Purpose I/O Port

26 April 20, 2012 Ver. 2.5

6.2 External Interrupt I/O Port

MC96F7816/C7816

Level Shift (1.8V to ExtVDD)

Level Shift (ExtVDD to 1.8V)

V DD

PULL-UP

REGISTER

OPEN DRAIN

REGISTER

DATA

REGISTER

SUB-FUNC DATA OUTPUT

SUB-FUNC ENABLE

SUB-FUNC DIRECTION

DIRECTION

REGISTER

EXTERNAL

INTERRUPT

0

MUX

1

INTERRUPT

ENABLE

1

MUX

0

Q D

VDD r

CP

FLAG

CLEAR

PORTx INPUT or

SUB-FUNC DATA INPUT

POLARITY

REG.

V DD

0

MUX

1 Q D r

CP

DEBOUNCE

CLK

DEBOUNCE

ENABLE

CMOS or

Schmitt Level

Input

V DD

ANALOG CHANNEL

ENABLE

ANALOG INPUT

PAD

Figure 6.2 External Interrupt I/O Port

April 20, 2012 Ver. 2.5 27

MC96F7816/C7816

7. MC96F7816 Electrical Characteristics

7.1 Absolute Maximum Ratings

Table 7-1 Absolute Maximum Ratings

Parameter

Supply Voltage

Symbol

VDD

Rating

-0.3 ~ +6.5

Unit

V

Note

–

V

I

V

O

-0.3 ~ VDD+0.3

-0.3 ~ VDD+0.3

V

V

Voltage on any pin with respect to VSS

Normal Voltage Pin

I

OH

∑ I

OH

I

OL

∑ I

OL

-10

-80

60

120 mA

Maximum current output sourced by (I

OH

per

I/O pin) mA Maximum current ( ∑ I

OH

) mA Maximum current sunk by (I mA Maximum current ( ∑ I

OL

)

OL

per I/O pin)

Total Power

Dissipation

P

T

600 mW

–

Storage Temperature T

STG

-65 ~ +150 °C

–

Note) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

7.2 Recommended Operating Conditions

Table 7-2 Recommended Operating Conditions

Parameter

Supply Voltage

Operating Temperature

Symbol

VDD

T

OPR f

X

Conditions

= 32 ~ 38kHz f

X

= 0.4 ~ 4.2MHz f

X

= 0.4 ~ 10.0MHz f

X

= 0.4 ~ 12.0MHz

VDD= 1.8 ~ 5.5V

SX-tal

X-tal,

Internal RC

MIN

1.8

1.8

2.7

3.0

-40

TYP

–

–

–

–

–

(T

A

= -40°C ~ +85°C)

MAX Unit

5.5

5.5

5.5

5.5

85

V

°C

28 April 20, 2012 Ver. 2.5

MC96F7816/C7816

7.3 A/D Converter Characteristics

Table 7-3 A/D Converter Characteristics

Parameter

Resolution

Integral Linear Error

Differential Linearity

Error

Zero Offset Error

Full Scale Error

Conversion Time

Symbol

–

ILE

DLE

ZOE

FSE t

CON

Conditions

AVREF= 2.7V fx= 8MHz

–

– 5.5V

(T

A

= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V)

MIN

–-

–

TYP

12

–

MAX

–

±4

Unit bit

12bit resolution, fx=8MHz

–

–

–

20

–

–

–

–

±1

±3

±3

–

LSB

μS

Analog Input Voltage V

AN

– AVSS – AVREF

Analog Reference

Voltage

Analog Ground

Voltage

Analog Input Leakage

Current

AVREF

AVSS

I

AN

–

–

AVREF= 5.12V

1.8

VSS

–

–

–

–

VDD

VSS+0.3

10

V

μA

ADC Operating Current I

ADC

Enable

Disable

VDD = 5.12V

–

–

1

–

2

0.1 mA

μA

Notes) 1. Zero offset error is the difference between 000000000000 and the converted output for zero input voltage(VSS);

2. Full scale error is the difference between 111111111111 and the converted output for full-scale input voltage (AVREF)

7.4 Power-On Reset Characteristics

Table 7-4 Power-On Reset Characteristics

Parameter

RESET Release Level

VDD Voltage Rising Time

POR Current

Symbol

V

POR t

R

I

POR

(T

A

= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V)

Conditions

–

–

–

MIN

–

0.05

–

TYP

1.4

–

0.2

MAX

–

30.0

–

Unit

V

V/mS

μA

April 20, 2012 Ver. 2.5 29

MC96F7816/C7816

7.5 Low Voltage Reset and Low Voltage Indicator Characteristics

Table 7-5 LVR and LVI Characteristics

Parameter

Detection Level

Hysteresis

Minimum Pulse Width

LVR and LVI Current

Symbol

V

V

LVR

LVI

△V t

LW

I

BL

Conditions

Enable (Both)

–

–

Enable (One of two)

Disable (Both)

(T

A

= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V)

The LVR can select all levels but

LVI can select other levels except

1.60V.

VDD= 3V

MIN

–

1.85

1.95

2.05

2.17

2.29

2.39

2.55

2.73

2.94

3.18

3.37

3.70

4.10

–

100

–

–

–

TYP

1.60

2.00

2.10

2.20

2.32

2.44

2.59

2.75

2.93

3.14

3.38

3.67

4.00

4.40

10

–

8.0

6.0

–

Unit

V mV

μS

μA

3.34

3.58

3.97

4.30

4.70

100

–

14.0

12.0

0.1

MAX

1.75

2.15

2.25

2.35

2.47

2.59

2.79

2.95

3.13

30 April 20, 2012 Ver. 2.5

MC96F7816/C7816

7.6 Internal RC Oscillator Characteristics

Table 7-6 Internal RC Oscillator Characteristics

Parameter

Frequency

Tolerance

Clock Duty Ratio

Stabilization Time

IRC Current

Symbol f

IRC

–

TOD t

WDTS

I

IRC

(T

A

= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V)

Conditions

–

T

A

= 0°C

– +70°C

VDD= 2.0V

– 5.5V

T

A

= -20°C – +85°C

MIN TYP MAX

–

-1.5

-2.5

T

A

= -40°C – +85°C -3.5

4.0

–

–

–

–

+1.5

+2.5

+3.5

Enable

Disable

–

–

40

–

–

–

50

–

0.5

–

60

100

–

0.1

Unit

MHz

%

%

%

%

μS mA

μA

7.7 Internal Watch-Dog Timer RC Oscillator Characteristics

Table 7-7 Internal WDTRC Oscillator Characteristics

Parameter

Frequency

Stabilization Time

WDTRC Current

Symbol

I f

WDTRC t

WDTS

WDTRC

(T

A

= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V)

Enable

Conditions

–

–

Disable

MIN

3

–

–

–

TYP

6

–

1

–

MAX

9

1

–

0.1

Unit kHz mS

μA

April 20, 2012 Ver. 2.5 31

MC96F7816/C7816

7.8 LCD Voltage Characteristics

Table 7-8 LCD Voltage Characteristics

Parameter Symbol

(T

A

= -40°C ~ +85°C, VDD= 2.0V ~ 5.5V, VSS= 0V)

Conditions

Voltage booster disabled( Resister bias),

1/4 bias

LCDCCR=0000b

Min

Typx0.95

Typ

1/4xVDD

1.000

Max

Typx1.05

Units

V

LCDCCR=0001b

1.045

LCDCCR=0010b

1.090

LCDCCR=0011b

1.135

LCDCCR=0100b

1.180

LCDCCR=0101b

1.225

LCD Voltage VLC3

Voltage booster enabled,

1/2,1/3

bias

LCDCCR=0110b

LCDCCR=0111b

LCDCCR=1000b

LCDCCR=1001b

Typx0.9

1.270

1.315

1.360

1.405

Typx1.1 V

LCDCCR=1010b

1.450

LCDCCR=1011b

1.500

LCDCCR=1100b

1.550

LCDCCR=1101b

1.600

LCDCCR=1110b 1.650

LCD Mid Bias

Voltage

VLC0/1/2

VLC0/1

VLC2

LCDCCR=1111b


1/2 bias, No panel load,

VDD=3V



VDD=3V

VLC1 Voltage booster disabled,

VDD=2.7V to 5.5V,

VLC2

1/4 bias, LCD clock = 0Hz,

VLC3 VLC0=VDD

Typx0.9

Typx0.9

Typx0.9

Typ-0.2

Typ-0.2

Typ-0.2

1.700

2xVLC3

3xVLC3

2xVLC3

0.75xVDD

0.5xVDD

0.25xVDD

Typx1.1

Typx1.1

Typx1.1

Typ+0.2

Typ+0.2

Typ+0.2

V

V

V

LCD Driver Output

Impedance

RLO VLCD=3V, ILOAD=±10uA

–

5 10 kΩ

LCD Bias Dividing

Resistor

LCD Block Current

RLCD

ILCD

Internal resistor mode,

TA = 25°C

Voltage booster mode,

VDD=3V, VLCD=3.15V,

1/3Bias

40

–

60

3

80

6

Note) It is middle output voltage when the VDD and the V

LC0

node are connected in the case of resister bias. uA

32 April 20, 2012 Ver. 2.5

MC96F7816/C7816

Table 7-8 LCD Voltage Characteristics(Condinued)


(T

A

= -40°C ~ +85°C, VDD= 2.0V ~ 5.5V, VSS= 0V)

Conditions

LCDCCR=0000b

Min Typ

0.856

Max Units

LCDCCR=0001b

0.887

LCDCCR=0010b

0.918

LCDCCR=0011b

0.949

LCDCCR=0100b

0.980

LCDCCR=0101b

1.011

LCDCCR=0110b

1.052

LCD Voltage VLC3


1/4 bias

LCDCCR=0111b

LCDCCR=1000b

Typx0.9

1.073

1.104

Typx1.1

V

LCDCCR=1001b

1.135

LCDCCR=1010b

1.166

LCDCCR=1011b

1.197

LCDCCR=1100b

1.228

LCDCCR=1101b 1.259

LCDCCR=1110b 1.290

VLC0

LCDCCR=1111b 1.321

Typx0.9 4xVLC3 Typx1.1

LCD Mid Bias

Voltage

VLC1

VLC2



VDD=3V



V


LC0

node are connected in the case of resister bias.

April 20, 2012 Ver. 2.5 33

MC96F7816/C7816

7.9 DC Characteristics

Table 7-9 DC Characteristics

Parameter

Input High Voltage

Input Low Voltage

Output High

Voltage

Output Low

Voltage

Input High Leakage

Current

Input Low Leakage

Current

Symbol

V

IH1

V

IH2

V

IL1

V

IL2

V

OH1

V

OH2

V

OL

I

IH

(T

A

= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V, f

XIN

= 12MHz)

Conditions MIN TYP MAX Unit

P0x, P1x, P30, P9x, RESETB

All input pins except V

IH1



IL1

VDD= 4.5V, I

OH

= -2mA;

All output ports except V

OH2

;

0.8VDD

0.7VDD

–

–

VDD-1.0

–

–

–

–

–

VDD

VDD

0.2VDD V

0.3VDD V

–

V

V

V

VDD-1.0

– –

V VDD= 3.0V, I

OH

= -10mA; P07

VDD= 4.5V, I

OL

= 15mA;

All output ports

– – 1.0 V

All input ports

– –

1

μA

I

IL

-1

– – μA

Pull-Up Resistor

OSC Feedback

Resistor

Supply Current

R

R

I

I

I

R

R

PU1

PU2

X1

X2

DD1

DD3

DD4

(RUN)

I

DD2

(IDLE)

I

DD5

All input ports

VI=0V,

T

A

= 25°C

All Input ports

VI=0V,

T

A

= 25°C

RESETB

VDD=5.0V

VDD=3.0V

VDD=5.0V

VDD=3.0V

XIN= VDD, XOUT= VSS

T

A

= 25°C, VDD= 5V

SXIN=VDD, SXOUT=VSS

T

A

= 25°C ,VDD=5V f

XIN

= 12MHz, VDD= 5V±10% f

XIN

= 10MHz, VDD= 3V±10% f

IRC

= 4MHz, VDD= 5V±10% f

XIN

= 12MHz, VDD= 5V±10% f

XIN

= 10MHz, VDD= 3V±10% f

IRC

= 4MHz, VDD= 5V±10%

Sub RUN f

SUB

= 32.768kHz

VDD= 3V±10%

T

A

= 25°C,PSAVE=1 Sub IDLE

STOP, VDD= 5V±10%, T

A

= 25°C

25

50

150

300

600

1750

–

–

–

–

–

–

–

–

–

50

100

250

500

1200

3500

3.0

2.2

1.4

2.0

1.3

0.6

50.0

4.0

0.5

100

200

400

700

2000

7000

6.0

4.4

2.8

4.0

2.6

1.2

80.0

8.0

3.0 k k k

Ω

Ω

Ω mA mA

μA

μA

μA

Notes) 1. Where the f

XIN

is an external main oscillator, f

SUB

is an external sub oscillator, the f

IRC

is an internal RC oscillator, and the fx is the selected system clock.

2. All supply current items don ‟t include the current of an internal Watch-dog timer RC (WDTRC) oscillator and a peripheral block.

3. All supply current items include the current of the power-on reset (POR) block.

34 April 20, 2012 Ver. 2.5

7.10 AC Characteristics

Table 7-10 AC Characteristics

Parameter

RESETB Input Low

Width

Interrupt Input High,

Low width

External Counter Input

High, Low Width

External Counter

Transition Time

Symbol t

RST

Conditions

Input, VDD= 5V t

IWH

, t

IWL

All interrupt, VDD= 5V t

ECWH

, t

ECWL

ECn, VDD = 5 V

(n=0, 2) t

REC

, t

FEC

ECn, VDD = 5 V

(n=0, 2) t RST

RESETB

External

Interrupt

ECn

MC96F7816/C7816

(T

A

= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V)

MIN TYP MAX Unit

10

– – μS

200

200

20

–

–

–

–

–

– nS

0.2 VDD

Figure 7.1 Input Timing for RESETB t

IWL t

IWH

0.8 VDD

0.2 VDD

Figure 7.2 Input Timing for External Interrupts t FEC t

ECWL t

REC t

ECWH

Figure 7.3 Input Timing for EC0, EC2

April 20, 2012 Ver. 2.5 35

SO

36

MC96F7816/C7816

7.11 Serial I/O Characteristics

Table 7-11 Serial I/O Characteristics

Parameter

SCK Cycle Time

SCK High, Low width

SI Setup Time to SCK

High

SI Hold Time to SCK

High

Output Delay for SCK to

SO

Symbol t

KCY t

KH t t t

, t

SIK

KSI

KL

KSO

Conditions

External SCK source

Internal SCK source

External SCK source

Internal SCK source

External SCK source

Internal SCK source

External SCK source

Internal SCK source

External SCK source

Internal SCK source t

KL t

KH

(T

A

= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V)

MIN

1,000

1,000

500 t

KCY

/2-50

250

250

400

400

TYP

–

MAX

–

Unit nS nS nS nS

– –

300

250 nS

SCK t SIK t KSI

SI t

KSO

Output Data

Figure 7.4 Serial Interface Data Transfer Timing

April 20, 2012 Ver. 2.5

7.12 UART Characteristics

Table 7-12 UART Characteristics

Parameter

Serial Port Clock Cycle Time

Output Data Setup to Clock Rising Edge

Clock Rising Edge to Input Data Valid

Output Data Hold after Clock Rising Edge

Input Data Hold after Clock Rising Edge

Serial Port Clock High, Low Level Width t

HIGH

MC96F7816/C7816

Symbol t

(T

A

= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, f

XIN

=11.1MHz)

SCK

MIN

1250 t

TYP

CPU

x 16

MAX

1650

Unit nS t t t t

S1

S2

H1

H2 t

590

–

CPU

- 50

0 t

CPU t

x 13

–

CPU

–

–

590

–

– nS nS nS nS t

HIGH

, t

LOW

470 t

CPU

x 8 970 nS t

SCK t

LOW

Shift Clock

Data Out

Data In

Figure 7.5 Waveform for UART Timing Characteristics t

SCK t S1

D0 t

S2

Valid t

H1

D1 D2 D3 D4 D5

Valid t H2

Valid Valid Valid

Figure 7.6 Timing Waveform for the UART Module

Valid

D6

Valid

D7

Valid

April 20, 2012 Ver. 2.5 37

MC96F7816/C7816

7.13 Data Retention Voltage in Stop Mode

Table 7-13 Data Retention Voltage in Stop Mode

Parameter

Data Retention Supply Voltage

Symbol

V

DDDR

Conditions

–

(T

A

= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V)

MIN TYP MAX Unit

1.8 – 5.5 V

Data Retention Supply Current – – 1 μA I

DDDR

VDDDR= 1.8V,

(T

A

= 25°C), Stop mode

~ ~

Stop Mode

Idle Mode

(Watchdog Timer Active)

Normal

Operating Mode

V

DD

~ ~

Data Retention

V

DDDR

Execution of

STOP Instruction

0.8V

DD

INT Request t

WAIT

VDD

RESETB

NOTE: tWAIT is the same as (the selected bit overflow of BIT) X 1/(BIT Clock)

Figure 7.7 Stop Mode Release Timing when Initiated by an Interrupt

RESET

Occurs

~ ~

~ ~

Stop Mode

Data Retention

V

DDDR

Execution of

STOP Instruction

0.2 VDD

0.8 VDD

TWAIT

NOTE : tWAIT is the same as (4096 X 4 X 4/f IRC ) = (16.4 mS at fx=1MHz).

Figure 7.8 Stop Mode Release Timing when Initiated by RESETB

Oscillation

Stabillization Time

Normal

Operating Mode

38 April 20, 2012 Ver. 2.5

MC96F7816/C7816

7.14 Internal Flash Rom Characteristics

Table 7-14 Internal Flash Rom Characteristics

(T

A

= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V)

Parameter

Sector Write Time

Sector Erase Time

Hard-Lock Time

Page Buffer Reset Time

Symbol t

FSW t

FSE t

FHL t

FBR

Condition

–

–

–

–

MIN

–

–

–

–

TYP

2.5

2.5

2.5

–

MAX

2.7

2.7

2.7

5

Unit mS

μS

Flash Programming Frequency

Endurance of Write/Erase f

PGM

NF

WE

–

–

0.4

–

–

–

– MHz

100,000 Times

Note) During a flash operation, SCLK[1:0] of SCCR must be set to “00” or “01” (INT-RC OSC or Main X-TAL for system clock).

7.15 Input/Output Capacitance

Table 7-15 Input/Output Capacitance

Parameter

Input Capacitance

Output Capacitance

I/O Capacitance

Symbol

C

IN

C

OUT

C

IO

Condition fx= 1MHz

Unmeasured pins are connected to VSS

MIN

(T

A

= -40°C ~ +85°C, VDD= 0V)

TYP MAX Unit

– –

10 pF

April 20, 2012 Ver. 2.5 39

MC96F7816/C7816

7.16 Main Clock Oscillator Characteristics

Table 7-16 Main Clock Oscillator Characteristics

Oscillator

Crystal

Ceramic Oscillator

External Clock

Parameter

Main Oscillation Frequency


XIN Input Frequency

Condition

1.8V

– 5.5V

2.7V – 5.5V

3.0V

– 5.5V

1.8V

– 5.5V

2.7V – 5.5V

3.0V – 5.5V

1.8V

– 5.5V

2.7V – 5.5V

3.0V – 5.5V

(T

A

= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V)

MIN

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

0.4

TYP

–

–

–

–

–

–

–

–

–

MAX

4.2

10.0

12.0

4.2

10.0

12.0

4.2

10.0

12.0

Unit

MHz

MHz

MHz

XIN XOUT

C1 C2

Figure 7.9 Crystal/Ceramic Oscillator

XIN XOUT

External

Clock

Source

Open

Figure 7.10 External Clock

40 April 20, 2012 Ver. 2.5

7.17 Sub Clock Oscillator Characteristics

Table 7-17 Sub Clock Oscillator Characteristics

Oscillator

Crystal

External Clock

Parameter

Sub oscillation frequency

SXIN input frequency

MC96F7816/C7816

Condition

1.8V – 5.5V

(T

A

= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V)

MIN

32

TYP

32.768

MAX

38

Unit kHz

32 – 100 kHz

SXIN SXOUT VREG

0.1uF

C1 C2

Figure 7.11 Crystal Oscillator

SXIN SXOUT

External

Clock

Source

Open


April 20, 2012 Ver. 2.5 41

MC96F7816/C7816

7.18 Main Oscillation Stabilization Characteristics

Table 7-18 Main Oscillation Stabilization Characteristics

Oscillator

Crystal

Ceramic

External Clock

Parameter fx > 1MHz

Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range. f

XIN

= 0.4 to 12MHz

XIN input high and low width (t

XH

, t

XL

)

1/f XIN t XL

(T

A

= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V)

MIN TYP MAX Unit

– – 60 mS

–

42

–

–

10

1250 mS nS t XH

XIN

0.8VDD

0.2VDD

Figure 7.13 Clock Timing Measurement at XIN

7.19 Sub Oscillation Characteristics

Table 7-19 Sub Oscillation Stabilization Characteristics

Oscillator

Crystal

External Clock

Parameter

–

SXIN Input High and Low Width (t

XH

, t

XL

)

1/f SUB t XL

(T

A

= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V)

MIN

–

5

TYP

–

–

MAX

10

15

Unit

S

μS t XH

SXIN

0.8VDD

0.2VDD

Figure 7.14 Clock Timing Measurement at SXIN

42 April 20, 2012 Ver. 2.5

7.20 Operating Voltage Range

(f XIN =0.4 to 12MHz)

12.0MHz

10.0MHz

32.768KHz

4.2MHz

0.4MHz

MC96F7816/C7816

(f SUB =32 to 38KHz)

1.8

2.7

3.0

Supply voltage (V)

5.5

1.8

Figure 7.15 Operating Voltage Range

Supply voltage (V)

5.5

April 20, 2012 Ver. 2.5 43

MC96F7816/C7816

7.21 Recommended Circuit and Layout

VDD

VSS

0.1uF

This 0.1uF capacitor should be within { }

PCB layout.

VDD VCC

+

0.1uF

DC Power

I/O

XIN

XOUT

SXIN

SXOUT

VREG

VCC

High-Current Part

Infrared LED,

{ } etc

The MCU power line (VDD and VSS)

{ } the PCB layout.

0.01uF

{ }

X-tal

The main and sub crystal should be as close by the MCU as possible.

C1

C2

32.768kHz

0.1uF

The load capacitors of the sub clock

- C1, C2: C

L

x 2 ± 15%

- C

L

= (C1 x C2)/(C1 + C2) - Cstray

- C

L

: the specific capacitor value of crystal

- Cstray: the parasitic capacitor of a PCB (1pF – 1.5pF)

The VREG pin is the output of an internal regulator for sub oscillator.

So, this 0.1uF capacitor is needed and should be as close by the MCU as possible if the sub clock is used for system.

Figure 7.16 Recommended Circuit and Layout

44 April 20, 2012 Ver. 2.5

MC96F7816/C7816

7.22 Typical Characteristics

These graphs and tables provided in this section are only for design guidance and are not tested or guaranteed.

In graphs or tables some data are out of specified operating range (e.g. out of specified VDD range). This is only for information and devices are guaranteed to operate properly only within the specified range.

The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and

(mean - 3σ) respectively where σ is standard deviation. mA

3.50

3.00

2.50

2.00

1.50

1.00

0.50

0.00

12MHz -40℃

12MHz +25℃

12MHz +85℃

IRC 4MHz -40℃

IRC 4MHz +25℃

IRC 4MHz +85℃

2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V

Figure 7.17 RUN (IDD1) Currnet mA

2.50

2.00

1.50

1.00

0.50

0.00

2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V

Figure 7.18 IDLE (IDD2) Current

12MHz -40℃

12MHz +25℃

12MHz +85℃

IRC 4MHz -40℃

IRC 4MHz +25℃

IRC 4MHz +85℃

April 20, 2012 Ver. 2.5 45

MC96F7816/C7816 uA

70.0

60.0

50.0

40.0

30.0

20.0

10.0

0.0

2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V

Figure 7.19 SUB RUN (IDD3) Current uA

7.00

6.00

5.00

4.00

3.00

2.00

1.00

0.00

2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V

Figure 7.20 SUB IDLE (IDD4) Currnet

-40℃

+25℃

+85℃

-40℃

+25℃

+85℃

46 April 20, 2012 Ver. 2.5

uA

2.50

2.00

1.50

1.00

0.50

0.00

2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V

Figure 7.21 STOP (IDD5) Current

MC96F7816/C7816

-40℃

+25℃

+85℃

April 20, 2012 Ver. 2.5 47

MC96F7816/C7816

8. MC96C7816 Electrical Characteristics(Mask Version)

8.1 Absolute Maximum Ratings

Table 8-1 Absolute Maximum Ratings

Parameter

Supply Voltage

Symbol

VDD

Rating

-0.3 ~ +6.5

Unit

V

Note

–

V

I

V

O

-0.3 ~ VDD+0.3

-0.3 ~ VDD+0.3

V

V

Voltage on any pin with respect to VSS

Normal Voltage Pin

I

OH

∑ I

OH

I

OL

∑ I

OL

-10

-80

60

120 mA

Maximum current output sourced by (I

OH

per

I/O pin) mA Maximum current ( ∑ I

OH

) mA Maximum current sunk by (I mA Maximum current ( ∑ I

OL

)

OL

per I/O pin)

Total Power

Dissipation

P

T

600 mW

–

Storage Temperature T

STG

-65 ~ +150 °C

–

Note) Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

8.2 Recommended Operating Conditions

Table 8-2 Recommended Operating Conditions

Parameter

Supply Voltage

Operating Temperature

Symbol

VDD

T

OPR f

X

Conditions

= 32 ~ 38kHz f

X

= 0.4 ~ 4.2MHz f

X

= 0.4 ~ 10.0MHz

VDD= 1.8 ~ 5.5V

SX-tal

X-tal,

Internal RC

MIN

1.8

1.8

2.7

-40

TYP

–

–

–

–

(T

A

= -40°C ~ +85°C)

MAX Unit

5.5

5.5

5.5

85

V

°C

48 April 20, 2012 Ver. 2.5

MC96F7816/C7816

8.3 A/D Converter Characteristics

Table 8-3 A/D Converter Characteristics

Parameter

Resolution

Integral Linear Error

Differential Linearity

Error

Zero Offset Error

Full Scale Error

Conversion Time

Symbol

–

ILE

DLE

ZOE

FSE t

CON

Conditions

AVREF= 2.7V fx= 8MHz

–

– 5.5V

(T

A

= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V)

MIN

–-

–

TYP

12

–

MAX

–

±4

Unit bit

12bit resolution, fx=8MHz

–

–

–

20

–

–

–

–

±1

±3

±3

–

LSB

μS

Analog Input Voltage V

AN

– AVSS – AVREF

Analog Reference

Voltage

Analog Ground

Voltage

Analog Input Leakage

Current

AVREF

AVSS

I

AN

–

–

AVREF= 5.12V

1.8

VSS

–

–

–

–

VDD

VSS+0.3

10

V

μA

ADC Operating Current I

ADC

Enable

Disable

VDD = 5.12V

–

–

1

–

2

0.1 mA

μA

Notes) 1. Zero offset error is the difference between 000000000000 and the converted output for zero input voltage(VSS);

2. Full scale error is the difference between 111111111111 and the converted output for full-scale input voltage (AVREF)

8.4 Power-On Reset Characteristics

Table 8-4 Power-On Reset Characteristics

Parameter

RESET Release Level

VDD Voltage Rising Time

POR Current

Symbol

V

POR t

R

I

POR

(T

A

= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V)

Conditions

–

–

–

MIN

–

0.05

–

TYP

1.4

–

0.2

MAX

–

30.0

–

Unit

V

V/mS

μA

April 20, 2012 Ver. 2.5 49

MC96F7816/C7816

8.5 Low Voltage Reset and Low Voltage Indicator Characteristics

Table 8-5 LVR and LVI Characteristics

Parameter

Detection Level

Hysteresis

Minimum Pulse Width

LVR and LVI Current

Symbol

V

V

LVR

LVI

△V t

LW

I

BL

Conditions

Enable (Both)

–

–

Enable (One of two)

Disable (Both)

(T

A

= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V)

The LVR can select all levels but

LVI can select other levels except

1.60V.

VDD= 3V

MIN

–

1.85

1.95

2.05

2.17

2.29

2.39

2.55

2.73

2.94

3.18

3.37

3.70

4.10

–

100

–

–

–

TYP

1.60

2.05

2.15

2.25

2.37

2.49

2.64

2.80

2.98

3.19

3.43

3.77

4.10

4.50

10

–

8.0

6.0

–

Unit

V mV

μS

μA

3.44

3.68

4.17

4.50

4.90

100

–

14.0

12.0

0.1

MAX

1.75

2.25

2.35

2.45

2.57

2.69

2.89

3.05

3.23

50 April 20, 2012 Ver. 2.5

MC96F7816/C7816

8.6 Internal RC Oscillator Characteristics

Table 8-6 Internal RC Oscillator Characteristics

Parameter

Frequency

Tolerance

Clock Duty Ratio

Stabilization Time

IRC Current

Symbol f

IRC

–

TOD t

WDTS

I

IRC

Conditions

–

VDD= 2.0V

– 5.5V

–

–

Enable

Disable

(T

A

= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V)

MIN TYP MAX

–

4.0

–

-20

–

+20

40

–

–

–

50

–

0.5

–

60

100

–

0.1

Unit

MHz

%

%

μS mA

μA

8.7 Internal Watch-Dog Timer RC Oscillator Characteristics

Table 8-7 Internal WDTRC Oscillator Characteristics

Parameter

Frequency

Stabilization Time

WDTRC Current

Symbol f

I t

WDTRC

WDTS

WDTRC

(T

A

= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V)

Enable

Disable

Conditions

–

–

MIN

3

–

–

–

TYP

6

–

1

–

MAX

9

1

–

0.1

Unit kHz mS

μA

April 20, 2012 Ver. 2.5 51

MC96F7816/C7816

8.8 LCD Voltage Characteristics

Table 8-8 LCD Voltage Characteristics


(T

A

= -40°C ~ +85°C, VDD= 2.0V ~ 5.5V, VSS= 0V)

Conditions

Voltage booster disabled,

1/4 bias

LCDCCR=0000b

Min

Typx0.95

Typ

1/4xVDD

0.950

Max

Typx1.05

Units

V

LCDCCR=0001b 1.000

LCDCCR=0010b 1.050

LCDCCR=0011b 1.100

LCDCCR=0100b 1.150

LCDCCR=0101b

1.200

LCDCCR=0110b

1.250

LCD Voltage VLC3


1/3 bias

LCDCCR=0111b

LCDCCR=1000b

Typx0.9

1.300

1.350

Typx1.1

V

LCDCCR=1001b

1.400

LCDCCR=1010b

1.450

LCDCCR=1011b

1.500

LCDCCR=1100b

1.550

LCDCCR=1101b

1.600

LCDCCR=1110b

1.650

LCD Mid Bias

Voltage

VLC0/1

VLC2

LCDCCR=1111b



VDD=3V

VLC1 Voltage booster disabled,

VDD=2.7V to 5.5V,

VLC2

1/4 bias, LCD clock = 0Hz,

VLC3 VLC0=VDD

Typx0.9

Typx0.9

Typ-0.2

Typ-0.2

Typ-0.2

1.700

3xVLC3

2xVLC3

0.75xVDD

0.5xVDD

0.25xVDD

Typx1.1

Typx1.1

Typ+0.2

Typ+0.2

Typ+0.2

V

V

LCD Driver Output

Impedance

RLO

VLCD=3V, ILOAD=±10uA

– 5 10 kΩ

LCD Bias Dividing

Resistor

RLCD

Internal resistor mode,

TA = 25 C

40 60 80

LCD Block Current

ILCD

Voltage booster mode,

VDD=3V, VLCD=3.15V,

1/3Bias

– 3 6


LC0

node are connected in the case of resister bias. uA

52 April 20, 2012 Ver. 2.5

MC96F7816/C7816

8.9 DC Characteristics

Table 8-9 DC Characteristics

Parameter

Input High Voltage

Input Low Voltage

Output High

Voltage

Output Low

Voltage

Input High Leakage

Current

Input Low Leakage

Current

Symbol

V

IH1

V

IH2

V

IL1

V

IL2

V

OH1

V

OH2

V

OL

I

IH

(T

A

= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, VSS= 0V, f

XIN

= 10MHz)

Conditions MIN TYP MAX Unit



IH1



IL1

VDD= 4.5V, I

OH

= -2mA;

All output ports except V

OH2

;

0.8VDD

0.7VDD

–

–

VDD-1.0

–

–

–

–

–

VDD

VDD

0.2VDD V

0.3VDD V

–

V

V

V

VDD-1.0

– –

V VDD= 3.0V, I

OH

= -10mA; P07

VDD= 4.5V, I

OL

= 15mA;

All output ports

– – 1.0 V

All input ports

– –

1

μA

I

IL

-1

– – μA

Pull-Up Resistor

OSC Feedback

Resistor

Supply Current

R

R

I

I

I

R

R

PU1

PU2

X1

X2

DD1

DD3

DD4

(RUN)

I

DD2

(IDLE)

I

DD5

All input ports

VI=0V,

T

A

= 25°C

All Input ports

VI=0V,

T

A

= 25°C

RESETB

VDD=5.0V

VDD=3.0V

VDD=5.0V

VDD=3.0V

XIN= VDD, XOUT= VSS

T

A

= 25°C, VDD= 5V

SXIN=VDD, SXOUT=VSS

T

A

= 25°C ,VDD=5V

VDD= 5V±10% f

XIN

= 10MHz

VDD= 3V±10% f

IRC

= 4MHz, VDD= 5V±10%

VDD= 5V±10% f

XIN

= 10MHz

VDD= 3V±10% f f

IRC

= 4MHz, VDD= 5V±10%

SUB

= 32.768kHz

VDD= 3V±10%

T

A

= 25°C,PSAVE=1

Sub RUN

Sub IDLE

STOP, VDD= 5V±10%, T

A

= 25°C

25

50

150

300

600

1750

–

–

–

–

–

–

–

–

–

50

100

250

500

1200

3500

3.0

2.2

1.4

2.0

1.3

0.6

25.0

4.0

0.5

100

200

400

700

2000

7000

6.0

4.4

2.8

4.0

2.6

1.2

50.0

8.0

3.0 k k k

Ω

Ω

Ω mA mA

μA

μA

μA

Notes) 1. Where the f

XIN

is an external main oscillator, f

SUB

is an external sub oscillator, the f

IRC

is an internal RC oscillator, and the fx is the selected system clock.

2. All supply current items don ‟t include the current of an internal Watch-dog timer RC (WDTRC) oscillator and a peripheral block.

3. All supply current items include the current of the power-on reset (POR) block.

April 20, 2012 Ver. 2.5 53

MC96F7816/C7816

8.10 AC Characteristics

Table 8-10 AC Characteristics

Parameter

RESETB Input Low

Width

Interrupt Input High,

Low width

External Counter Input

High, Low Width

External Counter

Transition Time

Symbol t

RST

Conditions

Input, VDD= 5V t

IWH

, t

IWL

All interrupt, VDD= 5V t

ECWH

, t

ECWL

ECn, VDD = 5 V

(n=0, 2) t

REC

, t

FEC

ECn, VDD = 5 V

(n=0, 2) t RST

RESETB

External

Interrupt

ECn

(T

A

= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V)

MIN TYP MAX Unit

10

– – μS

200

200

20

–

–

–

–

–

– nS

0.2 VDD

Figure 8.1 Input Timing for RESETB t

IWL t

IWH

0.8 VDD

0.2 VDD

Figure 8.2 Input Timing for External Interrupts t FEC t

ECWL t

REC t

ECWH

Figure 8.3 Input Timing for EC0, EC2

54 April 20, 2012 Ver. 2.5

SO

8.11 Serial I/O Characteristics

Table 8-11 Serial I/O Characteristics

Parameter

SCK Cycle Time

SCK High, Low width

SI Setup Time to SCK

High

SI Hold Time to SCK

High

Output Delay for SCK to

SO

Symbol t

KCY t

KH t t t

, t

SIK

KSI

KL

KSO

Conditions

External SCK source

Internal SCK source

External SCK source

Internal SCK source

External SCK source

Internal SCK source

External SCK source

Internal SCK source

External SCK source

Internal SCK source t

KL t

KH

MC96F7816/C7816

(T

A

= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V)

MIN

1,000

1,000

500 t

KCY

/2-50

250

250

400

400

TYP

–

MAX

–

Unit nS nS nS nS

– –

300

250 nS

SCK t SIK t KSI

SI t

KSO

Output Data

Figure 8.4 Serial Interface Data Transfer Timing

April 20, 2012 Ver. 2.5 55

MC96F7816/C7816

8.12 UART Characteristics

Table 8-12 UART Characteristics

Parameter

Serial Port Clock Cycle Time

Output Data Setup to Clock Rising Edge

Clock Rising Edge to Input Data Valid

Output Data Hold after Clock Rising Edge

Input Data Hold after Clock Rising Edge

Serial Port Clock High, Low Level Width t

HIGH

(T

A

= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V, f

XIN

=8.0MHz)

Symbol MIN TYP MAX Unit

1750 t

SCK t

S1 t

S2 t

H1 t

H2 t

HIGH

, t

LOW

900

– t

CPU

- 50

0

800 t

CPU

x 16 t

CPU

x 13

– t

CPU

– t

CPU

x 8

2250

–

900

–

–

1200 nS nS nS nS nS nS t

SCK t

LOW

Shift Clock

Data Out

Data In

Figure 8.5 Waveform for UART Timing Characteristics t

SCK t S1

D0 t

S2

Valid t

H1

D1 D2 D3 D4 D5

Valid t H2

Valid Valid Valid

Figure 8.6 Timing Waveform for the UART Module

Valid

D6

Valid

D7

Valid

56 April 20, 2012 Ver. 2.5

MC96F7816/C7816

8.13 Data Retention Voltage in Stop Mode

Table 8-13 Data Retention Voltage in Stop Mode

Parameter

Data Retention Supply Voltage

Symbol

V

DDDR

Conditions

–

(T

A

= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V)

MIN TYP MAX Unit

1.8 – 5.5 V

Data Retention Supply Current – – 1 μA I

DDDR

VDDDR= 1.8V,

(T

A

= 25°C), Stop mode

~ ~

Stop Mode

Idle Mode

(Watchdog Timer Active)

Normal

Operating Mode

V

DD

~ ~

Data Retention

V

DDDR

Execution of

STOP Instruction

0.8V

DD

INT Request t

WAIT

VDD

RESETB

NOTE: tWAIT is the same as (the selected bit overflow of BIT) X 1/(BIT Clock)

Figure 8.7 Stop Mode Release Timing when Initiated by an Interrupt

RESET

Occurs

~ ~

~ ~

Stop Mode

Data Retention

V

DDDR

Execution of

STOP Instruction

0.2 VDD

0.8 VDD

TWAIT

NOTE : tWAIT is the same as (4096 X 4 X 4/f IRC ) = (16.4 mS at fx=1MHz).

Figure 8.8 Stop Mode Release Timing when Initiated by RESETB

Oscillation

Stabillization Time

Normal

Operating Mode

April 20, 2012 Ver. 2.5 57

MC96F7816/C7816

8.14 Input/Output Capacitance

Table 8-14 Input/Output Capacitance

Parameter

Input Capacitance

Output Capacitance

I/O Capacitance

Symbol

C

IN

C

OUT

C

IO

Condition fx= 1MHz

Unmeasured pins are connected to VSS

MIN

(T

A

= -40°C ~ +85°C, VDD= 0V)

TYP MAX Unit

– – 10 pF

8.15 Main Clock Oscillator Characteristics

Table 8-15 Main Clock Oscillator Characteristics

Oscillator

Crystal

Ceramic Oscillator

External Clock

Parameter



XIN Input Frequency

Condition

1.8V

– 5.5V

2.7V

– 5.5V

1.8V – 5.5V

2.7V – 5.5V

1.8V

– 5.5V

2.7V

– 5.5V

(T

A

= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V)

MIN

0.4

0.4

0.4

0.4

0.4

0.4

TYP

–

–

–

–

–

–

MAX

4.2

10.0

4.2

10.0

4.2

10.0

Unit

MHz

MHz

MHz

XIN XOUT

C1 C2

Figure 8.9 Crystal/Ceramic Oscillator

XIN XOUT

External

Clock

Source

Open


58 April 20, 2012 Ver. 2.5

8.16 Sub Clock Oscillator Characteristics

Table 8-16 Sub Clock Oscillator Characteristics

Oscillator

Crystal

External Clock

Parameter

Sub oscillation frequency

SXIN input frequency

MC96F7816/C7816

Condition

1.8V – 5.5V

(T

A

= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V)

MIN

32

TYP

32.768

MAX

38

Unit kHz

32 – 100 kHz

SXIN SXOUT VREG

0.1uF

C1 C2

Figure 8.11 Crystal Oscillator

SXIN SXOUT

External

Clock

Source

Open


April 20, 2012 Ver. 2.5 59

MC96F7816/C7816

8.17 Main Oscillation Stabilization Characteristics

Table 8-17 Main Oscillation Stabilization Characteristics

Oscillator

Crystal

Ceramic

External Clock

Parameter fx > 1MHz

Oscillation stabilization occurs when VDD is equal to the minimum oscillator voltage range. f

XIN

= 0.4 to 10MHz

XIN input high and low width (t

XH

, t

XL

)

1/f XIN t XL

(T

A

= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V)

MIN TYP MAX Unit

– – 60 mS

–

50

–

–

10

1250 mS nS t XH

XIN

0.8VDD

0.2VDD

Figure 8.13 Clock Timing Measurement at XIN

8.18 Sub Oscillation Characteristics

Table 8-18 Sub Oscillation Stabilization Characteristics

Oscillator

Crystal

External Clock

Parameter

–

SXIN Input High and Low Width (t

XH

, t

XL

)

1/f SUB t XL

(T

A

= -40°C ~ +85°C, VDD= 1.8V ~ 5.5V)

MIN

–

5

TYP

–

–

MAX

10

15

Unit

S

μS t XH

SXIN

0.8VDD

0.2VDD

Figure 8.14 Clock Timing Measurement at SXIN

60 April 20, 2012 Ver. 2.5

8.19 Operating Voltage Range

(f XIN =0.4 to 10MHz)

10.0MHz

32.768kHz

MC96F7816/C7816

(f SUB =32 to 38kHz)

4.2MHz

0.4MHz

1.8

2.7

Supply voltage (V)

5.5

1.8

Figure 8.15 Operating Voltage Range

Supply voltage (V)

5.5

April 20, 2012 Ver. 2.5 61

MC96F7816/C7816

8.20 Recommended Circuit and Layout

VDD

VSS

0.1uF

This 0.1uF capacitor should be within { }

PCB layout.

VDD VCC

+

0.1uF

DC Power

I/O

XIN

XOUT

SXIN

SXOUT

VREG

VCC

High-Current Part

Infrared LED,

{ } etc

The MCU power line (VDD and VSS)

{ } the PCB layout.

0.01uF

{ }

X-tal

The main and sub crystal should be as close by the MCU as possible.

C1

C2

32.768kHz

0.1uF

The load capacitors of the sub clock

- C1, C2: C

L

x 2 ± 15%

- C

L

= (C1 x C2)/(C1 + C2) - Cstray

- C

L

: the specific capacitor value of crystal

- Cstray: the parasitic capacitor of a PCB (1pF – 1.5pF)

The VREG pin is the output of an internal regulator for sub oscillator.

So, this 0.1uF capacitor is needed and should be as close by the MCU as possible if the sub clock is used for system.

Figure 8.16 Recommended Circuit and Layout

62 April 20, 2012 Ver. 2.5

MC96F7816/C7816

8.21 Typical Characteristics

These graphs and tables provided in this section are only for design guidance and are not tested or guaranteed.

In graphs or tables some data are out of specified operating range (e.g. out of specified VDD range). This is only for information and devices are guaranteed to operate properly only within the specified range.

The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. “Typical” represents the mean of the distribution while “max” or “min” represents (mean + 3σ) and

(mean - 3σ) respectively where σ is standard deviation. mA

2.50

2.00

1.50

1.00

0.50

0.00

2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V

Figure 8.17 RUN (IDD1) Currnet

10MHz -40℃

10MHz +25℃

10MHz +85℃

IRC 4MHz -40℃

IRC 4MHz +25℃

IRC 4MHz +85℃ mA

1.80

1.60

1.40

1.20

1.00

0.80

0.60

0.40

0.20

0.00

2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V

Figure 8.18 IDLE (IDD2) Current

10MHz -40℃

10MHz +25℃

10MHz +85℃

IRC 4MHz -40℃

IRC 4MHz +25℃

IRC 4MHz +85℃

April 20, 2012 Ver. 2.5 63

MC96F7816/C7816 uA

35.0

30.0

25.0

20.0

15.0

10.0

5.0

0.0

2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V

Figure 8.19 SUB RUN (IDD3) Current uA

5.00

4.00

3.00

2.00

1.00

0.00

2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V

Figure 8.20 SUB IDLE (IDD4) Currnet

-40℃

+25℃

+85℃

-40℃

+25℃

+85℃

64 April 20, 2012 Ver. 2.5

0.60

0.40

0.20

0.00 uA

1.20

1.00

0.80

2.5V 3.0V 3.5V 4.0V 4.5V 5.0V 5.5V

Figure 8.21 STOP (IDD5) Current

MC96F7816/C7816

-40℃

+25℃

+85℃

April 20, 2012 Ver. 2.5 65

MC96F7816/C7816

9. Memory

The MC96F7816 addresses two separate address memory stores: Program memory and Data memory. The logical separation of Program and Data memory allows Data memory to be accessed by 8-bit addresses, which makes the 8-bit CPU access the data memory more rapidly. Nevertheless, 16-bit Data memory addresses can also be generated through the DPTR register.

MC96F7816 provides on-chip 16K bytes of the ISP type flash program memory, which can be read and written to. Internal data memory (IRAM) is 256 bytes and it includes the stack area. External data memory (XRAM) is

256 bytes and it includes 37 bytes of LCD display RAM.

9.1 Program Memory

A 16-bit program counter is capable of addressing up to 64K bytes, but this device has just 16K bytes program memory space.

Figure 9-1 shows the map of the lower part of the program memory. After reset, the CPU begins execution from location 0000H. Each interrupt is assigned a fixed location in program memory. The interrupt causes the CPU to jump to that location, where it commences execution of the service routine. External interrupt 10, for example, is assigned to location 000BH. If external interrupt 10 is going to be used, its service routine must begin at location

000BH. If the interrupt is not going to be used, its service location is available as general purpose program memory. If an interrupt service routine is short enough (as is often the case in control applications), it can reside entirely within that 8 byte interval. Longer service routines can use a jump instruction to skip over subsequent interrupt locations, if other interrupts are in use.

66 April 20, 2012 Ver. 2.5

FFFFH

MC96F7816/C7816

3FFFH

16K Bytes

0000H

Figure 9.1 Program Memory

- 16K bytes Including Interrupt Vector Region

April 20, 2012 Ver. 2.5 67

MC96F7816/C7816

9.2 Data Memory

Figure 9-2 shows the internal data memory space available.

FFH FFH

Upper 128 Bytes

Internal RAM

(Indirect Addressing)

Special Function Registers

128 Bytes

(Direct Addressing)

80H 80H

7FH

Lower 128 Bytes

Internal RAM

(Direct or Indirect

Addressing)

00H

Figure 9.2 Data Memory Map

The internal data memory space is divided into three blocks, which are generally referred to as the lower 128 bytes , upper 128 bytes, and SFR space.

Internal data memory addresses are always one byte wide, which implies an address space of only 256 bytes.

However, in fact the addressing modes for internal RAM can accommodate up to 384 bytes by using a simple trick. Direct addresses higher than 7FH access one memory space and indirect addresses higher than 7FH access a different memory space. Thus Figure 9-2 shows the upper 128 byte and SFR space occupying the same block of addresses, 80H through FFH, although they are physically separate entities.

The lower 128 bytes of RAM are present in all 8051 devices as mapped in Figure 9-3. The lowest 32 bytes are grouped into 4 banks of 8 registers. Program instructions call out these registers as R0 through R7. Two bits in the Program Status Word select which register bank is in use. This allows more efficient use of code space, since register instructions are shorter than instructions that use direct addressing.

The next 16 bytes above the register banks form a block of bit-addressable memory space. The 8051 instruction set includes a wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions. The bit addresses in this area are 00H through 7FH.

All of the bytes in the lower 128 bytes can be accessed by either direct or indirect addressing. The upper 128 bytes RAM can only be accessed by indirect addressing. These spaces are used for data RAM and stack.

68 April 20, 2012 Ver. 2.5

80 Bytes

7FH

General Purpose

Register

16 Bytes

(128bits)

8 Bytes

8 Bytes

8 Bytes

8 Bytes

30H

2FH

Bit Addressable

10H

0FH

08H

07H

00H

20H

1FH

18H

17H

Register Bank 3

(8 Bytes)

Register Bank 2

(8 Bytes)

Register Bank 1

(8 Bytes)

Register Bank 0

(8 Bytes)

Figure 9.3 Lower 128 Bytes RAM

MC96F7816/C7816

7F 7E 7D 7C 7B 7A 79 78

77 76 75 74 73 72 71 70

6F 6E 6D 6C 6B 6A 69 68

67 66 65 64 63 62 61 60

5F 5E 5D 5C 5B 5A 59 58

57 56 55 54 53 52 51 50

4F 4E 4D 4C 4B 4A 49 48

47 46 45 44 43 42 41 40

3F 3E 3D 3C 3B 3A 39 38

37 36 35 34 33 32 31 30

2F 2E 2D 2C 2B 2A 29 28

27 26 25 24 23 22 21 20

1F 1E 1D 1C 1B 1A 19 18

17 16 15 14 13 12 11 10

0F 0E 0D 0C 0B 0A 09 08

07 06 05 04 03 02 01 00

R7

R6

R5

R4

R3

R2

R1

R0

April 20, 2012 Ver. 2.5 69

MC96F7816/C7816

9.3 XRAM Memory

MC96F7816 has 256 bytes XRAM. This area has no relation with RAM/FLASH. It can be read and written to through SFR with 8-bit unit.

00FFH

External RAM

256 Bytes

(Indirect Addressing)

0025H

0024H

0000H

LCD Display RAM

Figure 9.4 XDATA Memory Area

70 April 20, 2012 Ver. 2.5

9.4 SFR Map

MC96F7816/C7816

9.4.1 SFR Map Summary

Table 9-1 SFR Map Summary

00H/8H

(1)

01H/9H 02H/0AH

0F8H IP1

–

03H/0BH

FSADRH FSADRM

- Reserved

M8051 compatible

04H/0CH 05H/0DH 06H/0EH

FSADRL FIDR FMCR

07H/0FH

–

0F0H B P9IO UARTCR1 UARTCR2 UARTCR3 UARTST UARTBD UARTDR

0E8H RSTFR P8IO

0E0H ACC

0D8H LVRCR

P7IO

P6IO

0D0H PSW P5IO

0C8H OSCCR P4IO

P03FSR

P4PU

P6OD

P0OD

T3CRL

P1FSR

P5PU

P9OD

P1OD

T3CRH

P2FSR P4FSR P5FSR P6FSR

P6PU

P0PU

P7PU

P1PU

P8PU

P2PU

P2OD P3OD P4OD

T3ADRL T3ADRH T3BDRL

P9PU

P3PU

P5OD

T3BDRH

0C0H

0B8H

0B0H

0A8H

P9

IP

P5

IE

P3IO

P2IO

P1IO

IE1

T2CRL

T1CR

T0CR

IE2

T2CRH

T1CNT

T0CNT

IE3

EIFLAG0

T2ADRL T2ADRH T2BDRL T2BDRH

–

T1DRL

T0DR/

T0CDR

–

T1DRH

SIOCR

P7FSR

CARCR

SIODR

P8FSR

SIOPS

P9FSR

EIPOL0 EIFLAG1 EIPOL1L EIPOL1H P0IO EO

LCDCRL LCDCRH LCDCCR ADCCRL ADCCRH ADCDRL ADCDRH

0A0H

98H

P4

P3

90H

88H

P2

P1

P6

WTDR/

WTCNT

SP

P7

SCCR

80H P0 DPL

NOTE) These registers are bit-addressable.

P8

BITCR

DPH

P0DB

BITCNT

DPL1

P1DB

WDTCR

DPH1

WTCR

WDTDR/

WDTCNT

LVICR

BUZCR

BUZDR

PCON

April 20, 2012 Ver. 2.5 71

MC96F7816/C7816

9.4.2 SFR Map

Table 9-2 SFR Map

94H

95H

96H

97H

98H

99H

9AH

9BH

8FH

90H

91H

92H

93H

9CH

9DH

9EH

9FH

Address

80H

81H

82H

83H

84H

85H

86H

87H

88H

89H

8AH

8BH

8CH

8DH

8EH

Function

P0 Data Register

Stack Pointer

Data Pointer Register Low

Data Pointer Register High

Data Pointer Register Low 1

Data Pointer Register High 1

Low Voltage Indicator Control Register

Power Control Register

P1 Data Register

Watch Timer Data Register

Watch Timer Counter Register

System and Clock Control Register

BIT Control Register

Basic Interval Timer Counter Register

Watch Dog Timer Control Register

Watch Dog Timer Data Register

Watch Dog Timer Counter Register

BUZZER Data Register

P2 Data Register

P6 Data Register

P7 Data Register

P8 Data Register

P0 Debounce Enable Register


Watch Timer Control Register

BUZZER Control Register

P3 Data Register

LCD Driver Control Low Register

LCD Driver Control High Register

LCD Contrast Control Register

A/D Converter Control Low Register

A/D Converter Control High Register

A/D Converter Data Low Register

A/D Converter Data High Register

P0

@Reset

Symbol R/W

7 6 5 4 3 2 1 0

R/W 0 0 0 0 0 0 0 0

SP

DPL

R/W

R/W

0

0

0

0

0

0

0

0

0

0

1

0

1

0

1

0

DPH

DPL1

DPH1

LVICR

PCON

P1

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W

– –

0 0 0 0 0 0

R/W 0

– – –

0 0 0 0

R/W 0 0 0 0 0 0 0 0

WTDR

WTCNT

SCCR

BITCR

W 0 1 1 1 1 1 1 1

R – 0 0 0 0 0 0 0

R/W 0 0 – – – – 0 0

R/W 0

– – –

0 0 0 1

BITCNT R 0 0 0 0 0 0 0 0

WDTCR R/W 0 0 0

– – – –

0

WDTDR

WDTCNT

W 1 1 1 1 1 1 1 1

R 0 0 0 0 0 0 0 0

BUZDR R/W 1 1 1 1 1 1 1 1

P2 R/W 0 0 0 0 0 0 0 0

P6 R/W 0 0 0 0 0 0 0 0

P7

P8

P0DB

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 0 – – 0 0 0 0

P1DB R/W 0 0 0 0 0 0 0 0

WTCR R/W 0 – – 0 0 0 0 0

BUZCR R/W – – – – – 0 0 0

P3 R/W

– – –

0 0 0 0 0

LCDCRL R/W

– –

0 0 0 0 0 0

LCDCRH R/W

– – – –

0 0 0 0

LCDCCR R/W – – – – 0 0 0 0

ADCCRL R/W 0 0 0 0

–

0 0 0

ADCCRH R/W 0

– – – –

0 0 0

ADCDRL

ADCDRH

R

R x x x x x x x x x x x x x x x x

72 April 20, 2012 Ver. 2.5

MC96F7816/C7816

Table 9-2 SFR Map (Continued)

AAH

ABH

ACH

ADH

AEH

AFH

B0H

B1H

B2H

B3H

B4H

A0H

A1H

A2H

A3H

A4H

A5H

A6H

A7H

A8H

A9H

B4H

B5H

B6H

B7H

B8H

B9H

BAH

BBH

BCH

BDH

BEH

BFH

Address Function

P4 Data Register

P0 Direction Register

Extended Operation Register

External Interrupt Flag 0 Register

P4

@Reset

Symbol R/W

7 6 5 4 3 2 1 0

R/W 0 0 0 0 0 0 0 0

P0IO R/W 0 0 0 0 0 0 0 0

EO R/W – – – 0 – 0 0 0

EIFLAG0 R/W 0 0 0

–

0 0 0 0

External Interrupt Polarity 0 Register


Port 7 Function Selection Register



P5 Data Register


Timer 0 Control Register

Timer 0 Counter Register

Timer 0 Data Register

EIPOL0 R/W 0 0 0 0 0 0 0 0

EIFLAG1 R/W 0 0 0 0 0 0 0 0

External Interrupt Polarity 1 Low Register EIPOL1L R/W 0 0 0 0 0 0 0 0

External Interrupt Polarity 1 High Register EIPOL1H R/W 0 0 0 0 0 0 0 0

Interrupt Enable Register IE R/W 0

–

0

–

0 0 0 0

Interrupt Enable Register 1



Reserved

IE1

IE2

IE3

–

R/W – – 0 0 0 – – –

R/W – – – 0 0 0 0 0

R/W – – – 0 0 0 – 0

– –

P7FSR

P8FSR

P9FSR

P5

P1IO

T0CR

T0CNT

T0DR

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W

– – – – –

0 0 0

R/W 0 0 0 0 0 0 0 0

R/W

R/W

R

0

0

0

–

0

0

0

0

0

0

0

0

0

0

0

0

0 0 0 0 0 0 0 0

R/W 1 1 1 1 1 1 1 1

Timer 0 Capture Data Register

SIO Control Register

SIO Data Register

SIO Pre-scaler Register

Interrupt Priority Register




Timer 1 Data Low Register

Timer 1 Data High Register

Carrier Control Register

Reserved

T0CDR

SIOCR

R 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

SIODR

SIOPS

IP

P2IO

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W – – 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 0

–

0 0 0 0 0 T1CR

T1CNT

T1DRL

R

R/W

0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1

T1DRH R/W 1 1 1 1 1 1 1 1

CARCR R/W

– –

0 0

– –

0 0

– – –

April 20, 2012 Ver. 2.5 73

MC96F7816/C7816


Address

D0H

D1H

D2H

D3H

D4H

D5H

D6H

D7H

D8H

D9H

DAH

DBH

DCH

DDH

DEH

DFH

C8H

C9H

CAH

CBH

CCH

CDH

CEH

CFH

C0H

C1H

C2H

C3H

C4H

C5H

C6H

C7H

Function

P9 Data Register


Timer 2 Control Low Register

Timer 2 Control High Register

Timer 2 A Data Low Register

Timer 2 A Data High Register

Timer 2 B Data Low Register

Timer 2 B Data High Register

Oscillator Control Register








Program Status Word Register


P0 Open-drain Selection Register






Low Voltage Reset Control Register




P0 Pull-up Resistor Selection Register




Symbol

PSW

P5IO

P0OD

P1OD

P2OD

P3OD

P4OD

P5OD

LVRCR

P6IO

P6OD

P9OD

P0PU

P1PU

P2PU

P3PU

P9

P3IO

T2CRL

T2CRH

T2ADRL

T2ADRH

T2BDRL

T2BDRH

OSCCR

P4IO

T3CRL

T3CRH

T3ADRL

T3ADRH

T3BDRL

T3BDRH

@Reset

R/W

7 6 5 4 3 2 1 0

R/W – – – – 0 0 – –

R/W – – – 0 0 0 0 0

R/W 0 0 0 0 – 0 0 0

R/W 0

–

0 0

– – –

0

R/W 1 1 1 1 1 1 1 1

R/W 1 1 1 1 1 1 1 1

R/W 1 1 1 1 1 1 1 1

R/W 1 1 1 1 1 1 1 1

R/W

– – –

0 1 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0

–

0

–

0

R/W 0

–

0 0

– – –

0

R/W 1 1 1 1 1 1 1 1

R/W 1 1 1 1 1 1 1 1

R/W 1 1 1 1 1 1 1 1

R/W 1 1 1 1 1 1 1 1

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W

– – –

0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0

– –

0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W – – – – 0 0 – –

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W

– – –

0 0 0 0 0

74 April 20, 2012 Ver. 2.5


Address

EAH

EBH

ECH

EDH

EEH

EFH

F0H

F1H

F2H

E0H

E1H

E2H

E3H

E4H

E5H

E6H

E7H

E8H

E9H

F3H

F4H

F5H

F6H

F7H

F8H

F9H

FAH

FBH

FCH

FDH

FEH

FFH

Function

Accumulator A Register








Reset Flag Register


Port 0/3 Function Selection Register






B Register


UART Control Register 1



UART Status Register

UART Baud Rate Generation Register

UART Data Register

Interrupt Priority Register 1

Reserved

Flash Sector Address High Register

Flash Sector Address Middle Register

Flash Sector Address Low Register

Flash Identification Register

Flash Mode Control Register

Reserved

MC96F7816/C7816

Symbol

ACC

P7IO

P4PU

P5PU

P6PU

P7PU

P8PU

P9PU

RSTFR

P8IO

P03FSR

P1FSR

P2FSR

P4FSR

P5FSR

P6FSR

B

P9IO

UARTCR1

UARTCR2

UARTCR3

UARTST

UARTBD

UARTDR

IP1

–

FSADRH

FSADRM

FSADRL

FIDR

FMCR

–

@Reset

R/W

7 6 5 4 3 2 1 0

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W

– – – – 0 0 0 0

R/W 1 x 0 0 x

– – –

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W – – – – 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W

– – – – 0 0 – –

R/W – – 0 0 0 0 0 –

R/W 0 0 0 0 0 0 0 0

R/W – 0 – – – 0 0 0

R/W 1 0 0 0 0 0 0 0

R/W 1 1 1 1 1 1 1 1

R/W 0 0 0 0 0 0 0 0

R/W

– – 0 0 0 0 0 0

– –

R/W

– – – – 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 0 0 0 0 0 0 0

R/W 0 – – – – 0 0 0

– –

April 20, 2012 Ver. 2.5 75

MC96F7816/C7816

9.4.3 Compiler Compatible SFR

ACC (Accumulator Register) : E0H

7 6 5 4

R/W

ACC

3

R/W R/W R/W

B (B Register) : F0H

7 6

ACC

R/W

5

Accumulator

4 3

B

R/W R/W R/W R/W R/W

B

SP (Stack Pointer) : 81H

7 6

B Register

5 4

R/W

SP

3

R/W R/W R/W R/W

SP

DPL (Data Pointer Register Low) : 82H

7 6 5

Stack Pointer

4

DPL

R/W R/W R/W R/W

3

R/W

DPL Data Pointer Low

DPH (Data Pointer Register High) : 83H

7 6 5 4

DPH

R/W R/W R/W R/W

3

R/W

DPH Data Pointer High

2

R/W

1 0

R/W R/W

Initial value : 00H

2

R/W

1 0

R/W R/W

Initial value : 00H

2

R/W

1 0

R/W R/W

Initial value : 07H

2

R/W

1 0

R/W R/W

Initial value : 00H

2

R/W

1 0

R/W R/W

Initial value : 00H

76 April 20, 2012 Ver. 2.5

MC96F7816/C7816

DPL1 (Data Pointer Register Low 1) : 84H

7 6 5 4 3 2 1 0

DPL1

R/W R/W R/W R/W R/W R/W R/W R/W

Initial value : 00H

DPL1 Data Pointer Low 1

DPH1 (Data Pointer Register High 1) : 85H

7 6 5 4 3

DPH1

R/W R/W R/W R/W R/W

2 1 0

R/W R/W R/W

Initial value : 00H

CY

R/W

AC

R/W

DPH1

F0

R/W

Data Pointer High 1

PSW (Program Status Word Register) : D0H

7 6 5 4

RS1

R/W

3

RS0

R/W

2

OV

R/W

1

F1

R/W

0

P

R/W

Initial value : 00H

CY

AC

F0

RS1

RS0

OV

F1

P

Carry Flag

Auxiliary Carry Flag

General Purpose User-Definable Flag

Register Bank Select bit 1

Register Bank Select bit 0

Overflow Flag

User-Definable Flag

Parity Flag. Set/cleared by hardware each instruction cycle to indicate an odd/even number of „1‟ bits in the accumulator

EO (Extended Operation Register) : A2H

7 6 5

- - -

4

TRAP_EN

- - - R/W

3

-

-

2

DPSEL2

R/W

1

DPSEL1

R/W

0

DPSEL0

R/W

Initial value : 00H

TRAP_EN

DPSEL[2:0]

Select the Instruction (Keep always „0‟).

0 Select MOVC @(DPTR++), A

1 Select Software TRAP Instruction

Select Banked Data Pointer Register

DPSEL2 DPSEL1 SPSEL0 Description

0 0 0 DPTR0

0

Reserved

0 1 DPTR1

April 20, 2012 Ver. 2.5 77

MC96F7816/C7816

10. I/O Ports

10.1 I/O Ports

The MC96F7816 has ten groups of I/O ports (P0 ~ P9). Each port can be easily configured by software as I/O pin, internal pull up and open-drain pin to meet various system configurations and design requirements. Also P0 and P1 include function that can generate interrupt according to change of state of the pin.

10.2 Port Register

10.2.1 Data Register (Px)

Data Register is a bidirectional I/O port. If ports are configured as output ports, data can be written to the corresponding bit of the Px. If ports are configured as input ports, the data can be read from the corresponding bit of the Px.

10.2.2 Direction Register (PxIO)

Each I/O pin can be independently used as an input or an output through the PxIO register. Bits cleared in this register will make the corresponding pin of Px to input mode. Set bits of this register will make the pin to output mode. Almost bits are cleared by a system reset, but some bits are set by a system reset.

10.2.3 Pull-up Resistor Selection Register (PxPU)

The on-chip pull-up resistor can be connected to I/O ports individually with a pull-up resistor selection register

(PxPU). The pull-up register selection controls the pull-up resister enable/disable of each port. When the corresponding bit is 1, the pull-up resister of the pin is enabled. When 0, the pull-up resister is disabled. All bits are cleared by a system reset.

10.2.4 Open-drain Selection Register (PxOD)

There are internally open-drain selection registers (PxOD) for P0 ~ P6 and P9. The open-drain selection register controls the open-drain enable/disable of each port. Almost ports become push-pull by a system reset, but some ports become open-drain by a system reset.

10.2.5 Debounce Enable Register (PxDB)

P0[1:0], P30, P93, and P1[7:0] support debounce function. Debounce clocks of each ports are fx/1, fx/4, and fx/4096.

10.2.6 Port Function Selection Register (PxFSR)

These registers define alternative functions of ports. Please remember that these registers should be set properly for alternative port function. A reset clears the PFSRx register to

„00H‟, which makes all pins to normal

I/O ports.

78 April 20, 2012 Ver. 2.5

10.2.7 Register Map

MC96F7816/C7816

Table 10-1 Port Register Map

Address

E2H

D6H

B0H

D1H

E3H

D7H

91H

DEH

D4H

98H

C1H

DFH

D5H

A0H

C9H

D9H

E4H

DAH

80H

A1H

DCH

D2H

94H

88H

B1H

DDH

D3H

95H

90H

B9H

Name

P4PU

P4OD

P5

P5IO

P5PU

P5OD

P6

P2PU

P2OD

P3

P3IO

P3PU

P3OD

P4

P4IO

P6IO

P6PU

P6OD

P0

P0IO

P0PU

P0OD

P0DB

P1

P1IO

P1PU

P1OD

P1DB

P2

P2IO

Dir

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Default

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

Description

P0 Data Register





P1 Data Register





P2 Data Register




P3 Data Register




P4 Data Register




P5 Data Register




P6 Data Register




April 20, 2012 Ver. 2.5 79

MC96F7816/C7816

Table 10-1 Register Map (Continued)

Name

P7

P7IO

P7PU

P8

P8IO

P8PU

P9

P9IO

P9PU

P9OD

P03FSR

P1FSR

P2FSR

P4FSR

P5FSR

P6FSR

P7FSR

P8FSR

P9FSR

Address

92H

E1H

E5H

93H

E9H

E6H

C0H

F1H

E7H

DBH

EAH

EBH

ECH

EDH

EEH

EFH

ADH

AEH

AFH

Dir

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Default

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

Description

P7 Data Register



P8 Data Register



P9 Control & Data Register




Port 0/3 Function Selection Register









80 April 20, 2012 Ver. 2.5

10.3 P0 Port

10.3.1 P0 Port Description

MC96F7816/C7816

P0 is 8-bit I/O port. P0 control registers consist of P0 data register (P0), P0 direction register (P0IO), debounce enable register (P0DB), P0 pull-up resistor selection register (P0PU), and P0 open-drain selection register

(P0OD). The P07 and P05~P03 function can be selected by the PFSR0[3:0] bits of the P03FSR register. Refer to the port function selection registers.

10.3.2 Register description for P0

P0 (P0 Data Register) : 80H

7

P07

R/W

6

P06

R/W

5

P05

R/W

4

P04

R/W

3

P03

R/W

2

P02

R/W

P0PU[7:0] Configure Pull-up Resistor of P0 Port

0 Disable

1 Enable

P0OD (P0 Open-drain Selection Register) : D2H

7

P07OD

6

P06OD

5

P05OD

4

P04OD

R/W R/W R/W R/W

3

P03OD

R/W

2

P02OD

R/W

1

P01

R/W

P0IO (P0 Direction Register) : A1H

7 6 5

P07IO

R/W

P0[7:0]

P06IO

R/W

P05IO

P0IO[7:0]

R/W

I/O Data

4

P04IO

R/W

3

P03IO

R/W

2

P02IO

R/W

1

P01IO

R/W

0

P00IO

R/W

Initial value : 00H

P0 Data I/O Direction.

0

1

Input

Output

Note: SI/SCK-in/EC2/EINT8/EINT12 function possible when input

P0PU (P0 Pull-up Resistor Selection Register) : DCH

7

P07PU

6

P06PU

5

P05PU

4

P04PU

R/W R/W R/W R/W

3

P03PU

R/W

2

P02PU

R/W

1

P01PU

R/W

0

P00PU

R/W

Initial value : 00H

1

P01OD

R/W

0

P00

R/W

Initial value : 00H

0

P00OD

R/W

Initial value : 00H

P0OD[7:0] Configure Open-drain of P0 Port

0 Push-pull output

1 Open-drain output

April 20, 2012 Ver. 2.5 81

MC96F7816/C7816

P0DB (P0 Debounce Enable Register): 94H

7 6 5 4

DBCLK1

R/W

DBCLK0

R/W

-

-

-

-

3

P93DB

R/W

2

P30DB

R/W

1

P01DB

R/W

0

P00DB

R/W

Initial value: 00H

DBCLK[1:0]

P93DB

P30DB

P01DB

P00DB

Configure Debounce Clock of Port

DBCLK1 DBCLK0 Description

0 0 fx (SCLK)

0

1

1

0 fx/4 fx/4096

1 1 Reserved

Configure Debounce of P93 Port

0

1

Disable

Enable


0 Disable

1 Enable


0

1

Disable

Enable


0

1

Disable

Enable

Notes) 1. If the same level is not detected on enabled pin three or four times in a row at the sampling clock, the signal is eliminated as noise.

2. A pulse level should be input for the duration of 3 clock or more to be actually detected as a valid edge.

3. The port debounce is automatically disabled at stop mode and recovered after stop mode release.

82 April 20, 2012 Ver. 2.5

10.4 P1 Port


MC96F7816/C7816

P1 is 8-bit I/O port. P1 control registers consist of P1 data register (P1), P1 direction register (P1IO), debounce enable register (P1DB), P1 pull-up resistor selection register (P1PU), and P1 open-drain selection register

(P1OD) . Refer to the port function selection registers for the P1 function selection.



7

P17

R/W

6

P16

R/W

5

P15

R/W

4

P14

R/W

3

P13

R/W

2

P12

R/W

1

P11

R/W

0

P10

R/W

Initial value : 00H

7

P17IO

R/W

6

R/W

P1[7:0]

P1IO (P1 Direction Register) : B1H

P16IO

5

P15IO

R/W

I/O Data

4

P14IO

R/W

3

P13IO

R/W

2

P12IO

R/W


0

1

Disable

Enable


7 6 5 4

P17OD

R/W

P16OD

R/W

P15OD

R/W

P14OD

R/W

3

P13OD

R/W

2

P12OD

R/W

1

P11IO

R/W

P1IO[7:0] P1 Data I/O Direction

0 Input

1 Output

Note: EINT0

– EINT7 function possible when input

P1PU (P1 Pull-up Resistor Selection Register) : DDH

7 6 5 4

P17PU

R/W

P16PU

R/W

P15PU

R/W

P14PU

R/W

3

P13PU

R/W

2

P12PU

R/W

1

P11PU

R/W

0

P10PU

R/W

Initial value : 00H

1

P11OD

R/W

0

P10IO

R/W

Initial value : 00H

0

P10OD

R/W

Initial value : 00H


0 Push-pull output

1 Open-drain output

April 20, 2012 Ver. 2.5 83

MC96F7816/C7816

P1DB (P1 Debounce Enable Register) : 95H

7 6 5 4

P17DB

R/W

P16DB

R/W

P15DB

R/W

P14DB

R/W

3

P13DB

R/W

2

P12DB

R/W

1

P11DB

R/W

0

P10DB

R/W

Initial value : 00H

P17DB

P16DB

P15DB

P14DB

P13DB

P12DB

P11DB

P10DB


0

1

Disable

Enable


0 Disable

1 Enable


0

1

Disable

Enable


0 Disable

1 Enable


0

1

Disable

Enable


0 Disable

1 Enable


0

1

Disable

Enable


0 Disable

1 Enable

Notes) 1. If the same level is not detected on enabled pin three or four times in a row at the sampling clock, the signal is eliminated as noise.

2. A pulse level should be input for the duration of 3 clock or more to be actually detected as a valid edge.

3. The port debounce is automatically disabled at stop mode and recovered after stop mode release.

4. Refer to the port 0 debounce enable register (P0DB) for the debounce clock of port 1.

84 April 20, 2012 Ver. 2.5

10.5 P2 Port


MC96F7816/C7816

P2 is 8-bit I/O port. P2 control registers consist of P2 data register (P2), P2 direction register (P2IO), P2 pull-up resistor selection register (P2PU) and P2 open-drain selection register (P2OD). Refer to the port function selection registers for the P2 function selection.



7 6

P27 P26

R/W R/W

5

P25

R/W

4

P24

R/W

3

P23

R/W

2

P22

R/W

P2[7:0]

P2IO (P2 Direction Register) : B9H

7

P27IO

6

P26IO

5

P25IO

R/W R/W R/W

I/O Data

4

P24IO

R/W

3

P23IO

R/W


0 Input

1 Output

P2PU (P2 Pull-up Resistor Selection Register) : DEH

7

P27PU

6

P26PU

5

P25PU

4

P24PU

R/W R/W R/W R/W

3

P23PU

R/W

2

P22IO

R/W

2

P22PU

R/W


0 Disable

1 Enable


7

P27OD

6

P26OD

5

P25OD

4

P24OD

R/W R/W R/W R/W

3

P23OD

R/W

2

P22OD

R/W


0 Push-pull output

1 Open-drain output

1

P21

R/W

0

P20

R/W

Initial value : 00H

1

P21IO

R/W

0

P20IO

R/W

Initial value : 00H

1

P21PU

R/W

0

P20PU

R/W

Initial value : 00H

1

P21OD

R/W

0

P20OD

R/W

Initial value : 00H

April 20, 2012 Ver. 2.5 85

MC96F7816/C7816

10.6 P3 Port





7

-

-

6

-

-

5

-

-

4

P34

R/W

3

P33

R/W

2

P32

R/W

1

P31

R/W

0

P30

R/W

Initial value : 00H

P3[4:0]

P3IO (P3 Direction Register) : C1H

7

-

-

6

-

-

5

-

-

I/O Data

4

P34IO

R/W

3

P33IO

R/W

2

P32IO

R/W


0

1

Disable

Enable


7 6 5 4

-

-

-

-

-

-

P34OD

R/W

3

P33OD

R/W

2

P32OD

R/W

1

P31IO

R/W


0 Input

1 Output

Note: RXD/EINT13 function possible when input

P3PU (P3 Pull-up Resistor Selection Register) : DFH

7 6 5 4

-

-

-

-

-

-

P34PU

R/W

3

P33PU

R/W

2

P32PU

R/W

1

P31PU

R/W

0

P30PU

R/W

Initial value : 00H

1

P31OD

R/W

0

P30IO

R/W

Initial value : 00H

0

P30OD

R/W

Initial value : 00H


0

1

Push-pull output

Open-drain output

86 April 20, 2012 Ver. 2.5

10.7 P4 Port


MC96F7816/C7816



P4 (P4 Data Register) : A0H

7 6

P47 P46

R/W R/W

5

P45

R/W

4

P44

R/W

3

P43

R/W

2

P42

R/W

P4[7:0]

P4IO (P4 Direction Register) : C9H

7

P47IO

6

P46IO

5

P45IO

R/W R/W R/W

I/O Data

4

P44IO

R/W

3

P43IO

R/W


0 Input

1 Output

P4PU (P4 Pull-up Resistor Selection Register) : E2H

7

P47PU

6

P46PU

5

P45PU

4

P44PU

R/W R/W R/W R/W

3

P43PU

R/W

2

P42IO

R/W

2

P42PU

R/W


0 Disable

1 Enable


7

P47OD

6

P46OD

5

P45OD

4

P44OD

R/W R/W R/W R/W

3

P43OD

R/W

2

P42OD

R/W


0 Push-pull output

1 Open-drain output

1

P41

R/W

0

P40

R/W

Initial value : 00H

1

P41IO

R/W

0

P40IO

R/W

Initial value : 00H

1

P41PU

R/W

0

P40PU

R/W

Initial value : 00H

1

P41OD

R/W

0

P40OD

R/W

Initial value : 00H

April 20, 2012 Ver. 2.5 87

MC96F7816/C7816

10.8 P5 Port




P5 (P5 Data Register) : B0H

7 6

P57 P56

R/W R/W

5

P55

R/W

4

P54

R/W

3

P53

R/W

2

P52

R/W

P5[7:0]

P5IO (P5 Direction Register) : D1H

7

P57IO

6

P56IO

5

P55IO

R/W R/W R/W

I/O Data

4

P54IO

R/W

3

P53IO

R/W


0 Input

1 Output


7

P57PU

6

P56PU

5

P55PU

4

P54PU

R/W R/W R/W R/W

3

P53PU

R/W

2

P52IO

R/W

2

P52PU

R/W


0 Disable

1 Enable


7

P57OD

6

P56OD

5

P55OD

4

P54OD

R/W R/W R/W R/W

3

P53OD

R/W

2

P52OD

R/W


0 Push-pull output

1 Open-drain output

1

P51

R/W

0

P50

R/W

Initial value : 00H

1

P51IO

R/W

0

P50IO

R/W

Initial value : 00H

1

P51PU

R/W

0

P50PU

R/W

Initial value : 00H

1

P51OD

R/W

0

P50OD

R/W

Initial value : 00H

88 April 20, 2012 Ver. 2.5

10.9 P6 Port


MC96F7816/C7816




7 6

P67 P66

R/W R/W

5

P65

R/W

4

P64

R/W

3

P63

R/W

2

P62

R/W

P6[7:0]

P6IO (P6 Direction Register) : D9H

7

P67IO

6

P66IO

5

P65IO

R/W R/W R/W

I/O Data

4

P64IO

R/W

3

P63IO

R/W


0 Input

1 Output


7

P67PU

6

P66PU

5

P65PU

4

P64PU

R/W R/W R/W R/W

3

P63PU

R/W

2

P62IO

R/W

2

P62PU

R/W


0 Disable

1 Enable

P6OD (P6 Open-drain Selection Register) : DAH

7

P67OD

6

P66OD

5

P65OD

4

P64OD

R/W R/W R/W R/W

3

P63OD

R/W

2

P62OD

R/W


0 Push-pull output

1 Open-drain output

1

P61

R/W

0

P60

R/W

Initial value : 00H

1

P61IO

R/W

0

P60IO

R/W

Initial value : 00H

1

P61PU

R/W

0

P60PU

R/W

Initial value : 00H

1

P61OD

R/W

0

P60OD

R/W

Initial value : 00H

April 20, 2012 Ver. 2.5 89

MC96F7816/C7816

10.10 P7 Port


P7 is 8-bit I/O port. P7 control registers consist of P7 data register (P7), P7 direction register (P7IO), and P7 pull-up resistor selection register (P7PU). Refer to the port function selection registers for the P7 function selection.



7 6

P77 P76

R/W R/W

5

P75

R/W

4

P74

R/W

P7[7:0]

P7IO (P7 Direction Register) : E1H

7

P77IO

6

P76IO

5

P75IO

R/W R/W R/W

I/O Data

4

P74IO

R/W

3

P73

R/W

2

P72

R/W

3

P73IO

R/W

2

P72IO

R/W

R/W R/W

P7IO[7:0]

R/W

P7PU[7:0]

P7 Data I/O Direction

0 Input

1 Output


7

P77PU

6

P76PU

5

P75PU

4

P74PU

R/W

3

P73PU

R/W

2

P72PU

R/W

Configure Pull-up Resistor of P7 Port

0 Disable

1 Enable

1

P71

R/W

0

P70

R/W

Initial value : 00H

1

P71IO

R/W

0

P70IO

R/W

Initial value : 00H

1

P71PU

R/W

0

P70PU

R/W

Initial value : 00H

90 April 20, 2012 Ver. 2.5

10.11 P8 Port


MC96F7816/C7816

P8 is 8-bit I/O port. P8 control registers consist of P8 data register (P8), P8 direction register (P8IO), and P8 pull-up resistor selection register (P8PU). Refer to the port function selection registers for the P8 function selection.



7 6

P87

R/W

P86

R/W

5

P85

R/W

4

P84

R/W

P8[7:0]

P8IO (P8 Direction Register) : E9H

7 6 5

P87IO

R/W

P86IO

R/W

P85IO

R/W

I/O Data

4

P84IO

R/W

3

P83

R/W

2

P82

R/W

3

P83IO

R/W

2

P82IO

R/W

P87PU

R/W

P8IO[7:0]

P86PU

R/W

P85PU

R/W

P8PU[7:0]

P8 Data I/O Direction

0

1

Input

Output


7 6 5 4

P84PU

R/W

3

P83PU

R/W

2

P82PU

R/W


0

1

Disable

Enable

1

P81

R/W

0

P80

R/W

Initial value : 00H

1

P81IO

R/W

0

P80IO

R/W

Initial value : 00H

1

P81PU

R/W

0

P80PU

R/W

Initial value : 00H

April 20, 2012 Ver. 2.5 91

MC96F7816/C7816

10.12 P9 Port


P9 is 2-bit I/O port. P9 control registers consist of P9 data register (P9), P9 direction register (P9IO), P9 pull-up resistor selection register (P9PU), and P9 open-drain selection register (P9OD). Refer to the port function selection registers for the P9 function selection.


P9 (P9 Data Register) : C0H

7

-

-

6

-

-

5

-

-

4

-

-

3

P93

R/W

2

P92

R/W

1 x

-

0 x

-

Initial value : 00H

P9[3:2]

P9IO (P9 Direction Register) : F1H

7

-

-

6

-

-

5

-

-

I/O Data

4

-

-

3

P93IO

R/W

2

P92IO

R/W

P9PU[3:2]

P9PU[1:0]


0 Disable

1 Enable

Keep always

„00b‟

P9OD (P9 Open-drain Selection Register) : DBH

7

-

6

-

5

-

4

-

- - - -

3

P93OD

R/W

2

P92OD

R/W

1 x

-


0 Input

1 Output

Note: EINT10/EC0 function possible when input


7 6 5 4

-

-

-

-

-

-

-

-

3

P93PU

R/W

2

P92PU

R/W

1

P91PU

R/W

0

P90PU

R/W

Initial value : 00H

1 x

-

0 x

-

Initial value : 00H

0 x

-

Initial value : 00H


0 Push-pull output

1 Open-drain output

92 April 20, 2012 Ver. 2.5

10.13 Port Function

10.13.1 Port Function Description

MC96F7816/C7816

Port function control registers consist of Port function selection register 0 ~ 9. (P03FSR ~ P9FSR).

10.13.2 Register description for P03FSR ~ P9FSR

P03FSR (Port 0/3 Function Selection Register) : EAH

7 6 5 4

PFSR33

R/W

PFSR32

R/W

PFSR31

PFSR33

PFSR32

PFSR31

PFSR30

PFSR03

PFSR02

PFSR01

PFSR00

R/W

PFSR30

R/W

3

PFSR03

R/W

2

PFSR02

R/W

1

PFSR01

R/W

0

PFSR00

R/W

Initial value : 00H

P33 Function Select

0 I/O Port

1 TXD Function

P32 Function Select

0 I/O Port

1 T2O/PWM2O Function

P31 Function Select

0

1

I/O Port

T3O/PWM3O Function

P30 Function Select

0 I/O Port

1 LVIREF Function

P07 Function Select

0

1

I/O Port

REM Function

P05 Function Select

0 I/O Port

1 SO Function

P04 Function Select

0

1

I/O Port (SCK-in function possible when input)

SCK-out Function

P03 Function Select

0 I/O Port

1 BUZO Function

April 20, 2012 Ver. 2.5 93

MC96F7816/C7816

P1FSR (Port 1 Function Selection Register) : EBH

7 6 5 4

-

-

-

-

PFSR13

PFSR12

PFSR11

PFSR10

-

-

-

-

3

PFSR13

R/W

2

PFSR12

R/W

1

PFSR11

R/W

0

PFSR10

R/W

Initial value : 00H

P13 Function Select

0

1

I//O Port (EINT3 function possible when input)

AN7 Function

P12 Function Select

0 I//O Port (EINT2 function possible when input)

1 AN6 Function

P11 Function Select

0

1

I//O Port (EINT1 function possible when input)

AN5 Function

P10 Function Select

0 I//O Port (EINT0 function possible when input)

1 AN4 Function

94 April 20, 2012 Ver. 2.5

P2FSR (Port 2 Function Selection Register) : ECH

7 6 5 4

PFSR27

R/W

PFSR26

R/W

PFSR25

R/W

PFSR24

R/W

3

PFSR23

R/W

PFSR27

PFSR26

PFSR25

PFSR24

PFSR23

PFSR22

PFSR21

PFSR20

P27 Function Select

0

1

I/O Port

AN3 Function

P26 Function Select

0 I/O Port

1 AN2 Function

P25 Function Select

0

1

I/O Port

AN1 Function

P24 Function Select

0 I/O Port

1 AN0 Function

P23 Function Select

0

1

I/O Port

SEG36 Function

P22 Function Select

0

1

I/O Port

SEG35 Function

P21 Function Select

0 I/O Port

1 SEG34 Function

P20 Function Select

0

1

I/O Port

SEG33 Function

2

PFSR22

R/W

MC96F7816/C7816

1

PFSR21

R/W

0

PFSR20

R/W

Initial value : 00H

April 20, 2012 Ver. 2.5 95

MC96F7816/C7816

P4FSR (Port 4 Function Selection Register) : EDH

7 6 5 4

PFSR47

R/W

PFSR46

R/W

PFSR45

R/W

PFSR44

R/W

3

PFSR43

R/W

2

PFSR42

R/W

1

PFSR41

R/W

0

PFSR40

R/W

Initial value : 00H

PFSR47

PFSR46

PFSR45

PFSR44

PFSR43

PFSR42

PFSR41

PFSR40

P47 Function Select

0

1

I/O Port

COM1/SEG0 Function

P46 Function Select

0 I/O Port

1 COM0 Function

P45 Function Select

0

1

I/O Port

CAPL Function

P44 Function Select

0 I/O Port

1 CAPH Function

P43 Function Select

0

1

I/O Port

VLC3 Function

P42 Function Select

0

1

I/O Port

VLC2 Function

P41 Function Select

0 I/O Port

1 VLC1 Function

P40 Function Select

0

1

I/O Port

VLC0 Function

Notes) 1. The P4.7 is automatically configured as common or segment signal according to the duty in the

LCDCRL register when the pin is selected as a sub-function.

96 April 20, 2012 Ver. 2.5

P5FSR (Port 5 Function Selection Register) : EEH

7 6 5 4

PFSR57

R/W

PFSR56

R/W

PFSR55

R/W

PFSR54

R/W

3

PFSR53

R/W

PFSR57

PFSR56

PFSR55

PFSR54

PFSR53

PFSR52

PFSR51

PFSR50

P57 Function Select

0

1

I/O Port

SEG32 Function

P56 Function Select

0 I/O Port

1 SEG31 Function

P55 Function Select

0

1

I/O Port

SEG30 Function

P54 Function Select

0 I/O Port

1 SEG29 Function

P53 Function Select

0

1

I/O Port

SEG28 Function

P52 Function Select

0

1

I/O Port

SEG27 Function

P51 Function Select

0 I/O Port

1 SEG26 Function

P50 Function Select

0

1

I/O Port

SEG25 Function

2

PFSR52

R/W

MC96F7816/C7816

1

PFSR51

R/W

0

PFSR50

R/W

Initial value : 00H

April 20, 2012 Ver. 2.5 97

MC96F7816/C7816

P6FSR (Port 6 Function Selection Register) : EFH

7 6 5 4

PFSR67

R/W

PFSR66

R/W

PFSR65

R/W

PFSR64

R/W

3

PFSR63

R/W

PFSR67

PFSR66

PFSR65

PFSR64

PFSR63

PFSR62

PFSR61

PFSR60

P67 Function Select

0

1

I/O Port

SEG24 Function

P66 Function Select

0 I/O Port

1 SEG23 Function

P65 Function Select

0

1

I/O Port

SEG22 Function

P64 Function Select

0 I/O Port

1 SEG21 Function

P63 Function Select

0

1

I/O Port

SEG20 Function

P62 Function Select

0

1

I/O Port

SEG19 Function

P61 Function Select

0 I/O Port

1 SEG18 Function

P60 Function Select

0

1

I/O Port

SEG17 Function

2

PFSR62

R/W

1

PFSR61

R/W

0

PFSR60

R/W

Initial value : 00H

98 April 20, 2012 Ver. 2.5

P7FSR (Port 7 Function Selection Register) : ADH

7 6 5 4

PFSR77

R/W

PFSR76

R/W

PFSR75

R/W

PFSR74

R/W

3

PFSR73

R/W

PFSR77

PFSR76

PFSR75

PFSR74

PFSR73

PFSR72

PFSR71

PFSR70

P77 Function Select

0

1

I/O Port

SEG16 Function

P76 Function Select

0 I/O Port

1 SEG15 Function

P75 Function Select

0

1

I/O Port

SEG14 Function

P74 Function Select

0 I/O Port

1 SEG13 Function

P73 Function Select

0

1

I/O Port

SEG12 Function

P72 Function Select

0

1

I/O Port

SEG11 Function

P71 Function Select

0 I/O Port

1 SEG10 Function

P70 Function Select

0

1

I/O Port

SEG9 Function

2

PFSR72

R/W

MC96F7816/C7816

1

PFSR71

R/W

0

PFSR70

R/W

Initial value : 00H

April 20, 2012 Ver. 2.5 99

MC96F7816/C7816

P8FSR (Port 8 Function Selection Register) : AEH

7 6 5 4

PFSR87

R/W

PFSR86

R/W

PFSR85

R/W

PFSR84

R/W

3

PFSR83

R/W

2

PFSR82

R/W

1

PFSR81

R/W

0

PFSR80

R/W

Initial value : 00H

PFSR87

PFSR86

PFSR85

PFSR84

PFSR83

PFSR82

PFSR81

PFSR80

P87 Function Select

0

1

I/O Port

SEG8 Function

P86 Function Select

0 I/O Port

1 SEG7 Function

P85 Function Select

0

1

I/O Port

COM7/SEG6 Function

P84 Function Select

0 I/O Port

1 COM6/SEG5 Function

P83 Function Select

0

1

I/O Port

COM5/SEG4 Function

P82 Function Select

0

1

I/O Port

COM4/SEG3 Function

P81 Function Select

0 I/O Port

1 COM3/SEG2 Function

P80 Function Select

0

1

I/O Port

COM2/SEG1 Function

Notes) 1. The P85 ~ P80 are automatically configured as common or segment signal according to the duty in the LCDCRL register when the pin is selected as a sub-function.

100 April 20, 2012 Ver. 2.5

MC96F7816/C7816

P9FSR (Port 9 Function Selection Register) : AFH

7 6 5 4

-

-

-

-

-

-

-

-

3

-

-

2

PFSR92

R/W

1

PFSR91

R/W

0

PFSR90

R/W

Initial value : 00H

PFSR92

PFSR9[1:0]

P93 Function Select

0

1

I/O Port (EINT10 function possible when input)

T0O/PWM0O Function

Keep always

„11b‟

Notes) 1. Refer to the configure option for the P92/RESETB.

April 20, 2012 Ver. 2.5 101

MC96F7816/C7816

11. Interrupt Controller

11.1 Overview

The MC96F7816 supports up to 24 interrupt sources. The interrupts have separate enable register bits associated with them, allowing software control. They can also have four levels of priority assigned to them. The non-maskable interrupt source is always enabled with a higher priority than any other interrupt source, and is not controllable by software. The interrupt controller has following features:

- Receive the request from 24 interrupt source

- 6 group priority

- 4 priority levels

- Multi Interrupt possibility

- If the requests of different priority levels are received simultaneously, the request of higher priority level is served first.

- Each interrupt source can be controlled by EA bit and each IEx bit

- Interrupt latency: 3~9 machine cycles in single interrupt system

The non-maskable interrupt is always enabled. The maskable interrupts are enabled through four pair of interrupt enable registers (IE, IE1, IE2, IE3). Each bit of IE, IE1, IE2, IE3 register individually enables/disables the corresponding interrupt source. Overall control is provided by bit 7 of IE (EA). When EA is set to „0‟, all interrupts are disabled: when EA is set to

„1‟, interrupts are individually enabled or disabled through the other bits of the interrupt enable registers. The EA bit is always cleared to

„0‟ jumping to an interrupt service vector and set to „1‟ executing the [RETI] instruction. The MC96F7816 supports a four-level priority scheme. Each maskable interrupt is individually assigned to one of four priority levels according to IP and IP1.

Table 11-1 shows the Interrupt Group Priority Level that is available for sharing interrupt priority. Priority of a group is set by two bits of interrupt priority registers (one bit from IP, another one from IP1). Interrupt service routine serves higher priority interrupt first. If two requests of different priority levels are received simultaneously, the request of higher priority level is served prior to the lower one.

Table 11-1 Interrupt Group Priority Level

Interrupt

Group

0 (Bit0)

1 (Bit1)

2 (Bit2)

3 (Bit3)

4 (Bit4)

5 (Bit5)

Highest

Interrupt 0

Interrupt 1

Interrupt 2

Interrupt 3

Interrupt 4

Interrupt 5

Interrupt 6

Interrupt 7

Interrupt 8

Interrupt 9

Interrupt 10

Interrupt 11

Interrupt 12

Interrupt 13

Interrupt 14

Interrupt 15

Interrupt 16

Interrupt 17

Lowest

Interrupt 18

Interrupt 19

Interrupt 20

Interrupt 21

Interrupt 22

Interrupt 23

Highest

Lowest

102 April 20, 2012 Ver. 2.5

MC96F7816/C7816

11.2 External Interrupt

The external interrupt on INT0, INT1, INT2, INT3, and INT5 pins receive various interrupt request depending on the external interrupt polarity 0 register (EIPOL0), external interrupt polarity 1 high register (EIPOL1H), and external interrupt polarity 1 low register (EIPOL1L) as shown in Figure 11.1. Also each external interrupt source has control enable/disable bits. The external interrupt flag 0 register (EIFLAG0) and external interrupt flag 1 register (EIFLAG1) provides the status of external interrupts.

EINT8 Pin FLAG8 INT0 Interrupt

2


2


2


2

EIPOL0

EINT0 Pin

EINT1 Pin

EINT2 Pin

EINT3 Pin

EINT4 Pin

EINT5 Pin

EINT6 Pin

EINT7 Pin

2

2

2

2

2

2

2

2

EIPOL1H,EIPOL1L

FLAG0

FLAG1

FLAG2

FLAG3

FLAG4

FLAG5

FLAG6

FLAG7

Figure 11.1 External Interrupt Description

INT5 Interrupt

April 20, 2012 Ver. 2.5 103

MC96F7816/C7816

11.3 Block Diagram

EINT8

EINT10

EINT0

EINT1

EINT2

EINT3

EINT4

EINT5

EINT6

EINT7

EINT12

EINT13

UART Rx

UART Tx

SIO

Timer 0 overflow

Timer 0

Timer 1

Timer 2

Timer 3

EIPOL0

EIFLAG0.0

FLAG8

EIFLAG0.1

FLAG10

EIFLAG0.2

FLAG12

EIFLAG0.3

FLAG13

FLAG0

FLAG1

FLAG2

FLAG3

FLAG4

FLAG5

FLAG6

FLAG7

EIFLAG1.0

EIFLAG1.1

EIFLAG1.2

EIFLAG1.3

EIFLAG1.4

EIFLAG1.5

EIFLAG1.6

EIFLAG1.7

EIPOL1L, EIPOL1H

SIOIFR

T0OVIFR

T0IFR

T1IFR

T2IFR

T3IFR

IE

IE1

IE2

IP IP1

0

0

0

0

1

1

1

1

2

2

2

2

3

3

3

3

4

4

4

4

5

5

5

5

6

6

6

6

7

7

7

7

8

8

8

8

9

9

9

9

10

10

10

10

11

11

11

11

12

12

12

12

13

13

13

13

14

14

14

14

15

15

15

15

16

16

16

16

17

17

17

17

Priority High

Level 0

Level 1

Level 2

Level 3

EA

Release

Stop/Sleep

ADC

WT

WDT

BIT

ADCIFR

WTIFR

WDTIFR

BITIFR

IE3

18

18

18

18

19

19

19

19

20

20

20

20

21

21

21

21

22

22

22

22

23

23

23

23

Priority Low

Figure 11.2 Block Diagram of Interrupt

Notes) 1. The release signal for stop/idle mode may be generated by all interrupt sources which are enabled without reference to the priority level.

2. An interrupt request is delayed while data are written to IE, IE1, IE2, IE3, IP, IP1, and PCON register.

104 April 20, 2012 Ver. 2.5

MC96F7816/C7816

11.4 Interrupt Vector Table

The interrupt controller supports 24 interrupt sources as shown in the Table 11-2. When interrupt is served, long call instruction (LCALL) is executed and program counter jumps to the vector address. All interrupt requests have their own priority order.

Table 11-2 Interrupt Vector Address Table

Interrupt Source

Hardware Reset

External Interrupt 8




–


– 7

–

–

–

UART Rx Interrupt

UART Tx Interrupt

SIO Interrupt

T0 Overflow Interrupt

T0 Match Interrupt




–

ADC Interrupt

–

WT Interrupt

WDT Interrupt

BIT Interrupt

–

INT12

INT13

INT14

INT15

INT16

INT17

INT18

INT19

INT20

INT21

INT22

INT23

Symbol

Interrupt

Enable Bit

RESETB 0 0

INT0 IE.0

INT1

INT2

INT3

INT4

IE.1

IE.2

IE.3

IE.4

INT5

INT6

INT7

INT8

INT9

INT10

INT11

IE.5

IE1.0

IE1.1

IE1.2

IE1.3

IE1.4

IE1.5

IE2.0

IE2.1

IE2.2

IE2.3

IE2.4

IE2.5

IE3.0

IE3.1

IE3.2

IE3.3

IE3.4

IE3.5

Polarity

20

21

22

23

24

13

14

15

16

17

18

19

6

7

8

9

10

11

12

0

1

2

3

4

5

Mask

Non-Maskable

Maskable

Maskable

Maskable

Maskable

Maskable

Maskable

Maskable

Maskable

Maskable

Maskable

Maskable

Maskable

Maskable

Maskable

Maskable

Maskable

Maskable

Maskable

Maskable

Maskable

Maskable

Maskable

Maskable

Maskable

Vector Address

0063H

006BH

0073H

007BH

0083H

008BH

0093H

009BH

00A3H

00ABH

00B3H

00BBH

0000H

0003H

000BH

0013H

001BH

0023H

002BH

0033H

003BH

0043H

004BH

0053H

005BH

For maskable interrupt execution, EA bit must set „1‟ and specific interrupt must be enabled by writing „1‟ to associated bit in the IEx. If an interrupt request is received, the specific interrupt request flag is set to

„1‟. And it remains „1‟ until CPU accepts interrupt. If the interrupt is served, the interrupt request flag will be cleared automatically.

11.5 Interrupt Sequence

An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to „0‟ by a reset or an instruction. Interrupt acceptance always generates at last cycle of the instruction. So instead of fetching the current instruction, CPU executes internally LCALL instruction and saves the PC at stack. For the interrupt service routine, the interrupt controller gives the address of LJMP instruction to CPU. Since the end of the execution of current instruction, it needs 3~9 machine cycles to go to the interrupt service routine. The interrupt service task is terminated by the interrupt return instruction [RETI]. Once an interrupt request is generated, the following process is performed.

April 20, 2012 Ver. 2.5 105

MC96F7816/C7816

9

10

1 IE.EA Flag  0

2

3

Program Counter low Byte

SP  SP + 1

M(SP)  (PCL)

Program Counter high Byte

SP  SP + 1

M(SP)  (PCH)

4

6

Interrupt Vector Address occurrence

(Interrupt Vector Address)

5

ISR(Interrupt Service Routine) move, execute

Return from ISR

RETI

Saves PC value in order to continue process again after executing ISR

7

8

Program Counter high Byte recovery

(PCH)  (SP-1)

Program Counter low Byte recovery

(PCL)  (SP-1)

IE.EA Flag  1

Main Program execution

Figure 11.3 Interrupt Vector Address Table

106 April 20, 2012 Ver. 2.5

11.6 Effective Timing after Controlling Interrupt Bit

Case a) Control Interrupt Enable Register (IE, IE1, IE2, IE3)

Interrupt Enable Register command

Next Instruction

Next Instruction

After executing IE set/clear, enable register is effective.

MC96F7816/C7816

Figure 11.4 Effective Timing of Interrupt Enable Register

Case b) Interrupt flag Register

Interrupt Flag Register

Command

Next Instruction

Next Instruction

After executing next instruction, interrupt flag result is effective.

Figure 11.5 Effective Timing of Interrupt Flag Register

April 20, 2012 Ver. 2.5 107

MC96F7816/C7816

11.7 Multi Interrupt

If two requests of different priority levels are received simultaneously, the request of higher priority level is served first. If more than one interrupt request are received, the interrupt polling sequence determines which request is served first by hardware. However, for special features, multi-interrupt processing can be executed by software.

Main Program

Service

INT1 ISR

INT0 ISR

Enable INT0

Disable others

Set IE.EA

Occur

INT1 Interrupt Occur

INT0 Interrupt

Clear IE.EA

Enable INT0

Enable others

RETI

RETI

Figure 11.6 Effective Timing of Interrupt

Figure 11.6 shows an example of multi-interrupt processing. While INT1 is served, INT0 which has higher priority than INT1 is occurred. Then INT0 is served immediately and then the remain part of INT1 service routine is executed. If the priority level of INT0 is same or lower than INT1, INT0 will be served after the INT1 service has completed.

An interrupt service routine may be only interrupted by an interrupt of higher priority and, if two interrupts of different priority occur at the same time, the higher level interrupt will be served first. An interrupt cannot be interrupted by another interrupt of the same or a lower priority level. If two interrupts of the same priority level occur simultaneously, the service order for those interrupts is determined by the scan order.

108 April 20, 2012 Ver. 2.5

11.8 Interrupt Enable Accept Timing

MC96F7816/C7816

Max. 4 Machine Cycle

System

Clock

Interrupt goes

Active

Interrupt

Latched

4 Machine Cycle

Interrupt Processing

: LCALL & LJMP

Interrupt Routine

Figure 11.7 Interrupt Response Timing Diagram

11.9 Interrupt Service Routine Address

Basic Interval Timer

Vector Table Address

00B3H

00B4H

01H

25H

Basic Interval Timer

Service Routine Address

0125H

0126H

0EH

2EH

Figure 11.8 Correspondence between Vector Table Address and the Entry Address of ISP

11.10 Saving/Restore General-Purpose Registers

INTxx : PUSH PSW

PUSH DPL

PUSH DPH

PUSH B

Interrupt_Processing:

∙

∙

POP ACC

POP B

POP DPH

POP DPL

POP PSW

RETI

Main Task

Interrupt

Service Task

Saving

Register

Figure 11.9 Saving/Restore Process Diagram and Sample Source

Restoring

Register

April 20, 2012 Ver. 2.5 109

MC96F7816/C7816

11.11 Interrupt Timing

SCLK

INT_SRC

INTR_ACK

LAST_CYC

INTR_LCALL

INT_VEC

PROGA

CLP2

Interrupt sampled here

CLP1 CLP2 C1P1 C1P2

8-Bit interrupt Vector

C2P1 C2P2

{8 ‟h00, INT_VEC}

Figure 11.10 Timing Chart of Interrupt Acceptance and Interrupt Return Instruction

Interrupt sources are sampled at the last cycle of a command. If an interrupt source is detected the lower 8-bit of interrupt vector (INT_VEC) is decided. M8051W core makes interrupt acknowledge at the first cycle of a command, and executes long call to jump to interrupt service routine.

Note) command cycle CLPx: L=Last cycle, 1=1 st

cycle or 1 st

phase, 2=2 nd

cycle or 2 nd

phase

11.12 Interrupt Register Overview

11.12.1 Interrupt Enable Register (IE, IE1, IE2, IE3)

Interrupt enable register consists of global interrupt control bit (EA) and peripheral interrupt control bits. Total 24 peripherals are able to control interrupt.

11.12.2 Interrupt Priority Register (IP, IP1)

The 24 interrupts are divided into 6 groups which have each 4 interrupt sources. A group can be assigned 4 levels interrupt priority using interrupt priority register. Level 3 is the highest priority, while level 0 is the lowest priority. After a reset IP and IP1 are cleared to „00H‟. If interrupts have the same priority level, lower number interrupt is served first.

110 April 20, 2012 Ver. 2.5

11.12.3 External Interrupt Flag Register (EIFLAG0, EIFLAG1)

MC96F7816/C7816

The external interrupt flag 0 register (EIFLAG0) and external interrupt flag 1 register (EIFLAG1) are set to „1‟ when the external interrupt generating condition is satisfied. The flag is cleared when the interrupt service routine is executed. Alternatively, the flag can be cleared by writing a „0‟ to it.

11.12.4 External Interrupt Polarity Register (EIPOL0, EIPOL1H, EIPOL1L)

The external interrupt polarity 0 register (EIPOL0 ), external interrupt polarity 1 high register (EIPOL1H) and external interrupt polarity 1 low register (EIPOL1L) determines which type of rising/falling/both edge interrupt.

Initially, default value is no interrupt at any edge.

April 20, 2012 Ver. 2.5 111

MC96F7816/C7816


Table 11-3 Interrupt Register Map

Name

IE

IE1

IE2

IE3

IP

IP1

EIFLAG0

EIPOL0

EIFLAG1

EIPOL1L

EIPOL1H

Address

A3H

A4H

A5H

A6H

A7H

A8H

A9H

AAH

ABH

B8H

F8H

Dir

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Default

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

00H

Description

Interrupt Enable Register




Interrupt Priority Register

Interrupt Priority Register 1


External Interrupt Polarity 0 Register


External Interrupt Polarity 1 Low Register

External Interrupt Polarity 1 High Register

11.13 Interrupt Register Description

The interrupt register is used for controlling interrupt functions. Also it has external interrupt control registers.

The interrupt register consists of interrupt enable register (IE), interrupt enable register 1 (IE1), interrupt enable register 2 (IE2) and interrupt enable register 3 (IE3). For external interrupt, it consists of external interrupt flag 0 register (EIFLAG0), external interrupt polarity 0 register (EIPOL0) and external interrupt flag 1 register (EIFLAG1), external interrupt polarity 1 low register (EIPOL1L) and external interrupt polarity 1 high register (EIPOL1H).

112 April 20, 2012 Ver. 2.5

11.13.1 Register Description for Interrupt

MC96F7816/C7816

IE (Interrupt Enable Register) : A8H

7

EA

R/W

6

-

-

5

INT5E

R/W

4

-

-

3

INT3E

R/W

2

INT2E

R/W

1

INT1E

R/W

0

INT0E

R/W

Initial value : 00H

EA

INT5E

INT3E

INT2E

INT1E

INT0E

IE1 (Interrupt Enable Register 1): A9H

7 6 5

-

-

-

-

INT11E

R/W

Enable or Disable All Interrupt bits

0 All Interrupt disable

1 All Interrupt enable

Enable or Disable External Interrupt 0 ~ 7 (EINT0 ~ EINT7)

0

1

Disable

Enable

Enable or Disable External Interrupt 13 (EINT13)

0 Disable

1 Enable


0

1

Disable

Enable


0 Disable

1 Enable


0

1

Disable

Enable

4

INT10E

R/W

3

INT9E

R/W

2

-

-

1

-

-

0

-

-

Initial value: 00H

INT11E

INT10E

INT9E

Enable or Disable SIO Interrupt

0 Disable

1 Enable

Enable or Disable UART Tx Interrupt

0

1

Disable

Enable

Enable or Disable UART Rx Interrupt

0 Disable

1 Enable

April 20, 2012 Ver. 2.5 113

MC96F7816/C7816

IE2 (Interrupt Enable Register 2) : AAH

7

-

-

6

-

-

5

-

-

4

INT16E

R/W

3

INT15E

R/W

2

INT14E

R/W

1

INT13E

R/W

0

INT12E

R/W

Initial value : 00H

INT16E

INT15E

INT14E

INT13E

INT12E

IE3 (Interrupt Enable Register 3) : ABH

7

-

6

-

5

-

- - -

Enable or Disable Timer 3 Match Interrupt

0 Disable

1 Enable


0

1

Disable

Enable


0 Disable

1 Enable


0

1

Disable

Enable

Enable or Disable Timer 0 Overflow Interrupt

0 Disable

1 Enable

4

INT22E

R/W

3

INT21E

R/W

2

INT20E

R/W

1

-

-

0

INT18E

R/W

Initial value : 00H

INT22E

INT21E

INT20E

INT18E

Enable or Disable BIT Interrupt

0

1

Disable

Enable

Enable or Disable WDT Interrupt

0 Disable

1 Enable

Enable or Disable WT Interrupt

0

1

Disable

Enable

Enable or Disable ADC Interrupt

0 Disable

1 Enable

IP (Interrupt Priority Register) : B8H

7

-

6

-

5

IP5

- - R/W

4

IP4

R/W

3

IP3

R/W

2

IP2

R/W

1

IP1

R/W

0

IP0

R/W

Initial value : 00H

114 April 20, 2012 Ver. 2.5

MC96F7816/C7816

IP1 (Interrupt Priority Register 1) : F8H

7 6 5

-

-

-

-

IP15

R/W

4

IP14

R/W

3

IP13

R/W

2

IP12

R/W

1

IP11

R/W

0

IP10

R/W

Initial value : 00H

IP[5:0], IP1[5:0] Select Interrupt Group Priority

IP1x IPx

0 0

Description level 0 (lowest)

0

1

1

1

0

1 level 1 level 2 level 3 (highest)

EIFLAG0 (External Interrupt Flag 0 Register) : A3H

7

T0OVIFR

R/W

6

T0IFR

R/W

5

SIOIFR

R/W

4

-

-

3

FLAG13

R/W

2

FLAG12

R/W

1

FLAG10

R/W

0

FLAG8

R/W

Initial value : 00H

T0OVIFR

T0IFR

SIOIFR

When T0 Overflow Interrupt occurrs, this bit becomes

„1‟. For clearing bit, write „0‟ to this bit or auto clear by INT_ACK signal.

0 T0 overflow interrupt no generation

1 T0 overflow interrupt generation

When T0 Match Interrupt occurrs, this bit becomes


0 T0 match interrupt no generation

1 T0 match interrupt generation

When Serial I/O Interrupt occurrs, this bit becomes


0 Serial I/O interrupt no generation

1 Serial I/O interrupt generation

EIFLAG0[3:0] When an External Interrupt is occurred, the flag becomes

„1‟. The flag is cleared by writing

„0‟ to the bit or automatically cleared by

INT_ACK signal.

0

1

External Interrupt not occurred

External Interrupt occurred

EIPOL0 (External Interrupt Polarity 0 Register): A4H

7 6 5 4

POL13 POL12

R/W R/W R/W R/W

3

R/W

POL10

2

R/W

1

R/W

0

POL8

R/W

Initial value: 00H

EIPOL0[7:0] External Interrupt (EINT8, EINT10, EINT12, EINT13) polarity selection

POLn[1:0] Description

0

0

1

1

Where n = 8, 10, 12 and 13

0

1

0

1

No interrupt at any edge

Interrupt on rising edge

Interrupt on falling edge

Interrupt on falling/rising edge

April 20, 2012 Ver. 2.5 115

MC96F7816/C7816

EIFLAG1 (External Interrupt Flag 1 Register) : A5H

7

FLAG7

R/W

6

FLAG6

R/W

5

FLAG5

R/W

4

FLAG4

R/W

3

FLAG3

R/W

2

FLAG2

R/W

1

FLAG1

R/W

0

FLAG0

R/W

Initial value : 00H

EIFLAG1[7:0] When an External Interrupt is occurred, the flag becomes

„1‟. The flag is cleared only by writing „0‟ to the bit. So, the flag should be cleared by software.

0

1

External Interrupt not occurred

External Interrupt occurred

EIPOL1L (External Interrupt Polarity 1 Low Register) : A6H

7 6 5 4 3

POL3 POL2

R/W R/W R/W R/W R/W

POL1

2

R/W

1

R/W

0

POL0

R/W

Initial value : 00H

EIPOL1L[7:0] External Interrupt (EINT0, EINT1, EINT2, EINT3) polarity selection


0

0

0

1

No interrupt at any edge


1

1

Where n = 0, 1, 2 and 3

0

1



EIPOL1H(External Interrupt Polarity 1 High Register) : A7H

7 6 5 4 3

POL7 POL6

R/W R/W R/W R/W R/W

POL5

2

R/W

1

R/W

0

POL4

R/W

Initial value : 00H

EIPOL1H[7:0] External Interrupt (EINT4, EINT5, EINT6, EINT7) polarity selection


0 0 No interrupt at any edge

0

1

1

Where n = 4, 5, 6 and 7

1

0

1




116 April 20, 2012 Ver. 2.5

12. Peripheral Hardware

12.1 Clock Generator

12.1.1 Overview

MC96F7816/C7816

As shown in Figure 12.1, the clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and the peripheral hardware. It contains main/sub-frequency clock oscillator. The main/sub clock operation can be easily obtained by attaching a crystal between the XIN/SXIN and XOUT/SXOUT pin, respectively. The main/sub clock can be also obtained from the external oscillator. In this case, it is necessary to put the external clock signal into the XIN/SXIN pin and open the XOUT/SXOUT pin. The default system clock is 1MHz INT-RC Oscillator and the default division rate is four. In order to stabilize system internally, it is used 1MHz INT-RC oscillator on POR.

- Calibrated Internal RC Oscillator (4 MHz)

. INT-RC OSC/1 (4 MHz)

. INT-RC OSC/2 (2 MHz)

. INT-RC OSC/4 (1 MHz, Default system clock)

. INT-RC OSC/8 (0.5 MHz)

- Main Crystal Oscillator (1~12 MHz for MC96F7816, 1~10 MHz for MC96C7816)

- Sub Crystal Oscillator (32.768 kHz)

- Internal WDTRC Oscillator (6 kHz)

12.1.2 Block Diagram

XIN

XOUT

STOP Mode

XCLKE

STOP Mode

IRCE

SXIN

SXOUT

STOP Mode

SCLKE

Main OSC f

XIN

Internal RC OSC

(4MHz)

1/1

1/2

1/4

1/8

M

U

X f

IRC

Clock

Change

DCLK

System

Clock Gen.

SCLK (fx)

(Core, System,

Peripheral)

Sub OSC

WT

2

IRCS[1:0] f

SUB

2

SCLK[1:0]

/4096

BIT clock

WDTRC OSC

(6kHz)

BIT

Stabilization Time

Generation

BIT overflow

WDT clock

M

U

X

/256

WDT

STOP Mode

WONS

Figure 12.1 Clock Generator Block Diagram

April 20, 2012 Ver. 2.5 117

MC96F7816/C7816


Table 12-1 Clock Generator Register Map

Name

SCCR

OSCCR

Address

8AH

C8H

Dir

R/W

R/W

Default

00H

08H

12.1.4 Clock Generator Register Description

Description

System and Clock Control Register

Oscillator Control Register

The clock generator register uses clock control for system operation. The clock generation consists of System and clock control register and oscillator control register.

118 April 20, 2012 Ver. 2.5

MC96F7816/C7816

12.1.5 Register Description for Clock Generator

SCCR (System and Clock Control Register) : 8AH

7

WONS

R/W

6

PSAVE

R/W

WONS

PSAVE

SCLK [1:0]

5

-

-

4

-

-

3

-

-

2

-

-

1

SCLK1

R/W

0

SCLK0

R/W

Initial value : 00H

Control the Operation of WDT RC-Oscillation during STOP mode

0 WDTRC-Oscillator is disabled at STOP mode

1 WDTRC-Oscillator is enabled at STOP mode

Notes)

1. When this bit is

“1”, the WDTRC oscillator (6kHz) is oscillated and selected as the clock source of the WDT block in the STOP mode, but the WDTRC stops and the BIT overflow clock is the clock source for the WDT block at normal mode.

2. When this bit is

“0”, the WDTRC is always stopped and the BIT overflow clock is selected as the clock source for the WDT block

Power Save Mode Control Bit

0 Normal circuit for sub oscillator

1 Power saving circuit for sub oscillator

Notes)

1. A capacitor (0.1

μF) should be connected between VREG and

VSS when the sub oscillator is used to power saving mode.

2. The PSAVE automatically cleared to

„0‟ when the sub oscillator is stopped by SCLKE or CPU is entered into STOP mode in sub operating mode.

3. The delay is needed 500ms over from sub osc start to PSAVE change to

“1”.

System Clock Selection Bit

SCLK1 SCLK0 Description

0

0

0

1

INT RC OSC for system clock

External Main OSC (f

XIN

) for system clock

Note) PFSR9[1:0] keep always

„11b‟ and

P9PU[1:0] keep always „00b‟

1 x External Sub OSC (f

SUB

) for system clock

Where x is “don‟t care.”

April 20, 2012 Ver. 2.5 119

MC96F7816/C7816

OSCCR (Oscillator Control Register) : C8H

7 6 5 4

-

-

-

-

IRCS[1:0]

IRCE

XCLKE

SCLKE

-

-

IRCS1

R/W

3

IRCS0

R/W

2

IRCE

R/W

1

XCLKE

R/W

0

SCLKE

R/W

Initial value : 08H

Internal RC Oscillator Post-divider Selection

IRCS1 IRCS0 Description

0 0 INT-RC/8 (0.5MHz)

0

1

1

0

INT-RC/4 (1MHz)

INT-RC/2 (2MHz)

1 1 INT-RC/1 (4MHz)

Control the Operation of the Internal RC Oscillator

0

1

Enable operation of INT-RC OSC

Disable operation of INT-RC OSC

Control the Operation of the External Main Oscillator

0 Disable operation of X-TAL

1 Enable operation of X-TAL

Note) PFSR9[1:0] keep always „11b‟ and P9PU[1:0] keep always

„00b‟

Control the Operation of the External Sub Oscillator

0

1

Disable operation of SX-TAL

Enable operation of SX-TAL

Note) The delay is needed 500ms over from sub osc start to PSAVE change to “1”.

120 April 20, 2012 Ver. 2.5

12.2 Basic Interval Timer

12.2.1 Overview

MC96F7816/C7816

The MC96F7816 has one 8-bit basic interval timer that is free-run and can ‟t stop. Block diagram is shown in

Figure 12.2. In addition, the basic interval timer generates the time base for watchdog timer counting. It also provides a basic interval timer interrupt (BITIFR).

The MC96F7816 has these basic interval timer (BIT) features:

- During Power On, BIT gives a stable clock generation time

- On exiting Stop mode, BIT gives a stable clock generation time

- As timer function, timer interrupt occurrence


BIT Clock

RESET

STOP

BCK[2:0]

Start CPU

8-Bit Up Counter

BITCNT clear

BCLR selected bit overflow

WDT

BITIFR clear

INT_ACK

To interrupt block

Figure 12.2 Basic Interval Timer Block Diagram

April 20, 2012 Ver. 2.5 121

MC96F7816/C7816


Table 12-2 Basic Interval Timer Register Map

Name

BITCNT

BITCR

Address

8CH

8BH

Dir

R

R/W

Default

00H

01H

12.2.4 Basic Interval Timer Register Description

Description

Basic Interval Timer Counter Register

Basic Interval Timer Control Register

The basic interval timer register consists of basic interval timer counter register (BITCNT) and basic interval timer control register (BITCR). If BCLR bit is set to „1‟, BITCNT becomes „0‟ and then counts up. After 1 machine cycle, BCLR bit is cleared to „0‟ automatically.

12.2.5 Register Description for Basic Interval Timer

BITCNT (Basic Interval Timer Counter Register) : 8CH

7

BITCNT7

R

6

BITCNT6

R

5

BITCNT5

R

4

BITCNT4

R

3

BITCNT3

R

2

BITCNT2

R

1

BITCNT1

R

0

BITCNT0

R

Initial value : 00H

BITCNT[7:0] BIT Counter

BITCR (Basic Interval Timer Control Register) : 8BH

7

BITIFR

R/W

6

-

-

BITIFR

BCLR

BCK[2:0]

5

-

-

4

-

-

3

BCLR

R/W

2

BCK2

R/W

1

BCK1

R/W

0

BCK0

R/W

Initial value : 01H

1

1

1

1

When BIT Interrupt occurs, this bit becomes


0 BIT interrupt no generation

1 BIT interrupt generation

If this bit is written to

„1‟, BIT Counter is cleared to „0‟

0 Free Running

0

0

0

0

1 Clear Counter

Select BIT overflow period

BCK2 BCK1 BCK0 Description

0

0

1

1

0

1

0

1

Bit 0 overflow (BIT Clock * 2)

Bit 1 overflow (BIT Clock * 4) (default)



0

0

1

1

0

1

0

1





122 April 20, 2012 Ver. 2.5

12.3 Watch Dog Timer

12.3.1 Overview

MC96F7816/C7816

The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or something like that, and resumes the CPU to the normal state. The watchdog timer signal for malfunction detection can be used as either a CPU reset or an interrupt request. When the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals. It is possible to use free running 8bit timer mode (WDTRSON=

‟0‟) or watch dog timer mode (WDTRSON=‟1‟) as setting WDTCR[6] bit. If WDTCR[5] is written to „1‟, WDT counter value is cleared and counts up. After 1 machine cycle, this bit is cleared to „0‟ automatically. The watchdog timer consists of 8-bit binary counter and the watchdog timer data register. When the value of 8-bit binary counter is equal to the 8 bits of WDTCNT, the interrupt request flag is generated. This can be used as watchdog timer interrupt or reset of CPU in accordance with the bit WDTRSON.

The input clock source of Watch Dog Timer is the BIT overflow. The interval of watchdog timer interrupt is decided by BIT overflow period and WDTDR set value. The equation can be described as

WDT Interrupt Interval = (BIT Interrupt Interval) X (WDTDR Value+1)

12.3.2 WDT Interrupt Timing Waveform

Source Clock

BIT Overflow

WDTCNT[7:0] 0

WDTDR[7:0]

WDTIFR

Interrupt

WDTRESETB

1 n

2 3 0 1 2 3

3

WDTCL

Occur

WDTDR  0000_0011b

Match

Detect

0 1

Counter Clear

2

RESET

Figure 12.3 Watch Dog Timer Interrupt Timing Waveform

April 20, 2012 Ver. 2.5 123

MC96F7816/C7816


WDT Clock

WDTEN

WDTCNT clear

To RESET

Circuit

WDTDR

WDTCL

WDTCR

WDTRSON

WDTIFR clear

INT_ACK

To interrupt block

Figure 12.4 Watch Dog Timer Block Diagram


Table 12-3 Watch Dog Timer Register Map

Name

WDTCNT

WDTDR

WDTCR

Address

8EH

8EH

8DH

Dir

R

W

R/W

Default

00H

FFH

00H

12.3.5 Watch Dog Timer Register Description

Description

Watch Dog Timer Counter Register

Watch Dog Timer Data Register

Watch Dog Timer Control Register

The watch dog timer register consists of watch dog timer counter register (WDTCNT), watch dog timer data register (WDTDR) and watch dog timer control register (WDTCR).

124 April 20, 2012 Ver. 2.5

12.3.6 Register Description for Watch Dog Timer

MC96F7816/C7816

WDTCNT (Watch Dog Timer Counter Register: Read Case) : 8EH

7 6 5 4 3 2 1 0

WDTCNT 7 WDTCNT 6 WDTCNT 5 WDTCNT 4 WDTCNT3 WDTCNT 2 WDTCNT 1 WDTCNT 0

R R R R R R R R

Initial value : 00H

WDTCNT[7:0] WDT Counter

WDTDR (Watch Dog Timer Data Register: Write Case) : 8EH

7 6 5 4 3

WDTDR 7

W

WDTDR 6

W

WDTDR 5

W

WDTDR 4

W

WDTDR 3

W

2

WDTDR 2

W

1

WDTDR 1

W

0

WDTDR 0

W

Initial value : FFH

WDTDR[7:0]

WDTCR (Watch Dog Timer Control Register) : 8DH

7 6 5 4

WDTEN

R/W

WDTRSON

R/W

WDTEN

WDTRSON

WDTCL

WDTCL

R/W

WDTIFR

-

-

3

-

-

2

-

-

1

-

-

0

WDTIFR

R/W

Initial value : 00H

Control WDT Operation

0

1

Disable

Enable

Control WDT RESET Operation

0 Free Running 8-bit timer

1 Watch Dog Timer RESET ON

Clear WDT Counter

0 Free Run

1 Clear WDT Counter (auto clear after 1 Cycle)

When WDT Interrupt occurs, this bit becomes

„1‟. For clearing bit, write

„0‟ to this bit or auto clear by INT_ACK signal.

0 WDT Interrupt no generation

1 WDT Interrupt generation

Set a period

WDT Interrupt Interval=(BIT Interrupt Interval) x(WDTDR Value+1)

Note) Do not write “0” in the WDTDR register.

April 20, 2012 Ver. 2.5 125

MC96F7816/C7816

12.4 Watch Timer

12.4.1 Overview

The watch timer has the function for RTC (Real Time Clock) operation. It is generally used for RTC design. The internal structure of the watch timer consists of the clock source select circuit, timer counter circuit, output select circuit, and watch timer control register. To operate the watch timer, determine the input clock source, output interval, and set WTEN to

„1‟ in watch timer control register (WTCR). It is able to execute simultaneously or individually. To stop or reset WT, clear the WTEN bit in WTCR register. Even if CPU is STOP mode, sub clock is able to be so alive that WT can continue the operation. The watch timer counter circuits may be composed of 21bit counter which contains low 14-bit with binary counter and high 7-bit counter in order to raise resolution. In

WTDR, it can control WT clear and set interval value at write time, and it can read 7-bit WT counter value at read time.

The watch timer supplies the clock frequency for the LCD driver (f

LCD

). Therefore, if the watch timer is disabled, the LCD driver controller does not operate.

12.4.2 Block Diagram fx

P r c a e s l e r f

SUB fx/64 fx/128 fx/256

M

U

X

WTCR WTEN f

WCK 14Bit

Binary Counter f

WCK

/2

14

WTIFR WTIN1 WTIN0 WTCK1 WTCK0 f LCD =1024Hz

Timer counter

Clear Match

WTCL

Comparator match f

WCK

14

/(2 X(7 bit WTDR Value +1)) f

WCK

/2

14 f

WCK

/2

13 f

WCK

/2 7

MUX

WTIFR

Clear

2

INT_ACK

Reload Match

WTCL

To interrupt block

WTDR

Write case

WTCL WTDR6 WTDR5 WTDR4 WTDR3 WTDR2 WTDR1 WTDR0

WTCNT

Read case

WTCNT6 WTCNT5 WTCNT4 WTCNT3 WTCNT2 WTCNT1 WTCNT0

Figure 12.5 Watch Timer Block Diagram

126 April 20, 2012 Ver. 2.5


MC96F7816/C7816

Table 12-4 Watch Timer Register Map

Name

WTCNT

WTDR

WTCR

Address

89H

89H

96H

Dir

R

W

R/W

Default

00H

7FH

00H

12.4.4 Watch Timer Register Description

Description

Watch Timer Counter Register

Watch Timer Data Register

Watch Timer Control Register

The watch timer register consists of watch timer counter register (WTCNT), watch timer data register (WTDR), and watch timer control register (WTCR). As WTCR is 6-bit writable/ readable register, WTCR can control the clock source (WTCK[1:0]), interrupt interval (WTIN[1:0]), and function enable/disable (WTEN). Also there is WT interrupt flag bit (WTIFR).

12.4.5 Register Description for Watch Timer

WTCNT (Watch Timer Counter Register: Read Case) : 89H

7

-

-

6

WTCNT 6

R

5

WTCNT 5

R

4

WTCNT 4

R

3

WTCNT 3

R

2

WTCNT 2

R

1

WTCNT 1

R

0

WTCNT0

R

Initial value : 00H

WTCL

R/W W

WTCNT[6:0]

WTDR (Watch Timer Data Register: Write Case) : 89H

7 6 5 4

WTDR 6

WTCL

WTDR 5

W

WTDR[6:0]

WT Counter

WTDR 4

W

3

WTDR 3

W

2

WTDR 2

W

1

WTDR 1

W

0

WTDR 0

W

Initial value : 7FH

Clear WT Counter

0

1

Free Run

Clear WT Counter (auto clear after 1 Cycle)

Set WT period

WT Interrupt Interval=fwck/(2^14 x(7bit WTDR Value+1))

Note) Do not write “0” in the WTDR register.

April 20, 2012 Ver. 2.5 127

MC96F7816/C7816

WTCR (Watch Timer Control Register) : 96H

7 6 5 4

WTEN

R/W

-

-

-

-

WTIFR

R/W

3

WTIN1

R/W

2

WTIN0

R/W

1

WTCK1

R/W

0

WTCK0

R/W

Initial value : 00H

WTEN

WTIFR

Control Watch Timer

0 Disable

1 Enable

When WT Interrupt occurs, this bit becomes


0

1

WT Interrupt no generation

WT Interrupt generation

WTIN[1:0]

WTCK[1:0]

Determine interrupt interval

WTIN1 WTIN0 Description

0

0

0

1 f

WCK

/2^7 f

WCK

/2^13 f

WCK

/2^14 1

1

0

1 f

WCK

/(2^14 x (7bit WTDR Value+1))

Determine Source Clock

WTCK1 WTCK0 Description

0

0

1

1

0

1

0

1 f

SUB f

X

/256 f

X

/128 f

X

/64

NOTE) f

X

– System clock frequency (Where fx= 4.19MHz) f

SUB

– Sub clock oscillator frequency (32.768kHz) f

WCK

– Selected Watch timer clock f

LCD

– LCD frequency (Where f

X

= 4.19MHz, WTCK[1:0]=

‟10‟; f

LCD

= 1024Hz)

128 April 20, 2012 Ver. 2.5

12.5 Timer 0

12.5.1 Overview

MC96F7816/C7816

The 8-bit timer 0 consists of multiplexer, timer 0 counter register, timer 0 data register, timer 0 capture data register and timer 0 control register (T0CNT, T0DR, T0CDR, T0CR).

It has three operating modes:

- 8-bit timer/counter mode

- 8-bit PWM output mode

- 8-bit capture mode

The timer/counter 0 can be clocked by an internal or an external clock source (EC0). The clock source is selected by clock selection logic which is controlled by the clock selection bits(T0CK[2:0]).

- TIMER0 clock source: f

X

/2, 4, 8, 32, 128, 512, 2048 and EC0

In the capture mode, by EINT10, the data is captured into input capture data register (T0CDR). In timer/counter mode, whenever counter value is equal to T0DR, T0O port toggles. Also the timer 0 outputs PWM wave form through PWM0O port in the PWM mode.

Table 12-5 Timer 0 Operating Modes

T0EN

1

1

1

PFSR92 T0MS[1:0] T0CK[2:0]

1

1

0

00

01

1X

XXX

XXX

XXX

Timer 0

8 Bit Timer/Counter Mode

8 Bit PWM Mode

8 Bit Capture Mode

April 20, 2012 Ver. 2.5 129

MC96F7816/C7816

12.5.2 8-Bit Timer/Counter Mode

The 8-bit timer/counter mode is selected by control register as shown in Figure 12.6.

The 8-bit timer have counter and data register. The counter register is increased by internal or external clock input. Timer 0 can use the input clock with one of 2, 4, 8, 32, 128, 512 and 2048 prescaler division rates

(T0CK[2:0]). When the value of T0CNT and T0DR is identical in timer 0, a match signal is generated and the interrupt of Timer 0 occurs. T0CNT value is automatically cleared by match signal. It can be also cleared by software (T0CC).

The external clock (EC0) counts up the timer at the rising edge. If the EC0 is selected as a clock source by

T0CK[2:0], EC0 port should be set to the input port by P92IO bit.

T0CR T0EN

1

-

-

T0MS1 T0MS0 T0CK2 T0CK1 T0CK0

0 0 x x x

T0CC x

ADDRESS : B2H

INITIAL VALUE: 0000_0000B

EC0 fx e s

P r c a l e r fx/2 fx/4 fx/8 fx/32 fx/128 fx/512 fx/2048

M

U

X

3

T0CK[2:0]

T0EN

8-bit Timer 0 Counter

T0CNT(8Bit)

Clear

T0DR(8Bit)

Match

Comparator

MUX

2

T0MS[1:0]

8-bit Timer 0 Data Register

Figure 12.6 8-Bit Timer/Counter Mode for Timer 0

T0CC

Match signal

INT_ACK

Clear

T0IFR

To interrupt block

T0O/PWM0O

130 April 20, 2012 Ver. 2.5

T0CNT

Value

Timer 0

(T0IFR)

Interrupt

MC96F7816/C7816

Match with T0DR n-2 n-1 n

0

1

2

Up-count

5

4

6

3

Interrupt Period

= P

CP

x (n+1)

Count Pulse Period

P

CP

Occur

Interrupt

Occur

Interrupt

Figure 12.7 8-Bit Timer/Counter 0 Example

TIME

Occur

Interrupt

April 20, 2012 Ver. 2.5 131

MC96F7816/C7816

12.5.3 8-Bit PWM Mode

The timer 0 has a high speed PWM (Pulse Width Modulation) function. In PWM mode, T0O/PWM0O pin outputs up to 8-bit resolution PWM output. This pin should be configured as a PWM output by setting P9FSR[2] to „1‟. In the 8-bit timer/counter mode, a match signal is generated when the counter value is identical to the value of T0DR. When the value of T0CNT and T0DR is identical in timer 0, a match signal is generated and the interrupt of timer 0 occurs. In PWM mode, the match signal does not clear the counter. Instead, it runs continuously, overflowing at “FFH”, and then continues incrementing from “00H”. The timer 0 overflow interrupt is generated whenever a counter overflow occurs. T0CNT value is cleared by software (T0CC) bit.

T0CR T0EN

1

-

-

T0MS1 T0MS0 T0CK2 T0CK1 T0CK0

0 1 x x x

T0CC x

ADDRESS : B2H


EC0

INT_ACK

Clear

T0OVIFR

Clear

T0CC

To interrupt block fx e s

P r c a l e r fx/2 fx/4 fx/8 fx/32 fx/128 fx/512 fx/2048

M

U

X

3

T0CK[2:0]

T0EN


T0CNT(8Bit)

T0DR(8Bit)

Match

Comparator

MUX

2

T0MS[1:0]


INT_ACK

Clear

T0IFR

To interrupt block

T0O/PWM0O

Figure 12.8 8-Bit PWM Mode for Timer 0

132 April 20, 2012 Ver. 2.5

PWM Mode(T0MS = 01b)

Set T0EN

(Clear and Start)

Timer 0 clock

T0CNT XX 00H 01H 02H

T0DR

T0 Overflow

Interrupt

1. T0DR = 4AH

T0PWM

T0 Match

Interrupt

2. T0DR = 00H

T0PWM

T0 Match

Interrupt

3. T0DR = FFH

T0PWM

T0 Match

Interrupt

4AH

MC96F7816/C7816

FEH FFH 00H

Figure 12.9 PWM Output Waveforms in PWM Mode for Timer 0

April 20, 2012 Ver. 2.5 133

MC96F7816/C7816

12.5.4 8-Bit Capture Mode

The timer 0 capture mode is set by T0MS[1:0] as „1x‟. The clock source can use the internal/external clock.

Basically, it has the same function as the 8-bit timer/counter mode and the interrupt occurs when T0CNT is equal to T0DR. T0CNT value is automatically cleared by match signal and it can be also cleared by software (T0CC).

This timer interrupt in capture mode is very useful when the pulse width of captured signal is wider than the maximum period of timer.

The capture result is loaded into T0CDR.

According to EIPOL0 register setting, the external interrupt EINT10 function is chosen. Of cource, the EINT10 pin must be set to an input port.

T0CDR and T0DR are in the same address. In the capture mode, reading operation reads T0CDR, not T0DR and writing operation will update T0DR.

T0CR T0EN

1

-

-

T0MS1 T0MS0

1 x

T0CK2 x

T0CK1 T0CK0 x x

T0CC x

ADDRESS : B2H


EC0 fx


T0CNT(8Bit)

Clear

P r e s c a l e r fx/2 fx/4 fx/8 fx/32 fx/128 fx/512 fx/2048

M

U

X

3

T0CK[2:0]

T0EN

Clear

T0DR(8Bit)

Match

Comparator

MUX

2

T0MS[1:0]


T0CC

Match signal

INT_ACK

Clear

T0IFR

EINT10

2

EIPOL0[3:2]

T0CDR(8Bit)

2

T0MS[1:0]

INT_ACK

Clear

FLAG10

(EIFLAG0.1)

Figure 12.10 8-Bit Capture Mode for Timer 0

To interrupt block

To interrupt block

134 April 20, 2012 Ver. 2.5

T0CNT Value

MC96F7816/C7816

T0CDR Load n-2 n-1 n

0

1

2

Up-count

5

4

3

6


P

CP

TIME

Ext. EINT10 PIN

Interrupt

Request

(FLAG10)

Interrupt Interval Period

Figure 12.11 Input Capture Mode Operation for Timer 0

FF

H

FF

H

XX

H

T0CNT

00

H

Interrupt

Request

(T0IFR)

Ext. EINT10 PIN

Interrupt

Request

(FLAG10)

00

H

00

H

Interrupt Interval Period = FF

H

+01

H

+FF

H

+01

H

+YY

H

+01

H

Figure 12.12 Express Timer Overflow in Capture Mode

YY

H

00

H

00

H

April 20, 2012 Ver. 2.5 135

MC96F7816/C7816


EC0 fx

EINT10 a l e s c r

P r e fx/2 fx/4 fx/8 fx/32 fx/128 fx/512 fx/2048

M

U

X

3

T0CK[2:0]

T0EN

Clear

INT_ACK

Clear

T0OVIFR

To interrupt block


T0CNT (8Bit)

Clear

Match

Comparator

T0DR (8Bit)


MUX

2

T0MS[1:0]

T0CC

Match signal

INT_ACK

Clear

T0IFR

To interrupt block

T0O/PWM0O

T0CDR (8Bit)

2

EIPOL0[3:2]

2

T0MS[1:0]

INT_ACK

Clear

FLAG10

(EIFLAG0.1)

To interrupt block

Figure 12.13 8-Bit Timer 0 Block Diagram

136 April 20, 2012 Ver. 2.5


MC96F7816/C7816

Table 12-6 Timer 0 Register Map

Name

T0CNT

T0DR

T0CDR

T0CR

Address

B3H

B4H

B4H

B2H

Dir

R

R/W

R

R/W

Default

00H

FFH

00H

00H

Description


Timer 0 Data Register

Timer 0 Capture Data Register


12.5.6.1 Timer/Counter 0 Register Description

The timer/counter 0 register consists of timer 0 counter register (T0CNT), timer 0 data register (T0DR), timer 0 capture data register (T0CDR), and timer 0 control register (T0CR). The T0IFR and T0OVIFR bits are in the timer interrupt flag register (TIFR).

12.5.6.2 Register Description for Timer/Counter 0

T0CNT (Timer 0 Counter Register) : B3H

7 6 5

T0CNT7

R

T0CNT6

R

T0CNT5

R

4

T0CNT4

R

3

T0CNT3

R

2

T0CNT2

R

1

T0CNT1

R

0

T0CNT0

R

Initial value : 00H

T0DR7

R/W

T0CNT[7:0]

T0DR6

R/W

T0DR5

R/W

T0 Counter

T0DR (Timer 0 Data Register: Write Case when Capture mode) : B4H

7 6 5 4 3 2

T0DR4

R/W

T0DR3

R/W

T0DR2

R/W

T0DR[7:0] T0 Data

T0CDR (Timer 0 Capture Data Register: Read Case, Capture mode only) : B4H

7 6 5 4 3 2

T0CDR7

R

T0CDR6

R

T0CDR5

R

T0CDR4

R

T0CDR3

R

T0CDR2

R

1

T0CDR1

R

0

T0CDR0

R

Initial value : 00H

T0CDR[7:0] T0 Capture

1

T0DR1

R/W

0

T0DR0

R/W

Initial value : FFH

April 20, 2012 Ver. 2.5 137

MC96F7816/C7816

T0CR (Timer 0 Control Register) : B2H

7 6 5

T0EN

R/W

-

-

T0MS1

R/W

4

T0MS0

R/W

3

T0CK2

R/W

2

T0CK1

R/W

1

T0CK0

R/W

0

T0CC

R/W

Initial value : 00H

T0EN

T0MS[1:0]

T0CK[2:0]

T0CC

Control Timer 0

0

1

Timer 0 disable

Timer 0 enable

Control Timer 0 Operation Mode

T0MS1 T0MS0 Description

0

0

0

1

Timer/counter mode (T0O: toggle at match)

PWM mode (The overflow interrupt can occur)

0

0

0

1

1

1 x Capture mode (The match interrupt can occur)

Select Timer 0 clock source. fx is a system clock frequency

T0CK2 T0CK1 T0CK0 Description

0 0 0 fx/2

0

1

1

0

0

1

0

1

0

1 fx/4 fx/8 fx/32 fx/128 fx/512

1

1

1

1

1

0

1

Clear timer 0 Counter

0 No effect fx/2048

External Clock (EC0)

Clear the Timer 0 counter (When write, automatically cleared

“0” after being cleared counter)

Notes) 1. Match Interrupt is generated in Capture mode.

2. Refer to the external interrupt flag 0 register (EIFLAG0) for the T0 overflow and interval interrupt flags.

138 April 20, 2012 Ver. 2.5

12.6 Timer 1

12.6.1 Overview

MC96F7816/C7816

The 8-bit timer 1 consists of multiplexer, timer 1 counter register, timer 1 data high/low register, and timer 1 control register (T1CNT, T1DRH, T1DRL, T1CR) . For carrier mode, it has the carrier control register (CARCR).

It has two operating modes:


- 8-bit carrier mode

The timer/counter 1 can be clocked by an internal clock source. The clock source is selected by clock selection logic which is controlled by the clock selection bits (T1CK[1:0]).


X

/1, fx/2, fx/4, fx/8

In the carrier mode, Timer 1 can be used to generate the carrier frequency or a remote controller signal. Timer 1 can output the comparison result between T1CNT & T1DRH/L and carrier frequency through REM port. T1CNT value is cleared by hardware.


T1EN

1

1

1

PFSR03

1

1

1

CAR1

0

1

1

T1CK[1:0]

XXX

XXX

XXX

CMOD

0

0

1

Timer 1

8 Bit Timer/Counter

8 Bit Carrier (One-shot)

8 Bit Carrier (Repeat)

April 20, 2012 Ver. 2.5 139

MC96F7816/C7816

12.6.2 8-Bit Timer/Counter 1 Mode


The 8-bit timer have counter and data register. The counter register is increased by internal clock source.

Timer 1 can use the input clock with one of 1, 2, 4 and 8 prescaler division rates (T1CK[1:0]). When the value of

T1CNT and the T1DRH is identical in Timer 1, a match signal is generated and the interrupt of Timer 1 occurs.

The match signal generates a timer 1 interrupt and clear the counter. The timer 1 interval can be output through

REM port.

T1CR T1EN

1

T1IFR x -

CAR1

0

T1CK1 T1CK0 x x

T1CN x

T1ST x

ADDRESS : BAH

INITIAL VALUE: 0000_0000B fx

Pre scaler fx/1 fx/2 fx/4 fx/8

M

U

X

T1ST


T1CNT (8Bit)

Clear

INT_ACK

Clear

Match

T1EN

T1IFR

2

T1CK[1:0]

Comparator

T1DRH (8Bit)

8-bit Timer 1 Data high Register

REMO

T1M

(T3 clock source)


To interrupt block

REM

140 April 20, 2012 Ver. 2.5

T1CNT

Value

Timer 1

(T1IFR)

Interrupt

T1CNT

Value

MC96F7816/C7816

Match with T1DR n-2 n-1 n

0

1

2

Up-count

5

4

6

3


= P

CP

x (n+1)


P

CP

Occur

Interrupt

Occur

Interrupt


Match with T1DR

Disable Enable

Clear&Start

STOP

Up-count

TIME

Occur

Interrupt

TIME

Timer 1

(T1IFR)

Interrupt

T1ST

Start&Stop

T1CN

Control count

Occur

Interrupt

Occur

Interrupt

T1ST = 1

T1ST = 0

T1ST = 1

T1CN = 1

T1CN = 1

T1CN = 0

Figure 12.16 8-Bit Timer/Counter 1 Counter Operation

April 20, 2012 Ver. 2.5 141

MC96F7816/C7816

12.6.3 8-Bit Timer 1 Carrier Frequency Mode.

The carrier frequency and the pulse of data are calculated by the formula in the following sheet .The Figure

12.17 shows the block diagram of Timer 1 for carrier frequency mode.

T1CR T1EN

1

T1IFR x -

CAR1

1

T1CK1 T1CK0 x x

T1CN x

T1ST x

ADDRESS : BAH

INITIAL VALUE: 0000_0000B fx


M

U

X

2

T1CK[1:0]

T1EN

CMOD

T1ST


T1CNT (8Bit)

Clear

T1M

(T3 clock source)

MUX

Match

Comparator

REMO REM

T1IT

T1DRL (8Bit)

T1IFR

Clear

INT_ACK

To interrupt block

T1DRH (8Bit)

Figure 12.17 Carrier Mode for Timer 1

Note)

When one of T1DRH and T1DRL values is “00H”, the carrier frequency generator (REM) output always becomes a “High” or “Low”. At that time, Timer 1 Interrupt Flag Bit (T1IFR) is not set.

142 April 20, 2012 Ver. 2.5

12.6.4 Carrier Output Pulse Width Calculatins

MC96F7816/C7816 t

LOW t

HIGH t

LOW

To generate the above repeated waveform consisted of low period time (t

LOW

), and high period time (t

HIGH

).

When REMO = 0, t

LOW

= (T1DRL + 1) x 1/f

T1

, 0H < T1DRL < 100H, where f

T1

= The selected clock. t

HIGH

= (T1DRH + 1) x 1/f

T1

, 0H < T1DRH < 100H, where f

T1

= The selected clock.

When REMO = 1, t

LOW

= (T1DRH + 1) x 1/f

T1

, 0H < T1DRH < 100H, where f

T1

= The selected clock. t

HIGH

= (T1DRL + 1) x 1/f

T1

, 0H < T1DRL < 100H, where f

T1

= The selected clock.

To make t

LOW

= 24 us and t

HIGH

= 15 us. f

X

= 4 MHz, f

T1

= 4 MHz/4 = 1 MHz

When REMO = 0, t

LOW

= 24 us = (T1DRL + 1) /f

T1

= (T1DRL + 1) x 1us, T1DRL = 22. t

HIGH

= 15 us = (T1DRH + 1) /f

T1

= (T1DRH + 1) x 1us, T1DRH = 13.

When REMO = 1, t

LOW

= 24 us = (T1DRH + 1) / f

T1

= (T1DRH + 1) x 1us, T1DRH = 22. t

HIGH

= 15 us = (T1DRL + 1) / f

T1

= (T1DRL + 1) x 1us, T1DRL = 13.

April 20, 2012 Ver. 2.5 143

MC96F7816/C7816

0H

Timer 1 Clock

(T1CK[1:0])

REMO = '0'

T1DRL = 00H

T1DRH = 00H

REMO = '0'

T1DRL = 00H

T1DRH = 01-FFH

REMO = '0'

T1DRL = 01-FFH

T1DRH = 00H

REMO = '1'

T1DRL = 00H

T1DRH = 00H

REMO = '1'

T1DRL = 00H

T1DRH = 01-FFH

REMO = '1'

T1DRL = 01-FFH

T1DRH = 00H

Low

High

Low

High

Low

High

0H 100H 200H

Timer 1 Clock

(T1CK[1:0])

REMO = '1'

T1DRL = DFH

T1DRH = 1FH

REMO = '0'

T1DRL = DFH

T1DRH = 1FH

REMO = '1'

T1DRL = 7FH

T1DRH = 7FH

80H

E0H

E0H

80H

20H

20H

144

REMO = '0'

T1DRL = 7FH

T1DRH = 7FH

80H

80H

Figure 12.18 Carrier Output Waveforms in Repeat Mode for Timer 1

April 20, 2012 Ver. 2.5


MC96F7816/C7816 fx


M

U

X

2

T1CK[1:0]

T1EN

T1ST


T1CNT (8Bit)

Clear

Match

Comparator

T1DRH (8Bit)

8-bit Timer 1 Data high Register

INT_ACK

Clear

T1IFR

REMO

T1M

(T3 clock source)




Name

T1CNT

T1DRH

T1DRL

T1CR

CARCR

Address

BBH

BDH

BCH

BAH

BEH

Dir

R

R/W

R/W

R/W

R/W

Default

00H

FFH

FFH

00H

00H

Description


Timer 1 Data High Register

Timer 1 Data Low Register


Carrier Control Register


To interrupt block

REM

The timer/counter 1 register consists of timer 1 counter register (T1CNT), timer 1 data high register (T1DRH), timer 1 data low register (T1DRL), timer 1 control register (T1CR) and carrier control register (CARCR).

April 20, 2012 Ver. 2.5 145

MC96F7816/C7816

12.6.6.2 Register description for Timer/Counter 1

T1CNT (Timer 1 Counter Register) : BBH

7 6 5

T1CNT7 T1CNT6 T1CNT5

4

T1CNT4

R R R R

T1CNT[7:0] T1 Counter

T1DRH (Timer 1 Data High Register) : BDH

7 6 5

T1DRH7 T1DRH6 T1DRH5

4

T1DRH4

R/W R/W R/W R/W

3

T1CNT3

R

T1DRH[7:0] T1 Data High

T1DRL (Timer 1 Data Low Register: Carrier mode only) : BCH

7 6 5 4 3

T1DRL7

R/W

T1DRL6

R/W

T1DRL5

R/W

T1DRL4

R/W

T1DRL3

R/W

T1DRL[7:0] T1 Data Low

3

T1DRH3

R/W

2

T1CNT2

R

1

T1CNT1

R

0

T1CNT0

R

Initial value : 00H

2

T1DRH2

R/W

1

T1DRH1

R/W

0

T1DRH0

R/W

Initial value : FFH

2

T1DRL2

R/W

1

T1DRL1

R/W

0

T1DRL0

R/W

Initial value : FFH

146 April 20, 2012 Ver. 2.5

MC96F7816/C7816

T1CR (Timer 1 Control Register) : BAH

7 6 5

T1EN

R/W

T1IFR-

R/W

-

-

4

CAR1

R/W

3

T1CK1

R/W

2

T1CK0

R/W

1

T1CN

R/W

T1EN

T1IFR

CAR1

T1CK[1:0]

T1CN

T1ST

Control Timer 1

0 Timer 1 disable

1 Timer 1 enable

When T1 Match Interrupt occurs, this bit becomes


0

1

T1 match interrupt no generation

T1 match interrupt generation

Control Timer 1 Operation mode

0 Timer/counter mode

1 Carrier mode

Select Timer 1 clock source. fx is system clock frequency

T1CK1 T1CK0 Description

0 0 fx/1

0

1

1

0 fx/2 fx/4

1 1 fx/8

Control Timer 1 Counter pause/continue

0

1

Temporary count stop

Continue count

Control Timer 1 start/stop

0

1

Counter stop

Clear counter and start

CARCR (Carrier Control Register: Carrier mode only) : BEH

7 6 5 4 3

-

-

-

-

T1IT1

R/W

T1IT0

R/W

-

-

2

-

-

1

CMOD

R/W

0

REMO

R/W

Initial value : 00H

T1IT[1:0]

CMOD

REMO

0

T1ST

R/W

Initial value : 00H

T1 Interrupt Time Select

T1IT1 T1IT0 Description

0 0 Elapsed time for low data value

0

1

1

0

Elapsed time for high data value

Elapsed time for low and high data value

1 1 Not available

Carrier Frequency Mode Select

0

1

One-shot mode

Repeating mode

REM Output Control

0 T1DRL→ Low width, T1DRH→ High width

1 T1DRL→ High width, T1DRH→ Low width

April 20, 2012 Ver. 2.5 147

MC96F7816/C7816

12.7 Timer 2

12.7.1.1 Overview

The 16-bit timer 2 consists of multiplexer, timer 2 A data high/low register, timer 2 B data high/low register and timer 2 control high/low register (T2ADRH, T2ADRL, T2BDRH, T2BDRL, T2CRH, T2CRL).

It has four operating modes:



- 16-bit PPG output mode (one-shot mode)

- 16-bit PPG output mode (repeat mode)

The timer/counter 2 can be clocked by an internal or an external clock source (EC2). The clock source is selected by clock selecttion logic which is controlled by the clock selection bits(T2CK[2:0]).


X

/1, 2, 4, 8, 64, 512, 2048 and EC2

In the capture mode, by EINT12, the data is captured into input capture data register (T2BDRH/T2BDRL). n timer/counter mode, whenever counter value is equal to T2ADRH/L, T2O port toggles.. Also the timer 2 outputs

PWM wave form to PWM2O port in the PPG mode.


T2EN

1

1

1

1

PFSR32 T2MS[1:0] T2CK[2:0]

1

0

00

01

XXX

XXX

1

1

10

11

XXX

XXX

Timer 2


16 Bit Capture Mode

16 Bit PPG Mode

(one-shot mode)

16 Bit PPG Mode

(repeat mode)

148 April 20, 2012 Ver. 2.5


MC96F7816/C7816


The 16-bit timer have counter and data register. The counter register is increased by internal or external clock input. Timer 2 can use the input clock with one of 1, 2, 4, 8, 64, 512 and 2048 prescaler division rates (T2CK[2:0]).

When the values of T2CNTH/T2CNTL and T2ADRH/T2ADRL are identical in timer 2, a match signal is generated and the interrupt of Timer 2 occurs. T2CNTH/T2CNTL values are automatically cleared by match signal. It can be also cleared by software (T2CC).

The external clock (EC2) counts up the timer at the rising edge. If the EC2 is selected as a clock source by

T2CK[2:0], EC2 port should be set to the input port by P02IO bit.

T2CRH T2EN

1

–

–

T2MS1 T2MS0

0 0

–

–

–

–

–

–

T2CC

X

ADDRESS:C3H

INITIAL VALUE : 0000_0000B

T2CRL

T2CK2

X

T2CK1 T2CK0 T2IFR

X X X

–

–

T2POL T2ECE T2CNTR

X X X

ADDRESS:C2H


EC2

T2ECE

Edge

Detector fx

16-bit A Data Register

T2ADRH/T2ADRL

T2CK[2:0]

3

Reload

Buffer Register A

A Match

T2CC

T2EN

INT_ACK

Clear l e r e s c a

P r fx/1 fx/2 fx/4 fx/8 fx/64 fx/512 fx/2048

M

U

X

T2EN

A Match

Comparator

Clear

16-bit Counter

T2CNTH/T2CNTL

R

T2IFR

Pulse

Generator


2

T2MS[1:0] T2POL

To interrupt block

A Match

T2CC

T2EN

T2O

April 20, 2012 Ver. 2.5 149

MC96F7816/C7816

T2CNTH/L

Value

Timer 2

(T2IFR)

Interrupt

Match with T2ADRH/L n-2 n-1 n

0

1

2

Up-count

5

4

6

3


= P

CP

x (n+1)


P

CP

Occur

Interrupt

Occur

Interrupt


TIME

Occur

Interrupt

150 April 20, 2012 Ver. 2.5


MC96F7816/C7816

The timer 2 capture mode is set by T2MS[1:0] as „01‟. The clock source can use the internal/external clock.

Basically, it has the same function as the 16-bit timer/counter mode and the interrupt occurs when

T2CNTH/T2CNTL are equal to T2ADRH/T2ADRL. T2CNTH/T2CNTL values are automatically cleared by match signal and it can be also cleared by software (T2CC).


The capture result is loaded into T2BDRH/T2BDRL. In the timer 2 capture mode, timer 2 output(T2O) waveform is not available.

According to EIPOL0 register setting, the external interrupt EINT12 function is chosen. Of cource, the EINT12 pin must be set to an input port.

T2CRH T2EN

1

–

–

T2MS1 T2MS0

0 1

–

–

–

–

–

–

T2CC

X

ADDRESS:C3H


T2CRL T2CK2

X

T2CK1 T2CK0 T2IFR

X X

X

–

–

T2POL T2ECE T2CNTR

X X X

ADDRESS:C2H


EC2


T2ADRH/T2ADRL

Reload

T2ECE

T2CK[2:0]

3

Buffer Register A

A Match

T2CC

T2EN

INT_ACK

Clear

Edge

Detector fx

P s c r e a l e r fx/1 fx/2 fx/4 fx/8 fx/64 fx/512 fx/2048

EIPOL0[5:4]

2

EINT12

M

U

X

T2EN

Clear

A Match

Comparator

Clear

16-bit Counter

T2CNTH/T2CNTL

R

T2IFR

To interrupt block

A Match

T2CC

T2EN

T2CNTR

2

T2MS[1:0]

16-bit B Data Register

T2BDRH/T2BDRL

INT_ACK

Clear

FLAG12

(EIFLAG0.2)


To interrupt block

April 20, 2012 Ver. 2.5 151

MC96F7816/C7816

T2CNTH/L

Value

T2BDRH/L Load n-2 n-1 n

0

1

2

Up-count

5

4

3

6


P

CP

Ext. EINT12 PIN

Interrupt

Request

(FLAG12)



FFFF

H

FFFF

H

XX

H

T2CNTH/L

00

H

Interrupt

Request

(T2IFR)

Ext. EINT12 PIN

Interrupt

Request

(FLAG12)

00

H

00

H

Interrupt Interval Period = FFFF

H

+01

H

+FFFF

H

+01

H

+YY

H

+01

H


YY

H

00

H

00

H

TIME

152 April 20, 2012 Ver. 2.5

12.7.4 16-Bit PPG Mode

MC96F7816/C7816

The timer 2 has a PPG (Programmable Pulse Generation) function. In PPG mode, the T2O/PWM2O pin outputs up to 16-bit resolution PWM output. This pin should be configured as a PWM output by set PFSR32 to

„1‟ . The period of the PWM output is determined by the T2ADRH/T2ADRL. And the duty of the PWM output is determined by the T2BDRH/T2BDRL.

T2CRH T2EN

1

–

–

T2MS1 T2MS0

1 1

–

–

–

–

–

–

T2CC

X

ADDRESS:C3H


T2CRL T2CK2

X

T2CK1 T2CK0 T2IFR

X X X

–

–

T2POL T2ECE T2CNTR

X X X

ADDRESS:C2H


EC2

T2ECE

Edge

Detector fx e s c

P r e r a l fx/1 fx/2 fx/4 fx/8 fx/64 fx/512 fx/2048

T2CK[2:0]

3

M

U

X

T2EN


T2ADRH/T2ADRL

Reload

Buffer Register A

A Match

T2CC

T2EN

INT_ACK

Clear

A Match

Comparator

Clear

16-bit Counter

T2CNTH/T2CNTL

R

Comparator

Buffer Register B

Reload

B Match

T2IFR

To interrupt block

Pulse

Generator

2

T2MS[1:0] T2POL

A Match

T2CC

T2EN

A Match

T2CC

T2EN

T2O/

PWM2O


T2BDRH/T2BDRL

Note) The T2EN is automatically cleared to logic “0” after one pulse is generated at a PPG one-shot mode.

Figure 12.25 16-Bit PPG Mode for Timer 2

April 20, 2012 Ver. 2.5 153

MC96F7816/C7816

Repeat Mode(T2MS = 11b) and "Start High"(T2POL = 0b).

Set T2EN

Clear and Start

Timer 2 clock

Counter X

T2ADRH/L M

0 1 2 3 4 5 6 7 8

T2 Interrupt

1. T2BDRH/L(5) < T2ADRH/L

PWM2O

2. T2BDRH/L >= T2ADRH/L

PWM2O

3. T2BDRH/L = "0000H"

PWM2O

Low Level

B Match

M-1 0 1 2 3 4

A Match

A Match

A Match

One-shot Mode(T2MS = 10b) and "Start High"(T2POL = 0b).

Clear and Start

Set T2EN

Timer 2 clock

Counter X

T2ADRH/L M

0 1 2 3 4 5 6 7 8 M-1

T2 Interrupt


PWM2O B Match A Match


PWM2O

3. T2BDRH/L = "0000H"

PWM2O

Low Level

A Match

A Match

Figure 12.26 16-Bit PPG Mode Timming chart for Timer 2

0

154 April 20, 2012 Ver. 2.5


EC2

EINT12

MC96F7816/C7816


T2ADRH/T2ADRL

T2ECE

T2CK[2:0]

3

Buffer Register A

Reload

A Match

T2CC

T2EN

INT_ACK

Clear

Edge

Detector fx s c a

P r e l e r fx/1 fx/2 fx/4 fx/8 fx/64 fx/512 fx/2048

M

U

X

T2EN

Clear

A Match

Comparator

16-bit Counter

T2CNTH/T2CNTL

R

Clear

B Match

T2IFR

Pulse

Generator

EIPOL0[5:4]

2

T2CNTR

Comparator

Buffer Register B

Reload

2

T2MS[1:0] T2POL

A Match

T2CC

T2EN


T2BDRH/T2BDRL

INT_ACK

Clear

2

T2MS[1:0]

FLAG12

(EIFLAG0.2)

Figure 12.27 16-Bit Timer/Counter Mode for Timer 2 and Block Diagram

To interrupt block

A Match

T2CC

T2EN

T2O/

PWM2O

To interrupt block



Name

T2ADRH

T2ADRL

T2BDRH

T2BDRL

T2CRH

T2CRL

Address

C5H

C4H

C7H

C6H

C3H

C2H

Dir

R/W

R/W

R/W

R/W

R/W

R/W

Default

FFH

FFH

FFH

FFH

00H

00H

Description








The timer/counter 2 register consists of timer 2 A data high register (T2ADRH), timer 2 A data low register

(T2ADRL), timer 2 B data high register (T2BDRH), timer 2 B data low register (T2BDRL), timer 2 control High register (T2CRH) and timer 2 control low register (T2CRL).

April 20, 2012 Ver. 2.5 155

MC96F7816/C7816


T2ADRH (Timer 2 A data High Register) : C5H

7 6 5 4 3 2 1 0

T2ADRH7 T2ADRH6 T2ADRH5 T2ADRH4 T2ADRH3 T2ADRH2 T2ADRH1 T2ADRH0


Initial value : FFH

T2ADRH[7:0] T2 A Data High Byte

T2ADRL (Timer 2 A Data Low Register) : C4H

7 6 5 4 3 2 1 0

T2ADRL7 T2ADRL6 T2ADRL5 T2ADRL4 T2ADRL3 T2ADRL2 T2ADRL1 T2ADRL0


Initial value : FFH

T2ADRL[7:0] T2 A Data Low Byte

Note) Do not write “0000H” in the T2ADRH/T2ADRL register when

PPG mode.

T2BDRH (Timer 2 B Data High Register) : C7H

7 6 5 4 3 2 1 0

T2BDRH7 T2BDRH6 T2BDRH5 T2BDRH4 T2BDRH3 T2BDRH2 T2BDRH1 T2BDRH0


Initial value : FFH

T2BDRH[7:0] T2 B Data High Byte

T2BDRL (Timer 2 B Data Low Register) : C6H

7 6 5 4 3 2 1 0

T2BDRL7 T2BDRL6 T2BDRL5 T2BDRL4 T2BDRL3 T2BDRL2 T2BDRL1 T2BDRL0


Initial value : FFH

T2BDRL[7:0] T2 B Data Low

156 April 20, 2012 Ver. 2.5

MC96F7816/C7816

T2CRH (Timer 2 Control High Register) : C3H

7

T2EN

R/W

6

–

–

T2EN

T2MS[1:0]

T2CC

5

T2MS1

R/W

4

T2MS0

R/W

3

–

–

2

–

–

1

–

–

0

T2CC

R/W

Initial value : 00H

Control Timer 2

0 Timer 2 disable

1 Timer 2 enable (Counter clear and start)



0 0 Timer/counter mode (T2O: toggle at A match)

0

1

1

0

Capture mode (The A match interrupt can occur)

PPG one-shot mode (PWM2O)

1 1 PPG repeat mode (PWM2O)

Clear Timer 2 Counter

0

1

No effect

Clear the Timer 2 counter (When write, automatically cleared “0” after being cleared counter)

April 20, 2012 Ver. 2.5 157

MC96F7816/C7816

T2CRL (Timer 2 Control Low Register) : C2H

7 6 5

T2CK2

R/W

T2CK1

R/W

T2IFR

T2POL

T2ECE

T2CK0

T2CNTR

R/W

T2CK[2:0]

4

T2IFR

R/W

3

–

–

2

T2POL

R/W

1

T2ECE

R/W

0

T2CNTR

R/W

Initial value : 00H

Select Timer 2 clock source. fx is main system clock frequency


0 0 0 fx/2048

0 0 1 fx/512

0

0

1

1

1

1

0

0

0

1

0

1 fx/64 fx/8 fx/4 fx/2

1 1 0 fx/1

1 1 1 External clock (EC2)

When T2 Match Interrupt occurs, this bit becomes „1‟. For clearing bit, write




T2O/PWM2O Polarity Selection

0

1

Start High (T2O/PWM2O is low level at disable)

Start Low (T2O/PWM2O is high level at disable)

Timer 2 External Clock Edge Selection

0 External clock falling edge

1 External clock rising edge

Timer 2 Counter Read Control

0

1

No effect

Load the counter value to the B data register (When write, automatically cleared

“0” after being loaded)

158 April 20, 2012 Ver. 2.5

12.8 Timer 3

12.8.1.1 Overview

MC96F7816/C7816

The 16-bit timer 3 consists of multiplexer, timer 3 A data high/low register, timer 3 B data high/low register and timer 3 control high/low register (T3ADRH, T3ADRL, T3BDRH, T3BDRL, T3CRH, T3CRL).

It has four operating modes:



- 16-bit PPG output mode (one-shot mode)

- 16-bit PPG output mode (repeat mode)

The timer/counter 3 can be divided clock of the system clock selectd from prescaler output and T1M (timer 1 match signal). The clock source is selected by clock selection logic which is controlled by the clock selection bits

(T3CK[2:0]).


X

/1, 2, 4, 8, 64, 512, 2048 and T1M

In the capture mode, by EINT13, the data is captured into input capture data register (T3BDRH/T3BDRL). In timer/counter mode, whenever counter value is equal to T3ADRH/L, T3O port toggles. Also the timer 3 outputs

PWM wave form to PWM3O port in the PPG mode.


T3EN

1

1

1

1

PFSR31 T3MS[1:0] T3CK[2:0]

1

0

00

01

XXX

XXX

1

1

10

11

XXX

XXX

Timer 3


16 Bit Capture Mode

16 Bit PPG Mode

(one-shot mode)

16 Bit PPG Mode

(repeat mode)

April 20, 2012 Ver. 2.5 159

MC96F7816/C7816



The 16-bit timer have counter and data register. The counter register is increased by internal or timer 1 match clock input. Timer 3 can use the input clock with one of 1, 2, 4, 8, 64, 512, 2048 and T1M prescaler division rates

(T3CK[2:0]). When the values of T3CNTH/T3CNTL and T3ADRH/T3ADRL are identical in timer 3, a match signal is generated and the interrupt of Timer 3 occurs. The T3CNTH/T3CNTL values are automatically cleared by match signal. It can be also cleared by software (T3CC).

T3CRH

T3CRL

T3EN

1

–

–

T3MS1

0

T3MS0

0

T3CK2

X

T3CK1 T3CK0 T3IFR

X X X

T1M fx

–

–

–

–

–

–

T3POL

X

–

–

–

–

T3CC

X

ADDRESS:CBH


T3CNTR

X

ADDRESS:CAH



T3ADRH/T3ADRL s c a

P r e l e r fx/1 fx/2 fx/4 fx/8 fx/64 fx/512 fx/2048

T3CK[2:0]

3

Reload

Buffer Register A

A Match

T3CC

T3EN

INT_ACK

Clear

T3EN

A Match

T3IFR

M

U

X

Comparator

Clear

16-bit Counter

T3CNTH/T3CNTL

R

Pulse

Generator

2

T3MS[1:0] T3POL


To interrupt block

A Match

T3CC

T3EN

T3O

160 April 20, 2012 Ver. 2.5

T3CNTH/L

Value

Timer 3

(T3IFR)

Interrupt

MC96F7816/C7816

Match with T3ADRH/L n-2 n-1 n

0

1

2

Up-count

5

4

6

3


= P

CP

x (n+1)


P

CP

Occur

Interrupt

Occur

Interrupt


TIME

Occur

Interrupt

April 20, 2012 Ver. 2.5 161

MC96F7816/C7816


The timer 3 capture mode is set by T3MS[1:0] as „01‟. The clock source can use the internal clock. Basically, it has the same function as the 16-bit timer/counter mode and the interrupt occurs when T3CNTH/T3CNTL is equal to T3ADRH/T3ADRL. T3CNTH/T3CNTL values are automatically cleared by match signal and it can be also cleared by software (T3CC).


The capture result is loaded into T3BDRH/T3BDRL. In the timer 3 capture mode, timer 3 output(T3O) waveform is not available.

According to EIPOL0 registers setting, the external interrupt EINT13 function is chosen. Of cource, the EINT13 pin must be set to an input port.

T3CRH

T3EN

1

–

–

T3MS1 T3MS0

0 1

–

–

–

–

–

–

T3CC

X

ADDRESS:CBH


T3CRL

T3CK2

X

T3CK1 T3CK0 T3IFR

X X

X

–

–

T3POL

X

–

–

T3CNTR

X

ADDRESS:CAH



T3ADRH/T3ADRL

Reload

T3CK[2:0]

3

Buffer Register A

A Match

T3CC

T3EN

INT_ACK

Clear

EINT13 fx

T1M e r c a l e s


M

U

X

T3EN

Clear

A Match

Comparator

Clear

16-bit Counter

T3CNTH/T3CNTL

R

T3IFR

To interrupt block

A Match

T3CC

T3EN

EIPOL0[7:6]

2

T3CNTR

2

T3MS[1:0]


T3BDRH/T3BDRL

INT_ACK

Clear

FLAG13

(EIFLAG0.3)


To interrupt block

162 April 20, 2012 Ver. 2.5

T3CNTH/L

Value

MC96F7816/C7816

T3BDRH/L Load n-2 n-1 n

0

1

2

Up-count

5

4

3

6


P

CP

TIME

Ext. EINT13 PIN

Interrupt

Request

(FLAG13)



FFFF

H

FFFF

H

XX

H

T3CNTH/L

00

H

Interrupt

Request

(T3IFR)

Ext. EINT13 PIN

Interrupt

Request

(FLAG13)

00

H

00

H

Interrupt Interval Period = FFFF

H

+01

H

+FFFF

H

+01

H

+YY

H

+01

H


YY

H

00

H

00

H

April 20, 2012 Ver. 2.5 163

MC96F7816/C7816

12.8.4 16-Bit PPG Mode

The timer 3 has a PPG (Programmable Pulse Generation) function. In PPG mode, the T3O/PWM3O pin outputs up to 16-bit resolution PWM output. This pin should be configured as a PWM output by set PFSR31 to

„1‟ . The period of the PWM output is determined by the T3ADRH/T3ADRL. And the duty of the PWM output is determined by the T3BDRH/T3BDRL.

T3CRH T3EN

1

–

–

T3MS1 T3MS0

1 1

–

–

–

–

–

–

T3CC

X

ADDRESS:CBH


T3CRL T3CK2

X

T3CK1 T3CK0 T3IFR

X X X

–

–

T3POL

X

–

–

T3CNTR

X

ADDRESS:CAH


T1M fx a l s c e r

P r e fx/1 fx/2 fx/4 fx/8 fx/64 fx/512 fx/2048

T3CK[2:0]

3

M

U

X

T3EN


T3ADRH/T3ADRL

Reload

Buffer Register A

A Match

T3CC

T3EN

INT_ACK

Clear

A Match

T3IFR

To interrupt block

Comparator

16-bit Counter

T3CNTH/T3CNTL

Comparator

Buffer Register B

R

Reload

Clear

B Match

Pulse

Generator

2

T3MS[1:0] T3POL

A Match

T3CC

T3EN

A Match

T3CC

T3EN

T3O/

PWM3O


T3BDRH/T3BDRL

Note) The T3EN is automatically cleared to logic “0” after one pulse is generated at a PPG one-shot mode.

Figure 12.33 16-Bit PPG Mode for Timer 3

164 April 20, 2012 Ver. 2.5

Repeat Mode(T3MS = 11b) and "Start High"(T3POL = 0b).

Set T3EN

Clear and Start

Timer 3 clock

Counter X

T3ADRH/L M

0

T3 Interrupt


PWM3O


PWM3O

3. T3BDRH/L = "0000H"

PWM3O

Low Level

1 2 3 4 5 6

B Match

7 8 M-1 0 1 2 3 4

A Match

A Match

A Match

MC96F7816/C7816

One-shot Mode(T3MS = 10b) and "Start High"(T3POL = 0b).

Clear and Start

Set T3EN

Timer 3 clock

Counter X

T3ADRH/L M

0 1 2 3 4 5 6 7 8 M-1

T3 Interrupt


PWM3O B Match A Match


PWM3O

3. T3BDRH/L = "0000H"

PWM3O

Low Level

A Match

A Match

Figure 12.34 16-Bit PPG Mode Timming chart for Timer 3

0

April 20, 2012 Ver. 2.5 165

MC96F7816/C7816


EINT13


T3ADRH/T3ADRL fx

T1M

EIPOL0[7:6]

2 c a l e r e s


T3CNTR

T3CK[2:0]

3

M

U

X

2

T3MS[1:0]

T3EN

Clear

Reload

Buffer Register A

Comparator

16-bit Counter

T3CNTH/T3CNTL

Comparator

Buffer Register B


T3BDRH/T3BDRL

R

Reload

A Match

Clear

B Match

A Match

T3CC

T3EN

INT_ACK

Clear

T3IFR

Pulse

Generator

To interrupt block

A Match

T3CC

T3EN

T3O/

PWM3O

2

T3MS[1:0] T3POL

A Match

T3CC

T3EN

INT_ACK

Clear

FLAG13

(EIFLAG0.3)

To interrupt block




Name

T3ADRH

T3ADRL

T3BDRH

T3BDRL

T3CRH

T3CRL

Address

CDH

CCH

CFH

CEH

CBH

CAH

Dir

R/W

R/W

R/W

R/W

R/W

R/W

Default

FFH

FFH

FFH

FFH

00H

00H

Description








The timer/counter 3 register consists of timer 3 A data high register (T3ADRH), timer 3 A data low register

(T3ADRL), timer 3 B data high register (T3BDRH), timer 3 B data low register (T3BDRL), timer 3 control High register (T3CRH) and timer 3 control low register (T3CRL).

166 April 20, 2012 Ver. 2.5


MC96F7816/C7816

T3ADRH (Timer 3 A data High Register) : CDH

7 6 5 4 3 2 1 0

T3ADRH7 T3ADRH6 T3ADRH5 T3ADRH4 T3ADRH3 T3ADRH2 T3ADRH1 T3ADRH0


Initial value : FFH

T3ADRH[7:0] T3 A Data High Byte

T3ADRL (Timer 3 A Data Low Register) : CCH

7 6 5 4 3 2 1 0

T3ADRL7 T3ADRL6 T3ADRL5 T3ADRL4 T3ADRL3 T3ADRL2 T3ADRL1 T3ADRL0


Initial value : FFH

T3ADRL[7:0] T3 A Data Low Byte

Note) Do not write “0000H” in the T3ADRH/T3ADRL register when

PPG mode.

T3BDRH (Timer 3 B Data High Register) : CFH

7 6 5 4 3 2 1 0

T3BDRH7 T3BDRH6 T3BDRH5 T3BDRH4 T3BDRH3 T3BDRH2 T3BDRH1 T3BDRH0


Initial value : FFH

T3BDRH[7:0] T3 B Data High Byte

T3BDRL (Timer 3 B Data Low Register) : CEH

7 6 5 4 3 2 1 0

T3BDRL7 T3BDRL6 T3BDRL5 T3BDRL4 T3BDRL3 T3BDRL2 T3BDRL1 T3BDRL0


Initial value : FFH

T3BDRL[7:0] T3 B Data Low

April 20, 2012 Ver. 2.5 167

MC96F7816/C7816

T3CRH (Timer 3 Control High Register) : CBH

7

T3EN

R/W

6

–

–

T3EN

T3MS[1:0]

T3CC

5

T3MS1

R/W

4

T3MS0

R/W

3

–

–

2

–

–

1

–

–

0

T3CC

R/W

Initial value : 00H

Control Timer 3

0 Timer 3 disable

1 Timer 3 enable (Counter clear and start)



0 0 Timer/counter mode (T3O: toggle at A match)

0

1

1

0

Capture mode (The A match interrupt can occur)

PPG one-shot mode (PWM3O)

1 1 PPG repeat mode (PWM3O)

Clear Timer 3 Counter

0

1

No effect

Clear the Timer 3 counter (When write, automatically cleared “0” after being cleared counter)

168 April 20, 2012 Ver. 2.5

MC96F7816/C7816

T3CRL (Timer 3 Control Low Register) : CAH

7 6 5

T3CK2

R/W

T3CK1

R/W

T3IFR

T3POL

T3CK0

T3CNTR

R/W

T3CK[2:0]

4

T3IFR

R/W

3

–

–

2

T3POL

R/W

1

–

–

0

T3CNTR

R/W

Initial value : 00H

Select Timer 3 clock source. fx is main system clock frequency


0 0 0 fx/2048

0 0 1 fx/512

0

0

1

1

1

1

0

0

0

1

0

1 fx/64 fx/8 fx/4 fx/2

1 1 0 fx/1

1 1 1 T1M

When T3 Match Interrupt occurs, this bit becomes „1‟. For clearing bit, write




T3O/PWM3O Polarity Selection

0

1

Start High (T3O/PWM3O is low level at disable)

Start Low (T3O/PWM3O is high level at disable)

Timer 3 Counter Read Control

0 No effect

1 Load the counter value to the B data register (When write, automatically cleared “0” after being loaded)

April 20, 2012 Ver. 2.5 169

MC96F7816/C7816

12.9 Buzzer Driver

12.9.1 Overview

The Buzzer consists of 8 bit counter, buzzer data register (BUZDR), and buzzer control register (BUZCR). The

Square Wave (61.035Hz~125.0 kHz @8MHz) is outputted through P03/BUZO pin. The buzzer data register

(BUZDR) controls the bsuzzer frequency (look at the following expression). In buzzer control register (BUZCR),

BUCK[1:0] selects source clock divided by prescaler. f

BUZ

(Hz)



Oscillator Frequency

2



Prescaler Ratio



(BUZDR



1)

Table 12-13 Buzzer Frequency at 8 MHz

BUZDR[7:0]

0000_0000

0000_0001

…

1111_1101

1111_1110

1111_1111

BUZCR[2:1]=00

125kHz

62.5kHz

…

492.126Hz

490.196Hz

488.281Hz

Buzzer Frequency (kHz)

BUZCR[2:1]=01 BUZCR[2:1]=10

62.5kHz 31.25kHz

31.25kHz

…

246.063Hz

245.098Hz

244.141Hz

15.625kHz

…

123.031Hz

122.549Hz

122.07Hz

BUZCR[2:1]=11

15.625kHz

7.812kHz

…

61.515Hz

61.274Hz

61.035Hz

12.9.2 Block Diagram fx


MUX

BUZEN

2

BUCK[1:0]

8-bit Up-Counter

Counter

Clear

BUZDR

Comparator

F/F BUZO

Figure 12.36 Buzzer Driver Block Diagram

170 April 20, 2012 Ver. 2.5


Table 12-14 Buzzer Driver Register Map

Name

BUZDR

BUZCR

Address

8FH

97H

Dir

R/W

R/W

Default

FFH

00H

12.9.4 Buzzer Driver Register Description

Description

Buzzer Data Register

Buzzer Control Register

MC96F7816/C7816

Buzzer driver consists of buzzer data register (BUZDR), buzzer control register (BUZCR).

12.9.5 Register Description for Buzzer Driver

BUZDR (Buzzer Data Register) : 8FH

7 6 5

BUZDR7 BUZDR6 BUZDR5

R/W R/W R/W

4

BUZDR4

R/W

3

BUZDR3

R/W

2

BUZDR2

R/W

BUZDR[7:0] This bits control the Buzzer frequency

Its resolution is 00H ~ FFH

BUZCR (Buzzer Control Register) : 97H

7 6 5

-

-

-

-

-

-

4

-

-

3

-

-

2

BUCK1

R/W

BUCK[1:0]

BUZEN

Buzzer Driver Source Clock Selection

BUCK1 BUCK0 Description

0

0

0

1 fx/32 fx/64

1

1

0

1 fx/128 fx/256

Buzzer Driver Operation Control

0 Buzzer Driver disable

1 Buzzer Driver enable

Note) fx is the System clock oscillation frequency.

1

BUZDR1

R/W

0

BUZDR0

R/W

Initial value : FFH

1

BUCK0

R/W

0

BUZEN

R/W

Initial value : 00H

April 20, 2012 Ver. 2.5 171

MC96F7816/C7816

12.10 SIO

12.10.1 Overview

The serial input/output is used to transmit/receive 8-bit data serially. The serial input/output(SIO) module is a useful serial interface to communicate with other peripheral of microcontroller devices. This SIO is 8-bit clock synchronous type and consists of SIO pre-scaler register, SIO data register, SIO control register, and control circuit as illustrated in Figure 12.37. The SO pin is designed to input and output. So SIO can operate with two pins minimally. Pin P05/SO, P04/SCK and P06/SI pins are controlled by the SIO control register (SIOCR) and port function selection control registers (PFSR02 and PFSR01). The SI pin must be set to input port.

The contents of the SIO data register can be written into or read out by software. The data in the SIO data register can be shifted synchronously with the transfer clock signal. SIO data register (SIODR) is an 8 bit shift register. MSB-first and LSB-first transfers are possible.


CSEL

SCK fx

Pre scaler fx/4

SIOPS

M

U

X

CSEL

CLK

3-Bit Counter

Clear

CCLR

SEDGE

CLK 8-Bit SIO shift buffer

(SIODR)

SIOP

INT_ACK

Clear

SIOIFR

SIOM[1:0]

To interrupt block

DAT

1

0

SO

SI

IOSW

SIOM[1:0]

Figure 12.37 SIO Block Diagram

Note) The system clock should be greater than the SIO input clock. So, take care of using the external clock.

172 April 20, 2012 Ver. 2.5

12.10.3 SIO Pre-Scaler Register (SIOPS)

MC96F7816/C7816

SIOPS contains the SIO pre-scaler value. The SIO clock rate (baud rate) is calculated by the following fomula.

Baud rate = Input clock (fx/4)/(Pre-scaler value + 1) or SCK input clock, where the input clock is fx/4

SIOPS

MSB LSB

SIOPS7 SIOPS6 SIOPS5 SIOPS4 SIOPS3 SIOPS2 SIOPS1 SIOPS0

R/W

R/W R/W R/W R/W R/W R/W R/W

ADDRESS : B7H


Baud rate = (fx/4)/(SIOPS + 1)

Figure 12.38 SIO Pre-Scaler Register (SIOPS)

12.10.4 The usage of SIO

1. Select transmitter/receiver mode.

2. In transmitter mode, write data to be sent to SIODR.

3. Set CCLR to “1” to clear SIO counter and start shifting.

4. If Tx or Rx is completed, the SiO interrupt is generated and SIOIFR is set to

“1”.

5. In receiver mode, the received data can be acquired by reading SIODR.

April 20, 2012 Ver. 2.5 173

MC96F7816/C7816

12.10.5 SIO Timing Diagram

SCK

[SEDGE=0]

SO[P05]

SI[P06]

(IOSW = 0)

IOSWIN[P05]

(IOSW = 1)

SIOIFR

(SIO Int. Req)

SIO status

(CCLR = 1)

SCK

[SEDGE=1]

SO[P05]

SI[P06]

(IOSW = 0)

IOSWIN[P05]

(IOSW = 1)

SIOIFR

(SIO Int. Req)

SIO status

(CCLR = 1)

174

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

Figure 12.39 SIO Timing Diagram at SEDGE=0

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

Figure 12.40 SIO Timing Diagram at SEDGE=1

Transmit

Complete

Transmit

Complete

April 20, 2012 Ver. 2.5


Table 12-15 SIO Register Map

Name

SIOPS

SIODR

SIOCR

Address

B7H

B6H

B5H

Dir

R/W

R/W

R/W

Default

00H

00H

00H

12.10.7 SIO Register Description

Description

SIO Pre-scaler Register

SPI Data Register

SIO Control Register

MC96F7816/C7816

The SIO register consists of SIO pre-scaler register (SIOPS), SIO sata Register (SIODR), and SIO control register (SIOCR). The SIOIFR bit is in the timer interrupt flag register (TIFR).

12.10.8 Register Description for SIO

SIOPS (SIO Pre-scaler Register) : B7H

7 6 5

SIOPS7

R/W

SIOPS6

R/W

SIOPS5

R/W

4

SIOPS4

R/W

3

SIOPS3

R/W

2

SIOPS2

R/W

SIOPS [7:0]

SIODR (SIO Data Register) : B6H

7 6 5

SIODR7

R/W

SIODR6

R/W

SIODR5

R/W

SIO Pre-scaler

Baud Rate = (fx/4)/(SIOPS+1)

4

SIODR4

R/W

3

SIODR3

R/W

2

SIODR2

R/W

SIODR [7:0] SIO Data

1

SIOPS1

R/W

0

SIOPS0

R/W

Initial value : 00H

1

SIODR1

R/W

0

SIODR0

R/W

Initial value : 00H

April 20, 2012 Ver. 2.5 175

MC96F7816/C7816

SIOCR (SIO Control Register) : B5H

7 6 5

CSEL

R/W

DAT

R/W

SIOP

R/W

4

IOSW

R/W

3

SIOM1

R/W

2

SIOM0

R/W

1

CCLR

R/W

0

SEDGE

R/W

Initial value : 00H

CSEL

DAT

SIOP

IOSW

SIOM[1:0]

CCLR

SEDGE

SIO Shift Clock Selection

0

1

Internal clock (P.S clock)

External clock (SCK)

Data Direction Control

0 MSB first mode

1 LSB first mode

SIO Shift Operation Enable

0

1

Disable shifter and clock counter

Enable shifter and clock counter

Serial Input Pin Selection Bit

0 SI pin selection

1 SO pin selection

Note) If SO pin is selected for a serial data input, SO pin should be set to an input and port. So, the SIOM, PFSR02, and P05IO bits should be set to

„01b‟, „0b‟ and „0b‟ respectively. Refer to the P0IO and P03FSR register for setting.

SIO Mode Selection

SIOM1 SIOM0 Description

0

0

0

1

Transmit mode

Receive mode

1 x Transmit/Receive mode

SIO Counter Clear and Shift Start

0

1

No action

Clear 3-bit counter and start shifting

SIO Clock Edge Selection

0 Tx at falling edges, Rx at rising edges

1 Tx at rising edge, Rx at falling edges

Note) Refer to the external interrupt flag 0 register (EIFLAG0) for the serial I/O interrupt flag.

176 April 20, 2012 Ver. 2.5

12.11 12-Bit A/D Converter


MC96F7816/C7816

The analog-to-digital converter (A/D) allows conversion of an analog input signal to corresponding 12-bit digital value. The A/D module has eight analog inputs.

The output of the multiplexer is the input into the converter which generates the result through successive approximation. The A/D module has four registers which are the A/D converter control high register (ADCCRH), A/D converter control low register (ADCCRL), A/D converter data high register (ADCDRH), and A/D converter data low register (ADCDRL). The channels to be converted are selected by setting ADSEL[2:0]. To execute A/D conversion, ADST bit should be set to „1‟. The register ADCDRH and

ADCDRL contains the results of the A/D conversion. When the conversion is completed, the result is loaded into the ADCDRH and ADCDR L, the A/D conversion status bit AFLAG is set to „1‟, and the A/D interrupt is set. During

A/D conversion, AFLAG bit is read as „0‟.

12.11.2 Conversion Timing

The A/D converstion process requires 4 steps (4 clock edges) to convert each bit and 10 clocks to set up A/D conversion. Therefore, total of 58 clocks are required to complete a 12-bit conversion: When fxx/4 is selected for conversion clock with a 8MHz fxx clock frequency, one clock cycle is 0.5

μs. Each bit conversion requires 4 clocks, the conversion rate is calculated as follows:

4 clocks/bit × 12 bits + set-up time = 58 clocks,

58 clock × 0.5 μs = 29.0 μs at 2.0 MHz (8 MHz/4)

Note : The A/D converter needs at least 20 μs for conversion time. So you must set the conversion time more than 20 μs .


Input Pins

AN0

AN1

AN2

AN6

AN7

ADSEL[2:0]

(Select one input pin of the assigned pins)

M

U

X

Reference

Voltage

+

-

ADCLK

Clock

Selector

ADST

Clear

AFLAG

Comparator

Control

Logic

ADCIFR

Clear

INT_ACK

To interrupt block

ADCDRH (R), ADCDRL (R)

AVREF/VDD AVSS

Figure 12.41 12-bit ADC Block Diagram

April 20, 2012 Ver. 2.5 177

MC96F7816/C7816

Analog

Input

0~1000pF

AN0~

AN7

Figure 12.42 A/D Analog Input Pin with

Capacitor

12.11.4 ADC Operation

Analog

Power

Input

22uF

AVREF

Figure 12.43 A/D Power (AVDD) Pin with

Capacitor

Align bit set “0”

ADCO11 ADCO10 ADCO9 ADCO8 ADCO7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0

ADCDRH7 ADCDRH6 ADCDRH5 ADCDRH4 ADCDRH3 ADCDRH2 ADCDRH1 ADCDRH0 ADCDRL7 ADCDRL6 ADCDRL5 ADCDRL4

ADCDRH[7:0]

ADCDRL[7:4]

ADCDRL[3:0] bits are “0”

Align bit set “1”

ADCO11 ADCO10 ADCO9 ADCO8 ADCO7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0

ADCDRH3 ADCDRH2 ADCDRH1 ADCDRH0 ADCDRL7 ADCDRL6 ADCDRL5 ADCDRL4 ADCDRL3 ADCDRL2 ADCDRL1 ADCDRL0

ADCDRH[3:0]

ADCDRH[7:4] bits are “0”

ADCDRL[7:0]

Figure 12.44 ADC Operation for Align Bit

178 April 20, 2012 Ver. 2.5

MC96F7816/C7816

SET ADCCRH

SET ADCCRL

Select ADC Clock and Data Align Bit.

ADC enable & Select AN Input Channel.

Converting START

N

AFLAG = 1?

Y

READ ADCDRH/L

Start ADC Conversion.

If Conversion is completed, AFLAG is set “1” and ADC interrupt is occurred.

After Conversion is completed, read ADCDRH and ADCDRL.

ADC END

Figure 12.45 A/D Converter Operation Flow


Table 12-16 ADC Register Map

Name

ADCDRH

ADCDRL

ADCCRH

ADCCRL

Address

9FH

9EH

9DH

9CH

Dir

R

R

R/W

R/W

Default xxH xxH

00H

00H

12.11.6 ADC Register Description

Description

A/D Converter Data High Register

A/D Converter Data Low Register

A/D Converter Control High Register

A/D Converter Control Low Register

The ADC register consists of A/D converter data high register (ADCDRH), A/D converter data low register

(ADCDRL), A/D converter control high register (ADCCRH), and A/D converter control low register (ADCCRL).

April 20, 2012 Ver. 2.5 179

MC96F7816/C7816

12.11.7 Register Description for ADC

ADCDRH (A/D Converter Data High Register) : 9FH

7

ADDM11

R

6

ADDM10

R

5

ADDM9

R

4

ADDM8

R

3

ADDM7

ADDL11

R

2

ADDM6

ADDL10

R

1

ADDM5

ADDL9

R

0

ADDM4

ADDL8

R

Initial value : xxH

ADDM3

ADDL7

R R

ADDM[11:4]

ADDL[11:8]

ADDM2

ADDL6

ADDM1

ADDL5

R

MSB align, A/D Converter High Data (8-bit)

LSB align, A/D Converter High Data (4-bit)

ADCDRL (A/D Converter Data Low Register) : 9EH

7 6 5 4

ADDM0

ADDL4

R

3

ADDL3

R-

2

ADDL2

R

1

ADDL1

R

0

ADDL0

R

Initial value : xxH

ADDM[3:0]

ADDL[7:0]

MSB align, A/D Converter Low Data (4-bit)

LSB align, A/D Converter Low Data (8-bit)

ADCCRH (A/D Converter High Register) : 9DH

7 6 5 4

ADCIFR

R/W

-

-

ADCIFR

ALIGN

-

-

CKSEL[1:0]

-

-

3

-

-

2

ALIGN

R/W

1

CKSEL1

R/W

0

CKSEL0

R/W

Initial value : 00H

When ADC interrupt occurs, this bit becomes „1‟. For clearing bit, write „0‟ to this bit or auto clear by INT_ACK signal.

0

1

ADC Interrupt no generation

ADC Interrupt generation

A/D Converter data align selection.

0 MSB align (ADCDRH[7:0], ADCDRL[7:4])

1 LSB align (ADCDRH[3:0], ADCDRL[7:0])

A/D Converter Clock selection

CKSEL1 CKSEL0 Description

0 0 fx/1

0

1

1

1

0

1 fx/2 fx/4 fx/8

180 April 20, 2012 Ver. 2.5

MC96F7816/C7816

ADCCRL (A/D Converter Counter Low Register) : 9CH

7 6 5 4

STBY

R/W

ADST

R/W

STBY

ADST

REFSEL

AFLAG

REFSEL

R/W

ADSEL[2:0]

AFLAG

R

3

-

-

2

ADSEL2

R/W

1

ADSEL1

R/W

0

ADSEL0

R/W

Initial value : 00H

1

1

1

Control Operation of A/D

(The ADC module is automatically disabled at stop mode)

0

1

ADC module disable

ADC module enable

Control A/D Conversion stop/start.

0 No effect

1 ADC Conversion Start and auto clear

A/D Converter Reference Selection

0 Internal Reference (VDD)

1 External Reference (AVREF)

A/D Converter Operation State (This bit is cleared to

„0‟ when the STBY bit is set to „0‟ or when the CPU is at STOP mode)

0

1

During A/D Conversion

A/D Conversion finished

0

0

1

A/D Converter input selection

ADSEL2 ADSEL1 ADSEL0 Description

0

0

0

0

0

1

AN0

AN1

1

1

0

0

1

0

AN2

AN3

AN4

0

1

1

1

0

1

AN5

AN6

AN7

April 20, 2012 Ver. 2.5 181

MC96F7816/C7816

12.12 UART


The universal asynchronous serial receiver and transmitter (UART) is a highly flexible serial communication device. The main features are listed below.

- Full Duplex Operation (Independent Serial Receive and Transmit Registers)

- Baud Rate Generator

- Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits

- Odd or Even Parity Generation and Parity Check Supported by Hardware

- Data OverRun Detection

- Framing Error Detection

- Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete

UART has baud rate generator, transmitter and receiver. The baud rate generator for asynchronous operation.

The Transmitter consists of a single write buffer, a serial shift register, parity generator and control logic for handling different serial frame formats.

The write buffer allows continuous transfer of data without any delay between frames. The receiver is the most complex part of the UART module due to its clock and data recovery units. The recovery unit is used for asynchronous data reception. In addition to the recovery unit, the receiver includes a parity checker, a shift register, a two-level receive FIFO (UARTDR) and control logic. The receiver supports the same frame formats as the transmitter and can detect frame error, data overrun and parity errors.

182 April 20, 2012 Ver. 2.5


MC96F7816/C7816

To interrupt block

UARTBD

WAKEIE

WAKE

RXD

At Stop mode

Low level detector

M

U

X

RXCIE

RXC

Rx

Control

TXD

SCLK Baud Rate Generator

Clock

Recovery

Data

Recovery

Receive Shift Register

(RXSR)

LOOPS

INT_ACK

Clear

Tx

Control

TXC

DOR/PE/FE

Checker

UARTDR[0]

(Rx)

UARTDR[1]

(Rx) Stop bit

Generator

UPM0

M

U

X

UPM1

Parity

Generator

Empty signal

UDRE

Transmit Shift Register

(TXSR)

UARTDR(Tx)

TXCIE UDRIE

N

E

L

I

B

U

S

I

N

T

E

R

N

A

L

To interrupt block

Figure 12.46 UART Block Diagram

April 20, 2012 Ver. 2.5 183

MC96F7816/C7816

12.12.3 Clock Generation

UARTBD

U2X f

SCLK

(UARTBD+1)

SCLK

Baud Rate

Generator

/8 /2

M

U

X txclk rxclk

Figure 12.47 Clock Generation Block Diagram

The clock generation logic generates the base clock for the transmitter and receiver.

Following table shows equations for calculating the baud rate (in bps).

Table 12-17 Equations for Calculating Baud Rate Register Setting

Operating Mode

Normal Mode(U2X=0)

Double Speed Mode(U2X=1)

Equation for Calculating Baud Rate

184 April 20, 2012 Ver. 2.5

12.12.4 Data format

MC96F7816/C7816

A serial frame is defined to be one character of data bits with synchronization bits (start and stop bits), and optionally a parity bit for error detection.

The UART supports all 30 combinations of the following as valid frame formats.

- 1 start bit

- 5, 6, 7, 8 or 9 data bits

- no, even or odd parity bit

- 1 or 2 stop bits

A frame starts with the start bit followed by the least significant data bit (LSB). Then the next data bits, up to nine, are succeeding, ending with the most significant bit (MSB). If parity function is enabled, the parity bit is inserted between the last data bit and the stop bit. A high-to-low transition on data pin is considered as start bit.

When a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle state. The idle means high state of data pin. The following figure shows the possible combinations of the frame formats. Bits inside brackets are optional.

Idle St D0 D1 D2

1 data frame

D3 D4

Character bits

[D5] [D6] [D7] [D8] [P] Sp1 Sp2 Idle / St

Figure 12.48 Frame Format

1 data frame consists of the following bits

• Idle No communication on communication line (TxD/RxD)

• St Start bit (Low)

• Dn Data bits (0~8)

• Parity bit ------------ Even parity, Odd parity, No parity

• Stop bit(s) ---------- 1 bit or 2 bits

The frame format used by the UART is set by the USIZE[2:0], UPM[1:0] and USBS bits in UARTCR1 and

UARTCR3 register. The Transmitter and Receiver use the same setting.

12.12.5 Parity bit

The parity bit is calculated by doing an exclusive-OR of all the data bits. If odd parity is used, the result of the exclusive-or is inverted. The parity bit is located between the MSB and first stop bit of a serial frame.

P even

= D n-1

^ … ^ D

3

^ D

2

^ D

1

^ D

0

^ 0

P odd

= D n-1

^ … ^ D

3

^ D

2

^ D

1

^ D

0

^ 1

P even

: Parity bit using even parity

P odd

: Parity bit using odd parity

D n

: Data bit n of the character

April 20, 2012 Ver. 2.5 185

MC96F7816/C7816

12.12.6 UART Transmitter

The UART transmitter is enabled by setting the TXE bit in UARTCR2 register.

When the Transmitter is enabled, the TXD pin should be set to TXD function for the serial output pin of UART by the PFSR33.

The baud-rate, operation mode and frame format must be setup once before doing any transmission.

12.12.6.1 Sending Tx data

A data transmission is initiated by loading the transmit buffer (UARTDR register I/O location) with the data to be transmitted. The data written in transmit buffer is moved to the shift register when the shift register is ready to send a new frame. The shift register is loaded with the new data if it is in idle state or immediately after the last stop bit of the previous frame is transmitted. When the shift register is loaded with new data, it will transfer one complete frame according to the settings of control registers.

If the 9-bit characters are used, the ninth bit must be written to the TX8 bit in UARTCR3 register before it is loaded to the transmit buffer (UARTDR register).

12.12.6.2 Transmitter flag and interrupt

The UART transmitter has 2 flags which indicate its state.

One is UART data register empty flag (UDRE) and the other is transmit complete flag (TXC). Both flags can be interrupt sources.

UDRE flag indicates whether the transmit buffer is ready to receive new data. This bit is set when the transmit buffer is empty and cleared when the transmit buffer contains data to be transmitted but has not yet been moved into the shift register. And also this flag can be cleared by writing „0‟ to this bit position. Writing „1‟ to this bit position is prevented.

When the data register empty interrupt enable (UDRIE) bit in UARTCR2 register is set and the global interrupt is enabled, UART data register empty interrupt is generated while UDRE flag is set.

The transmit complete (TXC) flag bit is set when the entire frame in the transmit shift register has been shifted out and there is no more data in the transmit buffer. The TXC flag is automatically cleared when the transmit complete interrupt service routine is executed, or it can be cleared by writing

„0‟ to TXC bit in UARTST register.

When the transmit complete interrupt enable (TXCIE) bit in UARTCR2 register is set and the global interrupt is enabled, UART transmit complete interrupt is generated while TXC flag is set.

186 April 20, 2012 Ver. 2.5

12.12.6.3 Parity Generator

MC96F7816/C7816

The parity generator calculates the parity bit for the serial frame data to be sent. When parity bit is enabled

(UPM[1]=1), the transmitter control logic inserts the parity bit between the MSB and the first stop bit of the frame to be sent.

12.12.6.4 Disabling Transmitter

Disabling the transmitter by clearing the TXE bit will not become effective until ongoing transmission is completed. When the Transmitter is disabled, the TXD pin can be used as a normal general purpose I/O (GPIO).

12.12.7 UART Receiver

The UART receiver is enabled by setting the RXE bit in the UARTCR2 register. When the receiver is enabled, the RXD pin should be set to the input port for the serial input pin of UART by P34IO bit. The baud-rate, mode of operation and frame format must be set before serial reception.

12.12.7.1 Receiving Rx data

The receiver starts data reception when it detects a valid start bit (LOW) on RXD pin. Each bit after start bit is sampled at pre-defined baud-rate (asynchronous) and shifted into the receive shift register until the first stop bit of a frame is received. Even if there‟s 2 nd

stop bit in the frame, the 2 nd

stop bit is ignored by the receiver.

That is, receiving the first stop bit means that a complete serial frame is present in the receiver shift register and contents of the shift register are to be moved into the receive buffer. The receive buffer is read by reading the UARTDR register.

If 9-bit characters are used (USIZE[2:0] =

“111”), the ninth bit is stored in the RX8 bit position in the UARTCR3 register. The 9 th

bit must be read from the RX8 bit before reading the low 8 bits from the UARTDR register.

Likewise, the error flags FE, DOR, PE must be read before reading the data from UARTDR register. It ‟s because the error flags are stored in the same FIFO position of the receive buffer.

April 20, 2012 Ver. 2.5 187

MC96F7816/C7816

12.12.7.2 Receiver Flag and Interrupt

The UART receiver has one flag that indicates the receiver state.

The receive complete (RXC) flag indicates whether there are unread data in the receive buffer. This flag is set when there are unread data in the receive buffer and cleared when the receive buffer is empty. If the receiver is disabled (RXE=0), the receiver buffer is flushed and the RXC flag is cleared.

When the receive complete interrupt enable (RXCIE) bit in the UARTCR2 register is set and global interrupt is enabled, the UART receiver complete interrupt is generated while RXC flag is set.

The UART receiver has three error flags which are frame error (FE), data overrun (DOR) and parity error (PE).

These error flags can be read from the UARTST register. As received data are stored in the 2-level receive buffer, these error flags are also stored in the same position of receive buffer. So, before reading received data from

UARTDR register, read the UARTST register first which contains error flags.

The frame error (FE) flag indicates the state of the first stop bit. The FE flag is „0‟ when the stop bit was correctly detected as „1‟, and the FE flag is „1‟ when the stop bit was incorrect, i.e. detected as „0‟. This flag can be used for detecting out-of-sync conditions between data frames.

The data overrun (DOR) flag indicates data loss due to a receive buffer full condition. DOR occurs when the receive buffer is full, and another new data is present in the receive shift register which are to be stored into the receive buffer. After the DOR flag is set, all the incoming data are lost. To prevent data loss or clear this flag, read the receive buffer.

The parity error (PE) flag indicates that the frame in the receive buffer had a parity error when received. If parity check function is not enabled (UPM[1]=0), the PE bit is always read „0‟.

12.12.7.3 Parity Checker

If parity bit is enabled (UPM[1]=1), the Parity Checker calculates the parity of the data bits in incoming frame and compares the result with the parity bit from the received serial frame.

12.12.7.4 Disabling Receiver

In contrast to transmitter, disabling the Receiver by clearing RXE bit makes the Receiver inactive immediately.

When the receiver is disabled, the receiver flushes the receive buffer, the remaining data in the buffer is all reset, and the RXD pin can be used as a normal general purpose I/O (GPIO).

188 April 20, 2012 Ver. 2.5

12.12.7.5 Asynchronous Data Reception

MC96F7816/C7816

To receive asynchronous data frame, the UART includes a clock and data recovery unit. The clock recovery logic is used for synchronizing the internally generated baud-rate clock to the incoming asynchronous serial frame on the RXD pin.

The data recovery logic samples and low pass filters the incoming bits, and this removes the noise of RXD pin.

The next figure illustrates the sampling process of the start bit of an incoming frame. The sampling rate is 16 times the baud-rate for normal mode (U2X=0) and 8 times the baud-rate for double speed mode (U2X=1). The horizontal arrows show the synchronization variation due to the asynchronous sampling process. Note that larger time variation is shown when using the double speed mode.

RXD

START

IDLE BIT0

Sample

(U2X = 0)

0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3

Sample

(U2X = 1)

0 1 2 3 4 5 6 7 8 1 2

Figure 12.49 Start Bit Sampling

When the receiver is enabled (RXE=1), the clock recovery logic tries to find a high-to-low transition on the RXD line, the start bit condition. After detecting high to low transition on RXD line, the clock recovery logic uses samples 8, 9, and 10 for normal mode, and samples 4, 5, and 6 for double speed mode to decide if a valid start bit is received. If more than 2 samples have logical low level, it is considered that a valid start bit is detected and the internally generated clock is synchronized to the incoming data frame. And the data recovery can begin. The synchronization process is repeated for each start bit.

As described above, when the receiver clock is synchronized to the start bit, the data recovery can begin. Data recovery process is almost similar to the clock recovery process. The data recovery logic samples 16 times for each incoming bits for normal mode and 8 times for double speed mode. And uses sample 8, 9, and 10 to decide data value for normal mode, and samples 4, 5, and 6 for double speed mode.

If more than 2 samples have low levels, the received bit is considered to a logic

„0‟ and if more than 2 samples have high levels, the received bit is considered to a logic

„1‟. The data recovery process is then repeated until a complete frame is received including the first stop bit. The decided bit value is stored in the receive shift register in order. Note that the Receiver only uses the first stop bit of a frame. Internally, after receiving the first stop bit, the Receiver is in idle state and waiting to find start bit.

RXD

Sample

(U2X = 0)

Sample

(U2X = 1)

BIT n

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1

1 2 3 4 5 6 7 8 1

April 20, 2012 Ver. 2.5

Figure 12.50 Sampling of Data and Parity Bit

189

MC96F7816/C7816

The process for detecting stop bit is like clock and data recovery process. That is, if 2 or more samples of 3 center values have high level, correct stop bit is detected, else a frame error (FE) flag is set. After deciding whether the first stop bit is valid or not, the Receiver goes to idle state and monitors the RXD line to check a valid high to low transition is detected (start bit detection).

RXD

Sample

(U2X = 0)

Sample

(U2X = 1)

STOP 1

(A) (B)

1 2 3 4 5 6 7 8 9 10 11 12 13

1 2 3 4 5 6 7

Figure 12.51 Stop Bit Sampling and Next Start Bit Sampling


(C)

Table 12-18 UART Register Map

Name

UARTBD

UARTDR

UARTCR1

UARTCR2

UARTCR3

UARTST

Address

F6H

F7H

F2H

F3H

F4H

F5H

Dir

R/W

R/W

R/W

R/W

R/W

R/W

Default

FFH

00H

00H

00H

00H

80H

12.12.9 UART Register Description

Description

UART Baud Rate Generation Register

UART Data Register




UART Status Register

UART module consists of UART baud rate generation register (UARTBD), UART data register (UARTDR),

UART control register 1 (UARTCR1), UART control register 2 (UARTCR2) ,UART control register 3 (UARTCR3), and UART status register (UARTST).

12.12.10 Register Description for UART

UARTBD (UART Baud Rate Generation Register) : F6H

7 6 5 4

UARTBD7

R/W

UARTBD6

R/W

UARTBD5

R/W

UARTBD4

R/W

3

UARTBD3

R/W

2

UARTBD2

R/W

1

UARTBD1

R/W

0

UARTBD0

R/W

Initial value : FFH

UARTBD [7:0] The value in this register is used to generate internal baud rate. To prevent malfunction, do not write „0‟.

190 April 20, 2012 Ver. 2.5

MC96F7816/C7816

UARTDR (UART Data Register) : F7H

7 6 5

UARTDR7

R/W

UARTDR6

R/W

UARTDR5

R/W

4

UARTDR4

R/W

3

UARTDR3

R/W

2

UARTDR2

R/W

UARTDR [7:0] The UART Transmit Buffer and Receive Buffer share the same I/O address with this DATA register. The Transmit Data Buffer is the destination for data written to the UARTDR register. Reading the

UDATA register returns the contents of the Receive Buffer.

Write this register only when the UDRE flag is set.

UARTCR1 (UART Control Register 1) : F2H

7

-

6

-

5

UPM1

4

UPM0

- - R/W R/W

3

USIZE2

R/W

2

USIZE1

R/W

1

USIZE0

R/W

0

-

-

Initial value : 00H

UPM[1:0]

USIZE[2:0]

1

1

1

1

0

0

0

0

Selects Parity Generation and Check methods

UPM1 UPM0 Parity

0

0

0

1

No Parity

Reserved

1

1

0

1

Even Parity

Odd Parity

Selects the Length of Data Bits in Frame

USIZE2 USIZE1 USIZE0 Data Length

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

5 bit

6 bit

7 bit

8 bit

Reserved

Reserved

Reserved

9 bit

1

UARTDR1

R/W

0

UARTDR0

R/W

Initial value : 00H

April 20, 2012 Ver. 2.5 191

MC96F7816/C7816


7 6 5 4

UDRIE

R/W

TXCIE

R/W

UDRIE

TXCIE

RXCIE

WAKEIE

TXE

RXE

U2X

RXCIE

UARTEN

R/W

WAKEIE

R/W

3

TXE

R/W

2

RXE

R/W

1

UARTEN

R/W

0

U2X

R/W

Initial value : 00H

Interrupt enable bit for UART Data Register Empty

0

1

Interrupt from UDRE is inhibited (use polling)

When UDRE is set, request an interrupt

Interrupt enable bit for Transmit Complete

0

1

Interrupt from TXC is inhibited (use polling)

When TXC is set, request an interrupt

Interrupt enable bit for Receive Complete

0 Interrupt from RXC is inhibited (use polling)

1 When RXC is set, request an interrupt

Interrupt enable bit for Wake in STOP mode. When device is in stop mode, if RXD goes to LOW level an interrupt can be requested to wakeup system. At that time the UDRIE bit and UARTST register value should be set to

„0b‟ and “00H”, respectively.

0 Interrupt from Wake is inhibited

1 When WAKE is set, request an interrupt

Enables the transmitter unit

0

1

Transmitter is disabled

Transmitter is enabled

Enables the receiver unit

0 Receiver is disabled

1 Receiver is enabled

Activate UART module by supplying clock. When one of TXE and RXE values is

“1”, the UARTEN bit always set to “1”.

0

1

USART is disabled (clock is halted)

USART is enabled

This bit selects receiver sampling rate.

0 Normal operation

1 Double Speed operation

192 April 20, 2012 Ver. 2.5

MC96F7816/C7816


7 6 5 4

-

-

LOOPS

R/W

LOOPS

USBS

TX8

RX8

-

-

-

-

3

-

-

2

USBS

R/W

1

TX8

R/W

0

RX8

R

Initial value : 00H

Controls the Loop Back Mode of UART, for test mode

0

1

Normal operation

Loop Back mode

Selects the length of stop bit.

0

1

1 Stop Bit

2 Stop Bit

The ninth bit of data frame in UART. Write this bit first before loading the

UARTDR register

0

1

MSB (9 th

bit) to be transmitted is

„0‟

MSB (9 th

bit) to be transmitted is „1‟

The ninth bit of data frame in UART. Read this bit first before reading the receive buffer

0

1

MSB (9 th

bit) received is

„0‟

MSB (9 th

bit) received is „1‟

April 20, 2012 Ver. 2.5 193

MC96F7816/C7816

UARTST (UART Status Register) : F5H

7 6 5

UDRE

R/W

TXC

R/W

RXC

R

UDRE

TXC

RXC

WAKE

SOFTRST

DOR

FE

PE

4

WAKE

R/W

3

SOFTRST

R/W

2

DOR

R

1

FE

R/W

0

PE

R/W

Initial value : 80H

The UDRE flag indicates if the transmit buffer (UARTDR) is ready to receive new data. If UDRE is „1‟, the buffer is empty and ready to be written. This flag can generate a UDRE interrupt.

0 Transmit buffer is not empty.

1 Transmit buffer is empty.

This flag is set when the entire frame in the transmit shift register has been shifted out and there is no new data currently present in the transmit buffer. This flag is automatically cleared when the interrupt service routine of a TXC interrupt is executed. This flag can generate a

TXC interrupt. This bit is automatically cleared.

0

1

Transmission is ongoing.

Transmit buffer is empty and the data in transmit shift register are shifted out completely.

This flag is set when there are unread data in the receive buffer and cleared when all the data in the receive buffer are read. The RXC flag can be used to generate a RXC interrupt.

0

1

There is no data unread in the receive buffer

There are more than 1 data in the receive buffer

This flag is set when the RXD pin is detected low while the CPU is in stop mode. This flag can be used to generate a WAKE interrupt. This bit should be cleared by program software.

0 No WAKE interrupt is generated.

1 WAKE interrupt is generated

This is an internal reset and only has effect on UART. Writing

„1‟ to this bit initializes the internal logic of UART and this bit is automatically cleared.

0 No operation

1 Reset UART

This bit is set if a Data OverRun occurs. While this bit is set, the incoming data frame is ignored. This flag is valid until the receive buffer is read.

0

1

No Data OverRun

Data OverRun detected

This bit is set if the first stop bit of next character in the receive buffer is detected as „0‟. This bit is valid until the receive buffer is read.

0 No Frame Error

1 Frame Error detected

This bit is set if the next character in the receive buffer has a Parity Error to be received while Parity Checking is enabled. This bit is valid until the receive buffer is read.

0

1

No Parity Error

Parity Error detected

194 April 20, 2012 Ver. 2.5

12.12.11 Baud Rate setting (example)

MC96F7816/C7816

Table 12-19 Examples of UARTBD Settings for Commonly Used Oscillator Frequencies

Baud

Rate

2400

4800

9600

14.4k

19.2k

28.8k

38.4k

57.6k

76.8k

115.2k

230.4k

(continued)

UARTBD fx=1.00MHz

ERROR

-

-

-

2

1

1

-

25

12

6

3

0.2%

0.2%

-7.0%

8.5%

8.5%

8.5%

-18.6%

-

-

-

-

2400

4800

9600

14.4k

19.2k

28.8k

38.4k

57.6k

76.8k

115.2k

230.4k

250k

0.5M

1M

Baud

Rate

2400

4800

9600

14.4k

19.2k

28.8k

38.4k

57.6k

76.8k

115.2k

230.4k

250k

0.5M

(continued) fx=3.6864MHz

UARTBD ERROR

95

47

23

15

11

7

5

3

2

1

-

-

-

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

-

-

-

Baud

Rate

UARTBD fx=8.00MHz

ERROR

25

16

12

8

6

207

103

51

34

3

1

1

-

-

0.2%

0.2%

0.2%

-0.8%

0.2%

2.1%

0.2%

-3.5%

-7.0%

8.5%

8.5%

0.0%

-

- fx=1.8432MHz

UARTBD ERROR

1

-

-

5

3

2

1

47

23

11

7

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

-25.0%

0.0%

-

-

UARTBD fx=4.00MHz

ERROR

103

51

25

16

12

8

6

3

2

1

-

-

-

0.2%

0.2%

0.2%

2.1%

0.2%

-3.5%

-7.0%

8.5%

8.5%

8.5%

-

-

- fx=11.0592MHz

UARTBD ERROR

35

23

17

11

8

-

143

71

47

5

2

2

-

-

-

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

-7.8%

-

-

UARTBD fx=2.00MHz

ERROR

1

-

-

6

3

2

1

51

25

12

8

0.2%

0.2%

0.2%

-3.5%

-7.0%

8.5%

8.5%

8.5%

-18.6%

-

- fx=7.3728MHz

UARTBD ERROR

191

95

47

31

23

15

11

7

5

3

1

1

-

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

0.0%

-7.8%

-

April 20, 2012 Ver. 2.5 195

MC96F7816/C7816

12.13 LCD Driver


The LCD driver is controlled by the LCD control register (LCDCRH/L) and LCD driver contrast control register

(LCDCCR). The LCLK[1:0] determines the frequency of COM signal scanning of each segment output. A RESET clears the LCD control register LCDCRH, LCDCRL and LCDCCR values to logic

„0‟.

The LCD display can continue operating during IDLE and STOP modes if a sub-frequency clock is used as system clock source.

The clock and duty for LCD driver is automatically initialized by hardware, whenever LCDCRL register data value is rewritten. So, don ‟t rewrite LCDCRL frequently.

196 April 20, 2012 Ver. 2.5

12.13.2 LCD Display RAM Organization

MC96F7816/C7816

Display data are stored to the display data area in the external data memory.

The display data which stored to the display external data area (address 0000H-0024H) are read automatically and sent to the LCD driver by the hardware. The LCD driver generates the segment signals and common signals in accordance with the display data and drive method. Therefore, display patterns can be changed by only overwriting the contents of the display external data area with a program.

Figure 12-52 shows the correspondence between the display external data area and the COM/SEG pins. The

LCD is turned on lights when the display data is “1” and turned off when “0”.

SEG36

SEG35

SEG34

SEG33

SEG32

SEG31

SEG30

SEG29

0024H

0023H

0022H

0021H

0020H

001FH

001EH

001DH

April 20, 2012 Ver. 2.5

SEG7

SEG6

SEG5

SEG4

SEG3

SEG2

SEG1

SEG0

C

O

M

0

0007H

0006H

0005H

0004H

0003H

0002H

0001H

0000H bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7

C

O

M

1

C

O

M

2

C

O

M

3

C

O

M

4

C

O

M

5

C

O

M

6

C

O

M

7

Figure 12.52 LCD Circuit Block Diagram

197

MC96F7816/C7816

12.13.3 LCD Signal Waveform

COM0

SEG0

SEG3

SEG2

COM0

SEG1

SEG0

1 Frame

SEG1

COM0-SEG0

COM0-SEG1

Figure 12.53 LCD Signal Waveforms (Static)

VDD

VSS

VLC0

VSS

+VLC0

VSS

-VLC0

VLC0

VSS

VLC0

VSS

+VLC0

VSS

-VLC0

198 April 20, 2012 Ver. 2.5

COM0

SEG1

COM1

SEG2 SEG3 SEG4

COM0

COM1

SEG1

SEG2

COM0-SEG1

0 1 0 1

MC96F7816/C7816

VDD

VSS

1 Frame

VLC0(VLC1, VLC2)

VLC3

VSS

VLC0(VLC1, VLC2)

VLC3

VSS

VLC0(VLC1, VLC2)

VLC3

VSS

VLC0(VLC1, VLC2)

VLC3

VSS

+VLC0(VLC1, VLC2)

+VLC3

VSS

-VLC3

-VLC0(VLC1, VLC2)

Figure 12.54 LCD Signal Waveforms (1/2Duty, 1/2Bias)

April 20, 2012 Ver. 2.5 199

MC96F7816/C7816

COM0

COM1

COM2

SEG4 SEG3 SEG2

COM0

COM1

COM2

SEG2

SEG3

COM0-SEG2

0 1 2 0 1 2

1 Frame

VDD

VSS

VLC0(VLC1)

VLC2

VLC3

VSS

VLC0(VLC1)

VLC2

VLC3

VSS

VLC0(VLC1)

VLC2

VLC3

VSS

VLC0(VLC1)

VLC2

VLC3

VSS

VLC0(VLC1)

VLC2

VLC3

VSS

+VLC0(VLC1)

+VLC2

+VLC3

VSS

-VLC3

-VLC2

-VLC0(VLC1)


200 April 20, 2012 Ver. 2.5

COM0

COM1

COM2

COM3

SEG4 SEG3

COM0

COM1

COM2

SEG3

SEG4

COM0-SEG3

0 1 2 3 0 1 2 3

MC96F7816/C7816

VDD

VSS

1 Frame

VLC0(VLC1)

VLC2

VLC3

VSS

VLC0(VLC1)

VLC2

VLC3

VSS

VLC0(VLC1)

VLC2

VLC3

VSS

VLC0(VLC1)

VLC2

VLC3

VSS

VLC0(VLC1)

VLC2

VLC3

VSS

+VLC0(VLC1)

+VLC2

+VLC3

VSS

-VLC3

-VLC2

-VLC0(VLC1)


April 20, 2012 Ver. 2.5 201

MC96F7816/C7816

COM0

COM1

COM2

COM3

COM4

COM5

COM6

COM7

S

E

G

7

S

E

G

8

S

E

G

9

S

E

G

1

0

S

E

G

1

1

COM0

COM1

0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7

1 Frame

COM2

SEG7

SEG8

COM0-SEG7

VDD

VSS

VLC0

VLC1

VLC2

VLC3

VSS

VLC0

VLC1

VLC2

VLC3

VSS

+VLC0

+VLC1

+VLC2

+VLC3

VSS

-VLC3

-VLC2

-VLC1

-VLC0

VLC0

VLC1

VLC2

VLC3

VSS

VLC0

VLC1

VLC2

VLC3

VSS

VLC0

VLC1

VLC2

VLC3

VSS


202 April 20, 2012 Ver. 2.5

12.13.4 LCD Voltage Dividing Connection

(1/2 BIAS)

R

MC96F7816/C7816

(1/3 BIAS)

VLCD

(1/4 BIAS)

VLCD

2R

R R R

2R

R R R R

VLC0 VLC1 VLC2 VLC3 VLC0 VLC1 VLC2 VLC3

DISP

LBRS

DISP

LBRS

VSS VSS


Notes)

1. The internal resistors are disconnected in the static.

2. When 1/2 bias are selected, the VLC0, VLC1 and VLC2 are internally connected.

3. When 1/3 bias are selected, the VLC0 and VLC1 are internally connected.

4. When the internal resistors are selected, all the P40/VLC0, P41/VLC1, P42/VLC2, P43/VLC3, P44/CAPH, and

P45/CAPL pins can be used for normal I/O.

Figure 12.58 Internal Resistor Bias Connection

April 20, 2012 Ver. 2.5 203

MC96F7816/C7816

(1/2 BIAS)

(1/3 BIAS)

2R

VLCD

VLC0 VLC1 VLC2 VLC3

VLC0 VLC1 VLC2

R

VLC3

VSS

(1/4 BIAS)

2R

VLCD

VLC0 VLC1 VLC2 VLC3

DISP

LBRS

DISP

LBRS


R R R R R R R

VSS VSS

Notes)

1. A resistor connection is not needed when it is static.

2. When the external resistor bias is selected, the internal resistors for bias are disconnected.

3. When the external resistor bias is selected, the dividing resistors should be connected like the above figure and the needed bias pins should be selected as the LCD bias function pins (VLC0, VLC1, VLC2, and VLC3) by

P4FSR register.

- When it is static, all the P40/VLC0, P41/VLC1, P42/VLC2, P43/VLC3, P44/CAPH, and P45/CAPL pins can be used for normal I/O.

- When it is 1/2 bias, the P40/VLC0, and P43/VLC3 pins should be selected as VLC0 and VLC3 functions. The other pins can be used for normal I/O.

- When it is 1/3 bias, the P40/VLC0, P42/VLC2, and P43/VLC3 pins should be selected as VLC0, VLC2 and

VLC3 functions. The other pins can be used for normal I/O.

- When it is 1/4 bias, the P40/VLC0, P41/VLC1, P42/VLC2, and P43/VLC3 pins should be selected as VLC0,

VLC1, VLC2 and VLC3 functions. The other pins can be used for normal I/O.

Figure 12.59 External Resistor Bias Connection

204 April 20, 2012 Ver. 2.5

(STATIC, 1/2 BIAS)

VLCD

MC96F7816/C7816

VLC0 VLC1 VLC2 VLC3

(1/3 BIAS)

VLCD

VLC0 VLC1 VLC2 VLC3

VLC0 VLC1 VLC2

0.1uF

(1/4 BIAS)

VLC3

0.1uF

CAPH

0.1uF

CAPL

VSS

VLCD

VLC0 VLC1 VLC2 VLC3

VLC0 VLC1

0.1uF

VLC2

0.1uF

VLC3

0.1uF

CAPH

0.1uF

CAPL VLC0

0.1uF

VLC1

0.1uF

VLC2

0.1uF

VLC3

0.1uF

CAPH

0.1uF

CAPL

VSS

Notes) When the capacitor bias is selected for the VLCD voltage, all the P40/VLC0, P41/VLC1, P42/VLC2,

P43/VLC3, P44/CAPH, and P45/CAPL pins should be selected for LCD bias function pins by the P4FSR and should be connected like the above figure.

Figure 12.60 Capacitor Bias Connection

April 20, 2012 Ver. 2.5 205

MC96F7816/C7816


Port

Latch

SEG/Port

Driver

LCD

Display

RAM

COM/Port

Driver fLCD

LCDCRL

Timing

Controller

LCDCRH

LCDCCR

Voltage

Booster

VLC0

VLC1

VLC2

VLC3

CAPH

CAPL

Figure 12.61 LCD Circuit Block Diagram

Note) The clock and duty for LCD driver is automatically initialized by hardware, whenever LCDCRL register data value is rewritten. So, don ‟t rewrite LCDCRL frequently


Table 12-20 LCD Register Map

Name

LCDCRH

LCDCRL

LCDCCR

Address

9AH

99H

9BH

Dir

R/W

R/W

R/W

Default

00H

00H

00H

12.13.7 LCD Driver Register Description

Description

LCD Driver Control High Register

LCD Driver Control Low Register

LCD Driver Contrast Control Register

LCD driver register has three control registers, LCD driver control high register (LCDCRH), LCD driver control low register (LCDCRL) and LCD driver contrast control register (LCDCCR).

206 April 20, 2012 Ver. 2.5

12.13.8 Register Description for LCD Driver

MC96F7816/C7816

LCDCRH (LCD Driver Control High Register) : 9AH

7

-

-

6

-

-

LBRS

5

-

-

BTYPE[1:0]

DISP

4

-

-

3

LBRS

R/W

2

BTYPE1

R/W

1

BTYPE0

R/W

0

DISP

R/W

Initial value : 00H

LCD Bias Resistor Select

0 Not select P-Tr resistor

1 Select P-Tr resistor 2R

LCD Duty and Bias Select (note)

BTYPE1 BTYPE0 Description

0

0

0

1

Internal resistor bias

External resistor bias

1

1

0

1

0

1

Capacitor bias (Voltage booster)

Not available

Notes)

1. All the VLC0 – VLC3, CAPH, and CAPL pins must be used as bias functions (P4FSR.5-.0 =

“111111b”) When the capacitor bias is selected for the LCD bias type.

2. Refer to the P4FSR register for pin functions.

LCD Display Control

Display off (The LCD block and voltage booster are off)

Normal display on (When the BTYPE[1:0] = “10b”, the voltage booster is turn on)

April 20, 2012 Ver. 2.5 207

MC96F7816/C7816

LCDCRL (LCD Driver Control Low Register) : 99H

7 6 5 4

-

-

-

-

DBS[3:0]

DBS3

R./W

LCLK[1:0]

DBS2

R/W

3

DBS1

R/W

2

DBS0

R/W

1

LCLK1

R/W

0

LCLK0

R/W

Initial value : 00H

0

0

0

0

LCD Duty and Bias Select

DBS3 DBS2 DBS1 DBS0 Description

0 0 0 0 1/8Duty, 1/4Bias (60k ohm)

0 0 0 1 1/6Duty, 1/4Bias (60k ohm)

0

0

1

1

1

1

0

0

0

1

0

1

1/5Duty, 1/3Bias (60k ohm)




0

0

1

1

1

1

0

0

1

1

0

0

0

1

0

1




Static

Others Values: Not available

LCD Clock Select (When f

WCK

(Watch timer clock)= 32.768 kHz)

LCLK1 LCLK0 Description

0 0 f

LCD

= 128Hz

0

1

1

0 f

LCD

= 256Hz f

LCD

= 512Hz

1 1 f

LCD

= 1024Hz

Note) The LCD clock is generated by watch timer clock (f

WCK

). So the watch timer should be enabled when the LCD display is turned on.

Table 12-21 LCD Frame Frequency

LCD Clock

Frequency (f

LCD

)

Static

LCD Frame Frequency (f

FRAME

)

1/2 Duty 1/3 Duty 1/4 Duty 1/5 Duty 1/6 Duty 1/8 Duty

128

256

512

128

256

512

64

128

256

43

85

171

32

64

128

1024 1024 512 341 256

The LCD frame frequency is calculated by the following formula:

26

51

102

205

21

43

85

171

16

32

64

128

LCD Frame Frequency (f

FRAME

) = f

LCD

× Duty[Hz]

Ex) In cace of 1/4 duty and f

LCD

= 512Hz, f

FRAME

= f

LCD

× 1/4 = 512 × 1/4 = 128[Hz]

Unit

Hz

208 April 20, 2012 Ver. 2.5

MC96F7816/C7816

LCDCCR (LCD Driver Contrast Control Register) : 9BH

7

-

-

6

-

-

5

-

-

4

-

-

3

VLCD3

R/W

2

VLCD2

R/W

1

VLCD1

R/W

0

VLCD0

R/W

Initial value : 00H

VLCD[3:0] VLCD3 Voltage Control when the capacitor bias bias is selected

Description

1

1

1

1

0

0

0

0

0

0

0

MC96F7816(FLASH) MC96C7816(MASK)

VLCD3 VLCD2 VLCD1 VLCD0

0 0 0 0

1/2, 1/3 Bias 1/4 Bias 1/2, 1/3 Bias 1/4 Bias

VLC3 = 1.000V 0.856V 0.950V 0.800V

0

0

0

1

0

1

1

0

1

0

1

0

VLC3 =

VLC3 =

VLC3 =

VLC3 =

1.045V

1.090V

1.135V

1.180V

0.887V

0.918V

0.949V

0.980V

1.000V

1.050V

1.100V

1.150V

0.833V

0.867V

0.900V

0.933V

1

1

1

0

0

0

0

0

1

1

0

0

1

1

1

0

1

0

1

0

1

VLC3 =

VLC3 =

VLC3 =

1.225V

1.270V

1.315V

VLC3 = 1.360V

VLC3 = 1.405V

VLC3 = 1.450V

VLC3 = 1.500V

1.011V

1.052V

1.073V

1.200V

1.250V

1.300V

1.104V 1.350V

1.135V 1.400V

1.166V 1.450V

1.197V 1.500V

0.967V

1.000V

1.033V

1.067V

1.100V

1.133V

1.167V

1

1

1

1

1

1

1

1

0

0

1

1

0

1

0

1

VLC3 =

VLC3 =

VLC3 =

VLC3 =

1.550V

1.600V

1.650V

1.700V

1.228V

1.259V

1.290V

1.321V

1.550V

1.600V

1.650V

1.700V

1.200V

1.233V

1.267V

1.300V

Notes)

1. The VLCD0 voltage can be calculated by the below formulas.

- VLC0 = VLC3 x 2 ; 1/2 bias

- VLC0 = VLC3 x 3 ; 1/3 bias

- VLC0 = VLC3 x 4 ; 1/4 bias, static

2. When the 1/4 bias is selected, the VLCD[3:0] value should be between “0000b” and

“1001b”.

3.The VLC3

‟s electrical characteristics is ±10% with 1/2, 1/3, 1/4 capacitor bias in

MC96F7816(FLASH).

April 20, 2012 Ver. 2.5 209

MC96F7816/C7816

13. Power Down Operation

13.1 Overview

The MC96F7816 has two power-down modes to minimize the power consumption of the device. In power down mode, power consumption is reduced considerably. The device provides three kinds of power saving functions,

Main-IDLE, Sub-IDLE and STOP mode. In three modes, program is stopped.

13.2 Peripheral Operation in IDLE/STOP Mode

Table 13-1 Peripheral Operation during Power Down Mode

Peripheral

CPU

IDLE Mode

ALL CPU Operation are Disable

RAM Retain

Basic Interval Timer Operates Continuously

Watch Dog Timer Operates Continuously

Watch Timer Operates Continuously

Timer0~3 Operates Continuously

ADC

BUZ

SIO

UART

LCD Controller

Operates Continuously





Internal OSC

(4MHz)

WDTRC OSC

(6kHz)

Main OSC

Oscillation

Stop

Oscillation

Sub OSC

(32.768kHz)

I/O Port

Control Register

Oscillation

Retain

Retain

Address Data Bus Retain

Release Method By RESET, all Interrupts

STOP Mode

ALL CPU Operation are Disable

Retain

Stop

Stop (Can be operated with WDTRC OSC)

Stop (Can be operated with sub clock)

Halted (Only when the Event Counter Mode is

Enabled, Timer operates Normally)

Stop

Stop

Only operate with external clock

Stop

Stop (Can be operated with sub clock)

Stop when the system clock (fx) is f

IRC

Can be operated with setting value

Stop when fx = f

XIN

Stop when fx = f

SUB

Retain

Retain

Retain

By RESET, Timer Interrupt (EC0,EC2),

SIO (External clock), External Interrupt,

UART by RX, WT (sub clock), WDT

210 April 20, 2012 Ver. 2.5

MC96F7816/C7816

13.3 IDLE Mode

The power control register is set to „01h‟ to enter the IDLE Mode. In this mode, the internal oscillation circuits remain active. Oscillation continues and peripherals are operated normally but CPU stops. It is released by reset or interrupt. To be released by interrupt, interrupt should be enabled before IDLE mode. If using reset, because the device becomes initialized state, the registers have reset value.

OSC

CPU Clock

External

Interrupt

Release

Stand-by Mode Normal Operation Normal Operation

Figure 13.1 IDLE Mode Release Timing by External Interrupt

April 20, 2012 Ver. 2.5 211

MC96F7816/C7816

13.4 STOP Mode

The power control register is set to „03H‟ to enter the STOP Mode. In the stop mode, the selected oscillator, system clock and peripheral clock is stopped, but watch timer can be continued to operate with sub clock. With the clock frozen, all functions are stopped, but the on-chip RAM and control registers are held. For example, If the internal RC oscillator (f IRC ) is selected for the system clock and the sub clock (f SUB ) is oscillated, the internal

RC oscillator stops oscillation and the sub clock is continuously oscillated in stop mode. At that time, the watch timer and LCD controller can be operated with the sub clock.

The source for exit from STOP mode is hardware reset and interrupts. The reset re-defines all the control registers.

When exit from STOP mode, enough oscillation stabilization time is required to normal operation. Figure 13.2 shows the timing diagram. When released from STOP mode, the Basic interval timer is activated on wake-up.

Therefore, before STOP instruction, user must be set its relevant prescale divide ratio to have long enough time.

This guarantees that oscillator has started and stabilized.

OSC

CPU Clock

External

Interrupt

BIT Counter

Release

STOP Instruction

Execute n n+1 n+2 n+3

Normal Operation

0

STOP Operation

1 2

Clear & Start

By Software setting

FE FF 0 1

Normal Operation

Before executed STOP instruction, BIT must be set properly by software to get stabilization.

Figure 13.2 STOP Mode Release Timing by External Interrupt

212 April 20, 2012 Ver. 2.5

MC96F7816/C7816

13.5 Release Operation of STOP Mode

After STOP mode is released, the operation begins according to content of related interrupt register just before

STOP mode start (Figure 13.3). If the global interrupt Enable Flag (IE.EA) is set to `1`, the STOP mode is released by the interrupt which each interrupt enable flag = `1` and the CPU jumps to the relevant interrupt service routine. Even if the IE.EA bit is cleared to „0‟, the STOP mode is released by the interrupt of which the interrupt enable flag is set to

„1‟.

SET PCON[7:0]

SET IEx.b

STOP Mode

Interrupt Request

Corresponding Interrupt

Enable Bit(IE, IE1, IE2, IE3)

IEx.b==1 ?

Y

STOP Mode

Release

N

Interrupt Service

Routine

Next Instruction

Figure 13.3 STOP Mode Release Flow

April 20, 2012 Ver. 2.5 213

MC96F7816/C7816


Table 13-2 Power Down Operation Register Map

Name

PCON

Address

87H

Dir

R/W

Default

00H

Description

Power Control Register

13.5.2 Power Down Operation Register Description

The power down operation register consists of the power control register (PCON).

13.5.3 Register Description for Power Down Operation

PCON (Power Control Register) : 87H

7

PCON7

R/W

6

-

-

5

-

-

4

-

-

3

PCON3

R/W

2

PCON2

R/W

1

PCON1

R/W

0

PCON0

R/W

Initial value : 00H

PCON[7:0] Power Control

01H IDLE mode enable

03H STOP mode enable

Notes) 1. To enter IDLE mode

, PCON must be set to „01H‟.

2. To enter STOP mode, PCON must be set to „03H‟.

3. The PCON register is automatically cleared by a release signal in STOP/IDLE mode.

4. Three or more NOP instructions must immediately follow the instruction that make the device enter

STOP/IDLE mode. Refer to the following examples.

Ex1) MOV

NOP

NOP

NOP

•

•

•

PCON, #01H ; IDLE mode Ex2) MOV PCON, #03H

NOP

NOP

NOP

•

•

•

; STOP mode

214 April 20, 2012 Ver. 2.5

14. RESET

14.1 Overview

The following is the hardware setting value.

Table 14-1 Reset State

On Chip Hardware

Program Counter (PC)

Accumulator

Stack Pointer (SP)

Peripheral Clock

Control Register

Initial Value

0000h

00h

07h

On

Refer to the Peripheral Registers

14.2 Reset Source

The MC96F7816 has five types of reset sources. The following is the reset sources.

- External RESETB

- Power ON RESET (POR)

- WDT Overflow Reset (In the case of WDTEN = `1`)

- Low Voltage Reset (In the case of LVREN = `0 `)

- OCD Reset

MC96F7816/C7816

14.3 RESET Block Diagram

Ext RESET

Disable by FUSE

LVR

LVR Enable

POR RST

WDT RST

WDT RSTEN

OCD RST

OCD RSTEN

RESET Noise

Canceller

RESET Noise

Canceller

S Q

R

IFBIT

(BIT Overflow)

Figure 14.1 RESET Block Diagram

Internal

Reset

April 20, 2012 Ver. 2.5 215

MC96F7816/C7816

14.4 RESET Noise Canceller

The Figure 14.2 is the noise canceller diagram for noise cancellation of RESET. It has the noise cancellation value of about 2us (@V

DD

=5V) to the low input of system reset. t < T

RNC t < T

RNC

A t > T

RNC t > T

RNC t > T

RNC

A’

Figure 14.2 Reset noise canceller timer diagram

14.5 Power On RESET

When rising device power, the POR (Power On Reset) has a function to reset the device. If POR is used, it executes the device RESET function instead of the RESET IC or the RESET circuits.

Fast VDD Rise Time

VDD nPOR

(Internal Signal)

BIT Overflows

BIT Starts

Internal RESETB

Oscillation

Figure 14.3 Fast VDD Rising Time

Slow VDD Rise Time, min. 0.15V/mS

V

POR

=1.4V (Typ)

VDD nPOR

(Internal Signal) BIT Overflows

BIT Starts

Internal RESETB

Oscillation

Figure 14.4 Internal RESET Release Timing On Power-Up

216 April 20, 2012 Ver. 2.5

Counting for config read start after POR is released

VDD

Internal nPOR

PAD RESETB

“H”

LVR_RESETB

BIT (for Config) 00 01 02 03 00 01

..

27 28 F1

BIT (for Reset) 00

00 01

1us X 256 X 28h = about 10ms

02 03

Config Read

1us X 4096 X 4h = about 16ms

RESET_SYSB

INT-OSC (4MHz)

INT-OSC 4MHz/4

INT-OSC 4MHz /4 = 1MHz (1us)

Figure 14.5 Configuration Timing when Power-on

MC96F7816/C7816

04 00

:VDD Input

:Internal OSC

⑥

④

Reset Release

Config Read

POR

②

①

April 20, 2012 Ver. 2.5

③ ⑤

Figure 14.6 Boot Process Wave Form

⑦

217

MC96F7816/C7816

Table 14-2 Boot Process Description

Description Process

①

②

-No Operation

③

④

⑤

⑥

⑦

Remarks

-1st POR level Detection -about 1.4V

- (INT-OSC 4MHz/4)x256x28h Delay section (=10ms)

-VDD input voltage must rise over than flash operating voltage for Config read

-Slew Rate

0.15V/ms

- Config read point

- Rising section to Reset Release Level

-about 1.5V ~ 1.6V

-Config Value is determined by

Writing Option

-16ms point after POR or Ext_reset release

- Reset Release section (BIT overflow) i) after16ms, after External Reset Release (External reset) ii) 16ms point after POR (POR only)

- BIT is used for Peripheral stability

-Normal operation

218 April 20, 2012 Ver. 2.5

MC96F7816/C7816

14.6 External RESETB Input

The External RESETB is the input to a Schmitt trigger. If RESETB pin is held with low for at least 10us over within the operating voltage range and stable oscillation, it is applied and the internal state is initialized. After reset state becomes „1‟, it needs the stabilization time with 16ms and after the stable state, the internal RESET becomes „1‟. The Reset process step needs 5 oscillator clocks. And the program execution starts at the vector address stored at address 0000H.

1 2 3 4 5

OSC

RESETB

Internal

RESETB

ADDRESS

BUS

CORE

BUS

TST = 16.4ms

Release

Release

? ? 00 01 02 ?

Stabilization Time

? ? ? 02 ? ? ?

RESET Process

Step

Main Program

Figure 14.7 Timing Diagram after RESET

PRESCALER COUNT START

VDD

OSC START TIMING

Figure 14.8 Oscillator generating waveform example

Note) As shown Figure 14.8, the stable generating time is not included in the start-up time.

The RESETB pin has a Pull-up register by H/W.

April 20, 2012 Ver. 2.5 219

MC96F7816/C7816

14.7 Brown Out Detector Processor

The MC96F7816 has an On-chip brown-out detection circuit(BOD) for monitoring the VDD level during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be selected by LVRVS[3:0]. In the STOP mode, this will contribute significantly to the total current consumption. So to minimize the current consumption, the LVREN bit is set to off by software.

External VDD

LVRVS[3:0]

LVREN

Brown Out

Detector

(BOD) RESET_BODB

VDD

Internal

RESETB

VDD

Internal

RESETB

CPU

Write

SCLK

(System CLK)

D Q

CP r

LVRF

(Low Voltage

Reset Flag) nPOR

Figure 14.9 Block Diagram of BOD

V

BOD

MAX

V

BOD

MIN

16ms

V

BOD

MAX

V

BOD

MIN t < 16ms 16ms

Figure 14.10 Internal Reset at the power fail situation

220 April 20, 2012 Ver. 2.5

MC96F7816/C7816

“H”

VDD

“H”

Internal nPOR

“H”

PAD RESETB

LVR_RESETB

BIT (for Config) F1 00 01 02

..

..

..

27 28

BIT (for Reset)

Config Read

RESET_SYSB

INT-OSC (4MHz)

INT-OSC 4MHz/4

00 01

1us X 256 X 28h = about 10ms

02 03

1us X 4096 X 4h = about 16ms

Main OSC Off

F1

04

INT-OSC 4MHz /4 = 1MHz (1us)

Figure 14.11 Configuration timing when BOD RESET

14.8 LVI Block Diagram

VDD

Reference

Voltage

Generator

0000b

0001b

0010b

0011b

0100b

0101b

0110b

0111b

1000b

1001b

1010b

1011b

1100b

M

U

X

LVI Circuit

LVIEN

LVIREF

4

LVILS[3:0]

Figure 14.12 LVI Diagram

LVIF

April 20, 2012 Ver. 2.5

00

221

MC96F7816/C7816


Table 14-3 Reset Operation Register Map

Name

RSTFR

LVRCR

LVICR

Address

E8H

D8H

86H

Dir

R/W

R/W

R/W

Default

80H

00H

00H

14.8.2 Reset Operation Register Description

Description

Reset Flag Register

Low Voltage Reset Control Register

Low Voltage Indicator Control Register

The reset control register consists of the reset flag register (RSTFR), low voltage reset control register (LVRCR), and low voltage indicator control register (LVICR).

14.8.3 Register Description for Reset Operation

RSTFR (Reset Flag Register) : E8H

7

PORF

R/W

6

EXTRF

R/W

5

WDTRF

R/W

4

OCDRF

R/W

3

LVRF

R/W

2

-

-

1

-

-

0

-

-

Initial value : 80H

PORF

EXTRF

WDTRF

OCDRF

Power-On Reset flag bit. The bit is reset by writing

„0‟ to this bit.

0 No detection

1 Detection

External Reset (RESETB) flag bit. The bit is reset by writing „0‟ to this bit or by Power-On Reset.

0 No detection

1 Detection

Watch Dog Reset flag bit. The bit is reset by writing „0‟ to this bit or by

Power-On Reset.

0 No detection

1 Detection

On-Chip Debug Reset flag bit. The bit is reset by writing „0‟ to this bit or by

Power-On Reset.

0 No detection

LVRF

1 Detection

Low Voltage Reset flag bit. The bit is reset by writing

„0‟ to this bit or by

Power-On Reset.

0

1

No detection

Detection

Notes) 1. When the Power-On Reset occurs, the PORF bit is only set to

“1”, the other flag (WDTRF and OCDRF) bits are all cleared to “0”.

2. When the Power-On Reset occurs, the EXTRF bit is unknown, At that time, the EXTRF bit can be set to

“1” when External Reset (RESETB) occurs.

3. When the Power-On Reset occurs, the LVRF bit is unknown, At that time, the LVRF bit can be set to

“1” when Low Voltage Reset(LVR) occurs.

4. When a reset except the POR occurs, the corresponding flag bit is only set to

“1”, the other flag bits are kept in the previous values.

222 April 20, 2012 Ver. 2.5

MC96F7816/C7816

LVRCR (Low Voltage Reset Control Register) : D8H

7 6 5 4

LVRST

R/W

-

-

-

-

LVRVS3

R/W

3

LVRVS2

R/W

2

LVRVS1

R/W

1

LVRVS0

R/W

0

LVREN

R/W

Initial value : 00H

LVRST

LVRVS[3:0]

LVREN

1

1

1

1

0

0

0

1

1

0

0

0

0

LVR Enable when Stop Release

0

1

Not effect at stop release

LVR enable at stop release

Notes)

When this bit is

„1‟, the LVREN bit is cleared to „0‟ by stop mode to release. (LVR enable)

When this bit is

„0‟, the LVREN bit is not effect by stop mode to release.

LVR Voltage Select

LVRVS3 LVRVS2 LVRVS1 LVRVS0 Description

0 0 0 0

F7816

1.60V

0

0

0

1

1

1

1

0

0

0

1

1

0

0

1

1

0

0

1

0

1

0

1

0

1

0

1

2.00V

2.10V

2.20V

2.32V

2.44V

2.59V

2.75V

2.93V

3.14V

C7816

1.60V

2.05V

2.15V

2.25V

2.37V

2.49V

2.64V

2.80V

2.98V

3.19V

1

1

0

0

1

1

1

1

1

1

0

0

1

1

LVR Operation

0 LVR Enable

1 LVR Disable

0

1

0

1

0

1

3.38V

3.67V

4.00V

4.40V

Not available

Not available

3.43V

3.77V

4.10V

4.50V

NOTES) 1. The LVRVS[3:0] bits are cleared by a power-on reset but are retained by other reset signals.

2. The LVRVS[3:0] bits should be set to „0000b‟ while LVREN bit is “1”.

April 20, 2012 Ver. 2.5 223

MC96F7816/C7816

LVICR (Low Voltage Indicator Control Register) : 86H

7 6 5 4

-

-

-

-

LVIF

LVIEN

LVIF

R/W

LVILS[3:0]

LVIEN

R/W

3

LVILS3

R/W

2

LVILS2

R/W

1

LVILS1

R/W

0

LVILS0

R/W

Initial value : 00H

1

1

1

1

0

1

1

1

1

0

0

0

0

0

0

0

Low Voltage Indicator Flag Bit

0

1

No detection

Detection

LVI Enable/Disable

0

1

Disable

Enable

LVI Level Select

LVILS3 LVILS2 LVILS1 LVILS0 Description

0

0

0

0

1

1

1

0

0

1

1

0

0

1

0

1

0

1

0

1

0

F7816

2.00V

2.10V

2.20V

2.32V

2.44V

2.59V

2.75V

1

0

0

0

0

1

1

1

1

1

0

0

1

1

0

0

1

1

1

0

1

0

1

0

1

0

1

C7816

2.05V

2.15V

2.25V

2.37V

2.49V

2.64V

2.80V

2.93V

3.14V

3.38V

3.67V

4.00V

2.98V

3.19V

3.43V

3.77V

4.10V

4.40V 4.50V

Ext. Reference (LVIREF)

Not available

Not available

224 April 20, 2012 Ver. 2.5

15. On-chip Debug System

15.1 Overview

15.1.1 Description

MC96F7816/C7816

On-chip debug system (OCD) of MC96F7816 can be used for programming the non-volatile memories and onchip debugging. Detail descriptions for programming via the OCD interface can be found in the following chapter.

Figure 15.1 shows a block diagram of the OCD interface and the On-chip Debug system.

15.1.2 Feature

• Two-wire external interface: 1-wire serial clock input, 1-wire bi-directional serial data bus

• Debugger Access to:

− All Internal Peripheral Units

− Internal data RAM

− Program Counter

− Flash and Data EEPROM Memories

• Extensive On-chip Debug Support for Break Conditions, Including

− Break Instruction

− Single Step Break

− Program Memory Break Points on Single Address

− Programming of Flash, EEPROM, Fuses, and Lock Bits through the two-wire Interface

− On-chip Debugging Supported by Dr.Choice

®

• Operating frequency

Supports the maximum frequency of the target MCU

April 20, 2012 Ver. 2.5 225

MC96F7816/C7816

Target MCU internal circuit

USB

Format converter

DSCL

DSDA

BDC

DBG

Control

CPU DBG Register

Address bus

Internal data bus

User I/O

Code memory

IRAM

Flash

EEPROM

Data memory

Figure 15.1 Block Diagram of On-Chip Debug System

15.2 Two-Pin External Interface

15.2.1 Basic Transmission Packet

Peripheral

• 10-bit packet transmission using two-pin interface.

• 1-packet consists of 8-bit data, 1-bit parity and 1-bit acknowledge.

• Parity is even of „1‟ for 8-bit data in transmitter.

• Receiver generates acknowledge bit as „0‟ when transmission for 8-bit data and its parity has no error.

• When transmitter has no acknowledge (Ac knowledge bit is „1‟ at tenth clock), error process is executed in transmitter.

• When acknowledge error is generated, host PC makes stop condition and transmits command which has error again.

• Background debugger command is composed of a bundle of packet.

• Start condition and stop condition notify the start and the stop of background debugger command respectively.

226 April 20, 2012 Ver. 2.5

MC96F7816/C7816

Figure 15.2 10-bit Transmission Packet

15.2.2 Packet Transmission Timing

15.2.2.1 Data Transfer

DSDA

LSB acknowledgement signal from receiver

LSB acknowledgement signal from receiver

DSCL

St

START

1 10

ACK

1

Figure 15.3 Data Transfer on the Twin Bus

10

ACK

Sp

STOP

April 20, 2012 Ver. 2.5 227

MC96F7816/C7816

15.2.2.2 Bit Transfer

DSDA

DSCL data line stable: data valid except Start and Stop change of data allowed

Figure 15.4 Bit Transfer on the Serial Bus

15.2.2.3 Start and Stop Condition

DSDA

DSCL

St

START condition

Figure 15.5 Start and Stop Condition

DSDA

Sp

STOP condition

DSCL

228 April 20, 2012 Ver. 2.5

15.2.2.4 Acknowledge Bit

MC96F7816/C7816

Data output by transmitter no acknowledge

Data output

By receiver

DSCL from master

1 2 9 acknowledge

10 clock pulse for acknowledgement

Figure 15.6 Acknowledge on the Serial Bus

Acknowledge bit transmission

Minimum

500ns

Host PC

DSCL OUT

Target Device

DSCL OUT

Start wait wait HIGH

Maximum 5 T

SCLK start HIGH minimum 1 T

SCLK for next byte transmission

DSCL

Internal Operation

Figure 15.7 Clock Synchronization during Wait Procedure

Acknowledge bit transmission

April 20, 2012 Ver. 2.5 229

MC96F7816/C7816

15.2.3 Connection of Transmission

Two-pin interface connection uses open-drain (wire-AND bidirectional I/O). pull up resistors

Rp Rp

VDD

DSDA(Debugger Serial Data Line)

DSCL(Debugger Serial Clock Line)

VDD VDD

DSCL

OUT

DSCL

IN

DSDA

OUT

DSDA

IN

DSCL

OUT

DSCL

IN

Host Machine(Master) Target Device(Slave)

Current source for DSCL to fast 0 to 1 transition in high speed mode

Figure 15.8 Connection of Transmission

DSDA

OUT

DSDA

IN

230 April 20, 2012 Ver. 2.5

16. Flash Memory

16.1 Overview

16.1.1 Description

MC96F7816/C7816

MC96F7816 incorporates flash memory to which a program can be written, erased, and overwritten while mounted on the board. The flash memory can be read by

„MOVC‟ instruction and it can be programmed in OCD, serial ISP mode or user program mode.

• Flash Size : 16K bytes

• Single power supply program and erase

• Command interface for fast program and erase operation

• Up to 100,000 program/erase cycles at typical voltage and temperature for flash memory

April 20, 2012 Ver. 2.5 231

MC96F7816/C7816

16.1.2 Flash Program ROM Structure

03FFFH

03FC0H

03FBFH

03F80H

03F7FH

03F40H

03F3FH

Sector 255

Sector 254

Sector 253

Sector 252

ROM

Address

03FC0H

03F80H

03F40H

Flash

Sector

Address

Accessed by

MOVX instruction only

00080H

0007FH

00040H

0003FH

00000H

Sector 2

00080H

Sector 1

00040H

Sector 0

00000H

64bytes

Flash Page Buffer

(External Data Memory, 64bytes)

803FH

8000H

Page(Sector)

Buffer

Address

Flash Controller

FSADRH/M/L

FIDR

FMCR

Figure 16.1 Flash Program ROM Structure

232 April 20, 2012 Ver. 2.5


MC96F7816/C7816

Table 16-1 Flash Memory Register Map

Name

FSADRH

FSADRM

FSADRL

FIDR

FMCR

Address

FAH

FBH

FCH

FDH

FEH

Dir

R/W

R/W

R/W

R/W

R/W

Default

00H

00H

00H

00H

00H

Description

Flash Sector Address High Register

Flash Sector Address Middle Register

Flash Sector Address Low Register

Flash Identification Register

Flash Mode Control Register

16.1.4 Register Description for Flash Memory Control and Status

Flash control register consists of the flash sector address high register (FSADRH), flash sector address middle register (FSADRM), flash sector address low register (FSADRL), flash identification register (FIDR), and flash mode control register (FMCR). They are mapped to SFR area and can be accessed only in programming mode.

April 20, 2012 Ver. 2.5 233

MC96F7816/C7816

16.1.5 Register Description for Flash

FSADRH (Flash Sector Address High Register) : FAH

7 6 5 4

-

-

-

-

-

-

-

-

3

FSADRH3

R/W

2

FSADRH 2

R/W

1 0

FSADRH1

R/W

FSADRH0

R/W

Initial value : 00H

FSADRM7

R/W

FSADRH[3:0] Flash Sector Address High

FSADRM (Flash Sector Address Middle Register) : FBH

7 6 5 4

FSADRM6

R/W

FSADRM5

R/W

FSADRM4

R/W

3

FSADRM3

R/W

2

FSADRM2

R/W

1 0

FSADRM1 FSADRM0

R/W R/W

Initial value : 00H

FSADRL7

R/W

FSADRM[7:0] Flash Sector Address Middle

FSADRL (Flash Sector Address Low Register) : FCH

7 6 5 4

FSADRL6

R/W

FSADRL5

R/W

FSADRL4

R/W

3

FSADRL3

R/W

2

FSADRL2

R/W

1 0

FSADRL1

R/W

FSADRL0

R/W

Initial value : 00H

R/W R/W

FSADRL[7:0]

FIDR[7:0]

R/W

Flash Sector Address Low

FIDR (Flash Identification Register) : FDH

7 6 5

FIDR7 FIDR6 FIDR5

4

FIDR4

R/W

3

FIDR3

R/W

2

FIDR2

R/W

1

FIDR1

R/W

0

FIDR0

R/W

Initial value : 00H

Flash Identification

Others No identification value

10100101 Identification value for a flash mode

(These bits are automatically cleared to logic

„00H‟ immediately after one time operation except “flash page buffer reset mode”)

234 April 20, 2012 Ver. 2.5

MC96F7816/C7816

FMCR (Flash Mode Control Register) : FEH

7 6 5 4

FMBUSY

R

-

-

FMBUSY

FMCR[2:0]

-

-

-

-

3

-

-

2

FMCR2

R/W

1

FMCR1

R/W

0

FMCR0

R/W

Initial value : 00H

Flash Mode Busy Bit. This bit will be used for only debugger.

0 No effect when “1” is written

1 Busy

Flash Mode Control Bits. During a flash mode operation, the CPU is hold and the global interrupt is on disable state regardless of the IE.7

(EA) bit.

FMCR2 FMCR1 FMCR0 Description

0

0

0

1

1

0

Select flash page buffer reset mode and start regardless of the FIDR

value (Clear all 64bytes to

„0‟)

Select flash sector erase mode and start operation when the

FIDR=

”10100101b‟

0 1 1 Select flash sector write mode and start operation when the

FIDR= ”10100101b‟

1 0 0 Select flash sector hard lock and start operation when the

FIDR=

”10100101b‟

Others Values: No operation

(These bits are automatically cleared to logic

„00H‟ immediately after one time operation)

April 20, 2012 Ver. 2.5 235

MC96F7816/C7816

16.1.6 Serial In-System Program (ISP) Mode

Serial in-system program uses the interface of debugger which uses two wires. Refer to chapter 14 in details about debugger

16.1.7 Protection Area (User program mode)

MC96F7816 can program its own flash memory (protection area). The protection area can not be erased or programmed. The protection areas are available only when the PAEN bit is cleared to

„0‟, that is, enable protection area at the configure option 1 if it is needed. If the protection area isn ‟t enabled (PAEN =‟1‟), this area can be used as a normal program memory.

The size of protection area can be varied by setting of configure option 1.

Table 16-2 Protection Area size

Address of Protection Area Protection Area Size Select

PASS1 PASS0

0

0

1

1

0

1

0

1

Size of Protection Area

3.8K Bytes

1.7K Bytes

768 Bytes

256 Bytes

Note) Refer to chapter 16 in configure option control.

0100H

– 0FFFH

0100H

– 07FFH

0100H – 03FFH

0100H

– 01FFH

236 April 20, 2012 Ver. 2.5

16.1.8 Erase Mode

MC96F7816/C7816

The sector erase program procedure in user program mode

1. Page buffer clear (FMCR=0x01)

2. Write „0‟ to page buffer

3. Set flash sector address register (FSADRH/FSADRM/FSADRL).

4. Set flash identification register (FIDR).

5. Set flash mode control register (FMCR).

6. Erase verify

Program Tip – sector erase

MOV FMCR,#0x01

NOP

NOP

NOP

MOV A,#0

MOV R0,#64

MOV DPH,#0x80

MOV DPL,#0

Pgbuf_clr: MOVX @DPTR,A

INC DPTR

DJNZ R0, Pgbuf_clr

;page buffer clear

;Dummy Instruction, This instruction must be needed



;Sector size is 64bytes

;Write ‘0’ to all page buffer

MOV FSADRH,#0x00

MOV FSADRM,#0x7F

MOV FSADRL,#0x40

MOV FIDR,#0xA5

MOV FMCR,#0x02

NOP

NOP

NOP

MOV A,#0

MOV R0,#64

MOV R1,#0

Erase_verify:

MOV DPH,#0x7F

MOV DPL,#0x40

Verify_error:

MOVC A,@A+DPTR

SUBB A,R1

JNZ

INC

Verify_error

DPTR

DJNZ R0, Erase_verify

;Select sector 509

;Identification value

;Start flash erase mode




;erase verify


April 20, 2012 Ver. 2.5 237

MC96F7816/C7816

The Byte erase program procedure in user program mode


2. Write „0‟ to page buffer




6. Erase verify

Program Tip – byte erase

MOV FMCR,#0x01

NOP

NOP

NOP

MOV A,#0

MOV DPH,#0x80

MOV DPL,#0

MOVX @DPTR,A

MOV DPH,#0x80

MOV DPL,#0x05

MOVX @DPTR,A

;page buffer clear




;Write ‘0’ to page buffer

MOV FSADRH,#0x00

MOV FSADRM,#0x7F

MOV FSADRL,#0x40

MOV FIDR,#0xA5

MOV FMCR,#0x02

NOP

NOP

NOP

MOV A,#0

MOV R1,#0

MOV DPH,#0x7F

MOV

JNZ

DPL,#0x40

MOVC A,@A+DPTR

SUBB A,R1

Verify_error

MOV A,#0

MOV

MOV

MOV

R1,#0

DPH,#0x7F

DPL,#0x45

MOVC A,@A+DPTR

Verify_error:

SUBB A,R1

JNZ Verify_error

;Select sector 509


;Start flash erase mode




;erase verify

;0x7F40 = 0 ?

;0x7F45 = 0 ?

238 April 20, 2012 Ver. 2.5

16.1.9 Write Mode

MC96F7816/C7816

The sector Write program procedure in user program mode


2. Write data to page buffer




6. Erase verify

Program Tip – sector write

MOV FMCR,#0x01

NOP

NOP

NOP

MOV A,#0

MOV R0,#64

MOV DPH,#0x80

MOV DPL,#0

Pgbuf_WR: MOVX @DPTR,A

INC A

INC DPTR

DJNZ R0, Pgbuf_WR

;page buffer clear





;Write data to all page buffer

MOV FSADRH,#0x00

MOV FSADRM,#0x7F

MOV FSADRL,#0x40

MOV FIDR,#0xA5

MOV FMCR,#0x03

NOP

NOP

NOP

MOV

MOV

MOV

A,#0

MOV R0,#64

MOV R1,#0

DPH,#0x7F

DPL,#0x40

Write_verify:

MOVC A,@A+DPTR

SUBB A,R1

Verify_error:

JNZ

INC

INC

Verify_error

R1

DPTR

DJNZ R0, Write_verify

;Select sector 509


;Start flash write mode




;write verify


April 20, 2012 Ver. 2.5 239

MC96F7816/C7816

The Byte Write program procedure in user program mode


2. Write data to page buffer




6. Erase verify

Program Tip – byte write

MOV FMCR,#0x01

NOP

NOP

NOP

MOV A,#5

MOV DPH,#0x80

MOV DPL,#0

MOVX @DPTR,A

MOV A,#6

MOV DPH,#0x80

MOV DPL,#0x05

MOVX @DPTR,A

;page buffer clear




;Write data to page buffer

;Write data to page buffer

MOV FSADRH,#0x00

MOV FSADRM,#0x7F

MOV FSADRL,#0x40

MOV FIDR,#0xA5

MOV FMCR,#0x03

NOP

NOP

NOP

MOV

MOV

MOV

MOV

SUBB

JNZ

A,#0

R1,#5

A,R1

DPH,#0x7F

DPL,#0x40

MOVC A,@A+DPTR

Verify_error

Verify_error:

MOV A,#0

MOV R1,#6

MOV DPH,#0x7F

MOV DPL,#0x45

MOVC A,@A+DPTR

SUBB A,R1

JNZ Verify_error

;Select sector 509


;Start flash write mode




;write verify

;0x7F40 = 5 ?

;0x7F45 = 6 ?

240 April 20, 2012 Ver. 2.5

16.1.10 Read Mode

MC96F7816/C7816

The Reading program procedure in user program mode

1. Load receive data from flash memory on MOVC instruction by indirectly addressing mode.

Program Tip – reading

MOV A,#0

MOV DPH,#0x7F

MOV DPL,#0x40

MOVC A,@A+DPTR

;flash memory address

;read data from flash memory

16.1.11 Hard Lock Mode

The Reading program procedure in user program mode



Program Tip – reading

MOV FIDR,#0xA5

MOV FMCR,#0x04

NOP

NOP

NOP


;Start flash hard lock mode




April 20, 2012 Ver. 2.5 241

MC96F7816/C7816

17. Configure Option

17.1 Configure Option Control Register

The data for configure option should be written in the configure option area (003EH – 003FH) by programmer

(Writer tools).

CONFIGURE OPTION 1 : ROM Address 003FH

7

R_P

6

HL

5

-

4

-

3

-

2

-

1

-

0

RSTS

Initial value : 00H

R_P

HL

RSTS

Read Protection

0 Disable

“Read protection”

1 Enable

“Read protection”

Hard-Lock

0 Disable

“Hard-lock”

1 Enable “Hard-lock”

RESETB Select

0 P92/EC0 port

1 RESETB port with a pull-up resistor

CONFIGURE OPTION 2 : ROM Address 003EH

7

-

6

-

5

-

4

-

3

-

2

PAEN

PAEN

PASS [1:0]

1

PASS1

0

PASS0

Initial value : 00H

Protection Area Enable/Disable

0 Disable Protection (Erasable by instruction)

1 Enable Protection (Not erasable by instruction)

Protection Area Size Select

PASS1 PASS0 Description

0

0

0

1

3.8K bytes (Address 0100H – 0FFFH)

1.7K bytes (Address 0100H

– 07FFH)

1

1

0

1

768 bytes (Address 0100H – 03FFH)

256 bytes (Address 0100H

– 01FFH)

242 April 20, 2012 Ver. 2.5

MC96F7816/C7816

18. APPENDIX

A. Instruction Table

Instructions are either 1, 2 or 3 bytes long as listed in the „Bytes‟ column below.

Each instruction takes either 1, 2 or 4 machine cycles to execute as listed in the following table. 1 machine cycle comprises 2 system clock cycles.

Mnemonic

ARITHMETIC

Description Hex code

ADD A,Rn

ADD A,dir

ADD A,@Ri

Add register to A

Add direct byte to A

Add indirect memory to A

Bytes

1

2

1

Cycles

1

1

1

28-2F

25

26-27

ADD A,#data

ADDC A,Rn

ADDC A,dir

ADDC A,@Ri

ADDC A,#data

SUBB A,Rn

SUBB A,dir

SUBB A,@Ri

SUBB A,#data

INC A

INC Rn

INC dir

INC @Ri

DEC A

DEC Rn

DEC dir

DEC @Ri

INC DPTR

MUL AB

DIV AB

DA A

Add immediate to A

Add register to A with carry

Add direct byte to A with carry

Add indirect memory to A with carry

Add immediate to A with carry

Subtract register from A with borrow

Subtract direct byte from A with borrow

Subtract indirect memory from A with borrow

Subtract immediate from A with borrow

Increment A

Increment register

Increment direct byte

Increment indirect memory

Decrement A

Decrement register

Decrement direct byte

Decrement indirect memory

Increment data pointer

Multiply A by B

Divide A by B

Decimal Adjust A

1

1

1

1

2

4

4

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

2

1

1

1

1

1

1

2

1

1

2

1

2

1

2

2

1

2

1

14

18-1F

15

16-17

A3

A4

84

D4

24

38-3F

35

36-37

34

98-9F

95

96-97

94

04

08-0F

05

06-07

Mnemonic

LOGICAL

Description Hex code

ANL A,Rn

ANL A,dir

ANL A,@Ri

ANL A,#data

ANL dir,A

ANL dir,#data

ORL A,Rn

ORL A,dir

ORL A,@Ri

ORL A,#data

ORL dir,A

ORL dir,#data

XRL A,Rn

XRL A,dir

AND register to A

AND direct byte to A

AND indirect memory to A

AND immediate to A

AND A to direct byte

AND immediate to direct byte

OR register to A

OR direct byte to A

OR indirect memory to A

OR immediate to A

OR A to direct byte

OR immediate to direct byte

Exclusive-OR register to A

Exclusive-OR direct byte to A

Bytes

1

3

1

2

2

1

2

2

1

2

2

3

1

2

Cycles

1

2

1

1

1

1

1

1

1

1

1

2

1

1

58-5F

55

56-57

54

52

53

48-4F

45

46-47

44

42

43

68-6F

65

April 20, 2012 Ver. 2.5 243

MC96F7816/C7816

XRL A, @Ri

XRL A,#data

XRL dir,A

XRL dir,#data

CLR A

CPL A

SWAP A

RL A

RLC A

RR A

RRC A

Exclusive-OR indirect memory to A

Exclusive-OR immediate to A

Exclusive-OR A to direct byte

Exclusive-OR immediate to direct byte

Clear A

Complement A

Swap Nibbles of A

Rotate A left

Rotate A left through carry

Rotate A right

Rotate A right through carry

Mnemonic

MOV A,Rn

MOV A,dir

MOV A,@Ri

MOV A,#data

MOV Rn,A

MOV Rn,dir

MOV Rn,#data

MOV dir,A

MOV dir,Rn

MOV dir,dir

MOV dir,@Ri

MOV dir,#data

MOV @Ri,A

MOV @Ri,dir

MOV @Ri,#data

MOV DPTR,#data

MOVC A,@A+DPTR

MOVC A,@A+PC

MOVX A,@Ri

MOVX A,@DPTR

MOVX @Ri,A

MOVX @DPTR,A

PUSH dir

POP dir

XCH A,Rn

XCH A,dir

XCH A,@Ri

XCHD A,@Ri

Mnemonic

CLR C

CLR bit

SETB C

SETB bit

CPL C

CPL bit

Description

Move register to A

DATA TRANSFER

Move direct byte to A

Move indirect memory to A

Move immediate to A

Move A to register

Move direct byte to register

Move immediate to register

Move A to direct byte

Move register to direct byte

Move direct byte to direct byte

Move indirect memory to direct byte

Move immediate to direct byte

Move A to indirect memory

Move direct byte to indirect memory

Move immediate to indirect memory

Move immediate to data pointer

Move code byte relative DPTR to A

Move code byte relative PC to A

Move external data(A8) to A

Move external data(A16) to A

Move A to external data(A8)

Move A to external data(A16)

Push direct byte onto stack

Pop direct byte from stack

Exchange A and register

Exchange A and direct byte

Exchange A and indirect memory

Exchange A and indirect memory nibble

BOOLEAN

Description

Clear carry

Clear direct bit

Set carry

Set direct bit

Complement carry

Complement direct bit

244

1

2

2

3

1

1

1

1

1

1

1

1

1

1

2

1

1

1

1

1

1

1

1

1

1

1

2

2

1

2

1

1

2

3

1

1

2

3

1

2

1

2

2

2

2

3

Bytes Cycles

1 1

2

1

2

1

1

1

1

2

1

1

2

2

2

2

2

2

2

2

1

1

1

1

1

2

2

2

2

2

1

2

86-87

75

F6-F7

A6-A7

76-77

90

93

83

E2-E3

E0

F2-F3

F0

C0

D0

C8-CF

C5

C6-C7

D6-D7

Hex code

E8-EF

E5

E6-E7

74

F8-FF

A8-AF

78-7F

F5

88-8F

85

Bytes

1

2

1

2

1

2

Cycles

1

1

1

1

1

1

Hex code

C3

C2

D3

D2

B3

B2

April 20, 2012 Ver. 2.5

66-67

64

62

63

E4

F4

C4

23

33

03

13

MC96F7816/C7816

ANL C,bit

ANL C,/bit

ORL C,bit

ORL C,/bit

MOV C,bit

MOV bit,C

AND direct bit to carry

AND direct bit inverse to carry

OR direct bit to carry

OR direct bit inverse to carry

Move direct bit to carry

Move carry to direct bit

2

2

2

2

2

2

2

2

2

2

1

2

82

B0

72

A0

A2

92

Mnemonic

BRANCHING

Description

ACALL addr 11

LCALL addr 16

RET

RETI

AJMP addr 11

LJMP addr 16

SJMP rel

JC rel

JNC rel

Absolute jump to subroutine

Long jump to subroutine

Return from subroutine

Return from interrupt

Absolute jump unconditional

Long jump unconditional

Short jump (relative address)

Jump on carry = 1

Jump on carry = 0

JB bit,rel

JNB bit,rel

JZ rel

JNZ rel

Jump on direct bit = 1

Jump on direct bit = 0

JBC bit,rel Jump on direct bit = 1 and clear

JMP @A+DPTR Jump indirect relative DPTR

Jump on accumulator = 0

Jump on accumulator ≠ 0

CJNE A,dir,rel

CJNE A,#d,rel

Compare A,direct jne relative

Compare A,immediate jne relative

CJNE Rn,#d,rel Compare register, immediate jne relative

CJNE @Ri,#d,rel Compare indirect, immediate jne relative

DJNZ Rn,rel

DJNZ dir,rel

Decrement register, jnz relative

Decrement direct byte, jnz relative

MISCELLANEOUS

Bytes

2

3

1

1

2

3

2

2

2

3

3

3

1

2

2

3

3

3

3

3

3

Cycles

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

Mnemonic

NOP No operation

Description Bytes

1

Cycles

1

Hex code

00

Mnemonic

ADDITIONAL INSTRUCTIONS (selected through EO[7:4])

Description Bytes Cycles Hex code

MOVC @(DPTR++),A

TRAP

M8051W/M8051EW-specific instruction supporting software download into program memory

Software break command

1

1

2

1

A5

A5

In the above table, an entry such as E8-EF indicates a continuous block of hex opcodes used for 8 different registers, the register numbers of which are defined by the lowest three bits of the corresponding code. Noncontinuous blocks of codes, shown as 11

→F1 (for example), are used for absolute jumps and calls, with the top 3 bits of the code being used to store the top three bits of the destination address.

The CJNE instructions use the abbreviation #d for immediate data; other instructions use #data.

B5

B4

B8-BF

B6-B7

D8-DF

D5

20

30

10

73

60

70

Hex code

11 →F1

12

22

32

01

→E1

02

80

40

50

April 20, 2012 Ver. 2.5 245

MC96F7816/C7816

B. Mask Order Sheet (MC96C7816)

MASK ORDER & VERIFICATION SHEET

MC96C7816-LF

Customer should write inside thick line box.

1. Customer Information 2. Device Information

Q:MQFP

L:LQFP

Company Name Package

□ 80MQFP □ 80LQFP

Application

Order Date

Tel:

E-mail:

Name &

Signature:

YYYY

Fax:

MM

• •

DD

3. Marking Specification

Q or L

Q:MQFP

L:LQFP

C7816-LF

YYWW

ROM Code Number

Work Week

ROM Size

□ 16K

Unused ROM

□ 00H

RESETB Use

□ Yes

□ FFH

□ No

Mask Data File Name: ( .OTP)

Check Sum: ( )

3FFFH

.OTP file data

Customer’s logo

0000H

YYWW

Customer logo is not required.

If the customer logo must be used in the special mark, please submit a clean original of the logo.

Customer’s part number

(Please check mark into □ )

4. Delivery Schedule

Customer Sample

YYYY

Date

MM

• •

DD

• • Risk Order

5. ROM Code Verification

Verification Date: • •

Check Sum:

E-mail:

Quantity pcs pcs

Tel:

Name &

Signature:

246

ABOV Confirmation

Fax:

April 20, 2012 Ver. 2.5

MC96F7816/C7816

C. Instructions on how to use the input port.



Error occur status

 Using compare jump instructions with input port, it could cause error due to the timing conflict inside the

MCU.

 Compare jump Instructions which cause potential error used with input port condition:

JB bit, rel ; jump on direct bit=1

JNB bit, rel ; jump on direct bit=0

JBC bit, rel ; jump on direct bit=1 and clear

CJNE A, dir, rel ; compare A, direct jne relative

DJNZ dir, rel ; decrement direct byte, jnz relative

 It is only related with Input port. Internal parameters, SFRs and output bit ports don ‟t cause any error by using compare jump instructions.

 If input signal is fixed, there is no error in using compare jump instructions.

 Error status example while(1){

if (P00==1){ P10=1; }

else { P10=0; } zzz: JNB 080.0, xxx ; it possible to be error

SETB 088.0

SJMP yyy

P11^=1;

} xxx: CLR 088.0 yyy: MOV C,088.1

CPL C

MOV 088.1,C

SJMP zzz unsigned char ret_bit_err(void) MOV R7, #000

{

return !P00;

JB 080.0, xxx ; it possible to be error

MOV R7, #001

} xxx: RET

 Preventative measures (2 cases)

 Do not use input bit port for bit operation but for byte operation. Using byte operation instead of bit oper ation will not cause any error in using compare jump instructions for input port. while(1){

if ((P0&0x01)==0x01){ P10=1; }

} else { P10=0; }

P11^=1; zzz: MOV A, 080 ; read as byte

JNB 0E0.0, xxx ; compare

SETB 088.0

SJMP yyy xxx: CLR 088.0 yyy: MOV C,088.1

CPL C

MOV 088.1,C

SJMP zzz

April 20, 2012 Ver. 2.5 247

MC96F7816/C7816



If you use input bit port for compare jump instruction, you have to copy the input port as internal paramet er or carry bit and then use compare jump instruction. bit tt; while(1){

tt=P00;

if (tt==0){ P10=1;}

else {P10=0;}

P11^=1;

} zzz: MOV C,080.0 ; input port use internal parameter

MOV 020.0, C ; move

JB 020.0, xxx ; compare

SETB 088.0

SJMP yyy xxx: CLR 088.0 yyy: MOV C,088.1

CPL C

MOV 088.1,C

SJMP zzz

248 April 20, 2012 Ver. 2.5

ABOV MC96F7816, MC96C7816 microcontroller User’s Manual

Assistant Bot

ABOV SEMICONDUCTOR Co., Ltd.

8-BIT MICROCONTROLLERS

User’s Manual (Ver. 2.5)

REVISION HISTORY

Table of Contents

List of Figures

List of Tables

MC96F7816/C7816

CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

WITH 12-BIT A/D CONVERTER

MC96F7816L

(80LQFP-1212)

Key Features

Frequently Answers and Questions

What is the main difference between MC96F7816 and MC96C7816?

What is the difference between STOP and IDLE mode?

How many I/O ports does the microcontroller have?

What is the maximum operating frequency of this microcontroller?

Related manuals

Table of contents

ABOV MC96F7816, MC96C7816 microcontroller User’s Manual

Assistant Bot

ABOV SEMICONDUCTOR Co., Ltd.

8-BIT MICROCONTROLLERS

User’s Manual (Ver. 2.5)

REVISION HISTORY

Table of Contents

List of Figures

List of Tables

MC96F7816/C7816

CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

WITH 12-BIT A/D CONVERTER

MC96F7816L

(80LQFP-1212)

Key Features

Frequently Answers and Questions

What is the main difference between MC96F7816 and MC96C7816?

What is the difference between STOP and IDLE mode?

How many I/O ports does the microcontroller have?

What is the maximum operating frequency of this microcontroller?

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Table of contents