NXP P89LPC9331, P89LPC9341, P89LPC9351 Microcontroller User manual

UM10308

P89LPC9331/9341/9351 User manual

Rev. 02 — 5 May 2009 User manual

Document information

Info

Keywords

Abstract

Content

P89LPC9331/9341/9351

Technical information for the P89LPC9331/9341/9351 device

NXP Semiconductors

UM10308

P89LPC9331/9341/9351 User manual

Revision history

Rev Date

02 20090505

01 20081118

Description

Added information for P89LPC9331 and P89LPC9341 devices.

Initial version.

Contact information

For more information, please visit:

http://www.nxp.com

For sales office addresses, please send an email to:

[email protected]

UM10308_2

User manual Rev. 02 — 5 May 2009

© NXP B.V. 2009. All rights reserved.

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UM10308

P89LPC9331/9341/9351 User manual

1.

Introduction

The P89LPC9331/9341/9351 are single-chip microcontrollers designed for applications demanding high-integration, low cost solutions over a wide range of performance requirements. The P89LPC9331/9341/9351 are based on a high performance processor architecture that executes instructions in two to four clocks, six times the rate of standard

80C51 devices. Many system-level functions have been incorporated into the

P89LPC9331/9341/9351 in order to reduce component count, board space, and system cost.

Table 1.

Product comparison overview

Device Flash

Memory

Sector size

ADC1

P89LPC9331 4 kB

P89LPC9341 4 kB

P89LPC9351 8 kB

1 kB

1 kB

1 kB

X

X

X

ADC0

X

X

X

PGA0

-

-

X

PGA1

-

-

X

Temp

Sensor

X

X

X

CCU

-

-

X

-

-

DATA

EEPROM

X

Product Comparison Overview

1.1 Pin configuration

P2.0/AD03/DAC0

P2.1/AD02

P0.0/CMP2/KBI0/AD01

P1.7/AD00

P1.6

P1.5/RST

V

SS

P3.1/XTAL1

P3.0/XTAL2/CLKOUT

P1.4/INT1

P1.3/INT0/SDA

P1.2/T0/SCL

P2.2/MOSI

P2.3/MISO

9

10

11

12

13

14

7

8

5

6

3

4

1

2

P89LPC9331FDH/

P89LPC9341FDH

002aae462

28

27

P2.7

P2.6

26

25

P0.1/CIN2B/KBI1/AD10

P0.2/CIN2A/KBI2/AD11

24

23


P0.4/CIN1A/KBI4/DAC1/AD13

22

21

P0.5/CMPREF/KBI5

V

DD

P0.6/CMP1/KBI6

20

19

18

17

16

15

P0.7/T1/KBI7

P1.0/TXD

P1.1/RXD

P2.5/SPICLK

P2.4/SS

Fig 1.

P89LPC9331/9341 TSSOP28 pin configuration

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P89LPC9331/9341/9351 User manual

P2.0/ICB/DAC0/AD03

P2.1/OCD/AD02

P0.0/CMP2/KBI0/AD01

P1.7/OCC/AD00

P1.6/OCB

P1.5/RST

V

SS

P3.1/XTAL1

P3.0/XTAL2/CLKOUT

P1.4/INT1

P1.3/INT0/SDA

P1.2/T0/SCL

P2.2/MOSI

P2.3/MISO

9

10

11

12

13

14

7

8

5

6

3

4

1

2

P89LPC9351FDH

002aad557

Fig 2.

P89LPC9351 TSSOP28 pin configuration

28

27

P2.7/ICA

P2.6/OCA

26

25

24

23





22

21

P0.5/CMPREF/KBI5

V

DD

P0.6/CMP1/KBI6 20

19

18

17

16

15

P0.7/T1/KBI7

P1.0/TXD

P1.1/RXD

P2.5/SPICLK

P2.4/SS

P1.6/OCB

P1.5/RST

V

SS

P3.1/XTAL1

7

8

5

6

P3.0/XTAL2/CLKOUT

P1.4/INT1

9

10

P1.3/INT0/SDA 11

P89LPC9351FA

25

24

23

22




P0.5/CMPREF/KBI5

21

20

V

DD

P0.6/CMP1/KBI6

19 P0.7/T1/KBI7

002aad558

Fig 3.

PLCC28 pin configuration

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P89LPC9331/9341/9351 User manual

1.2 Pin description

Table 2.

Pin description

Symbol Pin

PLCC28,

TSSOP28

P0.0 to P0.7

Type Description

I/O

P0.0/CMP2/

KBI0/AD01

P0.1/CIN2B/

KBI1/AD10

P0.2/CIN2A/

KBI2/AD11

P0.3/CIN1B/

KBI3/AD12

P0.4/CIN1A/

KBI4/DAC1/AD13

P0.5/CMPREF/

KBI5

P0.6/CMP1/KBI6

P0.7/T1/KBI7

3

26

25

24

23

22

20

19

I/O

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

O

I/O

I/O

I/O

I/O

O

I/O

I/O

O

I/O

I/O

Port 0: Port 0 is an 8-bit I/O port with a user-configurable output type. During reset

Port 0 latches are configured in the input only mode with the internal pull-up disabled. The operation of Port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is configured independently. Refer to

Section 5.1 “Port configurations” for details.

The Keypad Interrupt feature operates with Port 0 pins.

All pins have Schmitt trigger inputs.

Port 0 also provides various special functions as described below:

P0.0 — Port 0 bit 0.

CMP2 — Comparator 2 output

KBI0 — Keyboard input 0.

AD01 — ADC0 channel 1 analog input.

P0.1 — Port 0 bit 1.

CIN2B — Comparator 2 positive input B.



P0.2 — Port 0 bit 2.

CIN2A — Comparator 2 positive input A.



P0.3 — Port 0 bit 3. High current source.

CIN1B — Comparator 1 positive input B.




CIN1A — Comparator 1 positive input A.


DAC1 — Digital-to-analog converter output 1.



CMPREF — Comparator reference (negative) input.



CMP1 — Comparator 1 output.



T1 — Timer/counter 1 external count input or overflow output.


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P89LPC9331/9341/9351 User manual

Table 2.

Pin description

…continued

Symbol Pin

PLCC28,

TSSOP28

Type Description

P1.0 to P1.7

I/O, I

[1]

Port 1: Port 1 is an 8-bit I/O port with a user-configurable output type, except for three pins as noted below. During reset Port 1 latches are configured in the input only mode with the internal pull-up disabled. The operation of the configurable

Port 1 pins as inputs and outputs depends upon the port configuration selected.

Each of the configurable port pins are programmed independently. Refer to

Section 5.1 “Port configurations” for details. P1.2 to P1.3 are open drain when

used as outputs. P1.5 is input only.



P1.0/TXD 18

P1.1/RXD 17

I/O

O

I/O

I

P1.0 — Port 1 bit 0.

TXD — Transmitter output for serial port.

P1.1 — Port 1 bit 1.

RXD — Receiver input for serial port.

P1.2/T0/SCL

P1.3/INT0/SDA

P1.4/INT1

12

11

10

I/O

I/O

P1.2 — Port 1 bit 2 (open-drain when used as output).

T0 — Timer/counter 0 external count input or overflow output (open-drain when used as output).

SCL — I

2

C-bus serial clock input/output.

P1.3 — Port 1 bit 3 (open-drain when used as output).

INT0 — External interrupt 0 input.

SDA — I

2

C-bus serial data input/output.


P1.5/RST 6 I

I

I/O

I/O

I

I/O

I/O

I

P1.6/OCB

P1.7/OCC/AD00

P2.0 to P2.7

5

4

I

I/O

O

I/O

O

I/O

INT1 — External interrupt 1 input.

P1.5 — Port 1 bit 5 (input only).

RST — External Reset input during power-on or if selected via UCFG1. When functioning as a reset input, a LOW on this pin resets the microcontroller, causing

I/O ports and peripherals to take on their default states, and the processor begins execution at address 0. Also used during a power-on sequence to force ISP mode.


OCB — Output Compare B.(P89LPC9351)


OCC — Output Compare C.(P89LPC9351)


Port 2: Port 2 is an 8-bit I/O port with a user-configurable output type. During reset





P2.0/ICB/DAC0

/AD03

1 I/O

I

I

O

P2.0 — Port 2 bit 0.

ICB — Input Capture B.(P89LPC9351)

DAC0 — Digital-to-analog converter output.


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Table 2.

Pin description

…continued

Symbol

P2.1/OCD/AD02

Pin

PLCC28,

TSSOP28

2

Type

I/O

Description

P2.1 — Port 2 bit 1.

P2.2/MOSI

P2.3/MISO

13

14

I

O

I/O

I/O

I/O

I/O

OCD — Output Compare D.(P89LPC9351)


P2.2 — Port 2 bit 2.

MOSI — SPI master out slave in. When configured as master, this pin is output; when configured as slave, this pin is input.

P2.3 — Port 2 bit 3.

P2.4/SS

P2.5/SPICLK

15

16

I

I/O

I/O

I/O

MISO — When configured as master, this pin is input, when configured as slave, this pin is output.

P2.4 — Port 2 bit 4.

SS — SPI Slave select.

P2.6/OCA

P2.7/ICA

27

28

I/O

O

I/O

P2.5 — Port 2 bit 5.

SPICLK — SPI clock. When configured as master, this pin is output; when configured as slave, this pin is input.

P2.6 — Port 2 bit 6.

OCA — Output Compare A.(P89LPC9351)

P2.7 — Port 2 bit 7.

P3.0 to P3.1

I

I/O

P3.0/XTAL2/

CLKOUT

P3.1/XTAL1

V

V

SS

DD

9

8

7

21

I

I/O

I

I

O

O

I/O

ICA — Input Capture A.(P89LPC9351)

Port 3: Port 3 is a 2-bit I/O port with a user-configurable output type. During reset





P3.0 — Port 3 bit 0.

XTAL2 — Output from the oscillator amplifier (when a crystal oscillator option is selected via the flash configuration.

CLKOUT — CPU clock divided by 2 when enabled via SFR bit (ENCLK -TRIM.6).

It can be used if the CPU clock is the internal RC oscillator, watchdog oscillator or external clock input, except when XTAL1/XTAL2 are used to generate clock source for the RTC/system timer.

P3.1 — Port 3 bit 1.

XTAL1 — Input to the oscillator circuit and internal clock generator circuits (when selected via the flash configuration). It can be a port pin if internal RC oscillator or watchdog oscillator is used as the CPU clock source, and if XTAL1/XTAL2 are not used to generate the clock for the RTC/system timer.

Ground: 0 V reference.

Power supply: This is the power supply voltage for normal operation as well as

Idle and Power-down modes.

[1] Input/output for P1.0 to P1.4, P1.6, P1.7. Input for P1.5.

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1.3 Logic symbols

DAC1

AD01

AD10

AD11

AD12

AD13

KBI0

KBI1

KBI2

KBI3

KBI4

KBI5

KBI6

KBI7

CLKOUT

CMP2

CIN2B

CIN2A

CIN1B

CIN1A

CMPREF

CMP1

T1

XTAL2

XTAL1

PORT 0

PORT 3

V

DD

V

SS

P89LPC9331/

P89LPC9341

PORT 1

PORT 2

TXD

RXD

T0

INT0

INT1

RST

AD00

SCL

SDA

AD03

AD02

MOSI

MISO

SS

SPICLK

DAC0

002aae461

Fig 4.

P89LPC9331/9341 logic symbol

DAC1

AD01

AD10

AD11

AD12

AD13

KBI0

KBI1

KBI2

KBI3

KBI4

KBI5

KBI6

KBI7

CLKOUT

CMP2

CIN2B

CIN2A

CIN1B

CIN1A

CMPREF

CMP1

T1

XTAL2

XTAL1

PORT 0

PORT 3

V

DD

V

SS

P89LPC9351

002aad556

PORT 1

PORT 2

TXD

RXD

T0

INT0

INT1

RST

OCB

OCC

ICB

OCD

MOSI

MISO

SS

SPICLK

OCA

ICA

SCL

SDA

AD00

AD03

AD02

DAC0

Fig 5.

P89LPC9351 logic symbol

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P89LPC9331/9341/9351 User manual

P3[1:0]

P2[7:0]

P1[7:0]

P0[7:0]

1.4 Block diagram

P89LPC9331/9341/9351

ACCELERATED 2-CLOCK 80C51 CPU

CRYSTAL

OR

RESONATOR

XTAL1

XTAL2

4 kB/8 kB

CODE FLASH

256-BYTE

DATA RAM

512-BYTE

AUXILIARY RAM

(1) internal bus

512-BYTE

DATA EEPROM

(1)

PORT 3

CONFIGURABLE I/Os

PORT 2

CONFIGURABLE I/Os

PORT 1

CONFIGURABLE I/Os

PORT 0

CONFIGURABLE I/Os

KEYPAD

INTERRUPT

WATCHDOG TIMER

AND OSCILLATOR

PROGRAMMABLE

OSCILLATOR DIVIDER

CPU clock

CONFIGURABLE

OSCILLATOR

ON-CHIP RC

OSCILLATOR

WITH CLOCK

DOUBLER

UART

I

2

C-BUS

SPI

REAL-TIME CLOCK/

SYSTEM TIMER

TIMER 0

TIMER 1

ANALOG

COMPARATORS

CCU (CAPTURE/

COMPARE UNIT)

(1)

ADC1/DAC1

(2)

ADC0/TEMP

SENSOR/DAC0

(3)

POWER MONITOR

(POWER-ON RESET,

BROWNOUT RESET)

002aad555

(1) P89LPC9351

(2) PGA1 on P89LPC9351

(3) PGA0 on P89LPC9351

Fig 6.

Block diagram

T0

T1

CMP2

CIN2B

CIN2A

CMP1

CIN1A

CIN1B

OCA

OCB

OCC

OCD

ICA

ICB

AD10

AD11

AD12

AD13

DAC1

AD00

AD01

AD02

AD03

DAC0

TXD

RXD

SCL

SDA

SPICLK

MOSI

MISO

SS

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1.5 Special function registers

Remark: SFR accesses are restricted in the following ways:

•

User must not attempt to access any SFR locations not defined.

•

Accesses to any defined SFR locations must be strictly for the functions for the SFRs.

•

SFR bits labeled ‘-’, ‘0’ or ‘1’ can only be written and read as follows:

– ‘-’ Unless otherwise specified, must be written with ‘0’, but can return any value when read (even if it was written with ‘0’). It is a reserved bit and may be used in future derivatives.

– ‘0’ must be written with ‘0’, and will return a ‘0’ when read.

– ‘1’ must be written with ‘1’, and will return a ‘1’ when read.

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Table 3.

Special function registers - P89LPC9331/9341

* indicates SFRs that are bit addressable.

Name Description SFR addr.

Bit address

Bit functions and addresses

MSB

E7 E6 E5 E4 E3 E2 E1

LSB

E0

Reset value

Hex Binary

E0H

8EH ENBI0 ENADCI0 TMM0 EDGE0 ADCI0

00

ENADC0 ADCS01 ADCS00 00

0000 0000

0000 0000

ACC*

ADCON0

ADCON1

ADINS

Accumulator

A/D control register 0

A/D control register 1

A/D input select

ADMODA A/D mode register A

ADMODB A/D mode register B

AD0BH A/D_0 boundary high register

AD0BL A/D_0 boundary low register

AD0DAT0 A/D_0 data register 0







97H

A3H

C0H

A1H

BBH

A6H

C5H

C6H

C7H

F4H

C4H

BCH

D5H

ENBI1

ADI13

BNDI1

CLK2

ENADCI1

ADI12

BURST1

CLK1

TMM1

ADI11

SCC1

CLK0

EDGE1

ADI10

SCAN1

INBND0

ADCI1

ADI03

BNDI0


ADI02

BURST0

ENDAC1 ENDAC0

ADI01

SCC0

BSA1

ADI00 00

SCAN0 00

BSA0 00

FF

00

00

00

00

00

FF

00

00

0000 0000

0000 0000

0000 0000

000x 0000

1111 1111

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

1111 1111

0000 0000

0000 0000


Table 3.


…continued



D6H


MSB LSB

Reset value

Hex

00

Binary

0000 0000 AD1DAT1 A/D_1 data register 1



AUXR1 Auxiliary function register

D7H

F5H

A2H CLKLP EBRR ENT1 ENT0 SRST 0 DPS

00

00

00

0000 0000

0000 0000

0000 00x0

F7 F6 F5 F4 F3 F2 F1 F0

B*

BRGR0

BRGR1

[2]

[2]

B register

Bit address

F0H

BEH Baud rate generator 0 rate low

Baud rate generator 0 rate high

BFH

BDH BRGCON Baud rate generator 0 control

CMP1

CMP2

Comparator 1 control register


DIVM CPU clock divide-by-M control

DPTR

DPH

Data pointer

(2 bytes)

Data pointer high

ACH

ADH

95H

83H

DPL Data pointer low

82H

-

-

-

-

-

-

CE1

CE2

-

CP1

CP2

-

CN1

CN2

-

OE1

OE2

SBRGS

CO1

CO2

00

00

00

BRGEN

00

[2]

CMF1

00

[1]

CMF2

00

[1]

00

00

00

0000 0000

0000 0000

0000 0000 xxxx xx00 xx00 0000 xx00 0000

0000 0000

0000 0000

0000 0000


Table 3.


…continued


Name

FMADRH

Description SFR addr.

E7H


MSB LSB

Reset value

Hex

00

Binary

0000 0000

FMADRL

FMCON

FMDATA

I2ADR

Program flash address high

Program flash address low

Program flash control (Read)

Program flash control (Write)

Program flash data

I

2

C-bus slave address register

E6H

E4H

E5H

BUSY

DBH I2ADR.6

-

I2ADR.5

-

I2ADR.4

-

I2ADR.3

HVA

I2ADR.2

HVE

I2ADR.1

SV

I2ADR.0

OI

E4H FMCMD.7

FMCMD.6

FMCMD.5

FMCMD.4

FMCMD.3

FMCMD.2

FMCMD.1

FMCMD.0

GC

00

70

00

00

0000 0000

0111 0000

0000 0000

0000 0000

I2CON*

DF

-

DE

I2EN

DD

STA

DC

STO

DB

SI

DA

AA

D9

-

D8

CRSEL 00 x000 00x0

I2DAT

I2SCLH

I2SCLL

I2STAT

IEN0*

IEN1*

Bit address

I

2

C-bus control register

D8H

I

2

C-bus data register

DAH

Serial clock generator/SCL duty cycle register high

Serial clock generator/SCL duty cycle register low

I

2

C-bus status register

DDH

DCH

D9H

Bit address

Interrupt enable 0

A8H

Interrupt enable 1

Bit address

E8H

STA.4

AF

EA

EF

EAD

STA.3

AE

EWDRT

EE

EST

STA.2

AD

EBO

ED

-

STA.1

AC

ES/ESR

EC

-

STA.0

AB

ET1

EB

ESPI

0

AA

EX1

EA

EC

0

A9

ET0

E9

EKBI

0

A8

EX0

E8

EI2C

00

00

F8

00

00

[1]

0000 0000

0000 0000

1111 1000

0000 0000

00x0 0000


Table 3.


…continued



Bit address


MSB

BF BE BD BC BB BA B9

LSB

B8

Reset value

Hex Binary

IP0* Interrupt priority 0

B8H PWDRT PBO PS/PSR PT1 PX1 PT0 PX0

00

[1]

x000 0000

IP0H Interrupt priority 0 high

B7H PWDRTH PBOH PSH/

PSRH

PT1H PX1H PT0H PX0H

00

[1]

x000 0000

IP1*

IP1H

KBCON

KBMASK

KBPATN

P0*

P1*

P2*

P3*

P0M1

P0M2

P1M1

Bit address

Interrupt priority 1

Interrupt priority 1 high

F8H

F7H

94H Keypad control register

Keypad interrupt mask register

86H

FF

PAD

PADH

-

FE

PST

PSTH

-

FD

-

-

-

FC

-

-

-

FB

PSPI

PSPIH

-

FA

PC

PCH

-

F9

PKBI

PKBIH

PATN

_SEL

F8

PI2C

PI2CH

KBIF

00

00

00

00

[1]

[1]

[1]

Keypad pattern register

93H FF

Port 0

Bit address

80H

Bit address

87

T1/KB7

97

86

CMP1

/KB6

96

85

CMPREF

/KB5

95

84

CIN1A

/KB4

94

83

CIN1B

/KB3

93

82

CIN2A

/KB2

92

81

CIN2B

/KB1

91

80

CMP2

/KB0

90

[1]

Port 1 90H

Bit address

-

A7

-

A6

RST

A5

INT1

A4

INT0/SDA T0/SCL

A3 A2

RXD

A1

TXD

A0

[1]

Port 2 A0H SPICLK SS MISO MOSI -

[1]

Port 3

Port 0 output mode 1

Bit address B7 B6 B5 B4 B3 B2 B1 B0

B0H XTAL1 XTAL2

[1]

84H (P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0) FF

[1]


85H (P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0)

00

[1]


91H (P1M1.7) (P1M1.6) (P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3

[1]

00x0 0000

00x0 0000 xxxx xx00

0000 0000

1111 1111

1111 1111

0000 0000

11x1 xx11


Table 3.


…continued


Name

P1M2

P2M1

P2M2

P3M1

P3M2

PCON

PCONA

Description





SFR addr.


MSB

92H (P1M2.7) (P1M2.6)

A4H

A5H

B1H

(P2M1.7)

(P2M2.7)

-


Power control register

B2H

87H

Power control register A

B5H

Bit address

-

SMOD1

RTCPD

D7

(P2M1.6)

(P2M2.6)

-

-

SMOD0

-

D6

-

(P2M1.5)

(P2M2.5)

-

-

-

VCPD

D5

(P1M2.4)

(P2M1.4)

(P2M2.4)

-

-

BOI

ADPD

D4

(P1M2.3)

(P2M1.3)

(P2M2.3)

-

-

GF1

I2PD

D3

(P1M2.2)

(P2M1.2)

(P2M2.2)

-

-

GF0

SPPD

D2

(P1M2.1)

(P2M1.1)

(P2M2.1)

(P3M1.1)

(P3M2.1)

PMOD1

SPD

D1

LSB

(P1M2.0)

(P2M1.0)

(P2M2.0)

(P3M1.0)

(P3M2.0)

PMOD0

-

D0

Reset value

Hex

00

FF

00

03

00

00

00

[1]

[1]

[1]

[1]

[1]

[1]

Binary

00x0 xx00

1111 1111

0000 0000 xxxx xx11 xxxx xx00

0000 0000

0000 0000

PSW* D0H CY AC F0 RS1 RS0 OV F1 P 00 0000 0000

PT0AD

RSTSRC

RTCCON

RTCH

RTCL

SADDR

SADEN

SBUF

Program status word

Port 0 digital input disable

Reset source register

RTC control

RTC register high

RTC register low

Serial port address register

Serial port address enable

Serial Port data buffer register

F6H

DFH

D1H

D2H

D3H

A9H

B9H

99H

-

-

RTCF

-

BOIF

RTCS1

PT0AD.5

PT0AD.4

PT0AD.3

PT0AD.2

PT0AD.1

BOF

RTCS0

POF

-

R_BK

-

R_WD

-

R_SF

ERTC

-

R_EX

00

[3]

RTCEN

60

[1][6]

00

[6]

00

[6]

00

00 xx xx00 000x

011x xx00

0000 0000

0000 0000

0000 0000

0000 0000 xxxx xxxx


Table 3.


…continued



Bit address


MSB

9F 9E 9D 9C 9B 9A 99

LSB

98

Reset value

Hex Binary

SCON* SM1 SM2 REN TB8 RB8 TI RI 00 0000 0000

SSTAT

SP

SPCTL

SPSTAT

SPDAT

TAMOD

TCON*

TH0

TH1

TL0

TL1

TMOD

TRIM

WDCON

Serial port control

Serial port extended status register

Stack pointer

SPI control register

SPI status register

SPI data register

Timer 0 and 1 auxiliary mode

98H

BAH

81H

E2H

E1H

E3H

8FH

SM0/FE

DBMOD

SSIG

SPIF

-

Timer 0 and 1 control

Bit address

88H

Timer 0 high 8CH

Timer 1 high

Timer 0 low

Timer 1 low

Timer 0 and 1 mode

Internal oscillator trim register

8DH

8AH

8BH

89H T1GATE

96H

8F

TF1

RCCLK

Watchdog control register

A7H PRE2

INTLO

SPEN

WCOL

-

8E

TR1

T1C/T

ENCLK

PRE1

CIDIS

DORD

-

-

8D

TF0

T1M1

TRIM.5

PRE0

DBISEL

MSTR

-

T1M2

8C

TR0

T1M0

TRIM.4

-

FE

CPOL

-

-

8B

IE1

T0GATE

TRIM.3

-

BR

CPHA

-

-

8A

IT1

T0C/T

TRIM.2

WDRUN

OE

SPR1

-

-

89

IE0

T0M1

TRIM.1

WDTOF

STINT 00

SPR0

-

T0M2

88

IT0

T0M0

TRIM.0

WDCLK

07

04

00

00

00

00

00

00

00

00

00

[5][6]

[4][6]

0000 0000

0000 0111

0000 0100

00xx xxxx

0000 0000 xxx0 xxx0

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000


Table 3.


…continued


Name

WDL


Watchdog load C1H


MSB LSB

Reset value

Hex

FF

Binary

1111 1111

WFEED1 C2H

WFEED2

Watchdog feed 1

Watchdog feed 2

C3H

[1] All ports are in input only (high-impedance) state after power-up.

[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.

[3] The RSTSRC register reflects the cause of the P89LPC9331/9341 reset except BOIF bit. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is x011 0000.

[4] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.

Other resets will not affect WDTOF.

[5] On power-on reset and watchdog reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6] The only reset sources that affect these SFRs are power-on reset and watchdog reset.


Table 4.

Extended special function registers - P89LPC9331/9341

[1]

Name

BODCFG

CLKCON

TPSCON

RTCDATH

RTCDATL


FFC8H


MSB

BOD configuration register

CLOCK Control register

Temperature sensor control register

FFDEH

FFCAH

Real-time clock data register high

Real-time clock data register low

FFBFH

FFBEH

CLKOK

-

-

-

-

LSB

BOICFG1 BOICFG0

Reset value

Hex Binary

[2]

XTALWD CLKDBL FOSC2 FOSC1

TSEL1 TSEL0 -

FOSC0

-

[3]

00 0000 0000

00 0000 0000

00 0000 0000

[1] Extended SFRs are physically located on-chip but logically located in external data memory address space (XDATA). The MOVX A,@DPTR and MOVX @DPTR,A instructions are used to access these extended SFRs.

[2] The BOICFG1/0 will be copied from UCFG1.5 and UCFG1.3 when power-on reset.

[3] CLKCON register reset value comes from UCFG1 and UCFG2. The reset value of CLKCON.2 to CLKCON.0 come from UCFG1.2 to UCFG1.0 and reset value of CLKDBL bit comes from UCFG2.7.


Table 5.

Special function registers - P89LPC9351



Bit address


MSB

E7 E6 E5 E4 E3 E2 E1

LSB

E0

Reset value

Hex Binary

E0H

8EH ENBI0 ENADCI0 TMM0 EDGE0 ADCI0

00


0000 0000

0000 0000

ACC* Accumulator

ADCON0 A/D control register 0

ADCON1 A/D control register 1

ADINS A/D input select

ADMODA A/D mode register A

ADMODB A/D mode register B












97H

A3H

C0H

A1H

BBH

A6H

C5H

C6H

C7H

F4H

C4H

BCH

D5H

D6H

D7H

ENBI1

ADI13

BNDI1

CLK2

ENADCI1

ADI12

BURST1

CLK1

TMM1

ADI11

SCC1

CLK0

EDGE1

ADI10

SCAN1

ADCI1

ADI03

BNDI0


ADI02

BURST0

INBND0 ENDAC1 ENDAC0

ADI01

SCC0

BSA1

ADI00 00

SCAN0 00

BSA0 00

FF

00

00

00

00

00

FF

00

00

00

00

0000 0000

0000 0000

0000 0000

000x 0000

1111 1111

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

1111 1111

0000 0000

0000 0000

0000 0000

0000 0000


Table 5.


…continued




MSB LSB

Reset value

Hex Binary

00 0000 0000 AD1DAT3 A/D_1 data register 3

AUXR1 Auxiliary function register

F5H

A2H

Bit address

CLKLP

F7

EBRR

F6

ENT1

F5

ENT0

F4

SRST

F3

0

F2

-

F1

DPS

F0

00 0000 00x0

F0H

BEH

00

00

0000 0000

0000 0000

B*

BRGR0

[2]

B register

Baud rate generator 0 rate low

BRGR1

[2]

Baud rate generator 0 rate high

BRGCON Baud rate generator 0 control

CCCRA

CCCRB

Capture compare

A control register

Capture compare

B control register

CCCRC

CCCRD

CMP1

CMP2

Capture compare

C control register

Capture compare

D control register



DEECON Data EEPROM control register

DEEDAT Data EEPROM data register

DEEADR Data EEPROM address register

BFH

BDH

EAH

EBH

ECH

EDH

ACH

ADH

F1H

F2H

F3H

-

ICECA2

ICECB2

-

-

-

-

EEIF

-

ICECA1

ICECB1

-

-

-

-

HVERR

-

ICECA0

ICECB0

-

-

CE1

CE2

ECTL1

-

ICESA

ICESB

-

-

CP1

CP2

ECTL0

-

ICNFA

ICNFB

-

-

CN1

CN2

-

-

FCOA

FCOB

FCOC

FCOD

OE1

OE2

SBRGS

OCMA1

OCMB1

OCMC1

OCMD1

CO1

CO2

00

BRGEN 00

[2]

OCMA0 00

OCMB0 00

OCMC0 00

OCMD0 00

CMF1 00

[1]

CMF2 00

[1]

EWERR1 EWERR0 EADR8 08

00

00

0000 0000 xxxx xx00

0000 0000

0000 0000 xxxx x000 xxxx x000 xx00 0000 xx00 0000

00001000

0000 0000

0000 0000


Table 5.


…continued


Name

DIVM


95H


MSB LSB

Reset value

Hex Binary

00 0000 0000 CPU clock divide-by-M control

DPTR

DPH

DPL

Data pointer

(2 bytes)

Data pointer high 83H

Data pointer low 82H

E7H FMADRH Program flash address high

FMADRL Program flash address low

FMCON Program flash control (Read)

E6H

E4H BUSY HVA HVE SV OI

00

70

Program flash control (Write)

FMDATA Program flash data

I2ADR I

2

C-bus slave address register

I2CON*

I2DAT

I2SCLH

I2SCLL

I2STAT

E4H

E5H

DBH

I

2

C-bus control register

Bit address

D8H

I

2

C-bus data register

DAH

DDH Serial clock generator/SCL duty cycle register high

Serial clock generator/SCL duty cycle register low

I

2

C-bus status register

DCH

D9H

FMCMD.7

I2ADR.6

DF

-

STA.4

FMCMD.6

I2ADR.5

DE

I2EN

STA.3

FMCMD.5

I2ADR.4

DD

STA

STA.2

FMCMD.4

I2ADR.3

DC

STO

STA.1

FMCMD.3

I2ADR.2

DB

SI

STA.0

FMCMD.2

I2ADR.1

DA

AA

0

FMCMD.1

I2ADR.0

D9

-

0

FMCMD.0

GC

D8

CRSEL

0

00

00

00

00

00

F8

00

00

00

0000 0000

0000 0000

0000 0000

0000 0000

0111 0000

0000 0000

0000 0000 x000 00x0

0000 0000

0000 0000

1111 1000


Table 5.


…continued


Name

ICRAH



MSB LSB

Reset value

Hex Binary

00 0000 0000

ICRAL

ICRBH

ICRBL

Input capture A register high

Input capture A register low

ABH

AAH

Input capture B register high

Input capture B register low

AFH

AEH

Bit address AF AE AD AC AB AA A9 A8

00

00

00

0000 0000

0000 0000

0000 0000

00 0000 0000 IEN0*

IEN1*

Interrupt enable 0 A8H

Bit address

Interrupt enable 1 E8H

Bit address

IP0*

IP0H

Interrupt priority 0 B8H


B7H

Bit address

IP1*

IP1H

Interrupt priority 1 F8H


F7H

94H KBCON Keypad control register

KBMASK Keypad interrupt mask register

86H

93H KBPATN Keypad pattern register

OCRAH Output compare

A register high

OCRAL

OCRBH

Output compare

A register low

Output compare

B register high

EFH

EEH

FBH

EA

EF

EADEE

BF

-

-

FF

PADEE

PAEEH

-

EWDRT

EE

EST

BE

PWDRT

PWDRTH

FE

PST

PSTH

-

EBO

ED

-

BD

PBO

PBOH

FD

-

-

-

ES/ESR

EC

ECCU

BC

PS/PSR

PSH/

PSRH

FC

PCCU

PCCUH

-

ET1

EB

ESPI

BB

PT1

PT1H

FB

PSPI

PSPIH

-

EX1

EA

EC

BA

PX1

PX1H

FA

PC

PCH

-

ET0

E9

EKBI

B9

PT0

PT0H

F9

PKBI

PKBIH

PATN

_SEL

EX0

E8

EI2C

B8

PX0

PX0H

KBIF

00

[1]

00

[1]

00

[1]

F8

PI2C 00

[1]

PI2CH 00

[1]

00

[1]

00

FF

00

00

00

00x0 0000 x000 0000 x000 0000

00x0 0000

00x0 0000 xxxx xx00

0000 0000

1111 1111

0000 0000

0000 0000

0000 0000


Table 5.


…continued


Name

OCRBL



MSB LSB

Reset value

Hex Binary

00 0000 0000

OCRCH

OCRCL

OCRDH

OCRDL

Output compare

B register low

Output compare

C register high

Output compare

C register low

Output compare

D register high

FAH

FDH

FCH

FFH

Output compare

D register low

FEH

Bit address 87 86 85 84 83 82 81 80

00

00

00

00

0000 0000

0000 0000

0000 0000

0000 0000

P0* Port 0 80H T1/KB7 CMP1

/KB6

CMPREF

/KB5

CIN1A

/KB4

CIN1B

/KB3

CIN2A

/KB2

CIN2B

/KB1

CMP2

/KB0

[1]

P1*

P2*

P3*

P0M1

P0M2

P1M1

P1M2

P2M1

P2M2

Port 1

Bit address

90H

Bit address

A0H Port 2

Port 3


Bit address

B0H

84H

85H Port 0 output mode 2


91H

92H Port 1 output mode 2



A4H

A5H

97

OCC

A7

ICA

96

OCB

A6

OCA

95

RST

A5

SPICLK

94

INT1

A4

SS

93

INT0/SDA

A3

MISO

92

T0/SCL

A2

MOSI

91

RXD

A1

OCD

90

TXD

A0

ICB

[1]

[1]

B7 B6 B5 B4 B3 B2 B1 B0

XTAL1 XTAL2

[1]

(P0M1.7) (P0M1.6) (P0M1.5) (P0M1.4) (P0M1.3) (P0M1.2) (P0M1.1) (P0M1.0)

FF

[1]

(P0M2.7) (P0M2.6) (P0M2.5) (P0M2.4) (P0M2.3) (P0M2.2) (P0M2.1) (P0M2.0) 00

[1]

(P1M1.7) (P1M1.6)

(P1M2.7) (P1M2.6) -

(P1M1.4) (P1M1.3) (P1M1.2) (P1M1.1) (P1M1.0) D3

[1]

(P1M2.4) (P1M2.3) (P1M2.2) (P1M2.1) (P1M2.0) 00

[1]

(P2M1.7) (P2M1.6) (P2M1.5) (P2M1.4) (P2M1.3) (P2M1.2) (P2M1.1) (P2M1.0)

FF

[1]

(P2M2.7) (P2M2.6) (P2M2.5) (P2M2.4) (P2M2.3) (P2M2.2) (P2M2.1) (P2M2.0) 00

[1]

1111 1111

0000 0000

11x1 xx11

00x0 xx00

1111 1111

0000 0000


Table 5.


…continued



Bit functions and addresses Reset value

P3M1 B1H

MSB

-

LSB Hex Binary

(P3M1.1) (P3M1.0) 03

[1]

xxxx xx11

P3M2

PCON

PCONA



Power control register

Power control register A

B2H

87H

B5H

-

SMOD1

RTCPD

-

SMOD0

DEEPD

-

-

VCPD

-

BOI

ADPD

-

GF1

I2PD

-

GF0

SPPD

(P3M2.1) (P3M2.0) 00

[1]

PMOD1

SPD

PMOD0 00

CCUPD 00

[1]

xxxx xx00

0000 0000

0000 0000

Bit address D7 D6 D5 D4 D3 D2 D1 D0

CY AC F0 RS1 RS0 OV F1 P 00 0000 0000 PSW*

PT0AD

SADEN

SBUF

Program status word

Port 0 digital input disable

D0H

F6H

RSTSRC Reset source register

DFH

RTCCON RTC control

RTCH RTC register high

D1H

D2H

RTCL

SADDR

RTC register low

Serial port address register

D3H

A9H

Serial port address enable

Serial Port data buffer register

B9H

99H

Bit address

SCON*

SSTAT

SP

SPCTL

Serial port control 98H

Serial port extended status register

BAH

Stack pointer

SPI control register

81H

E2H

-

-

RTCF

9F

SM0/FE

DBMOD

SSIG

-

BOIF

RTCS1

9E

SM1

INTLO

SPEN

PT0AD.5

PT0AD.4

PT0AD.3

PT0AD.2

PT0AD.1

BOF

RTCS0

9D

SM2

CIDIS

DORD

POF

-

9C

REN

DBISEL

MSTR

R_BK

-

9B

TB8

FE

CPOL

R_WD

-

9A

RB8

BR

CPHA

R_SF

ERTC

99

TI

OE

SPR1

-

R_EX

RTCEN 60

[1][6]

011x xx00

00

[6]

0000 0000

00

[6]

0000 0000

00 0000 0000

98

RI 00

STINT 00

SPR0

00

[3]

00 xx

07

04 xx00 000x

0000 0000 xxxx xxxx

0000 0000

0000 0000

0000 0111

0000 0100


Table 5.


…continued




SPSTAT E1H

MSB

SPIF WCOL -

LSB

-

Hex Binary

00 00xx xxxx

SPDAT

SPI status register

SPI data register E3H 00 0000 0000

T1M2 T0M2 00 xxx0 xxx0 TAMOD

TCON*

TCR20*

TCR21

TH0

TH1

TH2

TICR2

TIFR2

Timer 0 and 1 auxiliary mode

Timer 1 high

CCU timer high

8FH

Timer 0 and 1 control

Bit address

88H

C8H CCU control register 0

CCU control register 1

Timer 0 high

F9H

8CH

8DH

CDH

C9H CCU interrupt control register

CCU interrupt flag register

E9H

DEH TISE2

TL0

TL1

TL2

TMOD

CCU interrupt status encode register

Timer 0 low

Timer 1 low

CCU timer low

TOR2H

Timer 0 and 1 mode

CCU reload register high

TOR2L CCU reload register low

TPCR2H Prescaler control register high

8AH

8BH

CCH

89H

CFH

CEH

CBH

8F

TF1

PLEEN

TCOU2

TOIE2

TOIF2

-

T1GATE

-

8E

TR1

HLTRN

-

-

T1C/T

-

8D

TF0

HLTEN

-

-

T1M1

-

8C

TR0

ALTCD

-

-

T1M0

-

8B

IE1

ALTAB

PLLDV.3

PLLDV.2

PLLDV.1

PLLDV.0

00

TOCIE2D TOCIE2C TOCIE2B TOCIE2A

TOCF2D TOCF2C TOCF2B TOCF2A

-

T0GATE

-

8A

IT1

TDIR2

-

-

ENCINT.2

ENCINT.1

ENCINT.0 00

T0C/T

-

89

IE0

88

IT0 00

TMOD21 TMOD20 00

00

00

00

TICIE2B TICIE2A 00

TICF2B

T0M1

TICF2A 00

T0M0

00

00

00

00

00

00

TPCR2H.1 TPCR2H.0 00

0000 0000

0000 0000

0xxx 0000

0000 0000

0000 0000

0000 0000

0000 0x00

0000 0x00 xxxx x000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000

0000 0000 xxxx xx00


Table 5.


…continued


Name Description

TPCR2L Prescaler control register low

TRIM Internal oscillator trim register

SFR addr.


MSB LSB Hex

CAH TPCR2L.7 TPCR2L.6 TPCR2L.5 TPCR2L.4 TPCR2L.3 TPCR2L.2 TPCR2L.1 TPCR2L.0 00

Binary

0000 0000

96H RCCLK ENCLK TRIM.5

TRIM.4

TRIM.3

TRIM.2

TRIM.1

TRIM.0

[5][6]

A7H PRE2 PRE1 PRE0 WDRUN WDTOF WDCLK

[4][6]

WDCON Watchdog control register

WDL Watchdog load C1H FF 1111 1111

WFEED1 Watchdog feed 1

WFEED2 Watchdog feed 2

C2H

C3H

[1] All ports are in input only (high-impedance) state after power-up.

[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.

[3] The RSTSRC register reflects the cause of the P89LPC9351 reset except BOIF bit. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is x011 0000.

[4] After reset, the value is 1110 01x1, i.e., PRE2 to PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.

Other resets will not affect WDTOF.

[5] On power-on reset and watchdog reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.

[6] The only reset sources that affect these SFRs are power-on reset and watchdog reset.


Table 6.

Extended special function registers - P89LPC9351

[1]

Name

BODCFG

CLKCON


FFC8H


MSB

BOD configuration register

CLOCK

Control register

FFDEH CLKOK -

-

XTALWD

-

CLKDBL

-

FOSC2 FOSC1

LSB

BOICFG1 BOICFG0

FOSC0

Reset value

Hex Binary

[2]

[3]

1000 xxxx

PGACON1 PGA1 control register

FFE1H ENPGA1 PGASEL11 PGASEL10 PGATRIM1 PGAG11 PGAG10 00 0000 0000

PGACON1B PGA1 control register B

PGA1TRIM8X16X PGA1 trim register

FFE4H -

FFE3H 16XTRIM3

-

16XTRIM2

-

16XTRIM1

-

16XTRIM0 8XTRIM3 8XTRIM2 8XTRIM1

PGAENO

FF1

00 0000 0000

8XTRIM0

[4]


PGACON0 PGA0 control register

FFE2H 4XTRIM3 4XTRIM2 4XTRIM1 4XTRIM0 2XTRIM3 2XTRIM2 2XTRIM1

FFCAH ENPGA0 PGASEL01 PGASEL00 PGATRIM0 TSEL1 TSEL0 PGAG01

2XTRIM0

[4]

PGAG00 00 0000 0000

PGACON0B PGA0 control register B


FFCEH -

FFCDH 16XTRIM3

-

16XTRIM2

-

16XTRIM1

-

16XTRIM0 8XTRIM3 8XTRIM2 8XTRIM1

PGAENO

FF0

00 0000 0000

8XTRIM0

[4]


FFCCH 4XTRIM3 4XTRIM2 4XTRIM1 4XTRIM0 2XTRIM3 2XTRIM2 2XTRIM1 2XTRIM0

[4]

RTCDATH FFBFH 00 0000 0000

RTCDATL

Real-time clock data register high

Real-time clock data register low

FFBEH 00 0000 0000

[1] Extended SFRs are physically located on-chip but logically located in external data memory address space (XDATA). The MOVX A,@DPTR and MOVX @DPTR,A instructions are used to access these extended SFRs.

[2] The BOICFG1/0 will be copied from UCFG1.5 and UCFG1.3 when power-on reset.

[3] CLKCON register reset value comes from UCFG1 and UCFG2. The reset value of CLKCON.2 to CLKCON.0 come from UCFG1.2 to UCFG1.0 and reset value of CLKDBL bit comes from UCFG2.7.

[4] On power-on reset and watchdog reset, the PGAxTRIM8X16X and PGAxTRIM2X4X registers are initialized with a factory preprogrammed value. Other resets will not cause initialization.


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1.6 Memory organization

FF00h

FFEFh

1FFFh

1E00h

1C00h

1BFFh

1800h

17FFh

1400h

13FFh

1000h

0FFFh

0C00h

0BFFh

0800h

07FFh

0400h

03FFh

0000h

IAP entrypoints

ISP CODE

(512B)

(1)

SECTOR 7

SECTOR 6

SECTOR 5

SECTOR 4

SECTOR 3

SECTOR 2

SECTOR 1

SECTOR 0 read-protected

IAP calls only

IDATA routines

entry points for:

-51 ASM. code

-C code

ISP serial loader

entry points for:

-UART (auto-baud)

-I2C, SPI, etc.

(1)

FFEFh

FF1Fh

FF00h

1FFFh

1E00h entry points

FFh

SPECIAL FUNCTION

REGISTERS

(DIRECTLY ADDRESSABLE)

IDATA (incl. DATA)

128 BYTES ON-CHIP

DATA MEMORY (STACK

AND INDIR. ADDR.)

DATA

128 BYTES ON-CHIP

DATA MEMORY (STACK,

DIRECT AND INDIR. ADDR.)

4 REG. BANKS R[7:0] data memory

(DATA, IDATA)

FFFFh

80h

7Fh

00h

EXTENDED SFRs

FFB0h

RESERVED

XDATA

(512 BYTES)

(P89LPC9351)

01FFh

0000h

01FFh

DATA EEPROM

(512 BYTES)

[SFR ACCESS]

(P89LPC9351)

data EEPROM

002aae090

0000h

(1) ISP code is located at the end of sector 3 on the P89LPC9331 and at the end of sector 7 on the P89LPC9341/9351.

Fig 7.

P89LPC9331/9341/9351 memory map

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The various P89LPC9331/9341/9351 memory spaces are as follows:

DATA — 128 bytes of internal data memory space (00h:7Fh) accessed via direct or indirect addressing, using instruction other than MOVX and MOVC. All or part of the Stack may be in this area.

IDATA — Indirect Data. 256 bytes of internal data memory space (00h:FFh) accessed via indirect addressing using instructions other than MOVX and MOVC. All or part of the

Stack may be in this area. This area includes the DATA area and the 128 bytes immediately above it.

SFR — Special Function Registers. Selected CPU registers and peripheral control and status registers, accessible only via direct addressing.

XDATA — ‘External’ Data or Auxiliary RAM. Duplicates the classic 80C51 64 kB memory space addressed via the MOVX instruction using the DPTR, R0, or R1. All or part of this space could be implemented on-chip. The P89LPC9351 has 512 bytes of on-chip XDATA memory, plus extended SFRs located in XDATA.-

CODE — 64 kB of Code memory space, accessed as part of program execution and via the MOVC instruction. The P89LPC9331/9341/9351 has 4 kB/8 kB of on-chip Code memory.

The P89LPC9351 also has 512 bytes of on-chip Data EEPROM that is accessed via

SFRs (see Section

Section 18 “Data EEPROM (P89LPC9351)” ).

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Table 7.

Data RAM arrangement

Type

DATA

IDATA

XDATA

Data RAM

Directly and indirectly addressable memory

Size (bytes)

128

Indirectly addressable memory 256

Auxiliary (‘External Data’) on-chip memory that is accessed using the MOVX instructions (P89LPC9351)

512

2.

Clocks

2.1 Enhanced CPU

The P89LPC9331/9341/9351 uses an enhanced 80C51 CPU which runs at six times the speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most instructions execute in one or two machine cycles.

2.2 Clock definitions

The P89LPC9331/9341/9351 device has several internal clocks as defined below:

OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock sources and can also be optionally divided to a slower frequency (see

Figure 9 and

Section 2.10 “CPU Clock (CCLK) modification: DIVM register” ). Note: f

osc

is defined as the OSCCLK frequency.

CCLK — CPU clock; output of the DIVM clock divider. There are two CCLK cycles per machine cycle, and most instructions are executed in one to two machine cycles (two or four CCLK cycles).

RCCLK — The internal 7.373 MHz RC oscillator output.The clock doubler option, when enabled, provides an output frequency of 14.746 MHz.

PCLK — Clock for the various peripheral devices and is

CCLK

⁄

2

.

2.2.1 Oscillator Clock (OSCCLK)

The P89LPC9351 provides several user-selectable oscillator options in generating the

CPU clock. This allows optimization for a range of needs from high precision to lowest possible cost. These options are configured when the flash is programmed and include an on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external crystal, or an external clock source.

2.3 Crystal oscillator option

The crystal oscillator can be optimized for low, medium, or high frequency crystals covering a range from 20 kHz to 18 MHz. It can be the clock source of OSCCLK, RTC and

WDT.

2.3.1 Low speed oscillator option

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic resonators are also supported in this configuration

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2.3.2 Medium speed oscillator option

This option supports an external crystal in the range of 100 kHz to 4 MHz. Ceramic resonators are also supported in this configuration.

2.3.3 High speed oscillator option

This option supports an external crystal in the range of 4 MHz to 18 MHz. Ceramic resonators are also supported in this configuration.

2.4 Clock output

The P89LPC9331/9341/9351 supports a user-selectable clock output function on the

XTAL2 / CLKOUT pin when the crystal oscillator is not being used. This condition occurs if a different clock source has been selected (on-chip RC oscillator, watchdog oscillator, external clock input on X1) and if the Real-time Clock and Watchdog Timer are not using the crystal oscillator as their clock source. This allows external devices to synchronize to the P89LPC9331/9341/9351. This output is enabled by the ENCLK bit in the TRIM register.

The frequency of this clock output is

1

⁄

2

that of the CCLK. If the clock output is not needed in Idle mode, it may be turned off prior to entering Idle, saving additional power. Note: on reset, the TRIM SFR is initialized with a factory preprogrammed value. Therefore when setting or clearing the ENCLK bit, the user should retain the contents of other bits of the

TRIM register. This can be done by reading the contents of the TRIM register (into the

ACC for example), modifying bit 6, and writing this result back into the TRIM register.

Alternatively, the ‘ANL direct’ or ‘ORL direct’ instructions can be used to clear or set bit 6 of the TRIM register.

2.5 On-chip RC oscillator option

The P89LPC9331/9341/9351 has a 6-bit TRIM register that can be used to tune the frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory pre-programmed value to adjust the oscillator frequency to 7.373 MHz

± 1 % at room temperature. (Note: the initial value is better than 1 %; please refer to the

P89LPC9331/9341/9351 data sheet for behavior over temperature). End user applications can write to the TRIM register to adjust the on-chip RC oscillator to other frequencies. Increasing the TRIM value will decrease the oscillator frequency. When the clock doubler option is enabled (UCFG2.7 = 1), the output frequency is doubled. If CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0 allowing highest performance access. This bit can then be set in software if CCLK is running at 8 MHz or slower. When clock doubler option is enabled, BOE1 bit (UCFG1.5) and BOE0 bit (UCFG1.3) are required to hold the device in reset at power-up until V

DD

has reached its specified level.

Table 8.

On-chip RC oscillator trim register (TRIM - address 96h) bit allocation

Bit 7 6 5 4 3 2

Symbol

Reset

RCCLK

0

ENCLK

0

TRIM.5

TRIM.4

TRIM.3

TRIM.2

Bits 5:0 loaded with factory stored value during reset.

1

TRIM.1

0

TRIM.0

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Table 9.

On-chip RC oscillator trim register (TRIM - address 96h) bit description

Bit

0

1

2

Symbol

TRIM.0

TRIM.1

TRIM.2

Description

Trim value. Determines the frequency of the internal RC oscillator. During reset, these bits are loaded with a stored factory calibration value. When writing to either bit 6 or bit 7 of this register, care should be taken to preserve the current TRIM value by reading this register, modifying bits 6 or 7 as required, and writing the result to this register.

3

4

TRIM.3

TRIM.4

5

6

TRIM.5

ENCLK

7 RCCLK when = 1,

CCLK

⁄

2

is output on the XTAL2 pin provided the crystal oscillator is not being used.

when = 1, selects the RC Oscillator output as the CPU clock (CCLK). This allows for fast switching between any clock source and the internal RC oscillator without needing to go through a reset cycle.

2.6 Watchdog oscillator option

The watchdog has a separate oscillator which has a frequency of 400 kHz, calibrated to

± 5 % at room temperature. This oscillator can be used to save power when a high clock frequency is not needed.

2.7 External clock input option

In this configuration, the processor clock is derived from an external source driving the

XTAL1 / P3.1 pin. The rate may be from 0 Hz up to 18 MHz. The XTAL2 / P3.0 pin may be used as a standard port pin or a clock output. When using an oscillator frequency above

12 Mhz, BOE1 bit (UCFG1.5) and BOE0 bit (UCFG1.3) are required to hold the device in reset at power-up until V

DD

has reached its specified level.

quartz crystal or ceramic resonator

XTAL1

(1)

XTAL2

002aad364

Note: The oscillator must be configured in one of the following modes: Low frequency crystal, medium frequency crystal, or high frequency crystal.

(1) A series resistor may be required to limit crystal drive levels. This is especially important for low frequency crystals (see text).

Fig 8.

Using the crystal oscillator

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XTAL1

XTAL2

HIGH FREQUENCY

MEDIUM FREQUENCY

LOW FREQUENCY

RTC

ADC1

ADC0

RC OSCILLATOR

WITH CLOCK DOUBLER

(7.3728 MHz/14.7456 MHz

± 1 %)

RCCLK

WATCHDOG

OSCILLATOR

(400 kHz

± 5 %)

TIMER 0 AND

TIMER 1

OSCCLK

DIVM

CCLK

PCLK

÷2

I

2

C-BUS

PCLK

SPI UART

CPU

WDT

32

× PLL

CCU

(P89LPC9351)

002aad559

Fig 9.

Block diagram of oscillator control

2.8 Clock source switching on the fly

P89LPC9331/9341/9351 can implement clock switching on any sources of watchdog oscillator, 7/14 MHz IRC oscillator, crystal oscillator and external clock input during code is running. CLKOK bit in register CLKCON is read only and used to indicate the clock switch status. When CLKOK is ‘0’, clock switch is processing, not completed. When CLKOK is

‘1’, clock switch is completed. When start new clock source switch, CLKOK is cleared automatically. Notice that when CLKOK is ‘0’, Writing to CLKCON register is not allowed.

During reset, CLKCON register value comes from UCFG1 and UCFG2. The reset value of

CLKCON.2 to CLKCON.0 come from UCFG1.2 to UCFG1.0 and reset value of CLKDBL bit comes from UCFG2.7.

Table 10.

Clock control register (CLKCON - address FFDEh) bit allocation

Bit 7 6 5 4 3

Symbol

Reset

CLKOK

1

-

0

-

0

XTALWD

0

CLKDBL x

2

FOSC2 x

1

FOSC1 x

0

FOSC0 x

Table 11.

Clock control register (CLKCON - address FFDEh) bit description

Bit Symbol Description

2:0

3

FOSC2, FOSC1,

FOSC0

CLKDBL

CPU oscillator type selection for clock switch. See

information. Combinations other than those shown in

future use and should not be used.

Section 2 for additional

Table 12

are reserved for

Clock doubler option for clock switch. When set, doubles the output frequency of the internal RC oscillator.

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Table 11.

Clock control register (CLKCON - address FFDEh) bit description

…continued

Bit

4

6:5

7

-

Symbol

XTALWD

CLKOK

Description

external crystal oscillator as the clock source of watchdog timer. When =0, disable external crystal oscillator as the clock source of watchdog timer.

reserved

Clock switch completed flag. When = 1, clock switch is completed. When =0, clock switch is processing and writing to register CLKCON is not allowed.

Table 12.

Oscillator type selection for clock switch

FOSC[2:0] Oscillator configuration

111

100

011

010

001

000

External clock input on XTAL1.

Watchdog Oscillator, 400 kHz ± 5 %.

Internal RC oscillator, 7.373 MHz ± 1 %.

Low frequency crystal, 20 kHz to 100 kHz.

Medium frequency crystal or resonator, 100 kHz to 4 MHz.

High frequency crystal or resonator, 4 MHz to 18 MHz.

2.9 Oscillator Clock (OSCCLK) wake-up delay

The P89LPC9331/9341/9351 has an internal wake-up timer that delays the clock until it stabilizes depending on the clock source used. If the clock source is any of the three crystal selections (low, medium and high frequencies) the delay is 1024 OSCCLK cycles plus 60

µs to 100 µs. If the clock source is the internal RC oscillator, the delay is

200

µs to 300 µs. If the clock source is watchdog oscillator or external clock, the delay is

32 OSCCLK cycles.

2.10 CPU Clock (CCLK) modification: DIVM register

The OSCCLK frequency can be divided down, by an integer, up to 510 times by configuring a dividing register, DIVM, to provide CCLK. This produces the CCLK frequency using the following formula:

CCLK frequency = f osc

/ (2N)

Where: f osc

is the frequency of OSCCLK, N is the value of DIVM.

Since N ranges from 0 to 255, the CCLK frequency can be in the range of f osc

to f osc

/510.

(for N = 0, CCLK = f osc

).

This feature makes it possible to temporarily run the CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can retain the ability to respond to events other than those that can cause interrupts (i.e. events that allow exiting the Idle mode) by executing its normal program at a lower rate. This can often result in lower power consumption than in Idle mode. This can allow bypassing the oscillator start-up time in cases where Power-down mode would otherwise be used. The value of DIVM may be changed by the program at any time without interrupting code execution.

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2.11 Low power select

The P89LPC9331/9341/9351 is designed to run at 18 MHz (CCLK) maximum. However, if

CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to a logic 1 to lower the power consumption further. On any reset, CLKLP is logic 0 allowing highest performance. This bit can then be set in software if CCLK is running at 8 MHz or slower.

3.

A/D converter

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3.1 General description

The P89LPC9331/9341/9351 have two 8-bit, 4-channel multiplexed successive approximation analog-to-digital converter modules sharing common control logic. An on-chip temperature sensor is integrated with one of the ADC modules and operates over wide temperature. In P89LPC9351, two high-speed programmable gain amplifiers (PGA) are integrated. The PGAs provide selectable gains of 2x, 4x, 8x, or 16x. A block diagram of the A/D converter is shown in

Figure 10

and Figure 11

. Each A/D converter consists of an 4-input multiplexer which feeds a sample-and-hold circuit providing an input signal to one of two comparator inputs. The control logic in combination with the SAR drives a digital-to-analog converter which provides the other input to the comparator. The output of the comparator is fed to the SAR.

3.2 A/D features

•

Two 8-bit, 4-channel multiplexed input, successive approximation A/D converters

•

Programmable Gain Amplifier (PGA) with selectable gains of 2x, 4x, 8x, or 16x

(P89LPC9351)

•

On-chip wide range temperature sensor

•

Four result registers for each A/D

•

Six operating modes

– Fixed channel, single conversion mode

– Fixed channel, continuous conversion mode

– Auto scan, single conversion mode

– Auto scan, continuous conversion mode

– Dual channel, continuous conversion mode

– Single step mode

•

Four conversion start modes

– Timer triggered start

– Start immediately

– Edge triggered

– Dual start immediately

•

8-bit conversion time of

≥ 1.61 µs at an A/D clock of 8.0 MHz

•

Interrupt or polled operation

•

High and low boundary limits interrupt

•

DAC output to a port pin with high output impedance

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AD00

AD01

AD02

AD03

V ref(bg)

V sen

AD10

AD11

AD12

AD13

•

Clock divider

•

Power down mode

Anin00

Anin01

Anin02

Anin03 input MUX input MUX

Anin10

Anin11

Anin12

Anin13 input MUX

Fig 10. P89LPC9331/9341 ADC block diagram

4

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comp

SAR

8

DAC0

CONTROL

LOGIC comp

SAR

DAC1 to comparators

CCLK

8

002aae463

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AD00

AD01

AD02

AD03

V ref(bg)

V sen

PGA0

Anin00

Anin01

Anin02

Anin03 input MUX comp

+

–

SAR

8

DAC0

AD10

AD11

AD12

AD13

PGA1

Anin10

Anin11 input MUX

Anin12

Anin13 comp

+

–

SAR

CONTROL

LOGIC

8

DAC1

CCLK

4

002aad576 to comparators

Fig 11. P89LPC9351 ADC block diagram

3.2.1 Programmable Gain Amplifier (PGA) (P89LPC9351)

Additional PGA is integrated in each ADC module to improve the effective resolution of the ADC. A single channel can be selected for amplification. The block diagram of PGA is

shown in Figure 12

.

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AD03

V ref(bg)

V sen

AD00

AD01

AD02

MUX

TSEL1, TSEL0

AD10

AD11

AD12

AD13

MUX

4

Σ

PGA0 TRIM

REGISTERS

PGATRIM0

PGA0 GAIN

PGAG01, PGAG00

MUX

Anin00

Anin01

Anin02

Anin03

PGASEL01,

PGASEL00

MUX

4

Σ

PGA1 TRIM

REGISTERS

PGATRIM1

PGA1 GAIN

PGAG11, PGAG10

MUX

Anin10

Anin11

Anin12

Anin13

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PGASEL11,

PGASEL10

002aae098

Fig 12. PGA block diagram

Register PGACONx and PGACONxB are used for PGA configuration. The gain of PGA can be programmable to 2, 4, 8 or 16 by configuring PGAGx1 and PGAGx0 bits. PGA is enabled by setting ENPGAx bit. If ENPGAx is cleared, PGA is disabled and bypassed, which means the PGA gain value is 1.

Four external analog input signals (ADx0-ADx3) are selected by configuring PGASELx1 and PGASELx0. Temperature sensor, the internal reference voltage V ref(bg)

(1.23 V ± 10 %) and analog input channel AD03 multiplex the same input channel to

PGA0. Selecting temperature sensor, the internal reference voltage or AD03 input pin is achieved by configuring TSEL1 and TSEL0 bits in register PGACON0.

PGA outputs go into the 4-input multiplexer of A/D converter, allowing the amplified signal to be converted by the ADC. For PGA1, its outputs also pass to analog comparators.

3.2.1.1

PGA calibration

PGA calibration is needed when changing to different gain level. PGA offset voltage is used to guarantee the linearity of PGA output. PGAENOFFx bit in register PGACONxB is used to enable PGA offset voltage. To calibrate PGA, PGA input need to be grounded and only PGA offset voltage connects into amplifier. PGATRIMx bit in register PGACONx is used as trim enable bit. If set, PGA input is grounded for calibration mode. 4-bit trim value is used to provide the PGA offset voltage in PGA trim registers PGAxTRIM2X4X and

PGAxTRIM8X16X. Then through A/D conversion, we can get PGA trim result. The trim result from the ADC then needs to be subtracted from each result of the ADC. Users need to store the trim result and do the offset subtraction by themselves.

PGA usage steps:

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1. Select PGA gain level and input channel by configuring PGACONx register. Enable

PGA by Setting ENPGAx bit.

2. Setting PGAENOFFx bit to enable PGA offset voltage.

3. Setting PGATRIMx bit to ground PGA input.

4. Using ADC to get converting result as PGA offset result and store it.

5. Clear PGATRIMx bit to enable input signal.

6. Using ADC to get converting result.

7. Get amplified ADC result by subtracting PGA offset result from ADC result.

End users application can write to PGA trim registers to adjust PGA offset voltage.

Increasing 4-bit trim value will increase the corresponding PGA offset voltage. During reset, 4-bits trim value is initialized to a factory pre-programmed value. To guarantee the linearity of PGA output, it is recommended not to change the PGA trim registers.

Table 13.

PGA trim register

Register bits

PGAxTRIM2X4X[3:0]

Contains

trim value for 2x gain value

PGAxTRIM2X4X[7:4]

PGAxTRIM8X16X[3:0]

PGAxTRIM8X16X[7:4] trim value for 4x gain value trim value for 8x gain value trim value for 16x gain value

3.2.1.2

Channel selection dependency

In auto scan mode and fixed channel single conversion mode, the PGA channel selection is dependent on the ADC channel selection, which means the PGA channel selection is tracking ADC channel selection. In other modes, the PGA channel selection is independent and can be different from the ADC channel selection. If different, the gain of the selected ADC channel is 1.

Table 14.

PGA channel selection

ADC conversion mode

Fixed channel, continuous conversion mode

Dual channel, continuous conversion mode

Single step mode

Fixed channel, single conversion mode

Auto Scan, single/continuous conversion mode

PGA channel selection dependency

PGA channel selection is independent to

ADC channel selection the PGA channel selection is dependent on the ADC channel selection

3.2.2 Temperature sensor

An on-chip wide range temperature sensor is integrated with ADC0 module. It provides temperature sensing capability of

−40 °C ~ 85 °C. To get an accurate temperature value, it is necessary to get supply voltage by measuring the internal reference voltage V ref(bg)

first.

Temperature sensor voltage can be calculated by the following formula:

V sen

=

A sen

×

V

⁄

A

(1)

In formula (1), A ref(bg) is the A/D converting result of V ref(bg) and A sen

is the A/D converting result of V sen

.

Temperature Sensor transfer function can be shown in the following formula:

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V sen

=

m

×

temp

+ b (where m = 11.3 mV/

°C, b = 890 mV)

P89LPC9331/9341 Temperature Sensor usage steps:

1. Config TSEL1 and TSEL0 as ‘01’ to choose internal reference voltage.

2. Using ADC to get converting result as A ref

.

3. Config TSEL1 and TSEL0 as ‘10’ to choose temperature sensor.

4. Using ADC to get converting result as A sen

.

5. Calculate V sen

with formula (1).

6. Calculate Temperature with formula (2).

P89LPC9351 Temperature Sensor usage steps:

1. Setting PGASEL01 and PGASEL00 bits to choose AD03 channel.

2. Config TSEL1 and TSEL0 as ‘01’ to choose internal reference voltage.

3. Using ADC to get converting result as A ref

.

4. Config TSEL1 and TSEL0 as ‘10’ to choose temperature sensor.

5. Using ADC to get converting result as A sen

.

6. Calculate V sen

with formula (1).

7. Calculate Temperature with formula (2).

(2)

3.2.3 ADC operating modes

3.2.3.1

Fixed channel, single conversion mode

A single input channel can be selected for conversion. A single conversion will be performed and the result placed in the result register which corresponds to the selected

input channel (see Table 15

). An interrupt, if enabled, will be generated after the conversion completes. The input channel is selected in the ADINS register. This mode is selected by setting the SCANx bit in the ADMODA register.

Table 15.

Input channels and result registers for fixed channel single, auto scan single and auto scan continuous conversion mode

Result register Input channel

AD0DAT0 Anin00

AD0DAT1

AD0DAT2

AD0DAT3

AD1DAT0

Anin01

Anin02

Anin03

Anin10

AD1DAT1

AD1DAT2

AD1DAT3

Anin11

Anin12

Anin13

3.2.3.2

Fixed channel, continuous conversion mode

A single input channel can be selected for continuous conversion. The results of the

conversions will be sequentially placed in the four result registers (see Table 16 ). An

interrupt, if enabled, will be generated after every four conversions. Additional conversion

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results will again cycle through the four result registers, overwriting the previous results.

Continuous conversions continue until terminated by the user. This mode is selected by setting the SCCx bit in the ADMODA register.

Table 16.

Result registers and conversion results for fixed channel, continuous conversion mode

Result register Contains

ADxDAT0 Selected channel, first conversion result

ADxDAT1

ADxDAT2

ADxDAT3

Selected channel, second conversion result

Selected channel, third conversion result

Selected channel, fourth conversion result

3.2.3.3

Auto scan, single conversion mode

Any combination of the four input channels can be selected for conversion by setting a channel’s respective bit in the ADINS register. The channels are converted from LSB to

MSB order (in ADINS). A single conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel

(See Table 15 ). An interrupt, if enabled, will be generated after all selected channels have

been converted. If only a single channel is selected this is equivalent to single channel, single conversion mode.This mode is selected by setting the SCANx bit in the ADMODA register.

3.2.3.4

Auto scan, continuous conversion mode

Any combination of the four input channels can be selected for conversion by setting a channel’s respective bit in the ADINS register. The channels are converted from LSB to

MSB order (in ADINS). A conversion of each selected input will be performed and the result placed in the result register which corresponds to the selected input channel (See

Table 15

). An interrupt, if enabled, will be generated after all selected channels have been converted. The process will repeat starting with the first selected channel. Additional conversion results will again cycle through the result registers of the selected channels, overwriting the previous results.Continuous conversions continue until terminated by the user.This mode is selected by setting the BURSTx bit in the ADMODA register.

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3.2.3.5

Dual channel, continuous conversion mode

The any combination of two of the four input channels can be selected for conversion. The result of the conversion of the first channel is placed in the first result register. The result of the conversion of the second channel is placed in the second result register.The first channel is again converted and its result stored in the third result register. The second channel is again converted and its result placed in the fourth result register (See

Table 17

). An interrupt is generated, if enabled, after every set of four conversions (two conversions per channel).This mode is selected by setting the SCCx bit in the ADMODA register.

Table 17.

Result registers and conversion results for dual channel, continuous conversion mode

Result register Contains

ADxDAT0

ADxDAT1

ADxDAT2

ADxDAT3

First channel, first conversion result

Second channel, first conversion result

First channel, second conversion result

Second channel, second conversion result

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3.2.3.6

Single step mode

This special mode allows ‘single-stepping’ in an auto scan conversion mode. Any combination of the four input channels can be selected for conversion. After each channel is converted, an interrupt is generated, if enabled, and the A/D waits for the next start condition. The result of each channel is placed in the result register which corresponds to

the selected input channel (See Table 15

). May be used with any of the start modes. This mode is selected by clearing the BURSTx, SCCx, and SCANx bits in the ADMODA register which correspond to the ADC in use.

3.2.3.7

Conversion mode selection bits

Each A/D uses three bits in ADMODA to select the conversion mode for that A/D. These

mode bits are summarized in Table 18 ,below. Combinations of the three bits, other than

the combinations shown, are undefined.

Table 18.

Conversion mode bits

Burst1 SCC1 Scan1 ADC1 conversion mode

Burst0 SCC0 Scan0 ADC0 conversion mode

0

0

0

1

0

0

1

0

0

1

0

0

Single step

Fixed channel, single

Auto scan, single

Fixed channel, continuous

Dual channel, continuous

Auto scan, continuous

0

0

0

1

0

0

1

0

0

1

0

0

Single step

Fixed channel, single

Auto scan, single

Fixed channel, continuous

Dual channel, continuous

Auto scan, continuous

3.2.4 Conversion start modes

3.2.4.1

Timer triggered start

An A/D conversion is started by the overflow of Timer 0. Once a conversion has started, additional Timer 0 triggers are ignored until the conversion has completed. The Timer triggered start mode is available in all A/D operating modes.This mode is selected by the

TMMx bit and the ADCSx1 and ADCSx0 bits (See Table 20

and Table 22

).

3.2.4.2

Start immediately

Programming this mode immediately starts a conversion.This start mode is available in all

A/D operating modes.This mode is selected by setting the ADCSx1 and ADCSx0 bits in the ADCONx register (See

Table 20

and

Table 22

).

3.2.4.3

Edge triggered

An A/D conversion is started by rising or falling edge of P1.4. Once a conversion has started, additional edge triggers are ignored until the conversion has completed. The edge triggered start mode is available in all A/D operating modes.This mode is selected by setting the ADCSx1 and ADCSx0 bits in the ADCONx register (See

Table 20

and

Table 22

).

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3.2.4.4

Dual start immediately

Programming this mode starts a synchronized conversion of both A/D converters.This start mode is available in all A/D operating modes. Both A/D converters must be in the same operating mode. In the autoscan single conversion modes, both A/D converters must select an identical number of channels. Writing a 11 to the ADCSx1, ADCSx0 bits in either ADCONx register will start a simultaneous conversion of both A/Ds. Both A/Ds must be enabled.

3.2.5 Boundary limits interrupt

Each of the A/D converters has both a high and low boundary limit register. The user may select whether an interrupt is generated when the conversion result is within (or equal to) the high and low boundary limits or when the conversion result is outside the boundary limits. An interrupt will be generated, if enabled, if the result meets the selected interrupt criteria. The boundary limit may be disabled by clearing the boundary limit interrupt enable.

An early detection mechanism exists when the interrupt criteria has been selected to be outside the boundary limits. In this case, after the four MSBs have been converted, these four bits are compared with the four MSBs of the boundary high and low registers. If the four MSBs of the conversion meet the interrupt criteria (i.e.- outside the boundary limits) an interrupt will be generated, if enabled. If the four MSBs do not meet the interrupt criteria, the boundary limits will again be compared after all 8 bits have been converted.

The boundary status register (BNDSTA0) flags the channels which caused a boundary interrupt.

3.2.6 DAC output to a port pin with high output impedance

Each A/D converter’s DAC block can be output to a port pin. In this mode, the ADxDAT3 register is used to hold the value fed to the DAC. After a value has been written to the

DAC (written to ADxDAT3), the DAC output will appear on the channel 3 pin. The DAC output is enabled by the ENDAC1 and ENDAC0 bits in the ADMODB register (See

Table 26

).

3.2.7 Clock divider

The A/D converter requires that its internal clock source be in the range of 320kHz to

8MHz to maintain accuracy. A programmable clock divider that divides the clock from 1 to

8 is provided for this purpose (See Table 26 ).

3.2.8 I/O pins used with ADC functions

The analog input pins maybe be used as either digital I/O or as inputs to A/D through PGA and thus have a digital input and output function. In order to give the best analog performance, pins that are being used with the ADC should have their digital outputs and inputs disabled and have the 5V tolerance disconnected. Digital outputs are disabled by putting the port pins into the input-only mode as described in the Port Configurations section (see

Table 42

). Digital inputs will be disconnected automatically from these pins when the pin has been selected by setting its corresponding bit in the ADINS register and its corresponding A/D has been enabled.

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When used as digital I/O these pins are 5 V tolerant. If selected as input signals in ADINS, these pins will be 3V tolerant if the corresponding A/D is enabled and the device is not in power down. Otherwise the pin will remain 5V tolerant. Please refer to the

P89LPC9331/9341/9351 data sheet for specifications.

3.2.9 Power-down and Idle mode

In Idle mode the A/D converter, if enabled, will continue to function and can cause the device to exit Idle mode when the conversion is completed if the A/D interrupt is enabled.

If PGAs, temperature sensor or A/D is enabled, it will consume power. Power can be reduced by disabling the PGAs, temperature sensor and A/D. If ADC is configured to be in power down mode via PCONA.4, the internal clock to the ADC is disabled. During ADC0 power down mode, configuration of PGA0 can not be changed by writing to the

PGACON0 register. However, PGA1 can still be configured if either the ADC1 or the analog comparator is enabled or running. To fully power-down the ADC, the user should clear the ENADC bits in ADCONx registers. PGA can be disabled via clearing ENPGAx bit and temperature sensor can be disabled via setting TSEL1/0 not to ‘10’.

In Power-down mode or Total Power-down mode, the A/D, PGA and Temp sensor do not function.

Table 19.

A/D Control register 0 (ADCON0 - address 8Eh) bit allocation

Bit

Symbol

Reset

7

ENBI0

0

6

ENADCI0

0

5

TMM0

0

4

EDGE0

0

3

ADCI0

0

2

ENADC0

0

1

ADCS01

0

0

ADCS00

0

Table 20.

A/D Control register 0 (ADCON0 - address 97h) bit description

Bit

1:0

Symbol Description

ADCS01,ADCS00 A/D start mode bits, see below.

2

3

4

5

6

7

ENADC0

ADCI0

EDGE0

TMM0

ENADCI0

ENBI0

00 — Timer Trigger Mode when TMM0 = 1. Conversions starts on overflow of Timer

0. When TMM0 =0, no start occurs (stop mode).

01 — Immediate Start Mode. Conversion starts immediately.

10 — Edge Trigger Mode. Conversion starts when edge condition defined by bit

EDGE0 occurs.

Enable ADC0. When set = 1, enables ADC0, when = 0, the ADC is in power-down.

A/D Conversion complete Interrupt 0. Set when any conversion or set of multiple conversions has completed. Cleared by software.

An edge conversion start is triggered by a falling edge on P1.4 when EDGE0 =0 while in edge-triggered mode. An edge conversion start is triggered by a rising edge on P1.4 when EDGE0 =1 while in edge-triggered mode.

Timer Trigger Mode 0. Selects either stop mode (TMM0 = 0) or timer trigger mode

(TMM0 = 1) when the ADCS01 and ADCS00 bits = 00.

Enable A/D Conversion complete Interrupt 0. When set, will cause an interrupt if the

ADCI0 flag is set and the A/D interrupt is enabled.

Enable A/D boundary interrupt 0. When set, will cause an interrupt if the boundary interrupt 0 flag, BNDI0, is set and the A/D interrupt is enabled.

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Table 21.

A/D Control register 1(ADCON1 - address 97h) bit allocation

Bit

Symbol

Reset

7

ENBI1

0

6

ENADCI1

0

5

TMM1

0

4

EDGE1

0

3

ADCI1

0

Table 23.

A/D Mode register A (ADMODA - address 0C0h) bit allocation

Bit

Symbol

Reset

7

BNDI1

0

6

BURST1

0

5

SCC1

0

4

SCAN1

0

3

BNDI0

0

2

ENADC1

0

Table 22.

A/D Control register 1(ADCON1 - address 97h) bit description

Bit

1:0

Symbol Description

ADCS11,ADCS10 A/D start mode bits, see below.

2

3

4

5

6

7

ENADC1

ADCI1

EDGE1

TMM1

ENADCI1

ENBI1

00 — Timer Trigger Mode when TMM1 = 1. Conversions starts on overflow of Timer

0. When TMM1 =0, no start occurs (stop mode).

01 — Immediate Start Mode. Conversion starts immediately.

10 — Edge Trigger Mode. Conversion starts when edge condition defined by bit

EDGE1 occurs.

11 — Dual Immediate Start Mode. Both ADC’s start a conversion immediately.

Enable A/D channel 1. When set = 1, enables ADC1. Must also be set for D/A operation of this channel.

A/D Conversion complete Interrupt 1. Set when any conversion or set of multiple conversions has completed. Cleared by software.

When = 0, an Edge conversion start is triggered by a falling edge on P1.4 When = 1, an Edge conversion start is triggered by a rising edge on P1.4.

Timer Trigger Mode 1. Selects either stop mode (TMM1 = 0) or timer trigger mode

(TMM1 = 1) when the ADCS11 and ADCS10 bits = 00.

Enable A/D Conversion complete Interrupt 1. When set, will cause an interrupt if the

ADCI1 flag is set and the A/D interrupt is enabled.

Enable A/D boundary interrupt 1. When set, will cause and interrupt if the boundary interrupt 1flag, BNDI1, is set and the A/D interrupt is enabled.

2

BURST0

0

1

ADCS11

0

1

SCC0

0

0

ADCS10

0

0

SCAN0

0

6

7

4

5

1

2

3

Table 24.

A/D Mode register A (ADMODA - address 0C0h) bit description

Bit

0

Symbol

SCAN0

Description

When = 1, selects single conversion mode (auto scan or fixed channel) for ADC0

SCC0

BURST0

BNDI0

When = 1, selects fixed channel, continuous conversion mode for ADC0

When = 1, selects auto scan, continuous conversion mode for ADC0

ADC0 boundary interrupt flag. When set, indicates that the converted result is outside of the range defined by the ADC0 boundary registers

SCAN1

SCC1

BURST1

BNDI1

When = 1, selects single conversion mode (auto scan or fixed channel) for ADC1.

When = 1, selects fixed channel, continuous conversion mode for ADC1.

When = 1, selects auto scan, continuous conversion mode for ADC1.

ADC1 boundary interrupt flag. When set, indicates that the converted result is outside of the range defined by the ADC1 boundary registers.

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Table 25.

A/D Mode register B (ADMODB - address A1h) bit allocation

Bit

Symbol

Reset

7

CLK2

0

6

CLK1

0

5

CLK0

0

4

INBND0

0

3

ENDAC1

0

Table 27.

A/D Input select (ADINS - address A3h) bit allocation

Bit 7 6 5 4 3

Symbol

Reset

AIN13

0

AIN12

0

AIN11

0

AIN10

0

AIN03

0

2

ENDAC0

0

2

3

4

Table 26.

A/D Mode register B (ADMODB - address A1h) bit description

Bit

0

Symbol

BSA0

Description

ADC0 Boundary Select All. When =1, BNDI0 will be set if any ADC0 input exceeds the boundary limits. When = 0, BNDI0 will be set only if the AD00 input exceeded the boundary limits.

1 BSA1

ENDAC0

ENDAC1

INBND0

ADC1 Boundary Select All. When =1, BNDI1 will be set if any ADC1 input exceeds the boundary limits. When = 0, BNDI1 will be set only if the AD10 input exceeded the boundary limits.

When =1 selects DAC mode for ADC0; when = 0 selects ADC mode.

When =1 selects DAC mode for ADC1; when = 0 selects ADC mode.

When set = 1, generates an interrupt if the conversion result is inside or equal to the boundary limits. When cleared = 0, generates an interrupt if the conversion result is outside the boundary limits.

7:5 CLK2,CLK1,CLK0 Clock divider to produce the ADC clock. Divides CCLK by the value indicated below.

The resulting ADC clock should be 8 MHz or less. A minimum of 0.5 MHz is required to maintain A/D accuracy.

CLK2:0 — Divisor

000 — 1

001 — 2

010 — 3

011 — 4

100 — 5

101 — 6

110 — 7

111 — 8

2

AIN02

0

1

BSA1

0

1

AIN01

0

0

BSA0

0

0

AIN00

0

6

7

4

5

2

3

0

1

Table 28.

A/D Input select (ADINS - address A3h) bit description


AIN00

AIN01

AIN02

AIN03

When set, enables the Anin00 pin for sampling and conversion.




AIN10

AIN11

AIN12

AIN13





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Table 29.

Temperature Sensor control register (TPSCON - address FFCAh) bit allocation (P89LPC9331/9341)

Bit

Symbol

Reset

-

7

0

-

6

0

-

5

0

-

4

0

3

TSEL1

0

2

TSEL0

0

-

1

0

-

0

0

Table 30.

Temperature Sensor control register (TPSCON - address FFCAh) bit description (P89LPC9331/9341)

Bit

1:0

3:2

-

Symbol

TSEL1, TSEL0

Description

Reserved

Temperature sensor mux selection. Select among temperature sensor, internal reference voltage and AD03

4:7 -

00 : AD03

01 : internal reference voltage

10 : temperature sensor enabled and selected

11 : AD03

Reserved

Table 31.

PGA0 Control register (PGACON0 - address FFCAh) bit allocation (P89LPC9351)

Bit 7 6 5 4 3 2 1

Symbol

Reset

ENPGA0

0

PGASEL01 PGASEL00 PGATRIM0 TSEL1

0 0 0 0

TSEL0

0

PGAG01

0

0

PGAG00

0

Table 32.

PGA0 Control register (PGACON0 - address FFCAh) bit description (P89LPC9351)


1:0 PGAG01,

PGAG00

PGA Gain selection bits.

3:2

4

6:5

TSEL1, TSEL0

PGATRIM0

PGASEL01,

PGASEL00

00 : Gain = 2

01 : Gain = 4

10 : Gain = 8

11 : Gain = 16

Temperature sensor mux selection. Select among temperature sensor, internal reference voltage and AD03

00 : AD03

01 : internal reference voltage

10 : temperature sensor enabled and selected

11 : AD03

PGA0 trim enable bit. If set, PGA0 is grounded for calibration mode. If cleared, normal operation mode.

PGA input channel selection

7 ENPGA0

00 : AD00 using PGA

01 : AD01 using PGA

10 : AD02 using PGA

11 : AD03/Bandgap/Temperature sensor using PGA

PGA0 enable. If set, enable PGA0. If cleared, disable PGA0.

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Table 33.

PGA1 Control register (PGACON1 - address FFE1h) bit allocation (P89LPC9351)

Bit

Symbol

Reset

7

ENPGA1

0

6

PGASEL11

0

5

PGASEL10

0

4

PGATRIM1

0

-

3

0

-

2

0 0

1

PGAG11

0

PGAG10

0

Table 34.

PGA1 Control register (PGACON1 - address FFE1h) bit description (P89LPC9351)

Bit

1:0

Symbol

PGAG11,PGAG10

Description

PGA Gain selection bits.

3:2

4

6:5

-

PGATRIM1

PGASEL11,

PGASEL10

00 : Gain = 2

01 : Gain = 4

10 : Gain = 8

11 : Gain = 16 reserved

PGA1 trim enable bit. If set, PGA1 is grounded for calibration mode. If cleared, normal operation mode.

PGA input channel selection

7 ENPGA1

00 : AD10 using PGA

01 : AD11 using PGA

10 : AD12 using PGA

11 : AD13 using PGA

PGA1 enable. If set, enable PGA1. If cleared, disable PGA1.

Table 35.

PGA0 Control register B (PGACON0B - address FFCEh) bit allocation (P89LPC9351)

Bit 7 6 5 4 3 2 1

Symbol

Reset

-

0

-

0

-

0

-

0

-

0

-

0

-

0

0

PGAENOFF0

0

Table 36.

PGA0 Control register B (PGACON0B - address FFCEh) bit description (P89LPC9351)


0

1:7 -

PGAENOFF0 PGA offset voltage enable bit. When set, enable the offset voltage on the PGA.

Reserved

Table 37.

PGA1 Control register B (PGACON1B - address FFE4h) bit allocation (P89LPC9351)

Bit 7 6 5 4 3 2 1

Symbol

Reset

-

0

-

0

-

0

-

0

-

0

-

0

-

0

0

PGAENOFF1

0

Table 38.

PGA1 Control register B (PGACON1B - address FFE4h) bit description (P89LPC9351)


0

1:7 -

PGAENOFF1 PGA offset voltage enable bit. When set, enable the offset voltage on the PGA.

Reserved

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4.

Interrupts

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The P89LPC9331/9341/9351 uses a four priority level interrupt structure. This allows great flexibility in controlling the handling of the P89LPC9331/9341/9351’s 15 interrupt sources.

Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global enable bit, EA, which enables all interrupts.

Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt service cannot be interrupted by any other interrupt source. If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced.

If requests of the same priority level are pending at the start of an instruction cycle, an internal polling sequence determines which request is serviced. This is called the arbitration ranking. Note that the arbitration ranking is only used for pending requests of the same priority level.

Table 40 summarizes the interrupt sources, flag bits, vector

addresses, enable bits, priority bits, arbitration ranking, and whether each interrupt may wake-up the CPU from a Power-down mode.

4.1 Interrupt priority structure

Table 39.

Interrupt priority level

Priority bits

0

1

IPxH

0

1

IPx

0

1

0

1

Interrupt priority level

Level 0 (lowest priority)

Level 1

Level 2

Level 3

There are four SFRs associated with the four interrupt levels: IP0, IP0H, IP1, IP1H. Every interrupt has two bits in IPx and IPxH (x = 0, 1) and can therefore be assigned to one of four levels, as shown in

Table 40

.

The P89LPC9331/9341/9351 has two external interrupt inputs in addition to the Keypad

Interrupt function. The two interrupt inputs are identical to those present on the standard

80C51 microcontrollers.

These external interrupts can be programmed to be level-triggered or edge-triggered by clearing or setting bit IT1 or IT0 in Register TCON. If ITn = 0, external interrupt n is triggered by a low level detected at the INTn pin. If ITn = 1, external interrupt n is edge triggered. In this mode if consecutive samples of the INTn pin show a high level in one cycle and a low level in the next cycle, interrupt request flag IEn in TCON is set, causing an interrupt request.

Since the external interrupt pins are sampled once each machine cycle, an input high or low level should be held for at least one machine cycle to ensure proper sampling. If the external interrupt is edge-triggered, the external source has to hold the request pin high

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for at least one machine cycle, and then hold it low for at least one machine cycle. This is to ensure that the transition is detected and that interrupt request flag IEn is set. IEn is automatically cleared by the CPU when the service routine is called.

If the external interrupt is level-triggered, the external source must hold the request active until the requested interrupt is generated. If the external interrupt is still asserted when the interrupt service routine is completed, another interrupt will be generated. It is not necessary to clear the interrupt flag IEn when the interrupt is level sensitive, it simply tracks the input pin level.

If an external interrupt has been programmed as level-triggered and is enabled when the

P89LPC9331/9341/9351 is put into Power-down mode or Idle mode, the interrupt

occurrence will cause the processor to wake-up and resume operation. Refer to Section

6.3 “Power reduction modes” for details. Note: the external interrupt must be programmed

as level-triggered to wake-up from Power-down mode.

4.2 External Interrupt pin glitch suppression

Most of the P89LPC9331/9341/9351 pins have glitch suppression circuits to reject short glitches (please refer to the P89LPC9331/9341/9351 data sheet, Dynamic characteristics for glitch filter specifications). However, pins SDA/INT0/P1.3 and SCL/T0/P1.2 do not have the glitch suppression circuits. Therefore, INT1 has glitch suppression while INT0 does not.

Table 40.

Summary of interrupts

Description

External interrupt 0

Timer 0 interrupt

External interrupt 1

Timer 1 interrupt

Serial port Tx and Rx

Serial port Rx

Brownout detect

Watchdog timer/Real-time clock

I

2

C interrupt

KBI interrupt

Comparators 1 and 2 interrupts

SPI interrupt

Capture/Compare Unit

(P89LPC9351)

Serial port Tx

ADC, Data EEPROM write complete (P89LPC9351)

Interrupt flag bit(s)

IE0

TF0

IE1

0003h

000Bh

0013h

TF1

TI and RI

001Bh

0023h

RI

BOIF 002Bh

WDOVF/RTCF 0053h

SI

KBIF

CMF1/CMF2

SPIF

TI

ADCI1, BNDI1

Vector address

Interrupt enable bit(s)

Interrupt priority

Arbitration ranking

Power- down wake-up

IP0H.0, IP0.0

1 (highest) Yes EX0 (IEN0.0)

ET0 (IEN0.1)

EX1 (IEN0.2)

IP0H.1, IP0.1

4

IP0H.2, IP0.2

7

ET1 (IEN0.3) IP0H.3, IP0.3

10

ES/ESR (IEN0.4) IP0H.4, IP0.4

13

No

Yes

No

No

0033h

003Bh

0043h

004Bh

005Bh

006Bh

0073h

EBO (IEN0.5)

EWDRT (IEN0.6)

EI2C (IEN1.0)

EKBI (IEN1.1)

EC (IEN1.2)

ESPI (IEN1.3)

ECCU(IEN1.4)

EST (IEN1.6)

EAD (IEN1.7)

IP0H.5, IP0.5

IP0H.6, IP0.6

IP1H.0, IP1.0

IP1H.1, IP1.1

IP1H.2, IP1.2

IP1H.3, IP1.3

IP1H.4, IP1.4

IP1H.6, IP1.6

IP1H.7, IP1.7

2

3

5

8

11

14

6

12

15 (lowest)

Yes

Yes

No

Yes

Yes

No

No

No

No

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RTCF

ERTC

(RTCCON.1)

WDOVF

EWDRT

CMF2

CMF1

EC

EA (IE0.7)

TF0

ET0

TF1

ET1

TI & RI/RI

ES/ESR

TI

EST

SI

EI2C

SPIF

ESPI any CCU interrupt

(1)

ECCU

IE0

EX0

IE1

EX1

BOIF

EBO

KBIF

EKBI

EEIF

(2)

ENADCI0

ADCI0

ENADCI1

ADCI1

ENBI0

BNDI0

ENBI1

BNDI1

EADEE

(2)

EAD

(3)

(1) See Section 10

.

(2) P89LPC9351

(3) P89LPC9331/9341

Fig 13. Interrupt sources, interrupt enables, and power-down wake-up sources

002aad560 wake-up

(if in power-down) interrupt to CPU

5.

I/O ports

The P89LPC9331/9341/9351 has four I/O ports: Port 0, Port 1, Port 2, and Port 3. Ports 0,

1,and 2 are 8-bit ports, and Port 3 is a 2-bit port. The exact number of I/O pins available

depends upon the clock and reset options chosen (see Table 41 ).

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Table 41.

Number of I/O pins available

Clock source

On-chip oscillator or watchdog oscillator

Reset option

No external reset (except during power up) 26

External RST pin supported

Number of I/O pins

25

External clock input No external reset (except during power up) 25

External RST pin supported 24

Low/medium/high speed oscillator

(external crystal or resonator)

No external reset (except during power up) 24

External RST pin supported 23

5.1 Port configurations

All but three I/O port pins on the P89LPC9331/9341/9351 may be configured by software

to one of four types on a pin-by-pin basis, as shown in Table 42 . These are:

quasi-bidirectional (standard 80C51 port outputs), push-pull, open drain, and input-only.

Two configuration registers for each port select the output type for each port pin.

P1.5 (RST) can only be an input and cannot be configured.

P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be configured to be either input-only or open drain.

0

1

1

Table 42.

Port output configuration settings

PxM1.y

0

PxM2.y

0

Port output mode

Quasi-bidirectional

1

0

1

Push-pull

Input only (high-impedance)

Open drain

5.2 Quasi-bidirectional output configuration

Quasi-bidirectional outputs can be used both as an input and output without the need to reconfigure the port. This is possible because when the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. When the pin is driven low, it is driven strongly and able to sink a large current. There are three pull-up transistors in the quasi-bidirectional output that serve different purposes.

One of these pull-ups, called the ‘very weak’ pull-up, is turned on whenever the port latch for the pin contains a logic 1. This very weak pull-up sources a very small current that will pull the pin high if it is left floating.

A second pull-up, called the ‘weak’ pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level. This pull-up provides the primary source current for a quasi-bidirectional pin that is outputting a 1. If this pin is pulled low by an external device, the weak pull-up turns off, and only the very weak pull-up remains on. In order to pull the pin low under these conditions, the external device has to sink enough current to overpower the weak pull-up and pull the port pin below its input threshold voltage.

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port latch data

The third pull-up is referred to as the ‘strong’ pull-up. This pull-up is used to speed up low-to-high transitions on a quasi-bidirectional port pin when the port latch changes from a logic 0 to a logic 1. When this occurs, the strong pull-up turns on for two CPU clocks quickly pulling the port pin high.

The quasi-bidirectional port configuration is shown in Figure 14

.

Although the P89LPC9331/9341/9351 is a 3 V device most of the pins are 5 V-tolerant. If

5 V is applied to a pin configured in quasi-bidirectional mode, there will be a current flowing from the pin to V

DD

causing extra power consumption. Therefore, applying 5 V to pins configured in quasi-bidirectional mode is discouraged.

A quasi-bidirectional port pin has a Schmitt-triggered input that also has a glitch suppression circuit

(Please refer to the P89LPC9331/9341/9351 data sheet, Dynamic characteristics for glitch filter specifications).

V

DD

2 CPU

CLOCK DELAY

P strong

P very weak

P weak port pin input data

002aaa914 glitch rejection

Fig 14. Quasi-bidirectional output

5.3 Open drain output configuration

The open drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port pin when the port latch contains a logic 0. To be used as a logic output, a port configured in this manner must have an external pull-up, typically a resistor tied to V

DD

. The pull-down for this mode is the same as for the quasi-bidirectional mode.

The open drain port configuration is shown in

Figure 15

.

An open drain port pin has a Schmitt-triggered input that also has a glitch suppression circuit.

Please refer to the P89LPC9331/9341/9351 data sheet, Dynamic characteristics for glitch filter specifications.

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port pin port latch data input data glitch rejection

002aaa915

Fig 15. Open drain output

5.4 Input-only configuration

The input port configuration is shown in

Figure 16

. It is a Schmitt-triggered input that also has a glitch suppression circuit.


input data port pin glitch rejection

002aaa916

Fig 16. Input only

5.5 Push-pull output configuration

The push-pull output configuration has the same pull-down structure as both the open drain and the quasi-bidirectional output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. The push-pull mode may be used when more source current is needed from a port output.

The push-pull port configuration is shown in Figure 17

.

A push-pull port pin has a Schmitt-triggered input that also has a glitch suppression circuit.


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P

V

DD strong

N port pin port latch data

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input data glitch rejection

002aaa917

Fig 17. Push-pull output

5.6 Port 0 and Analog Comparator functions

The P89LPC9331/9341/9351 incorporates two Analog Comparators. In order to give the best analog performance and minimize power consumption, pins that are being used for analog functions must have both the digital outputs and digital inputs disabled.

Digital outputs are disabled by putting the port pins into the input-only mode as described

in the Port Configurations section (see Figure 16

).

Digital inputs on Port 0 may be disabled through the use of the PT0AD register. Bits 1 through 5 in this register correspond to pins P0.1 through P0.5 of Port 0, respectively.

Setting the corresponding bit in PT0AD disables that pin’s digital input. Port bits that have their digital inputs disabled will be read as 0 by any instruction that accesses the port.

On any reset, PT0AD bits 1 through 5 default to logic 0s to enable the digital functions.

5.7 Additional port features

After power-up, all pins are in Input-Only mode. Please note that this is different from

the LPC76x series of devices.

•

After power-up, all I/O pins except P1.5, may be configured by software.

•

Pin P1.5 is input only. Pins P1.2 and P1.3 are configurable for either input-only or open drain.

Every output on the P89LPC9331/9341/9351 has been designed to sink typical LED drive current. However, there is a maximum total output current for all ports which must not be exceeded. Please refer to the P89LPC9331/9341/9351 data sheet for detailed specifications.

All ports pins that can function as an output have slew rate controlled outputs to limit noise generated by quickly switching output signals. The slew rate is factory-set to approximately 10 ns rise and fall times.

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P1.5

P1.6

P1.7

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

P3.0

P3.1

P0.5

P0.6

P0.7

P1.0

P1.1

P1.2

P1.3

P1.4

Table 43.

Port output configuration

Port pin Configuration SFR bits

PxM1.y

PxM2.y

P0.0

P0.1

P0.2

P0.3

P0.4

P0M1.0

P0M1.1

P0M1.2

P0M1.3

P0M1.4

P0M2.0

P0M2.1

P0M2.2

P0M2.3

P0M2.4

P1M1.5

P1M1.6

P1M1.7

P2M1.0

P2M1.1

P2M1.2

P2M1.3

P2M1.4

P0M1.5

P0M1.6

P0M1.7

P1M1.0

P1M1.1

P1M1.2

P1M1.3

P1M1.4

P2M1.5

P2M1.6

P2M1.7

P3M1.0

P3M1.1

P0M2.5

P0M2.6

P0M2.7

P1M2.0

P1M2.1

P1M2.2

P1M2.3

P1M2.4

P1M2.5

P1M2.6

P1M2.7

P2M2.0

P2M2.1

P2M2.2

P2M2.3

P2M2.4

P2M2.5

P2M2.6

P2M2.7

P3M2.0

P3M2.1

Alternate usage Notes

KBI0, CMP2, AD01

KBI1, CIN2B, AD10

Refer to Section 5.6 “Port 0 and

KBI2, CIN2A, AD11

Analog Comparator functions” for

usage as analog inputs.

KBI3, CIN1B, AD12

KBI4, CIN1A, AD13,

DAC1

KBI5, CMPREF

KBI6, CMP1

KBI7, T1

TXD

RXD

T0, SCL Input-only or open-drain input-only or open-drain INT0, SDA

INT1

RST

OCB

OCC, AD00

ICB, AD03, DAC0

OCD, AD02

MOSI

MISO

SS

SPICLK

OCA

ICA

CLKOUT, XTAL2

XTAL1

6.

Power monitoring functions

The P89LPC9331/9341/9351 incorporates power monitoring functions designed to prevent incorrect operation during initial power-on and power loss or reduction during operation. This is accomplished with two hardware functions: Power-on Detect and

Brownout Detect.

6.1 Brownout detection

The brownout detect function determines if the power supply voltage drops below a certain level. Enhanced BOD has 3 independent functions: BOD reset, BOD interrupt and

BOD EEPROM/FLASH.

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BOD reset will cause a processor reset and it is always on, except in total power-down mode. It could not be disabled in software. BOD interrupt will generate an interrupt and could be enabled or disabled in software.

BOD reset and BOD interrupt, each has 4 trip voltage levels. BOE1 bit (UCFG1.5) and

BOE0 bit (UCFG1.3) are used as trip point configuration bits of BOD reset. BOICFG1 bit and BOICFG0 bit in register BODCFG are used as trip point configuration bits of BOD

interrupt. BOD reset voltage should be lower than BOD interrupt trip point. Table 44

gives

BOD trip points configuration.

In total power-down mode (PMOD1/PMOD0 = '11'), the circuitry for the Brownout

Detection is disabled for lowest power consumption. When PMOD1/PMOD0 not equal to

'11', BOD reset is always on and BOD interrupt is enabled by setting BOI (PCON.4) bit.

Please refer

Table 45

for BOD reset and BOD interrupt configuration. BOF bit

(RSTSRC.5), BOD reset flag is default as '0' and is set when BOD reset is tripped. BOIF bit (RSTSRC.6), BOD interrupt flag is default as '0' and is set when BOD interrupt is tripped.

BOD EEPROM/FLASH is used for flash/Data EEPROM program/erase protection. BOD

EEPROM/FLASH is always on, except in power-down or total power down mode

(PCON.1=1). It can not be disabled in software. BOD EEPROM/FLASH has only 1 trip voltage level of 2.4 V. When voltage supply is lower than 2.4 V, the BOD

EEPROM/FLASH is tripped and flash/Data EEPROM program/erase is blocked.

If brownout detection is enabled the brownout condition occurs when V

DD

falls below the brownout trip voltage and is negated when V

DD

rises above the brownout trip voltage.

For correct activation of Brownout Detect, certain V

DD

rise and fall times must be observed. Please see the data sheet for specifications.

1

1

1

1

0

0

0

0

1

1

1

1

0

0

0

0

Table 44.

BOD Trip points configuration

BOE1

(UCFG1.5)

BOE0

(UCFG1.3)

BOICFG1

(BOICFG.1)

0

0

0

0

0

0

1

1

1

1

1

1

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

BOICFG0

(BOICFG.0)

BOD Reset BOD

Interrupt

Reserved

2.2V

2.2V

2.2V

Reserved

2.4V

2.4V

Reserved

3.0V

2.4V

2.6V

3.2V

2.6V

3.2V

3.2V

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Table 45.

BOD Reset and BOD Interrupt configuration

PMOD1/PMOD0(PCON[1:0]) BOI

(PCON.4)

EBO

(IEN0.5)

11 (total power-down)

≠ 11 (any mode other than total power down)

X

0

1

X

X

0

X

1

0

1

X

X

EA

(IEN0.7)

X

Y

Y

Y

Y

BOD

Reset

N

BOD

Interrupt

N

N

N

N

Y

6.2 Power-on detection

The Power-On Detect has a function similar to the Brownout Detect, but is designed to work as power initially comes up, before the power supply voltage reaches a level where the Brownout Detect can function. The POF flag (RSTSRC.4) is set to indicate an initial power-on condition. The POF flag will remain set until cleared by software by writing a logic 0 to the bit. BOF (RSTSRC.5) will be set when POF is set.

6.3 Power reduction modes

The P89LPC9331/9341/9351 supports three different power reduction modes as

determined by SFR bits PCON[1:0] (see Table 46

).

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Table 46.

Power reduction modes

PMOD1

(PCON.1)

0

PMOD0

(PCON.0)

0

Description

Normal mode (default) - no power reduction.

0 1 Idle mode. The Idle mode leaves peripherals running in order to allow them to activate the processor when an interrupt is generated. Any enabled interrupt source or reset may terminate Idle mode.

1 0

1 1

Power-down mode:

The Power-down mode stops the oscillator in order to minimize power consumption.

The P89LPC9331/9341/9351 exits Power-down mode via any reset, or certain interrupts - external pins INT0/INT1, brownout Interrupt, keyboard, Real-time Clock/System Timer), watchdog, and comparator trips. Waking up by reset is only enabled if the corresponding reset is enabled, and waking up by interrupt is only enabled if the corresponding interrupt is enabled and the EA SFR bit

(IEN0.7) is set. External interrupts should be programmed to level-triggered mode to be used to exit

Power-down mode.

In Power-down mode the internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock AND the RTC is enabled.

In Power-down mode, the power supply voltage may be reduced to the RAM keep-alive voltage

VRAM. This retains the RAM contents at the point where Power-down mode was entered. SFR contents are not guaranteed after V

DD

has been lowered to VRAM, therefore it is recommended to wake-up the processor via Reset in this situation. V

DD

must be raised to within the operating range before the Power-down mode is exited.

When the processor wakes up from Power-down mode, it will start the oscillator immediately and begin execution when the oscillator is stable. Oscillator stability is determined by counting 1024

CPU clocks after start-up when one of the crystal oscillator configurations is used, or 200ms to

300ms after start-up for the internal RC, or 32 OSCCLK cycles after start-up for external clock input.

Some chip functions continue to operate and draw power during Power-down mode, increasing the total power used during power-down. These include:

•

Brownout Detect

•

Watchdog Timer if WDCLK (WDCON.0) is logic 1.

•

Comparators (Note: Comparators can be powered down separately with PCONA.5 set to logic 1 and comparators disabled);

•

Real-time Clock/System Timer (and the crystal oscillator circuitry if this block is using it, unless

RTCPD, i.e., PCONA.7 is logic 1).

Total Power-down mode: This is the same as Power-down mode except that the Brownout

Detection circuitry and the voltage comparators are also disabled to conserve additional power.

Note that a brownout reset or interrupt will not occur. Voltage comparator interrupts and Brownout interrupt cannot be used as a wake-up source. The internal RC oscillator is disabled unless both the RC oscillator has been selected as the system clock AND the RTC is enabled.

The following are the wake-up options supported:

•

Watchdog Timer if WDCLK (WDCON.0) is logic 1. Could generate Interrupt or Reset, either one can wake up the device

•

External interrupts INT0/INT1 (when programmed to level-triggered mode).

•

Keyboard Interrupt

•

Real-time Clock/System Timer (and the crystal oscillator circuitry if this block is using it, unless

RTCPD, i.e., PCONA.7 is logic 1).

Note: Using the internal RC-oscillator to clock the RTC during power-down may result in relatively high power consumption. Lower power consumption can be achieved by using an external low frequency clock when the Real-time Clock or watchdog timer is running during power-down.

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Table 47.

Power Control register (PCON - address 87h) bit allocation

Bit

Symbol

Reset

7

SMOD1

0

6

SMOD0

0

-

-

5 4

BOI

0

3

GF1

0

2

GF0

0

1

PMOD1

0

0

PMOD0

0

Table 48.

Power Control register (PCON - address 87h) bit description

Bit

0

Symbol

PMOD0

Description

Power Reduction Mode (see

Section 6.3

)

1

2

PMOD1

GF0

3

4

5

6

-

GF1

BOI

SMOD0

General Purpose Flag 0. May be read or written by user software, but has no effect on operation

General Purpose Flag 1. May be read or written by user software, but has no effect on operation

Brownout Detect Interrupt Enable. When logic 1, Brownout Detection will generate a interrupt.

Reserved.

Framing Error Location:

•

When logic 0, bit 7 of SCON is accessed as SM0 for the UART.

•

When logic 1, bit 7 of SCON is accessed as the framing error status (FE) for the

UART

7 SMOD1 Double Baud Rate bit for the serial port (UART) when Timer 1 is used as the baud rate source. When logic 1, the Timer 1 overflow rate is supplied to the UART. When logic 0, the Timer 1 overflow rate is divided by two before being supplied to the

UART. (See Section 11

)

Table 49.

Power Control register A (PCONA - address B5h) bit allocation

Bit

Symbol

Reset

7

RTCPD

0

6

DEEPD

0

5

VCPD

0

4

ADPD

0

3

I2PD

0

2

SPPD

0

1

SPD

0

0

0

CCUPD

Table 50.

Power Control register A (PCONA - address B5h) bit description


0 CCUPD Compare/Capture Unit (CCU) power-down: When logic 1, the internal clock to the

CCU is disabled. Note that in either Power-down mode or Total Power-down mode, the CCU clock will be disabled regardless of this bit. (Note: This bit is overridden by the CCUDIS bit in FCFG1. If CCUDIS = 1, CCU is powered down.)(P89LPC9351)

1

2

3

4

SPD

SPPD

I2PD

ADPD

Serial Port (UART) power-down: When logic 1, the internal clock to the UART is disabled. Note that in either Power-down mode or Total Power-down mode, the

UART clock will be disabled regardless of this bit.

SPI power-down: When logic 1, the internal clock to the SPI is disabled. Note that in either Power-down mode or Total Power-down mode, the SPI clock will be disabled regardless of this bit.

I

2

C power-down: When logic 1, the internal clock to the I

2

C-bus is disabled. Note that in either Power-down mode or Total Power-down mode, the I

2

C clock will be disabled regardless of this bit.

A/D Converter Power down: When ‘1’, turns off the clock to the ADC. To fully power-down the ADC, the user should also set the ENADC1 and ENADC0 bits in registers ADCON1 and ADCON0.

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Table 50.

Power Control register A (PCONA - address B5h) bit description

…continued

Bit

5

Symbol

VCPD

Description

Analog Voltage Comparators power-down: When logic 1, the voltage comparators are powered down. User must disable the voltage comparators prior to setting this bit.

6

7

DEEPD

RTCPD

Data EEPROM power-down: When logic 1, the Data EEPROM is powered down.

Note that in either Power-down mode or Total Power-down mode, the Data

EEPROM will be powered down regardless of this bit.

Real-time Clock power-down: When logic 1, the internal clock to the Real-time

Clock is disabled.

7.

Reset

The P1.5/RST pin can function as either an active low reset input or as a digital input,

P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to 1, enables the external reset input function on P1.5. When cleared, P1.5 may be used as an input pin.

Remark: During a power-on sequence, The RPE selection is overridden and this pin will always functions as a reset input. An external circuit connected to this pin should not hold this pin low during a Power-on sequence as this will keep the device in reset. After power-on this input will function either as an external reset input or as a digital input as defined by the RPE bit. Only a power-on reset will temporarily override the selection defined by RPE bit. Other sources of reset will not override the RPE bit.

Note: During a power cycle, V

DD

must fall below V

POR

(see P89LPC9331/9341/9351 data

sheet, Static characteristics) before power is reapplied, in order to ensure a power-on reset.

Reset can be triggered from the following sources:

•

External reset pin (during power-on or if user configured via UCFG1);

•

Power-on detect;

•

Brownout detect;

•

Watchdog timer;

•

Software reset;

•

UART break character detect reset.

For every reset source, there is a flag in the Reset Register, RSTSRC. The user can read this register to determine the most recent reset source. These flag bits can be cleared in software by writing a ‘0’ to the corresponding bit. More than one flag bit may be set:

•

During a power-on reset, both POF and BOF are set but the other flag bits are cleared.

•

A watchdog reset is similar to a power-on reset, both POF and BOF are set but the other flag bits are cleared.

•

For any other reset, previously set flag bits that have not been cleared will remain set.

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RPE (UCFG1.6)

RST pin

WDTE (UCFG1.7) watchdog timer reset software reset SRST (AUXR1.3) power-on detect

UART break detect

EBRR (AUXR1.6) brownout detect reset chip reset

002aae129

Fig 18. Block diagram of reset

Table 51.

Reset Sources register (RSTSRC - address DFh) bit allocation

Bit

Symbol

Reset

[1]

-

7

x

6

BOIF

0

5

BOF

1

4

POF

1

3

R_BK

0

2

R_WD

0

[1] The value shown is for a power-on reset. Other reset sources will set their corresponding bits.

1

R_SF

0

0

R_EX

0

Table 52.

Reset Sources register (RSTSRC - address DFh) bit description


0 R_EX external reset Flag. When this bit is logic 1, it indicates external pin reset. Cleared by software by writing a logic 0 to the bit or a Power-on reset. If RST is still asserted after the Power-on reset is over, R_EX will be set.

1 R_SF software reset Flag. Cleared by software by writing a logic 0 to the bit or a Power-on reset

2 R_WD Watchdog Timer reset flag. Cleared by software by writing a logic 0 to the bit or a Power-on reset.(NOTE:

UCFG1.7 must be = 1)

3 R_BK break detect reset. If a break detect occurs and EBRR (AUXR1.6) is set to logic 1, a system reset will occur.

This bit is set to indicate that the system reset is caused by a break detect. Cleared by software by writing a logic 0 to the bit or on a Power-on reset.

4 POF

5 BOF

Power-on Detect Flag. When Power-on Detect is activated, the POF flag is set to indicate an initial power-up condition. The POF flag will remain set until cleared by software by writing a logic 0 to the bit. (Note: On a

Power-on reset, both BOF and this bit will be set while the other flag bits are cleared.)

BOD Reset Flag. When BOD Reset is activated, this bit is set. It will remain set until cleared by software by writing a logic 0 to the bit. (Note: On a Power-on reset, both POF and this bit will be set while the other flag bits are cleared.)

6 BOIF

7 -

BOD Interrupt Flag. When BOD Interrupt is activated, this bit is set. It will remain set until cleared by software by writing a logic 0 to the bit.

reserved

7.1 Reset vector

Following reset, the P89LPC9331/9341/9351 will fetch instructions from either address

0000h or the Boot address. The Boot address is formed by using the Boot Vector as the high byte of the address and the low byte of the address = 00h. The Boot address will be

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used if a UART break reset occurs or the non-volatile Boot Status bit (BOOTSTAT.0) = 1, or the device has been forced into ISP mode. Otherwise, instructions will be fetched from address 0000H.

8.

Timers 0 and 1

The P89LPC9331/9341/9351 has two general-purpose counter/timers which are upward compatible with the 80C51 Timer 0 and Timer 1. Both can be configured to operate either as timers or event counters (see

Table 54 ). An option to automatically toggle the Tx pin

upon timer overflow has been added.

In the ‘Timer’ function, the timer is incremented every PCLK.

In the ‘Counter’ function, the register is incremented in response to a 1-to-0 transition on its corresponding external input pin (T0 or T1). The external input is sampled once during every machine cycle. When the pin is high during one cycle and low in the next cycle, the count is incremented. The new count value appears in the register during the cycle following the one in which the transition was detected. Since it takes two machine cycles

(four CPU clocks) to recognize a 1-to-0 transition, the maximum count rate is

1

⁄

4

of the

CPU clock frequency. There are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it should be held for at least one full machine cycle.

The ‘Timer’ or ‘Counter’ function is selected by control bits TnC/T (x = 0 and 1 for Timers 0 and 1 respectively) in the Special Function Register TMOD. Timer 0 and Timer 1 have five operating modes (modes 0, 1, 2, 3 and 6), which are selected by bit-pairs (TnM1, TnM0) in TMOD and TnM2 in TAMOD. Modes 0, 1, 2 and 6 are the same for both

Timers/Counters. Mode 3 is different. The operating modes are described later in this section.

Table 53.

Timer/Counter Mode register (TMOD - address 89h) bit allocation

Bit

Symbol

Reset

7

T1GATE

0

6

T1C/T

0

5

T1M1

0

4

T1M0

0

3

T0GATE

0

2

T0C/T

0

1

T0M1

0

0

T0M0

0

Table 54.

Timer/Counter Mode register (TMOD - address 89h) bit description


0 T0M0

1 T0M1

Mode Select for Timer 0. These bits are used with the T0M2 bit in the TAMOD register to determine the

Timer 0 mode (see Table 56

).

2 T0C/T Timer or Counter selector for Timer 0. Cleared for Timer operation (input from CCLK). Set for Counter operation (input from T0 input pin).

3 T0GATE Gating control for Timer 0. When set, Timer/Counter is enabled only while the INT0 pin is high and the TR0 control pin is set. When cleared, Timer 0 is enabled when the TR0 control bit is set.

4 T1M0 Mode Select for Timer 1. These bits are used with the T1M2 bit in the TAMOD register to determine the

Timer 1 mode (see Table 56

).

5 T1M1

6 T1C/T Timer or Counter Selector for Timer 1. Cleared for Timer operation (input from CCLK). Set for Counter operation (input from T1 input pin).

7 T1GATE Gating control for Timer 1. When set, Timer/Counter is enabled only while the INT1 pin is high and the TR1 control pin is set. When cleared, Timer 1 is enabled when the TR1 control bit is set.

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Table 55.

Timer/Counter Auxiliary Mode register (TAMOD - address 8Fh) bit allocation

Bit

Symbol

Reset

7

-x

-

6

x

-

5

x

4

T1M2

0

-

3

x

-

2

x

-

1

x

0

T0M2

0

Table 56.

Timer/Counter Auxiliary Mode register (TAMOD - address 8Fh) bit description


0 T0M2 Mode Select for Timer 0. These bits are used with the T0M2 bit in the TAMOD register to determine the

Timer 0 mode (see

Table 56 ).

1:3 - reserved

4 T1M2

5:7 -

Mode Select for Timer 1. These bits are used with the T1M2 bit in the TAMOD register to determine the

Timer 1 mode (see

Table 56 ).

The following timer modes are selected by timer mode bits TnM[2:0]:

000 — 8048 Timer ‘TLn’ serves as 5-bit prescaler. (Mode 0)

001 — 16-bit Timer/Counter ‘THn’ and ‘TLn’ are cascaded; there is no prescaler.(Mode 1)

010 — 8-bit auto-reload Timer/Counter. THn holds a value which is loaded into TLn when it overflows.

(Mode 2)

011 — Timer 0 is a dual 8-bit Timer/Counter in this mode. TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits. TH0 is an 8-bit timer only, controlled by the Timer 1 control bits (see text).

Timer 1 in this mode is stopped. (Mode 3)

100 — Reserved. User must not configure to this mode.


110 — PWM mode (see Section 8.5

).


reserved

8.1 Mode 0

Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit

Counter with a divide-by-32 prescaler.

Figure 19 shows Mode 0 operation.

In this mode, the Timer register is configured as a 13-bit register. As the count rolls over from all 1s to all 0s, it sets the Timer interrupt flag TFn. The count input is enabled to the

Timer when TRn = 1 and either TnGATE = 0 or INTn = 1. (Setting TnGATE = 1 allows the

Timer to be controlled by external input INTn, to facilitate pulse width measurements).

TRn is a control bit in the Special Function Register TCON (

Table 58

). The TnGATE bit is in the TMOD register.

The 13-bit register consists of all 8 bits of THn and the lower 5 bits of TLn. The upper 3 bits of TLn are indeterminate and should be ignored. Setting the run flag (TRn) does not clear the registers.

Mode 0 operation is the same for Timer 0 and Timer 1. See Figure 19

. There are two different GATE bits, one for Timer 1 (TMOD.7) and one for Timer 0 (TMOD.3).

8.2 Mode 1

Mode 1 is the same as Mode 0, except that all 16 bits of the timer register (THn and TLn)

are used. See Figure 20 .

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8.3 Mode 2

Mode 2 configures the Timer register as an 8-bit Counter (TLn) with automatic reload, as

shown in Figure 21

. Overflow from TLn not only sets TFn, but also reloads TLn with the contents of THn, which must be preset by software. The reload leaves THn unchanged.

Mode 2 operation is the same for Timer 0 and Timer 1.

8.4 Mode 3

When Timer 1 is in Mode 3 it is stopped. The effect is the same as setting TR1 = 0.

Timer 0 in Mode 3 establishes TL0 and TH0 as two separate 8-bit counters. The logic for

Mode 3 on Timer 0 is shown in

Figure 22 . TL0 uses the Timer 0 control bits: T0C/T,

T0GATE, TR0, INT0, and TF0. TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1. Thus, TH0 now controls the

‘Timer 1’ interrupt.

Mode 3 is provided for applications that require an extra 8-bit timer. With Timer 0 in Mode

3, an P89LPC9331/9341/9351 device can look like it has three Timer/Counters.

Note: When Timer 0 is in Mode 3, Timer 1 can be turned on and off by switching it into and out of its own Mode 3. It can still be used by the serial port as a baud rate generator, or in any application not requiring an interrupt.

8.5 Mode 6

In this mode, the corresponding timer can be changed to a PWM with a full period of 256

timer clocks (see Figure 23 ). Its structure is similar to mode 2, except that:

•

TFn (n = 0 and 1 for Timers 0 and 1 respectively) is set and cleared in hardware;

•

The low period of the TFn is in THn, and should be between 1 and 254, and;

•

The high period of the TFn is always 256

− THn.

•

Loading THn with 00h will force the Tx pin high, loading THn with FFh will force the Tx pin low.

Note that interrupt can still be enabled on the low to high transition of TFn, and that TFn can still be cleared in software like in any other modes.

Table 57.

Timer/Counter Control register (TCON) - address 88h) bit allocation

Bit 7 6 5 4 3 2

Symbol

Reset

TF1

0

TR1

0

TF0

0

TR0

0

IE1

0

IT1

0

1

IE0

0

0

IT0

0

Table 58.

Timer/Counter Control register (TCON - address 88h) bit description


0 IT0

1 IE0

Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts.

Interrupt 0 Edge flag. Set by hardware when external interrupt 0 edge is detected. Cleared by hardware when the interrupt is processed, or by software.

2 IT1 Interrupt 1 Type control bit. Set/cleared by software to specify falling edge/low level triggered external interrupts.

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Table 58.

Timer/Counter Control register (TCON - address 88h) bit description

…continued


3 IE1 Interrupt 1 Edge flag. Set by hardware when external interrupt 1 edge is detected. Cleared by hardware when the interrupt is processed, or by software.

4 TR0 Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter 0 on/off.

5 TF0

6

7

TR1

TF1

Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor vectors to the interrupt routine, or by software. (except in mode 6, where it is cleared in hardware)

Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter 1 on/off

Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the interrupt is processed, or by software (except in mode 6, see above, when it is cleared in hardware).

PCLK

Tn pin

TRn

Gate

INTn pin

C/T = 0

C/T = 1 control

TLn

(5-bits)

THn

(8-bits) overflow

TFn toggle interrupt

Tn pin

ENTn

002aaa919

Fig 19. Timer/counter 0 or 1 in Mode 0 (13-bit counter)

PCLK

Tn pin

C/T = 0

C/T = 1 control

TLn

(8-bits)

THn

(8-bits) overflow

TFn toggle interrupt

TRn

Gate

INTn pin

Tn pin

ENTn

002aaa920

Fig 20. Timer/counter 0 or 1 in mode 1 (16-bit counter)

PCLK

Tn pin

TRn

Gate

INTn pin

C/T = 0

C/T = 1 control

TLn

(8-bits) reload overflow toggle

TFn

THn

(8-bits)

ENTn

002aaa921 interrupt

Tn pin

Fig 21. Timer/counter 0 or 1 in Mode 2 (8-bit auto-reload)

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PCLK

T0 pin

TR0

Gate

INT0 pin

C/T = 0

C/T = 1 control

TL0

(8-bits) overflow toggle

TF0 interrupt

T0 pin

(P1.2 open drain)

ENT0

(AUXR1.4)

Osc/2 control

TH0

(8-bits) overflow

TF1 interrupt toggle

TR1

T1 pin

(P0.7)

ENT1

(AUXR1.5)

002aaa922

Fig 22. Timer/counter 0 Mode 3 (two 8-bit counters)

TRn

Gate

INTn pin

C/T = 0

PCLK control overflow

TLn

(8-bits)

TFn reload THn on falling transition and (256-THn) on rising transition toggle interrupt

Tn pin

THn

(8-bits)

ENTn

002aaa923

Fig 23. Timer/counter 0 or 1 in mode 6 (PWM auto-reload)

8.6 Timer overflow toggle output

Timers 0 and 1 can be configured to automatically toggle a port output whenever a timer overflow occurs. The same device pins that are used for the T0 and T1 count inputs and

PWM outputs are also used for the timer toggle outputs. This function is enabled by control bits ENT0 and ENT1 in the AUXR1 register, and apply to Timer 0 and Timer 1 respectively. The port outputs will be a logic 1 prior to the first timer overflow when this mode is turned on. In order for this mode to function, the C/T bit must be cleared selecting

PCLK as the clock source for the timer.

9.

Real-time clock system timer

The P89LPC9331/9341/9351 has a simple Real-time Clock/System Timer that allows a user to continue running an accurate timer while the rest of the device is powered down.

The Real-time Clock can be an interrupt or a wake-up source (see Figure 24

).

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The Real-time Clock is a 23-bit down counter. The clock source for this counter can be either the CPU clock (CCLK) or the XTAL1-2 oscillator. There are five SFRs used for the

RTC:

RTCCON — Real-time Clock control.

RTCH — Real-time Clock counter reload high (bits 22 to 15).

RTCL — Real-time Clock counter reload low (bits 14 to 7).

RTCDATH — Real-time clock data register high.

RTCDATL — Real-time Clock data register low.

The Real-time clock system timer can be enabled by setting the RTCEN (RTCCON.0) bit.

The Real-time Clock is a 23-bit down counter (initialized to all 0’s when RTCEN = 0) that is comprised of a 7-bit prescaler and a 16-bit loadable down counter. When RTCEN is written with logic 1, the counter is first loaded with (RTCH, RTCL, ‘1111111’) and will count down. When it reaches all 0’s, the counter will be reloaded again with (RTCH, RTCL,

‘1111111’) and a flag - RTCF (RTCCON.7) - will be set.

The 16-bit counter portion of the RTC is readable by reading the RTCDATH and

RTCDATL registers.

Power-on reset

RTCH RTCL

Reload on underflow

MSB

23-bit down counter

LSB

RTCDATH RTCDATL

RTC Reset

7-bit prescaler

÷128

XTAL2 XTAL1

CCLK internal oscillators

LOW FREQ.

MED. FREQ.

HIGH FREQ.

Wake-up from power-down

Interrupt if enabled

(shared with WDT)

ERTC

RTCF

RTC underflow flag

RTCEN

RTC enable

RTCS1 RTCS2

RTC clk select

002aae091

Fig 24. Real-time clock/system timer block diagram

9.1 Real-time clock source

RTCS1/RTCS0 (RTCCON[6:5]) are used to select the clock source for the RTC if either the Internal RC oscillator or the internal WD oscillator is used as the CPU clock. If the internal crystal oscillator or the external clock input on XTAL1 is used as the CPU clock, then the RTC will use CCLK as its clock source.

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9.2 Changing RTCS1/RTCS0

RTCS1/RTCS0 cannot be changed if the RTC is currently enabled (RTCCON.0 = 1).

Setting RTCEN and updating RTCS1/RTCS0 may be done in a single write to RTCCON.

However, if RTCEN = 1, this bit must first be cleared before updating RTCS1/RTCS0.

9.3 Real-time clock interrupt/wake-up

If ERTC (RTCCON.1), EWDRT (IEN1.0.6) and EA (IEN0.7) are set to logic 1, RTCF can be used as an interrupt source. This interrupt vector is shared with the watchdog timer. It can also be a source to wake-up the device.

9.3.1 Real-time clock read back

Users can read RTCDATH and RTCDATL registers and get the 16-bit counter portion of the RTC.

9.4 Reset sources affecting the Real-time clock

Only power-on reset and watchdog reset will reset the Real-time Clock and its associated

SFRs to their default state.

Table 59.

Real-time Clock/System Timer clock sources

FOSC2:0

000

RCCLK

0

RTCS1:0

00

RTC clock source

High frequency crystal

01

10

11

1


/DIVM

High frequency crystal 00

01

10

11

001 0 00

01

10

11

CPU clock source


/DIVM

Internal RC oscillator


Medium frequency crystal Medium frequency crystal

/DIVM

1

Medium frequency crystal

/DIVM

Medium frequency crystal Internal RC oscillator 00

01

10

11 Internal RC oscillator

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Table 59.

Real-time Clock/System Timer clock sources

…continued

FOSC2:0

010

RCCLK

0

RTCS1:0

00

RTC clock source

Low frequency crystal

CPU clock source


/DIVM

01

10

11

1


/DIV

Low frequency crystal Internal RC oscillator 00

01

10

11

011 0

1

00

01

10

11






/DIVM



/DIVM

Internal RC oscillator 00

01

10

100

101

110

111

0

1 x x

0

11

00

01

10

11

00

01

10

11 xx xx

00




High frequency crystal Watchdog oscillator

/DIVM



Watchdog oscillator /DIVM

High frequency crystal Internal RC oscillator



Internal RC oscillator undefined undefined

External clock input undefined undefined

External clock input

/DIVM

1

01

10

11

00

External clock input /DIVM

External clock input Internal RC oscillator

01

10

11 Internal RC oscillator

Table 60.

Real-time Clock Control register (RTCCON - address D1h) bit allocation

Bit 7

Symbol RTCF

Reset 0

6

RTCS1

1

5

RTCS0

1

-

4

x

-

3

x

-

2

x

1

ERTC

0

0

RTCEN

0

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5

6

7

Table 61.

Real-time Clock Control register (RTCCON - address D1h) bit description


0 RTCEN Real-time Clock enable. The Real-time Clock will be enabled if this bit is logic 1.

Note that this bit will not power-down the Real-time Clock. The RTCPD bit

(PCONA.7) if set, will power-down and disable this block regardless of RTCEN.

1 ERTC

2:4 -

Real-time Clock interrupt enable. The Real-time Clock shares the same interrupt as the watchdog timer. Note that if the user configuration bit WDTE

(UCFG1.7) is logic 0, the watchdog timer can be enabled to generate an interrupt. Users can read the RTCF (RTCCON.7) bit to determine whether the

Real-time Clock caused the interrupt. reserved

Real-time Clock source select (see

Table 59 ).

RTCS0

RTCS1

RTCF Real-time Clock Flag. This bit is set to logic 1 when the 23-bit Real-time Clock reaches a count of logic 0. It can be cleared in software.

10. Capture/Compare Unit (CCU) (P89LPC9351)

This unit features:

•

A 16-bit timer with 16-bit reload on overflow

•

Selectable clock (CCUCLK), with a prescaler to divide the clock source by any integer between 1 and 1024.

•

Four Compare / PWM outputs with selectable polarity

•

Symmetrical / Asymmetrical PWM selection

•

Seven interrupts with common interrupt vector (one Overflow, 2xCapture,

4xCompare), safe 16-bit read/write via shadow registers.

•

Two Capture inputs with event counter and digital noise rejection filter.

10.1 CCU Clock (CCUCLK)

The CCU runs on the CCUCLK, which can be either PCLK in basic timer mode or the output of a PLL (see

Figure 25

). The PLL is designed to use a clock source between

0.5 MHz to 1 MHz that is multiplied by 32 to produce a CCUCLK between 16 MHz and

32 MHz in PWM mode (asymmetrical or symmetrical). The PLL contains a 4-bit divider

(PLLDV3:0 bits in the TCR21 register) to help divide PCLK into a frequency between

0.5 MHz and 1 MHz.

10.2 CCU Clock prescaling

This CCUCLK can further be divided down by a prescaler. The prescaler is implemented as a 10-bit free-running counter with programmable reload at overflow. Writing a value to the prescaler will cause the prescaler to restart.

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16-BIT SHADOW REGISTER

TOR2H TO TOR2L

16-BIT SHADOW REGISTER

OCRxH TO OCRxL

16-BIT COMPARE

VALUE

TIMER > COMPARE

COMPARE CHANNELS A TO D

FCOx

OCD

OCC

OCB

OCA

16-BIT TIMER RELOAD

REGISTER

OVERFLOW/

UNDERFLOW

16-BIT UP/DOWN TIMER

WITH RELOAD

10-BIT DIVIDER

16-BIT CAPTURE

REGISTER ICRxH, L

EVENT

COUNTER

ICNFx

NOISE

FILTER

INTERRUPT FLAG

TICF2x SET

CAPTURE CHANNELS A, B

ICESx

EDGE

SELECT

ICB

ICA

002aab009

4-BIT

DIVIDER

32

× PLL

Fig 25. Capture Compare Unit block diagram

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10.3 Basic timer operation

The Timer is a free-running up/down counter counting at the pace determined by the prescaler. The timer is started by setting the CCU Mode Select bits TMOD21 and

TMOD20 in the CCU Control Register 0 (TCR20) as shown in the table in the TCR20 register description (

Table 66

).

The CCU direction control bit, TDIR2, determines the direction of the count. TDIR2 = 0:

Count up, TDIR2 = 1: Count down. If the timer counting direction is changed while the counter is running, the count sequence will be reversed in the CCUCLK cycle following the write of TDIR2. The timer can be written or read at any time and newly-written values will take effect when the prescaler overflows. The timer is accessible through two SFRs,

TL2(low byte) and TH2(high byte). A third 16-bit SFR, TOR2H:TOR2L, determines the overflow reload value. TL2, TH2 and TOR2H, TOR2L will be 0 after a reset

Up-counting: When the timer contents are FFFFH, the next CCUCLK cycle will set the counter value to the contents of TOR2H:TOR2L.

Down-counting: When the timer contents are 0000H, the next CCUCLK cycle will set the counter value to the contents of TOR2H:TOR2L. During the CCUCLK cycle when the reload is performed, the CCU Timer Overflow Interrupt Flag (TOIF2) in the CCU Interrupt

Flag Register (TIFR2) will be set, and, if the EA bit in the IEN0 register and ECCU bit in the IEN1 register (IEN1.4) are set, program execution will vector to the overflow interrupt.

The user has to clear the interrupt flag in software by writing a logic 0 to it.

When writing to the reload registers, TOR2H and TOR2L, the values written are stored in two 8-bit shadow registers. In order to latch the contents of the shadow registers into

TOR2H and TOR2L, the user must write a logic 1 to the CCU Timer Compare/Overflow

Update bit TCOU2, in CCU Timer Control Register 1 (TCR21). The function of this bit

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depends on whether the timer is running in PWM mode or in basic timer mode. In basic timer mode, writing a one to TCOU2 will cause the values to be latched immediately and the value of TCOU2 will always read as zero. In PWM mode, writing a one to TCOU2 will cause the contents of the shadow registers to be updated on the next CCU Timer overflow. As long as the latch is pending, TCOU2 will read as one and will return to zero when the latching takes place. TCOU2 also controls the latching of the Output Compare registers OCR2A, OCR2B and OCR2C.

When writing to timer high byte, TH2, the value written is stored in a shadow register.

When TL2 is written, the contents of TH2’s shadow register is transferred to TH2 at the same time that TL2 gets updated. Thus, TH2 should be written prior to writing to TL2. If a write to TL2 is followed by another write to TL2, without TH2 being written in between, the value of TH2 will be transferred directly to the high byte of the timer.

If the 16-bit CCU Timer is to be used as an 8-bit timer, the user can write FFh (for upcounting) or 00h (for downcounting) to TH2. When TL2 is written, FFh:TH2 (for upcounting) and 00h (for downcounting) will be loaded to CCU Timer. The user will not need to rewrite TH2 again for an 8-bit timer operation unless there is a change in count direction

When reading the timer, TL2 must be read first. When TL2 is read, the contents of the timer high byte are transferred to a shadow register in the same PCLK cycle as the read is performed. When TH2 is read, the contents of the shadow register are read instead. If a read from TL2 is followed by another read from TL2 without TH2 being read in between, the high byte of the timer will be transferred directly to TH2.

Table 62.

CCU prescaler control register, high byte (TPCR2H - address CBh) bit allocation

Bit 7 6 5 4 3 2 1

Symbol

Reset

x

x

x

x

x

x

0

TPCR2H.1

TPCR2H.0

0 0

Table 63.

CCU prescaler control register, high byte (TPCR2H - address CBh) bit description


0 TPCR2H.0

Prescaler bit 8

1 TPCR2H.1

Prescaler bit 9

Table 64.

CCU prescaler control register, low byte (TPCR2L - address CAh) bit allocation

Bit

Symbol

Reset

7 6 5 4 3 2 1 0

TPCR2L.7

TPCR2L.6

TPCR2L.5

TPCR2L.4

TPCR2L.3

TPCR2L.2

TPCR2L.1

TPCR2L.0

0 0 0 0 0 0 0 0

2

3

0

1

4

Table 65.

CCU prescaler control register, low byte (TPCR2L - address CAh) bit description


TPCR2L.0

TPCR2L.1

TPCR2L.2

TPCR2L.3

TPCR2L.4

Prescaler bit 0

Prescaler bit 1

Prescaler bit 2

Prescaler bit 3

Prescaler bit 4

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Table 65.

CCU prescaler control register, low byte (TPCR2L - address CAh) bit description

6

7

Bit

5

Symbol

TPCR2L.5

TPCR2L.6

TPCR2L.7

Description

Prescaler bit 5

Prescaler bit 6

Prescaler bit 7

Table 66.

CCU control register 0 (TCR20 - address C8h) bit allocation

Bit 7 6 5 4 3

Symbol

Reset

PLLEN

0

HLTRN

0

HLTEN

0

ALTCD

0

ALTAB

0

2

TDIR2

0

1

TMOD21

0

0

TMOD20

0

Table 67.

CCU control register 0 (TCR20 - address C8h) bit description


1:2 TMOD20/21 CCU Timer mode (TMOD21, TMOD20):

00 — Timer is stopped

01 — Basic timer function

10 — Asymmetrical PWM (uses PLL as clock source)

11 — Symmetrical PWM (uses PLL as clock source)

2 TDIR2 Count direction of the CCU Timer. When logic 0, count up, When logic 1, count down.

3 ALTAB

4 ALTCD

PWM channel A/B alternately output enable. When this bit is set, the output of PWM channel A and B are alternately gated on every counter cycle.

PWM channel C/D alternately output enable. When this bit is set, the output of PWM channel C and D are alternately gated on every counter cycle.

5 HLTEN

6

7

HLTRN

PLLEN

PWM Halt Enable. When logic 1, a capture event as enabled for Input Capture A pin will immediately stop all activity on the PWM pins and set them to a predetermined state.

PWM Halt. When set indicates a halt took place. In order to re-activate the PWM, the user must clear the HLTRN bit.

Phase Locked Loop Enable. When set to logic 1, starts PLL operation. After the PLL is in lock this bit it will read back a one.

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10.4 Output compare

The four output compare channels A, B, C and D are controlled through four 16-bit SFRs,

OCRAH:OCRAL, OCRBH:OCRBL, OCRCH:OCRCL, OCRDH: OCRDL. Each output compare channel needs to be enabled in order to operate. The channel is enabled by selecting a Compare Output Action by setting the OCMx1:0 bits in the Capture Compare x

Control Register CCCRx (x = A, B, C, D). When a compare channel is enabled, the user will have to set the associated I/O pin to the desired output mode to connect the pin.

(Note: The SFR bits for port pins P2.6, P1.6, P1.7, P2.1 must be set to logic 1 in order for the compare channel outputs to be visible at the port pins.) When the contents of TH2:TL2 match that of OCRxH:OCRxL, the Timer Output Compare Interrupt Flag - TOCFx is set in

TIFR2. This happens in the CCUCLK cycle after the compare takes place. If EA and the

Timer Output Compare Interrupt Enable bit TOCIE2x (in TICR2 register), as well as ECCU bit in IEN1 are all set, the program counter will be vectored to the corresponding interrupt.

The user must manually clear the bit by writing a logic 0 to it.

Two bits in OCCRx, the Output Compare x Mode bits OCMx1 and OCMx0 select what action is taken when a compare match occurs. Enabled compare actions take place even if the interrupt is disabled.

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In order for a Compare Output Action to occur, the compare values must be within the counting range of the CCU timer.

When the compare channel is enabled, the I/O pin (which must be configured as an output) will be connected to an internal latch controlled by the compare logic. The value of this latch is zero from reset and can be changed by invoking a forced compare. A forced compare is generated by writing a logic 1 to the Force Compare x Output bit FCOx bit in

OCCRx. Writing a one to this bit generates a transition on the corresponding I/O pin as set up by OCMx1/OCMx0 without causing an interrupt. In basic timer operating mode the

FCOx bits always read zero. (Note: This bit has a different function in PWM mode.) When an output compare pin is enabled and connected to the compare latch, the state of the compare pin remains unchanged until a compare event or forced compare occurs.

Table 68.

Capture compare control register (CCRx - address Exh) bit allocation

Bit

Symbol

Reset

7

ICECx2

0

6

ICECx1

0

5

ICECx0

0

4

ICESx

0

3

ICNFx

0

2

FCOx

0

1

OCMx1

0

0

OCMx0

0

Table 69.

Capture compare control register (CCRx - address Exh) bit description

Bit Symbol

0 OCMx0

Description

Output Compare x Mode. See Table 71 “Output compare pin behavior.”

1 OCMx1

2 FCOx

3 ICNFx

4

5

ICESx

ICECx0

6 ICECx1

7 ICECx2

Force Compare X Output Bit. When set, invoke a force compare.

Input Capture x Noise Filter Enable Bit. When logic 1, the capture logic needs to see four consecutive samples of the same value in order to recognize an edge as a capture event. The inputs are sampled every two CCLK periods regardless of the speed of the timer.

Input Capture x Edge Select Bit. When logic 0: Negative edge triggers a capture, When logic 1: Positive edge triggers a capture.

Capture Delay Setting Bit 0. See Table 70

for details.


for details.


for details.

When the user writes to change the output compare value, the values written to OCRH2x and OCRL2x are transferred to two 8-bit shadow registers. In order to latch the contents of the shadow registers into the capture compare register, the user must write a logic 1 to the CCU Timer Compare/Overflow Update bit TCOU2, in the CCU Control Register 1 -

TCR21. The function of this bit depends on whether the timer is running in PWM mode or in basic timer mode. In basic timer mode, writing a one to TCOU2 will cause the values to be latched immediately and the value of TCOU2 will always read as zero. In PWM mode, writing a one to TCOU2 will cause the contents of the shadow registers to be updated on the next CCU Timer overflow. As long as the latch is pending, TCOU2 will read as one and will return to zero when the latch takes place. TCOU2 also controls the latching of all the

Output Compare registers as well as the Timer Overflow Reload registers - TOR2.

10.5 Input capture

Input capture is always enabled. Each time a capture event occurs on one of the two input capture pins, the contents of the timer is transferred to the corresponding 16-bit input capture register ICRAH:ICRAL or ICRBH:ICRBL. The capture event is defined by the

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Input Capture Edge Select ICESx bit (x being A or B) in the CCCRx register. The user will have to configure the associated I/O pin as an input in order for an external event to trigger a capture.

A simple noise filter can be enabled on the input capture input. When the Input Capture

Noise Filter ICNFx bit is set, the capture logic needs to see four consecutive samples of the same value in order to recognize an edge as a capture event. The inputs are sampled every two CCLK periods regardless of the speed of the timer.

An event counter can be set to delay a capture by a number of capture events. The three bits ICECx2, ICECx1 and ICECx0 in the CCCRx register determine the number of edges the capture logic has to see before an input capture occurs.

When a capture event is detected, the Timer Input Capture x (x is A or B) Interrupt Flag

TICF2x (TIFR2.1 or TIFR2.0) is set. If EA and the Timer Input Capture x Enable bit

TICIE2x (TICR2.1 or TICR2.0) is set as well as the ECCU (IEN1.4) bit is set, the program counter will be vectored to the corresponding interrupt. The interrupt flag must be cleared manually by writing a logic 0 to it.

When reading the input capture register, ICRxL must be read first. When ICRxL is read, the contents of the capture register high byte are transferred to a shadow register. When

ICRxH is read, the contents of the shadow register are read instead. (If a read from ICRxL is followed by another read from ICRxL without ICRxH being read in between, the new value of the capture register high byte (from the last ICRxL read) will be in the shadow register).

1

1

1

0

1

0

0

Table 70.

Event delay counter for input capture

ICECx2

0

ICECx1

0

ICECx0

0

0

1

1

0

1

0

1

0

0

1

1

1

0

1

5

7

3

4

15

1

2

Delay (numbers of edges)

0

10.6 PWM operation

PWM Operation has two main modes, asymmetrical and symmetrical. These modes of timer operation are selected by writing 10H or 11H to TMOD21:TMOD20 as shown in

Section 10.3 “Basic timer operation”

.

In asymmetrical PWM operation, the CCU Timer operates in downcounting mode regardless of the setting of TDIR2. In this case, TDIR2 will always read 1.

In symmetrical mode, the timer counts up/down alternately and the value of TDIR2 has no effect. The main difference from basic timer operation is the operation of the compare module, which in PWM mode is used for PWM waveform generation.

Table 71 shows the

behavior of the compare pins in PWM mode.

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The user will have to configure the output compare pins as outputs in order to enable the

PWM output. As with basic timer operation, when the PWM (compare) pins are connected to the compare logic, their logic state remains unchanged. However, since the bit FCO is used to hold the halt value, only a compare event can change the state of the pin.

TOR2 compare value timer value

0x0000 non-inverted inverted

002aaa893

Fig 26. Asymmetrical PWM, downcounting

TOR2 compare value timer value

0 non-inverted

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inverted

002aaa894

Fig 27. Symmetrical PWM

The CCU Timer Overflow interrupt flag is set when the counter changes direction at the top. For example, if TOR contains 01FFH, CCU Timer will count: 01FEH, 01FFH, 01FEH.

The flag is set in the counter cycle after the change from TOR to TOR-1.

When the timer changes direction at the bottom, in this example, it counts 0001H, 0000H,

0001H. The CCU Timer overflow interrupt flag is set in the counter CCUCLK cycle after the transition from 0001H to 0000H.

The status of the TDIR2 bit in TCR20 reflects the current counting direction. Writing to this bit while operating in symmetrical mode has no effect.

10.7 Alternating output mode

In asymmetrical mode, the user can program PWM channels A/B and C/D as alternating pairs for bridge drive control. By setting ALTAB or ALTCD bits in TCR20, the output of these PWM channels are alternately gated on every counter cycle. This is shown in the following figure:

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TOR2

COMPARE VALUE A (or C)

COMPARE VALUE B (or D)

TIMER VALUE

0

PWM OUTPUT A (or C) (P2.6)

002aaa895

PWM OUTPUT B (or D) (P1.6)

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Fig 28. Alternate output mode

Table 71.

Output compare pin behavior.

OCMx1

[1]

OCMx0

[1]

Output Compare pin behavior

Basic timer mode Asymmetrical PWM

0 0

Symmetrical PWM

Output compare disabled. On power-on, this is the default state, and pins are configured as inputs.

0 1 Set when compare in operation. Cleared on

compare match.

[2]

Non-Inverted PWM. Set on compare match.

Cleared on CCU Timer underflow.

Non-Inverted PWM.

Cleared on compare match, upcounting. Set on compare match, downcounting.

1

1

0

1 invalid configuration

Toggles on compare

match

[2]

Inverted PWM. Cleared on compare match. Set on CCU Timer

underflow.

[2]

Inverted PWM. Set on compare match, upcounting. Cleared on compare match,

downcounting.

[2]

[1] x = A, B, C, D

[2] ‘ON’ means in the CCUCLK cycle after the event takes place.

10.8 Synchronized PWM register update

When the OCRx registers are written, a built in mechanism ensures that the value is not updated in the middle of a PWM pulse. This could result in an odd-length pulse. When the registers are written, the values are placed in two shadow registers, as is the case in basic timer operation mode. Writing to TCOU2 will cause the contents of the shadow registers to be updated on the next CCU Timer overflow. If OCRxH and/or OCRxL are read before the value is updated, the most currently written value is read.

10.9 HALT

Setting the HLTEN bit in TCR20 enables the PWM Halt Function. When halt function is enabled, a capture event as enabled for the Input Capture A pin will immediately stop all activity on the PWM pins and set them to a predetermined state defined by FCOx bit. In

PWM Mode, the FCOx bits in the CCCRx register hold the value the pin is forced to during halt. The value of the setting can be read back. The capture function and the interrupt will

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still operate as normal even if it has this added functionality enabled. When the PWM unit is halted, the timer will still run as normal. The HLTRN bit in TCR20 will be set to indicate that a halt took place. In order to re-activate the PWM, the user must clear the HLTRN bit.

The user can force the PWM unit into halt by writing a logic 1 to HLTRN bit.

10.10 PLL operation

The PWM module features a Phase Locked Loop that can be used to generate a

CCUCLK frequency between 16 MHz and 32 MHz. At this frequency the PWM module provides ultrasonic PWM frequency with 10-bit resolution provided that the crystal frequency is 1 MHz or higher (The PWM resolution is programmable up to 16 bits by writing to TOR2H:TOR2L). The PLL is fed an input signal of 0.5 MHz to 1 MHz and generates an output signal of 32 times the input frequency. This signal is used to clock the timer. The user will have to set a divider that scales PCLK by a factor of 1 to 16. This divider is found in the SFR register TCR21. The PLL frequency can be expressed as follows:

PLL frequency = PCLK / (N+1)

Where: N is the value of PLLDV3:0.

Since N ranges in 0 to 15, the CCLK frequency can be in the range of PCLK to

PCLK

⁄

16

.

Table 72.

CCU control register 1 (TCR21 - address F9h) bit allocation

Bit

Symbol

Reset

7

TCOU2

0

-

6

x

-

5

x

-

4

x

3

PLLDV.3

0

2

PLLDV.2

0

1

PLLDV.1

0

0

PLLDV.0

0

Table 73.

CCU control register 1 (TCR21 - address F9h) bit description


0:3 PLLDV.3:0 PLL frequency divider.

4:6 -

7 TCOU2

Reserved.

In basic timer mode, writing a logic 1 to TCOU2 will cause the values to be latched immediately and the value of TCOU2 will always read as logic 0. In PWM mode, writing a logic 1 to TCOU2 will cause the contents of the shadow registers to be updated on the next CCU Timer overflow. As long as the latch is pending, TCOU2 will read as logic 1 and will return to logic 0 when the latching takes place. TCOU2 also controls the latching of the Output Compare registers OCRAx, OCRBx and OCRCx.

Setting the PLLEN bit in TCR20 starts the PLL. When PLLEN is set, it will not read back a one until the PLL is in lock. At this time, the PWM unit is ready to operate and the timer can be enabled. The following start-up sequence is recommended:

1. Set up the PWM module without starting the timer.

2. Calculate the right division factor so that the PLL receives an input clock signal of

500 kHz - 1 MHz. Write this value to PLLDV.

3. Set PLLEN. Wait until the bit reads one

4. Start the timer by writing a value to bits TMOD21, TMOD20

When the timer runs from the PLL, the timer operates asynchronously to the rest of the microcontroller. Some restrictions apply:

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•

The user is discouraged from writing or reading the timer in asynchronous mode. The results may be unpredictable

•

Interrupts and flags are asynchronous. There will be delay as the event may not actually be recognized until some CCLK cycles later (for interrupts and reads)

10.11 CCU interrupt structure

There are seven independent sources of interrupts in the CCU: timer overflow, captured input events on Input Capture blocks A/B, and compare match events on Output Compare blocks A through D. One common interrupt vector is used for the CCU service routine and interrupts can occur simultaneously in system usage. To resolve this situation, a priority encode function of the seven interrupt bits in TIFR2 SFR is implemented (after each bit is

AND-ed with the corresponding interrupt enable bit in the TICR2 register). The order of priority is fixed as follows, from highest to lowest:

•

TOIF2

•

TICF2A

•

TICF2B

•

TOCF2A

•

TOCF2B

•

TOCF2C

•

TOCF2D

An interrupt service routine for the CCU can be as follows:

1. Read the priority-encoded value from the TISE2 register to determine the interrupt source to be handled.

2. After the current (highest priority) event is serviced, write a logic 0 to the corresponding interrupt flag bit in the TIFR2 register to clear the flag.

3. Read the TISE2 register. If the priority-encoded interrupt source is ‘000’, all CCU interrupts are serviced and a return from interrupt can occur. Otherwise, return to step

List item 2

for the next interrupt.

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EA (IEN0.7)

ECCU (IEN1.4)

TOIE2 (TICR2.7)

TOIF2 (TIFR2.7)

TICIE2A (TICR2.0)

TICF2A (TIFR2.0)

TICIE2B (TICR2.1)

TICF2B (TIFR2.1)

TOCIE2A (TICR2.3)

TOCF2A (TIFR2.3)

TOCIE2B (TICR2.4)

TOCF2B (TIFR2.4)

TOCIE2C (TICR2.5)

TOCF2C (TIFR2.5)

TOCIE2D (TICR2.6)

TOCF2D (TIFR2.6) other interrupt sources interrupt to

CPU

PRIORITY

ENCODER

002aaa896

ENCINT.0

ENCINT.1

ENCINT.2

Fig 29. Capture/compare unit interrupts

Table 74.

CCU interrupt status encode register (TISE2 - address DEh) bit allocation

Bit

Symbol

Reset

-

7

x

-

6

x

-

5

x

-

4

x

-

3

x

2

0

1

ENCINT.2

ENCINT.1

ENCINT.0

0

0

0

Table 75.

CCU interrupt status encode register (TISE2 - address DEh) bit description


2:0 ENCINT.2:0 CCU Interrupt Encode output. When multiple interrupts happen, more than one interrupt flag is set in

CCU Interrupt Flag Register (TIFR2). The encoder output can be read to determine which interrupt is to be serviced. The user must write a logic 0 to clear the corresponding interrupt flag bit in the TIFR2

register after the corresponding interrupt has been serviced. Refer to Table 77

for TIFR2 description.

000 — No interrupt pending.

001 — Output Compare Event D interrupt (lowest priority)

010 — Output Compare Event C interrupt.

011 — Output Compare Event B interrupt.

100 — Output Compare Event A interrupt.

101 — Input Capture Event B interrupt.

110 — Input Capture Event A interrupt.

111 — CCU Timer Overflow interrupt (highest priority).

3:7 Reserved.

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Table 76.

CCU interrupt flag register (TIFR2 - address E9h) bit allocation

Bit

Symbol

Reset

7

TOIF2

0

6

TOCF2D

0

5

TOCF2C

0

4

TOCF2B

0

3

TOCF2A

0

-

2

x

Table 78.

CCU interrupt control register (TICR2 - address C9h) bit allocation

Bit

Symbol

Reset

7

TOIE2

0

6

TOCIE2D

0

5

TOCIE2C

0

4

TOCIE2B

0

3

TOCIE2A

0

-

2

x

1

TICF2B

0

Table 77.

CCU interrupt flag register (TIFR2 - address E9h) bit description

Bit Symbol

0 TICF2A

1

2 -

TICF2B

3 TOCF2A

Description

Input Capture Channel A Interrupt Flag Bit. Set by hardware when an input capture event is detected.

Cleared by software.

Input Capture Channel B Interrupt Flag Bit. Set by hardware when an input capture event is detected.


Reserved for future use. Should not be set to logic 1 by user program.

4 TOCF2B

Output Compare Channel A Interrupt Flag Bit. Set by hardware when the contents of TH2:TL2 match that of OCRHA:OCRLA. Compare channel A must be enabled in order to generate this interrupt. If EA bit in

IEN0, ECCU bit in IEN1 and TOCIE2A bit are all set, the program counter will vectored to the corresponding interrupt. Cleared by software.

Output Compare Channel B Interrupt Flag Bit. Set by hardware when the contents of TH2:TL2 match that of OCRHB:OCRLB. Compare channel B must be enabled in order to generate this interrupt. If EA bit in

IEN0, ECCU bit in IEN1 and TOCIE2B bit are set, the program counter will vectored to the corresponding interrupt. Cleared by software.

5 TOCF2C

6

7

TOCF2D

TOIF2

Output Compare Channel C Interrupt Flag Bit. Set by hardware when the contents of TH2:TL2 match that of OCRHC:OCRLC. Compare channel C must be enabled in order to generate this interrupt. If EA bit in

IEN0, ECCU bit in IEN1 and TOCIE2C bit are all set, the program counter will vectored to the corresponding interrupt. Cleared by software.

Output Compare Channel D Interrupt Flag Bit. Set by hardware when the contents of TH2:TL2 match that of OCRHD:OCRLD. Compare channel D must be enabled in order to generate this interrupt. If EA bit in

IEN0, ECCU bit in IEN1 and TOCIE2D bit are all set, the program counter will vectored to the corresponding interrupt. Cleared by software.

CCU Timer Overflow Interrupt Flag bit. Set by hardware on CCU Timer overflow. Cleared by software.

1

TICIE2B

0

0

TICF2A

0

0

TICIE2A

0

Table 79.

CCU interrupt control register (TICR2 - address C9h) bit description

Bit Symbol

0 TICIE2A

1

2 -

TICIE2B

Description

Input Capture Channel A Interrupt Enable Bit. If EA bit and this bit all be set, when a capture event is detected, the program counter will vectored to the corresponding interrupt.

Input Capture Channel B Interrupt Enable Bit. If EA bit and this bit all be set, when a capture event is detected, the program counter will vectored to the corresponding interrupt.

Reserved for future use. Should not be set to logic 1 by user program.

3 TOCIE2A Output Compare Channel A Interrupt Enable Bit. If EA bit and this bit are set to 1, when compare channel is enabled and the contents of TH2:TL2 match that of OCRHA:OCRLA, the program counter will vectored to the corresponding interrupt.

4 TOCIE2B Output Compare Channel B Interrupt Enable Bit. If EA bit and this bit are set to 1, when compare channel

B is enabled and the contents of TH2:TL2 match that of OCRHB:OCRLB, the program counter will vectored to the corresponding interrupt.

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Table 79.

CCU interrupt control register (TICR2 - address C9h) bit description

…continued


5 TOCIE2C Output Compare Channel C Interrupt Enable Bit. If EA bit and this bit are set to 1, when compare channel

C is enabled and the contents of TH2:TL2 match that of OCRHC:OCRLC, the program counter will vectored to the corresponding interrupt.

6 TOCIE2D Output Compare Channel D Interrupt Enable Bit. If EA bit and this bit are set to 1, when compare channel

D is enabled and the contents of TH2:TL2 match that of OCRHD:OCRLD, the program counter will vectored to the corresponding interrupt.

7 TOIE2 CCU Timer Overflow Interrupt Enable bit.

11. UART

The P89LPC9331/9341/9351 has an enhanced UART that is compatible with the conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud rate source. The P89LPC9331/9341/9351 does include an independent Baud Rate Generator.

The baud rate can be selected from the oscillator (divided by a constant), Timer 1 overflow, or the independent Baud Rate Generator. In addition to the baud rate generation, enhancements over the standard 80C51 UART include Framing Error detection, break detect, automatic address recognition, selectable double buffering and several interrupt options.

The UART can be operated in 4 modes, as described in the following sections.

11.1 Mode 0

Serial data enters and exits through RXD. TXD outputs the shift clock. 8 bits are transmitted or received, LSB first. The baud rate is fixed at

1

⁄

16

of the CPU clock frequency.

11.2 Mode 1

10 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), and a stop bit (logic 1). When data is received, the stop bit is stored in

RB8 in Special Function Register SCON. The baud rate is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator (see

Section 11.6 “Baud Rate generator and selection”

).

11.3 Mode 2

11 bits are transmitted (through TXD) or received (through RXD): start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). When data is transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of 0 or 1. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When data is received, the 9th data bit goes into RB8 in Special Function Register SCON and the stop bit is not saved. The baud rate is programmable to either

1

⁄

16

or

1

⁄

32

of the CCLK frequency, as determined by the SMOD1 bit in PCON.

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11.4 Mode 3

11 bits are transmitted (through TXD) or received (through RXD): a start bit (logic 0), 8 data bits (LSB first), a programmable 9th data bit, and a stop bit (logic 1). Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator (see

Section 11.6

“Baud Rate generator and selection”

).

In all four modes, transmission is initiated by any instruction that uses SBUF as a destination register. Reception is initiated in Mode 0 by the condition RI = 0 and REN = 1.

Reception is initiated in the other modes by the incoming start bit if REN = 1.

11.5 SFR space

The UART SFRs are at the following locations:

Table 80.

UART SFR addresses

Register

PCON

SCON

SBUF

SADDR

SADEN

SSTAT

BRGR1

Description

Power Control

Serial Port (UART) Control

Serial Port (UART) Data Buffer

Serial Port (UART) Address

Serial Port (UART) Address Enable

SFR location

87H

98H

99H

A9H

B9H

Serial Port (UART) Status BAH

Baud Rate Generator Rate High Byte BFH

BRGR0

BRGCON

Baud Rate Generator Rate Low Byte BEH

Baud Rate Generator Control BDH

11.6 Baud Rate generator and selection

The P89LPC9331/9341/9351 enhanced UART has an independent Baud Rate Generator.

The baud rate is determined by a value programmed into the BRGR1 and BRGR0 SFRs.

The UART can use either Timer 1 or the baud rate generator output as determined by

BRGCON[2:1] (see Figure 30 ). Note that Timer T1 is further divided by 2 if the SMOD1 bit

(PCON.7) is set. The independent Baud Rate Generator uses CCLK.

11.7 Updating the BRGR1 and BRGR0 SFRs

The baud rate SFRs, BRGR1 and BRGR0 must only be loaded when the Baud Rate

Generator is disabled (the BRGEN bit in the BRGCON register is logic 0). This avoids the loading of an interim value to the baud rate generator. (CAUTION: If either BRGR0 or

BRGR1 is written when BRGEN = 1, the result is unpredictable.)

Table 81.

UART baud rate generation

SCON.7

(SM0)

SCON.6

(SM1)

PCON.7

(SMOD1)

BRGCON.1

(SBRGS)

0

0

0

1

X

0

1

X

X

0

0

1

Receive/transmit baud rate for UART

CCLK

CCLK

⁄

⁄

16

(256-TH1)64

CCLK

⁄

(256-TH1)32

CCLK

⁄

((BRGR1,BRGR0)+16)

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Table 81.

UART baud rate generation

…continued

SCON.7

(SM0)

1

SCON.6

(SM1)

0

PCON.7

(SMOD1)

0

1

BRGCON.1

(SBRGS)

X

X

1 1 0

1

X

0

0

1

Receive/transmit baud rate for UART

CCLK

⁄

32

CCLK

⁄

16

CCLK

⁄

(256-TH1)64

CCLK

⁄

(256-TH1)32

CCLK

⁄

((BRGR1,BRGR0)+16)

Table 82.

Baud Rate Generator Control register (BRGCON - address BDh) bit allocation

Bit 7

Symbol --

Reset x

-

6

x

-

5

x

-

4

x

-

3

x

-

2

x

1

SBRGS

0

0

BRGEN

0

Table 83.

Baud Rate Generator Control register (BRGCON - address BDh) bit description


0 BRGEN Baud Rate Generator Enable. Enables the baud rate generator. BRGR1 and

BRGR0 can only be written when BRGEN = 0.

1 SBRGS Select Baud Rate Generator as the source for baud rates to UART in modes 1 and

3 (see

Table 81 for details)

2:7 reserved timer 1 overflow

(PCLK-based)

SMOD1 = 1

÷2

SMOD1 = 0 baud rate generator

(CCLK-based)

Fig 30. Baud rate generation for UART (Modes 1, 3)

SBRGS = 0 baud rate modes 1 and 3

SBRGS = 1

002aaa897

11.8 Framing error

A Framing error occurs when the stop bit is sensed as a logic 0. A Framing error is reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6) is 1, framing errors can be made available in SCON.7. If SMOD0 is 0, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON[7:6]) are programmed when SMOD0 is logic 0.

11.9 Break detect

A break detect is reported in the status register (SSTAT). A break is detected when any 11 consecutive bits are sensed low. Since a break condition also satisfies the requirements for a framing error, a break condition will also result in reporting a framing error. Once a break condition has been detected, the UART will go into an idle state and remain in this idle state until a stop bit has been received. The break detect can be used to reset the device and force the device into ISP mode by setting the EBRR bit (AUXR1.6)

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Table 84.

Serial Port Control register (SCON - address 98h) bit allocation

Bit

Symbol

Reset

7

SM0/FE x

6

SM1 x

5

SM2 x

4

REN x

3

TB8 x

2

RB8 x 0

1

TI

0

RI

0

Table 85.

Serial Port Control register (SCON - address 98h) bit description


0 RI Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or approximately halfway through the stop bit time in Mode 1. For Mode 2 or Mode 3, if SMOD0, it is set near the middle of the 9th data bit (bit 8). If SMOD0 = 1, it is set near the middle of the stop bit (see SM2 - SCON.5 - for exceptions). Must be cleared by software.

1 TI

2

3

4

5

RB8

TB8

REN

SM2

Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the stop bit (see description of INTLO bit in SSTAT register) in the other modes.

Must be cleared by software.

The 9th data bit that was received in Modes 2 and 3. In Mode 1 (SM2 must be 0),

RB8 is the stop bit that was received. In Mode 0, RB8 is undefined.

The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired.

Enables serial reception. Set by software to enable reception. Clear by software to disable reception.

Enables the multiprocessor communication feature in Modes 2 and 3. In Mode 2 or

3, if SM2 is set to 1, then Rl will not be activated if the received 9th data bit (RB8) is 0. In Mode 0, SM2 should be 0. In Mode 1, SM2 must be 0.

6 SM1 With SM0 defines the serial port mode, see

Table 86 .

7 SM0/FE The use of this bit is determined by SMOD0 in the PCON register. If SMOD0 = 0, this bit is read and written as SM0, which with SM1, defines the serial port mode. If

SMOD0 = 1, this bit is read and written as FE (Framing Error). FE is set by the receiver when an invalid stop bit is detected. Once set, this bit cannot be cleared by valid frames but is cleared by software. (Note: UART mode bits SM0 and SM1 should be programmed when SMOD0 is logic 0 - default mode on any reset.)

Table 86.

Serial Port modes

SM0, SM1

00

01

10

11

UART mode

Mode 0: shift register

Mode 1: 8-bit UART

Mode 2: 9-bit UART

Mode 3: 9-bit UART

UART baud rate

CCLK

⁄

16

(default mode on any reset)

Variable (see

Table 81 )

CCLK

⁄

32

or

CCLK

⁄

16

Variable (see

Table 81 )

Table 87.

Serial Port Status register (SSTAT - address BAh) bit allocation

Bit 7 6

Symbol DBMOD INTLO

Reset x x

5

CIDIS x

4

DBISEL x

3

FE x

2

BR x

1

OE

0

0

STINT

0

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Table 88.

Serial Port Status register (SSTAT - address BAh) bit description


0 STINT Status Interrupt Enable. When set = 1, FE, BR, or OE can cause an interrupt. The interrupt used (vector address 0023h) is shared with RI (CIDIS = 1) or the combined TI/RI (CIDIS = 0). When cleared = 0, FE, BR, OE cannot cause an interrupt. (Note: FE, BR, or OE is often accompanied by a RI, which will generate an interrupt regardless of the state of STINT). Note that BR can cause a break detect reset if EBRR (AUXR1.6) is set to logic 1.

1 OE Overrun Error flag is set if a new character is received in the receiver buffer while it is still full (before the software has read the previous character from the buffer), i.e., when bit 8 of a new byte is received while RI in SCON is still set. Cleared by software.

2

3

BR

FE

Break Detect flag. A break is detected when any 11 consecutive bits are sensed low. Cleared by software.

Framing error flag is set when the receiver fails to see a valid STOP bit at the end of the frame. Cleared by software.

4 DBISEL Double buffering transmit interrupt select. Used only if double buffering is enabled.

This bit controls the number of interrupts that can occur when double buffering is enabled. When set, one transmit interrupt is generated after each character written to SBUF, and there is also one more transmit interrupt generated at the beginning

(INTLO = 0) or the end (INTLO = 1) of the STOP bit of the last character sent (i.e., no more data in buffer). This last interrupt can be used to indicate that all transmit operations are over. When cleared = 0, only one transmit interrupt is generated per character written to SBUF. Must be logic 0 when double buffering is disabled. Note that except for the first character written (when buffer is empty), the location of the transmit interrupt is determined by INTLO. When the first character is written, the transmit interrupt is generated immediately after SBUF is written.

5 CIDIS Combined Interrupt Disable. When set = 1, Rx and Tx interrupts are separate.

When cleared = 0, the UART uses a combined Tx/Rx interrupt (like a conventional

80C51 UART). This bit is reset to logic 0 to select combined interrupts.

6 INTLO Transmit interrupt position. When cleared = 0, the Tx interrupt is issued at the beginning of the stop bit. When set = 1, the Tx interrupt is issued at end of the stop bit. Must be logic 0 for mode 0. Note that in the case of single buffering, if the Tx interrupt occurs at the end of a STOP bit, a gap may exist before the next start bit.

7 DBMOD Double buffering mode. When set = 1 enables double buffering. Must be logic 0 for

UART mode 0. In order to be compatible with existing 80C51 devices, this bit is reset to logic 0 to disable double buffering.

11.10 More about UART Mode 0

In Mode 0, a write to SBUF will initiate a transmission. At the end of the transmission, TI

(SCON.1) is set, which must be cleared in software. Double buffering must be disabled in this mode.

Reception is initiated by clearing RI (SCON.0). Synchronous serial transfer occurs and RI will be set again at the end of the transfer. When RI is cleared, the reception of the next character will begin. Refer to

Figure 31

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write to

SBUF shift

RXD (data out)

TXD (shift clock)

TI

S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16 S1 ... S16

D0 D1 D2 D3 D4 D5 D6 D7 transmit

WRITE to SCON

(clear RI)

RI shift

RXD

(data in)

TXD (shift clock)

D0 D1 D2 D3 D4 D5 D6 D7 receive

002aaa925

Fig 31. Serial Port Mode 0 (double buffering must be disabled)

11.11 More about UART Mode 1

Reception is initiated by detecting a 1-to-0 transition on RxD. RxD is sampled at a rate 16 times the programmed baud rate. When a transition is detected, the divide-by-16 counter is immediately reset. Each bit time is thus divided into 16 counter states. At the 7th, 8th, and 9th counter states, the bit detector samples the value of RxD. The value accepted is the value that was seen in at least 2 of the 3 samples. This is done for noise rejection. If the value accepted during the first bit time is not 0, the receive circuits are reset and the receiver goes back to looking for another 1-to-0 transition. This provides rejection of false start bits. If the start bit proves valid, it is shifted into the input shift register, and reception of the rest of the frame will proceed.

The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated: RI = 0 and either

SM2 = 0 or the received stop bit = 1. If either of these two conditions is not met, the received frame is lost. If both conditions are met, the stop bit goes into RB8, the 8 data bits go into SBUF, and RI is activated.

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TX clock write to

SBUF shift

TXD

TI start bit

D0 D1 D2 D3 D4 D5 D6 D7 stop bit transmit

INTLO = 0 INTLO = 1

RX clock

RXD shift

RI

÷16 reset start bit

D0 D1 D2 D3 D4 D5 D6 D7 stop bit receive

002aaa926

Fig 32. Serial Port Mode 1 (only single transmit buffering case is shown)

11.12 More about UART Modes 2 and 3

Reception is the same as in Mode 1.

The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions are met at the time the final shift pulse is generated. (a) RI = 0, and

(b) Either SM2 = 0, or the received 9th data bit = 1. If either of these conditions is not met, the received frame is lost, and RI is not set. If both conditions are met, the received 9th data bit goes into RB8, and the first 8 data bits go into SBUF.

TX clock write to

SBUF shift

TXD

TI start bit

D0 D1 D2 D3 D4 D5 D6 D7 TB8 stop bit transmit

INTLO = 0 INTLO = 1

RX clock

RXD shift

RI

÷16 reset start bit

D0 D1 D2 D3 D4 D5 D6 D7

RB8 stop bit receive

SMOD0 = 0 SMOD0 = 1

002aaa927

Fig 33. Serial Port Mode 2 or 3 (only single transmit buffering case is shown)

11.13 Framing error and RI in Modes 2 and 3 with SM2 = 1

If SM2 = 1 in modes 2 and 3, RI and FE behaves as in the following table.

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Table 89.

FE and RI when SM2 = 1 in Modes 2 and 3

Mode

2

PCON.6

(SMOD0)

0

RB8 RI

0 No RI when RB8 = 0

3 1

1

0

1

FE

Similar to Figure 33

, with SMOD0 = 0, RI occurs during RB8, one bit before FE

No RI when RB8 = 0

Similar to Figure 33

, with SMOD0 = 1, RI occurs during STOP bit

Occurs during STOP bit


Will NOT occur


11.14 Break detect

A break is detected when 11 consecutive bits are sensed low and is reported in the status register (SSTAT). For Mode 1, this consists of the start bit, 8 data bits, and two stop bit times. For Modes 2 and 3, this consists of the start bit, 9 data bits, and one stop bit. The break detect bit is cleared in software or by a reset. The break detect can be used to reset the device and force the device into ISP mode. This occurs if the UART is enabled and the the EBRR bit (AUXR1.6) is set and a break occurs.

11.15 Double buffering

The UART has a transmit double buffer that allows buffering of the next character to be written to SBUF while the first character is being transmitted. Double buffering allows transmission of a string of characters with only one stop bit between any two characters, provided the next character is written between the start bit and the stop bit of the previous character.

Double buffering can be disabled. If disabled (DBMOD, i.e. SSTAT.7 = 0), the UART is compatible with the conventional 80C51 UART. If enabled, the UART allows writing to

SnBUF while the previous data is being shifted out.

11.16 Double buffering in different modes

Double buffering is only allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be disabled (DBMOD = 0).

11.17 Transmit interrupts with double buffering enabled (Modes 1, 2, and 3)

Unlike the conventional UART, when double buffering is enabled, the Tx interrupt is generated when the double buffer is ready to receive new data. The following occurs during a transmission (assuming eight data bits):

1. The double buffer is empty initially.

2. The CPU writes to SBUF.

3. The SBUF data is loaded to the shift register and a Tx interrupt is generated immediately.

4. If there is more data, go to 6, else continue.

5. If there is no more data, then:

– If DBISEL is logic 0, no more interrupts will occur.

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– If DBISEL is logic 1 and INTLO is logic 0, a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter (which is also the last data).

– If DBISEL is logic 1 and INTLO is logic 1, a Tx interrupt will occur at the end of the

STOP bit of the data currently in the shifter (which is also the last data).

– Note that if DBISEL is logic 1 and the CPU is writing to SBUF when the STOP bit of the last data is shifted out, there can be an uncertainty of whether a Tx interrupt is generated already with the UART not knowing whether there is any more data following.

6. If there is more data, the CPU writes to SBUF again. Then:

– If INTLO is logic 0, the new data will be loaded and a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter.

– If INTLO is logic 1, the new data will be loaded and a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter.

– Go to 3.

TXD write to

SBUF

TX interrupt single buffering (DBMOD/SSTAT.7 = 0), early interrupt (INTLO/SSTAT.6 = 0) is shown

TXD write to

SBUF

TX interrupt double buffering (DBMOD/SSTAT.7 = 1), early interrupt (INTLO/SSTAT.6 = 0) is shown, no ending TX interrupt (DBISEL/SSTAT.4 = 0)

TXD write to

SBUF

TX interrupt double buffering (DBMOD/SSTAT.7 = 1), early interrupt (INTLO/SSTAT.6 = 0) is shown, with ending TX interrupt (DBISEL/SSTAT.4 = 1)

002aaa928

Fig 34. Transmission with and without double buffering

11.18 The 9th bit (bit 8) in double buffering (Modes 1, 2, and 3)

If double buffering is disabled (DBMOD, i.e. SSTAT.7 = 0), TB8 can be written before or after SBUF is written, provided TB8 is updated before that TB8 is shifted out. TB8 must not be changed again until after TB8 shifting has been completed, as indicated by the Tx interrupt.

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If double buffering is enabled, TB8 MUST be updated before SBUF is written, as TB8 will be double-buffered together with SBUF data. The operation described in the

Section

11.17 “Transmit interrupts with double buffering enabled (Modes 1, 2, and 3)”

becomes as follows:

1. The double buffer is empty initially.

2. The CPU writes to TB8.

3. The CPU writes to SBUF.

4. The SBUF/TB8 data is loaded to the shift register and a Tx interrupt is generated immediately.

5. If there is more data, go to 7, else continue on 6.

6. If there is no more data, then:

– If DBISEL is logic 0, no more interrupt will occur.

– If DBISEL is logic 1 and INTLO is logic 0, a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter (which is also the last data).

– If DBISEL is logic 1 and INTLO is logic 1, a Tx interrupt will occur at the end of the

STOP bit of the data currently in the shifter (which is also the last data).

7. If there is more data, the CPU writes to TB8 again.

8. The CPU writes to SBUF again. Then:

– If INTLO is logic 0, the new data will be loaded and a Tx interrupt will occur at the beginning of the STOP bit of the data currently in the shifter.

– If INTLO is logic 1, the new data will be loaded and a Tx interrupt will occur at the end of the STOP bit of the data currently in the shifter.

9. Go to 4.

10. Note that if DBISEL is logic 1 and the CPU is writing to SBUF when the STOP bit of the last data is shifted out, there can be an uncertainty of whether a Tx interrupt is generated already with the UART not knowing whether there is any more data following.

11.19 Multiprocessor communications

UART modes 2 and 3 have a special provision for multiprocessor communications. In these modes, 9 data bits are received or transmitted. When data is received, the 9th bit is stored in RB8. The UART can be programmed such that when the stop bit is received, the serial port interrupt will be activated only if RB8 = 1. This feature is enabled by setting bit

SM2 in SCON. One way to use this feature in multiprocessor systems is as follows:

When the master processor wants to transmit a block of data to one of several slaves, it first sends out an address byte which identifies the target slave. An address byte differs from a data byte in that the 9th bit is 1 in an address byte and 0 in a data byte. With

SM2 = 1, no slave will be interrupted by a data byte. An address byte, however, will interrupt all slaves, so that each slave can examine the received byte and see if it is being addressed. The addressed slave will clear its SM2 bit and prepare to receive the data bytes that follow. The slaves that weren’t being addressed leave their SM2 bits set and go on about their business, ignoring the subsequent data bytes.

Note that SM2 has no effect in Mode 0, and must be logic 0 in Mode 1.

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11.20 Automatic address recognition

Automatic address recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes (mode 2 and mode 3), the

Receive Interrupt flag (RI) will be automatically set when the received byte contains either the ‘Given’ address or the ‘Broadcast’ address. The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data.

Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses.

All of the slaves may be contacted by using the Broadcast address. Two special Function

Registers are used to define the slave’s address, SADDR, and the address mask,

SADEN. SADEN is used to define which bits in the SADDR are to be used and which bits are ‘don’t care’. The SADEN mask can be logically ANDed with the SADDR to create the

‘Given’ address which the master will use for addressing each of the slaves. Use of the

Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme:

Table 90.

Slave 0/1 examples

Example 1

Slave 0 SADDR

Example 2

= 1100 0000 Slave 1

SADEN

Given

= 1111 1101

= 1100 00X0

SADDR

SADEN

Given

= 1100 0000

= 1111 1110

= 1100 000X

In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000.

In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0:

Table 91.

Slave 0/1/2 examples

Example 1

Slave 0 SADDR

SADEN

Given

Example 2

= 1100 0000 Slave 1 SADDR

= 1111 1001 SADEN

= 1100 0XX0 Given

Example 3

= 1110 0000 Slave 2

= 1111 1010

= 1110 0X0X

SADDR

SADEN

Given

= 1100 0000

= 1111 1100

= 1110 00XX

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In the above example the differentiation among the 3 slaves is in the lower 3 address bits.

Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. The Broadcast Address for each slave is created by taking the logical OR of

SADDR and SADEN. Zeros in this result are treated as don’t-cares. In most cases, interpreting the don’t-cares as ones, the broadcast address will be FF hexadecimal. Upon

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reset SADDR and SADEN are loaded with 0s. This produces a given address of all ‘don’t cares’ as well as a Broadcast address of all ‘don’t cares’. This effectively disables the

Automatic Addressing mode and allows the microcontroller to use standard UART drivers which do not make use of this feature.

12. I

2

C interface

The I

2

C-bus uses two wires, serial clock (SCL) and serial data (SDA) to transfer information between devices connected to the bus, and has the following features:

•

Bidirectional data transfer between masters and slaves

•

Multimaster bus (no central master)

•

Arbitration between simultaneously transmitting masters without corruption of serial data on the bus

•

Serial clock synchronization allows devices with different bit rates to communicate via one serial bus

•

Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer

•

The I

2

C-bus may be used for test and diagnostic purposes

A typical I

2

C-bus configuration is shown in Figure 35 . Depending on the state of the

direction bit (R/W), two types of data transfers are possible on the I

2

C-bus:

•

Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after each received byte.

•

Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by the master. The slave then returns an acknowledge bit.

Next follows the data bytes transmitted by the slave to the master. The master returns an acknowledge bit after all received bytes other than the last byte. At the end of the last received byte, a ‘not acknowledge’ is returned. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a repeated START condition. Since a repeated START condition is also the beginning of the next serial transfer, the I

2

C-bus will not be released.

The P89LPC9331/9341/9351 device provides a byte-oriented I

2

C interface. It has four operation modes: Master Transmitter Mode, Master Receiver Mode, Slave Transmitter

Mode and Slave Receiver Mode.

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RP RP

I

2

C-bus

SDA

SCL

P1.3/SDA P1.2/SCL

P89LPC9331/9341/

9351

OTHER DEVICE

WITH I

2

C-BUS

INTERFACE

OTHER DEVICE

WITH I

2

C-BUS

INTERFACE

002aad731

Fig 35. I

2

C-bus configuration

The P89LPC9331/9341/9351 CPU interfaces with the I

2

C-bus through six Special

Function Registers (SFRs): I2CON (I

2

C Control Register), I2DAT (I

2

C Data Register),

I2STAT (I

2

C Status Register), I2ADR (I

2

C Slave Address Register), I2SCLH (SCL Duty

Cycle Register High Byte), and I2SCLL (SCL Duty Cycle Register Low Byte).

12.1 I

2

C data register

I2DAT register contains the data to be transmitted or the data received. The CPU can read and write to this 8-bit register while it is not in the process of shifting a byte. Thus this register should only be accessed when the SI bit is set. Data in I2DAT remains stable as long as the SI bit is set. Data in I2DAT is always shifted from right to left: the first bit to be transmitted is the MSB (bit 7), and after a byte has been received, the first bit of received data is located at the MSB of I2DAT.

Table 92.

I

2

C data register (I2DAT - address DAh) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol I2DAT.7

I2DAT.6

I2DAT.5

I2DAT.4

I2DAT.3

I2DAT.2

I2DAT.1

I2DAT.0

Reset 0 0 0 0 0 0 0 0

12.2 I

2

C slave address register

I2ADR register is readable and writable, and is only used when the I

2

C interface is set to slave mode. In master mode, this register has no effect. The LSB of I2ADR is general call bit. When this bit is set, the general call address (00h) is recognized.

Table 93.

I

2

C slave address register (I2ADR - address DBh) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol I2ADR.6

I2ADR.5

I2ADR.4

I2ADR.3

I2ADR.2

I2ADR.1

I2ADR.0

GC

Reset 0 0 0 0 0 0 0 0

Table 94.

I

2

C slave address register (I2ADR - address DBh) bit description


0 GC General call bit. When set, the general call address (00H) is recognized, otherwise it is ignored.

1:7 I2ADR1:7 7 bit own slave address. When in master mode, the contents of this register has no effect.

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12.3 I

2

C control register

The CPU can read and write this register. There are two bits are affected by hardware: the

SI bit and the STO bit. The SI bit is set by hardware and the STO bit is cleared by hardware.

CRSEL determines the SCL source when the I

2

C-bus is in master mode. In slave mode this bit is ignored and the bus will automatically synchronize with any clock frequency up to 400 kHz from the master I

2

C device. When CRSEL = 1, the I

2

C interface uses the

Timer 1 overflow rate divided by 2 for the I

2

C clock rate. Timer 1 should be programmed by the user in 8 bit auto-reload mode (Mode 2).

Data rate of I

2

C-bus = Timer overflow rate / 2 = PCLK / (2*(256-reload value)).

If f osc

= 12 MHz, reload value is 0 to 255, so I

2

C data rate range is 11.72 Kbit/sec to

3000 Kbit/sec.

When CRSEL = 0, the I

2

C interface uses the internal clock generator based on the value of I2SCLL and I2CSCLH register. The duty cycle does not need to be 50 %.

The STA bit is START flag. Setting this bit causes the I

2

C interface to enter master mode and attempt transmitting a START condition or transmitting a repeated START condition when it is already in master mode.

The STO bit is STOP flag. Setting this bit causes the I

2

C interface to transmit a STOP condition in master mode, or recovering from an error condition in slave mode.

If the STA and STO are both set, then a STOP condition is transmitted to the I

2

C-bus if it is in master mode, and transmits a START condition afterwards. If it is in slave mode, an internal STOP condition will be generated, but it is not transmitted to the bus.

Table 95.

I

2

C Control register (I2CON - address D8h) bit allocation

Bit

Symbol -

7

Reset x

6

I2EN

0

5

STA

0

4

STO

0

3

SI

0

2

AA

0

-

1

x

0

CRSEL

0

Table 96.

I

2

C Control register (I2CON - address D8h) bit description


0 CRSEL SCL clock selection. When set = 1, Timer 1 overflow generates SCL, when cleared

= 0, the internal SCL generator is used base on values of I2SCLH and I2SCLL.

1 reserved

2 AA The Assert Acknowledge Flag. When set to 1, an acknowledge (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line on the following situations:

(1) The ‘own slave address’ has been received. (2) The general call address has been received while the general call bit (GC) in I2ADR is set. (3) A data byte has been received while the I

2

C interface is in the Master Receiver Mode. (4) A data byte has been received while the I

2

C interface is in the addressed Slave Receiver

Mode. When cleared to 0, an not acknowledge (high level to SDA) will be returned during the acknowledge clock pulse on the SCL line on the following situations: (1)

A data byte has been received while the I

2

C interface is in the Master Receiver

Mode. (2) A data byte has been received while the I

2

C interface is in the addressed Slave Receiver Mode.

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Table 96.

I

2

C Control register (I2CON - address D8h) bit description

…continued


3 SI I

2

C Interrupt Flag. This bit is set when one of the 25 possible I

2

C states is entered.

When EA bit and EI2C (IEN1.0) bit are both set, an interrupt is requested when SI is set. Must be cleared by software by writing 0 to this bit.

4 STO

5

6

STA

I2EN

STOP Flag. STO = 1: In master mode, a STOP condition is transmitted to the

I

2

C-bus. When the bus detects the STOP condition, it will clear STO bit automatically. In slave mode, setting this bit can recover from an error condition. In this case, no STOP condition is transmitted to the bus. The hardware behaves as if a STOP condition has been received and it switches to ‘not addressed’ Slave

Receiver Mode. The STO flag is cleared by hardware automatically.

Start Flag. STA = 1: I

2

C-bus enters master mode, checks the bus and generates a

START condition if the bus is free. If the bus is not free, it waits for a STOP condition (which will free the bus) and generates a START condition after a delay of a half clock period of the internal clock generator. When the I

2

C interface is already in master mode and some data is transmitted or received, it transmits a repeated START condition. STA may be set at any time, it may also be set when the I

2

C interface is in an addressed slave mode. STA = 0: no START condition or repeated START condition will be generated.

I

2

C Interface Enable. When set, enables the I

2

C interface. When clear, the I

2

C function is disabled.

7 reserved

12.4 I

2

C Status register

This is a read-only register. It contains the status code of the I

2

C interface. The least three bits are always 0. There are 26 possible status codes. When the code is F8H, there is no relevant information available and SI bit is not set. All other 25 status codes correspond to defined I

2

C states. When any of these states entered, the SI bit will be set. Refer to

Table 102 to

Table 105 for details.

Table 97.

I

2

C Status register (I2STAT - address D9h) bit allocation

Bit 7

Symbol STA.4

Reset 0

6

STA.3

0

5

STA.2

0

4

STA.1

0

3

STA.0

0

2

0

0

1

0

0

0

0

0

Table 98.

I

2

C Status register (I2STAT - address D9h) bit description


0:2 Reserved, are always set to 0.

3:7 STA[0:4] I

2

C Status code.

12.5 I

2

C SCL duty cycle registers I2SCLH and I2SCLL

When the internal SCL generator is selected for the I

2

C interface by setting CRSEL = 0 in the I2CON register, the user must set values for registers I2SCLL and I2SCLH to select the data rate. I2SCLH defines the number of PCLK cycles for SCL = high, I2SCLL defines the number of PCLK cycles for SCL = low. The frequency is determined by the following formula:

Bit Frequency = f

PCLK

/ (2*(I2SCLH + I2SCLL))

Where f

PCLK

is the frequency of PCLK.

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The values for I2SCLL and I2SCLH do not have to be the same; the user can give different duty cycles for SCL by setting these two registers. However, the value of the register must ensure that the data rate is in the I

2

C data rate range of 0 to 400 kHz. Thus the values of I2SCLL and I2SCLH have some restrictions and values for both registers greater than three PCLKs are recommended.

50

60

100

150

10

15

25

30

-

200

8

9

6

7

Table 99.

I

2

C clock rates selection

I2SCLL+

I2SCLH

CRSEL

Bit data rate (Kbit/sec) at f osc

7.373 MHz 3.6865 MHz 1.8433 MHz 12 MHz

0

0

0

0

-

-

-

-

307

263

230

205

154

132

115

102

-

-

-

-

0

0

0

0

0

0

0

0

0

1

369

246

147

123

74

61

37

25

18

3.6 Kbps to

922 Kbps

Timer 1 in mode 2

184

123

74

61

37

31

18

12

9

1.8 Kbps to

461 Kbps

Timer 1 in mode 2

92

61

37

31

18

15

9

6

5

0.9 Kbps to

230 Kbps

Timer 1 in mode 2

6 MHz

120

100

60

40

-

400

240

200

-

-

375

333

300

200

120

100

60

50

30

20

30 15

5.86 Kbps to

1500 Kbps

Timer 1 in mode 2

2.93 Kbps to

750 Kbps

Timer 1 in mode 2

12.6 I

2

C operation modes

12.6.1 Master Transmitter mode

In this mode data is transmitted from master to slave. Before the Master Transmitter mode can be entered, I2CON must be initialized as follows:

Table 100. I

2

C Control register (I2CON - address D8h)

Bit

-

7 6

I2EN

5

STA

4

STO

3

SI value 1 0 0 0

2

AA x -

-

1 0

CRSEL bit rate

CRSEL defines the bit rate. I2EN must be set to 1 to enable the I

2

C function. If the AA bit is 0, it will not acknowledge its own slave address or the general call address in the event of another device becoming master of the bus and it can not enter slave mode. STA, STO, and SI bits must be cleared to 0.

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The first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. In this case, the data direction bit (R/W) will be logic 0 indicating a write. Data is transmitted 8 bits at a time. After each byte is transmitted, an acknowledge bit is received. START and STOP conditions are output to indicate the beginning and the end of a serial transfer.

The I

2

C-bus will enter Master Transmitter Mode by setting the STA bit. The I

2

C logic will send the START condition as soon as the bus is free. After the START condition is transmitted, the SI bit is set, and the status code in I2STAT should be 08h. This status code must be used to vector to an interrupt service routine where the user should load the slave address to I2DAT (Data Register) and data direction bit (SLA+W). The SI bit must be cleared before the data transfer can continue.

When the slave address and R/W bit have been transmitted and an acknowledgment bit has been received, the SI bit is set again, and the possible status codes are 18h, 20h, or

38h for the master mode or 68h, 78h, or 0B0h if the slave mode was enabled (setting

AA = Logic 1). The appropriate action to be taken for each of these status codes is shown in

Table 102 .

S slave address R/W A DATA A DATA A/A P logic 0 = write logic 1 = read from Master to Slave from Slave to Master data transferred

(n Bytes + acknowledge)

A = acknowledge (SDA LOW)

A = not acknowledge (SDA HIGH)

S = START condition

P = STOP condition

002aaa929

Fig 36. Format in the Master Transmitter mode

12.6.2 Master Receiver mode

In the Master Receiver Mode, data is received from a slave transmitter. The transfer started in the same manner as in the Master Transmitter Mode. When the START condition has been transmitted, the interrupt service routine must load the slave address and the data direction bit to I

2

C Data Register (I2DAT). The SI bit must be cleared before the data transfer can continue.

When the slave address and data direction bit have been transmitted and an acknowledge bit has been received, the SI bit is set, and the Status Register will show the status code. For master mode, the possible status codes are 40H, 48H, or 38H. For slave mode, the possible status codes are 68H, 78H, or B0H. Refer to

Table 104 for details.

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S slave address R A DATA A DATA A P logic 0 = write logic 1 = read from Master to Slave from Slave to Master data transferred





002aaa930

Fig 37. Format of Master Receiver mode

After a repeated START condition, I

2

C-bus may switch to the Master Transmitter Mode.

S SLA R A logic 0 = write logic 1 = read

DATA A DATA A data transferred


RS from Master to Slave from Slave to Master

SLA W A DATA





SLA = slave address

RS = repeat START condition

A P

002aaa931

Fig 38. A Master Receiver switches to Master Transmitter after sending Repeated Start

12.6.3 Slave Receiver mode

In the Slave Receiver Mode, data bytes are received from a master transmitter. To initialize the Slave Receiver Mode, the user should write the slave address to the Slave

Address Register (I2ADR) and the I

2

C Control Register (I2CON) should be configured as follows:

Table 101. I

2

C Control register (I2CON - address D8h)

Bit

-

7 6

I2EN

5

STA

4

STO

3

SI value 1 0 0 0

2

AA

1 -

-

1

-

0

CRSEL

CRSEL is not used for slave mode. I2EN must be set = 1 to enable I

2

C function. AA bit must be set = 1 to acknowledge its own slave address or the general call address. STA,

STO and SI are cleared to 0.

After I2ADR and I2CON are initialized, the interface waits until it is addressed by its own address or general address followed by the data direction bit which is 0(W). If the direction bit is 1(R), it will enter Slave Transmitter Mode. After the address and the direction bit have been received, the SI bit is set and a valid status code can be read from the Status

Register(I2STAT). Refer to Table 105

for the status codes and actions.

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S slave address W A DATA A DATA A/A P/RS logic 0 = write logic 1 = read from Master to Slave from Slave to Master data transferred






RS = repeated START condition

002aaa932

Fig 39. Format of Slave Receiver mode

12.6.4 Slave Transmitter mode

The first byte is received and handled as in the Slave Receiver Mode. However, in this mode, the direction bit will indicate that the transfer direction is reversed. Serial data is transmitted via P1.3/SDA while the serial clock is input through P1.2/SCL. START and

STOP conditions are recognized as the beginning and end of a serial transfer. In a given application, the I

2

C-bus may operate as a master and as a slave. In the slave mode, the

I

2

C hardware looks for its own slave address and the general call address. If one of these addresses is detected, an interrupt is requested. When the microcontrollers wishes to become the bus master, the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted. If bus arbitration is lost in the master mode, the I

2

C-bus switches to the slave mode immediately and can detect its own slave address in the same serial transfer.

S slave address R A DATA A DATA A P logic 0 = write logic 1 = read from Master to Slave from Slave to Master data transferred






002aaa933

Fig 40. Format of Slave Transmitter mode

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P1.3/SDA

P1.2/SCL

8

ADDRESS REGISTER I2ADR

P1.3

COMPARATOR

INPUT

FILTER

OUTPUT

STAGE

INPUT

FILTER

OUTPUT

STAGE

P1.2

SHIFT REGISTER

8

ACK

I2DAT

BIT COUNTER /

ARBITRATION &

SYNC LOGIC

TIMING

AND

CONTROL

LOGIC

SERIAL CLOCK

GENERATOR timer 1 overflow

I2CON

I2SCLH

I2SCLL

CONTROL REGISTERS &

SCL DUTY CYCLE REGISTERS

8

CCLK interrupt status bus

STATUS

DECODER

I2STAT STATUS REGISTER

8

002aaa899

Fig 41. I

2

C serial interface block diagram

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Table 102. Master Transmitter mode

Status code

(I2STAT)

Status of the I

2

C hardware

Application software response to/from I2DAT to I2CON

08H

10H

18h

A START condition has been transmitted

Load SLA+W

A repeat START condition has been transmitted

Load SLA+W or

Load SLA+R x

SLA+W has been transmitted; ACK has been received

Load data byte or 0 no I2DAT action or

1 no I2DAT action or

0

STA STO SI

x 0 0

0

0

0

1

0

0

0

0 no I2DAT action 1 1 0

20h

28h

SLA+W has been transmitted;

NOT-ACK has been received

Data byte in

I2DAT has been transmitted; ACK has been received

Load data byte or no I2DAT action or no I2DAT action or no I2DAT action no I2DAT action or no I2DAT action or no I2DAT action

0

1

0

1

Load data byte or 0

1

0

1

0

0

1

1

0

0

1

1

0

0

0

0

0

0

0

0

Next action taken by I

2

C hardware

x x x x x x x x

AA

x x x x x x

SLA+W will be transmitted;

ACK bit will be received

As above; SLA+W will be transmitted; I

2

C-bus switches to Master Receiver Mode

Data byte will be transmitted;


Repeated START will be transmitted;

STOP condition will be transmitted;

STO flag will be reset

STOP condition followed by a

START condition will be transmitted; STO flag will be reset.




STOP condition will be transmitted; STO flag will be reset


START condition will be transmitted; STO flag will be reset






START condition will be transmitted; STO flag will be reset

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Table 102. Master Transmitter mode

…continued

Status code

(I2STAT)

Status of the I

2

C hardware


30h

38H

Data byte in

I2DAT has been transmitted, NOT

ACK has been received

Arbitration lost in

SLA+R/W or data bytes

STA STO SI

Load data byte or 0 0 0 no I2DAT action or no I2DAT action or no I2DAT action

No I2DAT action or

1

0

1

0

No I2DAT action 1

0

1

1

0

0

0

0

0

0

0

AA

x x x x x x

Next action taken by I hardware

2

C






START condition will be transmitted. STO flag will be reset.

I

2

C-bus will be released; not addressed slave will be entered

A START condition will be transmitted when the bus becomes free.

Table 103. Master Receiver mode

Status code

(I2STAT)

Status of the I

2

C hardware

08H


Load SLA+R

STA STO SI

x 0 0

10H

A START condition has been transmitted

A repeat START condition has been transmitted

Load SLA+R or

Load SLA+W x 0 0 x


2

C hardware

STA

x SLA+R will be transmitted; ACK bit will be received

38H

40h

48h

Arbitration lost in

NOT ACK bit

SLA+R has been transmitted; NOT

ACK has been received no I2DAT action or

0 no I2DAT action 1

SLA+R has been transmitted; ACK has been received no I2DAT action or no I2DAT action or

No I2DAT action or no I2DAT action or no I2DAT action or

0

0

1

0

1

0

0

0

0

0

1

1

0

0

0

0

0

0

0 x x

0

1 x x x

As above

SLA+W will be transmitted; I

2

C-bus will be switched to Master

Transmitter Mode

I

2

C-bus will be released; it will enter a slave mode

A START condition will be transmitted when the bus becomes free

Data byte will be received; NOT ACK bit will be returned

Data byte will be received; ACK bit will be returned

Repeated START will be transmitted



STOP condition followed by a START condition will be transmitted; STO flag will be reset

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Table 103. Master Receiver mode

…continued

Status code

(I2STAT)

Status of the I

2

C hardware


50h Read data byte

STA STO SI

0 0 0 Data byte has been received;

ACK has been returned read data byte 0 0 0

58h Data byte has been received;

NACK has been returned

Read data byte or 1 read data byte or 0

0

1

0

0 read data byte 1 1 0


2

C hardware

x x

STA

0

1 x

Data byte will be received; NOT ACK bit will be returned





STOP condition followed by a START condition will be transmitted; STO flag will be reset

Table 104. Slave Receiver mode

Status code

(I2STAT)

Status of the I

2

C hardware


60H Own SLA+W has been received;

ACK has been received no I2DAT action or no I2DAT action x

STA STO SI

x 0 0

0 0

68H

70H

78H

80H

Arbitration lost in

SLA+R/Was master; Own

SLA+W has been received, ACK returned

General call address(00H) has been received,

ACK has been returned

No I2DAT action or x no I2DAT action x

No I2DAT action or x no I2DAT action x

Arbitration lost in

SLA+R/W as master; General call address has been received,

ACK bit has been returned no I2DAT action or x no I2DAT action x

Previously addressed with own SLA address;

Data has been received; ACK has been returned

Read data byte or x read data byte x

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

AA

0

1

0

1

0

1

0

1

0

1


2 hardware

C

Data byte will be received and NOT

ACK will be returned

Data byte will be received and ACK will be returned













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…continued

Status code

(I2STAT)

Status of the I

2

C hardware


88H Previously addressed with own SLA address;

Data has been received; NACK has been returned

Read data byte or 0 read data byte

or

0

STA STO SI

0 0

0 0

90H

98H

Previously addressed with

General call; Data has been received; ACK has been returned read data byte

or read data byte

Read data byte or x read data byte

Previously addressed with

General call; Data has been received; NACK has been returned

Read data byte read data byte read data byte read data byte

1

1 x

0

0

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0


2

C hardware

AA

0

1

0

1

0

1

Switched to not addressed SLA mode; no recognition of own SLA or general address

Switched to not addressed SLA mode; Own SLA will be recognized; general call address will be recognized if I2ADR.0 = 1

Switched to not addressed SLA mode; no recognition of own SLA or

General call address. A START condition will be transmitted when the bus becomes free

Switched to not addressed SLA mode; Own slave address will be recognized; General call address will be recognized if I2ADR.0 = 1. A

START condition will be transmitted when the bus becomes free.




0

1

0

1


General call address

Switched to not addressed SLA mode; Own slave address will be recognized; General call address will be recognized if I2ADR.0 = 1.


General call address. A START condition will be transmitted when the bus becomes free.



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…continued

Status code

(I2STAT)

A0H

Status of the I

2

C hardware


A STOP condition or repeated

START condition has been received while still addressed as

SLA/REC or

SLA/TRX

No I2DAT action 0 no I2DAT action 0 no I2DAT action 1

STA STO SI

0 0

0

0

0

0 no I2DAT action 1 0 0


2

C hardware

AA

0

1

0

1


General call address






Table 105. Slave Transmitter mode

Status code

(I2STAT)

Status of the I

2

C hardware


A8h

STA STO SI

Load data byte or x 0 0 Own SLA+R has been received;

ACK has been returned load data byte x 0 0

B0h

B8H

Arbitration lost in

SLA+R/W as master; Own

SLA+R has been received, ACK has been returned

Load data byte or x load data byte x

Data byte in

I2DAT has been transmitted; ACK has been received

Load data byte or x load data byte x

0

0

0

0

0

0

0

0


2

C hardware

AA

0

1

0

1

Last data byte will be transmitted and ACK bit will be received

Data byte will be transmitted; ACK will be received


Data byte will be transmitted; ACK bit will be received

0

1


Data byte will be transmitted; ACK will be received

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Table 105. Slave Transmitter mode

…continued

Status code

(I2STAT)

Status of the I

2

C hardware


C0H Data byte in

I2DAT has been transmitted;

NACK has been received

No I2DAT action or no I2DAT action or

STA STO SI

0 0 0

0 0 0

C8H no I2DAT action or

1 no I2DAT action 1

Last data byte in

I2DAT has been transmitted

(AA = 0); ACK has been received

No I2DAT action or no I2DAT action or

0

0 no I2DAT action or

1 no I2DAT action 1

0

0

0

0

0

0

0

0

0

0

0

0


2

C hardware

AA

0

1

0

1

0

1

0

1


General call address.







General call address.






13. Serial Peripheral Interface (SPI)

The P89LPC9331/9341/9351 provides another high-speed serial communication interface, the SPI interface. SPI is a full-duplex, high-speed, synchronous communication bus with two operation modes: Master mode and Slave mode. Up to 3 Mbit/s can be supported in either Master or Slave mode. It has a Transfer Completion Flag and Write

Collision Flag Protection.

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CPU clock

DIVIDER

BY 4, 16, 64, 128

SELECT

SPI clock (master)

8-BIT SHIFT REGISTER

READ DATA BUFFER clock

CLOCK LOGIC

S

M

M

S

PIN

CONTROL

LOGIC

S

M

MISO

P2.3

MOSI

P2.2

SPICLK

P2.5

SS

P2.4

SPI CONTROL

MSTR

SPEN

SPI STATUS REGISTER

SPI interrupt request

SPI CONTROL REGISTER internal data bus

002aaa900

Fig 42. SPI block diagram

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User manual

The SPI interface has four pins: SPICLK, MOSI, MISO and SS:

•

SPICLK, MOSI and MISO are typically tied together between two or more SPI devices. Data flows from master to slave on the MOSI (Master Out Slave In) pin and flows from slave to master on the MISO (Master In Slave Out) pin. The SPICLK signal is output in the master mode and is input in the slave mode. If the SPI system is disabled, i.e. SPEN (SPCTL.6) = 0 (reset value), these pins are configured for port functions.

•

SS is the optional slave select pin. In a typical configuration, an SPI master asserts one of its port pins to select one SPI device as the current slave. An SPI slave device uses its SS pin to determine whether it is selected. The SS is ignored if any of the following conditions are true:

– If the SPI system is disabled, i.e. SPEN (SPCTL.6) = 0 (reset value)

– If the SPI is configured as a master, i.e., MSTR (SPCTL.4) = 1, and P2.4 is configured as an output (via the P2M1.4 and P2M2.4 SFR bits);

– If the SS pin is ignored, i.e. SSIG (SPCTL.7) bit = 1, this pin is configured for port functions.

Note that even if the SPI is configured as a master (MSTR = 1), it can still be converted to a slave by driving the SS pin low (if P2.4 is configured as input and SSIG = 0). Should this

happen, the SPIF bit (SPSTAT.7) will be set (see Section 13.4 “Mode change on SS”

)

Typical connections are shown in

Figure 43

to

Figure 45

.

Table 106. SPI Control register (SPCTL - address E2h) bit allocation

Bit 7

Symbol SSIG

Reset 0

6

SPEN

0

5

DORD

0

4

MSTR

0

3

CPOL

0

2

CPHA

1

Rev. 02 — 5 May 2009

1

SPR1

0

0

SPR0

0


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Table 107. SPI Control register (SPCTL - address E2h) bit description


0 SPR0

1

2

SPR1

CPHA

SPI Clock Rate Select

SPR1, SPR0:

00 —

CCLK

⁄

4

01 —

CCLK

⁄

16

10 —

CCLK

⁄

64

11 —

CCLK

⁄

128

SPI Clock PHAse select (see

Figure 46

to

Figure 49 ):

1 — Data is driven on the leading edge of SPICLK, and is sampled on the trailing edge.

0 — Data is driven when SS is low (SSIG = 0) and changes on the trailing edge of

SPICLK, and is sampled on the leading edge. (Note: If SSIG = 1, the operation is not defined.

3 CPOL

4 MSTR

SPI Clock POLarity (see

Figure 46 to

Figure 49

):

1 — SPICLK is high when idle. The leading edge of SPICLK is the falling edge and the trailing edge is the rising edge.

0 — SPICLK is low when idle. The leading edge of SPICLK is the rising edge and the trailing edge is the falling edge.

Master/Slave mode Select (see

Table 111

).

5 DORD SPI Data ORDer.

1 — The LSB of the data word is transmitted first.

0 — The MSB of the data word is transmitted first.

6 SPEN SPI Enable.

1 — The SPI is enabled.

0 — The SPI is disabled and all SPI pins will be port pins.

7 SSIG SS IGnore.

1 — MSTR (bit 4) decides whether the device is a master or slave.

0 — The SS pin decides whether the device is master or slave. The SS pin can be

used as a port pin (see Table 111 ).

Table 108. SPI Status register (SPSTAT - address E1h) bit allocation

Bit 7 6 5 4 3 2

Symbol SPIF

Reset 0

WCOL

0

x

x

x

x

1

x

0

x

Table 109. SPI Status register (SPSTAT - address E1h) bit description


0:5 reserved

6 WCOL SPI Write Collision Flag. The WCOL bit is set if the SPI data register, SPDAT, is

written during a data transfer (see Section 13.5 “Write collision” ). The WCOL flag

is cleared in software by writing a logic 1 to this bit.

7 SPIF SPI Transfer Completion Flag. When a serial transfer finishes, the SPIF bit is set and an interrupt is generated if both the ESPI (IEN1.3) bit and the EA bit are set. If

SS is an input and is driven low when SPI is in master mode, and SSIG = 0, this bit

will also be set (see Section 13.4 “Mode change on SS”

). The SPIF flag is cleared in software by writing a logic 1 to this bit.

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Table 110. SPI Data register (SPDAT - address E3h) bit allocation

Bit 7

Symbol MSB

6 5 4 3 2

Reset 0 0 0 0 0 0

1

0

0

LSB

0 master

8-BIT SHIFT

REGISTER

SPI CLOCK

GENERATOR

MISO

MOSI

SPICLK

PORT

MISO

MOSI

SPICLK

SS slave

8-BIT SHIFT

REGISTER

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002aaa901

Fig 43. SPI single master single slave configuration

In Figure 43 , SSIG (SPCTL.7) for the slave is logic 0, and SS is used to select the slave.

The SPI master can use any port pin (including P2.4/SS) to drive the SS pin.

master

8-BIT SHIFT

REGISTER

SPI CLOCK

GENERATOR

MISO

MOSI

SPICLK

SS

MISO

MOSI

SPICLK

SS slave

8-BIT SHIFT

REGISTER

SPI CLOCK

GENERATOR

002aaa902

Fig 44. SPI dual device configuration, where either can be a master or a slave

Figure 44

shows a case where two devices are connected to each other and either device can be a master or a slave. When no SPI operation is occurring, both can be configured as masters (MSTR = 1) with SSIG cleared to 0 and P2.4 (SS) configured in quasi-bidirectional mode. When a device initiates a transfer, it can configure P2.4 as an output and drive it low, forcing a mode change in the other device (see

Section 13.4

“Mode change on SS” ) to slave.

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master

8-BIT SHIFT

REGISTER

SPI CLOCK

GENERATOR

MISO

MOSI

SPICLK port

MISO

MOSI

SPICLK

SS slave

8-BIT SHIFT

REGISTER

MISO

MOSI slave

8-BIT SHIFT

REGISTER port

SPICLK

SS

002aaa903

Fig 45. SPI single master multiple slaves configuration

In Figure 45 , SSIG (SPCTL.7) bits for the slaves are logic 0, and the slaves are selected

by the corresponding SS signals. The SPI master can use any port pin (including

P2.4/SS) to drive the SS pins.

13.1 Configuring the SPI

Table 111 shows configuration for the master/slave modes as well as usages and

directions for the modes.

Table 111. SPI master and slave selection

SPEN SSIG SS Pin MSTR Master or Slave

Mode

0 x P2.4

[1]

x SPI

Disabled

MISO MOSI SPICLK Remarks

P2.3

[1]

P2.2

[1]

P2.5

[1]

SPI disabled. P2.2, P2.3, P2.4, P2.5 are used as port pins.

1 0 0 0 Slave output input input Selected as slave.

1 0 1 0 Slave Hi-Z input input

1 0 0 1 (->

0)

[2]

Slave output input input

Not selected. MISO is high-impedance to avoid bus contention.

P2.4/SS is configured as an input or quasi-bidirectional pin. SSIG is 0. Selected externally as slave if SS is selected and is driven low. The MSTR bit will be cleared to logic 0 when SS becomes low.

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Table 111. SPI master and slave selection

…continued

SPEN SSIG SS Pin MSTR Master or Slave

Mode

MISO MOSI SPICLK Remarks

1 0 1 1 Master

(idle) input Hi-Z Hi-Z MOSI and SPICLK are at high-impedance to avoid bus contention when the MAster is idle.

The application must pull-up or pull-down

SPICLK (depending on CPOL - SPCTL.3) to avoid a floating SPICLK.

1

1

1

1

P2.4

P2.4

[1]

[1]

0

1

Master

(active)

Slave

Master input output output input output output input output

MOSI and SPICLK are push-pull when the

Master is active.

[1] Selected as a port function

[2] The MSTR bit changes to logic 0 automatically when SS becomes low in input mode and SSIG is logic 0.

13.2 Additional considerations for a slave

When CPHA equals zero, SSIG must be logic 0 and the SS pin must be negated and reasserted between each successive serial byte. If the SPDAT register is written while SS is active (low), a write collision error results. The operation is undefined if CPHA is logic 0 and SSIG is logic 1.

When CPHA equals one, SSIG may be set to logic 1. If SSIG = 0, the SS pin may remain active low between successive transfers (can be tied low at all times). This format is sometimes preferred in systems having a single fixed master and a single slave driving the MISO data line.

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13.3 Additional considerations for a master

In SPI, transfers are always initiated by the master. If the SPI is enabled (SPEN = 1) and selected as master, writing to the SPI data register by the master starts the SPI clock generator and data transfer. The data will start to appear on MOSI about one half SPI bit-time to one SPI bit-time after data is written to SPDAT.

Note that the master can select a slave by driving the SS pin of the corresponding device low. Data written to the SPDAT register of the master is shifted out of the MOSI pin of the master to the MOSI pin of the slave, at the same time the data in SPDAT register in slave side is shifted out on MISO pin to the MISO pin of the master.

After shifting one byte, the SPI clock generator stops, setting the transfer completion flag

(SPIF) and an interrupt will be created if the SPI interrupt is enabled (ESPI, or IEN1.3 = 1).

The two shift registers in the master CPU and slave CPU can be considered as one distributed 16-bit circular shift register. When data is shifted from the master to the slave, data is also shifted in the opposite direction simultaneously. This means that during one shift cycle, data in the master and the slave are interchanged.

13.4 Mode change on SS

If SPEN = 1, SSIG = 0 and MSTR = 1, the SPI is enabled in master mode. The SS pin can be configured as an input (P2M2.4, P2M1.4 = 00) or quasi-bidirectional (P2M2.4, P2M1.4

= 01). In this case, another master can drive this pin low to select this device as an SPI

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slave and start sending data to it. To avoid bus contention, the SPI becomes a slave. As a result of the SPI becoming a slave, the MOSI and SPICLK pins are forced to be an input and MISO becomes an output.

The SPIF flag in SPSTAT is set, and if the SPI interrupt is enabled, an SPI interrupt will occur.

User software should always check the MSTR bit. If this bit is cleared by a slave select and the user wants to continue to use the SPI as a master, the user must set the MSTR bit again, otherwise it will stay in slave mode.

13.5 Write collision

The SPI is single buffered in the transmit direction and double buffered in the receive direction. New data for transmission can not be written to the shift register until the previous transaction is complete. The WCOL (SPSTAT.6) bit is set to indicate data collision when the data register is written during transmission. In this case, the data currently being transmitted will continue to be transmitted, but the new data, i.e., the one causing the collision, will be lost.

While write collision is detected for both a master or a slave, it is uncommon for a master because the master has full control of the transfer in progress. The slave, however, has no control over when the master will initiate a transfer and therefore collision can occur.

For receiving data, received data is transferred into a parallel read data buffer so that the shift register is free to accept a second character. However, the received character must be read from the Data Register before the next character has been completely shifted in.

Otherwise. the previous data is lost.

WCOL can be cleared in software by writing a logic 1 to the bit.

13.6 Data mode

Clock Phase Bit (CPHA) allows the user to set the edges for sampling and changing data.

The Clock Polarity bit, CPOL, allows the user to set the clock polarity.

Figure 46

to

Figure 49

show the different settings of Clock Phase bit CPHA.

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Clock cycle

SPICLK (CPOL = 0)

SPICLK (CPOL = 1)

1 2 3 4 5 6 7 8

MOSI (input)

DORD = 0

DORD = 1

MISO (output)

DORD = 0

DORD = 1

MSB

LSB

MSB

LSB

6

1

6

1

5

2

5

2

4

3

4

3

3

4

3

4

2

5

2

5

1

6

1

6

LSB

MSB

LSB

MSB

(1)

SS (if SSIG bit = 0)

002aaa934

(1) Not defined

Fig 46. SPI slave transfer format with CPHA = 0

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Clock cycle

SPICLK (CPOL = 0)

SPICLK (CPOL = 1)

1 2 3 4 5 6 7 8

MOSI (input)

DORD = 0

DORD = 1

MSB

LSB

6

1

MISO (output)

DORD = 0

DORD = 1

(1)

MSB

LSB

6

1

5

2

5

2

4

3

4

3

3

4

3

4

2

5

2

5

1

6

1

6

LSB

MSB

LSB

MSB


002aaa935

(1) Not defined

Fig 47. SPI slave transfer format with CPHA = 1

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Clock cycle

SPICLK (CPOL = 0)

SPICLK (CPOL = 1)

1 2 3 4 5 6 7 8

MOSI (input)

DORD = 0

DORD = 1

MSB

LSB

MISO (output)

DORD = 0

DORD = 1

MSB

LSB

6

1

6

1

5

2

5

2

4

3

4

3

3

4

3

4

2

5

2

5

1

6

1

6

LSB

MSB

LSB

MSB


002aaa936

(1) Not defined

Fig 48. SPI master transfer format with CPHA = 0

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Clock cycle

SPICLK (CPOL = 0)

SPICLK (CPOL = 1)

1 2 3 4 5 6 7 8

MOSI (input)

MISO (output)

DORD = 0

DORD = 1

MSB

LSB

6

1

DORD = 0

DORD = 1

MSB

LSB

6

1

5

2

5

2

4

3

4

3

3

4

3

4

2

5

2

5

1

6

1

6

LSB

MSB

LSB

MSB


002aaa937

(1) Not defined

Fig 49. SPI master transfer format with CPHA = 1

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13.7 SPI clock prescaler select

The SPI clock prescaler selection uses the SPR1-SPR0 bits in the SPCTL register (see

Table 107 ).

14. Analog comparators

Two analog comparators are provided on the P89LPC9331/9341/9351. Input and output options allow use of the comparators in a number of different configurations. Comparator operation is such that the output is a logic 1 (which may be read in a register and/or routed to a pin) when the positive input (one of two selectable pins) is greater than the negative input (selectable from a pin or an internal reference voltage). Otherwise the output is a zero. Each comparator may be configured to cause an interrupt when the output value changes.

In LPC9351, the comparators inputs can be amplified by using PGA1 module. The PGA1 can supply gain factors of 2x, 4x, 8x, or 16x, eliminating the need for external opamps in

the end application. Refer to Section 3.2.1 “Programmable Gain Amplifier (PGA)

(P89LPC9351)” for PGA details.

14.1 Comparator configuration

Each comparator has a control register, CMP1 for comparator 1 and CMP2 for comparator

2. The control registers are identical and are shown in

Table 113

.

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The overall connections to both comparators are shown in Figure 50 and Figure 51 . There

are eight possible configurations for each comparator, as determined by the control bits in the corresponding CMPn register: CPn, CNn, and OEn. These configurations are shown in

Figure 52 .

When each comparator is first enabled, the comparator output and interrupt flag are not guaranteed to be stable for 10 microseconds. The corresponding comparator interrupt should not be enabled during that time, and the comparator interrupt flag must be cleared before the interrupt is enabled in order to prevent an immediate interrupt service.

Table 112. Comparator Control register (CMP1 - address ACh, CMP2 - address ADh) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol -

Reset x

x

CEn

0

CPn

0

CNn

0

OEn

0

COn

0

CMFn

0

Table 113. Comparator Control register (CMP1 - address ACh, CMP2 - address ADh) bit description


0 CMFn Comparator interrupt flag. This bit is set by hardware whenever the comparator output COn changes state. This bit will cause a hardware interrupt if enabled.


1 COn

2 OEn

3

4

CNn

CPn

Comparator output, synchronized to the CPU clock to allow reading by software.

Output enable. When logic 1, the comparator output is connected to the CMPn pin if the comparator is enabled (CEn = 1). This output is asynchronous to the CPU clock.

Comparator negative input select. When logic 0, the comparator reference pin

CMPREF is selected as the negative comparator input. When logic 1, the internal comparator reference, V

REF

, is selected as the negative comparator input.

Comparator positive input select. When logic 0, CINnA is selected as the positive comparator input. When logic 1, CINnB is selected as the positive comparator input.

5 CEn

6:7 -

Comparator enable. When set, the corresponding comparator function is enabled.

Comparator output is stable 10 microseconds after CEn is set.

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(P0.4) CIN1A

(P0.3) CIN1B

(P0.5) CMPREF

V ref(bg)

CP1 comparator 1

CO1

OE1 change detect

CN1

CMF1

CMP1 (P0.6) interrupt

CP2 comparator 2 change detect

CMF2

(P0.2) CIN2A

(P0.1) CIN2B

CO2

OE2

CN2

Fig 50. P89LPC9331/9341 comparator input and output connections

(P0.4) CIN1A

(P0.3) CIN1B

PGA1

(P0.2) CIN2A

(P0.1) CIN2B

(P0.5) CMPREF

V ref(bg)

CP1 comparator 1

CO1

OE1 change detect

CN1

CMP2 (P0.0)

CMF1

EC

002aae483

CMP1 (P0.6) interrupt

CP2 comparator 2 change detect

CMF2

EC

CMP2 (P0.0)

CO2

CN2

Fig 51. P89LPC9351 comparator input and output connections

OE2

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002aad561

14.2 Internal reference voltage

An internal reference voltage, V ref(bg)

, may supply a default reference when a single comparator input pin is used. Please refer to the P89LPC9331/9341/9351 data sheet for specifications.

14.3 Comparator input pins

Comparator input and reference pins maybe be used as either digital I/O or as inputs to the comparator. When used as digital I/O these pins are 5 V tolerant. However, when selected as comparator input signals in CMPn lower voltage limits apply. Please refer to the P89LPC9331/9341/9351 data sheet for specifications.

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14.4 Comparator interrupt

Each comparator has an interrupt flag CMFn contained in its configuration register. This flag is set whenever the comparator output changes state. The flag may be polled by software or may be used to generate an interrupt. The two comparators use one common interrupt vector. The interrupt will be generated when the interrupt enable bit EC in the

IEN1 register is set and the interrupt system is enabled via the EA bit in the IEN0 register.

If both comparators enable interrupts, after entering the interrupt service routine, the user will need to read the flags to determine which comparator caused the interrupt.

When a comparator is disabled the comparator’s output, COx, goes high. If the comparator output was low and then is disabled, the resulting transition of the comparator output from a low to high state will set the comparator flag, CMFx. This will cause an interrupt if the comparator interrupt is enabled. The user should therefore disable the comparator interrupt prior to disabling the comparator. Additionally, the user should clear the comparator flag, CMFx, after disabling the comparator.

14.5 Comparators and power reduction modes

Either or both comparators may remain enabled when Power-down mode or Idle mode is activated, but both comparators are disabled automatically in Total Power-down mode.

If a comparator interrupt is enabled (except in Total Power-down mode), a change of the comparator output state will generate an interrupt and wake-up the processor. If the comparator output to a pin is enabled, the pin should be configured in the push-pull mode in order to obtain fast switching times while in Power-down mode. The reason is that with the oscillator stopped, the temporary strong pull-up that normally occurs during switching on a quasi-bidirectional port pin does not take place.

Comparators consume power in Power-down mode and Idle mode, as well as in the normal operating mode. This should be taken into consideration when system power consumption is an issue. To minimize power consumption, the user can power-down the comparators by disabling the comparators and setting PCONA.5 to logic 1, or simply putting the device in Total Power-down mode.

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CINnA

CMPREF

COn

002aaa618 a. CPn, CNn, OEn = 0 0 0

CINnA

V

REF

(1.23 V)

COn

002aaa621 c. CPn, CNn, OEn = 0 1 0

CINnA

CMPREF

COn

CMPn

002aaa620 b. CPn, CNn, OEn = 0 0 1

CINnA

V

REF

(1.23 V)

COn

CMPn

002aaa622 d. CPn, CNn, OEn = 0 1 1

CINnB

CMPREF

COn

002aaa623 e. CPn, CNn, OEn = 1 0 0

CINnB

CMPREF

COn

CMPn

002aaa624 f. CPn, CNn, OEn = 1 0 1

CINnB

V

REF

(1.23 V)

COn

002aaa625

CINnB

V

REF

(1.23 V)

COn

CMPn

002aaa626 g. CPn, CNn, OEn = 1 1 0 h. CPn, CNn, OEn = 1 1 1

Fig 52. Comparator configurations. (Suppose PGA1 is disabled, or gain = 1)

14.6 Comparators configuration example

The code shown below is an example of initializing one comparator. Comparator 1 is configured to use the CIN1A and CMPREF inputs, outputs the comparator result to the

CMP1 pin, and generates an interrupt when the comparator output changes.

CMPINIT:

MOV PT0AD,#030h

ANL P0M2,#0CFh

ORL P0M1,#030h

MOV CMP1,#024h

;Disable digital INPUTS on CIN1A, CMPREF.

;Disable digital OUTPUTS on pins that are used

;for analog functions: CIN1A, CMPREF.

;Turn on comparator 1 and set up for:

;Positive input on CIN1A.

;Negative input from CMPREF pin.

CALL delay10us before use.

ANL CMP1,#0FEh

SETB EC

SETB EA

RET

;Output to CMP1 pin enabled.

;The comparator needs at least 10 microseconds

;Clear comparator 1 interrupt flag.

;Enable the comparator interrupt,

;Enable the interrupt system (if needed).

;Return to caller.

The interrupt routine used for the comparator must clear the interrupt flag (CMF1 in this case) before returning

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15. Keypad interrupt (KBI)

The Keypad Interrupt function is intended primarily to allow a single interrupt to be generated when Port 0 is equal to or not equal to a certain pattern. This function can be used for bus address recognition or keypad recognition. The user can configure the port via SFRs for different tasks.

There are three SFRs used for this function. The Keypad Interrupt Mask Register

(KBMASK) is used to define which input pins connected to Port 0 are enabled to trigger the interrupt. The Keypad Pattern Register (KBPATN) is used to define a pattern that is compared to the value of Port 0. The Keypad Interrupt Flag (KBIF) in the Keypad Interrupt

Control Register (KBCON) is set when the condition is matched while the Keypad

Interrupt function is active. An interrupt will be generated if it has been enabled by setting the EKBI bit in IEN1 register and EA = 1. The PATN_SEL bit in the Keypad Interrupt

Control Register (KBCON) is used to define equal or not-equal for the comparison.

In order to use the Keypad Interrupt as an original KBI function like in the 87LPC76x series, the user needs to set KBPATN = 0FFH and PATN_SEL = 0 (not equal), then any key connected to Port0 which is enabled by KBMASK register is will cause the hardware to set KBIF = 1 and generate an interrupt if it has been enabled. The interrupt may be used to wake-up the CPU from Idle or Power-down modes. This feature is particularly useful in handheld, battery powered systems that need to carefully manage power consumption yet also need to be convenient to use.

In order to set the flag and cause an interrupt, the pattern on Port 0 must be held longer than 6 CCLKs

Table 114. Keypad Pattern register (KBPATN - address 93h) bit allocation

Bit

Symbol

Reset

7

1

6

1

5

1

4

1

3

1

2

KBPATN.7

KBPATN.6

KBPATN.5

KBPATN.4

KBPATN.3

KBPATN.2

KBPATN.1

KBPATN.0

1

1

1

0

1

Table 115. Keypad Pattern register (KBPATN - address 93h) bit description

Bit Symbol Access Description

0:7 KBPATN.7:0 R/W Pattern bit 0 - bit 7

Table 116. Keypad Control register (KBCON - address 94h) bit allocation

Bit

Symbol

Reset

-

7

x

-

6

x

-

5

x

-

4

x

-

3

x

-

2

x

1 0

PATN_SEL KBIF

0 0

Table 117. Keypad Control register (KBCON - address 94h) bit description

Bit Symbol Access Description

0 KBIF R/W Keypad Interrupt Flag. Set when Port 0 matches user defined conditions specified in KBPATN,

KBMASK, and PATN_SEL. Needs to be cleared by software by writing logic 0.

1 PATN_SEL R/W

2:7 -

Pattern Matching Polarity selection. When set, Port 0 has to be equal to the user-defined

Pattern in KBPATN to generate the interrupt. When clear, Port 0 has to be not equal to the value of KBPATN register to generate the interrupt.

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Table 118. Keypad Interrupt Mask register (KBMASK - address 86h) bit allocation

Bit

Symbol

Reset

7

0

6

0

5

0

4

0

3

0

2

0

1

KBMASK.7

KBMASK.6

KBMASK.5

KBMASK.4

KBMASK.3

KBMASK.2

KBMASK.1

KBMASK.0

0

0

0

Table 119. Keypad Interrupt Mask register (KBMASK - address 86h) bit description


0 KBMASK.0

When set, enables P0.0 as a cause of a Keypad Interrupt.

1 KBMASK.1


2 KBMASK.2


3 KBMASK.3


4 KBMASK.4


5 KBMASK.5


6 KBMASK.6


7 KBMASK.7


[1] The Keypad Interrupt must be enabled in order for the settings of the KBMASK register to be effective.

16. Watchdog timer (WDT)

The watchdog timer subsystem protects the system from incorrect code execution by causing a system reset when it underflows as a result of a failure of software to feed the timer prior to the timer reaching its terminal count. The watchdog timer can only be reset by a power-on reset.

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16.1 Watchdog function

The user has the ability using the WDCON, CLKCON and UCFG1 registers to control the run /stop condition of the WDT, the clock source for the WDT, the prescaler value, and whether the WDT is enabled to reset the device on underflow. In addition, there is a safety mechanism which forces the WDT to be enabled by values programmed into UCFG1 either through IAP or a commercial programmer.

The WDTE bit (UCFG1.7), if set, enables the WDT to reset the device on underflow.

Following reset, the WDT will be running regardless of the state of the WDTE bit.

The WDRUN bit (WDCON.2) can be set to start the WDT and cleared to stop the WDT.

Following reset this bit will be set and the WDT will be running. All writes to WDCON need

to be followed by a feed sequence (see Section 16.2

). Additional bits in WDCON allow the

user to select the clock source for the WDT and the prescaler.

When the timer is not enabled to reset the device on underflow, the WDT can be used in

‘timer mode’ and be enabled to produce an interrupt (IEN0.6) if desired.

The Watchdog Safety Enable bit, WDSE (UCFG1.4) along with WDTE, is designed to force certain operating conditions at power-up. Refer to

Table 120

for details.

Figure 54

shows the watchdog timer in watchdog mode. It consists of a programmable

13-bit prescaler, and an 8-bit down counter. The down counter is clocked (decremented) by a tap taken from the prescaler. The clock source for the prescaler is either PCLK,

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crystal oscillator or the watchdog oscillator selected by the WDCLK bit in the WDCON register and XTALWD bit in the CLKCON register. (Note that switching of the clock sources will not take effect immediately - see

Section 16.3

).

The watchdog asserts the watchdog reset when the watchdog count underflows and the watchdog reset is enabled. When the watchdog reset is enabled, writing to WDL or

WDCON must be followed by a feed sequence for the new values to take effect.

If a watchdog reset occurs, its behavior is similar to power on reset. Both POF and BOF are cleared.

Table 120. Watchdog timer configuration

WDTE WDSE FUNCTION

0 x

1 0

The watchdog reset is disabled. The timer can be used as an internal timer and can be used to generate an interrupt. WDSE has no effect.

The watchdog reset is enabled. The user can set WDCLK to choose the clock source.

1 1 The watchdog reset is enabled, along with additional safety features:

1. WDCLK is forced to 1 (using watchdog oscillator)

2. WDCON and WDL register can only be written once

3. WDRUN is forced to 1

PCLK

0

Watchdog oscillator

1 crystal oscillator

0

1

÷32

Watchdog clock after a Watchdog feed sequence

÷32

XTALWD

PRE2

PRE1

PRE0

DECODE

000

001

010

011

100

101

110

111

÷64

÷2

÷128

÷2

÷256

÷2

÷512

÷2

÷1024

÷2 ÷2

÷2048 ÷4096

÷2

TO WATCHDOG

DOWN COUNTER

(after one prescaler count delay)

002aae092

Fig 53. Watchdog Prescaler

16.2 Feed sequence

The watchdog timer control register and the 8-bit down counter (See Figure 54 ) are not

directly loaded by the user. The user writes to the WDCON and the WDL SFRs. At the end of a feed sequence, the values in the WDCON and WDL SFRs are loaded to the control register and the 8-bit down counter. Before the feed sequence, any new values written to these two SFRs will not take effect. To avoid a watchdog reset, the watchdog timer needs to be fed (via a special sequence of software action called the feed sequence) prior to reaching an underflow.

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To feed the watchdog, two write instructions must be sequentially executed successfully.

Between the two write instructions, SFR reads are allowed, but writes are not allowed.

The instructions should move A5H to the WFEED1 register and then 5AH to the WFEED2 register. An incorrect feed sequence will cause an immediate watchdog reset. The program sequence to feed the watchdog timer is as follows:

CLR EA ;disable interrupt

MOV WFEED1,#0A5h ;do watchdog feed part 1

MOV WFEED2,#05Ah ;do watchdog feed part 2

SETB EA ;enable interrupt

This sequence assumes that the P89LPC9331/9341/9351 interrupt system is enabled and there is a possibility of an interrupt request occurring during the feed sequence. If an interrupt was allowed to be serviced and the service routine contained any SFR writes, it would trigger a watchdog reset. If it is known that no interrupt could occur during the feed sequence, the instructions to disable and re-enable interrupts may be removed.

In watchdog mode (WDTE = 1), writing the WDCON register must be IMMEDIATELY followed by a feed sequence to load the WDL to the 8-bit down counter, and the WDCON to the shadow register. If writing to the WDCON register is not immediately followed by the feed sequence, a watchdog reset will occur.

For example: setting WDRUN = 1:

MOV ACC,WDCON ;get WDCON

SETB ACC.2 ;set WD_RUN=1

MOV WDL,#0FFh ;New count to be loaded to 8-bit down counter

CLR EA ;disable interrupt

MOV WDCON,ACC ;write back to WDCON (after the watchdog is enabled, a feed

MOV WFEED1,#0A5h ;do watchdog feed part 1

MOV WFEED2,#05Ah ;do watchdog feed part 2

SETB EA ;enable interrupt

In timer mode (WDTE = 0), WDCON is loaded to the control register every CCLK cycle

(no feed sequence is required to load the control register), but a feed sequence is required to load from the WDL SFR to the 8-bit down counter before a time-out occurs.

The number of watchdog clocks before timing out is calculated by the following equations:

tclks

=

(

2

(

5

+

PRE

)

(3) where:

PRE is the value of prescaler (PRE2 to PRE0) which can be the range 0 to 7, and;

WDL is the value of watchdog load register which can be the range of 0 to 255.

The minimum number of tclks is:

tclks

=

(

2

(

5

+

0

)

The maximum number of tclks is:

(4)

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Table 121. Watchdog Timer Control register (WDCON - address A7h) bit allocation

Bit

Symbol

Reset

0

WDCLK

1

(5)

Table 122. Watchdog Timer Control register (WDCON - address A7h) bit description


0 WDCLK Watchdog input clock select. When set, the watchdog oscillator is selected. When cleared, PCLK is selected. (If the CPU is powered down, the watchdog is disabled if WDCLK = 0, see

Section 16.5

). (Note: If

both WDTE and WDSE are set to 1, this bit is forced to 1.) Refer to Section 16.3

for details.

1 WDTOF Watchdog Timer Time-Out Flag. This bit is set when the 8-bit down counter underflows. In watchdog mode, a feed sequence will clear this bit. It can also be cleared by writing a logic 0 to this bit in software.

2 WDRUN Watchdog Run Control. The watchdog timer is started when WDRUN = 1 and stopped when WDRUN = 0.

This bit is forced to 1 (watchdog running) and cannot be cleared to zero if both WDTE and WDSE are set to

1.

reserved 3:4 -

5 PRE0

6 PRE1

7 PRE2

Clock Prescaler Tap Select. Refer to Table 123 for details.

Table 123. Watchdog timeout vales

PRE2 to PRE0 WDL in decimal)

000

001

010

011

100

101

110

111

7

PRE2

1

tclks

=

(

2

(

5

+

7

)

Table 123 shows sample P89LPC9331/9341/9351 timeout values.

0

0

0

0

0

0

0

0

6

PRE1

1

255

255

255

255

255

255

255

255

5

PRE0

1

-

4

x

-

3

x

2

WDRUN

1

1

WDTOF

1/0

33

8,193

65

16,385

129

32,769

257

65,537

513

131,073

1,025

262,145

2,049

524,289

4097

1,048,577

Timeout Period

(in watchdog clock cycles)

Watchdog Clock Source

400 KHz Watchdog

Oscillator Clock

(Nominal)

82.5

µs

20.5 ms

162.5

µs

41.0 ms

322.5

µs

81.9 ms

642.5

µs

163.8 ms

1.28 ms

327.7 ms

2.56 ms

655.4 ms

5.12 ms

1.31 s

10.2 ms

2.62 s

12 MHz CCLK (6 MHz

CCLK

⁄

2

Watchdog

Clock)

5.50

µs

1.37 ms

10.8

µs

2.73 ms

21.5

µs

5.46 ms

42.8

µs

10.9 ms

85.5

µs

21.8 ms

170.8

µs

43.7 ms

341.5

µs

87.4 ms

682.8

µs

174.8 ms

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16.3 Watchdog clock source

The watchdog timer system has an on-chip 400 KHz oscillator. The watchdog timer can be clocked from the watchdog oscillator, PCLK or crystal oscillator (refer to

Figure 53

) by configuring the WDCLK bit in the Watchdog Control Register WDCON and XTALWD bit in

CLKCON register. When the watchdog feature is enabled, the timer must be fed regularly by software in order to prevent it from resetting the CPU.

Table 124. Watchdog input clock selection

WDCLK(WDCON.0) XTALWD(CLKCON.4)

0

1 x

0

0

1

Watchdog input clock selection

PCLK watchdog oscillator

Crystal oscillator

WDCLK bit is used to switch between watchdog oscillator and PCLK. And XTALWD bit is used to switch between watchdog oscillator/PCLK and crystal oscillator. After changing clock source, switching of the clock source will not immediately take effect. As shown in

Figure 55

, the selection is loaded after a watchdog feed sequence. In addition, due to clock synchronization logic, it can take two old clock cycles before the old clock source is deselected, and then an additional two new clock cycles before the new clock source is selected.

Since the prescaler starts counting immediately after a feed, switching clocks can cause some inaccuracy in the prescaler count. The inaccuracy could be as much as 2 old clock source counts plus 2 new clock cycles.

Note: When switching clocks, it is important that the old clock source is left enabled for two clock cycles after the feed completes. Otherwise, the watchdog may become disabled when the old clock source is disabled. For example, suppose PCLK (WCLK = 0) is the current clock source. After WCLK is set to logic 1, the program should wait at least two

PCLK cycles (4 CCLKs) after the feed completes before going into Power-down mode.

Otherwise, the watchdog could become disabled when CCLK turns off. The watchdog oscillator will never become selected as the clock source unless CCLK is turned on again first.

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MOV WFEED1, #0A5H

MOV WFEED2, #05AH

PCLK

Watchdog oscillator

0

0


1

XTALWD

÷32

WDL (C1H)

PRESCALER

8-BIT DOWN

COUNTER

SHADOW REGISTER reset

WDCON (A7H)

PRE2 PRE1 PRE0 WDRUN WDTOF WDCLK

002aae093

Fig 54. Watchdog Timer in Watchdog Mode (WDTE = 1)

16.4 Watchdog Timer in Timer mode

Figure 55

shows the Watchdog Timer in Timer Mode. In this mode, any changes to

WDCON are written to the shadow register after one watchdog clock cycle. A watchdog underflow will set the WDTOF bit. If IEN0.6 is set, the watchdog underflow is enabled to cause an interrupt. WDTOF is cleared by writing a logic 0 to this bit in software. When an underflow occurs, the contents of WDL is reloaded into the down counter and the watchdog timer immediately begins to count down again.

A feed is necessary to cause WDL to be loaded into the down counter before an underflow occurs. Incorrect feeds are ignored in this mode.

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PCLK

Watchdog oscillator

MOV WFEED1, #0A5H

MOV WFEED2, #05AH

0

0


1

÷32

XTALWD

WDL (C1H)

PRESCALER

8-BIT DOWN

COUNTER

SHADOW REGISTER interrupt

WDCON (A7H) PRE2 PRE1 PRE0 WDRUN WDTOF WDCLK

002aae094

Fig 55. Watchdog Timer in Timer Mode (WDTE = 0)

16.5 Power-down operation

The WDT oscillator and external crystal oscillator will continue to run in power-down, consuming approximately 50

µA, as long as the WDT oscillator is selected as the clock source for the WDT. Selecting PCLK as the WDT source will result in the WDT oscillator

going into power-down with the rest of the device (see Section 16.3

). Power-down mode

will also prevent PCLK from running and therefore the watchdog is effectively disabled.

16.6 Periodic wake-up from power-down without an external oscillator

Without using an external oscillator source, the power consumption required in order to have a periodic wake-up is determined by the power consumption of the internal oscillator source used to produce the wake-up. The Real-time clock running from the internal RC oscillator can be used. The power consumption of this oscillator is approximately 300

µA.

Instead, if the WDT is used to generate interrupts the current is reduced to approximately

50

µA. Whenever the WDT underflows, the device will wake-up.

17. Additional features

The AUXR1 register contains several special purpose control bits that relate to several

chip features. AUXR1 is described in Table 126

Table 125. AUXR1 register (address A2h) bit allocation

Bit 7 6 5 4 3

Symbol CLKLP EBRR

Reset 0 0

ENT1

0

ENT0

0

SRST

0

2

0

0

1

x

0

DPS

0

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Table 126. AUXR1 register (address A2h) bit description


0 DPS Data Pointer Select. Chooses one of two Data Pointers.

1

2

3

4

-

0

SRST

ENT0

Not used. Allowable to set to a logic 1.

This bit contains a hard-wired 0. Allows toggling of the DPS bit by incrementing

AUXR1, without interfering with other bits in the register.

Software Reset. When set by software, resets the P89LPC9331/9341/9351 as if a hardware reset occurred.

When set the P1.2 pin is toggled whenever Timer 0 overflows. The output frequency is therefore one half of the Timer 0 overflow rate. Refer to

Section 8

“Timers 0 and 1” for details.

5

6

ENT1

EBRR

When set, the P0.7 pin is toggled whenever Timer 1 overflows. The output frequency is therefore one half of the Timer 1 overflow rate. Refer to

Section 8

“Timers 0 and 1” for details.

UART Break Detect Reset Enable. If logic 1, UART Break Detect will cause a chip reset and force the device into ISP mode.

7 CLKLP Clock Low Power Select. When set, reduces power consumption in the clock circuits. Can be used when the clock frequency is 8 MHz or less. After reset this bit is cleared to support up to 12 MHz operation.

17.1 Software reset

The SRST bit in AUXR1 gives software the opportunity to reset the processor completely, as if an external reset or watchdog reset had occurred. If a value is written to AUXR1 that contains a 1 at bit position 3, all SFRs will be initialized and execution will resume at program address 0000. Care should be taken when writing to AUXR1 to avoid accidental software resets.

17.2 Dual Data Pointers

The dual Data Pointers (DPTR) adds to the ways in which the processor can specify the address used with certain instructions. The DPS bit in the AUXR1 register selects one of the two Data Pointers. The DPTR that is not currently selected is not accessible to software unless the DPS bit is toggled.

Specific instructions affected by the Data Pointer selection are:

INC DPTR — Increments the Data Pointer by 1

JMP@A+DPTR — Jump indirect relative to DPTR value

MOV DPTR, #data16 — Load the Data Pointer with a 16-bit constant

MOVC A, @A+DPTR — Move code byte relative to DPTR to the accumulator

MOVX A, @DPTR — Move accumulator to data memory relative to DPTR

MOVX @DPTR, A — Move from data memory relative to DPTR to the accumulator

Also, any instruction that reads or manipulates the DPH and DPL registers (the upper and lower bytes of the current DPTR) will be affected by the setting of DPS. The MOVX instructions have limited application for the P89LPC9331/9341/9351 since the part does not have an external data bus. However, they may be used to access Flash configuration information (see Flash Configuration section) or auxiliary data (XDATA) memory.

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Bit 2 of AUXR1 is permanently wired as a logic 0. This is so that the DPS bit may be toggled (thereby switching Data Pointers) simply by incrementing the AUXR1 register, without the possibility of inadvertently altering other bits in the register.

18. Data EEPROM (P89LPC9351)

The P89LPC9331/9341/9351 has 512 bytes of on-chip Data EEPROM that can be used to save configuration parameters. The Data EEPROM is SFR based, byte readable, byte writable, and erasable (via row fill and sector fill). The user can read, write, and fill the memory via three SFRs and one interrupt:

•

Address Register (DEEADR) is used for address bits 7 to 0 (bit 8 is in the DEECON register).

•

Control Register (DEECON) is used for address bit 8, setup operation mode, and

status flag bit (see Table 127

).

•

Data Register (DEEDAT) is used for writing data to, or reading data from, the Data

EEPROM.

Table 127. Data EEPROM control register (DEECON address F1h) bit allocation

Bit 7 6 5 4 3 2 1

Symbol EEIF HVERR ECTL1 ECTL0 -

Reset 0 0 0 0 0

EWERR

1

0

EWERR

0

0

0

EADR8

0

Table 128. Data EEPROM control register (DEECON address F1h) bit description


0 EADR8 Most significant address (bit 8) of the Data EEPROM. EADR7-0 are in DEEADR.

1 EWERR

0

2

3 -

EWERR

1

Data EEPROM write error flag 0. Set when V

DD

< 2.4V during program or erase operation to indicate the previous operation may not be correct. Can be cleared by power on reset, watchdog reset or software write.

Data EEPROM write error flag 1. Set when a program or erase is requested and

V

DD

< 2.4V. Can be cleared by power on reset, watchdog reset or software write.

Reserved.

5:4 ECTL1:0 Operation mode selection:

The following modes are selected by ECTL[1:0]:

00 — Byte read / write mode.

01 — Reserved.

10 — Row (64 bytes) fill.

11 — Block fill (512 bytes).

6 HVERR High voltage error. Indicates a programming voltage error during program or erase.

7 EEIF Data EEPROM interrupt flag. Set when a read or write finishes, reset by software.

Byte Mode: In this mode data can be read and written to one byte at a time. Data is in the

DEEDAT register and the address is in the DEEADR register. Each write requires approximately 4 ms to complete. Each read requires three machines after writing the address to the DEEADR register.

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Row Fill: In this mode the addressed row (64 bytes, with address DEEADR[5:0] ignored) is filled with the DEEDAT pattern. To erase the entire row to 00h or program the entire row to FFh, write 00h or FFh to DEEDAT prior to row fill. Each row fill requires approximately

4 ms to complete.

Block Fill: In this mode all 512 bytes are filled with the DEEDAT pattern. To erase the block to 00h or program the block to FFh, write 00h or FFh to DEEDAT prior to the block fill.

Prior to using this command EADR8 must be set = 1. Each Block Fill requires approximately 4 ms to complete.

In any mode, after the operation finishes, the hardware will set EEIF bit. An interrupt can be enabled via the IEN1.7 bit. If IEN1.7 and the EA bits are set, it will generate an interrupt request. The EEIF bit will need to be cleared by software.

Data EEPROM program or erase will be blocked when V

DD

<2.4V (See Table 128

).

EWERR1 and EWERR0 bits are used to indicate the write error for BOD EEPROM.

EWERR0 will be Set when V

DD

< 2.4V during program or erase operation to indicate the previous operation may not be correct. EWERR1 will be Set when a program or erase is requested and V

DD

<2.4V. Both can be cleared by power on reset, watchdog reset or software write.

18.1 Data EEPROM read

A byte can be read via polling or interrupt:

1. Write to DEECON with ECTL1/ECTL0 (DEECON[5:4]) = ‘00’ and correct bit 8 address to EADR8. (Note that if the correct values are already written to DEECON, there is no need to write to this register.)

2. Without writing to the DEEDAT register, write address bits 7 to 0 to DEEADR.

3. If both the EIEE (IEN1.7) bit and the EA (IEN0.7) bit are logic 1s, wait for the Data

EEPROM interrupt then read/poll the EEIF (DEECON.7) bit until it is set to logic 1. If

EIEE or EA is logic 0, the interrupt is disabled, only polling is enabled.

4. Read the Data EEPROM data from the DEEDAT SFR.

Note that if DEEDAT is written prior to a write to DEEADR (if DEECON[5:4] = ‘00’), a Data

EEPROM write operation will commence. The user must take caution that such cases do not occur during a read. An example is if the Data EEPROM is read in an interrupt service routine with the interrupt occurring in the middle of a Data EEPROM cycle. The user should disable interrupts during a Data EEPROM write operation (see

Section 18.2

).

18.2 Data EEPROM write

A byte can be written via polling or interrupt:

1. Write to DEECON with ECTL1/ECTL0 (DEECON[5:4]) = ‘00’ and EWERR1/EWERR0

(DEECON[2:1]) =’00’ and correct bit 8 address to EADR8. (Note that if the correct values are already written to DEECON, there is no need to write to this register.)

2. Write the data to the DEEDAT register.

3. Write address bits 7 to 0 to DEEADR.

4. Poll EWERR1 flag. If EWERR1 (DEECON.2) bit is logic 1, BOD EEPROM occurred

(Vdd<2.4V) and Data EEPROM program is blocked.

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EIEE or EA is logic 0, the interrupt is disabled and only polling is enabled. When EEIF is logic 1, the operation is complete and data is written.

6. Poll EWERR0 flag. If EWERR0 (DEECON.1) bit is logic 1, it means BOD EEPROM occurred (Vdd<2.4V) during program or erase and the previous operation may not be correct.

As a write to the DEEDAT register followed by a write to the DEEADR register will automatically set off a write (if DEECON[5:4] = ‘00’), the user must take great caution in a write to the DEEDAT register. It is strongly recommended that the user disables interrupts prior to a write to the DEEDAT register and enable interrupts after all writes are over. An example is as follows:

CLR EA

MOV DEEDAT,@R0

MOV DEEADR,@R1

SETB EA

;disable interrupt

;write data pattern

;write address for the data

;wait for the interrupt orpoll the DEECON.7 (EEIF) bit

18.3 Hardware reset

During any hardware reset, including watchdog and system timer reset, the state machine that ‘remembers’ a write to the DEEDAT register will be initialized. If a write to the

DEEDAT register occurs followed by a hardware reset, a write to the DEEADR register without a prior write to the DEEDAT register will result in a read cycle.

18.4 Multiple writes to the DEEDAT register

If there are multiple writes to the DEEDAT register before a write to the DEEADR register, the last data written to the DEEDAT register will be written to the corresponding address.

18.5 Sequences of writes to DEECON and DEEDAT registers

A write to the DEEDAT register is considered a valid write (i.e, will trigger the state machine to ‘remember’ a write operation is to commence) if DEECON[5:4] = ‘00’. If these mode bits are already ‘00’ and address bit 8 is correct, there is no need to write to the

DEECON register prior to a write to the DEEDAT register.

18.6 Data EEPROM Row Fill

A row (64 bytes) can be filled with a predetermined data pattern via polling or interrupt:

1. Write to DEECON with ECTL1/ECTL0 (DEECON[5:4]) = ‘10’ and EWERR1/EWERR0

(DEECON[2:1]) =’00’ and correct bit 8 address to EADR8. (Note that if the correct values are already written to DEECON, there is no need to write to this register.)

2. Write the fill pattern to the DEEDAT register. (Note that if the correct values are already written to DEEDAT, there is no need to write to this register.)

3. Write address bits 7 to 0 to DEEADR. Note that address bits 5 to 0 are ignored.



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EIEE or EA is logic 0, the interrupt is disabled and only polling is enabled. When EEIF is logic 1, the operation is complete and row is filled with the DEEDAT pattern.


18.7 Data EEPROM Block Fill

The Data EEPROM array can be filled with a predetermined data pattern via polling or interrupt:

1. Write to DEECON with ECTL1/ECTL0 (DEECON[5:4]) = ‘11’and EWERR1/EWERR0

(DEECON[2:1]) =’00’. Set bit EADR8 = 1.

2. Write the fill pattern to the DEEDAT register.

3. Write any address to DEEADR. Note that the entire address is ignored in a block fill operation.





EIEE or EA is logic 0, the interrupt is disabled and only polling is enabled. When EEIF is logic 1, the operation is complete.


19. Flash memory

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19.1 General description

The P89LPC9331/9341/9351 Flash memory provides in-circuit electrical erasure and programming. The Flash can be read and written as bytes. The Sector and Page Erase functions can erase any Flash sector (1 kB) or page (64 bytes). The Chip Erase operation will erase the entire program memory. Five Flash programming methods are available.

On-chip erase and write timing generation contribute to a user-friendly programming interface. The P89LPC9331/9341/9351 Flash reliably stores memory contents even after

100,000 erase and program cycles. The cell is designed to optimize the erase and programming mechanisms. P89LPC9331/9341/9351 uses V

DD

as the supply voltage to perform the Program/Erase algorithms. When voltage supply is lower than 2.4 V, the BOD

FLASH is tripped and flash erase/program is blocked.

19.2 Features

•

Parallel programming with industry-standard commercial programmers

•

In-Circuit serial Programming (ICP) with industry-standard commercial programmers.

•

IAP-Lite allows individual and multiple bytes of code memory to be used for data storage and programmed under control of the end application.

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•

Internal fixed boot ROM, containing low-level In-Application Programming (IAP) routines that can be called from the end application (in addition to IAP-Lite).

•

Default serial loader providing In-System Programming (ISP) via the serial port, located in upper end of user program memory.

•

Boot vector allows user provided Flash loader code to reside anywhere in the Flash memory space, providing flexibility to the user.

•

Programming and erase over the full operating voltage range

•

Read/Programming/Erase using ISP, IAP or IAP-Lite

•

Any flash program operation in 2 ms (4 ms for erase/program)

•

Programmable security for the code in the Flash for each sector

•

> 100,000 typical erase/program cycles for each byte

•

10-year minimum data retention

19.3 Flash programming and erase

The P89LPC9331/9341/9351 program memory consists 1 kB sectors. Each sector can be further divided into 64-byte pages. In addition to sector erase and page erase, a 64-byte page register is included which allows from 1 to 64 bytes of a given page to be programmed at the same time, substantially reducing overall programming time. Five methods of programming this device are available.

•

Parallel programming with industry-standard commercial programmers.

•

In-Circuit serial Programming (ICP) with industry-standard commercial programmers.

•

IAP-Lite allows individual and multiple bytes of code memory to be used for data storage and programmed under control of the end application.

•

Internal fixed boot ROM, containing low-level In-Application Programming (IAP) routines that can be called from the end application (in addition to IAP-Lite).

•

A factory-provided default serial loader, located in upper end of user program memory, providing In-System Programming (ISP) via the serial port.

•

Note: Flash erase/program will be blocked if BOD FLASH is detected (Vdd<2.4 V).

19.4 Using Flash as data storage: IAP-Lite

The Flash code memory array of this device supports IAP-Lite in addition to standard IAP functions. Any byte in a non-secured sector of the code memory array may be read using the MOVC instruction and thus is suitable for use as non-volatile data storage. IAP-Lite provides an erase-program function that makes it easy for one or more bytes within a page to be erased and programmed in a single operation without the need to erase or program any other bytes in the page. IAP-Lite is performed in the application under the control of the microcontroller’s firmware using four SFRs and an internal 64-byte ‘page register’ to facilitate erasing and programing within unsecured sectors. These SFRs are:

•

FMCON (Flash Control Register). When read, this is the status register. When written, this is a command register. Note that the status bits are cleared to logic 0s when the command is written.

•

FMADRL, FMADRH (Flash memory address low, Flash memory address high). Used to specify the byte address within the page register or specify the page within user code memory

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•

FMDATA (Flash Data Register). Accepts data to be loaded into the page register.

The page register consists of 64 bytes and an update flag for each byte. When a LOAD command is issued to FMCON the page register contents and all of the update flags will be cleared. When FMDATA is written, the value written to FMDATA will be stored in the page register at the location specified by the lower 6 bits of FMADRL. In addition, the update flag for that location will be set. FMADRL will auto-increment to the next location.

Auto-increment after writing to the last byte in the page register will ‘wrap-around’ to the first byte in the page register, but will not affect FMADRL[7:6]. Bytes loaded into the page register do not have to be continuous. Any byte location can be loaded into the page register by changing the contents of FMADRL prior to writing to FMDATA. However, each location in the page register can only be written once following each LOAD command.

Attempts to write to a page register location more than once should be avoided.

FMADRH and FMADRL[7:6] are used to select a page of code memory for the erase-program function. When the erase-program command is written to FMCON, the locations within the code memory page that correspond to updated locations in the page register, will have their contents erased and programmed with the contents of their corresponding locations in the page register. Only the bytes that were loaded into the page register will be erased and programmed in the user code array. Other bytes within the user code memory will not be affected.

Writing the erase-program command (68H) to FMCON will start the erase-program process and place the CPU in a program-idle state. The CPU will remain in this idle state until the erase-program cycle is either completed or terminated by an interrupt. When the program-idle state is exited FMCON will contain status information for the cycle.

If an interrupt occurs during an erase/programming cycle, the erase/programming cycle will be aborted and the OI flag (Operation Interrupted) in FMCON will be set. If the application permits interrupts during erasing-programming the user code should check the

OI flag (FMCON.0) after each erase-programming operation to see if the operation was aborted. If the operation was aborted, the user’s code will need to repeat the process starting with loading the page register.

The erase-program cycle takes 4 ms (2 ms for erase, 2 ms for programming) to complete, regardless of the number of bytes that were loaded into the page register.

Erasing-programming of a single byte (or multiple bytes) in code memory is accomplished using the following steps:

•

Write the LOAD command (00H) to FMCON. The LOAD command will clear all locations in the page register and their corresponding update flags.

•

Write the address within the page register to FMADRL. Since the loading the page register uses FMADRL[5:0], and since the erase-program command uses FMADRH and FMADRL[7:6], the user can write the byte location within the page register

(FMADRL[5:0]) and the code memory page address (FMADRH and FMADRL[7:6]) at this time.

•

Write the data to be programmed to FMDATA. This will increment FMADRL pointing to the next byte in the page register.

•

Write the address of the next byte to be programmed to FMADRL, if desired. (Not needed for contiguous bytes since FMADRL is auto-incremented). All bytes to be programmed must be within the same page.

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•

Write the data for the next byte to be programmed to FMDATA.

•

Repeat writing of FMADRL and/or FMDATA until all desired bytes have been loaded into the page register.

•

Write the page address in user code memory to FMADRH and FMADRL[7:6], if not previously included when writing the page register address to FMADRL[5:0].

•

Write the erase-program command (68H) to FMCON, starting the erase-program cycle.

•

Read FMCON to check status. If aborted, repeat starting with the LOAD command.

Table 129. Flash Memory Control register (FMCON - address E4h) bit allocation

Bit 7 6 5 4 3 2 1 0

Symbol (R) HVA HVE SV OI

Symbol (W) FMCMD.7

FMCMD.6

FMCMD.5

FMCMD.4

FMCMD.3

FMCMD.2

FMCMD.1

FMCMD.0

Reset 0 0 0 0 0 0 0 0

Table 130. Flash Memory Control register (FMCON - address E4h) bit description

Bit Symbol

0 OI

Access

R

Description

Operation interrupted. Set when cycle aborted due to an interrupt or reset.

1

FMCMD.0

W

SV R

Command byte bit 0.

Security violation. Set when an attempt is made to program, erase, or CRC a secured sector or page.

Command byte bit 1

2

3

FMCMD.1

W

HVE R

FMCMD.2

W

HVA R

High voltage error. Set when an error occurs in the high voltage generator.

Command byte bit 2.

High voltage abort. Set if either an interrupt or BOD FLASH is detected during a program or erase cycle.

6

7

4

5

4:7 -

FMCMD.3

W

R

FMCMD.4

FMCMD.5

W

W

FMCMD.6

W

FMCMD.7

W

Command byte bit 3.

reserved.

Command byte bit 4.

Command byte bit 5.

Command byte bit 6.

Command byte bit 7.

An assembly language routine to load the page register and perform an erase/program operation is shown below.

;**************************************************

;* pgm user code *

;**************************************************

;* *

;* Inputs:

;* R3 = number of bytes to program (byte)

;* R4 = page address MSB(byte)

;* R5 = page address LSB(byte)

*

*

*

*

;* R7 = pointer to data buffer in RAM(byte)

;* Outputs:

;* R7 = status (byte)

*

*

*

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;* C = clear on no error, set on error

;**************************************************

*

LOAD

EP

EQU

EQU

00H

68H

PGM_USER:

MOV

MOV

MOV

MOV

LOAD_PAGE:

MOV

A,R7

MOV

INC

DJNZ

MOV

FMCON,#LOAD

FMADRH,R4

FMADRL,R5

;

R0,A

;load command, clears page register

;get high address

;get low address

;get pointer into R0

FMDAT,@R0

R0

;write data to page register

;point to next byte

R3,LOAD_PAGE ;do until count is zero

FMCON,#EP ;else erase & program the page

MOV

MOV

ANL

JNZ

CLR

RET

R7,FMCON

A,R7

A,#0FH

BAD

C

;copy status for return

;read status

;save only four lower bits

;

;clear error flag if good

;and return

BAD:

SETB

RET

C ;set error flag

;and return

A C-language routine to load the page register and perform an erase/program operation is shown below.

#include <REG9351.H> unsigned char idata dbytes[64]; // data buffer unsigned char Fm_stat; // status result bit PGM_USER (unsigned char, unsigned char); bit prog_fail; void main ()

{ prog_fail=PGM_USER(0x1F,0xC0);

} bit PGM_USER (unsigned char page_hi, unsigned char page_lo)

{

#define LOAD 0x00 // clear page register, enable loading

#define EP 0x68 // erase & program page unsigned char i; // loop count

FMCON = LOAD; //load command, clears page reg

FMADRH = page_hi; //

FMADRL = page_lo; //write my page address to addr regs for (i=0;i<64;i=i+1)

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{

FMDATA = dbytes[i];

}

FMCON = EP; //erase & prog page command

Fm_stat = FMCON; //read the result status if ((Fm_stat & 0x0F)!=0) prog_fail=1; else prog_fail=0; return(prog_fail);

}

19.5 In-circuit programming (ICP)

In-Circuit Programming is a method intended to allow commercial programmers to program and erase these devices without removing the microcontroller from the system.

The In-Circuit Programming facility consists of a series of internal hardware resources to facilitate remote programming of the P89LPC9331/9341/9351 through a two-wire serial interface. NXP has made in-circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area. The ICP function uses five pins (V

DD

, V

SS

, P0.5, P0.4, and RST). Only a small connector needs to be available to interface your application to an external programmer in order to use this feature.

19.6 ISP and IAP capabilities of the P89LPC9331/9341/9351

An In-Application Programming (IAP) interface is provided to allow the end user’s application to erase and reprogram the user code memory. In addition, erasing and reprogramming of user-programmable bytes including UCFG1, UCFG2, the Boot Status

Bit, and the Boot Vector is supported. As shipped from the factory, the upper 512 bytes of user code space contains a serial In-System Programming (ISP) loader allowing for the device to be programmed in circuit through the serial port. This ISP boot loader will, in turn, call low-level routines through the same common entry point that can be used by the end-user application.

19.7 Boot ROM

When the microcontroller contains a a 256 byte Boot ROM that is separate from the user’s

Flash program memory. This Boot ROM contains routines which handle all of the low level details needed to erase and program the user Flash memory. A user program simply calls a common entry point in the Boot ROM with appropriate parameters to accomplish the desired operation. Boot ROM operations include operations such as erase sector, erase page, program page, CRC, program security bit, etc. The Boot ROM occupies the program memory space at the top of the address space from FF00 to FFFFh, thereby not conflicting with the user program memory space. This function is in addition to the IAP-Lite feature.

19.8 Power on reset code execution

The P89LPC9331/9341/9351 contains two special Flash elements: the BOOT VECTOR and the Boot Status Bit. Following reset, the P89LPC9331/9341/9351 examines the contents of the Boot Status Bit. If the Boot Status Bit is set to zero, power-up execution starts at location 0000H, which is the normal start address of the user’s application code.

When the Boot Status Bit is set to one, the contents of the Boot Vector is used as the high byte of the execution address and the low byte is set to 00H.

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The factory default settings for this device is shown in

Table 131 , below.

The factory pre-programmed boot loader can be erased by the user. Users who wish to use this loader should take cautions to avoid erasing the last 1 kB sector on the device.

Instead, the page erase function can be used to erase the eight 64-byte pages located in this sector. A custom boot loader can be written with the Boot Vector set to the custom boot loader, if desired.

Table 131. Boot loader address and default Boot vector

Product Flash size End address

Signature bytes

P89LPC9331

Mfg id Id 1

15h DDh

Id 2

37h

P89LPC9341

P89LPC9351

4 kB

× 8

0FFFh

8 kB

× 8

1FFFh

8 kB

× 8

1FFFh

15h

15h

DDh

DDh

38h

2Eh

Sector size

Page size

Pre-programmed serial loader

1 kB

× 8

64

× 8

0E00h to 0FFFh

1 kB

× 8

64

× 8

1E00h to 1FFFh

1 kB

× 8

64

× 8

1E00h to 1FFFh

Default Boot vector

0Fh

1Fh

1Fh

19.9 Hardware activation of Boot Loader

The boot loader can also be executed by forcing the device into ISP mode during a power-on sequence (see

Figure 56 ). This is accomplished by powering up the device with

the reset pin initially held low and holding the pin low for a fixed time after V

DD

rises to its normal operating value. This is followed by three, and only three, properly timed low-going pulses. Fewer or more than three pulses will result in the device not entering ISP mode.

Timing specifications may be found in the data sheet for this device.

This has the same effect as having a non-zero status bit. This allows an application to be built that will normally execute the user code but can be manually forced into ISP operation. If the factory default setting for the Boot Vector is changed, it will no longer point to the factory pre-programmed ISP boot loader code. If this happens, the only way it is possible to change the contents of the Boot Vector is through the parallel or ICP programming method, provided that the end user application does not contain a customized loader that provides for erasing and reprogramming of the Boot Vector and

Boot Status Bit. After programming the Flash, the status byte should be programmed to zero in order to allow execution of the user’s application code beginning at address

0000H.

V

DD t

VR t

RH

RST t

RL

002aaa912

Fig 56. Forcing ISP mode

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19.10 In-system programming (ISP)

In-System Programming is performed without removing the microcontroller from the system. The In-System Programming facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the

P89LPC9331/9341/9351 through the serial port. This firmware is provided by NXP and embedded within each P89LPC9331/9341/9351 device. The NXP In-System

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Programming facility has made in-circuit programming in an embedded application possible with a minimum of additional expense in components and circuit board area. The

ISP function uses five pins (V

DD

, V

SS

, TXD0, RXD0, and RST). Only a small connector needs to be available to interface your application to an external circuit in order to use this feature.

19.11 Using the In-system programming (ISP)

The ISP feature allows for a wide range of baud rates to be used in your application, independent of the oscillator frequency. It is also adaptable to a wide range of oscillator frequencies. This is accomplished by measuring the bit-time of a single bit in a received character. This information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. The ISP feature requires that an initial character (an uppercase U) be sent to the P89LPC9331/9341/9351 to establish the baud rate. The ISP firmware provides auto-echo of received characters. Once baud rate initialization has been performed, the ISP firmware will only accept Intel Hex-type records. Intel Hex records consist of ASCII characters used to represent hexadecimal values and are summarized below:

:NNAAAARRDD..DDCC<crlf>

In the Intel Hex record, the ‘NN’ represents the number of data bytes in the record. The

P89LPC9331/9341/9351 will accept up to 64 (40H) data bytes. The ‘AAAA’ string represents the address of the first byte in the record. If there are zero bytes in the record, this field is often set to 0000. The ‘RR’ string indicates the record type. A record type of

‘00’ is a data record. A record type of ‘01’ indicates the end-of-file mark. In this application, additional record types will be added to indicate either commands or data for the ISP facility. The maximum number of data bytes in a record is limited to 64 (decimal). ISP commands are summarized in

Table 132 . As a record is received by the

P89LPC9331/9341/9351, the information in the record is stored internally and a checksum calculation is performed. The operation indicated by the record type is not performed until the entire record has been received. Should an error occur in the checksum, the P89LPC9331/9341/9351 will send an ‘X’ out the serial port indicating a checksum error. If the checksum calculation is found to match the checksum in the record, then the command will be executed. In most cases, successful reception of the record will be indicated by transmitting a ‘.’ character out the serial port.

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Table 132. In-system Programming (ISP) hex record formats

Record type

00

01

Command/data function

Program User Code Memory Page

: nnaaaa00dd..ddcc

Where: nn = number of bytes to program; aaaa = page address; dd..dd= data bytes; cc = checksum;

Example:100000000102030405006070809DC3

Read Version Id

: 00xxxx01cc

Where: xxxx = required field but value is a ‘don’t care’; cc = checksum

Example: 00000001FF

02 Miscellaneous Write Functions

:02xxxx02ssddcc

Where: xxxx = required field but value is a ‘don’t care’; ss= subfunction code; dd= data; cc= checksum

Subfunction codes:

00= UCFG1

01= UCFG2

02= Boot Vector

03= Status Byte

04= reserved

05= reserved

06= reserved

07= reserved

08= Security Byte 0

09= Security Byte 1

0A= Security Byte 2

0B= Security Byte 3

0C= Security Byte 4

0D= Security Byte 5

0E= Security Byte 6

0F= Security Byte 7

10= Clear Configuration Protection

Example::020000020347B2

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…continued

Record type

03


Miscellaneous Read Functions

: 01xxxx03sscc

Where xxxx = required field but value is a ‘don’t care’; ss= subfunction code; cc = checksum

Subfunction codes:

00= UCFG1

01= UCFG2

02= Boot Vector

03= Status Byte

04= reserved

05= reserved

06= reserved

07= reserved

08= Security Byte 0

09= Security Byte 1

0A= Security Byte 2

0B= Security Byte 3

0C= Security Byte 4

0D= Security Byte 5

0E= Security Byte 6

0F= Security Byte 7

10= Manufacturer Id

11= Device Id

12= Derivative Id

04

05

Example: 0100000312EA

Erase Sector/Page

: 03xxxx04ssaaaacc

Where: xxxx = required field but value is a ‘don’t care’; aaaa = sector/page address; ss= 01 erase sector; ss = 00 erase page; cc = checksum

Example :03000004010000F8

Read Sector CRC

: 01xxxx05aacc

Where: xxxx = required field but value is a ‘don’t care’; aa= sector address high byte; cc= checksum

Example: 0100000504F6

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…continued

Record type

06


Read Global CRC

: 00xxxx06cc

Where: xxxx = required field but value is a ‘don’t care’; cc= checksum

Example: 00000006FA

07

08

Direct Load of Baud Rate

: 02xxxx07HHLLcc

Where: xxxx = required field but value is a ‘don’t care’; HH= high byte of timer;

LL = low byte of timer; cc = checksum

Example: 02000007FFFFF9

Reset MCU

: 00xxxx08cc

Where: xxxx = required field but value is a ‘don’t care’; cc = checksum

Example: 00000008F8

19.12 In-application programming (IAP)

Several In-Application Programming (IAP) calls are available for use by an application program to permit selective erasing and programming of Flash sectors, pages, security bits, configuration bytes, and device id. All calls are made through a common interface,

PGM_MTP. The programming functions are selected by setting up the microcontroller’s registers before making a call to PGM_MTP at FF03H. The IAP calls are shown in

Table 134 .

19.13 IAP authorization key

IAP functions which write or erase code memory require an authorization key be set by the calling routine prior to performing the IAP function call. This authorization key is set by writing 96H to RAM location FFH. The following example was written using the Keil C compiler. The methods used to access a specific physical address in memory may vary with other compilers.

#include <ABSACC.H> /* enable absolute memory access */

#define key DBYTE[0xFF] /* force key to be at address 0xFF */

short (*pgm_mtp) (void) = 0xFF00; /* set pointer to IAP entry point */; key = 0x96; /* set the authorization key */ pgm_mtp (); /* execute the IAP function call */

After the function call is processed by the IAP routine, the authorization key will be cleared. Thus it is necessary for the authorization key to be set prior to EACH call to

PGM_MTP that requires a key. If an IAP routine that requires an authorization key is called without a valid authorization key present, the MCU will perform a reset.

19.14 Flash write enable

This device has hardware write enable protection. This protection applies to both ISP and

IAP modes and applies to both the user code memory space and the user configuration bytes (UCFG1, UCFG2, BOOTVEC, and BOOTSTAT). This protection does not apply to

ICP or parallel programmer modes. If the Activate Write Enable (AWE) bit in BOOTSTAT.7

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is a logic 0, an internal Write Enable (WE) flag is forced set and writes to the flash memory and configuration bytes are enabled. If the Active Write Enable (AWE) bit is a logic 1, then the state of the internal WE flag can be controlled by the user.

The WE flag is SET by writing the Set Write Enable (08H) command to FMCON followed by a key value (96H) to FMDATA:

FMCON = 0x08;

FMDATA = 0x96;

The WE flag is CLEARED by writing the Clear Write Enable (0BH) command to FMCON followed by a key value (96H) to FMDATA, or by a reset:

FMCON = 0x0B;

FMDATA = 0x96;

The ISP function in this device sets the WE flag prior to calling the IAP routines. The IAP function in this device executes a Clear Write Enable command following any write operation. If the Write Enable function is active, user code which calls IAP routines will need to set the Write Enable flag prior to each IAP write function call.

19.15 Configuration byte protection

In addition to the hardware write enable protection, described above, the ‘configuration bytes’ may be separately write protected. These configuration bytes include UCFG1,

UCFG2, BOOTVEC, and BOOTSTAT. This protection applies to both ISP and IAP modes and does not apply to ICP or parallel programmer modes.

If the Configuration Write Protect bit (CWP) in BOOTSTAT.6 is a logic 1, writes to the configuration bytes are disabled. If the Configuration Write Protect bit (CWP) is a logic 0, writes to the configuration bytes are enabled. The CWP bit is set by programming the

BOOTSTAT register. This bit is cleared by using the Clear Configuration Protection (CCP) command in IAP or ISP.

The Clear Configuration Protection command can be disabled in ISP or IAP mode by programming the Disable Clear Configuration Protection bit (DCCP) in BOOTSTAT.7 to a logic 1. When DCCP is set, the CCP command may still be used in ICP or parallel programming modes. This bit is cleared by writing the Clear Configuration Protection

(CCP) command in either ICP or parallel programming modes.

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19.16 IAP error status

It is not possible to use the Flash memory as the source of program instructions while programming or erasing this same Flash memory. During an IAP erase, program, or CRC the CPU enters a program-idle state. The CPU will remain in this program-idle state until the erase, program, or CRC cycle is completed. These cycles are self timed. When the cycle is completed, code execution resumes. If an interrupt occurs during an erase, programming or CRC cycle, the erase, programming, or CRC cycle will be aborted so that the Flash memory can be used as the source of instructions to service the interrupt. An

IAP error condition will be flagged by setting the carry flag and status information returned.

The status information returned is shown in Table 133

. If the application permits interrupts during erasing, programming, or CRC cycles, the user code should check the carry flag after each erase, programming, or CRC operation to see if an error occurred. If the operation was aborted, the user’s code will need to repeat the operation.

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Table 133. IAP error status

Bit

0

Flag

OI

Description

Operation Interrupted. Indicates that an operation was aborted due to an interrupt occurring during a program or erase cycle.

1

2

3

4 to 7 -

SV

HVE High Voltage Error. Set if error detected in high voltage generation circuits. Cycle is aborted. Memory contents may be corrupted.

VE

Security Violation. Set if program or erase operation fails due to security settings. Cycle is aborted. Memory contents are unchanged. CRC output is invalid.

Verify error. Set during IAP programming of user code if the contents of the programmed address does not agree with the intended programmed value. IAP uses the MOVC instruction to perform this verify. Attempts to program user code that is MOVC protected can be programmed but will generate this error after the programming cycle has been completed.

unused; reads as a logic 0

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Table 134. IAP function calls

IAP function IAP call parameters

Program User Code Page

(requires ‘key’)

Input parameters:

ACC = 00h

R3= number of bytes to program

R4= page address (MSB)

R5= page address (LSB)

R7= pointer to data buffer in RAM

F1= 0h = use IDATA

Return parameter(s):

R7= status

Carry= set on error, clear on no error

Read Version Id Input parameters:

ACC = 01h


R7=IAP version id

Misc. Write (requires ‘key’) Input parameters:

ACC = 02h

R5= data to write

R7= register address

00= UCFG1

01= UCFG2

02= Boot Vector

03= Status Byte

04 to 07 = reserved

08= Security Byte 0

09= Security Byte 1

0A= Security Byte 2

0B= Security Byte 3

0C= Security Byte 4

0D= Security Byte 5

0E= Security Byte 6

0F= Security Byte 7

10 = Clear Configuration Protection


R7= status


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…continued

IAP function

Misc. Read

IAP call parameters

Input parameters:

ACC = 03h

R7= register address

00= UCFG1

01= UCFG2

02= Boot Vector

03= Status Byte

04 to 07 = reserved

08= Security Byte 0

09= Security Byte 1

0A= Security Byte 2

0B= Security Byte 3

0C= Security Byte 4

0D= Security Byte 5

0E= Security Byte 6

0F= Security Byte 7


R7= register data if no error, else error status


Erase Sector/Page

(requires ‘key’)

Input parameters:

ACC = 04h

R4= address (MSB)

R5= address (LSB)

R7= 00H (erase page) or 01H (erase sector)


R7= data


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IAP function

Read Sector CRC

IAP call parameters

Input parameters:

ACC = 05h

R7= sector address


R4= CRC bits 31:24

R5= CRC bits 23:16

R6= CRC bits 15:8

R7= CRC bits 7:0 (if no error)

R7= error status (if error)


Read Global CRC

Read User Code

Input parameters:

ACC = 06h


R4= CRC bits 31:24

R5= CRC bits 23:16

R6= CRC bits 15:8

R7= CRC bits 7:0 (if no error)

R7= error status (if error)


Input parameters:

ACC = 07h

R4= address (MSB)

R5= address (LSB)


R7= data

19.17 User configuration bytes

A number of user-configurable features of the P89LPC9331/9341/9351 must be defined at power-up and therefore cannot be set by the program after start of execution. These features are configured through the use of an Flash byte UCFG1 and UCFG2 shown in

Table 136 and

Table 139

.

Table 135. Flash User Configuration Byte 1 (UCFG1) bit allocation

Bit

Symbol

Unprogrammed value

7

WDTE

0

6

RPE

1

5

BOE1

1

4

WDSE

0

3

BOE0

0

2

FOSC2

0

1

FOSC1

1

0

FOSC0

1

Table 136. Flash User Configuration Byte 1 (UCFG1) bit description


0 FOSC0

CPU oscillator type select. See Section 2 “Clocks”

for additional information. Combinations other than those

1 FOSC1 shown in

Table 137

are reserved for future use and should not be used.

2 FOSC2

3 BOE0

Brownout Detect Configuration (see Section 6.1 “Brownout detection” )

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4 WDSE

Watchdog Safety Enable bit. Refer to Table 120 “Watchdog timer configuration” for details.

5 BOE1

6 RPE

Brownout Detect Configuration (see Section 6.1 “Brownout detection” )

Reset pin enable. When set = 1, enables the reset function of pin P1.5. When cleared, P1.5 may be used as an input pin. NOTE: During a power-up sequence, the RPE selection is overridden and this pin will always functions as a reset input. After power-up the pin will function as defined by the RPE bit. Only a power-up reset will temporarily override the selection defined by RPE bit. Other sources of reset will not override the

RPE bit.

7 WDTE Watchdog timer reset enable. When set = 1, enables the watchdog timer reset. When cleared = 0, disables

the watchdog timer reset. The timer may still be used to generate an interrupt. Refer to Table 120 “Watchdog timer configuration”

for details.

Table 137. Oscillator type selection

FOSC[2:0] Oscillator configuration

111 External clock input on XTAL1.

100

011

010

001

000

Watchdog Oscillator, 400 kHz ± 5 %.

Internal RC oscillator, 7.373 MHz ± 1 %.

Low frequency crystal, 20 kHz to 100 kHz.

Medium frequency crystal or resonator, 100 kHz to 4 MHz.

High frequency crystal or resonator, 4 MHz to 18 MHz.

Table 138. Flash User Configuration Byte 2 (UCFG2) bit allocation

Bit

Symbol

Unprogrammed value

7

CLKDBL

0

-

6

x

-

5

x

-

4

x

-

3

x

-

2

x



0:6 Not used.

7 CLKDBL Clock doubler. When set, doubles the output frequency of the internal RC oscillator.

-

1

x

-

0

x

19.18 User security bytes

This device has three security bits associated with each of its eight sectors, as shown in

Table 140

Table 140. Sector Security Bytes (SECx) bit allocation

Bit 7 6 5 4

Symbol

Unprogrammed value

-

0

-

0

-

0

-

0

3

-

0

2

EDISx

0

1 0

SPEDISx MOVCDISx

0 0

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Table 141. Sector Security Bytes (SECx) bit description


0 MOVCDISx MOVC Disable. Disables the MOVC command for sector x. Any MOVC that attempts to read a byte in a

MOVC protected sector will return invalid data. This bit can only be erased when sector x is erased.

1 SPEDISx Sector Program Erase Disable x. Disables program or erase of all or part of sector x. This bit and sector x are erased by either a sector erase command (ISP, IAP, commercial programmer) or a 'global' erase command (commercial programmer).

2 EDISx

3:7 -

Erase Disable ISP. Disables the ability to perform an erase of sector x in ISP or IAP mode. When programmed, this bit and sector x can only be erased by a 'global' erase command using a commercial programmer. This bit and sector x CANNOT be erased in ISP or IAP modes. reserved

Table 142. Effects of Security Bits

EDISx SPEDISx MOVCDISx Effects on Programming

0

0

0

0

0

1

0

1 x

None.

Security violation flag set for sector CRC calculation for the specific sector.

Security violation flag set for global CRC calculation if any MOVCDISx bit is set.

Cycle aborted. Memory contents unchanged. CRC invalid. Program/erase commands will not result in a security violation.

Security violation flag set for program commands or an erase page command.

Cycle aborted. Memory contents unchanged. Sector erase and global erase are allowed.

1 x x Security violation flag set for program commands or an erase page command.

Cycle aborted. Memory contents unchanged. Global erase is allowed.

19.19 Boot Vector register

Table 143. Boot Vector (BOOTVEC) bit allocation

Bit 7 6 5

Symbol

Factory default value

-

0

-

0

-

0

4 3 2 1 0

BOOTV4 BOOTV3 BOOTV2 BOOTV1 BOOTV0

1 1 1 1 1

Table 144. Boot Vector (BOOTVEC) bit description


0:4 BOOTV[0:4] Boot vector. If the Boot Vector is selected as the reset address, the P89LPC9331/9341/9351 will start execution at an address comprised of 00h in the lower eight bits and this BOOTVEC as the upper eight bits after a reset.

5:7 reserved

19.20 Boot status register

Table 145. Boot Status (BOOTSTAT) bit allocation

Bit

Symbol

Factory default value

7

DCCP

0

6

CWP

0

5

AWP

0

-

4

0

-

3

0

-

2

0

-

1

0

0

BSB

1

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Table 146. Boot Status (BOOTSTAT) bit description

Bit Symbol

0 BSB

Description

Boot Status Bit. If programmed to logic 1, the P89LPC9331/9341/9351 will always start execution at an address comprised of 00H in the lower eight bits and BOOTVEC as the upper bits after a reset. (See

Section 7.1 “Reset vector” ).

1:4 -

5 AWP

6

7

CWP

DCCP reserved

Activate Write Protection bit. When this bit is cleared, the internal Write Enable flag is forced to the set state, thus writes to the flash memory are always enabled. When this bit is set, the Write Enable internal flag can be set or cleared using the Set Write Enable (SWE) or Clear Write Enable (CWE) commands.

Configuration Write Protect bit. Protects inadvertent writes to the user programmable configuration bytes (UCFG1, BOOTVEC, and BOOTSTAT). If programmed to a logic 1, the writes to these registers are disabled. If programmed to a logic 0, writes to these registers are enabled.

This bit is set by programming the BOOTSTAT register. This bit is cleared by writing the Clear

Configuration Protection (CCP) command to FMCON followed by writing 96H to FMDATA.

Disable Clear Configuration Protection command. If Programmed to ‘1’, the Clear Configuration

Protection (CCP) command is disabled during ISP or IAP modes. This command can still be used in

ICP or parallel programmer modes. If programmed to ‘0’, the CCP command can be used in all programming modes. This bit is set by programming the BOOTSTAT register. This bit is cleared by writing the Clear Configuration Protection (CCP) command in either ICP or parallel programmer modes.

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20. Instruction set

Table 147. Instruction set summary

Mnemonic

ADD A,Rn

ADD A,dir

ADD A,@Ri

ADD A,#data

ADDC A,Rn

ADDC A,dir

ADDC A,@Ri

ADDC A,#data

SUBB A,Rn

SUBB A,dir

SUBB A,@Ri

SUBB A,#data

INC A

INC Rn

INC dir

INC @Ri

DEC A

DEC Rn

DEC dir

DEC @Ri

INC DPTR

MUL AB

DIV AB

DA A

ANL A,Rn

ANL A,dir

ANL A,@Ri

ANL A,#data

ANL dir,A

ANL dir,#data

ORL A,Rn

ORL A,dir

ORL A,@Ri

ORL A,#data

ORL dir,A

ORL dir,#data

Description

ARITHMETIC

Add register to A

Add direct byte to A

Add indirect memory to A

Add immediate to A

Add register to A with carry

Add direct byte to A with carry

Add indirect memory to A with carry

Add immediate to A with carry

Subtract register from A with borrow

Subtract direct byte from A with borrow

Subtract indirect memory from A with borrow

Subtract immediate from A with borrow

Increment A

Increment register

Increment direct byte

Increment indirect memory

Decrement A

Decrement register

Decrement direct byte

Decrement indirect memory

Increment data pointer

Multiply A by B

Divide A by B

Decimal Adjust A

LOGICAL

AND register to A

AND direct byte to A

AND indirect memory to A

AND immediate to A

AND A to direct byte

AND immediate to direct byte

OR register to A

OR direct byte to A

OR indirect memory to A

OR immediate to A

OR A to direct byte

OR immediate to direct byte

UM10308_2


Bytes

3

1

2

2

1

2

1

2

2

2

1

3

1

1

2

1

1

1

1

1

2

1

2

1

1

2

1

2

1

1

2

1

2

1

2

1

Cycles

2

4

1

1

4

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Hex code

2

1

1

1

1

1

1

1

1

1

1

2

58 to 5F

55

56 to 57

54

52

53

48 to 4F

45

46 to 47

44

42

43


153 of 162

94

04

08 to 0F

05

06 to 07

14

18 to 1F

15

16 to 17

A3

A4

84

D4

28 to 2F

25

26 to 27

24

38 to 3F

35

36 to 37

34

98 to 9F

95

96 to 97


UM10308

P89LPC9331/9341/9351 User manual


…continued

Mnemonic

XRL A,Rn

Description

Exclusive-OR register to A

XRL A,dir

XRL A, @Ri

XRL A,#data

XRL dir,A

XRL dir,#data

CLR A

CPL A

SWAP A

RL A

RLC A

Rotate A right

RRC A

MOV A,Rn

MOV A,dir

Move indirect memory to A

MOV A,#data

MOV Rn,A

MOV Rn,dir

MOV Rn,#data

MOV dir,A

MOV dir,Rn

MOV dir,dir

MOV dir,@Ri

MOV dir,#data

MOV @Ri,A

MOV @Ri,dir

MOV @Ri,#data

MOV DPTR,#data

MOVC A,@A+DPTR

MOVC A,@A+PC

MOVX A,@Ri

MOVX A,@DPTR

MOVX @Ri,A

MOVX @DPTR,A

PUSH dir

POP dir

XCH A,Rn

XCH A,dir

XCH A,@Ri

Exclusive-OR direct byte to A

Exclusive-OR indirect memory to A

Exclusive-OR immediate to A

Exclusive-OR A to direct byte

Exclusive-OR immediate to direct byte

Clear A

Complement A

Swap Nibbles of A

Rotate A left

Rotate A left through carry

RR A

Rotate A right through carry

DATA TRANSFER

Move register to A

Move direct byte to A

MOV A,@Ri

Move immediate to A

Move A to register

Move direct byte to register

Move immediate to register

Move A to direct byte

Move register to direct byte

Move direct byte to direct byte

Move indirect memory to direct byte

Move immediate to direct byte

Move A to indirect memory

Move direct byte to indirect memory

Move immediate to indirect memory

Move immediate to data pointer

Move code byte relative DPTR to A

Move code byte relative PC to A

Move external data(A8) to A

Move external data(A16) to A

Move A to external data(A8)

Move A to external data(A16)

Push direct byte onto stack

Pop direct byte from stack

Exchange A and register

Exchange A and direct byte

Exchange A and indirect memory

UM10308_2


1

1

1

1

1

1

3

1

2

2

2

1

Bytes

1

1

2

1

1

1

1

3

1

2

1

2

1

2

2

3

1

3

2

2

2

2

2

2

1

1

2

1

1

1

1

1

1

1

2

1

1

1

1

1

Cycles

1

90

93

94

E2 to E3

E0

F2 to F3

F0

C0

D0

C8 to CF

C5

C6 to C7

E8 to EF

E5

E6 to E7

74

F8 to FF

A8 to AF

78 to 7F

F5

88 to 8F

85

86 to 87

75

F6 to F7

A6 to A7

76 to 77


154 of 162

2

2

2

2

2

2

2

2

1

1

2

1

2

1

2

1

2

2

1

2

2

1

1

1

1

1

1

23

33

03

13

63

E4

F4

C4

Hex code

68 to 6F

65

66 to 67

64

62


UM10308

P89LPC9331/9341/9351 User manual


…continued

Mnemonic

XCHD A,@Ri

Description Bytes

Exchange A and indirect memory nibble 1

Mnemonic

CLR C

CLR bit

SETB C

SETB bit

CPL C

CPL bit

BOOLEAN

Description

Clear carry

Clear direct bit

Set carry

Set direct bit

Complement carry

Complement direct bit

1

2

1

2

Bytes

1

2

ANL C,bit

ANL C,/bit

ORL C,bit

ORL C,/bit

MOV C,bit

MOV bit,C

ACALL addr 11

LCALL addr 16

RET

RETI

AJMP addr 11

LJMP addr 16

SJMP rel

JC rel

JNC rel

JB bit,rel

JNB bit,rel

JBC bit,rel

JMP @A+DPTR

JZ rel

JNZ rel

CJNE A,dir,rel

CJNE A,#d,rel

CJNE Rn,#d,rel

CJNE @Ri,#d,rel

DJNZ Rn,rel

DJNZ dir,rel

NOP

AND direct bit to carry

AND direct bit inverse to carry

OR direct bit to carry

OR direct bit inverse to carry

Move direct bit to carry

Move carry to direct bit

BRANCHING

Absolute jump to subroutine

Long jump to subroutine

Return from subroutine

Return from interrupt

Absolute jump unconditional

Long jump unconditional

Short jump (relative address)

Jump on carry = 1

Jump on carry = 0

Jump on direct bit = 1

Jump on direct bit = 0

Jump on direct bit = 1 and clear

Jump indirect relative DPTR

Jump on accumulator = 0

Jump on accumulator

≠ 0

Compare A, direct jne relative

Compare A, immediate jne relative

Compare register, immediate jne relative 3

Compare indirect, immediate jne relative 3

3

3

2

2

3

1

3

3

2

2

3

2

1

2

2

3

1

2

2

Decrement register, jnz relative

Decrement direct byte, jnz relative

MISCELLANEOUS

No operation

2

3

2

2

2

2

1

10

73

60

70

40

50

20

30

116F1

12

22

32

016E1

02

80

B5

B4

B8 to BF

B6 to B7

D8 to DF

D5

00

Hex code

D6 to D7

82

B0

72

A0

A2

92

D3

D2

B3

B2

Hex code

C3

C2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

2

1

Cycles

1

2

2

2

2

1

2

1

1

1

1

Cycles

1

1

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21. Legal information

21.1

Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.

21.2

Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.

Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.

21.3

Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.

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22. Tables

Table 1.

Product comparison overview. . . . . . . . . . . . . . .3

Table 2.

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5

Table 3.

Special function registers (P89LPC9331/9341) 11

Table 4.

Extended special function registers

(P89LPC9331/9341) . . . . . . . . . . . . . . . . . . . .18

Table 5.

Special function registers (P89LPC9351) . . . .19

Table 6.

Extended special function registers

(P89LPC9351) . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 7.

Data RAM arrangement . . . . . . . . . . . . . . . . . .29

Table 8.

On-chip RC oscillator trim register (TRIM - address 96h) bit allocation . . . . . . . . . . . . . . . .30

Table 9.

On-chip RC oscillator trim register (TRIM - address 96h) bit description . . . . . . . . . . . . . .31

Table 10. Clock control register (CLKCON - address

FFDEh) bit allocation . . . . . . . . . . . . . . . . . . . .32

Table 11. Clock control register (CLKCON - address

FFDEh) bit description . . . . . . . . . . . . . . . . . . .32

Table 12. Oscillator type selection for clock switch . . . . .33

Table 13. PGA trim register . . . . . . . . . . . . . . . . . . . . . .38

Table 14. PGA channel selection . . . . . . . . . . . . . . . . . . .38

Table 15. Input channels and result registers for fixed channel single, auto scan single and auto scan continuous conversion mode . . . . . . . . . . . . . .39

Table 16. Result registers and conversion results for fixed channel, continuous conversion mode . . . . . .40

Table 17. Result registers and conversion results for dual channel, continuous conversion mode . . . . . .40

Table 18. Conversion mode bits . . . . . . . . . . . . . . . . . . .41

Table 19. A/D Control register 0 (ADCON0 - address 8Eh) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 20. A/D Control register 0 (ADCON0 - address 97h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .43

Table 21. A/D Control register 1(ADCON1 - address 97h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 22. A/D Control register 1(ADCON1 - address 97h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 23. A/D Mode register A (ADMODA - address 0C0h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 24. A/D Mode register A (ADMODA - address 0C0h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 25. A/D Mode register B (ADMODB - address A1h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 26. A/D Mode register B (ADMODB - address A1h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 27. A/D Input select (ADINS - address A3h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 28. A/D Input select (ADINS - address A3h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Table 29. Temperature Sensor control register (TPSCON - address FFCAh) bit allocation

(P89LPC9331/9341) . . . . . . . . . . . . . . . . . . . .46

Table 30. Temperature Sensor control register (TPSCON - address FFCAh) bit description

(P89LPC9331/9341) . . . . . . . . . . . . . . . . . . . . .46

Table 31. PGA0 Control register (PGACON0 - address

FFCAh) bit allocation (P89LPC9351) . . . . . . . .46

UM10308_2



FFCAh) bit description (P89LPC9351) . . . . . . 46


FFE1h) bit allocation (P89LPC9351) . . . . . . . 47


FFE1h) bit description (P89LPC9351) . . . . . . 47

Table 35. PGA0 Control register B (PGACON0B - address

FFCEh) bit allocation (P89LPC9351) . . . . . . . 47


FFCEh) bit description (P89LPC9351) . . . . . . 47


FFE4h) bit allocation (P89LPC9351) . . . . . . . 47


FFE4h) bit description (P89LPC9351) . . . . . . 47

Table 39. Interrupt priority level . . . . . . . . . . . . . . . . . . . 48

Table 40. Summary of interrupts . . . . . . . . . . . . . . . . . . . 49

Table 41. Number of I/O pins available . . . . . . . . . . . . . . 51

Table 42. Port output configuration settings . . . . . . . . . . 51

Table 43. Port output configuration . . . . . . . . . . . . . . . . . 55

Table 44. BOD Trip points configuration . . . . . . . . . . . . . 56

Table 45. BOD Reset and BOD Interrupt configuration . . 57

Table 46. Power reduction modes . . . . . . . . . . . . . . . . . 58

Table 47. Power Control register (PCON - address 87h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 48. Power Control register (PCON - address 87h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 49. Power Control register A (PCONA - address B5h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 50. Power Control register A (PCONA - address B5h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 59

Table 51. Reset Sources register (RSTSRC - address DFh) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 52. Reset Sources register (RSTSRC - address DFh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . 61

Table 53. Timer/Counter Mode register (TMOD - address

89h) bit allocation . . . . . . . . . . . . . . . . . . . . . . 62

Table 54. Timer/Counter Mode register (TMOD - address

89h) bit description . . . . . . . . . . . . . . . . . . . . . 62

Table 55. Timer/Counter Auxiliary Mode register (TAMOD - address 8Fh) bit allocation . . . . . . . . . . . . . . . 63

Table 56. Timer/Counter Auxiliary Mode register (TAMOD - address 8Fh) bit description . . . . . . . . . . . . . . 63

Table 57. Timer/Counter Control register (TCON) - address

88h) bit allocation . . . . . . . . . . . . . . . . . . . . . . 64

Table 58. Timer/Counter Control register (TCON - address

88h) bit description . . . . . . . . . . . . . . . . . . . . . 64

Table 59. Real-time Clock/System Timer clock sources . 68

Table 60. Real-time Clock Control register (RTCCON - address D1h) bit allocation . . . . . . . . . . . . . . . 69

Table 61. Real-time Clock Control register (RTCCON - address D1h) bit description . . . . . . . . . . . . . . 70

Table 62. CCU prescaler control register, high byte

(TPCR2H - address CBh) bit allocation . . . . . 72

Table 63. CCU prescaler control register, high byte

(TPCR2H - address CBh) bit description . . . . 72

Table 64. CCU prescaler control register, low byte (TPCR2L


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- address CAh) bit allocation . . . . . . . . . . . . . .72

Table 65. CCU prescaler control register, low byte (TPCR2L

- address CAh) bit description . . . . . . . . . . . . .72

Table 66. CCU control register 0 (TCR20 - address C8h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Table 67. CCU control register 0 (TCR20 - address C8h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Table 68. Capture compare control register (CCRx - address Exh) bit allocation . . . . . . . . . . . . . . .74

Table 69. Capture compare control register (CCRx - address Exh) bit description . . . . . . . . . . . . . .74

Table 70. Event delay counter for input capture . . . . . . .75

Table 71. Output compare pin behavior.. . . . . . . . . . . . . .77

Table 72. CCU control register 1 (TCR21 - address F9h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Table 73. CCU control register 1 (TCR21 - address F9h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Table 74. CCU interrupt status encode register (TISE2 - address DEh) bit allocation . . . . . . . . . . . . . . .80

Table 75. CCU interrupt status encode register (TISE2 - address DEh) bit description . . . . . . . . . . . . . .80

Table 76. CCU interrupt flag register (TIFR2 - address E9h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Table 77. CCU interrupt flag register (TIFR2 - address E9h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .81

Table 78. CCU interrupt control register (TICR2 - address

C9h) bit allocation . . . . . . . . . . . . . . . . . . . . . .81

Table 79. CCU interrupt control register (TICR2 - address

C9h) bit description . . . . . . . . . . . . . . . . . . . . .81

Table 80. UART SFR addresses . . . . . . . . . . . . . . . . . . .83

Table 81. UART baud rate generation . . . . . . . . . . . . . . .83

Table 82. Baud Rate Generator Control register (BRGCON

- address BDh) bit allocation . . . . . . . . . . . . . .84

Table 83. Baud Rate Generator Control register (BRGCON

- address BDh) bit description . . . . . . . . . . . . .84

Table 84. Serial Port Control register (SCON - address 98h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Table 85. Serial Port Control register (SCON - address 98h) bit description . . . . . . . . . . . . . . . . . . . . . . . . .85

Table 86. Serial Port modes . . . . . . . . . . . . . . . . . . . . . .85

Table 87. Serial Port Status register (SSTAT - address BAh) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Table 88. Serial Port Status register (SSTAT - address BAh) bit description . . . . . . . . . . . . . . . . . . . . . . . . .86

Table 89. FE and RI when SM2 = 1 in Modes 2 and 3 . .89

Table 90. Slave 0/1 examples . . . . . . . . . . . . . . . . . . . . .92

Table 91. Slave 0/1/2 examples . . . . . . . . . . . . . . . . . . .92

Table 92. I

2

C data register (I2DAT - address DAh) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Table 93. I

2

C slave address register (I2ADR - address DBh) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Table 94. I

2

C slave address register (I2ADR - address DBh) bit description . . . . . . . . . . . . . . . . . . . . . . . . . .94

Table 95. I

2

C Control register (I2CON - address D8h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

Table 96. I

2

C Control register (I2CON - address D8h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . .95

Table 97. I

2

C Status register (I2STAT - address D9h) bit

UM10308_2


allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 98. I

2

C Status register (I2STAT - address D9h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

Table 99. I

2

C clock rates selection . . . . . . . . . . . . . . . . . 97

Table 100.I

2

C Control register (I2CON - address D8h) . . 97

Table 101.I

2

C Control register (I2CON - address D8h) . . 99

Table 102.Master Transmitter mode . . . . . . . . . . . . . . . 102

Table 103.Master Receiver mode . . . . . . . . . . . . . . . . . 103

Table 104.Slave Receiver mode . . . . . . . . . . . . . . . . . . 104

Table 105.Slave Transmitter mode . . . . . . . . . . . . . . . . 106

Table 106.SPI Control register (SPCTL - address E2h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Table 107.SPI Control register (SPCTL - address E2h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 108.SPI Status register (SPSTAT - address E1h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 109.SPI Status register (SPSTAT - address E1h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Table 110. SPI Data register (SPDAT - address E3h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Table 111. SPI master and slave selection . . . . . . . . . . . 111

Table 112. Comparator Control register (CMP1 - address

ACh, CMP2 - address ADh) bit allocation . . . 118

Table 113. Comparator Control register (CMP1 - address

ACh, CMP2 - address ADh) bit description . . 118

Table 114. Keypad Pattern register (KBPATN - address 93h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 115. Keypad Pattern register (KBPATN - address 93h) bit description . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 116. Keypad Control register (KBCON - address 94h) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 117. Keypad Control register (KBCON - address 94h) bit description . . . . . . . . . . . . . . . . . . . . . . . . 122

Table 118. Keypad Interrupt Mask register (KBMASK - address 86h) bit allocation . . . . . . . . . . . . . . 123

Table 119. Keypad Interrupt Mask register (KBMASK - address 86h) bit description . . . . . . . . . . . . . 123

Table 120.Watchdog timer configuration . . . . . . . . . . . . 124

Table 121.Watchdog Timer Control register (WDCON - address A7h) bit allocation . . . . . . . . . . . . . . 126

Table 122.Watchdog Timer Control register (WDCON - address A7h) bit description . . . . . . . . . . . . . 126

Table 123.Watchdog timeout vales . . . . . . . . . . . . . . . . 126

Table 124.Watchdog input clock selection . . . . . . . . . . . 127

Table 125.AUXR1 register (address A2h) bit allocation 129

Table 126.AUXR1 register (address A2h) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Table 127.Data EEPROM control register (DEECON address F1h) bit allocation. . . . . . . . . . . . . . . 131

Table 128.Data EEPROM control register (DEECON address F1h) bit description. . . . . . . . . . . . . . 131

Table 129.Flash Memory Control register (FMCON - address

E4h) bit allocation . . . . . . . . . . . . . . . . . . . . . 137

Table 130.Flash Memory Control register (FMCON - address

E4h) bit description . . . . . . . . . . . . . . . . . . . . 137

Table 131.Boot loader address and default Boot vector 140

Table 132.In-system Programming (ISP) hex record formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142


158 of 162


Table 133.IAP error status . . . . . . . . . . . . . . . . . . . . . . .146

Table 134.IAP function calls . . . . . . . . . . . . . . . . . . . . . .147

Table 135.Flash User Configuration Byte 1 (UCFG1) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .149

Table 136.Flash User Configuration Byte 1 (UCFG1) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .149

Table 137.Oscillator type selection . . . . . . . . . . . . . . . . .150

Table 138.Flash User Configuration Byte 2 (UCFG2) bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .150

Table 139.Flash User Configuration Byte 2 (UCFG2) bit description . . . . . . . . . . . . . . . . . . . . . . . . . . .150

Table 140.Sector Security Bytes (SECx) bit allocation . .150

Table 141.Sector Security Bytes (SECx) bit description .151

Table 142.Effects of Security Bits . . . . . . . . . . . . . . . . . .151

Table 143.Boot Vector (BOOTVEC) bit allocation . . . . .151

Table 144.Boot Vector (BOOTVEC) bit description . . . .151

Table 145.Boot Status (BOOTSTAT) bit allocation . . . . .151

Table 146.Boot Status (BOOTSTAT) bit description . . . .152

Table 147.Instruction set summary . . . . . . . . . . . . . . . .153

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P89LPC9331/9341/9351 User manual

UM10308_2



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UM10308

P89LPC9331/9341/9351 User manual

23. Figures

Fig 1.

P89LPC9331/9341 TSSOP28 pin configuration . .3

Fig 2.

P89LPC9351 TSSOP28 pin configuration . . . . . . .4

Fig 3.

PLCC28 pin configuration . . . . . . . . . . . . . . . . . . .4

Fig 4.

P89LPC9331/9341 logic symbol . . . . . . . . . . . . . .8

Fig 5.

P89LPC9351 logic symbol. . . . . . . . . . . . . . . . . . .8

Fig 6.

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Fig 7.

P89LPC9331/9341/9351 memory map . . . . . . . .28

Fig 8.

Using the crystal oscillator . . . . . . . . . . . . . . . . . .31

Fig 9.

Block diagram of oscillator control . . . . . . . . . . . .32

Fig 10. P89LPC9331/9341 ADC block diagram. . . . . . . .35

Fig 11. P89LPC9351 ADC block diagram . . . . . . . . . . . .36

Fig 12. PGA block diagram . . . . . . . . . . . . . . . . . . . . . . .37

Fig 13. Interrupt sources, interrupt enables, and power-down wake-up sources . . . . . . . . . . . . . . .50

Fig 14. Quasi-bidirectional output . . . . . . . . . . . . . . . . . .52

Fig 15. Open drain output . . . . . . . . . . . . . . . . . . . . . . . .53

Fig 16. Input only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Fig 17. Push-pull output . . . . . . . . . . . . . . . . . . . . . . . . . .54

Fig 18. Block diagram of reset . . . . . . . . . . . . . . . . . . . . .61

Fig 19. Timer/counter 0 or 1 in Mode 0 (13-bit counter) .65

Fig 20. Timer/counter 0 or 1 in mode 1 (16-bit counter) .65

Fig 21. Timer/counter 0 or 1 in Mode 2 (8-bit auto-reload) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Fig 22. Timer/counter 0 Mode 3 (two 8-bit counters) . . . .66

Fig 23. Timer/counter 0 or 1 in mode 6 (PWM auto-reload) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Fig 24. Real-time clock/system timer block diagram . . . .67

Fig 25. Capture Compare Unit block diagram . . . . . . . . .71

Fig 26. Asymmetrical PWM, downcounting . . . . . . . . . . .76

Fig 27. Symmetrical PWM . . . . . . . . . . . . . . . . . . . . . . . .76

Fig 28. Alternate output mode . . . . . . . . . . . . . . . . . . . . .77

Fig 29. Capture/compare unit interrupts . . . . . . . . . . . . .80

Fig 30. Baud rate generation for UART (Modes 1, 3) . . .84

Fig 31. Serial Port Mode 0 (double buffering must be disabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Fig 32. Serial Port Mode 1 (only single transmit buffering case is shown) . . . . . . . . . . . . . . . . . . . . . . . . . . .88

Fig 33. Serial Port Mode 2 or 3 (only single transmit buffering case is shown) . . . . . . . . . . . . . . . . . . .88

Fig 34. Transmission with and without double buffering .90

Fig 35. I

2

C-bus configuration . . . . . . . . . . . . . . . . . . . . . .94

Fig 36. Format in the Master Transmitter mode. . . . . . . .98

Fig 37. Format of Master Receiver mode . . . . . . . . . . . .99

Fig 38. A Master Receiver switches to Master Transmitter after sending Repeated Start . . . . . . . . . . . . . . . .99

Fig 39. Format of Slave Receiver mode . . . . . . . . . . . .100

Fig 40. Format of Slave Transmitter mode . . . . . . . . . .100

Fig 41. I

2

C serial interface block diagram . . . . . . . . . . .101

Fig 42. SPI block diagram . . . . . . . . . . . . . . . . . . . . . . .108

Fig 43. SPI single master single slave configuration . . . 110

Fig 44. SPI dual device configuration, where either can be a master or a slave . . . . . . . . . . . . . . . . . . . . . . . . 110

Fig 45. SPI single master multiple slaves configuration. 111

Fig 46. SPI slave transfer format with CPHA = 0. . . . . . 114

Fig 47. SPI slave transfer format with CPHA = 1. . . . . . 115

Fig 48. SPI master transfer format with CPHA = 0 . . . . 116

UM10308_2


Fig 49. SPI master transfer format with CPHA = 1 . . . . 117

Fig 50. P89LPC9331/9341 comparator input and output connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Fig 51. P89LPC9351 comparator input and output connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

Fig 52. Comparator configurations. (Suppose PGA1 is disabled, or gain = 1). . . . . . . . . . . . . . . . . . . . . 121

Fig 53. Watchdog Prescaler . . . . . . . . . . . . . . . . . . . . . 124

Fig 54. Watchdog Timer in Watchdog Mode

(WDTE = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

Fig 55. Watchdog Timer in Timer Mode (WDTE = 0) . . 129

Fig 56. Forcing ISP mode . . . . . . . . . . . . . . . . . . . . . . . 140


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P89LPC9331/9341/9351 User manual

24. Contents

4

4.1

4.2

5

2

2.5

2.6

2.7

2.8

2.9

2.10

2.1

2.2

2.2.1

2.3

2.3.1

2.3.2

2.3.3

2.4

1

1.1

1.2

1.3

1.4

1.5

1.6

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . 3

Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

Logic symbols . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Special function registers . . . . . . . . . . . . . . . . 10

Memory organization . . . . . . . . . . . . . . . . . . . 28

Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Enhanced CPU . . . . . . . . . . . . . . . . . . . . . . . . 29

Clock definitions . . . . . . . . . . . . . . . . . . . . . . . 29

Oscillator Clock (OSCCLK). . . . . . . . . . . . . . . 29

Crystal oscillator option. . . . . . . . . . . . . . . . . . 29

Low speed oscillator option . . . . . . . . . . . . . . 29

Medium speed oscillator option . . . . . . . . . . . 30

High speed oscillator option . . . . . . . . . . . . . . 30

Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . 30

On-chip RC oscillator option . . . . . . . . . . . . . . 30

Watchdog oscillator option . . . . . . . . . . . . . . . 31

External clock input option . . . . . . . . . . . . . . . 31

Clock source switching on the fly . . . . . . . . . . 32

Oscillator Clock (OSCCLK) wake-up delay . . 33

CPU Clock (CCLK) modification: DIVM register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Low power select . . . . . . . . . . . . . . . . . . . . . . 34 2.11

3 A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3.1

3.2

3.2.1

General description . . . . . . . . . . . . . . . . . . . . 34

A/D features . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Programmable Gain Amplifier (PGA)

(P89LPC9351) . . . . . . . . . . . . . . . . . . . . . . . . 36

3.2.1.1

PGA calibration. . . . . . . . . . . . . . . . . . . . . . . . 37

3.2.1.2

Channel selection dependency . . . . . . . . . . . 38

3.2.2

3.2.3

Temperature sensor . . . . . . . . . . . . . . . . . . . . 38

ADC operating modes . . . . . . . . . . . . . . . . . . 39

3.2.3.1

Fixed channel, single conversion mode . . . . . 39

3.2.3.2

Fixed channel, continuous conversion mode . 39

3.2.3.3

Auto scan, single conversion mode . . . . . . . . 40

3.2.3.4

Auto scan, continuous conversion mode . . . . 40

3.2.3.5

Dual channel, continuous conversion mode . . 40

3.2.3.6

Single step mode . . . . . . . . . . . . . . . . . . . . . . 41

3.2.3.7

Conversion mode selection bits . . . . . . . . . . . 41

3.2.4

Conversion start modes . . . . . . . . . . . . . . . . . 41

3.2.4.1

Timer triggered start . . . . . . . . . . . . . . . . . . . . 41

3.2.4.2

Start immediately . . . . . . . . . . . . . . . . . . . . . . 41

3.2.4.3

Edge triggered . . . . . . . . . . . . . . . . . . . . . . . . 41

3.2.4.4

Dual start immediately . . . . . . . . . . . . . . . . . . 42

3.2.5

3.2.6

Boundary limits interrupt . . . . . . . . . . . . . . . . . 42

DAC output to a port pin with high output impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Clock divider . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3.2.7

3.2.8

3.2.9

I/O pins used with ADC functions . . . . . . . . . . 42

Power-down and Idle mode . . . . . . . . . . . . . . 43

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Interrupt priority structure . . . . . . . . . . . . . . . . 48

External Interrupt pin glitch suppression. . . . . 49

I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

UM10308_2

User manual

11.14

Rev. 02 — 5 May 2009

7

7.1

8

8.1

8.2

8.3

8.4

8.5

8.6

9

9.1

9.2

9.3

9.3.1

9.4

5.1

5.2

5.3

5.4

5.5

5.6

5.7

6

6.1

6.2

6.3

11

11.1

11.2

11.3

11.4

11.5

11.6

11.7

11.8

11.9

11.10

11.11

11.12

11.13

10

10.1

10.2

10.3

10.4

10.5

10.6

10.7

10.8

10.9

10.10

10.11

Port configurations . . . . . . . . . . . . . . . . . . . . . 51

Quasi-bidirectional output configuration. . . . . 51

Open drain output configuration. . . . . . . . . . . 52

Input-only configuration . . . . . . . . . . . . . . . . . 53

Push-pull output configuration . . . . . . . . . . . . 53

Port 0 and Analog Comparator functions . . . . 54

Additional port features . . . . . . . . . . . . . . . . . 54

Power monitoring functions . . . . . . . . . . . . . 55

Brownout detection . . . . . . . . . . . . . . . . . . . . 55

Power-on detection . . . . . . . . . . . . . . . . . . . . 57

Power reduction modes . . . . . . . . . . . . . . . . . 57

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Reset vector. . . . . . . . . . . . . . . . . . . . . . . . . . 61

Timers 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . 62

Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Timer overflow toggle output . . . . . . . . . . . . . 66

Real-time clock system timer. . . . . . . . . . . . . 66

Real-time clock source. . . . . . . . . . . . . . . . . . 67

Changing RTCS1/RTCS0 . . . . . . . . . . . . . . . 68

Real-time clock interrupt/wake-up . . . . . . . . . 68

Real-time clock read back . . . . . . . . . . . . . . . 68

Reset sources affecting the Real-time clock . 68

Capture/Compare Unit (CCU) (P89LPC9351) 70

CCU Clock (CCUCLK) . . . . . . . . . . . . . . . . . . 70

CCU Clock prescaling . . . . . . . . . . . . . . . . . . 70

Basic timer operation . . . . . . . . . . . . . . . . . . . 71

Output compare . . . . . . . . . . . . . . . . . . . . . . . 73

Input capture . . . . . . . . . . . . . . . . . . . . . . . . . 74

PWM operation . . . . . . . . . . . . . . . . . . . . . . . 75

Alternating output mode. . . . . . . . . . . . . . . . . 76

Synchronized PWM register update . . . . . . . 77

HALT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

PLL operation. . . . . . . . . . . . . . . . . . . . . . . . . 78

CCU interrupt structure . . . . . . . . . . . . . . . . . 79

UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

SFR space . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Baud Rate generator and selection . . . . . . . . 83

Updating the BRGR1 and BRGR0 SFRs . . . . 83

Framing error . . . . . . . . . . . . . . . . . . . . . . . . . 84

Break detect. . . . . . . . . . . . . . . . . . . . . . . . . . 84

More about UART Mode 0 . . . . . . . . . . . . . . . 86

More about UART Mode 1 . . . . . . . . . . . . . . . 87

More about UART Modes 2 and 3 . . . . . . . . . 88

Framing error and RI in Modes 2 and 3 with

SM2 = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

Break detect. . . . . . . . . . . . . . . . . . . . . . . . . . 89


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11.19

11.20

12

12.1

12.2

12.3

12.4

12.5

11.15

11.16

11.17

11.18

12.6

12.6.1

12.6.2

12.6.3

12.6.4

14

14.1

14.2

14.3

14.4

14.5

14.6

13

13.1

13.2

13.3

13.4

13.5

13.6

13.7

15

16

16.1

16.2

16.3

16.4

16.5

16.6

17

17.1

17.2

18

18.1

Double buffering . . . . . . . . . . . . . . . . . . . . . . . 89

Double buffering in different modes . . . . . . . . 89

Transmit interrupts with double buffering enabled

(Modes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . 89

The 9th bit (bit 8) in double buffering (Modes 1, 2, and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

Multiprocessor communications . . . . . . . . . . . 91

Automatic address recognition . . . . . . . . . . . . 92

I

2

C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

I

2

C data register . . . . . . . . . . . . . . . . . . . . . . . 94

I

2

C slave address register . . . . . . . . . . . . . . . 94

I

2

C control register . . . . . . . . . . . . . . . . . . . . . 95

I

2

C Status register. . . . . . . . . . . . . . . . . . . . . . 96

I

2

C SCL duty cycle registers I2SCLH and

I2SCLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

I

2

C operation modes. . . . . . . . . . . . . . . . . . . . 97

Master Transmitter mode . . . . . . . . . . . . . . . . 97

Master Receiver mode . . . . . . . . . . . . . . . . . . 98

Slave Receiver mode . . . . . . . . . . . . . . . . . . . 99

Slave Transmitter mode . . . . . . . . . . . . . . . . 100

Serial Peripheral Interface (SPI) . . . . . . . . . . 107

Configuring the SPI . . . . . . . . . . . . . . . . . . . 111

Additional considerations for a slave . . . . . . 112

Additional considerations for a master . . . . . 112

Mode change on SS . . . . . . . . . . . . . . . . . . . 112

Write collision . . . . . . . . . . . . . . . . . . . . . . . . 113

Data mode . . . . . . . . . . . . . . . . . . . . . . . . . . 113

SPI clock prescaler select . . . . . . . . . . . . . . 117

Analog comparators . . . . . . . . . . . . . . . . . . . 117

Comparator configuration . . . . . . . . . . . . . . . 117

Internal reference voltage . . . . . . . . . . . . . . . 119

Comparator input pins . . . . . . . . . . . . . . . . . 119

Comparator interrupt. . . . . . . . . . . . . . . . . . . 120

Comparators and power reduction modes . . 120

Comparators configuration example. . . . . . . 121

Keypad interrupt (KBI). . . . . . . . . . . . . . . . . . 122

Watchdog timer (WDT) . . . . . . . . . . . . . . . . . 123

Watchdog function . . . . . . . . . . . . . . . . . . . . 123

Feed sequence . . . . . . . . . . . . . . . . . . . . . . . 124

Watchdog clock source . . . . . . . . . . . . . . . . 127

Watchdog Timer in Timer mode . . . . . . . . . . 128

Power-down operation . . . . . . . . . . . . . . . . . 129

Periodic wake-up from power-down without an external oscillator . . . . . . . . . . . . . . . . . . . . . 129

Additional features . . . . . . . . . . . . . . . . . . . . 129

Software reset. . . . . . . . . . . . . . . . . . . . . . . . 130

Dual Data Pointers . . . . . . . . . . . . . . . . . . . . 130

Data EEPROM (P89LPC9351) . . . . . . . . . . . . 131

Data EEPROM read . . . . . . . . . . . . . . . . . . . 132

18.6

18.7

19

19.1

19.2

19.3

19.4

19.5

19.6

18.2

18.3

18.4

18.5

19.7

19.8

19.9

19.10

19.11

19.12

19.13

19.14

19.15

19.16

19.17

19.18

19.19

19.20

20

21

21.1

21.2

21.3

22

23

24

Data EEPROM write . . . . . . . . . . . . . . . . . . 132

Hardware reset . . . . . . . . . . . . . . . . . . . . . . 133

Multiple writes to the DEEDAT register . . . . 133

Sequences of writes to DEECON and DEEDAT registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

Data EEPROM Row Fill . . . . . . . . . . . . . . . . 133

Data EEPROM Block Fill . . . . . . . . . . . . . . . 134

Flash memory . . . . . . . . . . . . . . . . . . . . . . . . 134

General description . . . . . . . . . . . . . . . . . . . 134

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

Flash programming and erase . . . . . . . . . . . 135

Using Flash as data storage: IAP-Lite . . . . . 135

In-circuit programming (ICP) . . . . . . . . . . . . 139

ISP and IAP capabilities of the

P89LPC9331/9341/9351 . . . . . . . . . . . . . . . 139

Boot ROM . . . . . . . . . . . . . . . . . . . . . . . . . . 139

Power on reset code execution . . . . . . . . . . 139

Hardware activation of Boot Loader. . . . . . . 140

In-system programming (ISP) . . . . . . . . . . . 140

Using the In-system programming (ISP) . . . 141

In-application programming (IAP) . . . . . . . . 144

IAP authorization key . . . . . . . . . . . . . . . . . . 144

Flash write enable . . . . . . . . . . . . . . . . . . . . 144

Configuration byte protection . . . . . . . . . . . . 145

IAP error status . . . . . . . . . . . . . . . . . . . . . . 145

User configuration bytes . . . . . . . . . . . . . . . 149

User security bytes . . . . . . . . . . . . . . . . . . . 150

Boot Vector register . . . . . . . . . . . . . . . . . . . 151

Boot status register . . . . . . . . . . . . . . . . . . . 151

Instruction set . . . . . . . . . . . . . . . . . . . . . . . . 153

Legal information . . . . . . . . . . . . . . . . . . . . . 156

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 156

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . 156

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . 156

Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161

Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

© NXP B.V. 2009.

All rights reserved.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: [email protected]

Date of release: 5 May 2009

Document identifier: UM10308_2

NXP P89LPC9331, P89LPC9341, P89LPC9351 Microcontroller User manual

Assistant Bot

Rev. 02 — 5 May 2009 User manual

Contact information

1.

Introduction

2.

Clocks

2.2.1 Oscillator Clock (OSCCLK)

2.3.1 Low speed oscillator option

2.3.2 Medium speed oscillator option

2.3.3 High speed oscillator option

3.

A/D converter

3.2.1 Programmable Gain Amplifier (PGA) (P89LPC9351)

Σ

Σ

3.2.2 Temperature sensor

3.2.3 ADC operating modes

3.2.4 Conversion start modes

3.2.5 Boundary limits interrupt

3.2.6 DAC output to a port pin with high output impedance

3.2.7 Clock divider

3.2.8 I/O pins used with ADC functions

3.2.9 Power-down and Idle mode

4.

Interrupts

5.

I/O ports

6.

Power monitoring functions

7.

Reset

8.

Timers 0 and 1

9.

Real-time clock system timer

9.3.1 Real-time clock read back

10. Capture/Compare Unit (CCU) (P89LPC9351)

11. UART

12. I

C interface

12.6.1 Master Transmitter mode

12.6.2 Master Receiver mode

12.6.3 Slave Receiver mode

12.6.4 Slave Transmitter mode

13. Serial Peripheral Interface (SPI)

14. Analog comparators

15. Keypad interrupt (KBI)

16. Watchdog timer (WDT)

17. Additional features

18. Data EEPROM (P89LPC9351)

19. Flash memory

20. Instruction set

21. Legal information

22. Tables

23. Figures

24. Contents

Key Features

Frequently Answers and Questions

What is the P89LPC9331/9341/9351 series?

What are the key features of the P89LPC9331/9341/9351 series?

What applications are the P89LPC9331/9341/9351 series suited for?

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