MAX17497A/MAX17497B AC-DC and DC-DC Peak Current

MAX17497A/MAX17497B AC-DC and DC-DC Peak Current
EVALUATION KIT AVAILABLE
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
General Description
The MAX17497A/MAX17497B include both a currentmode fixed-frequency flyback converter and a synchronous step-down regulator. They contain all the control
circuitry required to design wide input-voltage nonisolated power supplies to supply multiple output rails for
smart meters, industrial control, and other similar applications. The MAX17497A has its rising/falling undervoltage
lockout (UVLO) thresholds optimized for universal offline
(85V AC to 265V AC) applications, while the MAX17497B
supports undervoltage lockout (UVLO) thresholds suitable to low-voltage DC-DC applications. Both devices
also include a 3.3V fixed-output synchronous step-down
regulator that delivers up to 600mA load current.
The switching frequency of the MAX17497A flyback
converter is 250kHz, while the MAX17497B flyback/
boost converter is 500kHz. The internally compensated
synchronous step-down regulator switches at 1MHz on
both versions. These frequencies allow the use of tiny
magnetic and filter components resulting in compact,
cost-effective power supplies. An EN/UVLO input allows
the user to start the power supply precisely at the desired
input voltage, while also functioning as an on/off pin. The
OVI pin enables implementation of an input overvoltageprotection scheme that ensures the converter shuts
down when the DC input voltage exceeds the desired
maximum value.
Programmable current limit allows proper sizing and
protection of the primary switching FET. The devices
support a maximum duty cycle greater than 92% and
provides programmable slope compensation to allow
optimization of control-loop performance. The devices
provide an open-drain RESETN pin that serves as a
power-good indicator and enters the high-impedance
state to indicate that the flyback/boost converter and
3.3V step-down regulator outputs are in regulation. An
SSF pin allows programmable soft-start time for the flyback/boost converter, while an internal digital soft-start is
employed for the 3.3V step-down regulator to limit inrush
current. Hiccup mode overcurrent protection and thermal
shutdown are provided to minimize dissipation under
overcurrent and overtemperature fault conditions. The
devices are available in a space-saving 16-pin (3mm x
3mm) TQFN package with 0.5mm lead spacing.
Benefits and Features
S Reduced Component Count and Board Space
 Flyback/Boost with Integrated Internally
Compensated Step-Down Regulator
 No Current-Sense Resistor
 Space-Saving 16-Pin (3mm x 3mm) TQFN
Package
S Minimal Radio Interference
 250kHz Switching in Offline Version
Minimizes Interference with Radio Receivers
in Smart Meter Applications
S Reduced Inrush Current
 Programmable Flyback/Boost Soft-Start
 Internal Digital Soft-Start for Step-Down
Regulator
S Reduced Power Dissipation Under Fault
 Hiccup Mode Overcurrent Protection
 Thermal Shutdown with Hysteresis
S Robust Protection Features
 Flyback/Boost Programmable Current Limit
 Input Overvoltage Protection
S Optimized Loop Performance
 Programmable Slope Compensation for
Flyback/Boost Maximizes Obtainable Phase
Margin
S High Efficiency
 Low RDSON, 150mI, 65V-Rated Internal
nMOSFET
 3.3V Step-Down Regulator Efficiency Greater
Than 90%
S Optional Spread Spectrum
Applications
AC-DC Power Supplies for Smart Meter
Applications
Universal-Input Offline AC-DC Power Supplies
Wide-Range DC Input Flyback/Boost Industrial
Power Supplies
Ordering Information appears at end of data sheet.
For related parts and recommended products to use with this part,
refer to www.maximintegrated.com/MAX17497A.related.
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-5981; Rev 3; 4/13
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
ABSOLUTE MAXIMUM RATINGS
IN to SGND.............................................................-0.3V to +40V
EN/UVLO to SGND........................................ -0.3V to VIN + 0.3V
OVI to SGND................................................-0.3V to VCC + 0.3V
VCC to SGND...........................................................-0.3V to +6V
SSF, RLIMF, EAFN, COMPF, SCOMPF
to SGND................................................ -0.3V to (VCC + 0.3V)
LXF to SGND..........................................................-0.3V to +70V
INB to SGND..........................................................-0.3V to +26V
LXB to SGND............................................... -0.3V to VINB + 0.3V
OUTB to SGND........................................................-0.3V to +6V
RESETN to SGND.....................................................-0.3V to +6V
PGNDF, PGNDB to SGND....................................-0.3V to +0.3V
Continuous Power Dissipation (Single-Layer Board)
TQFN (derate 20.8mW/NC above +70NC)..................1700mW
Operating Temperature Range......................... -40NC to +125NC
Storage Temperature Range............................. -65NC to +160NC
Junction Temperature (continuous).................................+150NC
Lead Temperature (soldering, 10s).................................+300NC
Soldering Temperature (reflow).......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = +15V, VEN/UVLO = +2V, COMPF = open, CIN = 1FF, CVCC = 1FF, TA = TJ = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 1)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
INPUT SUPPLY (VIN)
IN Voltage Range (VIN)
IN Supply Startup Current Under
UVLO
MAX17497A
4.5
29
MAX17497B
4.5
36
IINSTARTUP, VIN < UVLO or EN/UVLO = SGND
22
36
FA
mA
IN Supply Current (IIN)
Switching, fSW = 250kHz
2.75
4.5
IN Boostrap UVLO Rising
Threshold
MAX17497A
19
20.5
22
MAX17497B
3.85
4.15
4.4
IN Bootstrap UVLO Falling
EN/UVLO Threshold
EN/UVLO Input Leakage Current
V
V
3.65
3.95
4.25
Rising
1.18
1.23
1.28
V
Falling
1.11
1.17
1.21
0V < VEN/UVLO < 1.5V, TA = +25NC
-100
0
+100
nA
4.8
5
5.2
V
160
300
mV
V
LDO
VCC Output Voltage Range
6V < VIN < 29V, 0mA < IVCC < 50mA
VCC Dropout Voltage
VIN = 4.5V, IVCC = 20mA
VCC Current Limit
VCC = 0V, VIN = 6V
50
100
mA
Rising
1.18
1.23
1.28
Falling
1.11
1.17
1.21
0V < VOVI < 1.5V, TA = +25NC
-100
0
OVERVOLTAGE PROTECTION
OVI Threshold
OVI Masking Delay
OVI Input Leakage Current
Maxim Integrated
2
V
Fs
+100
nA
2
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
ELECTRICAL CHARACTERISTICS (continued)
(VIN = +15V, VEN/UVLO = +2V, COMPF = open, CIN = 1FF, CVCC = 1FF, TA = TJ = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 1)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
FLYBACK/BOOST CONVERTER
Flyback/Boost Switching
Frequency
MAX17497A
235
250
265
MAX17497B
470
500
530
Flyback/Boost Maximum Duty
Cycle
fSW = 250kHz (MAX17497A)
92
94.5
97
fSW = 500kHz (MAX17497B)
90
92
94
SSF Pullup Current
VSSF = 400mV
kHz
%
9
10
11
FA
SSF Set Point Voltage
1.12
1.22
1.24
V
SSF Peak Current-Limit Enable
Threshold
1.11
1.17
1.21
V
1.2
1.22
EAFN Regulation Point
EAFN Input Bias Current
0V < VEAFN < 1.5V, TA = +25NC
-100
Error-Amplifier Open-Loop
Voltage Gain
1.24
V
+100
nA
90
dB
Error-Amplifier Transconductance
VCOMPF = 2V, VRLIMF = 1V
1.5
1.8
2.1
mS
Error-Amplifier Source Current
VCOMPF = 2V, VEAFN = 1V
80
120
210
FA
Error-Amplifier Sink Current
VCOMPF = 2V, VEAFN = 1.5V
80
120
210
FA
0.45
0.5
0.55
I
31
33.5
36
V
175
380
mI
Current-Sense Transresistance
IN Clamp Voltage
EN/UVLO = SGND, IIN_ = 1mA (MAX17497A)
(Note 2)
LXF DMOS Switch On-Resistance
(RDSON_LXF)
ILXF = 200mA
LXF DMOS Peak Current Limit
RLIMF = 100K
1.62
1.9
2.23
A
LXF DMOS Runaway Current
Limit
RLIMF = 100K
1.9
2.3
2.6
A
LXF Leakage Current
VLXF = 65V, TA = +25NC
0.1
2
FA
Peak Switch Current Limit with
RLIMF Open
0.35
0.45
0.54
A
Runaway Switch Current Limit
with RLIMF Open
0.39
0.5
0.6
A
9
10
11
FA
RLIMF Reference Current
Number of Flyback/Boost
Runaway Current-Limit Hits
Before Hiccup Timeout
1
#
Flyback/Boost Overcurrent
Hiccup Timeout
32
ms
Maxim Integrated
3
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
ELECTRICAL CHARACTERISTICS (continued)
(VIN = +15V, VEN/UVLO = +2V, COMPF = open, CIN = 1FF, CVCC = 1FF, TA = TJ = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 1)
PARAMETER
CONDITIONS
MIN
Minimum On-Time
TYP
MAX
UNITS
11
FA
150
kI
225
mV/Fs
110
SCOMPF Pullup Current
9
Slope-Compensation Resistor
Range
MAX17497B
30
Slope-Compensation Ramp
SCOMPF = 100kI
175
Default Slope-Compensation
Ramp
SCOMPF = open
10
200
ns
60
mV/Fs
STEP-DOWN REGULATOR
INB Voltage Range
INB Quiescent Supply Current
INB UVLO Threshold
7
VINB = 16V, VOUTB > 3.3V
V
300
FA
Rising
6.2
6.5
6.7
Falling
5.9
6.2
6.4
425
800
High-Side RDSON
ILXB =200mA
Low-Side RDSON
ILXB =200mA
Switching Frequency
LXB Leakage Current
16
200
0.94
VLXB = VINB - 1V, VLXB = VPGNDB + 1V,
TA = +25NC
LXB Dead Time
(Note 3)
VOUTB Output-Voltage Accuracy
7V < VINB <16V, 50mA < IOUT < 600mA
VOUTB Input Bias Current
VOUTB = 3.3V
Peak Current-Limit Fault
Threshold
VOUTB = 3.1V
0.9
Runaway Current-Limit Threshold
VOUTB < 100mV
1.05
Soft-Start Duration Count
VINB > 7V
Number of Runaway Current-Limit
Hits Before Hiccup Timeout
Overcurrent Hiccup Timeout
Minimum On-Time
mI
225
425
mI
1
1.06
MHz
0.1
1
FA
5
3.245
V
ns
3.3
3.355
V
7
10
FA
1.1
1.23
A
1.25
1.45
A
2048
Cycles
1
Hits
32,768
Cycles
100
ns
RESETN
RESETN Output Leakage Current
(Off-State)
VRESETN = 5V, TA = +25NC
-1
+1
FA
RESETN Output Voltage
(On-State)
IRESETN = 10mA
0
0.4
V
Maxim Integrated
4
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
ELECTRICAL CHARACTERISTICS (continued)
(VIN = +15V, VEN/UVLO = +2V, COMPF = open, CIN = 1FF, CVCC = 1FF, TA = TJ = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.) (Note 1)
PARAMETER
CONDITIONS
RESETN Higher Thresholds
RESETN Lower Thresholds
MIN
TYP
MAX
EAFN rising
93.5
95
96.5
OUTB rising
93.5
95
96.5
EAFN falling
90.5
92
93.5
OUTB falling
90.5
92
93.5
RESETN Delay After EAFN and
VOUTB Reach 95% Regulation
(MAX17497A/MAX17497B)
UNITS
%
%
4
ms
160
NC
20
NC
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Temperature rising
Thermal Shutdown Hysteresis
Note 1: All devices are 100% production tested at TA = +25NC. Limits over temperature are guaranteed by design.
Note 2: The MAX17497A is intended for use in universal input power supplies. The internal clamp circuit at IN is used to prevent
the bootstrap capacitor from charging to a voltage beyond the absolute maximum rating of the device when EN/UVLO is
low (shutdown mode). Externally limit the current to IN (hence to clamp) to 2mA (max) when EN/UVLO is low.
Note 3: Guarantees cross conduction is avoided and it is not larger than specified max value to guarantee loop-regulation capability.
Typical Operating Characteristics
(VIN = +15V, VEN/UVLO = +2V, COMPF = open, CIN = 1FF, CVCC = 1FF, TA = TJ = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.)
BOOTSTRAP UVLO WAKE-UP LEVEL
vs. TEMPERATURE (MAX17497A)
MAX17497A/B toc01
MAX17497A/B toc02
4.15
MAX17497A/B toc03
4.015
20.22
20.20
20.18
20.16
IN UVLO SHUTDOWN LEVEL (V)
4.010
20.24
IN UVLO WAKE-UP LEVEL (V)
BOOTSTRAP UVLO WAKE-UP LEVEL (V)
20.26
IN UVLO SHUTDOWN LEVEL vs. TEMPERATURE
(MAX17497A /MAX17497B)
IN UVLO WAKE-UP LEVEL
vs. TEMPERATURE (MAX17497B)
4.10
4.05
4.00
3.95
4.005
4.000
3.995
3.990
3.985
3.980
20.14
3.90
-40 -20
0
20
40
60
TEMPERATURE (°C)
Maxim Integrated
80
100 120
3.975
-40 -20
0
20
40
60
TEMPERATURE (°C)
80
100 120
-40 -20
0
20
40
60
80
100 120
TEMPERATURE (°C)
5
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
Typical Operating Characteristics (continued)
(VIN = +15V, VEN/UVLO = +2V, COMPF = open, CIN = 1FF, CVCC = 1FF, TA = TJ = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.)
EN/UVLO RISING LEVEL vs. TEMPERATURE
(MAX17497A/MAX17497B)
1.235
1.230
1.225
1.220
1.215
MAX17497A/B toc05
1.170
EN/UVLO FALLING LEVEL (V)
EN/UVLO RISING LEVEL (V)
EN/UVLO FALLING LEVEL vs. TEMPERATURE
(MAX17497A/MAX17497B)
MAX17497A/B toc04
1.165
1.160
1.155
1.150
1.145
1.210
-40 -20
0
20
40
60
80
1.140
100 120
-40 -20
0
20
40
60
80
100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
OVI RISING LEVEL vs. TEMPERATURE
(MAX17497A /MAX17497B)
OVI FALLING LEVEL vs. TEMPERATURE
(MAX17497A/MAX17497B)
MAX17497A/B toc06
1.225
MAX17497A/B toc07
1.160
OVI FALLING LEVEL (V)
OVI RISING LEVEL (V)
1.155
1.220
1.215
1.150
1.145
1.140
1.210
1.135
-40 -20
0
20
40
60
100 120
0
20
40
60
80
100 120
TEMPERATURE (°C)
IN CURRENT UNDER UVLO vs. TEMPERATURE
(MAX17497A/MAX17497B)
IN CURRENT DURING SWITCHING
vs. TEMPERATURE
MAX17497A/B toc08
26
24
22
MAX17497A/B toc09
3.6
IN CURRENT DURING SWITCHING (mA)
28
3.4
3.2
3.0
2.8
2.6
2.4
20
-40 -20
0
20
40
60
TEMPERATURE (°C)
Maxim Integrated
-40 -20
TEMPERATURE (°C)
30
IN CURRENT UNDER UVLO (µA)
80
80
100 120
-40 -20
0
20
40
60
80
100 120
TEMPERATURE (°C)
6
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
Typical Operating Characteristics (continued)
(VIN = +15V, VEN/UVLO = +2V, COMPF = open, CIN = 1FF, CVCC = 1FF, TA = TJ = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.)
ENABLE STARTUP WAVEFORM
(FULL LOAD)
LXF AND PRIMARY
CURRENT WAVEFORM
MAX17497A/B toc11
MAX17497A/B toc10
EN/UVLO
5V/div
VDC
200V/div
VOUTF
10V/div
VDRAIN
100V/div
VOUTB
2V/div
IPRI
1A/div
4ms/div
2µs/div
ENABLE SHUTDOWN WAVEFORM
(FULL LOAD)
RESETN WAVEFORM
MAX17497A/B toc12
MAX17497A/B toc13
VOUTF
5V/div
EN/UVLO
5V/div
VDC
200V/div
VOUTB
2V/div
VOUTF
10V/div
VRESETN
5V/div
VOUTB
2V/div
4ms/div
2ms/div
PEAK CURRENT LIMIT (ILIMF)
vs. RLIMF AT ROOM TEMPERATURE
PEAK-CURRENT LIMIT AT RLIMF = 100kI
vs. TEMPERATURE
1600
1400
1200
1000
800
600
400
MAX17497A/B toc15
2.00
1.99
PEAK-CURRENT LIMIT (A)
MAX17497A/B toc14
PEAK CURRENT LIMIT (ILIMF) (mA)
1800
1.98
1.97
1.96
1.95
200
0
1.94
0
10
20
30
40
50
60
70
RLIMF AT ROOM TEMPERATURE (kI)
Maxim Integrated
80
-40 -20
0
20
40
60
80
100 120
TEMPERATURE (°C)
7
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
Typical Operating Characteristics (continued)
(VIN = +15V, VEN/UVLO = +2V, COMPF = open, CIN = 1FF, CVCC = 1FF, TA = TJ = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.)
TRANSIENT RESPONSE
(FLYBACK-15V OUTPUT)
BODE PLOT (FLYBACK CONVERTER)
MAX17497A/B toc16
MAX17497A/B toc17
VOUTF (AC)
200mV/div
PHASE
36°/div
GAIN
10dB/div
BW = 6.9kHz
PM = 55°
ILOAD
0.5A/div
6 7 891
2
3 4 5 6 7 891
1ms/div
MAX17497A/B toc18
3.33
6.46
VOUTB VOLTAGE (V)
INB WAKE-UP LEVEL (A)
MAX17497A/B toc19
3.34
6.47
6.45
6.44
6.43
3.32
3.31
3.30
3.29
3.28
6.42
3.27
3.26
6.41
-40 -20
0
20
40
60
80
100 120
-40
-20
0
20
60
80
LXB AND INDUCTOR WAVEFORM
VOUTB vs. INB VOLTAGE
MAX17497A/B toc21
MAX17497A/B toc20
3.328
40
TEMPERATURE (°C)
TEMPERATURE (°C)
3.325
VOUTB VOLTAGE (V)
3 4
VOUTB vs. TEMPERATURE
INB WAKE-UP LEVEL vs. TEMPERATURE
6.48
2
0dBm
ILXB
0.5A/div
3.322
3.319
3.316
VLXB
5V/div
3.313
3.310
6
8
10
12
14
16
400ns/div
INB VOLTAGE (V)
Maxim Integrated
8
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
Typical Operating Characteristics (continued)
(VIN = +15V, VEN/UVLO = +2V, COMPF = open, CIN = 1FF, CVCC = 1FF, TA = TJ = -40NC to +125NC, unless otherwise noted. Typical
values are at TA = +25NC.)
LOAD STEP ON BUCK REGULATOR
(3.3V OUTPUT)
VOUTB vs. LOAD CURRENT
MAX17497A/B toc23
MAX17497A/B toc22
3.33
VOUTB VOLTAGE (V)
3.325
VOUTB
50mV/div
3.320
ILOAD
0.2A/div
3.315
3.310
0.1
0.2
0.3
0.4
0.5
1ms/div
0.6
LOAD CURRENT, IOUTB (A)
EFFICIENCY GRAPH vs. LOAD CURRENT
(FLYBACK CONVERTER)
BODE PLOT (BUCK REGULATOR)
MAX17497A/B toc24
100
MAX17497A/B toc25
0
90
EFFICIENCY (%)
80
PHASE
36°/div
6 7 891
2
VDC = 310V
60
50
40
30
GAIN
10dB/div
BW = 110kHz
PM = 57°
70
20
10
3 4 5 6 7 891
2
3 4
0
0
0dBm
0.2
0.4
0.6
0.8
1.0
1.2
1.4
LOAD CURRENT (A)
EFFICIENCY vs. LOAD CURRENT
(BUCK REGULATOR)
MAX17497A/B toc26
100
90
EFFICIENCY (%)
80
VINB = 15V
70
60
50
40
30
20
10
0
0
0.1
0.2
0.3
0.4
0.5
0.6
LOAD CURRENT (A)
Maxim Integrated
9
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
LXB
PGNDB
OUTB
TOP VIEW
INB
Pin Configuration
12
11
10
9
RESETN 13
PGNDF 14
MAX17497A
MAX17497B
LXF 15
EP
1
2
3
4
VCC
OVI
RLIMF
+
EN/UVLO
IN 16
8
SSF
7
COMPF
6
EAFN
5
SCOMPF
TQFN
Pin Description
PIN
NAME
1
EN/UVLO
2
VCC
Linear Regulator Output. Connect input bypass capacitor of at least 1FF from VCC to SGND as close
as possible to the IC.
3
OVI
Overvoltage Comparator Input. Connect a resistor-divider between the input supply (OVI) and SGND
to set the input overvoltage threshold.
4
RLIMF
Current-Limit Setting Pin. Connect a resistor between RLIMF and SGND to set the peak-current limit
for nonisolated flyback converter. Peak-current limit defaults to 500mA if unconnected.
5
SCOMPF
Slope Compensation Input Pin. Connect a resistor between SCOMPF and SGND to set slope comp
ramp. Connect to VCC for minimum slope comp. See the Programming the Slope Compensation for
the Flyback/Boost Converter (SCOMPF) section.
6
EAFN
Feedback/Inverting Input of the Error Amplifier for Nonisolated Flyback Converter. Connect to
midpoint of resistor-divider from the positive terminal of the output capacitor of the flyback/boost
converter to SGND.
7
COMPF
Error-Amplifier Output of Flyback/Boost Converter. Connect the frequency-compensation network
between COMPF and SGND. See Figure 9.
Maxim Integrated
FUNCTION
Enable/Undervoltage-Lockout Pin. Drive to > 1.23V to start the devices. To externally program the
UVLO threshold of the input supply, connect a resistor-divider between input supply EN/UVLO and
SGND.
10
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
Pin Description (continued)
PIN
NAME
FUNCTION
8
SSF
Soft-Start Pin for Flyback/Boost Converter. Connect a capacitor from SSF to SGND to set the
soft-start time interval.
9
OUTB
Feedback for Step-Down Regulator. Connects OUTB to the positive terminal of the step-down
regulator output capacitor.
10
PGNDB
Power Ground for Step-Down Regulator
11
LXB
External Inductor Connection for Step-Down Regulator. Connect to one end of the output inductor.
Connect the other end of output inductor to output capacitor.
12
INB
Internal Step-Down Regulator Input. Connect INB to either VOUTF, the output of flyback/boost
converter, or directly to the DC input source, as needed in the application. Bypass INB to PGNDB
with a 2.2FF minimum ceramic capacitor.
13
RESETN
Open-Drain Output. RESETN goes high when both the outputs are within 5% of their regulation point.
RESETN goes low when either of the outputs falls below 92% of their regulation value.
14
PGNDF
Power Ground for Flyback/Boost Converter
15
LXF
External Transformer/Inductor Connection for Flyback/Boost Converter
16
IN
Internal Linear Regulator Input. Connect IN to the input-voltage source. Bypass IN to PGNDF with
ceramic capacitor of at least 1FF.
—
EP
Exposed Pad. Internally connected to SGND. Connect EP to a large copper plane at SGND potential
to provide adequate thermal dissipation. Connect EP (SGND) to PGNDF at a single point.
Detailed Description
The MAX17497A is optimized for implementing a nonisolated offline flyback converter with output power of up to
30W and a 3.3V, 600mA power rail using the on-board
synchronous step-down regulator. The output voltage of
the flyback converter serves as the input supply voltage
to the on-board 3.3V integrated synchronous step-down
regulator. The outputs of the flyback converter and stepdown regulator are regulated with independent feedback
loops, thus providing two accurately controlled voltages
for the system. If needed, more semi-regulated outputs
can be generated using additional secondary windings
on the flyback converter transformer. The MAX17497B is
optimized for implementing a nonisolated flyback/boost
converter up to 15W and a 3.3V, 600mA synchronous
step-down regulator in low-voltage DC-DC applications
down to 4.5V DC. See the Figure 1 for more information.
Maxim Integrated
Input Voltage Range
The MAX17497A has different rising and falling UVLO
thresholds on the IN pin than those of the MAX17497B.
The thresholds for the MAX17497A are optimized for
implementing power-supply startup schemes typically
used for offline AC-DC power supplies. The MAX17497A
is therefore well suited for operation from the rectified DC bus in AC-DC power-supply applications typically encountered in electric metering and other lowpower industrial power-supply applications. As such,
the MAX17497A has no limitation on the maximum
input voltage as long as the external components are
rated suitably and the maximum operating voltages of
the MAX17497A are respected. The MAX17497A can
successfully be used in universal input rectified (85V to
265V AC) bus applications, rectified 3-phase DC bus
applications, and telecom (36V to 72V DC) applications.
11
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
The MAX17497B is intended for implementing a nonisolated flyback/boost converter with an on-board 60V rated
n-channel MOSFET. The IN pin of the MAX17497B has
a maximum operating voltage of 36V. The MAX17497B
implements rising and falling thresholds on the IN pin that
assume power-supply startup schemes, typical of lower
voltage DC-DC applications, down to an input voltage of
4.5V DC. Therefore, flyback/boost converters with a 4.5V
to 36V supply voltage range can be implemented with
the MAX17497B. See the Startup Operation section for
more details on power-supply startup schemes for both
devices. The on-board synchronous step-down regulator
is rated for a 16V (max) operating input voltage.
Linear Regulator (VCC)
The devices have an internal linear regulator powered
from the IN pin. The output of the linear regulator is connected to the VCC pin and should be decoupled with a
1FF capacitor to ground for stable operation. The VCC
regulator output supplies the operating current for the
devices. The maximum operating voltage of the IN pin
is 29V for the MAX17497A and 36V for the MAX17497B.
Configuring the Power Stage (LXF)
The devices use an internal nMOSFET to implement
internal current sensing for current-mode control and
overcurrent protection of the flyback/boost converter.
To facilitate this, the drain of the internal nMOSFET is
connected to the source of the external MOSFET in
the MAX17497A application. The gate of the external
MOSFET is connected to the IN pin. Ensure by design
that the IN pin voltage does not exceed the maximum
operating gate-voltage rating of the external MOSFET.
The external MOSFET gate-source voltage is controlled
by the switching action of the internal nMOSFET, while
also sensing the source current of the external MOSFET.
In the MAX17497B application, the LXF pin is directly
connected to either the flyback transformer primary winding or to the boost-converter inductor.
Maximum Duty Cycle
The MAX17497A/MAX17497B offer a maximum duty cycle
greater than 90%. Both devices can be used to implement both
flyback and boost converters involving large input-to-out-
Maxim Integrated
put voltage ratios in DC-DC applications. The on-board
synchronous step-down regulator has a maximum duty
cycle of 85% and is internally compensated for stable
operation.
RESETN Power-Good Signal
The devices include a RESETN signal that serves as a
power-good signal to the system. RESETN is an opendrain signal and requires a pullup resistor to the preferred supply voltage. The RESETN signal monitors both
the flyback/boost output and the synchronous step-down
regulator output, pulling high when both outputs are at
95% (typ) of their regulation values. The RESETN signal
pulls low when either of the outputs fall below 92% (typ)
of their regulation values.
Sequencing
The MAX17497A is typically configured such that the
output of the flyback converter serves as the input source
to the integrated synchronous step-down regulator.
Because the synchronous step-down regulator has a 6.5V
input UVLO threshold, the 3.3V output always comes up
after the output of the flyback converter. Figure 2 shows
the sequencing of the MAX17497A outputs configured
as described above. The sequencing for the devices is
identical when the MAX17497B is configured as either
a flyback or boost output generating the input supply
voltage for the integrated step-down regulator. The stepdown regulator can also operate from an independent 7V
to 16V DC supply. In this case, the step-down regulator
starts up when its INB pin voltage exceeds 7V, provided
that the EN/UVLO pin voltage is greater than 1.23V (typ).
Soft-Start
The devices implement soft-start operation for the flyback/
boost converter, as well as the synchronous step-down
regulator. A capacitor connected to the SSF pin programs
the soft-start period for the flyback/boost converter, while
the step-down regulator has a fixed internal digital softstart scheme. The step-down regulator includes soft-start
duration of 2ms. See the Programming the Soft-Start of the
Flyback/Boost Converter (SSF) section for more details
on selection of the SSF capacitor.
12
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
IN
33V CLAMP
(MAX17497A ONLY)
VCC
5V, 50mA
CHIPEN
HICCUP
LDO
REF
SSDONE
1.23V
POK
SSF
SSDONEF
SSDONE
1.17V
MAX17497A
MAX17497B
10µA
EN/UVLO
OSC
VSUM
1.23V
OVI
VCS
VSCOMPF
CHIPEN
LXF
VCS
RUNAWAY
HICCUP
CLK
1.23V
SSDONEF
CONTROL
LOGIC AND
DRIVER
PEAK
VSUM
1 RUNAWAY
PGNDF
PWK
COMPF
10µA
RESTEIN
RLIMFINT
RLIMF
1.23V
EAFN
CHIPEN
SSDONEB
250mV
ISLOPE
1 RUNAWAY
VCSB
VCSBSUM
VSS
VOUTB
INB
10µA
FIX_SLOPE
SLOPE
COMPENSATION
SCOMF
VSCOMPF
CHIPEN
VCSB
INB
HICCUP
1.23V
RUNAWAY
EAFN
PEAK
1V
CONTROL
LOGIC AND
DRIVER
LXB
VCSBSUM
1.23V
PWM
PGNDB
COMF
CLK
VOUTB
COMP
INB
CLK
EN_BUCK
POK
SSDONEB
CHIPEN
STEP-DOWN
SOFT-START
1.23V
Figure 1. MAX17497A/MAX17497B Block Diagram
Maxim Integrated
13
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
EN/UVLO
95%
6.5V
VOUTF
tSSF
95%
VOUTB
92%
tSSB
4ms
RESETN
tRESETN
Figure 2. Sequencing of MAX17497A/MAX17497B Output Voltage Rails
Spread-Spectrum Factory Option
For EMI-sensitive applications, a spread-spectrumenabled version of the device can be requested from
the factory. The frequency-dithering feature modulates
the switching frequency by Q10% at a rate of 1/16 the
switching frequency. This spread-spectrum-modulation
technique spreads the energy of switching-frequency
harmonics over a wider band while reducing their peaks,
helping to meet stringent EMI goals.
Applications Information
Startup Voltage and Input OvervoltageProtection Setting (EN/UVLO, OVI)
The devices’ EN/UVLO pin serves as an enable/disable
input, as well as an accurate programmable input UVLO
pin. The devices do not commence startup operations
unless the EN/UVLO pin voltage exceeds 1.23V (typ).
The devices turn off if the EN/UVLO pin voltage falls
below 1.17V (typ). A resistor-divider from the input DC
bus to ground can be used to divide down and apply a
fraction of the input DC voltage (VDC) to the EN/UVLO
pin. The values of the resistor-divider can be selected
such that the EN/UVLO pin voltage exceeds the 1.23V
(typ) turn-on threshold at the desired input DC bus voltage. The same resistor-divider can be modified with an
Maxim Integrated
additional resistor (ROVI) to implement input overvoltage
protection in addition to the EN/UVLO functionality, as
shown in Figure 3. When voltage at the OVI pin exceeds
1.23V (typ), the devices stop switching and resume
switching operations only if voltage at the OVI pin falls
below 1.17V (typ). For given values of startup DC input
voltage (VSTART), and input overvoltage-protection voltage (VOVI), the resistor values for the divider can be calculated as follows, assuming a 24.9kI resistor for ROVI:
 V

R EN= R OVI ×  OVI − 1 kΩ
 VSTART 
where ROVI is in kI and VSTART and VOVI are in volts.
V

= R OVI + R EN ×  START − 1 kΩ
R SUM
 1.23

where REN and ROVI are in kI and VSTART is in volts.
RSUM may need to be implemented as equal multiple resistors
in series (RDC1, RDC2, RDC3) such that voltage across each
resistor is limited to its maximum operating voltage.
=
R
DC1 R=
DC2 R=
DC3
R SUM
kΩ
3
14
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
VDC
VDC
VOUTF
D1
VDC
RDC1
RSUM
COUTF
RIN1
RDC2
RSTART
RIN2
RDC3
VOUTF
EN/UVLO
MAX17497A
MAX17497B
REN
RIN3
MAX17497A
D2
IN
OVI
CSTART
ROVI
Figure 3. Programming EN/UVLO and OVI
Startup Operation
The MAX17497A is optimized for implementing offline
flyback converters. A cost-effective RC startup circuit
is used in offline applications. In this startup method,
when the input DC voltage is applied, the startup
resistor (RSTART) charges the startup capacitor (CSTART),
causing the voltage at the IN pin to increase towards the
rising IN UVLO threshold (20V typ). During this time, the
MAX17497A draws a low startup current of 20FA (typ)
through RSTART. When the voltage at IN reaches the
rising IN UVLO threshold, the MAX17497A commences
switching operations and drives the internal nMOSFET
whose drain is connected to the LXF pin. In this condition, the MAX17497A draws 2.5mA current in from
CSTART, in addition to the current required to switch the
gate of the external nMOSFET (Q1). Since this current
cannot be supported by the current through RSTART,
the voltage on CSTART starts to drop. When suitably
configured as show in Figure 4, the external nMOSFET
is switched by the LXF pin and the flyback converter
generates an output voltage (VOUTF) bootstrapped to
the IN pin through the diode (D2). If VOUTF exceeds
the sum of 6V and the drop across D2 before the
voltage on CSTART falls below 5V, then the IN voltage is sustained by VOUTF, allowing the MAX17497A
to continue operating with energy from VOUTF. The
large hysteresis (15V typ) of the MAX17497A allows
for a small startup capacitor (CSTART). The low startup
Maxim Integrated
LXF
LDO
VCC
CVCC
Figure 4. MAX17497A RC-Based Startup Circuit
current (20FA typ) allows the use of a large startup resistor (RSTART), thus reducing power dissipation at higher
DC bus voltages. RSTART may need to be implemented
as equal, multiple resistors in series (RIN1, RIN2 and
RIN3) to share the applied high DC voltage in offline
applications, such that the voltage across each resistor
is limited to the maximum continuous operating-voltage
rating. RSTART and CSTART can be calculated as:

 Q GATE × fsw  t SSF
C START =
µF
IIN + 
 ×
10 6

 10

where IIN is the supply current drawn at the IN pin in mA,
QGATE is the gate charge of the external MOSFET used in
nC, fSW is the switching frequency of the converter in Hz,
and tSSF is the soft-start time programmed for the flyback
converter in ms (see the Programming the Soft-Start of the
Flyback/Boost Converter (SSF) section).
R START
=
(VSTART − 10) × 50 kΩ
1 + C START 
where CSTART is the startup capacitor in FF.
For designs that cannot accept power dissipation in
the startup resistors at high DC input voltages in offline
applications, the startup circuit can be set up with a
current source instead of a startup resistor, as shown
in Figure 5.
15
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
The startup capacitor (CSTART) can be calculated as
follows:
VDC

 Q GATE × fsw  t SSF
C START =
µF
IIN + 
 ×
10 6

 10

where IIN is the supply current drawn at the IN pin in mA,
QGATE is the gate charge of the external MOSFET used
in nC, fSW is the switching frequency of the converter in
Hz, and tSSF is the soft-start time programmed for the
flyback converter in ms.
RIN1
VDC
RSTART
RIN2
COUTF
RIN3
Resistors RSTART and RISRC can be calculated as:
M1
VSTART
=
R START
MΩ
10
VBEQ1
=
RISRC
MΩ
70
The IN UVLO rising threshold of the MAX17497B is
set to 3.9V with hysteresis of 200mV, optimized for
low-voltage DC-DC applications down to 4.5V. For
applications where the input DC voltage is low enough
(e.g., 4.5V to 5.5V DC) so the power loss incurred to
supply the operating current of the MAX17497B can be
tolerated, the IN pin is directly connected to the DC input
(Figure 6). For higher DC input voltages (e.g., 16V to 32V
DC), a startup circuit (Figure 7) can be used to minimize
power dissipation in the startup circuit. In this startup scheme, the transistor (Q1) supplies the switching
current until a bias winding NB comes up. The resistor
(RZ) can be calculated as:
RZ =
9 × (VINMIN − 6.3) kΩ
where VINMIN is the minimum input DC voltage.
Programming the Soft-Start of the
Flyback/Boost Converter (SSF)
VOUTF
D1
IN
Q1
VOUTF
D2
MAX17497A
RISRC
IN
CSTART
LXF
LDO
VCC
PGNDF
CVCC
Figure 5. MAX17497A Current-Source-Based Startup Circuit
VDC
VOUTF
D1
IN
IN
LDO
VCC
CIN
CVCC
COUTF
MAX17497B
LXF
Np
Ns
The devices’ soft-start period of the flyback/boost converter can be programmed by selecting the value of
the capacitor connected from the SSF pin to GND. The
capacitor (CSSF) can be calculated as:
C SSF
= 8.13 × t SSF nF
where tSSF is expressed in ms.
Maxim Integrated
Figure 6. MAX17497B Typical Startup Circuit with IN
Connected Directly to DC Input
16
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
Programming the Output Voltage of
the Flyback/Boost Converter (EAFN)
Set the output voltage of the flyback/boost converter by
selecting the correct values for the resistor-divider connected from the flyback/boost output to ground (VOUTF)
with the midpoint of the divider connected to the EAFN
pin (Figure 8). With RB selected in the range of 20kI to
50kI, RU can be calculated as:
V

RU = RB ×  OUTF − 1 kΩ
 1.22

where RB is in kI.
VDC
VOUTF
D2
RZ
ZD1
6.3V
NB
MAX17497B
IN
IN
where IPK is expressed in amperes.
COUTF
LDO
CIN
LXF
The devices include a robust overcurrent-protection
scheme that protects them during overload and shortcircuit conditions. For the flyback/boost converter, the
devices include a cycle-by-cycle peak current limit that
turns off the driver whenever the current into the LXF pin
exceeds an internal limit programmed by the resistor
connected from the RLIMF pin to ground. The devices
include a runaway current limit that protects them during
short-circuit conditions. One occurrence of the runaway
current limit trigger a hiccup mode, protecting the converter by immediately suspending switching for a period
of time (32ms). This allows the overload current to decay
due to power loss in the converter resistances, load, and
the output diode of the flyback/boost converter before
soft-start is attempted again. The RLIMF resistor for a
desired current limit (IPK) can be calculated as:
R LIMF =50 × IPK kΩ
D1
Q1
Programming the Current Limit of the
Flyback/Boost Converter (RLIMF)
Np
Ns
VCC
For a given peak-current-limit setting, the runaway
current limit is typically 20% higher. The runaway currentlimit-triggered hiccup operation is always enabled, even
during soft-start operation.
Programming the Slope Compensation for
the Flyback/Boost Converter (SCOMPF)
CVCC
Figure 7. MAX17497B Typical Startup Circuit with Bias Winding
to Turn Off Q1 and Reduce Power Dissipation
VOUTF
RU
EAFN
MAX17497A
MAX17497B
RB
When both devices operate at maximum duty cycle of
49%, in theory they do not require slope compensation
to prevent subharmonic instability that occurs naturally
in continuous peak-current-mode controlled converters
operating at duty cycles greater than 50%. In practice,
the MAX17497A requires a minimum amount of slope
compensation to provide stable, jitter-free operation. The
MAX17497A allows the user to program this default value
of slope compensation simply by connecting the RLIMF
pin to VCC. It is recommended that discontinuous-mode
designs also use this minimum amount of slope compensation to provide noise immunity and jitter-free operation.
Figure 8. Programming the Output Voltage of the Flyback/Boost
Converter
Maxim Integrated
17
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
The MAX17497A flyback/boost converter can be
designed to operate in discontinuous mode or to enter
into continuous-conduction mode at a specific heavyload condition for a given DC input voltage. In continuous-conduction mode, the flyback/boost converter needs
slope compensation to avoid subharmonic instability that
occurs naturally over all specified load and line conditions in peak-current-mode-controlled converters operating at duty cycles greater than 50%. A minimum amount
of slope signal is added to the sensed current signal
even for converters operating below 50% duty cycles
to provide stable, jitter-free operation. The SCOMPF pin
allows the user to program the necessary slope compensation by setting the value of the RSCOMPF resistor
connected from the SCOMPF pin to ground:
The flyback/boost converter can be used to implement
the following converters and operating modes:
• Nonisolated flyback converter in discontinuousconduction mode (DCM flyback)
• Nonisolated flyback converter in continuous-conduction mode (CCM flyback)
• Boost converter in discontinuous-conduction mode
(DCM boost)
• Boost converter in continuous-conduction mode
(CCM boost)
Calculations for loop-compensation values (RZ, CZ, and
CP) for these converter types, and design procedures for
power-stage components, are detailed in the following
sections.
R SCOMPF
= 0.5 S E kΩ
where the slope (SE) is expressed in millivolts per microsecond.
Step-Down Overcurrent Protection
The devices’ step-down regulator includes a robust
overcurrent-protection scheme that protects them during overload and short-circuit conditions. A runaway
current limit on the high-side switch current at 1A (typ)
protects the device under short-circuit conditions. One
occurrence of the runaway current limit trigger a hiccup
mode to protect the converter by immediately suspending switching for 32ms. This allows the overload current
to decay, due to power loss in the converter resistances,
and load before soft-start is attempted again.
Error Amplifier, Loop Compensation,
and Power-Stage Design of the
Flyback/Boost Converter
The devices’ flyback/boost converter requires that proper loop compensation be applied to the error-amplifier
output to achieve stable operation. The goal of the compensator design is to achieve the desired closed-loop
bandwidth and sufficient phase margin at the crossover
frequency of the open-loop gain-transfer function of the
converter. The error amplifier included in the devices is a
transconductance amplifier. The compensation network
used to apply the necessary loop compensation is shown
in Figure 9.
Maxim Integrated
DCM Flyback
Primary Inductance Selection
In a DCM flyback converter, the energy stored in the
primary inductance of the flyback transformer is ideally
delivered entirely to the output. The maximum primaryinductance value for which the converter remains in
discontinuous mode at all operating conditions can be
calculated as:
L PRIMAX ≤
(VINMIN × D MAX ) 2 × 0.4
(VOUTF + VD ) × IOUTF × fSW
where DMAX is 0.35 for the MAX17497A and 0.7 for the
MAX17497B, VD is the forward-voltage drop of the output rectifier diode on the secondary side, and fSW is the
switching frequency of the power converter. Choose the
primary inductance value to be less than LPRIMAX.
COMPF
RZ
CP
MAX17497A
MAX17497B
CZ
Figure 9. Programming the Output Voltage of the Flyback/Boost
Converter
18
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
Duty-Cycle Calculation
The accurate value of the duty cycle (DNEW) for the
selected primary inductance LPRI can be calculated
using the following equation:
D NEW =
2.5 × L PRI × (VOUTF + VD ) × IOUTF × fSW
VINMIN
Turns Ratio Calculation (Ns/Np)
Transformer turns ratio (K = Ns/Np) can be calculated as:
+ VD ) × (1 − D NEW )
(V
K = OUTF
VINMIN × D NEW
Peak/RMS Current Calculation
RMS current values in the primary and secondary are
needed by the transformer manufacturer to design the
wire diameter for the different windings. Peak current
calculations are useful in setting the current limit. Use the
following equations to calculate the primary and secondary peak and RMS currents:
Maximum primary peak current:
V
× D NEW
IPRIPEAK = INMIN
L PRI × fSW
Maximum primary RMS current:
I=
PRIRMS IPRIPEAK ×
D NEW
3
Maximum secondary RMS current:
I
I SECPEAK = PRIPEAK
K
Maximum secondary peak current:
I SECRMS =
2 × IOUT × IPRIPEAK
3× K
For current-limit setting, the peak current can be calculated as:
=
ILIMF IPRIPEAK × 1.2
Primary Snubber Selection
Ideally, the external nMOSFET experiences a drainsource-voltage stress equal to the sum of the input voltage and the reflected voltage across the primary winding during the off period of the nMOSFET. In practice,
Maxim Integrated
parasitic inductances and capacitors in the circuit, such
as leakage inductance of the flyback transformer, cause
voltage overshoot and ringing. Snubber circuits are used
to limit the voltage overshoots to safe levels within the
voltage rating of the external nMOSFET. The snubber
capacitor can be calculated using the following equation:
C SNUB =
2 × L LK × IPRIPEAK 2 × K 2
VOUTF 2
where LLK is the leakage inductance obtained from the
transformer specifications (usually 1% to 2% of the primary inductance).
The power dissipated in the snubber resistor is calculated using the following equation:
PSNUB = 0.833 × L LK × IPRIPEAK 2 × fSW
The snubber resistor can be calculated based on the
following equation:
R SNUB =
6.25 × VOUTF 2
PSNUB × K 2
The voltage rating of the snubber diode is:
V


= VINMAX +  2.5 × OUTF 
VDSNUB
K


Output-Capacitor Selection
X7R ceramic output capacitors are preferred in industrial
applications due to their stability over temperature. The
output capacitor is usually sized to support a step load
of 50% of the maximum output current in the application
so that the output-voltage deviation is contained to 3% of
the output-voltage change. The output capacitance can
be calculated as:
I
×t
C OUTF = STEP RESPONSE
∆VOUTF
t RESPONSE ≅ (
0.33
1
+
)
fC
fSW
where ISTEP is the load step, tRESPONSE is the response
time of the controller, DVOUTF is the allowable output voltage deviation, and fC is the target closed-loop crossover
frequency. fC is chosen to be 1/10 of the switching frequency (fSW). For the flyback converter, the output
capacitor supplies the load current when the main switch
19
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
is on, and the output-voltage ripple is therefore a function
of load current and duty cycle. Use the following equation to calculate the output-capacitor ripple:
2
IOUT × IPRIPEAK − (K × IOUTF )
∆VCOUTF =
2 × IPRIMPEAK 2 × fSW × C OUTF
where IOUTF is the load current and DNEW is the duty
cycle at minimum input voltage.
Input-Capacitor Selection
The MAX17497A is optimized for implementing offline
AC-DC converters. In such applications, the input capacitor must be selected based either on the ripple due to
the rectified line voltage or on hold-up time requirements.
Hold-up time can be defined as the time period over
which the power supply should regulate its output voltage from the instant the AC power fails. The MAX17497B
is useful for implementing low-voltage DC-DC applications where the switching-frequency ripple must be
used to calculate the input capacitor. In both cases, the
capacitor must be sized to meet RMS current requirements for reliable operation.
Capacitor Selection Based on Switching Ripple
(MAX17497B): For DC-DC applications, X7R ceramic
capacitors are recommended due to their stability over
the operating temperature range. The ESR and ESL of a
ceramic capacitor are relatively low, so the ripple voltage
is dominated by the capacitive component. For the flyback converter, the input capacitor supplies the current
when the main switch is on. The following equation calculates the input capacitor for a specified peak-to-peak
input switching-ripple voltage (VIN_RIP):
CIN =
D NEW × IPRIPEAK 1 − (0.5 × D NEW )
2
2 × fSW × VIN_RIP
Capacitor Selection Based on Rectified Line Voltage
Ripple (MAX17497A): For the flyback converter, the
input capacitor supplies the input current when the diode
rectifier is off:
CIN =
0.45 × PLOAD
η × VINPK
2
where PLOAD is the rated output power, VINPK is the
peak voltage at minimum input, and η is the efficiency at
minimum input at maximum load.
Maxim Integrated
Capacitor Selection Based on Hold-Up Time
Requirements (MAX17497A): For a given output power
(PHOLDUP) that needs to be delivered during hold-up
time (tHOLDUP), DC bus voltage at which the AC supply
fails (VINFAIL), and the minimum DC bus voltage at which
the converter can regulate the output voltages (VINMIN),
the input capacitor (CIN) is estimated as:
CIN =
3 × PHOLDUP × t HOLDUP
(VINFAIL 2 − VINMIN 2 )
The input capacitor RMS current can be calculated as
follows:
2.7 × PLOAD
IINCRMS =
η × VINPK
External MOSFET Selection
MOSFET selection criteria includes the maximum drain
voltage, peak/RMS current in the primary, and the
maximum allowable power dissipation of the package
without exceeding the junction temperature limits. The
voltage seen by the MOSFET drain is the sum of the input
voltage, the reflected secondary voltage on the transformer primary, and the leakage inductance spike. The
MOSFET’s absolute maximum VDS rating must be higher
than the worst-case drain voltage:
 V

+ VD 
× 2.5
VDSMAX =
VINMAX +  OUTF

K



The drain-current rating of the external MOSFET is
selected to be greater than the worst-case peak currentlimit setting.
Secondary Diode Selection
Secondary diode-selection criteria includes the maximum reverse voltage, average current in the secondary,
reverse recovery time, junction capacitance, and the
maximum allowable power dissipation of the package.
The voltage stress on the diode is the sum of the output
voltage and the reflected primary voltage.
The maximum operating reverse-voltage rating must be
higher than the worst-case reverse voltage:
VSECDIODE= 1.25 × (K × VINMAX + VOUTF )
The current rating of the secondary diode should be
selected such that the power loss in the diode (given
as the product of forward-voltage drop and the average
20
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
diode current) should be low enough to ensure that the
junction temperature is within limits. This necessitates
the diode-current rating be in the order of 2 x IOUTF to
3x IOUTF. Select fast-recovery diodes with a recovery
time less than 50ns, or Schottky diodes with low junction
capacitance.
Error-Amplifier Compensation Design
The loop-compensation values are calculated as:
R
=
Z 450 ×
2
  0.1f
SW   × V
1 + 

OUTF × I OUTF
  fP  


2 × L PRI × fSW
fP =
IOUTF
π × VOUTF × C OUTF
CZ =
1
π × R Z × fP
1
CP =
π × R Z × fSW
The devices’ switching frequency (fSW) can be obtained from the Electrical Characteristics section.
In a typical application, the integrated step-down
regulator is fed off the flyback converter’s output. The
step-down regulator poses negative input impedance
or constant input power behavior. Due to this behavior,
the loop bandwidth measured for the flyback converter
would be smaller than the design bandwidth.
CCM Flyback
Transformer Turns Ratio Calculation (K = Ns/Np)
The transformer turns ratio can be calculated using the
following equation:
K=
(VOUT + VD ) × (1 − D MAX )
VINMIN × D MAX
where DMAX is the duty cycle assumed at minimum input
(0.35 for the MAX17497A and 0.7 for the MAX17497B).
Primary Inductance Calculation
Calculate the primary inductance based on the ripple:
L PRI =
(VOUTF + VD ) × (1 − D NOM) 2
2 × IOUTF × β × fSW × K 2
where DNOM, the nominal duty cycle at nominal operating DC input voltage (VINNOM), is given as:
Maxim Integrated
D NOM =
(VOUT + VD )
VINNOM × K + (VOUT + VD )
The output current, down to which the flyback converter
should operate in CCM, is determined by selection of
the fraction A in the above primary inductance formula.
For example, A should be selected as 0.15 so that the
converter operates in CCM down to 15% of the maximum output-load current. Since the ripple in the primary
current waveform is a function of duty cycle, and is
maximum-at-maximum DC input voltage, the maximum
(worst-case) load current, down to which the converter
operates in CCM, occurs at maximum operating DC input
voltage. VD is the forward drop of the selected output
diode at maximum output current.
Peak and RMS Current Calculation
RMS current values in the primary and secondary are
needed by the transformer manufacturer to design the
wire diameter for the different windings. Peak-current
calculations are useful in setting the current limit. Use the
following equations to calculate the primary and secondary peak and RMS currents:
Maximum primary peak current:
I
× K   VINMIN × D MAX 
IPRIPEAK  OUTF
=

+
1
D
−
MAX   2 × L PRI × fSW 

Maximum primary RMS current:
=
IPRIRMS
 ∆I 2 
IPRIPEAK 2 +  PRI  − (IPRIPEAK × ∆IPRI)
 3 


× D MAX
2
where DIPRI is the ripple current in the primary current
waveform, and is given by:
 VINMIN × D MAX 
∆IPRI =


 L PRI × fSW 
Maximum secondary peak current:
I
I SECPEAK = PRIPEAK
K
Maximum secondary RMS current:
21
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
=
I SECRMS
2
 ∆I
I SECPEAK 2 +  SEC  − (I SECPEAK × ∆I SEC )


3


× 1 − D MAX 2
where DISEC is the ripple current in the secondary current
waveform, and is given by:
 VINMIN × D MAX 
∆I SEC =


 L PRI × fSW × K 
Current-limit setting the peak current can be calculated
as follows:
=
ILIMF IPRIPEAK × 1.2
Primary RCD Snubber Selection
The design procedure for RCD snubber selection is identical to that outlined in the DCM Flyback section.
Output-Capacitor Selection
X7R ceramic output capacitors are preferred in industrial
applications due to their stability over temperature. The
output capacitor is usually sized to support a step load
of 50% of the maximum output current in the application,
such that the output-voltage deviation is contained to 3%
of the output-voltage change. The output capacitance
can be calculated as:
I
×t
C OUTF = STEP RESPONSE
∆VOUTF
t RESPONSE ≅ (
0.33
1
+
)
fC
fSW
where ISTEP is the load step, tRESPONSE is the response
time of the controller, DVOUTF is the allowable output
voltage deviation, and fC is the target closed-loop crossover frequency. fC is chosen to be less than 1/5 of the
worst-case (lowest) RHP zero frequency (fRHP). The right
half-plane zero frequency is calculated as:
fZRHP =
(1 − D MAX ) 2 × VOUTF
2 × π × D MAX × L PRI × IOUTF × K 2
For the CCM flyback converter, the output capacitor
supplies the load current when the main switch is on,
and therefore the output-voltage ripple is a function of
load current and duty cycle. Use the following equation
to estimate the output-voltage ripple:
Maxim Integrated
IOUTF × D MAX
∆VCOUTF =
fSW × C OUTF
Input-Capacitor Selection
The design procedure for input capacitor selection is
identical to that outlined in the DCM Flyback section.
External MOSFET Selection
The design procedure for external MOSFET selection is
identical to that outlined in the DCM Flyback section.
Secondary Diode Selection
The design procedure for secondary diode selection is
identical to that outlined in the DCM Flyback section.
Error-Amplifier Compensation Design
In the CCM flyback converter, the primary inductance
and the equivalent load resistance introduces a right
half-plane zero at the following frequency:
fZRHP =
(1 − D MAX ) 2 × VOUTF
2 × π × D MAX × L PRI × IOUTF × K 2
The loop-compensation values are calculated as:
RZ
=
f

200 × IOUTF
× K 1 +  RHP 
(1 − D MAX )
 5 × fP 
2
× (1 + D MAX )
where fP, the pole due to output capacitor and load, is
given by:
fP =
(1 + D MAX ) × IOUTF
2 × π × C OUTF × VOUTF
The above selection sets the loop-gain crossover frequency (fC, where the loop gain equals 1) equal to 1/5
the right half-plane zero frequency:
f
fC ≤ ZRHP
5
With the control-loop zero placed at the load pole frequency:
1
2π × R Z × fP
With the high-frequency pole placed at 1/2 the switching
frequency:
CZ =
CP =
1
π × R Z × fSW
22
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
DCM Boost
In a DCM boost converter, the inductor current returns to
zero in every switching cycle. Energy stored during the
on-time of the main switch is delivered entirely to the load
in each switching cycle.
Inductance Selection
The design procedure starts with calculating the boost
converter’s input inductor, such that it operates in DCM
at all operating line and load conditions. The critical
inductance required to maintain DCM operation is calculated as:
2
(V
 OUTF − VINMIN ) × VINMIN  × 0.4
L IN ≤
IOUTF × VOUTF 2 × fSW
where VINMIN is the minimum input voltage.
Peak/RMS Current Calculation
To set the current limit, the peak current in the inductor
can be calculated as:
ILIMF
= IPK × 1.2
voltage deviation, and fC is the target closed-loop crossover frequency. fC is chosen to be 1/10 the switching
frequency (fSW). For the boost converter, the output
capacitor supplies the load current when the main switch
is on, and therefore the output-voltage ripple is a function
of duty cycle and load current. Use the following equation to calculate the output-capacitor ripple:
IOUTF × L IN × IPK
∆VCOUTF =
VINMIN × C OUTF
Input-Capacitor Selection
The value of the required input capacitor can be calculated based on the ripple allowed on the input DC bus.
The size of the input capacitor should be based on the
RMS value of the AC current handled by it. The calculations are as:


3.75 × IOUTF
CINF = 

 VINMIN × fSWMIN × (1 − D MAX ) 
The capacitor RMS can be calculated as:
where IPK is given by:
2 × (VOUTF − VINMIN) × IOUTF 
IPK = 

L INMIN × fSWMIN


LINMIN is the minimum value of the input inductor, taking
into account tolerance and saturation effects. fSWMIN is
the minimum switching frequency for the MAX17497B
from the Electrical Characteristics section.
Output-Capacitor Selection
X7R ceramic output capacitors are preferred in industrial
applications due to their stability over temperature. The
output capacitor is usually sized to support a step load
of 50% of the maximum output current in the application,
such that the output-voltage deviation is contained to 3%
of the output-voltage change. The output capacitance
can be calculated as:
I
×t
C OUT = STEP RESPONSE
∆VOUTF
t RESPONSE ≅ (
0.33
1
+
)
fC
fSW
I CIN_RMS =
IPK
2× 3
Error-Amplifier Compensation Design
The DC gain of the power stage is given as:
2 × (VOUTF − VINMIN) × fSW × VOUTF 2 × L IN
(2VOUTF − VINMIN) 2 × IOUTF
G DC =
The loop-compensation values for the error amplifier can
be calculated as:
fP =
(2 × VOUTF − VINMIN) × IOUTF
2π (VOUTF − VINMIN ) × VOUTF × C OUTF
where VINMIN is the minimum operating input voltage
and IOUTF is the maximum load current.
2
=
RZ
 0.1× fSW 
230 × VOUTF
 ms 
× 1+ 
 × 1 +

GDC
f
 mp 
P


where ms = default slope compensation and mp =
VINMIN/L x 0.5.
where ISTEP is the load step, tRESPONSE is the response
time of the controller, DVOUTF is the allowable outputMaxim Integrated
23
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
CZ =
CP =
1
2π × fP × R Z
1
π × fSW × R Z
Slope Compensation
In theory, the DCM boost converter does not require
slope compensation for stable operation. In practice, the
converter needs a minimum amount of slope for good
noise immunity at very light loads. The minimum slope
is set for the devices by connecting the SCOMPF pin to
the VCC pin.
Output Diode Selection
The voltage rating of the output diode for the boost
converter ideally equals the output voltage of the boost
converter. In practice, parasitic inductances and capacitances in the circuit interact to produce voltage overshoot during the turn-off transition of the diode that
occurs when the main switch turns on. The diode rating
should therefore be selected with the necessary margin
to accommodate this extra voltage stress. A voltage rating of 1.3 x VOUTF provides the necessary design margin
in most cases.
The current rating of the output diode should be selected
such that the power loss in the diode (given as the
product of forward-voltage drop and the average diode
current) should be low enough to ensure that the junction
temperature is within limits. This necessitates the diode
current rating to be in the order of 2 x IOUTF to 3 x IOUTF.
Select fast-recovery diodes with a recovery time less than
50ns, or Schottky diodes with low junction capacitance.
current into LXF is useful in estimating the conduction
loss in the internal nMOSFET and is given as:
ILXF_RMS =
IPK 3 × L INS × fSW
3 × VINMIN
where IPK is the peak current calculated at the lowest
operating input voltage (VINMIN).
CCM Boost
In a CCM boost converter, the inductor current does
not return to zero during a switching cycle. Since the
MAX17497B implements a nonsynchronous boost converter, the inductor current enters DCM operation at load
currents below a critical value, equal to 1/2 the peak-topeak ripple in the inductor current.
Inductor Selection
The design procedure starts with calculating the boost
converter’s input inductor at nominal input voltage for a
ripple in the inductor current, equal to 30% of the maximum input current:
V × D × (1 − D)
L IN = IN
0.3 × IOUTF × fSW
where D is the duty cycle calculated as:
V
+ VD − VIN
D = OUTF
VOUTF + VD
VD is the voltage drop across the output diode of the
boost converter at maximum output current.
Peak/RMS Current Calculation
To set the current limit, the peak current in the inductor
and internal nMOSFET can be calculated as:
V
× D MAX × (1 − D MAX )
IOUTF 
=
IPK  OUTF
+
 × 1.2
Internal MOSFET RMS Current Calculation
L
f
(1
D MAX ) 
×
−
IN
SW

The voltage stress on the internal MOSFET, whose drain
for D MAX < 0.5
is connected to LXF, ideally equals the sum of the output voltage and the forward drop of the output diode.
In practice, voltage overshoot and ringing occur due
0.25 × VOUTF
IOUTF 
+
IPK= 
to action of circuit parasitic elements during the turn-off
 × 1.2 for D MAX ≥ 0.5
(1 − D MAX ) 
 L IN × fSW
transition. The maximum rating of the internal nMOSFET
of the devices is 65V, making it possible to design boost
DMAX, the maximum duty cycle, is obtained by substitutconverters with output voltages up to 48V, with sufficient
ing the minimum input operating voltage (VINMIN) in the
margin for voltage overshoot and ringing. The RMS
equation above for duty cycle. LINMIN is the minimum
Maxim Integrated
24
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
value of the input inductor taking into account tolerance
where:
and saturation effects. fSWMIN is the minimum switching frequency for the MAX17497B from the Electrical
V
× D MAX × (1 − D MAX ) 
=
∆ILIN  OUTF
 for D MAX < 0.5
Characteristics section.
L IN × fSW


Output-Capacitor Selection
0.25 × V

X7R ceramic output capacitors are preferred in industrial
OUTF  for D
∆ILIN 
MAX ≥ 0.5
applications due to their stability over temperature. The =
 L IN × fSW 

output capacitor is usually sized to support a step load
of 50% of the maximum output current in the application,
Error-Amplifier Compensation Design
such that the output-voltage deviation is contained to 3%
The loop-compensation values for the error amplifier can
of the output-voltage change. The output capacitance
now be calculated as:
can be calculated as:
I
×t
C OUTF = STEP RESPONSE
∆VOUTF
t RESPONSE ≅ (
0.33
1
+
)
fC
fSW
where ISTEP is the load step, tRESPONSE is the response
time of the controller, DVOUTF is the allowable outputvoltage deviation, and fC is the target closed-loop
crossover frequency. fC is chosen as 1/10 the switching frequency (fSW). For the boost converter, the output
capacitor supplies the load current when the main switch
is on, and therefore the output-voltage ripple is a function
of duty cycle and load current. Use the following equation to calculate the output-capacitor ripple:
IOUTF × D MAX
∆VCOUTF =
C OUTF × fSW
Input-Capacitor Selection
The input ceramic capacitor value required can be
calculated based on the ripple allowed on the input DC
bus. The input capacitor should be sized based on the
RMS value of the AC current handled by it. The calculations are as:
RZ =
90 × VOUTF 2 × C OUTF × (1 − D MAX )
IOUTF × L IN
where DMAX is the duty cycle at the lowest operating input
voltage and IOUTF_MAX is the maximum load current:
V
× C OUTF
C Z = OUTF
2 × IOUTF × R Z
CP =
1
π × fSW × R Z
Slope-Compensation Ramp
The slope required to stabilize the converter at duty
cycles greater than 50% can be calculated as:
SE =
0.41 × (VOUTF − VINMIN)
V per µs
L IN
where LIN is in FH.
Output Diode Selection
The design procedure for output diode selection is identical to that outlined in the DCM Boost section.


3.75 × IOUTF
CINF = 

 VINMIN × fSW × (1 − D MAX ) 
The input-capacitor RMS current can be calculated as:
∆I
I CIN_RMS = LIN
2× 3
Maxim Integrated
25
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
Internal MOSFET RMS Current Calculation
The voltage stress on the internal MOSFET, whose drain
is connected to LXF, ideally equals the sum of the output
voltage and the forward drop of the output diode. In practice, voltage overshoot and ringing occur due to action
of circuit parasitic elements during the turn-off transition.
The devices’ maximum rating of the internal nMOSFET
is 65V, making it possible to design boost converters
with output voltages up to 48V, with sufficient margin for
voltage overshoot and ringing. The RMS current into LXF
is useful in estimating the conduction loss in the internal
nMOSFET and is given as:
I
× D MAX
ILXF_RMS = OUTF
(1 − D MAX )
where DMAX is the duty cycle at the lowest operating
input voltage and IOUTF is the maximum load current.
Thermal Considerations
It should be ensured that the junction temperature of the
devices does not exceed +125NC under the operating
conditions specified for the power supply. The power dissipated in the devices to operate can be calculated using
the following equation:
P=
IN VIN × IIN
where VIN is the voltage applied at the IN pin and IIN is
operating supply current.
The internal nMOSFET experiences conduction loss and
transition loss when switching between on and off states.
These losses are calculated as:
PCONDUCTION
= ILXF_RMS
2 ×R
DSON_LXF
PTRANSITION = 0.5 × VINMAX × IPK × (t R + t F ) × fSW
where tR and tF are the rise and fall times of the internal
nMOSFET in CCM operation. In DCM operation, because
the switch current starts from zero only, tF exists and the
transition loss equation changes to:
PTRANSITION = 0.5 × VINMAX × IPK × t F × fSW
Additional loss occurs in the system in every switching cycle due to energy stored in the drain-source
Maxim Integrated
capacitance of the internal MOSFET being lost when
the MOSFET turns on and discharges the drain-source
capacitance voltage to zero. This loss is estimated as:
PCAP =0.5 × C DS × VDSMAX 2 × fSW
The internal step-down regulator also has similar losses
that affect the temperature rise of the part. These losses
are estimated as:
(
1
PLOSSBUCK
= POUT × ( − 1) − IOUTB 2 × R DC
η
)
where E is the efficiency of the internal step-down
regulator at the output current (IOUTB), and RDC is the
DC resistance of the output inductor.
The total power loss in the devices can be calculated
from the following equation:
PLOSS =
PIN + PCONDUCTION + PTRANSITION + PCAP
+ PLOSSBUCK
The maximum power that can be dissipated in the
devices is 1666mW at +70NC temperature. The powerdissipation capability should be derated as the temperature rises above +70NC at 21mW/NC. For a multilayer
board, the thermal-performance metrics for the package
are given below:
θ JA = 48°C/ W
θ JC =10°C/ W
The junction temperature rise of the devices can be
estimated at any given maximum ambient temperature
(TA_MAX) from the following equation:
TJ_MAX
= TA_MAX + (θ JA × PLOSS )
If the application has a thermal-management system that
ensures that the devices’ exposed pad is maintained at a
given temperature (TEP_MAX) by using proper heatsinks,
then the junction temperature rise can be estimated at
any given maximum ambient temperature from the following equation:
T=
J_MAX TEP_MAX + (θ JC × PLOSS )
26
Maxim Integrated
NEUTRAL
85V AC TO
265V AC
LINE
D1
C1
0.1µF/
1kV
R1
10I
R10
1.2MI
R9
1.2MI
R8
1.2MI
R7
1.2MI
L1
1mH
D2
R15
3MI
R14
3MI
3MI
R12
3MI
C7
2.2µF/50V
VOUT1
C3
100µF/
400V
C2
100µF/
400V
VIN
R6
10kI
R5
36.5kI
R4
1.1MI
R3
1.1MI
R2
1.1MI
Q1
VIN
IN
C11
330pF
C6
0.47µF
/35V
R23
10kI
N2
FQT1N80TF
C9
0.15µF
R19
4.22kI
VCC
VOUT1
R18
442kI
R17
49.9kI
C4
2.2µF
R11
30kI
C12
47nF
IN
MAX17497A
OVI
EN/UVLO
PGNDF
COMPF
EAFN
SCOMPF
VCC
RLIMF
SSF
IN
OUTB
PGNDB
LXB
INB
RESETN
LXF
EP
C13
1µF/25V
VOUT3
L2
15µH
VOUT1
R22
10kI
C8
0.1µF/25V
IN
C16
10µF/6.3V
VCC
D5
R20
10I
R16
100kI/0.5W
VOUT3
3.3V, 0.6A
RESETN
N1
D3
C10
2.2nF/
250V
T1
D4
C14
22µF/
25V
VOUT1
C15
OPEN
PGND
VOUT1
12V, 0.3A
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
Figure 10. MAX17497A Typical Application Example (e.g., Smart Meter)
27
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
IN
VIN
10.8V TO
13.2V DC
EP
IN
C1
10µF
C2
0.1µF
C3
47nF
PGND
SSF
R1
75kI
IN
RLIMF
C4
2.2µF
L1
15µH
VCC
VCC
D1
SS26-TP
VOUT1
24V, 0.2A
LXF
C7
4.7µF/35V
R2
OPEN
SCOMPF
MAX17497B
R3
9.92kI
EAFN
RESETN
RESETN
R9
10kI
R4
184kI
VCC
VOUT1
R5
15kI
COMPF
C5
10nF
IN
C8
1µF/25V
INB
C6
47pF
IN
L2
15µH
PGNDF
R6
481kI
VOUT2
3.3V, 0.6A
LXB
C9
10µF/6.3V
EN/UVLO
PGNDB
R7
25kI
OVI
OUTB
R8
49.9kI
Figure 11. MAX17497B Typical Application Example
Maxim Integrated
28
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
Layout, Grounding, and Bypassing
All connections carrying pulsed currents must be very
short and as wide as possible. The inductance of these
connections must be kept to an absolute minimum due
to the high di/dt of the currents in high-frequency switching power converters. This implies that the loop areas for
forward and return pulsed currents in various parts of the
circuit should be minimized. Additionally, small-current
loop areas reduce radiated EMI. Similarly, the heatsink
of the main MOSFET presents a dV/dt source; therefore,
the surface area of the MOSFET heatsink should be minimized as much as possible.
Ground planes must be kept as intact as possible. The
ground plane for the power section of the converter
should be kept separate from the analog ground plane,
except for a connection at the least noisy section of the
power ground plane, typically the return of the input filter
capacitor. The negative terminal of the filter capacitor,
the ground return of the power switch, and the currentsensing resistor must be close together. PCB layout also
affects the thermal performance of the design. A number
of thermal vias that connect to a large ground plane
should be provided under the exposed pad of the part for
efficient heat dissipation. For a sample layout that ensures
first-pass success, refer to the MAX17497A evaluation kit
layout available at www.maximintegrated.com.
For universal AC input designs, follow all applicable
safety regulations. Offline power supplies can require UL,
VDE, and other similar agency approvals.
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
DESCRIPTION
MAX17497AATE+
-40NC to +125NC
16 TQFN
250kHz, Offline Flyback Converter with 3.3V, 600mA
Synchronous Step-Down Converter
MAX17497BATE+
-40NC to +125NC
16 TQFN
500kHz, Flyback/Boost Converter with 3.3V, 600mA
Synchronous Step-Down Converter
+Denotes a lead(Pb)-free/RoHS-compliant package.
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
PACKAGE CODE
OUTLINE NO.
LAND PATTERN NO.
16 TQFN
T1633+5
21-0136
90-0032
Maxim Integrated
29
MAX17497A/MAX17497B
AC-DC and DC-DC Peak Current-Mode Converters
with Integrated Step-Down Regulator
Revision History
REVISION
NUMBER
REVISION
DATE
0
11/11
Initial release
—
1
1/12
Removed future product reference for MAX17497B
29
DESCRIPTION
PAGES
CHANGED
2
10/12
Modified according to GBD data
1–4, 7–9, 17,
18, 19, 21, 22,
24, 25, 27, 28,
29
3
4/13
Part modification, updated Figure 1, Figure 10, and equations
1, 12, 13, 21,
24, 27
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent
licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and
max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000
© 2013 Maxim Integrated Products, Inc.
30
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
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