LPV531 Programmable Micropower CMOS Input, Rail-to

LPV531 Programmable Micropower CMOS Input, Rail-to
LPV531
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SNOSAK5B – MARCH 2006 – REVISED MARCH 2013
LPV531 Programmable Micropower CMOS Input, Rail-to-Rail Output Operational Amplifier
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FEATURES
1
•
•
•
•
2
•
•
•
•
•
(Typical 5V Supply, unless otherwise Noted.)
Supply Voltage 2.7V to 5.5V
Dynamic Power Mode Setting
Continuously Programmable Supply Current
– Range 5 μA to 425 μA
Continuously Programmable Bandwidth
– Range 73 kHz to 4.6 MHz
Input Common Mode Voltage Range −0.3V to
3.8V
CMRR 95 dB
Rail-to-Rail Output Voltage Swing
Input Offset Voltage 1 mV
APPLICATIONS
•
•
•
AC Coupled Circuits
Portable Instrumentation
Active Filters
R1
R2
VIN
R3
VOUT
+
+V
The LPV531 is an extremely versatile operational
amplifier. A single external resistor gives the system
designer the ability to define the quiescent current,
gain bandwidth product and output short circuit
current. This innovative feature gives the system
designer a method to dynamically switch the power
level to optimize the performance of the op amp and
meet the system design requirements.
The LPV531 can be tailored to a wide variety of
applications. It offers the system designer the ability
to dynamically trade off supply current for bandwidth
by adjusting the current drawn from the ISEL pin using
a DAC or switching in different value resistors in
series with the ISEL pin. The LPV531 is capable of
operating from 73 kHz, consuming only 5 μA, to as
fast as 4.6 MHz, consuming only 425 μA. The input
offset voltage is relatively independent and therefore
is not significantly affected by the chosen power level.
Utilizing a CMOS input stage, the LPV531 achieves
an input bias current of 50 fA and a common mode
input voltage which extends from the negative rail to
within 1.2V of the positive supply. The LPV531's railto-rail class AB output stage enables this op amp to
offer maximum dynamic range at low supply voltage.
Typical Application
C1
DESCRIPTION
C2
ISEL
Offered in the space saving 6-pin SOT package, the
LPV531 is ideal for use in handheld electronics and
portable applications. The LPV531 is manufactured
using TI’s advanced VIP50 process.
A fixed supply current/gain bandwidth is available
upon request.
R4
REXT
Figure 1. AC Coupled Application
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2013, Texas Instruments Incorporated
LPV531
SNOSAK5B – MARCH 2006 – REVISED MARCH 2013
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
ESD Tolerance
(1) (2)
(3)
Human Body Model
2000V
Machine Model
200V
VIN Differential
±2V
Supply Voltage (V+ - V−)
6V
−65°C to +150°C
Storage Temperature Range
Junction Temperature
(4)
+150°C
Soldering Information
(1)
(2)
(3)
(4)
Infrared or Convection (20 sec)
235°C
Wave Soldering Lead Temp. (10 sec)
260°C
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics Tables.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
Human Body Model is 1.5 kΩ in series with 100 pF. Machine Model is 0Ω in series with 200 pF.
Typical values represent the most likely parametric norm.
Operating Ratings
(1)
−40°C to +85°C
Operating Temperature Range
+
−
Supply Voltage (V – V )
Package Thermal Resistance (θJA )
2.7V to 5.5V
(2)
6-Pin SOT
(1)
(2)
2
171°C/W
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics Tables.
The maximum power dissipation is a function of TJ(MAX), θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
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5V Full Power Mode Electrical Characteristics
Unless otherwise specified, all limits are ensured for TJ = 25°C, V+ = 5V, V− = 0V, VCM = VO = V+/2, ISEL pin connected to V−,
RL = 100 kΩ. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
(1)
Typ
(2)
VOS
Input Offset Voltage
ΔVOS
Input Offset Voltage Difference
TC VOS
Input Offset Average Drift
(3)
±2
IB
Input Bias Current
(4)
.05
CMRR
Common Mode Rejection Ratio
VCM Stepped from 0V to 3.5V
72
68
95
PSRR
Power Supply Rejection Ratio
V+ = 2.7V to 5.5V
VCM = 1V
74
70
90
CMVR
Input Common Mode Voltage
Range
CMRR ≥ 50 dB
AVOL
Large Signal Voltage Gain
VO = 0.5V to 4.5V
RL = 1 kΩ to V+/2
87
84
96
VO = 0.5V to 4.5V
RL = 10 kΩ to V+/2
104
100
114
VO = 0.5V to 4.5V
RL = 100 kΩ, to V+/2
108
104
128
VO
Output Swing High
Output Swing Low
(VOS in Full Power Mode) −
(VOS in Low Power Mode)
Output Short Circuit Current
(5)
±4.5
±5
±0.1
±2
3.8
80
85
RL = 100 kΩ to V+/2
30
50
60
RL = 1 kΩ to V+/2
160
210
230
RL = 10 kΩ to V+/2
105
120
135
RL = 100 kΩ to V /2
95
120
135
Sourcing, VO = 2.5V
VID = 100 mV
−15
−8
−3
SR
Slew Rate
GBW
Gain Bandwidth Product
CL = 20 pF
4.6
en
Input-Referred Voltage Noise
f = 100 kHz
20
f = 1 kHz
28
f = 1 kHz
6
(1)
(2)
(3)
(4)
(5)
(6)
mV from
V+
mV
mA
24
Supply Current
Input-Referred Current Noise
V
dB
55
IS
in
pA
dB
RL = 10 kΩ to V+/2
425
1.55
1
mV
dB
180
195
AV = +1, VIN = 0.5V to 3.5V
CL = 15 pF
mV
±10
±100
120
13
10
Units
μV/°C
RL = 1 kΩ to V+/2
Sinking, VO = 2.5V
VID = −100 mV
(6)
(1)
±1
−0.3
+
ISC
Max
2.5
530
650
μA
V/μs
MHz
nV/√Hz
fA/√Hz
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametric norm.
Offset voltage average drift is determined by dividing the change in VOS at temperature extremes into the total temperature change.
Specified by design.
Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature
of 150°C.
Slew rate is the slower of the rising or falling slew rates.
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5V Mid-Power Mode Electrical Characteristics
Unless otherwise specified, all limits are ensured for TJ = 25°C, V+ = 5V, V− = 0V, VCM = VO = V+/2, ISEL pin connected to V−
through 100 kΩ resistor, RL = 100 kΩ. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
(1)
Typ
(2)
VOS
Input Offset Voltage
ΔVOS
Input Offset Voltage Difference
TC VOS
Input Offset Average Drift
(3)
±2
IB
Input Bias Current
(4)
.05
CMRR
Common Mode Rejection Ratio
VCM Stepped from 0V to 3.5V
72
68
92
PSRR
Power Supply Rejection Ratio
V+ = 2.7V to 5.5V
72
68
88
CMVR
Input Common Mode Voltage
Range
CMRR ≥ 50 dB
AVOL
Large Signal Voltage Gain
VO = 0.5V to 4.5V
RL = 10 kΩ to V+/2
86
82
96
VO = 0.5V to 4.5V
RL = 100 kΩ to V+/2
100
98
114
VO
Output Swing High
Output Swing Low
ISC
Output Short Circuit Current
(5)
(VOS in Full Power Mode) −
(VOS in Low Power Mode)
±1
±4.5
±5
±0.1
±2
−0.3
110
120
RL = 10 kΩ to V+/2
150
165
180
RL = 100 kΩ to V+/2
105
120
135
Sourcing, VO = 2.5V
VID = 100 mV
−4
−1.5
−1
4
Slew Rate
GBW
Gain Bandwidth Product
CL = 20 pF
625
en
Input-Referred Voltage Noise
f = 100 kHz
55
f = 1 kHz
60
f = 1 kHz
6
(1)
(2)
(3)
(4)
(5)
(6)
4
AV = +1, VIN = 0.5V to 3.5V
180
100
250
pA
V
dB
65
SR
mV
dB
RL = 100 kΩ to V+/2
42
mV
dB
160
175
Supply Current
Input-Referred Current Noise
±10
±100
115
1.5
1
Units
μV/°C
3.8
IS
in
(1)
RL = 10 kΩ to V+/2
Sinking, VO = 2.5V
VID = −100 mV
(6)
Max
55
62
mV from
V+
mV
mA
μA
V/ms
kHz
nV/√Hz
fA/√Hz
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametric norm.
Offset voltage average drift is determined by dividing the change in VOS at temperature extremes into the total temperature change.
Specified by design.
Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature
of 150°C.
Slew rate is the slower of the rising or falling slew rates.
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SNOSAK5B – MARCH 2006 – REVISED MARCH 2013
5V Low Power Mode Electrical Characteristics
Unless otherwise specified, all limits are ensured for TJ = 25°C, V+ = 5V, V− = 0V, VCM = VO = V+/2, ISEL connected to V−
through 1 MΩ resistor, RL = 100 kΩ. Boldface limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
(1)
Typ
(2)
VOS
Input Offset Voltage
ΔVOS
Input Offset Voltage Difference
TC VOS
Input Offset Average Drift
(3)
±2
IB
Input Bias Current
(4)
.05
CMRR
Common Mode Rejection Ratio
VCM Stepped from 0V to 3.5V
72
68
90
PSRR
Power Supply Rejection Ratio
V+ = 2.7V to 5.5V
72
68
85
CMVR
Input Common-Mode Voltage
Range
CMRR ≥ 50 dB
AVOL
Large Signal Voltage Gain
VO = 0.5V to 4.5V
RL = 10 kΩ to V+/2
(VOS in Full Power Mode) −
(VOS in Low Power Mode)
VO = 0.5V to 4.5V
RL = 100 kΩ to V+/2
VO
Output Swing High
Output Swing Low
ISC
Output Short Circuit Current
(5)
Max
(1)
±1
±4.5
±5
±0.1
±2
−0.3
mV
mV
μV/°C
±10
±100
pA
dB
dB
3.8
V
90
80
78
dB
100
RL = 10 kΩ to V+/2
175
400
1600
RL = 100 kΩ to V+/2
115
200
230
RL = 10 kΩ to V+/2
250
1200
1800
RL = 100 kΩ to V+/2
150
165
180
Sourcing, VO = 2.5V
VID = 100 mV
−400
−100
−35
Sinking, VO = 2.5V
VID = −100 mV
Units
80
35
mV from
V+
mV
µA
300
IS
Supply Current
SR
Slew Rate
GBW
Gain Bandwidth Product
CL = 20 pF
73
kHz
en
Input-Referred Voltage Noise
f = 1 kHz
200
nV/√Hz
in
Input-Referred Current Noise
f = 1 kHz
60
fA/√Hz
(1)
(2)
(3)
(4)
(5)
(6)
(6)
5
AV = +1, VIN = 0.5V to 3.5V
10
8
28
7
8
μA
V/ms
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametric norm.
Offset voltage average drift is determined by dividing the change in VOS at temperature extremes into the total temperature change.
Specified by design.
Continuous short circuit operation at elevated ambient temperature can result in exceeding the maximum allowed junction temperature
of 150°C.
Slew rate is the slower of the rising or falling slew rates.
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Power Select Electrical Characteristics
Unless otherwise specified, all limits are ensured for TJ = 25°C, V+ = 5V, V− = 0V, VCM = VO = V+/2, RL = 100 kΩ. Boldface
limits apply at the temperature extremes.
Symbol
Parameter
Conditions
Min
(1)
Typ
(2)
Max
(1)
Units
tLF
Time from Low Power Mode to
Full Power Mode
210
ns
tFL
Time from Full Power Mode to
Low Power Mode
500
ns
VREXT
Voltage @ ISEL Pin
ISEL Pin Left Open
RINT
(1)
(2)
100
110
125
mV
9
11
14.5
kΩ
All limits are specified by testing or statistical analysis.
Typical values represent the most likely parametric norm.
Connection Diagram
1
6
-
+
V
OUT
2
5
ISEL
V
+
3
4
IN-
IN+
Figure 2. 6-Pin SOT – Top View
See Package Number DDC
6
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Typical Performance Characteristics
Unless otherwise specified, V = 5V, TJ = 25°C. For Full Power Mode the ISEL pin is connected to V−; for Mid-Power Mode the
ISEL pin is connected to V− through a 100 kΩ resistor; for Low Power Mode the ISEL pin is connected to V− through a 1 MΩ
resistor.
+
Supply Current
vs.
ISEL
Supply Current
vs.
ISEL
1000
600
SUPPLY CURRENT (PA)
500
SUPPLY CURRENT (PA)
25°C
85°C
400 -40°C
300
200
100
85°C
10
-40°C
25°C
100
0
-12
-8
-10
-4
-6
-2
1
-0.1
0
-1
-10
ISEL (PA)
ISEL (PA)
Figure 3.
Figure 4.
Supply Current
vs.
Supply Voltage
(Full Power Mode)
Supply Current
vs.
Supply Voltage
(Mid Power Mode)
55
550
85°C
50
450
SUPPLY CURRENT (PA)
25°C
400
350
-40°C
45
25°C
40
35
-40°C
30
300
250
2.5
3.5
4.5
5.5
25
2.5
6.5
3.5
4.5
5.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Figure 5.
Figure 6.
Supply Current
vs.
Supply Voltage
(Low Power Mode)
Gain and Phase
vs.
Frequency
(Full Power Mode)
7
120
6.5
RL = 100 k:
CL = 20 pF
100
85°C
135
113
+
V = 5V
6
80
GAIN (dB)
SUPPLY CURRENT (PA)
85°C
25°C
5
-40°C
90
PHASE
60
68
GAIN
40
45
20
23
0
0
PHASE (°)
SUPPLY CURRENT (PA)
500
4
3
2.5
3.5
4.5
5.5
-20
100
6.5
SUPPLY VOLTAGE (V)
1k
10k
100k
1M
10M
-23
100M
FREQUENCY (Hz)
Figure 7.
Figure 8.
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Typical Performance Characteristics (continued)
Unless otherwise specified, V = 5V, TJ = 25°C. For Full Power Mode the ISEL pin is connected to V−; for Mid-Power Mode the
ISEL pin is connected to V− through a 100 kΩ resistor; for Low Power Mode the ISEL pin is connected to V− through a 1 MΩ
resistor.
+
120
Gain and Phase
vs.
Frequency
(Low Power Mode)
RL = 100 k:
CL = 20 pF
100
120
135
113
+
RL = 100 k:
100
PHASE
V = 5V
60
68
40
45
GAIN
20
GAIN (dB)
90
PHASE
PHASE (°)
GAIN (dB)
80
23
-20
100
1k
10k
100k
-23
10M
1M
113
+
V = 5V
90
60
68
40
45
GAIN
20
23
0
0
-20
100
1k
FREQUENCY (Hz)
10k
-23
1M
100k
FREQUENCY (Hz)
Figure 9.
Figure 10.
Input Offset Voltage
vs.
Common Mode Voltage
(Full Power Mode)
Input Offset Voltage
vs.
Common Mode Voltage
(Mid Power Mode)
1.5
1.5
DEVICE A @ 85°C
DEVICE A @ 85°C
1
1
0.5
VOS (mV)
0.5
VOS (mV)
135
80
0
0
CL = 20 pF
PHASE (°)
Gain and Phase
vs.
Frequency
(Mid Power Mode)
DEVICE B @ 85°C
DEVICE B @ 25°C
0
DEVICE A @ 25°C
-0.5
DEVICE B @ 85°C
DEVICE B @ 25°C
0
DEVICE A @ 25°C
-0.5
DEVICE B @ -40°C
DEVICE B @ -40°C
-1
-1
DEVICE A @ -40°C
DEVICE A @ -40°C
-1.5
-1.5
0
2
1
3
0
4
2
1
3
VCM (V)
VCM (V)
Figure 11.
Figure 12.
Input Offset Voltage
vs.
Common Mode Voltage
(Low Power Mode)
CMRR
vs.
Frequency
1.5
4
100
DEVICE A @ 85°C
90
FULL POWER MODE
1
80
70
DEVICE B @ 85°C
CMRR (dB)
VOS (mV)
0.5
DEVICE B @ 25°C
0
DEVICE A @ 25°C
-0.5
DEVICE B @ -40°C
50
40 MID POWER MODE
30
DEVICE A @ -40°C
-1
60
20
-1.5
0
8
1
2
3
10
10
4
LOW POWER MODE
100
1k
10k
VCM (V)
FREQUENCY (Hz)
Figure 13.
Figure 14.
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1M
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Typical Performance Characteristics (continued)
Unless otherwise specified, V = 5V, TJ = 25°C. For Full Power Mode the ISEL pin is connected to V−; for Mid-Power Mode the
ISEL pin is connected to V− through a 100 kΩ resistor; for Low Power Mode the ISEL pin is connected to V− through a 1 MΩ
resistor.
+
PSRR
vs.
Frequency
(Full Power Mode)
PSRR
vs.
Frequency
(Mid Power Mode)
100
100
90
90
80
80
-PSRR
70
60
PSRR (dB)
PSRR (dB)
60
+PSRR
50
+PSRR
70
40
50
-PSRR
40
30
30
20
20
10
10
0
0
10
1k
100
10k
100k
1M
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 15.
Figure 16.
PSRR
vs.
Frequency
(Low Power Mode)
Small Signal Non-Inverting Response
(Full Power Mode)
100
INPUT
90
80
+PSRR
(50 mV/DIV)
70
PSRR (dB)
60
50
40
-PSRR
OUTPUT
30
20
10
0
10
100
1k
10k
100k
TIME (10 Ps/DIV)
1M
FREQUENCY (Hz)
Small Signal Non-Inverting Response
(Mid Power Mode)
Small Signal Non-Inverting Response
(Low Power Mode)
(50 mV/DIV)
OUTPUT
OUTPUT
(50 mV/DIV)
INPUT
Figure 18.
INPUT
Figure 17.
TIME (10 Ps/DIV)
TIME (100 Ps/DIV)
Figure 19.
Figure 20.
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Typical Performance Characteristics (continued)
Unless otherwise specified, V = 5V, TJ = 25°C. For Full Power Mode the ISEL pin is connected to V−; for Mid-Power Mode the
ISEL pin is connected to V− through a 100 kΩ resistor; for Low Power Mode the ISEL pin is connected to V− through a 1 MΩ
resistor.
+
Large Signal Non-Inverting Response
(Mid Power Mode)
OUTPUT
OUTPUT
(2 V/DIV)
(2 V/DIV)
INPUT
INPUT
Large Signal Non-Inverting Response
(Full Power Mode)
TIME (10 Ps/DIV)
Figure 21.
Figure 22.
Large Signal Non-Inverting Response
(Low Power Mode)
Small Signal Inverting Pulse Response
(Full Power Mode)
OUTPUT
OUTPUT
(2 V/DIV)
(50 mV/DIV)
INPUT
INPUT
TIME (10 Ps/DIV)
TIME (100 Ps/DIV)
TIME (10 Ps/DIV)
Figure 24.
Small Signal Inverting Pulse Response
(Mid Power Mode)
Small Signal Inverting Pulse Response
(Low Power Mode)
OUTPUT
OUTPUT
(50 mV/DIV)
(50 mV/DIV)
INPUT
INPUT
Figure 23.
TIME (100 Ps/DIV)
TIME (10 Ps/DIV)
Figure 25.
10
Figure 26.
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Typical Performance Characteristics (continued)
Unless otherwise specified, V = 5V, TJ = 25°C. For Full Power Mode the ISEL pin is connected to V−; for Mid-Power Mode the
ISEL pin is connected to V− through a 100 kΩ resistor; for Low Power Mode the ISEL pin is connected to V− through a 1 MΩ
resistor.
+
(2 V/DIV)
OUTPUT
OUTPUT
(2 V/DIV)
INPUT
Large Signal Inverting Response
(Mid Power Mode)
INPUT
Large Signal Inverting Response
(Full Power Mode)
TIME (10 Ps/DIV)
TIME (10 Ps/DIV)
Figure 27.
Figure 28.
Large Signal Inverting Response
(Low Power Mode)
ISINK
vs.
Supply Current
INPUT
100
ISINK (mA)
(2 V/DIV)
10
85°C
OUTPUT
1
-40°C
25°C
0.1
TIME (100 Ps/DIV)
1
10
100
1000
SUPPLY CURRENT (PA)
Figure 29.
Figure 30.
ISOURCE
vs.
Supply Current
Gain Bandwidth Product
vs.
ISEL
5000
GAIN BANDWIDTH PRODUCT (kHz)
ISOURCE (mA)
100
10
85°C
1
-40°C
25°C
0.1
4500
4000
3500
3000
2500
2000
1500
1000
500
0
1
10
100
1000
SUPPLY CURRENT (PA)
-10
-8
-6
-4
-2
0
ISEL CURRENT (PA)
Figure 31.
Figure 32.
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Typical Performance Characteristics (continued)
Unless otherwise specified, V = 5V, TJ = 25°C. For Full Power Mode the ISEL pin is connected to V−; for Mid-Power Mode the
ISEL pin is connected to V− through a 100 kΩ resistor; for Low Power Mode the ISEL pin is connected to V− through a 1 MΩ
resistor.
+
Input Referred Voltage Noise
vs.
Frequency
Phase Margin
vs.
Capacitive Load
70
1000
LOW POWER MODE
LOW POWER MODE
PHASE MARGIN (°)
VOLTAGE NOISE (nV/ Hz)
RL=100 k:
60
MID POWER MODE
100
50
40
FULL POWER MODE
30
20
10
FULL POWER MODE
MID POWER MODE
10
1
10
100
1k
10k
100k
100
1000
CAPACITIVE LOAD (pF)
FREQUENCY (Hz)
Figure 33.
12
0
10
Figure 34.
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APPLICATION INFORMATION
The LPV531 is an extremely versatile operational amplifier because performance and power consumption can be
adjusted during operation. This provides a method to dynamically optimize the supply current, the bandwidth and
the output short circuit current in the application. The power level can be set by the current drawn from the ISEL
pin according to the application performance requirements.
CIRCUIT TOPOLOGY
As shown in Figure 35, the LPV531 contains two internal bias reference generators that deliver a reference
current (IREF) to the amplifier core. The programmable bias generator generates a 110 mV reference voltage
(VINT). This reference voltage is converted into a programmable reference current (IPROG) through the internal
resistor (RINT) and the external resistor (REXT) connected to the ISEL pin. Internally, IPROG is added to the output
current from the low power bias generator (ISTDB). When the ISEL pin is left floating, IPROG equals zero and the IREF
equals ISTDB. The value of ISTDB is such that in this mode the power supply current is below 1 µA. In this 1 µA
power mode, the LPV531 is functional but performance over the full temperature range is not ensured. The 1 µA
power mode operation is only recommended for applications with a temperature range between 0 and 70°C.
VCC
IPROG
ISTDB
PROGRAMMABLE
BIAS GENERATOR
LOW POWER
BIAS GERERATOR
IREF
+IN
OUT
VINT
RINT
BIAS
-IN
VEE
ISEL
Figure 35. Simplified Schematic
POWER MODE CONTROL
To illustrate typical configurations three possible solutions to control the power mode(s) of the LPV531 will be
described.
Single Power Mode
If the application requires one single power mode for the LPV531, then the easiest way to achieve this is to
connect a resistor (REXT) from the ISEL pin to V−. Together with the internal circuitry, REXT will determine the
current drawn from the ISEL pin. Internally the ISEL pin is connected to an 11 kΩ internal series resistor (RINT)
which is biased at VINT = 110 mV. This set up is illustrated in Figure 36.
For a desired supply current, bandwidth, short circuit current, or load resistance, the required value of REXT can
be calculated using the equations in the section “DETERMINING THE ISEL LEVELS”.
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IN
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4
+
+
+
6 V
VINT = 110 mV
RINT = 11 k:
IN
3
-
1
2 V
OUT
-
5
ISEL
REXT
Figure 36. Single Power Mode
Switched Discrete Power Modes
In this typical application, the LPV531 can operate at two (or more) power modes in order to fulfill the demands
of the design. One of the modes is used to save power. It is a low power mode which is set by using a large
resistor. The others are the higher power modes which are set by one or more smaller resistors. The larger
resistor that sets the low power mode can be permanently connected while the smaller resistor(s) can be
switched in parallel to set the high power mode(s). This configuration allows the designer to get the required
performance from the LPV531 when needed.
+
IN
-
LPV531
+
REXT = 1 M:
LOW
POWER
MODE
VOUT
ISEL
REXT = 100 k:
MID
POWER
MODE
REXT = 0:
HIGH
POWER
MODE
Figure 37. Power Modes Set by Resistors and Switches
The switches shown in Figure 37 can be easily implemented with an open drain I/O port of an ASIC or any other
simple pull down switch.
DAC Controlled Power Modes
For voltage controlled filter applications, where control of the gain bandwidth is essential, a DAC and a resistive
voltage divider can be used. In this application the current drawn from the ISEL pin is controlled by the DAC. The
DAC’s total output range is divided to match the V− to VINT voltage which has the range of 0-110 mV.
14
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-
+
LPV531
IN
-
DAC
+
VOUT
ISEL
VCONTROL
REXT2
REXT1
Figure 38. DAC Controlled Power Mode Configurations
The output of the resistive voltage divider should have an impedance that is small compared to the value of RINT
to allow a linear control of the power level. Therefore, REXT2 needs to have a value in the order of RINT/10 and
REXT1 = 125 mV * REXT2 /VCONTROL,MAX. For 1 µA power mode operation, these resistor values will divide the
maximum voltage of VCONTROL to 125 mV.
DETERMINING THE REXT VALUES AND ISEL LEVELS
To determine the value of REXT that is needed for a certain supply current or bandwidth, the following equations
can be used:
110 mV
PSI = 1 PA + 40 x
REXT + 11k
(1)
or
REXT = 40 x
110 mV
PSI ± 1 PA
GBW = 11 kHz +
-11 k:
(2)
50[GHz · :]
REXT + 11 k:
or
REXT =
50[GHz · :]
GBW - 11 kHz
-11 k:
(3)
For the power modes characterized in this datasheet, these formulas lead to the values in Table 1. These values
deviate slightly from the typical values presented in the Electrical Characteristics tables. The values in Table 1
are calculated using approximated linear equations while the values in the Electrical Characteristics tables are
the result of characterization measurement procedures.
Table 1. Values for Characterized Power Modes
REXT
ISEL
Supply Current
Gain Bandwidth Product
1Ω
9 µA
400 µA
4.6 MHz
100 kΩ
0.9 µA
40 µA
460 kHz
1 MΩ
99 nA
5.3 µA
60 kHz
To calculate the REXT which will allow the LPV531 to deliver a minimum output current at all times and over all
temperatures, use the following equations:
ISC =
35V
REXT + 11 k:
or
REXT =
35V
-11 k:
ISC
(4)
+
If the output has to be kept at V /2 for a known load resistance, the required REXT can be calculated with the
following equations:
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RLOAD,MIN =
0.07
REXT + 11 k:
or
REXT =
www.ti.com
0.07
RLOAD,MIN
-11 k:
(5)
For the characterized power modes these equations lead to the minimum values in Table 2 below.
Table 2. Minimum Values for Characterized Power Modes
REXT
ISEL
ISC
RLOAD
1Ω
9 µA
3 mA
770Ω
100 kΩ
0.9 µA
300 µA
7.8 kΩ
1 MΩ
99 nA
55 µA
70.8 kΩ
The smallest load resistor that the LPV531 can drive when in low power mode is 70.8 kΩ, as shown in Table 2.
When driving smaller loads, such as the 10 kΩ load resistor used in the Electrical Characteristics tables
specification, the output swing in the low power mode is limited. If the application requires a 10 kΩ load then it is
not recommended to use the LPV531 in low power mode.
ISEL SENSITIVITY
The ISEL pin is a current reference that directly affects the entire internal bias condition. Therefore, the ISEL pin is
very sensitive to parasitic signal coupling. In order to protect the ISEL pin from unwanted distortion, it is important
to route the PCB layout such that there is as little coupling between the ISEL pin and the output or other signal
traces as possible.
Typical Application
AC COUPLED CIRCUITS
The programmable power mode makes the LPV531 ideal for AC coupled circuits where the circuit needs to be
kept active to maintain a quiescent charge on the coupling capacitors with minimal power consumption.
Figure 39 shows the schematic of an inverting AC coupled amplifier using the LPV531 with the ISEL pin controlled
by I/O ports of a microcontroller. The advantage of the low power active mode for AC coupled amplifiers is the
elimination of the time needed to re-establish a quiescent operating point when the amplifier is switched to full
power mode.
When an amplifier without a low power active mode is used in low power applications, there are two ways to
minimize power consumption. The first method turns off the amplifier by switching off power to the op amp using
a transistor switch. The second method uses an amplifier with a shutdown pin. Both of these methods have the
problem of allowing the coupling capacitors, C1 and C2 to discharge the quiescent DC voltage stored on them
when in the shutdown state. When the amplifier is turned on again, the quiescent DC voltages must reestablish
themselves. During this time, the amplifier’s output is not usable because the output signal is a mixture of the
amplified input signal and the charging voltage on the coupling capacitors. The settling time can range from a
several milliseconds to several seconds depending on the resistor and capacitor values.
When the LPV531 is placed into the low power mode, the power consumption is minimal but the amplifier is
active to maintain the quiescent DC voltage on the coupling capacitors. The transition back to the operational
high power mode is fast, within a few hundred nanoseconds. The active low power mode of the LPV531
separates two critical aspects of a low power AC amplifier design. The values of the gain resistors, bias resistors,
and coupling capacitors can be chosen independently of the turn-on and stabilization time.
16
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C1
R2
R1
VIN
-
R3
VOUT
+
+V
C2
ISEL
R4
REXT
I/O PIN
MICROCONTROLLER
Figure 39. Inverting AC Coupled Application
PROGRAMMABLE POWER LEVELS AND THE EFFECTS OF STABILITY COMPENSATION METHODS
USING EXTERNAL COMPONENTS
In some op amp application circuits, external capacitors are used to improve the stability of the feedback loop
around the amplifier. When using the programmable power level feature of the LPV531 such stability
improvement methods may not work. This is related to the internal frequency compensation method applied
inside the LPV531.
Figure 40 shows the bode plot of the frequency response of the LPV531. The gain-bandwidth product is
determined by the transconductance of the input stage (gm,in) and the internal Miller compensation capacitor
(Cm). The non-dominant pole is formed by the transconductance of the output stage (gm,out) and the load
capacitance connected to the output of the LPV531 (Cl). The frequency response crosses the frequency axis with
a single-pole slope (20 dB/decade). This ensures the stability of feedback loops formed around the LPV531.
GAIN
20 dB/decade
gm,in/Cm
FREQUENCY (Hz)
gm,out/CI
40 dB/decade
Figure 40. Bode Plot of the Frequency Response
When the load capacitance is increased, the pole at the output will shift to lower frequencies. Eventually, the
output pole will shift below the unity gain frequency. This will cause the frequency characteristic to move through
the 0 dB axis with a slope of 40 dB/decade and a feedback loop formed around the LPV531 may oscillate. The
LPV531 is internally compensated in such a manner that it will be stable for load capacitances up to 100 pF.
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When the power setting of the LPV531 is reduced, both the transconductance of the input stage and the
transconductance of the output stage will scale lineary with the power level to lower levels. This means that both
the unity gain frequency and the pole to the transconductance of the output stage and the load capacitance will
move down. Because both the unity gain frequency and the output pole move down in similar amounts, the
stability of the LPV531 is still the same. This is shown in Figure 41 which gives the phase margin as a function of
the load capacitance in the low power mode (5 µA), mid-power mode (40 µA) and high power mode (400 µA).
Though the power level and unity gain frequency move with about two decades, the phase margin as a function
of the capacitive load is hardly affected. This means that when the LPV531 is stable in an application circuit with
a given load capacitance in the high power mode, the circuit will remain stable with the same capacitive load
connected when the power level is reduced.
70
RL=100 k:
60
PHASE MARGIN (°)
LOW POWER MODE
50
40
30
FULL POWER MODE
20
10
MID POWER MODE
0
10
100
1000
CAPACITIVE LOAD (pF)
Figure 41. Phase Margin vs. Capacitive Load
Figure 42 shows a method that is sometimes used to allow an op amp to drive larger capacitors than it was
originally designed to do. The capacitive load is isolated from the output of the op amp with an isolation resistor
(RISO). This moves the output pole, that was originally located at gm,out/Cl, to a higher frequency. This method
requires that the value of RISO is in the same order of magnitude as 1/gm,out. For the LPV531, this method will not
be effective when used across a broad range of power levels. This is because the high power mode will require a
relatively small value for RISO, while such a small RISO will be ineffective at low power levels. In most applications
this should not be a problem as the LPV531 can drive sufficient capacitive loads without the need for an external
isolation resistor.
1 M:
1 M:
VIN
RISO
+
ISEL
VOUT
CL
Figure 42. Compensation by Isolation Resistor
18
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INPUT CAPACITANCE AND FEEDBACK CIRCUIT ELEMENTS
The LPV531 has a very low input bias current (50 fA). To obtain this performance a large CMOS input stage is
used, which adds to the input capacitance of the op amp, CIN. Though this does not affect the DC and low
frequency performance, at higher frequencies the input capacitance interacts with the input and the feedback
impedances to create a pole, which results in lower phase margin and gain peaking. The gain peaking can be
reduced by carefully choosing the appropriate feedback resistor, as well as, by using a feedback capacitance,
CF. For example, in the inverting amplifier shown in Figure 43, if CIN and CF are ignored and the open loop gain
of the op amp is considered infinite then the gain of the circuit is −R2/R1. An op amp, however, usually has a
dominant pole, which causes its gain to drop with frequency. Hence, this gain is only valid for DC and low
frequency. To understand the effect of the input capacitance coupled with the non-ideal gain of the op amp, the
circuit needs to be analyzed in the frequency domain using a Laplace transform.
CF
R2
R1
-
+
CIN
VIN
+
+
-
-
AV = -
VOUT
VIN
=-
VOUT
R2
R1
Figure 43. Inverting Amplifier
For simplicity, the op amp is modeled as an ideal integrator with a unity gain frequency of A0 . Hence, its transfer
function (or gain) in the frequency domain is A0/s. Solving the circuit equations in the frequency domain, ignoring
CF for the moment, results in the following equation for the gain:
VOUT
-R2/R1
(s) =
VIN
s2
s
+
1+
§ A0 R 1
§ A0
¨
¨C R
+
R
R
2
© 1
© IN 2
§
¨
©
§
¨
©
(6)
It can be inferred from the denominator of the transfer function that it has two poles, whose expressions can be
obtained by solving for the roots of the denominator:
1
1
+
r
R1
R2
§1
1
+
¨
R2
© R1
§
¨
©
-1
P1,2 =
2CIN
2
-
4 A0CIN
R2
(7)
Equation 7 shows that as the values of R1 and R2 are increased, the magnitude of the poles is reduced, and
hence the bandwidth of the amplifier is decreased. Furthermore, R1 and R2 are related by the gain of the
amplifier.
AV = −R2/R1, or alternatively
R2 = −AVR1
It is the presence of pairs of poles in Equation 7 that causes gain peaking. In order to eliminate this effect, the
poles should be placed in Butterworth position, since poles in Butterworth position do not cause gain peaking. To
achieve a Butterworth pair, the quantity under the square root in Equation 7 should be set to equal −1. Using this
fact and the relation between R1 and R2, the optimum value for R1 can be found. This is shown in Equation 8. If
R1 is chosen to be larger than this optimum value, gain peaking will occur.
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R1 <
(1 - AV)
www.ti.com
2
2A0AVCIN
(8)
In Figure 43, CF is added to compensate for input capacitance and to increase stability. In addition, CF reduce or
eliminates the gain peaking that can be caused by having a larger feedback resistor.
20
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SNOSAK5B – MARCH 2006 – REVISED MARCH 2013
REVISION HISTORY
Changes from Revision A (March 2013) to Revision B
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 20
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21
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
LPV531MK/NOPB
ACTIVE
SOT
DDC
6
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
AV2A
LPV531MKX/NOPB
ACTIVE
SOT
DDC
6
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
AV2A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LPV531MK/NOPB
SOT
DDC
6
1000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
LPV531MKX/NOPB
SOT
DDC
6
3000
178.0
8.4
3.2
3.2
1.4
4.0
8.0
Q3
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LPV531MK/NOPB
SOT
DDC
6
1000
210.0
185.0
35.0
LPV531MKX/NOPB
SOT
DDC
6
3000
210.0
185.0
35.0
Pack Materials-Page 2
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