3.3 VOLT COMMUNICATIONS CLOCK PLL MK2049

3.3 VOLT COMMUNICATIONS CLOCK PLL MK2049
DATASHEET
3.3 VOLT COMMUNICATIONS CLOCK PLL
MK2049-45
Description
Features
The MK2049-45 is a dual Phase-Locked Loop (PLL) device
which can provide frequency synthesis and jitter
attenuation. The first PLL is VCXO based and uses a
pullable crystal to track signal wander and attenuate input
jitter. The second PLL is a translator for frequency
multiplication. Basic configuration is determined by a
Mode/Frequency Selection Table. Loop bandwidth and
damping factor are programmable via external loop filter
component selection.
• Packaged in 20 pin SOIC
• 3.3 V + 5% operation
• Meets the TR62411, ETS300 011, and GR-1244
•
•
•
Buffer Mode accepts a 10 to 50MHz input and will provide a
jitter attenuated output at 0.5 x ICLK, 1 x ICLK or 2 x ICLK.
In this mode the MK2049-45 is ideal for filtering jitter from
high frequency clocks.
•
•
•
•
•
In External Mode, ICLK accepts an 8 kHz clock and will
produce output frequencies from a table of common
communciations clock rates, CLK and CLK/2. This allows
for the generation of clocks frequency-locked to an 8 kHz
backplane clock, simplifying clock synchronization in
communications systems.
specification for MTIE, Pull-in/Hold-in Range, Phase
Transients, and Jitter Generation for Stratum 3, 4, and 4E
Accepts multiple inputs: 8 kHz backplane clock, or 10 to
50 MHz
Locks to 8 kHz + 100 ppm (External mode)
Buffer Mode allows jitter attenuation of 10 - 50 MHz input
and x1 / x0.5 or x1 / x2 outputs
Exact internal ratios enable zero ppm error
Output rates include T1, E1, T3, E3, and OC3
submultiples
Available in Pb (lead) free package
See also the MK2049-34 and MK2049-36
Not recommended for new designs. Use the
MK2049-45A.
The MK2049-45 can be dynamically switched between T1,
E1, T3, E3 outputs with the same 24.576 MHz crystal.
ICS can customize these devices for many other different
frequencies. Contact your ICS representative for more
details.
Block Diagram
RSET
ISET
Reference
Divider
(used in buffer
mode only)
ICLK
CS
CP
CL
RS
CAP2
CL Optional Crystal Load Caps
External Pullable Crystal
CAP1 X1
X2
Phase
Detector
VCXO
Charge
Pump
VCXO
PLL
Reference
Divider
Feedback
Divider (N)
VCO
Translator
PLL
Feedback
Divider
Output
Divider
CLK
Divide
by 2
CLK/2
8k
4
FS3:0
Divider Value
Look-up Table
IDT™ / ICS™ 3.3 VOLT COMMUNICATIONS CLOCK PLL
1
MK2049-45
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MK2049-45
3.3 VOLT COMMUNICATIONS CLOCK PLL
VCXO AND SYNTHESIZER
Pin Assignment
FS1
X2
1
2
20
19
FS0
RES
X1
VDD
3
4
18
17
CAP2
GND
FCAP
VDD
GND
CLK
CLK/2
8k
5
6
16
15
CAP1
VDD
7
8
9
10
14
13
GND
ICLK
FS3
FS2
12
11
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
FS1
Input
Frequency select 1. Determines CLK input/outputs per table on page 2.
Internal pull-up resistor.
2
X2
Input
Crystal connection. Connect to a MHz crystal as shown in table on page 2.
3
X1
Input
Crystal connection. Connect to a MHz crystal as shown in table on page 2.
4
VDD
Power
Power supply. Connect to +3.3V.
5
FCAP
-
6
VDD
Power
Power supply. Connect to +3.3V.
7
GND
Power
Connect to ground
8
CLK
Output
Clock output determined by status of FS3:0 per tables on page 2.
9
CLK/2
Output
Clock output determined by status of FS3:0 per tables page 2. Always 1/2 of
CLK.
10
8k
Output
Recovered 8 kHz clock output.
11
FS2
Input
Frequency select 2. Determines CLK input/outputs per table on page 2.
Internal pull-up resistor.
12
FS3
Input
Frequency select 3. Determines CLK input/outputs per table on page 2.
Internal pull-up resistor.
13
ICLK
Input
Input clock connection. Connect to 8 kHz backplane or MHz clock.
14
GND
Power
Connect to ground.
15
VDD
Power
Power Supply. Connect to +3.3V.
16
CAP1
Loop
Filter
Connect the loop filter capacitors and resistor between this pin and CAP2.
17
GND
Power
Connect to ground.
Filter capacitor. Connect a 1000 pF ceramic capacitor to ground.
IDT™ / ICS™ 3.3 VOLT COMMUNICATIONS CLOCK PLL
2
MK2049-45
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MK2049-45
3.3 VOLT COMMUNICATIONS CLOCK PLL
Pin
Number
Pin
Name
Pin
Type
18
CAP2
Loop
Filter
19
RES
-
20
FS0
Input
VCXO AND SYNTHESIZER
Pin Description
Connect the loop filter capacitors and resistor between this pin and CAP1.
Connect a resistor to ground. See table.
Frequency select 0. Determines CLK input/outputs per table on page 2.
Internal pull-up resistor.
Output Decoding Table - External Mode (MHz)
ICLK
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
FS1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
FS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CLK/2
1.544
2.048
22.368
17.184
19.44
12.8
25.92
4.096
18.528
12.352
24.576
16.384
17.28
62.5
CLK
3.088
4.096
44.736
34.368
38.88
25.6
51.84
8.192
37.056
24.704
49.152
32.768
34.56
125
8k
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
Crystal
Used (MHz)
24.576
24.576
24.576
24.576
19.44
25.6
17.28
16.384
24.704
24.704
16.384
16.384
17.28
25
N
3072
3072
3072
3072
2430
3200
2160
2048
3088
3088
2048
2048
2160
3125
Output Decoding Table - Buffer Mode (MHz)
ICLK
FS3
FS2
FS1
FS0
CLK/2
CLK
8k
Crystal
N
20 - 50
1
1
1
0
ICLK
2*ICLK
N/A
ICLK/2
3
10 - 25
1
1
1
1
ICLK/2
ICLK
N/A
ICLK
3
0 = connect directly to ground, 1 = connect directly to VDD
Crystal is connected to pins 2 and 3; clock input is applied to pin 13.
Functional Description
The MK2049-45 is a clock generator IC that generates an
output clock directly from an internal VCXO circuit which
works in conjunction with an external quartz crystal. The
VCXO is controlled by an internal PLL (Phase Locked Loop)
circuit, enabling the device to perform clock regeneration
from an input reference clock. The MK2049-45 is configured
to provide a high frequency communications reference clock
output from an 8 kHz input clock or to jitter attenuate and
IDT™ / ICS™ 3.3 VOLT COMMUNICATIONS CLOCK PLL
buffer a high frequency input clock. There are 14 selectable
output frequencies and two buffer mode selections. Please
refer to the Output Clock Selection Table on Page 2.
Most typical PLL clock devices use an internal VCO (Voltage
Controlled Oscillator) for output clock generation. By using
a VCXO with an external crystal, the MK2049-45 is able to
generate a low jitter, low phase-noise output clock within a
3
MK2049-45
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MK2049-45
3.3 VOLT COMMUNICATIONS CLOCK PLL
VCXO AND SYNTHESIZER
http://www.icst.com/products/telecom/vcxocrystals.htm
low bandwidth PLL. This serves to provide input clock jitter
attenuation and enables stable operation with a low
frequency reference clock.
PLL Loop Filter Components
All analog PLL circuits use a loop filter to establish operating
stability. The MK2049-45 uses external loop filter
components for the following reasons:
The VCXO circuit requires an external pullable crystal for
operation. External loop filter components enable a PLL
configuration with low loop bandwidth.
1) Larger loop filter capacitor values can be used, allowing
a lower loop bandwidth. This enables the use of lower input
clock reference frequencies and also input clock jitter
attenuation capabilities. Larger loop filter capacitors also
allow higher loop damping factors when less passband
peaking is desired.
Application Information
Output Frequency Configuration
The MK2049-45 is configured to generate a set of output
frequencies from an 8 kHz input clock. Please refer to the
Output Clock Selection Table on Page 2. Input bits FS3:0
are set according to this table, as is the external crystal
frequency. Please refer to the Quartz Crystal section on this
page regarding external crystal requirements.
2) The loop filter values can be user selected to optimize
loop response characteristics for a given application.
Referencing the External Component Schematic on this
page, the external loop filter is made up of components RS,
CS and CP. RSET establishes PLL charge pump current and
therefore influences loop filter characteristics.
Quartz Crystal
It is important that the correct type of quartz crystal is used
with the MK2049-45. Failure to do so may result in reduced
frequency pullability range, inability of the loop to lock, or
excessive output phase jitter.
Tools for optimizing the values of these four components
can be found at: http://www.icst.com/products/telecom/
The MK2049-45 operates by phase-locking the VCXO
circuit to the input signal of the selected ICLK input. The
VCXO consists of the external crystal and the integrated
VCXO oscillator circuit. To achieve the best performance
and reliability, a crystal device with the recommended
parameters (shown below) must be used, and the layout
guidelines discussed in the PCB Layout Recommendations
section must be followed.
CAP2
CP
0.0003 µF
RS 820 kohms
CS 0.1 µF
CAP1
Figure 3. Typical Loop Filter
The frequency of oscillation of a quartz crystal is determined
by its cut and by the external load capacitance. The
MK2049-45 incorporates variable load capacitors on-chip
which “pull”, or change, the frequency of the crystal. The
crystals specified for use with the MK2049-45 are designed
to have zero frequency error when the total of on-chip +
stray capacitance is 14 pF. To achieve this, the layout should
use short traces between the MK2049-45 and the crystal.
A complete description of the recommended crystal
parameters in the ICS application note, MAN05.
To obtain a list of qualified crystal devices please visit our
website at:
IDT™ / ICS™ 3.3 VOLT COMMUNICATIONS CLOCK PLL
4
MK2049-45
REV G 101904
MK2049-45
3.3 VOLT COMMUNICATIONS CLOCK PLL
VCXO AND SYNTHESIZER
Charge Pump Current Table
RSET
(kΩ)
13.02
15
16
18
20
22
24
27
36
47
56
75
100
150
200
modulation.
Charge Pump Current
(ICP) (µA)
Recommended Power Supply Connection for
Optimal Device Performance
139
125
119
109
100
93
86
68
56
43
35
28
22
15
12
VDD Pin
Connection to 3.3V
Power Plane
VDD Pin
Bulk Decoupling Capacitor
(such as 1 µF Tantalum)
VDD Pin
0.01 µF Decoupling Capacitors
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground,
shown as CL in the External Component Schematic. These
capacitors are used to adjust the stray capacitance of the
board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) been the crystal and device.
Special considerations must be made in choosing loop
components CS and CP. These recommendations can be
found at
http://www.icst.com/products/telecom/loopfiltercap.htm
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a commonly
used trace impedance), place a 33Ω resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20Ω. (The
optional series termination resistor is not shown in the
External Component Schematic.)
Please refer to MAN05 for the procedure to determine
capacitor values.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following guidelines should be observed. Please
also refer to the Recommended PCB Layout drawing on
Page 7.
Decoupling Capacitors
As with any high performance mixed-signal IC, the
MK2049-45 must be isolated from system power supply
noise to perform optimally.
1) Each 0.01 µF decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No via’s should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. To further
guard against interfering system supply noise, the
MK2049-45 should use one common connection to the PCB
power plane as shown in the diagram on the next page. The
ferrite bead and bulk capacitor help reduce lower frequency
noise in the supply that can lead to output clock phase
IDT™ / ICS™ 3.3 VOLT COMMUNICATIONS CLOCK PLL
Ferrite
Bead
2) The loop filter components must also be placed close to
5
MK2049-45
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MK2049-45
3.3 VOLT COMMUNICATIONS CLOCK PLL
VCXO AND SYNTHESIZER
the CHGP and VIN pins. CP should be closest to the device.
Coupling of noise from other system signal traces should be
minimized by keeping traces short and away from active
signal traces. Use of vias should be avoided.
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the MK2049-45. This includes signal traces just
underneath the device, or on layers adjacent to the ground
plane layer used by the device.
3) The external crystal should be mounted just next to the
device with short traces. The X1 and X2 traces should not
be routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
MAN05 may also be referenced for additional suggestions
on layout of the crystal section.
4) To minimize EMI the 33 Ω series termination resistor, if
needed, should be placed close to the clock output.
5) An optimum layout is one with all components on the
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK2049-45. These ratings, which are
standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at
these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical
parameters are guaranteed only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD
7V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature
-40 to +85°C
Storage Temperature
-65 to +150°C
Junction Temperature
125°C
Soldering Temperature
250°C
Recommended Operation Conditions
Parameter
Min.
Ambient Operating Temperature
-40
Power Supply Voltage (measured in respect to GND)
IDT™ / ICS™ 3.3 VOLT COMMUNICATIONS CLOCK PLL
Typ.
6
+3.15
+3.3
Max.
Units
+85
°C
+3.45
V
MK2049-45
REV G 101904
MK2049-45
3.3 VOLT COMMUNICATIONS CLOCK PLL
VCXO AND SYNTHESIZER
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85°C
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
3.15
3.3
3.45
V
Operating Voltage
VDD
Supply Current
IDD
Input High Voltage
VIH
Input Low Voltage
VIL
Input High Current
IIH
VIH = VDD
Input Low Current
IIL
VIL = 0
Input Capacitance, except X1
CIN
Output High Voltage (CMOS
Level)
VOH
IOH = -4 mA
VDD-0.4
V
Output High Voltage
VOH
IOH = -8 mA
2.4
V
Output Low Voltage
VOL
IOL = 8 mA
Short Circuit Current
IOS
VIN, VCXO Control Voltage
VXC
Clock outputs
unloaded, VDD = 3.3V
25
mA
2
V
0.8
V
-10
+10
µA
-10
+10
µA
7
pF
0.4
V
±50
0
mA
VDD
V
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85° C
Parameter
Symbol
VCXO Crystal Pull Range
fXP
Conditions
Using Recommended
Crystal
Min.
Typ.
-115
Max. Units
+115
ppm
0.4
UI
Input Jitter Tolerance
tji
Input pulse width (1)
tpi
Output Duty Cycle (% high
time)
tOD
Measured at VDD/2,
CL=15pF
Output Rise Time
tOR
0.8 to 2.0V, CL=15 pF
1.0
ns
Output Fall Time
tOF
2.0 to 0.8V, CL=15 pF
1.0
ns
Skew, ICLK to Output Clock
Note 2
tIO
All output clock
selections except 1.544
and 2.048 MHz
Timing Jitter, Filtered
500Hz-1.3MHz (OC-3)
tjf
Referenced to
Mitel/Zarlink MT9045,
Note 3
IDT™ / ICS™ 3.3 VOLT COMMUNICATIONS CLOCK PLL
In reference to input
clock period
10
7
ns
40
60
-5
+5
400
%
ns
ps
MK2049-45
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MK2049-45
3.3 VOLT COMMUNICATIONS CLOCK PLL
Parameter
VCXO AND SYNTHESIZER
Symbol
Timing Jitter, Filtered
65kHz-1.3MHz (OC-3)
tjf
Frequency Error
Conditions
Min.
Referenced to
Mitel/Zarlink MT9045,
Note 3
Relative to ICLK
Nominal Output Impedance
ZOUT
Typ.
Max. Units
230
ps
0
ppm
20
Ω
Note 1: Minimum high or low time of input clock.
Note 2: For the 1.544 MHz and 2.048 MHz output selections, the input to output clock skew is not controlled nor
predictable and will change between power up cycles. Because it is dependent on the phase relationship between
the output and feedback divider states following power up, the input to output clock skew will remain stable during a
given power up cycle. If controlled input to output skew is desired for this output clock frequency please refer to the
MK2049 or MK2069 products.
Note 3: Input reference is the 8 kHz output from a Mitel/Zarlink MT9045 device in freerun mode
(SEL2:0 = 100, 19.44 MHz external crystal).
Marking Diagram
20
Marking Diagram (Pb free)
20
11
MK2049-45SILF
######
YYWW
MK2049-45SI
######
YYWW
1
11
10
1
10
Notes:
1. ###### is the lot number.
2. YYWW is the last two digits of the year and the week that the part was assembled.
3. “LF” designates Pb (lead) free package.
IDT™ / ICS™ 3.3 VOLT COMMUNICATIONS CLOCK PLL
8
MK2049-45
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MK2049-45
3.3 VOLT COMMUNICATIONS CLOCK PLL
VCXO AND SYNTHESIZER
Package Outline and Package Dimensions (20 pin SOIC, 300 Mil. Wide Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Symbol
A
A1
A2
B
C
D
E
e
H
h
L
α
In d e x
A re a
E
H
1
2
h x 45o
D
Min
A2
A1
Max
-2.65
1.10
-2.05
2.55
0.33
0.51
0.18
0.32
12.60
13.00
7.40
7.60
1.27 Basic
10.00
10.65
0.25
0.75
0.40
1.27
0°
8°
Inches
Min
Max
-0.104
0.0040
-0.081
0.100
0.013
0.020
0.007
0.013
0.496
0.512
0.291
0.299
0.050 Basic
0.394
0.419
0.010
0.029
0.016
0.050
0°
8°
A
e
L C
B
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
MK2049-45SI
MK2049-45SI
Tubes
20-pin SOIC
-40 to +85° C
MK2049-45SITR
MK2049-45SI
Tape and Reel
20-pin SOIC
-40 to +85° C
MK2049-45SILF
MK2049-45SILF
Tubes
20-pin SOIC
-40 to +85° C
MK2049-45SILFTR
MK2049-45SILF
Tape and Reel
20-pin SOIC
-40 to +85° C
“LF” denotes Pb (lead) free package.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no
responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS
does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
IDT™ / ICS™ 3.3 VOLT COMMUNICATIONS CLOCK PLL
9
MK2049-45
REV G 101904
MK2049-45
3.3 VOLT COMMUNICATIONS CLOCK PLL
VCXO AND SYNTHESIZER
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
For Tech Support
800-345-7015
408-284-8200
Fax: 408-284-2775
<product line email>
<product line phone>
Corporate Headquarters
Asia Pacific and Japan
Europe
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
IDT Europe, Limited
Prime House
Barnett Wood Lane
Leatherhead, Surrey
United Kingdom KT22 7DE
+44 1372 363 339
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered
trademarks used to identify products or services of their respective owners.
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