NUS3055MUTAG Low Profile Overvoltage Protection IC with

NUS3055MUTAG Low Profile Overvoltage Protection IC with
NUS3055MUTAG
Low Profile Overvoltage
Protection IC with
Integrated MOSFET
This device represents a new level of safety and integration by
combining the NCP345 overvoltage protection circuit (OVP) with a
30 V P−channel power MOSFET. It is specifically designed to protect
sensitive electronic circuitry from overvoltage transients and power
supply faults. During such hazardous events, the IC quickly
disconnects the input supply from the load, thus protecting the load
before any damage can occur.
The OVP IC is optimized for applications that use an external
AC−DC adapter or a car accessory charger to power a portable product
or recharge its internal batteries. It has a nominal overvoltage
threshold of 6.85 V which makes them ideal for single cell Li−Ion as
well as 3/4 cell NiCD/NiMH applications.
Features
•
•
•
•
•
•
•
•
•
OvervoltageTurn−Off Time of Less Than 1.0 ms
Accurate Voltage Threshold of 6.85 V, Nominal
Undervoltage Lockout Protection; 2.8 V, Nominal
High Accuracy Undervoltage Threshold of 2.0%
−30 V Integrated P−Channel Power MOSFET
Low RDS(on) = 75 mW @ −4.5 V
Low Profile 0.55 mm height, 2.5 X 3.0 mm LLGA Package Suitable
for Portable Applications
Maximum Solder Reflow Temperature @ 260°C
This device is manufactured with a Pb−Free external lead finish only.
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MARKING
DIAGRAM
8
1
TLLGA8
CASE 517AH
1
XXXX
A
Y
WW
G
XXXX
AYWW
G
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
PIN CONNECTIONS
VCC 8
OUT
7
GATE
6
SRC
5
1 IN
2 GND
DRAIN
4
3 CNTRL
4 DRAIN
(Bottom View)
Benefits
• Provide Battery Protection
• Integrated Solution Offers Cost and Space Savings
• Integrated Solution Improves System Reliability
Applications
• Portable Computers and PDAs
• Cell Phones and Handheld Products
• Digital Cameras
© Semiconductor Components Industries, LLC, 2006
December, 2006 − Rev. 0
ORDERING INFORMATION
Device
Package
Shipping †
NUS3055MUTAG
TLLGA8
(Pb−Free)
3000 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Publication Order Number:
NUS3055/D
NUS3055MUTAG
Schottky
Diode
AC/DC Adapter of
Accessory Charger
VCC
SRC
DRAIN
P−CH
IN
Undervoltage
Lock Out
+
Logic
−
GATE
+
C1
FET
Driver
LOAD
OUT
Vref
NUS3055
CNTRL
GND
Microprocessor Port
Figure 1. Simplified Schematic
PIN FUNCTION DESCRIPTIONS
Pin #
Symbol
Pin Description
1
IN
This pin senses an external voltage point. If the voltage on this input rises above the overvoltage threshold
(VTH), the OUT pin will be driven to within 1.0 V of VCC, thus disconnecting the P−Channel Power MOSFET. The
nominal threshold level is 6.85 V and this threshold level can be increased with the addition of an external
resistor between IN and VCC.
2
GND
3
CNTRL
This logic signal is used to control the state of OUT and turn−on/off the P−Channel Power MOSFET. A logic High
results in the OUT signal being driven to within 1.0 V of VCC which disconnects the FET. If this pin is not used,
the input should be connected to ground.
4
DRAIN
Drain pin of the P−Channel Power MOSFET
Circuit Ground
5
SRC
Source pin of the P−Channel Power MOSFET
6
GATE
Gate pin of the P−Channel Power MOSFET
7
OUT
This signal drives the gate of a P−Channel Power MOSFET. It is controlled by the voltage level on IN or the logic
state of the CNTRL input. When an overvoltage event is detected, the OUT pin is driven to within 1.0 V of VCC in
less than 1.0 _sec provided that gate and stray capacitance is less than 12 nF.
8
VCC
Positive Voltage supply. If VCC falls below 2.8 V (nom), the OUT pin will be driven to within 1.0 V of VCC, thus
disconnecting the P−channel FET.
OVERVOLTAGE PROTECTION CIRCUIT TRUTH TABLE
IN
CNTRL
OUT
<Vth
L
GND
<Vth
H
VCC
>Vth
L
VCC
>Vth
H
VCC
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2
NUS3055MUTAG
MAXIMUM RATINGS (TA = 25°C unless otherwise stated)
Rating
Pin
Symbol
Min
Max
Unit
OUT Voltage to GND
7
VO
−0.3
30
V
Input and CNTRL Pin Voltage to GND
1
3
Vinput
VCNTRL
−0.3
−0.3
30
13
V
VCC Maximum Range
8
VCC(max)
−0.3
30
V
Maximum Power Dissipation (Note 1)
−
PD
−
1.0
W
−
RθJA
−
342
124
°C/W
Junction Temperature
−
TJ
−
150
°C
Operating Ambient Temperature
−
TA
−40
85
°C
VCNTRL Operating Voltage
3
−
0
5.0
V
−
Tstg
−65
150
°C
1, 2, 3, 7, 8
−
2.5
−
kV
−30
V
20
V
−1.0
A
Thermal Resistance Junction−to−Air (Note 1)
OVP IC
P−Channel FET
Storage Temperature Range
ESD Performance (HBM) (Note 2)
Drain−to−Source Voltage
VDSS
Gate−to−Source Voltage
VGS
Continuous Drain Current, Steady State, TA = 25°C (Note 1)
ID
−20
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Surface−mounted on FR4 board using 1 inch sq pad size (Cu area = 1.127 in sq [1 oz] including traces).
2. Human body model (HBM): MIL STD 883C Method 3015−7, (R = 1500 W, C = 100 pF, F = 3 pulses delay 1 s).
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NUS3055MUTAG
ELECTRICAL CHARACTERISTICS (TA= 25°C, Vcc = 6.0 V, unless otherwise specified)
Characteristic
Symbol
Pin
Min
VCC(opt)
8
3.0
4.8
25
V
−
1, 8
−
0.75
1.0
mA
Input Threshold (VInput connected to VCC; VInput increasing)
VTh
1
6.65
6.85
7.08
V
Input Hysteresis (VInput connected to VCC; VInput decreasing)
VHyst
1
50
100
200
mV
Input Impedance (Input = VTh)
Rin
1
70
150
−
kW
CNTRL Voltage High
Vih
3
1.5
−
−
V
CNTRL Voltage Low
Vil
3
−
−
0.5
V
CNTRL Current High (Vih = 5.0 V)
Iih
3
−
95
200
mA
CNTRL Current Low (Vil = 0.5 V)
Iil
3
−
10
20
mA
Undervoltage Lockout (VCC decreasing)
VLock
3
2.5
2.8
3.0
V
Output Sink Current (VCC < VTh, VOUT = 1.0 V)
ISink
7
10
33
50
mA
Output Voltage High (VCC = Vin = 8.0 V; ISource = 10 mA)
Output Voltage High (VCC = Vin = 8.0 V; ISource = 0.25 mA)
Output Voltage High (VCC = Vin = 8.0 V; ISource = 0 mA)
Voh
7
VCC−1.0
VCC−0.25
VCC−0.1
−
−
V
Output Voltage Low
(Input < 6.5 V; ISink = 0 mA; VCC = 6.0 V, CNTRL = 0 V)
Vol
7
−
−
0.1
V
Turn ON Delay − Input (Note 3)
(VInput connected to VCC; VInput step down signal from 8.0 to
6.0 V; measured to 50% point of OUT)*
TON IN
7
−
−
10
ms
Turn OFF Delay − Input (VInput connected to VCC; VInput step
up signal from 6.0 to 8.0 V; CL = 12 nF Output > VCC − 1.0 V)
TOFF IN
7
−
0.5
1.0
ms
Turn ON Delay − CNTRL (CNTRL step down signal from 2.0
to 0.5 V; measured to 50% point of OUT) (Note 3)
TON CT
7
−
−
10
ms
Turn OFF Delay − CNTRL (CNTRL step up signal from 0.5 to
2.0 V; CL = 12 nF Output > VCC −1.0 V)
TOFF CT
7
−
1.0
2.0
ms
Min
Typ
Max
Units
66
66
110
110
VCC Operating Voltage Range
Supply Current (ICC + IInput; VCC = 6.0 V Steady State)
Typ
Max
Unit
3. Guaranteed by design.
P−CHANNEL MOSFET (TA= 25°C unless otherwise specified)
Parameter
Symbol
Drain to Source On Resistance
(VGS = −4.5 V, ID = 600 mA)
(VGS = −4.5 V, ID = 1.0 A)
RDS(on)
Zero Gate Voltage Drain Current
(VGS = 0 V, VDS = −24 V)
IDSS
mW
mA
−1.0
Turn On Delay (Note 4)
(VGS = −4.5 V, ID = −1.0 A, RG = 6.0 W, VDS = 15 V)
ton
Turn Off Delay (Note 4)
(VGS = −4.5 V, ID = −1.0 A, RG = 6.0 W, VDS = 15 V)
toff
Input Capacitance (Note 3)
(VGS = 0 V, f = 1.0 MHz, VDS = −15 V)
Cin
ns
11
ns
28
pF
750
Gate to Source Leakage Current
(VGS = ±20 V, VDS = 0 V)
IGSS
nA
±10
Drain to Source Breakdown Voltage
(VGS = 0 V, ID = −250 mA)
V(BR)DSS
V
30
Gate Threshold Voltage
(VGS = VDS, ID = −250 mA)
V(GS)th
V
−3.0
4. Switching characteristics are independent of operating junction temperature.
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4
−1.0
NUS3055MUTAG
TYPICAL PERFORMANCE CURVES
(TA= 25°C, unless otherwise specified)
OVERVOLTAGE PROTECTION IC
7.05
1.0
7.00
0.9
I supply (mA)
Voltage (V)
6.95
6.90
6.85
0.8
0.7
6.80
0.6
6.75
6.70
−40
−25
−10
5
20
35
50
65
80
0.5
−40
95
−25
−10
5
20
35
50
65
80
95
Temperature (°C)
Ambient Temperature (°C)
Figure 2. Typical Vth Threshold Variation vs.
Temperature
Figure 3. Typical Supply Current vs. Temperature
Icc ) Iin, VCC + 6 V
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NUS3055MUTAG
TYPICAL PERFORMANCE CURVES
(TA= 25°C, unless otherwise specified)
−ID, DRAIN CURRENT (AMPS)
12
−4.5 V −4.2 V
−10V
11
10
9
RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)
30 V, P−CHANNEL MOSFET
−4 V
−8 V
−6 V
8
7
−3.8 V
−5.5 V
−5 V
6
−3.6 V
5
4
3
−3.4 V
−3.2 V
2
1
0
−3 V
TJ = 25°C
0
0.4
0.8
1.2
1.6
2
2.4
2.8
3.2
3.6
4
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
TJ = 25°C
ID = −3.7 A
0.2
0.1
0
2
3
5
6
7
8
9
10
−VGS, GATE VOLTAGE (VOLTS)
Figure 4. On−Region Characteristics
Figure 5. On−Resistance vs. Gate−to−Source
Voltage
100000
10
−IS, SOURCE CURRENT (AMPS)
VGS = 0 V
−IDSS, LEAKAGE CURRENT (nA)
4
TJ = 150°C
10000
1000
TJ = 100°C
100
5
10
15
20
25
−VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
VGS = 0 V
TJ = 150°C
1
TJ = 100°C
TJ = 25°C
0.1
0.3
30
TJ = −55°C
0.4
0.5
0.6
0.7
0.8
0.9
1.0
−VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 7. Diode Forward Voltage vs. Current
Figure 6. Drain−to−Source Leakage Current
vs. Voltage
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1.1
NUS3055MUTAG
TYPICAL APPLICATION CIRCUITS & OPERATION WAVEFORMS
(TA= 25°C, unless otherwise specified)
VCC
P−CH
IN
Undervoltage
Lock Out
+
Logic
−
GATE
12 W
FET
Driver
OUT
Vref
6 Vdc
8 Vdc
NUS3055
GND
CNTRL
Figure 8. Test Circuit for TON IN and TOFF IN
Input Voltage
TON IN
Output Voltage
TON IN Test
TA=25°C
Figure 9. TON IN Waveforms
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7
NUS3055MUTAG
TOFF IN
Input Voltage
TOFF IN Test
TA=25°C
Output Voltage
Figure 10. TOFF IN Waveforms
VCC
P−CH
IN
Undervoltage
Lock Out
+
Logic
−
GATE
12 W
FET
Driver
OUT
Vref
6 Vdc
8 Vdc
NUS3055
GND
CNTRL
Figure 11. Test Circuit for TON CT and TOFF CT
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8
NUS3055MUTAG
TON CT
CNTR signal
Input Voltage
TON CT Test
TA=25°C
Output Voltage
Figure 12. TON CT Waveforms
TOFF CT
CNTR signal
Input Voltage
TOFF CT Test
TA=25°C
Output Voltage
Figure 13. TOFF CT Waveforms
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NUS3055MUTAG
PACKAGE DIMENSIONS
LLGA8 3x2.5, 0.65P
CASE 517AH
ISSUE A
PIN ONE
REFERENCE
2X
0.10 C
2X
ÉÉÉ
ÉÉÉ
ÉÉÉ
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND
0.20mm FROM TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
A B
D
E
DIM
A
A1
b
b2
D
D2
E
E2
e
G
K
L
TOP VIEW
A
0.10 C
6X
0.08 C
MILLIMETERS
MIN
MAX
0.50
0.60
0.00
0.05
0.35
0.45
0.45
0.55
3.00 BSC
1.25
1.35
2.50 BSC
1.55
1.65
0.65 BSC
0.05 REF
0.15 REF
0.35
0.45
SIDE VIEW
A1
C
SEATING
PLANE
SOLDERING FOOTPRINT*
G
D2
2.80
b2
4X
K
1
4
e
E2
8
8X
5
L
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
1
0.55
8X
BOTTOM VIEW
b
0.10 C A B
0.05 C
1.35
NOTE 3
8X
0.45
0.45
7X
0.03
0.65
PITCH
1.50
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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Phone: 81−3−5773−3850
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ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NUS3055/D
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