HIP6501 - Digchip

HIP6501 - Digchip
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HIP6501
®
Triple Linear Power Controller with ACPI
Control Interface
The HIP6501, paired with either the HIP6020 or HIP6021,
simplifies the implementation of ACPI-compliant designs in
microprocessor and computer applications. The IC
integrates two linear controllers and a low-current pass
transistor, as well as the monitoring and control functions
into a 16-pin SOIC package. One linear controller generates
the 3.3VDUAL voltage plane from an ATX power supply’s
5VSB output during sleep states (S3, S4/S5), powering the
PCI slots through an external pass transistor, as instructed
by the status of the 3.3VDUAL enable pin. An additional pass
transistor is used to switch in the ATX 3.3V output for PCI
operation during S0 and S1 (active) operating states. The
second linear controller supplies the computer system’s
2.5V/3.3V memory power through an external pass
transistor in active states. During S3 state, an integrated
pass transistor supplies the 2.5V/3.3V sleep-state power. A
third controller powers up a 5VDUAL plane by switching in
the ATX 5V output in active states, or the ATX 5VSB in sleep
states.
The HIP6501’s operating mode (active-state outputs or
sleep-state outputs) is selectable through two control pins:
S3 and S5. Further control of the logic governing activation
of different power modes is offered through two enabling
pins: EN3VDL and EN5VDL. In active states, the 3.3VDUAL
linear regulator uses an external N-Channel pass MOSFET
to connect the output (VOUT1) directly to the 3.3V input
supplied by an ATX (or equivalent) power supply, while
incurring minimal losses. In sleep state, the 3.3VDUAL output
is supplied from the ATX 5VSB through an NPN transistor,
also external to the controller. Active state power delivery for
the 2.5/3.3VMEM output is done through an external NPN
transistor, or an NMOS switch for the 3.3V setting. In sleep
states, conduction on this output is transferred to an internal
pass transistor. The 5VDUAL output is powered through two
external MOS transistors. In sleep states, a PMOS (or PNP)
transistor conducts the current from the ATX 5VSB output,
while in active states, current flow is transferred to an NMOS
transistor connected to the ATX 5V output. Similar to the
3.3VDUAL output, the operation of the 5VDUAL output is
dictated not only by the status of the S3 and S5 pins, but that
of the EN5VDL pin as well.
February 2000
File Number
4748.2
Features
• Provides 3 ACPI-Controlled Voltages
- 5V Active/Sleep (5VDUAL)
- 3.3V Active/Sleep (3.3VDUAL)
- 2.5V/3.3V Active/Sleep (2.5VMEM)
• Simple Control Design - No Compensation Required
• Excellent Output Voltage Regulation
- 3.3VDUAL Output: ±2.0% Over Temperature; Sleep
States Only
- 2.5V/3.3V Output: ±2.0% Over Temperature; Both
Operational States (3.3V setting in sleep only)
• Fixed Output Voltages Require No Precision External
Resistors
• Small Size
- Small External Component Count
• Selectable 2.5VMEM Output Voltage Via FAULT/MSEL Pin
- 2.5V for RDRAM Memory
- 3.3V for SDRAM Memory
• Under-Voltage Monitoring of All Outputs with Centralized
FAULT Reporting
• Adjustable Soft-Start Function Eliminates 5VSB
Perturbations
Applications
• Motherboard Power Management for Computers
Pinout
HIP6501 (SOIC)
TOP VIEW
5VSB 1
EN3VDL 2
3V3DLSB 3
3V3DL 4
EN5VDL 5
S3 6
S5
7
GND 8
16 VSEN2
15 DRV2
14 12V
13 SS
12 5VDL
11 5VDLSB
10 DLA
9
FAULT/MSEL
Ordering Information
PART NUMBER
HIP6501CB
HIP6501EVAL1
TEMP.
RANGE (oC)
0 to 70
PACKAGE
16 Ld SOIC
PKG.
NO.
M16.15
Evaluation Board
10
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
11
5VDL
FAULT/MSEL
12V BIAS
0.2V
-
-
+
+
-
UV COMPARATOR
-
+
+
UV DETECTOR
EA4
10µA
MEM VOLTAGE
SELECT COMP
3V3DLSB
12V MONITOR
10.8V/9.0V
40µA
3.75V
12V
-
+
Block Diagram
SS
5VSB
EN3VDL
S5
EN5VDL
FIGURE 1.
S3
-
+
1.265V
GND
TO
UV DETECTOR
5VSB POR
4.5V/4.0V
MONITOR AND CONTROL
3V3DL
EA2
+
TEMPERATURE
MONITOR
(TMON)
TO 12V
VSEN2
DRV2
5VDLSB
DLA
HIP6501
HIP6501
Simplified Power System Diagram
+5VIN
+12VIN
+5VSB
+3.3VIN
Q1
LINEAR
CONTROLLER
2.5VMEM
Q2
LINEAR
CONTROLLER
Q3
HIP6501
Q4
3.3VDUAL
Q5
CONTROL
LOGIC
FAULT
5VDUAL
SHUTDOWN
S3
S5
EN5VDL
EN3VDL
FIGURE 2.
Typical Application
+5VIN
+12VIN
+5VSB
+3.3VIN
12V
5VSB
DRV2
3V3DLSB
Q2
VSEN2
Q3
VOUT1
Q1
VOUT2
3V3DL
3.3VDUAL
COUT1
2.5/3.3VMEM
COUT2
FAULT/MSEL
RSEL
HIP6501
FAULT
Q4
S3
SLP_S3
5VDLSB
S5
SLP_S5
DLA
Q5
EN5VDL
EN5VDL
SS
COUT3
CSS
SHUTDOWN
GND
FIGURE 3.
12
VOUT3
5VDL
EN3VDL
EN3VDL
5VDUAL
HIP6501
Absolute Maximum Ratings
Thermal Information
Supply Voltage, V5VSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
12V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +14.5V
DLA, DRV2 . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to V12V +0.3V
All Other Pins . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 5VSB + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 3 [5kV]
Thermal Resistance (Typical, Note 1)
Recommended Operating Conditions
θJA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
Supply Voltage, V5VSB . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±±5%
Secondary Bias Voltage, V12V . . . . . . . . . . . . . . . . . . +12V ±±10%
Digital Inputs, VS3, VS5, VEN3VDL, VEN5VDL . . . . . . . . . .0 to +5.5V
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Junction Temperature Range . . . . . . . . . . . . . . . . . . . 0oC to 125oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted; Refer to Figures 1, 2 and 3
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
20
-
mA
-
10
-
mA
Rising 5VSB POR Threshold
-
-
4.5
V
5VSB POR Hysteresis
-
0.2
-
V
Rising 12V Threshold
-
-
10.8
V
Soft-Start Current
-
10
-
µA
Shutdown Soft-Start Voltage
-
-
0.8
V
-
-
2.0
%
VCC SUPPLY CURRENT
Operating Supply Current
I5VSB
Shutdown Supply Current
I5VSB(OFF)
VSS = 0.8V, S3 = 0, S5 = 0
POWER-ON RESET, SOFT-START, AND 12V MONITOR
2.5V/3.3V LINEAR REGULATOR (VOUT2)
Regulation
VSEN2 Nominal Voltage Level
VVSEN2
RSEL = 1kΩ
-
2.5
-
V
VSEN2 Nominal Voltage Level
VVSEN2
RSEL = 10kΩ
-
3.3
-
V
VSEN2 Undervoltage Rising Threshold
-
75
-
%
VSEN2 Undervoltage Hysteresis
-
6
-
%
VSEN2 Output Current
IVSEN2
5VSB = 5V
250
300
-
mA
DRV2 Output Drive Current
IDRV2
5VSB = 5V, RSEL = 1kΩ
20
30
-
mA
-
200
-
Ω
-
-
2.0
%
-
3.3
-
V
-
2.450
-
V
RSEL = 10kΩ
DRV2 Output Impedance
3.3VDUAL LINEAR REGULATOR (VOUT1)
Sleep-Mode Regulation
3V3DL Nominal Voltage Level
V3V3DL
3V3DL Undervoltage Rising Threshold
13
HIP6501
Electrical Specifications
Recommended Operating Conditions, Unless Otherwise Noted; Refer to Figures 1, 2 and 3 (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
200
-
mV
5.0
8.5
-
mA
-
90
-
Ω
5VDL Undervoltage Rising Threshold
-
3.750
-
V
5VDL Undervoltage Hysteresis
-
260
-
mV
-20
-
-40
mA
-
350
-
Ω
40
50
60
ms
Maximum Allowable S3 to S5 Skew
-
2
-
µs
5VSB POR Extension Past Threshold Voltage
-
3.3
-
ms
-
-
2.2
V
0.8
-
-
V
-
70
-
kΩ
-
100
-
Ω
-
10
-
µs
3V3DL Undervoltage Hysteresis
3V3DLSB Output Drive Current
I3V3DLSB
5VSB = 5V
DLA Output Impedance
5VDUAL SWITCH CONTROLLER (VOUT3)
5VDLSB Output Drive Current
I5VDLSB
5VDLSB = 4V
5VDLSB Pull-UP Impedance to 5VSB
TIMING INTERVALS
Active State Assessment Past 12V Threshold
Note 2
CONTROL I/O (S3, S5, EN3VDL, EN5VDL, FAULT)
High Level Threshold
Low Level Threshold
S3, S5 Internal Pull-up Impedance to 5VSB
FAULT Output Impedance
FAULT = high
FAULT Undervoltage Reporting Delay
TEMPERATURE MONITOR
Fault-Level Threshold
Note 3
125
-
-
oC
Shutdown-Level Threshold
Note 3
-
150
-
oC
NOTES:
2. Guaranteed by Correlation.
3. Guaranteed by Design.
Functional Pin Description
5VSB (Pin 1)
S3 and S5 (Pins 6 and 7)
Provide a 5V bias supply for the IC to this pin by connecting
it to the ATX 5VSB output. This pin also provides the base
bias current for all the external NPN transistors controlled by
the IC. The voltage at this pin is monitored for power-on
reset (POR) purposes.
These pins switch the IC’s operating state from active (S0, S1)
to S3 and S4/S5 sleep states. Connect S3 to SLP_S3 and S5
to SLP_S5. These are digital inputs featuring internal 70kΩ
(typical) resistor pull-ups to 5VSB. Internal circuitry de-glitches
the S3 pin for disturbances and skews lasting as long as 2µs
(typical). Additional circuitry blocks any illegal state transitions
(such as S3 to S4/S5 or vice versa). When entering an S4/S5
sleep state, the S3 and S5 signals have to go low within less
than 0.5µs of each other. If transition to S4/S5 sleep state is
signaled by the SLP_S3 signal going low first, then followed by
the SLP_S5 signal going low, then an RC delay circuit needs be
inserted in line with the S3 pin (see Typical Application diagram).
GND (Pin 8)
Signal ground for the IC. All voltage levels are measured
with respect to this pin.
14
HIP6501
EN3VDL and EN5VDL (Pins 2 and 5)
3V3DL (Pin 4)
These pins control the logic governing the output behavior in
response to S3 and S4/S5 requests. These are digital inputs
whose status can only be changed during active states
operation or during chip shutdown (SS pin grounded by
external open-drain device). The input information is
latched-in when entering a sleep states, as well as following
5VSB POR release or exit from shutdown.
Connect this pin to the 3.3V dual output (VOUT1). In sleep
states, the voltage at this pin is regulated to 3.3V; in active
states, ATX 3.3V output is delivered to this node through a
fully on N-MOS transistor. During all operating states, this
pin is monitored for under-voltage events.
FAULT/MSEL (Pin 9)
This is a multiplexed function pin allowing the setting of the
memory output voltage to either 2.5V or 3.3V (for RDRAM or
SDRAM memory systems). The memory voltage setting is
latched-in 3ms (typically) after 5VSB POR release. In case
of an under-voltage on any of the outputs or an overtemperature event, this pin is used to report the fault
condition by being pulled to 5VSB.
SS (Pin 13)
Connect a small ceramic capacitor (allowable range: 5nF0.22µF; 0.1µF recommended) from this pin to GND. The
internal soft-start (SS) current source along with the external
capacitor creates a voltage ramp used to control the rampup of the output voltages. Pulling this pin low with an opendrain device shuts down all the outputs as well as forces the
FAULT pin low. The CSS capacitor is also used to provide a
controlled voltage slew rate during active-to-sleep transitions
on the 3.3VDUAL and 2.5/3.3VMEM outputs.
3V3DLSB (Pin 3)
Connect this pin to the base of a suitable NPN transistor. In
sleep states, this transistor is used to regulate the voltage at
the 3V3DL pin to 3.3V.
DLA (Pin 10)
Connect this pin to the gates of suitable N-MOSFETs, which
in active states, are used to switch in the ATX 3.3V and 5V
outputs into the 3.3VDUAL and 5VDUAL outputs, respectively.
5VDL (Pin 12)
Connect this pin to the 5VDUAL output (VOUT3). In either
operating state, the voltage at this pin is provided through a
fully on MOS transistor. This pin is also monitored for undervoltage events.
5VDLSB (Pin 11)
Connect this pin to the gate of a suitable P-MOSFET or bipolar
PNP. In sleep states, this transistor is switched on, connecting
the ATX 5VSB output to the 5VDUAL regulator output.
Description
12V (Pin 14)
Operation
Connect this pin to the ATX (or equivalent) 12V output. This
pin is used to monitor the status of the power supply as well
as provide bias for the NMOS-compatible output drivers.
12V presence at the chip in the absence of bias voltage, or
severe 12V brownout during active states (S0, S1) operation
can lead to chip misbehavior.
The HIP6501 controls 3 output voltages (refer to Figures 1, 2,
and 3). It is designed for microprocessor computer applications
with 3.3V, 5V, 5VSB, and 12V outputs from an ATX power
supply. The IC is composed of two linear controllers supplying
the PCI slots’ 3.3VAUX power (3.3VDUAL, VOUT1) and the 2.5V
RDRAM or 3.3V SDRAM memory power (2.5/3.3VMEM,
VOUT2), and a dual switch controller supplying the 5VDUAL
voltage (VOUT3) In addition, all the control and monitoring
functions necessary for complete ACPI implementation are
integrated into the HIP6501.
VSEN2 (Pin 16)
Connect this pin to the memory output (VOUT2). In sleep
states, this pin is regulated to 2.5V or 3.3V (based on RSEL)
through an internal pass transistor capable of delivering
300mA (typically). When VOUT2 is programmed to 2.5V , the
active-state voltage at this pin is regulated through an
external NPN transistor connected at the DRV2 pin. For the
3.3V setting, the ATX 3.3V is passed to this pin through a
fully on N-MOS transistor. During all operating states, the
voltage at this pin is monitored for under-voltage events.
DRV2 (Pin 15)
For the 2.5V RDRAM systems connect this pin to the base of
a suitable NPN transistor. This pass transistor regulates the
2.5V output from the ATX 3.3V during active states
operation. For 3.3V SDRAM systems connect this pin to the
gate of a suitable N-MOS transistor; this transistor is used to
switch in the ATX 3.3V output.
15
Initialization
The HIP6501 automatically initializes upon receipt of input
power. The Power-On Reset (POR) function continually
monitors the 5VSB input supply voltage, initiating soft-start
operation after it exceeds its POR threshold (in either S3 or
S4/S5 states). To insure stabilization of the 5VSB supply
before operation is allowed, POR is released 3.3ms
(typically) after 5VSB exceeds the POR threshold. The
5VSB POR trip event is also used to lock in the memory
voltage setting based on RSEL.
Operational Truth Tables
The EN3VDL and EN5VDL pins offer a host of choices in
terms of the overall system architecture and supported
features. Tables 1-3 describe the truth combinations
pertaining to each of the three outputs.
HIP6501
TABLE 1. 3.3VDUAL OUTPUT (VOUT1) TRUTH TABLE
COMMENTS
As seen in Table 3, 2.5/3.3VMEM output is maintained in S3
(Suspend-To-RAM), but not in S4/S5 state. The dual-voltage
support accommodates both SDRAM as well as RDRAM
type memories.
EN3VDL
S5
S3
3V3DL
0
1
1
3.3V
S0, S1 STATES (active)
0
1
0
3.3V
S3
0
0
1
Note 4
0
0
0
3.3V
S4/S5
1
1
1
3.3V
S0, S1 STATES (active)
1
1
0
3.3V
S3
Functional Timing Diagrams
1
0
1
Note 4
Maintains previous state
1
0
0
0V
Figures 4-8 are timing diagrams, detailing the power
up/down sequences of all three outputs in response to the
status of the enable (EN3VDL, EN5VDL) and sleep-state
pins (S3, S5), as well as the status of the ATX supply.
Maintains previous state
S4/S5
NOTE:
4. Combination not allowed.
As seen in Table 1, EN3VDL simply controls whether the
3.3VDUAL plane remains powered up during S4/S5 sleep
state.
TABLE 2. 5VDUAL OUTPUT (VOUT3) TRUTH TABLE
EN5VDL
S5
S3
5VDL
COMMENTS
0
1
1
5V
S0, S1 STATES (active)
0
1
0
0V
S3
0
0
1
Note 5
0
0
0
0V
S4/S5
1
1
1
5V
S0, S1 STATES (active)
1
1
0
5V
S3
1
0
1
Note 5
1
0
0
5V
Maintains previous state
Maintains previous state
S4/S5
NOTE:
Additionally, the internal circuitry does not allow the
transition from an S3 (suspend to RAM) state to an S4/S5
(suspend to disk/soft off) state or vice versa. The only ‘legal’
transitions are from an active state (S0, S1) to a sleep state
(S3, S4/S5) and vice versa.
The status of the EN3VDL and EN5VDL pins can only be
changed while in active (S0, S1) states, when the bias
supply (5VSB pin) is below POR level, or during chip
shutdown (SS pin shorted to GND); a status change of these
two pins while in a sleep state is ignored.
Not shown in these diagrams is the de-glitching feature used
to protect against false sleep state tripping. Once the status
of the S3 pin changes from high to low, the S5 pin’s status is
evaluated and the chip transitions to the new state. If at the
end of the filtering period (minimum 0.5µs) the configuration
requested does not represent an illegal state transition (such
as from S3 to S4/S5 or vice versa), then the controller
transitions to the new configuration. Otherwise, the
previously attained valid state is maintained until valid
control signals are received from the system. This particular
feature is useful in noisy computer environments if the
control signals have to travel over significant distances.
5. Combination not allowed.
Very similarly, Table 2 details the fact that EN5VDL status
controls whether the 5VDUAL plane supports sleep states.
TABLE 3. 2.5/3.3VMEM OUTPUT (VOUT2) TRUTH TABLE
RSEL
S5
S3
2.5/3.3VMEM
COMMENTS
1kΩ
1
1
2.5V
S0, S1 STATES (active)
1kΩ
1
0
2.5V
S3
1kΩ
0
1
Note 6
1kΩ
0
0
0V
10kΩ
1
1
3.3V
S0, S1 STATES (active)
10kΩ
1
0
3.3V
S3
10kΩ
0
1
Note 6
10kΩ
0
0
0V
NOTE:
6. Combination not allowed.
16
Maintains previous state
S4/S5
5VSB
S3
S5
12V
3V3DLSB
DLA
3V3DL
5VDLSB
5VDL
Maintains previous state
S4/S5
FIGURE 4. 3VDUAL AND 5VDUAL TIMING DIAGRAM FOR
EN3VDL = 1, EN5VDL = 1
HIP6501
5VSB
5VSB
S3
S3
S5
S5
12V
12V
3V3DLSB
INTERNAL
VSEN2
DEVICE
DLA
DRV2
3V3DL
VSEN2
5VDLSB
FIGURE 8. 2.5/3.3VMEM TIMING DIAGRAM
5VDL
FIGURE 5. 3VDUAL AND 5VDUAL TIMING DIAGRAM FOR
EN3VDL = 1, EN5VDL = 0
Soft-Start Circuit
SOFT-START INTO SLEEP STATES (S3, S4/S5)
The 5VSB POR function initiates the soft-start sequence.
An internal 10µA current source charges an external
capacitor to 5V. The error amplifiers reference inputs are
clamped to a level proportional to the SS (soft-start) pin
voltage. As the SS pin voltage slews from about 1.25V to
2.5V, the input clamp allows a rapid and controlled output
voltage rise.
5VSB
S3
S5
12V
3V3DLSB
DLA
3V3DL
5VDLSB
5VDL
FIGURE 6. 3VDUAL AND 5VDUAL TIMING DIAGRAM FOR
EN3VDL = 0, EN5VDL = 1
5VSB
S3
S5
12V
3V3DLSB
DLA
3V3DL
5VDLSB
5VDL
FIGURE 7. 3VDUAL AND 5VDUAL TIMING DIAGRAM FOR
EN3VDL = 0, EN5VDL = 0
17
Figure 9 shows the soft-start sequence for the typical
application start-up in a sleep state with all output voltages
enabled. At time T0 5VSB (bias) is applied to the circuit. At
time T1, 5VSB surpasses POR level, and an internal fast
charge circuit quickly raises the SS capacitor voltage to
approximately 1V. At this point, the 10µA current source
continues the charging up to T2, where a voltage of 1.25V
(typically) is reached and an internal clamp limits further
charging. Clamping of the soft-start voltage (T2 to T3
interval) should only be noticed with capacitors smaller than
0.1µF; soft-start capacitors of 0.1µF and above should
present a soft-start ramp void of this plateau. At time T3,
3ms (typically) past the 5VSB POR (T1), the memory output
voltage selection is latched in and the charging of the softstart capacitor resumes, using the 10µA current source. At
this point, the error amplifiers’ reference inputs are starting
their transitions, causing the output voltages to ramp up
proportionally. The ramping continues until time T4 when all
the voltages reach the set value. At time T5, when the softstart capacitor value reaches approximately 2.8V, the undervoltage monitoring circuits are activated and the soft-start
capacitor is quickly discharged down to the value attained at
time T2 (approximately 1.25V).
HIP6501
5VSB
(1V/DIV)
SOFT-START
(1V/DIV)
ramped-up, reaching regulation limits at time T3.
Simultaneous with the memory voltage ramp-up, the DLA
pin is pulled high (to 12V), turning on Q3 and Q5, and
bringing the 3.3VDUAL and 5VDUAL outputs in regulation at
time T2. At time T4, when the soft-start voltage reaches
approximately 2.8V, the under-voltage monitoring circuits
are enabled and the soft-start capacitor is quickly discharged
to approximately 2.45V.
UV DETECT ENABLE
(LOGIC LEVEL)
0V
+12VIN
OUTPUT
VOLTAGES
(1V/DIV)
VOUT1 (3.3VDUAL)
DLA PIN
(2V/DIV)
INPUT VOLTAGES
(2V/DIV)
VOUT3 (5VDUAL)
+5VIN
+5VSB
+3.3VIN
VOUT2 (2.5VMEM)
SOFT-START
(1V/DIV)
0V
0V
T0
T1 T2 T3
OUTPUT
VOLTAGES
(1V/DIV) VOUT3 (5VDUAL)
T4 T5
TIME
FIGURE 9. SOFT-START INTERVAL IN A SLEEP STATE (ALL
OUTPUTS ENABLED)
VOUT1 (3.3VDUAL)
VOUT2 (2.5VMEM)
SOFT-START INTO ACTIVE STATES (S0, S1)
If both S3 and S5 are logic high at the time the 5VSB is
applied, the HIP6501 will assume an active state and keep
off the controlled external transistors until about 50ms after
the ATX’s 12V output (sensed at the 12V pin) exceeds the
set threshold (typically 10.8V). This timeout feature is
necessary in order to insure the main ATX outputs are
stabilized. The timeout also assures smooth transitions from
sleep into active when sleep states are being supported.
During sleep to active state transitions from conditions
where the outputs are initially 0V (such as S4/S5 to S0
transition with EN3VDL = 1 and EN5VDL = 0, or simple
power-up sequence directly into active state), the 3VDUAL
and 5VDUAL outputs go through a quasi soft-start by being
pulled high through the body diodes of the N-Channel
MOSFETs connected between these outputs and the 3.3V
and 5V ATX outputs, respectively. Figure 10 shows this
start-up scenario.
5VSB is already present when the main ATX outputs are
turned on at time T0. Similarly, the soft-start capacitor has
already been charged up to 1.25V and the clamp is active,
awaiting for the 12V POR timer to expire. As a result of
3.3VIN and 5VIN ramping up, the 3.3VDUAL and 5VDUAL
output capacitors charge up through the body diodes of Q3
and Q5, respectively (see Figure 3). At time T1, the 12V ATX
output exceeds the HIP6501’s 12V under-voltage threshold,
and the internal 50ms (typical) timer is initiated. At T2 the
time-out initiates a soft-start, and the memory output is
18
0V
T0
T1
T2
T3 T4
TIME
FIGURE 10. SOFT-START INTERVAL IN AN ACTIVE STATE
Requests to go into a sleep state during an active state softstart ramp-up result in a chip reset, followed by a new softstart sequence into the desired state.
Fault Protection
All the outputs are monitored against under-voltage events.
A severe over-current caused by a failed load on any of the
outputs, would, in turn, cause that specific output to
suddenly drop. If any of the output voltages drop below 69%
of their set value, such event is reported by having the
FAULT/MSEL pin pulled to 5V. Additionally, the 2.5/3.3V
memory regulator is internally current limited while in a sleep
state. Exceeding the maximum current rating of this output in
a sleep state can lead to output voltage drooping. If
excessive, this droop can ultimately trip the under-voltage
detector and send a FAULT signal to the computer system.
However, a FAULT condition will only set off the FAULT flag,
and it will not shut off or latch off any part of the circuit. If
shutdown or latch off of the circuit is desired, this can be
achieved by externally pulling or latching the SS pin low.
HIP6501
Pulling the SS pin low will also force the FAULT pin to go
low.
Undervoltage sensing is disabled on all disabled outputs
and during soft-start ramp-up intervals. SS voltage
reaching the 2.8V threshold signals activation of the undervoltage monitor.
Another condition that could set off the FAULT flag is chip
over-temperature. If the HIP6501 reaches an internal
temperature of 125oC (minimum), the FAULT flag is set
(FAULT/MSEL pulled high), but the chip continues to
operate until the temperature reaches 150oC (typical), when
unconditional latched shutdown of all outputs takes place.
The thermal latch can be reset only by cycling the 5VSB off,
and then on.
Output Voltages
The output voltages are internally set and do not require any
external components. Selection of the memory voltage is
done by means of an external resistor connected between
the FAULT/MSEL pin and ground. An internal 40µA (typical)
current source creates a voltage drop across this resistor.
During every 5VSB trip above POR level, this voltage is
compared with an internal reference (200mV typically).
Based on this comparison, the output voltage is set at either
2.5V (RSEL = 1kΩ), or 3.3V (RSEL = 10kΩ). It is very
important that no capacitor is connected to the
FAULT/MSEL pin; the presence of a capacitive element at
this pin can lead to false memory voltage selection. See
Figure 11 for details.
FAULT/MSEL
MEM VOLTAGE
SELECT COMP
RSEL
+
40µA
RSEL
VMEM
1kΩ
2.5V
10kΩ
3.3V
+
-
0.2V
FIGURE 11. 2.5/3.3VMEM OUTPUT VOLTAGE SELECTION
CIRCUITRY DETAILS
Application Guidelines
Soft-Start Interval
The 5VSB output of a typical ATX supply is capable of
725mA. During power-up in a sleep state, it needs to provide
sufficient current to charge up all the output capacitors and
simultaneously provide some amount of current to the output
loads. Drawing excessive amounts of current from the 5VSB
19
output of the ATX can lead to voltage collapse and induce a
pattern of consecutive restarts with unknown effects on the
system’s behavior or health.
The built-in soft-start circuitry allows tight control of the slewup speed of the output voltages controlled by the HIP6501,
thus enabling power-ups free of supply drop-off events.
Since the outputs are ramped up in a linear fashion, the
current dedicated to charging the output capacitors can be
calculated with the following formula:
I SS
I COUT = ------------------------------ × Σ ( C OUT × V OUT ) , where
C SS × V BG
ISS - soft-start current (typically 10µA)
CSS - soft-start capacitor
VBG - bandgap voltage (typically 1.26V)
Σ(COUTxVOUT) - sum of the products between the
capacitance and the voltage of an output
Due to the various system timing events, it is recommended
that the soft-start interval not be set to exceed 30ms.
Additionally, the recommended soft-start capacitor range
spans from 5nF up to 0.22µF (0.1µF recommended).
Shutdown
In case of a FAULT condition that might endanger the
computer system, or at any other time, the HIP6501 can be
shut down by pulling the SS pin below the specified
shutdown level (typically 0.8V) with an open drain or open
collector device capable of sinking a minimum of 2mA.
Pulling the SS pin low effectively shuts down all the pass
elements. Upon release of the SS pin, the HIP6501
undergoes a new soft-start cycle and resumes normal
operation in accordance to the ATX supply and control
pins status.
Layout Considerations
The typical application employing a HIP6501 is a fairly
straight-forward implementation. Similar to any other linear
regulators, attention has to be paid to a few potentially
sensitive small signal components, such as those
connected to high-impedance nodes or those supplying
critical by-pass currents.
The power components (pass transistors) and the controller
IC should be placed first. The controller should be placed in
a central position on the motherboard, closer to the memory
load if possible. Insure the VSEN2 connection is properly
sized to carry 200mA without significant resistive losses. The
pass transistors should be placed on pads capable of
heatsinking matching the device’s power dissipation. Where
applicable, multiple via connections to a large internal plane
can significantly lower localized device temperature rise.
Placement of the decoupling and bulk capacitors should
follow a placement reflecting their purpose. As such, the
HIP6501
(output capacitors) and the loads. Use the remaining printed
circuit layers for small signal wiring.
+12VIN
+5VSB
Q4
5VDLSB
CSS
VOUT3
5VDL
Q2
3V3DLSB
CHF1
CHF3
CBULK3
HIP6501
VOUT1
3V3DL
Q5
DLA
+5VIN
CBULK1
LOAD
A multi-layer printed circuit board is recommended. Figure
12 shows the connections of most of the components in the
converter. Note that the individual capacitors each could
represent numerous physical capacitors. Dedicate one solid
layer for a ground plane and make all critical component
ground connections through vias placed as close to the
component as possible. Dedicate another solid layer as a
power plane and break this plane into smaller islands of
common voltage levels. Ideally, the power plane should
support both the input power and output power nodes. Use
copper filled polygons on the top and bottom circuit layers to
create power islands connecting the filtering components
5VSB
SS
VOUT2 CHF2
VSEN2
Q3
LOAD
12V
The only critical small signal component is the soft-start
capacitor, CSS. Locate this component close to SS pin of the
control IC and connect to ground through a via placed close
to the capacitor’s ground pad. Minimize any leakage current
paths from SS node, since the internal current source is
only 10µA.
CIN
C5VSB
C12V
GND DRV2
Q1 CBULK2
LOAD
high-frequency decoupling capacitors (CHF) should be
placed as close as possible to the load they are decoupling;
the ones decoupling the controller (C12V, C5VSB) close to
the controller pins, the ones decoupling the load close to the
load connector or the load itself (if embedded). The bulk
capacitance (aluminum electrolytics or tantalum capacitors)
placement is not as critical as the high-frequency capacitor
placement, but having these capacitors close to the load
they serve is preferable.
+3.3VIN
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT/POWER PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 12. PRINTED CIRCUIT BOARD ISLANDS
Component Selection Guidelines
Output Capacitors Selection
The output capacitors for all outputs should be selected to
allow the output voltage to meet the dynamic regulation
requirements of active state operation (S0, S1). The load
transient for the various microprocessor system’s
components may require high quality capacitors to supply
the high slew rate (di/dt) current demands. Thus, it is
recommended that capacitors COUT1 and COUT2 should be
selected for transient load regulation.
Also, during the transition between active and sleep states,
there is a short interval of time during which none of the
power pass elements are conducting - during this time the
output capacitors have to supply all the output current. The
output voltage drop during this brief period of time can be
approximated with the following formula:
tt 

∆V OUT = I OUT ×  ESR OUT + --------------- , where
C OUT

∆VOUT - output voltage drop
ESROUT - output capacitor bank ESR
20
HIP6501
IOUT - output current during transition
COUT - output capacitor bank capacitance
tt - active-to-sleep or sleep-to-active transition time (10µs
typical)
Since the output voltage drop is heavily dependent on the
ESR (equivalent series resistance) of the output capacitor
bank, the capacitors should be chosen to maintain the
output voltage above the lowest allowable regulation level.
Input Capacitors Selection
The input capacitors for an HIP6501 application must have
sufficiently low ESR so that the input voltage does not dip
excessively when energy is transferred to the output
capacitors. If the ATX supply does not meet the
specifications, certain imbalances between the ATX’s
outputs and the HIP6501’s regulation levels could result in a
brisk transfer of energy from the input capacitors to the
supplied outputs. When transiting from active to sleep
states, this phenomena could result in the 5VSB voltage
dropping below the POR level (typically 4.3V) and
temporarily disabling the HIP6501. The solution to this
potential problem is to use larger input capacitors (on 5VSB)
with a lower total combined ESR.
Transistor Selection/Considerations
The HIP6501 typically requires one P-Channel and two
N-Channel power MOSFETs and two bipolar NPN
transistors.
One general requirement for selection of transistors for all
the linear regulators/switching elements is package selection
for efficient removal of heat. The power dissipated in a linear
regulator/switching element is
P LINEAR = I O × ( V IN – V OUT )
Select a package and heatsink that maintains the junction
temperature below the rating with the maximum expected
ambient temperature.
Q1
The active element on the 2.5V/3.3VMEM output has
different requirements for each of the two voltage settings. In
2.5V systems utilizing RDRAM (or voltage-compatible)
memory, Q1 must be a bipolar NPN capable of conducting
the maximum required output current and it must have a
minimum current gain (hfe) of 100-150 at this current and
0.7V VCE. In such systems, the 2.5V output is regulated
from the ATX 3.3V output while in an active state. In 3.3V
systems (SDRAM or compatible) Q1 must be an N-Channel
MOSFET, since the MOSFET serves as a switch during
active states (S0, S1). The main criteria for the selection of
this transistor is output voltage budgeting. The maximum
21
rDS(ON) allowed at highest junction temperature can be
expressed with the following equation:
V IN MIN – V OUT MIN
, where
r DS ( ON ) MAX = -----------------------------------------------------I OUT MAX
VIN MIN - minimum input voltage
VOUT MIN - minimum output voltage allowed
IOUT MAX - maximum output current
The gate bias available for this MOSFET is approximately 8V.
HIP6501
Q4
If a P-Channel MOSFET is used to switch the 5VSB output
of the ATX supply into the 5VDUAL output during S3 and
S4/S5 states (as dictated by EN5VDL status), then, similar
to the situation where Q1 is a MOSFET, the selection criteria
of this device is also proper voltage budgeting. The
maximum rDS(ON), however, has to be achieved with only
4.5V of VGS, so a logic level MOSFET needs to be selected.
If a PNP device is chosen to perform this function, it has to
have a low saturation voltage while providing the maximum
sleep-state current and have a current gain sufficiently high
to be saturated using the minimum drive current (typically
20mA; 4mA during soft-start).
Q3, Q5
The two N-Channel MOSFETs are used to switch the 3.3V
and 5V inputs provided by the ATX supply into the
3.3VDUAL and 5VDUAL outputs, respectively, while in
active (S0, S1) states. Similar rDS(ON) criteria apply in these
cases as well, unlike the PMOS, however, these NMOS
transistors get the benefit of an increased VGS drive
(approximately 8V and 7V, respectively).
Q2
The NPN transistor used as sleep-state pass element on the
3.3VDUAL output must have a minimum current gain of 100
at VCE = 1.5V, and ICE = 500mA throughout the in-circuit
operating temperature range.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site www.intersil.com
22
HIP6501
HIP6501 Application Circuit
Figure 13 shows an application circuit of an ACPI-compliant
power management system for a microprocessor computer
system. The power supply provides the PCI 3.3VDUAL
voltage (VOUT1), the RDRAM 2.5VMEM memory voltage
(VOUT2), and the 5VDUAL voltage (VOUT3) from +3.3V, +5V,
+5VSB, and +12VDC ATX supply outputs. For systems
employing SDRAM memory, replace R1 with 10kΩ and Q1
with an HUF76113SK8. Q4 can also be a PNP, such as an
MMBT2907AL. For detailed information on the circuit,
including a Bill-of-Materials and circuit board description, see
Application Note AN9846.
Also see Intersil Corporation web page
(http://www.intersil.com/tsc) for the latest information.
+5VIN
+12VIN
+3.3VIN
+
+5VSB
C1
10µF
+
C2
1µF
C4
1µF
12V
C5
1µF
5VSB
3V3DLSB
Q2
2SD1802
DRV2
Q1
2SD1802
VSEN2
Q3
1/2 HUF76113DK8
VOUT1
C3
220µF
VOUT2
3V3DL
3.3VDUAL
+
C6
1µF
C8, 9 +
2x150µF
C7
220µF
FAULT/MSEL
C14
R2
2K
U1
HIP6501
Q4
FDV304P
5VDLSB
R1
1K
DLA
0.1µF
Q5
1/2 HUF76113DK8
S3
S3
S5
S5
VOUT3
5VDL
EN5VDL
EN5VDL
+
EN3VDL
EN3VDL
SHUTDOWN
(FROM OPEN-DRAIN N-MOS)
SS
C13
0.1µF
GND
FIGURE 13. TYPICAL HIP6501 APPLICATION CIRCUIT
23
2.5VMEM
C10
1µF
C11
150µF
C12
1µF
5VDUAL
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