DESCRIPTION APPLICATIONS FEATURES BLOCK DIAGRAM

DESCRIPTION APPLICATIONS FEATURES BLOCK DIAGRAM
PT6314
Dot Character VFD Controller/Driver IC
DESCRIPTION
PT6314 is a VFD Controller/Driver IC utilizing CMOS
technology providing 80 segment outputs and 24 grid
outputs. It supports dot matrix displays of up to 16
columns x 2 lines, 20 columns x 2 lines or 24 columns
x 2 lines. PT6314 also features a character generator
ROM which stores 248 x 5 x 8 dos characters. Pin
assignments and application circuits are optimized for
easy PCB layout and cost saving advantages.
APPLICATIONS
• Electronic equipment with VFD display
• Microprocessor peripherals
FEATURES
• CMOS technology
• Provides up to 80 x 8 display RAM
• Capable of driving segment for cursor displays (48
units)
• Built-in oscillation circuit
• Parallel data input/output (switchable 4 or 8 bits) or
serial data input/output
• Alphanumeric and symbolic display via the built-in
ROM (5 x 8 dots): 248 characters
• Eight user-defined 5 x 8 dot character CGRAM
• Display contents capability:
- 16 columns x 2(1) rows + 32(16) cursors
- 20 columns x 2(1) rows + 40(20) cursors
- 24 columns x 2(1) rows + 48(24) cursors
• Custom ROM available (please contact PTC
BLOCK DIAGRAM
Tel: 886-66296288‧Fax: 886-29174598‧ http://www.princeton.com.tw‧2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan
PT6314
CONTENTS
1.
APPLICATION CIRCUITS ........................................................................................................................................ 3
1.1 SERIAL INTERFACE ........................................................................................................................................... 3
1.2 i80 INTERFACE ................................................................................................................................................... 3
1.3 M68 INTERFACE ................................................................................................................................................. 4
2.
ORDER INFORMATION ........................................................................................................................................... 5
3.
PIN CONFIGURATION ............................................................................................................................................. 5
4.
PIN DESCRIPTION................................................................................................................................................... 6
4.1 DUTY RATIO SETTING ....................................................................................................................................... 8
4.2 SEGMENT SETTING ........................................................................................................................................... 8
4.3 VFD DISPLAY .................................................................................................................................................... 14
5.
FUNCTION DESCRIPTION .................................................................................................................................... 15
5.1 BLOCK FUNCTIONS ......................................................................................................................................... 15
5.2 DISPLAY DATA RAM (DDRAM) ........................................................................................................................ 16
5.3 CHARACTER GENERATOR ROM (CGROM) .................................................................................................. 18
5.4 CHARACTER GENERATOR RAM (CGRAM) ................................................................................................... 18
5.5 TIMING GENERATION CIRCUIT ...................................................................................................................... 19
5.6 VFD DRIVER CIRCUIT ...................................................................................................................................... 19
5.7 CURSOR/BLINK CONTROL CIRCUIT .............................................................................................................. 19
5.8 CPU INTERFACE (DATA TRANSFER) ............................................................................................................. 20
6.
INSTRUCTIONS ..................................................................................................................................................... 23
6.1 “CLEAR DISPLAY” INSTRUCTION ................................................................................................................... 23
6.2 “CURSOR/ HOME” INSTRUCTION .................................................................................................................. 24
6.3 “ENTRY MODE” INSTRUCTION ....................................................................................................................... 24
6.4 “DISPLAY ON/OFF” INSTRUCTION.................................................................................................................. 25
6.6 “FUNCTION SET” I INSTRUCTION ................................................................................................................... 26
6.7 “CGRAM ADDRESS SET” INSTRUCTION ....................................................................................................... 27
6.8 “DDRAM ADDRESS SET INSTRUCTION ........................................................................................................ 27
6.9 “READ BUSY FLAG AND ADDRESS” INSTRUCTION .................................................................................... 27
6.10 “WRITE DATA TO CGRAM OR DDRAM” INSTRUCTION ............................................................................. 27
6.11 “READ DATA FROM CGRAM OR DDRAM” INSTRUCTION ......................................................................... 28
6.12 POWER ON RESET......................................................................................................................................... 28
6.13 CGRAM STROKE FLOWCHART .................................................................................................................... 29
6.14 DDRAM STROKE FLOWCHART .................................................................................................................... 29
7.
ABSOLUTE MAXIMUM RATINGS ......................................................................................................................... 30
8.
RECOMMENDED OPERAING RANGE ................................................................................................................. 30
9.
ELECTRICAL CHARACTERISTICS ....................................................................................................................... 31
10. SWITCHING CHARACTERISTICS ........................................................................................................................ 31
11. SWITCHING TIMING .............................................................................................................................................. 32
11.1 TIMING 1 REQUIREMENTS ............................................................................................................................ 32
11.2 TIMING 2 REQUIREMENTS ............................................................................................................................ 34
11.3 TIMING 3 REQUIREMENTS ............................................................................................................................ 35
11.4 TIMING 4 REQUIREMENTS ............................................................................................................................ 36
12. FONT TABLE .......................................................................................................................................................... 37
12.1 ENGLISH/JAPANESE CHARACTER FONT TABLE (PT6314-001) ............................................................... 37
12.2 ENGLISH /EUROPEAN CHARACTER FONT TABLE (PT6314-002) ............................................................. 38
12.3 UROPEAN CHARACTER FONT TABLE (PT6314-007) ................................................................................. 39
12.4 JAPANESE CHARACTER FONT TABLE (PT6314-008) ................................................................................ 40
13. PACKAGE INFORMATION .................................................................................................................................... 41
IMPORTANT NOTICE ..................................................................................................................................................... 42
V1.5
2
October 2009
PT6314
1. APPLICATION CIRCUITS
1.1 SERIAL INTERFACE
1.2 i80 INTERFACE
V1.5
3
October 2009
PT6314
1.3 M68 INTERFACE
V1.5
4
October 2009
PT6314
2. ORDER INFORMATION
Valid Part Number
PT6314-001
PT6314-002
PT6314-007
PT6314-008
Package Type
144 Pins, LQFP
144 Pins, LQFP
144 Pins, LQFP
144 Pins, LQFP
Top Code
PT6314-001
PT6314-002
PT6314-007
PT6314-008
3. PIN CONFIGURATION
Note: Pin No. 38 to 71, 73 to 107, 110 to 119 are used as Segment Signal Output Pins, Pin No.120 to 143 are used as Grid Signal Output Pins and are
configured according to the Tables shown in the Duty Ratio Setting Section (see pages 8 to 13).
V1.5
5
October 2009
PT6314
4. PIN DESCRIPTION
Pin Name
I/O
VDD2
-
VFD Driving Power Supply Pin
1, 36
VSS2
-
VFD Driving Power Supply Pin
2, 35
VDD1
-
Logic Power Supply Pin
3
CLK
O
Oscillation Signal Output Pin
4
OSC2
O
Oscillation Output Pin
5
OSC1
I
Oscillation Input Pin
6
/RESET
I
Reset Pin
When this pin is set to “0”, all internal registers and commands are initialized. The Segment
and Grid Outputs are fixed to VDD.
7
TEST
I
Test Pin
0 or floating : the Normal Operation Mode
1:the Test Mode is active
8
DLS
I
Display Line Select Pin
This pin is used to select the number of display lines when the Power is ON, Reset or
Resetting.
0: 1 line is selected (N=”0”)* 1: 2 lines are selected (N=”1”)*
9
DS1, DS0
I
Duty Select Pin
These pins set the duty ratio. The duty ratio is determined by the number of Grid.
I
Read/Write (Write) Signal Pin
Under the M68 Parallel Data Transfer Mode (R/W), this pin functions as the Data Transfer
Select Pin.
0: Write Function
1: Read Function
Under the i80 parallel data Transfer Mode (/WR), thispin is Write Enable Pin. It writes data at
the rising edge of this signal.
Under the Serial Transfer Mode, the Read or Write function is selected by instruction and this
pin is connect to either “H” or “L”.
12
I
Register Select/Strobe Pin
Under the Parallel Transfer Mode is selected, this pin acts as the Register Select Pin.
0: Instruction Register (IR) 1: Data register (DR)
Under Serial Data Transfer Mode, this pin acts as the Strobe Input Pin.
13
E(/RD)/SCK
I
Enable (Read)/Shift Clock
Under the M68 Parallel Data Transfer Mode (E), this pin functions as the Write Enable Pin.
Data is written at the falling edge.
Under the i80 Parallel Data Transfer Mode (/RD), this pin functions as the Read Enable Pin.
When this pin is set to “LOW”, data is outputted to the Data Bus.
Under the Serial Data Transfer Mode, this pin functions as the Shift Clock Input Pin. Data is
written at the rising edge.
14
SI/SO
I/O
Serial Input/Output Pin
Under the Serial Data Transfer Mode, this pin functions as an I/O Pin.
Under the Parallel Data Transfer Mode, this pin may be connected to either “H” or “L”
15
DB0 to DB7
I/O
Parallel Data Input/Output Pins
Under the Parallel Data Transfer Mode, these pins are used as I/O Pin.
Under the 4-bit Transfer Mode, DB4 to DB7 are used.
IFSEL
I
I/F Select Pin
This pin is used to select the I/F mode: Serial or Parallel Transfer
0: Serial Data Transfer
1: Parallel Data Transfer
24
MCU
I
Interface Select Pin
This pin is used to select the interface mode: i80 or M68.
0: i80 CPU Mode
1: M68 CPU Mode
25
/CS
I
Chip Select Pin
When this pin is set to “L” the PT6314 is active.
26
R/W(/WR)
RS/STB
V1.5
Description
6
Pin No.
10, 11
16-23
October 2009
PT6314
Pin Name
I/O
Description
Pin No.
I
Segment Output Select Pin
This pins are used to set SG1 to SG80.
/CLR
O
Extension Grid Driver Clear Signal Output Pin
Active: Low
The Grid Data stored in extension driver latch are outputted when this pin is set to “HIGH”. If
this pin is set to ”LOW”, the extension driver outputs LOW.
29
LATCH
O
Extension Grid Driver Latch Enable Signal Output Pin
30
SDO
O
Extension Grid Driver Serial Data Output Pin
31
Extension Grid Driver Shift Clock Output Pin
Rising Edge: Active
32
RL1,RL2
SLK O
27, 28
TESTOUT
O
Test Pin for IC Testing only.
This pin should be “open”.
33
VSS1
-
Logic Ground Pin
34
GR1 to GR24
O
Grid Signal Output Pins
143-120
SG1 to SG80
O
Segment Signal Output Pins
see (2)
Notes:
1. *=N is the Display Line Select Flag in “Function Set” Command
2. Refer to Duty Ratio Setting Section
V1.5
7
October 2009
PT6314
4.1 DUTY RATIO SETTING
DS0 and DS1 control the duty ratio of PT6314. Please refer to the table below.
DS0
DS1
DUTY RATIO
0
0
1/16 (No. of GRID=16)
0
1
1/24 (No. of GRID=24)
1
0
1/20 (No. of GRID=20)
1
1
1/40 ( No. of GRID=40)
Please take note that the external extension grid driver is needed to set up 1/40 duty mode.
4.2 SEGMENT SETTING
CONDITION 1: 2-LINE DISPLAY (N=“1”), RL1=“0” AND RL2=“0Z”
The number of Segment Pins is controlled by the RL1 and RL2.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
SG1
38
SG18
55
NC
SG2
39
SG19
56
SG35
SG3
40
SG20
57
SG36
SG4
41
SG21
58
SG37
SG5
42
SG22
59
SG38
SG6
43
SG23
60
SG39
SG7
44
SG24
61
SG40
SG8
45
SG25
62
SG41
SG9
46
SG26
63
SG42
SG10
47
SG27
64
SG43
SG11
48
SG28
65
SG44
SG12
49
SG29
66
SG45
SG13
50
SG30
67
SG46
SG14
51
SG31
68
SG47
SG15
52
SG32
69
SG48
SG16
53
SG33
70
SG49
SG17
54
SG34
71
SG50
SG68
106
SG77
116
GR18
SG69
107
SG78
117
GR17
SG70
108
SG79
118
GR16
NC
109
SG80
119
GR15
SG71
110
GR24
120
GR14
SG72
111
GR23
121
GR13
SG73
112
GR22
122
GR12
SG74
113
GR21
123
GR11
SG75
114
GR20
124
GR10
SG76
115
GR19
125
GR9
V1.5
8
Pin No.
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
126
127
128
129
130
131
132
133
134
135
Pin Name
SG51
SG52
SG53
SG54
SG55
SG56
SG57
SG58
SG59
SG60
SG61
SG62
SG63
SG64
SG65
SG66
SG67
GR8
GR7
GR6
GR5
GR4
GR3
GR2
GR1
NC
Pin No.
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
136
137
138
139
140
141
142
143
144
October 2009
PT6314
CONDITION 2: 2-LINE DISPLAY (N=“1”), RL1=“0”, RL2=“1”
Pin Name
SG40
SG39
SG38
SG37
SG36
SG35
SG34
SG33
SG32
SG31
SG30
SG29
SG28
SG27
SG26
SG25
SG24
SG68
SG69
SG70
NC
SG71
SG72
SG73
SG74
SG75
SG76
V1.5
Pin No.
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
106
107
108
109
110
111
112
113
114
115
Pin Name
SG23
SG22
SG21
SG20
SG19
SG18
SG17
SG16
SG15
SG14
SG13
SG12
S G11
SG10
SG9
SG8
SG7
SG77
SG78
SG79
SG80
GR24
GR23
GR22
GR21
GR20
GR19
Pin No.
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
116
117
118
119
120
121
122
123
124
125
Pin Name
NC
SG6
SG5
SG4
SG3
SG2
SG1
SG41
SG42
SG43
SG44
SG45
SG46
SG47
SG48
SG49
SG50
GR18
GR17
GR16
GR15
GR14
GR13
GR12
GR11
GR10
GR9
9
Pin No.
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
126
127
128
129
130
131
132
133
134
135
Pin Name
SG51
SG52
SG53
SG54
SG55
SG56
SG57
SG58
SG59
SG60
SG61
SG62
SG63
SG64
SG65
SG66
SG67
GR8
GR7
GR6
GR5
GR4
GR3
GR2
GR1
NC
Pin No.
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
136
137
138
139
140
141
142
143
144
October 2009
PT6314
CONDITION 3: 2-LINE DISPLAY (N=“1”), RL1=“1”, AND RL2=“0”
Pin Name
SG41
SG42
SG43
SG44
SG45
SG46
SG47
SG48
SG49
SG50
SG51
SG52
SG53
SG54
SG55
SG56
SG57
SG13
SG12
SG11
NC
SG10
SG9
SG9
SG7
SG6
SG5
V1.5
Pin No.
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
106
107
108
109
110
111
112
113
114
115
Pin Name
SG58
SG59
SG60
SG61
SG62
SG63
SG64
SG65
SG66
SG67
SG68
SG69
SG70
SG71
SG72
SG73
SG74
SG4
SG3
SG2
SG1
GR24
GR23
GR22
GR21
GR20
GR19
Pin No.
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
116
117
118
119
120
121
122
123
124
125
Pin Name
NC
SG75
SG76
SG77
SG78
SG79
SG80
SG40
SG39
SG38
SG37
SG36
SG35
SG34
SG33
SG32
SG31
GR18
GR17
GR16
GR15
GR14
GR13
GR12
GR11
GR10
GR9
10
Pin No.
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
126
127
128
129
130
131
132
133
134
135
Pin Name
SG30
SG29
SG28
SG27
SG26
SG25
SG24
SG23
SG22
SG21
SG20
SG19
SG18
SG17
SG16
SG15
SG14
GR8
GR7
GR6
GR5
GR4
GR3
GR2
GR1
NC
Pin No.
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
136
137
138
139
140
141
142
143
144
October 2009
PT6314
CONDITION 4: 2-LINE DISPLAY (N=“1”), RL1=“1” AND RL2=“1”
Pin Name
SG80
SG79
SG78
SG77
SG76
SG75
SG74
SG73
SG72
SG71
SG70
SG69
SG68
SG67
SG66
SG65
SG64
SG13
SG12
SG11
NC
SG10
SG9
SG9
SG7
SG6
SG5
V1.5
Pin No.
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
106
107
108
109
110
111
112
113
114
115
Pin Name
SG63
SG62
SG61
SG60
SG59
SG58
SG57
SG56
SG55
SG54
SG53
SG52
SG51
SG50
SG49
SG48
SG47
SG4
SG3
SG2
SG1
GR24
GR23
GR22
GR21
GR20
GR19
Pin No.
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
116
117
118
119
120
121
122
123
124
125
Pin Name
NC
SG75
SG76
SG77
SG78
SG79
SG80
SG40
SG39
SG38
SG37
SG36
SG35
SG34
SG33
SG32
SG31
GR18
GR17
GR16
GR15
GR14
GR13
GR12
GR11
GR10
GR9
11
Pin No.
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
126
127
128
129
130
131
132
133
134
135
Pin Name
SG30
SG29
SG28
SG27
SG26
SG25
SG24
SG23
SG22
SG21
SG20
SG19
SG18
SG17
SG16
SG15
SG14
GR8
GR7
GR6
GR5
GR4
GR3
GR2
GR1
NC
Pin No.
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
136
137
138
139
140
141
142
143
144
October 2009
PT6314
CONDITION 5:1-LINE DISPLAY (N=“0”), RL2=“0”
The RL1 setting is irrelevant. The table below shows the Segment Pin setting.
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
Pin No.
SG1
38
SG18
55
NC
72
SG2
39
SG19
56
SG35
73
SG3
40
SG20
57
SG36
74
SG4
41
SG21
58
SG37
75
SG5
42
SG22
59
SG38
76
SG6
43
SG23
60
SG39
77
SG7
44
SG24
61
SG40
78
SG8
45
SG25
62
*
79
SG9
46
SG26
63
*
80
SG10
47
SG27
64
*
81
SG11
48
SG28
65
*
82
SG12
49
SG29
66
*
83
SG13
50
S G30
67
*
84
SG14
51
SG31
68
*
85
SG15
52
SG32
69
*
86
SG16
53
SG33
70
*
87
SG17
54
SG34
71
*
88
*
106
*
116
GR18
126
*
107
*
117
GR17
127
*
108
*
118
GR16
128
NC
109
*
119
GR15
129
*
110
GR24
120
GR14
130
*
111
GR23
121
GR13
131
*
112
GR22
122
GR12
132
*
113
GR21
123
GR11
133
*
114
GR20
124
GR10
134
*
115
GR19
125
GR9
135
Pin Name
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
GR8
GR7
GR6
GR5
GR4
GR3
GR2
GR1
NC
Pin No.
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
136
137
138
139
140
141
142
143
144
Note: *=Not Used
V1.5
12
October 2009
PT6314
CONDITION 6: 1-LINE DISPLAY, RL2=“1”
The RL1 setting is irrelevant. Segment Output Pin settings are as follows:
Pin Name
Pin No.
Pin Name
Pin No.
Pin Name
SG40
38
SG23
55
NC
SG39
39
SG22
56
SG6
SG38
40
SG21
57
SG5
SG37
41
SG20
58
SG4
SG36
42
SG19
59
SG3
SG35
43
SG18
60
SG2
SG34
44
SG17
61
SG1
SG33
45
SG16
62
*
SG32
46
SG15
63
*
SG31
47
SG14
64
*
SG30
48
SG13
65
*
SG29
49
SG12
66
*
SG28
50
S G11
67
*
SG27
51
SG10
68
*
SG26
52
SG9
69
*
SG25
53
SG8
70
*
SG24
54
SG7
71
*
*
106
*
116
GR18
*
107
*
117
GR17
*
108
*
118
GR16
NC
109
*
119
GR15
*
110
GR24
120
GR14
*
111
GR23
121
GR13
*
112
GR22
122
GR12
*
113
GR21
123
GR11
*
114
GR20
124
GR10
*
115
GR19
125
GR9
Pin No.
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
126
127
128
129
130
131
132
133
134
135
Pin Name
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
GR8
GR7
GR6
GR5
GR4
GR3
GR2
GR1
NC
Pin No.
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
136
137
138
139
140
141
142
143
144
Note: *=Not Used
V1.5
13
October 2009
PT6314
4.3 VFD DISPLAY
PT6314 supports 24 character x 2 display lines. Please refer to the diagram below for VFD Display construction.
V1.5
14
October 2009
PT6314
5. FUNCTION DESCRIPTION
5.1 BLOCK FUNCTIONS
5.1.1 CPU INTERFACE
PT6314 provides either 4 or 8 bits parallel or serial interface. These interface modes may be selected using the IFSEL
Pin (Pin No.24) as follows:
IFSEL Setting
Data Transfer Mode
“0”
Serial Data Transfer
“1”
Parallel Data Transfer
5.1.2 REGISTERS (INSTRUCTION REGISTER & DATA REGISTER)
PT6314 supports two 8-bit registers, namely: an Instruction Register (IR) and a Data Register (DR) which may be
selected using the Register Selector (RS) Signal. Please refer to Table below
IFSEL
/CS
RS
E/SCK
R/W
MCU
SI/SO
DBn
0
/CS
STB
SCK
*
*
SI/SO
*
1
/CS
RS
E/(/RD)
R/D(/WR)
MCU
*
DBn
Note: *=This pin must be kept in either “HIGH” or “LOW” State.
The Instruction Register (IR) stores (1) instruction codes (i.e. display clear and cursor shift), (2) Display Data RAM
(DDRAM) Address Information and (3) Character Generator RAM (CGRAM). It can only be written from the MCU.
The Data Register (DR) acts as a temporary storage for (1) data to be written into the DDRAM or CGRAM and (2) data
to be read from the DDRAM or CGRAM. Data written into the DR from the MCU is automatically written into the DDRAM
or CGRAM by internal operation. When the data stored in DR is read by the MCU, data transfer is completed. After the
completion of the data transfer (that is, after the MCU has finished reading the first set of data), the DDRAM or CGRAM
data in the next address is sent to the DR. The MCU then again performs its Read operation for the next set of data.
BUSY FLAG (READ BF FLAG)
The Busy Flag Data (DB7) always outputs “0”.
ADDRESS COUNTER (AC)
The Address Counter (AC) designates the addresses of the DDRAM and CGRAM. When an address of instruction is
written into the Instruction Register, the address information is sent from the Instruction Register (IR) to the Address
Counter. The selection of either the DRAM or CGRAM is also determined concurrently by the instruction. After writing
into the DDRAM or CGRAM, the Address Counter is increased by 1. (The Address Counter is decreased by 1 after data
is read from the DDRAM or CGRAM.) The contents of the Address Counter are then outputted to the DB0~DB6 when
RS=”0” and R/W=”1”. Please refer to the table below.
Common
M68
i80
Register Selection
RS
R/W
/RD
/WR
0
0
1
0
Write IR Data as internal operation (i.e. display clear)
0
1
0
1
Read data to busy flag (DB7) and Address Counter (DB6 to DB0)
1
0
1
0
Write DR Data (DR→DDRAM/CGRAM)
1
1
0
1
Read DR Data (DDRAM/CGRAM→DR)
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5.2 DISPLAY DATA RAM (DDRAM)
The Display Data RAM (DDRAM) stores the display data shown in the 8-bit character codes. When expanded the
Display Data RAM supports a capacity of 80 x 8 bits or 80 characters. The area in the DDRAM that is not in used for
display may be used as general data RAM.
High Order Bits
Low Order Bits
AC
AC6
AC5
AC4
AC3
AC2
AC1
AC0
hexadecimal
hexadecimal
Please note that the DDRAM Address (ADD) is set in the Address Counter(AC) as hexadecimal.
Example: DDRAM Address “26”:
0
1
2
0
0
1
1
0
6
5.2.1 N=“0” 1-LINE DISPLAY, 80 CHARACTERS
Display Position
Digit
DDRAM Address(hexadecimal)
1
00
2
01
3
02
4
03
5
04
6
05
……
……
79
4E
80
4F
5.2.2 N=“0” 1-LINE DISPLAY, LESS THAN 80 CHARACTERS
In cases when there are less than 80 display characters, the display begins at the head position. For example, if only one
piece of PT6314 is being used, 24 characters are displayed. When the display shift operation is performed, the DDRAM
address shifts, please refer to the figure below.
Display Position
Digit
DDRAM Address(hexadecimal)
1
00
2
01
3
02
4
03
5
04
6
05
……
……
23
16
24
17
For Shift-Left
01
02
03
04
05
06
……
17
18
For Shift-Right
4F
00
01
02
03
04
……
15
16
5
04
44
6
05
45
……
……
……
39
26
66
40
27
67
5.2.3 N=“1” 2-LINE DISPLAY, 40 CHARACTERS
Display Position
Digit
DDRAM Address
(hexadecimal)
1
00
40
2
01
41
3
02
42
4
03
43
5.2.4 N=“1” 2-LINE DISPLAY, LESS THAN 40 CHARACTERS
In cases when the number of display characters is less than 40 x 2 lines, the two lines are displayed from the head. The
line end address and the second line start address are not consecutive. For example, if only one PT6314 is being used,
24 characters x 2 lines are displayed. When the display shift operation is performed, the DDRAM address shifts.
Display Position
Digit
DDRAM Address
(hexadecimal)
1
00
40
2
01
41
3
02
42
4
03
43
5
04
44
6
05
45
……
……
……
23
16
56
24
17
57
For Shift-Left
01
41
02
42
03
43
04
44
05
45
06
46
……
……
17
57
18
58
For Shift-Right
27
67
00
40
01
41
02
42
03
43
04
44
……
……
15
55
16
56
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5.2.5 N=“1” 2-LINE DISPLAY, 40 CHARACTERS
PT6314 can be extended using one of the 16 output extension drivers as GRID. Under this condition, a 40-character x 2
lines display may be constructed.
Display Position
Digit
1
00
40
2
01
41
3
02
42
4
03
43
……
……
……
23
16
56
24
17
57
25
18
58
……
……
……
39
26
66
40
27
67
Digit
1
01
41
2
02
42
3
03
43
4
04
44
……
……
……
23
17
57
24
18
58
25
19
59
……
……
……
39
27
67
40
00
40
Digit
1
27
67
2
00
40
3
4
……
01
02
……
41
42
……
PT6314 Display
23
15
55
24
16
56
25
……
39
40
17
……
25
26
57
……
65
66
Extension Driver Display
DDRAM Address
(hexadecimal)
For Shift-Left
For Shift-Right
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5.3 CHARACTER GENERATOR ROM (CGROM)
The CGROM is the Read Only Memory (ROM) responsible for the generation of 5 x 8 dots character patterns from 8-bit
character codes. A total of up to 240 character patterns can be generated. Please note that Character Codes -- 00H to
07H are allocated to the CGRAM.
5.4 CHARACTER GENERATOR RAM (CGRAM)
The Character Generator RAM (CGRAM) allows the user to reconstruct the character patterns from 8-bit by software
programming. Eight character patterns can be written and constructed using 5 x 8 dots. Areas that are not used for
display purposes may be used as general data RAM.
The table below shows the relationship between the CGRAM Address, Character Code (DDRAM) and the 5x7 (cursor
included) dot character patterns (CGRAM).
Character Code (DDRAM Data)
D7
D6
D5
D4
D3
D2
D1
D0
High Order Bit
Low Order Bit
0
0
0
0
X
0
0
0
0
0
0
0
0
0
0
0
X
X
0
1
0
1
1
1
CGRAM Address
A5
A4
A3
A2
A1
A0
High Order Bit
Low Order Bit
0
0
0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0
0
1
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
D7
D6
D5
High Order Bit
X
X
X
X
X
X
X
X
X
CGRAM Data
D4
D3
D2
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
1
1
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
D1
D0
Low Order Bit
1
1
0
1
0
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
0
0
0
0
0
1
1
Character Pattern No. 1
Cursor Position
Character Pattern No. 2
Cursor Position
Character Pattern No. 8
Cursor Position
Notes:
1. X= Irrelevant
2. Character Code Bits 0 to 2 correspond to the CGRAM Address Bits 3 to 5 (3 bits: 8 type).
3. CGRAM Address Bits 0 to 2 determine the character pattern line position. The 8th line is the cursor
position and its display is formed by a logical OR with the cursor. Maintain the 8th line data,
corresponding to the cursor display position at 0 as the cursor display. If the 8th line data is “1” all
the 1 bits will light up the 8th line regardless of the cursor presence.
4. Character pattern row position corresponds to the CGRAM data bits 0 to 4. (bit 4 is positioned at the
left)
5. The CGRAM character patterns are selected when the character code bits 4 to 7 are all set to “0”.
The Character Code Bit 3 is irrelevant, the “P” Display shown above (Character Pattern No. 1) can
be selected by either character Code 00H or 07H.
6. When CGRAM Data=“1” the Display is turned ON. When CGRAM data=“0” display is turned OFF.
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5.5 TIMING GENERATION CIRCUIT
Timing signals for internal circuit operations(i.e. DDRAM, CGRAM) are generated by the Timing Generation Circuit. The
Display RAM Read timing and the MCU access internal operation timing are generated separately in order to avoid
interferences. Thus, for example, when data is being written to the DDRAM, no undesirable interference occur (i.e.
flickering in areas other than the display location)
5.6 VFD DRIVER CIRCUIT
The VFD Driver Circuit is composed of 24 grid and 80 segment signal drivers. During power On, the character font and
number of digits are selected by the hardware (DS0 and DS1), the required grid signal drivers automatically output drive
waveforms while the other grid signal drivers continue to output non-selected waveforms. The serial data sent is latched
when the display data character pattern corresponding to the last address of the display data RAM (DDRAM). Since the
serial data is latched when the display data character pattern corresponding to the starting address enters the internal
shift register, PT6314 drives from the head display.
5.7 CURSOR/BLINK CONTROL CIRCUIT
Cursor and Character blinking are generated by the Cursor / Blink Control Circuit. The cursor or the blinking will appear
with the digit located at the display data RAM (DDRAM) address set in the address counter (AC).
For example, when the address counter is 08H, the cursor position is displayed at DDRAM Address 08H.
AC6
AC5
AC4
AC3
AC2
AC1
AC0
AC
0
0
0
1
0
0
0
5.7.1 FOR 1-LINE DISPLAY:
Display position
Digit
DDRAM Address(hexadecimal)
1
00
2
01
3
02
4
03
5
04
6
05
7
06
8
07
9
08
10
09
11
0A
12
0B
Cursor Position
5.7.2 FOR 2-LINE DISPLAY:
Display position
Digit
DDRAM Address(hexadecimal)
1
00
40
2
01
41
3
02
42
4
03
43
5
04
44
6
05
45
7
06
46
8
07
47
9
08
48
10
09
49
11
0A
4A
12
0B
4B
Cursor Position
Note:
The cursor or blinking appears when the address counter (AC) selects the Character Generator RAM (CGRAM). The cursor and blinking become
meaningless. When the Address Counter is a CGRAM Address, the cursor or the blinking is displayed in a meaningless position.
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PT6314
5.8 CPU INTERFACE (DATA TRANSFER)
5.8.1 M68 PARALLEL DATA TRANSFER
The M68 type of parallel data transfer is selected when IFSEL is set to “1” and MCU is set to “0” Under this mode, the
PT6314 can interface with the CPU in 4 or 8 bits . Please take note that the internal registers are composed of 8 bits.
During data transfer in 4 bits, DB4 to DB7 performs the data transfer operation two times, the DB0 to DB3 must be set to
either “H” or “L”. The higher order 4 bits (D4 to D7) are initially transferred followed by the lower order 4 bits (D0 toD3).
please refer to the diagrams below.
4-BIT M68 TYPE PARALLEL DATA TRANSFER
8-BIT M68 TYPE PARALLEL DATA TRANSFER
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5.8.2 i80 TYPE PARALLEL DATA TRANSFER
The i80 type of parallel data transfer mode is selected when IFSEL is set to “1”and MCU is set to “0”. A type of pipeline
process is performed between LSIs via the bus holder attached to the internal data bus whenever data is sent from the
MCU. It is important to take note that certain restrictions exists in the read sequence of this display data RAM. The data
of the specified address is not generated by the read instructions issued immediately after the address setup. This data
is generated in the when the data is read the second time. Thus, a dummy read is required whenever the address setup
or write cycle operation is selected. Please refer to the diagrams below.
WRITING
READING
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5.8.3 SERIAL DATA TRANSFER
PT6314 supports serial data transfer mode. When data is written, it can be inputted when the Strobe goes to “0”. The first
byte -- Start Byte consists of a total of 8 bits: the Synchronous bits (bit 1 - bit 5), R/W (bit 6), RS (bit 7) and bit 8. The
register will be selected (IR or DR) by the RS (bit 7) and the data write or read is selected by R/W (bit 6 = “0”) in this byte.
The Start Byte is followed by the 8-bit Instruction Byte. The Start Byte selects which is process is to be inputted first: read
the Busy Flag + Address Counter (AC6 to AC0) or read the data which was written in the DDRAM or CGRAM. Data is
outputted at the falling edge of the shift clock.
DATA WRITE
DATA READ
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6. INSTRUCTIONS
Instruction
RS
R/W
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
Clear Display
0
0
0
0
0
0
0
0
0
1
Cursor Home
0
0
0
0
0
0
0
0
1
X
Entry Mode Set
0
0
0
0
0
0
0
1
1/D
S
Display ON/Off
0
0
0
0
0
0
1
D
C
B
Cursor or Display
Shift
0
0
0
0
0
1
SC
R/L
X
X
Function Set
0
0
0
0
1
DL
N
X
BR1
BR0
0
0
0
1
0
0
1
ADD
0
1
BF-=”0”
ACC
1
0
Write Data
1
1
Read DR Data
CGRAM Address
Set
DDRAM Address
Set
Read Busy Flag &
Address
Write Data to
CGRAM or DDRAM
Read Data to
CGRAM or DDRAM
ACG
Description
Clear all display, and sets DDRAM address
at 00H
Set DDRAM address at 00H. Also returns
the display being shifted to the original
position. DDRAM contents remain
unchanged.
Sets the cursor direction and specifies
display shift. These operations are
performed during the writing/reading of data.
Sets all display on/off (D)
Cursor on/off (C).
Cursor blinks on character position (B)
Shifts display or cursor, also keeps DDRAM
contents.
Sets data length (in parallel data transfer)
and number of line.
Sets address of CGRAM. After which
CGRAM data is transferred.
Sets DDRAM address, after which DDRAM
data is transferred.
Reads busy flag (BF) and address counter.
BF=”0”
Writes data into the CGRAM or DDRAM.
Reads data from CGRAM or DDRAM
Notes:
1. I/D=“1”: Increment
I/D=“0”: Decrement
2. S=”1”: Display Shift Enabled
S=“0”: Cursor Shift Enabled
3. D, C, B=“1”: Turn On
D, C, B=“0”: Turn OFF
4. S/C=“1”: Display Shift
S/C=”0”: Cursor Shift
5. R/L=“1”: Shift to the Right
R/L=“0”: Shift to the Left
6. DL=“1”: 8 Bits
DL=“0”: 4 Bits
7. N=“0”: 1-Line Display
N=“1”: 2-Line Display
8. BR1, BR0=“00”: 100%
BR1, BR0=”10”: 50%
BR1, BR0=”01”: 75%
BR1, BR0=“11”: 25%
9. X=Irrelevant
10. DDRAM: Display Data RAM
11. CGRAM: Character Generator RAM
12. ACG: CGRAM Address
13. ADD: DDRAM Address
14. ACC: Address Counter
6.1 “CLEAR DISPLAY” INSTRUCTION
CODE
RS
0
R/W
0
DB7
0
DB6
0
DB5
0
DB4
0
DB3
0
DB2
0
DB1
0
DB0
1
During Reset,
DB7
0
DB6
0
DB5
0
DB4
0
DB3
0
DB2
0
DB1
0
DB0
1
The CLEAR DISPLAY Instruction performs the following operations:
1. Fills all Display Data RAM (DDRAM) location with 20H (Blank Character).
2. Clears the contents of the Address Counter (ACC) to 00H.
3. Sets the display for Zero Character Shift (Returns to original position.)
4. Sets the Address Counter to point to the Display Data RAM (DDRAM).
5. If the cursor is displayed, this instruction will move the cursor to the left most character in the upper display line.
6. Sets the Address Counter (ACC) to increment on each access of the DDRAM or CGRAM.
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PT6314
6.2 “CURSOR HOME” INSTRUCTION
CODE
RS
0
R/W
0
DB7
0
DB6
0
DB5
0
DB4
0
DB3
0
DB2
0
DB1
1
DB0
X
The CURSOR HOME Instruction performs the following operations:
1. Clears the contents of the Address Counter (ACC) to 00H.
2. Sets the Address Counter to point to the Display Data RAM (DDRAM).
3. Sets the Display for Zero Character Shift (Returns to the original position).
4. If the cursor is displayed, this instruction moves the cursor to the left most character in the upper line display.
6.3 “ENTRY MODE” INSTRUCTION
CODE
RS
0
R/W
0
DB7
0
DB6
0
DB5
0
DB4
0
DB3
0
DB2
01
DB1
1/D
DB0
S
The “I/D” Bit provides a way to modify the contents of the address counter after every access to the DDRAM or CGRAM.
When I/D is set to “1” the Address Counter is incremented after the DDRAM or CGRAM has been accessed. When the
I/D is set to “0” the Address Counter is decremented after the DDRAM or CGRAM has been accessed.
The “S” Bit controls the display or cursor shift after each read or write operation to the DDRAM. If S is set to “1” the
“Display Shift” Instruction is enabled. If the S is set to “0” the “Cursor Shift” Instruction is enabled.
The direction in which the display is shifted is opposite to that of the cursor. For example, if S=”0” and I/D=”1” the cursor
will shift one character to the right after the MCU writes to the DDRAM. But, if the S=”1” and I/D=”1” the display will shift
one character to the left and the cursor will remain in the same position in the panel display. The cursor has already been
shifted in the direction selected by the I/D during the reading of the DDRAM irrespective of the value of “S”. Reading and
writing the CGRAM always shifts the cursor. Both lines are shifted at the same time.
The table below shows the various cursor and display shift movements by the “Entry Mode Set”.
I/D
S
After Writing DDRAM Data
After Reading DDRAM Data
0
0
Cursor moves one character to the left.
Cursor moves one character to the left.
1
0
Cursor moves one character to the right. Cursor moves one character to the right.
Display shifts one character to the right
Cursor moves one character to the left.
0
1
without any cursor movement.
Display shifts one character to the left
1
1
Cursor moves one character to the right.
without any cursor movement.
During Reset,
DB7
0
V1.5
DB6
0
DB5
0
DB4
0
24
DB3
0
DB2
1
DB1
1
DB0
0
October 2009
PT6314
6.4 “DISPLAY ON/OFF” INSTRUCTION
CODE
RS
0
R/W
0
DB7
0
DB6
0
DB5
0
DB4
0
DB3
1
DB2
D
DB1
C
DB0
B
The above instruction controls the various display features:
D=“1”: Display ON
D=“0”: Display OFF
C=“1”: Cursor ON
C=“0”: Cursor OFF
B=“1”: Blinking ON
B=”0”: Blinking OFF
Blinking is achieved by alternating a normal and an all “ON” display of a character. The cursor blinks with a frequency of
approximately 1 Hz and 50% duty.
BLINK
(1Hz)
Cursor Line
During Reset,
DB7
0
DB6
0
DB5
0
DB4
0
DB3
1
DB2
0
DB1
0
DB0
0
6.5 “CURSOR OR DISPLAY SHIFT” INSTRUCTION
CODE
RS
0
R/W
0
DB7
0
DB6
0
DB5
0
DB4
1
DB3
S/C
DB2
R/L
DB1
X
DB0
X
The instruction above will shift the display and/or move the cursor one character to the left or right, without DDRAM
reading or writing.
“S/C” Bit selects between the movement of both cursor and display or the movement of the cursor alone. When
“S/C”=”1” the cursor and the display are both shifted. When “S/C”=”0” only the cursor is shifted.
The “R/L” Bit selects the left or right movement direction of the cursor and/or display. When “R/L”=”1” the cursor and/or
display is shifted one character to the right. When “R/L” is ”0” the cursor and/or character is shifted to the left.
The table below summarizes display and cursor shift and movement.
S/C
R/L
Cursor
0
0
Move one character to the left.
0
1
Move one character to the right.
1
0
Move one character to the left with display
1
1
Move one character to the right with display
V1.5
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Display
No shift
No shift
Shift one character to the left.
Shift one character to the right.
October 2009
PT6314
6.6 “FUNCTION SET” INSTRUCTION
CODE
RS
0
R/W
0
DB7
0
DB6
0
DB5
1
DB4
DL
DB3
N
DB2
X
DB1
BR1
DB0
BR0
The instruction above sets the data length of the data bus lines. This instruction initializes the system, and must be the
first instructed executed after power is turned ON.
The “DL” and “N” settings are described below:
“DL”=”1”: 8-bit MCU Interface using DB7 to DB0
“DL”=”0”: 4-bit MCU Interface using DB7 to DB4
“N”=”0”: 1-Line Display using SG1 to SG40. (SG41 to SG80 are fixed at “Low Level”)
“N”=”1”:2-Line Display using SG1 to SG80
x = Not Relevant
BR1 and BR0 flags are used to modulate the pulse width of the Segment Output thereby controlling the VFD brightness.
BR1
BR0
Brightness
tp
0
0
100%
tDSP x 1.00
0
1
75%
tDSP x 0.75
1
0
50%
tDSP x 0.5
1
1
25%
tDSP x 0.25
tDSP≒200μs, tBLK≒10μs
where n = number of Grid, T =n x (tDSP + tBLK)
During Reset,
DB7
0
V1.5
DB6
0
DB5
1
DB4
1
26
DB3
1
DB2
0
DB1
0
DB0
0
October 2009
PT6314
6.7 “CGRAM ADDRESS SET” INSTRUCTION
CODE
RS
0
R/W
0
DB7
0
DB6
1
DB5
A
DB4
A
DB3
A
DB2
A
DB1
A
DB0
A
The above instruction is used to (1) load new 6-bit address into the address counter, and (2) set the address counter to
point to the CGRAM.
Once the “CGRAM Address Set” instructions has been executed, the contents of the address counter (ACC) is
automatically modified after every access of the CGRAM, as determined by the ”Entry Mode Set” instruction. The active
width of the address counter, when it is addressing the CGRAM is 6 bits. The counter will wrap around from 00H to 3FH
if more than 64 bytes of data is written to the CGRAM.
During Reset, this instruction is irrelevant.
6.8 “DDRAM ADDRESS SET” INSTRUCTION
CODE
RS
0
R/W
0
DB7
1
DB6
A
DB5
A
DB4
A
DB3
A
DB2
A
DB1
A
DB0
A
The above instruction is used to (1) load new 7 bits address into the address counter, and (2) set the address counter to
point to the CGRAM.
Once the “DDRAM Address Set” instruction has been executed, the contents of the address counter (ACC) is
automatically modified after every access of the DDRAM, as determined by the “Entry Mode Set” instruction. The valid
DDRAM address range is given below.
Line Display
Number of Characters
Address Range
1st Line
40
00H to 27H
2nd Line
40
40H to 67H
During Reset, this instruction is irrelevant.
6.9 “READ BUSY FLAG AND ADDRESS” INSTRUCTION
CODE
RS
0
R/W
1
DB7
BF
DB6
A
DB5
A
DB4
A
DB3
A
DB2
A
DB1
A
DB0
A
The above instruction reads the Busy Flag (BF) * and the value of the address counter in binary “AAAAAAA”. This
address counter is used by the CGRAM and DDRAM addresses and its values are determined by the previous
instruction. Address counter contents are the same as that of “CGRAM Address Set” and “DDRAM Address Set”
Instructions.
Note: * The Busy Flag (BF) = “0”
6.10 “WRITE DATA TO CGRAM OR DDRAM” INSTRUCTION
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
D
D
D
D
D
A
D
D
←High Order Bit
Low Order Bit→
The above instruction write 8 bits binary data “DDDDDDDD” to the CGRAM or DDRAM.
Writing into the CGRAM or DDRAM is determined by the previous instruction of the “CGRAM or DDRAM Address Set”.
After a data is written, the value of the address is automatically increased or decreased by one in accordance to the
selection made by the “Entry Mode Set”. The “Entry Mode Set” also determines the display shift.
CODE
V1.5
RS
1
R/W
0
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October 2009
PT6314
6.11 “READ DATA FROM CGRAM OR DDRAM” INSTRUCTION
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
D
D
D
D
D
A
D
D
←High Order Bit
Low Order Bit→
The above instruction reads the 8 bits binary data “DDDDDDDD” from the CGRAM or DDRAM. The “CGRAM or
DDRAM Address Set” instruction must be executed first before this instruction can be entered. If the “CGRAM or
DDRAM Address Set” is not executed prior to the “READ Data from CGRAM or DDRAM” then the first READ data
becomes invalid. When “Read” Instructions are serially executed, the next address data is normally read from the
second “Read”. Before the cursor shifts by the “Cursor or Display Shift” Instruction, the address set instruction do not
need to be executed before the read instruction (only applies to DDRAM). The operation of the cursor shift instruction is
the same as the “DDRAM Address Set” Instruction.
CODE
RS
1
R/W
1
After reading one data, the value of the address is automatically increased or decreased by 1 in accordance to the
selection made in the “Entry Mode”. Please note that the address counter is automatically increased or decreased by 1
after “Write Data to CGRAM or DDRAM” Instruction is executed. At this moment, the address counter’s target data
cannot be read if the “Read Data from CGRAM or DDRAM” Instruction is executed. Thus, to read data correctly, the
“Address Set” or “Cursor Shift” (if Read Data from DDRAM only) Instruction must be executed before reading.
6.12 POWER ON RESET
When PT6314 is initialized, the internal status after power supply has been reset is as follows:
1. Display Clear: 20H (space code) fills the DDRAM
2. Address Counter is set to 00H
3. Address Counter is pointed to the DDRAM
4. Display ON/OFF: D=0, C=0, B=0 (Display OFF)
5. Entry Mode Set: I/D=1, S=0 (Increment, Cursor Shifts are enabled)
6. Function Set: DL=1, N=1 (8-Bit MCU Interface, 2-Line Display are enabled.)
7. Brightness Control: BR0=BR1=0 (Brightness = 100%)
For the MCU Interface and Duty Ratio Selection, please refer to the table below.
TEST
0
1
1
1
1
1
1
Pin Name
IFSEL DS1
X
X
0
X
1
X
X
0
X
0
X
1
X
1
Function
Remarks
DS0
X
X
X
0
1
0
Self Test Mode
Serial Interface
Parallel Interface
Duty=1/16(16Cx1 or 2L Display)
Duty=1/20(20Cx1 or 2L Display)
Duty=1/24(24Cx1 or 2L Display)
1
Duty=1/40(40Cx1 or 2L Display)
This is effective specially after long usage.
SI/SO, SCK, STB
RS, E, R/W, DB7 to DB4 or DB7 to DB0
It does not need to use the extension driver.
The number of display lines is selected by instruction.
Extension driver must be used. The number of display
lines is selected by instruction.
The above table shows the relationship between the status of PT6314 and the pin states during RESET.
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PT6314
6.13 CGRAM STROKE FLOWCHART
6.14 DDRAM STROKE FLOWCHART
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PT6314
7. ABSOLUTE MAXIMUM RATINGS
(Unless otherwise stated, Ta=+25℃, Vss1=Vss2=0V)
Parameter
Symbol
Logic power supply voltage
VDD1
Logic input voltage
Vi
Logic output voltage
Vo
Driver power supply voltage
VDD2
Driver output voltage
VO2
IOL2S
Segment
IOH2S
Driver output current
IOL2G
Grid
IOH2G
Power dissipation
PD
Operating temperature
Topr
Storage temperature
Tstg
Rating
-0.5 to +6.0
-0.5 to VDD1 + 0.5
-0.5 to VDD1 +0.5
-0.5 to +60
-0.5 to VDD2 + 0.5
+10
-4
+10
-20
1.2
-40 to +85
-65 to +150
Unit
V
V
V
V
V
mA
mA
mA
mA
W
℃
℃
8. RECOMMENDED OPERATING RANGE
(Unless otherwise specified, Ta=+25℃, Vss1=Vss2=0V)
Parameter
Symbol
Logic power supply voltage
VDD1
Logic system input voltage
VIN
Driver power supply voltage
VDD2
IOL2S
Segment
IOH2S
Drive output current
IOL2G
Grid
IOH2G
Min.
4.5
0
20
-
Typ.
5.0
-
Max.
5.5
VDD1
50
+5
-2
+5
-15
Unit
V
V
V
mA
mA
mA
mA
Note: It is recommended that the order in which power is to be applied to the chipset is as follows: VDD1 → Input → VDD2
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PT6314
9. ELECTRICAL CHARACTERISTICS
(Unless otherwise specified, Ta=-40 to +85℃, VDD1=5.0V, VDD2=50V, VSS1=VSS2=0V)
Parameter
High level input voltage 1
Low level input voltage 1
High level input voltage 2
Low level input voltage 2
High level output voltage
(LOGIC)
Low level output voltage
(LOGIC)
High level input current
High level leakage current
Low level leakage current
High level output voltage
(DRIVER)
Symbol
VIH1
VIL1
VIH2
VIL2
VOH1
VOL1
IIH
ILOH
ILOL
VOH2S1
VOH2S2
VOH2G
Low level output voltage
(DRIVER)
VOL2
Current consumption
IDD1
IDD2
Condition
Logic, Expect E/SCK,RESET
Logic, Expect E/SCK,RESET, DLS
E/SCK, RESET
E/SCK, RESET,DLS
DBn, SI/SO, SDO, SLK,
LATCH,/CLR, IOH1=-0.1mA
DBn, SI/SO, SDO, SLK,
LATCH,/CLR, IOL1=+0.1mA
TEST, VIN=VDD1
Logic, VINOUT=VDD1
Logic, VINOUT=VSS1
SG1to SG80, IOH2=-1mA
SG1 to SG80, IOH2=-2mA
GR1 to GR24, IOL2=-15mA
SG1 to SG80, GR1 to GR24
IOL2=1mA
Logic
Driver
Min.
0.7VDD1
0.8VDD1
-
Typ.
-
Max.
0.3 VDD1
0.2 VDD1
Unit
V
V
V
V
VDD1-0.5
-
-
V
-
-
VSS1+0.5
V
20
46
45
45
-
500
1.0
-1.0
-
μA
μA
μA
V
V
V
-
-
5
V
-
-
100
100
μA
μA
Note: The Typical (Typ.) Value is a reference value when Ta=25℃.
10. SWITCHING CHARACTERISTICS
(Unless otherwise specified, Ta=-40 to +85℃, VDD1=5.0 ±10%)
Parameter
Oscillation frequency
Operation frequency
Rise time
Rise time
Fall time
V1.5
Symbol
Fosc
fc
TTLH1
TTLH2
TTHL
Condition
R=56KΩ
OSC1 External Clock
SG1 to SG80, CL=50pF
GR1 to GR24, CL=50pF
SG1 to SG80, GR1 to GR24m, CL=50pF
31
Min.
Typ.
Max.
Unit
392
450
-
560
560
-
728
900
2.0
2.0
2.0
KHz
KHz
μs
μs
μs
October 2009
PT6314
11. SWITCHING TIMING
11.1 TIMING 1 REQUIREMENTS
(Unless otherwise specified, Ta=-40 to +85℃); M68 Interface Parallel Data Transfer: Write (VDD1=5.0V ±10%)
Parameter
Enable cycle time
Enable “H” pulse width
Enable ”L” pulse width
RS, R/W - E setup time
RS, R/W - E hold time
Data setup time
Data hold time
Reset pulse width
Symbol
tCYCE
PWEH
PWEL
tAS
tAH
tDS
tDH
tWRE
Condition
E↑ → E↑
E
E
RS,R/W → E↑
E↓ → RS,R/W
Data → E↓
E↓ → Data
Min.
Typ.
Max.
Unit
500
230
230
20
10
80
10
500
-
-
ns
ns
ns
ns
ns
ns
ns
ns
Min.
Typ.
Max.
Unit
500
230
230
20
10
5
-
160
-
ns
ns
ns
ns
ns
ns
ns
M68 Interface Parallel Data Transfer: Read (VDD1=5.0±10%)
Parameter
Enable cycle time
Enable “H” pulse width
Enable ”L” pulse width
RS, R/W - E setup time
RS, R/W - E hold time
Data delay time
Data hold time
V1.5
Symbol
tCYCE
PWEH
PWEL
tAS
tAH
tDD
tDHR
Condition
E↑ → E↑
E
E
RS,R/W → E↑
E↓ → RS,R/W
E↑ → Data
E↓ → Data
32
October 2009
PT6314
11.1.1 PARALLEL I/F (M68 INPUT)
11.1.2 PARALLEL I/F (M68 OUTPUT)
Notes:
1. Input Signal Rise Time and Fall Time (tF, tR) < 15ns.
2. All timing is specified using 0.20VDD1 and 0.80VDD1 as reference.
3. PWEH is the overlap between /CS=”L” and E.
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11.2 TIMING 2 REQUIREMENTS
(Unless otherwise specified, Ta=-40 To +85℃);i80 Interface Parallel Data Transfer: Write (VDD1=5.0 ±10%)
Parameter
Symbol
Condition
Min.
Typ. Max.
RS hold time
tRH8
10
RS setup time
tRS8
10
System cycle time
tCYC8
168
Control “L” pulse width (WR)
tCCLW
/WR
30
Control “L” pulse width (RD)
tCCLR
/RD
70
Control “H” pulse width (RD)
tCCHW
/WR
100
Control “H” pulse width (RD)
tCCHR
/RD
70
Data setup time
tDS8
D0 to D7
55
Data hold time
tDH8
Do to D7
55
RD access time
tACC8
Do to D7, CL=100pF
70
Output disable time
tOH8
Do to D7, CL=100pF
5
Reset pulse width
tWRE
500
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11.2.1 PARALLEL I/F (i80)
Notes:
1. Input signal rise time and fall time (tF, tR) < 15ns
2. All timing is specified using 0.20VDD1 and 0.80VDD1 as reference.
3. tCCLW and tCCLR are specified as the overlap between /CS=”L” /WR and /RD=”L”
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11.3 TIMING 3 REQUIREMENTS
(Unless otherwise specified, Ta=-40 to +85℃); Serial Data Transfer: (VDD1=5V±10%)
Parameter
Symbol
Condition
Min.
Shift clock cycle
tCYK
SCK
500
High level shift clock pulse width
tWHK
SCK
200
Low level shift clock pulse width
tWLK
SCK
200
Shift clock hold time
tHSTBK
STB↓ → SCK↓
100
Data setup time
tDS
Data → SCK↑
100
Data hold time
tDH
SCK↑ → Data
100
STB hold time
tDKSTB
SCK↑ → STB↑
500
STB pulse width
tWSTB
500
Wait time
tWAIT
8th CLK↑→ 1st CLK↓
1
Output data delay time
tODD
SCK↓ → Data
Output data hold time
tODH
SCK↑ → Data
5
Reset pulse width
tWRE
500
Typ.
-
Max.
150
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11.3.1SERIAL I/F (INPUT)
11.3.2 SERIAL I/F (OUTPUT)
Notes:
1. Input Signal Rise Time and Fall Time (tF, tR) < 15 ns.
2. All timing is specified using 0.20VDD1 and 0.80VDD1 as reference.
11.3.3 AC MEASUREMENT POINT
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11.4 TIMING 4 REQUIREMENTS
(Unless otherwise specified, Ta=-40 to +85℃)
M68 & i80 Serial Interface Common Timing: Power ON RESET (VDD1=5.0±10%)
Parameter
Symbol
Condition
Reset time
tRES
VDD
VDD rising time
trDD
VDD
VDD off width
tOFF
VDD
V1.5
36
Min.
100
1
1
Typ.
-
Max.
-
Unit
μs
μs
ms
October 2009
PT6314
12. FONT TABLE
12.1 ENGLISH/JAPANESE CHARACTER FONT TABLE (PT6314-001)
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12.2 ENGLISH/EUROPEAN CHARACTER FONT TABLE (PT6314-002)
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12.3 EUROPEAN CHARACTER FONT TABLE (PT6314-007)
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PT6314
12.4 JAPANESE CHARACTER FONT TABLE (PT6314-008)
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October 2009
PT6314
13. PACKAGE INFORMATION
144 Pins, LQFP (BODY SIZE: 20 X 20MM, PITCH SIZE: 0.50mm,
THK BODY: 1.40mm)
Symbol
Min.
Nom.
Max.
A
-
-
1.6
A1
0.05
-
0.15
A2
1.35
1.4
1.45
b
0.17
0.22
0.27
c
0.09
-
0.2
D
22 BSC.
D1
20 BSC.
e
0.5 BSC.
E
22 BSC.
E1
20 BSC.
L
0.45
0.6
L1
θ
0.75
1 REF.
0°
3.5°
7°
Notes:
1. Refer to JEDEC MS-026
2. All dimensions are in millimeter.
V1.5
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PT6314
IMPORTANT NOTICE
Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements,
improvements, and other changes to its products and to discontinue any product without notice at any time.
PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No
circuit patent licenses are implied.
Princeton Technology Corp.
2F, 233-1, Baociao Road,
Sindian, Taipei 23145, Taiwan
Tel: 886-2-66296288
Fax: 886-2-29174598
http://www.princeton.com.tw
V1.5
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October 2009
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