MC33567 Dual Linear Controller for High Current Voltage Regulation

MC33567 Dual Linear Controller for High Current Voltage Regulation
MC33567
Dual Linear Controller
for High Current
Voltage Regulation
The MC33567 Dual Linear Power Supply Controller is designed to
facilitate power management for motherboard applications where
reliable regulation of high current supply planes is required. It
provides the Drive, Sense and Control signals to interface two
external, N−channel MOSFETs for regulating two different supply
planes. Undervoltage short circuit detection places the operation of the
system into a protected mode pending removal of the short.
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MARKING
DIAGRAM
Features
• Two Independent Regulated Supplies
• MC33567−1: 1.515 V − Supply for GTL and AGP Planes
•
•
•
•
•
•
•
1
1.818 V − Supply for I/O Plane and Memory
Termination
MC33567−2: Dual 2.525 V Supplies for Clock and Memory
MC33567−3: 2.3 V − Voltage Supply
1.2 V − Voltage Supply
Undervoltage Short Circuit Protection
Supply Undervoltage Detection
Drive Capability for N−Channel MOSFETs
Bypass Function for 3.3 V AGP Card Detection
Pb−Free Package May be Available. The G−Suffix Denotes a
Pb−Free Lead Finish
x
A
L
Y
W
DRV1 1
SENSE1 2
• Motherboards
• Dual Power Supplies
7 DRV2
SHDN1 3
6 SENSE2
GND
5 SHDN2
4
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
1
VCC
DRV1
Startup &
Undervoltage
Shutdown
SHDN1
VCC
8 VCC
ORDERING INFORMATION
REF
66 k
GND
3
8
= 1, 2 or 3
= Assembly Location
= Wafer Lot
= Year
= Work Week
3.3 V
VCC
4
M567x
ALYW
PIN CONNECTIONS
Applications
3.3 V
SO−8
D SUFFIX
CASE 751
8
Control
Vout1
2
SENSE1
CL
+
UVLO
−
+
8.5 V
−
Vin Bypass On (MC33567−1 only)
3.3 V
VCC
REF
3.3 V
7
VCC
DRV2
66 k
Startup &
Undervoltage
Shutdown
5
SHDN2
Control
6
Vout2
SENSE2
CL
REF
Figure 1. Simplified Block Diagram
 Semiconductor Components Industries, LLC, 2003
December, 2003 − Rev. 3
1
Publication Order Number:
MC33567/D
MC33567
PIN ASSIGNMENTS AND FUNCTIONS
PIN #
PIN NAME
PIN DESCRIPTION
1
DRV1
2
SENSE1
Sense 1 line. Sense load voltage and provides feedback to regulator.
3
SHDN1
TTL high level turns on regulation for gate 1. (Internal pull−up to 3.3 V)
4
GND
5
SHDN2
TTL high level turns on regulation for gate 2. (Internal pull−up to 3.3 V)
6
SENSE2
Sense 2 line. Sense load voltage and provides feedback to regulator.
7
DRV2
Gate 2 drive. Saturates external FET in bypass mode (MC33567−1 only).
Is internally clamped to ground in power down mode.
8
VCC
Supply voltage for operation and gate drive output − typically 12 V.
Gate 1 drive. Is internally clamped to ground in power down mode.
MAXIMUM RATINGS (Notes 1, 2 and 3)
Rating
Symbol
Value
Unit
VCC
12.5
Vdc
V SHDN
VCC
Vdc
Operating Ambient Temperature
TA
0 to 80
°C
Operating Junction Temperature
TJ
−5.0 to 125
°C
Supply Voltage
SHUTDOWN Voltage
TL
300
°C
Tstg
−55 to 150
°C
RθJA (Note 2)
159
°C/W
RθJC
28
°C/W
Lead Temperature (Soldering, 10 seconds)
Storage Temperature Range
Package Thermal Resistance, Junction to Ambient
Thermal Resistance, Junction to Case
1. ESD Ratings
ESD Machine Model protection up to 200 V, class B.
ESD Human Body Model protection up to 2000 V, class 2.
2. Minimum pad test board with 5 MIL wide and 2.8 MIL thick copper traces1 inch long.
3. All characterizing done with MTD3055VL N−Channel MOSFETs.
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MC33567
DC ELECTRICAL CHARACTERISTICS
(VCC = 12 V, V SHDN1 = V SHDN2 = 2.0 V, TA = 0°C to 80°C, typical values shown are for TJ = 25°C unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
Unit
Vcc
9.0
12
12.5
V
IqL
IqH
−
−
5.8
6.3
9.0
10
mA
UVLO
7.0
8.5
9.0
V
UVLOVhys
0.2
0.5
0.9
V
Vdrv
−
10.5
−
V
Ipkdrv
10
20
30
mA
Isink
4.0
7.0
10
mA
Shutdown Threshold Voltage (Drive output on to off, ramp V SHDN to 0 V)
SHDNVth
0.8
1.13
1.3
V
Shutdown Threshold Hysteresis (Drive output off to on)
SHDNhys
50
130
200
mV
Shutdown Disable Time (Drive output on to off, ramp V SHDN to 0 V)
SHDNtdis
−
0.5
2.0
s
I SHDN
−
−50
−
A
SCuvd
70
75
80
%Vout
Drive Output Response Time to short circuit (Ramp down Vsense to 0 V)
SCtd
200
325
500
s
Drive Output On Time in hiccup mode (Vsense = 0 V)
SCton
0.5
0.97
1.5
ms
Drive Output Off Time in hiccup mode (Vsense = 0 V)
SCtoff
20
47.7
60
ms
Regulator Output Voltage (Vin = 3.3 V, IL = 5.0 mA to 1.3 A)
MC33567−1
Output 1
Output 2
MC33567−2
Output 1
Output 2
MC33567−3
Output 1
Output 2
Vout1
Vout2
Vout1
Vout2
Vout1
Vout2
1.773
1.477
2.462
2.462
2.243
1.170
1.818
1.515
2.525
2.525
2.300
1.200
1.864
1.553
2.589
2.589
2.358
1.230
Output Voltage Regulation (IL = 5.0 mA to 1.3 A)
Vreg%
−2.5
−
+2.5
Supply Voltage
Quiescent Current
V SHDN1 = V SHDN2 = 0 V
V SHDN1 = V SHDN2 = 2.0 V
UNDERVOLTAGE LOCKOUT
Undervoltage Lockout Threshold Voltage (VCC Increasing)
Hysteresis Voltage (VCC Decreasing)
DRIVE OUTPUTS
Drive Output Voltage (Gate to Ground)
Drive Output Source Current (TJ = 25°C)
Gate Drive Output Sink Current (Vsense = 0 V, TJ = 25°C)
SHUTDOWN INPUTS
Shutdown Input Current (V SHDN = 0 V)
SHORT CIRCUIT
Short Circuit/Undervoltage Detect Threshold
(Load current increased until output voltage drops activating hiccup mode)
OUTPUT REGULATION
V
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%
MC33567
OPERATING DESCRIPTION
Introduction
The MC33567 series is a family of Dual Linear FET
Controllers designed for Power Management applications
where high current, voltage regulation is needed. Some
computer applications include:
• 1.2 V − Power Supply
• 1.515 V − AGP (Advanced Graphic Port) and GTL+
(Gunning Transistor Logic − Intel’s electrical bus
technology)
• 1.818 V − I/O planes on motherboards
• 2.3 V − Power Supply
• 2.525 V − Clock and memory
The MC33567 provides tight output voltage regulation,
(Vout), and incorporates individual SHDN controls for each
FET controller and voltage protection by sensing the output
voltage.
Listed below are the SHDN threshold voltage levels and
the corresponding regulator output voltages:
1. If the SHDN pin is left open, the output voltage is set
to its regulated value.
2. If a voltage less than 0.8 V is applied to the SHDN pin,
the output voltage is set to 0 V.
3. If a voltage greater than 1.3 V and less than 4.1 V is
applied to the SHDN pin, the output voltage is set to its
regulated voltage.
4. If the SHDN voltage is pulled above 4.1 V, the
MC33567 enters a Vin bypass mode. In this mode, the
MOSFET is fully enhanced and the output voltage is
the MOSFET drain voltage (Vin) minus the MOSFET
drain−source on voltage VDS(on). This feature is only
available on REGULATOR 2 of the MC33567−1.
Table 1 summarizes the output voltage options and its
relationship with VSHDN.
Output:
Table 1. Logic Table for SHDN Pin
The MC33567 provides tight output voltage regulation
from one or two supply voltages using 2 external N−Channel
MOSFETs. Each controller operates independently and
regulates the output voltage to a predetermined level (1.2 V,
1.515 V 1.818 V, 2.3 V or 2.525 V). In addition, regulator 2
of the MC33567−1 incorporates a Vin bypass mode on which
the external FET is fully enhanced.
Device
REGULATOR 2
The regulated outputs of the MC33567 can be disabled
with the use of the SHDN pin. It also determines the output
voltage level. SHDN can be controlled externally from
board signals like the AGP or GTL+ as shown in Figure 3.
No Connect
0.8 V
1.3 V
1.818 V
0V
1.818 V
No Connect
0.8 V
1.3 V V SHDN 4.1 V
4.1 V
1.515 V
0V
1.515 V
Vin−VDS(on)
(Bypass
Mode)
No Connect
0.8 V
1.3 V
2.525 V
0V
2.525 V
No Connect
0.8 V
1.3 V
2.3 V
0V
2.3 V
No Connect
0.8 V
1.3 V
1.2 V
0V
1.2 V
MC33567−2
REGULATOR 1 &
REGULATOR 2
AGP
Card
Voltage
Vout or Vin*
3.3 V (Vin)
12 V (VCC)
Vout (V)
MC33567−1
REGULATOR 1
Shutdown:
AGP
Card Type
Detection
V SHDN (V)
MC33567−3
REGULATOR 1
REGULATOR 2
3.3 V
10 k
Undervoltage Detection:
1
8
2
7
3
MC33567 6
4
5
If Vout drops below 75% of the regulated threshold for
greater than 250 µs or a short circuit condition is present, that
output will go into short circuit or Hiccup Mode. While in
Hiccup mode, the output is turned ON for 1.0 ms and OFF
for 40 ms for a duty cycle of 1:41 as shown in Figure 4. This
mode will continue as long as the fault is present. Once the
fault is removed, the regulator will resume normal
operation.
DRV2
SENSE2
SHDN2
*Vin while on bypass mode (MC33567−1 only)
Figure 3. 1.5 V/3.3 V AGP Card Detection
1 ms
40 ms
Figure 4. Hiccup Mode Duty Cycle
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MC33567
Sense:
The required RDS(on) can be calculated using the equation
below:
If the load is located away from the regulator, the voltage
drop on the connecting cable or trace can become
significant. The MC33567 provides tight voltage load
regulation with varying load currents using it’s SENSE
feature. As shown in Figure 5, the MC33567 senses the
voltage at the load and provides feedback to the regulator.
The regulator voltage is then adjusted to compensate for the
load changes. It is recommended that the SENSE connection
be placed as close as possible to the load. Also, use a separate
trace to connect the source of the N−channel MOSFET to the
load to avoid interference or coupling with the SENSE
signal. The use of the SENSE feature is required for correct
device operation. If the SENSE pin is not connected to the
load, the output will go into Hiccup mode.
The current into the SENSE pin is given by the following
equation:
RDS(on) 0.5
Vin = Input Voltage, typically 3.3 V
Vout = Regulator Output Voltage
(1.2 V, 1.515 V, 1.818 V, 2.3 V, or 2.525 V)
ILOAD= Load Current
A safety margin of 0.5 was added to account for RDS(on)
variations over the operating temperature range.
Stability:
After evaluating the regulator, driver and load system
using control theory it is demonstrated that the output
capacitor, external driver gain and error amplifier gain
bandwidth play an important role on the system stability. To
insure system stability the following set of design guidelines
should be followed:
Vin
Ci Cgs Cgd
f DRV
p 100 A
1
ISENSE
20 · 1 SENSE
1.8 k
+
VOUT
−
ILOAD
where:
V
ISENSE 100 A out
1.8 k
Feedback
to
Regulator
Vin Vout
a
(3 · p)
1
Ci · Ro
11 1f 1
(3 · )
· g1 Rs p · g1
m
a
m
RL
Co · Rs 5 · 1 1
a
p
where:
f = Driver pole frequency
Ci = Input and reverse transfer capacitance when device
is off
Ro = Regulator output resistance (50 for the MC33567)
p = Secondary pole for open loop
a = Error amplifier gain bandwidth
1 = Error amp second pole (set 1 = a, if not specified)
Rs = Output capacitor ESR
gm = Maximum driver transconductance gain
Co = Output capacitance
T = Overall loop response time
Figure 5. Voltage Regulation Using Sense Feature
N−Channel MOSFET Selection:
The
MC33567
was
characterized
using
ON Semiconductor’s MTD3055VL N−channel MOSFET.
Other MOSFETs can be used with the MC33567 as long as
power and stability requirements are met.
Power:
A MOSFET with a low drain−source on resistance
(RDS(on)) will insure the output voltage is not drastically
reduced due to excessive voltage drop across the MOSFET.
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MC33567
Adjustable Output Voltage:
The output capacitor capacitance and ESR required for
using the MTD3055VL as external driver are calculated as
follows:
f The MC33567 will regulate Vout to its preset voltage level,
referenced at the sense pin. However, other Vout levels can
be obtained scaling the sense voltage. This is done using a
resistive network between the load and the sense pin as
shown in Figure 6.
1
1
10.87 MHz
(1240 pF 600 pF) · (50 )
Ci · Ro
p 1 1
1
11 1f 1 5 MHz
10.87 MHz
Vin
3.42 MHz
1
20 · 1 1
a
(3 · p)
5 MHz
20 · 1 (3 · 3.42
MHz)
·
(3 · )
· g1 Rs p · g1
m
a
m
DRV
+
(3 · 3.42 MHz)
1
Rs 5 MHz
8.8 mhos
R1
Vout(new)
SENSE
1
·
8.8 mhos
1.8 k
RINT
ISENSE
R2
+
Vout
−
−
3.8 m Rs 233.2 m
selecting an ESR of 30 m, we have:
Figure 6. Output Voltage Scaling Using
Resistive Network
Co 5 · 1 1
Rs
a
p
Co 5
1 1
·
30 m
5 MHz 3.42 MHz
The regulator will increase the load voltage until the
SENSE pin voltage reaches the regulator voltage level, Vout.
The new output voltage, Vout(new), is calculated as follows:
Co 82.07 F
100 µF is selected as it is an industry standard value.
Please note that if the system is designed to work with
several drivers, the system has to be designed around the
driver with higher gain to insure stability for all of them.
The design guidelines discussed in this section are
conservative enough that satisfactory results may be
obtained with devices that lie just outside of these
guidelines, although deviation from these guidelines will
generally cause instability. For a more detailed analysis on
linear regulators stability please refer to ON Semiconductor
application note AND8037/D.
Vout(new) Vout R1 *
VRout2 ISENSE
Please note that in this configuration R2 and the sense
internal resistor are in parallel. The parallel combination
will reduce the effective resistance of R2. If R2 is in the range
of RINT, the parallel combination will be almost half of the
original intended value of R2. This will cause Vout(new) to be
smaller than calculated using the above equation. This is
avoided making R2 as small as possible, probably in the
range of 10 to 50 Ohms. Vout(new) is limited by the external
driver drain current and its required Gate−Source voltage as
well as the Drive Output Voltage, Vdrv.
PCB Layout Guidelines
It is recommended that the MC33567 be placed as
physically close as possible to the external series pass
MOSFET transistors. Use short traces to minimize
extraneous signals from being induced on the SENSE or
DRV line. Also, avoid routing the SENSE line near the load
and input current path, as well as the GND return current
path to prevent signal coupling.
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MC33567
12 V
Power Supply
C2
100 µF
DRV1
Q1
3.3 V
Vin
1
8
2
7
DRV2
SENSE1
C1
100 µF
C3
100 µF
VCC
MC33567
SHDN1
Q2
SENSE2
3
6
4
5
SHDN2
LOAD2
C4
100 µF
SHDN2
SHDN1
LOAD1
AGP
Card
Figure 7. Application Block Diagram
Parts List
Qty
Reference
Part/Description
Vendor
4
C1, C2, C3, C4
100 µF Electrolytic Capacitor
Various
1
U1
MC33567
ON Semiconductor
2
Q1, Q2
MTD3055VL
ON Semiconductor
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Notes
N−Channel MOSFET
MC33567
MC33567 TYPICAL CHARACTERISTICS
200
200
PHASE MARGIN
= 48° @ 8 kHz
PHASE MARGIN
= 60° @ 200 kHz
100
GAIN dB
0
ILOAD = 2 A
C = 200 F
RESR = 50 m
PHASE MARGIN
= 48° @ 500 kHz
100
GAIN dB
0
ILOAD = 2 A
C = 200 F
RESR = 200 m
−100
−100
10
100
1,000
10,000
100,000
f, FREQUENCY (Hz)
10
1,000,000
1.540
Gate Drive 2 Open
1,000
10,000
100,000
f, FREQUENCY (Hz)
1,000,000
Gate Drive 2 Open
1.535
1.835
1.830
1.530
IL = 1.3 A
1.825
1.525
1.820
1.520
1.815
IL = 5 mA
IL = 1.3 A
1.515
1.810
IL = 5 mA
1.510
1.505
1.805
1.800
1.795
1.790
−10
VOUT2, REGULATOR 2 OUTPUT VOLTAGE (V)
1.840
100
Figure 9. Gain−Phase Plot for Output Capacitor
with 200 m ESR
Figure 8. Gain−Phase Plot for Output Capacitor
with 50 m ESR
VOUT1, REGULATOR 1 OUTPUT VOLTAGE (V)
PHASE MARGIN
= 85° @ 8 kHz
PHASE °
GAIN/PHASE (dB/0°)
GAIN/PHASE (dB/°)
PHASE °
1.500
1.495
0
10
20
30
40
50
60
70
80
90
1.490
−10
0
10
20
30
40
50
60
70
80
TA,TEMPERATURE (°C)
TA,TEMPERATURE (°C)
Figure 10. Regulator 1 (Suffix 1)
Output Voltage vs. Ambient Temperature
Figure 11. Regulator 2 (Suffix 1)
Output Voltage vs. Ambient Temperature
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90
Regulator 1
1.35
1.30
1.25
1.20
Regulator 2
1.15
1.10
−10
2.320
0
10
20
30
40
50
60
70
80
90
1.9
Regulator 1
1.7
1.5
1.3
1.1
Regulator 2
0.9
0.7
−10
20
30
40
50
60
70
80
90
Figure 12. Short Circuit/Undervoltage Detect
Threshold (Suffix 1) vs. Ambient Temperature
Figure 13. Short Circuit/Undervoltage Detect
Threshold (Suffix 3) vs. Ambient Temperature
Gate Drive 2 Open
IL = 1.3 A
2.310
2.300
IL = 5 mA
2.295
2.290
2.285
2.280
2.275
0
10
20
30
40
50
60
70
80
90
TA,TEMPERATURE (°C)
1.200
Gate Drive 2 Open
1.215
1.210
1.205
IL = 5 mA
1.200
IL = 1.3 A
1.195
1.190
1.185
1.180
1.175
1.170
−10
0
10
20
30
40
50
60
70
80
90
TA,TEMPERATURE (°C)
Figure 14. Regulator 1 (Suffix 3)
Output Voltage vs. Ambient Temperature
Figure 15. Regulator 2 (Suffix 3)
Output Voltage vs. Ambient Temperature
6.4
8.0
Iq, QUIESCENT CURRENT (mA)
ISINK, GATE DRIVE SINK CURRENT (mA)
10
TA,TEMPERATURE (°C)
2.305
7.6
Regulator 1
7.2
Regulator 2
6.8
6.4
6.0
5.6
−10
0
TA,TEMPERATURE (°C)
2.315
2.270
−10
SCUVD, SHORT CIRCUIT/UNDERVOLTAGE
DETECT THRESHOLD (V)
1.40
VOUT2, REGULATOR 2 OUTPUT VOLTAGE (V)
VOUT1, REGULATOR 1 OUTPUT VOLTAGE (V)
SCUVD, SHORT CIRCUIT/UNDERVOLTAGE
DETECT THRESHOLD (V)
MC33567
0
10
20
30
40
50
60
70
80
6.3
Quiescent Current with both SHDNs High
6.2
6.1
6.0
IL = 50 mA
5.9
5.8
5.7
5.6
Quiescent Current with both SHDNs Low
5.5
5.4
−10
90
0
10
20
30
40
50
60
70
TA,TEMPERATURE (°C)
TA,TEMPERATURE (°C)
Figure 16. Gate Drive Sink Current
vs. Ambient Temperature
Figure 17. Quiescent Current
vs. Ambient Temperature
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80
90
UVLO, UNDERVOLTAGE LOCKOUT
THRESHOLD VOLTAGE (V)
8.6
Startup Threshold
8.5
8.4
8.3
8.2
8.1
Minimum Operating Threshold
8.0
7.9
−10
0
10
20
40
30
50
60
70
80
90
VHYS, UVLO HYSTERESIS VOLTAGE (mV)
MC33567
520
510
500
490
480
470
460
450
440
−10
0
10
SCTOFF, DRIVE OUTPUT OFF TIME
IN HICCUP MODE (ms)
VDRV, DRIVE OUTPUT VOLTAGE (V)
10.75
VSHDN = 4.2 V
VCC = 12 V
10.65
10.60
Series 1
10.55
10.50
10.45
10.40
10.35
0
10
20
30
40
50
60
70
80
90
70
80
90
80
90
49.0
48.5
48.0
47.5
47.0
46.5
46.0
45.5
45.0
−10
0
10
20
30
40
50
60
70
TA,TEMPERATURE (°C)
Figure 21. Drive Output Off Time in Hiccup Mode
vs. Ambient Temperature
1.06
SCTON, DRIVE OUTPUT ON TIME IN
HICCUP MODE (ms)
60
49.5
Figure 20. Regulator 2 Maximum Gate Voltage
vs. Ambient Temperature
1.04
1.02
1.00
0.98
0.96
0.94
0.92
0
50
50.0
TA,TEMPERATURE (°C)
0.90
−10
40
Figure 19. UVLO Hysteresis Voltage
vs. Ambient Temperature
Figure 18. Undervoltage Lockout Threshold
vs. Ambient Temperature
10.30
−10
30
TA,TEMPERATURE (°C)
TA,TEMPERATURE (°C)
10.70
20
10
20
30
40
50
60
70
80
90
TA,TEMPERATURE (°C)
Figure 22. Drive Output On Time in Hiccup Mode
vs. Ambient Temperature
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MC33567
ORDERING INFORMATION
Vout1
Vout2
Package
Shipping†
MC33567D−1
1.818 V
1.515 V or Vin*
SO−8
98 Units/Rail
MC33567D−1R2
1.818 V
1.515 V or Vin*
SO−8
2500/Tape & Reel
1.818 V
1.515 V or Vin*
SO−8
(Pb−Free)
2500/Tape & Reel
MC33567D−2
2.525 V
2.525 V
SO−8
98 Units/Rail
MC33567D−2R2
2.525 V
2.525 V
SO−8
2500/Tape & Reel
MC33567D−3
2.300 V
1.200 V
SO−8
98 Units/Rail
MC33567D−3R2
2.300 V
1.200 V
SO−8
2500/Tape & Reel
Device
MC33567D−1R2G
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*While on bypass mode.
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MC33567
PACKAGE DIMENSIONS
SO−8
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751−07
ISSUE AA
−X−
A
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN
EXCESS OF THE D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDAARD IS 751−07
5
0.25 (0.010)
S
B
1
M
Y
M
4
K
−Y−
G
C
N
DIM
A
B
C
D
G
H
J
K
M
N
S
X 45 SEATING
PLANE
−Z−
0.10 (0.004)
H
D
0.25 (0.010)
M
Z Y
S
X
M
J
S
MILLIMETERS
MIN
MAX
4.80
5.00
3.80
4.00
1.35
1.75
0.33
0.51
1.27 BSC
0.10
0.25
0.19
0.25
0.40
1.27
0
8
0.25
0.50
5.80
6.20
INCHES
MIN
MAX
0.189
0.197
0.150
0.157
0.053
0.069
0.013
0.020
0.050 BSC
0.004
0.010
0.007
0.010
0.016
0.050
0
8
0.010
0.020
0.228
0.244
SOLDERING FOOTPRINT*
1.52
0.060
7.0
0.275
4.0
0.155
0.6
0.024
1.270
0.050
SCALE 6:1
mm inches
Figure 23. SO−8
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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12
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MC33567/D
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