ISL6442 Datasheet

ISL6442 Datasheet
ISL6442
®
Data Sheet
October 31, 2008
FN9204.2
Dual (180° Out-of-Phase) PWM and Linear
Controller
Features
The ISL6442 is a high-performance, triple output controller
that provides a single high-frequency power solution
primarily for Broadband, DSL and Networking applications.
This device integrates complete control, monitoring and
protection functions for two synchronous buck PWM
controllers and one linear controller. Input voltage ripple and
total RMS input current is substantially reduced by
synchronized 180° out-of-phase operation of the two PWMs.
• ±1.5% PWM Switcher Reference Accuracy Over Line and
Temperature
The two PWM buck converters provide simple voltage mode
control. The output voltage of the converters can be
precisely regulated to as low as 0.6V, with a maximum
tolerance of ±1.5% over temperature and line variations.
Programmable switching frequency up to 2.5MHz provides
fast transient response and small external components. The
linear controller provides a low-current output.
• Fast Transient Response
- High-Bandwidth Error Amplifier
The ISL6442 has voltage-tracking capability. Each controller
has soft-start and independent enable functions combined
on a single pin. A capacitor from SS/EN to ground sets the
soft-start time; pulling SS/EN pin below 1V disables the
controller. Both outputs can soft-start into a pre-biased load.
• Externally Adjustable Soft-Start Time
- Independent Enable Control
- Voltage Tracking Capability
- Able to Soft-Start into a Pre-Biased Load
The ISL6442 incorporates robust protection features. An
adjustable overcurrent protection circuit monitors the output
current by sensing the voltage drop across the upper
MOSFET rDS(ON). Hiccup mode overcurrent operation
protects the DC/DC converters from damage under over
load and short circuit conditions. A PGOOD signal is issued
when soft-start is complete and PWM outputs are within 10%
of their regulated values and the linear regulator output is
higher than 75% of its nominal value. Thermal shut-down
circuitry turns the device off if the IC temperature exceeds
+150°C.
• 4.5V to 5.5V or 5.5V to 24V Input Voltage Range
• Three Programmable Power Output Voltages
- Two PWM Controllers with Out-of-Phase Operation
- Voltage-Mode PWM Control
- One Linear Controller
• Programmable Switching Frequency from 300kHz to 2.5MHz
• Extensive Circuit Protection Functions
- Overvoltage, Undervoltage, and Overtemperature
- Programmable Overcurrent Limit with Hiccup Mode
Operation
- Lossless Current Sensing (No Sense Resistor Needed)
• PGOOD Output with Delay
• 24 Ld QSOP
• Pb-Free (RoHS Compliant)
Applications
• Complete 1 Chip Solution for DSL Modems/Routers
• DSP, ASIC, and FPGA Point of Load Regulation
• ADSL, Broadband and Networking Applications
Pinout
ISL6442
(24 LD QSOP)
TOP VIEW
Ordering Information
PART
NUMBER
(Note)
ISL6442IAZ*
PART
MARKING
ISL 6442IAZ
TEMP.
RANGE (°C)
-40 to +85
PACKAGE
(Pb-free)
PKG.
DWG. #
24 Ld QSOP M24.15
*Add “-TK” suffix for tape and reel. Please refer to TB347 for details
on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets, molding compounds/die attach
materials, and 100% matte tin plate plus anneal (e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations). Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
1
OCSET1 1
24 VIN
SS1/EN1 2
23 BOOT1
COMP1 3
22 UGATE1
FB1 4
21 PHASE1
RT 5
20 LGATE1
SGND 6
19 VCC
LCDR 7
18 PGND
LCFB 8
17 LGATE2
FB2 9
16 PHASE2
COMP2 10
15 UGATE2
SS2/EN2 11
14 BOOT2
OCSET2 12
13 PGOOD
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL6442
Block Diagram
VIN
VCC
VCC
REFERENCE
BIAS CURRENT
POWER ON
RESET
AND CONTROL
30µA 100µA 0.6V
5V LINEAR
REGULATOR
110µA
OCSET1
VCC
BOOT1
UVP1
OVP1
PG1
EN1
COMP1
UGATE1
OUTPUT1
DRIVERS
FB1
PWM1
0.6V
FAULT1
VCC5
30µA
UVP1
OVP1
PG1
EN1
VCC5
30µA
SS1
SS1
SS2/EN2
1V DET
SS2 EN2
EN1
FAULT2
UVP2
OVP2
PG2
EN2
LGATE1
OVERCURRENT
PGND
RAMP1
0°
STARTUP
SS1/EN1
PHASE1
GATE CONTROL
LOGIC
VCC
DEAD-TIME
CONTROL
110µA
CLOCK AND
SAWTOOTH
GENERATOR
OCSET2
VCC
RAMP2
180°
UGATE2
OUTPUT2
DRIVERS
PWM2
SS2
BOOT2
UVP2
OVP2
PG2
EN2
0.6V
PHASE2
GATE CONTROL
LOGIC VCC
DEAD-TIME
CONTROL
LGATE2
FB2
OVERCURRENT
PGND
COMP2
FAULT3
PG3
LCFB
RT
PG1
PG2
PG3
PGOOD
0.6V
LCFB
LCDR
SGND
PGND
FIGURE 1. BLOCK DIAGRAM
2
FN9204.2
October 31, 2008
ISL6442
Typical Application Schematics
VOLTAGE INPUTS REQUIRED
VIN (4.5V TO 24V) = VIN1 = VIN2
VCC
VCC (5V; INTERNAL IF VIN > 5.6V)
VIN
OPTIONAL
CONNECTION
(FOR VIN = VCC = 5V)
VIN3 (≤ VCC) FOR LINEAR
CVCC CVIN
TYPE3 COMPENSATION SHOWN
ROCSET1
C102
VCC
VIN1 = VIN
VIN
COMP1
R102
VOUT1
OCSET1
C101
BOOT1
R101
COCSET1
CBOOT1
FB1
R103
C103
UGATE1
R100
VOUT1
C202
VOUT2
L100
PHASE1
LGATE1
COMP2
R202
CIN1
Q101
COUT1
Q102
C201
R201
FB2
R203
ROCSET2
R200
C203
VIN2 = VIN
ISL6442
OCSET2
TYPE3 COMPENSATION SHOWN
BOOT2
COCSET2
CBOOT2
Q201
CIN2
UGATE2
VCC
VOUT2
L200
PHASE2
RPGOOD
LGATE2
COUT2
Q202
PGOOD
RT
Q301
R303
SS1/EN1
VIN3
CIN3
LCDR
R302
SS2/EN2
C301
VOUT3
LCFB
CSS1/EN1 CSS2/EN2
R301
RRT
SGND
PGND
R300
COUT3
FIGURE 2. ISL6442 TYPICAL APPLICATION
3
FN9204.2
October 31, 2008
ISL6442
Absolute Maximum Ratings (Note 1)
Thermal Information
SS1/EN1, SS2/EN2, COMP1, COMP2 to SGND . . . -0.3V to +6.0V
VCC, FB1, FB2, RT, PGOOD to SGND . . . . . . . . . . . -0.3V to +6.0V
LCDR, LCFB to SGND. . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V
VIN, OCSET1, and OCSET2 to PGND . . . . . . . . . . . . -0.3V to +28V
BOOT1 and BOOT2 to PGND . . . . . . . . . . . . . . . . . . . -0.3V to +33V
BOOT1 to PHASE1, and BOOT2 to PHASE2 . . . . . . -0.3V to +6.0V
UGATE1 to PHASE1 . . . . . . . . . . . . . . . . . -0.3V to (BOOT1 +0.3V)
UGATE2 to PHASE2 . . . . . . . . . . . . . . . . . -0.3V to (BOOT2 +0.3V)
LGATE1, LGATE2 to PGND . . . . . . . . . . . . . . -0.3V to (VCC+0.3V)
PHASE1, PHASE2 to PGND . . . . . . . . . . . . . . . . . . . . . . -1V to 28V
SGND to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 0.3V
Thermal Resistance (Typical, Note 2)
θJA (°C/W)
QSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
85
Maximum Junction Temperature (Plastic Package).-55°C to +150°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±10%
VIN Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5V to 24V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. All voltages are measured with respect to GND.
2. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
Operating Conditions Unless Otherwise Noted: VIN = 12V, or VCC = 5V ±10%, TA = -40°C to +85°C. Typical
values are at +25°C. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not production tested.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VIN = 5.5V or 12V; LGATEx, UGATEx Open,
FB forced above regulation point (no
switching)
4.5
7.5
mA
VIN = 24V
50
70
mA
1.25
2
mA
5.2
5.5
V
VIN SUPPLY
Input Operating Supply Current
ICC_op
Input Standby Supply Current
ICC_sb
VIN = 5.5V, 12V, 24V;
SS1/EN1 = SS2/EN2 = 0V
Output Voltage
VVCC
VIN > 5.5V
4.5
Maximum Output Current
IICC_max
VIN = 12V
80
VCC Current Limit (Note 3)
IICC_CL
VCC is pulled to PGND; (Note 4)
VREF1,
VREF2
VIN = 5V or 12V; TA = +25°C
VCC INTERNAL REGULATOR
mA
300
mA
0.6000
V
REFERENCE AND SOFT-START
Reference Voltage at FB1, FB2
Reference Voltage at FB1, FB2
VREF1,
VREF2
VIN = 5V or 12V; TA = 0°C to +85°C
0.5925
0.6085
V
VIN = 5V or 12V; TA = -40°C to +85°C
0.5900
0.6085
V
VIN = 24V; TA = +25°C
0.6015
V
VIN = 24V; TA = 0°C to +85°C
0.5940
0.6100
V
VIN = 24V; TA = -40°C to +85°C
0.5915
0.6100
V
ENx/SSx Soft-Start Current
ISSx
20
30
40
µA
ENx/SSx Enable Threshold
VENx
0.8
1.0
1.2
V
ENx/SSxEnable Threshold
Hysteresis
VENx_hys
(Note 3)
50
mV
ENx/SSx Soft-Start Top of Ramp
Voltage
VSSx_top
(Note 3)
3.2
V
POWER-ON RESET ON VCC
Rising Threshold
VPOR_r
4.2
4.4
4.475
V
Falling Threshold
VPOR_f
3.85
4.0
4.1
V
4
FN9204.2
October 31, 2008
ISL6442
Electrical Specifications
Operating Conditions Unless Otherwise Noted: VIN = 12V, or VCC = 5V ±10%, TA = -40°C to +85°C. Typical
values are at +25°C. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not production tested. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
PWM CONVERTERS
Minimum UGATE on Time
tUGATE_min (Note 3)
Maximum Duty Cycle
DCmax
VIN = 4.5 or 12V; FSW = 300kHz
95
%
Maximum Duty Cycle
DCmax
VIN = 4.5V; FSW = 2.5MHz
80
%
FBx Pin Bias Current
IFBx
(Note 3)
FSW
VIN = 5V or 12V; RT = 52.3kΩ
270
300
330
kHz
VIN = 24V; RT = 52.3kΩ
270
305
340
kHz
VIN = 5V; RT = 5.23kΩ
2.25
2.5
2.75
MHz
VIN = 12V; RT = 5.23kΩ
2.25
2.55
2.85
MHz
100
ns
80
nA
OSCILLATOR
Low End Frequency
High End Frequency
FSW
Frequency Adjustment Range
FSW
RT = 52.3kΩ; (Note 3)
0.3
MHz
RT = 5.23kΩ; (Note 3)
2.5
MHz
(Note 4)
1.25
V
Gate Drive Peak Current
(Note 3)
0.7
A
Rise Time
(Note 3); CL = 1000pF
20
ns
Fall Time
(Note 3); CL = 1000pF
20
ns
Dead Time Between Drivers
(Note 3)
30
ns
PWM Sawtooth Ramp Amplitude
(Peak-to-Peak)
VP-P
PWM CONTROLLER GATE DRIVERS
ERROR AMPLIFIERS
DC Gain
Gain
(Note 4)
88
dB
Gain-Bandwidth Product
GBWP
(Note 4)
15
MHz
Slew Rate
SR
(Note 4); COMP = 10pF
5
V/µs
Maximum Output Voltage
VEA_max
VCC = 5V; RL = 10kΩ to ground
3.9
4.4
PROTECTION and OUTPUT MONITOR
Overvoltage Threshold
OV
113
116
121
%
Undervoltage Threshold
UV
78
82
88
%
OCSET Current Source
IOCSET
VOCSET = 4.5V
80
110
140
µA
Drive Sink Current
ILCDR
LCDR
50
LCFB Feedback Threshold
VLCFB
TA = +25°C
LINEAR CONTROLLER
LCFB Input Leakage Current
mA
0.595
V
TA = -40°C to +85°C
0.570
0.620
V
TA = 0°C to +70°C
0.580
0.610
V
ILCFB
(Note 3)
Power-Good Lower Threshold
PG_lowx
LCFB = VCC, LDO disabled
PGOOD for Ch1 and Ch2 only
88
91
94
%
Power-Good Higher Threshold
PG_hix
LCFB = VCC, LDO disabled
PGOOD for Ch1 and Ch2 only
107
110
113
%
80
nA
PGOOD
5
FN9204.2
October 31, 2008
ISL6442
Electrical Specifications
Operating Conditions Unless Otherwise Noted: VIN = 12V, or VCC = 5V ±10%, TA = -40°C to +85°C. Typical
values are at +25°C. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise
specified. Temperature limits established by characterization and are not production tested. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Power-Good Lower Threshold
PG_low3
LDO enabled, PGOOD for LDO;
Ch1 and Ch2 disabled; (Note 3)
75
%
PGOOD Delay
tPGOOD
(Note 3); FSW = 1.4MHz
370
ms
PGOOD Leakage Current
IPGOOD
VPULLUP = 5.5V
5
µA
PGOOD Voltage Low
VPG_low
IPGOOD = -4mA
0.5
V
THERMAL
Shutdown Temperature
(Note 4)
150
°C
Shutdown Hysteresis
(Note 4)
20
°C
NOTES:
3. Limits established by characterization and are not production tested.
4. Design guideline only; not production tested.
0.65
4.0
0.64
3.5
0.63
3.0
0.62
FSW (MHz)
REFERENCE VOLTAGE (V)
Typical Performance Curves
0.61
0.60
0.59
2.5
2.0
1.5
0.58
1.0
0.57
0.5
0.56
0.55
-40
-20
0
20
40
TEMPERATURE (°C)
60
FIGURE 3. REFERENCE VOLTAGE VARIATION OVER
TEMPERATURE
6
80
0.0
0
5
10
15
20
RT (kΩ)
25
30
35
40
FIGURE 4. FREQUENCY vs RT RESISTOR
FN9204.2
October 31, 2008
ISL6442
Pin Descriptions
BOOT1, 2 (Pins 23, 14) - These pins power the upper
MOSFET drivers of each PWM converter. The anode of the
each internal bootstrap diode is connected to the VCC pin.
The cathode of the bootstrap diode is connected to this pin,
which should also connect to the bootstrap capacitor.
UGATE1, 2 (Pins 22, 15) - These pins provide the gate
drive for upper MOSFETs, bootstrapped from the VCC pin.
PHASE1, 2 (Pins 21, 16) - These are the junction points of
the upper MOSFET sources, output filter inductor and lower
MOSFET drains. Connect these pins accordingly to the
respective converter.
LGATE1, 2 (Pins 20, 17) - These are the outputs of the lower
N-Channel MOSFET drivers, sourced from the VCC pin.
PGND (Pin 18) - This pin provides the power ground
connection for the lower gate drivers. This pin should be
connected to the source of the lower MOSFET for PWM1
and PWM2 and the negative terminals of the external input
capacitors.
FB1, 2 (Pins 4, 9) - These pins are connected to the feedback
resistor divider and provide the voltage feedback signals for the
respective controller. They set the output voltage of the
converter. In addition, the PGOOD circuit and OVP circuit use
these inputs to monitor the output voltage status.
COMP1, 2 (Pins 3, 10) - These pins are the error amplifier
outputs for the respective PWM. They are used, along with the
FB pins, as the compensation point for the PWM error amplifier.
PGOOD (Pin 13) - This is an open drain logic output used to
indicate the status of the output voltages. This pin is pulled low
when either of the two PWM outputs is not within 10% of the
respective nominal voltage or when the linear output drops
below 75% of its nominal voltage. To maintain the PGOOD
function if the linear output is not used, connect LCFB to VCC.
SGND (Pin 6) - This is the signal ground, common to both
controllers, and must be routed separately from the high
current grounds (PGND). All voltage levels are measured
with respect to this pin.
VIN (Pin 24) - This pin powers the controllers with an
internal linear regulator (if VIN > 5.5V) and must be closely
decoupled to ground using a ceramic capacitor as close to
the VIN pin as possible. VIN is also the input voltage applied
to the upper FET of both converters.
TABLE 1. INPUT SUPPLY CONFIGURATION
INPUT
5.5V to 24V
5V ±10%
PIN CONFIGURATION
Connect the input supply to the VIN pin. The
VCC pin will provide a 5V output from the
internal voltage regulator.
Connect the input supply to the VCC pin.
7
VCC (Pin 19) - This pin supplies the bias for the regulators,
powers the low side gate drivers and external boot circuitry
for high side gate drivers. The IC may be powered directly
from a single 5V (±10%) supply at this pin; when used as a
5V supply input, this pin must be externally connected to
VIN. When VIN > 5.5, VCC is the output of the internal 5V
linear regulator output. The VCC pin must always be
decoupled to power ground with a minimum of 1µF ceramic
capacitor, placed very close to the pin.
RT (Pin 5) - This is the operating frequency adjustment pin.
By placing a resistor from this pin to SGND, the oscillator
frequency can be programmed from 300kHz to 2.5MHz.
SS1/EN1, 2 (Pins 2, 11) - These pins provide
enable/disable and soft-start function for their respective
controllers. The output is held off when the pin is pulled to
the ground. When the chip is enabled, the regulated 30µA
pull-up current source charges the capacitor connected from
the pin to ground. The output voltage of the converter follows
the ramping voltage on the SS/EN pin. Note that if either
input is held low during power-up, neither channel will start a
soft-start ramp until both are released. Once both outputs
are running, then either one can be separately disabled and
then enabled. But if both are disabled, that requires that both
are released before either starts up. See Soft-Start and
Voltage Tracking section for more details.
LCFB (Pin 8) - This pin is the feedback pin for the linear
controller. An external voltage divider network connected to
this pin sets the output voltage of the linear controller. If the
linear controller is not used, tie this pin to VCC.
LCDR (Pin 7) - Open drain output PNP Transistor Driver.
LCDR connects to the base of an external PNP pass
transistor to form a positive linear regulator.
OCSET1, 2 (Pins 1, 12) - These pins are the overcurrent set
points for the respective PWM controllers. Connect a resistor
(ROCSET) from this pin to the drain of the upper MOSFET.
ROCSET, an internal 100µA current source, and the upper
MOSFET ON resistance rDS(ON) set the converter
overcurrent (OC) trip point according to Equation 1:
I OCSET • R OCSET
I OC = --------------------------------------------------r DS ( ON ) )
(EQ. 1)
IOC includes the DC load current, as well as the ripple
current. An overcurrent trip initiates hiccup mode.
Functional Description
Soft-Start and Voltage Tracking
After the VCC pin exceeds its rising POR trip point (nominal
4.4V), the chip operation begins. While the voltage on both
SS1/EN1 and SS2/EN2 is below 1.0V, the internal switch
between SS1/EN1 and SS2/EN2 is turned on so that the
voltage across these two pins is the same. If either pin is
held low externally, nothing happens until both pins are
FN9204.2
October 31, 2008
ISL6442
released. Then both 30µA current sources will start charging
up both capacitors in parallel. Once the voltage on both of
these pins is above 1.0V, this internal switch is turned off and
each 30µA internal current source charges its corresponding
soft-start capacitor connected to its soft-start pin. The
charging continues until the voltage across the soft-start
capacitor reaches 3.2V. However, the output voltage reaches
its regulation value when the soft-start capacitor voltage
reaches 1.6V. Figure 5 shows the typical waveforms for
SS2/EN2 and VOUT2; SS1/EN1 and VOUT1 are similar.
SS2/EN2 (0.5V/DIV)
From 0.0V to 1.0V, C = (C1 + C2 µF); dV = 1V; I = (30 + 30µA);
for a 0.1µF capacitor on each pin, t = 3.3ms. This time
represents the delay from when the soft-start ramp begins, until
the output voltage ramp begins.
Then, from 1.0V to 1.6V, the outputs will ramp individually
from zero to full-scale. Use the same equation to calculate the
time for each ramp; now if V = 0.6V, C = 0.1µF, and I = 30µA,
then t = 2ms.
Finally, there is a delay after 1.6V, until the ramp gets to
~3.2V, which signals that the ramp is done; when both ramps
are done, the PGOOD delay begins.
Figure 7 shows a typical power-up sequence. VIN turns on
and begins to ramp up; once VCC passes the rising POR trip
point, the linear output is enabled (with no soft-start ramp).
The SS1/EN1 pins also start charging (if not held low
externally); after a delay for them to reach 1V, VOUT1 and
VOUT2 begin to ramp; they are shown in tracking mode.
1.6V
1.0V
VOUT2 (2V/DIV)
VOUT2 (1V/DIV)
GND>
VOUT (1V/DIV)
FIGURE 5. SOFT-START
The soft-start ramps for each output can be selected
independently, but the ISL6442 also has voltage tracking
capability. By selecting the soft-start capacitance to be
proportional to the output voltage, the output voltage can be
tracked. For example, in Figure 6, SS1 capacitor = 0.18µF
and SS2 capacitor = 0.33µF, which match the output voltage
ratio (1.8V and 3.3V). Therefore, the lower VOUT1 ramp will
track with the VOUT2 ramp until they both reach 1.8V;
VOUT1 then levels off, while VOUT2 continues rising
towards 3.3V.
SS1/EN1 (0.5V/DIV) SS2/EN2 (0.5V/DIV)
GND>
1.6V
1.0V
GND>
FIGURE 6. VOLTAGE TRACKING
The basic timing equation is shown in Equation 2:
dV
t = C • ------I
VIN (5V/DIV)
(EQ. 2)
where:
GND>
VOUT2 (1V/DIV)
t is the charge time
C is the external capacitance
VOUT1 (1V/DIV)
dV is the voltage charged
VOUT3 (1V/DIV)
I is the charging current (nominal 30µA)
GND>
FIGURE 7. OUTPUT VOLTAGES
8
FN9204.2
October 31, 2008
ISL6442
Figure 8 shows pre-biased outputs before soft-start. The
solid blue curve shows no pre-bias; the output starts ramping
from GND. The magenta dotted line shows the output
pre-biased to a voltage less than the final output. The FETs
don’t turn on until the soft-start ramp voltage exceeds the
output voltage; then the output starts ramping seamlessly
from there. The cyan dotted line shows the output prebiased above the final output (but below the OVP
(Overvoltage Protection)). The FETs will not turn on until the
end of the soft-start ramp; then the output will be quickly
pulled down to the final value.
If the output is pre-biased above the OVP level, the ISL6442
will go into OVP at the end of soft-start, which will keep the
FETs off. The output can recover if the voltage goes below the
UV (Undervoltage) trip point, at which time a retry will occur. If
successful, the output will ramp back up to the normal level.
VOUT1 has the same functionality as previously described
for VOUT2. Each output should react independently of the
other, unless they are related by the circuit configuration.
all 3 outputs are within their expected ranges, the PGOOD
will start an internal timer, with Equation 3:
0.5236
t PGOOD = -----------------F SW
(EQ. 3)
where:
tPGOOD is the delay time (in sec)
FSW is the switching frequency (in MHz)
Once the time-out is complete, the internal pull-down device
will shut off, allowing the open-drain PGOOD output to rise
through an external pull-up resistor, to a 5V (or lower) supply,
which signals that the “Power is GOOD”. Figure 9 shows the
three outputs turning on, and the delay for PGOOD. If any of
the conditions is subsequently violated, then PGOOD goes
low. Once the voltage returns to the normal region, a new
delay will start, after which the PGOOD will go high again.
The PGOOD delay is inversely proportional to the clock
frequency. If the clock is running as slow as 524kHz, the
delay will be one second long. There is no way to adjust the
PGOOD delay independently of the clock.
SS2/EN2 (0.5V/DIV)
PGOOD (5V/DIV)
GND>
VOUT3 (2V/DIV)
GND>
VOUT2 OVER-CHARGED
VOUT2 (2V/DIV)
VOUT2 (2V/DIV)
VOUT2 PRE-BIASED
GND>
GND>
VOUT1 (2V/DIV)
GND>
FIGURE 8. SOFT-START WITH PRE-BIAS
NOTE: Neither output cannot be independently disabled during
power-up; both SS/EN pins are pulled low internally during POR, and
due to the internal switch, neither will start charging if either pin is still
held low. Once the outputs are running, either output can be disabled
and then enabled again, without affecting the other one that’s
running. But if both SS/EN pins are held low at the same time, then
the internal switch will turn on, and both SS/EN pins must be released
before they both start to ramp.
The linear output does not have a soft-start ramp; however, it
may follow the ramp of its input supply, if timed to coincide
with its rise, after the VCC rising POR trip. If the input to the
linear is from one of the two switcher outputs, then it will
share the same ramp rate as the switcher.
PGOOD
A group of comparators (separate from the protection
comparators) monitor the output voltages (via the FB pins)
for PGOOD. Each switcher has an lower and upper
boundary (nominally around 90% and 110% of the target
value) and the linear has a lower boundary (around 75% of
the target). Once both switcher output ramps are done, and
9
FIGURE 9. PGOOD DELAY
Monotonic Output
During soft-start period, the low side MOSFET is disabled to
achieve monotonic output voltage when the inductor current
is negative. This also allows ramping up into a pre-charged
output voltage.
Switching Frequency
The switching frequency of the ISL6442 is determined by the
external resistor placed from the RT pin to SGND. See
Figure 10 for a graph of Frequency versus RT Resistance.
The “Electrical Specifications” Table on page 5 lists a low
end value of 52.3kΩ for 300kHz operation (not shown on
graph). Running at both high frequency and high VIN
voltages is not recommended, due to the increased power
dissipation on-chip (mostly from the internal VCC regulator,
which supplies gate drivers). The user should check the
maximum acceptable IC temperature, based on their
particular conditions.
FN9204.2
October 31, 2008
ISL6442
3.0
soft-start ramp, and it does NOT shut off, unless VCC goes
back below the falling POR trip point. It is suggested that using
one of the switcher outputs as the input to the linear allows it to
be ramped and enabled/disabled with that switcher.
2.5
Protection Mechanisms
4.0
FSW (MHz)
3.5
2.0
1.5
1.0
0.5
0.0
0
5
10
15
20
25
30
35
40
RT (kΩ)
FIGURE 10. FREQUENCY vs RT RESISTOR
Output Regulation
Figure 11 shows the generic feedback resistor circuit for any
of the three VOUT’s; the VOUT is divided down to equal the
reference. All three use a 0.6V internal reference (check the
“Electrical Specifications” Table on page 4 for the exact
reference value at 24V). The RUP is connected to the VOUT;
the RLOW to GND; the common point goes to the FB pin.
VOUT
FB
EA
RUP
COMP
RLOW
0.6V
FIGURE 11. OUTPUT REGULATION
VOUT must be greater than 0.6V and 2 resistors are needed,
and their accuracy directly affect the regulator tolerance.
R LOW
FB = V OUT ⋅ ----------------------------------R
+R
UP
(EQ. 4)
LOW
Use Equation 5 to choose the resistor values. RUP is part of
the compensation network for the switchers, and should be
selected to be compatible; 1kΩ to 5kΩ is a good starting
value. Find FB from the “Electrical Specifications” Table on
page 5 (for the right condition), plug in the desired value for
VOUT, and solve for RLOW.
OCP - (Function independent for both PWM). The overcurrent
function protects the PWM Converter from a shorted output by
using the upper MOSFET’s ON-resistance, rDS(ON) to monitor
the current. This method enhances the converter’s efficiency
and reduces cost by eliminating a current sensing resistor. The
overcurrent function cycles the soft-start function in a hiccup
mode to provide fault protection. A resistor connected to the
drain of the upper MOSFET and OCSET pin programs the
overcurrent trip level. The PHASE node voltage will be
compared against the voltage on the OCSET pin, while the
upper MOSFET is on. A current (typically 110µA) is pulled from
the OCSET pin to establish the OCSET voltage. If PHASE is
lower than OCSET while the upper MOSFET is on then an
overcurrent condition is detected for that clock cycle. The upper
gate pulse is immediately terminated, and a counter is
incremented. If an overcurrent condition is detected for 32
consecutive clock cycles, and the circuit is not in soft-start, the
ISL6442 enters into the soft-start hiccup mode. During hiccup,
the external capacitor on the SS/EN pin is discharged, then
released and a soft-start cycle is initiated. During soft-start,
pulse termination current limiting is enabled, but the 32-cycle
hiccup counter is held in reset until soft-start is completed.
Figure 12 shows an example of the hiccup mode. As the
SS2/EN2 is pulled below the enable trip point, VOUT2 shuts
off, and the voltage goes to GND, at which time the output
current goes to zero. As SS2/EN2 rises above the enable
trip point, the output tries to turn on, the current spikes up,
and then is held constant (by the pulse-termination current
limiting); the output voltage rises, but not up to the desired
value. When the SS2/EN2 ramp reaches ~3V, the cycle
repeats, and can continue indefinitely. If the short-circuit is
removed, the output will ramp up with the next soft-start, and
normal operation will resume. VOUT1 and SS1/EN1 will
independently function the same way.
GND>
VOUT2 (2V/DIV)
FB ⋅ R UP
R LOW = -----------------------------V OUT – FB
(EQ. 5)
The maximum duty cycle of the ISL6442 approaches 100%
at low frequency, but falls off at higher frequency; see the
“Electrical Specifications” Table on page 5. In addition, there
is a minimum UGATE pulse width, in order to properly sense
overcurrent. The two switchers are 180° out of phase.
The linear output voltage is restricted to approximately a 1V to
4V range. VIN3 should be equal or less than VCC (in order to
be sure that LCDR can turn off the PNP). Note that the linear
output is off until the rising POR trips; it does not have a
10
0A>
IOUT2 (2A/DIV)
SS2/EN2 (1V/DIV)
GND>
FIGURE 12. OVERCURRENT PROTECTION
FN9204.2
October 31, 2008
ISL6442
UVP - (Function independent for both PWM). If the voltage
on the FB pin falls to 82% (typical) of the reference voltage
for 8 consecutive PWM cycles, then the circuit enters into
soft-start hiccup mode. This mode is identical to the
overcurrent hiccup mode. The UVP comparator is separate
from the one sensing for PGOOD, which should have
already detected a problem, before the UVP trips.
OVP - (Function independent for both PWM). If voltage on
FB pin rises to 116% (typical) of the reference voltage, the
lower gate driver is turned on continuously (with diode
emulation enabled). If SS_DN (internal soft-start done
signal) is true (not in soft-start) and the overvoltage condition
continues for 32 consecutive PWM cycles, then that output
is latched off with the gate drivers three-stated. The
capacitor on the SS/EN pin will not be discharged. The
switcher will restart when the SS/EN pin is externally driven
below 1V, or if power is recycled to the chip, or when the
voltage on the FB pin falls to the 82% (typical) undervoltage
threshold - after 8 clock cycles the chip will enter soft-start
hiccup mode. The hiccup mode is identical to the
overcurrent hiccup mode. The OVP comparator is separate
from the one sensing for PGOOD, which should have
already detected a problem, before the OVP trips.
Application Guidelines
PWM Controller
DISCUSSION
The PWM must be compensated such that it achieves the
desired transient performance goals, stability, and DC
regulation requirements.
The first parameter that needs to be chosen is the switching
frequency, FSW. This decision is based on the overall size
constraints and the frequency plan of the end equipment.
Smaller space requires higher frequency. This allows the
output inductor, input capacitor bank, and output capacitor
bank to be reduced in size and/or value. The power supply
must be designed such that the frequency and its distribution
over component tolerance, time and temperature causes
minimal interference in RF stages, IF stages, PLL loops,
mixers, etc.
INDUCTOR SELECTION
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current, and the ripple voltage is a function
of the ripple current. The ripple current and voltage are
approximated by the following equations, where ESR is the
output capacitance ESR value.
V IN - V OUT V OUT
ΔI = -------------------------------- • ---------------F SW • L
V IN
(EQ. 6)
11
ΔVOUT = ΔI x ESR
(EQ. 7)
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance value reduces
the converter’s response time to a load transient (and
usually increases the DCR of the inductor, which decreases
the efficiency). Increasing the switching frequency (FSW) for
a given inductor also reduces the ripple current and voltage.
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6442 will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval, the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
L OUT × I TRAN
t RISE = --------------------------------------V IN – V OUT
(EQ. 8)
L OUT × I TRAN
t FALL = --------------------------------------V OUT
(EQ. 9)
where: ITRAN is the transient load current step, tRISE is the
response time to the application of load, and tFALL is the
response time to the removal of load. With a +5V input
source, the worst case response time can be either at the
application or removal of load and dependent upon the
output voltage setting. Be sure to check both of these
equations at the minimum and maximum output levels for
the worst case response time.
Finally, check that the inductor Isat rating is sufficiently above
the maximum output current (DC load plus ripple current).
OUTPUT CAPACITOR SELECTION
An output capacitor is required to filter the output and supply
the load transient current. The filtering requirements are a
function of the switching frequency and the ripple current.
The load transient requirements are a function of the slew
rate (di/dt) and the magnitude of the transient load current.
These requirements are generally met with a mix of
capacitors and careful layout.
Modern microprocessors produce transient load rates above
1A/ns. High frequency capacitors initially supply the transient
and slow the current load rate seen by the bulk capacitors.
The bulk filter capacitor values are generally determined by
the ESR (effective series resistance) and voltage rating
requirements rather than actual capacitance requirements.
FN9204.2
October 31, 2008
ISL6442
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements. Keep in mind that not all
applications have the same requirements; some may need
many ceramic capacitors in parallel; others may need only one.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient.
An aluminum electrolytic capacitor's ESR value is related to
the case size with lower ESR available in larger case sizes.
However, the equivalent series inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
INPUT CAPACITOR SELECTION
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time Q1 (upper FET)
turns on. Place the small ceramic capacitors physically close
to the MOSFETs and between the drain of Q1 and the source
of Q2 (lower FET).
The important parameters for the bulk input capacitor are the
voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. The capacitor voltage rating
should be at least 1.25 times greater than the maximum
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
1/2 the DC load current.
of the regulator is a major contributor to the overall IC power
dissipation (especially as Cin of the FET or VIN or FSW
increases).
Since VCC is around 5V, that affects the FET selection in two
ways. First, the FET gate-source voltage rating (VGS) can be
as low as 12V (this rating is usually consistent with the 20V
or 30V breakdown chosen above). Second, the FETs must
have a low threshold voltage (around 1V), in order to have its
rDS(ON) rating at VGS = 4.5V in the 10mΩ to 40mΩ range
that is typically used for these applications. While some
FETs are also rated with gate voltages as low as 2.7V, with
typical thresholds under 1V, these can cause application
problems. As LGATE shuts off the lower FET, it does not
take much ringing in the LGATE signal to turn the lower FET
back on, while the Upper FET is starting to turn on, causing
some shoot-through current. Therefore, avoid FETs with
thresholds below 1V.
If the power efficiency of the system is important, then other
FET parameters are also considered. Efficiency is a
measure of power losses from input to output, and it
contains two major components: losses in the IC (mostly in
the gate drivers) and losses in the FETs. For low duty cycle
applications (such as 12V in to 1.5V out), the upper FET is
usually chosen for low gate charge, since switching losses
are key, while the lower FET is chosen for low rDS(ON), since
it is on most of the time. For high duty cycles (such as 5.0V
in to 3.3V out), the opposite may be true.
Feedback Compensation Equations
This section highlights the design consideration for a voltage
mode controller requiring external compensation. To address a
broad range of applications, a type-3 feedback network is
recommended (see Figure 13).
C2
R2
C1
COMP
FB
C3
R1
ISL6442
R3
SWITCHER MOSFET SELECTION
VIN for the ISL6442 has a wide operating voltage range
allowed, so both FETs should have a source-drain
breakdown voltage (VDS) above the maximum supply
voltage expected; 20V or 30V are typical values available.
The ISL6442 gate drivers (UGATEx and LGATEx) were
designed to drive single FETs (for up to ~10A of load current) or
smaller dual FETs (up to 4A). Both sets of drivers are sourced
by the internal VCC regulator (unless VIN = VCC = 5V, in which
case the gate driver current comes from the external 5V
supply). The maximum current of the regulator (ICC_max) is
listed in the “Electrical Specifications” Table on page 4; this may
limit how big the FETs can be. In addition, the power dissipation
12
VOUT
FIGURE 13. COMPENSATION CONFIGURATION FOR ISL6442
CIRCUIT
Figure 14 highlights the voltage-mode control loop for a
synchronous-rectified buck converter, applicable to the
ISL6442 circuit. The output voltage (VOUT) is regulated to the
reference voltage, VREF. The error amplifier output (COMP pin
voltage) is compared with the oscillator (OSC) modified
sawtooth wave to provide a pulse-width modulated wave with
an amplitude of VIN at the PHASE node. The PWM wave is
smoothed by the output filter (L and C). The output filter
capacitor bank’s equivalent series resistance is represented by
the series resistor E.
FN9204.2
October 31, 2008
ISL6442
to the FB pin, Ro in Figure 14, the design procedure can
be followed as presented in Equation 12.
C2
COMP
C3
R3
R2
V OSC ⋅ R1 ⋅ F 0
R2 = --------------------------------------------d MAX ⋅ V IN ⋅ F LC
C1
2. Calculate C1 such that FZ1 is placed at a fraction of the FLC,
at 0.1 to 0.75 of FLC (to adjust, change the 0.5 factor to
desired number). The higher the quality factor of the output
filter and/or the higher the ratio FCE/FLC, the lower the FZ1
frequency (to maximize phase boost at FLC).
R1
FB
E/A
+
(EQ. 12)
Ro
VREF
1
C1 = -----------------------------------------------2π ⋅ R2 ⋅ 0.5 ⋅ F LC
VOUT
OSCILLATOR
VIN
PWM
CIRCUIT
HALF-BRIDGE
DRIVE
L
D
PHASE
LGATE
ISL6442
3. Calculate C2 such that FP1 is placed at FCE.
C1
C2 = --------------------------------------------------------2π ⋅ R2 ⋅ C1 ⋅ F CE – 1
VOSC
UGATE
(EQ. 13)
C
E
EXTERNAL CIRCUIT
4. Calculate R3 such that FZ2 is placed at FLC. Calculate C3
such that FP2 is placed below FSW (typically, 0.5 to 1.0
times FSW). FSW represents the switching frequency.
Change the numerical factor to reflect desired placement
of this pole. Placement of FP2 lower in frequency helps
reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at
the COMP pin and minimizing resultant duty cycle jitter.
R1
R3 = ---------------------F SW
------------ – 1
F LC
FIGURE 14. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
(EQ. 14)
1
C3 = ------------------------------------------------2π ⋅ R3 ⋅ 0.7 ⋅ F SW
(EQ. 15)
The modulator transfer function is the small-signal transfer
function of VOUT /VCOMP. This function is dominated by a DC
gain, given by dMAXVIN /VOSC , and shaped by the output
filter, with a double pole break frequency at FLC and a zero at
FCE . For the purpose of this analysis, L and D represent the
channel inductance and its DCR, while C and E represent the
total output capacitance and its equivalent series resistance.
It is recommended a mathematical model is used to plot the
loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (GMOD), feedback
compensation (GFB) and closed-loop response (GCL):
1
F LC = --------------------------2π ⋅ L ⋅ C
(EQ. 10)
d MAX ⋅ V IN
1 + s(f) ⋅ E ⋅ C
G MOD ( f ) = ------------------------------ ⋅ ---------------------------------------------------------------------------------------2
V OSC
1 + s(f) ⋅ (E + D) ⋅ C + s (f) ⋅ L ⋅ C
1
F CE = -----------------------2π ⋅ C ⋅ E
(EQ. 11)
The compensation network consists of the error amplifier
(internal to the ISL6442) and the external R1-R3, C1-C3
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F0; typically 0.1 to 0.3 of FSW) and adequate phase
margin (better than 45°). Phase margin is the difference
between the closed loop phase at F0dB and 180°. The
equations that follow relate the compensation network’s poles,
zeros and gain to the components (R1, R2, R3, C1, C2, and
C3) in Figure 14. Use the following guidelines for locating the
poles and zeros of the compensation network:
(EQ. 16)
1 + s ( f ) ⋅ R2 ⋅ C1
G FB ( f ) = ------------------------------------------------------ ⋅
s ( f ) ⋅ R1 ⋅ ( C1 + C2 )
(EQ. 17)
1 + s ( f ) ⋅ ( R1 + R3 ) ⋅ C3
⋅ ----------------------------------------------------------------------------------------------------------------------------C1
⋅
C2
( 1 + s ( f ) ⋅ R3 ⋅ C3 ) ⋅ ⎛ 1 + s ( f ) ⋅ R2 ⋅ ⎛ ----------------------⎞ ⎞
⎝
⎝ C1 + C2⎠ ⎠
G CL ( f ) = G MOD ( f ) ⋅ G FB ( f )
(EQ. 18)
where:
s ( f ) = 2π ⋅ f ⋅ j
1. Select a value for R1 (1kΩ to 5kΩ, typically). Calculate
value for R2 for desired converter bandwidth (F0). If
setting the output voltage via an offset resistor connected
13
FN9204.2
October 31, 2008
ISL6442
COMPENSATION BREAK FREQUENCY EQUATIONS
Linear Regulator Compensation
1
F Z1 = -------------------------------2π ⋅ R2 ⋅ C1
(EQ. 19)
DISCUSSION
1
F Z2 = --------------------------------------------------2π ⋅ ( R1 + R3 ) ⋅ C3
(EQ. 20)
1
F P1 = ----------------------------------------------C1 ⋅ C2
2π ⋅ R2 ⋅ ---------------------C1 + C2
(EQ. 21)
1
F P2 = -------------------------------2π ⋅ R3 ⋅ C3
(EQ. 22)
Figure 15 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the previously mentioned guidelines
should yield a compensation gain similar to the curve plotted.
The open loop error amplifier gain bounds the compensation
gain. Check the compensation gain at FP2 against the
capabilities of the error amplifier. The closed loop gain, GCL, is
constructed on the log-log graph of Figure 15 by adding the
modulator gain, GMOD (in dB), to the feedback compensation
gain, GFB (in dB). This is equivalent to multiplying the
modulator transfer function and the compensation transfer
function and then plotting the resulting gain.
FP1
FP2
GAIN
FZ1 FZ2
R2
20 log ⎛ --------⎞
⎝ R1⎠
MODULATOR GAIN
COMPENSATION GAIN
CLOSED LOOP GAIN
OPEN LOOP E/A GAIN
IN
20 log --------------------------------V
OSC
GFB
LOG
GCL
GMOD
LOG
FLC
FCE
F0
FREQUENCY
FIGURE 15. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
A stable control loop has a gain crossing with close to a
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin. The mathematical model presented makes a
number of approximations and is generally not accurate at
frequencies approaching or exceeding half the switching
frequency. When designing compensation networks, select
target crossover frequencies in the range of 10% to 30% of
the switching frequency, FSW.
14
1
F P1 = --------------------------------------------------2π • R OUT • C OUT
(EQ. 23)
where:
1
R OUT = -----------------------------------------------1
1
------------------------------------ + ----R301 + R302 r o
(EQ. 24)
For most pass elements, ro is approximately 100kΩ.
It also has a zero determined by the ESR value of the output
capacitor and the Capacitance value of the output capacitor:
1
F Z1 = --------------------------------------------------2π • R ESR • C OUT
(EQ. 25)
The compensation network is composed of R300, C300, the
internal circuitry of the ISL6442, β (also know as hFE in data
sheets) of the pass element, and the Miller capacitance of
the pass element. The pole is located at:
1
F P2 = ---------------------------------2π • R X • C X
d MAX ⋅ V
0
The linear regulator controller controls an external pass
element, typically a PNP bipolar junction transistor; see
Figure 16 for reference. The error amplifier in the ISL6442
has approximately 72dB (V) of gain. The linear regulator
circuit must be compensated such that the gain of the
internal error amplifier crosses through 0dB with a slope of
20dB/decade. This allows easily predictable phase response
through the 0dB point. The output circuit has a dominant
pole determined by the output capacitance and the
combination of the sense resistor and the output resistance
of the BJT.
(EQ. 26)
where:
1
R X = -----------------------------------------------------------------------1
1
1
-------------- + -------------------- + -----------------------R300 1.20kΩ 320Ω • β
(EQ. 27)
and:
C X = C300 + 180pF + C Miller
(EQ. 28)
If CMiller is unspecified, use 1000pF.
The Zero is located at:
1
F Z2 = ----------------------------------------------------------2π • ESR C300 • C300
(EQ. 29)
FN9204.2
October 31, 2008
ISL6442
Q300
R307
VIN3
VIN
CIN3
LCDR
ISL6442
R300
C300
VOUT3
UGATE
Q1
LOUT
R301
R302
COUT3
VOUT
PHASE
CIN
Q2
LGATE
COUT
LOAD
LCFB
PGND
FIGURE 16. LINEAR COMPENSATION COMPONENTS
RETURN
Strategy
1. The output capacitor of the linear regulator circuit must be
chosen such that the ESR Zero is less than 200kHz:
F Z1 < 200kHz
FIGURE 17. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
(EQ. 30)
V OUT3 – 0.6V
R301 = -------------------------------------I sen
(EQ. 31)
0.6V
R302 = -----------I sen
(EQ. 32)
+VIN
VCC
CVCC
BOOT
CBOOT C
IN
Q1 L
OUT
ISL6442
SS
4. Make:
F Z1
F P2 = ---------10
(EQ. 33)
5. Fix R300 at 100Ω. Solve for C300. Use an MLCC, COG
or NPO type capacitor for this value.
Layout Considerations
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
wide, short printed circuit traces. The critical components
should be located as close together as possible using ground
plane construction or single point grounding.
Figure 17 shows the critical power components of the
converter. To minimize the voltage overshoot, the
interconnecting wires indicated by heavy lines should be part
of ground or power plane in a printed circuit board. The
components shown in Figure 17 should be located as close
together as possible. Please note that the capacitors CIN
and COUT each represent numerous physical capacitors.
Locate the ISL6442 within 1 inch of the MOSFETs, Q1 and
Q2. The circuit traces for the MOSFETs’ gate and source
connections from the ISL6442 must be sized to handle up to
2A peak current.
15
+VIN
RT
where Isen = is the current through the resistor divider,
and 0.6V is the internal voltage reference that LCFB will
equal.
3. Compute the pole and zero for the linear regulator circuit
from Equations 31 and 32.
PHASE
Q2 COUT
VOUT
LOAD
2. The voltage divider can be chosen to sink 250µA to
1.5mA of sense current, but this is simply a guideline, not
a rule. The values should be chosen such that
VIN
SGND PGND
RRT CSS
CVIN
PGND
SGND
FIGURE 18. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
Figure 18 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Locate the RT resistor as
close as possible to the RT pin and the SGND pin. Provide
local decoupling between VCC and GND pins.
For each switcher, minimize any leakage current paths on
the SS/EN pin and locate the capacitor, CSS close to the
SS/EN pin because the internal current source is only 30µA.
All of the compensation network components for each
switcher should be located near the associated COMP and
FB pins. Locate the capacitor, CBOOT as close as practical
to the BOOT and PHASE pins (but keep the noisy PHASE
plane away from the IC (except for the PHASE pin
connection).
The OCSET circuits (see Figure 2) should have a separate
trace from the upper FET to the OCSET R and C; that will
more accurately sense the VIN at the FET than just tying
them to the VIN plane. The OCSET R and C should be
placed near the IC pins.
FN9204.2
October 31, 2008
ISL6442
Shrink Small Outline Plastic Packages (SSOP)
Quarter Size Outline Plastic Packages (QSOP)
M24.15
N
INDEX
AREA
H
0.25(0.010) M
24 LEAD SHRINK SMALL OUTLINE PLASTIC PACKAGE
(0.150” WIDE BODY)
B M
E
1
2
INCHES
GAUGE
PLANE
-B-
SYMBOL
3
L
0.25
0.010
SEATING PLANE
-A-
A
D
h x 45°
-C-
α
e
A2
A1
B
C
0.10(0.004)
0.17(0.007) M
C A M
B S
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication Number 95.
MIN
MAX
MILLIMETERS
MIN
MAX
NOTES
A
0.053
0.069
1.35
1.75
-
A1
0.004
0.010
0.10
0.25
-
A2
-
0.061
-
1.54
-
B
0.008
0.012
0.20
0.30
9
C
0.007
0.010
0.18
0.25
-
D
0.337
0.344
8.55
8.74
3
E
0.150
0.157
3.81
3.98
4
e
0.025 BSC
0.635 BSC
-
H
0.228
0.244
5.80
6.19
-
h
0.0099
0.0196
0.26
0.49
5
L
0.016
0.050
0.41
1.27
6
N
α
24
0°
24
8°
0°
7
8°
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
Rev. 2 6/04
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch)
per side.
5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of “B”
dimension at maximum material condition.
10. Controlling dimension: INCHES. Converted millimeter dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
16
FN9204.2
October 31, 2008
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising