bq2403x Single-Chip Charge and System

bq2403x Single-Chip Charge and System
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bq24030, bq24031, bq24032A, bq24035, bq24038
SLUS618I – AUGUST 2004 – REVISED DECEMBER 2014
bq2403x Single-Chip Charge and System Power-path Management IC (bqTINY™)
1 Features
3 Description
•
•
The bqTINY™ III-series of devices are highly
integrated Li-ion linear chargers and system powerpath management devices targeted at space-limited
portable applications. The bqTINY III-series offer
integrated USB-port and DC supply (AC adapter),
power-path management with autonomous powersource selection, power FETs and current sensors,
high accuracy current and voltage regulation, charge
status, and charge termination, in a single monolithic
device.
1
•
•
•
•
•
•
•
•
•
•
•
•
Small 3.5-mm × 4.5-mm QFN Package
Designed for Single-Cell Li-Ion- or Li-PolymerBased Portable Applications
Integrated Dynamic Power-Path Management
(DPPM) Feature Allowing the AC Adapter or the
USB Port to Simultaneously Power the System
and Charge the Battery
Power Supplement Mode Allows Battery to
Supplement the USB or AC Input Current
Autonomous Power Source Selection (AC Adapter
or USB)
Integrated USB Charge Control With Selectable
100-mA and 500-mA Maximum Input Current
Regulation Limits
Dynamic Total Current Management
for USB
Supports Up to 2-A Total Current
3.3-V Integrated LDO Output
Thermal Regulation for Charge Control
Charge Status Outputs for LED or System
Interface Indicates Charge and Fault Conditions
Reverse Current, Short-Circuit, and Thermal
Protection
Power Good (AC Adapter and USB Port Present)
Status Outputs
Charge Voltage Options: 4.1 V, 4.2 V, or 4.36 V
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE (NOM)
bq24030
bq24031
bq24032A
VQFN (20)
4.50 mm × 3.50 mm
bq24035
bq24038
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications
•
•
•
•
The bqTINY III-series powers the system while
independently charging the battery. This feature
reduces the charge and discharge cycles on the
battery, allows for proper charge termination and
allows the system to run with an absent or defective
battery pack. This feature also allows for the system
to instantaneously turn on from an external power
source in the case of a deeply discharged battery
pack. The IC design is focused on supplying
continuous power to the system when available from
the AC, USB, or battery sources.
Smart Phones and PDAs
MP3 Players
Digital Cameras Handheld Devices
Internet Appliances
4 Power Flow Diagram
AC Adapter
(2)
AC
OUT
VDC
USB Port
D+
D−
GND
System
Q1
USB
40 mW
BAT
PACK+
+
VBUS
PACK−
GND
Q3
bq2403x
Q2
UDG−04082
(1)
See Figure 2 and Functional Block Diagram for more detailed feature information.
(2)
P-FET back gate body diodes are disconnected to prevent body diode conduction.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
bq24030, bq24031, bq24032A, bq24035, bq24038
SLUS618I – AUGUST 2004 – REVISED DECEMBER 2014
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
9
Features ..................................................................
Applications ...........................................................
Description .............................................................
Power Flow Diagram .............................................
Revision History.....................................................
Description (continued).........................................
Device Options.......................................................
Pin Configuration and Functions .........................
Specifications.........................................................
9.1
9.2
9.3
9.4
9.5
9.6
9.7
1
1
1
1
2
3
3
4
5
Absolute Maximum Ratings ..................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 6
Dissipation Ratings ................................................... 6
Electrical Characteristics........................................... 6
Typical Characteristics ............................................ 10
10 Detailed Description ........................................... 11
10.1 Overview ............................................................... 11
10.2 Functional Block Diagram .................................... 12
10.3 Feature Description............................................... 13
10.4 Device Functional Modes...................................... 17
11 Application and Implementation........................ 23
11.1 Application Information.......................................... 23
11.2 Typical Application ............................................... 23
12 Power Supply Recommendations ..................... 27
13 Layout................................................................... 28
13.1 Layout Guidelines ................................................. 28
13.2 Layout Example .................................................... 28
13.3 Thermal Considerations ........................................ 29
14 Device and Documentation Support ................. 30
14.1
14.2
14.3
14.4
14.5
14.6
Device Support......................................................
Documentation Support ........................................
Related Links ........................................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
30
30
30
30
30
30
15 Mechanical, Packaging, and Orderable
Information ........................................................... 30
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (October 2009) to Revision I
•
Page
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
Changes from Revision G (Sept 2007) to Revision H
Page
•
Changed "safety timer" to "fast-charge safety timer" for TMR description............................................................................. 4
•
Changed "safety timer" to "fast-charge safety timer" in footnote, and expanded footnote description. ................................. 9
•
Changed "all safety timers" to "the fast-charge safety timer" (and added parenthetical statement regarding the precharge safety timer) in Charge Timer Operation paragraph................................................................................................. 21
2
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SLUS618I – AUGUST 2004 – REVISED DECEMBER 2014
6 Description (continued)
The power select pin, PSEL, defines which input source is to be used first (primary source – AC or USB). If the
primary source is not available, then the IC automatically switches over to the other secondary source if available
or the battery as the last option. If the PSEL is set low, the USB input is selected first and if not available, the AC
line is selected (if available) but programmed to a USB input limiting rate (100 mA/500 mA max). This feature
allows the use of one input connector, where the host programs the PSEL pin according to what source is
connected (AC adaptor or USB port).
The bq24038 replaces USBPG with pin VBSEL, to enable user selection of the charge voltage. In addition, pin
ACPG was modified to PG. PG is active low when either ac power or USB power is detected.
The ISET1 pin programs the battery's fast charge constant current level with a resistor. During normal AC
operation, the input supply provides power to both the OUT (System) and BAT pins. For peak or excessive loads
(typically when operating from the USB power, PSEL = Low) that would cause the input source to enter current
limit (or Q3 - USB FET limiting current) and its source and system voltage (OUT pin) to drop, the dynamic powerpath management (DPPM) feature reduces the charging current attempting to prevent any further drop in system
voltage. This feature allows the selection of a lower current rated adaptor based on the average load (ISYS-AVG +
IBAT-PGM ) rather than a high peak transient load.
7 Device Options
TA
–40°C to 125°C
(1)
(2)
(3)
(4)
(5)
(6)
BATTERY
VOLTAGE (V)
OUT PIN FOR AC
INPUT CONDITIONS (1)
PART
NUMBER (2) (3)
(4)
4.2
Regulated to 6 V
(5)
bq24030RHLR
4.2
Regulated to 6 V (5)
bq24030RHLT
4.1
Regulated to 6 V
(5)
bq24031RHLR
4.1
Regulated to 6 V (5)
bq24031RHLT
4.2
Regulated to 4.4 V (5)
bq24032ARHLR
4.2
Regulated to 4.4 V (5)
bq24032ARHLT
(6)
4.2
Cutoff for AC overvoltage
4.2
Cutoff for AC overvoltage (6)
bq24035RHLR
bq24035RHLT
4.2/4.36 Selectable
Regulated to 4.4 V
bq24038RHLR
4.2/4.36 Selectable
Regulated to 4.4 V
bq24038RHLT
When power is applied via the USB pin (PSEL=low), the input voltage is switched straight through to the OUT pin, unless the USB input
current limit is active, and then the OUT pin voltage will typically drop to the DPPM-OUT threshold or Battery voltage (whichever is
higher).
For the most current package and ordering information, see Mechanical, Packaging, and Orderable Information, or see the TI website at
www.ti.com.
The RHL package is available in the following options:
R - taped and reeled in quantities of 3,000 devices per reel.
T - taped and reeled in quantities of 250 devices per reel.
This product is RoHS compatible, including a lead concentration that does not exceed 0.1% of total product weight, and is suitable for
use in specified lead-free soldering processes. In addition, this product uses package materials that do not contain halogens, including
bromine (Br) or antimony (Sb) above 0.1% of total product weight.
If AC < VO(OUT-REG), the AC is connected to the OUT pin by a P-FET, (Q1).
If AC > V(CUT-OFF) the P-FET disconnects the OUT pin from the AC.
Copyright © 2004–2014, Texas Instruments Incorporated
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8 Pin Configuration and Functions
USB
LDO
RHL Package
20 Pins
Top View
USBPG / VBSEL
STAT1
2
STAT2
3
18
ACPG / PG
AC
4
17
OUT
BAT
5
16
OUT
BAT
6
15
OUT
ISET2
7
14
TMR
PSEL
8
13
DPPM
9 10
ISET1
CE
20 19
11 12
TS
VSS
1
Pin Functions
PIN
NAME
bq24038
bq24030, 31, 32A, 35
I/O
DESCRIPTION
AC
4
4
I
Charge input voltage from AC adapter
ACPG
—
18
O
AC power-good status output (open-drain)
BAT
5, 6
5, 6
I/O
Battery input and output.
CE
9
9
I
Chip enable input (active high)
DPPM
13
13
I
Dynamic power-path management set point (account for scale factor)
ISET1
10
10
I/O
ISET2
7
7
I
Charge current set point for USB port. (High = 500 mA, Low = 100 mA)
LDO
1
1
O
3.3-V LDO regulator
OUT
Charge current set point for AC input and precharge and termination set point for
both AC and USB
15, 16, 17
15, 16, 17
O
Output terminal to the system
PG
18
—
O
AC or USB power-good status output (open-drain)
PSEL
8
8
I
Power source selection input (Low for USB, High for AC)
STAT1
2
2
O
Charge status output 1 (open-drain)
STAT2
3
3
O
Charge status output 2 (open-drain)
TMR
14
14
I/O
Timer program input programmed by resistor. Disable fast-charge safety timer and
termination by tying TMR to LDO.
TS
12
12
I/O
Temperature sense input
USB
20
20
I
USB charge input voltage
USBPG
—
19
O
USB power-good status output (open-drain)
VBSEL
19
—
I
Battery charge voltage selection
–
Ground input (the thermal pad on the underside of the package) There is an
internal electrical connection between the exposed thermal pad and VSS pin of
the device. The exposed thermal pad must be connected to the same potential as
the VSS pin on the printed-circuit board. Do not use the thermal pad as the
primary ground input for the device. VSS pin must be connected to ground at all
times.
VSS
4
11
11
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SLUS618I – AUGUST 2004 – REVISED DECEMBER 2014
9 Specifications
9.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
Input voltage
Input voltage
Input current
Output current
MIN
MAX
UNIT
AC (DC voltage with respect to VSS)
–0.3
18
V
USB (DC voltage with respect to VSS)
–0.3
7
V
BAT, CE, DPPM, ACPG, PSEL, OUT, ISET1, ISET2, STAT1, STAT2, TS,
USBPG , PG, VBSEL (all DC voltages with respect to VSS)
–0.3
7
V
LDO (DC voltage with respect to VSS)
–0.3
VO(OUT) +
0.3
V
TMR
–0.3
VO(LDO) +
0.3
V
AC
3.5
A
USB
1000
mA
OUT
4
A
3.5
A
BAT
(2)
–4
Output source
current (in
regulation at
3.3 V LDO)
LDO
30
mA
Output sink
current
ACPG, STAT1, STAT2, USBPG, PG
15
mA
150
°C
300
°C
150
°C
Junction temperature, TJ
–40
Lead temperature (soldering, 10 seconds)
Storage temperature, Tstg
(1)
(2)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltage
values are with respect to the network ground terminal unless otherwise noted.
Negative current is defined as current flowing into the BAT pin.
9.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
UNIT
±1000
V
±250
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
9.3 Recommended Operating Conditions
VCC
Supply voltage (from AC input)
(1) (2)
MIN
MAX
bq24030/31/32A/35, bq24038 (at VBSEL = LOW)
4.35
16
bq24038 (at VBSEL = HIGH)
4.55
16
4.35
6
(1)
VCC
Supply voltage (from USB input)
IAC
Input current, AC
IUSB
Input current, USB
TJ
Operating junction temperature range
(1)
(2)
2
0.5
–40
125
UNIT
V
A
°C
VCC is defined as the greater of AC or USB input.
Verify that power dissipation and junction temperatures are within limits at maximum VCC .
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9.4 Thermal Information
bq2403x
THERMAL METRIC (1)
RHL
UNIT
20 PINS
RθJA
Junction-to-ambient thermal resistance
40.1
RθJC(top)
Junction-to-case (top) thermal resistance
42.0
RθJB
Junction-to-board thermal resistance
16.6
ψJT
Junction-to-top characterization parameter
0.7
ψJB
Junction-to-board characterization parameter
16.6
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.2
(1)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
9.5 Dissipation Ratings
(1)
PACKAGE
TA ≤ 40°C
POWER RATING
DERATING FACTOR
TA > 40°C
θJA
20-pin RHL (1)
1.81 W
21 mW/°C
46.87 °C/W
This data is based on using the JEDEC High-K board and the exposed die pad is connected to a Cu pad on the board. This is
connected to the ground plane by a 2×3 via matrix.
9.6 Electrical Characteristics
over junction temperature range (0°C ≤ TJ ≤ 125°C) and the recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT BIAS CURRENTS
ICC(SPLY)
Active supply current, VCC
VVCC > VVCC(min)
1
2
ICC(SLP)
Sleep current (current into BAT pin)
V(AC) < V(BAT), V(USB) < V(BAT),
2.6 V ≤ VI(BAT) ≤ VO(BAT-REG),
Excludes load on OUT pin
2
5
ICC(AS-STDBY)
AC standby current
VI(AC) ≤ 6 V, Total current into AC pin with chip disabled,
Excludes all loads, CE=LOW, after t(CE-HOLDOFF) delay
200
ICC(USB-
USB standby current
Total current into USB pin with chip disabled, Excludes all
loads, CE=LOW, after t(CE-HOLDOFF) delay
200
BAT standby current
Total current into BAT pin with AC and/or USB present
and chip disabled; Excludes all loads (OUT and LDO),
CE=LOW, after t(CE-HOLDOFF) delay, 0°C ≤ TJ ≤ 85°C (1)
Charge done current, BAT
Charge DONE, AC or USB supplying the load
STDBY)
ICC(BATSTDBY)
IIB(BAT)
45
60
1
5
6.4
6.8
mA
μA
HIGH AC CUTOFF MODE
VCUT-OFF
Input ac cutoff voltage, bq24035
VI(AC) > 6.8 V, AC FET (Q1) turns off, USB FET (Q3) turns
on if USB power present, otherwise BAT FET (Q2) turns
on.
6.1
V
LDO OUTPUT
VO(LDO)
Output regulation voltage
Active only if AC or USB is present,
VI(OUT) ≥ VO(LDO) + (IO(LDO) × RDS(on))
3.3
Regulation accuracy (2)
IO(LDO)
Output current
RDS(on)
On resistance
C(OUT)
(3)
–5%
V
5%
OUT to LDO
Output capacitance
20
mA
50
Ω
1
μF
OUT PIN-VOLTAGE REGULATION (4)
VO(OUT-REG)
(1)
(2)
(3)
(4)
6
Output
regulation
voltage
bq24030/31
VI(AC) ≥ 6 V+VDO
6.0
6.3
bq24032A
VI(AC) ≥ 4.4 V+VDO
4.4
4.5
bq24038
VBSEL = HIGH or VBSEL = LOW, VI(AC) > 4.4 V+VDO
4.4
4.5
V
This includes the quiescent current for the integrated LDO.
In standby mode (CE low) the accuracy is ±10%.
LDO output capacitor not required but one with a value of 0.1 μF is recommended.
When power is applied to the USB pin and PSEL is low, the USB input is switched straight through to the OUT pin (not regulated). This
voltage may drop to the DPPM-OUT threshold or battery voltage (which ever is higher) if the USB input current limit is active.
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SLUS618I – AUGUST 2004 – REVISED DECEMBER 2014
Electrical Characteristics (continued)
over junction temperature range (0°C ≤ TJ ≤ 125°C) and the recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUT PIN – DPPM REGULATION
V(DPPM-SET)
DPPM set point (5)
VDPPM-SET < VOUT
2.6
5
V
I(DPPM-SET)
DPPM current source
AC or USB present
95
100
105
μA
SF
DPPM scale factor
V(DPPM-REG)= V(DPPM-SET) × SF
1.139
1.150
1.162
VI(AC) ≥ VCC(min), PSEL = High, II(AC) = 1 A,
(IO(OUT)+ IO(BAT)), or no AC
300
475
VI(USB) ≥ VCC(min), PSEL = Low, ISET2 = High,
II(USB) = 0.4 A, (IO(OUT)+IO(BAT)), or no AC
140
180
VI(USB) ≥ VCC(min), PSEL = Low, ISET2 = Low,
II(USB) = 0.08 A, (IO(OUT)+ IO(BAT))
28
36
40
100
OUT PIN – FET (Q1, Q3, AND Q2) DROP-OUT VOLTAGE (RDSon)
AC to OUT dropout voltage (6)
V(ACDO)
V(USBDO)
(7)
V(BATDO)
USB to OUT dropout voltage
BAT to OUT dropout voltage
(discharging)
VI
(BAT)
≥ 3 V, Ii(BAT)= 1.0 A, VCC < Vi(BAT)
mV
mV
OUT PIN - BATTERY SUPPLEMENT MODE
VBSUP1
VBSUP2
Enter battery supplement mode
(battery supplements OUT current
in the presence of input source
Exit battery supplement mode
VI(BAT)> 2 V
VI(OUT)
≤ VI(BAT)
– 60 mV
VI(OUT)
≥ VI(BAT)
– 20 mV
VI(BAT)> 2 V
V
OUT PIN - SHORT CIRCUIT
IOSH1
BAT to OUT short-circuit recovery
Current source between BAT to OUT for short-circuit
recovery to VI(OUT) ≤ VI(BAT) –200 mV
RSHAC
AC to OUT short-circuit limit
VI(OUT) ≤ 1 V
500
RSHVSB
USB to OUT short-circuit limit
VI(OUT) ≤ 1 V
500
10
mA
Ω
BAT PIN CHARGING – PRECHARGE
V(LOWV)
Precharge to fast-charge transition
threshold
Voltage on BAT
TDGL(F)
Deglitch time for fast-charge to
precharge transition (8)
tFALL = 100 ns, 10 mV overdrive,
VI(BAT) decreasing below threshold
IO(PRECHG)
Precharge range
1 V < VI(BAT) < V(LOWV), t < t(PRECHG),
IO(PRECHG) = (K(SET)× V(PRECHG))/ RSET
V(PRECHG)
Precharge set voltage
1 V < VI(BAT) < V(LOWV), t < t(PRECHG)
230
100
2.9
3
3.1
22.5
10
V
ms
150
mA
250
270
mV
1000
1500
mA
BAT PIN CHARGING - CURRENT REGULATION
IO(BAT)
AC battery charge current range (9)
Vi (BAT) > V(LOWV), VI(OUT) - VI (BAT) > V(DO-MAX),
PSEL = High IOUT(BAT) = (K(SET) × V(SET) / RSET),
VI(OUT) > VO(OUT-REG) + V(DO-MAX)
RPBAT
BAT to OUT pullup
Vi
1V
1000
RPOUT
AC to OUT and USB to OUT shortcircuit pullup
VI(OUT) < 1 V
500
V(SET)
Battery charge current set
voltage (10)
Voltage on ISET1, VVCC ≥ 4.35 V,
VI(OUT)- VI(BAT) > V(DO-MAX), VI(BAT) > V(LOWV)
K(SET)
Charge current set factor, BAT
(BAT)<
Ω
2.475
2.500
2.525
100 mA ≤ IO(BAT) ≤ 1 A
400
425
450
10 mA ≤ IO(BAT) ≤ 100 mA (11)
300
450
600
V
(5)
(6)
V(DPPM-SET) is scaled up by the scale factor for controlling the output voltage V(DPPM-REG).
VDO(max), dropout voltage is a function of the FET, RDS(on), and drain current. The dropout voltage increases proportionally to the
increase in current.
(7) RDS(on) of USB FET Q3 is calculated by: (VUSB – VOUT) / (IOUT + IBAT) when II(USB) ≤ II(USB-MIN) (FET fully on, not in regulation).
(8) All deglitch periods are a function of the timer setting and is modified in DPPM or thermal regulation modes by the percentages that the
program current is reduced.
(9) When input current remains below 2 A, the battery charging current may be raised until the thermal regulation limits the charge current.
(10) For half-charge rate, V(SET) is 1.25 V ± 25 mV for bq24032A/38 only.
(11) Specification is for monitoring charge current via the ISET1 pin during voltage regulation mode, not for a reduced fast-charge level.
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Electrical Characteristics (continued)
over junction temperature range (0°C ≤ TJ ≤ 125°C) and the recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
USB PIN INPUT CURRENT REGULATION
USB input current range,
bq24030/32A/35/38 (12)
I(USB)
VI(BAT) > V(LOWV), VI(USB) - VI(BAT) > V(DO-MAX),
ISET2= Low, PSEL = Low, or no AC (13)
100
mA
VI(BAT) > V(LOWV),
VI(USB) - VI(BAT) > V(DO-MAX), ISET2= High,
PSEL = Low, or no AC (12)
400
500
BAT PIN CHARGING VOLTAGE REGULATION, VO (BAT-REG) + V (DO-MAX) < VCC, ITERM < IBAT(OUT) ≤ 1 A
bq24030/32A/35
Battery charge
voltage
VO(BAT-REG)
4.2
bq24031
bq24038
Battery charge voltage regulation
accuracy
4.1
VBSEL = HI
4.36
VBSEL = LO
4.2
TA = 25°C
V
–0.5%
0.5%
–1%
1%
10
150
mA
CHARGE TERMINATION DETECTION
I(TERM)
Charge termination detection range
VI(BAT) < V(RCH), I(TERM) = (K(SET) × V(TERM))/ RSET
V(TERM-AC)
AC-charge termination detection
voltage, measured on ISET1
VI(BAT) > V(RCH) , PSEL = High, ACPG = Low
V(TAPER-USB)
USB-charge termination detection
voltage, measured on ISET1
VI(BAT) > V(RCH), PSEL = Low or
PSEL = High and ACPG = High
TDGL(TERM)
Deglitch time for termination
detection
tFALL = 100 ns, 10 mV overdrive,
ICHG increasing above or decreasing below threshold
235
250
265
mV
95
100
130
mV
22.5
ms
TEMPERATURE SENSE COMPARATORS
VLTF
High voltage threshold
Temp fault at V(TS) > VLTF
2.465
2.500
2.535
VHTF
Low voltage threshold
Temp fault at V(TS) < VHTF
0.485
0.500
0.515
V
ITS
Temperature sense current source
94
100
106
μA
TDGL(TF)
Deglitch time for temperature fault
detection (8)
R(TMR) = 50 kΩ, VI(BAT) increasing or decreasing above and
below; 100-ns fall time, 10-mv overdrive
22.5
V
ms
BATTERY RECHARGE THRESHOLD
VRCH
Recharge threshold voltage
TDGL(RCH)
Deglitch time for recharge
detection (8)
VO(BAT-
VO(BAT-
REG)
REG)
REG)
–0.075
–0.100
–0.125
R(TMR) = 50 kΩ, VI(BAT) increasing
or decreasing below threshold,
100-ns fall time, 10-mv overdrive
22.5
VO(BATV
ms
(12) With the PSEL= low, the bqTINY III-series defaults to USB charging. If USB input is ≤ VBAT, then the bqTINY III-series charges from the
AC input at the USB charge rate. In this configuration, the specification is 400 mA (min) and 500 mA (max).
(13) With the PSEL= low, the bqTINY III-series defaults to USB charging. If USB input is ≤ VBAT, then the bqTINY III-series charges from the
AC input at the USB charge rate. In this configuration, the specification is 80 mA (min) and 100 mA (max).
8
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Electrical Characteristics (continued)
over junction temperature range (0°C ≤ TJ ≤ 125°C) and the recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.25
V
5
μA
STAT1, STAT2. ACPG AND USBPG, PG OPEN DRAIN (OD) OUTPUTS (14)
VOL
Low-level output saturation voltage
ILKG
Input leakage current
IOL = 5 mA, An external pullup
resistor ≥ 1 K required.
1
ISET2, CE, VBSEL INPUTS
VIL
Low-level input voltage
0
VIH
High-level input voltage
1.4
IIL
Low-level input current, CE
–1
IIH
High-level input current, CE
IIL
Low-level input current, ISET2
VISET2 = 0 V
IIH
High-level input current, ISET2
VISET2 = VCC
IIL1
Low-level input current
VBSEL = Low
IIH1
High-level input current
VBSEL = High
t(CE-HLDOFF)
Holdoff time, CE
CE going low only
Low-level input voltage
Falling Hi→Low; 280 K ± 10% applied when low.
0.4
V
1
–20
40
6
μA
1
15
3.3
6.2
ms
PSEL INPUT
VIL
VIH
High-level input voltage
Input RPSEL sets external hysteresis
IIL
Low-level input current, PSEL
IIH
High-level input current, PSEL
0.975
1
VIL + 0.01
1.025
V
VIL +
0.024
V
μA
–1
μA
TIMERS
K(TMR)
R(TMR)
Timer set factor
(15)
t(CHG) = K(TMR) × R(TMR)
0.313
External resistor limits
0.360
30
0.09 ×
t(CHG)
t(PRECHG)
Precharge timer
I(FAULT)
Timer fault recovery pullup from
OUT to BAT
0.10 ×
t(CHG)
0.414
s/Ω
100
kΩ
0.11 ×
t(CHG)
1
s
kΩ
CHARGER SLEEP THRESHOLDS (ACPG , PG, and USBPG THRESHOLDS, LOW → POWER GOOD)
V(SLPENT)
Sleep-mode entry threshold
V(UVLO) ≤ VI(BAT) ≤ VO(BAT-REG),
No t(BOOT-UP) delay
V(SLPEXIT)
(16)
Sleep-mode exit threshold
V(UVLO) ≤ VI(BAT) ≤ VO(BAT-REG),
No t(BOOT-UP) delay
t(DEGL)
Deglitch time for sleep mode (17)
R(TMR) = 50 kΩ,
V(AC) or V(USB) or decreasing below threshold, 100-ns fall
time, 10-mv overdrive
(16)
VVCC ≤
VI(BAT)
+125 mV
VVCC ≥
VI(BAT)
+190 mV
22.5
V
ms
(14) See Charger Sleep mode for ACPG (VCC = VAC) and USBPG (VCC = VUSB) specifications.
(15) To disable the fast-charge safety timer and charge termination, tie TMR to the LDO pin. Tying the TMR pin high changes the timing
resistor from the external value to an internal 50 kΩ ±25%, which can add an additional tolerance to any timed spectification. The TMR
pin normally regulates to 2.5 V when the charge current is not restricted by the DPPM or thermal feedback loops. If these loops become
active, the TMR pin voltage will be reduced proportionally to the reduction in charge current and the clock frequency will be reduced by
the same percentage (timed durations will count down slower, extending their time). The TMR pin is clamped at 0.80 V, for a maximum
time extension of 2.5 V ÷ 0.8 V × 100 = 310%.
(16) The IC is considered in sleep mode when both AC and USB are absent (ACPG = USBPG = OPEN DRAIN).
(17) Does not declare sleep mode until after the deglitch time and implement the needed power transfer immediately according to the
switching specification.
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Electrical Characteristics (continued)
over junction temperature range (0°C ≤ TJ ≤ 125°C) and the recommended supply voltage range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
120
150
180
ms
START-UP CONTROL and USB BOOT-UP
t(BOOT-UP)
On the first application of USB input power or AC input
with PSEL Low
Boot-up time
SWITCHING POWER SOURCE TIMING
tSW-BAT
Switching power source from inputs
(AC or USB) to battery
tSW-AC/USB
Switching from AC to USB, or, USB
to AC by input source removal. (18)
tSW-PSEL
Switching from AC to USB, or USB
to AC by toggling PSEL
Only AC power or USB power applied. Measure from:
[xxPG: Lo → Hi to I(xx) > 5 mA],
xx = AC or USB I(OUT) = 100 mA, RTRM = 50 K
50
Measure from:
I(AC) < 5 mA to I(USB) > 5 mA or I(USB)
< 5 mA → I(AC) > 5 mA;
I(OUT) = 100 mA, RTMR = 50 K,
ISET2 = hi, ROUT > 15 Ω, VDPPM = 2.5 V
100
50
μs
100
THERMAL SHUTDOWN REGULATION (19)
T(SHTDWN)
TJ(REG)
Temperature trip
TJ (Q1 and Q3 only)
155
Thermal hysteresis
TJ (Q1 and Q3 only)
30
Temperature regulation limit
TJ (Q2)
115
Undervoltage lockout
Decreasing VCC
2.45
°C
135
UVLO
V(UVLO)
2.50
Hysteresis
27
2.65
V
mV
(18) The power handoff is implemented once the PG pin goes high (removed sources PG) which is when the removed source drops to the
battery voltage. If the battery voltage is critically low, the system may lose power unless the system takes control of the PSEL pin and
switches to the available power source prior to shutdown. The USB source often has less current available; so, the system may have to
reduce its load when switching from AC to USB.
(19) Reaching thermal regulation reduces the charging current. Battery supplement current is not restricted by either thermal regulation or
shutdown. Input power FETs turn off during thermal shutdown. The battery FET is only protected by a short-circuit limit which typically
does not cause a thermal shutdown (input FETs turning off) by itself.
9.7 Typical Characteristics
4.44
VOUT, VAC = 5.5 V
II = 100 A
+3 Sigma
4.42
Voltage - V
4.4
Mean
4.38
4.36
-3 Sigma
4.34
4.32
-60
-40
-20
0
20
40
60
80
100
120
140
o
T - Temperatures - C
Figure 1. Typical OUT Voltage Regulation, bq24032A
10
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10 Detailed Description
10.1 Overview
The bqTINY III-series of devices are highly integrated Li-ion linear chargers and system power-path management
devices targeted at space-limited portable applications. The bqTINY III-series offer integrated USB-port and DC
supply (AC adapter), power-path management with autonomous power-source selection, power FETs and
current sensors, high accuracy current and voltage regulation, charge status, and charge termination, in a single
monolithic device.
The bqTINY III-series supports a precision Li-ion or Li-polymer charging system suitable for single-cell portable
devices. See a typical charge profile, application circuit, and an operational flow chart in Figure 2 through
Figure 6, respectively.
Pre-Conditioning
Phase
Current Regulation Phase
Voltage Regulation and Charge Termination Phase
Regulation
Voltage
Regulation
Current
Charge
Voltage
Minimum
Charge
Voltage
Charge
Complete
Charge
Current
Pre−
Conditioning
and Term
Detect
UDG−04087
Figure 2. Charge Profile
The bqTINY III-series power the system while independently charging the battery. This feature reduces the
charge and discharge cycles on the battery, allows for proper charge termination and allows the system to run
with an absent or defective battery pack. This feature also allows for the system to instantaneously turn on from
an external power source in the case of a deeply discharged battery pack. The IC design is focused on supplying
continuous power to the system when available from the AC adapter, USB port or battery sources.
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10.2 Functional Block Diagram
Short−Circuit Recovery
500 Ω
BAT
Short−Circuit
Recovery
USB
Charge
Enable
100 mA /
500 mA
AC
VO(OUT)
OUT
VO(LDO)
Q1
1 kΩ
3.3−V LDO
Fault
Recovery
LDO
10 mA
VSET
500 Ω
+
VIO(AC)
AC Charge
Enable
Short Circuit
Recovery
VI(IUSB−SNS)
VO(OUT)
Q2
Q3
+
VI(BAT)
BAT
VO(OUT−REG)
VI(IUSB−SNS)
USB
VI(ISET1)
ISET1
Reference, Bias & UVLO
VI(IUSB−SNS)
UVLO
TMR
Oscillator
VI(BAT)
VI(BAT)
USB
Charge
Enable
+
VO(BAT−REG)
VI(ISET1)
VO(OUT)
DPPM
+
DPPM
I(DPPM) Scaling
BAT
Charge
Enable
VSET
VDPPM
+
+
Disable−
Sleep
200 mV
Suspend
Thermal
Shutdown
1V
+
I(TS)
TS
+
VO(OUT)
TJ(REG)
*
60 mV
VI(BAT)
+
TJ
V(HTF)
+
Fast Precharge
+
1V
+
100 mA / 500 mA
VSET
VO(BAT−REG)
+
*
V(LTF)
280 kΩ
Power Source Selection
USB Charge Enable
PSEL
AC Charge Enable
CE
BAT Charge Enable
VO(BAT−REG)
Recharge
VBAT
*
Precharge
VBAT
*
Charge
Control
Timer
and
Display
Logic
500 mA/ 100 mA
Fast Precharge
1C − 500 mA
C/S − 100 mA
ISET2
ACPG
V(SET)
VI(ISET1)
USBPG
Term
*
STAT1
VBAT
VAC
VSS
12
STAT2
Sleep (USB)
VBAT
VUSB
(1)
Sleep (AC)
*
*
*
Signal Deglitched
UDG−04084
For bq24038 see bq24038 Differences.
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10.3 Feature Description
10.3.1 bq24038 Differences
The bq24038 replaces USBPG with pin VBSEL, to enable user selection of the charge voltage. In addition, pin
ACPG was modified to PG. PG is active low when either AC power or USB power is detected.
10.3.2 Power-Path Management
The bqTINY III-series powers the system while independently charging the battery. This features reduces the
charge and discharge cycles on the battery, allows for proper charge termination, and allows the system to run
with an absent or defective battery pack. This feature gives the system priority on input power, allowing the
system to power up with a deeply discharged battery pack. This feature works as follows (note that PSEL is
assumed HIGH for this discussion).
AC Adapter
(2)
AC
OUT
VDC
USB Port
GND
D+
D−
System
Q1
USB
40 mW
BAT
PACK+
+
VBUS
PACK−
GND
Q3
bq2403x
Q2
UDG−04082
Figure 3. Power-Path Management
10.3.2.1 Case 1: AC Mode (PSEL = High)
10.3.2.1.1 System Power
In this case, the system load is powered directly from the AC adapter through the internal transistor Q1 (see
Figure 3). For bq24030/31, Q1 acts as a switch as long as the AC input remains at or below 6 V (VO(OUT-REG)).
Once the AC voltage goes above 6 V, Q1 starts regulating the output voltage at 6 V. For bq24035, once the AC
voltage goes above VCUT-OFF (~6.4 V), Q1 turns off. For bq24032A/38, the output is regulated at 4.4 V from the
AC input. Note that switch Q3 is turned off for both devices. If the system load exceeds the capacity of the
supply, the output voltage drops down to the battery's voltage.
10.3.2.1.2 Charge Control
When AC is present, the battery is charged through switch Q2 based on the charge rate set on the ISET1 input.
10.3.2.1.3 Dynamic Power-Path Management (DPPM)
This feature monitors the output voltage (system voltage) for input power loss due to brown outs, current limiting,
or removal of the input supply. If the voltage on the OUT pin drops to a preset value, V(DPPM-SET) × SF, due to a
limited amount of input current, then the battery charging current is reduced until the output voltage stops
dropping. The DPPM control tries to reach a steady-state condition where the system gets its needed current and
the battery is charged with the remaining current. No active control limits the current to the system; therefore, if
the system demands more current than the input can provide, the output voltage drops just below the battery
voltage and Q2 turns on which supplements the input current to the system. DPPM has three main advantages.
1. This feature allows the designer to select a lower power wall adapter, if the average system load is moderate
compared to its peak power. For example, if the peak system load is 1.75 A, average system load is 0.5 A
and battery fast-charge current is 1.25 A, the total peak demand could be 3 A. With DPPM, a 2-A adaptor
could be selected instead of a 3.25-A supply. During the system peak load of 1.75 A and charge load of 1.25
A, the smaller adaptor’s voltage drops until the output voltage reaches the DPPM regulation voltage
threshold. The charge current is reduced until there is no further drop on the output voltage. The system gets
its 1.75-A charge and the battery charge current is reduced from 1.25 A to 0.25 A. When the peak system
load drops to 0.5 A, the charge current returns to 1 A and the output voltage returns to its normal value.
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Feature Description (continued)
2. Using DPPM provides a power savings compared to configurations without DPPM. Without DPPM, if the
system current plus charge current exceed the supply’s current limit, then the output is pulled down to the
battery. Linear chargers dissipate the unused power (VIN-VOUT) × ILOAD. The current remains high (at current
limit) and the voltage drop is large for maximum power dissipation. With DPPM, the voltage drop is less (VINV(DPPM-REG)) to the system which means better efficiency. The efficiency for charging the battery is the same
for both cases. The advantages include less power dissipation, lower system temperature, and better overall
efficiency.
3. The DPPM sustains the system voltage no matter what causes it to drop, if at all possible. It does this by
reducing the noncritical charging load while maintaining the maximum power output of the adaptor.
Note that the DPPM voltage, V(DPPM-REG), is programmed as follows:
V(DPPM-REG) = I(DPPM) ´ R(DPPM) ´ SF
where
•
•
•
R(DPPM) is the external resistor connected between the DPPM and VSS pins.
I(DPPM) is the internal current source.
SF is the scale factor as specified in the specification table.
(1)
The safety timer is dynamically adjusted while in DPPM mode. The voltage on the ISET1 pin is directly
proportional to the programmed charging current. When the programmed charging current is reduced, due to
DPPM, the ISET1 and TMR voltages are reduced and the timer’s clock is proportionally slowed, extending the
safety time. In normal operation, V(TMR) = 2.5 V; when the clock is slowed the voltage V(TMR) is reduced. For
example, if V(TMR) = 1.25 V, the safety timer has a value close to 2 times the normal operation timer value. See
Figure 8 through Figure 11.
10.3.2.2 Case 2: USB (PSEL = Low) bq24030/31/32A/38
10.3.2.2.1 System Power
In this case, the system load is powered directly from the USB port through the internal switch Q3 (see Figure 4).
Note in this case, Q3 regulates the total current to the 100 mA or 500 mA level, as selected on the ISET2 input.
Switch Q1 is turned off in this mode. If the system and battery load is less than the selected regulated limit, then
Q3 is fully on and VOUT is approximately (V(USB)-V(USB-DO)). The systems power management is responsible for
keeping its system load below the USB current level selected (if the battery is critically low or missing).
Otherwise, the output drops to the battery voltage; therefore, the system should have a low power mode for USB
power application. The DPPM feature keeps the output from dropping below its programmed threshold, due to
the battery charging current, by reducing the charging current.
10.3.2.2.2 Charge Control
When USB is present and selected, Q3 regulates the input current to the value selected by the ISET2 pin
(0.1/0.5 A). The charge current to the battery is set by the ISET1 resistor (typically > 0.5 A). Because the charge
current typically is programmed for more current than Q3 allows, the output voltage drops to the battery voltage
or DPPM voltage, whichever is higher. If the DPPM threshold is reached first, the charge current is reduced until
VOUT stops dropping. If VOUT drops to the battery voltage, the battery is able to supplement the input current to
the system.
10.3.2.2.3 Dynamic Power-Path Management (DPPM)
The theory of operation is the same as described in CASE 1, except that Q3 restricts the amount of input current
delivered to the output and battery instead of the input supply.
Note that the DPPM voltage, V(DPPM), is programmed as follows:
V(DPPM-REG) = I(DPPM) ´ R(DPPM) ´ SF
(2)
and
V(DPPM-REG) = V(DPPM-SET) ´ SF
where
•
14
R(DPPM) is the external resistor connected between the DPPM and VSS pins.
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Feature Description (continued)
•
•
I(DPPM) is the internal current source.
SF is the scale factor as specified in the specification table.
(3)
10.3.2.2.4 Battery Temperature Monitoring
The bqTINY™ III-series continuously monitors battery temperature by measuring the voltage between the TS
and VSS pins. An internal current source (I(TS) = 100 μA, typical) provides the bias for most common 10-kΩ
negative-temperature coefficient thermistors (NTC) (see Figure 4). The device compares the voltage on the TS
pin against the internal V(LTF) , and V(HTF) thresholds (0.5 V and 2.5 V, respectively are typical) to determine if
charging is allowed. Once a temperature outside the V(LTF) and V(HTF) thresholds is detected, the device
immediately suspends the charge. The device suspends charge by turning off the power FET and holding the
timer value (i.e., timers are not reset). Charge is resumed when the temperature returns to the normal range. The
allowed temperature range for 103AT-type thermistor is 0°C to 45°C. However, the user may increase the range
by adding two external resistors. See Figure 5.
PACK+
bqTINYIII
PACK−
ITS
PACK−
TS
NTC
9
BATTERY
PACK
VLTF
HTF
+
ITS
TS
LTF
PACK+
bqTINYIII
+
VHTF
LTF
9
VLTF
RT2
HTF
NTC
RT1 TEMP
BATTERY
PACK
VHTF
UDG−04086
UDG−04085
Figure 4. TS Pin Configuration
Figure 5. TS Pin Thresholds
10.3.3 Charge Status Outputs
The open-drain (OD) STAT1 and STAT2 outputs indicate various charger operations as shown in Table 1. These
status pins can be used to drive LEDs or communicate to the host processor. Note that OFF indicates the opendrain transistor is turned off. Note that this assumes CE = High.
Table 1. Status Pins Summary
10.3.4
CHARGE STATE
STAT1
STAT2
Precharge in progress
ON
ON
Fast charge in progress
ON
OFF
Charge done
OFF
ON
Charge suspend (temperature), timer fault, and sleep mode
OFF
OFF
ACPG, USBPG Outputs (Power Good), bq24030/31/32A/35
The two open-drain pins, ACPG, USBPG (AC and USB power good), indicate when the AC adapter or USB port
is present and above the battery voltage. The corresponding output turns ON (low) when exiting sleep mode
(input voltage above battery voltage). This output is turned off in the sleep mode (open drain). The ACPG,
USBPG pins can be used to drive an LED or communicate to the host processor. Note that OFF indicates the
open-drain transistor is turned off.
10.3.5
PG Output (Power Good), bq24038
The open-drain pin PG indicates when either the AC adapter or USB port is present and above the battery
voltage. This output is turned off in sleep mode (open drain). The PG pin can be used to drive a LED or
communicate with the host processor.
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10.3.6 CE Input (Chip Enable)
The CE (chip enable) digital input is used to disable or enable the bqTINY III-series. A high-level signal on this
pin enables the chip, and a low-level signal disables the device and initiates the standby mode. The bqTINY IIIseries enters the low-power standby mode when the CE input is low with either AC or USB present. In this
suspend mode, internal power FETs Q1 and Q3 (see Figure 3) are turned off; the battery (BAT pin) is used to
power the system via Q2 and the OUT pin which also powers the LDO. This feature is designed to limit the
power drawn from the input supplies (such as USB suspend mode).
10.3.7 VBSEL Input (Battery Voltage Selection), bq24038
The VBSEL (battery voltage select) digital input pin can be used to set the charge voltage to 4.2 V typical
(VBSEL = low) or 4.36 V typical (VBSEL = high). If VBSEL is left open, an internal current source pulldown
ensures that the charge voltage is set to 4.2 V typical.
10.3.8 DPPM Used As A Charge Disable Function
The DPPM pin can be used to disable the charge process. The DPPM pin has an output current source that,
when used with a resistor, sets the DPPM threshold. If the chosen resistance is too high, then the "DPPM-OUT"
voltage is programmed higher than the OUT pin regulation voltage and the part is put in DPPM mode. In this
mode the charging current is reduced until the OUT pin recovers to the DPPM_OUT threshold. Since the OUT
pin is in voltage regulation (below the DPPM-OUT threshold) it does not increase in amplitude, and the charge
current turns completely off. In DPPM mode the charge termination is diabled.
Note that the OUT pin regulates at 4.4V ±0.1V, with an adaptor input, on the bq24032A/bq24038 ICs, is switched
straight through on the bq24030/5 ICs (up to 6V); and, on USB inputs (all ICs) is switched straight through from
the USB input to the OUT pin.
If the DPPM pin is floated (resistor disconnected) then the DPPM pin will be driven high and the charge current
will go to zero. Note that this applies to both AC and USB charging. Another way to disable the charging is to
externally drive the DPPM pin high (to the OUT pin voltage).
10.3.9 Timer Fault Recovery
As shown in Figure 6, bqTINY III-series provides a recovery method to deal with timer fault conditions. The
following summarizes this method:
Condition 1: Charge voltage above recharge threshold (V(RCH)) and timeout fault occurs.
Recovery Method: bqTINY III-series waits for the battery voltage to fall below the recharge threshold. This could
happen as a result of a load on the battery, self-discharge, or battery removal. Once the battery falls below the
recharge threshold, the bqTINY III-series clears the fault and starts a new charge cycle. A POR or CE toggle also
clears the fault.
Condition 2: Charge voltage below recharge threshold (V(RCH)) and timeout fault occurs.
Recovery Method: Under this scenario, the bqTINY III-series applies the I(FAULT) current. This small current is
used to detect a battery removal condition and remains on as long as the battery voltage stays below the
recharge threshold. If the battery voltage goes above the recharge threshold, then the bqTINY III-series disables
the I(FAULT) current and executes the recovery method described for condition 1. Once the battery falls below the
recharge threshold, the bqTINY III-series clears the fault and starts a new charge cycle. A POR or CE toggle also
clears the fault.
10.3.10 Short-Circuit Recovery
The output can experience two types of short-circuit protection, one associated with the input and one with the
battery.
If the output drops below ~1 V, an output short-circuit condition is declared and the input FETs (AC and USB) are
turned off. To recover from this state, a 500-Ω pullup resistor from each input is applied (switched) to the output.
To recover, the load on the output has to be reduced {Rload > 1 V × 500 Ω/ (Vin–Vout)} such that the pullup
resistor is able to lift the output voltage above 1 V, for the input FETs to be turned back on.
16
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If the output drops 200 mV below the battery voltage, the battery FET is considered in short circuit and the
battery FET turns off. To recover from this state, there is a 10-mA ±8 mA current source from the battery to the
output. Once the output load is reduced, such that the current source can pick up the output within 200 mV of the
battery, the FET turns back on (As Vout increases in voltage the current source's drive drops toward 2 mA).
If the short is removed, and the minimum system load is still too large [R<(VBat –200 mV / 2mA)], the shortcircuit protection can be temporarily defeated. The battery short-circuit protection can be disabled (recommended
only for a short time) if the voltage on the DPPM pin is less than 1 V. Pulsing this pin below 1 V, for a few
microseconds, should be enough to recover.
This short-circuit disable feature was implemented mainly for power up when inserting a battery. Because the
BAT input voltage rises much faster than the OUT voltage (Vout<Vbat-200 mV), with most any capacitive load on
the output, the part can get stuck in short-circuit mode. Placing a capacitor between the DPPM pin and ground
slows the VDPPM rise time, during power up, and delays the short-circuit protection. Too large a capacitance on
this pin (too much of a delay) could allow too-high currents if the output was shorted to ground. The
recommended capacitance is 1 nF to 10 nF. The VDPPM rise time is a function of the 100-µA DPPM current
source, the DPPM resistor, and the capacitor added.
10.3.11 LDO Regulator
The bqTINY III-series provides a 3.3-V LDO regulator. This regulator is typically used to power USB transceiver
or drivers in portable applications. Note that this LDO is only enabled when either AC or USB inputs are present.
If the CE pin is low (chip disabled) and AC or USB is present, the LDO is powered by the battery. This is to
ensure low input current when the chip is disabled.
10.4 Device Functional Modes
10.4.1 Sleep Mode - V(IN) < VI(BAT)
The bqTINY III-series charger circuitry enters the low-power sleep mode if both AC and USB are removed from
the circuit. This feature prevents draining the battery into the bqTINY III-series during the absence of input
supplies. Note that in sleep mode, Q2 remains on (i.e., battery connected to the OUT pin) in order for the battery
to continue supplying power to the system.
The bqTINY III-series enters the low-power standby mode if while AC or USB is present, the CE input is low. In
this suspend mode, internal power FETs Q1 and Q3 (see Figure 3) are turned off, the BAT input is used to
power the system through OUT pin, and the LDO remains on (powered from output). This feature is designed to
limit the power drawn from the input supplies (such as USB suspend mode).
10.4.2 Standby Mode - V(IN) > VI(BAT)and CE (Chip Enable) Pin = Low
The CE (chip enable) digital input is used to disable or enable the IC. A high-level signal on this pin enables the
chip, and a low-level signal disables the device and initiates the standby mode. The bqTINY III-series enters the
low-power standby mode when the CE input is low with input present. In this suspend mode, internal power
FETs Q1 and Q3 (see Figure 3) are turned off, the BAT input is used to power the system through OUT pin, and
the LDO remains on (powered from output). This feature is designed to limit the power drawn from the input
supplies (such as USB suspend mode).
10.4.3 Battery Charge Mode - V(IN) > VI(BAT), Battery Present, CE Pin = High and DPPM Pin Not
Floating
10.4.3.1 Autonomous Power Source Selection, PSEL Control Pin
The PSEL pin selects the priority of the input sources (high = AC, low = USB), if that primary source is not
available (based on ACPG, USBPG signal), then it uses the secondary source. If neither input source is
available, then the battery is selected as the source. With the PSEL input high, the bqTINY III-series attempts to
charge from the AC input. If AC input is not present, the USB is selected. If both inputs are available, the AC
adapter has priority. With the PSEL input low, the bqTINY III-series defaults to USB charging. If USB input is
grounded, then the bqTINY III-series charges from the AC input at the USB charge rate (as selected by ISET2).
This feature can be used in system where AC and USB power source selection is done elsewhere. The PSEL
function is summarized in Table 2.
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Device Functional Modes (continued)
Table 2. Power Source Selection Function Summary
PSEL STATE
Low
High
(1)
(2)
(3)
18
AC
USB
CHARGE
SOURCE
MAXIMUM
CHARGE RATE (1)
SYSTEM
POWER
SOURCE
USB BOOT-UP
FEATURE
Present (2)
Absent
AC
ISET2
AC
Enabled
(3)
Enabled
Absent
Present
USB
ISET2
USB
Present
Present
USB
ISET2
USB
Enabled
Absent
Absent
N/A
N/A
Battery
Disabled
Present
Absent
AC
ISET1
AC
Disabled
Absent
Present
USB
ISET2
USB
Disabled
Present
Present
AC
ISET1
AC
Disabled
Absent
Absent
N/A
N/A
Battery
Disabled
Battery charge rate is always set by ISET1, but may be reduced by a limited input source (ISET2 USB mode) and IOUT system load.
Present is defined as input being at a higher voltage than the BAT voltage (sources power good is low).
AC Absent is defined as AC input not present (ACPG is High) or Q1 turned off due to overvoltage in bq24035.
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10.4.4 Charge Control
POR
SLEEP MODE
Vcc > V I(OUT)
checked at all
times?
No
Indicate SLEEP
MODE
Yes
V I(BAT) < V (LOWV)
Yes
Regulate
IO(PRECHG)
Reset and Start
t(PRECHG)timer
Indicate Charge−
In−Progress
?
No
Reset all timers,
Start t (CHG) timer
Regulate Current
or Voltage
Indicate Charge−
In−Progress
No
V I(OUT) <V(LOWV)
Yes
Yes
No
t(PRECHG)
Expired?
t (CHG)
Expired?
Yes
No
Yes
Yes
Fault Condition
V I(OUT) <V(LOWV)
?
Indicate Fault
No
VI(OUT)> V(RCH)
?
I(TERM)
No
detection?
No
Enable I
(FAULT)
current
Yes
No
Yes
V I(OUT)> V (RCH)
?
Turn off charge
Yes
Yes
Indicate DONE
Disable I (FAULT)
No
current
V I(OUT) < V (RCH)
?
Figure 6. Charge Control Operational Flow Chart
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10.4.4.1 Battery Pre-Conditioning
During a charge cycle, if the battery voltage is below the V(LOWV) threshold (3.0 V, typical), the bqTINY III-series
applies a precharge current, IO(PRECHG), to the battery. This feature revives deeply discharged cells. The resistor
connected between the ISET1 and VSS, RSET, determines the precharge rate. The V(PRECHG) and
K(SET) parameters are specified in the specifications table. Note that this applies to both AC and USB charging.
V(PRECHG) ´ K (SET)
IO(PRECHG) =
RSET
(4)
The bqTINY III-series activates a safety timer, t(PRECHG), during the conditioning phase. If V(LOWV) threshold is not
reached within the timer period, the bqTINY III-series turns off the charger and enunciates FAULT on the STAT1
and STAT2 pins. The timeout is extended if the charge current is reduced by DPPM. See the Timer Fault
Recovery section for additional details.
10.4.4.2 Battery Charge Current
The bqTINY III-series offers on-chip current regulation with programmable set point. The resistor connected
between the ISET1 and VSS, RSET, determines the charge level. The charge level may be reduced to give the
system priority on input current (see DPPM). The V(SET) and K(SET) parameters are specified in the specifications
table.
V(SET) ´ K (SET)
IO(BAT) =
RSET
(5)
When powered from a USB port, the input current available (0.1 A/0.5 A) is typically less than the programmed
(ISET1) charging current, and therefore, the DPPM feature attempts to keep the output from being pulled down
by reducing the charging current.
The charge level for the bq24032A/38, during AC operation only (PSEL = High), can be changed by a factor of 2
by setting the ISET2 pin high (full charge) or low (half charge). The voltage on the ISET1 pin, V(SET), is divided by
2 when in the half constant current charge mode. Note that with PSEL low, the ISET2 pin controls only the
0.1 A/0.5 A USB current level.
With ISET2 low the V(TMR) voltage remains at 2.5 V under normal operating conditions. In this case, the charge
rate is half the programmed current but the safety timer remains t(CHG). If the bqTINY III-series enters DPPM or
thermal regulation mode from this state, the safety timer immediately doubles and then the safety time is
adjusted (inversely proportionate) with the charge current.
See the section titled Power-Path Management for additional details.
10.4.4.3 Battery Voltage Regulation
The voltage regulation feedback is through the BAT pin. This input is tied directly to the positive side of the
battery pack. The bqTINY III-series monitors the battery-pack voltage between the BAT and VSS pins. When the
battery voltage rises to the VO(BAT-REG) threshold (4.1-V, 4.2-V, or 4.36-V versions), the voltage regulation phase
begins and the charging current begins to taper down.
If the battery is absent, the BAT pin cycles between charge done (VO(REG)) and charging (battery refresh
threshold, ~100 mV below VO(REG)). See Figure 14.
See Figure 15 for power up by battery insertion.
As a safety backup, the bqTINY III-series also monitors the charge time in the charge mode. If charge is not
terminated within this time period, t(CHG), the bqTINY III-series turns off the charger and enunciates FAULT on the
STAT1 and STAT2 pins. See the DPPM operation under Case 1 for information on extending the safety timer
during DPPM operation. See theTimer Fault Recovery section for additional details.
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10.4.4.4 Power Handoff
The design goal of the bqTINY III-series is to keep the system powered at all times (OUT pin); first, by either AC
or USB input––priority chosen by PSEL, and lastly by the battery. The input power source is only considered
present if its power-good status is low. There is a break-before-make switching action when switching between
AC to USB or USB to AC, for tSW-AC/USB, where the system capacitance should hold up the system voltage. Note
that the transfer of power occurs when the sources power-good pin goes high (open-drain output high = power
not present), which is when the input source drops to the battery's voltage. If the battery is below a useable
voltage, the system may reset. Typically, prior to losing the input power, the battery would have some useable
capacity, and a system reset would be avoided. If the battery was dead or missing, the system would lose power
unless the PSEL pin was used to transfer power prior to shutdown.
If this is a concern, there is a simple external solution. Externally toggling the PSEL (bq24030/31/5/8) pin
immediately starts the power-transfer process (does not wait for input to drop to the battery's voltage). This can
be implemented by a resistor divider between the AC input and ground with the PSEL pin tied between R1 (top
resistor) and R2 (resistor to ground). The resistor values are chosen such that the divider voltage will be at 1 V
(PSEL threshold) when the AC has dropped to its critical voltage (user defined). An internal ~280-kΩ resistor is
applied when PSEL < 1 V, to provide hysteresis. Choose R2 between 10 kΩ and 60 kΩ and V(ac-critical) between
3.5 V and 4.5 V. R1 can be found using the following equation:
R1 = R2 (V(ac-critical) – 1 V); V(ac-reset) = 1 + R1 (R2+280 k)/(280 k × R2);
(6)
Example: If R2 = 30 kΩ and V(ac-critical) = 4 V; R1 = 30 kΩ(4 V – 1 V) = 90 kΩ, V(ac-reset) = 1+ 90k (30 k+280
k)/(280 k×30 k) = 4.32 V. Therefore, for a 90 kΩ/30 kΩ divider, the bias on PSEL would switch power from AC to
USB (USBPG = L) when the VAC dropped to 4 V (independent of VBAT) and switches back when the VAC
recovers to 4.32 V. See Figure 9 through Figure 13.
10.4.4.5 Temperature Regulation and Thermal Protection
In order to maximize charge rate, the bqTINY III-series features a junction temperature regulation loop. If the
power dissipation of the bqTINY III-series results in a junction temperature greater than the TJ(REG) threshold
(125°C, typical), the bqTINY III-series throttles back on the charge current in order to maintain a junction
temperature around the TJ(REG) threshold. To avoid false termination, the termination detect function is disabled
while in this mode. The reduced charge current results in a longer charge time so the safety timer, t(CHG) is
extended inversely. This means that if the temperature regulation loop reduces the current to half of the
programmed charge rate, then the safety timer t(CHG) doubles. See Charge Timer Operation for more detail.
The bqTINY III-series also monitors the junction temperature, TJ, of the die and disconnects the OUT pin from
AC or USB inputs if TJ exceeds T(SHTDWN). This operation continues until TJ falls below T(SHTDWN) by the
hysteresis level specified in the specification table.
The battery supplement mode has no thermal protection. The Q2 FET continues to connect the battery to the
output (system), if input power is not sufficient; however, a short-circuit protection circuit limits the battery
discharge current such that the maximum power dissipation of the part is not exceeded under typical design
conditions.
10.4.4.6 Charge Timer Operation
As a safety backup, the bqTINY III-series monitors the charge time in the charge mode. If the termination
threshold is not detected within the time period, t(CHG), the bqTINY III-series turns off the charger and enunciates
FAULT on the STAT1 and STAT2 pins. The resistor connected between the TMR and VSS, RTMR, determines
the timer period. The K(TMR) parameter is specified in the specifications table. In order to disable the charge timer,
eliminate RTMR, connect the TMR pin directly to the LDO pin. Note that this action eliminates the fast-charge
safety timer (it does not disable or reset the pre-charge safety timer), disables termination, and also clears a fastcharge timer fault. TMR pin should not be left floating.
t(CHG) = K (TMR) ´ R(TMR)
(7)
While in the thermal regulation mode or DPPM mode, the bqTINY III-series dynamically adjusts the timer period
in order to provide the additional time needed to fully charge the battery. This proprietary feature is designed to
prevent against early or false termination. The maximum charge time in this mode, t(CHG-TREG), is calculated by
Equation 8.
t(CHG) ´ V(SET)
t(CHG-TREG) =
V(SET -REG)
(8)
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Note that because this adjustment is dynamic and changes as the ambient temperature changes and the charge
level changes, the timer clock is adjusted. It is difficult to estimate a total safety time without integrating the
above equation over the charge cycle. Therefore, understanding the theory that the safety time is adjusted
inversely proportionately with the charge current and the battery is a current-hour rating, the safety time
dynamically adjusts appropriately.
The V(SET) parameter is specified in the specifications table. V(SET-TREG) is the voltage on the ISET pin during the
thermal regulation or DPPM mode and is a function of charge current. (Note that charge current is dynamically
adjusted during the thermal regulation or DPPM mode.)
I(OUT) ´ R(SET)
V(SET -TREG) =
K (SET)
(9)
All deglitch times also adjusted proportionally to t(CHG-TREG).
10.4.4.7 Charge Termination and Recharge
The bqTINY III-series monitors the voltage on the ISET1 pin, during voltage regulation, to determine when
termination should occur (C/10 – 250 mV, C/25 – 100 mV). Once the termination threshold, I(TERM), is detected
the bqTINY III-series terminates charge. The resistor connected between the ISET1 and VSS, RSET, programs
the fast charge current level (C level, VISET1 = 2.5 V) and thus the C/10 and C/25 current termination threshold
levels. The V(TERM) and K(SET) parameters are specified in the specifications table. Note that this applies to both
AC and USB charging.
V(TERM) ´ K (SET)
I(TERM) =
RSET
(10)
After charge termination, the bqTINY III-series re-starts the charge once the voltage on the OUT pin falls below
the V(RCH) threshold (VO(BAT-REG) –100 mV, typical). This feature keeps the battery at full capacity at all times.
10.4.5 Boot-Up Sequence
In order to facilitate the system start-up and USB enumeration, the bqTINY III-series offers a proprietary boot-up
sequence. On the first application of power to the bqTINY III-series, this feature enables the 100-mA USB charge
rate for a period of approximately 150 ms, (t(BOOT-UP)), ignoring the ISET2 and CE inputs setting. At the end of
this period, the bqTINY III-series implements CE and ISET2 inputs settings. Table 2 indicates when this feature
is enabled. See Figure 16.
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11 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
11.1 Application Information
Compared to chargers without dynamic power path management (DPPM), this single-cell LiIon battery charger
provides instant system power even with a deeply discharged battery. The maximum charge current is set by
ISET2 but the input current limit circuitry, controlled by ISET1 and PSEL pins or the DPPM circuitry can reduce
the charge current from the maximum desired value.
11.2 Typical Application
bq24030/31/32A/35
AC Adapter
VDC
4
GND
AC
LDO
1
10 µF
OUT 15
10 µF
OUT 16
D+
D−
VBUS
20 USB
10 µF
14 TMR
RTMR
GND
USB Port
OUT 17
BAT
5
BAT
6
PACK+
STAT1
3
STAT2
19 USBPG
Battery P ack
+
1 µF
7 ISET2
2
System
10 µF
PACK −
TS 12
18 ACPG
DPPM 13
9
CE
ISET1 10
8
PSEL
TEMP
RSET
RDPPM
VSS 11
Control and
Status Signals
Figure 7. Typical Application Schematic
11.2.1 Design Requirements
A bq24070 (VOUT = 4.4 Vreg) is powered through an AC adaptor with IN input is set for ~5.1 V (1.5 A current
limit), I(CHG) = 1 A, V(DPPM-SET) = 3.7 V, V(DPPM-REG) = 1.15 × V(DPPM-SET) = 4.26 V, Mode = H, and USB input is not
connected. A 103AT thermistor is inside the battery pack. A 6-hour saftey timeout is desired.
11.2.2 Detailed Design Procedure
The minimum required 0.1 μF capacitors are placed on IN and OUT. Additional 10 μF capacitors are included on
IN and OUT to improve load transient response. The recommended (but not required) 33 μF capacitor on BAT is
added to allow for operation when no battery is attached. A 0.22 μF capacitor is connected between BAT and
ISET1 to improve operation at low charge currents.
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Typical Application (continued)
Rearranging Equation 5 gives RSET = V(SET) x K(SET) / IO(BAT) = 2.5 V x 425 / 1 A = 1062.5 Ω → 1070 Ω. Per
Equation 4, the precharge current is 100 mA and per Equation 10, the termination current is 100 mA. Since
MODE is high, in order to prevent the charge current from being reduced by 1/2, ISET2 is tied high.
Rearranging Equation 7 gives RTMR = t(CHG) / K(TMR) gives 6 hrs x 60 min/hr x 60 s/min / 0.360 s/Ω = 60 kΩ →
60.4 kΩ
Rearranging Equation 1 gives RDPPM = V(DPPM-REG) / (I(DPPM) x SF) = 4.26 V / ( 100 μA x 1.15) = 37.044 kΩ →37.4
kΩ. CDPPM of 10 nF was added to prevent the IC from falsely entering short circuit protection at start up.
Not shown are 1.5-kΩ resistors and LEDs pulled up to V(IN) from STAT1, STAT2 and PG.
11.2.2.1 Selecting the Input and Output Capacitors
In most applications, all that is needed is a high-frequency decoupling capacitor on each input (AC and USB). A
0.1-μF ceramic capacitor, placed in close proximity to AC and USB to VSS pins, works well. In some applications
depending on the power supply characteristics and cable length, it may be necessary to add an additional 10-μF
ceramic capacitor to each input.
The bqTINY III-series only requires a small output capacitor for loop stability. A 0.1-μF ceramic capacitor placed
between the OUT and VSS pin is typically sufficient.
The integrated LDO requires a maximum of 1-μF ceramic capacitor on its output. The output does not require a
capacitor for a steady-state load but a 0.1-μF minimum capacitance is recommended.
It is recommended to install a minimum of 33-μF capacitor between the BAT pin and VSS (in parallel with the
battery). This ensures proper hot plug power up with a no-load condition (no system load or battery attached).
This short-circuit disable feature was implemented mainly for power up when inserting a battery. Because the
BAT input voltage rises much faster than the OUT voltage (Vout<Vbat-200 mV), with most any capacitive load on
the output, the part can get stuck in short-circuit mode. Placing a 1 nF to 100 nF capacitor between the DPPM
pin and ground slows the VDPPM rise time, during power up, and delays the short-circuit protection.
11.2.3 Application Curves
Figure 8 illustrates DPPM and battery supplement modes as the output current (IOUT) is increased; channel 1
(CH1) VAC = 5.4 V; channel 2 (CH2) VOUT; channel 3 (CH3) IOUT = 0 to 2.2 A to 0 A; channel 4 (CH4) VBAT = 3.5
V; I(PGM-CHG) = 1 A. In typical operation, bq24032A (VOUT = 4.4 Vreg), through an AC adaptor overload condition
and recovery. The AC input is set for ~5.1 V (1.5 A current limit), I(CHG) = 1 A, V(DPPM-SET) = 3.7 V, V(DPPM-OUT) =
1.15 × V(DPPM-SET) = 4.26 V, VBAT = 3.5 V, PSEL = H, and USB input is not connected. The output load is
increased from 0 A to ~2.2 A and back to 0 A as shown in the bottom waveform. As the IOUT load reaches 0.5 A,
along with the 1-A charge current, the adaptor starts to current limit, the output voltage drops to the DPPM-OUT
threshold of 4.26 V. This is DPPM mode. The AC input tracks the output voltage by the dropout voltage of the
AC FET. The battery charge current is then adjusted back as necessary to keep the output voltage from falling
any further. Once the output load current exceeds the input current, the battery has to supplement the excess
current and the output voltage falls just below the battery voltage by the dropout voltage of the battery FET. This
is the battery supplement mode. When the output load current is reduced, the operation described is reversed as
shown. If V(DPPM-REG) was set below the battery voltage, during input current limiting, the output falls directly to the
battery's voltage.
Under USB operation, when the loads exceeds the programmed input current thresholds a similar pattern is
observed. If the output load exceeds the available USB current, the output instantly goes into the battery
supplement mode.
Figure 9 illustrates when PSEL is toggled low for 500 μs. Power transfers from AC to USB to AC; channel 1
(CH1) VAC = 5.4 V; channel 2 (CH2) V(USB) = 5 V; channel 3 (CH3) VOUT; output current, IOUT = 0.25 A; channel
4 (CH4) VBAT = 3.5 V; and I(PGM-CHG) = 1 A. When the PSEL went low (1st div), the AC FET opened, and the
output fell until the USB FET turned on. Turning off the active source before turning on the replacement source is
referred to as break-before-make switching. The rate of discharge on the output is a function of system
24
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Product Folder Links: bq24030 bq24031 bq24032A bq24035 bq24038
bq24030, bq24031, bq24032A, bq24035, bq24038
www.ti.com
SLUS618I – AUGUST 2004 – REVISED DECEMBER 2014
Typical Application (continued)
capacitance and load. Note the cable IR drop in the AC and USB inputs when they are under load. At the 4th
division, the output has reached steady-state operation at V(DPPM-REG) (charge current has been reduced due to
the limited USB input current). At the 6th division, the PSEL goes high and the USB FET turns off followed by the
AC FET turning on. The output returns to its regulated value, and the battery returns to its programmed current
level.
Figure 10 illustrates when AC is removed, power transfers to USB; PSEL = H (AC primary source); channel 1
(CH1) VAC = 5.4 V; channel 2 (CH2) V(USB) = 5 V; channel 3 (CH3) VOUT; output current, IOUT = 0.25 A; channel
4 (CH4) VBAT = 3.5 V; and I(PGM-CHG) = 1 A. The power transfer from AC to USB only takes place after the primary
source (AC) is considered bad (too low, VAC<=VBAT + 125 mV) indicated by the ACPG FET turning off (open
drain not shown). Thus, the output drops down to the battery voltage before the USB source is connected (6th
div). The output starts to recover when the USB FET starts to limit the input current (7th div) and the output drops
to the V(DPPM-REG) threshold.
Figure 11 illustrates when AC (low battery) is removed, power transfers to USB; PSEL = H; channel 1 (CH1)
VAC = 5.4 V; channel 2 (CH2) V(USB) = 5 V; channel 3 (CH3) VOUT; output current, IOUT = 0.25 A; channel 4
(CH4) VBAT = 2.25 V; and I(PGM-CHG) = 1 A. This figure is the same as where the battery has more capacity. Note
that the output drops to the battery voltage before switching to USB power. A resistor divider between AC and
ground tied to PSEL can toggle the power transfer earlier if necessary.
Figure 12 illustrates when AC is applied, power transfers from USB to AC; PSEL = H; channel 1 (CH1) VAC =
5.4 V; channel 2 (CH2) V(USB) = 5 V; channel 3 (CH3) VOUT; output current, IOUT = 0.25 A; channel 4 (CH4) VBAT
= 3.5 V; and I(PGM-CHG) = 1 A. The charger is set for AC priority but is running off USB until AC is applied. When
AC is applied (1st div) and the USB FET opens (2nd div), the AC FET closes (3rd div) and the output recovers
from the DPPM threshold (8th div).
Figure 13 illustrates when USB is removed, power transfers from USB to AC; PSEL = L; channel 1 (CH1) VAC =
5.4 V; channel 2 (CH2) V(USB) = 5 V; channel 3 (CH3) VOUT; output current, IOUT = 0.25 A; channel 4 (CH4) VBAT
= 3.5 V; and I(PGM-CHG) = 1 A. The USB source is removed (2nd div) and the output drops to the battery voltage
(declares USB bad, 4th div) and switches to AC (in USB mode) and recovers similar to the figure that is switching
to USB power. This power transfer occurred with PSEL low, which means that the AC input is regulated as if it
were a USB.
Figure 14 illustrates when the battery is absent, power transfers to USB; PSEL = H; channel 1 (CH1) VAC = 5.4
V; channel 2 (CH2) V(USB) = 5 V; channel 3 (CH3) VOUT; output current, IOUT = 0.25 A; channel 4 (CH4) VBAT;
I(PGM-CHG) = 1 A. Note the saw-tooth waveform due to cycling between charge done and refresh (new charge).
Figure 15 illustrates when a battery is inserted for power up; channel 1 (CH1) VAC = 0 V; channel 2 (CH2) VUSB
= 0 V; channel 3 (CH3) VOUT; output current, IOUT = 0.25 A for VOUT > 2 V; channel 4 (CH4) VBAT = 3.5 V; C(DPPM)
= 0 pF. When there are no power sources and the battery is inserted, the output tracks the battery voltage if
there is no load (<10 mA of load) on the output, as shown. If a load is present that keeps the output more than
200 mV below the battery, a short-circuit condition is declared. At this time, the load has to be removed to
recover. A capacitor can be placed on the DPPM pin to delay implementing the short-circuit mode and get
unrestricted (not limited) current.
Figure 16 illustrates USB bootup and power-up via USB; channel 1 (CH1) V(USH) = 0 to 5 V; channel 2 (CH2)
USB input current (0.2 A/div); PSEL = Low; CE = High; ISET2 = High; VBAT = 3.85 V; V(DPPM) = 3.0 V (V(DPPM) ×
1.15 < VBAT, otherwise DPPM mode increases time duration). When a USB source is applied (if AC is not
present), the CE pin and ISET2 pin are ignored during the boot-up time and a maximum input current of 100 mA
is made available to the OUT or BAT pins. After the boot-up time, the bqTINY III-series implements the CE and
ISET2 pins as programmed.
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SLUS618I – AUGUST 2004 – REVISED DECEMBER 2014
www.ti.com
Typical Application (continued)
VAC
Break Before Make
VOUT
VAC
VUSB
VOUT Reg. @ 4.4 V (bq24032A)
VDPPM − OUT = 4.26 V, DPPM Mode
VOUT
VOUT ≈ VBAT, BAT Supplement Mode
VBAT
System Capacitance
Powering System
DPPM Mode
USB is Charging System Capacitance
ICHG
Hi
IOUT
PSEL
Low
Figure 8. DPPM and Battery Supplement Modes
Figure 9. Toggle PSEL Low
USB Input Current Limit is Reached.
DPPM Mode
VUSB
VUSB
VOUT
VAC
VBAT
VOUT
DPPM Mode
VAC
AC Declared Not Present, USB Power Applied
VBAT
Figure 10. Remove AC – PWR XFER to USB
VAC
Figure 11. Remove AC (Low Battery) – PWR XFER to USB
AC is Applied (USB Mode)
VUSB
VOUT
VBAT
Break Before Make
VAC
AC Hits USB (ISET2) limit
DPPM Mode
VOUT Returns to Regulation (4.4 V, bq24032A)
Charging Current Returns to Ipgm
DPPM Mode
VOUT
VUSB
VBAT
USB Declared not Present
Figure 12. Apply AC – PWR XFER From USB to AC
26
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Figure 13. Remove USB – PWR XFER From USB to AC
Copyright © 2004–2014, Texas Instruments Incorporated
Product Folder Links: bq24030 bq24031 bq24032A bq24035 bq24038
bq24030, bq24031, bq24032A, bq24035, bq24038
www.ti.com
SLUS618I – AUGUST 2004 – REVISED DECEMBER 2014
Typical Application (continued)
VAC
VUSB
VOUT
VBAT
BAT PIN Capacitance Discharging to Refresh Threshold
Charging (Step) Followed by Charge Done
VBAT
VOUT
Figure 14. Battery Absent – PWR XFER to USB
Figure 15. Insert Battery – Power-Up Output via BAT
VUSB
IUSB
Figure 16. USB Boot-Up Power-Up
12 Power Supply Recommendations
A power supply capable of providing VCC between 4.35 V and 16 V and at least 100 mA up to 2 A is required for
the IC to operate. For the battery to fully charge, the power supply must be capable of providing at least VO(BATREG) + V(BATDO). As the input voltage increases, the IC's power dissipation increases. The IC's thermal protection
loop as explained in Temperature Regulation and Thermal Protection reduces the input current current from the
maximum (2 A when MODE = H and either 100 mA or 500 mA per ISET2 if MODE = L) to prevent damage to the
IC.
Copyright © 2004–2014, Texas Instruments Incorporated
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Product Folder Links: bq24030 bq24031 bq24032A bq24035 bq24038
27
bq24030, bq24031, bq24032A, bq24035, bq24038
SLUS618I – AUGUST 2004 – REVISED DECEMBER 2014
www.ti.com
13 Layout
13.1 Layout Guidelines
It is important to pay special attention to the PCB layout. The following provides some guidelines:
• To obtain optimal performance, the decoupling capacitor from input terminals to VSS and the output filter
capacitors from OUT to VSS should be placed as close as possible to the bqTINY III-series, with short trace
runs to both signal and VSS pins.
• All low-current VSS connections should be kept separate from the high-current charge or discharge paths
from the battery. Use a single-point ground technique incorporating both the small signal ground path and the
power ground path.
• The high-current charge paths into AC and USB and from the BAT and OUT pins must be sized appropriately
for the maximum charge current in order to avoid voltage drops in these traces.
• The bqTINY III-series is packaged in a thermally enhanced MLP package. The package includes a QFN
thermal pad to provide an effective thermal contact between the device and the printed-circuit board. Full
PCB design guidelines for this package are provided in the application note entitled QFN/SON PCB
Attachment (SLUA271).
13.2 Layout Example
Figure 17. Layout Schematic
28
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Copyright © 2004–2014, Texas Instruments Incorporated
Product Folder Links: bq24030 bq24031 bq24032A bq24035 bq24038
bq24030, bq24031, bq24032A, bq24035, bq24038
www.ti.com
SLUS618I – AUGUST 2004 – REVISED DECEMBER 2014
13.3 Thermal Considerations
The bqTINY III-series is packaged in a thermally enhanced MLP package. The package includes a QFN thermal
pad to provide an effective thermal contact between the device and the printed-circuit board (PCB). Full PCB
design guidelines for this package are provided in the application note entitled QFN/SON PCB Attachment
(SLUA271). The power pad should be tied to the VSS plane. The most common measure of package thermal
performance is thermal impedance (θJA) measured (or modeled) from the chip junction to the air surrounding the
package surface (ambient).
The mathematical expression for θJA is:
T - TA
qJA = J
P
where
•
•
•
TJ = chip junction temperature
TA = ambient temperature
P = device power dissipation
(11)
Factors that can greatly influence the measurement and calculation of θJA include:
• whether or not the device is board mounted
• trace size, composition, thickness, and geometry
• orientation of the device (horizontal or vertical)
• volume of the ambient air surrounding the device under test and airflow
• whether other surfaces are in close proximity to the device being tested
The device power dissipation, P, is a function of the charge rate and the voltage drop across the internal power
FET. It can be calculated from Equation 12:
P + ƪǒV IN * V OUTǓ
ǒI OUT ) I BATǓƫ ) ƪǒV OUT * VBATǓ
ǒIBATǓƫ
(12)
Due to the charge profile of Li-xx batteries, the maximum power dissipation is typically seen at the beginning of
the charge cycle when the battery voltage is at its lowest. See Figure 2. Typically the Li-ion battery's voltage
quickly (< 2 V minutes) ramps to approximately 3.5 V, when entering fast charge (1-C charge rate and battery
above V(LOWV)). Therefore, it is customary to perform the steady-state thermal design using 3.5 V as the
minimum battery voltage because the system board and charging device does not have time to reach a
maximum temperature due to the thermal mass of the assembly during the early stages of fast charge. This
theory is easily verified by performing a charge cycle on a discharged battery while monitoring the battery voltage
and chargers power pad temperature.
Copyright © 2004–2014, Texas Instruments Incorporated
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Product Folder Links: bq24030 bq24031 bq24032A bq24035 bq24038
29
bq24030, bq24031, bq24032A, bq24035, bq24038
SLUS618I – AUGUST 2004 – REVISED DECEMBER 2014
www.ti.com
14 Device and Documentation Support
14.1 Device Support
14.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
14.2 Documentation Support
14.2.1 Related Documentation
For related documentation see the following:
• QFN/SON PCB Attachment, SLUA271
14.3 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 3. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
bq24030
Click here
Click here
Click here
Click here
Click here
bq24031
Click here
Click here
Click here
Click here
Click here
bq24032A
Click here
Click here
Click here
Click here
Click here
bq24035
Click here
Click here
Click here
Click here
Click here
bq24038
Click here
Click here
Click here
Click here
Click here
14.4 Trademarks
bqTINY is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
14.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
14.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
15 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
30
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Copyright © 2004–2014, Texas Instruments Incorporated
Product Folder Links: bq24030 bq24031 bq24032A bq24035 bq24038
PACKAGE OPTION ADDENDUM
www.ti.com
30-Oct-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ24030RHLR
ACTIVE
VQFN
RHL
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ANB
BQ24030RHLRG4
ACTIVE
VQFN
RHL
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ANB
BQ24031RHLR
ACTIVE
VQFN
RHL
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
BZJ
BQ24031RHLRG4
ACTIVE
VQFN
RHL
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
BZJ
BQ24031RHLT
ACTIVE
VQFN
RHL
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
BZJ
BQ24032ARHLR
ACTIVE
VQFN
RHL
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BPE
BQ24032ARHLRG4
ACTIVE
VQFN
RHL
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BPE
BQ24032ARHLT
ACTIVE
VQFN
RHL
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BPE
BQ24032ARHLTG4
ACTIVE
VQFN
RHL
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BPE
BQ24035RHLR
ACTIVE
VQFN
RHL
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ANA
BQ24035RHLRG4
ACTIVE
VQFN
RHL
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
ANA
BQ24038RHLR
ACTIVE
VQFN
RHL
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BOW
BQ24038RHLRG4
ACTIVE
VQFN
RHL
20
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BOW
BQ24038RHLT
ACTIVE
VQFN
RHL
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BOW
BQ24038RHLTG4
ACTIVE
VQFN
RHL
20
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
BOW
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
30-Oct-2014
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF BQ24030, BQ24031 :
• Automotive: BQ24030-Q1, BQ24031-Q1
NOTE: Qualified Version Definitions:
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Oct-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
BQ24030RHLR
VQFN
RHL
20
3000
330.0
12.4
3.8
4.8
1.3
8.0
12.0
Q1
BQ24030RHLR
VQFN
RHL
20
3000
330.0
12.4
3.8
4.8
1.6
8.0
12.0
Q1
BQ24031RHLR
VQFN
RHL
20
3000
330.0
12.4
3.8
4.8
1.6
8.0
12.0
Q1
BQ24031RHLT
VQFN
RHL
20
250
180.0
12.4
3.8
4.8
1.6
8.0
12.0
Q1
BQ24032ARHLR
VQFN
RHL
20
3000
330.0
12.4
3.8
4.8
1.3
8.0
12.0
Q1
BQ24032ARHLR
VQFN
RHL
20
3000
330.0
12.4
3.8
4.8
1.6
8.0
12.0
Q1
BQ24032ARHLT
VQFN
RHL
20
250
180.0
12.4
3.8
4.8
1.6
8.0
12.0
Q1
BQ24032ARHLT
VQFN
RHL
20
250
180.0
12.4
3.8
4.8
1.3
8.0
12.0
Q1
BQ24035RHLR
VQFN
RHL
20
3000
330.0
12.4
3.8
4.8
1.6
8.0
12.0
Q1
BQ24038RHLR
VQFN
RHL
20
3000
330.0
12.4
3.8
4.8
1.6
8.0
12.0
Q1
BQ24038RHLR
VQFN
RHL
20
3000
330.0
12.4
3.8
4.8
1.3
8.0
12.0
Q1
BQ24038RHLT
VQFN
RHL
20
250
180.0
12.4
3.8
4.8
1.3
8.0
12.0
Q1
BQ24038RHLT
VQFN
RHL
20
250
180.0
12.4
3.8
4.8
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Oct-2014
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ24030RHLR
VQFN
RHL
20
3000
370.0
355.0
55.0
BQ24030RHLR
VQFN
RHL
20
3000
367.0
367.0
35.0
BQ24031RHLR
VQFN
RHL
20
3000
367.0
367.0
35.0
BQ24031RHLT
VQFN
RHL
20
250
210.0
185.0
35.0
BQ24032ARHLR
VQFN
RHL
20
3000
370.0
355.0
55.0
BQ24032ARHLR
VQFN
RHL
20
3000
367.0
367.0
35.0
BQ24032ARHLT
VQFN
RHL
20
250
210.0
185.0
35.0
BQ24032ARHLT
VQFN
RHL
20
250
195.0
200.0
45.0
BQ24035RHLR
VQFN
RHL
20
3000
367.0
367.0
35.0
BQ24038RHLR
VQFN
RHL
20
3000
367.0
367.0
35.0
BQ24038RHLR
VQFN
RHL
20
3000
370.0
355.0
55.0
BQ24038RHLT
VQFN
RHL
20
250
195.0
200.0
45.0
BQ24038RHLT
VQFN
RHL
20
250
210.0
185.0
35.0
Pack Materials-Page 2
IMPORTANT NOTICE FOR TI DESIGN INFORMATION AND RESOURCES
Texas Instruments Incorporated (‘TI”) technical, application or other design advice, services or information, including, but not limited to,
reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are
developing applications that incorporate TI products; by downloading, accessing or using any particular TI Resource in any way, you
(individually or, if you are acting on behalf of a company, your company) agree to use it solely for this purpose and subject to the terms of
this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
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