DS1305 Serial Alarm Real Time Clock (RTC)

DS1305 Serial Alarm Real Time Clock (RTC)
DS1305
DS1305
Serial Alarm Real Time Clock (RTC)
FEATURES
PIN ASSIGNMENT
• Real time clock counts seconds, minutes, hours, date
of the month, month, day of the week, and year with
leap year compensation valid up to 2100
VCC2
1
20
VCC1
VBAT
2
19
NC
X1
3
18
PF
NC
4
17
VCCIF
X2
5
16
SDO
NC
6
15
SDI
INT0
7
14
SCLK
NC
8
13
NC
INT1
9
12
CE
GND
10
11
SERMODE
• 96–byte nonvolatile RAM for data storage
• Two Time of Day Alarms – programmable on combination of seconds, minutes, hours, and day of the
week
• Serial interface supports Motorola Serial Peripheral
Interface (SPI) serial data ports or standard 3–wire
interface
DS1305 20–PIN TSSOP (173 MIL)
• Burst Mode for reading/writing successive addresses
in clock/RAM
• Dual power supply pins for primary and backup power
supplies
• Optional trickle charge output to backup supply
• 2.5 – 5.5 volt operation
VCC2
1
16
VCC1
VBAT
2
15
PF
X1
3
14
VCCIF
X2
4
13
SDO
NC
5
12
SDI
• Optional 2.0 – 5.5 volt full operation also available
INT0
6
11
SCLK
• Optional industrial temperature range –40°C to +85°C
INT1
7
10
CE
• Available in space–efficient 20–pin TSSOP package
GND
8
9
SERMODE
DS1305 16–PIN DIP (300 MIL)
ORDERING INFORMATION
DS1305
DS1305N
DS1305E
DS1305EN
16–Pin DIP
16–Pin DIP (Industrial)
20–Pin TSSOP
20–Pin TSSOP (Industrial)
DESCRIPTION
The DS1305 Serial Alarm Real Time Clock provides a
full BCD clock calendar which is accessed via a simple
serial interface. The clock/calendar provides seconds,
minutes, hours, day, date, month, and year information.
The end of the month date is automatically adjusted for
months with less than 31 days, including corrections for
leap year. The clock operates in either the 24–hour or
12–hour format with AM/PM indicator. In addition 96
bytes of nonvolatile RAM are provided for data storage.
Copyright 1995 by Dallas Semiconductor Corporation.
All Rights Reserved. For important information regarding
patents and other intellectual property rights, please refer to
Dallas Semiconductor data books.
PIN DESCRIPTION
VCC1
VCC2
VBAT
VCCIF
GND
X1, X2
INT0
INT1
SDI
SDO
CE
SCLK
SERMODE
PF
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Primary Power Supply
Backup Power Supply
+3 Volt Battery Input
Interface Logic Power Supply Input
Ground
32,768 Hz Crystal Connection
Interrupt 0 Output
Interrupt 1 Output
Serial Data In
Serial Data Out
Chip Enable
Serial Clock
Serial Interface Mode
Power Fail Output
041497 1/20
DS1305
An interface logic power supply input pin (VCCIF) allows
the DS1305 to drive SDO and PF pins to a level that is
compatible with the interface logic. This allows an easy
interface to 3 volt logic in mixed supply systems.
The DS1305 offers dual power supplies as well as a battery input pin. The dual power supplies support a programmable trickle charge circuit which allows a
rechargeable energy source (such as a super cap or
rechargeable battery) to be used for a backup supply.
The VBAT pin allows the device to be backed up by a
non–rechargeable battery. The DS1305 is fully operational from 2.5 to 5.5 volts.
Two programmable time of day alarms are provided by
the DS1305. Each alarm can generate an interrupt on a
programmable combination of seconds, minutes,
hours, and day. “Don’t care” states can be inserted into
one or more fields if it is desired for them to be ignored
for the alarm condition. The time of day alarms can be
programmed to assert two different interrupt outputs or
to assert one common interrupt output. Both interrupt
outputs operate when the device is powered by VCC1,
VCC2, or VBAT.
The DS1305 supports a direct interface to Motorola SPI
serial data ports or standard 3–wire interface. A straight
forward address and data format is implemented in
which data transfers can occur one byte at a time or in
multiple byte burst mode.
OPERATION
The block diagram in Figure 1 shows the main elements
of the Serial Alarm RTC. The following paragraphs
describe the function of each pin.
DS1305 BLOCK DIAGRAM Figure 1
32.768 KHz
VCC1
X1
VCC2
VBAT
POWER CONTROL
AND TRICKLE
CHARGER
X2
CLOCK/CALENDAR
LOGIC
VCCIF
CLOCK, CALENDAR,
AND ALARM
REGISTERS
VCC
PF
GND
INT0
CONTROL
REGISTERS
SCLK
SDI
SDO
CE
SERMODE
041497 2/20
SERIAL
INTERFACE
INPUT
SHIFT
REGISTER
USER
RAM
INT1
DS1305
SIGNAL DESCRIPTIONS
VCC1 – DC power is provided to the device on this pin.
VCC1 is the primary power supply.
VCC2 – This is the secondary power supply pin. In systems using the trickle charger, the rechargeable energy
source is connected to this pin.
VBAT – Battery input for any standard 3 volt lithium cell
or other energy source.
VCCIF (Interface Logic Power Supply Input) – The
VCCIF pin allows the DS1305 to drive SDO and PF output pins to a level that is compatible with the interface
logic, thus allowing an easy interface to 3 volt logic in
mixed supply systems. This pin is physically connected
to the source connection of the p–channel transistors in
the output buffers of the SDO and PF pins.
SERMODE (Serial Interface Mode Input) – The SERMODE pin offers the flexibility to choose between two
serial interface modes. When connected to GND, standard 3–wire communication is selected. When connected to VCC, Motorola SPI communication is
selected.
SCLK (Serial Clock Input) – SCLK is used to synchronize data movement on the serial interface for either the
SPI or 3–wire interface.
SDI (Serial Data Input) – When SPI communication is
selected, the SDI pin is the serial data input for the SPI
bus. When 3–wire communication is selected, this pin
must be tied to the SDO pin (the SDI and SDO pins function as a single I/O pin when tied together).
SDO (Serial Data Output) – When SPI communication
is selected, the SDO pin is the serial data output for the
SPI bus. When 3–wire communication is selected, this
pin must be tied to the SDI pin (the SDI and SDO pins
function as a single I/O pin when tied together).
CE (Chip Enable) – The Chip Enable signal must be
asserted high during a read or a write for both 3–wire
and SPI communication. This pin has an internal 55K
pull–down resistor (typical).
INT0 (Interrupt 0 Output) – The INT0 pin is an active
low output of the DS1305 that can be used as an inter-
rupt input to a processor. The INT0 pin can be programmed to be asserted by only Alarm 0 or can be programmed to be asserted by either Alarm 0 or Alarm 1.
The INT0 pin remains low as long as the status bit causing the interrupt is present and the corresponding interrupt enable bit is set. The INT0 pin operates when the
DS1305 is powered by VCC1, VCC2, or VBAT. The INT0
pin is an open drain output and requires an external
pull–up resistor.
INT1 (Interrupt 1 Output) – The INT1 pin is an active
low output of the DS1305 that can be used as an interrupt input to a processor. The INT1 pin can be programmed to be asserted by Alarm 1 only. The INT1 pin
remains low as long as the status bit causing the interrupt is present and the corresponding interrupt enable
bit is set. The INT1 pin operates when the DS1305 is
powered by VCC1, VCC2, or VBAT. The INT1 pin is an
open drain output and requires an external pull–up resistor.
Both INT0 and INT1 are open drain outputs. The two interrupts and the internal clock continue to run regardless of the level of VCC (as long as a power source is
present). However, it is important to insure pull–up resistors used with the interrupt pins are never pulled up to
a value which is greater than VCCX + 0.3V. It is also required to insure that during backup operation mode, the
voltage present at INT0 and INT1 does never exceed
the voltage of the backup source. At all times the current
on each interrupt should not exceed 4.0 mA at VCC = 5V,
or 1.5 mA at VCC = 2.5V.
PF (Power Fail Output) – The PF pin is used to indicate
loss of the primary power supply (VCC1). When VCC1 is
less than VCC2 or is less than VBAT, the PF pin will be
driven low.
X1, X2 – Connections for a standard 32.768 KHz quartz
crystal. The internal oscillator is designed for operation
with a crystal having a specified load capacitance of 6
pF. For more information on crystal selection and crystal layout considerations, please consult Application
Note 58, “Crystal Considerations with Dallas Real Time
Clocks”. The DS1305 can also be driven by an external
32.768 KHz oscillator. In this configuration, the X1 pin is
connected to the external oscillator signal and the X2
pin is floated.
041497 3/20
DS1305
RTC AND RAM ADDRESS MAP
The address map for the RTC and RAM registers of the
DS1305 is shown in Figure 2. Data is written to the RTC
by writing to address locations 80h to 9Fh and is written
ADDRESS MAP Figure 2
00H
CLOCK/CALENDAR
READ ADDRESSES ONLY
1FH
20H
96–BYTES USER RAM
READ ADDRESSES ONLY
7FH
80H
CLOCK/CALENDAR
WRITE ADDRESSES ONLY
9FH
A0H
96–BYTES USER RAM
WRITE ADDRESSES ONLY
FFH
041497 4/20
to the RAM by writing to address locations A0h to FFh.
RTC data is read by reading address locations 00h to
1Fh and RAM data is read by reading address locations
20h to 7Fh.
DS1305
CLOCK, CALENDAR, AND ALARM
These bits will always read 0 regardless of how they are
written. Also note that registers 12h to 1Fh (read) and
registers 92h to 9Fh are reserved. These registers will
always read 0 regardless of how they are written. The
contents of the time, calendar, and alarm registers are in
the Binary–Coded Decimal (BCD) format.
The time and calendar information is obtained by reading the appropriate register bytes. The real time clock
registers are illustrated in Figure 3. The time, calendar,
and alarm are set or initialized by writing the appropriate
register bytes. Note that some bits are set to zero.
RTC REGISTERS Figure 3
HEX ADDRESS
RANGE *
READ
WRITE
BIT7
00H
80H
0
10 SEC
SEC
00 – 59
01H
81H
0
10 MIN
MIN
00 – 59
02H
82H
0
03H
83H
0
0
0
04H
84H
0
05H
85H
0
06H
86H
07H
87H
M
08H
88H
M
09H
89H
M
0AH
8AH
0BH
BIT 0
12
10
01 – 12 + A/P
00 – 23
10 HR
HOURS
0
DAY
01 – 07
0
10 DATE
DATE
01 – 31
0
10 MONTH
MONTH
01 – 12
YEAR
00 – 99
10 SEC ALARM
SEC ALARM
00 – 59
10 MIN ALARM
MIN ALARM
00 – 59
24
A/P
10 YEAR
ALARM 0
10
12
01 – 12 + A/P
00 – 23
10 HR
HOUR ALARM
0
DAY ALARM
00 – 07
10 SEC ALARM
SEC ALARM
00 – 59
10 MIN ALARM
MIN ALARM
00 – 59
24
A/P
M
0
0
8BH
M
0CH
8CH
M
0DH
8DH
M
0EH
8EH
M
0FH
8FH
CONTROL REGISTER
10H
90H
STATUS REGISTER
11H
91H
TRICKLE CHARGER REGISTER
12H–1FH
92H–9FH
RESERVED
ALARM 1
10
12
24
A/P
0
0
10 HR
HOUR ALARM
0
DAY ALRM
01 – 12 + A/P
00 – 23
01 – 07
* RANGE FOR ALARM REGISTERS DOES NOT INCLUDE MASK ‘M’ BIT
041497 5/20
DS1305
The DS1305 can be run in either 12–hour or 24–hour
mode. Bit 6 of the hours register is defined as the 12– or
24–hour mode select bit. When high, the 12–hour mode
is selected. In the 12–hour mode, bit 5 is the AM/PM bit
with logic high being PM. In the 24–hour mode, bit 5 is
the second 10–hour bit (20–23 hours).
The DS1305 contains two time of day alarms. Time of
Day Alarm 0 can be set by writing to registers 87h to
8Ah. Time of Day Alarm 1 can be set by writing to registers 8Bh to 8Eh. The alarms can be programmed (by
the INTCN bit of the Control Register) to operate in two
different modes – each alarm can drive its own separate
interrupt output or both alarms can drive a common
interrupt output. Bit 7 of each of the time of day alarm
registers are mask bits (Table 1). When all of the mask
bits are logic “0”, a time of day alarm will only occur once
per week when the values stored in timekeeping registers 00h to 03h match the values stored in the time of
day alarm registers. An alarm will be generated every
day when bit 7 of the day alarm register is set to a logic
“1”. An alarm will be generated every hour when bit 7 of
the day and hour alarm registers is set to a logic “1”.
Similarly, an alarm will be generated every minute when
bit 7 of the day, hour, and minute alarm registers is set to
a logic “1”. When bit 7 of the day, hour, minute, and
seconds alarm registers is set to a logic “1”, alarm will
occur every second.
TIME OF DAY ALARM MASK BITS Table 1
ALARM REGISTER MASK BITS (BIT 7)
SECONDS
MINUTES
HOURS
DAYS
1
1
1
1
Alarm once per second
0
1
1
1
Alarm when seconds match
0
0
1
1
Alarm when minutes and seconds match
0
0
0
1
Alarm when hours, minutes, and seconds match
0
0
0
0
Alarm when day, hours, minutes, and seconds
match
SPECIAL PURPOSE REGISTERS
The DS1305 has three additional registers (Control
Register, Status Register, and Trickle Charger Register)
that control the real time clock, interrupts, and trickle
charger.
CONTROL REGISTER (READ 0FH, WRITE
8FH)
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
EOSC
WP
0
0
0
INTCN
AIE1
AIE0
EOSC (Enable oscillator) – This bit when set to logic
“0” will start the oscillator. When this bit is set to a logic
“1”, the oscillator is stopped and the DS1305 is placed
into a low–power standby mode with a current drain of
less than 100 nanoamps when power is supplied by
VBAT or VCC2.
WP (Write Protect) – Before any write operation to the
clock or RAM, this bit must be logic “0”. When high, the
write protect bit prevents a write operation to any other
041497 6/20
register and the WP bit is the only bit in the control register that can be written.
INTCN (Interrupt Control) – This bit controls the relationship between the two time of day alarms and the
interrupt output pins. When the INTCN bit is set to a
logic “1”, a match between the timekeeping registers
and the Alarm 0 registers will activate the INT0 pin (provided that the alarm is enabled) and a match between
the timekeeping registers and the Alarm 1 registers will
activate the INT1 pin (provided that the alarm is
enabled). When the INTCN bit is set to a logic “0”, a
match between the timekeeping registers and either
Alarm 0 or Alarm 1 will activate the INT0 pin (provided
that the alarms are enabled). INT1 has no function
when INTCN is set to a logic “0”.
AIE0 (Alarm Interrupt Enable 0) – When set to a logic
“1”, this bit permits the Interrupt 0 Request Flag (IRQF0)
bit in the status register to assert INT0. When the AIE0
bit is set to logic “0”, the IRQF0 bit does not initiate the
INT0 signal.
DS1305
AIE1 (Alarm Interrupt Enable 1) – When set to a logic
“1”, this bit permits the Interrupt 1 Request Flag (IRQF1)
bit in the status register to assert INT1 (when INTCN=1)
or to assert INT0 (when INTCN=0). When the AIE1 bit is
set to logic “0”, the IRQF1 bit does not initiate an interrupt signal.
pin will go low. If the INTCN bit is set to a logic “0” and
IRQF1 is at a logic “1” (and AIE0 bit is also a logic “1”),
the INT0 pin will go low. IRQF1 is cleared when any of
the Alarm 1 registers are read or written.
STATUS REGISTER (READ 10H)
This register controls the trickle charge characteristics
of the DS1305. The simplified schematic of Figure 4
shows the basic components of the trickle charger. The
trickle charge select (TCS) bits (bits 4–7) control the
selection of the trickle charger. In order to prevent accidental enabling, only a pattern of 1010 will enable the
trickle charger. All other patterns will disable the trickle
charger. The DS1305 powers up with the trickle charger
disabled. The diode select (DS) bits (bits 2–3) select
whether one diode or two diodes are connected
between VCC1 and VCC2. If DS is 01, one diode is
selected. If DS is 10, two diodes are selected. If DS is
00 or 11, the trickle charger is disabled independent of
TCS. The RS bits select the resistor that is connected
between VCC1 and VCC2. The resistor is selected by the
resister select (RS) bits as shown in Table 2.
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
0
0
0
0
0
0
IRQF1
IRQF0
IRQF0 (Interrupt 0 Request Flag) – A logic “1” in the
Interrupt Request Flag bit indicates that the current time
has matched the Alarm 0 registers. If the AIE0 bit is also
a logic “1”, the INT0 pin will go low. IRQF0 is cleared
when any of the Alarm 0 registers are read or written.
IRQF1 (Interrupt 1 Request Flag) – A logic “1” in the
Interrupt Request Flag bit indicates that the current time
has matched the Alarm 1 registers. This flag can be
used to generate an interrupt on either INT0 or INT1
depending on the status of the INTCN bit in the Control
Register. If the INTCN bit is set to a logic “1” and IRQF1
is at a logic “1” (and AIE1 bit is also a logic “1”), the INT1
TRICKLE CHARGE REGISTER (READ 11H,
WRITE 91H)
PROGRAMMABLE TRICKLE CHARGER Figure 4
R1
2KΩ
VCC2
VCC1
R2
4KΩ
R3
8KΩ
1 OF 16 SELECT
1 OF 2
SELECT
(NOTE: ONLY 1010 CODE ENABLES CHARGER)
TRICKLE
CHARGE
REGISTER
1 OF 3
SELECT
TCS
TCS
TCS
TCS
DS
DS
RS
RS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
TCS
=
TRICKLE CHARGER SELECT
DS
=
DIODE SELECT
RS
=
RESISTOR SELECT
041497 7/20
DS1305
TRICKLE CHARGER RESISTOR SELECT
Table 2
RS BITS
RESISTOR
TYPICAL VALUE
00
None
None
01
R1
2KΩ
10
R2
4KΩ
11
R3
8KΩ
If RS is 00, the trickle charger is disabled independent of
TCS.
Diode and resistor selection is determined by the user
according to the maximum current desired for battery or
super cap charging. The maximum charging current
can be calculated as illustrated in the following example.
Assume that a system power supply of 5 volts is applied
to VCC1 and a super cap is connected to VCC2. Also
assume that the trickle charger has been enabled with 1
diode and resister R1 between VCC1 and VCC2. The
maximum current IMAX would therefore be calculated as
follows:
IMAX
=
~
~
(5.0V – diode drop)/R1
(5.0V – 0.7V)/2KΩ
2.2mA
Obviously, as the super cap charges, the voltage drop
between VCC1 and VCC2 will decrease and therefore the
charge current will decrease.
POWER CONTROL
Power is provided through the VCC1, VCC2, and VBAT
pins. Three different power supply configurations are
illustrated in Figure 5. Configuration 1 shows the
DS1305 being backed up by a non–rechargeable
energy source such as a lithium battery. In this configuration, the system power supply is connected to VCC1
and VCC2 is grounded. The DS1305 will be write protected if VCC1 is less than VBAT.
Configuration 2 illustrates the DS1305 being backed up
by a rechargeable energy source. In this case, the VBAT
pin is grounded, VCC1 is connected to the primary power
supply, and VCC2 is connected to the secondary supply
(the rechargeable energy source). The DS1305 will
operate from the larger of VCC1 or VCC2. When VCC1 is
greater than VCC2 + 0.2V (typical), VCC1 will power the
DS1305. When VCC1 is less than VCC2, VCC2 will power
041497 8/20
the DS1305. The DS1305 does not write protect itself in
this configuration.
Configuration 3 shows the DS1305 in battery operate
mode where the device is powered only by a single battery. In this case, the VCC1 and VBAT pins are grounded
and the battery is connected to the VCC2 pin.
SERIAL INTERFACE
The DS1305 offers the flexibility to choose between two
serial interface modes. The DS1305 can communicate
with the SPI interface or with a standard 3–wire interface. The interface method used is determined by the
SERMODE pin. When this pin is connected to VCC, SPI
communication is selected. When this pin is connected
to ground, standard 3–wire communication is selected.
SERIAL PERIPHERAL INTERFACE (SPI)
The serial peripheral interface (SPI) is a synchronous
bus for address and data transfer and is used when
interfacing with the SPI bus on specific Motorola microcontrollers such as the 68HC05C4 and the 68HC11A8.
The SPI mode of serial communication is selected by
tying the SERMODE pin to VCC. Four pins are used for
the SPI. The four pins are the SDO (Serial Data Out),
SDI (Serial Data In), CE (Chip Enable), and SCLK
(Serial Clock). The DS1305 is the slave device in an SPI
application, with the microcontroller being the master.
The SDI and SDO pins are the serial data input and output pins for the DS1305, respectively. The CE input is
used to initiate and terminate a data transfer. The SCLK
pin is used to synchronize data movement between the
master (microcontroller) and the slave (DS1305)
devices.
The shift clock (SCLK), which is generated by the microcontroller, is active only during address and data transfer to any device on the SPI bus. The inactive clock
polarity is programmable in some microcontrollers. The
DS1305 offers an important feature in that the level of
the inactive clock is determined by sampling SCLK
when CE becomes active. Therefore either SCLK
polarity can be accommodated. Input data (SDI) is
latched on the internal strobe edge and output data
(SDO) is shifted out on the shift edge (see Table 3 and
Figure 6). There is one clock for each bit transferred.
Address and data bits are transferred in groups of eight.
DS1305
POWER SUPPLY CONFIGURATIONS FOR THE DS1305 Figure 5
Configuration 1: Backup Supply is a Non–Rechargeable Lithium Battery
SYSTEM
VCC
DS1305
VBAT
VCC1
VCC2
Note: Device is write protected if VCC < VBAT.
Configuration 2: Backup Supply is a Rechargeable Battery or Super Capacitor
DS1305
VBAT
VCC1
PRIMARY POWER SUPPLY
VCC2
SECONDARY POWER SUPPLY
(RECHARGEABLE)
Note: Device does not provide automatic write protection.
Configuration 3: Battery Operate Mode
DS1305
VBAT
VCC1
VCC2
041497 9/20
DS1305
FUNCTION TABLE Table 3
MODE
CE
SCLK
SDI
SDO
Disable Reset
L
Input Disabled
Input Disabled
High Z
Write
H
CPOL=1*
Data Bit Latch
High Z
X
Next data bit shift**
CPOL=0
Read
H
CPOL=1
CPOL=0
* CPOL is the “Clock Polarity” bit that is set in the control register of the microcontroller.
** SDO remains at High Z until eight bits of data are ready to be shifted out during a read.
SERIAL CLOCK AS A FUNCTION OF MICROCONTROLLER CLOCK POLARITY (CPOL) Figure 6
CE
CPOL = 1
SHIFT
INTERNAL
STROBE
SCLK
CE
SHIFT
CPOL = 0
SCLK
NOTE: CPOL is a bit that is set in the microcontroller’s Control Register.
041497 10/20
INTERNAL
STROBE
DS1305
ADDRESS AND DATA BYTES
specify a write or read to either a RTC or RAM location,
followed by one or more bytes of data. Data is transferred out of the SDO for a read operation and into the
SDI for a write operation (see Figure 7 and 8).
Address and data bytes are shifted MSB first into the
serial data input (SDI) and out of the serial data output
(SDO). Any transfer requires the address of the byte to
SPI SINGLE BYTE WRITE Figure 7
CE
SCLK*
ÎÎÎ
SDI
A7
SDO
A6
A5
A4
A3
A2
A1
A0
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
ÎÎ
D0
HIGH Z
SPI SINGLE BYTE READ Figure 8
CE
SCLK*
ÎÎÎ
ÎÎÎ
SDI
A7
SDO
A6
A5
A4
A3
HIGH Z
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎ
D7
D6
D5
D4
D3
D2
D1
D0
* SCLK can be either polarity.
The address byte is always the first byte entered after
CE is driven high. The most significant bit (A7) of this
byte determines if a read or write will take place. If A7 is
0, one or more read cycles will occur. If A7 is 1, one or
more write cycles will occur.
Data transfers can occur one byte at a time or in multiple
byte burst mode. After CE is driven high an address is
written to the DS1305. After the address, one or more
data bytes can be written or read. For a single byte
transfer one byte is read or written and then CE is driven
low. For a multiple byte transfer, however, multiple
bytes can be read or written to the DS1305 after the
address has been written. Each read or write cycle
causes the RTC register or RAM address to automatically increment. Incrementing continues until the device
is disabled. When the RTC is selected, the address
wraps to 00h after incrementing to 1Fh (during a read)
and wraps to 80h after incrementing to 9Fh (during a
write). When the RAM is selected, the address wraps to
20h after incrementing to 7Fh (during a read) and wraps
to A0h after incrementing to FFh (during a write).
041497 11/20
DS1305
SPI MULTIPLE BYTE BURST TRANSFER Figure 9
CE
SCLK
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
WRITE
READ
SDI
ADDRESS
BYTE
SDI
ADDRESS
BYTE
SDO
DATA
BYTE 0
DATA
BYTE 1
DATA
BYTE 0
DATA
BYTE 1
3–WIRE INTERFACE
DATA
BYTE N
DATA
BYTE N
As is the case with the SPI mode, an address byte is
written to the device followed by a single data byte or
multiple data bytes. Figure 10 illustrates a read and
write cycle. Figure 11 illustrates a multiple byte burst
transfer. In 3–wire mode, data is input on the rising edge
of SCLK and output on the falling edge of SCLK.
The 3–wire interface mode operates similar to the SPI
mode. However, in 3–wire mode there is one I/O
instead of separate data in and data out signals. The
3–wire interface consists of the I/O (SDI and SDO pins
tied together), CE, and SCLK pins. In 3–wire mode,
each byte is shifted in LSB first unlike SPI mode where
each byte is shifted in MSB first.
3–WIRE SINGLE BYTE TRANSFER Figure 10
CE
SCLK
I/O*
A0
A1
A2
A3
A4
A5
A6
A7
D0
D1
D2
D3
* I/O is SDI and SDO tied together
3–WIRE MULTIPLE BYTE BURST TRANSFER Figure 11
CE
SCLK
I/O*
ADDRESS
BYTE
* I/O is SDI and SDO tied together
041497 12/20
DATA
BYTE 0
DATA
BYTE 1
DATA
BYTE N
D4
D5
D6
D7
DS1305
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground
Operating Temperature
Storage Temperature
Soldering Temperature
–0.5V to +7.0V
0°C to 70°C
–55°C to +125°C
260°C for 10 seconds
* This is a stress rating only and functional operation of the device at these or any other conditions above those
indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods of time may affect reliability.
The Dallas Semiconductor DS1305 is built to the highest quality standards and manufactured for long term reliability.
All Dallas Semiconductor devices are made using the same quality materials and manufacturing methods. However,
standard versions of the DS1305 are not exposed to environmental stresses, such as burn–in, that some industrial
applications require. Products which have successfully passed through this series of environmental stresses are
marked IND or N, denoting their extended operating temperature and reliability rating. For specific reliability information on this product, please contact the factory in Dallas at (972) 371–4448.
RECOMMENDED DC OPERATING CONDITIONS
PARAMETER
Supply Voltage VCC1, VCC2
Logic 1 Input
Logic 0 Input
SYMBOL
VCC1,
VCC2
VIH
VIL
(0°C to 70°C*)
MIN
TYP
MAX
UNITS
NOTES
2.5
5.5
V
1, 9
V
1
V
1
2.0
VCC+0.3
VCC=2.5V
–0.3
+0.3
VCC=5V
–0.3
+0.8
VBAT Battery Voltage
VBAT
2.5
5.5
V
1
VCCIF Supply Voltage
VCCIF
2.5
5.5
V
14
DC ELECTRICAL CHARACTERISTICS
PARAMETER
(0°C to +70°C*; VCC = 2.5 to 5.5V**)
SYMBOL
Input Leakage
ILI
Output Leakage
ILO
Logic 0 Output
VOL
Logic 1 Output
VOH
VCC1 Active Supply Current
ICC1A
VCC1 Timekeeping Current
ICC1T
VCC1 Standby Current
ICC1S
VCC2 Active Supply Current
ICC2A
VCC2 Timekeeping Current
ICC2T
MIN
TYP
MAX
UNITS
+500
µA
1
µA
VCC=2.5V
0.4
VCC=5V
0.4
VCCIF=2.5V
1.6
VCCIF=5V
2.4
VCC1=2.5V
0.425
VCC1=5V
1.28
VCC1=2.5V
25.3
VCC1=5V
81
VCC1=2.5V
25
VCC1=5V
80
VCC2=2.5V
0.4
VCC2=5V
1.2
VCC2=2.5V
0.3
VCC2=5V
1
NOTES
V
2
V
13
mA
4 10
4,
µA
3 10
3,
µA
8 10
8,
mA
4 11
4,
µA
3 11
3,
* –40°C to +85°C for industrial device
**Unless otherwise noted.
041497 13/20
DS1305
DC ELECTRICAL CHARACTERISTICS (cont’d)
PARAMETER
SYMBOL
(0°C to +70°C*; VCC = 2.5 to 5.5V**)
MIN
TYP
MAX
UNITS
NOTES
nA
8 11
8,
VCC2=2.5V
100
VCC2=5V
100
IBATT
VBAT=3V
300
nA
12
Battery Standby Current
IBATS
VBAT=3V
100
nA
12
Trickle Charge Resistors
R1
R2
R3
2
4
8
KΩ
KΩ
KΩ
Trickle Charger Diode Voltage Drop
VTD
0.7
V
VCC2 Standby Current
ICC2S
Battery Timekeeping Current
CAPACITANCE
PARAMETER
(tA = 25°C)
SYMBOL
CONDITION
TYP
MAX
UNITS
Input Capacitance
CI
10
pF
Output Capacitance
CO
15
pF
Crystal Capacitance
CX
6
pF
3–WIRE AC ELECTRICAL CHARACTERISTICS
PARAMETER
Data to CLK Setup
CLK to Data Hold
CLK to Data Delay
CLK Low Time
CLK High Time
CLK Frequency
CLK Rise and Fall
* –40°C to +85°C for industrial device
**Unless otherwise noted.
041497 14/20
SYMBOL
tDC
tCDH
tCDD
tCL
tCH
tCLK
tR, tF
(0°C to 70°C*; VCC = 2.5V to 5.5V**)
MIN
VCC =2.5V
200
VCC=5V
50
VCC=2.5V
280
VCC=5V
70
TYP
MAX
VCC=2.5V
800
VCC=5V
200
VCC=2.5V
1000
VCC=5V
250
VCC=2.5V
1000
VCC=5V
250
VCC=2.5V
VCC=5V
NOTES
UNITS
NOTES
ns
5 6
5,
ns
5 6
5,
ns
5 6,
6 7
5,
ns
6
ns
6
MHz
6
0.6
DC
2.0
VCC=2.5V
2000
VCC=5V
500
ns
DS1305
3–WIRE AC ELECTRICAL CHARACTERISTICS (cont’d)
PARAMETER
SYMBOL
CE to CLK Setup
tCC
CLK to CE Hold
tCCH
CE Inactive Time
tCWH
CE to Output High Z
tCDZ
SCLK to Output High Z
tCCZ
(0°C to 70°C*; VCC = 2.5 to 5.5V**)
MIN
VCC =2.5V
4
VCC=5V
1
VCC=2.5V
240
VCC=5V
60
VCC=2.5V
4
VCC=5V
1
TYP
MAX
VCC=2.5V
280
VCC=5V
70
VCC=2.5V
280
VCC=5V
70
UNITS
NOTES
µs
6
ns
6
µs
6
ns
5 6
5,
ns
5 6
5,
* –40°C to +85°C for industrial device
**Unless otherwise noted.
TIMING DIAGRAM: 3–WIRE READ DATA TRANSFER Figure 12
CE
tCC
SCLK
tCCZ
tCDH
tCDZ
tCDD
tDC
I/O*
tCDD
A0
A1
A7
WRITE ADDRESS BYTE
D0
D1
READ DATA BIT
TIMING DIAGRAM: 3–WIRE WRITE DATA TRANSFER Figure 13
tCWH
CE
tCC
tCCH
tR
tCL
tF
SCLK
tCDH
tCH
tDC
I/O*
A0
A1
WRITE ADDRESS BYTE
A7
D0
WRITE DATA
* I/O is SDI and SDO tied together.
041497 15/20
DS1305
SPI AC ELECTRICAL CHARACTERISTICS
PARAMETER
Data to CLK Setup
CLK to Data Hold
CLK to Data Delay
CLK Low Time
CLK High Time
CLK Frequency
CLK Rise and Fall
CE to CLK Setup
CLK to CE Hold
CE Inactive Time
CE to Output High Z
* –40°C to +85°C for industrial device
**Unless otherwise noted.
041497 16/20
(0°C to 70°C*; VCC = 2.5 to 5.5V**)
SYMBOL
tDC
tCDH
tCDD
tCL
tCH
tCLK
tR, tF
tCC
tCCH
tCWH
tCDZ
MIN
VCC =2.5V
200
VCC=5V
50
VCC=2.5V
280
VCC=5V
70
TYP
MAX
VCC=2.5V
800
VCC=5V
200
VCC=2.5V
1000
VCC=5V
250
VCC=2.5V
1000
VCC=5V
250
VCC=2.5V
VCC=5V
UNITS
NOTES
ns
5 6
5,
ns
5 6
5,
ns
5 6,
6 7
5,
ns
6
ns
6
MHz
6
0.6
DC
2.0
VCC=2.5V
2000
VCC=5V
500
ns
VCC=2.5V
4
VCC=5V
1
VCC=2.5V
240
VCC=5V
60
VCC=2.5V
4
VCC=5V
1
VCC=2.5V
280
VCC=5V
70
µs
6
ns
6
µs
6
ns
5 6
5,
DS1305
TIMING DIAGRAM: SPI READ DATA TRANSFER Figure 14
CE
tCC
SCLK*
tCDD
tCDD
tCDH
tDC
SDI
A7
A6
A0
tCDZ
SDO
D7
D6
WRITE ADDRESS BYTE
D1
D0
READ DATA BYTE
TIMING DIAGRAM: SPI WRITE DATA TRANSFER Figure 15
tCWH
CE
tCC
tR
tCL
tF
tCCH
SCLK*
tCDH
tCH
tCDH
tDC
SDI
A7
A6
WRITE ADDRESS BYTE
A0
D7
D0
WRITE DATA BYTE
* SCLK can be either polarity, timing shown for CPOL = 1.
041497 17/20
DS1305
NOTES:
1. All voltages are referenced to ground.
2. Logic zero voltages are specified at a sink current of 4 mA at VCC=5V and 1.5 mA at VCC=2.5V, VOL=GND for
capacitive loads.
3. ICC1T and ICC2T are specified with CE set to a logic “0” and EOSC bit=0 (oscillator enabled).
4. ICC1A and ICC2A are specified with CE=VCC, SCLK=2 MHz (0–VCC) at VCC=5V; SCLK=500 KHz (0–5V) at
VCC=2.5V and EOSC bit=0 (oscillator enabled).
5. Measured at VIH=2.0V or VIL=0.8V and 10 ms maximum rise and fall time.
6. Measured with 50 pF load.
7. Measured at VOH=2.4V or VOL=0.4V.
8. ICC1S and ICC2S are specified with CE set to a logic “0”. The EOSC bit must be set to logic one (oscillator disabled).
9. VCC=VCC1, when VCC1>VCC2+0.2V (typical); VCC=VCC2, when VCC2>VCC1.
10. VCC2=0 volts.
11. VCC1=0 volts.
12. (VCC1 =VCC2) < VBAT.
13. Logic one voltages are specified at a source current of 1 mA at VCC=5V and 0.4 mA at 2.5V, VOH=VCC.
14. VCCIF must be less than or equal to the largest of VCC1, VCC2, and VBAT.
041497 18/20
DS1305
DS1305 16–PIN DIP (300 MIL)
B
1
A
D
E
C
F
K
G
PKG
J
H
16–PIN
DIM
MIN
MAX
A IN.
MM
0.740
18.80
0.780
19.81
B IN.
MM
0.240
6.10
0.260
6.60
C IN.
MM
0.120
3.05
0.140
3.56
D IN.
MM
0.300
7.62
0.325
8.26
E IN.
MM
0.015
0.38
0.040
1.02
F IN.
MM
0.120
3.05
0.140
3.56
G IN.
MM
0.090
2.29
0.110
2.79
H IN
MM
0.320
8.13
0.370
9.40
J IN
MM
0.008
0.20
0.012
0.30
K IN.
MM
0.015
0.38
0.021
0.53
041497 19/20
DS1305
DS1305 20–PIN TSSOP
D
n
E
H
SEE DETAIL A
c
B
e1
A2
A
A1
phi
L
DETAIL A
DIM
MIN
MAX
A MM
–
1.10
A1 MM
0.05
–
A2 MM
0.75
1.05
C MM
0.09
0.18
L MM
0.50
0.70
e1 MM
0.65 BSC
B MM
0.18
0.30
D MM
6.40
6.90
E MM
4.40 NOM
G MM
0.25 REF
H MM
phi
6.25
6.55
0°
8°
56–G2010–000
041497 20/20
G
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