Programmable Line Lock Clock Generator IC

Programmable Line Lock Clock Generator IC
FS6131-01
Programmable Line Lock Clock Generator IC
1.0
Features
3.0
ä
Applications
•
Complete programmable control via I C -bus
•
Frequency Synthesis
•
Selectable CMOS or PECL compatible outputs
•
Line-Locked and Genlock Applications
•
External feedback loop capability allows genlocking
•
Clock Multiplication
•
Tunable VCXO loop for jitter attenuation
•
Telecom Jitter Attenuation
•
Commercial (FS6131-01) and industrial (FS6131-01i)
temperature versions available
Figure 1: Pin Configuration
2
2.0
1
16
CLKN
SDA
2
15
The FS6131-01 is a monolithic CMOS clock generator/regenerator IC designed to minimize cost and compo2
nent count in a variety of electronic systems. Via the I Cbus interface, the FS6131-01 can be adapted to many
clock generation requirements.
The ability to tune the on-board voltage-controlled crystal
oscillator (VCXO), the length of the Reference and Feedback Dividers, their granularity, and the flexibility of the
Post Divider make the FS6131-01 the most flexible
stand-alone phase-locked loop (PLL) clock generator
available.
CLKP
ADDR
3
14
VDD
VSS
4
13
FBK
XIN
5
12
REF
FS6131
SCL
Description
XOUT
6
11
VSS
XTUNE
7
10
EXTLF
VDD
8
9
LOCK/IPRG
16-pin 0.150" SOIC
Figure 2: Block Diagram
LFTC
XTUNE
(optional)
Control
ROM
XCT[3:0],
XLVTEN
XIN
VCXO
Divider
VCXO
XOUT
(optional)
CLF
CLP
CRYSTAL LOOP
XLROM[2:0]
XLPDEN,
XLSWAP
Internal
Loop
Filter
XLCP[1:0]
0
UP
PhaseFrequency
Detector
Charge
Pump
RLF
EXTLF
1
(optional)
EXTLF
STAT[1:0]
DOWN
Lock
Detect
0
REFDIV[11:0]
REF
0
(fREF)
1
Reference
Divider
REFDSRC
VCOSPD,
OSCTYPE
MLCP[1:0]
0
(NR)
PhaseFrequency
Detector
1
0
UP
Charge
Pump
DOWN
11
Voltage
Controlled
Oscillator
ADDR
11
Feedback
Divider (NF)
SDA
I2C
Interface
01
(optional)
Clock
Gobbler
10
(fVCO)
CLKP
Post
Divider
(NPx)
(fCLK)
CLKN
CMOS/PECL
Output
10
00
FBKDSRC[1:0]
Registers
01
00
OUTMUX[1:0]
PDFBK
SCL
GBL
POST3[1:0]
POST2[1:0]
POST1[1:0]
LOCK/
IPRG
PDREF
1
FBK
CMOS
1
MAIN LOOP
FBKDIV[13:0]
FS6131
I2C is a licensed trademark of Philips Electronics, N.V. Windows and Windows NT are registered trademarks of Microsoft Corporation. American Microsystems, Inc. reserves the right to change detail
specifications as may be required to permit improvements in the design of its products.
FS6131-01
Programmable Line Lock Clock Generator IC
Table 1: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input,
DO = Digital Output; P = Power/Ground; # = Active Low pin
PIN
TYPE
NAME
DESCRIPTION
1
DI
SCL
Serial Interface Clock (requires an external pull-up)
2
DIO
SDA
Serial Interface Data Input/Output (requires an external pull-up)
3
DI
ADDR
4
P
VSS
Ground
5
AI
XIN
VCXO Feedback
6
AO
XOUT
VCXO Drive
7
AI
XTUNE
VCXO Tune
8
P
VDD
9
DIO
LOCK/IPRG
10
AI
EXTLF
11
P
VSS
12
DI
REF
Reference Frequency Input
13
DI
FBK
Feedback Input
Address Select Bit (see Section 5.2.1)
Power Supply (+5V)
Lock Indicator / PECL Current Drive Programming
External Loop Filter
Ground
14
P
VDD
Power Supply (+5V)
15
DO
CLKP
Differential Clock Output (+)
16
DO
CLKN
Differential Clock Output (-)
4.0
Functional Block Description
4.1
Main Loop PLL
frequency appearing at the inputs of the PFD are equal.
The input/output relationship between the reference frequency and the VCO frequency is
fVCO
f
= REF .
NF
NR
The Main Loop Phase Locked Loop (ML-PLL) is a standard phase- and frequency- locked loop architecture. As
shown in Figure 2, the ML-PLL consists of a Reference
Divider, a Phase-Frequency Detector (PFD), a charge
pump, an internal loop filter, a Voltage-Controlled Oscillator (VCO), a Feedback Divider, and a Post Divider.
During operation, the reference frequency (fREF), generated by either the on-board crystal oscillator or an external frequency source, is first reduced by the Reference
Divider. The integer value that the frequency is divided by
is called the modulus, and is denoted as NR for the Reference Divider. The divided reference is then fed into the
PFD.
The PFD controls the frequency of the VCO (fVCO)
through the charge pump and loop filter. The VCO provides a high-speed, low noise, continuously variable frequency clock source for the ML-PLL. The output of the
VCO is fed back to the PFD through the Feedback Divider (the modulus is denoted by NF) to close the loop.
The PFD will drive the VCO up or down in frequency until
the divided reference frequency and the divided VCO
If the VCO frequency is used as the PLL output frequency (fCLK) then the basic PLL equation can be rewritten as
æN ö
f CLK = f REF çç F ÷÷ .
è NR ø
4.1.1
Reference Divider
The Reference Divider is designed for low phase jitter.
The divider accepts either the output of either the Crystal
Loop (the VCXO output) or an external reference frequency, and provides a divided-down frequency to the
PFD. The Reference Divider is a 12-bit divider, and can
be programmed for any modulus from 1 to 4095. See
both Table 3 and Table 8 for additional programming information.
2
FS6131-01
Programmable Line Lock Clock Generator IC
4.1.2
Feedback Divider
The Feedback Divider is based on a dual-modulus
prescaler technique. The technique allows the same
granularity as a fully programmable feedback divider,
while still allowing the programmable portion to operate at
low speed. A high-speed pre-divider (also called a
prescaler) is placed between the VCO and the programmable Feedback Divider because of the high speeds at
which the VCO can operate. The dual-modulus technique
insures reliable operation at any speed that the VCO can
achieve and reduces the overall power consumption of
the divider.
For example, a fixed divide-by-eight could be used in the
Feedback Divider. Unfortunately, a divide-by-eight would
limit the effective modulus of the feedback divider path to
multiples of eight. The limitation would restrict the ability
of the PLL to achieve a desired input-frequency-tooutput-frequency ratio without making both the Reference
and Feedback Divider values comparatively large. Large
divider moduli are generally undesirable due to increased
phase jitter.
4.1.3
The requirement that M≥A means that the Feedback Divider can only be programmed for certain values below a
divider modulus of 56. The selection of divider values is
listed in Table 2.
If the desired Feedback Divider is less than 56, find the
divider value in the table. Follow the column up to find the
A-counter program value. Follow the row to the left to find
the M-counter value.
Above a modulus of 56, the Feedback Divider can be
programmed to any value up to 16383. See both Table 3
and Table 8 for additional programming information.
Table 2: Feedback Modulus Below 56
Figure 3: Feedback Divider
fvco
DualModulus
Prescaler
Feedback Divider Programming
M
Counter
A-COUNTER: FBKDIV[2:0]
M-COUNTER:
FBKDIV[13:3]
000
001
010
011
100
101
110
111
00000000001
8
9
-
-
-
-
-
-
00000000010
16
17
18
-
-
-
-
-
00000000011
24
25
26
27
-
-
-
-
00000000100
32
33
34
35
36
-
-
-
00000000101
40
41
42
43
44
45
-
-
00000000110
48
49
50
51
52
53
54
-
00000000111
56
57
58
59
60
61
62
63
FEEDBACK DIVIDER MODULUS
A
Counter
4.1.4
Post Divider
The Post Divider consists of three individually programmable dividers, as shown in Figure 4.
To understand the operation, refer to Figure 3. The Mcounter (with a modulus of M) is cascaded with the dualmodulus prescaler. If the prescaler modulus were fixed at
N, the overall modulus of the feedback divider chain
would be M×N. However, the A-counter causes the
prescaler modulus to be altered to N+1 for the first A outputs of the prescaler. The A-counter then causes the
dual-modulus prescaler to revert to a modulus of N until
the M-counter reaches its terminal state and resets the
entire divider. The overall modulus can be expressed as
A( N + 1) + N ( M − A) ,
Figure 4: Post Divider
fGBL
POST1[1:0]
POST2[1:0]
POST3[1:0]
Post
Divider 1
(NP1)
Post
Divider 2
(NP2)
Post
Divider 3
(NP3)
fout
POST DIVIDER (NPx)
The moduli of the individual dividers are denoted as NP1,
NP2, and NP3, and together they make up the array
modulus NPx.
where M ≥ A, which simplifies to
M × N + A.
N Px = N P1 × N P 2 × N P 3
3
FS6131-01
Programmable Line Lock Clock Generator IC
The Post Divider performs several useful functions. First,
it allows the VCO to be operated in a narrower range of
speeds compared to the variety of output clock speeds
that the device is required to generate. Second, it
changes the basic PLL equation to
4.2.1
Clock Gobbler (Phase Adjust)
The Clock Gobbler circuit takes advantage of the unknown relationship between input and output clocks to
permit the adjustment of the CLKP/CLKN output clock
phase relative to the REF input. The Clock Gobbler circuit
removes a VCO clock pulse before the pulse clocks the
Post Divider. In this way, the phase of the output clock
can be slipped until the output phase is aligned with the
input clock phase.
To adjust the phase relationship, switch the Feedback
Divider source to the Post Divider input via the
FBKDSRC bit, and toggle the GBL register bit. The Clock
Gobbler output clock is delayed by one VCO clock period
for each transition of the GBL bit from zero to one.
æ N öæ 1 ö
÷÷ .
f CLK = f REF çç F ÷÷çç
N
N
è R øè Px ø
The extra integer in the denominator permits more flexibility in the programming of the loop for many applications where frequencies must be achieved exactly.
Note that a nominal 50/50 duty factor is preserved for
selections which have an odd modulus.
4.2
Phase Adjust and Sampling
In line-locked or genlocked applications, it is necessary to
know the exact phase relation of the output clock relative
to the input clock. Since the VCO is included within the
feedback loop in a simple PLL structure, the VCO output
is exactly phase aligned with the input clock. Every cycle
of the input clock equals NR/NF cycles of the VCO clock.
4.2.2
Phase Alignment
To maintain a fixed phase relation between input and
output clocks, the Post Divider must be placed inside the
feedback loop. The source for the Feedback Divider is
obtained from the output of the Post Divider via the
FBKDSRC switch. In addition, the Feedback Divider must
be dividing at a multiple of the Post Divider.
Figure 5: Simple PLL
Reference
Divider (NR)
fIN
Figure 7: Aligned I/O Phase
Phase
Frequency
Detect
fIN
fOUT
VCO
Feedback
Divider (NF)
fOUT
Reference
Divider (NR)
fIN
fIN
fOUT
Figure 6: PLL with Post Divider
Reference
Divider (NR)
fIN
VCO
Feedback
Divider (NF)
fVCO
fOUT
Phase
Frequency
Detect
Post
Divider (NF)
VCO
Post
Divider (NF)
fOUT
Feedback
Divider (NF)
4.2.3
Phase Sampling and Initial Alignment
However, the ability to adjust the phase is useless without knowing the initial relation between output and input
phase. To aid in the initial synchronization of the output
phase to input phase, a Phase Align “flag” makes a transition (zero to one or one to zero) when the output clock
phase becomes aligned with the feedback source phase.
The feedback source clock is, by definition, locked to the
input clock phase.
First, the FS6131 is used to sample the output clock with
the feedback source clock and set/clear the Phase Align
flag when the two clocks match to within a feedback
source clock period. Then, the Clock Gobbler is used to
delay the output phase relative to the input phase one
VCO clock at a time until a transition on the flag occurs.
When a transition occurs, the output and input clocks are
phase aligned.
The addition of a Post Divider, while adding flexibility,
makes the phase relation between the input and output
clock unknown because the Post Divider is outside the
feedback loop.
fIN
Phase
Frequency
Detect
fOUT
fVCO
?
4
FS6131-01
Programmable Line Lock Clock Generator IC
To enter this mode, set STAT[1] to one and clear
STAT[0] to zero. If the CMOS bit is set to one, the
LOCK/IPRG pin can display the flag. The flag is always
available under software control by reading back the
STAT[1] bit, which will be overwritten by the flag in this
mode.
The VCO transfer function (in rad/s, and accounting for
the phase integration that occurs in the VCO) is:
K VCO ( s ) = 2πAVCO
The transfer function of the Feedback Divider is:
KF =
4.2.4
Feedback Divider Monitoring
The Feedback Divider clock can be brought out the
LOCK/IPRG pin independent of the output clock to allow
monitoring of the Feedback Divider clock. To enter this
mode, set both the STAT[1] and STAT[0] bits to one. The
CMOS bit must also be set to one to enable the
LOCK/IPRG pin as an output.
4.3
1
NF
Finally, the sampling effect that occurs in the Phase Detector is accounted for by:
ö
− æç s
æ
÷
ç 1 − e è f REF ø
K SAMP ( s ) = ç
s
ç
è
Loop Gain Analysis
For applications where an external loop filter is required,
the following analysis example can be used to determine
loop gain and stability.
The loop gain of a PLL is the product of all of the gains
within the loop.
Establish the basic operating parameters:
Set the charge pump current:
1
s
ö
÷
÷ f REF
÷
ø
The loop gain of the PLL is:
K LOOP ( s ) = K PD K LF ( s ) K VCO ( s ) K F K SAMP ( s )
Figure 8: Loop Gain vs. Frequency
I chgpump = 10 µA
100
RLF = 15kΩ
C1 = 0.015µF
Set the loop filter values:
10
Set the VCO gain (VCOSPD):
AVCO = 230 MHz / V
Set the Feedback Divider:
N F = 3500
Amplitude
C 2 = 220 pF
Set the Reference frequency (at the input to the Phase
Detector:
f REF = 20kHz
1
0.1
The transfer function of the Phase Detector and Charge
Pump combination is (in A/rad):
K PD =
I chgpump
0.01
0.1kHz
2π
10kHz
Frequency (fi)
The transfer function of the loop filter is (in V/A):
K LF ( s ) =
1kHz
1
æ
ö
ç
÷
1
÷
sC 2 + ç
ç R +æ 1
ö÷
ç LF ç sC ÷ ÷
è
1øø
è
5
100kHz
FS6131-01
Programmable Line Lock Clock Generator IC
The loop phase angle is:
[
]
Θ i = arg K LOOP ( j 2πf i ) .
4.4
Figure 9: Loop Phase vs. Frequency
Phase
-100°
-150°
0.1kHz
1kHz
10kHz
100kHz
Frequency (fi)
A Nyquist plot of gain vs. amplitude is shown below.
Figure 10: Loop Nyquist Plot
90°
1.2
1.0
135°
Voltage-Controlled Crystal Oscillator
The VCXO provides a tunable, low-jitter frequency reference for the rest of the FS6131 system components.
Loading capacitance for the crystal is internal to the device. No external components (other than the resonator
itself) are required for operation of the VCXO.
The resonator loading capacitance is adjustable under
register control. This feature permits factory coarse tuning of inexpensive resonators to the necessary precision
for digital video applications. Continuous fine-tuning of
the VCXO frequency is accomplished by varying the voltage on the XTUNE pin. The total change (from one extreme to the other) in effective loading capacitance is
1.5pF nominal, and the effect is shown in Figure 11. The
oscillator operates the crystal resonator in the parallelresonant mode. Crystal warping, or the “pulling” of the
crystal oscillation frequency, is accomplished by altering
the effective load capacitance presented to the crystal by
the oscillator circuit. The actual amount that changing the
load capacitance alters the oscillator frequency will be
dependent on the characteristics of the crystal as well as
the oscillator circuit itself.
The motional capacitance of the crystal (usually referred
to by crystal manufacturers as C1), the static capacitance
of the crystal (C0), and the load capacitance (CL) of the
oscillator determine the warping capability of the crystal
in the oscillator circuit. A simple formula to determine the
total warping capability of a crystal is
45°
0.8
Amplitude
0.6
0.4
0.2
Gain Margin
180°
∆f ( ppm) =
0°
where CL1 and CL2 are the two extremes of the applied
load capacitance obtained from Table 11.
Example: A crystal with the following parameters is used
with the FS6131. The total coarse tuning range is:
C1=0.02pF, C0=5.0pF, CL1=10.0pF, CL2=22.66pF
Phase
Margin
225°
6
C1 × (C L 2 − C L1) × 10
,
2 × (C 0 + C L 2 ) × (C 0 + C L1)
315°
∆f =
270°
Phase
6
0.02 × (22.66 − 10 ) × 10 6
= 305 ppm
2 × (5 + 22.66 ) × (5 + 10 )
FS6131-01
Programmable Line Lock Clock Generator IC
4.4.1
VCXO Tuning
The VCXO may be coarse tuned by a programmable adjustment of the crystal load capacitance via the XCT[3:0]
control bits. See Table 11 for the control code and the
associated loading capacitance.
The actual amount of frequency warping caused by the
tuning capacitance will depend on the crystal used. The
VCXO tuning capacitance includes an external 6pF load
capacitance (12pF from the XIN pin to ground and 12pF
from the XOUT pin to ground). The fine tuning capability
of the VCXO can be enabled by setting the XLVTEN bit
to a one, or disabled by setting it to a zero.
Figure 11 shows the typical effect of the coarse and fine
tuning mechanisms. The total coarse tune range is about
350ppm. The difference in VCXO frequency in parts per
million (ppm) is shown as the fine tuning voltage on the
XTUNE pin varies from 0V to 5V. Note that as the crystal
load capacitance is increased the VCXO frequency is
pulled somewhat less with each coarse step, and the fine
tuning range decreases. The fine tuning range always
overlaps a few coarse tuning ranges, eliminating the possibility of holes in the VCXO response. The different
crystal warping characteristics may change the scaling on
the Y-axis, but not the overall characteristic of the curves.
4.5
Crystal Loop
The Crystal Loop is designed to attenuate the jitter on a
highly jittered, low-Q, low frequency reference. The
Crystal Loop can also maintain a constant frequency output into the Main Loop if the low frequency reference is
intermittent.
The Crystal Loop consists of a Voltage-Controllable
Crystal Oscillator (VCXO), a divider, a PFD, and a charge
pump that tunes the VCXO to a frequency reference. The
frequency reference is phase-locked to the divided frequency of an external, high-Q, jitter-free crystal, thereby
locking the VCXO to the reference frequency. The VCXO
can continue to run off the crystal even if the frequency
reference becomes intermittent.
4.5.1
Locking to an External Frequency Source
When the Crystal Loop is synchronized to an external
frequency source, the FS6131 can monitor the Crystal
Loop and detect if the loop unlocks from the external
source. The Crystal Loop tries to drive to zero frequency
if the external source is dropped, and sets a Lock Status
error flag.
The Crystal Loop can also detect if the VCXO has
dropped out of the Fine Tune range, requiring a change
to the Coarse Tune. The Lock Status also latches the
direction the loop went out of range (high or low) when
the loop became unlocked.
Figure 11: VCXO Coarse and Fine Tuning
VCXO Range (ppm) vs. XTUNE Voltage (V)
4.5.1.1 Crystal Loop Lock Status Flag
To enable this mode, clear the STAT[1] and STAT[0] bits
to zero. If the CMOS bit is set to one, the LOCK/IPRG pin
will be low if the Crystal Loop becomes unlocked. The
flag is always available under software control by reading
back the STAT[1] bit, which is overwritten with a the
status flag (low = unlocked) in this mode (see Table 6).
200
VCXO Range (ppm)
150
XTUNE Voltage = 0.0V
100
XTUNE Voltage = 5.0V
50
0
-50
-100
-150
-200
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Coarse Tune Setting XCT[3:0]
7
FS6131-01
Programmable Line Lock Clock Generator IC
4.5.1.2 Out-Of-Range High/Low
The direction the loop has gone out-of-range can be determined by clearing STAT[1] to zero and setting STAT[0]
bit to one. If the CMOS bit is set to one, the LOCK/IPRG
pin will go high if the Crystal Loop went out of range high.
If the pin goes to a logic-low, the loop went out of range
low.
The out-of-range information is also available under software control by reading back the STAT[1] bit, which is
overwritten by the flag (high = out-of-range high, low =
out-of-range low) in this mode. The bit is set or cleared
only if the Crystal Loop loses lock (see Table 6).
4.7
4.5.1.3 Crystal Loop Disable
The Crystal Loop is disabled by setting the XLPDEN bit
to a logic-high (1). The bit disables the charge pump circuit in the loop.
Setting the XLPDEN bit low (0) permits the crystal loop to
operate as a control loop.
Figure 12: IPRG to CLKP/CLKN Current
25.0
IPRG Input Current (mA)
4.6
Differential Output Stage
The differential output stage supports both CMOS and
pseudo-ECL (PECL) signals. The desired output interface
is chosen via the program registers (see Table 4).
If a PECL interface is used, the transmission line is usually terminated using a Thévenin termination. The output
stage can only sink current in the PECL mode, and the
amount of sink current is set by a programming resistor
on the LOCK/IPRG pin. The ratio of IPRG current to output drive current is shown in Figure 12. Source current is
provided by the pull-up resistor that is part of the
Thévenin termination.
Connecting the FS6131 to an
External Reference Frequency
If a crystal oscillator is not used, tie XIN to ground and
shut down the crystal oscillator by setting XLROM[2:0]=1.
The REF and FBK pins do not have pull-up or pull-down
current, but do have a small amount of hysteresis to reduce the possibility of extra edges. Signals may be ACcoupled into these inputs with an external DC-bias circuit
to generate a DC-bias of 2.5V. Any Reference or Feedback signal should be square for best results, and the
signals should be rail-to-rail. Unused inputs should be
grounded to avoid unwanted signal injection.
20.0
15.0
10.0
5.0
0.0
0
20
40
60
CLKP/CLKN PECL Output Current (mA)
8
80
FS6131-01
Programmable Line Lock Clock Generator IC
5.0
Each data transfer is initiated by a START condition and
terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions
is determined by the master device, and can continue
indefinitely. However, data that is overwritten to the device after the first eight bytes will overflow into the first
register, then the second, and so on, in a first-in, firstoverwritten fashion.
2
I C-bus Control Interface
This device is a read/write slave device
2
meeting all Philips I C-bus specifications
except a “general call.” The bus has to be
controlled by a master device that generates
the serial clock SCL, controls bus access, and generates
the START and STOP conditions while the device works
as a slave. Both master and slave can operate as a
transmitter or receiver, but the master device determines
which mode is activated. A device that sends data onto
the bus is defined as the transmitter, and a device receiving data as the receiver.
2
I C-bus logic levels noted herein are based on a percentage of the power supply (VDD). A logic-one corresponds
to a nominal voltage of VDD, while a logic-zero corresponds to ground (VSS).
5.1
5.1.5
Acknowledge
When addressed, the receiving device is required to generate an Acknowledge after each byte is received. The
master device must generate an extra clock pulse to coincide with the Acknowledge bit. The acknowledging device must pull the SDA line low during the high period of
the master acknowledge clock pulse. Setup and hold
times must be taken into account.
The master must signal an end of data to the slave by not
generating and acknowledge bit on the last byte that has
been read (clocked) out of the slave. In this case, the
slave must leave the SDA line high to enable the master
to generate a STOP condition.
Bus Conditions
Data transfer on the bus can only be initiated when the
bus is not busy. During the data transfer, the data line
(SDA) must remain stable whenever the clock line (SCL)
is high. Changes in the data line while the clock line is
high will be interpreted by the device as a START or
STOP condition. The following bus conditions are defined
2
by the I C-bus protocol.
5.2
I2C-bus Operation
All programmable registers can be accessed randomly or
sequentially via this bi-directional two wire digital interface. The crystal oscillator does not have to run for communication to occur.
2
The device accepts the following I C-bus commands:
5.1.1
Not Busy
Both the data (SDA) and clock (SCL) lines remain high to
indicate the bus is not busy.
5.2.1
Slave Address
After generating a START condition, the bus master
broadcasts a seven-bit slave address followed by a R/W
bit. The address of the device is:
5.1.2
START Data Transfer
A high to low transition of the SDA line while the SCL input is high indicates a START condition. All commands to
the device must be preceded by a START condition.
5.1.3
STOP Data Transfer
A low to high transition of the SDA line while SCL is held
high indicates a STOP condition. All commands to the
device must be followed by a STOP condition.
A6
A5
A4
A3
A2
A1
A0
1
0
1
1
X
0
0
where X is controlled by the logic level at the ADDR pin.
The variable ADDR bit allows two different FS6131 devices to exist on the same bus. Note that every device on
2
an I C-bus must have a unique address to avoid bus
conflicts. The default address sets A2 to 0 via the pulldown on the ADDR pin.
5.1.4
Data Valid
The state of the SDA line represents valid data if the SDA
line is stable for the duration of the high period of the SCL
line after a START condition occurs. The data on the
SDA line must be changed only during the low period of
the SCL signal. There is one clock pulse per data bit.
9
FS6131-01
Programmable Line Lock Clock Generator IC
To initiate a write procedure, the R/W bit that is transmitted after the seven-bit device address is a logic-low. This
indicates to the addressed slave device that a register
address will follow after the slave device acknowledges
its device address. The register address is written into the
slave’s address pointer. Following an acknowledge by the
slave, the master is allowed to write up to eight bytes of
data into the addressed register before the register address pointer overflows back to the beginning address.
An acknowledge by the device between each byte of data
must occur before the next data byte is sent.
Registers are updated every time the device sends an
acknowledge to the host. The register update does not
wait for the STOP condition to occur. Registers are
therefore updated at different times during a Sequential
Register Write.
5.2.2
Random Register Write Procedure
Random write operations allow the master to directly
write to any register. To initiate a write procedure, the
R/W bit that is transmitted after the seven-bit device address is a logic-low. This indicates to the addressed slave
device that a register address will follow after the slave
device acknowledges its device address. The register
address is written into the slave’s address pointer. Following an acknowledge by the slave, the master is allowed to write eight bits of data into the addressed register. A final acknowledge is returned by the device, and
the master generates a STOP condition.
If either a STOP or a repeated START condition occurs
during a Register Write, the data that has been transferred is ignored.
5.2.5
Sequential Register Read Procedure
Sequential read operations allow the master to read from
each register in order. The register pointer is automatically incremented by one after each read. This procedure
is more efficient than the Random Register Read if several registers must be read.
To perform a read procedure, the R/W bit that is transmitted after the seven-bit address is a logic-low, as in the
Register Write procedure. This indicates to the addressed
slave device that a register address will follow after the
slave device acknowledges its device address. The register address is then written into the slave’s address
pointer.
Following an acknowledge by the slave, the master generates a repeated START condition. The repeated
START terminates the write procedure, but not until after
the slave’s address pointer is set. The slave address is
then resent, with the R/W bit set this time to a logic-high,
indicating to the slave that data will be read. The slave
will acknowledge the device address, and then transmits
all eight bytes of data starting with the initial addressed
register. The register address pointer will overflow if the
initial register address is larger than zero. After the last
byte of data, the master does not acknowledge the
transfer but does generate a STOP condition.
5.2.3
Random Register Read Procedure
Random read operations allow the master to directly read
from any register. To perform a read procedure, the R/W
bit that is transmitted after the seven-bit address is a
logic-low, as in the Register Write procedure. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its
device address. The register address is then written into
the slave’s address pointer.
Following an acknowledge by the slave, the master generates a repeated START condition. The repeated
START terminates the write procedure, but not until after
the slave’s address pointer is set. The slave address is
then resent, with the R/W bit set this time to a logic-high,
indicating to the slave that data will be read. The slave
will acknowledge the device address, and then transmits
the eight-bit word. The master does not acknowledge the
transfer but does generate a STOP condition.
5.2.4
Sequential Register Write Procedure
Sequential write operations allow the master to write to
each register in order. The register pointer is automatically incremented after each write. This procedure is
more efficient than the Random Register Write if several
registers must be written.
10
FS6131-01
Programmable Line Lock Clock Generator IC
Figure 13: Random Register Write Procedure
S
DEVICE ADDRESS
W A
7-bit Receive
Device Address
REGISTER ADDRESS
A
Register Address
A P
Data
Acknowledge
START
Command
DATA
Acknowledge
STOP Condition
WRITE Command
From bus host
to device
Acknowledge
From device
to bus host
Figure 14: Random Register Read Procedure
S
DEVICE ADDRESS
W A
7-bit Receive
Device Address
REGISTER ADDRESS
A S
DATA
A P
Data
Acknowledge
Repeat START
WRITE Command
From bus host
to device
R A
7-bit Receive
Device Address
Register Address
Acknowledge
START
Command
DEVICE ADDRESS
Acknowledge
STOP Condition
READ Command
NO Acknowledge
From device
to bus host
Figure 15: Sequential Register Write Procedure
S
DEVICE ADDRESS
W A
7-bit Receive
Device Address
REGISTER ADDRESS
DATA
Register Address
Acknowledge
START
Command
A
A
DATA
DATA
Data
Data
Acknowledge
A
Acknowledge
Data
Acknowledge
WRITE Command
From bus host
to device
A P
Acknowledge
STOP Command
From device
to bus host
Figure 16: Sequential Register Read Procedure
S
DEVICE ADDRESS
7-bit Receive
Device Address
W A
REGISTER ADDRESS
Register Address
Acknowledge
START
Command
WRITE Command
From bus host
to device
A S
DEVICE ADDRESS
R A
DATA
7-bit Receive
Device Address
Repeat START
Acknowledge
A
DATA
Data
Acknowledge
READ Command
From device
to bus host
11
A P
Data
Acknowledge
NO Acknowledge
STOP Command
FS6131-01
Programmable Line Lock Clock Generator IC
6.0
Programming Information
All register bits are cleared to zero on power-up. All register bits may be read back as written except STAT[1] (Bit 63).
Table 3: Register Map
ADDRESS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
STAT[1]
STAT[0]
XLVTEN
CMOS
XCT[3]
XCT[2]
XCT[1]
XCT[0]
(Bit 63)
(Bit 62)
(Bit 61)
(Bit 60)
(Bit 59)
(Bit 58)
(Bit 57)
(Bit 56)
0 = Fine Tune
Inactive
0 = PECL
1 = Fine Tune
Active
1 = CMOS, Lock
Status
00 = Crystal Loop – Lock Status
BYTE 7
01 = Crystal Loop – Out of Range
10 = Main Loop – Phase Status
11 = Feedback Divider Output
BYTE 6
XLPDEN
XLSWAP
XLCP[1]
XLCP[0]
XLROM[2]
XLROM[1]
XLROM[0]
GBL
(Bit 55)
(Bit 54)
(Bit 53)
(Bit 52)
(Bit 51)
(Bit 50)
(Bit 49)
(Bit 48)
0 = Crystal Loop
Operates
0 = Use with
External VCXO
1 = Crystal Loop
Powered Down
1 = Use with
Internal VCXO
OUTMUX[1]
OUTMUX[0]
OSCTYPE
VCOSPD
LFTC
EXTLF
MLCP[1]
(Bit 47)
(Bit 46)
(Bit 45)
(Bit 44)
(Bit 43)
(Bit 42)
(Bit 41)
0 = Low Phase
Jitter Oscillator
0 = High Speed
Range
0 = Short Time
Constant
0 = Internal Loop
Filter
1 = FS6031
Oscillator
1 = Low Speed
Range
1 = Long Time
Constant
1 = External Loop
Filter
00 = VCO Output
BYTE 5
VCXO Coarse Tune
See Table 11
01 = Reference Divider Output
10 = Phase Detector Input
11 = VCXO Output
00 = 1.5µA
01 = 5µA
0 = No Clock
Phase Adjust
Crystal Loop Control
See Table 10
10 = 8µA
1 = Clock Phase
Delay
11 = 24µA
MLCP[0]
(Bit 40)
00 = 1.5µA
01 = 5µA
10 = 8µA
11 = 24µA
FBKDSRC[1]
FBKDSRC[0]
FBKDIV[13]
FBKDIV[12]
FBKDIV[11]
FBKDIV[10]
FBKDIV[9]
FBKDIV[8]
(Bit 39)
(Bit 38)
(Bit 37)
(Bit 36)
(Bit 35)
(Bit 34)
(Bit 33)
(Bit 32)
8192
4096
2048
1024
512
256
00 = Post Divider Output
BYTE 4
01 = FBK Pin
10 = Post Divider Input
M Counter
11 = FBK Pin
BYTE 3
FBKDIV[7]
FBKDIV[6]
FBKDIV[5]
FBKDIV[4]
FBKDIV[3]
FBKDIV[2]
FBKDIV[1]
FBKDIV[0]
(Bit 31)
(Bit 30)
(Bit 29)
(Bit 28)
(Bit 27)
(Bit 26)
(Bit 25)
(Bit 24)
128
64
32
16
8
4
2
1
M Counter
BYTE 2
BYTE 1
BYTE 0
Reserved (0)
A Counter – See Table 2
POST3[1]
POST3[1]
POST2[1]
POST2[0]
POST1[1]
POST1[0]
(Bit 21)
(Bit 20)
(Bit 19)
(Bit 18)
(Bit 17)
(Bit 16)
Reserved (0)
00 = Divide by 1
00 = Divide by 1
00 = Divide by 1
01 = Divide by 3
01 = Divide by 3
01 = Divide by 2
10 = Divide by 5
10 = Divide by 5
10 = Divide by 4
11 = Divide by 4
11 = Divide by 4
11 = Divide by 8
PDFBK
PDREF
SHUT
REFDSRC
REFDIV[11]
REFDIV[10]
REFDIV[9]
REFDIV[8]
(Bit 15)
(Bit 14)
(Bit 13)
(Bit 12)
(Bit 11)
(Bit 10)
(Bit 9)
(Bit 8)
0 = Feedback
Divider
0 = Reference
Divider
0 = Main Loop
Operates
0 = VCXO
2048
1024
512
256
1 = FBK Pin
1 = REF Pin
1 = Main Loop
Powered Down
1 = Ref Pin
REFDIV[7]
REFDIV[6]
REFDIV[5]
REFDIV[4]
REFDIV[3]
REFDIV[2]
REFDIV[1]
REFDIV[0]
(Bit 7)
(Bit 6)
(Bit 5)
(Bit 4)
(Bit 3)
(Bit 2)
(Bit 1)
(Bit 0)
128
64
32
16
8
4
2
1
12
FS6131-01
Programmable Line Lock Clock Generator IC
Table 4: Device Configuration Bits
NAME
Table 5: LOCK/IPRG Pin Configuration Bits
DESCRIPTION
NAME
DESCRIPTION
REFerence Divider SouRCe
REFDSRC
(Bit 12)
Bit = 0
Crystal Oscillator (VCXO)
Bit = 1
REF pin
crystal loop lock STATus mode /
main loop phase align STATus mode
(see also Table 6)
main loop SHUT down select
SHUT
(Bit 13)
Bit = 0
Disabled (main loop operates)
Bit = 1
Enabled (main loop shuts down)
STAT[1:0]
(Bits 63-62)
Phase Detector REFerence source
PDREF
(Bit 14)
Bit = 0
Reference Divider
Bit = 1
REF pin
Bit 63 = 0
Bit 62 = 0
Crystal Loop Lock status:
Locked or Unlocked
Bit 63 = 0
Bit 62 = 1
Crystal Loop Lock status:
Out of Range High or Low
Bit 63 = 1
Bit 62 = 0
Main Loop Phase Align status
Bit 63 = 1
Bit 62 = 1
Feedback Divider output
Phase Detector FeedBacK source
PDFBK
(Bit 15)
Bit = 0
Feedback Divider
Bit = 1
FBK pin
Table 6: Lock Status
FeedBacK Divider SouRCe
FBKDSRC[1:0]
(Bits 39-38)
Bit 39 = 0
Bit 38 = 0
Post Divider Output
Bit 39 = 0
Bit 38 = 1
FBK pin
Bit 39 = 1
Bit 38 = 0
VCO Output (Post Divider Input)
Bit 39 = 1
Bit 38 = 1
FBK pin
CMOS
STAT
[1]
STAT
[0]
1
0
0
1
0
LOCK /
IPRG PIN
STAT[1]
READ
STATUS
1
1
Locked
0
0
Unlocked
0
0
Out-ofRange: Low
1
1
Out-ofRange: High
1
EXTernal Loop Filter select
EXTLF
(Bit 42)
Bit = 0
Internal Loop Filter
Bit = 1
EXTLF pin
Table 7: Main Loop Tuning Bits
OSCillator TYPe
OSCTYPE
(Bit 45)
Bit = 0
Low Phase Jitter Oscillator
Bit = 1
FS6031 Compatible Oscillator
NAME
VCO SPeeD range select (see Table 16)
VCOSPD
(Bit 44)
OUTput MUltipleXer select
OUTMUX[1:0]
(Bits 47-46)
Bit 47 = 0
Bit 46 = 0
Main Loop PLL (VCO Output)
Bit 47 = 0
Bit 46 = 1
Reference Divider Output
Bit 47 = 1
Bit 46 = 0
Phase Detector Input
Bit 47 = 1
Bit 46 = 1
VCXO Output
MLCP[1:0]
(Bits 41-40)
Bit = 0
No Clock Phase Adjust
Bit = 1
Clock Phase Delay
High Speed Range
Low Speed Range
Bit = 0
PECL Output
(positive-ECL output drive)
Bit = 1
CMOS Output /
Lock Status Indicator
Bit 41 = 0
Bit 40 = 0
Current = 1.5µA
Bit 41 = 0
Bit 40 = 1
Current = 5µA
Bit 41 = 1
Bit 40 = 0
Current = 8µA
Bit 41 = 1
Bit 40 = 1
Current = 24µA
Loop Filter Time Constant (internal)
LFTC
(Bit 43)
CLKP/CLKN output mode
CMOS
(Bit 60)
Bit = 0
Bit = 1
Main Loop Charge Pump current
clock GobBLer control
GBL
(Bit 48)
DESCRIPTION
13
Bit = 0
Short Time Constant: 13.5µs
Bit = 1
Long Time Constant: 135µs
FS6131-01
Programmable Line Lock Clock Generator IC
Table 8: Divider Control Bits
NAME
REFDIV[11:0]
(Bits 11-0)
Table 9: Crystal Loop Tuning Bits
DESCRIPTION
NAME
DESCRIPTION
Crystal Loop Charge Pump current
REFerence DIVider (NR)
FeedBacK DIVider (NF)
FBKDIV[13:0]
(Bits 37-24)
FBKDIV[2:0]
A-Counter Value
FBKDIV[13:3]
M-Counter Value
XLCP[1:0]
(Bits 53-52)
POST Divider #1 (NP1)
POST1[1:0]
(Bits 17-16)
Bit 17 = 0
Bit 16 = 0
Divide by 1
Bit 17 = 0
Bit 16 = 1
Divide by 2
Bit 17 = 1
Bit 16 = 0
Divide by 4
Bit 17 = 1
Bit 16 = 1
Divide by 8
XLROM[2:0]
(Bits 51-49)
POST2[1:0]
(Bits 19-18)
Divide by 1
Bit 19 = 0
Bit 18 = 1
Divide by 3
Bit 19 = 1
Bit 18 = 0
Divide by 5
Bit 19 = 1
Bit 18 = 1
Divide by 4
Current = 1.5µA
Bit 53 = 0
Bit 52 = 1
Current = 5µA
Bit 53 = 1
Bit 52 = 0
Current = 8µA
Bit 53 = 1
Bit 52 = 1
Current = 24µA
Crystal Loop Divider ROM select and Crystal
Oscillator Power-Down (see Table 10)
Crystal Loop Voltage fine Tune ENable
XLVTEN
(Bit 61)
POST Divider #2 (NP2)
Bit 19 = 0
Bit 18 = 0
Bit 53 = 0
Bit 52 = 0
Bit = 0
Disabled (fine tune is inactive)
Bit = 1
Enabled (fine tune is active)
Crystal Loop SWAP polarity
Use with an external VCXO that
increases in frequency in response to an increasing voltage
at the XTUNE pin.
Bit = 0
XLSWAP
(Bit 54)
Use with a VCXO that increases
in frequency in response to a
decreasing voltage at the XTUNE
pin.
Bit = 1
Use this setting for Internal
VCXO
POST Divider #3 (NP3)
POST3[1:0]
(Bits 21-20)
Reserved (0)
(Bits 23-22)
Bit 21 = 0
Bit 20 = 0
Divide by 1
Bit 21 = 0
Bit 20 = 1
Divide by 3
Bit 21 = 1
Bit 20 = 0
Divide by 5
Bit 21 = 1
Bit 20 = 1
Divide by 4
Crystal Loop Power Down Enable
XLPDEN
(Bit 55)
XCT[3:0]
(Bits 59-56)
Set these reserved bits to 0
Bit = 0
Disabled (crystal loop operates)
Bit = 1
Enabled
(crystal loop is powered down)
Crystal Coarse Tune (see Table 11)
Table 10: Crystal Loop Control ROM
14
XLROM
[2]
XLROM
[1]
XLROM
[0]
VCXO
DIVIDER
CRYSTAL
FREQUENCY (MHz)
0
0
0
1
-
0
0
1
3072
24.576
0
1
0
3156
25.248
0
1
1
2430
19.44
1
0
0
2500
20.00
1
0
1
4000
32.00
1
1
0
3375
27.00
1
1
1
Crystal Oscillator Power-Down
FS6131-01
Programmable Line Lock Clock Generator IC
6.1
VCXO Coarse Tune
Table 11: VCXO Coarse Tuning Capacitance
The VCXO may be coarse tuned by a programmable adjustment of the crystal load capacitance via XCT[3:0].
The actual amount of frequency warping caused by the
tuning capacitance will depend on the crystal used. The
VCXO tuning capacitance includes an external 6pF load
capacitance (12pF from the XIN pin to ground and 12pF
from the XOUT pin to ground). The fine tuning capability
of the VCXO can be enabled by setting the XLVTEN bit
to a logic-one, or disabled by setting the bit to a logiczero.
15
XCT[3]
XCT[2]
XCT[1]
XCT[0]
VCXO TUNING
CAPACITANCE (pF)
0
0
0
0
10.00
0
0
0
1
10.84
0
0
1
0
11.69
0
0
1
1
12.53
0
1
0
0
13.38
0
1
0
1
14.22
0
1
1
0
15.06
0
1
1
1
15.91
1
0
0
0
16.75
1
0
0
1
17.59
1
0
1
0
18.43
1
0
1
1
19.28
1
1
0
0
20.13
1
1
0
1
20.97
1
1
1
0
21.81
1
1
1
1
22.66
FS6131-01
Programmable Line Lock Clock Generator IC
7.0
Electrical Specifications
Table 12: Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at
these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance,
functionality, and reliability.
PARAMETER
SYMBOL
MIN.
Supply Voltage, dc (VSS = ground)
MAX.
UNITS
VDD
VSS-0.5
7
V
Input Voltage, dc
VI
VSS-0.5
VDD+0.5
V
Output Voltage, dc
VO
VSS-0.5
VDD+0.5
V
Input Clamp Current, dc (VI < 0 or VI > VDD)
IIK
-50
50
mA
Output Clamp Current, dc (VI < 0 or VI > VDD)
IOK
-50
50
mA
Storage Temperature Range (non-condensing)
TS
-65
150
°C
Ambient Temperature Range, Under Bias
TA
-55
125
°C
Junction Temperature
TJ
150
°C
260
°C
2
kV
Lead Temperature (soldering, 10s)
Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7)
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge.
Table 13: Operating Conditions
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
5V ± 10%
MIN.
TYP.
MAX.
4.5
5
5.5
V
70
°C
28
MHz
Supply Voltage
VDD
Ambient Operating Temperature Range
TA
0
Crystal Resonator Frequency
fXIN
19.44
27
UNITS
Crystal Resonator Load Capacitance
CXL
Parallel resonant, AT cut
18
pF
Crystal Resonator Motional Capacitance
CXM
Parallel resonant, AT cut
25
fF
Serial Data Transfer Rate
Standard mode
PECL Mode Programming Current
(LOCK/IPRG Pin High-Level Input Current)
IIH
Output Driver Load Capacitance
CL
PECL Mode
16
10
100
400
kb/s
15
mA
15
pF
FS6131-01
Programmable Line Lock Clock Generator IC
Table 14: DC Electrical Specifications
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
Overall
Supply Current, Dynamic,
(with Loaded Outputs)
IDD
fCLK = 66MHz; CMOS Mode, VDD = 5.5V
100
mA
Supply Current, Static
IDDL
SHUT = 1, XLROM[2:0] = 7, XLPDEN = 1
VDD = 5.5V
12
mA
High-Level Input Voltage
VIH
Outputs off
3.5
VDD+0.3
Low-Level Input Voltage
VIL
Outputs off
VSS-0.3
1.5
Hysteresis Voltage *
Vhys
Outputs off
Serial Communication I/O (SDA, SCL)
Input Leakage Current
2
II
Low-Level Output Sink Current (SDA)
IOL
Tristate Output Current
IZ
-1
VOL = 0.4V
20
V
V
V
1
32
µA
mA
-10
10
µA
Address Select Input (ADDR)
High-Level Input Voltage
VIH
2.4
VDD+0.3
V
Low-Level Input Voltage
VIL
VSS-0.3
0.8
V
High-Level Input Current (pull-down)
IIH
30
µA
Low-Level Input Current
IIL
-2
2
µA
VIH
3.5
VDD+0.3
V
Low-Level Input Voltage
VIL
VSS-0.3
1.5
Hysteresis Voltage
Vhys
500
II
-1
VIH = VDD = 5.5V
5
16
Reference Frequency Input (REF, FBK)
High-Level Input Voltage
Input Leakage Current
V
mV
1
µA
1
µA
Loop Filter Input (EXTLF)
Input Leakage Current
High-Level Output Source Current
Low-Level Output Sink Current
II
IOH
IOL
EXTLF = 0
-1
VO = 0.8V; EXTLF =1, MLCP[1:0] = 0
-1.5
VO = 0.8V; EXTLF =1, MLCP[1:0] = 1
-5
VO = 0.8V; EXTLF =1, MLCP[1:0] = 2
-8
VO = 0.8V; EXTLF =1, MLCP[1:0] = 3
-24
VO = 4.2V; EXTLF =1, MLCP[1:0] = 0
1.5
VO = 4.2V; EXTLF =1, MLCP[1:0] = 1
5
VO = 4.2V; EXTLF =1, MLCP[1:0] = 2
8
VO = 4.2V; EXTLF =1, MLCP[1:0] = 3
25
µA
µA
Crystal Oscillator Input (XIN)
Threshold Bias Voltage
VTH
1.5
High-Level Input Current
IIH
Outputs off; VIH = 5V
10
Low-Level Input Current
IIL
Outputs off; VIL = 0V
-10
Crystal Loading Capacitance *
CL(xtal)
As seen by an external crystal connected
to XIN and XOUT; VCXO tuning disabled
Input Loading Capacitance *
CL(XIN)
As seen by an external clock driver on
XOUT; XIN unconnected; VCXO disabled
17
2.2
3.5
V
24
30
mA
-19
-30
mA
10
pF
20
pF
FS6131-01
Programmable Line Lock Clock Generator IC
Table
15: DC Electrical Specifications, continued
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current flows out of the device.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
MIN.
TYP.
MAX.
UNITS
Crystal Oscillator Output (XOUT)
High-Level Output Source Current
IOH
VO = 0V, float XIN
-20
-30
-50
mA
Low-Level Output Sink Current
IOL
VO = 5V, float XIN
-20
-40
-50
mA
High-Level Input Voltage
VIH
Lock Status: Out of Range HIGH
3.2
VDD+0.3
V
Low-Level Input Voltage
VIL
Lock Status: Out of Range LOW
VSS-0.3
0.3
V
Hysteresis Voltage
Vhys
1
µA
VCXO Tuning I/O (XTUNE)
Input Leakage Current
High-Level Output Source Current
Low-Level Output Sink Current
II
IOH
IOL
1.0
XLPDEN = 0
V
-1
VO = 0.8V; XLCP[1:0] = 0
-1.5
VO = 0.8V; XLCP[1:0] = 1
-5
VO = 0.8V; XLCP[1:0] = 2
-8
VO = 0.8V; XLCP[1:0] = 3
-24
VO = 4.2V; XLCP[1:0] = 0
1.5
VO = 4.2V; XLCP[1:0] = 1
5
VO = 4.2V; XLCP[1:0] = 2
8
VO = 4.2V; XLCP[1:0] = 3
25
µA
µA
Lock Indicator / PECL Current Program I/O (LOCK/IPRG)
Low-Level Input Current
IIL
PECL Mode
-1
High-Level Output Source Current
IOH
CMOS Mode; VO = 2.4V
-25
5
Low-Level Output Sink Current
1
µA
-38
mA
9
mA
IOL
CMOS Mode; VO = 0.4V
zOH
VO = 0.5VDD; output driving high
66
zOL
VO = 0.5VDD; output driving low
76
Short Circuit Source Current *
ISCH
VO = 0V; shorted for 30s, max.
-47
mA
Short Circuit Sink Current *
ISCL
VO = 5V; shorted for 30s, max.
47
mA
High-Level Output Source Current
IOH
VO = 2.4V
-45
-68
mA
Low-Level Output Sink Current
IOL
VO = 0.4V
15
20
mA
zOH
VO = 0.5VDD; output driving high
28
zOL
VO = 0.5VDD; output driving low
33
Short Circuit Source Current *
ISCH
VO = 0V; shorted for 30s, max.
-100
mA
Short Circuit Sink Current *
ISCL
VO = 5V; shorted for 30s, max.
100
mA
Output Impedance *
Ω
Clock Outputs, CMOS Mode (CLKN, CLKP)
Output Impedance *
Ω
Clock Outputs, PECL Mode (CLKN, CLKP)
IPRG Current to Output Current Ratio
1:4
Low-Level Output Sink Current
IOL
Tristate Output Current
IZ
IPRG input current = 15mA
60
-10
18
mA
10
µA
FS6131-01
Programmable Line Lock Clock Generator IC
Table 16: AC Timing Specifications
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
CLOCK
(MHz)
MIN.
TYP.
MAX.
UNITS
Overall
Output Frequency *
fO(max)
CMOS Outputs
130
PECL Outputs
230
MHz
Low Phase Jitter Oscillator (OSCTYPE = 0)
VCO Frequency *
fVCO
VCOSPD = 0
40
160
VCOSPD = 1
40
100
VCOSPD = 0
40
230
VCOSPD = 1
40
140
FS6031 Compatible Oscillator (OSCTYPE = 1)
MHz
Low Phase Jitter Oscillator (OSCTYPE = 0)
VCO Gain *
AVCO
VCOSPD = 0
125
VCOSPD = 1
75
VCOSPD = 0
130
VCOSPD = 1
Loop Filter Time Constant *
MHz/V
FS6031 Compatible Oscillator (OSCTYPE = 1)
78
LFTC = 0
13.5
LFTC = 1
135
µs
Rise Time *
tr
CMOS Outputs, VO = 0.5V to 4.5V; CL = 15pF
1.1
ns
Fall Time *
tf
CMOS Outputs, VO = 4.5V to 0.5V; CL = 15pF
0.8
ns
Lock Time (Main Loop) *
Disable Time *
Frequency Synthesis
200
µs
Line Locked Modes (8kHz reference)
10
ms
From falling edge of SCL for the last data bit
(SHUT = 1 to 0) to output locked
10
µs
Divider Modulus
Feedback Divider
NF
FBKDIV[13:0] (See also Table 2)
8
16383
Reference Divider
NR
REFDIV[11:0]
1
4095
NP1
POST1[1:0] (See also Table 8)
1
8
NP2
POST2[1:0] (See also Table 8)
1
5
NP3
POST3[1:0] (See also Table 8)
1
5
Post Divider
19
FS6131-01
Programmable Line Lock Clock Generator IC
Table 17: AC Timing Specifications, continued
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data at TA = 27°C and are not production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
CLOCK
(MHz)
MIN.
Ratio of pulse width (as measured from rising edge to next falling
edge at 2.5V) to one clock period
100
47
TYP.
MAX.
UNITS
54
%
Clock Output (CLKP, CLKN)
Duty Cycle *
Jitter, Long Term (σy(τ)) *
Jitter, Period (peak-peak) *
tj(LT)
tj(∆P)
Rising edges 50ms apart at 2.5V, relative to an ideal clock,
CL=15pF, fREF=8kHz, NR=1, NF=193, NPx=64, CLF=0.054µF,
RLF=15.7kΩ, CLP=1800pF, OSCTYPE=0, MLCP=3, XLROM=7
1.544
270
Rising edges 50ms apart at 2.5V, relative to an ideal clock,
CL=15pF, fREF=15kHz, NR=1, NF=800, NPx=10, CLF=0.0246µF,
RLF=15.7kΩ, CLP=820pF, OSCTYPE=0, MLCP=3, XLROM=7
12.00
160
On rising edges 5ms apart at 2.5V relative to an ideal clock,
CL=15pF, fREF=31.5kHz, NR=1, NF=799, NPx=4, CLF=0.015µF,
RLF=15.7kΩ, CLP=470pF, OSCTYPE=0, MLCP=3, XLROM=7
25.175
100
On rising edges 500µs apart at 2.5V relative to an ideal clock,
CL=15pF, CMOS mode, fXIN=27MHz, NF=200, NR=27, NPx=2
100
30
On rising edges 500µs apart at 2.5V relative to an ideal clock,
CL=15pF, PECL mode, fXIN=27MHz, NF=200, NR=27, NPx=1
200
30
From rising edge to next rising edge at 2.5V, CL=15pF,
fREF=8kHz, NR=1, NF=193, NPx=64, CLF=0.054µF, RLF=15.7kΩ,
CLP=1800pF, OSCTYPE=0, MLCP=3, XLROM=7
1.544
140
From rising edge to next rising edge at 2.5V, CL=15pF,
fREF=15kHz, NR=1, NF=800, NPx=10, CLF=0.0246µF, RLF=15.7kΩ,
CLP=820pF, OSCTYPE=0, MLCP=3, XLROM=7
12.00
130
From rising edge to next rising edge at 2.5V, CL=15pF,
fREF=31.5kHz, NR=1, NF=799, NPx=4, CLF=0.015µF, RLF=15.7kΩ,
CLP=470pF, OSCTYPE=0, MLCP=3, XLROM=7
25.175
105
From rising edge to next rising edge at 2.5V, CL=15pF,
CMOS mode, fXIN=27MHz, NF=200, NR=27, NPx=2
100
340
From rising edge to next rising edge at 2.5V, CL=15pF,
PECL mode, fXIN=27MHz, NF=200, NR=27, NPx=1
200
270
20
ps
ps
FS6131-01
Programmable Line Lock Clock Generator IC
Table 18: Serial Interface Timing Specifications
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
SCL
STANDARD MODE
MIN.
MAX.
0
400
UNITS
Clock frequency
fSCL
Bus free time between STOP and START
tBUF
4.7
kHz
µs
Set up time, START (repeated)
tsu:STA
4.7
µs
Hold time, START
thd:STA
4.0
µs
Set up time, data input
tsu:DAT
SDA
250
ns
Hold time, data input
thd:DAT
SDA
0
µs
Output data valid from clock
tAA
Minimum delay to bridge undefined region of the falling
edge of SCL to avoid unintended START or STOP
Rise time, data and clock
tR
SDA, SCL
Fall time, data and clock
tF
SDA, SCL
High time, clock
tHI
SCL
tLO
SCL
Low time, clock
Set up time, STOP
tsu:STO
3.5
µs
1000
ns
300
ns
4.0
µs
4.7
µs
4.0
µs
Figure 17: Bus Timing Data
~
~
SCL
~
~
thd:STA
tsu:STA
tsu:STO
SDA
~
~
ADDRESS OR
DATA VALID
START
DATA CAN
CHANGE
STOP
Figure 18: Data Transfer Sequence
tHI
SCL
tR
~
~
tF
tLO
tsu:STA
thd:STA
tAA
tAA
SDA
OUT
21
~
~
SDA
IN
tsu:DAT
tsu:STO
~
~
thd:DAT
tBUF
FS6131-01
Programmable Line Lock Clock Generator IC
Table 19: CLKP, CLKN Clock Outputs (CMOS Mode)
Low Drive Current (mA)
MIN.
TYP.
MAX.
Voltage
(V)
High Drive Current (mA)
200
MIN.
TYP.
MAX.
0
0
0
0
0
-58
-98
-153
0.2
7
11
15
0.5
-56
-96
-150
0.5
18
27
37
1
-55
-94
-148
0.7
24
36
50
1.5
-53
-91
-142
1
32
49
69
2
-49
-85
-135
1.2
37
56
80
2.5
-43
-77
-124
1.5
43
66
95
2.7
-40
-73
-119
1.7
46
72
103
3
-35
-67
-111
2
51
79
115
3.2
-31
-62
-105
2.2
53
83
122
3.5
-25
-54
-95
2.5
55
88
130
3.7
-21
-48
-87
2.7
56
91
135
4
-14
-39
-75
3
57
93
140
4.2
-8
-32
-67
3.5
58
95
146
4.5
0
-21
-53
4
59
97
149
4.7
-13
-44
4.5
59
99
152
5
0
-28
100
155
5.2
-17
158
5.5
0
5
5.5
150
100
Output Current (mA)
Voltage
(V)
50
0
-
0.5 1.0 1.5 2.0 2.5
3.0 3.5 4.0 4.5
5.0 5.5
-50
-100
-150
MIN
TYP
-200
Output Voltage (V)
MAX
The data in this table represents nominal characterization data only.
Table 20: LOCK/IPRG Clock Output (CMOS Mode)
Low Drive Current (mA)
MIN.
TYP.
MAX.
Voltage
(V)
High Drive Current (mA)
80
MIN.
TYP.
MAX.
0
0
0
0
0
-35
-46
-61
0.2
4
4
4
0.5
-34
-45
-60
0.5
9
10
11
1
-33
-43
-57
0.7
12
13
15
1.5
-31
-41
-54
1
16
18
21
2
-28
-37
-50
1.2
19
21
25
2.5
-24
-33
-45
1.5
23
26
30
2.7
-23
-31
-42
1.7
25
29
33
3
-20
-28
-39
2
28
32
38
3.2
-17
-26
-36
2.2
29
35
41
3.5
-14
-22
-32
2.5
32
38
45
3.7
-11
-19
-29
2.7
33
39
48
4
-7
-15
-25
3
34
42
51
4.2
-4
-12
-22
3.5
35
45
56
4.5
0
-8
-17
4
35
46
60
4.7
-5
-14
4.5
36
46
62
5
0
-9
47
63
5.2
-5
63
5.5
0
5
5.5
22
60
40
Output Current (mA)
Voltage
(V)
20
0
-
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
-20
-40
-60
MIN
TYP
-80
Output Voltage (V)
The data in this table represents nominal characterization data only.
MAX
FS6131-01
Programmable Line Lock Clock Generator IC
8.0
Package Information
Table 21: 16-pin SOIC (0.150") Package Dimensions
DIMENSIONS
INCHES
MIN.
MAX.
16
MILLIMETERS
MIN.
MAX.
A
0.061
0.068
1.55
1.73
A1
0.004
0.0098
0.102
0.249
A2
0.055
0.061
1.40
1.55
B
0.013
0.019
0.33
0.49
C
0.0075
0.0098
0.191
0.249
D
0.386
0.393
9.80
9.98
E
0.150
0.157
3.81
3.99
R
e
0.050 BSC
E
1
ALL RADII:
0.005" TO 0.01"
B
0.230
0.244
5.84
6.20
h
0.010
0.016
0.25
0.41
L
0.016
0.035
0.41
0.89
Θ
0°
8°
0°
8°
h x 45°
7° typ.
e
1.27 BSC
H
H
AMERICAN MICROSYSTEMS, INC.
A2
D
A
A1
BASE PLANE
C
θ
L
SEATING PLANE
Table 22: 16-pin SOIC (0.150") Package Characteristics
PARAMETER
Thermal Impedance, Junction to Free-Air
Lead Inductance, Self
SYMBOL
ΘJA
L11
CONDITIONS/DESCRIPTION
TYP.
UNITS
Air flow = 0 ft./min.
108
°C/W
Corner lead
4.0
Center lead
3.0
nH
Lead Inductance, Mutual
L12
Any lead to any adjacent lead
0.4
nH
Lead Capacitance, Bulk
C11
Any lead to VSS
0.5
pF
23
FS6131-01
Programmable Line Lock Clock Generator IC
9.0
Ordering Information
9.1
Device Ordering Codes
ORDERING CODE
DEVICE
NUMBER
FONT
PACKAGE TYPE
OPERATING
TEMPERATURE RANGE
SHIPPING
CONFIGURATION
11274-001
FS6131
-01
16-pin (0.150”) SOIC
(Small Outline Package)
0°C to 70°C (Commercial)
Tape-and-Reel
11274-011
FS6131
-01
16-pin (0.150”) SOIC
(Small Outline Package)
0°C to 70°C (Commercial)
Tubes
11274-901
FS6131
-01i
16-pin (0.150”) SOIC
(Small Outline Package)
-40°C to 85°C (Industrial)
Tape-and-Reel
11274-911
FS6131
-01i
16-pin (0.150”) SOIC
(Small Outline Package)
-40°C to 85°C (Industrial)
Tubes
9.2
Demo Kit Ordering Codes
ORDERING CODE
KIT FOR DEVICE NUMBER:
11274-201
DESCRIPTION
Kit includes:
•
Populated board with example device
•
Interface Cable
•
Programming Assistance PC Software
FS6131-01
2
Purchase of I C components of American Microsystems, Inc., or one of its sublicensed Associated Compa2
2
nies conveys a license under Philips I C Patent Rights to use these components in an I C system, provided
2
that the system conforms to the I C Standard Specification as defined by Philips.
Copyright © 1998, 1999 American Microsystems, Inc.
Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale
only. AMI makes no warranty, express, statutory implied or by description, regarding the information set forth herein or
regarding the freedom of the described devices from patent infringement. AMI makes no warranty of merchantability or
fitness for any purposes. AMI reserves the right to discontinue production and change specifications and prices at any
time and without notice. AMI’s products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMI for
such applications.
American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796,
WWW Address: http://www.amis.com E-mail: tgp@amis.com
24
FS6131-01
Programmable Line Lock Clock Generator IC
10.0
Demonstration Board and Software
A simple demonstration board and Windows 3.1x/95/98-based software is available from American Microsystems that
illustrates the capabilities of the FS6131. The software can operate under Windows NT but cannot communicate with
the board.
The board schematic is shown below. Components listed with an asterisk (*) are not required in an actual application,
and are used here to preserve signal integrity with the cabling associated with the board. A cabled interface between a
computer parallel port (DB25 connector) and the board (J1) is provided. Components shown in dashed lines are optional, depending on the application.
Contact your local sales representative for more information.
Figure 19: Board Schematic
J1*
1
R1* 100
+5V
SCL
R2* 100
2
SDA
R5
10
R3* 100
3
ADDR
4
+5V
C2
2.2µF
5
+5V
C4
0.1µF
R12
6
1
+5V
CLKN
SCL
R14
R6 47
16
CLKN
+5V
2
GND
3
CLKP
SDA
ADDR
VDD
VSS
FBK
15
R7 47
CLKP
14
R13
C8
12pF
C9
12pF
4
5
+5V
Y1
27MHz
6
7
RP1
1k
8
R16
FS6131
XIN
REF
XOUT
VSS
XTUNE
EXTLF
VDD
LOCK/
IPRG
R15
12
11
FBK
REF
10
9
R9
R18
+5V
C10
C11
13
C7
C1
2.2µF
C3
0.1µF
R8
R17
R4
10
C6
LOCK
AMERICAN
MICROSYSTEMS, INC.
FS6131 DEMO BOARD
25
R19
FS6131-01
Programmable Line Lock Clock Generator IC
10.1
Demo Kit Contents
•
Demonstration board
•
Interface cable (DB25 to 6-pin connector)
•
Data sheet
•
Programming software
10.2
•
•
3. Connect a +5 Volt power supply to the board: RED =
+5V, BLACK = ground.
4. Remove all software keys from the computer parallel
port. Connect the supplied interface cable to the parallel port (DB25 connector) and to the demo board (6pin connector). Make sure the cable is facing away
from the board. Pin 1 is the red wire per Figure 23.
5. Connect the clock outputs to the target application
board with a twisted-pair cable.
Requirements
PC running MS Windows 3.1x or 95/98 with an accessible parallel (LPT1) port. Software also runs on
Windows NT in a calculation mode only.
10.4
Run the fs6131.exe program. Note that the
parallel port can not be accessed if your machine
is running Windows NT. A warning message will
appear stating: “This version of the demo program cannot
communicate with the FS6131 hardware when running
on a Windows NT operating system. Do you want to
continue anyway, using just the calculation features of
this program?” Clicking OK starts the program for calculation only.
The opening screen is shown in Figure 20.
2.0MB available space on hard drive C:
10.3
Demo Program Operation
Board Setup and Software
Installation Instructions
1. Run the self-expanding exe file to unzip the compressed demo files to a directory of your choice.
2. Run the setup.exe file to install the programming
software.
Figure 20: Opening Screen
26
FS6131-01
Programmable Line Lock Clock Generator IC
The best PLL performance is obtained by running the
VCO at as high a speed as possible. The last three solutions show a VCO speed of 200MHz. Furthermore, good
PLL performance is obtained with the smallest dividers
possible, which means solution #4 should provide the
best results.
10.4.1
Device Mode
The Device Mode block presets the demo program to
program the FS6131 either as a frequency synthesizer (a
stand alone clock generator) or as a line-locked or genlock clock generator.
Frequency Synthesis: For use as a stand alone clock
generator. Note that the Reference Source is the on-chip
crystal oscillator, the expected crystal frequency is
27MHz, and the Voltage Tune in the Crystal Oscillator
(i.e. the VCXO) is disabled. The default output frequency
(CLK freq.) requested is 100MHz, with a maximum error
of 10ppm, or about 100Hz. The Output Stage defaults to
CMOS mode.
Line-Locked/Genlock: For use in a line lock or genlock
application. Note that the Reference Source is the REF
Pin, and that the expected reference frequency is 8kHz.
The default output frequency requested is a 100x multiple
of the reference frequency.
Figure 21: Frequency Synthesizer Screen
10.4.2
Example: Frequency Synthesizer Mode
By default the demo program assumes the FS6131 is
configured as a stand alone clock generator. Note that
the Reference Source defaults to the on-chip crystal oscillator, the expected crystal frequency is 27MHz, and the
Voltage Tune in the Crystal Oscillator block (i.e. the
VCXO) is disabled. The default output frequency (CLK
freq.) requested is 100MHz, with a maximum error of
10ppm, or about 100Hz. The Output Stage defaults to
CMOS mode. The Loop Filter block is set to internal,
and the Check Loop Stability switch is on.
As an exercise, click on Calculate Solutions. The program takes into account all of the screen settings and
calculates all possible combinations of Reference, Feedback, and Post Divider values that will generate the output frequency (100MHz) from the input frequency
(27MHz) within the desired tolerance (10ppm).
A box will momentarily appear: “Calculating Solutions:
Press cancel to stop with the solutions calculated so far.”
A number in the box will increment for every unique solution that is found. This example will create six unique solutions, which are then displayed in a window in the lower
right portion of the program screen.
Clicking on Solution #4 highlights the row, and clicking on
Disp/Save Register Values provides a window with the
final values of key settings. A click on OK then displays a
second window containing register information per the
Register Map. If the solutions are to be saved to a file,
two formats are available: a text format for viewing, and a
data format for loading into the FS6131.
Clicking on Load Solution into Hardware (if enabled)
2
sends the information in an I C format to the FS6131 via
the parallel port. Note: This option is not available under
the Windows NT operating system.
If your operating system can support parallel port communication but the connection cable is not attached, an
error message is displayed: "The FS6131 Hardware was
not detected! "Make sure that it is connected to the LPT#
printer port and that it is properly connected to a +5Volt
power supply."
27
FS6131-01
Programmable Line Lock Clock Generator IC
10.4.3
Example: Line Locked Mode
Selecting the Line-Locked/Genlock option in the Device
Mode block changes the program default settings. The
Reference Source changes to the REF Pin input, and a
block appears to permit entry of the REF input frequency
in MHz. A Desired Multiple block allows entry of the reference frequency multiplying factor used to generate the
output frequency.
Exercise: Change the Ref Pin Frequency to 0.0315MHz,
and alter the Desired Multiple to 800. Change the Loop
Filter block to external, but leave the values for C1 and R
alone.
Click on Calculate Solutions. The program takes into
account all of the current screen settings and calculates
all possible combinations of Reference, Feedback, and
Post Divider values that will generate an output frequency
from the input frequency (31.5kHz) multiplied by the desired multiple of 800.
A box will appear: “No solutions were found! Do you want
to retry calculations with the Check Loop Stability option
turned off?” Choose Yes.
Another box will momentarily appear: “Calculating Solutions: Press cancel to stop with the solutions calculated
so far.” A number in the box will increment for every
unique solution that is found. This example will create
eight unique solutions, which are then displayed in a window in the lower right portion of the program screen.
For best results, try to keep the PostDiv value multiplied
by the FbkDiv value from getting larger than 5000 while
running the VCO as much above 70MHz as possible. If a
tradeoff must be made, it is better to run the VCO faster
and allow the divider values to get large. Solution #4 provides a PostDiv value of 800 and a FbkDiv value of 4 for
a combined value of 3200. The VCO is running at about
100MHz.
Click on Solution #4 to highlight the row, then click on
Suggest in the Loop Filter box to have the program
choose loop filter values. Suggested values for an external loop filter are 4700pF and 47kΩ.
Now reselect the Check Loop Stability box to turn this
feature on. Clicking on Calculate Solutions regenerates
the same solutions provided earlier, only this time the
new Loop Filter values were used.
Figure 22: Line-Locked Screen
Clicking on Solution #4 highlights the row, and clicking on
Disp/Save Register Values provides a window with the
final values of key settings. A click on OK then displays a
second window containing register information per the
Register Map. If the solutions are to be saved to a file,
two formats are available: a text format for viewing and a
data format for loading into the FS6131.
Clicking on Load Solution into Hardware (if enabled)
2
sends the information in an I C format to the FS6131 via
the parallel port. Note that this option is disabled for the
Windows NT operating system.
If your operating system can support parallel port communication but the connection cable is not attached, an
error message is displayed: "The FS6131 Hardware was
not detected! "Make sure that it is connected to the LPT#
printer port and that it is properly connected to a +5Volt
power supply."
Table 23: Cable Interface
Color
28
J1
DB25
Signal
Red
1
2, 13
SCL
White
2
3, 12
SDA
Green
3
8
ADDR
Blue
4
5
-
Brown
5
4
-
Black
6
25
GND
FS6131-01
Programmable Line Lock Clock Generator IC
Table 24: Sample Text Output
Figure 24: Board Silkscreen
AMI - FS6131 Solution Text File
Line-Locked / Genlock Mode
Desired Multiple = 800
Source = .0315MHz Reference Pin
External Loop Filter C1 = 47pF R = 4700Ohms
Crystal Oscillator Voltage Tune Disabled
Output Stage = CMOS
Reference Divider
Feedback Divider
Post Divider
Charge Pump (uA)
EXTLF
XLVTEN
XCT
CMOS
Register
Register
Register
Register
Register
Register
Register
Register
0
1
2
3
4
5
6
7
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
1
800
4
0
1
0
7
1
Figure 25: Board Traces - Component Side
1H (1)
40H (64)
2H (2)
20H (32)
3H (3)
24H (36)
0H (0)
17H (23)
Figure 23: Cable Connections
PIN
2
RED
3
WHT
8
GRN
5
BLU
4
BRN
13
BLK
12
25
PIN
1
Figure 26: Board Traces - Solder Side
2
3
4
5
6
J1
DB-25
29
FS6131-01
Programmable Line Lock Clock Generator IC
11.0
11.1.1
Example Calculation
In PECL mode, the output driver does not source current,
so the VIH value is determined by the ratios of the terminating resistors using the equation
Applications Information
A signal reflection will occur at any point on a PC-board
trace where impedance mismatches exist. Reflections
cause several undesirable effects in high-speed applications, such as an increase in clock jitter and a rise in
electromagnetic emissions from the board. Using a properly designed series termination on each high-speed line
can alleviate these problems by eliminating signal reflections.
11.1
V NMH = VCC ×
V IH = VCC − V NMH .
The resistor ratio must also match the line impedance via
the equation
If a PECL interface is desired, the transmission line must
be terminated using a Thévenin, or dual, termination. The
output stage can only sink current in the PECL mode,
and the amount of sink current is set by a programming
resistor on the LOCK/IPRG pin. Source current is provided by the pull-up resistor that is part of the Thévenin
termination.
zL =
VCC
Rp1
CLKN
Ri
from
PLL
IPRG
{
VCC
LOAD
Rp2
ö
÷÷
ø
If the load’s VIH(min) = VCC – 0.6, choose a VNMH = 0.45V. If
the line impedance is 75Ω, then Rp1 is about 82Ω. Substituting into the equation for line impedance and solving
for Rp2 gives a value of 880Ω (choose 910Ω).
To solve for the load’s VIL, an output sink current must be
programmed via the IPRG pin. If the desired VIH = VCC –
1.6, choose VCC – 2.0 for some extra margin. A sink current of 25mA through the 82Ω resistor generates a 2.05V
drop. The sink current is programmed via the IPRG pin,
where the ratio of IPRG current to output sink current is
1:4. An IPRG programming resistor of 750Ω at VDD = 5V
generates 6.6mA, or about 27mA output sink current.
Rn1
zL
R p1 + R p 2
æ V NMH
R p1 = z L + z L çç
è VCC − V NMH
zL
zO
R p1 R p 2
where zL is the line impedance.
Combining these equations, and solving for Rp1 gives
Figure 27: Thévenin Termination (PECL)
CLKP
R p1 + R p 2
where Rp1 is the pull-up resistor, Rp2 is the pull-down resistor, and VNMH is the desired noise margin, and
PECL Output Mode
PECL Mode Output
R p1
Rn2
Thévenin termination uses two resistors per transmission
line. The parallel resistance of the termination resistors
should be sized to equal the transmission line impedance, taking into account the driver sink current, the desired rise and fall times, and the VIH and VIL specifications
of the load.
30
FS6131-01
Programmable Line Lock Clock Generator IC
11.2
CMOS Output Mode
11.3
If a CMOS interface is desired, a transmission line is typically terminated using a series termination. Series termination adds no dc loading to the driver, and requires less
power than other resistive termination methods. In addition, no extra impedance exists from the signal line to a
reference voltage, such as ground.
Figure 28: Series Termination (CMOS)
zO
DRIVER
RS
LINE
zL
Serial Communications
Connection of devices to a standard-mode implementa2
tion of the I C-bus is similar to that shown in Figure 29.
Selection of the pull-up resistors (RP) and the optional
series resistors (RS) on the SDA and SCL lines depends
on the supply voltage, the bus capacitance, and the
number of connected devices with their associated input
currents.
Control of the clock and data lines is done through open
drain/collector current-sink outputs, and thus requires
external pull-up resistors on both lines.
A guideline is
RECEIVE
RP <
where tr is the maximum rise time (minus some margin)
2
and Cbus is the total bus capacitance. Assuming an I C
controller and 8 to 10 other devices on the bus, including
this one, results in values in the 5kΩ to 7kΩ range. Use of
a series resistor to provide protection against high voltage spikes on the bus will alter the values for RP.
As shown in Figure 28, the sum of the driver’s output impedance (zO) and the series termination resistance (RS)
must equal the line impedance (zL). That is,
RS = z L − zO .
When the source impedance (zO+RS) is matched to the
line impedance, then by voltage division the incident
wave amplitude is one-half of the full signal amplitude.
Vi = V
tr
,
2 × Cbus
Figure 29: Connections to the Serial Bus
( z O + RS )
V
=
( z O + RS ) + z L 2
RP
SDA
RP
SCL
However, the full signal amplitude may take up to twice
as long as the propagation delay of the line to develop,
reducing noise immunity during the half-amplitude period.
Note that the voltage at the receive end must add up to a
signal amplitude that meets the receiver switching
thresholds. The slew rate of the signal may be reduced
due to the additional RC delay of the load capacitance
and the line impedance. Also, note that the output driver
impedance will vary slightly with the output logic state
(high or low).
RS
RS
(optional)
(optional)
RS
Data In
Clock Out
(optional)
Data In
Clock In
Data Out
TRANSMITTER
RS
(optional)
Data Out
RECEIVER
11.3.1
For More Information
2
More information on the I C-bus can be found in the
2
document The I C-bus And How To Use It (Including
Specifications), available from Philips Semiconductors at
http://www-us2.semiconductors.philips.com.
31
FS6131-01
Programmable Line Lock Clock Generator IC
12.0
where the reference source frequency (fREF) can be either
supplied by the VCXO or applied to the REF pin.
Great flexibility is permitted in the programming of the
FS6131 to achieve exact desired output frequencies
since three integers are involved in the computation.
Device Application:
Stand-Alone Clock Generation
The length of the reference and feedback dividers, their
granularity, and the flexibility of the post Divider make the
FS6131 the most flexible monolithic stand-alone PLL
clock generation device available. The effective block
diagram of the FS6131 when programmed for StandAlone mode is shown in Figure 30.
The source of the Feedback Divider in the Stand-Alone
mode is the output of the VCO. By dividing the input reference frequency down by Reference Divider (NR), then
multiplying it up in the Main Loop through the Feedback
Divider (NF), and finally dividing the Main Loop output
frequency by the Post Divider (NPx), we have the defining
relationship for this mode. The equation for the output
clock frequency (fCLK) can be written as
æN
f CLK = f REF çç F
è NR
öæ 1
÷÷çç
øè N Px
ö
÷÷ ,
ø
12.1
Example Calculation
A Visual BASIC program is available to completely program the FS6131 based on the given parameters.
Suppose that the reference source frequency is
14.318MHz and the desired output frequency is 100MHz.
First, factor the 14.318MHz reference frequency (which is
four times the NTSC television color sub-carrier) into
prime numbers. The exact expression is
5
× 32 × 57 × 71
f REF = 14318181.81 = 2
.
11
(Eqn.1)
Figure 30: Block Diagram: Stand-Alone Clock Generation
LFTC
XTUNE
(optional)
Control
ROM
XCT[3:0],
XLVTEN
XIN
VCXO
Divider
VCXO
XOUT
(optional)
CLF
CLP
CRYSTAL LOOP
XLROM[2:0]
XLPDEN,
XLSWAP
Internal
Loop
Filter
XLCP[1:0]
RLF
EXTLF
UP
PhaseFrequency
Detector
Charge
Pump
(optional)
EXTLF
STAT[1:0]
DOWN
Lock
Detect
CMOS
REFDIV[11:0]
REF
(fREF)
Reference
Divider
REFDSRC
MLCP[1:0]
VCOSPD,
OSCTYPE
GBL
Voltage
Controlled
Oscillator
Clock
Gobbler
(optional)
POST3[1:0]
POST2[1:0]
POST1[1:0]
PDREF
(NR)
PhaseFrequency
Detector
FBK
UP
Charge
Pump
DOWN
OM[1:0]
(fVCO)
ADDR
CLKP
Post
Divider
(NPx)
(fCLK)
CLKN
CMOS/PECL
Output
PDFBK
Feedback
Divider (NF)
SCL
SDA
I2C
Interface
RIPRG
LOCK/
IPRG
FBKDSRC[1:0]
Registers
MAIN LOOP
FBKDIV[14:0]
FS6131
32
FS6131-01
Programmable Line Lock Clock Generator IC
As Eqn. 3 shows, the VCO frequency can be doubled by
multiplying the Feedback Divider by two. Set the Post
Divider to two to return the output frequency to the desired modulus. These divider settings place the VCO frequency at 200MHz.
Next, express the output and input frequencies as a ratio
of fCLK to fREF, where fCLK has also been converted to a
product of prime numbers.
(
)
f CLK 100000000.00
2 8 × 58
=
= 5 2 7 1
f REF
14318181.81 æ 2 × 3 × 5 × 7 ö
çç
÷÷
11
è
ø
Simplifying the above equation yields
(
)
f CLK
2 3 × 51 × 11 .
=
f REF
32 × 7
(
)
12.2
To generate 100.000MHz from 14.318MHz, program the
following (refer to Figure 30):
(Eqn. 2)
Deciding how to apportion the denominator integers between the Reference Divider and the Post Divider is an
iterative process. To obtain the best performance, the
VCO should be operated at the highest frequency possible without exceeding its upper limit of 230MHz. (see
Table 16). The VCO frequency (fVCO) can be calculated
by
f VCO = f REF
N
× F .
NR
Recall that the Reference Divider can have a value between 1 and 4096, but the Post Divider is limited to values derived from
N Px = N P1 × N P 2 × N P 3
where the values NP1, NP2, and NP3 are found in Table 8.
In this example, the smallest integer that can be removed
from the denominator of Eqn. 2 is three. Set the Post Divider at NPx=3, and the ratio of fCLK to fREF becomes (from
Eqn. 1)
(
)
f CLK
2 3 × 51 × 11 1 .
×
=
f REF
(3 × 7 )
3
Unfortunately, a Post Divider modulus of three requires a
VCO frequency of 300MHz, which is greater than the allowable fVCO noted in Table 16. For the best PLL performance, program the Post Divider modulus to allow the
VCO to operate at a nominal frequency that is at least
70MHz but less then 230MHz. Therefore, the Reference
2
Divider cannot be reduced below the modulus of 3 ×7 (or
63) as shown in Eqn. 2.
However, the VCO can still be operated at a frequency
higher than fCLK. Multiplying both the numerator and the
denominator by two does not alter the output frequency,
but it does increase the VCO frequency.
(
)
f CLK N F
1
2 3 × 51 × 11 × 2 1 880 1
=
×
=
× =
×
f REF N R N Px
2 63 2
32 × 7
(Eqn. 3)
(
)
Example Programming
33
•
Set the Reference Divider input to select the VCXO
via REFDSRC=0
•
Set the PFD input to select the Reference Divider
and the Feedback Divider via PDREF=0 and
PDFBK=0
•
Set the Reference Divider (NR) to a modulus of 63 via
REFDIV[11:0]
•
Set the Feedback Divider input to select the VCO via
FBKDSRC=1
•
Set the Feedback Divider (NF) to a modulus of 880
via FBKDIV[14:0]
•
Set NP1=2, NP2=1, and NP3=1 for a combined Post
Divider modulus of NPx=2 via POST1[1:0],
POST2[1:0], and POST3[1:0].
•
Select the internal loop filter via EXTLF=0
•
Set XLVTEN=0 and XLPDEN=1 to disable the VCXO
fine tune and the Crystal Loop Phase Frequency
Detector
•
Set VCOSPD=0 to select the VCO high speed range
FS6131-01
Programmable Line Lock Clock Generator IC
13.0
13.1
Device Application:
Line-Locked Clock Generation
Example Calculation
A Visual BASIC program is available to completely program the FS6131 based on the given parameters.
Suppose that we wish to reconstruct the pixel clock from
a VGA source. This is a typical requirement of an LCD
projection panel application.
First, establish the total number of pixel clocks desired
between horizontal sync (HSYNC) pulses. The number of
pixel clocks is known as the horizontal total, and the
Feedback Divider is programmed to that value. In this
example, choose the horizontal total to be 800.
Next, establish the frequency of the HSYNC pulses
(fHSYNC) on the line reference signal for the video mode. In
this case, let fHSYNC=31.5kHz. The output clock frequency
fCLK is calculated to be:
Line-locked clock generation, as used here, refers to the
process of synthesizing a clock frequency that is some
integer multiple of the horizontal line frequency in a
graphics system. The FS6131 is easily configured to
perform that function, as shown in Figure 31.
A line reference signal (fHSYNC) is applied to the REF input
for direct application to the Main Loop PFD. The Feedback Divider (NF) is programmed for the desired number
of output clocks per line.
The source for the Feedback Divider is selected to be the
output of the Post Divider (NPx) so that the edges of the
output clock maintain a consistent phase alignment with
the line reference signal. The modulus of the Post Divider
should be selected to maintain a VCO frequency that is
comfortably within the operating range noted in Table 16.
f CLK = f HSYNC × N F = 31.5kHz × 800 = 25.175MHz
Figure 31: Block Diagram: Line-Locked Clock Generation
LFTC
XTUNE
(optional)
Control
ROM
XCT[3:0],
XLVTEN
XIN
VCXO
Divider
VCXO
XOUT
(optional)
CLF
CLP
CRYSTAL LOOP
XLROM[2:0]
XLPDEN,
XLSWAP
Internal
Loop
Filter
XLCP[1:0]
RLF
EXTLF
UP
PhaseFrequency
Detector
Charge
Pump
(optional)
EXTLF
STAT[1:0]
DOWN
Reference
HSYNC
Lock
Detect
CMOS
REFDIV[11:0]
REF
(fREF)
Reference
Divider
REFDSRC
MLCP[1:0]
VCOSPD,
OSCTYPE
GBL
Voltage
Controlled
Oscillator
Clock
Gobbler
(NR)
PhaseFrequency
Detector
UP
Charge
Pump
DOWN
OM[1:0]
(optional)
POST3[1:0],
POST2[1:0],
POST1[1:0]
(fVCO)
ADDR
CLKP
Post
Divider
(NPx)
(fCLK)
CLKN
CMOS/PECL
Output
PDFBK
Feedback
Divider (NF)
SDA
I2C
Interface
LOCK/
IPRG
PDREF
FBK
SCL
RIPRG
FBKDSRC[1:0]
Registers
MAIN LOOP
FBKDIV[14:0]
FS6131
34
FS6131-01
Programmable Line Lock Clock Generator IC
However, the 31.5kHz line reference signal is too low in
frequency for the internal loop filter to be used. A series
combination of a 0.015µF capacitor and a 15kΩ resistor
from power (VDD) to the EXTLF pin provides an external
loop filter. A 100pF to 220pF capacitor in parallel with the
combination may improve the filter performance.
For the best PLL performance, program the Post Divider
modulus to allow the VCO to operate at a nominal frequency that is at least 70MHz but less then 230MHz. The
VCO frequency (fVCO) can be calculated by
13.2
Example Programming
To generate 800 pixel clocks between HSYNC pulses
occurring on the line reference signal every 31.5kHz,
program the following (refer to Figure 31):
•
Clear the OSCTYPE bit to 0
•
Turn off the crystal oscillator via XLROM=7
•
Set the PFD inputs to select the REF pin and the
Feedback Divider via PDREF=1 and PDFBK=0
f VCO = f HSYNC × N F × N Px .
•
Setting the Post Divider equal to four (NPx=4) is a reasonable solution, although there are a number of values
that will work. Try to keep
Set the Feedback Divider input to select the Post Divider via FBKDSRC=0
•
Set the Feedback Divider (NF) to a modulus of 800
(the desired number of pixel clocks per line) via
FBKDIV[14:0]
•
Set NP1=4, NP2=1, and NP3=1 for a combined Post
Divider modulus of NPx=4 via POST1[1:0],
POST2[1:0], and POST3[1:0].
•
Select the external loop filter via EXTLF=1
•
Set XLVTEN=0 and XLPDEN=1 to disable the VCXO
fine tune and the Crystal Loop Phase Frequency
Detector
•
Set VCOSPD=1 to select the VCO low speed range
N F × N Px < 5000
to avoid divider values from becoming too large. These
settings place the VCO frequency at about 100MHz.
Calculate the ideal charge pump current (Ipump) as
I pump =
2N N
f HSYNC
× 2 F Px
15kHz Rlf C lf AVCO
where Rlf is the external loop filter series resistor, Clf is
the external loop filter series capacitor, and AVCO is the
VCO gain. The VCO gain is either:
AVCO=125MHz/V if the High Range is selected, or
AVCO=75MHz/V if the Low Range is selected.
See Table 16 for more information on the VCO range.
With fhsync=31.5kHz, Clf=0.015µF, Rlf=15kΩ, NF=800,
NPx=4, and AVCO=125MHz/V, the charge pump current is
39.3µA. A 220pF cap across the entire loop filter is also
helpful.
• Set MLCP[1:0] to 3 to select the 32µA range
The output clock frequency fCLK is 25.175MHz, with an
internal VCO frequency of 100.8MHz. Note that the
Crystal Loop was unused in this application.
35
FS6131-01
Programmable Line Lock Clock Generator IC
The output clock frequency is:
14.0
f CLK = f HSYNC × horizontal total
Device Application: Genlocking
Genlocking refers to the process of synchronizing the
horizontal sync pulses (HSYNC) of a target graphics
system to the HSYNC of a source graphics system. In a
genlocked mode, the FS6131 increases (or decreases)
the frequency of the VCO until the FBK input is frequency
matched and phase-aligned to the frequency applied to
the REF input. Since the feedback divider is within the
graphics system and the graphics system is the source of
the signal applied to the FBK input of the FS6131, the
graphics system is effectively synchronized to the REF
input as shown in Figure 32.
To configure the FS6131 for genlocking, the REF input
(pin 12) and the FBK input (pin 13) are switched directly
onto the feedback input of the PFD. The Reference and
Feedback dividers are not used.
The only remaining task is to select a Post Divider
modulus (NPx) that allows the VCO frequency to be within
its nominal range.
14.1
Example Calculation
A Visual BASIC program is available to completely program the FS6131 based on the given parameters.
The FS6131 is being used to genlock an LCD projection
panel system to a VGA card-generated HSYNC. The total
number of pixel clocks generated by the VGA card,
known as the horizontal total, are 800. Therefore, the
LCD panel graphics system that is clocked by the
FS6131 is set to divide the output clock frequency (fCLK)
by 800. The input HSYNC reference frequency (fHSYNC) is
15kHz.
Figure 32: Block Diagram: Genlocking
LFTC
XTUNE
(optional)
Control
ROM
XCT[3:0],
XLVTEN
XIN
XLPDEN,
XLSWAP
VCXO
Divider
VCXO
CLF
CLP
CRYSTAL LOOP
XLROM[2:0]
XLCP[1:0]
XOUT
RLF
EXTLF
UP
PhaseFrequency
Detector
(optional)
Internal
Loop
Filter
Charge
Pump
(optional)
EXTLF
STAT[1:0]
DOWN
Reference
HSYNC
Lock
Detect
CMOS
REFDIV[11:0]
REF
(fCLK)
Reference
Divider
REFDSRC
MLCP[1:0]
VCOSPD,
OSCTYPE
GBL
Voltage
Controlled
Oscillator
Clock
Gobbler
(optional)
POST3[1:0],
POST2[1:0],
POST1[1:0]
PDREF
(NR)
PhaseFrequency
Detector
FBK
UP
Charge
Pump
DOWN
OM[1:0]
(fCLK)
CLKN
CMOS/PECL
Output
(fVCO)
ADDR
CLKP
Post
Divider
(NPx)
PDFBK
Feedback
Divider (NF)
SCL
SDA
I2C
Interface
RIPRG
LOCK/
IPRG
FBKDSRC[1:0]
Registers
FBKDIV[14:0]
MAIN LOOP
FS6131
System HSYNC
Video Graphics System
36
Clock In
FS6131-01
Programmable Line Lock Clock Generator IC
The output clock frequency is calculated as
f CLK = 15kHz × 800 = 12.0MHz .
14.2
For best performance, program the Post Divider (NPx)
modulus to allow the VCO to operate at a nominal frequency that is at least 70MHz but less then 230MHz. The
VCO frequency (fVCO) can be calculated by
f VCO = f CLK N Px .
Selecting the Post Divider modulus of NPx=6 is a reasonable solution, although there are a number of values that
will work. Try to keep
•
Clear the OSCTYPE bit to 0
•
Turn off the crystal oscillator via XLROM=7
•
Set the PFD inputs to select the REF and FBK pins
via PDREF=1 and PDFBK=1
•
Set NP1=2, NP2=3, and NP3=1 for a combined Post
Divider modulus of NPx=6 via POST1[1:0],
POST2[1:0], and POST3[1:0].
•
Select the external loop filter via EXTLF=1
•
Set XLVTEN=0 and XLPDEN=1 to disable the VCXO
fine tune and the Crystal Loop Phase Frequency
Detector
•
Set VCOSPD=1 to select the VCO low speed range
N F × N Px < 5000
to avoid divider values from becoming too large. The settings place the VCO frequency at about 72MHz.
Calculate the ideal charge pump current (Ipump) as
I pump =
Example Programming
To generate 800 pixel clocks between HSYNC pulses
occurring on the line reference signal every 15kHz, program the following (refer to Figure 32):
2N N
f HSYNC
× 2 F Px
15kHz Rlf C lf AVCO
• Set MLCP[1:0] to 3 to select the 32µA range
The output clock frequency fCLK is 12MHz, with an internal
VCO frequency of 72MHz. Note that the Crystal Loop
was unused in this application.
where Rlf is the external loop filter series resistor, Clf is
the external loop filter series capacitor, and AVCO is the
VCO gain. The VCO gain is either
AVCO=125MHz/V if the High Range is selected, or
AVCO=75MHz/V if the Low Range is selected.
See Table 16 for more information on the VCO range.
With fhsync=15kHz, Clf=0.015µF, Rlf=15kΩ, NF=800, NPx=6,
and AVCO=125MHz/V, the charge pump current is 24µA.
A 220pF cap across the entire loop filter is also helpful.
37
FS6131-01
Programmable Line Lock Clock Generator IC
15.0
15.1
Device Application:
Telecom Clock Regenerator
Example Calculation
A Visual BASIC program is available to completely program the FS6131 based on the given parameters.
In this example, an 8kHz reference frequency is supplied
to the FS6131 and an output clock frequency of
51.84MHz is desired.
First, select the frequency at which the VCXO will operate
from Table 10. The table shows the external crystal frequency options available to choose from, since the VCXO
runs at the crystal frequency. While the Main Loop can be
programmed to work with any of the frequencies in the
table, the best performance will be achieved with the
highest frequency at the Main Loop PFD.
The frequency at the Main Loop PFD (fMLpfd) is the VCXO
frequency (fVCXO) divided by the Main Loop Reference
Divider (NR).
The FS6131 can be used as a clock regenerator as
shown in Figure 33. This mode uses the voltagecontrolled crystal oscillator (VCXO) in its own phaselocked loop, referred to as the Crystal Loop. The VCXO
provides a "de-jittered" multiple of the reference frequency at the REF pin (usually 8kHz in telecom applications) for use by the Main Loop. In essence, the Crystal
Loop “cleans up” the reference signal for the Main Loop.
The Control ROM for the VCXO Divider is preloaded with
the most common ratios to permit locking of most standard telecommunications crystals to an 8kHz signal applied to the REF pin. The de-jittered multiple of the reference frequency from the VCXO is then supplied to the
Reference Divider in the Main Loop. The Reference Divider, along with the Feedback Divider, can be programmed to achieve the desired output clock frequency.
f MLpfd =
f VCXO
NR
Figure 33: Block Diagram: Telecom Clock Regenerator
LFTC
XTUNE
Control
ROM
XCT[3:0],
XLVTEN
(optional)
XIN
VCXO
Divider
VCXO
XOUT
(optional)
8kHz IN
(typical)
CLF
CLP
CRYSTAL LOOP
XLROM[2:0]
XLPDEN,
XLSWAP
Internal
Loop
Filter
XLCP[1:0]
RLF
EXTLF
UP
PhaseFrequency
Detector
Charge
Pump
(optional)
EXTLF
STAT[1:0]
DOWN
Lock
Detect
CMOS
REFDIV[11:0]
REF
(fREF)
Reference
Divider
REFDSRC
MLCP[1:0]
VCOSPD,
OSCTYPE
GBL
Voltage
Controlled
Oscillator
Clock
Gobbler
(NR)
PhaseFrequency
Detector
UP
Charge
Pump
DOWN
OM[1:0]
(optional)
POST3[1:0],
POST2[1:0],
POST1[1:0]
CLKP
Post
Divider
(NPx)
(fCLK)
CLKN
CMOS/PECL
Output
PDFBK
(fVCO)
ADDR
Feedback
Divider (NF)
SDA
I2C
Interface
LOCK/
IPRG
PDREF
FBK
SCL
RIPRG
FBKDSRC[1:0]
Registers
MAIN LOOP
FBKDIV[14:0]
FS6131
38
FS6131-01
Programmable Line Lock Clock Generator IC
The goal is to choose the highest crystal frequency from
Table 10 that generates the smallest value of NR.
The equation establishing the output frequency (fCLK) as a
function of the input VCXO frequency is
f CLK
N
= F
f VCXO N R
15.2
Example Programming
To generate a de-jittered output frequency of 51.84MHz
from an 8kHz reference, program the following (refer to
Figure 33):
(Eqn. 1)
•
where NF is the Feedback Divider modulus.
Choose a few different crystal frequencies from Table 10
and factor both the input VCXO and output clock frequencies into prime numbers. Look for the factors that
will give the smallest modulus for NR with the largest
FVCXO. The output and VCXO frequencies and the reduced factors from Eqn. 1 are in Table 25.
Program the VCXO Control ROM to 3 via
XLROM[2:0] to select an external 19.44MHz crystal
•
Enable the VCXO fine tune via XLVTEN=1
•
Enable the Crystal Loop PFD via XLPDEN=0 and
XLSWAP=0
•
Set the Reference Divider input to select the VCXO
via REFDSRC
•
Set the PFD input to select the Reference Divider
and the Feedback Divider via PDREF and PDFBK
Table 25: Clock Regenerator Example
•
Set the Reference Divider (NR) to a modulus of 3 via
REFDIV[11:0]
•
Set the Feedback Divider input to select the VCO via
FBKDSRC
•
Set the Feedback Divider (NF) to a modulus of 8 via
FBKDIV[14:0]
•
Set NP1=1, NP2=3, and NP3=1 for a combined Post
Divider modulus of NPx=3 via POST1[1:0],
POST2[1:0], and POST3[1:0].
•
Select the internal loop filter via EXTLF
VCXO FREQUENCY
FROM Table 10
(fVCXO, MHz)
f CLK
f VCXO
NF
NR
20.00
51840000
20000000
324
125
19.44
51840000
19440000
8
3
25.248
51840000
25248000
540
263
24.576
51840000
24576000
135
64
• Set VCOSPD=0 to select the VCO high speed range
These settings provide the highest frequency at the Main
Loop Phase Frequency Detector of 6.48MHz. The use of
a 19.44MHz crystal requires that XLROM[2:0] be set to
three as shown in Table 10.
A 19.44MHz crystal provides the smallest modulus for NR
(NR=3) with the highest crystal frequency.
Finally, choose a Post Divider (NPx) modulus that keeps
the VCO frequency in its most comfortable range. The
VCO frequency (fVCO) can be calculated by
f VCO = f CLK N Px
Selecting an overall modulus of NPx=3 sets the VCO frequency at 155.52MHz when the loop is locked.
39
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