DDR4 HM 4G based LRDIMM SPD - IDT Rev 1.0_150616
HMA84GL7MMR4N-TF
SERIAL PRESENCE DETECT
Byte
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41~59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78~116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155~253
254
255
256~319
320
321
322
323
324
325~328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353~381
382
383
384~511
Function described
Number of Serial PD Bytes Written / SPD Device Size
SPD Revision
Key Byte / DRAM Device Type
Key Byte / Module Type
SDRAM Density and Banks
SDRAM Addressing
SDRAM Device Type
SDRAM Optional Features
SDRAM Thermal and Refresh Options
Other SDRAM Optional Features (PPR)
Reserved
Module Nominal Volatage, VDD
Module Organization
Module Memory Bus Width
Module Thermal Sensor
Reserved
TF TD
Function support
SPD Bytes Used : 384 / SPD Bytes Total : 512
Rev 1.0
DDR4 SDRAM
LRDIMM
4GB/4BK/4Gb
16/10
DDP
Unlimited MAC
Reserved
Not supported
Blank
1.2V
4Rx4
LP/x72
Termal sensor incorporated
Blank
Reserved
Blank
Timebases
MTB : 125ps, FTB : 1ps
SDRAM Minimum Cycle Time (tCKAVGmin)
SDRAM Maximum Cycle Time (tCKAVGmax)
CAS Latencies Supported, First Byte
CAS Latencies Supported, Second Byte
0.938ns
1.500ns
14, 13, 12, 11, 9
16, 15
CAS Latencies Supported, Third Byte
CAS Latencies Supported, Fourth Byte
Minimum CAS Latency Time (tAAmin)
Minimum RAS to CAS Delay Time (tRCDmin)
Minimum RAS to CAS Delay Time (tRPmin)
Upper Nibbles for tRASmin and tRCmin
13.50ns
13.50ns
13.50ns
33ns / 46.50ns
tRASmin, Least Significant Byte
33ns
tRCmin, Least Significant Byte
46.50ns
tRFC1min, LSB
260ns
tRFC1min, MSB
260ns
tRFC2min, LSB
160ns
tRFC2min, MSB
160ns
tRFC4min, LSB
110ns
tRFC4min, MSB
110ns
Upper Nibble for tFAW
15ns
tFAWmin LSB
15ns
tRRD_Smin
3.7ns
tRRD_L min
5.30ns
tCCD_Lmin, same bank group
5.628ns
Reserved
Blank
DQ0-3
Connector to SDRAM Bit Mapping
Connector to SDRAM Bit Mapping
DQ4-7
Connector to SDRAM Bit Mapping
DQ8-11
Connector to SDRAM Bit Mapping
DQ12-15
Connector to SDRAM Bit Mapping
DQ16-19
Connector to SDRAM Bit Mapping
DQ20-23
Connector to SDRAM Bit Mapping
DQ24-27
Connector to SDRAM Bit Mapping
DQ28-31
Connector to SDRAM Bit Mapping
CB0-3
Connector to SDRAM Bit Mapping
CB4-7
Connector to SDRAM Bit Mapping
DQ32-35
Connector to SDRAM Bit Mapping
DQ36-39
Connector to SDRAM Bit Mapping
DQ40-43
Connector to SDRAM Bit Mapping
DQ44-47
Connector to SDRAM Bit Mapping
DQ48-51
Connector to SDRAM Bit Mapping
DQ52-55
Connector to SDRAM Bit Mapping
DQ56-59
DQ60-63
Connector to SDRAM Bit Mapping
Reserved
Fine offset for tCCD_Lmin, same bank group
tRRD_L min offset
tRRD_Smin offset
Blank
5.628ns
5.30ns
3.7ns
Fine offset for tRCmin
46.50ns
Fine offset for tRPmin
13.50ns
Fine offset for tRCDmin
13.50ns
Fine offset for tAAmin
13.50ns
Fine offset for tCKAVGmax
1.500ns
Fine offset for tCKAVGmin
0.938ns
CRC for Base Configuration Section, LSB
CRC cover 0~125 byte
CRC for Base Configuration Section, MSB
CRC cover 0~125 byte
RC Extention, Module Nominal Height
31.25
Module Maximum Thickness
1.2/1.4
Reference Raw Card Used
D0
DIMM Module Attributes
2rows, 1register
LRDIMM Thermal Heat Spreader Solution
Not incorporated
Register Manufacturer ID Code, LSB
Register Manufacturer ID Code, MSB
Register Revision Number
Address Mapping from Register to DRAM
Register Output Drive Strength for Contlrol
Register Output Drive Strength for CK
Data Buffer Revision Number
IDT
IDT
Revision 3.0
Mirrored
Moderate/Very Strong/Moderate/Strong
Strong/Strong
2.1
DRAM VrefDQ for Package Rank 0
Blank
DRAM VrefDQ for Package Rank 1
Blank
DRAM VrefDQ for Package Rank 2
Blank
DRAM VrefDQ for Package Rank 2
Data buffer Vref DQ for DRAM Interface
Blank
Blank
Data buffer MDQ Drive Strength and RTT for data rate <1866
Blank
Data buffer MDQ Drive Strength and RTT for 1866< data rate <2400
Blank
Data buffer MDQ Drive Strength and RTT for 2400< data rate <3200
Blank
DRAM Driver Strength
Blank
DRAM ODT (RTT_WR and RTT_NOM) for data rate <1866
Blank
DRAM ODT (RTT_WR and RTT_NOM) for 1866< data rate <2400
Balnk
DRAM ODT (RTT_WR and RTT_NOM) for 2400< data rate <3200
Blank
DRAM ODT (RTT_PARK) for data rate <1866
Blank
DRAM ODT (RTT_PARK) for 1866< data rate <2400
Blank
DRAM ODT (RTT_PARK) for 2400< data rate <3200
Reserved
Blank
Blank
CRC for Module Specific Section, LSB
CRC cover 128~253 byte
CRC for Module Specific Section, MSB
CRC cover 128~253 byte
Reserved
Blank
Module Manufacturer's ID Code, LSB
SK hynix
Module Manufacturer's ID Code, MSB
SK hynix
Module Manufacturing Location
Module Manufacturing Date
Module Manufacturing Date
Module Serial Number
SK hynix (Icheon)
Variable
Variable
Undefined
Module Part Number
H
Module Part Number
M
Module Part Number
A
Module Part Number
8Gb
Module Part Number
32GB
Module Part Number
Module Part Number
32GB
LRDIMM
Module Part Number
LP/x72
Module Part Number
M die
Module Part Number
DDP
Module Part Number
Lead & Halogen Free
Module Part Number
x4
Module Part Number
Commercial Temp & 1.2V
Module Part Number
-
Module Part Number
2133Mbps
Module Part Number
2133Mbps
Module Part Number
Blank Space
Module Part Number
Blank Space
Module Part Number
Blank Space
Module Part Number
Blank Space
Module Revision Code
DRAM Manufacturer's ID code, LSB
DRAM Manufacturer's ID code, MSB
DRAM Stepping
Revision 0
SK hynix
SK hynix
Undefined
Module Manufacturer's Specific Data
Reserved
Blank
Reserved
Blank
End User Programmable
HEX
23
10
0C
04
84
21
91
08
00
00
00
03
18
0B
80
00
00
00
08
0C
F4
03
00
00
6C
6C
6C
11
08
74
20
08
00
05
70
03
00
78
1E
2B
2E
00
0B
0B
0B
0B
0B
0B
0B
0B
0B
0B
0B
0B
0B
0B
0B
0B
0B
0B
00
86
B5
CE
00
00
00
00
00
C2
BB
73
11
11
03
09
00
80
B3
30
01
76
0A
21
1D
1D
1D
1D
25
15
15
00
00
14
14
00
27
27
00
00
3F
D3
00
80
AD
01
00
00
00
48
4D
41
38
34
47
4C
37
4D
4D
52
34
4E
2D
54
46
20
20
20
20
00
80
AD
FF
00
00
00
00
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