HDMI® Subsystem Xilinx FPGA IP

HDMI® Subsystem Xilinx FPGA IP
HDMI® Subsystem
Xilinx FPGA IP
Summary
Key Features
The Omnitek HDMI IP Core consists of the HDMI Rx Subsystem and the
HDMI Tx Subsystem. The HDMI Rx Subsystem will convert an HDMI
video stream up to 4KP60 to a RGB/YUV video AXI4-Stream and an
axillary AXI4-Stream. The HDMI Tx Subsystem will convert a RGB/YUV
video AXI4-Stream plus AUX data AXI4-Stream to a HDMI video stream.
Control
I2C
CPU
(AXI-Lite)
RGB/YUV AXI4-Stream
AUX AXI4-Stream
AVI
Packet
Register Bus (150MHz)
■■ Very low output latency
■■ Support for image sizes up to 4096 x 2160 at up to 60 fps
■■ Independent transceiver PHY (GT Core) to allow ease of integration
into different designs and packages
■■ Tx and Rx available as independent IP Subsystems
■■ Configurable optional cores to minimise resource usage
■■ Available as reference design
■■ Fully compatible with other Omnitek IP Cores via AXI4-Stream
Applications
AXI4 Stream
Interface
FIFO
FIFO
General
Control
Packet
Misc
Packet
HDMI Rx IP Subsystem
SPI
Mapper
Pixel
Subsampler
Video
Timing
Pixel Unpacking
(Deep Colour)
PIF
De-mul�plexor
TDMS/
TERC4
Decoder
TDMS/
TERC4
Decoder
TDMS/
TERC4
Decoder
Unscrambler
Packet Filter
CED
EDID/
DDC
2
EDID/DDC/SCDC
IC
Slave
Clk
Channel Bonding
FIFO
C2
SCDC
Register
FIFO
FIFO
C1
GT Core
HDMI Inputs
C0
Bit Synchroniser
HDMI Rx Subsystem
■■ Very small FPGA resource footprint
The HDMI Rx and Tx Subsystems can be used in a range of applications
including:
■■ HDMI to SDI conversion up to 4KP60
■■ SDI to HDMI conversion up to 4KP60
■■ HDMI to V-by-One conversion
FPGA
Op�onal
■■ Display screen interfaces
I2C
CPU
(AXI-Lite)
HDMI Outputs
GT Core
FIFO
FIFO
FIFO
C1
HDMI Tx IP Subsystem
Register Bus (150MHz)
■■ Multi-screen display controllers
■■ Interactive display systems
■■ HDMI switchers/routers
■■ HDMI to IP conversion
The SDI Subsystem can be implemented on the following Xilinx devices:
■■ Aritix-7, Kintex-7 and Virtex-7
C0
C2
Clk
EDID/DDC/SCDC
2
IC
Master
OverSample
OverSample
OverSample
TDMS/
TERC4
Encoder
TDMS/
TERC4
Encoder
TDMS/
TERC4
Encoder
Scrambler Scrambler Scrambler
FIFO
ECC
Packet Arbiter
Misc AVI
Packet Packet
SPI
Mul�plexor
Mapper
General
Control
Packet
PP (3:0)
AUX AXI4-Stream
Control
Pixel Packing
Deep Colour
Supported Devices
Video
Timing
HDMI Tx Subsystem
Pixel
Repe��on
■■ Projector interfaces
RGB/YUV AXI4-Stream
HDMI channels are de-serialised, checked, synchronized and bonded.
The data is decoded to remove the TMDS encoding then unscrambled.
The unscrambled data is de-multiplexed into an RGB/YUV video stream
and an auxiliary data stream. The video data stream unpacked, timed,
sub-sampled and then mapped as a RGB/YUV AXI4-Stream. The
auxiliary data stream is filtered to extract different packets and output as
an AXI4-Stream.
FPGA
Op�onal
RGB/YUV Video data as a AXI4-Stream is mapped, pixel repeated, timed
then multiplexed with the AUX Data on a second AXI4-Stream. The
RGB or YUV data stream produced is then split into separate RGB/YUV
streams for output as HDMI.
The 3 identical data channels for RGB/YUV scramble the data before
encoding as TMDS (Transition Minimized Differential Signalling). The
data is then oversampled and buffered before being serialised to provide
the HDMI output.
■■ Kintex Ultrascale and Virtex Ultrascale
■■ Kintex Ultrascale+ and Virtex Ultrascale+
■■ Zynq-7000 and Zynq Ultrascale+ MPSoC
Additional Requirements
The HDMI Rx and Tx Subsystems require an ARM processor, MicroBlaze
or AXI4-Lite CPU to allow configuration and HDMI connection feed back.
To maximise signal integrity and ensure HDMI physical layer compliance,
Omnitek recommends the use of external low-cost input equalizer/reclocker and output cable driver devices for the HDMI I/O.
HDCP Support
The Omnitek HDMI IP core does not currently support HDCP encryption.
If this feature is required, Omnitek recommends the use of low-cost
external HDCP decrypt/encrypt devices; please contact Omnitek for a
list of compatible parts. These external parts can also function as input
equalizer/re-clocker or output cable driver if necessary.
If the application requires HDCP support included as part of the FPGA IP,
there are 3rd party solutions also available. Please contact Omnitek for
more details.
IP Sub Blocks
RTVE Reference Design
The Omnitek GT Cores convert between serial and parallel AXI4 data.
The Bit Synchronizer and Channel Bonding blocks on the HDMI Rx
Subsystem ensure that the data from the HDMI input is correctly timed.
The TMDS/TERC4 Decoder blocks on the HDMI Rx Subsystem remove
Transition Minimized Differential Signalling from the 3 data streams.
The optional Unscrambler block removes Tx scrambling.
The Demultiplexer block on the HDMI Rx Subsystem separates the
video and auxiliary data streams.
The optional Pixel Unpacker block on the HDMI Rx Subsystem extracts
and High Dynamic Range information provided by the HDMI Tx.
The Video Timing blocks ensure that the video and axillary data steams
are correctly co-timed before output or processing.
The optional Pixel Subsampler block is required when the output AXI4Stream data bus is faster than that of the HDMI Rx Subsystem.
On the HDMI Rx Subsystem, the Mapper block assembles the data into
AXI4-Stream format. On the Tx Subsystem the Mapper block converts
the AXI4-Stream into the format required by Tx Subsystem.
The Filter block on the Rx Subsystem is used to extract General Control,
AVI and Misc Packet from the auxiliary data stream and outputs AXI4-S.
The optional Pixel Repetition block is required if the AXI4-Stream data
rate is slower than that of the HDMI Tx Subsystem.
The optional Pixel Packing block on the HDMI Rx Subsystem is required
to support Deep Colour (ie High Dynamic Range) content.
The Multiplexor block on the HDMI Tx Subsystem is use to combine the
video and auxiliary data streams.
The optional Scrambler blocks on the Tx Subsystem scramble the data.
The TMDS/TERC4 Encoder blocks on the Tx Subsystem encode the 3
HDMI data streams with Transition Minimized Differential Signalling.
The optional Oversampling block is required if the AXI4-Stream data
rate is faster than that of the HDMI Rx Subsystem.
Xilinx’s RTVE reference design (Real-Time Video Engine) incorporates
a range of IP cores alongside the OSVP Suite (Omnitek Scalable
Video Processor) to provide video processing IP and connectivity IP
functionality that offers a complete working FPGA design that can
be used both to evaluate the performance of the IP blocks in a video
application and as a starting point for your own video system designs.
HDMI Video Input / Output Formats
Reference Platform
The Omnitek OZ745-3 development platform using the Xilinx ZynqXC7Z045-3 plus HDMI 2.0 FMC board are required run the RTVE 4.1
reference design supporting the HDMI Rx and Tx Subsystems.
SD Card Slot
XADC
FDP Power
JTAG LVDS I/O x10
ARM PJTAG
USB Comms
Analogue +
Digital Audio I/O
16MB+256MB
QSPI Flash
1GB x 32 bit
DDR3 PS
Status LEDs
2GB x 64 bit
DDR3 PL
The HDMI Rx and Tx Subsystems can process video formats up to 4K
@60 Hz frame rate.
Xilinx Zynq
7045 FFG900
S Video +
VGA Input
HPC FMC
Genlock &
Clock Sythesis
DIP Switch
USB x 2
1G Ethernet
HDMI I/O
Composite SFP +
SDI I/O
(SD, HD, 3G)
SDI I/O
(SD, HD, 3G, 6G, 12G)
HDMI® is a registered trademark of HDMI Licensing and is used within
the document for identification purposes only.
UK Head Office
Intec 3, Level 1
Wade Road
Basingstoke
Hampshire
RG24 8NE
Tel: +44 (0)1256 345900
Fax: +44 (0)1256 345901
About Omnitek
Omnitek is a leading independent consultancy company specializing in the
design of products and IP for the broadcast, post-production, digital film, AV,
medical, aerospace/defence, automotive and consumer industries. Since its
foundation, Omnitek has completed many successful design projects for major
equipment manufacturers throughout Europe, Asia, and the United States.
Omnitek reserves the right to change specifications without notice. Refer to the
Omnitek web site for the latest specifications and further information:
www.omnitek.tv
Email: [email protected]
ISO 9001:2015
Copyright © 2017 Omnitek / Image Processing Techniques
Published 01/17
Version 2
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