Module 3: Adding Custom IP to an Embedded System

Module 3: Adding Custom IP to an Embedded System
For Academic Use Only
Systemy wbudowane laboratorium
Uniwersytet Zielonogórski
Wydział Elektrotechniki, Informatyki i Telekomunikacji
Instytut Informatyki i Elektroniki
Zakład InŜynierii Komputerowej
Module 3: Adding Custom IP
to an Embedded System
Targeting MicroBlaze™ on Spartan™-3E Starter Kit
This material exempt per Department of Commerce license exception TSU
Module 3: Adding Custom IP
to an Embedded System
Introduction
This lab guides you through the process of adding a custom peripheral to a processor system by
using the Create and Import Peripheral Wizard.
Objectives
After completing this lab, you will be able to:
• Create a custom peripheral and import it to the IP catalog
• Add the custom peripheral to your design
• Add pin location constraints
• Generate the bitstream and verify operation in hardware
Procedure
You will extend the Lab 2 hardware design by creating and adding a PLB peripheral (refer to
MYIP in Figure 3-1) to the system, and connecting it to the LCD on the Spartan-3E kit. You
will use the Create and Import Peripheral Wizard of Xilinx Platform Studio (XPS) to generate
the peripheral templates. You will complete the peripheral by adding LCD interface logic in the
templates. Next, you will connect the peripheral to the system and add pin location constraints
to connect the LCD controller peripheral to the on-board LCD. Finally, you will verify
operation in hardware using the provided software application.
This lab comprises the following steps:
1. Open the project
2. Generate a peripheral template
3. Create a peripheral
4. Add and connect the peripheral
5. Verify the design in hardware
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BRAM
LMB
BRAM
CNTLR
LMB
BRAM
CNTLR
MicroBlaze
UART
MDM
LEDs
GPIO
PSB
GPIO
DIP
GPIO
LCD
MPMC
CNTLR
DDR
MYIP
PLB
Figure 3-1. Design updated from previous lab
For each procedure within a primary step, there are general instructions (indicated by the
symbol). These general instructions only provide a broad outline for performing the
procedure. Below these general instructions, you will find accompanying step-by-step
directions and illustrated figures that provide more detail for performing the procedure. If you
feel confident about completing a procedure, you can skip the step-by-step directions and
move on to the next general instruction.
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Opening the Project
Step 1
Create a lab3 folder and copy the contents of the lab2 folder into the lab3 folder
if you wish to continue with the design you created in the previous lab,
otherwise copy the lab2 folder content from the completed folder into the lab3
folder. Open the project in XPS.
If you wish to continue using the design that you created in Lab 2, create a lab3 folder in
the c:\xup\embedded\labs directory and copy the contents from lab2 to lab3, otherwise
copy the content of lab2 folder from the completed folder
Open XPS by clicking Start → Programs → Xilinx ISE Design Suite 10.1i → EDK
→ Xilinx Platform Studio
Select Open a recent project, Click OK and browse to C:\xup\embedded\labs\lab3
Click system.xmp to open the project
Generate a Peripheral Template
Step 2
You will use the Create/Import Peripheral Wizard to create a PLB bus
peripheral template.
In XPS, select Hardware → Create or Import Peripheral to start the wizard
Click Next to continue to the Create and Import Peripheral Wizard flow selection (Figure
3-2).
Figure 3-2. Create and Import User Peripheral Dialog Box
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In the Select Flow panel, select Create templates for a new peripheral and click Next
Click next with the default option To an XPS project selected.
Select option to store
peripheral in XPS project
Figure 3-3. Repository or Project Dialog Box
Click Next and enter lcd_ip in the Name field, leave the default version number of 1.00.a,
click Next (see Figure 3-4)
Figure 3-4. Provide Core Name and Version Number
Select Processor Local Bus (PB v4.6), and click Next
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Figure 3-5. Select the PLB bus
Continuing with the wizard, select User Logic S/W Register support. Select
only one software accessible register of 32-bit width. Generate template driver
files. Browse to the C:\xup\embedded\labs\lab3 directory and answer the
questions at the end of this step
In the IPIF Services panel, deselect Include data phase timer and click Next
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Figure 3-6. IPIF Services Dialog Box
Click Next, accepting the default data width, and no burst and cache line support. Click
Next to accept default number of registers (one)
Figure 3-7. User SW Registers
Scroll through the IP Interconnect (IPIC) panel, which displays the default IPIC signals
that are available for the user logic based on the previous selection. Click Next
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Figure 3-8. IP Interconnect (IPIC) Dialog Box
In the (OPTIONAL) Peripheral Simulation Support panel, leave Generate BFM
simulation platform unchecked, and click Next
Figure 3-9. Peripheral Simulation Support Dialog Box
In the (OPTIONAL) Peripheral Implementation Options panel, click Generate
template driver files to help you to implement software interface, leaving others
unchecked
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Figure 3-10. Peripheral Implementation Options Dialog Box
Click Next, and you will see the summary information panel
Figure 3-11. Congratulations Dialog Box
Click Finish to close the wizard
Click on IP Catalog tab in XPS and observe that lcd_ip is added to the Project Local
pcores repository (Figure 3-12).
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Figure 3-12. IP Catalog Updated Entry
The peripheral which you just added becomes part of the available cores list. Use Windows
Explorer to browse to your project directory and ensure that the following structure has been
created by the Create and Import Peripheral Wizard (Figure 3-13)
lab3
pcores
lcd_v1_00_a
data
MPD
hdl
PAO
vhdl
devl
ipwiz.log
ipwiz.opt
Readme.txt
Figure 3-13. Structure Created by the Create and Import Peripheral Wizard
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Create the Peripheral
Step 3
Update the MPD file to include the lcd data output of the LCD controller
peripheral so the port can be connected in XPS.
Add a port called “lcd” to the MPD file.
Open lcd_ip_v2_1_0.mpd in the pcores\lcd_ip_v1_00_a\data under lab3 directory.
Add following line before the SPLB_Clk port under the Ports section
PORT lcd = “ “, DIR = O, VEC = [0:6]
Figure 3-14. Update the MPD file for the LCD Controller Peripheral
Save the file and close
Create the LCD controller using the appropriate HDL template files generated
from the Create/Import peripheral wizard: lcd_ip.vhd and user_logic.vhd. You
can edit these files using a standard text editor.
Open lcd_ip.vhd in the pcores\ lcd_ip_v1_00_a\hdl\vhdl directory.
Add user port lcd of width 7 under USER ports added here token (see Figure 3-15)
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Figure 3-15. Add the User Port LED
Search for next --USER and add port mapping statement, save the file and then close it
Figure 3-16. Add Port Mapping Statement
Open user_logic.vhd file from the vhdl directory and add lcd port definition in the USER
Ports area
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Figure 3-17. Add the lcd Port Definition
Search for next --USER and the enter the internal signal declaration according to the figure
below
Figure 3-18. Internal Signal Declaration for the User Logic
Search for –USER logic implementation and add the following code or copy it from
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Figure 3-19. Add Code
Save changes and close the user_logic.vhd
Select Project → Rescan User Repositories to have the changes in effect
Add and Connect the Peripheral
Step 4
Add and connect the LCD peripheral to the PLB bus in the System Assembly
View. Make internal and external port connections. Assign an address range to
it. Establish the LCD data port as external FPGA pins and assign the pin
location constraints so the peripheral interfaces to the LCD display on the
Spartan-3E starter kit.
In IP Catalog, select lcd_ip core, drag and drop it in the System Assembly View panel
Make sure that the Bus Interfaces filter is selected in the System Assembly View and
click on the circle in the bus connection diagram to make bus connection (Figure 3-20)
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Figure 3-20. Making Bus Connection
Select the Ports filter, and connect the lcd port of the lcd_ip_0 instance as an external pin
by selecting Make External (Figure 3-21)
Figure 3-21. Assign the lcd_0 Instance
Select Addresses filter and lock addresses of all devices except for the lcd_ip_0 instance.
Change the size of the lcd peripheral to 64K and click the Generate Addresses button.
Your results should look similar to that below (as shown in Figure 3-22)
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Figure 3-22. Generate Addresses
Modify the system.ucf file to assign external LCD controller connections to the
proper FPGA pin locations.
Open the system.ucf file by double-clicking the UCF File: data\system.ucf entry under
Project Files in the System tab
ucf
Open the C:\xup\embedded\sources\lab3.ucf file and copy the pin assignments into the
Figure 3-23. Adding UCF Constraints
Save and close the file
Verify the Design in Hardware
Step 5
Add a software program (lab3.c). Use EDK to generate the configuration file
and program the Spartan-3E xc3s500e-4fg320 device.
Click on the Applications tab and remove lab2.c file from the sources
Add lab3.c file in sources from C:\xup\embedded\sources folder
Open lab3.c and add space anywhere in white space and then save the file so new
timestamp occurs
Connect the USB and RS-232 cables to the XUP Spartan-3E board and power it up.
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Start a HyperTerminal with the following settings
• Baud rate: 115200
• Data bits: 8
• Parity: none
• Stop bits: 1
• Flow control: none
From EDK, click on Device Configuration Download Bitstream to download the
system to the FPGA
Note: this will perform the following steps
Run platgen to generate the netlists
Generate the bitstream
Run libgen to generate the libraries and drivers
Compile the program to generate the executable
Update the BRAMs in the bitstream with the executable
Download the bitstream to the FPGA
Note: Once the bitstream is downloaded, you should see the DONE LED ON and a
message displayed in HyperTerminal as shown in Figure 3-24
Figure 3-24. Screen Shot after the BitStream Downloading
You should see LCD Test Over in the HyperTerminal window and “Welcome to the #1
Prof Workshop” on the LCD panel on the XUP Spartan-3E board
?
Modify the main function of the lab3.c source file to display #{dip_check} instead #1. The
dip_check variable represents the status of switches. Analyze the lab2.c source file to check
how to read this value.
Write the main function of modified program.
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Conclusion
The Create and Import Peripheral Wizard was used to create peripheral templates for the PLB
bus. Logic was added to the templates to create an LCD interface peripheral. The peripheral
was then integrated into an existing processor system and tested in hardware using a provided
software application to display a message on the on-board LCD.
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