TA2024 – PREMILINARY STEREO 15W (4Ω) CLASS

T r i p a t h T e c h n o l o g y, I n c . - T e c h n i c a l I n f o r m a t i o n

TA2024 – PREMILINARY

STEREO 15W (4

Ω) CLASS-T™ DIGITAL AUDIO AMPLIFIER USING

DIGITAL POWER PROCESSING™ TECHNOLOGY

T e c h n i c a l I n f o r m a t i o n R e v i s i o n 1 . 5 – F e b r u a r y 2 0 0 2

1

G E N E R A L D E S C R I P T I O N

T h e T A 2 0 2 4 i s a 1 5 W / c h c o n t i n u o u s a v e r a g e t w o - c h a n n e l C l a s s - T D i g i t a l A u d i o

P o w e r A m p l i f i e r I C u s i n g T r i p a t h ’ s p r o p r i e t a r y D i g i t a l P o w e r P r o c e s s i n g ™ t e c h n o l o g y . C l a s s - T a m p l i f i e r s o f f e r b o t h t h e a u d i o f i d e l i t y o f C l a s s - A B a n d t h e p o w e r e f f i c i e n c y o f C l a s s - D a m p l i f i e r s .

A P P L I C A T I O N S

Computer/PC Multimedia

DVD Players

Cable Set-Top Products

Televisions

Video CD Players

Battery Powered Systems

B E N E F I T S

Fully integrated solution with FETs

Easier to design-in than Class-D

Reduced system cost with no heat sink

Dramatically improves efficiency versus Class-

AB

Signal fidelity equal to high quality linear amplifiers

High dynamic range compatible with digital media such as CD, DVD, and Internet audio

TYPICAL PERFORMANCE

F E A T U R E S

Class-T architecture

Single Supply Operation

“Audiophile” Quality Sound

0.04% THD+N @ 9W, 4

Ω

0.18% IHF-IM @ 1W, 4

Ω

11W @ 4

Ω, 0.1% THD+N

6W @ 8

Ω, 0.1% THD+N

High Power

15W @ 4

Ω, 10% THD+N

10W @ 8

Ω, 10% THD+N

High Efficiency

81% @ 15W, 4

Ω

88% @ 10W, 8

Ω

Dynamic Range = 102 dB

Mute and Sleep inputs

Turn-on & turn-off pop suppression

Over-current protection

Over-temperature protection

Bridged outputs

36-pin Power SOP package

2

1

0.5

10

5

VDD = 12V f = 1kHz

Av = 12

BW = 22Hz - 22kHz

THD+N versus Output Power

0.2

0.1

0.05

0.02

0.01

500m 1

R

L

= 8

Ω

2

Output Power (W)

5 10

R

L

= 4

Ω

20

TA2024 – MT/1.5/02 02

T r i p a t h T e c h n o l o g y, I n c . - T e c h n i c a l I n f o r m a t i o n

A B S O L U T E M A X I M U M R A T I N G S

(Note 1)

SYMBOL PARAMETER

V

DD

V5

SLEEP

MUTE

T

STORE

T

A

T

J

Supply Voltage

Input Section Supply Voltage

SLEEP Input Voltage

MUTE Input Voltage

Storage Temperature Range

Operating Free-air Temperature Range

Junction Temperature

16

6.0

-0.3 to 6.0

-0.3 to V5+0.3

-40 to 150

0 to 70

150

V

V

V

V

°C

°C

°C

Note 1 : Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.

Note 2 : See Power Dissipation Derating in the Applications Information section.

O P E R A T I N G C O N D I T I O N S

(Note 4)

V

DD

V

IH

V

IL

Supply Voltage

High-level Input Voltage (MUTE, SLEEP)

Low-level Input Voltage (MUTE, SLEEP)

8.5

3.5

12 13.2

1

V

V

V

Note 3: Recommended Operating Conditions indicate conditions for which the device is functional.

See Electrical Characteristics for guaranteed specific performance limits.

E L E C T R I C A L C H A R A C T E R I S T I C S

See Test/Application Circuit. Unless otherwise specified, V

DD

Bandwidth = 22kHz, R

L

= 4

Ω, T

A

= 12V, f = 1kHz, Measurement

= 25

°C, Package heat slug soldered to 2.8 square-inch PC pad.

I

SYMBOL PARAMETER

P

O

DD,MUTE

Output Power

(Continuous Average/Channel)

Mute Supply Current

TYP. UNITS

THD+N = 0.1% R

L

= 4

Ω

R

L

= 8

Ω

THD+N = 10% R

R

L

L

= 4

Ω

= 8

Ω

9

5.5

12

8

11

6

15

10

W

W

W

W

MUTE = V

IH

I

I

DD, SLEEP

Sleep Supply Current q

Quiescent Current

THD + N Total Harmonic Distortion Plus

Noise

IHF-IM IHF Intermodulation Distortion

SLEEP = V

V

IN

P

O

= 0 V

IH

= 9W/Channel

19kHz, 20kHz, 1:1 (IHF)

0.25

61

0.04

0.18

75

0.5 mA

%

%

CS

PSRR

Channel Separation

Power Supply Rejection Ratio

η Power Efficiency

V

OFFSET

Output Offset Voltage

V

OH

V e

OL

OUT

High-level output voltage

(FAULT & OVERLOAD)

Low-level output voltage

(FAULT & OVERLOAD)

Output Noise Voltage

A-Weighted, P

OUT

= 1W, R

L

= 8

Ω 89

30kHz Bandwidth 50 55

Vripple = 100mV. 60 80

P

OUT

= 10W/Channel, R

L

= 8

Ω

No Load, MUTE = Logic Low dB dB dB

88 %

50 150 mV

A-Weighted, input AC grounded 100 µV

Note: Minimum and maximum limits are guaranteed but may not be 100% tested.

2 TA2024 – MT/1.5/02 02

T r i p a t h T e c h n o l o g y, I n c . - T e c h n i c a l I n f o r m a t i o n

+5VGEN

DCAP2

DCAP1

V5D

AGND1

REF

OVERLOADB

AGND2

V5A

VP1

IN1

MUTE

NC

VP2

IN2

BIASCAP

AGND3

SLEEP

P I N D E S C R I P T I O N

Pin

2, 3

Function

DCAP2, DCAP1

4, 9

5, 8,

17

6

7

10, 14

11, 15

12

16

18

19

20, 35

24, 27;

31, 28

25, 26,

29, 30

13, 21,

23, 32,

34

36

1

V5D, V5A

AGND1, AGND2,

AGND3

REF

OVERLOADB

VP1, VP2

IN1, IN2

MUTE

BIASCAP

SLEEP

FAULT

PGND2, PGND1

OUTP2 & OUTM2;

OUTP1 & OUTM1

VDD2, VDD2

VDD1, VDD1

NC

CPUMP

5VGEN

Description

Charge pump switching pins. DCAP1 (pin 3) is a free running 300kHz square wave between VDDA and DGND (12Vpp nominal). DCAP2 (pin 2) is level shifted

10 volts above DCAP1 (pin 3) with the same amplitude (12Vpp nominal), frequency, and phase as DCAP1.

Digital 5VDC, Analog 5VDC

Analog Ground

Internal reference voltage; approximately 1.0 VDC.

A logic low output indicates the input signal has overloaded the amplifier.

Input stage output pins.

Single-ended inputs. Inputs are a “virtual” ground of an inverting opamp with approximately 2.4VDC bias.

When set to logic high, both amplifiers are muted and in idle mode. When low

(grounded), both amplifiers are fully operational. If left floating, the device stays in the mute mode. This pin should be tied to GND if not used.

Input stage bias voltage (approximately 2.4VDC).

When set to logic high, device goes into low power mode. If not used, this pin should be grounded

A logic high output indicates thermal overload, or an output is shorted to ground, or another output.

Power Grounds (high current)

Bridged outputs

Supply pins for high current H-bridges, nominally 12VDC.

Not connected. Not bonded internally.

Charge pump output (nominally 10V above VDDA)

Regulated 5VDC source used to supply power to the input section (pins 4 and 9).

T A 2 0 2 4 P I N O U T

36-pin Power SOP Package

(Top View)

3

4

5

6

7

1

2

8

9

10

11

12

13

14

15

16

17

18

32

31

30

29

28

27

26

25

24

23

22

21

20

19

36

35

34

33

OUTM2

VDD2

VDD2

OUTP2

NC

DGND

NC

PGND2

FAULT

CPUMP

PGND1

NC

VDDA

NC

OUTP1

VDD1

VDD1

OUTM1

3 TA2024 – MT/1.5/02 02

T r i p a t h T e c h n o l o g y, I n c . - T e c h n i c a l I n f o r m a t i o n

4

A P P L I C A T I O N / T E S T C I R C U I T

TA2024

C

I

2.2uF

+

R

I

20K

Ω

R

F

20K

Ω

C

A

0.1uF

VP1

10

IN1

BIASCAP

11

16

(Pin 8)

5V

Processing

&

Modulation

5V

MUTE

12

C

I

2.2uF

+

R

F

20K

Ω

VP2

14

IN2

15

R

I

20K

Ω

(Pin 8)

8.25K

R

Ω, 1%

6

REF

3

DCAP1

+12V

1meg Ω

C

D

0.1uF

2

DCAP2

18

SLEEP

0.1uF

4

V5D

C

S

0.1uF

To Pin 1

C

S

0.1uF

5

9

AGND1

V5A

8

17

AGND2

AGND3

13

21

23

32

34

NC

Processing

&

Modulation

5V

CPUMP

36

VDDA

33

DGND

22

+5VGEN

1

VDD1

30

VDD1

29

PGND1

35

VDD2

25

VDD2

26

PGND2

20

VDD1

31

OUTP1

L o

10uH, 2A

PGND1

VDD1

D

O

(Pin 35)

(Pin 35)

28

OUTM1

L o

10uH, 2A

*C o

0.47uF

C

Z

0.47uF

*C o

0.47uF

R

Z

10

Ω, 1/2W

C

CM

0.1uF

PGND1

19

7

VDD2

D

(Pin 35)

O

FAULT

OVERLOADB

24

OUTP2

L o

10uH, 2A

PGND2

VDD2

D

O

(Pin 20)

(Pin 20)

27

OUTM2

PGND2

D

O

(Pin 20)

L o

10uH, 2A

*C o

0.47uF

C

Z

0.47uF

*C o

0.47uF

R

Z

10

Ω, 1/2W

C

CM

0.1uF

+

C

P

1uF

C

S

0.1uF

C

S

0.1uF

To Pins 4,9

C

SW

0.1uF

C

SW

0.1uF

+

C

SW

180uF, 16V

+

C

SW

180uF, 16V

VDD (+12V)

R

L

4

Ω or *8Ω

4

R

Ω or *8Ω

Note: Analog and Digital/Power Grounds must

be connected locally at the TA2024

Analog Ground

Digital/Power Ground

All Diodes Motorola MBRS130T3

* Use C o

= 0.22

µF for 8 Ohm loads

TA2024 – MT/1.5/02 02

T r i p a t h T e c h n o l o g y, I n c . - T e c h n i c a l I n f o r m a t i o n

E X T E R N A L C O M P O N E N T S D E S C R I P T I O N

(Refer to the Application/Test Circuit)

Components Description

R

I

Inverting Input Resistance to provide AC gain in conjunction with R biased at the BIASCAP voltage (approximately 2.4VDC).

F

. This input is

R

F

C

I

Feedback resistor to set AC gain in conjunction with R

I

;

A

V

=

12 ( R

F

/ R

I to the Amplifier Gain paragraph in the Application Information section.

)

. Please refer

AC input coupling capacitor which, in conjunction with R

I f

C

=

1 ( 2

π

R

I

C

I

)

, forms a highpass filter at

R

REF

C

A

C

D

C

C

C

P

S

SW

Bias resistor. Locate close to pin 6 (REF) and ground at pin 8 (AGND2).

BIASCAP decoupling capacitor. Should be located close to pin 16.

Charge pump input capacitor. This capacitor should be connected directly between pins 2 (DCAP2) and 3 (DCAP1) and located physically close to the TA2024.

Charge pump output capacitor that enables efficient high side gate drive for the internal H-bridges. To maximize performance, this capacitor should be connected directly between pin 36 (CPUMP) and pin 33 (VDDA). Please observe the polarity shown in the Application/ Test Circuit.

Supply decoupling for the low current power supply pins. For optimum performance, these components should be located close to the pin and returned to their respective ground as shown in the Application/Test Circuit.

Supply decoupling for the high current, high frequency H-Bridge supply pins. These components must be located as close to the device as possible to minimize supply overshoot and maximize device reliability. Both the high frequency bypassing

(0.1uF) and bulk capacitor (180uF) should have good high frequency performance including low ESR and low ESL. Panasonic HFQ or FC capacitors are ideal for the bulk capacitor.

C

Z

R

Z

D

L

O

O

Zobel resistor, which in conjunction with C frequencies. The combination of R

Z

and C

Z

Z

, terminates the output filter at high

minimizes peaking of the output filter under both no load conditions or with real world loads, including loudspeakers which usually exhibit a rising impedance with frequency.

Schottky diodes that minimize undershoots of the outputs with respect to power ground during switching transitions. For maximum effectiveness, these diodes must be located close to the output pins and returned to their respective PGND. Please see Application/Test Circuit for ground return pin.

Output inductor, which in conjunction with C

O

, demodulates (filters) the switching waveform into an audio signal. Forms a second order filter with a cutoff frequency of f

C

=

1 ( 2

π

L

O

C

O

) and a quality factor of

Q

=

R

L

C

O

L

O

C

O

.

C

O

C

CM

Output capacitor.

Common Mode Capacitor.

5 TA2024 – MT/1.5/02 02

T r i p a t h T e c h n o l o g y, I n c . - T e c h n i c a l I n f o r m a t i o n

T Y P I C A L P E R F O R M A N C E

Efficiency versus Output Power

100

90

80

70

60

50

40

30

20

10

0

0

R

L

= 8

Ω

5

R

L

= 4 Ω

10

Output Power (W)

VDD = 12V f = 1kHz

Av = 12

THD+N < 10%

15 20

-50

-60

-70

-80

-90

-100

50

+0

-10

-20

-30

-40

VDD = 12V

Pout = 1W/Channel

RLoad = 4

Ω

0dBr = 12Vrms

19kHz, 20kHz, 1:1

Av = 11.7

BW = 10Hz - 80kHz

Intermodulation Performance

1k 2k 5k

Frequency (Hz)

10k 20k 30k

0.2

0.1

0.05

2

0.5

1

10

5

VDD = 12V

Pout = 5W/Channel

Av = 12

BW = 22Hz - 22kHz

THD+N versus Frequency

R

L

= 4

Ω

R

L

= 8

Ω

0.02

0.01

10 20 50 100 200 500

Frequency (Hz)

1k 2k 5k 10k 20k

6

+3

+2.5

+2

+1.5

+1

+0.5

+0

-0.5

-1

-1.5

-2

-2.5

-3

10

VDD = 12V

Pout = 1W

RLoad = 4 Ω

Av = 12

BW = 22Hz - 22kHz

20 50 100

Frequency Response

200 500

Frequency (Hz)

1k 2k 5k 10k 20k

Noise Floor

-100

-120

-140

20

+0

-20

-40

VDD = 12V

Pout = 0W

RLoad = 4

Ω

Av = 12

BW = 22Hz - 22kHz

A-Weighted Filter

-60

-80

50 100 200 500

Frequency (Hz)

1k 2k 5k 10k 20k

Channel Separation versus Frequency

+0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

20

VDD = 12V

Pout = 1W/Channel

RLoad = 4 Ω

Av = 12

BW = 22Hz - 22kHz

50 100 200 500 1k

Frequency (Hz)

2k 5k 10k 20k

TA2024 – MT/1.5/02 02

T r i p a t h T e c h n o l o g y, I n c . - T e c h n i c a l I n f o r m a t i o n

A P P L I C A T I O N I N F O R M A T I O N

L a y o u t R e c o m m e n d a t i o n s

The TA2024 is a power (high current) amplifier that operates at relatively high switching frequencies. The outputs of the amplifier switch between the supply voltage and ground at high speeds while driving high currents. This high-frequency digital signal is passed through an LC low-pass filter to recover the amplified audio signal. Since the amplifier must drive the inductive

LC output filter and speaker loads, the amplifier outputs can be pulled above the supply voltage and below ground by the energy in the output inductance. To avoid subjecting the TA2024 to potentially damaging voltage stress, it is critical to have a good printed circuit board layout. It is recommended that Tripath’s layout and application circuit be used for all applications and only be deviated from after careful analysis of the effects of any changes. Please contact Tripath

Technology for further information regarding reference design material regarding the TA2024.

T A 2 0 2 4 A m p l i f i e r G a i n

The gain of the TA2024 is set by the ratio of two external resistors, R

I

and R following formula:

F

, and is given by the

V

O

V

I

=

12

R

F

R

I where V

R

F

= R

I

I

is the input signal level and V

O

is the differential output signal level across the speaker.

9 Watts of RMS output power results from an 8.485V RMS signal across an 8

Ω speaker load. If

, then 9 Watts will be achieved with 0.707V RMS of input signal.

8 .

485 V

RMS

=

( R

L

∗

P

O

)

=

( 8

Ω ∗

9 W )

P r o t e c t i o n C i r c u i t s

The TA2024 is guarded against over-temperature and over-current conditions. When the device goes into an over-temperature or over-current state, the FAULT pin goes to a logic HIGH state indicating a fault condition. When this occurs, the amplifier is muted, all outputs are TRI-

STATED, and will float to 1/2 of V

DD

.

O v e r - t e m p e r a t u r e P r o t e c t i o n

An over-temperature fault occurs if the junction temperature of the part exceeds approximately

155

°C. The thermal hysteresis of the part is approximately 45°C, therefore the fault will automatically clear when the junction temperature drops below 110

°C.

O v e r - c u r r e n t P r o t e c t i o n

An over-current fault occurs if more than approximately 7 amps of current flows from any of the amplifier output pins. This can occur if the speaker wires are shorted together or if one side of the speaker is shorted to ground. An over-current fault sets an internal latch that can only be cleared if the MUTE pin is toggled or if the part is powered down. Alternately, if the MUTE pin is connected to the FAULT pin, the HIGH output of the FAULT pin will toggle the MUTE pin and automatically reset the fault condition.

O v e r l o a d

The OVERLOADB pin is a 5V logic output. When low, it indicates that the level of the input signal has overloaded the amplifier resulting in increased distortion at the output. The OVERLOADB signal can be used to control a distortion indicator light or LED through a simple buffer circuit, as the OVERLOADB cannot drive an LED directly.

7 TA2024 – MT/1.5/02 02

T r i p a t h T e c h n o l o g y, I n c . - T e c h n i c a l I n f o r m a t i o n

S l e e p P i n

The SLEEP pin is a 5V logic input that when pulled high (>3.5V) puts the part into a low quiescent current mode. This pin is internally clamped by a zener diode to approximately 6V thus allowing the pin to be pulled up through a large valued resistor (1meg

Ω recommended) to V

DD

SLEEP mode, the sleep pin should be grounded.

. To disable

F a u l t P i n

The FAULT pin is a 5V logic output that indicates various fault conditions within the device.

These conditions include: low supply voltage, low charge pump voltage, low 5V regulator voltage, over current at any output, and junction temperature greater than approximately 155

°C. All faults except overcurrent all reset upon removal of the condition. The FAULT output is capable of directly driving an LED through a series 200

Ω resistor. If the FAULT pin is connected directly to the MUTE input an automatic reset will occur in the event of an over-current condition.

P o w e r D i s s i p a t i o n D e r a t i n g

For operating at ambient temperatures above 25

°C the device must be derated based on a

150

°C maximum junction temperature, TJMAX as given by the following equation:

P

DISS

=

( T

JMAX

θ

JA

−

T

A

) where…

PDISS = maximum power dissipation

TJMAX = maximum junction temperature of TA2024

TA = operating ambient temperature

θJA = junction-to-ambient thermal resistance

Where

θ

JA

of the package is determined from the following graph:

Θ

JA vs Copper Area

50

40

30

20

10

0 1 2 3 4

Copper Area (square inches)

5 6

Pdiss - 1.35W

Pdiss - 2W

Pdiss - 3.4W

In the above graph Copper Area is the size of the copper pad on the PC board to which the heat slug of the TA2024 is soldered. The heat slug must be soldered to the PC Board to increase the maximum power dissipation capability of the TA2024 package. Soldering will minimize the likelihood of an over-temperature fault occurring during continuous heavy load conditions. The vias used for connecting the heatslug to the copper area on the PCB should be 0.013” diameter.

8 TA2024 – MT/1.5/02 02

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P e r f o r m a n c e M e a s u r e m e n t s o f t h e T A 2 0 2 4

The TA2024 operates by generating a high frequency switching signal based on the audio input.

This signal is sent through a low-pass filter (external to the Tripath amplifier) that recovers an amplified version of the audio input .

The frequency of the switching pattern is spread spectrum and typically varies between 100kHz and 1.0MHz, which is well above the 20Hz – 20kHz audio band. The pattern itself does not alter or distort the audio input signal but it does introduce some inaudible components.

The measurements of certain performance parameters, particularly noise related specifications such as THD+N, are significantly affected by the design of the low-pass filter used on the output as well as the bandwidth setting of the measurement instrument used. Unless the filter has a very sharp roll-off just beyond the audio band or the bandwidth of the measurement instrument is limited, some of the inaudible noise components introduced by the Tripath amplifier switching pattern will degrade the measurement.

One feature of the TA2024 is that it does not require large multi-pole filters to achieve excellent performance in listening tests, usually a more critical factor than performance measurements.

Though using a multi-pole filter may remove high-frequency noise and improve THD+N type measurements (when they are made with wide-bandwidth measuring equipment), these same filters degrade frequency response. The TA2024 Evaluation Board uses the Test/Application

Circuit in this data sheet, which has a simple two-pole output filter and excellent performance in listening tests. Measurements in this data sheet were taken using this same circuit with a limited bandwidth setting in the measurement instrument.

9 TA2024 – MT/1.5/02 02

T r i p a t h T e c h n o l o g y, I n c . - T e c h n i c a l I n f o r m a t i o n

P A C K A G E I N F O R M A T I O N

3 6 - L e a d P o w e r S m a l l O u t l i n e P a c k a g e ( P S O P ) , s i m i l a r t o J E D E C o u t l i n e M O -

1 6 6 , v a r i a t i o n A E :

For Package Dimensions, please contact Tripath Technology

3 2 1

TOP VIEW

36

SIDE VIEW

D1

BOTTOM VIEW

SEE DETAIL "A"

END VIEW

10 TA2024 – MT/1.5/02 02

T r i p a t h T e c h n o l o g y, I n c . - T e c h n i c a l I n f o r m a t i o n

A D V A N C E D I N F O R M A T I O N

This is a product in development. Tripath Technology, Inc. reserves the right to make any changes without further notice to improve reliability, function and design.

Tripath and Digital Power Processing are trademarks of Tripath Technology. Other trademarks referenced in this document are owned by their respective companies.

Tripath Technology, Inc. reserves the right to make changes without further notice to any products herein to improve reliability, function or design. Tripath does not assume any liability arising out of the application of use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

TRIPATH’S PRODUCT ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE

SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN CONSENT OF THE

PRESIDENT OF TRIPATH TECHONOLOGY, INC. As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in this labeling, can be reasonably expected to result in significant injury of the user.

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

C o n t a c t I n f o r m a t i o n

T R I P A T H T E C H N O L O G Y , I N C

2560 Orchard Parkway, San Jose, CA 95131

408.750.3000 - P

408.750.3001 - F

For more Sales Information, please visit us @ www.tripath.com/cont_s.htm

For more Technical Information, please visit us @ www.tripath.com/data.htm

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