Supply-Voltage Supervisors (Rev. D)
TL7759
SUPPLY-VOLTAGE SUPERVISORS
SLVS042D – JANUARY 1991 – REVISED JULY 1999
D
D
D
D
D
D
D
D, P, OR PW PACKAGE
(TOP VIEW)
Power-On Reset Generator
Automatic Reset Generation After Voltage
Drop
Precision Input Threshold
Voltage . . . 4.55 V ±120 mV
Low Standby Current . . . 20 µA
Reset Outputs Defined When VCC
Exceeds 1 V
True and Complementary Reset Outputs
Wide Supply-Voltage Range . . . 1 V to 7 V
NC
NC
NC
GND
1
8
2
7
3
6
4
5
RESET
RESET
NC
VCC
NC – No internal connection
description
The TL7759 is a supply-voltage supervisor designed for use as a reset controller in microcomputer and
microprocessor systems. The supervisor monitors the supply voltage for undervoltage conditions. During power
up, when the supply voltage, VCC, attains a value approaching 1 V, the RESET and RESET outputs become
active (high and low, respectively) to prevent undefined operation. If the supply voltage drops below the input
threshold voltage level (VIT– ), the reset outputs go to the reset active state until the supply voltage has returned
to its nominal value (see timing diagram).
The TL7759C is characterized for operation from 0°C to 70°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA
SMALL
OUTLINE
(D)
PLASTIC
DIP
(P)
SHRINK
SMALL
OUTLINE
(PW)
CHIP
FORM
(Y)
0°C to 70°C
TL7759CD
TL7759CP
TL7759CPW
TL7759Y
The D and PW packages are available taped and reeled. Add the suffix R to
the device type (e.g., TL7759CDR). Chip forms are tested at 25°C.
functional block diagram
5
+
7
–
8
VCC
RESET
RESET
Reference
Voltage
4
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright  1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
TL7759
SUPPLY-VOLTAGE SUPERVISORS
SLVS042D – JANUARY 1991 – REVISED JULY 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 V
Off-state output voltage range: RESET voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 20 V
RESET voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to 20 V
Low-level output current, IOL (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
High-level output current, IOH (RESET) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –10 mA
Package thermal impedance, θJA (see Notes 2 and 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
P package . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . 149°C/W
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to the network ground terminal.
2. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can impact reliability.
3. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
recommended operating conditions
Supply voltage, VCC
MIN
MAX
1
7
15
Transistor off RESET voltage
Output voltage,
voltage VO (see Note 4)
Transistor off RESET voltage
Low-level output current, IOL
RESET
High-level output current, IOH
RESET
Operating free-air temperature, TA
TL7759C
0
0
UNIT
V
V
24
mA
–8
mA
70
°C
NOTE 4: RESET output must not be pulled down below GND potential.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
TL7759C
PARAMETER
VOL
VOH
TEST CONDITIONS
Low-level output voltage
RESET
High-level output voltage
RESET
IOL = 24 mA
IOH = –8 mA
VCC = 4
4.3
3V
VIT
IT–
Input threshold voltage
g
(negative-going VCC)
TA = 25°C
TA = 0°C to 70°C
Vres§
Power up reset voltage
Power-up
RL = 2.2
2 2 kΩ
Vhys¶
Hysteresis at VCC input
TA = 25°C
TA = 0°C to 70°C
IOH
IOL
High-level output current
RESET
Low-level output current
RESET
ICC
Supply current
MIN
VCC–1
4.43
TYP‡
MAX
0.4
0.8
4.55
4.67
4.7
0.8
1
1.2
40
50
60
30
VCC = 7 V
V, See Figure 1
VOH = 15 V
VOL = 0 V
No load
VCC = 4.3 V
VCC = 5.5 V
70
1400
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
V
V
mV
1
µA
–1
µA
2000
‡ Typical values are at TA = 25°C.
§ This is the lowest voltage at which RESET becomes active, VCC slew rate ≤ 5 V/µs.
¶ This is the difference between positive-going input threshold voltage, VIT+, and negative-going input threshold voltage, VIT–.
2
V
V
4.4
TA = 25°C
TA = 0°C to 70°C
UNIT
40
µA
TL7759
SUPPLY-VOLTAGE SUPERVISORS
SLVS042D – JANUARY 1991 – REVISED JULY 1999
electrical characteristics, TA = 25°C (unless otherwise noted)
TL7759Y
PARAMETER
TEST CONDITIONS
VOL
Low-level output voltage
VIT–
Vres†
Input threshold voltage (negative-going VCC)
RESET
Power-up reset voltage
VCC = 4.3 V,
MIN
IOL = 24 mA
RL = 2.2 kΩ
TYP
MAX
UNIT
0.4
V
4.55
V
0.8
V
Vhys‡
Hysteresis at VCC input
50
ICC
Supply current
VCC = 4.3 V,
No load
1400
† This is the lowest voltage at which RESET becomes active, VCC slew rate ≤ 5 V/µs.
‡ This is the difference between positive-going input threshold voltage, VIT+, and negative-going input threshold voltage, VIT–.
mV
µA
timing diagram
VCC
VIT+
Vres
VIT–
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
ÇÇ
0
RESET
Output Undefined
for VCC Less Than 1 V
VIT –
Vres
VIT+
0
Output Undefined
switching characteristics at TA = 25°C (unless otherwise noted)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS
TL7759C
MIN
MAX
UNIT
tPLH
Propagation delay time, low-to high-level output
VCC
RESET
See Figures 2 and 3§
5
µs
tPHL
Propagation delay time, high-to low-level output
VCC
RESET
See Figures 2 and 4
5
µs
tr
Rise time
RESET
See Figures 2 and 4§
1
µs
tf
Fall time
RESET
See Figures 2 and 4
1
µs
tw(min)
Minimum pulse duration
RESET
See Figures 2 and 4
VCC
5
µs
§ VCC slew rate ≤ 5 V/µs
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
3
TL7759
SUPPLY-VOLTAGE SUPERVISORS
SLVS042D – JANUARY 1991 – REVISED JULY 1999
PARAMETER MEASUREMENT INFORMATION
15 V
VCC
RESET
+
7V
A
TL7759
_
RESET
GND
A
Figure 1. Test Circuit for Output Leakage Current
4.8 V
VCC
(see Note A)
4.3 V
tPLH
tPHL
90%
90%
RESET
50%
50%
10%
10%
tr
tf
NOTE A: VCC slew rate ≤ 5 V/µs.
Figure 2. Switching Diagram
VCC
Pulse
Generator
TL7759
0.1 mF
RESET
GND
RL = 1 kΩ
CL = 100 pF†
† CL Includes jig and probe capacitance.
Figure 3. Test Circuit for RESET Output Switching Characteristics
VCC
Pulse
Generator
0.1 mF
RL= 1k Ω
RESET
TL7759
GND
CL = 100 pF†
† CL Includes jig and probe capacitance.
Figure 4. Test Circuit for RESET Output Switching Characteristics
4
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
TL7759
SUPPLY-VOLTAGE SUPERVISORS
SLVS042D – JANUARY 1991 – REVISED JULY 1999
APPLICATION INFORMATION
5V
0.1 µF
5
VCC
RESET
7
System Reset
TL7759
RESET
8
1 kΩ
GND
4
Figure 5. Power-Supply System Reset Generation
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
5
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
TL7759CD
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
7759C
TL7759CDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
7759C
TL7759CP
ACTIVE
PDIP
P
8
50
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
0 to 70
TL7759CP
TL7759CPSR
ACTIVE
SO
PS
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T7759
TL7759CPWR
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T7759C
TL7759CPWRE4
ACTIVE
TSSOP
PW
8
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
0 to 70
T7759C
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
17-Mar-2017
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Feb-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
TL7759CDR
Package Package Pins
Type Drawing
SOIC
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
D
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
TL7759CPSR
SO
PS
8
2000
330.0
16.4
8.2
6.6
2.5
12.0
16.0
Q1
TL7759CPWR
TSSOP
PW
8
2000
330.0
12.4
7.0
3.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
15-Feb-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
TL7759CDR
SOIC
D
8
2500
340.5
338.1
20.6
TL7759CPSR
SO
PS
8
2000
367.0
367.0
38.0
TL7759CPWR
TSSOP
PW
8
2000
367.0
367.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0008A
TSSOP - 1.2 mm max height
SCALE 2.800
SMALL OUTLINE PACKAGE
C
6.6
TYP
6.2
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 0.65
8
1
3.1
2.9
NOTE 3
2X
1.95
4
5
B
4.5
4.3
NOTE 4
SEE DETAIL A
8X
0.30
0.19
0.1
C A
1.2 MAX
B
(0.15) TYP
0.25
GAGE PLANE
0 -8
0.15
0.05
0.75
0.50
DETAIL A
TYPICAL
4221848/A 02/2015
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153, variation AA.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
1
8
(R0.05)
TYP
SYMM
6X (0.65)
5
4
(5.8)
LAND PATTERN EXAMPLE
SCALE:10X
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
NOT TO SCALE
4221848/A 02/2015
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0008A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
8X (1.5)
8X (0.45)
SYMM
(R0.05) TYP
1
8
SYMM
6X (0.65)
5
4
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:10X
4221848/A 02/2015
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
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