Clock Control Block (altclkctrl) Megafunction User Guide

Clock Control Block (altclkctrl) Megafunction User Guide
Clock Control Block (ALTCLKCTRL)
Megafunction User Guide
101 Innovation Drive
San Jose, CA 95134
www.altera.com
Document Version:
Document Date:
2.4
December 2008
Copyright © 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other
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but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of
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device specifications before relying on any published information and before placing orders for products or services.
UG-MF9604-2.4
Contents
Chapter 1. About this Megafunction
Device Family Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Dynamic Clock Source Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Dynamic Power-Down of a Clock Network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2
Global Clock Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3
Regional Clock Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
External PLL Output Clock Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–4
Clock Enable Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–5
Clock Enable Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–6
Chapter 2. Getting Started
MegaWizard Plug-In Manager Page Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
Connectivity Restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
Design Example: Global Clock Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Design Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
Functional Simulation in the ModelSim-Altera Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
Chapter 3. Specifications
Ports and Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Input Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–1
Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2
Additional Information
Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Referenced Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
© December 2008
Altera Corporation
Info–1
Info–2
Info–2
Info–3
Clock Control Block (ALTCLKCTRL) Megafunction User Guide
iv
Clock Control Block (ALTCLKCTRL) Megafunction User Guide
© December 2008
Altera Corporation
1. About this Megafunction
Device Family Support
The Clock Control Block megafunction (also known as ALTCLKCTRL) supports the
following target Altera® device families:
■
Arria® GX
■
Stratix ® IV
■
Stratix III
■
Stratix II GX
■
Stratix II
■
HardCopy ® II
■
Cyclone® III
■
Cyclone II
Introduction
As design complexities increase, the use of vendor-specific intellectual property (IP)
blocks has become a common design methodology. Altera provides parameterizable
megafunctions that are optimized for Altera® device architectures. Using
megafunctions instead of coding your own logic saves valuable design time.
Additionally, the Altera-provided functions offer more efficient logic synthesis and
device implementation. You can scale the size of the megafunction by setting various
parameters.
Use the ALTCLKCTRL megafunction to control the clock control block in the
supported devices. The common applications of using this megafunction are to
dynamically select the clock source and dynamically power-down a clock network.
Dynamic Clock Source Selection
When using the clock control block, you can select the dynamic clock source that
drives the global clock network. However, only certain combinations of signal sources
are supported, as described in “Global Clock Control Block” on page 1–3. You cannot
select clock sources dynamically to drive the regional clock networks and the
dedicated external clock-out path.
Dynamic Power-Down of a Clock Network
The dynamic clock enable or disable feature allows internal logic to power-down the
clock network. When a clock network is powered-down, all the logic fed by that clock
network is not toggling, thus the overall power consumption of the device is reduced.
© December 2008
Altera Corporation
Clock Control Block (ALTCLKCTRL) Megafunction User Guide
1–2
Chapter 1: About this Megafunction
Features
Features
The ALTCLKCTRL megafunction implements a basic clock control block. In addition,
it offers the following features:
■
Supports specification of operation mode of the clock control block
■
Supports specification of the number of input clock sources
■
Provides an active high clock enable control input
General Description
The ALTCLKCTRL megafunction is a clock control function provided by the
Quartus® II MegaWizard® Plug-In Manager to easily configure the clock control block
in supported devices.
A clock control block is a dynamic clock buffer that allows you to enable and disable
the clock network and dynamically switch between multiple sources to drive the
clock network. Table 1–1 shows the clock control block and the devices that support it.
Table 1–1. Clock Buffers that Drive the Clock Control Block
Clock Control
Block
Arria GX
Stratix IV
Stratix III
Stratix II
Stratix II GX Cyclone III Cyclone II
HardCopy II
Global Clock
Network
v
v
v
v
v
v
v
v
Dual Regional
Clock Network
v
v
v
v
v
—
—
v
Regional
Clock Network
v
v
v
v
v
—
—
v
Dedicated
External Clock
Out Path
v
v
v
v
v
v
v
v
For Periphery
Clock
—
v
—
—
—
—
—
—
The global clock network allows a clock signal (or other global signals) to reach all
parts of the chip with a similar amount of skew. The regional clock network allows a
signal to reach one quadrant of the chip (though half of the chip can be reached by
driving two quadrants). The external clock-out path represents the clock path from
the outputs of the phase-locked loop (PLL) to the dedicated PLL_OUT pins. The
ALTCLKCTRL megafunction also provides glitch-free implementation for multiple
clock input signals.
Clock Control Block (ALTCLKCTRL) Megafunction User Guide
© December 2008
Altera Corporation
Chapter 1: About this Megafunction
General Description
1–3
Global Clock Control Block
When a clock control block is configured to drive a global clock network, you can
select the clock source statically or you can control the selection dynamically by using
internal logic to drive multiplexer selector inputs. When selecting the clock source
statically, you can set the clock source to any of the inputs. For example, you can use
the dedicated CLK pin, internal logic, and PLL outputs.
When selecting the clock source dynamically, you can select two PLL outputs (such as
c0 or c1), a combination of clock pins, or PLL outputs. Figure 1–1 shows a clock
control block and the possible sources that can drive the global clock network in a
Stratix II device.
Figure 1–1. Global Clock Control Block in Stratix II Devices
CLKp Pin
PLL Counter Outputs
CLKSELECT [1..0]
(1)
2
2
CLKn Pin
2
Internal Logic
This multiplexer
supports user-controlled
dynamic switching.
Static Clock Select
(2)
Enable/
Disable
Internal Logic
GCLK
Notes to Figure 1–1:
(1) You can dynamically control these clock select signals through internal logic only when the device is operating in user
mode.
(2) You can only set these clock select signals through a configuration file and cannot be dynamically controlled during
user-mode operation.
© December 2008
Altera Corporation
Clock Control Block (ALTCLKCTRL) Megafunction User Guide
1–4
Chapter 1: About this Megafunction
General Description
Regional Clock Control Block
When the clock control block is configured to drive a regional clock network, you can
only control the clock source selection statically. You can set any inputs to the clock
select multiplexer as the clock source. Figure 1–2 shows a clock control block
configured to drive a regional clock network in a Stratix II device.
Figure 1–2. Regional Clock Control Block in Stratix II Devices
CLKp Pin
PLL Counter Outputs
CLKn Pin
(2)
2
Internal Logic
Static Clock Select
(1)
Enable/
Disable
Internal Logic
RCLK
Notes to Figure 1–2:
(1) You can only control these clock select signals through a configuration file and cannot be dynamically controlled
during user-mode operation.
(2) Only the CLKn pins on the top and bottom of the device feed to the regional clock control blocks.
The unused global and regional clock networks are powered down automatically in
the configuration file generated by the Quartus II software. The dynamic clock enable
feature allows the internal logic to control the power for the GCLK and RCLK
networks. You can enable or disable the clock network with the ALTCLKCTRL
megafunction.
External PLL Output Clock Control Block
When the clock control block is configured to drive the dedicated external clock out,
you can only control the clock source selection statically. You can only set the PLL
outputs as the clock source. Figure 1–3 shows a clock control block configured to drive
a dedicated external clock out for Stratix II devices.
Clock Control Block (ALTCLKCTRL) Megafunction User Guide
© December 2008
Altera Corporation
Chapter 1: About this Megafunction
General Description
1–5
Figure 1–3. External PLL Output Clock Control Block in Stratix II Devices (Note 2)
PLL Counter Outputs
(c[0..5])
6
Static Clock
Select (1)
Enable/
Disable
Internal Logic
Internal Logic
Static Clock
Select (1)
PLL_Out Pin
Notes to Figure 1–3:
(1) You can only set these clock select signals through the configuration file and cannot be dynamically controlled during
user-mode operation.
(2) The clock control block feeds to a multiplexer within the PLL_OUT pin’s I/O element (IOE). The PLL_OUT pin is a
dual-purpose pin. Therefore, this multiplexer selects either an internal signal or the output of the clock control block.
Clock Enable Signals
In Stratix II devices, the clock enable signals are supported at the clock network level.
This allows you to enable or disable the GCLK and RCLK networks, or the PLL_OUT
pins, which is useful for applications that require low power or sleep mode.
Figure 1–4 shows how the ena clock enable signal is implemented.
Figure 1–4. Clock Enable Implementation in Stratix II Devices
clkena
clk
D
Q
clkena out
clk_out
© December 2008
Altera Corporation
Clock Control Block (ALTCLKCTRL) Megafunction User Guide
1–6
Chapter 1: About this Megafunction
General Description
Clock Enable Timing
Figure 1–5 shows a functional timing waveform example for clock-output enable.
Clock enable is synchronous with the falling edge of the input clock.
Figure 1–5. Clock Enable Timing
inclk
ena
outclk
Clock Control Block (ALTCLKCTRL) Megafunction User Guide
© December 2008
Altera Corporation
2. Getting Started
MegaWizard Plug-In Manager Page Descriptions
Start the MegaWizard® Plug-In Manager in one of the following ways:
■
On the Tools menu, click MegaWizard Plug-In Manager.
■
When working in the Block Editor, from the Edit menu, click Insert Symbol as
Block, or right-click in the Block Editor, point to Insert, and click Symbol as
Block. In the Symbol window, click MegaWizard Plug-In Manager.
■
Start the stand-alone version of the MegaWizard Plug-In Manager by typing the
following command at the command prompt:
qmegawizr
Figure 2–1 shows the block diagram of the ALTCLKCTRL megafunction with all the
available ports.
Figure 2–1. ALTCLKCTRL Ports and Parameters
ena
inclk 3x
inclk 2x
outclk
inclk 1x
inclk 0x
clkselect[1..0]
Table 2–1 provides descriptions of the options available on the individual pages of the
ALTCLKCTRL MegaWizard Plug-In Manager.
Table 2–1. ALTCLKCTRL MegaWizard Plug-In Manager Page Options and Description (1 of 3)
MegaWizard
Plug-in
Manager
Page
1
© December 2008
Configuration Setting
Which action do you want to perform?
Altera Corporation
Description
You can select from the following options: Create a new
custom megafunction variation, Edit an existing custom
megafunction variation, or Copy an existing custom
megafunction variation.
Clock Control Block (ALTCLKCTRL) Megafunction User Guide
2–2
Chapter 2: Getting Started
MegaWizard Plug-In Manager Page Descriptions
Table 2–1. ALTCLKCTRL MegaWizard Plug-In Manager Page Options and Description (2 of 3)
MegaWizard
Plug-in
Manager
Page
2a
Configuration Setting
Description
Select a megafunction from the list below
Select ALTCLKCTRL from the I/O category.
Which device family will you be using?
Specify the device family that you want to use.
Which type of output file do you want to create?
You can choose AHDL(.tdf), VHDL(.vhd), or Verilog HDL
(.v) as the output file type.
What name do you want for the output file?
Specify the name of the output file.
Return to this page for another create operation
Turn on this option if you want to return to this page to
create multiple megafunctions.
Currently selected device family
Specifies the device family you chose on page 2a.
Match project/default
Turn on this option to ensure that the device selected
matches the device family that is chosen in the previous
page.
Specify the ALTCLKCTRL buffering mode. You can select
from the following modes:
Auto (1) —Allows the compiler to pick the best clock
buffer to use.
For global clock—Allows a clock signal to reach all parts
of the chip with the same amount of skew; you can select
input port clkselect to switch between the four clock
inputs.
How do you want to use the ALTCLKCTRL?
3
For dual regional clock—half chip (1)—Allows a clock
signal to reach half of the chip by using two regional
clocks to drive two quadrants; only one clock input is
accepted.
For regional clock —quarter chip (1)—Allows a clock
signal to reach a quadrant of the chip; only one clock
input is accepted.
For external path—Represents the clock path from the
outputs of the PLL to the dedicated clock output pins;
only one clock output is accepted.
For periphery clock (2)—Allows a clock signal to reach a
quadrant or an octant of the chip depending on the
device; only one clock input is accepted.
How many clock inputs would you like? (3)
Specify the number of input clock sources for the clock
control block. You can specify up to four clock inputs.
Create ‘ena’ port to enable or disable the clock network
driven by this buffer (2) (4)
Turn on this option if you want to create an active high
clock enable signal to enable or disable the clock
network.
Ensure glitch-free switchover implementation
Turn on this option to implement a glitch-free switchover
when you use multiple clock inputs.
Clock Control Block (ALTCLKCTRL) Megafunction User Guide
© December 2008
Altera Corporation
Chapter 2: Getting Started
MegaWizard Plug-In Manager Page Descriptions
2–3
Table 2–1. ALTCLKCTRL MegaWizard Plug-In Manager Page Options and Description (3 of 3)
MegaWizard
Plug-in
Manager
Page
4
Configuration Setting
Generate netlist
Description
Turn on this option if you want to generate a netlist for
your third-party EDA synthesis tool to estimate the timing
and resource usage of the megafunction. If you turn on
this option, a netlist file (_syn.v) is generated. This file is
a representation of the customized logic used in the
Quartus® II software and provides connectivity of the
architectural elements in the megafunction but may not
represent true functionality.
Specify the types of files to be generated. Only the files
marked with red check marks are optional.
Choose from the following types of files:
6
Summary Page
■
Variation file (5)
■
AHDL Include file (<function name>.inc)
■
VHDL component declaration file
(<function name>.cmp)
■
Quartus II symbol file (<function name>.bsf)
■
Instantiation template file (<function name>_inst.v)
■
Verilog HDL black box file (<function name>_bb.v)
■
Synthesis area and timing estimation netlist (_syn.v)
(6)
For more information about the wizard-generated files,
refer to Quartus II Help or to the Recommended HDL
Coding Styles chapter in volume 1 of the Quartus II
Handbook.
Notes to Table 2–1:
(1)
(2)
(3)
(4)
(5)
(6)
This option is not supported in Cyclone® II and Cyclone III devices.
This option is not supported in Arria® GX, Cyclone II, Cyclone III, Hardcopy® II, Stratix ® II, and Stratix II GX devices.
You can change the number of clock inputs only if you choose the Auto or For global clock options.
Not supported if you choose the For periphery clock option.
The Variation file contains wrapper code in the language you specified on page 2a and is automatically generated.
The synthesis area and timing estimation netlist file (_syn.v) is automatically generated if the Generate netlist option on page 4 is turned on.
© December 2008
Altera Corporation
Clock Control Block (ALTCLKCTRL) Megafunction User Guide
2–4
Chapter 2: Getting Started
MegaWizard Plug-In Manager Page Descriptions
Connectivity Restrictions
The following section describes the restrictions associated with the signal sources that
can drive the inclk[] input.
General Restrictions
■
The inclk[] ports that you use must be consistent with the clkselect[] ports
that you use. For example, if the clkselect[] ports are set to 0, inclk[0] must
be used. If clkselect[0] is fed by anything other than 0 or 1 and
clkselect[1] is set to 1, you must use either inclk[0] or inclk[1].
■
If the clkselect[] ports are set to anything other than 0, only pins or PLL clock
outputs can feed the inclk[] ports. In addition, pins must feed only inclk[0]
or inclk[1], while PLL clock outputs must feed only inclk[2] or inclk[3].
■
If the clock control block feeds any inclk[] port of another clock control block,
both must be able to be reduced to a single clock control block of equivalent
functionality.
Stratix II Devices Restrictions
f
■
When connecting dedicated clock input pins to inclk0x and inclk1x, you must
connect the low order CLK pin to inclk0x and the high order CLK pin to
inclk1x. For example, if you are connecting CLK14p and CLK15p to a clock
control block, CLK14p must connect to inclk0x and CLK15p must connect to
inclk1x. The Quartus II software has the ability in most cases to swap ports as
required, but this can help to solve errors that you may encounter in the Quartus II
fitter.
■
When connecting PLL output ports to inclk2x and inclk3x, you must connect
the low order PLL port to inclk2x and the high order PLL port to inclk3x. For
example, if you are connecting PLL output ports C0 and C1 to a clock control
block, C0 must connect to inclk2x and C1 must connect to inclk3x. The
Quartus II software has the ability in most cases to swap ports as required, but this
can help to solve errors that you may encounter in the Quartus II fitter.
For more information about valid connectivity configurations, refer to the Clocking
section of the PLL chapter in the handbook of the device family you are using. Each
global and regional resource has a clock control block. Use the information shown in
the Clocking section of the handbook to determine the valid dedicated clock pin and
PLL output port resources which can feed any global or regional resource through a
clock control block.
Table 2–2 summarizes which ports are used by the different clock control block types.
If a port is not available for a particular clock network, clock control block placement
is restricted to only the clock network types that support that port.
Table 2–2. ALTCLKCTRL Megafunction Clock Control Block Port Usage
Port
inclk[3..0]
Global
Regional
External Clock
Has all four ports
Has only inclk[0]
Has only inclk[0]
clkselect[1:0]
Yes
No
No
ena
Yes
Yes
Yes
outclk
Yes
Yes
Yes
Clock Control Block (ALTCLKCTRL) Megafunction User Guide
© December 2008
Altera Corporation
Chapter 2: Getting Started
Design Example: Global Clock Buffer
2–5
As shown in Table 2–2, all clock buffer types support the clock enable feature, while
only the global clock network supports the dynamic clock source selection feature.
If the CLOCK_TYPE value is set to AUTO, the Quartus II software selects the clock
control block type that meets all the requirements. For example, if you use the
dynamic clock source selection and the clock control block feeds a pin, a global clock
control block is used. Similarly, if the clock control block feeds a pin that cannot be
reached by the PLL using an external clock output path (in other words, not a
dedicated clock path), a global clock network is used. In this case, a warning message
about the “irregular” path to the pin is issued.
Design Example: Global Clock Buffer
This design example uses the ALTCLKCTRL megafunction to select clock signals
from the PLL outputs and dedicated clock pins in the Stratix II device. This example
uses the MegaWizard Plug-In Manager in the Quartus II software.
Design Files
The design files are available on the Literature page of the Altera website
(www.altera.com). The files are located under the following sections:
■
On the Quartus II Literature page, expand the Using Megafunctions section and
then expand the I/O section
■
User Guides section
Example
In this example, perform the following:
■
Generate a clock control block using the ALTCLKCTRL megafunction in the
MegaWizard Plug-In Manager
■
Simulate the design in the ModelSim-Altera software
Perform the following steps to select clock signals from the PLL outputs and
dedicated clock pins in the Stratix II device:
1. Open altclkctrl_DesignExample.zip and extract altclkctrl_ex.qar.
2. In the Quartus II software, open altclkctrl_ex.qar and restore the archive file into
your working directory.
3. Open the top-level file, altclkctrl_ex.bdf.
4. Double-click on a blank area in the schematic.
5. In the Symbol window, click on the MegaWizard Plug-In Manager button. Page 1
of the MegaWizard Plug-In Manager appears.
6. Select Create a new custom megafunction variation.
7. Click Next. Page 2a of the MegaWizard Plug-In Manager appears.
8. In the MegaWizard Plug-In Manager pages, select or verify the configuration
settings shown in Table 2–3. Click Next to advance from one page to the next.
© December 2008
Altera Corporation
Clock Control Block (ALTCLKCTRL) Megafunction User Guide
2–6
Chapter 2: Getting Started
Example
Table 2–3. Configuration Settings for ALTCLKCTRL Design Example
MegaWizard
Plug-in
Manager Page
2a
3
4
5
Configuration Setting
Value
Which megafunction would you like to customize?
ALTCLKCTRL
Which device family will you be using?
Stratix II
Which type of output file do you want to create?
AHDL
What name do you want for the output file?
clkctrl_gclk
Currently selected device family
Stratix II
Match project/default
Selected
How do you want to use the altclkctrl?
For global clock
How many clock inputs would you like?
4
Create ‘ena’ port to enable or disable the clock network driven
by this buffer
Selected
Ensure glitch-free switchover implementation
Selected
Generate netlist
Selected
Variation file
Selected
AHDL Include file
Selected
VHDL component declaration file
Selected
Quartus II symbol file
Selected
Instantiation template file
Selected
Verilog HDL black-box file
Selected
Synthesis area and timing estimation netlist
Selected
9. Click Finish. The clkctrl_gclk module is now built.
10. In the Symbol window, click OK.
11. Move the mouse to align the clkctrl_gclk symbol with the existing ports in the
altclkctrl_ex.bdf. Click to place the symbol. You have now completed the design
file.
12. On the File menu, click Save.
13. Run a full compilation.
Clock Control Block (ALTCLKCTRL) Megafunction User Guide
© December 2008
Altera Corporation
Chapter 2: Getting Started
Functional Simulation in the ModelSim-Altera Software
2–7
Functional Simulation in the ModelSim-Altera Software
Simulate the clock control block design in the ModelSim® -Altera software to generate
a waveform display of the device behavior.
You need to be familiar with the ModelSim-Altera software before trying out the
design example. If you are unfamiliar with the ModelSim-Altera software, refer to the
ModelSim support page on the Altera website (www.altera.com). On this support
page, you will find links to such topics as installation, usage, and troubleshooting.
Set up and simulate the design in the ModelSim-Altera software by performing the
following steps:
1. Unzip the altclkctrl_ex_msim.zip file to any working directory on your PC.
2. Start the ModelSim-Altera software.
3. On the File menu, click Change Directory.
4. Select the folder in which you unzipped the files.
5. Click OK.
6. On the Tools menu, select TCL, then click Execute Macro.
7. Select the altclkctrl_ex_msim.do file and click Open. The altclkctrl_ex_msim.do
file is a script file for the ModelSim-Altera software to automate all the necessary
settings for the simulation.
8. Verify the results shown in the Waveform Viewer window with the expected
waveform in Figure 2–2.
You can rearrange signals, remove signals, add signals, and change the radix by
modifying the script in altclkctrl_ex_msim.do accordingly.
Figure 2–2 shows the expected simulation results in the ModelSim-Altera software.
Figure 2–2. ModelSim-Altera Simulation Waveforms
The objective of the functional simulation waveform is to highlight the dynamic clock
switching process. The design example uses four clock input ports named inclk3x,
inclk2x, inclk1x, and inclk0x with the output enable port named ena. Output is
enabled when the ena port is asserted.
© December 2008
Altera Corporation
Clock Control Block (ALTCLKCTRL) Megafunction User Guide
2–8
Chapter 2: Getting Started
Functional Simulation in the ModelSim-Altera Software
The megafunction uses a built-in multiplexer to output the selected clock at outlck
based on the value of clkselect[1..0]. Observe the behavior of the clkout
signal whenever the value of clkselect[1..0] changes. When the
clkselect[1..0] value is “00”, the inclk0x signal is output to outclk port.
When the clkselect[1..0] signal changes to “01”, the outclk port takes the
value of the inclk1x signal. This behavior is described in Table 2–4. The value of
clkselect[1..0] determines the signal selection of outclk.
Table 2–4. Clock Input Selection
Clock Control Block (ALTCLKCTRL) Megafunction User Guide
clkselect[1..0]
outclk
00
inclk0x
01
inclk1x
10
inclk2x
11
inclk3x
© December 2008
Altera Corporation
3. Specifications
Ports and Parameters
The parameter details are only relevant for users who bypass the MegaWizard ®
Plug-In Manager interface and use the megafunction as a directly parameterized
instantiation in their design.
Besides using the MegaWizard Plug-In Manager to instantiate the megafunction, you
can also instantiate the megafunction directly in the Verilog HDL, VHDL, or AHDL
code by calling the megafunction, and setting its parameters as you would in any
other module, component, or subdesign. The details of these parameters are hidden
from MegaWizard Plug-In Manager interface users.
1
Altera strongly recommends that you use the MegaWizard Plug-In Manager for
complex megafunctions. The MegaWizard Plug-In Manager ensures that you set all
megafunction parameters properly.
f
Refer to Figure 2–1 on page 2–1 for the block diagram of the ALTCLKCTRL
megafunction with all the available ports.
f
Refer to the latest version of the Quartus® II Help for the most current information
about the ports and parameters of this megafunction.
Table 3–1 shows the input ports, Table 3–2 shows the output ports, and Table 3–3
shows the ALTCLKCTRL megafunction parameters.
Input Ports
Table 3–1. ALTCLKCTRL Megafunction Input Ports
Port Name
Required
clkselect[]
No
© December 2008
Altera Corporation
Description
Input that dynamically selects
the clock source to drive the
clock network that is driven by
the clock buffer.
Comments
Input port[1 DOWNTO 0] wide.
If omitted, the default is GND.
If this signal is connected, only the global clock
network can be driven by this clock control block.
Binary Value
Signal Selection
00
inclk[0]
01
inclk[1]
10
inclk[2]
11
inclk[3]
Clock Control Block (ALTCLKCTRL) Megafunction User Guide
3–2
Chapter 3: Specifications
Ports and Parameters
Table 3–1. ALTCLKCTRL Megafunction Input Ports
Port Name
Required
Description
No
ena
Comments
Clock enable of the clock buffer
If omitted, the default value is VCC .
This option cannot be used for the external clock
output path in Cyclone® II device, and periphery clock
network path in Stratix® III and Stratix IV devices.
inclk[]
Yes
Clock input of the clock buffer
Input port [3 DOWNTO 0] wide.
You can specify up to four clock inputs,
inclk[3:0].
Clock pins, clock outputs from the PLL, and core
signals can drive the inclk[] port.
Multiple clock inputs are only supported for the global
and auto-selected clock networks.
Output Ports
Table 3–2. ALTCLKCTRL Megafunction Output Ports
Port Name
outclk
Required
Yes
Description
Comments
Output of the clock buffer.
—
Parameters
Table 3–3. ALTCLKCTRL Megafunction Parameters
Parameter Name
CLOCK_TYPE
Type
Required
String
Yes
Comments
This parameter specifies the operation mode. The values are:
Value
Signal Selection
AUTO
Auto-selected clock
(default value)
GCLK
Global clock
LCLK
Regional clock
EXTCLK
External clock
SIDE_CLK
Dual-regional clock
The clkselect and ena ports are unavailable if the
CLOCK_TYPE parameter is set to EXTCLK.
ENA_REGISTER_MODE
String
No
Register mode for the ena port. Values are NONE,
FALLING_EDGE, and DOUBLE_REGISTER. Only available in
Stratix III and Stratix IV devices.
LPM_HINT
String
No
Allows you to specify Altera-specific parameters in VHDL
Design Files (.vhd). The default value is UNUSED.
LPM_TYPE
String
No
Identifies the library of parameterized modules (LPM) entity
name in VHDL Design Files (.vhd).
INTENDED_DEVICE_FAMILY
String
No
Used for modeling and behavioral simulation purposes. Create
the ALTCLKCTRL megafunction with the MegaWizard Plug-In
Manager to get the value for this parameter.
Clock Control Block (ALTCLKCTRL) Megafunction User Guide
© December 2008
Altera Corporation
Additional Information
Document Revision History
The following table shows the revision history for the chapters in this user guide.
Date
December 2008
Document
Version
2.4
Changes Made
■
Updated the following sections:
Š“Device Family Support” section
Š“Introduction” section
Š“General Description” section
Š“Design Example: Global Clock Buffer” section
Š“Functional Simulation in the ModelSim-Altera
Software” section
Š“Ports and Parameters” section
Š“How to Contact Altera” section
■
Removed the following sections:
Š“Resource Utilization & Performance” section
Š“Software and System Requirements” section
Š“Inferring Megafunctions from HDL Code” section
Š“Instantiating Megafunctions in HDL Code or
Schematic Designs” section
Š“Identifying a Megafunction after Compilation” section
Š“SignalTap II Embedded Logic Analyzer” section
May 2007
© December 2008
2.3
■
Removed all screenshots in the “MegaWizard Plug-In
Manager Page Descriptions” section
■
Reorganized the “MegaWizard Plug-In Manager Page
Descriptions” section into table format.
■
Renamed “About this User Guide” section to “Additional
Information” and moved the section to the end of the
user guide.
Updated for Quartus II software version 7.1, including:
■
Added information on Cyclone® III and Arria ® GX device
support
■
Added Referenced Documents section
March 2007
2.2
Added Cyclone III device to list of supported devices.
December 2006
2.1
Updated device family support to include Stratix® III
devices.
Altera Corporation
Clock Control Block (ALTCLKCTRL) Megafunction User Guide
Info–2
Referenced Documents
Date
Document
Version
October 2006
September 2004
2.0
1.0
Changes Made
Updated for Quartus II version 6.0, including
■
Screen shots
■
ModelSim section in Chapter 2
Initial release
Referenced Documents
This user guide references the following documents:
■
Quartus II Integrated Synthesis chapter in volume 1 of the Quartus II Handbook
■
Recommended HDL Coding Styles chapter in volume 1 of the Quartus II Handbook
■
Design Debugging Using the SignalTap II Embedded Logic Analyzer chapter in
volume 3 of the Quartus II Handbook
How to Contact Altera
For the most up-to-date information about Altera ® products, refer to the following
table.
Contact (1)
Contact
Method
Address
Technical support
Website
www.altera.com/support
Technical training
Website
www.altera.com/training
Email
[email protected]
Product literature
Website
www.altera.com/literature
Non-technical support (General)
Email
[email protected]
(Software Licensing) Email
[email protected]
Note to table:
(1) You can also contact your local Altera sales office or sales representative.
Clock Control Block (ALTCLKCTRL) Megafunction User Guide
© December 2008
Altera Corporation
Info–3
Typographic Conventions
Typographic Conventions
This document uses the typographic conventions shown in the following table.
Visual Cue
Meaning
Bold Type with Initial
Capital Letters
Command names, dialog box titles, checkbox options, and dialog box options are shown in
bold, initial capital letters. Example: Save As dialog box.
bold type
External timing parameters, directory names, project names, disk drive names, file names, file
name extensions, and software utility names are shown in bold type. Examples: fMAX ,
\qdesigns directory, d: drive, chiptrip.gdf file.
Italic Type with Initial
Capital Letters
Document titles are shown in italic type with initial capital letters. Example: AN 75: High-Speed
Board Design.
Italic type
Internal timing parameters and variables are shown in italic type.
Examples: tPIA , n + 1.
Variable names are enclosed in angle brackets (< >) and shown in italic type. Example: <file
name>, <project name>.pof file.
Initial Capital Letters
Keyboard keys and menu names are shown with initial capital letters. Examples: Delete key, the
Options menu.
“Subheading Title”
References to sections within a document and titles of on-line help topics are shown in
quotation marks. Example: “Typographic Conventions.”
Courier type
Signal and port names are shown in lowercase Courier type. Examples: data1, tdi , input.
Active-low signals are denoted by suffix n , e.g., resetn.
Anything that must be typed exactly as it appears is shown in Courier type. For example:
c:\qdesigns\tutorial\chiptrip.gdf . Also, sections of an actual file, such as a Report
File, references to parts of files (e.g., the AHDL keyword SUBDESIGN), as well as logic function
names (e.g., TRI) are shown in Courier.
1., 2., 3., and
a., b., c., etc.
Numbered steps are used in a list of items when the sequence of the items is important, such
as the steps listed in a procedure.
■
Bullets are used in a list of items when the sequence of the items is not important.
●
•
v
The checkmark indicates a procedure that consists of one step only.
1
The hand points to information that requires special attention.
c
A caution calls attention to a condition or possible situation that can damage or destroy the
product or the user’s work.
w
A warning calls attention to a condition or possible situation that can cause injury to the user.
r
The angled arrow indicates you should press the Enter key.
f
The feet direct you to more information on a particular topic.
© December 2008
Altera Corporation
Clock Control Block (ALTCLKCTRL) Megafunction User Guide
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