Intel® Celeron® Mobile Processor

P4000 and U3000 Series

Datasheet

Revision 001

October 2010

Document Number: 324471-001

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2 Datasheet

Contents

1

2

Features Summary .................................................................................................... 9

1.1

Introduction .......................................................................................................9

1.2

Processor Feature Details ................................................................................... 11

1.2.1

Supported Technologies .......................................................................... 11

1.3

Interfaces......................................................................................................... 11

1.3.1

System Memory Support ......................................................................... 11

1.3.2

PCI Express* ......................................................................................... 12

1.3.3

Direct Media Interface (DMI).................................................................... 13

1.3.4

Platform Environment Control Interface (PECI) ........................................... 14

1.3.5

Intel® HD Graphics Controller.................................................................. 14

1.3.6

Embedded DisplayPort* (eDP*) ................................................................ 15

1.3.7

Intel® Flexible Display Interface (Intel® FDI) ............................................ 15

1.4

Power Management Support ............................................................................... 15

1.4.1

Processor Core ....................................................................................... 15

1.4.2

System ................................................................................................. 15

1.4.3

Memory Controller .................................................................................. 16

1.4.4

PCI Express* ......................................................................................... 16

1.4.5

DMI ...................................................................................................... 16

1.4.6

Integrated Graphics Controller ................................................................. 16

1.5

Thermal Management Support ............................................................................ 16

1.6

Package ........................................................................................................... 16

1.7

Terminology ..................................................................................................... 17

1.8

Related Documents............................................................................................ 19

Interfaces................................................................................................................ 20

2.1

System Memory Interface................................................................................... 20

2.1.1

System Memory Technology Supported ..................................................... 20

2.1.2

System Memory Timing Support ............................................................... 21

2.1.3

System Memory Organization Modes ......................................................... 21

2.1.4

Rules for Populating Memory Slots ............................................................ 23

2.1.5

Technology Enhancements of Intel

®

Fast Memory Access (Intel

®

FMA).......... 24

2.1.6

DRAM Clock Generation........................................................................... 24

2.1.7

System Memory Pre-Charge Power Down Support Details ............................ 24

2.2

PCI Express Interface......................................................................................... 25

2.2.1

PCI Express Architecture ......................................................................... 25

2.2.2

PCI Express Configuration Mechanism ....................................................... 27

2.2.3

PCI Express Ports and Bifurcation ............................................................. 27

2.3

DMI ................................................................................................................. 28

2.3.1

DMI Error Flow ....................................................................................... 28

2.3.2

Processor/PCH Compatibility Assumptions.................................................. 28

2.3.3

DMI Link Down ...................................................................................... 28

2.4

Intel® HD Graphics Controller............................................................................. 29

2.4.1

3D and Video Engines for Graphics Processing ............................................ 29

2.4.2

Integrated Graphics Display Pipes............................................................. 32

2.4.3

Intel Flexible Display Interface ................................................................. 34

2.5

Platform Environment Control Interface (PECI) ...................................................... 34

2.6

Interface Clocking ............................................................................................. 35

2.6.1

Internal Clocking Requirements ................................................................ 35

Datasheet 3

3

4

5

6

Technologies............................................................................................................36

3.1

Intel® Virtualization Technology ..........................................................................36

3.1.1

Intel® VT-x Objectives ............................................................................36

3.1.2

Intel® VT-x Features ..............................................................................36

3.2

Intel Graphics Dynamic Frequency .......................................................................37

Power Management .................................................................................................38

4.1

ACPI States Supported .......................................................................................38

4.1.1

System States........................................................................................38

4.1.2

Processor Core/Package Idle States...........................................................38

4.1.3

Integrated Memory Controller States .........................................................39

4.1.4

PCIe Link States .....................................................................................39

4.1.5

DMI States ............................................................................................39

4.1.6

Integrated Graphics Controller States ........................................................39

4.1.7

Interface State Combinations ...................................................................40

4.2

Processor Core Power Management ......................................................................40

4.2.1

Enhanced Intel SpeedStep® Technology ....................................................41

4.2.2

Low-Power Idle States .............................................................................41

4.2.3

Requesting Low-Power Idle States ............................................................43

4.2.4

Core C-states .........................................................................................44

4.2.5

Package C-States ...................................................................................45

4.3

IMC Power Management .....................................................................................48

4.3.1

Disabling Unused System Memory Outputs.................................................49

4.3.2

DRAM Power Management and Initialization ...............................................49

4.4

PCIe Power Management ....................................................................................50

4.5

DMI Power Management .....................................................................................51

4.6

Integrated Graphics Power Management ...............................................................51

4.6.1

Intel

®

Display Power Saving Technology 5.0 (Intel

®

DPST 5.0).....................51

4.6.2

Graphics Render C-State .........................................................................51

4.6.3

Graphics Performance Modulation Technology.............................................51

4.6.4

Intel

®

Smart 2D Display Technology (Intel

®

S2DDT)...................................51

4.7

Thermal Power Management ...............................................................................52

Thermal Management ..............................................................................................53

5.1

Thermal Design Power and Junction Temperature...................................................53

5.1.1

Intel Graphics Dynamic Frequency ............................................................53

5.1.2

Intel Graphics Dynamic Frequency Thermal Design Considerations and

Specifications .........................................................................................54

5.1.3

Idle Power Specifications .........................................................................56

5.1.4

Intelligent Power Sharing Control Overview ................................................57

5.1.5

Component Power Measurement/Estimation Error .......................................58

5.2

Thermal Management Features ............................................................................58

5.2.1

Processor Core Thermal Features ..............................................................58

5.2.2

Integrated Graphics and Memory Controller Thermal Features ......................65

5.2.3

Platform Environment Control Interface (PECI) ...........................................68

Signal Description .................................................................................................... 70

6.1

System Memory Interface ...................................................................................71

6.2

Memory Reference and Compensation ..................................................................73

6.3

Reset and Miscellaneous Signals ..........................................................................74

6.4

PCI Express Graphics Interface Signals .................................................................75

6.5

Embedded DisplayPort (eDP) ...............................................................................76

6.6

Intel Flexible Display Interface Signals..................................................................76

4 Datasheet

7

8

6.7

DMI ................................................................................................................. 77

6.8

PLL Signals ....................................................................................................... 77

6.9

TAP Signals ...................................................................................................... 78

6.10

Error and Thermal Protection .............................................................................. 79

6.11

Power Sequencing ............................................................................................. 80

6.12

Processor Power Signals ..................................................................................... 81

6.13

Ground and NCTF .............................................................................................. 83

6.14

Processor Internal Pull Up/Pull Down .................................................................... 83

Electrical Specifications ........................................................................................... 85

7.1

Power and Ground Pins ...................................................................................... 85

7.2

Decoupling Guidelines ........................................................................................ 85

7.2.1

Voltage Rail Decoupling ........................................................................... 85

7.3

Processor Clocking (BCLK, BCLK#) ...................................................................... 85

7.3.1

PLL Power Supply ................................................................................... 86

7.4

Voltage Identification (VID) ................................................................................ 86

7.5

Reserved or Unused Signals ................................................................................ 90

7.6

Signal Groups ................................................................................................... 91

7.7

Test Access Port (TAP) Connection ....................................................................... 93

7.8

Absolute Maximum and Minimum Ratings ............................................................. 94

7.9

Storage Conditions Specifications ........................................................................ 94

7.10

DC Specifications............................................................................................... 95

7.10.1 Voltage and Current Specifications............................................................ 96

7.11

Platform Environmental Control Interface (PECI) DC Specifications......................... 103

7.11.1 DC Characteristics ................................................................................ 103

7.11.2 Input Device Hysteresis......................................................................... 104

Processor Pin and Signal Information .................................................................... 105

8.1

Processor Pin Assignments................................................................................ 105

8.2

Package Mechanical Information........................................................................ 179

Figures

Figure 1-1

Figure 2-2

Figure 2-3

Figure 2-4

Figure 2-5

Figure 2-6

Figure 2-7

Figure 2-8

Figure 4-9

Intel® Celeron™ P4000 and U3000 mobile processor series on the Calpella

Platform ................................................................................................ 10

Intel Flex Memory Technology Operation ................................................... 22

Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes . 23

PCI Express Layering Diagram ................................................................. 25

Packet Flow through the Layers ................................................................ 26

PCI Express Related Register Structures in the Processor ............................. 27

Integrated Graphics Controller Unit Block Diagram ...................................... 29

Processor Display Block Diagram .............................................................. 32

Idle Power Management Breakdown of the Processor Cores.......................... 42

Figure 4-10 Thread and Core C-State Entry and Exit .................................................... 42

Figure 4-11 Package C-State Entry and Exit ................................................................ 47

Figure 5-12 Frequency and Voltage Ordering............................................................... 60

Figure 7-13 Active V

CC

and I

CC

Loadline (PSI# Asserted) .............................................. 97

Figure 7-14 Active V

CC

and I

CC

Loadline (PSI# Not Asserted) ........................................ 97

Figure 7-15 VAXG/IAXG Static and Ripple Voltage Regulation ........................................ 99

Figure 7-16 Input Device Hysteresis......................................................................... 104

Figure 8-17 Socket-G (rPGA988A) Pinmap (Top View, Upper-Left Quadrant).................. 106

Figure 8-18 Socket-G (rPGA988A) Pinmap (Top View, Upper-Right Quadrant)................ 107

Datasheet 5

Figure 8-19 Socket-G (rPGA988A) Pinmap (Top View, Lower-Left Quadrant) .................. 108

Figure 8-20 Socket-G (rPGA988A) Pinmap (Top View, Lower-Right Quadrant) ................ 109

Figure 8-21 BGA1288 Ballmap (Top View, Upper-Left Quadrant) .................................. 138

Figure 8-22 BGA1288 Ballmap (Top View, Upper-Right Quadrant) ................................ 139

Figure 8-23 BGA1288 Ballmap (Top View, Lower-Left Quadrant) .................................. 140

Figure 8-24 BGA1288 Ballmap (Top View, Lower-Right Quadrant) ................................ 141

Figure 8-25 rPGA Mechanical Package (Sheet 1 of 2) ................................................. 179

Figure 8-26 rPGA Mechanical Package (Sheet 2 of 2) .................................................. 180

Figure 8-27 BGA Mechanical Package (Sheet 2 of 2) ................................................... 181

Tables

Table 5-18

Table 5-19

Table 6-20

Table 6-21

Table 6-22

Table 6-23

Table 6-24

Table 6-25

Table 6-26

Table 6-27

Table 6-28

Table 6-29

Table 6-30

Table 6-31

Table 6-32

Table 6-33

Table 6-34

Table 7-35

Table 7-36

Table 7-37

Table 7-38

Table 7-39

Table 2-1

Table 2-2

Table 2-3

Table 2-4

Table 4-5

Table 4-6

Table 4-7

Table 4-8

Table 4-9

Table 4-10

Table 4-11

Table 4-12

Table 4-13

Table 4-14

Table 4-15

Table 4-16

Table 5-17

Supported SO-DIMM Module Configurations1 ..............................................20

DDR3 System Memory Timing Support ......................................................21

eDP/PEG Ball Mapping .............................................................................33

Processor Reference Clocks ......................................................................35

System States........................................................................................38

Processor Core/Package State Support ......................................................38

Integrated Memory Controller States .........................................................39

PCIe Link States .....................................................................................39

DMI States ............................................................................................39

Integrated Graphics Controller States ........................................................39

G, S and C State Combinations .................................................................40

D, S, and C State Combination .................................................................40

Coordination of Thread Power States at the Core Level ................................43

P_LVLx to MWAIT Conversion ...................................................................43

Coordination of Core Power States at the Package Level...............................46

Targeted Memory State Conditions............................................................50

Intel Celeron P4000 mobile processor series Dual-Core SV Thermal Power

Specifications .........................................................................................56

18 W Ultra Low Voltage (ULV) Processor Idle Power ....................................56

35 W Standard Voltage (SV) Processor Idle Power.......................................57

Signal Description Buffer Types ................................................................70

Memory Channel A..................................................................................71

Memory Channel B..................................................................................72

Memory Reference and Compensation .......................................................73

Reset and Miscellaneous Signals ...............................................................74

PCI Express Graphics Interface Signals ......................................................75

Intel® Flexible Display Interface ...............................................................76

DMI - Processor to PCH Serial Interface .....................................................77

PLL Signals ............................................................................................77

TAP Signals............................................................................................78

Error and Thermal Protection....................................................................79

Power Sequencing ..................................................................................80

Processor Power Signals ..........................................................................81

Ground and NCTF ...................................................................................83

Processor Internal Pull Up/Pull Down .........................................................83

Voltage Identification Definition ................................................................86

Market Segment Selection Truth Table for MSID[2:0] ..................................90

Signal Groups1.......................................................................................91

Processor Absolute Minimum and Maximum Ratings ....................................94

Storage Condition Ratings........................................................................95

6 Datasheet

Table 7-40

Table 7-41

Table 7-42

Table 7-43

Table 7-44

Table 7-45

Table 7-46

Table 7-47

Table 8-48

Table 8-49

Table 8-50

Table 8-51

Processor Core (VCC) Active and Idle Mode DC Voltage and Current Specifications

96

Processor Uncore I/O Buffer Supply DC Voltage and Current Specifications..... 98

Processor Graphics VID based (VAXG) Supply DC Voltage and Current

Specifications......................................................................................... 99

DDR3 Signal Group DC Specifications ...................................................... 100

Control Sideband and TAP Signal Group DC Specifications .......................... 101

PCI Express DC Specifications ................................................................ 102 eDP DC Specifications ........................................................................... 103

PECI DC Electrical Limits ....................................................................... 104 rPGA988A Processor Pin List by Pin Number ............................................. 110 rPGA988A Processor Pin List by Pin Name ................................................ 124

BGA1288 Processor Ball List by Ball Name ............................................... 142

BGA1288 Processor Ball List by Ball Number ............................................ 160

Datasheet 7

Revision History

Revision

Number

001 Initial release

Description

§

Revision Date

October 2010

8 Datasheet

Features Summary

1

1.1

Note:

Features Summary

Introduction

Intel® Celeron® P4000 and U3000 mobile processor seriesis the next generation of

64-bit, multi-core mobile processor built on 32-nanometer process technology. Based on the low-power/high-performance Nehalem micro-architecture, the processor is designed for a two-chip platform as opposed to the traditional three-chip platforms

(processor, GMCH, and ICH). The two-chip platform consists of a processor and the

Platform Controller Hub (PCH) and enables higher performance, lower cost, easier validation, and improved x-y footprint. The PCH may also be referred to as Mobile

Intel® 5 Series Chipset (formerly Ibex Peak-M). Intel® Celeron® P4000 and U3000 mobile processor series is designed for the Calpella platform and is offered in rPGA988A and BGA1288 package respectively.

Included in this family of processors is Intel® HD graphics and memory controller die on the same package as the processor core die. This two-chip solution of a processor core die with an integrated graphics and memory controller die is known as a multi-chip package (MCP) processor.

1. Throughout this document, Intel® Celeron® P4000 and U3000 mobile processor series is referred to as processor.

2. Throughout this document, Intel® HD graphics is referred as integrated graphics.

3. Integrated graphics and memory controller die is built on 45-nanometer process technology

4. Intel® Celeron® P4000 and U3000 mobile processor seriesis not Intel® vPro™ eligible

Datasheet 9

10

Features Summary

Figure 1-1. Intel® Celeron® P4000 and U3000 mobile processor series on the Calpella

Platform

Dual Core

Processor

Discrete Graphics

(PEG)

OR

Embedded

DisplayPort* (eDP)

PCI Express* x16

PCI Express x 1

Processor

GPU, Memory

Controller

800/1066 MT/s

2 Channels

1 SO-DIMM / Channel

DDR3 SO-DIMMs

Intel® Flexible

Display Interface

DMI2

(x4)

Digital Display x 3

LVDS Flat Panel

Analog CRT

Dual Channel NAND

Interface

SPI Flash

PCI

FWH

SPI

PCI

Intel®

Management

Engine

Mobile Intel® 5 Series Chipset

PCH

LPC

Serial ATA

USB 2.0

6 Ports

3 Gb/s

14 Ports

WiMax

Intel

®

HD Audio

PCI Express*

8 PCI Express* x1

Ports

(2.5 GT/s)

SMBUS 2.0

Controller Link 1

WiFi

Gigabit

Network Connection

Super I/O

PECI

GPIO

Datasheet

Features Summary

1.2

1.2.1

Note:

1.3

1.3.1

Processor Feature Details

•

Two execution cores

• A 32-KB instruction and 32-KB data first-level cache (L1) for each core

•

A 512-KB shared instruction/data second-level cache (L2), 256-KB for each core

• Up to 2-MB shared instruction/data third-level cache (L3), shared among all cores

Supported Technologies

• Intel® Virtualization Technology (Intel® VT-x)

•

Intel® 64 architecture

• Execute Disable Bit

Please refer to the Intel® Celeron® P4000 and U3000 mobile processor series

Specification Update for feature support details

Interfaces

System Memory Support

•

One or two channels of DDR3 memory with a maximum of one SO-DIMM per channel

• Single- and dual-channel memory organization modes

•

Data burst length of eight for all memory organization modes

• Memory DDR3 data transfer rates of 800 MT/s (SV/ULV) and 1066 MT/s (SV)

•

64-bit wide channels

• DDR3 I/O Voltage of 1.5 V

•

Non-ECC, unbuffered DDR3 SO-DIMMs only

• Theoretical maximum memory bandwidth of:

— 12.8 GB/s in dual-channel mode assuming DDR3 800 MT/s

• 1-Gb, and 2-Gb DDR3 DRAM technologies are supported for x8 and x16 devices.

•

Using 2-Gb device technologies, the largest memory capacity possible is 8 GB, assuming dual-channel mode with two x8, double-sided, un-buffered, non-ECC,

SO-DIMM memory configuration.

• Up to 32 simultaneous open pages, 16 per channel (assuming 4 Ranks of 8 Bank

Devices)

•

Memory organizations:

— Single-channel modes

— Dual-channel modes - Intel® Flex Memory Technology:

Datasheet 11

Features Summary

1.3.2

Dual-channel symmetric (Interleaved)

Dual-channel asymmetric

•

Command launch modes of 1n/2n

• Partial Writes to memory using Data Mask (DM) signals

•

On-Die Termination (ODT)

• Intel® Fast Memory Access (Intel® FMA):

— Just-in-Time Command Scheduling

— Command Overlap

— Out-of-Order Scheduling

PCI Express*

•

The Processor PCI Express ports are fully compliant to the PCI Express Base

Specification Revision 2.0.

— One 16-lane PCI Express* port intended for graphics attach.

•

Gen1 (2.5 GT/s) PCI Express* frequency is supported.

• Gen1 Raw bit-rate on the data pins of 2.5 Gb/s, resulting in a real bandwidth per pair of 250 MB/s given the 8b/10b encoding used to transmit data across this interface. This also does not account for packet overhead and link maintenance.

•

Maximum theoretical bandwidth on interface of 4 GB/s in each direction simultaneously, for an aggregate of 8 GB/s when x16 Gen 1.

• Hierarchical PCI-compliant configuration mechanism for downstream devices.

•

Traditional PCI style traffic (asynchronous snooped, PCI ordering).

• PCI Express extended configuration space. The first 256 bytes of configuration space aliases directly to the PCI compatibility configuration space. The remaining portion of the fixed 4-KB block of memory-mapped space above that (starting at

100h) is known as “extended configuration space”.

•

PCI Express Enhanced Access Mechanism. Accessing the device configuration space in a flat memory mapped fashion.

• Automatic discovery, negotiation, and training of link out of reset.

•

Traditional AGP style traffic (asynchronous non-snooped, PCI-X Relaxed ordering).

• Peer segment destination posted write traffic (no peer-to-peer read traffic) in

Virtual Channel 0:

— DMI -> PCI Express Port 0

• 64-bit downstream address format, but the processor never generates an address above 64 GB (Bits 63:36 will always be zeros).

•

64-bit upstream address format, but the processor responds to upstream read transactions to addresses above 64 GB (addresses where any of Bits 63:36 are

12 Datasheet

Features Summary

1.3.3

Datasheet non-zero) with an Unsupported Request response. Upstream write transactions to addresses above 64 GB will be dropped.

• Re-issues configuration cycles that have been previously completed with the

Configuration Retry status.

•

PCI Express reference clock is 100-MHz differential clock buffered out of system clock generator.

• Power Management Event (PME) functions.

•

Static lane numbering reversal

— Does not support dynamic lane reversal, as defined (optional) by the PCI

Express Base Specification.

— PCI Express 1x16 configuration

Normal (1x16): PEG_RX[15:0]; PEG_TX[15:0]

Reversal (1x16): PEG_RX[0:15]; PEG_TX[0:15]

• Supports Half Swing “low-power/low-voltage” mode.

•

Message Signaled Interrupt (MSI and MSI-X) messages

• PEG Lanes shared with Embedded DisplayPort* (see eDP, Section 1.3.6

).

•

Polarity inversion

Direct Media Interface (DMI)

•

Compliant to Direct Media Interface second generation (DMI2).

• Four lanes in each direction.

•

2.5 GT/s point-to-point DMI interface to PCH is supported.

• Raw bit-rate on the data pins of 2.5 Gb/s, resulting in a real bandwidth per pair of

250 MB/s given the 8b/10b encoding used to transmit data across this interface.

Does not account for packet overhead and link maintenance.

•

Maximum theoretical bandwidth on interface of 1 GB/s in each direction simultaneously, for an aggregate of 2 GB/s when DMI x4.

• Shares 100-MHz PCI Express reference clock.

•

64-bit downstream address format, but the processor never generates an address above 64 GB (Bits 63:36 will always be zeros).

• 64-bit upstream address format, but the processor responds to upstream read transactions to addresses above 64 GB (addresses where any of Bits 63:36 are nonzero) with an Unsupported Request response. Upstream write transactions to addresses above 64 GB will be dropped.

•

Supports the following traffic types to or from the PCH:

— DMI -> PCI Express Port 0 write traffic

— DMI -> DRAM

— DMI -> processor core (Virtual Legacy Wires (VLWs), Resetwarn, or MSIs only)

13

Features Summary

1.3.4

1.3.5

— Processor core -> DMI

• APIC and MSI interrupt messaging support:

— Message Signaled Interrupt (MSI and MSI-X) messages

• Downstream SMI, SCI and SERR error indication.

•

Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port

DMA, floppy drive, and LPC bus masters.

• DC coupling – no capacitors between the processor and the PCH.

•

Polarity inversion.

• PCH end-to-end lane reversal across the link.

•

Supports Half Swing “low-power/low-voltage.”

Platform Environment Control Interface (PECI)

The PECI is a one-wire interface that provides a communication channel between a

PECI client (the processor) and a PECI master (the PCH).

Intel® HD Graphics Controller

•

The integrated graphics controller contains a refresh of the fifth generation graphics core

• Intel® Dynamic Video Memory Technology (Intel® DVMT) support

•

Intel® Graphics Performance Modulation Technology (Intel® GPMT)

• Intel® Smart 2D Display Technology (Intel® S2DDT)

•

Intel® Clear Video Technology

— MPEG2 Hardware Acceleration

— WMV9/VC1 Hardware Acceleration

— AVC Hardware Acceleration

— ProcAmp

— Advanced Pixel Adaptive De-interlacing

— Sharpness Enhancement

— De-noise Filter

— High Quality Scaling

— Film Mode Detection (3:2 pull-down) and Correction

— Intel® TV Wizard

• 12 EUs

•

Dedicated analog and digital display ports are supported through the Intel 5 Series

Chipset PCH

14 Datasheet

Features Summary

1.3.6

1.3.7

1.4

1.4.1

1.4.2

Embedded DisplayPort* (eDP*)

•

Shared with PCI Express Graphics port

• Shared on upper four logical lanes, after any lane reversal

• eDP[3:0] map to PEG[12:15] (non-reversed)

• eDP[3:0] map to PEG[3:0] (reversed)

•

Concurrent eDP and PEG x1 supported

Intel® Flexible Display Interface (Intel® FDI)

•

Carries display traffic from the integrated graphics controller in the processor to the legacy display connectors in the PCH.

• Based on DisplayPort standard.

•

Two independent links - one for each display pipe.

• Four unidirectional downstream differential transmitter pairs:

— Scalable down to 3X, 2X, or 1X based on actual display bandwidth requirements

— Fixed frequency 2.7 GT/s data rate

•

Two sideband signals for Display synchronization:

— FDI_FSYNC and FDI_LSYNC (Frame and Line Synchronization)

•

One Interrupt signal used for various interrupts from the PCH:

— FDI_INT signal shared by both Intel FDI Links

•

PCH supports end-to-end lane reversal across both links.

Power Management Support

Processor Core

• Full support of ACPI C-states as implemented by the following processor C-states:

— Ultra low voltage supports C0, C1, C1E, C3, Deep Power Down Technology (code named C6)

— Standard voltage supports C0, C1, C1E, C3

•

Enhanced Intel SpeedStep® Technology

System

•

S0, S3, S4, S5

Datasheet 15

Features Summary

1.4.3

1.4.4

1.4.5

1.4.6

1.5

1.6

Memory Controller

•

Conditional self-refresh (Intel® Rapid Memory Power Management (Intel® RMPM))

• Dynamic power-down

PCI Express*

• L0s and L1 ASPM power management capability

DMI

• L0s and L1 ASPM power management capability

Integrated Graphics Controller

• Intel Smart 2D Display Technology (Intel S2DDT)

•

Intel® Display Power Saving Technology (Intel® DPST)

• Graphics Render C-State (RC6)

Thermal Management Support

• Digital Thermal Sensor

•

Adaptive Thermal Monitor

• THERMTRIP# and PROCHOT# support

•

On-Demand Mode

• Open and Closed Loop Throttling

•

Memory Thermal Throttling

• External Thermal Sensor (TS-on-DIMM and TS-on-Board)

•

Render Thermal Throttling

• Fan speed control with DTS

Package

• The Intel® Celeron® P4000 and U3000 mobile processor series is available is available on:

— A 37.5 x 37.5 mm rPGA package (rPGA988A) (Standard Voltage only)

— A 34 x 28 mm BGA package (BGA1288) (Ultra Low voltage only)

16 Datasheet

Features Summary

1.7

Terminology

Term

BLT

CRT

DDR3

DP

DMA

DMI

DTS

ECC eDP*

Intel® DPST

Enhanced Intel

SpeedStep®

Technology

Execute Disable Bit

Description

Block Level Transfer

Cathode Ray Tube

Third-generation Double Data Rate SDRAM memory technology

DisplayPort*

Direct Memory Access

Direct Media Interface

Digital Thermal Sensor

Error Correction Code

Embedded DisplayPort*

Intel

®

Display Power Saving Technology

Technology that provides power management capabilities to laptops.

(G)MCH

GPU

ICH

IMC

Intel® 64 Technology

ITPM

IOV

LCD

LVDS

MCP

NCTF

Nehalem

The Execute Disable bit allows memory to be marked as executable or non-executable, when combined with a supporting operating system.

If code attempts to run in non-executable memory the processor raises an error to the operating system. This feature can prevent some classes of viruses or worms that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the system. See the

Intel® 64 and IA-32 Architectures Software Developer's Manuals for more detailed information.

Legacy component - Graphics Memory Controller Hub

Graphics Processing Unit

The legacy I/O Controller Hub component that contains the main PCI interface, LPC interface, USB2, Serial ATA, and other I/O functions. It communicates with the legacy (G)MCH over a proprietary interconnect called DMI.

Integrated Memory Controller

64-bit memory extensions to the IA-32 architecture

Integrated Trusted Platform Module

I/O Virtualization

Liquid Crystal Display

Low Voltage Differential Signaling. A high speed, low power data transmission standard used for display connections to LCD panels.

Multi-Chip Package.

Non-Critical to Function. NCTF locations are typically redundant ground or non-critical reserved, so the loss of the solder joint continuity at end of life conditions will not affect the overall product functionality.

Intel’s 45-nm processor design, follow-on to the 45-nm Penryn design.

Datasheet 17

18

Features Summary

TAC

TDP

V

CC

V

SS

V

AXG

V

TT

V

DDQ

VLD x1 x4 x8 x16

PCH

PECI

PEG

Processor

Processor Core

Rank

Term

SCI

Storage Conditions

Description

Platform Controller Hub. The new, 2009 chipset with centralized platform capabilities including the main I/O interfaces along with display connectivity, audio features, power management, manageability, security and storage features. The PCH may also be referred to using the name (Mobile) Intel® 5 Series Chipset

Platform Environment Control Interface.

PCI Express* Graphics. External Graphics using PCI Express

Architecture. A high-speed serial interface whose configuration is software compatible with the existing PCI specifications.

The 64-bit, single-core or multi-core component (package).

The term “processor core” refers to Si die itself which can contain multiple execution cores. Each execution core has an instruction cache, data cache, and 256-KB L2 cache. All execution cores share the

L3 cache.

A unit of DRAM corresponding four to eight devices in parallel, ignoring

ECC. These devices are usually, but not always, mounted on a single side of a SO-DIMM.

System Control Interrupt. Used in ACPI protocol.

A non-operational state. The processor may be installed in a platform, in a tray, or loose. Processors may be sealed in packaging or exposed to free air. Under these conditions, processor landings should not be connected to any supply voltages, have any I/Os biased or receive any clocks. Upon exposure to “free air” (i.e., unsealed packaging or a device removed from packaging material) the processor must be handled in accordance with moisture sensitivity labeling (MSL) as indicated on the packaging material.

Thermal Averaging Constant.

Thermal Design Power.

Processor core power supply.

Processor ground.

Graphics core power supply.

L3 shared cache, memory controller, and processor I/O power rail.

DDR3 power rail.

Variable Length Decoding.

Refers to a Link or Port with one Physical Lane.

Refers to a Link or Port with four Physical Lanes.

Refers to a Link or Port with eight Physical Lanes.

Refers to a Link or Port with sixteen Physical Lanes.

Datasheet

Features Summary

1.8

Related Documents

Document

Public Specifications

Advanced Configuration and Power Interface Specification 3.0

PCI Local Bus Specification 3.0

PCI Express Base Specification 2.0

DDR3 SDRAM Specification

DisplayPort Specification

Intel® 64 and IA-32 Architectures Software Developer's Manuals

Volume 1: Basic Architecture

Volume 2A: Instruction Set Reference, A-M

Volume 2B: Instruction Set Reference, N-Z

Volume 3A: System Programming Guide

Volume 3B: System Programming Guide

§

Document Number/

Location http://www.acpi.info/ http://www.pcisig.com/ specifications http://www.pcisig.com

http://www.jedec.org

http://www.vesa.org

http://www.intel.com/ products/processor/ manuals/index.htm

253665

253666

253667

253668

253669

Datasheet 19

Interfaces

2 Interfaces

This chapter describes the interfaces supported by the processor.

2.1

System Memory Interface

2.1.1

System Memory Technology Supported

The Integrated Memory Controller (IMC) supports DDR3 protocols with two, independent, 64-bit wide channels each accessing one SO-DIMM. It supports a maximum of one, unbuffered non-ECC DDR3 SO-DIMM per-channel thus allowing up to two device ranks per-channel.

DDR3 Data Transfer Rates:

— 800 MT/s (PC3-6400) and 1066 MT/s (PC3-8500)

• DDR3 SO-DIMM Modules:

— Raw Card A – double-sided x16 unbuffered non-ECC

— Raw Card B – single-sided x8 unbuffered non-ECC

— Raw Card C – single-sided x16 unbuffered non-ECC

— Raw Card D – double-sided x8 (stacked) unbuffered non-ECC

— Raw Card F – double-sided x8 (planar) unbuffered non-ECC

• DDR3 DRAM Device Technology:

— Standard 1-Gb, and 2-Gb technologies and addressing are supported for x16 and x8 devices. There is no support for memory modules with different technologies or capacities on opposite sides of the same memory module. If one side of a memory module is populated, the other side is either identical or empty.

Table 2-1. Supported SO-DIMM Module Configurations

1

Raw

Card

Version

DIMM

Capacity

B

C

C

A

A

B

1 GB

2 GB

1 GB

2 GB

512 MB

1 GB

DRAM

Device

Technology

DRAM

Organization

1 Gb

2 Gb

1 Gb

2 Gb

1 Gb

2 Gb

64 M x 16

128 M x 16

128 M x 8

256 M x 8

64 M x 16

128 M x 16

# of

DRAM

Devices

# of

Physical

Device

Ranks

# of Row/

Col

Address

Bits

8

4

4

8

8

8

2

2

1

1

1

1

13/10

14/10

14/10

15/10

13/10

14/10

# of

Banks

Inside

DRAM

8

8

8

8

8

8

Page

Size

8K

8K

8K

8K

8K

8K

20 Datasheet

Interfaces

Table 2-1. Supported SO-DIMM Module Configurations

1

Raw

Card

Version

DIMM

Capacity

DRAM

Device

Technology

D

F

F

2

4 GB

2 GB

4 GB

2 Gb

1 Gb

2 Gb

DRAM

Organization

256 M x 8

128 M x 8

256 M x 8

# of

DRAM

Devices

# of

Physical

Device

Ranks

# of Row/

Col

Address

Bits

16

16

16

2

2

2

15/10

14/10

15/10

NOTES:

1.

System memory configurations are based on availability and are subject to change.

2.

Only Raw Card D SO-DIMMs at 1066 MT/s are supported.

# of

Banks

Inside

DRAM

8

8

8

Page

Size

8K

8K

8K

2.1.2

System Memory Timing Support

The IMC supports the following DDR3 Speed Bin, CAS Write Latency (CWL), and command signal mode timings on the main memory interface:

• tCL = CAS Latency

• tRCD = Activate Command to READ or WRITE Command delay

• tRP = PRECHARGE Command Period

• CWL = CAS Write Latency

•

Command Signal modes = 1n indicates a new command may be issued every clock and 2n indicates a new command may be issued every 2 clocks. Command launch mode programming depends on the transfer rate and memory configuration.

Table 2-2. DDR3 System Memory Timing Support

Transfer

Rate

(MT/s)

800

1066 tCL

(tCK)

6

7

8 tRCD

(tCK)

6

7

8 tRP

(tCK)

6

7

8

CWL

(tCK)

CMD Mode

5

6

1n

1n

NOTES:

1.

System memory timing support is based on availability and is subject to change.

Notes

1

1

2.1.3

System Memory Organization Modes

The IMC supports two memory organization modes, single-channel and dual-channel.

Depending upon how the SO-DIMM Modules are populated in each memory channel, a number of different configurations can exist.

Datasheet 21

Interfaces

2.1.3.1

Single-Channel Mode

In this mode, all memory cycles are directed to a single-channel. Single-channel mode is used when either Channel A or Channel B SO-DIMM connectors are populated in any order, but not both.

2.1.3.2

Dual-Channel Mode - Intel® Flex Memory Technology Mode

The IMC supports Intel Flex Memory Technology Mode. This mode combines the advantages of the Dual-Channel Symmetric (Interleaved) and Dual-Channel

Asymmetric Modes. Memory is divided into a symmetric and a asymmetric zone. The symmetric zone starts at the lowest address in each channel and is contiguous until the asymmetric zone begins or until the top address of the channel with the smaller capacity is reached. In this mode, the system runs with one zone of dual-channel mode and one zone of single-channel mode, simultaneously, across the whole memory array.

Figure 2-2. Intel Flex Memory Technology Operation

C

B

C H A

B C

T O M

N o n in te r le a v e d a c c e s s

C H B

C

B

D u a l c h a n n e l in te rl e a v e d a c c e s s

B B B

C H A C H B

B – T h e la r g e s t p h y s ic a l m e m o ry a m o u n t o f th e s m a lle r s iz e m e m o r y m o d u le

C – T h e re m a in in g p h y s ic a l m e m o ry a m o u n t o f th e la r g e r s iz e m e m o ry m o d u le

2.1.3.2.1

Dual-Channel Symmetric Mode

Dual-Channel Symmetric mode, also known as interleaved mode, provides maximum performance on real world applications. Addresses are ping-ponged between the channels after each cache line (64-byte boundary). If there are two requests, and the second request is to an address on the opposite channel from the first, that request can be sent before data from the first request has returned. If two consecutive cache lines are requested, both may be retrieved simultaneously, since they are ensured to be on opposite channels. Use Dual-Channel Symmetric mode when both Channel A and

Channel B SO-DIMM connectors are populated in any order, with the total amount of memory in each channel being the same.

22 Datasheet

Interfaces

When both channels are populated with the same memory capacity and the boundary between the dual channel zone and the single channel zone is the top of memory, IMC operates completely in Dual-Channel Symmetric mode.

The DRAM device technology and width may vary from one channel to the other. Note:

2.1.3.2.2

Dual-Channel Asymmetric Mode

This mode trades performance for system design flexibility. Unlike the previous mode, addresses start at the bottom of Channel A and stay there until the end of the highest rank in Channel A, and then addresses continue from the bottom of Channel B to the top. Real world applications are unlikely to make requests that alternate between addresses that sit on opposite channels with this memory organization, so in most cases, bandwidth is limited to a single channel.

This mode is used when Intel Flex Memory Technology is disabled and both Channel A and Channel B SO-DIMM connectors are populated in any order with the total amount of memory in each channel being different.

Figure 2-3. Dual-Channel Symmetric (Interleaved) and Dual-Channel Asymmetric Modes

Dual Channel Interleaved

(memory sizes must match)

CL

Top of

Memory

CH. B

CH. A

Dual Channel Asymmetric

(memory sizes can differ)

CL

CH. B

Top of

Memory

CH. A

CH.A-top

DRB

CH. B

CH. A

CH. B

CH. A

0 0

2.1.4

Rules for Populating Memory Slots

In all modes, the frequency of system memory is the lowest frequency of all memory modules placed in the system, as determined through the SPD registers on the memory modules. The system memory controller supports only one SO-DIMM

Datasheet 23

Interfaces

2.1.5

2.1.5.1

2.1.5.2

2.1.5.3

2.1.6

2.1.7

connector per channel. For dual-channel modes both channels must have an SO-DIMM connector populated. For single-channel mode, only a single-channel can have an

SO-DIMM connector populated.

Technology Enhancements of Intel

®

Fast Memory Access

(Intel

®

FMA)

The following sections describe the Just-in-Time Scheduling, Command Overlap, and

Out-of-Order Scheduling Intel FMA technology enhancements.

Just-in-Time Command Scheduling

The memory controller has an advanced command scheduler where all pending requests are examined simultaneously to determine the most efficient request to be issued next. The most efficient request is picked from all pending requests and issued to system memory Just-in-Time to make optimal use of Command Overlapping. Thus, instead of having all memory access requests go individually through an arbitration mechanism forcing requests to be executed one at a time, they can be started without interfering with the current request allowing for concurrent issuing of requests. This allows for optimized bandwidth and reduced latency while maintaining appropriate command spacing to meet system memory protocol.

Command Overlap

Command Overlap allows the insertion of the DRAM commands between the Activate,

Precharge, and Read/Write commands normally used, as long as the inserted commands do not affect the currently executing command. Multiple commands can be issued in an overlapping manner, increasing the efficiency of system memory protocol.

Out-of-Order Scheduling

While leveraging the Just-in-Time Scheduling and Command Overlap enhancements, the IMC continuously monitors pending requests to system memory for the best use of bandwidth and reduction of latency. If there are multiple requests to the same open page, these requests would be launched in a back to back manner to make optimum use of the open memory page. This ability to reorder requests on the fly allows the IMC to further reduce latency and increase bandwidth efficiency.

DRAM Clock Generation

Every supported SO-DIMM has two differential clock pairs. There are total of four clock pairs driven directly by the processor to two SO-DIMMs.

System Memory Pre-Charge Power Down Support Details

The IMC supports and enables slow exit DDR3 DRAM Device pre-charge power down

DLL control. During a pre-charge power down, a slow exit is where the DRAM device

DLL is disabled after entering pre-charge power down for potential power savings.

24 Datasheet

Interfaces

2.2

PCI Express Interface

This section describes the PCI Express interface capabilities of the processor. See the

PCI Express Base Specification for details of PCI Express.

The processor has one PCI Express controller that can support one external x16 PCI

Express Graphics Device or two external x8 PCI Express Graphics Devices. The primary

PCI Express Graphics port is referred to as PEG 0 and the secondary PCI Express

Graphics port is referred to as PEG 1.

2.2.1

PCI Express Architecture

Compatibility with the PCI addressing model is maintained to ensure that all existing applications and drivers operate unchanged.

The PCI Express configuration uses standard mechanisms as defined in the PCI

Plug-and-Play specification. The initial recovered clock speed of 1.25 GHz results in

2.5 Gb/s/direction which provides a 250 MB/s communications channel in each direction (500 MB/s total). That is close to twice the data rate of classic PCI. The fact that 8b/10b encoding is used accounts for the 250 MB/s where quick calculations would imply 300 MB/s.

The PCI Express architecture is specified in three layers: Transaction Layer, Data Link

Layer, and Physical Layer. The partitioning in the component is not necessarily along these same boundaries. Refer to Figure 2-4 for the PCI Express Layering Diagram.

Figure 2-4. PCI Express Layering Diagram

Datasheet

PCI Express uses packets to communicate information between components. Packets are formed in the Transaction and Data Link Layers to carry the information from the transmitting component to the receiving component. As the transmitted packets flow through the other layers, they are extended with additional information necessary to handle packets at those layers. At the receiving side, the reverse process occurs and

25

Interfaces packets get transformed from their Physical Layer representation to the Data Link

Layer representation and finally (for Transaction Layer Packets) to the form that can be processed by the Transaction Layer of the receiving device.

Figure 2-5. Packet Flow through the Layers

2.2.1.1

2.2.1.2

2.2.1.3

Transaction Layer

The upper layer of the PCI Express architecture is the Transaction Layer. The

Transaction Layer's primary responsibility is the assembly and disassembly of

Transaction Layer Packets (TLPs). TLPs are used to communicate transactions, such as read and write, as well as certain types of events. The Transaction Layer also manages flow control of TLPs.

Data Link Layer

The middle layer in the PCI Express stack, the Data Link Layer, serves as an intermediate stage between the Transaction Layer and the Physical Layer.

Responsibilities of Data Link Layer include link management, error detection, and error correction.

The transmission side of the Data Link Layer accepts TLPs assembled by the

Transaction Layer, calculates and applies data protection code and TLP sequence number, and submits them to Physical Layer for transmission across the Link. The receiving Data Link Layer is responsible for checking the integrity of received TLPs and for submitting them to the Transaction Layer for further processing. On detection of TLP error(s), this layer is responsible for requesting retransmission of TLPs until information is correctly received, or the Link is determined to have failed. The Data Link Layer also generates and consumes packets which are used for Link management functions.

Physical Layer

The Physical Layer includes all circuitry for interface operation, including driver and input buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedance matching circuitry. It also includes logical functions related to interface initialization and maintenance. The Physical Layer exchanges data with the Data Link Layer in an implementation-specific format, and is responsible for converting this to an appropriate serialized format and transmitting it across the PCI Express Link at a frequency and width compatible with the remote device.

26 Datasheet

Interfaces

2.2.2

PCI Express Configuration Mechanism

The PCI Express (external graphics) link is mapped through a PCI-to-PCI bridge structure.

Figure 2-6. PCI Express Related Register Structures in the Processor

PCI

Express

Device

PEG0

PCI-PCI

Bridge representing root PCI

Express port

(Device 1)

PCI

Compatible

Host Bridge

Device

(Device 0)

2.2.3

DMI

PCI Express extends the configuration space to 4096 bytes per-device/function, as compared to 256 bytes allowed by the Conventional PCI Specification. PCI Express configuration space is divided into a PCI-compatible region (which consists of the first

256 bytes of a logical device's configuration space) and an extended PCI Express region

(which consists of the remaining configuration space). The PCI-compatible region can be accessed using either the mechanisms defined in the PCI specification or using the enhanced PCI Express configuration access mechanism described in the PCI Express

Enhanced Configuration Mechanism section.

The PCI Express Host Bridge is required to translate the memory-mapped PCI Express configuration space accesses from the host processor to PCI Express configuration cycles. To maintain compatibility with PCI configuration addressing mechanisms, it is recommended that system software access the enhanced configuration space using

32-bit operations (32-bit aligned) only. See the PCI Express Base Specification for details of both the PCI-compatible and PCI Express Enhanced configuration mechanisms and transaction rules.

PCI Express Ports and Bifurcation

The external graphics attach (PEG) on the processor is a single, 16-lane (x16) port that can be:

• configured at narrower widths

• bifurcated into two x8 PCI Express ports that may train to narrower widths

The PEG port is being designed to be compliant with the PCI Express Base

Specification, Revision 2.0.

Datasheet 27

Interfaces

2.2.3.1

2.2.3.2

2.3

Note:

2.3.1

2.3.2

2.3.3

PCI Express Bifurcated Mode

When bifurcated, the signals which had previously been assigned to Lanes 15:8 of the single x16 Primary port are reassigned to lanes 7:0 of the x8 Secondary Port. This assignment applies whether the lane numbering is reversed or not. PCI Express Port 0 is mapped to PCI Device 1 and PCI Express Port 1 is mapped to PCI Device 6.

Static Lane Numbering Reversal

Does not support dynamic lane reversal, as defined (optional) by the PCI Express Base

Specification.

PCI Express 1x16 configuration:

•

Normal (1x16): PEG_RX[15:0]; PEG_TX[15:0]

• Reversal (1x16): PEG_RX[0:15]; PEG_TX[0:15]

DMI

DMI connects the processor and the PCH chip-to-chip. DMI2 is supported. The DMI is similar to a four-lane PCI Express supporting up to 1 GB/s of bandwidth in each direction.

Only DMI x4 configuration is supported.

DMI Error Flow

DMI can only generate SERR in response to errors, never SCI, SMI, MSI, PCI INT, or

GPE. Any DMI related SERR activity is associated with Device 0.

Processor/PCH Compatibility Assumptions

The processor is compatible with the PCH and is not compatible with any previous

(G)MCH or ICH products.

DMI Link Down

The DMI link going down is a fatal, unrecoverable error. If the DMI data link goes to data link down, after the link was up, then the DMI link hangs the system by not allowing the link to retrain to prevent data corruption. This is controlled by the PCH.

Downstream transactions that had been successfully transmitted across the link prior to the link going down may be processed as normal. No completions from downstream, non-posted transactions are returned upstream over the DMI link after a link down event.

28 Datasheet

Interfaces

2.4

Intel® HD Graphics Controller

This section details the 2D, 3D and video pipeline and their respective capabilities.

The integrated graphics is powered by a refresh of the fifth generation graphics core and supports twelve, fully-programmable execution cores. Full-precision, floating-point operations are supported to enhance the visual experience of compute-intensive applications.The integrated graphics controller contains several types of components; the graphics engines, planes, pipes, port and the Intel FDI. The integrated graphics has a 3D/2D Instruction Processing unit to control the 3D and 2D engines respectively. The integrated graphics controller’s 3D and 2D engines are fed with data through the IMC.

The outputs of the graphics engine are surfaces sent to memory, which are then retrieved and processed by the planes. The surfaces are then blended in the pipes and the display timings are transitioned from display core clock to the pixel (dot) clock.

Figure 2-7. Integrated Graphics Controller Unit Block Diagram

Video Engine

2D Engine

3D Engine

Vertex Fetch/Vertex

Shader

Geometry Shader

Clipper

Strip & Fan/Setup

Windower/IZ

Memory

Plane A

Sprite A

Cursor A

VGA

Plane B

Sprite B

Cursor B eDP

Alpha

Blend/

Gamma

/Panel

Fitter

Pipe A

Pipe B

M

U

X

Intel®

FDI

2.4.1

2.4.1.1

3D and Video Engines for Graphics Processing

The 3D graphics pipeline architecture simultaneously operates on different primitives or on different portions of the same primitive. All the cores are fully programmable, increasing the versatility of the 3D Engine. The Gen 5.75 3D engine provides the following performance and power-management enhancements:

•

Execution units (EUs) increased to 12 from the previous 10 EUsin Gen 5.0.

• Includes Hierarchal-Z

•

Includes video quality enhancements

3D Engine Execution Units

•

Support 12 EUs. The EUs perform 128-bit wide execution per clock.

Datasheet 29

Interfaces

2.4.1.2

2.4.1.2.1

2.4.1.2.2

2.4.1.2.3

2.4.1.2.4

2.4.1.2.5

2.4.1.2.6

•

Support SIMD8 instructions for vertex processing and SIMD16 instructions for pixel processing.

3D Pipeline

Vertex Fetch (VF) Stage

The VF stage executes 3DPRIMITIVE commands. Some enhancements have been included to better support legacy D3D APIs as well as SGI OpenGL*.

Vertex Shader (VS) Stage

The VS stage performs shading of vertices output by the VF function. The VS unit produces an output vertex reference for every input vertex reference received from the

VF unit, in the order received.

Geometry Shader (GS) Stage

The GS stage receives inputs from the VS stage. Compiled application-provided GS programs, specifying an algorithm to convert the vertices of an input object into some output primitives. For example, a GS shader may convert lines of a line strip into polygons representing a corresponding segment of a blade of grass centered on the line. Or it could use adjacency information to detect silhouette edges of triangles and output polygons extruding out from the edges.

Clip Stage

The Clip stage performs general processing on incoming 3D objects. However, it also includes specialized logic to perform a Clip Test function on incoming objects. The Clip

Test optimizes generalized 3D Clipping. The Clip unit examines the position of incoming vertices, and accepts/rejects 3D objects based on its Clip algorithm.

Strips and Fans (SF) Stage

The SF stage performs setup operations required to rasterize 3D objects. The outputs from the SF stage to the Windower stage contain implementation-specific information required for the rasterization of objects and also supports clipping of primitives to some extent.

Windower/IZ (WIZ) Stage

The WIZ unit performs an early depth test, which removes failing pixels and eliminates unnecessary processing overhead.

The Windower uses the parameters provided by the SF unit in the object-specific rasterization algorithms. The WIZ unit rasterizes objects into the corresponding set of pixels. The Windower is also capable of performing dithering, whereby the illusion of a higher resolution when using low-bpp channels in color buffers is possible. Color dithering diffuses the sharp color bands seen on smooth-shaded objects.

30 Datasheet

Interfaces

2.4.1.3

2.4.1.4

2.4.1.4.1

2.4.1.4.2

Video Engine

The Video Engine handles the non-3D (media/video) applications. It includes support for VLD and MPEG2 decode in hardware.

2D Engine

The 2D Engine contains BLT (Block Level Transfer) functionality and an extensive set of

2D instructions. To take advantage of the 3D during engine’s functionality, some BLT functions make use of the 3D renderer.

Integrated Graphics VGA Registers

The 2D registers consists of original VGA registers and others to support graphics modes that have color depths, resolutions, and hardware acceleration features that go beyond the original VGA standard.

Logical 128-Bit Fixed BLT and 256 Fill Engine

This BLT engine accelerates the GUI of Microsoft Windows* operating systems. The

128-bit BLT engine provides hardware acceleration of block transfers of pixel data for many common Windows operations. The BLT engine can be used for the following:

• Move rectangular blocks of data between memory locations

•

Data alignment

• To perform logical operations (raster ops)

The rectangular block of data does not change, as it is transferred between memory locations. The allowable memory transfers are between: cacheable system memory and frame buffer memory, frame buffer memory and frame buffer memory, and within system memory. Data to be transferred can consist of regions of memory, patterns, or solid color fills. A pattern is always 8 x 8 pixels wide and may be 8, 16, or 32 bits per pixel.

The BLT engine expands monochrome data into a color depth of 8, 16, or 32 bits. BLTs can be either opaque or transparent. Opaque transfers move the data specified to the destination. Transparent transfers compare destination color to source color and write according to the mode of transparency selected.

Data is horizontally and vertically aligned at the destination. If the destination for the

BLT overlaps with the source memory location, the BLT engine specifies which area in memory to begin the BLT transfer. Hardware is included for all 256 raster operations

(source, pattern, and destination) defined by Microsoft, including transparent BLT.

The BLT engine has instructions to invoke BLT and stretch BLT operations, permitting software to set up instruction buffers and use batch processing. The BLT engine can perform hardware clipping during BLTs.

Datasheet 31

Interfaces

2.4.2

Integrated Graphics Display Pipes

The integrated graphics controller display pipe can be broken down into three components:

• Display Planes

•

Display Pipes

• Embedded DisplayPort and Intel FDI

Figure 2-8. Processor Display Block Diagram

Plane A

eDP

Sprite A

Pipe A

Cursor A

VGA

Plane B

Alpha

Blend/

Gamma/

Panel

Fitter

M

U

X

Intel®

FDI

Pipe B

Sprite B

Cursor B

2.4.2.1

2.4.2.1.1

2.4.2.1.2

Display Planes

A display plane is a single displayed surface in memory and contains one image

(desktop, cursor, overlay). It is the portion of the display HW logic that defines the format and location of a rectangular region of memory that can be displayed on display output device and delivers that data to a display pipe. This is clocked by the Core

Display Clock.

Planes A and B

Planes A and B are the main display planes and are associated with Pipes A and B respectively. The two display pipes are independent, allowing for support of two independent display streams. They are both double-buffered, which minimizes latency and improves visual quality.

Sprite A and B

Sprite A and Sprite B are planes optimized for video decode, and are associated with

Planes A and B respectively. Sprite A and B are also double-buffered.

32 Datasheet

Interfaces

2.4.2.1.3

Cursors A and B

Cursors A and B are small, fixed-sized planes dedicated for mouse cursor acceleration, and are associated with Planes A and B respectively. These planes support resolutions up to 256 x 256 each.

2.4.2.1.4

2.4.2.2

VGA

Used for boot, safe mode, legacy games, etc. Can be changed by an application without

OS/driver notification, due to legacy requirements.

Display Pipes

The display pipe blends and synchronizes pixel data received from one or more display planes and adds the timing of the display output device upon which the image is displayed. This is clocked by the Display Reference clock inputs.

The display pipes A and B operate independently of each other at the rate of 1 pixel per clock. They can attach to any of the display ports. Each pipe sends display data to the

PCH over the Intel Flexible Display Interface (Intel FDI).

2.4.2.3

2.4.2.4

Display Ports

The display ports consist of output logic and pins that transmit the display data to the associated encoding logic and send the data to the display device (i.e., LVDS, HDMI,

DVI, SDVO, etc.). All display interfaces connecting external displays are now repartitioned and driven from the PCH with the exception of the eDP DisplayPort.

Embedded DisplayPort (eDP)

The DisplayPort abbreviated as DP (different than the generic term display port) specification is a VESA standard. DisplayPort consolidates internal and external connection methods to reduce device complexity, support cross industry applications, and provide performance scalability. The integrated graphics supports an embedded

DisplayPort (eDP) interface for display devices that are integrated into the system

(e.g., laptop LCD panel). All other display interfaces connecting to the LVDS or external panels are driven from the PCH.

The eDP interface is physically shared with a subset of the PCIe interface. Specifically, eDP[3:0] map to Logical Lanes PEG[12:15] of the PCIe interface. Mapping for reversed case is: eDP[3:0] maps to PEG[3:0], ex: eDP[0]=PEG[15] in non reversed case. In reversed case: eDP[0] = PEG[0].

Table 2-3. eDP/PEG Ball Mapping eDP Signal eDP_AUX eDP_AUX# eDP_HPD#

PEG Signal

PEG_RX[13]

PEG_RX#[13]

PEG_RX[12]

Lane Reversal

PEG_RX[2]

PEG_RX#[2]

PEG_RX[3]

Datasheet 33

Interfaces

Table 2-3. eDP/PEG Ball Mapping eDP Signal eDP_TX[0] eDP_TX#[0] eDP_TX[1] eDP_TX#[1] eDP_TX[2] eDP_TX#[2] eDP_TX[3] eDP_TX#[3]

PEG Signal

PEG_TX[15]

PEG_TX#[15]

PEG_TX[14]

PEG_TX#[14]

PEG_TX[13]

PEG_TX#[13]

PEG_TX[12]

PEG_TX#[12]

Lane Reversal

PEG_TX[0]

PEG_TX#[0]

PEG_TX[1]

PEG_TX#[1]

PEG_TX[2]

PEG_TX#[2]

PEG_TX[3]

PEG_TX#[3]

When eDP is enabled, the lower logical lanes are still available for standard PCIe devices, using the PEG 0 controller. PEG 0 is limited to x1. The board manufacture chooses whether to use eDP and whether to use lane numbering reversal.

The eDP interface supports link-speeds of 1.62 Gbps and 2.7 Gbps on 1, 2 or 4 data lanes. The eDP and PCI Express x1 may be supported concurrently. eDP interface may support -0.5% SSC and non-SSC clock settings.

2.4.3

Intel Flexible Display Interface

The Intel Flexible Display Interface (Intel FDI) is a proprietary link for carrying display traffic from the integrated graphics controller to the PCH display I/O’s. Intel FDI supports two independent channels; one for pipe A and one for pipe B.

•

Each channel has four transmit (Tx) differential pairs used for transporting pixel and framing data from the display engine.

• Each channel has one single-ended LineSync and one FrameSync input (1-V CMOS signaling).

•

One display interrupt line input (1-V CMOS signaling).

• Intel FDI may dynamically scalable down to 2X or 1X based on actual display bandwidth requirements.

•

Common 100-MHz reference clock is sent to both processor and PCH.

• Each channel transports at a rate of 2.7 Gbps.

•

PCH supports end-to-end lane reversal across both channels (no reversal support required)

2.5

Platform Environment Control Interface (PECI)

The PECI is a one-wire interface that provides a communication channel between a

PECI client (processor) and a PECI master, usually the PCH. The processor implements a PECI interface to:

34 Datasheet

Interfaces

2.6

2.6.1

•

Allow communication of processor thermal and other information to the PECI master.

• Read averaged Digital Thermal Sensor (DTS) values for fan speed control.

Interface Clocking

Internal Clocking Requirements

Table 2-4. Processor Reference Clocks

Reference Input Clocks

BCLK/BCLK#

PEG_CLK/PEG_CLK#

DPLL_REF_SSCLK/DPLL_REF_SSCLK#

Input Frequency

133 MHz

100 MHz

120 MHz

Associated PLL

Processor/Memory/Graphics

PCI Express*/DMI/Intel® FDI

Embedded DisplayPort* (eDP)

§

Datasheet 35

Technologies

3

3.1

3.1.1

3.1.2

36

Technologies

Intel

®

Virtualization Technology

Intel Virtualization Technology (Intel VT) makes a single system appear as multiple independent systems to software. This allows multiple, independent operating systems to run simultaneously on a single system. Intel VT comprises technology components to support virtualization of platforms based on Intel architecture microprocessors and chipsets. Intel Virtualization Technology (Intel VT-x) added hardware support in the processor to improve the virtualization performance and robustness. Intel Virtualization

Technology for Directed I/O (Intel VT-d) adds chipset hardware implementation to support and improve I/O virtualization performance and robustness.

Intel VT-x specifications and functional descriptions are included in the Intel ® 64 and

IA-32 Architectures Software Developer’s Manual, Volume 3B and is available at: http://www.intel.com/products/processor/manuals/index.htm.

Intel® VT-x Objectives

Intel VT-x provides hardware acceleration for virtualization of IA platforms. Virtual

Machine Monitor (VMM) can use Intel VT-x features to provide improved reliable virtualized platforms. By using Intel VT-x, a VMM is:

• Robust—VMMs no longer need to use paravirtualization or binary translation. This means that they will be able to run off-the-shelf OSs and applications without any special steps.

• Enhanced—Intel VT enables VMMs to run 64-bit guest operating systems on IA x86 processors.

• More reliable—Due to the hardware support, VMMs can now be smaller, less complex, and more efficient. This improves reliability and availability and reduces the potential for software conflicts.

• More secure—The use of hardware transitions in the VMM strengthens the isolation of VMs and further prevents corruption of one VM from affecting others on the same system.

Intel

®

VT-x Features

The processor core supports the following Intel VT-x features:

• Extended Page Tables (EPT)

— EPT is hardware assisted page table virtualization

— It eliminates VM exits from guest OS to the VMM for shadow page-table maintenance

• Virtual Processor IDs (VPID)

— Ability to assign a VM ID to tag processor core hardware structures (such as

Datasheet

Technologies

3.2

Note:

TLBs)

— This avoids flushes on VM transitions to give a lower-cost VM transition time and an overall reduction in virtualization overhead.

• Guest Preemption Timer

— Mechanism for a VMM to preempt the execution of a guest OS after an amount of time specified by the VMM. The VMM sets a timer value before entering a guest

— The feature aids VMM developers in flexibility and Quality of Service (QoS) guarantees

• Descriptor-Table Exiting

— Descriptor-table exiting allows a VMM to protect a guest OS from internal

(malicious software based) attack by preventing relocation of key system data structures like IDT (interrupt descriptor table), GDT (global descriptor table),

LDT (local descriptor table), and TSS (task segment selector).

— A VMM using this feature can intercept (by a VM exit) attempts to relocate these data structures and prevent them from being tampered by malicious software.

Intel Graphics Dynamic Frequency

Graphics render frequency are selected by the Intel graphics driver dynamically based on graphics workload demand as permitted by Intel Turbo Boost Technology Driver. The processor core die and the integrated graphics and memory controller core die have an individual TDP limit. If one component is not consuming enough thermal power to reach its TDP, the other component can increase its TDP limit and take advantage of the unused thermal power headroom. For the integrated graphics, this could mean an increase in the render core frequency (above its rated frequency) and increased graphics performance.

Please note that processor Turbo is not supported on Celeron processor skus.

Processor Utilization of Intel Graphics Dynamic Frequency require the following

•

Graphics driver

• Intel Turbo Boost Technology Driver

Enabling Intel Turbo Boost Technology and Intel Graphics Dynamic Frequency will maximize the performance of the GPU within its specified power levels. Compared with previous generation products, Intel Turbo Boost Technology and Intel Graphics

Dynamic Frequency will increase the ratio of application power to TDP. Thus, thermal solutions and platform cooling that are designed to less than thermal design guidance might experience thermal and performance issues since more applications will tend to run at the maximum power limit for significant periods of time. For more details, refer to Chapter 5, “Thermal Management” .

§

Datasheet 37

Power Management

4 Power Management

This chapter provides information on the following power management topics:

•

ACPI States

• Processor Core

•

Integrated Memory Controller (IMC)

• PCI Express

•

Direct Media Interface (DMI)

• Integrated Graphics Controller

4.1

ACPI States Supported

The ACPI states supported by the processor are described in this section.

4.1.1

System States

Table 4-5. System States

State

G0/S0

G1/S3-Cold

G1/S4

G2/S5

G3

Description

Full On

Suspend-to-RAM (STR). Context saved to memory (S3-Hot is not supported by the processor).

Suspend-to-Disk (STD). All power lost (except wakeup on PCH).

Soft off. All power lost (except wakeup on PCH). Total reboot.

Mechanical off. All power (AC and battery) removed from system.

4.1.2

Processor Core/Package Idle States

Table 4-6. Processor Core/Package State Support

State

C0

C1

C1E

C3

C6

Description

Active mode, processor executing code.

AutoHALT state.

AutoHALT state with lowest frequency and voltage operating point.

Execution cores in C3 flush their L1 instruction cache, L1 data cache, and L2 cache to the L3 shared cache. Clocks are shut off to each core.

Execution cores in this state save their architectural state before removing core voltage.

38 Datasheet

Power Management

4.1.3

Integrated Memory Controller States

Table 4-7. Integrated Memory Controller States

State

Power up

Pre-charge Power down

Active Power down

Self-Refresh

Description

CKE asserted. Active mode.

CKE deasserted (not self-refresh) with all banks closed.

CKE deasserted (not self-refresh) with minimum one bank active.

CKE deasserted using device self-refresh.

4.1.4

PCIe Link States

Table 4-8. PCIe Link States

State

L0

L0s

L1

L3

4.1.5

DMI States

Description

Full on – Active transfer state.

First Active Power Management low power state – Low exit latency.

Lowest Active Power Management - Longer exit latency.

Lowest power state (power-off) – Longest exit latency.

Table 4-9. DMI States

State

L0

L0s

L1

L3

4.1.6

Description

Full on – Active transfer state.

First Active Power Management low power state – Low exit latency.

Lowest Active Power Management - Longer exit latency.

Lowest power state (power-off) – Longest exit latency.

Integrated Graphics Controller States

Table 4-10.Integrated Graphics Controller States

State

D0

D3 Cold

Full on, display active.

Power-off.

Description

Datasheet 39

Power Management

4.1.7

Interface State Combinations

Table 4-11.G, S and C State Combinations

Global

(G) State

G1

G1

G2

G3

G0

G0

G0

G0

Sleep

(S) State

S3

S4

S5

NA

S0

S0

S0

S0

Processor

Core

(C) State

C0

C1/C1E

C3

C6

Power off

Power off

Power off

Power off

Processor

State

System Clocks Description

Full On

Auto-Halt

Deep Sleep

Deep Power

Down

On

On

On

On

Full On

Auto-Halt

Deep Sleep

Deep Power Down

Off, except RTC Suspend to RAM

Off, except RTC Suspend to Disk

Off, except RTC Soft Off

Power off Hard off

Table 4-12.D, S, and C State Combination

Graphics Adapter

(D) State

D0

D0

D0

D0

Sleep (S) State

S0

S0

S0

S0

D3

D3

D3

S0

S3

S4

Package (C) State

C0

C1/C1E

C3

C6

Any

N/A

N/A

Description

Full On, Displaying

Auto-Halt, Displaying

Deep sleep, Displaying

Deep Power Down,

Displaying

Not displaying

Not displaying, Graphics

Core is powered off

Not displaying, suspend to disk

4.2

Processor Core Power Management

While executing code, Enhanced Intel SpeedStep Technology optimizes the processor’s frequency and core voltage based on workload. Each frequency and voltage operating point is defined by ACPI as a P-state. When the processor is not executing code, it is idle. A low-power idle state is defined by ACPI as a C-state. In general, lower power

C-states have longer entry and exit latencies.

40 Datasheet

Power Management

4.2.1

4.2.2

Enhanced Intel SpeedStep® Technology

The following are the key features of Enhanced Intel SpeedStep Technology:

• Multiple frequency and voltage points for optimal performance and power efficiency. These operating points are known as P-states.

•

Frequency selection is software controlled by writing to processor MSRs. The voltage is optimized based on the selected frequency and the number of active processor cores.

— If the target frequency is higher than the current frequency, V

CC

is ramped up in steps to an optimized voltage. This voltage is signaled by the VID[6:0] pins to the voltage regulator. Once the voltage is established, the PLL locks on to the target frequency.

— If the target frequency is lower than the current frequency, the PLL locks to the target frequency, then transitions to a lower voltage by signaling the target voltage on the VID[6:0] pins.

— All active processor cores share the same frequency and voltage. In a multi-core processor, the highest frequency P-state requested amongst all active cores is selected.

— Software-requested transitions are accepted at any time. If a previous transition is in progress, the new transition is deferred until the previous transition is completed.

• The processor controls voltage ramp rates internally to ensure glitch-free transitions.

•

Because there is low transition latency between P-states, a significant number of transitions per-second are possible.

Low-Power Idle States

When the processor is idle, low-power idle states (C-states) are used to save power.

More power savings actions are taken for numerically higher C-states. However, higher

C-states have longer exit and entry latencies. Resolution of C-states occur at the thread, processor core, and processor package level. Thread-level C-states are available if Intel Hyper-Threading Technology is enabled.

Datasheet 41

42

Figure 4-9. Idle Power Management Breakdown of the Processor Cores

Thread 0 Thread 0

Core 0 State Core 1 State

Power Management

Processor Package State

Entry and exit of the C-States at the thread and core level are shown in below figure.

Figure 4-10.Thread and Core C-State Entry and Exit

MWAIT(C1), HLT

MWAIT(C1), HLT

(C1E Enabled)

MWAIT(C3),

P_LV2 I/O Read

MWAIT(C6),

P_LVL3 I/O Read

C1 C1E C3 C6

While individual threads can request low power C-states, power saving actions only take place once the core C-state is resolved. Core C-states are automatically resolved by the processor. For thread and core C-states, a transition to and from C0 is required before entering any other C-state.

Datasheet

Power Management

Table 4-13.Coordination of Thread Power States at the Core Level

Thread 1

Processor Core

C-State

C0

C1

C3

C6

C0

C0

C0

C0

C0

C1

C0

C1

1

C1 1

C1

1

C3

C0

C1

1

C3

C3

C6

C0

C1

1

C3

C6

NOTE:If enabled, the core C-state will be C1E if all actives cores have also resolved a core C1 state or higher

4.2.3

Note:

Requesting Low-Power Idle States

The primary software interfaces for requesting low power idle states are through the

MWAIT instruction with sub-state hints and the HLT instruction (for C1 and C1E).

However, software may make C-state requests using the legacy method of I/O reads from the ACPI-defined processor clock control registers, referred to as P_LVLx. This method of requesting C-states provides legacy support for operating systems that initiate C-state transitions via I/O reads.

For legacy operating systems, P_LVLx I/O reads are converted within the processor to the equivalent MWAIT C-state request. Therefore, P_LVLx reads do not directly result in

I/O reads to the system. The feature, known as I/O MWAIT redirection, must be enabled in the BIOS.

The P_LVLx I/O Monitor address needs to be set up before using the P_LVLx I/O read interface. Each P-LVLx is mapped to the supported MWAIT(Cx) instruction as follows.

Table 4-14.P_LVLx to MWAIT Conversion

P_LVLx

P_LVL2

MWAIT(Cx)

MWAIT(C3)

P_LVL3 MWAIT(C6)

Notes

The P_LVL2 base address is defined in the PMG_IO_CAPTURE

MSR, described in the RS - Nehalem Processor Family BWG.

C6. No sub-states allowed.

Note:

The BIOS can write to the C-state range field of the PMG_IO_CAPTURE MSR to restrict the range of I/O addresses that are trapped and emulate MWAIT like functionality. Any

P_LVLx reads outside of this range does not cause an I/O redirection to MWAIT(Cx) like request. They fall through like a normal I/O instruction.

When P_LVLx I/O instructions are used, MWAIT substates cannot be defined. The

MWAIT substate is always zero if I/O MWAIT redirection is used. By default, P_LVLx I/O redirections enable the MWAIT 'break on EFLAGS.IF’ feature which triggers a wakeup on an interrupt even if interrupts are masked by EFLAGS.IF.

Datasheet 43

Power Management

4.2.4

4.2.4.1

4.2.4.2

4.2.4.3

Core C-states

The following are general rules for all core C-states, unless specified otherwise:

• A core C-State is determined by the lowest numerical thread state (e.g., Thread 0 requests C1E while Thread 1 requests C3, resulting in a core C1E state). See

Table 4-11 .

•

A core transitions to C0 state when:

— An interrupt occurs

— There is an access to the monitored address if the state was entered via an

MWAIT instruction

• For core C1/C1E, and core C3, an interrupt directed toward a single thread wakes only that thread. However, since both threads are no longer at the same core

C-state, the core resolves to C0.

•

For core C6, an interrupt coming into either thread wakes both threads into C0 state.

• Any interrupt coming into the processor package may wake any core.

Core C0 State

The normal operating state of a core where code is being executed.

Core C1/C1E State

C1/C1E is a low power state entered when all threads within a core execute a HLT or

MWAIT(C1/C1E) instruction.

A System Management Interrupt (SMI) handler returns execution to either Normal state or the C1/C1E state. See the Intel

®

64 and IA-32 Architecture Software

Developer’s Manual, Volume 3A/3B: System Programmer’s Guide for more information.

While a core is in C1/C1E state, it processes bus snoops and snoops from other threads. For more information on C1E, see “Package C1/C1E” .

Core C3 State

Individual threads of a core can enter the C3 state by initiating a P_LVL2 I/O read to the P_BLK or an MWAIT(C3) instruction. A core in C3 state flushes the contents of its

L1 instruction cache, L1 data cache, and L2 cache to the shared L3 cache, while maintaining its architectural state. All core clocks are stopped at this point. Because the core’s caches are flushed, the processor does not wake any core that is in the C3 state when either a snoop is detected or when another core accesses cacheable memory.

44 Datasheet

Power Management

4.2.4.4

4.2.4.5

4.2.5

Core C6 State

Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or an

MWAIT(C6) instruction. Before entering core C6, the core will save its architectural state to a dedicated SRAM. Once complete, a core will have its voltage reduced to zero volts. During exit, the core is powered on and its architectural state is restored.

C-State Auto-Demotion

In general, deeper C-states such as Deep Power Down Technology (code named C6 state) have long latencies and have higher energy entry/exit costs. The resulting performance and energy penalties become significant when the entry/exit frequency of a deeper C-state is high. Therefore incorrect or inefficient usage of deeper C-states have a negative impact on battery life. In order to increase residency and improve battery life in deeper C-states, the processor supports C-state auto-demotion.

There are two C-State auto-demotion options:

•

Deep Power Down Technology (code named C6 state) to C3

• Deep Power Down Technology (code named C6 state)/C3 To C1

The decision to demote a core from Deep Power Down Technology (code named C6 state) to C3 or C3/Deep Power Down Technology (code named C6 state) to C1 is based on each core’s immediate residency history. Upon each core Deep Power Down

Technology (code named C6 state) request, the core C-state is demoted to C3 or C1 until a sufficient amount of residency has been established. At that point, a core is allowed to go into C3/Deep Power Down Technology (code named C6 state). Each option can be run concurrently or individually.

This feature is disabled by default.

Package C-States

The processor supports C0, C1/C1E, C3, and Deep Power Down Technology (code named C6 state) package idle power states. The following is a summary of the general rules for package C-state entry. These apply to all package C-states unless specified otherwise:

•

A package C-state request is determined by the lowest numerical core C-state amongst all cores.

• A package C-state is automatically resolved by the processor depending on the core idle power states and the status of the platform components.

— Each core can be at a lower idle power state than the package if the platform does not grant the processor permission to enter a requested package C-state.

— The platform may allow additional power savings to be realized in the processor.

Refer to Section 4.3.2.2

•

For package C-states, the processor is not required to enter C0 before entering any other C-state.

Datasheet 45

46

Power Management

The processor exits a package C-state when a break event is detected. Depending on the type of break event, the processor does the following:

• If a core break event is received, the target core is activated and the break event message is forwarded to the target core.

— If the break event is not masked, the target core enters the core C0 state and the processor enters package C0.

— If the break event is masked, the processor attempts to re-enter its previous package state.

•

If the break event was due to a memory access or snoop request.

— But the platform did not request to keep the processor in a higher package Cstate, the package returns to its previous C-state.

— And the platform requests a higher power C-state, the memory access or snoop request is serviced and the package remains in the higher power C-state.

Table 4-15 shows package C-state resolution for a dual-core processor. Figure 4-11 summarizes package C-state transitions.

Table 4-15.Coordination of Core Power States at the Package Level

Core 1

Package C-State

C0

C1

C3

C6

C0

C0

C0

C0

C0

C1

C0

C1

C1

C1

1

1

1

C3

C0

C1

C3

C3

1

Deep Power

Down

Technology

(code named

C6 state)

C0

C1

C3

C6

1

NOTE:

1.

If enabled, the package C-state will be C1E if all actives cores have resolved a core C1 state or higher.

Datasheet

Power Management

Figure 4-11.Package C-State Entry and Exit

C0

C3

C1 C6

4.2.5.1

4.2.5.2

Package C0

The normal operating state for the processor. The processor remains in the normal state when at least one of its cores is in the C0 or C1 state or when the platform has not granted permission to the processor to go into a low power state. Individual cores may be in lower power idle states while the package is in C0.

Package C1/C1E

No additional power reduction actions are taken in the package C1 state. However, if the C1E sub-state is enabled, the processor automatically transitions to the lowest supported core clock frequency, followed by a reduction in voltage.

The package enters the C1 low power state when:

• At least one core is in the C1 state.

•

The other cores are in a C1 or lower power state.

The package enters the C1E state when:

•

All cores have directly requested C1E via MWAIT(C1) with a C1E sub-state hint.

• All cores are in a power state lower that C1/C1E but the package low power state is limited to C1/C1E via the PMG_CST_CONFIG_CONTROL MSR.

•

All cores have requested C1 using HLT or MWAIT(C1) and C1E auto-promotion is enabled in IA32_MISC_ENABLES.

Datasheet 47

Power Management

4.2.5.3

4.2.5.4

4.2.5.5

4.3

No notification to the system occurs upon entry to C1/C1E.

Package C3 State

A processor enters the package C3 low power state when:

• At least one core is in the C3 state.

•

The other cores are in a C3 or lower power state, and the processor has been granted permission by the platform.

• The platform has not granted a request to a package C6 state but has allowed a package C6 state.

In package C3-state, the L3 shared cache is snoopable.

Package C6 State

A processor enters the package C6 low power state when:

• At least one core is in the C6 state.

•

The other cores are in a C6 or lower power state, and the processor has been granted permission by the platform.

In package C6 state, all cores have saved their architectural state and have had their core voltages reduced to zero volts. The L3 shared cache is still powered and snoopable in this state. The processor remains in package C6 state as long as any part of the L3 cache is active.

Power Status Indicator (PSI#) and DPRSLPVR#

PSI# and DPRSLPVR# are signals used to optimize VR efficiency over a wide power range depending on amount of activity within the processor core. The PSI# signal is utilized by the processor core to:

•

Improve intermediate and light load efficiency of the voltage regulator when the processor is active (P-states).

• Optimize voltage regulator efficiency in very low power states. Assertion of

DPRSLPVR# indicates that the processor core is in a C6 low power state.

The VR efficiency gains result in overall platform power savings and extended battery life.

IMC Power Management

The main memory is power managed during normal operation and in low-power ACPI

Cx states.

48 Datasheet

Power Management

4.3.1

4.3.2

4.3.2.1

4.3.2.2

Disabling Unused System Memory Outputs

Any system memory (SM) interface signal that goes to a memory module connector in which it is not connected to any actual memory devices (such as SO-DIMM connector is unpopulated, or is single-sided) is tri-stated. The benefits of disabling unused SM signals are:

• Reduced power consumption.

•

Reduced possible overshoot/undershoot signal quality issues seen by the processor

I/O buffer receivers caused by reflections from potentially un-terminated transmission lines.

When a given rank is not populated, the corresponding chip select and CKE signals are not driven.

At reset, all rows must be assumed to be populated, until it can be proven that they are not populated. This is due to the fact that when CKE is tristated with an SO-DIMM present, the SO-DIMM is not guaranteed to maintain data integrity.

DRAM Power Management and Initialization

The processor implements extensive support for power management on the SDRAM interface. There are four SDRAM operations associated with the Clock Enable (CKE) signals, which the SDRAM controller supports. The processor drives four CKE pins to perform these operations.

Initialization Role of CKE

During power-up, CKE is the only input to the SDRAM that has its level is recognized

(other than the DDR3 reset pin) once power is applied. It must be driven LOW by the

DDR controller to make sure the SDRAM components float DQ and DQS during powerup. CKE signals remain LOW (while any reset is active) until the BIOS writes to a configuration register. Using this method, CKE is guaranteed to remain inactive for much longer than the specified 200 micro-seconds after power and clocks to SDRAM devices are stable.

Conditional Self-Refresh

The processor conditionally places memory into self-refresh in the package C3 and C6 low-power states.

When entering the Suspend-to-RAM (STR) state, the processor core flushes pending cycles and then enters all SDRAM ranks into self refresh. In STR, the CKE signals remain LOW so the SDRAM devices perform self-refresh.

The target behavior is to enter self-refresh for the package C3 and C6 states as long as there are no memory requests to service. The target usage is shown in Table 4-16 .

Datasheet 49

Power Management

Table 4-16.Targeted Memory State Conditions

Mode Memory State with Internal Graphics

C0, C1, C1E Dynamic memory rank power down based on idle conditions.

C3, C6 If the internal graphics engine is idle and there are no pending display requests when in single display mode, then enter self-refresh.

Otherwise use dynamic memory rank power down based on idle conditions.

S3

S4

Self-Refresh Mode.

Memory power down (contents lost).

Memory State with External Graphics

Dynamic memory rank power down based on idle conditions.

If there are no memory requests, then enter self-refresh. Otherwise use dynamic memory rank power down based on idle conditions.

Self-Refresh Mode.

Memory power down (contents lost)

4.3.2.3

Dynamic Power Down Operation

Dynamic power-down of memory is employed during normal operation. Based on idle conditions, a given memory rank may be powered down. The IMC implements aggressive CKE control to dynamically put the DRAM devices in a power down state.

The processor core controller can be configured to put the devices in active power down

(CKE deassertion with open pages) or precharge power down (CKE deassertion with all pages closed). Precharge power down provides greater power savings but has a bigger performance impact, since all pages will first be closed before putting the devices in power down mode.

If dynamic power-down is enabled, all ranks are powered up before doing a refresh cycle and all ranks are powered down at the end of refresh.

4.3.2.4

DRAM I/O Power Management

Unused signals should be disabled to save power and reduce electromagnetic interference. This includes all signals associated with an unused memory channel.

Clocks can be controlled on a per SO-DIMM basis. Exceptions are made for per SO-

DIMM control signals such as CS#, CKE, and ODT for unpopulated SO-DIMM slots.

The I/O buffer for an unused signal should be tri-stated (output driver disabled), the input receiver (differential sense-amp) should be disabled, and any DLL circuitry related ONLY to unused signals should be disabled. The input path must be gated to prevent spurious results due to noise on the unused signals (typically handled automatically when input receiver is disabled).

4.4

PCIe Power Management

•

Active power management support using L0s, and L1 states.

• All inputs and outputs disabled in L2/L3 Ready state.

50 Datasheet

Power Management

4.5

4.6

4.6.1

4.6.2

4.6.3

4.6.4

DMI Power Management

Active power management support using L0s/L1 state.

Integrated Graphics Power Management

Intel

®

(Intel

Display Power Saving Technology 5.0

®

DPST 5.0)

Intel DPST maintains visual experience by managing display image brightness and contrast while adaptively dimming the backlight. As a result, the display backlight power can be reduced by up to 25% depending on Intel DPST settings and system use.

Intel DPST 5.0 provides enhanced image quality over the previous version of Intel

DPST.

Graphics Render C-State

Render C-State (RC6) is a technique designed to optimize the average power to the graphics render engine during times of idleness of the render engine. RC6 is entered when the graphics render engine, blitter engine and the video engine have no workload being currently worked on and no outstanding graphics memory transactions. When the render engine idleness condition is met: The graphics VR will lower the graphics voltage rail (V

AXG

) into a lower voltage state (0.3 V).The render frequency clock will shut down.

Graphics Performance Modulation Technology

Graphics Performance Modulation Technology (GPMT) is a method for optimizing the power efficiency in the graphics render engine while continuing to render 3D objects during battery operation. The GPMT feature will dynamically switch the render frequency based on the render workload, on power policy, skew, and environmental conditions.

Intel

®

Smart 2D Display Technology (Intel

®

S2DDT)

Intel S2DDT reduces display refresh memory traffic by reducing memory reads required for display refresh. Power consumption is reduced by less accesses to the IMC.

Intel S2DDT is most effective with:

•

Display images well suited to compression, such as text windows, slide shows, etc.

Poor examples are 3D games.

• Static screens such as screens with significant portions of the background showing

2D applications, CPU benchmarks, etc., or conditions when the CPU is idle. Poor examples are full-screen 3D games and benchmarks that flip the display image at or near display refresh rates.

Datasheet 51

Power Management

4.7

Thermal Power Management

•

See Section 5, “Thermal Management” on page 53 for all graphics thermal power management-related features.

§

52 Datasheet

Thermal Management

5 Thermal Management

A multi-chip package (MCP) processor requires a thermal solution to maintain temperatures of the processor core and graphics/memory core within operating limits.

A complete thermal solution provides both the component-level and the system-level thermal management. To allow for the optimal operation and long-term reliability of

Intel processor-based systems, the system/processor thermal solution should be designed so that the processor:

•

Remains below the maximum junction temperature (T j,Max

) specification at the maximum thermal design power (TDP).

• Conforms to system constraints, such as system acoustics, system skintemperatures, and exhaust-temperature requirements.

Caution: Thermal specifications given in this chapter are on the component and package level and apply specifically to the processor. Operating the processor outside the specified limits may result in permanent damage to the processor and potentially other components in the system.

5.1

5.1.1

Thermal Design Power and Junction Temperature

The TDP of an MCP processor is the expected maximum power from each of its components (processor core and integrated graphics and memory controller) while running realistic, worst case applications (TDP applications).TDP is not the absolute worst case power of each component. It could, for example, be exceeded under a synthetic worst case condition or under short power spikes. In production, a range of power is to be expected from the components due to the natural variation in the manufacturing process. The thermal solution, at a minimum, needs to ensure that the junction temperatures of both components do not exceed the maximum junction temperature (T j,max

) limit while running TDP applications.

Intel Graphics Dynamic Frequency

Typical workloads are not intensive enough to push both the processor core and the integrated graphics and memory controller towards their TDP limit simultaneously. As such, the opportunity exists to share thermal power between the components and boost the performance of either the processor core or integrated graphics and memory controller on demand. This intelligent power sharing capability is implemented by Intel

Turbo Boost Technology Driver on these processors. When enabled, the integrated graphics and memory controller can increase its thermal power consumption above its own component TDP limit. However, the sum of component thermal powers adhere to the specified MCP thermal power limit.

On this processor, Intel Graphics Dynamic Frequency is implemented via a combination of Intel silicon capabilities, graphics driver and the Intel Turbo Boost Technology driver.

If Intel provides Intel Graphics Dynamic Frequency support for the target operating

Datasheet 53

Thermal Management system that is shipped with the customer’s platform and Intel Graphics Dynamic

Frequency is enabled, the Intel Turbo Boost Technology driver and graphics driver must be installed and operating to keep the product operating within specification limits.

Caution: The TURBO_POWER_CURRENT_LIMIT MSR is exclusively reserved for Intel Turbo

Technology Driver use. Under no circumstances should this value be altered from the default register value after reset of the processor. Altering this MSR value may result in unpredictable behavior.

5.1.2

1

Note

2

3

4

Intel Graphics Dynamic Frequency Thermal Design

Considerations and Specifications

When designing a thermal solution for Intel Graphics Dynamic frequency enabled processor:

•

Both component TDPs as well as extreme thermal power levels for the processor core and integrated graphics and memory controller must be considered.

• Note that the processor can consume close to its maximum thermal power limit more frequently, and for prolonged periods of time.

•

One must ensure that the component T j,max

limits are not exceeded when either component is operating at its extreme thermal power limit.

There are two “extreme” design points:

•

The processor core operating at maximum thermal power level (which is greater than its component TDP) and the integrated graphics and memory controller operating at its minimum thermal power.

• The integrated graphics operates at its maximum thermal power level, while the processor core consumes the remaining thermal power budget.

In both cases, the combined component thermal power will not exceed the total MCP package power limit. The design approach accommodating two extreme power levels is referred to as a “two-point” design.

The following notes apply to Table and Table 5-18 .

Definition

The component TDPs given are not the maximum power the components can generate. Analysis indicates that real applications are unlikely to cause the processor to consume the theoretical maximum power dissipation for sustained periods of time.

A range of power is to be expected among the components due to the natural variation in the manufacturing process. Nevertheless, the individual component powers are not to exceed the component TDPs specified.

Concurrent package power refers to the actual power consumed by the package while TDP applications are running simultaneously by the processor core and the integrated graphics controller. An example of this could be the processor core running a Prime95* application, and the integrated graphics core running a Star Wars: Jedi Knight* menu simultaneously.

The thermal solution needs to ensure that the temperatures of both components do not exceed the maximum junction temperature (T j,max

) limit, as measured by the DTS and the critical temperature bit. Please refer to processor Specification Update for Tjmax value per sku.

54 Datasheet

Thermal Management

9

10

11

12

13

6

7

8

5

Note Definition

Processor core and integrated graphics and memory controller junction temperatures are monitored by their respective DTS. A DTS outputs a temperature relative to the maximum supported junction temperature. The error associated with DTS measurements will not exceed ±5°C within the operating range.

The power supply to the processor core and the integrated graphics /Memory core should be designed as per Intel’s guidelines.

Processor core currents is monitored by IMON VR feedback (ISENSE) and calculated using a moving average method. Error associated with power monitoring will depend upon individual VR design.

A thermal solution for an power sharing enabled system needs to ensure that the Tj limit is not exceeded while operating under the two extreme power conditions between the processor core and the integrated graphics and memory controller components.

Projected range in advance of the measured product data. Measured values will be available after silicon characterization.

For power sharing designs it is recommended to establish the full cooling capability within 10°C of the T j,max

specifications. Some processors may have a different Tj max value, please refer to the processor Specification Update for details.

In rare occasions the specified maximum power limits may be violated when the package is not at a thermally constrained environment

Tj, min =0 deg

While running intensive graphical and computational workloads simultaneously the concurrent package power may exceed specified limits in exceptional occasions. Nevertheless, the individual component powers are not to exceed the component TDPs specified.

Intel Celeron Mobile Processor U3000 Series Dual-Core ULV Thermal Power Specifications

TDP 1,2,6,7 Frequency

Power Sharing Design

Points

8

T j,max

4,5,10,12

HFM 10.5

LFM 9

HFM

LFM

10.5

9

8.5

8.5

8.5

8.5

18 1.20

17.5

667 MHz

18 1.06

17.5

667 MHz

500 up to

667

N/A

500 up to

667

N/A

Proc: 10.5

Int. Gfx: 4

Proc: 7

Int Gfx:11

N/A N/A

Proc: 10.5

Int. Gfx: 4

N/A

Proc: 7

Int Gfx:11

N/A

18

N/A

18

N/A

105 100

105 100

Datasheet 55

Thermal Management

Table 5-17.Intel Celeron Mobile Processor P4000 Series Dual-Core SV Thermal Power

Specifications

TDP

1,2,6,7

Frequency

Power Sharing Design

Points 8

T j,max

4,5,10,12

HFM

LFM 20

HFM

25

25

LFM 20

12.5

12.5

12.5

12.5

35 1.86

32.5

933 MHz

35

32.5

2.00

933 MHz

500 up to

667

N/A

500 up to

667

N/A

Proc:

29

Int.

Gfx: 6

N/A

Proc:

25

Int.

Gfx: 6

N/A

Proc:

15

Int

Gfx:20

N/A

Proc:

15

Int

Gfx:20

N/A

35

N/A

35

N/A

90

90

85

85

5.1.3

Idle Power Specifications

The idle power specifications in Table and Table 5-18 are not 100% tested. These power specifications are determined by the characterization of the processor currents at higher temperatures and extrapolating the values for the junction temperature indicated.

Table 5-18.18 W Ultra Low Voltage (ULV) Processor Idle Power

Symbol

P

C1E

P

C3

P

C6

Parameter

Idle power in the Package C1e state

Idle power in the Package C3 state

Idle power in the Package C6 state

Min

-

-

-

Typ

-

-

-

Max

12 W

5.0 W

2.6 W

T j

50ºC

35ºC

35ºC

56 Datasheet

Thermal Management

Table 5-19.35 W Standard Voltage (SV) Processor Idle Power

Symbol

P

C1E

P

C3

Parameter

Idle power in the Package C1e state

Idle power in the Package C3 state

Min

-

-

Typ

-

-

5.1.4

Note:

Max

16 W

7.5 W

T j

50 ºC

35 ºC

Intelligent Power Sharing Control Overview

Based upon knowledge of the processor core and integrated graphics and memory controller thermal power, performance state, and temperature, power sharing control does the following:

•

Utilizes internal graphics controller dynamic frequency performance states to achieve their highest performance within the rated thermal power envelope. Intel

Dynamic Frequency enabled processors will offer a range of upside performance capability beyond their rated or guaranteed frequency.

• Controls the processor core and internal graphics controller Intel Turbo Boost performance states to ensure that overall MCP thermal power consumption does not exceed the specified MCP thermal power limit.

•

Limits MCP component usage to ensure that each of the components' T j,max

value is not exceeded.

It is possible that the thermal influence between the MCP components could potentially cause a component to reach its T j,max

, invoking undesirable component hardware autothrottling. It is expected that when running the TDP workload, power sharing control may limit the entire range of component Intel Turbo Boost capabilities (effectively, disabling them).

The principal component of the power sharing control architecture is the policy manager within the Intel Turbo Boost Technology driver which:

• Communicates with the graphics software driver to limit, or increase, internal graphics thermal power.

•

Communicates with the processor core via the PCH to processor core PECI interface to limit, or increase, processor core thermal power.

The Intel Turbo Boost Technology policy manager will set a thermal power limit to which the graphics driver and processor core will adjust their Intel Turbo Boost

Technology performance dynamically, to stay within the limit.

The processor PECI pin must be connected to the PCH PECI pin in order for Intel Turbo

Boost Technology to properly function.

Datasheet 57

Thermal Management

5.1.5

Component Power Measurement/Estimation Error

The processor input pin (ISENSE) informs the processor core of how much amperage the processor core is consuming. This information is provided by the processor core VR.

The process will calculate its current power based upon the ISENSE input information and current voltage state. The internal graphics and memory controller power is estimated by the GFX driver using PMON.

Any error in power estimation or measurement may limit or completely eliminate the performance benefit of Intel Turbo Boost Technology. When a power limit is reached,

Power sharing control will adaptively remove Intel Turbo Boost Technology states to remain with the MCP thermal power limit. Power sharing control assumes the power error is always accurate so if the ISENSE input reports power greater than the actual power, control mechanisms will lower performance before the actual TDP power limit is reached. Intelligent Power sharing will provide better overall Intel Turbo Boost

Technology performance with increasing VR current sense accuracy. Designers and system manufacturers should study trade-offs on VR component accuracy characteristics, such as inductors, to find the best balance of cost vs. performance for their system price and performance targets.

5.2

Thermal Management Features

This section will cover thermal management features for the processor.

5.2.1

Processor Core Thermal Features

Occasionally the processor core will operate in conditions that exceed its maximum allowable operating temperature. This can be due to internal overheating or due to overheating in the entire system. In order to protect itself and the system from thermal failure, the processor core is capable of reducing its power consumption and thereby its temperature until it is back within normal operating limits via the Adaptive Thermal

Monitor.

The Adaptive Thermal Monitor can be activated when any core temperature, monitored by a digital thermal sensor (DTS), exceeds its maximum junction temperature (T j,Max

) and asserts PROCHOT#. The assertion of PROCHOT# activates the thermal control circuit (TCC). The TCC will remain active as long as any core exceeds its temperature limit. Therefore, the Adaptive Thermal Monitor will continue to reduce the processor core power consumption until the TCC is de-activated.

Caution: The Adaptive Thermal Monitor must be enabled for the processor to remain within specification.

5.2.1.1

Adaptive Thermal Monitor

The purpose of the Adaptive Thermal Monitor is to reduce processor core power consumption and temperature until it operates at or below its maximum operating temperature. Processor core power reduction is achieved by:

58 Datasheet

Thermal Management

5.2.1.1.1

•

Adjusting the operating frequency (via the core ratio multiplier) and input voltage

(via the VID signals).

• Modulating (starting and stopping) the internal processor core clocks (duty cycle).

The Adaptive Thermal Monitor dynamically selects the appropriate method. BIOS is not required to select a specific method as with previous-generation processors supporting

Intel® Thermal Monitor 1 (TM1) or Intel® Thermal Monitor 2 (TM2). The temperature at which the Adaptive Thermal Monitor activates the Thermal Control Circuit is not user configurable but is software visible in the IA32_TEMPERATURE_TARGET (0x1A2) MSR,

Bits 23:16.

The Adaptive Thermal Monitor does not require any additional hardware, software drivers, or interrupt handling routines. Note that the Adaptive Thermal

Monitor is not intended as a mechanism to maintain processor TDP. The system design should provide a thermal solution that can maintain TDP within its intended usage range.

Frequency/VID Control

Upon TCC activation, the processor core attempts to dynamically reduce processor core power by lowering the frequency and voltage operating point. The operating points are automatically calculated by the processor core itself and do not require the BIOS to program them as with previous generations of Intel processors. The processor core will scale the operating points such that:

• The voltage will be optimized according to the temperature, the core bus ratio, and number of cores in deep C-states.

•

The core power and temperature are reduced while minimizing performance degradation.

A small amount of hysteresis has been included to prevent an excessive amount of operating point transitions when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature and the hysteresis timer has expired, the operating frequency and voltage transition back to the normal system operating point. This is illustrated in

Figure 5-12 .

Datasheet 59

Figure 5-12.Frequency and Voltage Ordering

Thermal Management

60

Once a target frequency/bus ratio is resolved, the processor core will transition to the new target automatically.

•

On an upward operating point transition, the voltage transition precedes the frequency transition.

•

On a downward transition, the frequency transition precedes the voltage transition.

When transitioning to a target core operating voltage, a new VID code to the voltage regulator is issued. The voltage regulator must support dynamic VID steps to support this method.

During the voltage change:

• It will be necessary to transition through multiple VID steps to reach the target operating voltage.

•

Each step is 12.5 mV for Intel MVP-6.5 compliant VRs.

•

The processor continues to execute instructions. However, the processor will halt instruction execution for frequency transitions.

Datasheet

Thermal Management

5.2.1.1.2

5.2.1.2

Note:

If a processor load-based Enhanced Intel SpeedStep Technology/P-state transition

(through MSR write) is initiated while the Adaptive Thermal Monitor is active, there are two possible outcomes:

• If the P-state target frequency is higher than the processor core optimized target frequency, the p-state transition will be deferred until the thermal event has been completed.

•

If the P-state target frequency is lower than the processor core optimized target frequency, the processor will transition to the P-state operating point.

Clock Modulation

If the frequency/voltage changes are unable to end an Adaptive Thermal Monitor event, the Adaptive Thermal Monitor will utilize clock modulation. Clock modulation is done by alternately turning the clocks off and on at a duty cycle (ratio between clock

“on” time and total time) specific to the processor. The duty cycle is factory configured to 37.5% on and 62.5% off and cannot be modified. The period of the duty cycle is configured to 32 microseconds when the TCC is active. Cycle times are independent of processor frequency. A small amount of hysteresis has been included to prevent excessive clock modulation when the processor temperature is near its maximum operating temperature. Once the temperature has dropped below the maximum operating temperature, and the hysteresis timer has expired, the TCC goes inactive and clock modulation ceases. Clock modulation is automatically engaged as part of the TCC activation when the frequency/VID targets are at their minimum settings. Processor performance will be decreased by the same amount as the duty cycle when clock modulation is active. Snooping and interrupt processing are performed in the normal manner while the TCC is active.

Digital Thermal Sensor

Each processor execution core has an on-die Digital Thermal Sensor (DTS) which detects the core’s instantaneous temperature. The DTS is the preferred method of monitoring processor die temperature because

• It is located near the hottest portions of the die.

•

It can accurately track the die temperature and ensure that the Adaptive Thermal

Monitor is not excessively activated.

Temperature values from the DTS can be retrieved through

•

A software interface via processor Model Specific Register (MSR).

• A processor hardware interface as described in “Platform Environment Control

Interface (PECI)” on page 68 .

When temperature is retrieved by processor MSR, it is the instantaneous temperature of the given core. When temperature is retrieved via PECI, it is the average temperature of each execution core’s DTS over a programmable window (default window of 256 ms.) Intel recommends using the PECI output reading for fan speed or other platform thermal control.

Datasheet 61

Thermal Management

5.2.1.3

Note:

5.2.1.3.1

Code execution is halted in C1-C6. Therefore temperature cannot be read via the processor MSR without bringing a core back into C0. However, temperature can still be monitored through PECI in lower C-states.

Unlike traditional thermal devices, the DTS outputs a temperature relative to the maximum supported operating temperature of the processor (T j,max

). It is the responsibility of software to convert the relative temperature to an absolute temperature. The absolute reference temperature is readable in an MSR. The temperature returned by the DTS is an implied negative integer indicating the relative offset from T j,max

. The DTS does not report temperatures greater than T j,max

.

The DTS-relative temperature readout directly impacts the Adaptive Thermal Monitor trigger point. When a DTS indicates that the maximum processor core temperature has been reached (a reading of 0x0 on any core), the TCC will activate and indicate a

Adaptive Thermal Monitor event.

Changes to the temperature can be detected via two programmable thresholds located in the processor thermal MSRs. These thresholds have the capability of generating interrupts via the core's local APIC. Refer to the Intel® 64 and IA-32 Architectures

Software Developer's Manuals for specific register and programming details.

PROCHOT# Signal

PROCHOT# (processor hot) is asserted when the processor core temperature has reached its maximum operating temperature (T j,max

). This will activate the TCC and signal a thermal event which is then resolved by the Adaptive Thermal Monitor. See

Figure 5-12 (above) for a timing diagram of the PROCHOT# signal assertion relative to the Adaptive Thermal Response.

Only a single PROCHOT# pin exists at a package level of the processor. When any core arrives at the TCC activation point, the PROCHOT# signal will be driven by the processor core. PROCHOT# assertion policies are independent of Adaptive Thermal Monitor enabling.

Bus snooping and interrupt latching are active while the TCC is active.

Bi-Directional PROCHOT#

By default, the PROCHOT# signal is defined as an output only. However, the signal may be configured as bi-directional. When configured as a bi-directional signal, PROCHOT# can be used for thermally protecting other platform components should they overheat as well. When PROCHOT# is signaled externally:

•

The processor core will immediately reduce processor power to the minimum voltage and frequency supported. This is contrary to the internally-generated

Adaptive Thermal Monitor response.

• Clock modulation is not activated.

The TCC will remain active until the system deasserts PROCHOT#. The processor can be configured to generate an interrupt upon assertion and deassertion of the

PROCHOT# signal.

62 Datasheet

Thermal Management

5.2.1.3.2

5.2.1.3.3

Voltage Regulator Protection

PROCHOT# may be used for thermal protection of voltage regulators (VR). System designers can create a circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR is reached. By asserting PROCHOT# (pulled-low) and activating the TCC, the VR will cool down as a result of reduced processor power consumption. Bi-directional PROCHOT# can allow VR thermal designs to target thermal design current (I

TDC

) instead of maximum current. Systems should still provide proper cooling for the VR and rely on bi-directional PROCHOT# only as a backup in case of system cooling failure. Overall, the system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its TDP.

Thermal Solution Design and PROCHOT# Behavior

With a properly designed and characterized thermal solution, it is anticipated that

PROCHOT# will only be asserted for very short periods of time when running the most power intensive applications. The processor performance impact due to these brief periods of TCC activation is expected to be so minor that it would be immeasurable.

However, an under-designed thermal solution that is not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may:

• Cause a noticeable performance loss

•

Result in prolonged operation at or above the specified maximum junction temperature and affect the long-term reliability of the processor

• May be incapable of cooling the processor even when the TCC is active continuously

(in extreme situations)

5.2.1.3.4

5.2.1.4

Low-Power States and PROCHOT# Behavior

If the processor enters a low-power package idle state such as C3 or C6 with

PROCHOT# asserted, PROCHOT# will remain asserted until:

• The processor exits the low-power state

•

The processor junction temperature drops below the thermal trip point

Note that the PECI interface is fully operational during all C-states and it is expected that the platform continues to manage processor core thermals even during idle states by regularly polling for thermal data over PECI.

On-Demand Mode

The processor provides an auxiliary mechanism that allows system software to force the processor to reduce its power consumption via clock modulation. This mechanism is referred to as “On-Demand” mode and is distinct from Adaptive Thermal Monitor and

Datasheet 63

Thermal Management

5.2.1.4.1

5.2.1.4.2

5.2.1.5

5.2.1.6

bi-directional PROCHOT#. Platforms must not rely on software usage of this mechanism to limit the processor temperature. On-Demand Mode can be done via processor MSR or chipset I/O emulation.

On-Demand Mode may be used in conjunction with the Adaptive Thermal Monitor.

However, if the system software tries to enable On-Demand mode at the same time the

TCC is engaged, the factory configured duty cycle of the TCC will override the duty cycle selected by the On-Demand mode. If the I/O based and MSR-based On-Demand modes are in conflict, the duty cycle selected by the I/O emulation-based On-Demand mode will take precedence over the MSR-based On-Demand Mode.

MSR Based On-Demand Mode

If Bit 4 of the IA32_CLOCK_MODULATION MSR is set to a 1, the processor will immediately reduce its power consumption via modulation of the internal core clock, independent of the processor temperature. The duty cycle of the clock modulation is programmable via Bits 3:1 of the same IA32_CLOCK_MODULATION MSR. In this mode, the duty cycle can be programmed from 12.5% on/87.5% off to 87.5% on/12.5% off in

12.5% increments. Thermal throttling using this method will modulate each processor core’s clock independently.

I/O Emulation-Based On-Demand Mode

I/O emulation-based clock modulation provides legacy support for operating system software that initiates clock modulation through I/O writes to ACPI defined processor clock control registers on the chipset (PROC_CNT). Thermal throttling using this method will modulate all processor cores simultaneously.

THERMTRIP# Signal

Regardless of enabling the automatic or on-demand modes, in the event of a catastrophic cooling failure, the processor will automatically shut down when the silicon has reached an elevated temperature that risks physical damage to the processor. At this point the THERMTRIP# signal will go active. THERMTRIP# activation is independent of processor activity and does not generate any bus cycles.

Critical Temperature Detection

Critical Temperature detection is performed by monitoring the processor temperature and temperature gradient. This feature is intended for graceful shutdown before the

THERMTRIP# is activated. If the processor's Adaptive Thermal Monitor is triggered and the temperature remains high, a critical temperature status and sticky bit are latched in the thermal status MSR register and also generates a thermal interrupt if enabled. The assertion of critical temperature bit indicates that processor can no longer be assumed to be working reliably.For more details on the interrupt mechanism, refer to the Intel®

64 and IA-32 Architectures Software Developer's Manuals.

64 Datasheet

Thermal Management

5.2.2

5.2.2.1

5.2.2.1.1

5.2.2.1.2

Integrated Graphics and Memory Controller Thermal

Features

The integrated graphics and memory controller provides the following features for monitoring the integrated graphics and memory controller temperature and triggering thermal management:

•

One internal digital thermal sensor

• Hooks for an external thermal sensor mechanism which can either be TS-on-DIMM or TS-on-Board

The integrated graphics and memory controller has implemented several silicon level thermal management features that can lower both integrated graphics and memory controller and DDR3 power during periods of high activity. As a result, these features can help control temperature and help prevent thermally induced component failures.

These features include:

• Bandwidth throttling triggered by memory loading

•

Bandwidth throttling triggered by integrated graphics and memory controller heating

• THERMTRIP# support

•

Render Thermal Throttling

Internal Digital Thermal Sensor

The integrated graphics and memory controller incorporates one on-die digital thermal sensor for thermal management. The thermal sensor may be programmed to cause hardware throttling and/or software interrupts. Hardware throttling includes render thermal throttling and main memory programmable throttling thresholds. Sensor trip points may also be programmed to generate various interrupts including SCI, SMI,

INTR, and SERR. The internal thermal sensor reports six trip points: Aux0, Aux1, Aux2,

Aux3, Hot, and Catastrophic trip points in order of increasing temperature.

Aux0, Aux1, Aux2, Aux3 Temperature Trip Points

These trip points may be set dynamically if desired and provides a configurable interrupt mechanism to allow software to respond when a trip is crossed in either direction. These auxiliary temperature trip points do not automatically cause any hardware throttling but may be used by software to trigger interrupts.

Hot Temperature Trip Point

This trip point is set at the temperature at which the integrated graphics and memory controller must start throttling. It may optionally enable integrated graphics and memory controller throttling when the temperature is exceeded. This trip point may provide an interrupt to ACPI (or other software) when it is crossed in either direction.

Software could optionally set this as an interrupt when the temperature exceeds this level setting.

Datasheet 65

Thermal Management

5.2.2.1.3

5.2.2.1.4

Note:

5.2.2.1.5

5.2.2.1.6

5.2.2.2

Catastrophic Trip Point

This trip point is set at the temperature at which the integrated graphics and memory controller must be shut down immediately without any software support. This trip point may be programmed to generate an interrupt, enable throttling, or immediately shut down the system (via Halt or via THERMTRIP# assertion). Crossing a trip point in either direction may generate several types of interrupts.

Recommended Programming for Available Trip Points

See the integrated graphics and memory controller BIOS Specification for recommended Trip Point programming. Aux Trip Points (0, 1, 2, 3) should be programmed for software and firmware control via interrupts. HOT Trip Point should be set to throttle integrated graphics and memory controller to avoid T j,max

of 100°C.

Catastrophic Trip Point should be set to halt operation to avoid maximum Tj of 130°C.

Crossing a trip point in either direction may generate several types of interrupts. Each trip point has a register that can be programmed to select the type of interrupt to be generated. Crossing a trip point is implemented as edge detection on each trip point to generate the interrupts. Either edge (i.e., crossing the trip point in either direction) generates the interrupt.

Thermal Sensor Accuracy (T accuracy

)

The error associated with DTS measurement will not exceed ±5°C within the operating range. Integrated graphics and memory controller may not operate above T j,max

spec.

This value is based on product characterization and is not guaranteed by manufacturing test.

Software has the ability to program the T cat

, T hot

, and T aux

trip points, but these trip points should be selected with consideration for the thermal sensor accuracy and the quality of the platform thermal solution. Overly conservative (unnecessarily low) temperature settings may unnecessarily degrade performance due to frequent throttling, while overly aggressive (dangerously high) temperature settings may fail to protect the part against permanent thermal damage.

Hysteresis Operation

Hysteresis provides a small amount of positive feedback to the thermal sensor circuit to prevent a trip point from flipping back and forth rapidly when the temperature is right at the trip point. The digital hysteresis offset is programmable via processor registers.

Memory Thermal Throttling Options

The integrated graphics and memory controller has two, independent mechanisms that cause system memory throttling:

TDP Controller: The TDP Controller is the main mechanism for limiting MCH power by limiting memory bandwidth. Utilized as a thermal throttling mechanism, this feature is triggered by the Hot temperature trip point of the Graphics and Memory Controller

66 Datasheet

Thermal Management

Note:

5.2.2.3

Note:

5.2.2.4

digital thermal sensor (DTS) and initiates duty cycle throttling to delay memory transactions and thereby reducing MCH power. Power reduction is memory configuration and application dependant but duty cycle throttling intervals can be customized for maximum throttling efficiency. The TDP Controller can also be used as a bandwidth limiter using programmable memory read/write bandwidth thresholds. Intel sets the default thresholds that will not restrict bandwidth and performance for most applications but these thresholds can be modified to reduce MCH power regardless of

DTS temperature.

The TDP controller can be used as a closed loop thermal throttling (CLTT) mechanism or an open loop thermal throttling (OLTT) mechanism, although CLTT is recommended .

•

DRAM Thermal Management: Ensures that the DRAM chips are operating within thermal limits. The integrated graphics and memory controller can control the amount of integrated graphics and memory controller-initiated bandwidth per rank to a programmable limit via a weighted input averaging filter.

External Thermal Sensor Interface Overview

The integrated graphics and memory controller supports two inputs for external thermal sensor notifications, based on which it can regulate memory accesses.

The thermal sensors should be capable of measuring the ambient temperature only and should be able to assert PM_EXT_TS#[0] and/or PM_EXT_TS#[1] if the preprogrammed thermal limits/conditions are met or exceeded.

An external thermal sensor with a serial interface may be placed next to a SO-DIMM (or any other appropriate platform location), or a remote Thermal Diode may be placed next to the SO-DIMM (or any other appropriate platform location) and connected to the external Thermal Sensor.

Additional external thermal sensor's outputs, for multiple sensors, can be wire-OR'd together allow signaling from multiple sensors that are physically located separately.

Software can, if necessary, distinguish which SO-DIMM(s) is the source of the overtemp through the serial interface. However, since the SO-DIMM's is located on the same

Memory Bus Data lines, any integrated graphics and memory controller-based read throttle will apply equally.

Thermal sensors can either be directly routed to the integrated graphics and memory controller PM_EXT_TS#[0] and PM_EXT_TS#[1] pins or indirectly routed to integrated graphics and memory controller by invoking an Embedded Controller (EC) connected in between the thermal sensor and integrated graphics and memory controller pins. Both routing methods are applicable for both thermal sensors placed on the motherboard

(TS-on-Board) and/or thermal sensors located on the memory modules (TS-on-DIMM).

THERMTRIP# Operation

The integrated graphics and memory controller can assert THERMTRIP# (Thermal Trip) to indicates that its junction temperature has reached a level beyond which damage may occur. Upon assertion of THERMTRIP#, the integrated graphics and memory

Datasheet 67

Thermal Management controller will shut off its internal clocks (thus halting program execution) in an attempt to reduce the core junction temperature. Once activated, THERMTRIP# remains latched until RSTIN# is asserted.

5.2.2.5

Render Thermal Throttling

Render Thermal Throttling of the integrated graphics and memory controller allows for the reduction the render core engine frequency and voltage, thus reducing internal graphics controller power and integrated graphics and memory controller thermals.

Performance is degraded, but the platform thermal burden is relieved.

Render Thermal Throttling using several frequency/voltage operating points that can be used to throttle the render core. If the temperature of the integrated graphics and memory controller internal DTS exceeds the Hot-trip point, the integrated graphics will switch to a lower frequency/voltage operating point. After a timeout, the DTS is rechecked, and if the DTS temperature is still greater than the designed hysteresis, the integrated graphics will continue to switch to lower frequency/voltage operating points.

Once the DTS reports a temperature below the hysteresis value, the render clock frequency and voltage will be restored to its pre-thermal event state.

Caution: The Render Thermal Throttling must be enabled for the product to remain within specification.

5.2.3

5.2.3.1

Platform Environment Control Interface (PECI)

The Platform Environment Control Interface (PECI) is a one-wire interface that provides a communication channel between Intel processor and chipset components to external monitoring devices. The processor implements a PECI interface to allow communication of processor thermal information to other devices on the platform. The processor provides a digital thermal sensor (DTS) for fan speed control. The DTS is calibrated at the factory to provide a digital representation of relative processor temperature.

Averaged DTS values are read via the PECI interface.

The PECI physical layer is a self-clocked one-wire bus that begins each bit with a driven, rising edge from an idle level near zero volts. The duration of the signal driven high depends on whether the bit value is a Logic 0 or Logic 1. PECI also includes variable data transfer rate established with every message. The single wire interface provides low board routing overhead for the multiple load connections in the congested routing area near the processor and chipset components. Bus speed, error checking, and low protocol overhead provides adequate link bandwidth and reliability to transfer critical device operating conditions and configuration information.

Fan Speed Control with Digital Thermal Sensor

Digital Thermal Sensor based fan speed control (T

FAN

) is a recommended feature to achieve optimal thermal performance. At the T

FAN

temperature, Intel recommends full cooling capability well before the DTS reading reaches T j,max

. An example of this would be T

FAN

= T j,max

- 10ºC.

68 Datasheet

Thermal Management

5.2.3.2

Processor Thermal Data Sample Rate and Filtering

The processor digital thermal sensor (DTS) provides an improved capability to monitor device hot spots, which inherently leads to more varying temperature readings over short time intervals. To reduce the sample rate requirements on PECI and improve thermal data stability vs. time the processor DTS implements an averaging algorithm that filters the incoming data. This filter is expressed mathematically as:

PECI(t) = PECI(t-1)+1/(2^^X)*[Temp - PECI(t-1)] where:

• PECI(t) is the new averaged temperature

•

PECI(t-1) is the previous averaged temperature

• Temp is the raw temperature data from the DTS

•

X is the Thermal Averaging Constant (TAC)

The Thermal Averaging Constant is a BIOS configurable value that determines the time in milliseconds over which the DTS temperature values are averaged (the default time is 256 ms). Short averaging times will make the averaged temperature values respond more quickly to DTS changes. Long averaging times will result in better overall thermal smoothing but also incur a larger time lag between fast DTS temperature changes and the value read via PECI.

Within the processor, the DTS converts an analog signal into a digital value representing the temperature relative to PROCHOT# circuit activation. The conversions are in integers with each single number change corresponding to approximately 1°C.

DTS values reported via the internal processor MSR will be in whole integers.

As a result of the PECI averaging function described above, DTS values reported over

PECI will include a 6-bit fractional value. Under typical operating conditions, where the temperature is close to PROCHOT#, the fractional values may not be of interest. But when the temperature approaches zero, the fractional values can be used to detect the activation of the PROCHOT# circuit. An averaged temperature value between 0 and 1 can only occur if the PROCHOT# circuit has been activated during the averaging window. As PROCHOT# circuit activation time increases, the fractional value will approach zero. Fan control circuits can detect this situation and take appropriate action as determined by the system designers. Of course, fan control chips can also monitor the PROCHOT# pin to detect PROCHOT# circuit activation via a dedicated input pin on the package.

§

Datasheet 69

Signal Description

6 Signal Description

This chapter describes the processor signals. They are arranged in functional groups according to their associated interface or category. The following notations are used to describe the signal type:

Notations

I

O

I/O

Signal Type

Input Pin

Output Pin

Bi-directional Input/Output Pin

The signal description also includes the type of buffer used for the particular signal:

Table 6-20.Signal Description Buffer Types

Signal

PCI Express*

FDI

DMI

CMOS

DDR3

A

GTL

Ref

Asynchronous 1

Description

PCI Express interface signals. These signals are compatible with PCI

Express 2.0 Signalling Environment AC Specifications and are AC coupled.

The buffers are not 3.3-V tolerant. Refer to the PCIe specification.

Intel Flexible Display interface signals. These signals are compatible with

PCI Express 2.0 Signaling Environment AC Specifications, but are DC coupled. The buffers are not 3.3-V tolerant.

Direct Media Interface signals. These signals are compatible with PCI

Express 2.0 Signaling Environment AC Specifications, but are DC coupled.

The buffers are not 3.3-V tolerant.

CMOS buffers. 1.1-V tolerant

DDR3 buffers: 1.5-V tolerant

Analog reference or output. May be used as a threshold voltage or for buffer compensation

Gunning Transceiver Logic signaling technology

Voltage reference signal

Signal has no timing relationship with any reference clock.

NOTES:

1.

Qualifier for a buffer type.

70 Datasheet

Signal Description

6.1

System Memory Interface

Table 6-21.Memory Channel A (Sheet 1 of 2)

Signal Name

SA_BS[2:0]

SA_WE#

SA_RAS#

SA_CAS#

SA_DM[7:0]

SA_DQS[7:0]

SA_DQS#[7:0]

SA_DQ[63:0]

SA_MA[15:0]

SA_CK[1:0]

SA_CK#[1:0]

Description

Bank Select: These signals define which banks are selected within each SDRAM rank.

Write Enable Control Signal: Used with

SA_RAS# and SA_CAS# (along with

SA_CS#) to define the SDRAM Commands.

RAS Control Signal: Used with SA_CAS# and SA_WE# (along with SA_CS#) to define the SRAM Commands.

CAS Control Signal: Used with SA_RAS# and SA_WE# (along with SA_CS#) to define the SRAM Commands.

Data Mask: These signals are used to mask individual bytes of data in the case of a partial write and to interrupt burst writes.

When activated during writes, the corresponding data groups in the SDRAM are masked. There is one SA_DM[7:0] for every data byte lane.

Data Strobes: SA_DQS[7:0] and its complement signal group make up a differential strobe pair. The data is captured at the crossing point of SA_DQS[7:0] and its

SA_DQS#[7:0] during read and write transactions

Data Strobe Complements: These are the complementary strobe signals.

Data Bus: Channel A data signal interface to the SDRAM data bus.

Memory Address: These signals are used to provide the multiplexed row and column address to the SDRAM.

SDRAM Differential Clock: Channel A

SDRAM Differential clock signal pair. The crossing of the positive edge of SA_CK and the negative edge of its complement

SA_CK# are used to sample the command and control signals on the SDRAM.

SDRAM Inverted Differential Clock:

Channel A SDRAM Differential clock signalpair complement.

Direction/Buffer

Type

O

DDR3

O

DDR3

O

DDR3

O

DDR3

O

DDR3

I/O

DDR3

I/O

DDR3

I/O

DDR3

O

DDR3

O

DDR3

O

DDR3

Datasheet 71

Signal Description

72

Table 6-21.Memory Channel A (Sheet 2 of 2)

Signal Name

SA_CKE[1:0]

SA_CS#[1:0]

SA_ODT[1:0]

Description

Clock Enable: (1 per rank) Used to:

- Initialize the SDRAMs during power-up

- Power-down SDRAM ranks

- Place all SDRAM ranks into and out of selfrefresh during STR

Chip Select: (1 per rank) Used to select particular SDRAM components during the active state. There is one Chip Select for each SDRAM rank.

On Die Termination: Active Termination

Control.

Direction/Buffer

Type

O

DDR3

O

DDR3

O

DDR3

Table 6-22.Memory Channel B (Sheet 1 of 2)

Signal Name

SB_BS[2:0]

SB_WE#

SB_RAS#

SB_CAS#

SB_DM[7:0]

SB_DQS[7:0]

SB_DQS#[7:0]

SB_DQ[63:0]

Description

Bank Select: These signals define which banks are selected within each SDRAM rank.

Write Enable Control Signal: Used with

SB_RAS# and SB_CAS# (along with

SB_CS#) to define the SDRAM Commands.

RAS Control Signal: Used with SB_CAS# and SB_WE# (along with SB_CS#) to define the SRAM Commands.

CAS Control Signal: Used with SB_RAS# and SB_WE# (along with SB_CS#) to define the SRAM Commands.

Data Mask: These signals are used to mask individual bytes of data in the case of a partial write and to interrupt burst writes.

When activated during writes, the corresponding data groups in the SDRAM are masked. There is one SB_DM[7:0] for every data byte lane.

Data Strobes: SB_DQS[7:0] and its complement signal group make up a differential strobe pair. The data is captured at the crossing point of SB_DQS[7:0] and its

SB_DQS#[7:0] during read and write transactions.

Data Strobe Complements: These are the complementary strobe signals.

Data Bus: Channel B data signal interface to the SDRAM data bus.

Direction/

Buffer Type

O

DDR3

O

DDR3

O

DDR3

O

DDR3

O

DDR3

I/O

DDR3

I/O

DDR3

I/O

DDR3

Datasheet

Signal Description

Table 6-22.Memory Channel B (Sheet 2 of 2)

Signal Name

SB_MA[15:0]

SB_CK[1:0]

SB_CK#[1:0]

SB_CKE[1:0]

SB_CS#[1:0]

SB_ODT[1:0]

Description

Memory Address: These signals are used to provide the multiplexed row and column address to the SDRAM.

SDRAM Differential Clock: Channel B

SDRAM Differential clock signal pair. The crossing of the positive edge of SB_CK and the negative edge of its complement

SB_CK# are used to sample the command and control signals on the SDRAM.

SDRAM Inverted Differential Clock:

Channel B SDRAM Differential clock signalpair complement.

Clock Enable: (1 per rank) Used to:

- Initialize the SDRAMs during power-up.

- Power-down SDRAM ranks.

- Place all SDRAM ranks into and out of selfrefresh during STR.

Chip Select: (1 per rank) Used to select particular SDRAM components during the active state. There is one Chip Select for each SDRAM rank.

On Die Termination: Active Termination

Control.

Direction/

Buffer Type

O

DDR3

O

DDR3

O

DDR3

O

DDR3

O

DDR3

O

DDR3

6.2

Memory Reference and Compensation

Table 6-23.Memory Reference and Compensation

Signal Name

SM_RCOMP[2:0]

SA_DIMM_VREFDQ

SB_DIMM_VREFDQ

Description

System Memory Impedance

Compensation:.

Memory Channel A/B DIMM Voltage.

Direction/Buffer

Type

O

A

I

A

Datasheet 73

Signal Description

6.3

Reset and Miscellaneous Signals

Table 6-24.Reset and Miscellaneous Signals (Sheet 1 of 2)

Signal Name

SM_DRAMRST#

PM_EXT_TS#[0]

PM_EXT_TS#[1]

COMP0

COMP1

COMP2

COMP3

PM_SYNC

RESET_OBS#

RSTIN#

BPM#[7:0]

DBR#

Description

Direction/Buffer

Type

DDR3 DRAM Reset: Reset signal from processor to DRAM devices. One for all channels or SO-DIMMs.

External Thermal Sensor Input: If the system temperature reaches a dangerously high value then this signal can be used to trigger the start of system memory throttling.

Impedance compensation must be terminated on the system board using a precision resistor.

Impedance compensation must be terminated on the system board using a precision resistor.

Impedance compensation must be terminated on the system board using a precision resistor.

Impedance compensation must be terminated on the system board using a precision resistor.

Power Management Sync: A sideband signal to communicate power management status from the platform to the processor.

This signal is an indication of the processor being reset.

O

DDR3

I

CMOS

I

A

I

A

I

A

I

A

I

CMOS

Reset In: When asserted this signal will asynchronously reset the processor logic.

This signal is connected to the PLTRST# output of the PCH.

Breakpoint and Performance Monitor

Signals: Outputs from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance.

Debug Reset: Used only in systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. This signal only routes through the package and does not connect to the the processor silicon itself.

O

Asynchronous CMOS

I

CMOS

I/O

GTL

O

74 Datasheet

Signal Description

Table 6-24.Reset and Miscellaneous Signals (Sheet 2 of 2)

Signal Name

PRDY#

PREQ#

RSVD

RSVD_TP

RSVD_NCTF

Description

PRDY#: A processor output used by debug tools to determine processor debug readiness.

PREQ#: Used by debug tools to request debug operation of the processor.

RESERVED. All signals that are RSVD and

RSVD_NCTF must be left unconnected on the board. However, Intel recommends that all

RSVD_TP signals have via test points.

Direction/Buffer

Type

O

Asynchronous GTL

I

Asynchronous GTL

No Connect

Test Point

Non-Critical to

Function

6.4

PCI Express Graphics Interface Signals

Table 6-25.PCI Express Graphics Interface Signals

Signal Name

PEG_RX[15:0]

PEG_RX#[15:0]

PEG_TX[15:0]

PEG_TX#[15:0]

PEG_ICOMPI

PEG_ICOMPO

PEG_RCOMPO

PEG_RBIAS

Description

PCI Express Graphics Receive

Differential Pair

PCI Express Graphics Transmit

Differential Pair

PCI Express Graphics Input Current

Compensation

PCI Express Graphics Output Current

Compensation

PCI Express Graphics Resistance

Compensation

PCI Express Resistor Bias Control

Direction/Buffer

Type

I

PCI Express

O

PCI Express

I

A

I

A

I

A

I

A

Datasheet 75

Signal Description

6.5

Embedded DisplayPort (eDP)

Signal Name eDP_TX[3:0] eDP_TX#[3:0] eDP_AUX eDP_AUX# eDP_HPD# eDP_ICOMPI eDP_ICOMPO eDP_RCOMPO eDP_RBIAS

Embedded Display Port Signals

Description

Direction/Buffer

Type

Embedded DisplayPort Transmit Differential

Pair: Nominally, eDP_TX[3:0] is multiplexed with PEG_TX[12:15] and eDP_TX#[3:0] is multiplexed with PEG_TX#[12:15]. When reversed, eDP_TX[3:0] is multiplexed with

PEG_TX[3:0] and eDP_TX#[3:0] is multiplexed with PEG_TX#[3:0]

O

PCI Express

Embedded DisplayPort Auxiliary Differential

Pair: Nominally, eDP_AUX is multiplexed with

PEG_RX[13] and eDP_AUX# is multiplexed with PEG_RX#[13]. When reversed, eDP_AUX is multiplexed with PEG_RX[2] and eDP_AUX# is multiplexed with PEG_RX#[2]

I/O

PCI Express

Embedded DisplayPort Hot Plug Detect:

Nominally, eDP_HPD# is multiplexed with

PEG_RX[12]. When reversed, eDP_HPD# is multiplexed with PEG_RX[3]

Embedded DisplayPort Input Current

Compensation: Multiplexed with PEG_ICOMPI

Embedded DisplayPort Output Current and

Resistance Compensation: Multiplexed with

PEG_ICOMPO

Embedded DisplayPort Resistance

Compensation: Multiplexed with PEG_RCOMPO

I

A

I

A

I

A

I

PCI Express

Embedded DisplayPort Resistor Bias Control:

Multiplexed with PEG_RBIAS

I

A

Intel Flexible Display Interface Signals 6.6

Table 6-26.Intel® Flexible Display Interface (Sheet 1 of 2)

Signal Name

FDI_TX[3:0]

FDI_TX#[3:0]

FDI_FSYNC[0]

FDI_LSYNC[0]

Description

Intel® Flexible Display Interface

Transmit Differential Pair - Pipe A

Intel® Flexible Display Interface Frame

Sync - Pipe A

Intel® Flexible Display Interface Line Sync

- Pipe A

Direction/Buffer

Type

O

FDI

I

CMOS

I

CMOS

76 Datasheet

Signal Description

Table 6-26.Intel® Flexible Display Interface (Sheet 2 of 2)

Signal Name

FDI_TX[7:4]

FDI_TX#[7:4]

FDI_FSYNC[1]

FDI_LSYNC[1]

FDI_INT

Description

Intel® Flexible Display Interface

Transmit Differential Pair - Pipe B

Intel® Flexible Display Interface Frame

Sync - Pipe B

Intel® Flexible Display Interface Line Sync

- Pipe B

Intel® Flexible Display Interface Hot Plug

Interrupt

Direction/Buffer

Type

O

FDI

I

CMOS

I

CMOS

I

CMOS

6.7

DMI

Table 6-27.DMI - Processor to PCH Serial Interface

Signal Name

DMI_RX[3:0]

DMI_RX#[3:0]

DMI_TX[3:0]

DMI_TX#[3:0]

Description

DMI Input from PCH: Direct Media

Interface receive differential pair.

DMI Output to PCH: Direct Media

Interface transmit differential pair.

Direction/Buffer

Type

I

DMI

O

DMI

6.8

PLL Signals

Table 6-28.PLL Signals

Signal Name

BCLK

BCLK#

BCLK_ITP

BCLK_ITP#

PEG_CLK

PEG_CLK#

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

Description

Differential bus clock input to the processor

Buffered differential bus clock pair to ITP

Differential PCI Express Based

Graphics/DMI Clock In: These pins receive a 100-MHz Serial Reference clock from the external clock synthesizer. This clock is used to generate the clocks necessary for the support of PCI Express. This also is the reference clock for Intel® FDI.

Embedded Display Port PLL Differential

Clock In: With or without SSC -120 MHz.

Direction/Buffer

Type

I

Diff Clk

O

Diff Clk

I

Diff Clk

I

Diff Clk

Datasheet 77

Signal Description

6.9

TAP Signals

Table 6-29.TAP Signals

Signal Name

TCK

TDI

TDO

TDI_M

TDO_M

TMS

TRST#

TAPPWRGOOD

Description

Direction/Buffer

Type

TCK (Test Clock): Provides the clock input for the processor Test Bus (also known as the Test Access Port).

TDI (Test Data In): Transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support.

Test Data Output

I

CMOS

I

CMOS

Test Data In for the GPU/Memory core:

Tie TDI_M and TDO_M together on the motherboard

Test Data Output from the processor

core: Tie TDO_M and TDI_M together on the motherboard.

TMS (Test Mode Select): A JTAG specification support signal used by debug tools.

TRST# (Test Reset) Boundary-Scan test reset pin

Power good for ITP

O

CMOS

I

CMOS

O

CMOS

I

CMOS

I

CMOS

O

Asynchronous CMOS

78 Datasheet

Signal Description

6.10

Error and Thermal Protection

Table 6-30.Error and Thermal Protection

Signal Name

CATERR#

PECI

PROCHOT#

THERMTRIP#

Description

Catastrophic Error: This signal indicates that the system has experienced a catastrophic error and cannot continue to operate. The processor will set this for non-recoverable machine check errors or other unrecoverable internal errors.

External agents are allowed to assert this pin which will cause the processor to take a machine check exception.

PECI (Platform Environment Control

Interface): A serial sideband interface to the processor, it is used primarily for thermal, power, and error management. Details regarding the

PECI electrical specifications, protocols, and functions can be found in the RS - Platform

Environment Control Interface (PECI)

Specification, Revision 2.0.

Processor Hot: PROCHOT# goes active when the processor temperature monitoring sensor(s) detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control

Circuit (TCC) has been activated, if enabled. This signal can also be driven to the processor to activate the TCC.

Thermal Trip: The processor protects itself from catastrophic overheating by use of an internal thermal sensor. This sensor is set well above the normal operating temperature to ensure that there are no false trips. The processor will stop all execution when the junction temperature exceeds approximately 130°C. This is signaled to the system by the THERMTRIP# pin.

Direction/Buffer

Type

I/O

GTL

I/O

Asynchronous

I/O

Asynchronous GTL

O

Asynchronous GTL

Datasheet 79

Signal Description

6.11

Power Sequencing

Table 6-31.Power Sequencing

Signal Name

VCCPWRGOOD_0

VCCPWRGOOD_1

SM_DRAMPWROK

VTTPWRGOOD

SKTOCC#(rPGA988A only)

PROC_DETECT (BGA only)

Description

Direction/Buffer

Type

VCCPWRGOOD_0 and VCCPWRGOOD_1

(Power Good) Processor Input: The processor requires these signals to be a clean indication that:

-VCC, VCCPLL, and VTT supplies are stable and within their specifications

-BCLK is stable and has been running for a minimum number of cycles.

Both signals must then transition monotonically to a high state.

VCCPWRGOOD_0 and VCCPWRGOOD_1 can be driven inactive at any time, but BCLK and power must again be stable before a subsequent rising edge of these signals.

VCCPWRGOOD_0 and VCCPWRGOOD_1 should be tied together and connected to the

PROCPWRGD output signal of the PCH.

SM_DRAMPWROK Processor Input:

Connects to PCH DRAMPWROK.

I

Asynchronous CMOS

I

Asynchronous CMOS

I

Asynchronous CMOS

VTTPWRGOOD Processor Input: The processor requires this input signal to be a clean indication that the VTT power supply is stable and within specifications. Clean implies that the signal will remain low

(capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. Note it is not valid for VTTPWRGOOD to be deasserted while VCCPWRGOOD_0 and

VCCPWRGOOD_1 is asserted.

SKTOCC# (Socket Occupied)/

PROC_DETECT (Processor Detect): pulled to ground on the processor package. There is no connection to the processor silicon for this signal. System board designers may use this signal to determine if the processor is present.

80 Datasheet

Signal Description

6.12

Processor Power Signals

Table 6-32.Processor Power Signals (Sheet 1 of 3)

Signal Name

VCC

VTT

(VTT0 and VTT1)

VDDQ

VCCPLL

ISENSE

PROC_DPRSLPVR

PSI#

Description

Processor core power rail.

Processor I/O power rail (1.05 V). VTT0 and

VTT1 should share the same VR

Direction/Buffer

Type

Ref

Ref

DDR3 power rail (1.5 V)

Power rail for filters and PLLs (1.8 V)

Current Sense from an Intel® MVP6.5

Compliant Regulator to the processor core.

Ref

Ref

I

A

O

CMOS

Processor output signal to Intel MVP-6.5 controller to indicate that the processor is in the package C6 state.

Processor Power Status Indicator: This signal is asserted when the processor core current consumption is less than 15 A.

Assertion of this signal is an indication that the VR controller does not currently need to provide ICC above 15 A. The VR controller can use this information to move to a more efficient operating point. This signal will deassert at least 3.3 µs before the current consumption will exceed 15 A. The minimum

PSI# assertion and de-assertion time is 1

BCLK.

O

Asynchronous CMOS

Datasheet 81

82

Signal Description

Table 6-32.Processor Power Signals (Sheet 2 of 3)

Signal Name

VID[6]

VID[5:3]/CSC[2:0]

VID[2:0]/MSID[2:0]

VTT_SELECT

VCC_SENSE

VSS_SENSE

VTT_SENSE

VSS_SENSE_VTT

VAXG

VAXG_SENSE

VSSAXG_SENSE

GFX_VID[6:0]

GFX_VR_EN

Description

VID[6:0] (Voltage ID) Pins: Used to support automatic selection of power supply voltages (VCC). These are CMOS signals that are driven by the processor.

CSC[2:0]/VID[5:3] - Current Sense

Configuration bits, for ISENSE gain setting.

This value is latched on the rising edge of

VTTPWRGOOD.

MSID[2:0]/VID[2:0]- Market Segment

Identification is used to indicate the maximum platform capability to the processor. A processor will only boot if the

MSID[2:0] pins are strapped to the appropriate setting (or higher) on the platform (see Table 7-36 for MSID encodings). MSID is used to help protect the platform by preventing a higher power processor from booting in a platform designed for lower power processors.

MSID[2:0] are latched on the rising edge of

VTTPWRGOOD.

NOTE: VID[5:3] and VID[2:0] are bidirectional. As an input, they are CSC[2:0] and MSID[2:0] respectively.

The VTT_SELECT signal is used to select the correct VTT voltage level for the processor.

Voltage Feedback Signals to an Intel MVP-6.5

Compliant VR: Use VCC_SENSE to sense voltage and VSS_SENSE to sense ground near the silicon with little noise.

Isolated low impedance connection to the processor VTT voltage and ground. They can be used to sense or measure voltage near the silicon.

Graphics core power rail.

VAXG_SENSE and VSSAXG_SENSE provide an isolated, low impedance connection to the

VAXG voltage and ground. They can be used to sense or measure voltage near the silicon.

GFX_VID[6:0] (Voltage ID) pins are used to support automatic selection of nominal voltages (VAXG). These are CMOS signals that are driven by the processor.

GPU output signal to Intel MVP6.5 compliant

VR. This signal is used as an on/off control to enable/disable the GPU VR.

Direction/Buffer

Type

O

CMOS

O

CMOS

O

A

O

A

Ref

O

A

O

CMOS

O

CMOS

Datasheet

Signal Description

Table 6-32.Processor Power Signals (Sheet 3 of 3)

Signal Name

GFX_DPRSLPVR

GFX_IMON

VDDQ_CK

VTT0_DDR

VCAP0

VCAP1

VCAP2

Description

GPU output signal to Intel MVP6.5 compliant

VR. When asserted this signal indicates that the GPU is in render suspend mode. This signal is also used to control render suspend state exit slew rate.

Current Sense from an Intel MVP6.5

Compliant Regulator to the GPU.

Filtered power for VDDQ (BGA Only)

Filtered power for VTT0 (BGA Only)

Processor Connection to On-board decoupling capacitors (BGA only)

Direction/Buffer

Type

O

CMOS

I

A

Ref

Ref

PWR

6.13

Ground and NCTF

Table 6-33.Ground and NCTF

Signal Name

VSS

VSS_NCTF

DC_TEST_xx#

Description

Processor ground node

Non-Critical to Function: The pins are for package mechanical reliability.

Daisy Chain Test - These pins are for solder joint reliability and are non-critical to function (BGA only).

Direction/Buffer

Type

GND

NC

6.14

Processor Internal Pull Up/Pull Down

Table 6-34.Processor Internal Pull Up/Pull Down

Signal Name

SM_DRAMPWROK

VCCPWRGOOD_0

VCCPWRGOOD_1

VTTPWRGOOD

BPM#[7:0]

TCK

TDI

TMS

TRST#

Pull Up/Pull Down

Pull Down

Pull Down

Pull Down

Pull Up

Pull Up

Pull Up

Pull Up

Pull Up

VSS

VSS

VSS

VTT

VTT

VTT

VTT

VTT

Rail Value

10 - 20 k

10 - 20 k

10 - 20 k

44 - 55 k

44 - 55 k

44 - 55 k

44 - 55 k

1 - 5 k

Datasheet 83

Signal Description

Table 6-34.Processor Internal Pull Up/Pull Down

Signal Name

TDI_M

PREQ#

CFG[17:0]

Pull Up/Pull Down

Pull Up

Pull Up

Pull Up

VTT

VTT

VTT

Rail

§

Value

44 - 55 k

44 - 55 k

5 - 14 k

84 Datasheet

Electrical Specifications

7 Electrical Specifications

7.1

Power and Ground Pins

The processor has V

CC

, V

TT

, V

DDQ,

V

CCPLL,

V

AXG

and V

SS

(ground) inputs for on-chip power distribution. All power pins must be connected to their respective processor power planes, while all V

SS

pins must be connected to the system ground plane. Use of multiple power and ground planes is recommended to reduce I*R drop. The V

CC

pins must be supplied with the voltage determined by the processor Voltage IDentification

(VID) signals. Likewise, the V

AXG

pins must also be supplied with the voltage determined by the GFX_VID signals. Table 7-35 specifies the voltage level for the various VIDs. The voltage levels are the same for both the processor VIDs and

GFX_VIDs.

7.2

Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large current swings between low- and full-power states. To keep voltages within specification, output decoupling must be properly designed.

Caution: Design the board to ensure that the voltage provided to the processor remains within the specifications listed in Table 7-35 . Failure to do so can result in timing violations or reduced lifetime of the processor.

7.2.1

Voltage Rail Decoupling

The voltage regulator solution must:

• provide sufficient decoupling to compensate for large current swings generated during different power mode transitions.

• provide low parasitic resistance from the regulator to the socket.

• meet voltage and current specifications as defined in Table 7-35 .

7.3

Processor Clocking (BCLK, BCLK#)

The processor utilizes a differential clock to generate the processor core(s) operating frequency, memory controller frequency, and other internal clocks. The processor core frequency is determined by multiplying the processor core ratio by 133 MHz. Clock multiplying within the processor is provided by an internal phase locked loop (PLL), which requires a constant frequency input, with exceptions for Spread Spectrum

Clocking (SSC).

The processor’s maximum core frequency is configured during power-on reset by using its manufacturing default value. This value is the highest core multiplier at which the processor can operate.

Datasheet 85

Electrical Specifications

7.3.1

PLL Power Supply

An on-die PLL filter solution is implemented on the processor. Refer to Table 7-35 for

DC specifications

7.4

Note:

Voltage Identification (VID)

The processor uses seven voltage identification pins, VID[6:0], to support automatic selection of the processor power supply voltages. VID pins for the processor are CMOS outputs driven by the processor VID circuitry. A dedicated graphics voltage regulator is required to deliver voltage to the integrated graphics controller. Like the processor core, the integrated graphics controller will use seven voltage identification pins,

GFX_VID[6:0], to set the nominal operating voltage GFX_VID pins for the graphics core are CMOS outputs driven by the graphics core VID circuitry. Table 7-35 specifies the voltage level for VID[6:0] and GFX_VID[6:0]; 0 refers to a low-voltage level

VID signals are CMOS push/pull drivers. Refer to Table 7-44 for the DC specifications for these signals. The VID codes will change due to temperature, frequency, and/or power mode load changes in order to minimize the power of the part. A voltage range is provided in Table 7-35 . The specifications are set so that one voltage regulator can operate with all supported frequencies.

Individual processor VID values may be set during manufacturing so that two devices at the same core frequency may have different default VID settings. This is shown in the VID range values in Table 7-35 . The processor provides the ability to operate while transitioning to an adjacent VID and its associated processor core voltage (V

CC

). This will represent a DC shift in the loadline.

A low-to-high or high-to-low voltage state change will result in as many VID transitions as necessary to reach the target core voltage. Transitions above the maximum or below the minimum specified VID are not permitted. One VID transition occurs in 2.5 µs.

The VR utilized must be capable of regulating its output to the value defined by the new

VID values issued. DC specifications for dynamic VID transitions are included in

Table 7-35 .

Several of the VID signals (VID[5:3]/CSC[2:0] and VID[2:0]/MSID[2:0]) serve a dual purpose and are sampled during reset. Refer to the signal description table in

Chapter 6 for more information.

Table 7-35.Voltage Identification Definition (Sheet 1 of 4)

VID6

0

0

0

0

0

0

0

VID5

0

0

0

0

0

0

0

VID4

0

0

0

0

0

0

0

VID3

0

0

0

0

0

0

0

VID2

1

1

1

0

0

0

0

VID1

0

0

1

1

1

0

0

VID0

0

1

0

0

1

0

1

V

CC

(V)

1.5000

1.4875

1.4750

1.4625

1.4500

1.4375

1.4250

86 Datasheet

Electrical Specifications

VID5

1

1

1

1

1

1

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

Table 7-35.Voltage Identification Definition (Sheet 2 of 4)

VID6

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

VID4

0

0

0

0

0

0

1

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

1

0

0

0

0

0

0

0

0

1

1

0

1

1

1

0

0

0

0

0

0

0

0

VID3

0

0

0

0

0

0

1

0

1

1

1

1

1

1

0

1

0

0

0

0

0

0

1

0

1

1

1

1

1

1

0

1

0

0

1

0

0

0

1

1

1

1

1

1

0

1

VID2

1

1

0

1

0

0

1

0

1

1

0

1

0

0

1

0

1

1

0

1

0

0

1

0

1

1

0

1

0

0

1

0

0

0

1

0

0

1

1

1

0

1

0

0

1

0

VID1

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

1

0

0

1

1

0

0

1

1

0

VID0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

V

CC

(V)

1.2125

1.2000

1.1875

1.1750

1.1625

1.1500

1.1375

1.1250

1.1125

1.1000

1.0875

1.0750

1.0625

1.0500

1.0375

1.0250

1.4125

1.4000

1.3875

1.3750

1.3625

1.3500

1.3375

1.3250

1.3125

1.3000

1.2875

1.2750

1.2625

1.2500

1.2375

1.2250

1.0125

1.0000

0.9875

0.9750

0.9625

0.9500

0.9375

0.9250

0.9125

0.9000

0.8875

0.8750

0.8625

0.8500

Datasheet 87

Electrical Specifications

88

VID5

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

1

1

1

1

1

1

1

1

1

1

0

1

0

0

1

1

0

0

0

0

0

0

0

0

Table 7-35.Voltage Identification Definition (Sheet 3 of 4)

VID6

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

1

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

VID4

1

1

1

1

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

0

1

1

1

1

1

1

1

1

1

1

1

0

1

1

0

0

1

1

1

1

1

1

1

1

VID3

0

0

0

0

1

0

1

1

1

1

1

1

0

1

0

0

0

0

0

0

1

0

1

1

1

1

1

1

0

1

0

0

1

0

1

1

0

0

1

1

1

1

0

1

0

0

VID2

0

1

0

0

1

0

1

1

0

1

0

0

1

0

1

1

0

1

0

0

1

0

1

1

0

1

0

0

1

0

1

1

1

0

1

1

0

0

0

1

0

0

1

0

1

1

VID1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

0

1

0

1

1

0

0

1

1

0

0

1

VID0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

V

CC

(V)

0.6375

0.6250

0.6125

0.6000

0.5875

0.5750

0.5625

0.5500

0.5375

0.5250

0.5125

0.5000

0.4875

0.4750

0.4625

0.4500

0.8375

0.8250

0.8125

0.8000

0.7875

0.7750

0.7625

0.7500

0.7375

0.7250

0.7125

0.7000

0.6875

0.6750

0.6625

0.6500

0.4375

0.4250

0.4125

0.4000

0.3875

0.3750

0.3625

0.3500

0.3375

0.3250

0.3125

0.3000

0.2875

0.2750

Datasheet

Electrical Specifications

Table 7-35.Voltage Identification Definition (Sheet 4 of 4)

VID4

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

1

0

0

0

0

0

0

0

0

0

0

0

0

VID5

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

VID6

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

VID3

1

1

0

1

0

0

0

0

1

1

1

1

1

0

0

1

0

1

1

1

1

1

1

0

1

0

0

0

0

VID2

0

0

1

0

1

1

0

1

1

1

0

1

1

0

0

1

0

1

1

0

1

0

0

1

0

1

1

0

1

VID1

0

1

1

0

0

1

1

0

0

1

1

0

1

0

1

1

0

0

1

1

0

0

1

1

0

0

1

1

0

VID0

1

0

1

0

1

0

1

0

1

0

1

0

1

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

V

CC

(V)

0.0625

0.0500

0.0375

0.0250

0.0125

0.0000

0.0000

0.0000

0.0000

0.0000

0.0000

0.0000

0.0000

0.2625

0.2500

0.2375

0.2250

0.2125

0.2000

0.1875

0.1750

0.1625

0.1500

0.1375

0.1250

0.1125

0.1000

0.0875

0.0750

Datasheet 89

Electrical Specifications

1.

2.

Table 7-36.Market Segment Selection Truth Table for MSID[2:0]

MSID[2] MSID[1] MSID[0] Description 1,2

1

1

1

1

0

0

0

0

1

1

0

0

1

1

0

0

0

1

0

1

0

1

0

1

Reserved

Reserved

Reserved

Reserved

Standard Voltage (SV) 35-W Supported

Reserved

Reserved

Reserved

NOTES:

MSID[2:0] signals are provided to indicate the maximum platform capability to the processor.

MSID is used on rPGA988A platforms only.

3.

Processors specified for use with a -1.9 m

Notes

3

7.5

Reserved or Unused Signals

The following are the general types of reserved (RSVD) signals and connection guidelines:

• RSVD - these signals should not be connected

•

RSVD_TP - these signals should be routed to a test point

• RSVD_NCTF - these signals are non-critical to function and may be left unconnected

Arbitrary connection of these signals to V

CC

, V

TT

, V

DDQ

, V

CCPLL

, V

AXG

, V

SS

, or to any other signal (including each other) may result in component malfunction or incompatibility with future processors. See Chapter 8 for a pin listing of the processor and the location of all reserved signals.

For reliable operation, always connect unused inputs or bi-directional signals to an appropriate signal level. Unused active high inputs should be connected through a resistor to ground (V

SS

). Unused outputs maybe left unconnected; however, this may interfere with some Test Access Port (TAP) functions, complicate debug probing, and prevent boundary scan testing. A resistor must be used when tying bi-directional signals to power or ground. When tying any signal to power or ground, a resistor will also allow for system testability. Resistor values should be within ±20% of the impedance of the baseboard trace, unless otherwise noted in the appropriate platform design guidelines. For details see Table 7-44 .

90 Datasheet

Electrical Specifications

7.6

Signal Groups

Signals are grouped by buffer type and similar characteristics as listed in Table 7-37 .

The buffer type indicates which signaling technology and specifications apply to the signals. All the differential signals, and selected DDR3 and Control Sideband signals have On-Die Termination (ODT) resistors. There are some signals that do not have ODT and need to be terminated on the board.

Table 7-37.Signal Groups

1

(Sheet 1 of 3)

Signal Group

Alpha

Group

Type

System Reference Clock

Differential (a) CMOS Input

Signals

CMOS Output

BCLK, BCLK#

PEG_CLK, PEG_CLK#

DPLL_REF_SSCLK, DPLL_REF_SSCLK#

BCLK_ITP, BCLK_ITP# Differential

DDR3 Reference Clocks

2

Differential

(b)

(c) DDR3 Output SA_CK[1:0], SA_CK#[1:0]

SB_CK[1:0], SB_CK#[1:0]

DDR3 Command Signals

2

Single Ended (d) DDR3 Output SA_RAS#, SB_RAS#, SA_CAS#, SB_CAS#

SA_WE#, SB_WE#

SA_MA[15:0], SB_MA[15:0]

SA_BS[2:0], SB_BS[2:0]

SA_DM[7:0], SB_DM[7:0]

SM_DRAMRST#

SA_CS#[1:0], SB_CS#[1:0]

SA_ODT[1:0], SB_ODT[1:0]

SA_CKE[1:0], SB_CKE[1:0]

DDR3 Data Signals

2

Single ended

Differential

(e)

(f)

DDR3 Bi-directional SA_DQ[63:0], SB_DQ[63:0]

DDR3 Bi-directional SA_DQS[7:0], SA_DQS#[7:0]

SB_DQS[7:0], SB_DQS#[7:0]

TAP (ITP/XDP)

Single Ended

Single Ended

Single Ended

Single Ended

(g)

(ga)

(h)

(i)

CMOS Input

CMOS Input

CMOS Open-Drain

Output

Asynchronous

CMOS Output

TCK, TMS, TRST#

TDI,TDI_M

TDO, TDO_M

TAPPWRGOOD

Datasheet 91

Electrical Specifications

Table 7-37.Signal Groups

1

(Sheet 2 of 3)

Signal Group

Alpha

Group

Type

Control Sideband

Single Ended (ja)

Single Ended

Single Ended

Single Ended

Single Ended

Single Ended

Single Ended

Single Ended

Single Ended

(jb)

(k)

(l)

(m)

(n)

(o)

(p)

(qa)

Asynchronous

CMOS Input

Asynchronous

CMOS Input

Asynchronous

CMOS Output

Asynchronous GTL

Output

Asynchronous GTL

Input

GTL Bi-directional

Asynchronous Bidirectional

Asynchronous GTL

Bi-directional

CMOS Input

Single Ended

Single Ended

Single Ended

Single Ended

(qb)

(r)

(s)

(t)

(ta)

CMOS Input

CMOS Output

CMOS

Bi-directional

Analog Input

Analog Output

Signals

V

CCPWRGOOD_0

, V

CCPWRGOOD_1

, V

TTPWRGOOD

SM_DRAMPWROK

RESET_OBS#

PRDY#, THERMTRIP#

PREQ#

CATERR#, BPM#[7:0]

PECI

PROCHOT#

PM_SYNC, PM_EXT_TS#[0], PM_EXT_TS#[1],

CFG[17:0]

RSTIN#

PROC_DPRSLPVR

VID[6]

V

TT_SELECT

VID[5:3]/CSC[2:0]

VID[2:0]/MSID[2:0]

COMP0, COMP1, COMP2, COMP3,

SM_RCOMP[2:0], I

SENSE

SA_DIMM_VREFDQ

5

, SB_DIMM_VREFDQ

5

Single Ended

Power/Ground/Other

Single Ended (u) Power

(v)

(w)

(x)

(y)

Ground

No Connect /Test

Point

Asynchronous

CMOS Output

Sense Points

V

V

CC

, V

TT0

DDQ_CK

3

, V

TT1

, V

CCPLL

, V

DDQ

, V

AXG

, V

TT0_DDR

3

,

V

SS

, V

SS_NCTF

, DC_TEST_xx# 3

RSVD, RSVD_TP, RSVD_NCTF

PSI#

(z) Other

V

CC_SENSE

, V

SS_SENSE

, V

TT_SENSE

, V

SS_SENSE_VTT

,

V

AXG_SENSE

, V

SSAXG_SENSE

SKTOCC#, DBR#, PROC_DETECT 3 , VCAP0 3 ,

VCAP 3 , VCAP2 3

92 Datasheet

Electrical Specifications

Table 7-37.Signal Groups

1

(Sheet 3 of 3)

Signal Group

Alpha

Group

Type

Integrated Graphics

Single Ended

Single Ended

PCI Express* Graphics

Differential

Differential

Single Ended

(aa)

(ab)

(ac)

(ad)

(ae)

Analog Input

CMOS Output

Signals

GFX_IMON

GFX_VID[6:0], GFX_VR_EN, GFX_DPRSLPVR

PCI Express Input PEG_RX[15:0], PEG_RX#[15:0]

PCI Express Output PEG_TX[15:0], PEG_TX#[15:0]

Analog Input PEG_ICOMP0, PEG_ICOMPI, PEG_RCOMP0,

PEG_RBIAS

DMI

Differential

Differential

Intel® FDI

Single Ended

Differential

(af)

(ag)

(ah)

(ai)

DMI Input

DMI Output

CMOS Input

Analog Output

DMI_RX[3:0], DMI_RX#[3:0]

DMI_TX[3:0], DMI_TX#[3:0]

FDI_FSYNC[1:0], FDI_LSYNC[1:0], FDI_INT

FDI_TX[7:0], FDI_TX#[7:0]

NOTES:

1.

Refer to Chapter 6 for signal description details.

2.

3.

4.

SA and SB refer to DDR3 Channel A and DDR3 Channel B.

These signals are only applicable for the BGA package

These signals are only applicable for the rPGA988A package.

All Control Sideband Asynchronous signals are required to be asserted/deasserted for at least eight BCLKs in order for the processor to recognize the proper signal state. See

Section 7.10

for the DC specifications.

7.7

Test Access Port (TAP) Connection

Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, Intel recommends the processor be first in the TAP chain, followed by any other components within the system. A translation buffer should be used to connect to the rest of the chain unless one of the other components is capable of accepting an input of the appropriate voltage. Two copies of each signal may be required with each driving a different voltage level.

Datasheet 93

Electrical Specifications

7.8

Absolute Maximum and Minimum Ratings

Table 7-38 specifies absolute maximum and minimum ratings. At conditions outside functional operation condition limits, but within absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. If a device is returned to conditions within functional operation limits after having been subjected to conditions outside these limits (but within the absolute maximum and minimum ratings) the device may be functional, but with its lifetime degraded depending on exposure to conditions exceeding the functional operation condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-term reliability can be expected. Moreover, if a device is subjected to these conditions for any length of time it will either not function or its reliability will be severely degraded when returned to conditions within the functional operating condition limits.

Although the processor contains protective circuitry to resist damage from Electro-

Static Discharge (ESD), precautions should always be taken to avoid high static voltages or electric fields.

Table 7-38.Processor Absolute Minimum and Maximum Ratings

Symbol

V

CC

V

TT

V

V

V

DDQ

CCPLL

AXG

Parameter

Processor Core voltage with respect to V

SS

Voltage for the memory controller and Shared Cache with respect to V

SS

Processor I/O supply voltage for DDR3 with respect to

V

SS

Processor PLL voltage with respect to V

SS

Graphics voltage with respect to V

SS

SV

ULV

Min

-0.3

-0.3

-0.3

-0.3

-0.3

-0.3

Max

1.40

1.40

1.80

1.98

1.55

1.55

Unit

V

V

V

V

V

Notes

1, 2

NOTES:

1.

For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must be satisfied.

2.

V

CC and V

AXG

are VID based rails.

7.9

Storage Conditions Specifications

Environmental storage condition limits define the temperature and relative humidity to which the device is exposed to while being stored in a moisture barrier bag. The specified storage conditions are for component level prior to board attach.

Table 7-39 specifies absolute maximum and minimum storage temperature limits which represent the maximum or minimum device condition beyond which damage, latent or otherwise, may occur. The table also specifies sustained storage temperature, relative humidity, and time-duration limits. these limits specify the maximum or minimum

94 Datasheet

Electrical Specifications device storage conditions for a sustained period of time. At conditions outside sustained limits, but within absolute maximum and minimum ratings, quality and reliability may be affected.

Table 7-39.Storage Condition Ratings

Symbol Parameter

T

T absolute storage sustained storage

RH sustained storage

Time

sustained storage

The non-operating device storage temperature.

Damage (latent or otherwise) may occur when exceeded for any length of time.

The ambient storage temperature (in shipping media) for a sustained period of time)

The maximum device storage relative humidity for a sustained period of time.

A prolonged or extended period of time; typically associated with customer shelf life.

Min

-25°C

-5°C

0 Months

Max

125°C

40°C

60% @ 24°C

6 Months

Notes

1, 2, 3, 4

5, 6

6, 7

7

NOTES:

1.

Refers to a component device that is not assembled in a board or socket and is not electrically connected to

2.

a voltage reference or I/O signal.

Specified temperatures are not to exceed values based on data collected. Exceptions for surface mount

3.

reflow are specified by the applicable JEDEC standard. Non-adherence may affect processor reliability.

T absolute storage

applies to the unassembled component only and does not apply to the shipping media, moisture barrier bags, or desiccant.

4.

5.

6.

7.

Component product device storage temperature qualification methods may follow JESD22-A119 (low temp) and JESD22-A103 (high temp) standards when applicable for volatile memory.

Intel® branded products are specified and certified to meet the following temperature and humidity limits that are given as an example only (Non-Operating Temperature Limit: -40°C to 70°C and Humidity: 50% to 90%, non-condensing with a maximum wet bulb of 28°C.) Post board attach storage temperature limits are not specified for non-Intel branded boards.

The JEDEC J-JSTD-020 moisture level rating and associated handling practices apply to all moisture sensitive devices removed from the moisture barrier bag.

Nominal temperature and humidity conditions and durations are given and tested within the constraints imposed by T sustained storage and customer shelf life in applicable Intel boxes and bags.

7.10

DC Specifications

The processor DC specifications in this section are defined at the processor

pins, unless noted otherwise. See Chapter 8 for the processor pin listings and

Chapter 6 for signal definitions.

The DC specifications for the DDR3 signals are listed in Table 7-43 Control Sideband and Test Access Port (TAP) are listed in Table 7-44 .

Table 7-40 lists the DC specifications for the processor and are valid only while meeting specifications for junction temperature, clock frequency, and input voltages. Care should be taken to read all notes associated with each parameter.

Datasheet 95

Electrical Specifications

7.10.1

Voltage and Current Specifications

Table 7-40.Processor Core (VCC) Active and Idle Mode DC Voltage and Current

Specifications

V

I

I

I

Symbol

HFM_VID

LFM_VID

CC

CCMAX

CC_TDC

CC_LFM

I

C6

TOL

VID

VR Step

SLOPE

LL

Parameter

VID Range for Highest

Frequency Mode

VID Range for Lowest

Frequency Mode

V

CC

for processor core

Maximum Processor

Core I

CC

Thermal Design I

CC

I

I

CC

CC

at LFM

at C6 Idle-state

VID Tolerance

VID resolution

Processor Loadline

Segment

SV

ULV

SV

ULV

SV

ULV

SV

ULV

SV

ULV

ULV

SV

ULV

Min Typ Max

0.800

0.750

0.775

0.725

1.4

1.4

1.0

1.0

See Figure 7-13 and Figure 7-14

48

27

32

16

18

8

0.3

See Figure 7-13 and Figure 7-14

12.5

-1.9

-3.0

-0.9

Unit

V

V

V

A

A

A

A mV m

Note

1,2,7

1,2

2, 3, 4

5,7

6,7

6

Non-VR LL contribution

Non-VR Loadline

Contribution for V

CC m

5.

6.

7.

NOTES:

1.

Unless otherwise noted, all specifications in this table are based on pre-silicon estimates and simulations or empirical data. These specifications will be updated with characterized data from silicon measurements at

2.

a later date.

Each processor is programmed with a maximum valid voltage identification value (VID), which is set at manufacturing and cannot be altered. Individual maximum VID values are calibrated during manufacturing

3.

4.

such that two processors at the same frequency may have different settings within the VID range. Please note this differs from the VID employed by the processor during a power or thermal management event

(Intel Adaptive Thermal Monitor, Enhanced Intel SpeedStep Technology, or Low Power States).

The voltage specification requirements are defined across VCC_SENSE and VSS_SENSE pins on the bottom side of the baseboard.

Refer to Figure 7-13 and Figure 7-14 for the minimum, typical, and maximum V

CC

allowed for a given current. The processor should not be subjected to any V

CC

and I

CC

combination wherein V

CC

exceeds

V

CC_MAX

for a given current.

Processor core VR to be designed to electrically support this current

Processor core VR to be designed to thermally support this current indefinitely.

This specification assumes that Intel Turbo Boost Technology with Intelligent Power Sharing is enabled.

96 Datasheet

Electrical Specifications

Figure 7-13.Active V

CC

and I

CC

Loadline (PSI# Asserted)

V

C C

[ V ]

V

C C m a x

V

C C , D C m a x

V

C C n o m

S l o p e = S L O P E

L L

V C C _ S E N S E , V S S _ S E N S E p i n s .

D i f f e r e n t ia l R e m o t e S e n s e r e q u ir e d .

1 3 m V = R I P P L E

V

C C , D C m in

V

C C m in

± V

C C

T o le r a n c e

= V R S t . P t . E r r o r

0

V

C C

S e t P o i n t E r r o r T o l e r a n c e i s p e r b e l o w :

I

C C m a x

I

C C

[ A ]

T o l e r a n c e

- - - - - - - - - - - - - - -

±

V

C C - C O R E

V I D V o l t a g e R a n g e

- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

[ V I D * 1 . 5 % - 3 m V ] V

C C

> 0 . 7 5 0 0 V

± [ 1 1 . 5 m V - 3 m V ] 0 . 5 0 0 0 V < V

C C

= 0 . 7 5 0 0 V

Figure 7-14.Active V

CC

and I

CC

Loadline (PSI# Not Asserted)

V

CC

[V]

Slope = SLOPE

LL

VCC_SENSE, VSS_SENSE pins.

Differential Remote Sense required.

V

CC max

V

CC, DC max

V

CC nom

10mV= RIPPLE

V

CC, DC min

V

CC min

± V

CC

Tolerance

= VR St. Pt. Error

I

CC

[A]

0

V

CC

Set Point Error Tolerance is per below:

Tolerance

---------------

± [VID*1.5%]

I

CC max

V

CC- CO RE

VID Voltage Range

-------------------------------------------------------

V

CC

> 0.7500V

± [11.5mV] 0.5000V < V

CC

=0.7500V

Datasheet 97

Electrical Specifications

Table 7-41.Processor Uncore I/O Buffer Supply DC Voltage and Current Specifications

Symbol Unit Note

V

TT

V

DDQ

(DC+AC)

V

CCPLL

TOL

TT

TOL

DDQ

TOL

CCPLL

I

CCMAX_VTT

I

CCMAX_VDDQ

I

CCMAX_VDDQ_CK

I

CCMAX_VTT0_DDR

I

CCMAX_VCCPLL

I

CCTDC_VTT

I

CCAVG_VDDQ

(Standby)

Parameter Min Typ Max

Voltage for the memory controller and shared cache defined at the motherboard Vtt pinfield via

Voltage for the memory controller and shared cache defined across

VTT_SENSE and VSS_SENSE_VTT

Processor I/O supply voltage for DDR3

(DC + AC specification)

PLL supply voltage (DC + AC specification)

V

TT

Tolerance defined at the socket motherboard VTT pinfield via

V

TT

Tolerance defined across

VTT_SENSE and VSS_SENSE_VTT

VDDQ Tolerance

VCCPLL Tolerance

Max Current for V

TT

Rail

SV

ULV

Max Current for V

DDQ

Rail

Max Current for V

CCPLL

Rail

Thermal Design Current

(TDC) for V

TT

Rail

SV

ULV

Average Current for V

DDQ

Rail during

Standby

0.9975

0.9765

1.425

1.710

1.05

1.05

1.5

1.8

1.1025

1.1235

1.575

1.890

DC: ±2%

AC: ±3% including ripple

DC: ±2%

AC: ±5% including ripple

DC= ±3%

AC= ±2%

AC+DC= ±5%

AC+DC= ±5%

-

-

-

-

18

16

3

0.2

2.6

1.35

-

18

16

0.33

V

V

V

V

%

%

%

A

A

A

A

A

A

A

1

2

1

2

3

4

4

3

5

3.

4.

5.

NOTES:

1.

2.

The voltage specification requirements are defined across at the socket motherboard pinfield vias on the bottom side of the baseboard.

The voltage specification requirements are defined across VTT_SENSE and VSS_SENSE_VTT pins on the bottom side of the baseboard.

Defined at nominal VTT voltage

These are pre-silicon estimates and are subject to change.

Based on junction temperature of 50°C.

98 Datasheet

Electrical Specifications

Table 7-42.Processor Graphics VID based (V

AXG

Specifications

) Supply DC Voltage and Current

Symbol

GFX_VID

V

AXG

TOL

AXG

Non-VR LL contribution

LL

AXG

I

CCMAX_VAXG

I

CCTDC_VAXG

Parameter

VID Range for V

AXG

SV

ULV

Graphics core voltage

V

AXG

Tolerance

Non-VR Load Line Contribution for

V

AXG rPGA

BGA

V

AXG

Loadline

Max Current for Integrated

Graphics Rail

SV

ULV

Thermal Design Current

(TDC) for Integrated Graphics Rail

SV

ULV

Min

0

0

Typ

See Figure 7-15

See Figure 7-15

4

4.25

-7

-

-

Max

1.4

1.35

22

12

12

6

Unit

V m m

A

A

Note 1

2,3,4

4

4

NOTES:

1.

2.

3.

4.

These are pre-silicon estimates and are subject to change.

Minimum values assume Graphics Render C-state (RC6) is enabled.

V

AXG

is a VID-Based rail driven by an Intel MVP6.5 compliant voltage regulator.

This specification assumes Intel Turbo Boost Technology with Intelligent Power Sharing is enabled.

Figure 7-15.V

AXG

/I

AXG

Static and Ripple Voltage Regulation

V

AXG

[V]

Slope = LL

AXG at package VAXG_SENSE, and VSSAXG_SENSE pins

Differential Remote Sense required.

V

AXG_MAX

=

V

AXG_NOM

+2.2%*GFX_VID

V

AXG_NOM

= GFX_VID

V

AXG_MIN

=

V

AXG_NOM

-LL

AXG

*I

CCMAX_VAXG

-2.2%*GFX_VID

0

+ / - V I D * 2 . 2 %

V

AXG

Total tolerance window (GFX_DPRSLPVR de-asserted)

DC (set point +LL tolerance)+ AC (ripple) for Standard and Enhanced Performance Frequency Modes

I

AXG

[A]

I

CCMAX_VAXG

Datasheet 99

Electrical Specifications

Table 7-43.DDR3 Signal Group DC Specifications

Symbol

V

V

IL

V

IH

V

OL

OH

Parameter

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

R

R

R

R

R

ON

ON

ON

ON

ON

DDR3 Clock Buffer On

Resistance

DDR3 Clock Buffer On

Resistance

DDR3 Command Buffer

On Resistance

DDR3 Command Buffer

On Resistance

DDR3 Control Buffer On

Resistance

R

R

ON

ON

DDR3 Control Buffer On

Resistance

DDR3 Data Buffer On

Resistance

R

ON

DDR3 Data Buffer On

Resistance

Data ODT On-Die Termination for

Data Signals

I

LI

SM_RCOMP0

SM_RCOMP1

SM_RCOMP2

Input Leakage Current

COMP Resistance

COMP Resistance

COMP Resistance

Alpha

Group

(e,f)

(e,f)

(c,d,e,f)

Min

0.57*V

DDQ

(c,d,e,f)

Typ

(V

DDQ

/ 2)* (R

ON

/

(R

ON

+R

VTT_TERM

))

V

DDQ

- ((V

DDQ

/

2)* (R

ON

/

(R

ON

+R

VTT_TERM

))

21

(d)

(t)

(t)

(t)

21

16

20

21

20

21

21

102

51

99

24.7

128.7

100

24.9

130

Max

0.43*V

DDQ

31

36

24

31

31

31

31

36

138

69

±500

101

25.1

131.3

Units

V

V

V

A

Notes

1

8

8

8

2,4

3

6

4,6

5

5

5

5

5

5

5

5

7

5.

6.

7.

8.

NOTES:

1.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2.

3.

V

IL

is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.

V

IH

is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high value.

4.

V

IH

and V

OH

may experience excursions above V

DDQ

. However, input signal drivers must comply with the signal quality specifications.

This is the pull down driver resistance. Refer to processor I/O Buffer Models for I/V characteristics.

R

VTT_TERM

is the termination on the DIMM and in not controlled by the Processor.

The minimum and maximum values for these signals are programmable by BIOS to one of the two sets.

COMP resistance must be provided on the system board with 1% resistors. COMP resistors are to V

SS

.

100 Datasheet

Electrical Specifications

Table 7-44.Control Sideband and TAP Signal Group DC Specifications

Symbol

V

IL

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

IH

V

IL

V

IH

V

OL

Alpha Group

(m),(n),(p),(s)

(m),(n),(p),(s)

(g)

(g)

(ga)

(ga)

(qa)

(qa)

(ja),(qb)

(ja),(qb)

(jb)

(jb)

(k),(l),(n),(p),

(r),(s),(ab),(h),(i)

Parameter

Input Low Voltage

Input High Voltage

Input Low Voltage

Input High Voltage

Input Low Voltage

Input High Voltage

Input Low Voltage

Input High Voltage

Input Low Voltage

Input High Voltage

Input Low Voltage

Input High Voltage

Output Low Voltage

V

OH

(k),(l),(n),(p),(r),(s),( ab),(i)

R

ON

(k),(l),(n),(p),(r),(s),(i

)

(ab) R

ON

I

LI

(ja),(jb),(m),(n),(p),( qa),(s),(t),(aa),(g)

I

LI

(qb)

COMP0 (t)

COMP1 (t)

COMP2 (t)

COMP3 (t)

Output High Voltage

Buffer on Resistance

Buffer on Resistance

Input Leakage Current

Input Leakage Current

COMP Resistance

COMP Resistance

COMP Resistance

COMP Resistance

Min

0.76

*

V

TT

0.80

*

V

TT

0.75

*

V

TT

0.70

*

V

TT

0.75

*

V

TT

0.87

V

TT

10

20-30

49.4

49.4

19.8

19.8

Typ

49.9

49.9

20

20

Max

0.64

*

V

0.25

*

0.4

*

0.38

*

0.25

*

V

V

V

V

0.29

TT

TT

TT

TT

TT

V

TT

* R

ON

/

(R

ON

+

R

SYS_TERM

)

Units Notes 1,8

V

V

V

V

V

V

V

V

V

V

V

V

2,3

2,3,5

2,3

2,3,5

2,3

2,3,5

2,3

2,3,5

2,3

2,3,5

2,3

2,3,5

2,7

V 2,5

18

27-45

±200

±150

50.4

50.4

20.2

20.2

A

A

4

6

6

4

6

6

NOTES:

1.

Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2.

3.

4.

5.

6.

7.

The V

TT

referred to in these specifications refers to instantaneous V

Refer to the processor I/O Buffer Models for I/V characteristics.

TT

.

For V

IN

between “0” V and V

TT

. Measured when the driver is tristated.

V

IH and V

OH may experience excursions above V signal quality specifications.

TT

. However, input signal drivers must comply with the

COMP resistance must be provided on the system board with 1% resistors. COMP resistors are to V

SS

.

R

SYS_TERM

is the system termination on the signal.

Datasheet 101

Electrical Specifications

Table 7-45.PCI Express DC Specifications

V

V

Z

Z

V

V

Symbol

TX-DIFF-p-p

TX_CM-AC-p

TX-DIFF-DC

Z

RX-DC

RX-DIFF-DC

RX-DIFFp-p

RX_CM-AC-p

PEG_ICOMPO

PEG_ICOMPI

PEG_RCOMPO

PEG_RBIAS

Alpha

Group

(ad)

(ad)

(ad)

(ac)

(ac)

(ac)

(ac)

(ae)

(ae)

(ae)

(ae)

Parameter

Differential Peak-to-Peak Tx Voltage

Swing

Tx AC Peak Common Mode Output

Voltage (Gen 1 Only)

DC Differential Tx Impedance

(Gen 1 Only)

DC Common Mode Rx Impedance

DC Differential Rx Impedance

(Gen1 Only)

Differential Rx Input Peak-to-Peak

Voltage (Gen 1 only)

Rx AC Peak Common Mode Input

Voltage

Comp Resistance

Comp Resistance

Comp Resistance

Comp Resistance

Min

0.8

80

40

80

0.175

Typ Max

1.2

20

120

60

120

1.2

150

Units

V mV

V mV

Notes

1

3

1,2,6

1,10

1,8,9

1

1,11

1,7

49.5

49.5

49.5

742.5

50

50

50

750

50.5

50.5

50.5

757.5

4,5

4,5

4,5

4,5

4.

5.

6.

NOTES:

1.

Refer to the PCI Express Base Specification for more details.

2.

3.

V

TX-AC-CM-PP

and V

TX-AC-CM-P at least 10^

6

UI.

are defined in the PCI Express Base Specification. Measurement is made over

As measured with compliance test load. Defined as 2*|V

TXD+

- V

TXD-

|.

COMP resistance must be provided on the system board with 1% resistors. COMP resistors are to V

SS

.

PEG_ICOMPO, PEG_ICOMPI, PEG_RCOMPO are the same resistor

RMS value.

7.

8.

9.

10.

Measured at Rx pins into a pair of 50terminations into ground. Common mode peak voltage is defined by the expression: max{|(Vd+ - Vd-) - V-CMDC|}.

DC impedance limits are needed to guarantee Receiver detect.

The Rx DC Common Mode Impedance must be present when the Receiver terminations are first enabled to ensure that the Receiver Detect occurs properly. Compensation of this impedance can start immediately and the 15 Rx Common Mode Impedance (constrained by RLRX-CM to 50 ±20%) must be within the specified range by the time Detect is entered.

Low impedance defined during signaling. Parameter is captured for 5.0 GHz by RLTX-DIFF.

102 Datasheet

Electrical Specifications

Table 7-46.eDP DC Specifications

Symbol Parameter eDP_HPD#

V

IL

Input Low Voltage

V

IH eDP_AUX, eDP_AUX#

Input High Voltage

V

AUX-DIFFp-p

(Tx)

V

AUX-DIFFp-p

(Rx)

AUX Peak-to-Peak Voltage at the transmitting device

AUX Peak-to-Peak Voltage at the receiving device eDP COMPs eDP_ICOMPO eDP_ICOMPI eDP_RCOMPO eDP_RBIAS

Comp Resistance

Comp Resistance

Comp Resistance

Comp Resistance

Min

-0.3

0.6

0.39

0.32

49.5

49.5

49.5

742.5

Typ

50

50

50

750

Max

0.3

1.155

1.38

1.36

50.5

50.5

50.5

757.5

Units

V

V

V

Notes

4

1

1

2,3

2,3

2,3

2,3

NOTES:

1.

V

AUX-DIFFp-p

= 2*|V

AUXP

– V

AUXM

|. Please refer to the VESA DisplayPort Standard specification for more details.

2.

3.

4.

COMP resistance must be provided on the system board with 1% resistors. See the applicable platform design guide for implementation details. COMP resistors are to V

SS

.

eDP_ICOMPO, eDP_ICOMPI, eDP_RCOMPO are the same resistor.

These are pre-silicon estimates and are subject to change.

7.11

Platform Environmental Control Interface (PECI)

DC Specifications

PECI is an Intel proprietary interface that provides a communication channel between

Intel processors and chipset components to external Adaptive Thermal Monitor devices.

The processor contains a Digital Thermal Sensor (DTS) that reports a relative die temperature as an offset from Thermal Control Circuit (TCC) activation temperature.

Temperature sensors located throughout the die are implemented as analog-to-digital converters calibrated at the factory. PECI provides an interface for external devices to read the DTS temperature for thermal management and fan speed control. More detailed information may be found in the Platform Environment Control Interface

(PECI) Specification.

7.11.1

DC Characteristics

The PECI interface operates at a nominal voltage set by V

TT

. The set of DC electrical specifications shown in Table 7-47 is used with devices normally operating from a V

TT interface supply. V

TT

nominal levels will vary between processor families. All PECI devices will operate at the V

TT

level determined by the processor installed in the system. For specific nominal V

TT

levels, refer to Table 7-43 .

Datasheet 103

Electrical Specifications

Table 7-47.PECI DC Electrical Limits

Symbol

V in

V hysteresis

V n

V p

I source

I sink

I leak+

I leak-

C bus

V noise

Definition and Conditions

Input Voltage Range

Hysteresis

Negative-edge Threshold Voltage

Positive-edge Threshold Voltage

High-Level Output Source

(V

OH

= 0.75 * V

TT

)

Low-Level Output Sink

(V

OL

= 0.25 * V

TT

)

High-Impedance State Leakage to V

TT

(V leak

= V

OL

)

High-Impedance Leakage to GND

(V leak

= V

OH

)

Bus Capacitance Per Node

Signal Noise Immunity above 300 MHz

Min

-0.150

0.1 * V

TT

0.275 * V

TT

0.550 * V

TT

-6.0

0.5

N/A

N/A

N/A

0.1 * V

TT

Max

V

TT

N/A

0.500 * V

TT

0.725 * V

TT

N/A

1.0

100

100

10

N/A mA

µA

µA

NOTES:

1.

2.

V

TT supplies the PECI interface. PECI behavior does not affect V

TT

min/max specifications.

The leakage specification applies to powered devices on the PECI bus.

pF

V p-p

Units

V

V

V

V mA

Notes

1

2

2

7.11.2

Input Device Hysteresis

The input buffers in both client and host models must use a Schmitt-triggered input design for improved noise immunity. Use Figure 7-16 as a guide for input buffer design.

Figure 7-16.Input Device Hysteresis

V

TTD

Maximum V

P

Minimum V

P

PECI High Range

Minimum

Hysteresis

Valid Input

Signal Range

Maximum V

N

Minimum V

N

PECI Ground

PECI Low Range

104 Datasheet

Processor Pin and Signal Information

8

8.1

Processor Pin and Signal

Information

Processor Pin Assignments

•

Provides a listing of all processor pins ordered alphabetically by pin name for the rPGA988A and BGA1288 package respectively.

• Table 8-48 and Table 8-51 provides a listing of all processor pins ordered alphabetically by pin number for the rPGA988A and BGA1288 package respectively

•

Figure 8-21 , Figure 8-22 , Figure 8-23 , Figure 8-24 show the Top-Down view of the rPGA988A pinmap.

• Figure 8-21 , Figure 8-22 , Figure 8-23 , Figure 8-24 show the Top-Down view of the

BGA1288 ballmap.

Datasheet 105

Processor Pin and Signal Information

Figure 8-17.Socket-G (rPGA988A) Pinmap (Top View, Upper-Left Quadrant)

VTT0

SB_CK# [

0]

SB_CK[ 0] VDDQ

VSS

SA_M A[ 15

]

SA_M A[6

]

SB_CK[1]

VTT0 RSVD VSS SA_BS[ 2]

VTT0 RSVD SB_M A[ 5] VDDQ

VSS RSVD_TP RSVD_TP SB_BS[ 2]

VTT1

SA_DIM M

_VREF

VTT0 VTT0

VSS

SB_DIM M

_VREF

RSVD_TP VSS

VTT0

VTT0

FDI_TX# [

7]

RSVD COM P1

VTT_SELE

CT

VTT0

FDI_LSYN

C[0]

FDI_FSYN

C[ 0]

VSS RSVD_TP VTT0

VTT0

VSS

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

SA_DQ[ 31

]

VSS

SA_CKE[0

]

VTT0

SA_DQS#

[ 3]

SA_DQ[ 3

0]

VDDQ

VSS

SA_DQS[

3]

SA_DQ[ 2

6]

SA_DM [3

]

VTT0

SA_DQ[ 27

]

VSS

SA_DQ[ 2

4]

VTT0 VSS

SA_DQ[ 2

9]

SA_DQ[ 18

]

VTT0

SA_DQ[ 2

3]

SA_DQS#

[ 2]

SA_DQ[ 19

]

SA_DQ[ 2

2]

VSS

SA_DQ[ 16

]

SA_DQS[

2]

VSS

SA_DM [2

]

VTT0

SA_DQ[ 21

]

VSS

SA_DQ[ 17

]

SA_DQ[ 2

0]

VTT0 SA_DQ[ 9]

SA_DQS[1

]

SA_DQS#

[ 1]

SA_DQ[ 11]

106 Datasheet

Processor Pin and Signal Information

Figure 8-18.Socket-G (rPGA988A) Pinmap (Top View, Upper-Right Quadrant)

2 3 2 2 2 1 2 0 19 18 17 16 15 14 13

COM P3

VSSAXG_SE

NSE

VAXG VSS

VSS

VAXG_SEN

SE

VAXG VSS

VAXG VAXG

VAXG VAXG

VSS

VSS

VAXG PECI

SA_DQ[ 59

]

SA_DQS#

[7]

VAXG VSS

SA_DQ[6

2]

SA_DQS[

7]

GFX_VID[3] GFX_VID[ 1] VAXG VSS VAXG VAXG

VSS GFX_VID[2] VAXG VSS VAXG VAXG

VSS VAXG

PM _EXT_

TS# [1]

SA_DQ[6

3]

VSS

VSS VAXG

PM _EXT_

TS# [0]

VCCPWR

GOOD_1

SA_DM [7

]

GFX_VID[4] GFX_VID[0] VAXG VSS VAXG VAXG

VSS RSVD VAXG VSS VAXG VAXG

VSS VAXG

VTTPWR

GOOD

VSS

SA_DQ[ 5

8]

VSS VAXG

PM _SYN

C

RSTIN#

SA_DQ[61

]

BPM # [ 6] BPM # [1] VAXG VSS VAXG VAXG VSS VAXG

THERM TR

IP#

CATERR#

SM _DRA

M PWROK

VSS BPM # [ 0] VAXG VSS VAXG VAXG VSS VAXG RSVD VSS RSVD_TP

BPM # [ 7] BPM # [5] VAXG VSS VAXG VAXG VSS VAXG RSVD VTT0 VSS

Datasheet 107

Processor Pin and Signal Information

Figure 8-19.Socket-G (rPGA988A) Pinmap (Top View, Lower-Left Quadrant)

U

T

V CC

VSS

VCC

VSS

V CC

VSS

VCC

VSS

VCC

VSS

VC C

VS S

V CC

VSS

VC C

VS S

V CC

VSS

VC C

VS S

R

P

V CC

V CC

VCC

VCC

V CC

V CC

VCC

VCC

VCC

VCC

VC C

VC C

V CC

V CC

VC C

VC C

V CC

V CC

VC C

VC C

N

M

L

K

J

H

G

F

E

D

C

B

A

VSS VSS VSS VSS VSS VS S VSS VS S VSS VS S

PE G _ TX

# [1]

PE G _T X

[1 ]

P EG _ T X

# [2]

PE G _T X

[ 2]

P EG _ T X

[4 ]

PE G _ TX

#[3 ]

P EG _ T X

# [6 ]

PE G _ TX

[6]

VSS

PE G _T X

[0 ]

P EG _ T X

# [0]

VSS

P EG _ T X

# [4 ]

PE G _ TX

[3]

VSS RSVD

RS VD V CCP LL

VCC PLL V CCP LL

PE G _ RX

# [0]

VSS VSS

PE G _ RX

[0 ]

P EG _ RX

#[1 ]

PE G _ RX

# [2]

PE G _T X

#[5 ]

P EG _ T X

[5 ]

VSS

P EG _ T X

# [7 ]

VSS

P EG _ RX

[1 ]

PE G _ RX

[2 ]

VSS

VS S

VS S

P EG _ T X

# [8 ]

RS VD

P EG _ T X

[7 ]

PE G _ TX

#[9 ]

P EG _ T X

# [1 0]

PE G _ TX

[8]

RSVD

VS S

VSS

V TT 1

V TT 1

VT T1

VT T1

VS S

PE G _ RX

# [3]

VSS

VSS

P EG _ RX

[5 ]

PE G _ RX

[4 ]

PE G _ RX

# [8]

P EG _ RX

#[4 ]

VSS

VSS

PE G _ RX

[3 ]

P EG _ RX

#[5 ]

PE G _ RX

[8 ]

P EG _ RX

[ 6]

PE G _ RX

# [6 ]

RS VD

PE G _ TX

[9]

P EG _ T X

[1 0 ]

VS S

RSVD VSS

VT T1

P EG _ T X

# [1 1]

PE G _ TX

[1 1]

V TT 1

VSS

PE G _ TX

#[1 2 ]

P EG _ T X

[1 2 ]

VT T1

VT T1

VT T1

VTT 1 VT T1 VTT 1 VT T1 VSS VT T1 VSS VT T1

VTT 1

R SVD

VSS

VTT 1

V S S

D M I_ T X

# [3 ]

V SS VTT 1 VT T1 VTT 1 V SS

D MI_ TX

#[1 ]

D M I_ T X

[3 ]

FD I _ TX[

4]

F D I_ T X

# [4 ]

D MI_ TX

[1]

D M I_ T X

# [2 ]

V SS

F D I_ T X

# [6 ]

V SS

FD I _ TX[

6 ]

F D I_ T X[

7 ]

FD I _ TX

#[ 7]

VSS

FD I _ LS

YN C[0 ]

V SS

D M I_ T X

[2 ]

FD I _ TX

#[0 ]

VSS

FD I _ TX[

5 ]

FD I_ T X

#[5 ]

V SS

PE G _ RX

# [7]

P EG _ RX

[7 ]

RS VD _

N CT F

VSS

VSS

PE G _ RX

# [9]

P EG _ RX

#[1 0 ]

PE G _ RX

[1 0 ]

VSS

PE G _ RX

# [1 2]

VS S

P EG _ RX

[12 ]

P EG _ T X

# [1 3]

PE G _ TX

[1 3]

P EG _ T X

#[1 4]

VSS VS S

P EG _ T X

[1 4 ]

VS S

D M I_ T X

[0 ]

PE G _ TX

#[1 5 ]

P EG _ T X

[1 5 ]

D MI_ TX

#[0 ]

V SS

D MI _ RX

[1 ]

FD I _ TX[

0]

F D I_ T X

# [1 ]

D MI _ RX

# [1 ]

V SS

F DI _ T X[

1 ]

FD I _ TX[

2 ]

FD I_ T X

#[2 ]

V SS VSS

FD I _ TX

#[ 3]

FD I _ TX[

3 ]

RS VD _

N CT F

VSS_ N C

T F

PE G _ RX

[9 ]

P EG _ RX

#[1 1 ]

VSS

P EG _ RX

#[1 4 ]

PE G _ RX

[1 4 ]

P EG _ RX

#[1 3 ]

PE G _ RC

O MP O

PE G _IC

OMP I

VSS

D M I _R X

[0]

D MI _ RX

[2 ]

D M I_R X

#[2 ]

VSS RSVD

VSS _N C

T F

3 5

RSVD _

NC TF

34

RS VD _

N CT F

3 3

P EG _ RX

[11 ]

32

PE G _ RX

# [1 5]

3 1

P EG _ RX

[15 ]

30

VSS

29

P EG _ RX

[1 3]

28

VSS

27

PE G _IC

OM PO

2 6

PE G _ RB

I AS

25

D M I _R X

#[0 ]

2 4

VSS

23

D M I_R X

[3 ]

2 2

D MI_ RX

# [3 ]

21

RSVD

2 0

R SVD

R SVD

19

V SS

DP LL_ R

E F_ SSC

LK

1 8

108 Datasheet

Processor Pin and Signal Information

Figure 8-20.Socket-G (rPGA988A) Pinmap (Top View, Lower-Right Quadrant)

SA_DIM

M _VR EF

VTT0 VTT0 VTT0

SB_DIM

M _VR EF

R SVD_T

P

VSS VTT0

RSVD COM P1

VTT_SE

LECT

VTT0

FDI_FS

YNC [0]

VSS

RSV D_T

P

VTT0

FDI_FS

YNC [1]

P EG_CL

K

RSV D_T

P

VTT0

FDI_L S

YNC [1]

PEG_CL

K#

RSVD VTT0

FDI_IN

T

VSS RSVD VTT0

VSS

DPLL_R

EF _SS C

LK#

BC LK#

BCLK

VTT_SE

NSE

VS S_SE

NSE_VT

T

VTT0

VTT0

17 16 15 14

VTT0

VSS

VTT0

VTT0

VSS

VTT0

VTT0

VSS

VTT0

V TT0

V TT0

V TT0

V TT0

V TT0

V TT0

V TT0

V TT0

V TT0

V TT0 RSVD VSS

SA _B S[

2]

SA_MA[

9]

SB_MA[

0]

VSS

SA_MA[

12]

VSS VDDQ

V TT0 RSVD

SB_MA[

5]

VDDQ VSS

SB_MA[

2]

VDDQ

SA_MA[

14]

SA _MA[

11]

SA_MA [

7]

VSS

RS VD_T

P

RSVD_T

P

SB _B S[

2]

SB_MA[

7]

SB_MA[

9]

SB_MA[

8]

SB_MA[

12]

SB _MA[

6]

SB_MA [

4]

V TT0

S A_DQ[

31]

VSS

S A_C KE

[0]

SA_CK E

[1]

SB_MA[

14]

VSS

SB_MA[

11]

VSS VDDQ

V TT0

S A_DQ

S#[3]

SA_DQ[

30]

VDDQ VSS

S B_DQ [

31]

VDDQ

RS VD_T

P

RSVD_T

P

SB_MA [

15]

VSS

S A_DQ

S [3]

SA_DQ[ SA _DM[

26] 3]

SA_DQ[

25]

S B_DQ

S[3]

SB_DQ[ S B_CKE

30] [0]

SB_CK E

[1]

SB_DQ[

27]

V TT0

S A_DQ[

27]

VSS

S A_DQ [

24]

SA_DQ[

28]

V SS

SB_DQ

S #[3]

SB_DQ[

26]

VSS VDDQ

V TT0 VS S

SA_DQ[

29]

S A_DQ [

18]

VSS

S B_DQ [

28]

SB_DQ[

29]

V SS

SB_DQ[

25]

S B_DM[

3]

VTT0

SA_DQ[

23]

S A_DQ

S#[2]

SA_DQ[

19]

S A_DQ [

22]

SB_DQ[ S B_DQ [

18] 24]

SB_DQ

S #[2]

SB_DQ[

19]

SB_DQ[

22]

SB_DQ[

23]

VS S

SA_DQ[

16]

S A_DQ

S [2]

VSS

SA _DM[

2]

SB_DQ[

16]

V SS

SB_DQ

S[2]

SB _DM[

2]

VSS VDDQ

VTT0

VTT0

VS S

SA_DQ[

21]

VS S

SA_DQ[

9]

S A_DQ

S [1]

SA_DQ[ S A_DQ [

17] 20]

VSS

S B_DQ [

21]

SB_DQ[

15]

SA_DQ

S#[1]

S A_DQ [

11]

SM_DR

AMRST

#

S B_DQ [

13]

SB_DQ

S #[1]

V SS

SB_DQ[

17]

SB_DQ[

20]

SB_DQ[

14]

SB_DQ[

10]

SB_DQ[

11]

SA_DQ[

6]

S A_DQ[

12]

VSS

S A_DQ [

14]

SA_DQ[

10]

V SS

SB_DQ[

4]

SB_DQ

S[1]

VSS

S B_DM[

1]

VTT0

SA_DQ[

5]

VS S

SA_DQ[

8]

SA _DM[

1]

VSS

S B_DQ

S#[0]

SB_DM[

0]

V SS

SB_DQ[

9]

SB_DQ[

8]

VTT0

SA_DQ[

1]

S A_DQ

S#[0]

SA_DQ

S[0]

S A_DQ [

2]

SA_DQ[

15]

S B_DQ

S[0]

SB_DQ[

7]

SB_DQ[

2]

SB_DQ[

12]

RSV D_

NCTF

VS S

SA_DQ[ SA _DM[

4] 0]

VSS

S A_DQ [

13]

VSS

S B_DQ [

0]

VSS

SB_DQ[ V SS_NC

3] TF

VSS _NC

TF

VTT0

SA_DQ[

0]

VS S

SA_DQ[

7]

S A_DQ [

3]

SB_DQ[

5]

S B_DQ [

1]

SB_DQ[

6]

RSV D_

NCTF

K EY

U

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

13 12 11 10 9 8 7 6 5 4 3 2 1

Datasheet 109

Processor Pin and Signal Information

A27

A28

A29

A30

A31

A32

A33

A23

A24

A25

A26

A19

A20

A21

A22

Table 8-48.rPGA988A Processor Pin

List by Pin Number

Pin

Number

A10

A11

A12

A13

A14

A15

A6

A7

A8

A9

A2

A3

A4

A5

A16

Pin Name

KEY

RSVD_NCTF

SB_DQ[6]

SB_DQ[1]

SB_DQ[5]

SA_DQ[3]

SA_DQ[7]

VSS

SA_DQ[0]

VTT0

VTT0

VTT0

VTT0

VSS_SENSE_VT

T

BCLK

A17

A18

Buffer

Type

DDR3

DDR3

DDR3

DDR3

DDR3

GND

DDR3

REF

REF

REF

REF

Analog

DIFF

CLK

DIFF

CLK

DIFF

CLK

Dir.

I/O

I/O

I/O

I/O

I/O

I/O

O

I

I

I

DPLL_REF_SSC

LK#

DPLL_REF_SSC

LK

RSVD

RSVD

DMI_RX#[3]

DMI_RX[3]

VSS

DMI_RX#[0]

PEG_RBIAS

PEG_ICOMPO

VSS

PEG_RX[13]

VSS

PEG_RX[15]

PEG_RX#[15]

PEG_RX[11]

RSVD_NCTF

DMI

DMI

GND

DMI

Analog

Analog

GND

PCIe

GND

PCIe

PCIe

PCIe

I

I

I

I

I

I

I

I

I

Table 8-48.rPGA988A Processor Pin

List by Pin Number

Pin

Number

AB3

AB4

AB5

AB6

AB7

AB8

AB9

AB10

AA30

AA31

AA32

AA33

AA34

AA35

AB1

AB2

AB26

AB27

AB28

AB29

AA7

AA8

AA9

AA10

AA26

AA27

AA28

AA29

A34

A35

AA1

AA2

AA3

AA4

AA5

AA6

Pin Name

VCC

VCC

VCC

VCC

VCC

VCC

SB_BS[0]

SA_BS[1]

SA_RAS#

VDDQ

SB_MA[10]

VSS

VDDQ

SB_CS#[0]

RSVD

VTT0

VSS

VSS

VSS

VSS

RSVD_NCTF

VSS_NCTF

RSVD_TP

RSVD_TP

SA_MA[3]

RSVD_TP

RSVD_TP

SA_CK[0]

SA_CK#[0]

SA_MA[2]

SA_MA[5]

VSS

VCC

VCC

VCC

VCC

Buffer

Type

DDR3

REF

GND

GND

GND

GND

Dir.

O

O

O

O

O

O

O

O

O

O

REF

REF

REF

REF

REF

REF

REF

REF

DDR3

DDR3

DDR3

DDR3

GND

REF

REF

DDR3

DDR3

DDR3

REF

DDR3

GND

REF

DDR3

Datasheet 110

111

Processor Pin and Signal Information

Table 8-48.rPGA988A Processor Pin

List by Pin Number

Pin

Number

AC34

AC35

AD1

AD2

AD3

AD4

AD5

AD6

AC26

AC27

AC28

AC29

AC30

AC31

AC32

AC33

AD7

AD8

AD9

AD10

AC3

AC4

AC5

AC6

AC7

AC8

AC9

AC10

AB30

AB31

AB32

AB33

AB34

AB35

AC1

AC2

Pin Name

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

SB_ODT[1]

RSVD_TP

RSVD_TP

SA_MA[10]

RSVD_TP

SB_CS#[1]

RSVD_TP

SA_ODT[0]

RSVD_TP

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VDDQ

VSS

SA_BS[0]

VSS

SB_CAS#

SB_WE#

SB_ODT[0]

VSS

RSVD

VTT0 REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

DDR3

Buffer

Type

DDR3

GND

DDR3

DDR3

DDR3

GND

GND

GND

GND

GND

GND

GND

REF

GND

DDR3

DDR3

DDR3

GND

Dir.

O

O

O

O

O

O

O

O

Table 8-48.rPGA988A Processor Pin

List by Pin Number

Pin

Number

AF3

AF4

AF5

AF6

AE30

AE31

AE32

AE33

AE34

AE35

AF1

AF2

AE7

AE8

AE9

AE10

AE26

AE27

AE28

AE29

AE3

AE4

AE5

AE6

AD34

AD35

AE1

AE2

AD26

AD27

AD28

AD29

AD30

AD31

AD32

AD33

Pin Name

VSS

VSS

VSS

VSS

VSS

VSS

VDDQ

VSS

VDDQ

SA_CS#[1]

SA_WE#

VTT0

VSS

VSS

VSS

VSS

SB_DQ[32]

VSS

SA_DQ[33]

SA_DQ[36]

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

SA_CAS#

SA_CS#[0]

RSVD_TP

VDDQ

RSVD_TP

VSS

Buffer

Type

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

DDR3

DDR3

REF

Dir.

O

O

O

O

I/O

I/O

I/O

GND

GND

GND

GND

GND

GND

GND

GND

GND

REF

DDR3

DDR3

REF

GND

GND

REF

GND

DDR3

GND

DDR3

DDR3

Datasheet

Processor Pin and Signal Information

Pin

Number

AG26

AG27

AG28

AG29

AG30

AG31

AG32

AG33

AG3

AG4

AG5

AG6

AG7

AG8

AG9

AG10

AG34

AG35

AH1

AH2

AF30

AF31

AF32

AF33

AF34

AF35

AG1

AG2

AF7

AF8

AF9

AF10

AF26

AF27

AF28

AF29

Pin Name

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

SB_DQ[37]

SB_DQ[36]

SA_DQ[37]

SA_DM[4]

RSVD_TP

SA_MA[13]

RSVD

VSS

VCC

VCC

SB_DM[4]

SB_DQS#[4]

SB_MA[13]

VSS

SA_ODT[1]

VTT0

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

SB_DQ[33]

SB_DQS[4]

Table 8-48.rPGA988A Processor Pin

List by Pin Number

Buffer

Type

REF

REF

REF

REF

REF

REF

DDR3

DDR3

DDR3

GND

DDR3

REF

REF

REF

REF

REF

DDR3

DDR3

DDR3

DDR3

Dir.

O

O

DDR3

REF

REF

REF

REF

DDR3

DDR3

GND

REF

REF

REF

REF

REF

REF

I/O

I/O

I/O

I/O

I/O

O

O

O

I/O

Table 8-48.rPGA988A Processor Pin

List by Pin Number

Pin

Number

AH27

AH28

AH29

AH30

AH31

AH32

AH33

AH34

AH19

AH20

AH21

AH22

AH23

AH24

AH25

AH26

AH35

AJ1

AJ2

AJ3

AH11

AH12

AH13

AH14

AH15

AH16

AH17

AH18

AH3

AH4

AH5

AH6

AH7

AH8

AH9

AH10

Pin Name

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VAXG

VSS

VAXG

BPM#[5]

BPM#[7]

SKTOCC#

RSVD

VSS

VSS

VDDQ

VSS

SB_DQ[34]

VTT0

VTT0

VSS

VTT0

RSVD

VAXG

VSS

VAXG

VSS

SB_DQ[39]

SA_DQ[32]

VSS

SA_DQS#[4]

SA_DQS[4]

VSS

VTT0

GND

GND

GND

REF

GND

DDR3

GND

GND

GND

GND

GND

GND

GND

REF

GND

REF

REF

GND

REF

GTL

GTL

Buffer

Type

GND

DDR3

DDR3

GND

DDR3

DDR3

GND

REF

REF

REF

GND

REF

Dir.

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Datasheet 112

113

Processor Pin and Signal Information

Table 8-48.rPGA988A Processor Pin

List by Pin Number

Pin

Number

AJ28

AJ29

AJ30

AJ31

AJ32

AJ33

AJ34

AJ35

AJ20

AJ21

AJ22

AJ23

AJ24

AJ25

AJ26

AJ27

AK1

AK2

AK3

AK4

AJ12

AJ13

AJ14

AJ15

AJ16

AJ17

AJ18

AJ19

AJ4

AJ5

AJ6

AJ7

AJ8

AJ9

AJ10

AJ11

Pin Name

VSS

VAXG

BPM#[0]

VSS

BPM#[3]

BPM#[4]

RSVD

RSVD

CFG[11]

CFG[15]

CFG[16]

VSS

CFG[14]

RSVD

VCC_SENSE

VSS_SENSE

SB_DQ[35]

SB_DQ[45]

SB_DQ[40]

SB_DQ[41]

SB_DQ[38]

VSS

SA_DQ[39]

SA_DQ[38]

VSS

SA_DQ[41]

SA_DQ[40]

VSS

RSVD_TP

RSVD_TP

VSS

RSVD

VAXG

VSS

VAXG

VAXG

Analog

Analog

DDR3

DDR3

DDR3

DDR3

REF

GND

REF

REF

GND

REF

GTL

GND

GTL

GTL

Buffer

Type

DDR3

GND

DDR3

DDR3

GND

DDR3

DDR3

GND

GND

CMOS

CMOS

CMOS

GND

CMOS

Dir.

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I

I

I

I

O

O

I/O

I/O

I/O

I/O

AK24

AK25

AK26

AK27

AK28

AK29

AK30

AK31

AK16

AK17

AK18

AK19

AK20

AK21

AK22

AK23

AL1

AL2

AL3

AL4

AK32

AK33

AK34

AK35

VAXG

VSS

VAXG

VAXG

VSS

VAXG

BPM#[1]

BPM#[6]

BPM#[2]

VSS

RSVD_TP

VSS

CFG[10]

VSS

CFG[17]

CFG[9]

CFG[8]

VID[1]

VID[2]

VID[0]

SM_RCOMP[0]

SB_DM[5]

VSS

SB_DQS#[5]

Table 8-48.rPGA988A Processor Pin

List by Pin Number

Pin

Number

AK5

AK6

AK7

AK8

AK9

AK10

AK11

AK12

AK13

AK14

AK15

Pin Name

SB_DQ[44]

SA_DQ[34]

SA_DQ[35]

SA_DQ[44]

SA_DQS#[5]

SA_DQS[5]

SA_DQ[46]

SA_DQ[43]

SM_DRAMPWR

OK

CATERR#

THERMTRIP#

GND

REF

GTL

GTL

GTL

GND

GTL

Async

GTL

REF

GND

REF

REF

Buffer

Type

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

Dir.

I/O

I/O

I/O

I/O

O

I/O

I/O

I/O

I/O

I/O

O

I/O

I/O

I/O

GND

CMOS

GND

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

Analog

DDR3

GND

DDR3

I

I

O

O

O

I

O

I

I

I/O

Datasheet

114

Processor Pin and Signal Information

Table 8-48.rPGA988A Processor Pin

List by Pin Number

Pin

Number

AL29

AL30

AL31

AL32

AL33

AL34

AL35

AM1

AL21

AL22

AL23

AL24

AL25

AL26

AL27

AL28

AM2

AM3

AM4

AM5

AL13

AL14

AL15

AL16

AL17

AL18

AL19

AL20

AL5

AL6

AL7

AL8

AL9

AL10

AL11

AL12

Pin Name

VAXG

RSVD

VSS

RSVD

RSVD

RSVD_TP

RSVD

RSVD

RSVD

CFG[4]

VSS

CFG[3]

CSC[1]/VID[4]

VSS

CSC[0]/VID[3]

SM_RCOMP[1]

VSS

SB_DQ[47]

SB_DQ[46]

VSS

SB_DQS[5]

VSS

SA_DQ[45]

SA_DQ[47]

VSS

SA_DQ[42]

SA_DQ[51]

VSS

SA_DQ[61]

RSTIN#

PM_SYNC

VAXG

VSS

VAXG

VAXG

VSS

CMOS

GND

CMOS

CMOS

GND

CMOS

Analog

GND

DDR3

DDR3

GND

Buffer

Type

DDR3

CMOS

CMOS

REF

GND

REF

REF

GND

REF

DDR3

GND

DDR3

DDR3

GND

DDR3

DDR3

GND

GND

Dir.

I/O

I/O

I/O

I/O

I/O

I/O

I

I

I

I

I/O

I/O

I

I/O

I/O

Table 8-48.rPGA988A Processor Pin

List by Pin Number

AM16

AM17

AM18

AM19

AM20

AM21

AM22

AM23

AM24

AM25

AM26

AM27

AM28

AM29

AM30

AM31

AM32

AM33

AM34

Pin

Number

AM6

AM7

AM8

AM9

AM10

AM11

AM12

AM13

AM14

AM15

Pin Name

SB_DQ[42]

SA_DM[5]

VSS

SA_DQ[52]

SA_DQ[49]

VSS

SA_DQ[56]

SA_DQ[58]

VSS

VTTPWRGOOD

AM35

AN1

AN2

AN3

AN4

VAXG

VSS

VAXG

VAXG

VSS

VAXG

GFX_VID[0]

GFX_VID[4]

GFX_IMON

VSS

TAPPWRGOOD

VSS

CFG[1]

VSS

CFG[0]

CFG[5]

CFG[7]

CSC[2]/VID[5]

PROC_DPRSLPV

R

VID[6]

SM_RCOMP[2]

SB_DQ[43]

SB_DQ[53]

SB_DQ[52]

Buffer

Type

Analog

GND

Async

CMOS

GND

CMOS

GND

CMOS

CMOS

CMOS

CMOS

CMOS

REF

GND

REF

REF

GND

REF

CMOS

CMOS

DDR3

DDR3

GND

DDR3

DDR3

GND

DDR3

DDR3

GND

Async

CMOS

CMOS

Analog

DDR3

DDR3

DDR3

Dir.

I/O

O

I/O

I/O

I/O

I/O

I

O

I

I/O

I/O

I/O

I

I

I

I/O

O

O

O

I

O

I

Datasheet

Processor Pin and Signal Information

Table 8-48.rPGA988A Processor Pin

List by Pin Number

AN27

AN28

AN29

AN30

AN31

AN32

AN33

AN16

AN17

AN18

AN19

AN20

AN21

AN22

AN23

AN24

AN25

AN26

Pin

Number

AN5

AN6

AN7

AN8

AN9

AN10

AN11

AN12

AN13

AN14

AN15

Pin Name

SB_DQ[49]

SB_DQ[51]

SB_DQ[56]

SA_DQ[48]

SA_DQ[53]

SA_DM[6]

SA_DQS[6]

SA_DQ[57]

SA_DM[7]

VCCPWRGOOD_

1

PM_EXT_TS#[0

]

VAXG

VSS

VAXG

VAXG

VSS

VAXG

GFX_VID[2]

VSS

GFX_VID[6]

DBR#

PROCHOT#

Buffer

Type

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

Async

CMOS

CMOS

AN34

AN35

AP1

AP2

VCCPWRGOOD_

0

TCK

CFG[6]

CFG[12]

VSS

CFG[13]

PSI#

VSS

ISENSE

RSVD_NCTF

VSS

REF

GND

REF

REF

GND

REF

CMOS

GND

CMOS

Async

GTL

Async

CMOS

CMOS

CMOS

CMOS

GND

CMOS

Async

CMOS

GND

Analog

GND

Dir.

I

O

I

I

I

O

O

I/O

I

I

O

I

I/O

O

I/O

I/O

I/O

I/O

I/O

I/O

O

I

AP28

AP29

AP30

AP31

AP32

AP33

AP34

AP35

Table 8-48.rPGA988A Processor Pin

List by Pin Number

AP16

AP17

AP18

AP19

AP20

AP21

AP22

AP23

AP24

AP25

AP26

Pin

Number

AP10

AP11

AP12

AP13

AP14

AP15

AP6

AP7

AP8

AP9

AP3

AP4

AP4

AP5

Pin Name

SB_DQ[48]

VSS

VSS

SB_DQS[6]

SB_DQ[57]

VSS

SB_DQ[58]

SB_DQ[61]

VSS

SA_DQS#[6]

SA_DQ[55]

VSS

SA_DQ[63]

PM_EXT_TS#[1

]

VAXG

VSS

VAXG

VAXG

VSS

VAXG

GFX_VID[1]

GFX_VID[3]

GFX_VID[5]

RSVD

RESET_OBS#

AP27 PREQ#

REF

GND

REF

REF

GND

REF

CMOS

CMOS

CMOS

Async

CMOS

Async

GTL

CMOS

CMOS

Dir.

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I

I

O

O

O

O

O

I

TMS

TDO_M

RSVD

CFG[2]

RSVD

RSVD

VSS

RSVD_NCTF

Buffer

Type

GND

DDR3

DDR3

GND

DDR3

CMOS

DDR3

GND

GND

DDR3

DDR3

GND

DDR3

DDR3

CMOS

GND

I

Datasheet 115

116

Processor Pin and Signal Information

AR31

AR32

AR33

AR34

AR35

AT1

Table 8-48.rPGA988A Processor Pin

List by Pin Number

Pin

Number

AR25

AR26

AR27

AR28

AR29

AR30

AR17

AR18

AR19

AR20

AR21

AR22

AR23

AR24

AR9

AR10

AR11

AR12

AR13

AR14

AR15

AR16

AR1

AR2

AR3

AR4

AR5

AR6

AR7

AR8

Pin Name

VSS

VAXG

VAXG

VSS

VAXG

VAXG_SENSE

VSS

VSS

GFX_VR_EN

VSS

TDO

VSS

TDI_M

BCLK_ITP

RSVD_NCTF

RSVD_NCTF

VSS

SB_DM[6]

SB_DQS#[6]

VSS

SB_DQS[7]

SB_DQS#[7]

VSS

SB_DQ[62]

SA_DQ[50]

VSS

SA_DQS[7]

SA_DQ[62]

VSS

VAXG

Buffer

Type

Dir.

O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

O

O

O

I

O

REF

GND

REF

Analog

GND

GND

CMOS

GND

CMOS

GND

CMOS

DIFF

CLK

GND

DDR3

GND

DDR3

DDR3

GND

REF

GND

REF

GND

DDR3

DDR3

GND

DDR3

DDR3

GND

DDR3

VSS

RSVD

RSVD

VSS_NCTF

RSVD_NCTF

VSS_NCTF

AT31

AT32

AT33

AT34

AT35

Table 8-48.rPGA988A Processor Pin

List by Pin Number

AT23

AT24

AT25

AT26

AT27

AT28

Pin

Number

AT10

AT11

AT12

AT13

AT14

AT15

AT16

AT17

AT18

AT19

AT20

AT21

AT22

AT6

AT7

AT8

AT9

AT2

AT3

AT4

AT5

Pin Name

RSVD_TP

RSVD_NCTF

SB_DQ[50]

SB_DQ[54]

SB_DQ[55]

SB_DQ[60]

SB_DM[7]

SB_DQ[59]

SB_DQ[63]

SA_DQ[54]

SA_DQ[60]

SA_DQS#[7]

SA_DQ[59]

PECI

VAXG

VSS

VAXG

VAXG

VSS

VAXG

VSSAXG_SENS

E

COMP3

COMP2

GFX_DPRSLPVR

COMP0

TRST#

PRDY#

AT29

AT30

TDI

BCLK_ITP#

Buffer

Type

Analog

Analog

CMOS

Analog

CMOS

Async

GTL

CMOS

DIFF

CLK

Dir.

O

I

O

DDR3

DDR3

DDR3

Async

REF

GND

REF

REF

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

GND

REF

Analog

I

I

O

I

I

O

O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

RSVD

RSVD

RSVD_NCTF

RSVD_NCTF

VSS_NCTF

Datasheet

Processor Pin and Signal Information

B29

B30

B31

B32

B25

B26

B27

B28

B33

B34

B35

C1

B21

B22

B23

B24

B17

B18

B19

B20

Table 8-48.rPGA988A Processor Pin

List by Pin Number

Pin

Number

B13

B14

B15

B16

B9

B10

B11

B12

B5

B6

B7

B8

B1

B2

B3

B4

Pin Name

VSS_NCTF

VSS_NCTF

SB_DQ[3]

VSS

SB_DQ[0]

VSS

SA_DQ[13]

VSS

SA_DM[0]

SA_DQ[4]

VSS

VTT0

VSS

VTT0

VTT_SENSE

BCLK#

Buffer

Type

Dir.

I/O

I/O

I/O

O

I/O

O

I

GND

REF

GND

REF

Analog

DIFF

CLK

GND

GND

DDR3

GND

DDR3

GND

DDR3

GND

DDR3

DDR3

VSS

VSS

RSVD

RSVD

VSS

DMI_RX#[2]

DMI_RX[2]

DMI_RX[0]

VSS

PEG_ICOMPI

PEG_RCOMPO

PEG_RX#[13]

PEG_RX[14]

PEG_RX#[14]

VSS

PEG_RX#[11]

PEG_RX[9]

VSS_NCTF

RSVD_NCTF

RSVD_NCTF

GND

DMI

DMI

DMI

GND

Analog

Analog

PCIe

PCIe

PCIe

GND

PCIe

PCIe

I

I

I

I

I

I

I

I

I

I

Table 8-48.rPGA988A Processor Pin

List by Pin Number

Pin

Number

C34

C35

D1

D2

C26

C27

C28

C29

C30

C31

C32

C33

C22

C23

C24

C25

C18

C19

C20

C21

C14

C15

C16

C17

C10

C11

C12

C13

C6

C7

C8

C9

C2

C3

C4

C5

Pin Name

FDI_TX[3]

VSS

VSS

FDI_TX[1]

VSS

DMI_RX#[1]

VSS

PEG_TX[15]

PEG_TX#[15]

PEG_TX[14]

VSS

VSS

PEG_RX[12]

PEG_RX#[12]

VSS

PEG_RX#[9]

VSS

RSVD_NCTF

SB_DQ[8]

SB_DQ[9]

SB_DQ[12]

SB_DQ[2]

SB_DQ[7]

SB_DQS[0]

SA_DQ[15]

SA_DQ[2]

SA_DQS[0]

SA_DQS#[0]

SA_DQ[1]

VTT0

VTT0

VTT0

VTT0

RSVD

VSS

FDI_INT

Buffer

Type

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

REF

REF

REF

REF

DDR3

DDR3

Dir.

O

O

O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I

O

O

I

I

I

I

I/O

I/O

GND

PCIe

PCIe

PCIe

GND

GND

PCIe

PCIe

GND

CMOS

FDI

GND

GND

FDI

GND

DMI

GND

PCIe

GND

Datasheet 117

118

Processor Pin and Signal Information

D25

D26

D27

D28

D29

D30

D31

D32

D17

D18

D19

D20

D21

D22

D23

D24

D33

D34

D35

E1

E2

E3

Table 8-48.rPGA988A Processor Pin

List by Pin Number

Pin

Number

D11

D12

D13

D14

D15

D16

D3

D4

D5

D6

D7

D8

D9

D10

Pin Name

VSS

SB_DM[0]

SB_DQS#[0]

VSS

SA_DM[1]

SA_DQ[8]

VSS

SA_DQ[5]

VTT0

VTT0

VTT0

VTT0

RSVD

PEG_CLK#

Buffer

Type

GND

DDR3

DDR3

GND

DDR3

DDR3

GND

DDR3

REF

REF

REF

REF

Dir.

O

I/O

O

I/O

I/O

I

FDI_LSYNC[1]

FDI_TX#[3]

FDI_TX#[2]

FDI_TX[2]

FDI_TX#[1]

FDI_TX[0]

DMI_RX[1]

DMI_TX#[0]

DMI_TX[0]

VSS

PEG_TX#[14]

PEG_TX[13]

PEG_TX#[13]

VSS

PEG_RX[10]

PEG_RX#[10]

VSS

PEG_RX[7]

PEG_RX#[7]

SB_DM[1]

VSS

SB_DQS[1]

DMI

DMI

DMI

GND

PCIe

PCIe

PCIe

GND

DIFF

CLK

CMOS

FDI

FDI

FDI

FDI

FDI

PCIe

PCIe

GND

PCIe

PCIe

DDR3

GND

DDR3

I

O

O

O

O

O

O

I

O

I

I

O

O

O

O

I

I

I/O

E28

E29

E30

E31

E24

E25

E26

E27

E17

E18

E19

E20

E21

E22

E23

F1

F2

F3

F4

E32

E33

E34

E35

FDI_FSYNC[1]

VSS

FDI_TX#[5]

FDI_TX[5]

VSS

FDI_TX#[0]

DMI_TX[2]

VSS

VTT1

VTT1

PEG_TX[12]

PEG_TX#[12]

VSS

RSVD

RSVD

VSS

PEG_RX#[8]

PEG_RX[5]

VSS

SB_DQ[11]

SB_DQ[10]

SB_DQ[14]

SB_DQS#[1]

Table 8-48.rPGA988A Processor Pin

List by Pin Number

Pin

Number

E8

E9

E10

E11

E4

E5

E6

E7

E12

E13

E14

E15

E16

Pin Name

SB_DQ[4]

VSS

SA_DQ[10]

SA_DQ[14]

VSS

SA_DQ[12]

SA_DQ[6]

VSS

VTT0

VSS

VTT0

RSVD_TP

PEG_CLK

FDI

DMI

GND

REF

REF

PCIe

PCIe

GND

DIFF

CLK

CMOS

GND

FDI

FDI

GND

Buffer

Type

DDR3

GND

DDR3

DDR3

GND

DDR3

DDR3

GND

REF

GND

REF

Dir.

I/O

I/O

I/O

I/O

I/O

I

I

O

O

O

O

O

O

GND

PCIe

PCIe

GND

DDR3

DDR3

DDR3

DDR3

I

I

I/O

I/O

I/O

I/O

Datasheet

119

Processor Pin and Signal Information

Table 8-48.rPGA988A Processor Pin

List by Pin Number

Pin

Number

F33

F34

F35

G1

F29

F30

F31

F32

G2

G3

G4

G5

F25

F26

F27

F28

F21

F22

F23

F24

F17

F18

F19

F20

F13

F14

F15

F16

F9

F10

F11

F12

F5

F6

F7

F8

Pin Name

FDI_TX#[6]

VSS

DMI_TX#[2]

DMI_TX[1]

VSS

VTT1

VSS

PEG_TX[11]

PEG_TX#[11]

VSS

PEG_RX#[6]

PEG_RX[6]

PEG_RX[8]

PEG_RX#[5]

PEG_RX[3]

SB_DQ[20]

SB_DQ[17]

VSS

SB_DQ[15]

SB_DQ[21]

SB_DQ[13]

SM_DRAMRST#

SA_DQ[11]

SA_DQS#[1]

SA_DQS[1]

SA_DQ[9]

VTT0

VTT0

VTT0

VTT0

RSVD_TP

VSS

FDI_FSYNC[0]

FDI_LSYNC[0]

VSS

FDI_TX[6]

Buffer

Type

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

REF

REF

REF

REF

Dir.

I/O

O

I/O

I/O

I/O

I/O

O

O

O

O

O

O

I

I

I/O

I/O

DMI

DMI

GND

REF

GND

PCIe

PCIe

GND

GND

CMOS

CMOS

GND

FDI

FDI

GND

PCIe

PCIe

PCIe

PCIe

PCIe

DDR3

DDR3

GND

DDR3

DDR3

I

I/O

I/O

I

I

I

I

Table 8-48.rPGA988A Processor Pin

List by Pin Number

Pin

Number

H3

H4

H5

H6

G30

G31

G32

G33

G34

G35

H1

H2

G22

G23

G24

G25

G26

G27

G28

G29

G14

G15

G16

G17

G18

G19

G20

G21

G6

G7

G8

G9

G10

G11

G12

G13

Pin Name

FDI_TX[4]

DMI_TX[3]

DMI_TX#[1]

RSVD

VTT1

VTT1

VTT1

PEG_TX[10]

PEG_TX[9]

VSS

PEG_RX#[4]

PEG_RX[4]

VSS

PEG_RX#[3]

VDDQ

VSS

SB_DM[2]

SB_DQS[2]

VSS

SB_DQ[16]

VSS

SA_DQ[20]

SA_DQ[17]

VSS

SA_DQ[21]

VTT0

VTT0

VTT0

VTT0

VTT_SELECT

COMP1

RSVD

FDI_TX#[7]

FDI_TX[7]

VSS

FDI_TX#[4]

FDI

FDI

GND

FDI

FDI

DMI

DMI

Buffer

Type

GND

DDR3

DDR3

GND

DDR3

REF

REF

REF

REF

CMOS

Analog

Dir.

I/O

I/O

I/O

O

O

O

O

O

O

I

I

O

O

O

I

I

O

I/O

I/O

GND

PCIe

REF

GND

DDR3

DDR3

GND

DDR3

REF

REF

REF

PCIe

PCIe

GND

PCIe

PCIe

Datasheet

Processor Pin and Signal Information

Table 8-48.rPGA988A Processor Pin

List by Pin Number

Pin

Number

J4

J5

J6

J7

H31

H32

H33

H34

H35

J1

J2

J3

H23

H24

H25

H26

H27

H28

H29

H30

H15

H16

H17

H18

H19

H20

H21

H22

H7

H8

H9

H10

H11

H12

H13

H14

Pin Name

DMI_TX#[3]

VSS

VTT1

VSS

VTT1

VSS

PEG_TX#[10]

PEG_TX#[9]

PEG_TX[7]

VSS

PEG_RX[2]

PEG_RX[1]

VSS

SB_DQ[23]

SB_DQ[22]

SB_DQ[19]

SB_DQS#[2]

SB_DQ[24]

SB_DQ[18]

SA_DQ[22]

SA_DM[2]

VSS

SA_DQS[2]

SA_DQ[16]

VSS

VTT0

VSS

VTT0

VSS

RSVD_TP

RSVD

VSS

VTT1

VTT1

VTT1

VSS

Buffer

Type

DDR3

GND

DDR3

DDR3

GND

REF

GND

REF

GND

Dir.

O

I/O

I/O

O

O

O

O

I

I

REF

GND

REF

GND

PCIe

PCIe

PCIe

GND

GND

REF

REF

REF

GND

DMI

GND

PCIe

PCIe

GND

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Table 8-48.rPGA988A Processor Pin

List by Pin Number

Pin

Number

K1

K2

K3

K4

J32

J33

J34

J35

K5

K6

K7

K8

J28

J29

J30

J31

J24

J25

J26

J27

J20

J21

J22

J23

J16

J17

J18

J19

J12

J13

J14

J15

J8

J9

J10

J11

Pin Name

VTT1

VTT1

VTT1

VTT1

RSVD

RSVD

VSS

PEG_TX#[7]

VSS

PEG_RX#[2]

PEG_RX#[1]

PEG_RX[0]

SB_DM[3]

SB_DQ[25]

VSS

SB_DQ[29]

SB_DQ[28]

VSS

SA_DQ[18]

SA_DQ[29]

VTT0

RSVD

VTT1

VSS

VTT1

VSS

VTT1

VTT1

SA_DQ[19]

SA_DQS#[2]

SA_DQ[23]

VTT0

VTT0

VTT0

VTT0

VTT0

GND

DDR3

DDR3

GND

DDR3

DDR3

GND

PCIe

GND

PCIe

PCIe

PCIe

DDR3

DDR3

REF

GND

REF

GND

REF

REF

REF

REF

REF

REF

Buffer

Type

DDR3

DDR3

DDR3

REF

REF

REF

REF

REF

REF

Dir.

I/O

I/O

I/O

O

I

I

I

O

I/O

I/O

I/O

I/O

I/O

Datasheet 120

121

Processor Pin and Signal Information

Pin

Number

L32

L33

L34

L35

L28

L29

L30

L31

M1

M2

M3

M4

L9

L10

L26

L27

L5

L6

L7

L8

L1

L2

L3

L4

K32

K33

K34

K35

K28

K29

K30

K31

K9

K10

K26

K27

Pin Name

VSS

SA_DQ[28]

SA_DQ[24]

VSS

SA_DQ[27]

VTT0

VCCPLL

VCCPLL

RSVD

VSS

PEG_TX[3]

PEG_TX#[4]

VSS

PEG_TX#[0]

PEG_TX[0]

VSS

SB_DQ[27]

SB_CKE[1]

SB_CKE[0]

SB_DQ[30]

VSS

VTT0

VTT1

VSS

PEG_TX[8]

PEG_TX#[8]

VSS

PEG_TX[5]

PEG_TX#[5]

VSS

VSS

PEG_RX#[0]

VDDQ

VSS

SB_DQ[26]

SB_DQS#[3]

Table 8-48.rPGA988A Processor Pin

List by Pin Number

Buffer

Type

PCIe

GND

GND

PCIe

REF

GND

DDR3

DDR3

GND

REF

REF

GND

PCIe

PCIe

GND

PCIe

GND

DDR3

DDR3

GND

DDR3

REF

REF

REF

Dir.

O

O

O

O

I

I/O

I/O

I/O

I/O

I/O

GND

PCIe

PCIe

GND

PCIe

PCIe

GND

DDR3

DDR3

DDR3

DDR3

O

O

O

O

I/O

O

O

I/O

Table 8-48.rPGA988A Processor Pin

List by Pin Number

Pin

Number

N9

N10

N26

N27

N28

N29

N30

N31

N5

N6

N7

N8

N1

N2

N3

N4

N32

N33

N34

N35

M28

M29

M30

M31

M32

M33

M34

M35

M5

M6

M7

M8

M9

M10

M26

M27

Pin Name

SB_MA[15]

RSVD_TP

RSVD_TP

VDDQ

SB_DQ[31]

VSS

VDDQ

SA_DQ[30]

SA_DQS#[3]

VTT0

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

SB_DQS[3]

SA_DQ[25]

SA_DM[3]

SA_DQ[26]

SA_DQS[3]

VSS

VCCPLL

RSVD

PEG_TX[6]

PEG_TX#[6]

PEG_TX#[3]

PEG_TX[4]

PEG_TX[2]

PEG_TX#[2]

PEG_TX[1]

PEG_TX#[1]

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

DDR3

Buffer

Type

DDR3

DDR3

DDR3

DDR3

DDR3

GND

REF

Dir.

I/O

I/O

O

I/O

I/O

I/O

I/O

I/O

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

REF

DDR3

GND

REF

DDR3

DDR3

REF

O

O

O

O

O

O

O

O

O

Datasheet

Processor Pin and Signal Information

Pin

Number

R9

R10

R26

R27

R5

R6

R7

R8

R28

R29

R30

R31

R1

R2

R3

R4

P32

P33

P34

P35

P28

P29

P30

P31

P9

P10

P26

P27

P5

P6

P7

P8

P1

P2

P3

P4

Pin Name

VCC

VCC

VCC

VCC

SB_MA[4]

SB_MA[6]

SB_MA[12]

SB_MA[8]

SB_MA[9]

SB_MA[7]

SB_BS[2]

RSVD_TP

RSVD_TP

VSS

VCC

VCC

VCC

VCC

VCC

VCC

VDDQ

VSS

SB_MA[11]

VSS

SB_MA[14]

SA_CKE[1]

SA_CKE[0]

VSS

SA_DQ[31]

VTT0

VCC

VCC

VCC

VCC

VCC

VCC

Table 8-48.rPGA988A Processor Pin

List by Pin Number

Buffer

Type

REF

REF

REF

REF

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

REF

REF

REF

REF

REF

REF

REF

REF

GND

DDR3

GND

DDR3

DDR3

DDR3

GND

Dir.

O

O

O

O

I/O

GND

REF

REF

REF

REF

REF

REF

O

O

O

O

O

O

O

Table 8-48.rPGA988A Processor Pin

List by Pin Number

Pin

Number

U5

U6

U7

U8

U1

U2

U3

U4

T32

T33

T34

T35

T28

T29

T30

T31

U9

U10

U26

U27

T9

T10

T26

T27

T5

T6

T7

T8

T1

T2

T3

T4

R32

R33

R34

R35

Pin Name

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VDDQ

VSS

SA_MA[12]

VSS

SB_MA[0]

SA_MA[9]

SA_BS[2]

VSS

RSVD

VTT0

VCC

VCC

VCC

VCC

VCC

VCC

SA_MA[7]

SA_MA[11]

SA_MA[14]

VDDQ

SB_MA[2]

VSS

VDDQ

SB_MA[5]

RSVD

VTT0

VSS

VSS

Buffer

Type

REF

REF

REF

REF

DDR3

DDR3

DDR3

REF

DDR3

GND

REF

DDR3

REF

REF

REF

Dir.

O

O

O

O

O

O

O

O

O

GND

GND

GND

GND

REF

GND

DDR3

GND

REF

GND

GND

GND

GND

GND

GND

DDR3

DDR3

DDR3

GND

Datasheet 122

123

Processor Pin and Signal Information

Table 8-48.rPGA988A Processor Pin

List by Pin Number

Pin

Number

W1

W2

W3

W4

V32

V33

V34

V35

W5

W6

W7

W8

V28

V29

V30

V31

V9

V10

V26

V27

V5

V6

V7

V8

V1

V2

V3

V4

U28

U29

U30

U31

U32

U33

U34

U35

Pin Name

SA_MA[15]

VSS

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

SA_MA[1]

RSVD_TP

RSVD_TP

VDDQ

SB_BS[1]

VSS

VDDQ

SB_CK[0]

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

SA_MA[4]

SB_MA[1]

SB_MA[3]

RSVD_TP

RSVD_TP

SB_CK#[1]

SB_CK[1]

SA_MA[6]

Buffer

Type

REF

REF

REF

REF

REF

REF

REF

REF

DDR3

DDR3

DDR3

REF

DDR3

GND

REF

DDR3

Dir.

O

O

O

O

O

O

O

O

O

O

REF

REF

REF

REF

REF

REF

REF

REF

DDR3

DDR3

DDR3

DDR3

DDR3

GND

REF

REF

Table 8-48.rPGA988A Processor Pin

List by Pin Number

Pin

Number

Y32

Y33

Y34

Y35

Y28

Y29

Y30

Y31

Y9

Y10

Y26

Y27

Y5

Y6

Y7

Y8

Y1

Y2

Y3

Y4

W32

W33

W34

W35

W9

W10

W26

W27

W28

W29

W30

W31

Pin Name

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

SA_CK#[1]

SA_CK[1]

SB_RAS#

VSS

SA_MA[8]

VTT0

VCC

VCC

SB_CK#[0]

VTT0

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VDDQ

VSS

SA_MA[0]

VSS

Dir.

O

O

O

O

O

O

Buffer

Type

REF

REF

REF

REF

REF

REF

REF

REF

DDR3

DDR3

DDR3

GND

DDR3

REF

REF

REF

GND

GND

GND

GND

REF

GND

DDR3

GND

DDR3

REF

GND

GND

GND

GND

GND

GND

Datasheet

Processor Pin and Signal Information

CFG[3]

CFG[4]

CFG[5]

CFG[6]

CFG[7]

CFG[8]

CFG[9]

CFG[10]

CFG[11]

CFG[12]

CFG[13]

CFG[14]

CFG[15]

CFG[16]

CFG[17]

COMP0

COMP1

COMP2

COMP3

DBR#

BCLK

BCLK_ITP

BCLK_ITP#

BCLK#

BPM#[0]

BPM#[1]

BPM#[2]

BPM#[3]

BPM#[4]

BPM#[5]

BPM#[6]

BPM#[7]

CATERR#

CFG[0]

CFG[1]

CFG[2]

Table 8-49.rPGA988A Processor Pin

List by Pin Name

Pin Name

Pin

Number

AJ28

AN30

AN32

AJ32

AJ29

AJ30

AK30

AT26

AL32

AL30

AM31

AN29

AM32

AK32

AK31

AK28

G16

AT24

AT23

AN25

AJ25

AH22

AK23

AH23

AK14

AM30

AM28

AP31

A16

AR30

AT30

B16

AJ22

AK22

AK24

AJ24

Buffer

Type

Dir.

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

Analog

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

Analog

Analog

Analog

GTL

GTL

GTL

GTL

GTL

CMOS

CMOS

CMOS

DIFF CLK I

DIFF CLK O

DIFF CLK O

DIFF CLK I

GTL

GTL

GTL

GTL

I/O

I/O

I/O

I/O

I/O

I

I

I

I/O

I/O

I/O

I/O

I

I

I

I

I

I

I

I

I

O

I

I

I

I

I

I

I

I

I

I

Table 8-49.rPGA988A Processor Pin

List by Pin Name

Pin Name

FDI_FSYNC[1]

FDI_INT

FDI_LSYNC[0]

FDI_LSYNC[1]

FDI_TX[0]

FDI_TX[1]

FDI_TX[2]

FDI_TX[3]

FDI_TX[4]

FDI_TX[5]

FDI_TX[6]

FDI_TX[7]

FDI_TX#[0]

FDI_TX#[1]

FDI_TX#[2]

FDI_TX#[3]

DMI_RX[0]

DMI_RX[1]

DMI_RX[2]

DMI_RX[3]

DMI_RX#[0]

DMI_RX#[1]

DMI_RX#[2]

DMI_RX#[3]

DMI_TX[0]

DMI_TX[1]

DMI_TX[2]

DMI_TX[3]

DMI_TX#[0]

DMI_TX#[1]

DMI_TX#[2]

DMI_TX#[3]

DPLL_REF_SSCL

K

DPLL_REF_SSCL

K#

FDI_FSYNC[0]

Pin

Number

D25

F24

E23

G23

D24

G24

F23

H23

A18

B24

D23

B23

A22

A24

C23

B22

A21

A17

D20

C18

G22

E20

F20

G19

E22

D21

D19

D18

F17

E17

C17

F18

D17

D22

C21

Buffer

Type

DMI

DMI

DMI

DMI

DMI

DMI

DMI

DMI

DIFF CLK

DMI

DMI

DMI

DMI

DMI

DMI

DMI

DMI

DIFF CLK

FDI

FDI

FDI

FDI

FDI

FDI

FDI

FDI

FDI

FDI

CMOS

CMOS

CMOS

CMOS

CMOS

FDI

FDI

Dir.

I

O

O

O

O

I

O

O

O

O

I

I

I

I

I

I

I

I

O

O

O

O

O

O

O

O

O

O

O

O

I

I

I

I

I

Datasheet 124

125

Processor Pin and Signal Information

Table 8-49.rPGA988A Processor Pin

List by Pin Name

Pin Name

PECI

PEG_CLK

PEG_CLK#

PEG_ICOMPI

PEG_ICOMPO

PEG_RBIAS

PEG_RCOMPO

PEG_RX[0]

PEG_RX[1]

PEG_RX[2]

PEG_RX[3]

PEG_RX[4]

PEG_RX[5]

PEG_RX[6]

PEG_RX[7]

PEG_RX[8]

PEG_RX[9]

PEG_RX[10]

PEG_RX[11]

PEG_RX[12]

FDI_TX#[4]

FDI_TX#[5]

FDI_TX#[6]

FDI_TX#[7]

GFX_DPRSLPVR

GFX_IMON

GFX_VID[0]

GFX_VID[1]

GFX_VID[2]

GFX_VID[3]

GFX_VID[4]

GFX_VID[5]

GFX_VID[6]

GFX_VR_EN

ISENSE

KEY

Pin

Number

H34

H33

F35

G33

E34

F32

D34

F33

AT15

E16

D16

B26

A26

A25

B27

J35

B33

D31

A32

C30

AN22

AP23

AM23

AP24

AN24

AR25

AN35

A2

G21

E19

F21

G18

AT25

AM24

AM22

AP22

Buffer

Type

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

Analog

FDI

FDI

FDI

FDI

CMOS

Analog

CMOS

CMOS

Dir.

O

O

I

O

O

O

O

O

O

O

I

O

O

O

O

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

Async I/O

DIFF CLK I

DIFF CLK I

Analog I

Analog

Analog

Analog

PCIe

I

I

I

I

PCIe

PCIe

PCIe

PCIe

I

I

I

I

I

I

I

I

I

I

I

I

PEG_RX#[13]

PEG_RX#[14]

PEG_RX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]

PEG_TX[10]

PEG_TX[11]

PEG_TX[12]

PEG_TX[13]

PEG_TX[14]

PEG_TX[15]

PEG_TX#[0]

PEG_RX[13]

PEG_RX[14]

PEG_RX[15]

PEG_RX#[0]

PEG_RX#[1]

PEG_RX#[2]

PEG_RX#[3]

PEG_RX#[4]

PEG_RX#[5]

PEG_RX#[6]

PEG_RX#[7]

PEG_RX#[8]

PEG_RX#[9]

PEG_RX#[10]

PEG_RX#[11]

PEG_RX#[12]

Table 8-49.rPGA988A Processor Pin

List by Pin Name

Pin Name

Pin

Number

K31

M28

H31

K28

G30

G29

F28

E27

B28

B30

A31

L34

M34

M32

L30

M31

D28

C27

C25

L33

F34

F31

D35

E33

C33

D32

B32

C31

J34

J33

G35

G32

A28

B29

A30

K35

Buffer

Type

Dir.

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

I

O

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

Datasheet

Processor Pin and Signal Information

RSTIN#

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

Table 8-49.rPGA988A Processor Pin

List by Pin Name

Pin Name

Pin

Number

PEG_TX#[1]

PEG_TX#[2]

PEG_TX#[3]

PEG_TX#[4]

PEG_TX#[5]

PEG_TX#[6]

PEG_TX#[7]

PEG_TX#[8]

PEG_TX#[9]

PEG_TX#[10]

PEG_TX#[11]

PEG_TX#[12]

H30

H29

F29

E28

PEG_TX#[13]

PEG_TX#[14]

D29

D27

PEG_TX#[15] C26

PM_EXT_TS#[0] AN15

M35

M33

M30

L31

K32

M29

J31

K29

PM_EXT_TS#[1] AP15

PM_SYNC AL15

PRDY# AT28

PREQ# AP27

AM34

Buffer

Type

Dir.

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

CMOS

CMOS

CMOS

Async

GTL

Async

GTL

CMOS

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

O

I

O

O

O

O

O

O

I

I

O

O

O

O

O

O

O

O

O

I

O PROC_DPRSLPV

R

PROCHOT# AN26 I/O

PSI#

RESET_OBS#

AN33

AP26

Async

GTL

Async

CMOS

Async

CMOS

CMOS

O

O

I AL14

A19

A20

AB9

AC9

AG9

AH15

AH25

Table 8-49.rPGA988A Processor Pin

List by Pin Name

Pin Name

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD_NCTF

RSVD_NCTF

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

Pin

Number

G17

G25

H17

J17

J28

J29

L28

M27

AT31

AT32

B19

B20

C15

D15

E30

E31

T9

U9

A3

A33

AL28

AL29

AP25

AP30

AP32

AP33

AR32

AR33

AJ15

AJ26

AJ27

AJ33

AL22

AL24

AL25

AL27

Buffer

Type

Dir.

Datasheet 126

127

Processor Pin and Signal Information

RSVD_TP

RSVD_TP

RSVD_TP

RSVD_TP

RSVD_TP

RSVD_TP

RSVD_TP

RSVD_TP

RSVD_TP

RSVD_TP

RSVD_TP

RSVD_TP

RSVD_TP

RSVD_TP

RSVD_TP

RSVD_TP

RSVD_TP

RSVD_TP

RSVD_TP

RSVD_TP

RSVD_NCTF

RSVD_NCTF

RSVD_NCTF

RSVD_NCTF

RSVD_NCTF

RSVD_NCTF

RSVD_NCTF

RSVD_NCTF

RSVD_NCTF

RSVD_NCTF

RSVD_NCTF

RSVD_NCTF

RSVD_TP

RSVD_TP

RSVD_TP

RSVD_TP

Table 8-49.rPGA988A Processor Pin

List by Pin Name

Pin Name

Pin

Number

AJ12

AJ13

AK26

AL26

AT2

E15

F15

H16

N2

N3

R8

R9

AD2

AD3

AD5

AD7

AD9

AE3

AE5

AG7

AT34

B35

C1

C35

AA1

AA2

AA4

AA5

A34

AP1

AP35

AR1

AR2

AR35

AT3

AT33

Buffer

Type

Dir.

SA_DM[0]

SA_DM[1]

SA_DM[2]

SA_DM[3]

SA_DM[4]

SA_DM[5]

SA_DM[6]

SA_DM[7]

SA_DQ[0]

SA_DQ[1]

SA_DQ[2]

SA_DQ[3]

SA_DQ[4]

SA_DQ[5]

SA_DQ[6]

SA_DQ[7]

SA_DQ[8]

SA_DQ[9]

SA_DQ[10]

SA_DQ[11]

RSVD_TP

RSVD_TP

RSVD_TP

RSVD_TP

SA_BS[0]

SA_BS[1]

SA_BS[2]

SA_CAS#

SA_CK[0]

SA_CK[1]

SA_CK#[0]

SA_CK#[1]

SA_CKE[0]

SA_CKE[1]

SA_CS#[0]

SA_CS#[1]

Table 8-49.rPGA988A Processor Pin

List by Pin Name

Pin Name

Pin

Number

D8

F10

E6

F7

B10

D10

E10

A8

A10

C10

C7

A7

B9

D7

H7

M7

AG6

AM7

AN10

AN13

AA6

Y6

AA7

Y5

P7

P6

AE2

AE8

AC3

AB2

U7

AE1

V4

V5

W2

W3

Buffer

Type

Dir.

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

Datasheet

Processor Pin and Signal Information

SA_DQ[28]

SA_DQ[29]

SA_DQ[30]

SA_DQ[31]

SA_DQ[32]

SA_DQ[33]

SA_DQ[34]

SA_DQ[35]

SA_DQ[36]

SA_DQ[37]

SA_DQ[38]

SA_DQ[39]

SA_DQ[40]

SA_DQ[41]

SA_DQ[42]

SA_DQ[43]

SA_DQ[44]

SA_DQ[45]

SA_DQ[46]

SA_DQ[47]

SA_DQ[12]

SA_DQ[13]

SA_DQ[14]

SA_DQ[15]

SA_DQ[16]

SA_DQ[17]

SA_DQ[18]

SA_DQ[19]

SA_DQ[20]

SA_DQ[21]

SA_DQ[22]

SA_DQ[23]

SA_DQ[24]

SA_DQ[25]

SA_DQ[26]

SA_DQ[27]

Table 8-49.rPGA988A Processor Pin

List by Pin Name

Pin Name

Pin

Number

AF6

AG5

AJ7

AJ6

AJ10

AJ9

AL10

AK12

AH5

AF5

AK6

AK7

L6

K8

N8

P9

AK8

AL7

AK11

AL8

L7

M6

M8

L9

G7

G10

J7

J10

H10

G8

K7

J8

E9

B7

E7

C6

Buffer

Type

Dir.

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

SA_DQS[0]

SA_DQS[1]

SA_DQS[2]

SA_DQS[3]

SA_DQS[4]

SA_DQS[5]

SA_DQS[6]

SA_DQS[7]

SA_DQS#[0]

SA_DQS#[1]

SA_DQS#[2]

SA_DQS#[3]

SA_DQS#[4]

SA_DQS#[5]

SA_DQS#[6]

SA_DQS#[7]

SA_MA[0]

SA_MA[1]

SA_MA[2]

SA_MA[3]

SA_DQ[48]

SA_DQ[49]

SA_DQ[50]

SA_DQ[51]

SA_DQ[52]

SA_DQ[53]

SA_DQ[54]

SA_DQ[55]

SA_DQ[56]

SA_DQ[57]

SA_DQ[58]

SA_DQ[59]

SA_DQ[60]

SA_DQ[61]

SA_DQ[62]

SA_DQ[63]

Table 8-49.rPGA988A Processor Pin

List by Pin Name

Pin Name

Pin

Number

C9

F8

J9

N9

AH7

AK9

AP11

AT13

C8

F9

H9

M9

AH8

AK10

AN11

AR13

Y3

W1

AA8

AA3

AM12

AN12

AM13

AT14

AT12

AL13

AR14

AP14

AN8

AM10

AR11

AL11

AM9

AN9

AT11

AP12

Buffer

Type

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

Dir.

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

O

O

O

O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Datasheet 128

129

Processor Pin and Signal Information

SB_BS[0]

SB_BS[1]

SB_BS[2]

SB_CAS#

SB_CK[0]

SB_CK[1]

SB_CK#[0]

SB_CK#[1]

SB_CKE[0]

SB_CKE[1]

SB_CS#[0]

SB_CS#[1]

SB_DM[0]

SB_DM[1]

SB_DM[2]

SB_DM[3]

SB_DM[4]

SB_DM[5]

SB_DM[6]

SB_DM[7]

SA_MA[4]

SA_MA[5]

SA_MA[6]

SA_MA[7]

SA_MA[8]

SA_MA[9]

SA_MA[10]

SA_MA[11]

SA_MA[12]

SA_MA[13]

SA_MA[14]

SA_MA[15]

SA_ODT[0]

SA_ODT[1]

SA_RAS#

SA_WE#

Table 8-49.rPGA988A Processor Pin

List by Pin Name

Pin Name

Pin

Number

D4

E1

H3

K1

M3

M2

AB8

AD6

W8

V7

W9

V6

AB1

W5

R7

AC5

AH1

AL2

AR4

AT8

U3

AG8

T3

V9

AD8

AF9

AB3

AE9

V1

AA9

V8

T1

Y9

U6

AD4

T2

Buffer

Type

Dir.

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

SB_DQ[16]

SB_DQ[17]

SB_DQ[18]

SB_DQ[19]

SB_DQ[20]

SB_DQ[21]

SB_DQ[22]

SB_DQ[23]

SB_DQ[24]

SB_DQ[25]

SB_DQ[26]

SB_DQ[27]

SB_DQ[28]

SB_DQ[29]

SB_DQ[30]

SB_DQ[31]

SB_DQ[32]

SB_DQ[33]

SB_DQ[34]

SB_DQ[35]

SB_DQ[0]

SB_DQ[1]

SB_DQ[2]

SB_DQ[3]

SB_DQ[4]

SB_DQ[5]

SB_DQ[6]

SB_DQ[7]

SB_DQ[8]

SB_DQ[9]

SB_DQ[10]

SB_DQ[11]

SB_DQ[12]

SB_DQ[13]

SB_DQ[14]

SB_DQ[15]

Table 8-49.rPGA988A Processor Pin

List by Pin Name

Pin Name

Pin

Number

K5

K4

M4

N5

J5

K2

L3

M1

AF3

AG1

AJ3

AK1

G1

G5

J2

J1

H6

G2

J6

J3

C2

F5

F3

G4

D1

D2

F2

F1

E4

A6

A4

C4

B5

A5

C3

B3

Buffer

Type

Dir.

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Datasheet

Processor Pin and Signal Information

SB_DQ[52]

SB_DQ[53]

SB_DQ[54]

SB_DQ[55]

SB_DQ[56]

SB_DQ[57]

SB_DQ[58]

SB_DQ[59]

SB_DQ[60]

SB_DQ[61]

SB_DQ[62]

SB_DQ[63]

SB_DQS[0]

SB_DQS[1]

SB_DQS[2]

SB_DQS[3]

SB_DQS[4]

SB_DQS[5]

SB_DQS[6]

SB_DQS[7]

SB_DQ[36]

SB_DQ[37]

SB_DQ[38]

SB_DQ[39]

SB_DQ[40]

SB_DQ[41]

SB_DQ[42]

SB_DQ[43]

SB_DQ[44]

SB_DQ[45]

SB_DQ[46]

SB_DQ[47]

SB_DQ[48]

SB_DQ[49]

SB_DQ[50]

SB_DQ[51]

Table 8-49.rPGA988A Processor Pin

List by Pin Name

Pin Name

Pin

Number

AT7

AP9

AR10

AT10

C5

E3

H4

M5

AN4

AN3

AT5

AT6

AN7

AP6

AP8

AT9

AG2

AL5

AP5

AR7

AK5

AK2

AM4

AM3

AP3

AN5

AT4

AN6

AG4

AG3

AJ4

AH4

AK3

AK4

AM6

AN2

Buffer

Type

Dir.

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Table 8-49.rPGA988A Processor Pin

List by Pin Name

Pin Name

Pin

Number

AC7

AD1

Y7

AC6

AH24

AK13

R3

AF7

P5

N1

R4

R5

AB5

P3

R1

T8

R2

R6

U5

V2

T5

V3

AH2

AL4

AR5

AR8

D5

F4

J4

L4

SB_MA[8]

SB_MA[9]

SB_MA[10]

SB_MA[11]

SB_MA[12]

SB_MA[13]

SB_MA[14]

SB_MA[15]

SB_ODT[0]

SB_ODT[1]

SB_RAS#

SB_WE#

SKTOCC#

SM_DRAMPWRO

K

SM_DRAMRST#

SM_RCOMP[0]

SM_RCOMP[1]

SM_RCOMP[2]

TAPPWRGOOD

SB_DQS#[0]

SB_DQS#[1]

SB_DQS#[2]

SB_DQS#[3]

SB_DQS#[4]

SB_DQS#[5]

SB_DQS#[6]

SB_DQS#[7]

SB_MA[0]

SB_MA[1]

SB_MA[2]

SB_MA[3]

SB_MA[4]

SB_MA[5]

SB_MA[6]

SB_MA[7]

F6

AL1

AM1

AN1

AM26

DDR3

DDR3

Analog

Analog

Analog

Async

CMOS

O

I

I

O

I

O

Buffer

Type

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

Dir.

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

Datasheet 130

131

Processor Pin and Signal Information

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

TMS

TRST#

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

Table 8-49.rPGA988A Processor Pin

List by Pin Name

Pin Name

TCK

TDI

TDI_M

TDO

TDO_M

THERMTRIP#

Pin

Number

AN28

AT29

AR29

AR27

AP29

AK15

Buffer

Type

Dir.

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

CMOS

CMOS

REF

REF

REF

REF

REF

REF

CMOS

CMOS

CMOS

CMOS

CMOS

Async

GTL

I

O

I

I

O

O

I

I

AN19

AN21

AP16

AP18

AP19

AP21

AL19

AL21

AM16

AM18

AM19

AM21

AN16

AN18

AJ19

AJ21

AK16

AK18

AK19

AK21

AL16

AL18

AP28

AT27

AH16

AH18

AH19

AH21

AJ16

AJ18

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG_SENSE

VCC

VCC

VCC

VCC

VCC

VCC

VCC

Table 8-49.rPGA988A Processor Pin

List by Pin Name

Pin Name

Pin

Number

AC31

AC32

AC33

AC34

AC35

AD26

AD27

AD28

AA33

AA34

AA35

AC26

AC27

AC28

AC29

AC30

AD29

AD30

AD31

AD32

AR22

AA26

AA27

AA28

AA29

AA30

AA31

AA32

AR16

AR18

AR19

AR21

AT16

AT18

AT19

AT21

Buffer

Type

Dir.

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

Analog

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

O

Datasheet

Processor Pin and Signal Information

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

Table 8-49.rPGA988A Processor Pin

List by Pin Name

Pin Name

Pin

Number

P31

P32

P33

P34

P27

P28

P29

P30

AG29

AG30

AG31

AG32

AG33

AG34

AG35

P26

P35

R26

R27

R28

AF31

AF32

AF33

AF34

AF35

AG26

AG27

AG28

AD33

AD34

AD35

AF26

AF27

AF28

AF29

AF30

Buffer

Type

Dir.

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

Table 8-49.rPGA988A Processor Pin

List by Pin Name

Pin Name

Pin

Number

Y27

Y28

Y29

Y30

V33

V34

V35

Y26

Y31

Y32

Y33

Y34

V29

V30

V31

V32

U35

V26

V27

V28

U27

U28

U29

U30

U31

U32

U33

U34

R29

R30

R31

R32

R33

R34

R35

U26

Buffer

Type

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

Dir.

Datasheet 132

133

Processor Pin and Signal Information

Table 8-49.rPGA988A Processor Pin

List by Pin Name

Pin Name

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VID[0]

VID[1]

VID[2]

CSC[0]/VID[3]

VCC

VCC_SENSE

VCCPLL

VCCPLL

VCCPLL

VCCPWRGOOD_

0

VCCPWRGOOD_

1

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

CSC[1]/VID[4]

CSC[2]/VID[5]

VID[6]

VSS

VSS

VSS

Pin

Number

Y35

AJ34

L26

L27

M26

AN27

AN14

W7

Y1

AK35

AK33

AK34

AL35

AL33

AM33

AM35

A23

A27

A29

T4

T7

U1

W4

L1

N4

N7

P1

AB4

AB7

AC1

AE4

AE7

AF1

AJ1

H1

Buffer

Type

Dir.

REF

REF

REF

REF

CMOS

CMOS

CMOS

CMOS

REF

REF

REF

REF

REF

REF

REF

REF

REF

Analog

REF

REF

REF

Async

CMOS

Async

CMOS

REF

REF

REF

REF

REF

REF

CMOS

CMOS

CMOS

GND

GND

GND

O

I

I

O

O

O

I/O

I/O

I/O

O

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

Table 8-49.rPGA988A Processor Pin

List by Pin Name

Pin Name

Pin

Number

AE33

AE34

AE35

AE6

AF2

AF4

AF8

AG10

AD10

AE26

AE27

AE28

AE29

AE30

AE31

AE32

AH13

AH17

AH20

AH26

AB32

AB33

AB34

AB35

AB6

AC2

AC4

AC8

A9

AA10

AB26

AB27

AB28

AB29

AB30

AB31

Buffer

Type

Dir.

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

Datasheet

Processor Pin and Signal Information

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

Table 8-49.rPGA988A Processor Pin

List by Pin Name

Pin Name

Pin

Number

AK27

AK29

AL12

AL17

AL20

AL23

AL3

AL31

AJ20

AJ23

AJ31

AJ5

AJ8

AK17

AK20

AK25

AL34

AL6

AL9

AM11

AH34

AH35

AH6

AH9

AJ11

AJ14

AJ17

AJ2

AH27

AH28

AH29

AH3

AH30

AH31

AH32

AH33

Buffer

Type

Dir.

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

Table 8-49.rPGA988A Processor Pin

List by Pin Name

Pin Name

Pin

Number

AR17

AR20

AR23

AR24

AR26

AR28

AR3

AR31

AP17

AP2

AP20

AP34

AP4

AP7

AR12

AR15

AR6

AR9

AT17

AT20

AM8

AN17

AN20

AN23

AN31

AN34

AP10

AP13

AM14

AM17

AM2

AM20

AM25

AM27

AM29

AM5

Buffer

Type

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

Dir.

Datasheet 134

135

Processor Pin and Signal Information

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

Table 8-49.rPGA988A Processor Pin

List by Pin Name

Pin Name

Pin

Number

E2

E21

E24

E29

D9

E11

E13

E18

C29

C32

C34

D26

D3

D30

D33

D6

E32

E35

E5

E8

B6

B8

C16

C19

C20

C22

C24

C28

B21

B25

B31

B4

B11

B13

B17

B18

Buffer

Type

Dir.

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

Table 8-49.rPGA988A Processor Pin

List by Pin Name

Pin Name

Pin

Number

J32

K27

K3

K30

H8

J19

J21

J30

H2

H22

H24

H26

H28

H32

H35

H5

K33

K34

K6

K9

G31

G34

G6

G9

H11

H13

H15

H18

F27

F30

G20

G3

F16

F19

F22

F25

Buffer

Type

Dir.

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

Datasheet

Processor Pin and Signal Information

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

Table 8-49.rPGA988A Processor Pin

List by Pin Name

Pin Name

Pin

Number

T32

T33

T34

T35

T28

T29

T30

T31

T6

U2

U4

U8

N35

N6

P2

P4

P8

R10

T26

T27

N27

N28

N29

N30

N31

N32

N33

N34

L5

L8

M10

N26

L2

L29

L32

L35

Buffer

Type

Dir.

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

Table 8-49.rPGA988A Processor Pin

List by Pin Name

Pin Name

Pin

Number

W33

W34

W35

W6

Y2

Y4

Y8

A35

V10

W26

W27

W28

W29

W30

W31

W32

AR34

AT1

AT35

B1

B2

B34

AJ35

A15

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS_NCTF

VSS_NCTF

VSS_NCTF

VSS_NCTF

VSS_NCTF

VSS_NCTF

VSS_NCTF

VSS_SENSE

VSS_SENSE_VT

T

VSSAXG_SENSE

VTT_SELECT

VTT_SENSE

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

AT22

G15

B15

A11

A12

A13

A14

AB10

AC10

AE10

AF10

AH10

Analog

Analog

Analog

CMOS

Analog

REF

REF

REF

REF

REF

REF

REF

REF

REF

O

O

O

O

O

Buffer

Type

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

Dir.

Datasheet 136

137

Processor Pin and Signal Information

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

Table 8-49.rPGA988A Processor Pin

List by Pin Name

Pin Name

Pin

Number

H14

J11

J12

J13

J14

J15

J16

K10

F12

F13

F14

G11

G12

G13

G14

H12

L10

N10

P10

T10

C14

D11

D12

D13

D14

E12

E14

F11

AH11

AH12

AH14

B12

B14

C11

C12

C13

Buffer

Type

Dir.

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

VTT1

VTT1

VTT1

VTT1

VTT1

VTT1

VTT1

VTT1

VTT0

VTT0

VTT0

VTT1

VTT1

VTT1

VTT1

VTT1

VTT1

VTT1

VTT1

VTT1

VTT1

VTT1

VTT1

VTTPWRGOOD

Table 8-49.rPGA988A Processor Pin

List by Pin Name

Pin Name

Pin

Number

G28

H19

H20

H21

H25

H27

J18

J20

U10

W10

Y10

E25

E26

F26

G26

G27

J22

J23

J24

J25

J26

J27

K26

AM15

Buffer

Type

Dir.

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

Async

CMOS

I

Datasheet

Processor Pin and Signal Information

Figure 8-21.BGA1288 Ballmap (Top View, Upper-Left Quadrant)

Datasheet 138

Processor Pin and Signal Information

Figure 8-22.BGA1288 Ballmap (Top View, Upper-Right Quadrant)

139 Datasheet

Processor Pin and Signal Information

Figure 8-23.BGA1288 Ballmap (Top View, Lower-Left Quadrant)

Datasheet 140

Processor Pin and Signal Information

Figure 8-24.BGA1288 Ballmap (Top View, Lower-Right Quadrant)

141 Datasheet

Processor Pin and Signal Information

CFG[6]

CFG[7]

CFG[8]

CFG[9]

CFG[10]

CFG[11]

CFG[12]

CFG[13]

CFG[14]

CFG[15]

CFG[16]

CFG[17]

COMP0

BPM#[0]

BPM#[1]

BPM#[2]

BPM#[3]

BPM#[4]

BPM#[5]

BPM#[6]

BPM#[7]

CATERR#

CFG[0]

CFG[1]

CFG[2]

CFG[3]

CFG[4]

CFG[5]

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 1 of 37)

Pin Name

BCLKAC71

BCLK #

BCLK_ITP

BCLK_ITP #

Pin #

AK7

AK8

K71

J70

Buffer

Type

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

Analog

GTL

GTL

GTL

GTL

GTL

GTL

GTL

GTL

DIFF

CLK

DIFF

CLK

DIFF

CLK

DIFF

CLK

GTL

Dir

I

I

O

O

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I/O

I/O

I

I

I/O

I/O

I/O

I/O

I/O

I/O

I/O

AT2

AG7

AF4

AG2

AH1

AC2

AC4

AE2

AD1

AF8

AF6

AB7

AE66

M69

N61

AL4

AM2

AK1

AK2

AK4

AJ2

J69

J67

J62

K65

K62

J64

K69

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 2 of 37)

Pin Name

DC_TEST_BV5

DC_TEST_BV68

DC_TEST_BV69

DC_TEST_BV71

DC_TEST_C3

DC_TEST_C69

DC_TEST_C71

DC_TEST_E1

DC_TEST_E71

DMI_RX[0]

DMI_RX[1]

DMI_RX[2]

DMI_RX[3]

DMI_RX#[0]

DMI_RX#[1]

DMI_RX#[2]

DMI_RX#[3]

DMI_TX[0]

DMI_TX[1]

DMI_TX[2]

COMP1

COMP2

COMP3

DBR#

DC_TEST_A5

DC_TEST_A68

DC_TEST_A69

DC_TEST_A71

DC_TEST_BR1

DC_TEST_BR71

DC_TEST_BT1

DC_TEST_BT3

DC_TEST_BT69

DC_TEST_BT71

DC_TEST_BV1

DC_TEST_BV3

Pin #

DMI

DMI

DMI

DMI

DMI

DMI

DMI

DMI

DMI

DMI

DMI

Buffer

Type

Analog

Analog

Analog

Dir

I

O

I

I

J4

G17

M15

G13

J2

F7

J8

K8

E71

F9

J6

K9

BV5

BV68

BV69

BV71

C3

C69

C71

E1

BR1

BR71

BT1

BT3

BT69

BT71

BV1

BV3

AD69

AC70

AD71

W71

A5

A68

A69

A71

I

I

I

I

I

I

I

O

O

I

O

Datasheet 142

143

Processor Pin and Signal Information

FDI_FSYNC[0]

FDI_FSYNC[1]

FDI_INT

FDI_LSYNC[0]

FDI_LSYNC[1]

FDI_TX[0]

FDI_TX[1]

FDI_TX[2]

FDI_TX[3]

FDI_TX[4]

FDI_TX[5]

FDI_TX[6]

FDI_TX[7]

FDI_TX#[0]

FDI_TX#[1]

FDI_TX#[2]

FDI_TX#[3]

FDI_TX#[4]

FDI_TX#[5]

FDI_TX#[6]

FDI_TX#[7]

GFX_DPRSLPVR

GFX_IMON

GFX_VID[0]

GFX_VID[1]

GFX_VID[2]

GFX_VID[3]

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 3 of 37)

Pin Name

DMI_TX[3]

DMI_TX#[0]

DMI_TX#[1]

DMI_TX#[2]

DMI_TX#[3]

DPLL_REF_SSCLK

DPLL_REF_SSCLK#

Pin #

J11

H17

K15

J13

F10

Y2

W4

Buffer

Type

FDI

FDI

FDI

FDI

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

FDI

FDI

FDI

FDI

FDI

FDI

FDI

FDI

CMOS

CMOS

CMOS

CMOS

FDI

FDI

FDI

FDI

DMI

DMI

DMI

DMI

DMI

DIFF

CLK

DIFF

CLK

CMOS

Dir

I

O

O

O

O

O

I

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

I

I

I

I

I

M4

P1

N10

R7

U7

W8

AL71

AL69

AF71

AG67

AG70

AH71

U6

W10

L2

N7

N2

R2

N9

R8

AC7

AC9

AB5

AA1

AB2

K1

N5

PEG_RX[11]

PEG_RX[12]

PEG_RX[13]

PEG_RX[14]

PEG_RX[15]

PEG_RX#[0]

PEG_RX#[1]

PEG_RX#[2]

PEG_RX#[3]

PEG_RX#[4]

PEG_RX#[5]

PEG_RX#[6]

PEG_ICOMPI

PEG_ICOMPO

PEG_RBIAS

PEG_RCOMPO

PEG_RX[0]

PEG_RX[1]

PEG_RX[2]

PEG_RX[3]

PEG_RX[4]

PEG_RX[5]

PEG_RX[6]

PEG_RX[7]

PEG_RX[8]

PEG_RX[9]

PEG_RX[10]

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 4 of 37)

Pin Name

GFX_VID[4]

GFX_VID[5]

GFX_VID[6]

GFX_VR_EN

ISENSE

PECI

PEG_CLK

PEG_CLK#

Pin #

AN71

AM67

AM70

AH69

A41

N19

L21

J21

Buffer

Type

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

Analog

Analog

Analog

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

CMOS

CMOS

CMOS

CMOS

Analog

Async

Diff CLK

DIFF

CLK

Analog

Dir

I

I/O

I

I

O

O

O

O

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

I

D15

G40

G38

H34

B21

B19

B18

B16

P34

G28

H25

H24

M34

J28

G25

K24

B28

A27

B25

A24

B12

A13

B11

D12

F40

J38

G34

Datasheet

Processor Pin and Signal Information

PEG_TX[7]

PEG_TX[8]

PEG_TX[9]

PEG_TX[10]

PEG_TX[11]

PEG_TX[12]

PEG_TX[13]

PEG_TX[14]

PEG_TX[15]

PEG_TX#[0]

PEG_TX#[1]

PEG_TX#[2]

PEG_TX#[3]

PEG_TX#[4]

PEG_TX#[5]

PEG_TX#[6]

PEG_TX#[7]

PEG_TX#[8]

PEG_TX#[9]

PEG_TX#[10]

PEG_RX#[7]

PEG_RX#[8]

PEG_RX#[9]

PEG_RX#[10]

PEG_RX#[11]

PEG_RX#[12]

PEG_RX#[13]

PEG_RX#[14]

PEG_RX#[15]

PEG_TX[0]

PEG_TX[1]

PEG_TX[2]

PEG_TX[3]

PEG_TX[4]

PEG_TX[5]

PEG_TX[6]

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 5 of 37)

Pin Name Pin #

Buffer

Type

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

Dir

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

I

O

I

I

I

I

I

I

I

I

L20

N40

L38

M32

D40

A38

G32

B33

D36

J30

B30

D33

N28

M25

N24

F21

B35

L30

A31

B32

B14

L40

N38

N32

B39

B37

H32

A34

D29

B26

D26

B23

D22

A20

D19

A17

PROC_DPRSLPVR

PROCHOT#

PSI#

RESET_OBS#

RSTIN#

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD_TP

RSVD

RSVD_TP

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 6 of 37)

Pin Name

PEG_TX#[11]

PEG_TX#[12]

PEG_TX#[13]

PEG_TX#[14]

PEG_TX#[15]

PM_EXT_TS#[0]

PM_EXT_TS#[1]

PM_SYNC

PRDY#

PREQ#

Pin #

L28

N26

M24

G21

J20

AV66

AV64

M17

U71

U69

Buffer

Type

PCIe

PCIe

PCIe

PCIe

PCIe

CMOS

CMOS

CMOS

Async

GTL

Async

GTL

Dir

O

I/O

I/O

I

O

O

O

O

O

I

PROC_DETECT M71

F66

N67

F68

N70

AA71

AC69

AC71

AH66

AK66

AK69

AK71

AM66

AN69

G3

BE71

BE69

BB69

AY69

AW70

A10

AA69

CMOS

Async

GTL

Async

CMOS

Async

CMOS

CMOS

O

I/O

O

O

I

I/O

Datasheet 144

145

Processor Pin and Signal Information

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 7 of 37)

Pin Name Pin #

Buffer

Type

Dir

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

RSVD

VCAP0_VSS_SENSE W64

VCAP0_SENSE W66

RSVD_NCTF

RSVD_TP

A6

BR5

T2

T4

U1

V2

RSVD_NCTF

RSVD_NCTF

RSVD_NCTF

RSVD_NCTF

RSVD_NCTF

RSVD_NCTF

RSVD_TP

RSVD_TP

RSVD_TP

SA_BS[0]

SA_BS[1]

SA_BS[2]

AU1

BT38

BH38

BF21

BT5

BV6

BV8

C5

E3

F1

AN7

AP2

AV4

AV69

AV71

B7

B9

D8

R64

R66

AP66

AR69

AR71

AT67

AT70

AU2

AU69

AU71

DDR3

DDR3

DDR3

O

O

O

SA_DM[7]

SA_DQ[0]

SA_DQ[1]

SA_DQ[2]

SA_DQ[3]

SA_DQ[4]

SA_DQ[5]

SA_DQ[6]

SA_DQ[7]

SA_DQ[8]

SA_DQ[9]

SA_DQ[10]

SA_DQ[11]

SA_DQ[12]

SA_DQ[13]

SA_DQ[14]

SA_DQ[15]

SA_DQ[16]

SA_DQ[17]

SA_DQ[18]

SA_CAS#

SA_CK[0]

SA_CK[1]

SA_CK#[0]

SA_CK#[1]

SA_CKE[0]

SA_CKE[1]

SA_CS#[0]

SA_CS#[1]

SA_DM[0]

SA_DM[1]

SA_DM[2]

SA_DM[3]

SA_DM[4]

SA_DM[5]

SA_DM[6]

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 8 of 37)

Pin Name Pin #

Buffer

Type

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

Dir

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

O

O

O

O

I/O

O

I/O

O

O

O

O

O

O

O

O

O

BE8

BF11

BE11

BK5

BH13

BF9

BF6

BK7

BH59

AT8

AT6

BB5

BB9

AV7

AV6

BE6

BN8

BN11

BN9

BG17

BJ47

BB10

BJ10

BM15

BN24

BG44

BG53

BN62

BK43

BM34

BK36

BP35

BH36

BF20

BK24

BH40

Datasheet

Processor Pin and Signal Information

SA_DQ[35]

SA_DQ[36]

SA_DQ[37]

SA_DQ[38]

SA_DQ[39]

SA_DQ[40]

SA_DQ[41]

SA_DQ[42]

SA_DQ[43]

SA_DQ[44]

SA_DQ[45]

SA_DQ[46]

SA_DQ[47]

SA_DQ[48]

SA_DQ[49]

SA_DQ[50]

SA_DQ[51]

SA_DQ[52]

SA_DQ[53]

SA_DQ[54]

SA_DQ[19]

SA_DQ[20]

SA_DQ[21]

SA_DQ[22]

SA_DQ[23]

SA_DQ[24]

SA_DQ[25]

SA_DQ[26]

SA_DQ[27]

SA_DQ[28]

SA_DQ[29]

SA_DQ[30]

SA_DQ[31]

SA_DQ[32]

SA_DQ[33]

SA_DQ[34]

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 9 of 37)

Pin Name Pin #

Buffer

Type

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

Dir

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

BJ55

BH48

BJ48

BM53

BN55

BF55

BN57

BN65

BF48

BN40

BH43

BN44

BN47

BN48

BN51

BH53

BJ61

BF57

BJ57

BK64

BH25

BJ20

BH21

BG24

BG25

BJ40

BM43

BF47

BK15

BK9

BG15

BH17

BK17

BN20

BN17

BK25

SA_DQS[7]

SA_DQS#[0]

SA_DQS#[1]

SA_DQS#[2]

SA_DQS#[3]

SA_DQS#[4]

SA_DQS#[5]

SA_DQS#[6]

SA_DQS#[7]

SA_MA[0]

SA_MA[1]

SA_MA[2]

SA_MA[3]

SA_MA[4]

SA_MA[5]

SA_MA[6]

SA_MA[7]

SA_MA[8]

SA_MA[9]

SA_MA[10]

SA_DQ[55]

SA_DQ[56]

SA_DQ[57]

SA_DQ[58]

SA_DQ[59]

SA_DQ[60]

SA_DQ[61]

SA_DQ[62]

SA_DQ[63]

SA_DQS[0]

SA_DQS[1]

SA_DQS[2]

SA_DQS[3]

SA_DQS[4]

SA_DQS[5]

SA_DQS[6]

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 10 of 37)

Pin Name Pin #

Buffer

Type

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

Dir

O

O

O

O

I/O

O

O

O

O

O

O

O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

BE62

BT36

BP33

BV36

BG34

BG32

BN32

BK32

BE64

AY5

BJ7

BN13

BL21

BH44

BK51

BP58

BJ30

BN30

BF28

BH34

BC70

AY7

BJ5

BL13

BN21

BK44

BH51

BM60

BK61

BJ63

BF64

BB64

BB66

BJ66

BF65

AY64

Datasheet 146

147

Processor Pin and Signal Information

SB_CK#[1]

SB_CKE[0]

SB_CKE[1]

SB_CS#[0]

SB_CS#[1]

SB_DM[0]

SB_DM[1]

SB_DM[2]

SB_DM[3]

SB_DM[4]

SB_DM[5]

SB_DM[6]

SB_DM[7]

SB_DQ[0]

SB_DQ[1]

SB_DQ[2]

SB_DQ[3]

SB_DQ[4]

SB_DQ[5]

SB_DQ[6]

SA_MA[11]

SA_MA[12]

SA_MA[13]

SA_MA[14]

SA_MA[15]

SA_ODT[0]

SA_ODT[1]

SA_RAS#

SA_WE#

SB_BS[0]

SB_BS[1]

SB_BS[2]

SB_CAS#

SB_CK[0]

SB_CK[1]

SB_CK#[0]

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 11 of 37)

Pin Name Pin #

Buffer

Type

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

Dir

O

I/O

I/O

I/O

O

O

O

O

I/O

I/O

I/O

I/O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

O

BP22

BV47

BV57

BU65

BF67

BA2

AW2

BD1

BU39

BT26

BT24

BP46

BT43

BB4

BL4

BT13

BE4

AY1

BC2

BF2

BF38

BV43

BV41

BV24

BU46

BU33

BV38

BV34

BH30

BJ28

BF40

BN28

BN25

BF43

BL47

BL38

SB_DQ[23]

SB_DQ[24]

SB_DQ[25]

SB_DQ[26]

SB_DQ[27]

SB_DQ[28]

SB_DQ[29]

SB_DQ[30]

SB_DQ[31]

SB_DQ[32]

SB_DQ[33]

SB_DQ[34]

SB_DQ[35]

SB_DQ[36]

SB_DQ[37]

SB_DQ[38]

SB_DQ[39]

SB_DQ[40]

SB_DQ[41]

SB_DQ[42]

SB_DQ[7]

SB_DQ[8]

SB_DQ[9]

SB_DQ[10]

SB_DQ[11]

SB_DQ[12]

SB_DQ[13]

SB_DQ[14]

SB_DQ[15]

SB_DQ[16]

SB_DQ[17]

SB_DQ[18]

SB_DQ[19]

SB_DQ[20]

SB_DQ[21]

SB_DQ[22]

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 12 of 37)

Pin Name Pin #

Buffer

Type

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

Dir

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

BT20

BT48

BV48

BV50

BP49

BT47

BV52

BV54

BU16

BP15

BU19

BV22

BT22

BP19

BV19

BV20

BT54

BP53

BU53

BT59

BV10

BR10

BT12

BT15

BV15

BV12

BP12

BV17

BH2

BG4

BG1

BR6

BR8

BJ4

BK2

BU9

Datasheet

Processor Pin and Signal Information

SB_DQ[59]

SB_DQ[60]

SB_DQ[61]

SB_DQ[62]

SB_DQ[63]

SB_DQS[0]

SB_DQS[1]

SB_DQS[2]

SB_DQS[3]

SB_DQS[4]

SB_DQS[5]

SB_DQS[6]

SB_DQS[7]

SB_DQS#[0]

SB_DQS#[1]

SB_DQS#[2]

SB_DQS#[3]

SB_DQS#[4]

SB_DQS#[5]

SB_DQS#[6]

SB_DQ[43]

SB_DQ[44]

SB_DQ[45]

SB_DQ[46]

SB_DQ[47]

SB_DQ[48]

SB_DQ[49]

SB_DQ[50]

SB_DQ[51]

SB_DQ[52]

SB_DQ[53]

SB_DQ[54]

SB_DQ[55]

SB_DQ[56]

SB_DQ[57]

SB_DQ[58]

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 13 of 37)

Pin Name Pin #

Buffer

Type

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

Dir

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

BT17

BT50

BU56

BV62

BJ69

BE2

BM3

BU12

BC67

BK70

BK67

BD71

BD69

BD4

BN4

BV13

BT19

BT52

BV55

BU63

BR64

BR62

BT61

BN68

BL69

BJ71

BF70

BG71

BT57

BP56

BT55

BU60

BV59

BV61

BP60

BR66

SB_DQS#[7]

SB_MA[0]

SB_MA[1]

SB_MA[2]

SB_MA[3]

SB_MA[4]

SB_MA[5]

SB_MA[6]

SB_MA[7]

SB_MA[8]

SB_MA[9]

SB_MA[10]

SB_MA[11]

SB_MA[12]

SB_MA[13]

SB_MA[14]

SB_MA[15]

SB_ODT[0]

SB_ODT[1]

SB_RAS#

SB_WE#

SM_DRAMPWROK

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 14 of 37)

TMS

Pin Name

SM_DRAMRST#

SM_RCOMP[0]

SM_RCOMP[1]

SM_RCOMP[2]

TAPPWRGOOD

TCK

TDI

TDI_M

TDO

TDO_M

THERMTRIP#

Pin #

T67

T69

P71

T71

T70

N17

BJ12

BV33

BP39

BV40

Y70

N65

Buffer

Type

DDR3

DDR3

DDR3

DDR3

DDR3

Async

CMOS

DDR3

Analog

Analog

Analog

Async

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

Async

GTL

CMOS

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

Dir

O

O

O

O

O

O

O

O

O

O

O

O

I/O

O

O

O

O

O

O

O

O

I

O

I

I

O

I

O

O

O

I

I

I

BP26

BV27

BT27

BU42

BU26

BT29

BT45

BV26

BG69

BT34

BP30

BV29

BU30

BV31

BT33

BT31

BU23

BV45

BU49

BT40

BT41

AM5

Datasheet 148

149

Processor Pin and Signal Information

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

TRST#

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 15 of 37)

Pin Name Pin #

Buffer

Type

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

CMOS

REF

REF

REF

REF

REF

REF

REF

Dir

I

AL23

AL24

AL26

AL28

AL30

AL32

AN19

AN21

AF28

AH12

AH14

AJ10

AK12

AK14

AL19

AL21

AN23

AN24

AN26

AN28

AF14

AF15

AF17

AF19

AF21

AF23

AF24

AF26

P69

AD17

AD19

AD21

AD23

AD24

AD26

AD28

VCAP0

VCAP0

VCAP0

VCAP0

VCAP0

VCAP0

VCAP1

VCAP1

VCAP0

VCAP0

VCAP0

VCAP0

VCAP0

VCAP0

VCAP0

VCAP0

VCAP1

VCAP1

VCAP1

VCAP1

VCAP0

VCAP0

VCAP0

VCAP0

VCAP0

VCAP0

VCAP0

VCAP0

VAXG

VAXG

VAXG_SENSE

VCAP0

VCAP0

VCAP0

VCAP0

VCAP0

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 16 of 37)

Pin Name Pin #

Buffer

Type

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

REF

REF

Analog

PWR

PWR

PWR

PWR

PWR

Dir

O

BB48

BB51

BB55

BD48

BD51

BD55

AK39

AK42

AU51

AU55

AW50

AW53

AW57

AY50

AY53

AY57

AK46

AL39

AL42

AL46

AL57

AN50

AN53

AN57

AR48

AR51

AR55

AU48

AN30

AN32

AF12

AK50

AK53

AK57

AL50

AL53

Datasheet

Processor Pin and Signal Information

VCAP2

VCAP2

VCAP2

VCAP2

VCAP2

VCAP2

VCAP2

VCAP2

VCAP1

VCAP1

VCAP1

VCAP1

VCAP1

VCAP2

VCAP2

VCAP2

VCAP2

VCAP2

VCAP2

VCAP2

VCAP1

VCAP1

VCAP1

VCAP1

VCAP1

VCAP1

VCAP1

VCAP1

VCAP1

VCAP1

VCAP1

VCAP1

VCAP1

VCAP1

VCAP1

VCAP1

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 17 of 37)

Pin Name Pin #

Buffer

Type

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

PWR

Dir

AB60

AD59

AD60

AF59

AF60

AH59

AH60

AK59

BB41

BB44

BD37

BD41

BD44

AA59

AA60

AB59

AK60

AK62

R59

R60

AU44

AW39

AW42

AW46

AY39

AY42

AY46

BB37

AN39

AN42

AN46

AR37

AR41

AR44

AU37

AU41

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCAP2

VCAP2

VCAP2

VCAP2

VCC

VCC

VCC

VCC

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 18 of 37)

Pin Name Pin #

Buffer

Type

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

PWR

PWR

PWR

PWR

REF

REF

REF

REF

Dir

AF41

AF42

AF44

AF46

AF48

AF50

AF51

AF53

AB48

AB51

AB55

AD41

AD44

AD48

AD51

AD55

AF55

AF57

B42

B46

A57

AA41

AA44

AA48

AA51

AA55

AB41

AB44

U59

U60

W59

W60

A43

A47

A50

A54

Datasheet 150

151

Processor Pin and Signal Information

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 19 of 37)

Pin Name Pin #

Buffer

Type

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

Dir

J55

K44

K51

K60

G60

H44

H51

H60

F55

G44

G51

G55

E50

E53

E57

E60

L55

M44

M51

M60

D50

D52

D54

D55

D57

D59

E42

E46

B49

B53

B56

B60

D43

D45

D47

D48

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VCC_SENSE

VCCPLL

VCCPLL

VCCPLL

VCCPLL

VCCPLL

VCCPWRGOOD_0

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 20 of 37)

Pin Name

VCCPWRGOOD_1

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

Pin #

AM7

BB15

BB17

BB19

BB21

BB23

Buffer

Type

REF

REF

REF

Async

CMOS

Async

CMOS

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

Analog

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

Dir

O

I

I

W41

W44

W48

W51

W55

F64

R37

R39

U37

W37

W39

Y67

R48

R51

R55

U41

U44

U48

U51

U55

N42

N44

N48

N51

N55

P60

R41

R44

Datasheet

Processor Pin and Signal Information

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ_CK

VDDQ_CK

VID[0]

VID[1]

VID[2]

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

VDDQ

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 21 of 37)

Pin Name Pin #

Buffer

Type

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

CMOS

CMOS

CMOS

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

Dir

O

O

O

BJ38

BL30

BM25

BN38

BU28

BU35

BU40

BB12

BD32

BD33

BD35

BF15

BF16

BG43

BH28

BH32

BB14

A61

D61

D62

BD17

BD19

BD21

BD23

BD24

BD26

BD28

BD30

BB24

BB26

BB28

BB30

BB32

BB33

BB35

BD15

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

CSC[0]/VID[3]

CSC[1]VID[4]

CSC[2]VID[5]

VID[6]

VSS

VSS

VSS

VSS

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 22 of 37)

Pin Name Pin #

Buffer

Type

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

CMOS

CMOS

CMOS

CMOS

GND

GND

GND

GND

Dir

I/O

I/O

I/O

O

AA19

AA21

AA23

AA24

AA26

AA28

AA30

AA32

A55

A59

A64

A66

A8

AA14

AA15

AA17

AA33

AA35

AA37

AA39

A40

A45

A48

A52

A26

A29

A33

A36

A12

A15

A19

A22

A62

B63

D64

D66

Datasheet 152

153

Processor Pin and Signal Information

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 23 of 37)

Pin Name Pin #

Buffer

Type

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

Dir

AB42

AB46

AB50

AB53

AB57

AB62

AB70

AB9

AB26

AB28

AB30

AB32

AB33

AB35

AB37

AB39

AC1

AC10

AC5

AC64

AA66

AB14

AB15

AB17

AB19

AB21

AB23

AB24

AA4

AA42

AA46

AA50

AA53

AA57

AA62

AA64

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 24 of 37)

Pin Name Pin #

Buffer

Type

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

Dir

AH30

AH32

AH33

AH35

AH37

AH39

AH4

AH41

AH15

AH17

AH19

AH21

AH23

AH24

AH26

AH28

AH42

AH44

AH46

AH48

AE64

AE70

AF1

AF62

AF69

AG6

AG64

AG9

AC67

AD4

AD42

AD46

AD50

AD53

AD57

AD62

Datasheet

Processor Pin and Signal Information

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 25 of 37)

Pin Name Pin #

Buffer

Type

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

Dir

AK70

AL1

AL33

AL35

AL37

AL41

AL44

AL48

AK32

AK37

AK41

AK44

AK48

AK51

AK55

AK64

AL51

AL55

AL62

AM64

AK17

AK19

AK21

AK23

AK24

AK26

AK28

AK30

AH50

AH51

AH53

AH55

AH57

AH62

AJ70

AK15

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 26 of 37)

Pin Name Pin #

Buffer

Type

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

Dir

AR33

AR35

AR39

AR4

AR42

AR46

AR50

AR53

AR19

AR21

AR23

AR24

AR26

AR28

AR30

AR32

AR57

AR62

AT10

AT64

AN55

AN62

AP64

AP70

AR1

AR14

AR15

AR17

AM8

AN37

AN4

AN41

AN44

AN48

AN5

AN51

Datasheet 154

155

Processor Pin and Signal Information

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 27 of 37)

Pin Name Pin #

Buffer

Type

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

Dir

AW37

AW41

AW44

AW48

AW51

AW55

AW59

AW62

AU46

AU50

AU53

AU57

AU62

AU70

AV1

AV9

AW67

AY12

AY14

AY15

AU28

AU30

AU32

AU33

AU35

AU39

AU4

AU42

AU14

AU15

AU17

AU19

AU21

AU23

AU24

AU26

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 28 of 37)

Pin Name Pin #

Buffer

Type

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

Dir

B44

B48

B51

B55

B58

B62

B65

BA70

AY51

AY55

AY59

AY62

AY66

AY71

AY8

B40

BB1

BB39

BB42

BB46

AY32

AY33

AY35

AY37

AY4

AY41

AY44

AY48

AY17

AY19

AY21

AY23

AY24

AY26

AY28

AY30

Datasheet

Processor Pin and Signal Information

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 29 of 37)

Pin Name Pin #

Buffer

Type

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

Dir

BH20

BH24

BH47

BH55

BH57

BH70

BJ1

BJ21

BE9

BF13

BF30

BF62

BF8

BG36

BG51

BH15

BJ64

BJ9

BK10

BK34

BD42

BD46

BD50

BD53

BD57

BE1

BE65

BE70

BB50

BB53

BB57

BB62

BB7

BB71

BD14

BD39

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 30 of 37)

Pin Name Pin #

Buffer

Type

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

Dir

BR69

BT68

BU11

BU14

BU18

BU21

BU25

BU32

BM70

BN1

BN6

BN64

BN71

BP42

BR3

BR68

BU37

BU44

BU48

BU51

BL55

BL57

BL71

BM17

BM24

BM32

BM44

BM51

BK53

BK60

BK63

BL1

BL20

BL28

BL40

BL48

Datasheet 156

157

Processor Pin and Signal Information

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 31 of 37)

Pin Name Pin #

Buffer

Type

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

Dir

F71

G15

G20

G24

F4

F47

F48

F61

E68

E69

F20

F28

D41

D6

E12

E16

E30

E33

E37

E5

D13

D17

D20

D24

D27

D31

D34

D38

BU55

BU58

BU62

BU7

BV64

BV66

C68

D10

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 32 of 37)

Pin Name Pin #

Buffer

Type

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

Dir

K4

K43

K53

K6

K64

L13

L47

L48

J65

J9

K11

K17

K25

K32

K34

K36

L57

L70

M1

M36

J40

J47

J48

J57

H36

H43

H53

H71

G30

G43

G47

G48

G53

G57

G70

H1

Datasheet

Processor Pin and Signal Information

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 33 of 37)

Pin Name Pin #

Buffer

Type

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

Dir

U46

U50

U53

U57

U62

U64

U9

V70

R53

R57

R62

R70

T1

U39

U4

U42

W1

W42

W46

W50

N57

N63

P4

R14

R42

R46

R5

R50

M42

M53

N15

N21

N30

N46

N50

N53

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VSS

VSS

VSS

VSS

VSS

VSS_SENSE

VSS_SENSE_VTT

VSSAXG_SENSE

VTT_SELECT

VTT_SENSE

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 34 of 37)

Pin Name Pin #

Buffer

Type

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

CMOS

Analog

REF

REF

REF

REF

REF

REF

GND

GND

GND

GND

GND

Analog

Analog

Analog

Dir

O

O

O

O

O

AL12

AL14

AL15

AL17

AL59

AL60

AM10

AN12

AF30

AF32

AF33

AF35

AF37

AF39

AK33

AK35

AN14

AN15

AN17

AN33

AN1

N13

AD30

AD32

AD33

AD35

AD37

AD39

W53

W57

W6

W62

W69

F63

R12

AF10

Datasheet 158

159

Processor Pin and Signal Information

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 35 of 37)

Pin Name Pin #

Buffer

Type

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

Dir

R24

R26

R28

R30

R32

R33

R35

U23

AY60

BB59

BB60

BD59

BD60

BF59

BF60

R23

U24

U26

U28

U30

AU59

AU60

AW12

AW14

AW33

AW35

AW60

AY10

AN35

AN59

AN60

AN9

AR12

AR59

AR60

AU12

VTT1

VTT1

VTT1

VTT1

VTT1

VTT1

VTT1

VTT1

VTT0_DDR

VTT0_DDR

VTT0_DDR

VTT0_DDR

VTT0_DDR

VTT1

VTT1

VTT1

VTT1

VTT1

VTT1

VTT1

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0_DDR

VTT0_DDR

VTT0_DDR

VTT0_DDR

VTT0_DDR

Table 8-50.BGA1288 Processor Ball

List by Ball Name

(Sheet 36 of 37)

Pin Name Pin #

Buffer

Type

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

Dir

AD14

AD15

R15

R17

R19

R21

U12

U14

AW24

AW26

AW28

AW30

AW32

AA12

AB12

AD12

U15

U17

U19

U21

W32

W33

W35

AW15

AW17

AW19

AW21

AW23

U32

U33

U35

W23

W24

W26

W28

W30

Datasheet

Processor Pin and Signal Information

Table 8-50.BGA1288 Processor Ball

List by Ball Name

Pin Name

VTT1

VTT1

VTT1

VTT1

VTT1

VTT1

VTTPWRGOOD

(Sheet 37 of 37)

Pin #

W12

W14

W15

W17

W19

W21

H15

Buffer

Type

REF

REF

REF

REF

REF

REF

Async

CMOS

Dir

I

A26

A27

A29

A31

A19

A20

A22

A24

A12

A13

A15

A17

A5

A6

A8

A10

A33

A34

A36

A38

A40

A41

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 1 of 37)

Pin # Pin Name

Buffer

Type

Dir

DC_TEST_A5

RSVD_NCTF

VSS

RSVD

VSS

PEG_ICOMPO

VSS

PEG_RX#[14]

VSS

PEG_RX#[12]

VSS

PEG_RX[10]

VSS

PEG_RX[8]

VSS

PEG_TX#[9]

VSS

PEG_TX[6]

VSS

PEG_TX#[4]

VSS

ISENSE

GND

I

I

I

I

I

O

O

O

I

GND

PCIe

GND

PCIe

GND

PCIe

GND

PCIe

GND

Analog

GND

Analog

GND

PCIe

GND

PCIe

GND

PCIe

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 2 of 37)

Pin # Pin Name

A64

A66

A68

A69

A57

A59

A61

A62

A50

A52

A54

A55

A43

A45

A47

A48

A71

AA1

DC_TEST_A71

FDI_LSYNC[0]

AA4 VSS

AA12 VTT1

AA14 VSS

AA15 VSS

AA17 VSS

AA19 VSS

AA21 VSS

AA23 VSS

AA24 VSS

AA26 VSS

AA28 VSS

AA30 VSS

AA32 VSS

AA33 VSS

AA35 VSS

AA37 VSS

AA39 VSS

AA41 VCC

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VID[0]

CSC[0]/VID[3]

VSS

VSS

DC_TEST_A68

DC_TEST_A69

Buffer

Type

Dir

REF

GND

CMOS

CMOS

GND

GND

REF

GND

REF

GND

REF

GND

REF

GND

O

I/O

I

GND

GND

GND

GND

GND

GND

GND

GND

CMOS

GND

REF

GND

GND

GND

GND

GND

GND

GND

REF

Datasheet 160

161

Processor Pin and Signal Information

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 3 of 37)

Pin # Pin Name

AA42 VSS

AA44 VCC

AA46 VSS

AA48 VCC

AA50 VSS

AA51 VCC

AA53 VSS

AA55 VCC

AA57 VSS

AA59 VCAP2

AA60 VCAP2

AA62 VSS

AA64 VSS

AA66 VSS

AA69 RSVD

AA71 RSVD_TP

AB2

AB5

AB7

AB9

FDI_LSYNC[1]

FDI_INT

CFG[17]

VSS

AB12 VTT1

AB14 VSS

AB15 VSS

AB17 VSS

AB19 VSS

AB21 VSS

AB23 VSS

AB24 VSS

AB26 VSS

AB28 VSS

AB30 VSS

AB32 VSS

AB33 VSS

AB35 VSS

AB37 VSS

AB39 VSS

Buffer

Type

Dir

GND

REF

GND

REF

GND

REF

GND

REF

GND

PWR

PWR

GND

GND

GND

I

I

I

GND

GND

GND

GND

GND

GND

GND

GND

CMOS

CMOS

CMOS

GND

REF

GND

GND

GND

GND

GND

GND

GND

AB41 VCC

AB42 VSS

AB44 VCC

AB46 VSS

AB48 VCC

AB50 VSS

AB51 VCC

AB53 VSS

AB55 VCC

AB57 VSS

AB59 VCAP2

AB60 VCAP2

AB62 VSS

AB70 VSS

AC1

AC2

VSS

CFG[11]

AC4

AC5

AC7

AC9

CFG[12]

VSS

FDI_FSYNC[0]

FDI_FSYNC[1]

AC10 VSS

AC64 VSS

AC67 VSS

AC69 RSVD

AC70 COMP2

AC71 RSVD_TP

AD1

AD4

CFG[14]

VSS

AD12 VTT1

AD14 VTT1

AD15 VTT1

AD17 VAXG

AD19 VAXG

AD21 VAXG

AD23 VAXG

AD24 VAXG

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 4 of 37)

Pin # Pin Name

Buffer

Type

Dir

REF

GND

PWR

PWR

GND

GND

GND

CMOS

REF

GND

REF

GND

REF

GND

REF

GND

CMOS

GND

CMOS

CMOS

GND

GND

GND

I

I

I

I

Analog

CMOS

GND

REF

REF

REF

REF

REF

REF

REF

REF

I

I

Datasheet

Processor Pin and Signal Information

AD26 VAXG

AD28 VAXG

AD30 VTT0

AD32 VTT0

AD33 VTT0

AD35 VTT0

AD37 VTT0

AD39 VTT0

AD41 VCC

AD42 VSS

AD44 VCC

AD46 VSS

AD48 VCC

AD50 VSS

AD51 VCC

AD53 VSS

AD55 VCC

AD57 VSS

AD59 VCAP2

AD60 VCAP2

AD62 VSS

AD69 COMP1

AD71 COMP3

AE2 CFG[13]

AE64 VSS

AE66 COMP0

AE70 VSS

AF1 VSS

AF4

AF10

AF12

AF14

CFG[8]

VSSAXG_SENSE

VAXG_SENSE

VAXG

AF15

AF17

AF19

AF21

VAXG

VAXG

VAXG

VAXG

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 5 of 37)

Pin # Pin Name

Buffer

Type

Dir

GND

Analog

GND

GND

CMOS

Analog

Analog

REF

REF

GND

PWR

PWR

GND

Analog

Analog

CMOS

REF

REF

REF

REF

REF

GND

REF

GND

REF

GND

REF

GND

REF

REF

REF

REF

REF

REF

REF

REF

I

I

I

I

I

O

O

AF37

AF39

AF41

AF42

AF44

AF46

AF48

AF50

AF23

AF24

AF26

AF28

AF30

AF32

AF33

AF35

AF51

AF53

AF55

AF57

AF59

AF6

AF60

AF62

VCC

VCC

VCC

VCC

VCAP2

CFG[16]

VCAP2

VSS

AF69

AF71

AF8

AG2

VSS

GFX_VID[0]

CFG[15]

CFG[9]

AG6

AG7

VSS

CFG[7]

AG9 VSS

AG64 VSS

AG67 GFX_VID[1]

AG70 GFX_VID[2]

AH1

AH4

CFG[10]

VSS

VTT0

VTT0

VCC

VCC

VCC

VCC

VCC

VCC

VAXG

VAXG

VAXG

VAXG

VTT0

VTT0

VTT0

VTT0

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 6 of 37)

Pin # Pin Name

Buffer

Type

Dir

GND

CMOS

CMOS

CMOS

GND

CMOS

GND

GND

REF

REF

REF

REF

PWR

CMOS

PWR

GND

CMOS

CMOS

CMOS

GND

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

REF

I

I

O

I

I

O

O

I

Datasheet 162

163

Processor Pin and Signal Information

AH12 VAXG

AH14 VAXG

AH15 VSS

AH17 VSS

AH19 VSS

AH21 VSS

AH23 VSS

AH24 VSS

AH26 VSS

AH28 VSS

AH30 VSS

AH32 VSS

AH33 VSS

AH35 VSS

AH37 VSS

AH39 VSS

AH41 VSS

AH42 VSS

AH44 VSS

AH46 VSS

AH48 VSS

AH50 VSS

AH51 VSS

AH53 VSS

AH55 VSS

AH57 VSS

AH59 VCAP2

AH60 VCAP2

AH62 VSS

AH66 RSVD

AH69 GFX_VR_EN

AH71 GFX_VID[3]

AJ10

AJ2

AJ70

AK1

VAXG

CFG[5]

VSS

CFG[2]

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 7 of 37)

Pin # Pin Name

Buffer

Type

Dir

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

PWR

PWR

GND

GND

GND

GND

GND

GND

GND

GND

GND

REF

REF

GND

GND

GND

GND

GND

GND

CMOS

CMOS

REF

CMOS

GND

CMOS

O

O

I

I

AK41 VSS

AK42 VCAP1

AK44 VSS

AK46 VCAP1

AK48 VSS

AK50 VCAP0

AK51 VSS

AK53 VCAP0

AK55 VSS

AK57 VCAP0

AK59 VCAP2

AK60 VCAP2

AK62 VCAP2

AK64 VSS

AK12 VAXG

AK14 VAXG

AK15 VSS

AK17 VSS

AK19 VSS

AK21 VSS

AK23 VSS

AK24 VSS

AK26 VSS

AK28 VSS

AK30 VSS

AK32 VSS

AK33 VTT0

AK35 VTT0

AK37 VSS

AK39 VCAP1

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 8 of 37)

Pin #

AK2

AK4

AK7

AK8

Pin Name

CFG[3]

CFG[4]

BCLK

BCLK #

Buffer

Type

Dir

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

GND

GND

GND

REF

REF

GND

PWR

GND

PWR

PWR

PWR

PWR

GND

REF

REF

GND

GND

GND

GND

GND

GND

CMOS

CMOS

DIFF

CLK

DIFF

CLK

I

I

I

I

Datasheet

Processor Pin and Signal Information

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 9 of 37)

Pin # Pin Name

Buffer

Type

Dir

AL44

AL46

AL48

AL50

AL51

AL53

AL55

AL57

AL30

AL32

AL33

AL35

AL37

AL39

AL41

AL42

AL59

AL60

AL62

AL69

AL15

AL17

AL19

AL21

AL23

AL24

AL26

AL28

AK66 RSVD

AK69 RSVD

AK70 VSS

AK71 RSVD

AL1

AL4

AL12

AL14

VSS

CFG[0]

VTT0

VTT0

VTT0

VTT0

VAXG

VAXG

VAXG

VAXG

VAXG

VAXG

VSS

VCAP1

VSS

VCAP0

VSS

VCAP0

VSS

VCAP0

VAXG

VAXG

VSS

VSS

VSS

VCAP1

VSS

VCAP1

VTT0

VTT0

VSS

GFX_IMON

GND

I

O

GND

PWR

GND

PWR

REF

REF

GND

CMOS

GND

PWR

GND

PWR

GND

PWR

GND

PWR

REF

REF

REF

REF

REF

REF

GND

GND

GND

CMOS

REF

REF

REF

REF

REF

REF

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 10 of 37)

Pin #

AL71 GFX_DPRSLPVR

AM10 VTT0

AM2

AM5

CFG[1]

SM_DRAMPWROK

AM7

Pin Name

VCCPWRGOOD_1

Buffer

Type

Dir

CMOS

REF

CMOS

Async

CMOS

Async

CMOS

GND

GND

O

I

I

I

AN21 VAXG

AN23 VAXG

AN24 VAXG

AN26 VAXG

AN28 VAXG

AN30 VAXG

AN32 VAXG

AN33 VTT0

AN35 VTT0

AN37 VSS

AN39 VCAP1

AN41 VSS

AN42 VCAP1

AN44 VSS

AM8 VSS

AM64 VSS

AM66 RSVD

AM67 GFX_VID[5]

AM70 GFX_VID[6]

AN1

AN4

VTT_SELECT

VSS

AN5

AN7

VSS

RSVD_TP

AN9 VTT0

AN12 VTT0

AN14 VTT0

AN15 VTT0

AN17 VTT0

AN19 VAXG

CMOS

CMOS

CMOS

GND

GND

O

O

O

REF

REF

REF

REF

REF

REF

REF

GND

REF

REF

REF

REF

REF

REF

REF

REF

PWR

GND

PWR

GND

Datasheet 164

165

Processor Pin and Signal Information

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 11 of 37)

Pin # Pin Name

AR1

AR4

VSS

VSS

AR12 VTT0

AR14 VSS

AR15 VSS

AR17 VSS

AR19 VSS

AR21 VSS

AR23 VSS

AR24 VSS

AR26 VSS

AR28 VSS

AR30 VSS

AR32 VSS

AR33 VSS

AR35 VSS

AR37 VCAP1

AR39 VSS

AR41 VCAP1

AR42 VSS

AN46 VCAP1

AN48 VSS

AN50 VCAP0

AN51 VSS

AN53 VCAP0

AN55 VSS

AN57 VCAP0

AN59 VTT0

AN60 VTT0

AN62 VSS

AN69 RSVD

AN71 GFX_VID[4]

AP2 RSVD_TP

AP64 VSS

AP66 RSVD

AP70 VSS

Buffer

Type

Dir

PWR

GND

PWR

GND

PWR

GND

PWR

REF

REF

GND

CMOS

GND

O

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

REF

GND

GND

GND

GND

GND

PWR

GND

PWR

GND

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 12 of 37)

Pin # Pin Name

AR44 VCAP1

AR46 VSS

AR48 VCAP0

AR50 VSS

AR51 VCAP0

AR53 VSS

AR55 VCAP0

AR57 VSS

AR59 VTT0

AR60 VTT0

AR62 VSS

AR69 RSVD

AR71 RSVD

AT2 CFG[6]

AT6

AT8

SA_DQ[1]

SA_DQ[0]

AT10

AT64

AT67

AT70

VSS

VSS

RSVD

RSVD

AU1

AU2

RSVD_TP

RSVD

AU4 VSS

AU12 VTT0

AU14 VSS

AU15 VSS

AU17 VSS

AU19 VSS

AU21 VSS

AU23 VSS

AU24 VSS

AU26 VSS

AU28 VSS

AU30 VSS

AU32 VSS

AU33 VSS

Buffer

Type

Dir

PWR

GND

PWR

GND

PWR

GND

PWR

GND

REF

REF

GND

CMOS I

DDR3 I/O

DDR3 I/O

GND

GND

GND

GND

GND

GND

GND

GND

GND

REF

GND

GND

GND

GND

GND

GND

Datasheet

Processor Pin and Signal Information

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 13 of 37)

Pin # Pin Name

AU35 VSS

AU37 VCAP1

AU39 VSS

AU41 VCAP1

AU42 VSS

AU44 VCAP1

AU46 VSS

AU48 VCAP0

AU50 VSS

AU51 VCAP0

AU53 VSS

AU55 VCAP0

AU57 VSS

AU59 VTT0

AU60 VTT0

AU62 VSS

AU69 RSVD

AU70 VSS

AU71 RSVD

AV1 VSS

AV4

AV6

AV7

AV9

RSVD

SA_DQ[5]

SA_DQ[4]

VSS

AV64 PM_EXT_TS#[1]

AV66 PM_EXT_TS#[0]

AV69 RSVD

AV71 RSVD

AW12 VTT0

AW14 VTT0

AW15 VTT0_DDR

AW17 VTT0_DDR

AW19 VTT0_DDR

AW2 SB_DQ[1]

AW21 VTT0_DDR

AW23 VTT0_DDR

Buffer

Type

Dir

GND

PWR

GND

PWR

GND

REF

REF

GND

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

GND

DDR3 I/O

DDR3 I/O

GND

CMOS I/O

CMOS I/O

REF

REF

REF

REF

REF

DDR3 I/O

REF

REF

AW24 VTT0_DDR

AW26 VTT0_DDR

AW28 VTT0_DDR

AW30 VTT0_DDR

AW32 VTT0_DDR

AW33 VTT0

AW35 VTT0

AW37 VSS

AW39 VCAP1

AW41 VSS

AW42 VCAP1

AW44 VSS

AW46 VCAP1

AW48 VSS

AW50 VCAP0

AW51 VSS

AY1

AY4

AY5

AY7

AY8

AY10

AY12

AY14

AW53 VCAP0

AW55 VSS

AW57 VCAP0

AW59 VSS

AW60 VTT0

AW62 VSS

AW67 VSS

AW70 RSVD

AY15

AY17

AY19

AY21

VSS

VSS

VSS

VSS

SB_DQ[4]

VSS

SA_DQS#[0]

SA_DQS[0]

VSS

VTT0

VSS

VSS

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 14 of 37)

Pin # Pin Name

Buffer

Type

Dir

PWR

GND

PWR

GND

REF

GND

GND

DDR3 I/O

DDR3 I/O

GND

DDR3

DDR3

I/O

I/O

GND

REF

GND

GND

GND

GND

GND

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

REF

REF

REF

REF

REF

REF

REF

GND

Datasheet 166

167

Processor Pin and Signal Information

B16

B18

B19

B21

B9

B11

B12

B14

AY66

AY69

AY71

B7

AY51

AY53

AY55

AY57

AY59

AY60

AY62

AY64

AY37

AY39

AY41

AY42

AY44

AY46

AY48

AY50

AY23

AY24

AY26

AY28

AY30

AY32

AY33

AY35

VSS

VCAP0

VSS

VCAP0

VSS

VTT0

VSS

SA_DQ[62]

VSS

RSVD

VSS

RSVD

RSVD

PEG_RBIAS

PEG_ICOMPI

PEG_RX#[15]

PEG_RX[14]

PEG_RX[13]

PEG_RX[12]

PEG_RX[11]

VSS

VCAP1

VSS

VCAP1

VSS

VCAP1

VSS

VCAP0

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 15 of 37)

Pin # Pin Name

Buffer

Type

Dir

GND

PWR

GND

PWR

GND

PWR

GND

PWR

GND

GND

GND

GND

GND

GND

GND

GND

GND

PWR

GND

PWR

GND

REF

GND

DDR3 I/O

GND

GND

Analog

Analog

PCIe

PCIe

PCIe

PCIe

PCIe

I

I

I

I

I

I

I

B44

B46

B48

B49

B37

B39

B40

B42

B30

B32

B33

B35

B23

B25

B26

B28

B58

B60

B62

B63

B51

B53

B55

B56

VSS

VCC

VSS

VCC

VSS

VCC

VSS

CSC[1]/VID[4]

B65

BA2

VSS

SB_DQ[0]

BA70 VSS

BB1 VSS

BB4

BB5

BB7

BB9

SB_DM[0]

SA_DQ[2]

VSS

SA_DQ[3]

BB10 SA_DM[0]

BB12 VDDQ_CK

BB14 VDDQ_CK

BB15 VDDQ

PEG_RX#[10]

PEG_RX[9]

PEG_RX#[8]

PEG_RX[7]

PEG_TX[9]

PEG_TX#[10]

PEG_TX#[6]

PEG_TX#[7]

PEG_TX[4]

PEG_TX[3]

VSS

VCC

VSS

VCC

VSS

VCC

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 16 of 37)

Pin # Pin Name

Buffer

Type

Dir

GND

REF

GND

REF

GND

REF

GND

CMOS I/O

GND

DDR3 I/O

GND

GND

DDR3 O

DDR3 I/O

GND

DDR3 I/O

DDR3

REF

O

REF

REF

PCIe

PCIe

GND

REF

GND

REF

GND

REF

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

PCIe

O

O

O

O

O

O

I

I

I

I

Datasheet

Processor Pin and Signal Information

BB17 VDDQ

BB19 VDDQ

BB21 VDDQ

BB23 VDDQ

BB24 VDDQ

BB26 VDDQ

BB28 VDDQ

BB30 VDDQ

BB32 VDDQ

BB33 VDDQ

BB35 VDDQ

BB37 VCAP1

BB39 VSS

BB41 VCAP1

BB42 VSS

BB44 VCAP1

BB46 VSS

BB48 VCAP0

BB50 VSS

BB51 VCAP0

BB53 VSS

BB55 VCAP0

BB57 VSS

BB59 VTT0

BB60 VTT0

BB62 VSS

BB64 SA_DQ[58]

BB66 SA_DQ[59]

BB69 RSVD

BB71 VSS

BC2 SB_DQ[5]

BC67 SB_DQ[59]

BC70 SA_DQ[63]

BD1 SB_DQ[2]

BD4 SB_DQS[0]

BD14 VSS

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 17 of 37)

Pin # Pin Name

Buffer

Type

Dir

GND

PWR

GND

PWR

GND

PWR

GND

REF

REF

GND

DDR3 I/O

DDR3 I/O

REF

REF

REF

PWR

GND

PWR

GND

PWR

REF

REF

REF

REF

REF

REF

REF

REF

GND

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

GND

BD15 VDDQ

BD17 VDDQ

BD19 VDDQ

BD21 VDDQ

BD23 VDDQ

BD24 VDDQ

BD26 VDDQ

BD28 VDDQ

BD30 VDDQ

BD32 VDDQ

BD33 VDDQ

BD35 VDDQ

BD37 VCAP1

BD39 VSS

BD41 VCAP1

BD42 VSS

BD44 VCAP1

BD46 VSS

BD48 VCAP0

BD50 VSS

BD51 VCAP0

BD53 VSS

BD55 VCAP0

BD57 VSS

BE1

BE2

BE4

BE6

BD59 VTT0

BD60 VTT0

BD69 SB_DQ[63]

BD71 SB_DQ[62]

VSS

SB_DQS#[0]

SB_DQ[3]

SA_DQ[6]

BE8

BE9

SA_DQ[7]

VSS

BE11 SA_DQ[9]

BE62 SA_DQS#[7]

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 18 of 37)

Pin # Pin Name

Buffer

Type

Dir

PWR

GND

PWR

GND

PWR

GND

PWR

GND

REF

REF

DDR3

DDR3

I/O

I/O

GND

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3

GND

I/O

DDR3 I/O

DDR3 I/O

REF

REF

REF

REF

PWR

GND

PWR

GND

REF

REF

REF

REF

REF

REF

REF

REF

Datasheet 168

169

Processor Pin and Signal Information

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 19 of 37)

Pin # Pin Name

Buffer

Type

Dir

DDR3 I/O

GND

BF9

BF11

BF13

BF15

BF16

BF20

BF21

BF28

BE64 SA_DQS[7]

BE65 VSS

BE69 RSVD

BE70 VSS

BE71 RSVD

BF2 SB_DQ[6]

BF6

BF8

SA_DQ[13]

VSS

SA_DQ[12]

SA_DQ[8]

VSS

VDDQ

VDDQ

SA_CKE[0]

SA_BS[2]

SA_MA[9]

BF59

BF60

BF62

BF64

BF65

BF67

BF70

BG1

BF30

BF38

BF40

BF43

BF47

BF48

BF55

BF57

VSS

SA_WE#

SA_MA[13]

SA_ODT[0]

SA_DQ[34]

SA_DQ[35]

SA_DQ[48]

SA_DQ[52]

VTT0

VTT0

VSS

SA_DQ[57]

SA_DQ[61]

SB_DM[7]

SB_DQ[57]

SB_DQ[9]

BG4 SB_DQ[8]

BG15 SA_DQ[21]

BG17 SA_DQ[18]

BG24 SA_DQ[30]

GND

REF

REF

GND

DDR3 I/O

DDR3 I/O

DDR3 O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

GND

DDR3 I/O

DDR3 I/O

GND

REF

REF

DDR3

DDR3

DDR3

GND

DDR3

DDR3

DDR3

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

O

O

O

O

O

O

BG25 SA_DQ[31]

BG32 SA_MA[4]

BG34 SA_MA[3]

BG36 VSS

BG43 VDDQ

BG44 SA_DM[4]

BG51 VSS

BG53 SA_DM[5]

BG69 SB_DQS#[7]

BG71 SB_DQ[58]

BH2 SB_DQ[7]

BH13 SA_DQ[11]

BH15 VSS

BH17 SA_DQ[22]

BH20 VSS

BH21 SA_DQ[29]

BH24 VSS

BH25 SA_DQ[27]

BH28 VDDQ

BH30 SA_MA[11]

BH32 VDDQ

BH34 SA_MA[10]

BH36 SA_CK#[1]

BH38 SA_BS[1]

BH40 SA_CS#[0]

BH43 SA_DQ[37]

BH44 SA_DQS#[4]

BH47 VSS

BH48 SA_DQ[44]

BH51 SA_DQS[5]

BH53 SA_DQ[42]

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 20 of 37)

Pin # Pin Name

BH55 VSS

BH57 VSS

BH59 SA_DM[7]

BH70 VSS

Buffer

Type

Dir

REF

DDR3

REF

DDR3

O

DDR3

DDR3

DDR3 O

DDR3 I/O

O

O

O

DDR3 I/O

GND

DDR3 I/O

DDR3 I/O

DDR3+

C285

I/O

GND

GND

DDR3 I/O

GND

DDR3 I/O

DDR3 O

DDR3

GND

O

REF

DDR3

GND

DDR3

O

O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

GND

DDR3 I/O

GND

DDR3 I/O

GND

DDR3 I/O

Datasheet

Processor Pin and Signal Information

BJ21

BJ28

BJ30

BJ38

BJ40

BJ47

BJ48

BJ55

BJ1

BJ4

BJ5

BJ7

BJ9

BJ10

BJ12

BJ20

BJ57

BJ61

BJ63

BJ64

BJ66

BJ69

BJ71

BK2

SA_DQ[53]

SA_DQ[51]

SA_DQ[56]

VSS

SA_DQ[60]

SB_DQS[7]

SB_DQ[56]

SB_DQ[13]

BK5

BK7

SA_DQ[10]

SA_DQ[14]

BK9 SA_DQ[20]

BK10 VSS

BK15 SA_DQ[19]

BK17 SA_DQ[23]

BK24 SA_CKE[1]

BK25 SA_DQ[26]

BK32 SA_MA[6]

BK34 VSS

BK36 SA_CK[1]

BK43 SA_CAS#

VSS

SB_DQ[12]

SA_DQS[1]

SA_DQS#[1]

VSS

SA_DM[1]

SM_DRAMRST#

SA_DQ[28]

VSS

SA_MA[12]

SA_MA[7]

VDDQ

SA_DQ[32]

SA_CS#[1]

SA_DQ[45]

SA_DQ[43]

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 21 of 37)

Pin # Pin Name

Buffer

Type

Dir

DDR3 I/O

DDR3 I/O

DDR3 I/O

GND

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

GND

DDR3 I/O

DDR3 I/O

DDR3 O

DDR3 I/O

DDR3

GND

O

DDR3

DDR3

O

O

GND

DDR3 I/O

DDR3 I/O

DDR3 I/O

GND

DDR3 I/O

DDR3 O

DDR3 I/O

GND

DDR3

DDR3

REF

O

O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

BK44 SA_DQS[4]

BK51 SA_DQS#[5]

BK53 VSS

BK60 VSS

BK61 SA_DQ[55]

BK63 VSS

BK64 SA_DQ[54]

BK67 SB_DQ[61]

BK70 SB_DQ[60]

BL1 VSS

BL4

BL13

SB_DM[1]

SA_DQS[2]

BL20

BL21

BL28

BL30

VSS

SA_DQS#[3]

VSS

VDDQ

BL38

BL40

BL47

BL48

BL55

BL57

BL69

BL71

SA_RAS#

VSS

SA_ODT[1]

VSS

VSS

VSS

SB_DQ[55]

VSS

BM3 SB_DQS#[1]

BM15 SA_DM[2]

BM17 VSS

BM24 VSS

BM25 VDDQ

BM32 VSS

BM34 SA_CK[0]

BM43 SA_DQ[33]

BM44 VSS

BM51 VSS

BM53 SA_DQ[46]

BM60 SA_DQS[6]

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 22 of 37)

Pin # Pin Name

Buffer

Type

Dir

DDR3

DDR3

GND

GND

DDR3

DDR3

DDR3

GND

I/O

DDR3 I/O

DDR3 O

GND

GND

REF

GND

O

I/O

I/O

I/O

GND

REF

DDR3

GND

DDR3

GND

GND

GND

DDR3

DDR3

GND

GND

I/O

I/O

DDR3

GND

DDR3

DDR3

I/O

I/O

I/O

I/O DDR3

GND

DDR3

DDR3

O

I/O

GND

DDR3 I/O

O

O

Datasheet 170

171

Processor Pin and Signal Information

BM70 VSS

BN1 VSS

BN4

BN6

SB_DQS[1]

VSS

BN8

BN9

SA_DQ[15]

SA_DQ[17]

BN11 SA_DQ[16]

BN13 SA_DQS#[2]

BN17 SA_DQ[25]

BN20 SA_DQ[24]

BN21 SA_DQS[3]

BN24 SA_DM[3]

BN25 SA_MA[15]

BN28 SA_MA[14]

BN30 SA_MA[8]

BN32 SA_MA[5]

BN38 VDDQ

BN40 SA_DQ[36]

BN44 SA_DQ[38]

BN47 SA_DQ[39]

BN48 SA_DQ[40]

BN51 SA_DQ[41]

BN55 SA_DQ[47]

BN57 SA_DQ[49]

BN62 SA_DM[6]

BN64 VSS

BN65 SA_DQ[50]

BN68 SB_DQ[54]

BN71 VSS

BP12 SB_DQ[21]

BP15 SB_DQ[24]

BP19 SB_DQ[28]

BP22 SB_DM[3]

BP26 SB_MA[7]

BP30 SB_MA[1]

BP33 SA_MA[1]

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 23 of 37)

Pin # Pin Name

Buffer

Type

Dir

REF

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3

GND

O

DDR3 I/O

DDR3 I/O

GND

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3

DDR3

O

O

DDR3

DDR3

O

O

GND

GND

DDR3 I/O

GND

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 O

DDR3

DDR3

DDR3

DDR3

O

O

O

O

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 24 of 37)

Pin # Pin Name

BP35 SA_CK#[0]

BP39 SM_RCOMP[1]

BP42 VSS

BP46 SB_CS#[0]

BP49 SB_DQ[35]

BP53 SB_DQ[40]

BP56 SB_DQ[44]

BP58 SA_DQS#[6]

BP60 SB_DQ[49]

BR1 DC_TEST_BR1

BR3

BR5

VSS

RSVD_TP

BR6

BR8

SB_DQ[10]

SB_DQ[11]

BR10 SB_DQ[16]

BR62 SB_DQ[52]

BR64 SB_DQ[51]

BR66 SB_DQ[50]

BR68 VSS

BR69 VSS

BR71 DC_TEST_BR71

BT1 DC_TEST_BT1

BT3

BT5

DC_TEST_BT3

RSVD_NCTF

BT12 SB_DQ[17]

BT13 SB_DM[2]

BT15 SB_DQ[18]

BT17 SB_DQS[3]

BT19 SB_DQS#[3]

BT20 SB_DQ[31]

BT22 SB_DQ[27]

BT24 SB_CKE[1]

BT26 SB_CKE[0]

BT27 SB_MA[9]

BT29 SB_MA[12]

BT31 SB_MA[6]

Buffer

Type

Dir

DDR3

Analog

GND

DDR3

O

O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

GND

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

GND

GND

DDR3 I/O

DDR3 O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 O

DDR3

DDR3

DDR3

DDR3

O

O

O

O

Datasheet

Processor Pin and Signal Information

BT33 SB_MA[5]

BT34 SB_MA[0]

BT36 SA_MA[0]

BT38 SA_BS[0]

BT40 SB_RAS#

BT41 SB_WE#

BT43 SB_CS#[1]

BT45 SB_MA[13]

BT47 SB_DQ[36]

BT48 SB_DQ[32]

BT50 SB_DQS[4]

BT52 SB_DQS#[4]

BT54 SB_DQ[39]

BT55 SB_DQ[45]

BT57 SB_DQ[43]

BT59 SB_DQ[42]

BT61 SB_DQ[53]

BT68 VSS

BT69 DC_TEST_BT69

BT71 DC_TEST_BT71

BU7

BU9

VSS

SB_DQ[14]

BU11 VSS

BU12 SB_DQS#[2]

BU14 VSS

BU16 SB_DQ[23]

BU18 VSS

BU19 SB_DQ[25]

BU21 VSS

BU23 SB_MA[15]

BU25 VSS

BU26 SB_MA[11]

BU28 VDDQ

BU30 SB_MA[3]

BU32 VSS

BU33 SB_CK[0]

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 25 of 37)

Pin # Pin Name

Buffer

Type

Dir

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

GND

O

O

O

O

O

O

O

O

GND

DDR3

GND

DDR3

REF

DDR3

GND

DDR3

GND

DDR3 I/O

GND

DDR3 I/O

GND

DDR3 I/O

GND

DDR3 I/O

O

O

O

O

BU35 VDDQ

BU37 VSS

BU39 SB_CK#[1]

BU40 VDDQ

BU42 SB_MA[10]

BU44 VSS

BU46 SB_CAS#

BU48 VSS

BU49 SB_ODT[1]

BU51 VSS

BU53 SB_DQ[41]

BU55 VSS

BU56 SB_DQS[5]

BU58 VSS

BU60 SB_DQ[46]

BU62 VSS

BU63 SB_DQS#[6]

BU65 SB_DM[6]

BV1

BV3

DC_TEST_BV1

DC_TEST_BV3

BV5

BV6

DC_TEST_BV5

RSVD_NCTF

BV8 RSVD_NCTF

BV10 SB_DQ[15]

BV12 SB_DQ[20]

BV13 SB_DQS[2]

BV15 SB_DQ[19]

BV17 SB_DQ[22]

BV19 SB_DQ[29]

BV20 SB_DQ[30]

BV22 SB_DQ[26]

BV24 SB_BS[2]

BV26 SB_MA[14]

BV27 SB_MA[8]

BV29 SB_MA[2]

BV31 SB_MA[4]

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 26 of 37)

Pin # Pin Name

Buffer

Type

Dir

DDR3

GND

DDR3

GND

DDR3

GND

DDR3

GND

DDR3

DDR3

REF

GND

DDR3

REF

DDR3

GND

DDR3

GND

O

O

O

O

I/O

I/O

I/O

I/O

O

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3

DDR3

DDR3

DDR3

I/O

I/O

I/O

I/O

I/O

O

O

O

O

O

Datasheet 172

173

Processor Pin and Signal Information

BV33 SM_RCOMP[0]

BV34 SB_CK#[0]

BV36 SA_MA[2]

BV38 SB_CK[1]

BV40 SM_RCOMP[2]

BV41 SB_BS[1]

BV43 SB_BS[0]

BV45 SB_ODT[0]

BV47 SB_DM[4]

BV48 SB_DQ[33]

BV50 SB_DQ[34]

BV52 SB_DQ[37]

BV54 SB_DQ[38]

BV55 SB_DQS#[5]

BV57 SB_DM[5]

BV59 SB_DQ[47]

C5

C68

C69

C71

D6

D8

D10

D12

BV61 SB_DQ[48]

BV62 SB_DQS[6]

BV64 VSS

BV66 VSS

BV68 DC_TEST_BV68

BV69 DC_TEST_BV69

BV71 DC_TEST_BV71

C3 DC_TEST_C3

D13

D15

D17

D19

RSVD_NCTF

VSS

DC_TEST_C69

DC_TEST_C71

VSS

RSVD

VSS

PEG_RCOMPO

VSS

PEG_RX[15]

VSS

PEG_RX#[13]

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 27 of 37)

Pin # Pin Name

Buffer

Type

Dir

Analog

DDR3

DDR3

DDR3

Analog

DDR3

DDR3

DDR3

DDR3 O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 I/O

DDR3 O

DDR3 I/O

DDR3 I/O

DDR3 I/O

GND

GND

O

O

I

O

O

O

I

O

GND

GND

GND

Analog

GND

PCIe

GND

PCIe

I

I

I

E30

E33

E37

E42

E3

E5

E12

E16

D62

D64

D66

E1

D48

D50

D52

D54

D55

D57

D59

D61

D34

D36

D38

D40

D41

D43

D45

D47

D20

D22

D24

D26

D27

D29

D31

D33

VCC

VCC

VCC

VCC

VCC

VCC

VCC

VID[1]

VID[2]

CSC[2]/VID[5]

VID[6]

DC_TEST_E1

RSVD_NCTF

VSS

VSS

VSS

VSS

VSS

VSS

VCC

VSS

PEG_RX#[11]

VSS

PEG_RX#[9]

VSS

PEG_RX#[7]

VSS

PEG_TX[10]

VSS

PEG_TX[7]

VSS

PEG_TX#[3]

VSS

VCC

VCC

VCC

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 28 of 37)

Pin # Pin Name

Buffer

Type

Dir

GND

PCIe

GND

PCIe

GND

REF

REF

REF

GND

PCIe

GND

PCIe

GND

PCIe

GND

PCIe

I

I

I

O

O

O

REF

REF

REF

REF

REF

REF

REF

CMOS O

CMOS O

CMOS I/O

CMOS O

GND

GND

GND

GND

GND

GND

REF

Datasheet

Processor Pin and Signal Information

F71

G3

G13

G15

G17

G20

G21

G24

G25

G28

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 29 of 37)

Pin #

F10

F20

F21

F28

F1

F4

F7

F9

E60

E68

E69

E71

E46

E50

E53

E57

F61

F63

F64

F66

F68

F40

F47

F48

F55

Pin Name

VCC

VCC

VCC

VCC

VCC

VSS

VSS

DC_TEST_E71

RSVD_NCTF

VSS

DMI_RX#[0]

DMI_RX[0]

DMI_TX#[3]

VSS

PEG_TX[14]

VSS

PEG_RX[0]

VSS

VSS

VCC

VSS

VSS_SENSE

VCC_SENSE

PROC_DPRSLPVR

PSI#

Buffer

Type

Dir

REF

REF

REF

REF

REF

GND

GND

I

I

O

O

I

VSS

RSTIN#

DMI_TX[2]

VSS

DMI_TX[0]

VSS

PEG_TX#[14]

VSS

PEG_RX[5]

PEG_RX#[4]

PCIe

GND

GND

REF

GND

Analog

Analog

CMOS

Async

CMOS

GND

DMI

DMI

DMI

GND

PCIe

GND

GND

CMOS

DMI

GND

DMI

GND

PCIe

GND

PCIe

PCIe

I

O

I

I

O

O

O

O

O

O

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 30 of 37)

Pin #

J11

J13

J2

J4

H51

H53

H60

H71

J6

J8

H17

H24

H25

H32

H34

H36

H43

H44

G48

G51

G53

G55

G57

G60

G70

H1

H15

G30

G32

G34

G38

G40

G43

G44

G47

Pin Name

DMI_TX#[0]

PEG_RX#[6]

PEG_RX#[5]

PEG_TX[5]

PEG_RX#[2]

VSS

VSS

VCC

VCC

VSS

VCC

VSS

DMI_TX[3]

DMI_TX#[2]

DMI_RX[3]

DMI_RX#[3]

DMI_RX[1]

DMI_RX#[1]

VSS

PEG_TX#[5]

PEG_RX[2]

PEG_RX#[1]

PEG_RX#[0]

VSS

VCC

VSS

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VSS

VTTPWRGOOD

Buffer

Type

Dir

REF

GND

REF

GND

DMI

DMI

DMI

DMI

DMI

DMI

DMI

PCIe

PCIe

PCIe

PCIe

GND

GND

REF

GND

REF

GND

REF

GND

REF

GND

GND

Async

CMOS

GND

PCIe

PCIe

PCIe

PCIe

GND

REF

GND

I

O

I

I

I

I

O

O

I

I

I

I

O

O

I

I

Datasheet 174

175

Processor Pin and Signal Information

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 31 of 37)

Pin #

J9

J20

J21

K34

K36

K43

K44

K17

K24

K25

K32

K51

K53

K1

K4

K6

K8

K9

K11

K15

J62

J64

J65

J67

J69

J70

J47

J48

J55

J57

J28

J30

J38

J40

Pin Name

VSS

PEG_TX#[15]

PEG_CLK#

FDI_TX[0]

VSS

VSS

DMI_RX#[2]

DMI_RX[2]

VSS

DMI_TX#[1]

VSS

PEG_RX[6]

VSS

VSS

VSS

VSS

VSS

VCC

VCC

VSS

PEG_RX[4]

PEG_TX[8]

PEG_RX[1]

VSS

VSS

VSS

VCC

VSS

BPM#[2]

BPM#[5]

VSS

BPM#[1]

BPM#[0]

BCLK_ITP #

Buffer

Type

Dir

GND

GND

GND

GND

GND

REF

REF

GND

GND

GND

DMI

DMI

GND

DMI

GND

PCIe

GND

GND

REF

GND

GTL

GTL

GND

GTL

GTL

DIFF

CLK

FDI

GND

PCIe

DIFF

CLK

PCIe

PCIe

PCIe

GND

O

I

I/O

I/O

O

I

I

O

I

I

O

I

I/O

I/O

O

M15

M17

M24

M25

M32

M34

M36

M42

M44

M51

M53

M60

M69

L57

L70

M1

M4

L40

L47

L48

L55

L2

L13

L20

L21

L28

L30

L38

DMI_TX[1]

PM_SYNC

PEG_TX#[13]

PEG_TX[12]

PEG_TX#[2]

PEG_RX[3]

VSS

VSS

VCC

VCC

VSS

VCC

BPM#[7]

FDI_TX#[0]

VSS

PEG_TX[15]

PEG_CLK

PEG_TX#[11]

PEG_TX#[8]

PEG_TX#[1]

PEG_TX[0]

VSS

VSS

VCC

VSS

VSS

VSS

FDI_TX#[2]

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 32 of 37)

Pin #

K60

K62

K64

K65

K69

K71

Pin Name

VCC

BPM#[4]

VSS

BPM#[3]

BPM#[6]

BCLK_ITP

Buffer

Type

Dir

PCIe

PCIe

PCIe

PCIe

GND

GND

REF

REF

GND

REF

GND

GND

GND

FDI

DMI

CMOS

GND

REF

GTL

GND

PCIe

Diff CLK

PCIe

PCIe

PCIe

PCIe

GND

REF

GTL

GND

GTL

GTL

DIFF

CLK

FDI

I/O

I/O

I/O

O

O

I/O

O

O

O

O

I

O

O

I

O

O

O

O

I

Datasheet

Processor Pin and Signal Information

N38

N40

N42

N44

N46

N48

N50

N51

N19

N21

N24

N26

N28

N30

N32

N53

N55

N57

N61

N63

N65

N67

N2

N5

N7

N9

N10

N13

N15

N17

N70

P1

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 33 of 37)

Pin # Pin Name

Buffer

Type

Dir

M71 PROC_DETECT

GND

GTL

GND

CMOS

Async

GTL

Async

CMOS

FDI

REF

REF

GND

REF

GND

REF

GND

REF

GND

PCIe

PCIe

PCIe

GND

PCIe

PCIe

PCIe

FDI

FDI

FDI

FDI

FDI

Analog

GND

Async

GTL

O

Async I/O

O

O

O

O

O

O

O

O

O

O

O

O

I/O

I

I/O

O

O

FDI_TX[2]

FDI_TX[1]

FDI_TX#[1]

FDI_TX[4]

FDI_TX#[4]

VTT_SENSE

VSS

THERMTRIP#

PECI

VSS

PEG_TX[13]

PEG_TX#[12]

PEG_TX[11]

VSS

PEG_TX[2]

PEG_TX[1]

PEG_TX#[0]

VCC

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

CATERR#

VSS

TMS

PROCHOT#

RESET_OBS#

FDI_TX#[3]

R46

R48

R50

R51

R39

R41

R42

R44

R53

R55

R57

R59

R32

R33

R35

R37

R24

R26

R28

R30

R17

R19

R21

R23

R8

R12

R14

R15

P71

R2

R5

R7

P4

P34

P60

P69

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 34 of 37)

Pin # Pin Name

Buffer

Type

Dir

REF

REF

GND

REF

GND

REF

GND

REF

REF

REF

REF

REF

REF

REF

REF

REF

GND

REF

GND

PWR

FDI

Analog

GND

REF

REF

REF

REF

REF

GND

PCIe

REF

CMOS

CMOS

FDI

GND

FDI

I

I

I

O

O

O

O

VCCPLL

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VCCPLL

VSS

VCC

VSS

VCAP2

VSS

PEG_RX#[3]

VCC

TRST#

TDI_M

FDI_TX[3]

VSS

FDI_TX#[5]

FDI_TX[5]

VSS_SENSE_VTT

VSS

VTT1

VTT1

VTT1

VTT1

VTT0

Datasheet 176

177

Processor Pin and Signal Information

U24

U26

U28

U30

U32

U33

U35

U37

U4

U12

U14

U15

U17

U19

U21

U23

U39

U41

U42

U44

T69

T70

T71

U1

U6

U7

U9

T67

R70

T1

T2

T4

R60

R62

R64

R66

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 35 of 37)

Pin # Pin Name

Buffer

Type

Dir

PWR

GND

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VCCPLL

VSS

VTT1

VTT1

VTT1

VTT1

VTT1

VTT1

VTT0

VSS

VCC

VSS

VCC

VCAP2

VSS

RSVD

RSVD

VSS

VSS

RSVD

RSVD

FDI_TX[6]

FDI_TX#[6]

VSS

TCK

TDI

TDO_M

TDO

RSVD

GND

GND

FDI

FDI

GND

CMOS

CMOS

CMOS

CMOS

I

I

O

O

O

O

REF

REF

REF

REF

REF

REF

REF

REF

GND

REF

REF

REF

REF

REF

REF

REF

GND

REF

GND

REF

W19

W21

W23

W24

W26

W28

W30

W32

W33

W35

W6

W8

W10

W12

W14

W15

W17

V2

V70

W1

W4

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 36 of 37)

Pin #

U46

U48

U50

U51

U53

U55

U57

U59

U60

U62

U64

U69

U71

Pin Name

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCAP2

VCAP2

VSS

VSS

PREQ#

PRDY#

Buffer

Type

Dir

GND

REF

GND

REF

GND

REF

GND

PWR

PWR

GND

GND

Async

GTL

Async

GTL

I

O

RSVD

VSS

VSS

DPLL_REF_SSCLK# I

VTT1

VTT1

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VTT0

VSS

FDI_TX#[7]

FDI_TX[7]

VTT1

VTT1

VTT1

VTT1

REF

REF

REF

REF

FDI

FDI

REF

REF

GND

GND

DIFF

CLK

GND

REF

REF

REF

REF

REF

REF

REF

REF

O

O

Datasheet

178

Table 8-51.BGA1288 Processor Ball

List by Ball Number

(Sheet 37 of 37)

Pin #

W51

W53

W55

W57

W59

W60

W62

W64

W37

W39

W41

W42

W44

W46

W48

W50

W66

W69

W71

Y2

Pin Name

VCCPLL

VCCPLL

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCAP2

VCAP2

VSS

VCAP0_VSS_SENSE

VCAP0_SENSE

VSS

DBR#

DPLL_REF_SSCLK

Buffer

Type

Dir

REF

GND

REF

GND

PWR

PWR

GND

REF

REF

REF

GND

REF

GND

REF

GND

GND

O

I

Y67

Y70

VCCPWRGOOD_0

TAPPWRGOOD

DIFF

CLK

Async

CMOS

Async

CMOS

I

O

Processor Pin and Signal Information

Datasheet

Processor Pin and Signal Information

8.2

Package Mechanical Information

Figure 8-25. rPGA Mechanical Package (Sheet 1 of 2)

Datasheet 179

Figure 8-26.rPGA Mechanical Package (Sheet 2 of 2)

Processor Pin and Signal Information

180 Datasheet

Processor Pin and Signal Information

Figure 8-27.BGA Mechanical Package (Sheet 2 of 2)

Datasheet

§

181