PIC16F818/819 Data Sheet

PIC16F818/819 Data Sheet
PIC16F818/819
Data Sheet
18/20-Pin
Enhanced FLASH Microcontrollers
with nanoWatt Technology
 2002 Microchip Technology Inc.
Preliminary
DS39598C
Note the following details of the code protection feature on Microchip devices:
•
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•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
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•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
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Information contained in this publication regarding device
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Trademarks
The Microchip name and logo, the Microchip logo, KEELOQ,
MPLAB, PIC, PICmicro, PICSTART and PRO MATE are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL
and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
dsPIC, dsPICDEM.net, ECONOMONITOR, FanSense,
FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP,
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MPLINK, MPSIM, PICC, PICDEM, PICDEM.net, rfPIC, Select
Mode and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
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All other trademarks mentioned herein are property of their
respective companies.
© 2002, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
DS39598C - page ii
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
18/20-Pin Enhanced FLASH Microcontrollers
with nanoWatt Technology
Low Power Features:
Pin Diagram
• Power Managed modes:
- Primary RUN XT, RC oscillator, 87 µA,
1 MHz, 2V
- INTRC
7 µA, 31.25 kHz, 2V
- SLEEP
0.2 µA, 2V
• Timer1 oscillator 1.3 µA, 32 kHz, 2V
• Watchdog Timer 0.7 µA, 2V
• Wide operating voltage range:
- Industrial: 2.0V to 5.5V
RA2/AN2/VREFRA3/AN3/VREF+
RA4/AN4/T0CKI
RA5/MCLR/VPP
Vss
RB0/INT
RB1/SDI/SDA
RB2/SDO/CCP1
RB3/CCP1/PGM
Oscillators:
•
•
•
16 I/O pins with individual direction control
High sink/source current: 25 mA
Timer0: 8-bit timer/counter with 8-bit prescaler
Timer1: 16-bit timer/counter with prescaler,
can be incremented during SLEEP via external
crystal/clock
Timer2: 8-bit timer/counter with 8-bit period
register, prescaler and postscaler
Capture, Compare, PWM (CCP) module:
- Capture is 16-bit, max. resolution is 12.5 ns
- Compare is 16-bit, max. resolution is 200 ns
- PWM max. resolution is 10-bit
10-bit, 5-channel Analog-to-Digital converter
Synchronous Serial Port (SSP) with
SPI™ (Master/Slave) and I2C™ (Slave)
Program Memory
Data Memory
Device
FLASH
(bytes)
# Single Word
Instructions
SRAM
(bytes)
PIC16F818
1792
1024
128
128
PIC16F819
3584
2048
256
256
 2002 Microchip Technology Inc.
RA1/AN1
RA0/AN0
RA7/OSC1/CLKI
RA6/OSC2/CLKO
VDD
RB7/T1OSI/PGD
RB6/T1OSO/T1CKI/PGC
RB5/SS
RB4/SCK/SCL
• 100,000 erase/write cycles Enhanced FLASH
program memory typical
• 1,000,000 typical erase/write cycles EEPROM
data memory typical
• EEPROM Data Retention: > 40 years
• In-Circuit Serial ProgrammingTM (ICSPTM) via two pins
• Processor read/write access to program memory
• Low Voltage Programming
• In-Circuit Debugging via two pins
Peripheral Features:
•
18
17
16
15
14
13
12
11
10
Special Microcontroller Features:
• Three Crystal modes:
- LP, XT, HS
up to 20 MHz
• Two External RC modes
• One External Clock mode:
- ECIO
up to 20 MHz
• Internal oscillator block:
- 8 user selectable frequencies: 31 kHz, 125 kHz,
250 kHz, 500 kHz, 1 MHz, 2 MHz, 4 MHz, 8 MHz
•
•
•
•
•1
2
3
4
5
6
7
8
9
PIC16F818/819
18-pin DIP, SOIC
SSP
10-bit
A/D (ch)
CCP
(PWM)
SPI
Slave
I2C
16
5
1
Y
Y
2/1
16
5
1
Y
Y
2/1
EEPROM I/O Pins
(bytes)
Preliminary
Timers
8/16-bit
DS39598C-page 1
PIC16F818/819
Pin Diagrams
DS39598C-page 2
RA1/AN1
RA0/AN0
NC
23
22
NC
25
24
RA3/AN3/VREF+
RA2/AN2/VREF-
RA4/AN4/T0CKI
28
28-pin QFN
•1
2
3
4
5
6
7
8
9
10
RA2/AN2/VREFRA3/AN3/VREF+
RA4/AN4/T0CKI
RA5/MCLR/VPP
VSS
VSS
RB0/INT
RB1/SDI/SDA
RB2/SDO/CCP1
RB3/CCP1/PGM
RA1/AN1
RA0/AN0
RA7/OSC1/CLKI
RA6/OSC2/CLKO
VDD
RB7/T1OSI/PGD
RB6/T1OSO/T1CKI/PGC
RB5/SS
RB4/SCK/SCL
26
18
17
16
15
14
13
12
11
10
27
20
19
18
17
16
15
14
13
12
11
RA1/AN1
RA0/AN0
RA7/OSC1/CLKI
RA6/OSC2/CLKO
VDD
VDD
RB7/T1OSI/PGD
RB6/T1OSO/T1CKI/PGC
RB5/SS
RB4/SCK/SCL
RA5/MCLR/VPP
1
21
RA7/OSC1/CLKI
NC
2
20
RA6/OSC2/CLKO
VSS
3
19
VDD
NC
4
18
NC
VSS
5
17
VDD
NC
6
16
RB7/T1OSI/PGD
RB0/INT
7
15
RB6/T1OSO/T1CKI/PGC
12
13
14
RB5/SS
NC
10
RB3/CCP1/PGM
11
9
NC
8
RB1/SDI/SDA
RB2/SDO/CCP1
PIC16F818/819
RB4/SCK/SCL
•1
2
3
4
5
6
7
8
9
PIC16F818/819
RA2/AN2/VREFRA3/AN3/VREF+
RA4/AN4/T0CKI
RA5/MCLR/VPP
Vss
RB0/INT
RB1/SDI/SDA
RB2/SDO/CCP1
RB3/CCP1/PGM
PIC16F818/819
20-pin SSOP
18-pin PDIP, SOIC
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 5
2.0 Memory Organization ................................................................................................................................................................... 9
3.0 Data EEPROM and FLASH Program Memory........................................................................................................................... 25
4.0 Oscillator Configurations ............................................................................................................................................................ 33
5.0 I/O Ports ..................................................................................................................................................................................... 39
6.0 Timer0 Module ........................................................................................................................................................................... 53
7.0 Timer1 Module ........................................................................................................................................................................... 57
8.0 Timer2 Module ........................................................................................................................................................................... 63
9.0 Capture/Compare/PWM (CCP) Module ..................................................................................................................................... 65
10.0 Synchronous Serial Port (SSP) Module ..................................................................................................................................... 71
11.0 Analog-to-Digital Converter (A/D) Module.................................................................................................................................. 81
12.0 Special Features of the CPU...................................................................................................................................................... 89
13.0 Instruction Set Summary .......................................................................................................................................................... 103
14.0 Development Support............................................................................................................................................................... 111
15.0 Electrical Characteristics .......................................................................................................................................................... 117
16.0 DC and AC Characteristics Graphs and Tables....................................................................................................................... 143
17.0 Packaging Information.............................................................................................................................................................. 145
Appendix A: Revision History ............................................................................................................................................................ 151
Appendix B: Device Differences ........................................................................................................................................................ 151
Index .................................................................................................................................................................................................. 153
On-Line Support................................................................................................................................................................................. 159
Systems Information and Upgrade Hot Line ...................................................................................................................................... 159
Reader Response .............................................................................................................................................................................. 160
PIC16F818/819 Product Identification System .................................................................................................................................. 161
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 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 3
PIC16F818/819
NOTES:
DS39598C-page 4
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
1.0
DEVICE OVERVIEW
TABLE 1-1:
This document contains device specific information for
the operation of the PIC16F818/819 devices.
Additional information may be found in the PICmicroTM
Mid-Range MCU Reference Manual (DS33023), which
may be downloaded from the Microchip web site. The
Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the
device architecture and operation of the peripheral
modules.
The PIC16F818/819 belongs to the Mid-Range family
of the PICmicro® devices. The devices differ from each
other in the amount of FLASH program memory, Data
memory, and Data EEPROM (see Table 1-1). A block
diagram of the devices is shown in Figure 1-1. These
devices contain features that are new to the PIC16
product line:
• Internal RC oscillator with eight selectable
frequencies, including 31.25 kHz, 125 kHz,
250 kHz, 500 kHz, 1 MHz, 2 MHz, 4 MHz, and
8 MHz. The INTRC can be configured as the system clock via the configuration bits. Refer to
Section 4.5 and Section 12.1 for further details.
• The Timer1 module current consumption has
been greatly reduced from 20 µA (previous PIC16
devices) to 1.3 µA typical (32 kHz at 2V), which is
ideal for real-time clock applications. Refer to
Section 6.0 for further details.
• The amount of oscillator selections has increased.
The RC and INTRC modes can be selected with
an I/O pin configured as an I/O or a clock output
(FOSC/4). An external clock can be configured
with an I/O pin. Refer to Section 4.0 for further
details.
 2002 Microchip Technology Inc.
AVAILABLE MEMORY IN
PIC16F818/819 DEVICES
Device
Program
FLASH
Data
Memory
Data
EEPROM
PIC16F818
1K x 14
128 x 8
128 x 8
PIC16F819
2K x14
256 x 8
256 x 8
There are 16 I/O pins that are user configurable on a
pin-to-pin basis. Some pins are multiplexed with other
device functions. These functions include:
• External Interrupt
• Change on PORTB Interrupt
• Timer0 Clock Input
• Low Power Timer1 Clock/Oscillator
• Capture/Compare/PWM
• 10-bit, 5-channel Analog-to-Digital Converter
• SPI/I2C
• MCLR (RA5) can be configured as an Input
Table 1-2 details the pinout of the device with
descriptions and details for each pin.
Preliminary
DS39598C-page 5
PIC16F818/819
FIGURE 1-1:
PIC16F818/819 BLOCK DIAGRAM
13
FLASH
Program
Memory
1K/2K x 14
Program
Bus
RAM Addr(1)
PORTB
9
Addr MUX
Instruction reg
7
Direct Addr
8
Indirect
Addr
FSR reg
STATUS reg
8
3
Power-up
Timer
Instruction
Decode &
Control
Oscillator
Start-up Timer
Timing
Generation
Watchdog
Timer
Brown-out
Reset
MCLR
RB0/INT
RB1/SDI/SDA
RB2/SDO/CCP1
RB3/CCP1/PGM
RB4/SCK/SCL
RB5/SS
RB6/T1OSO/T1CKI/PGC
RB7/T1OSI/PGD
MUX
8
W reg
VDD, VSS
Timer0
Timer1
Timer2
10-bit, 5-channel
A/D
Synchronous
Serial Port
CCP1
Note 1:
RA0/AN0
RA1/AN1
RA2/AN2/VREFRA3/AN3/VREF+
RA4/AN4/T0CKI
RA5/MCLR/VPP
RA6/OSC2/CLKO
RA7/OSC1/CLKI
ALU
Power-on
Reset
RA7/OSC1/CLKI
RA6/OSC2/CLKO
PORTA
RAM
File
Registers
128/256 x 8
8-Level Stack
(13-bit)
14
8
Data Bus
Program Counter
Data EE
128/256 Bytes
Higher order bits are from the STATUS register.
DS39598C-page 6
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
TABLE 1-2:
Pin Name
PIC16F818/819 PINOUT DESCRIPTIONS
PDIP/
SSOP
SOIC
Pin#
Pin#
QFN
Pin#
I/O/P
Type
Buffer
Type
Description
PORTA is a bi-directional I/O port.
RA0/AN0
RA0
AN0
17
RA1/AN1
RA1
AN1
18
RA2/AN2/VREFRA2
AN2
VREF-
1
RA3/AN3/VREF+
RA3
AN3
VREF+
2
RA4/AN4/T0CKI
RA4
AN4
T0CKI
3
RA5/MCLR/VPP
RA5
MCLR
4
19
20
1
2
3
4
23
15
17
16
18
Bi-directional I/O pin.
Analog input channel 0.
I/O
I
TTL
Analog
Bi-directional I/O pin.
Analog input channel 1.
I/O
I
I
TTL
Analog
Analog
Bi-directional I/O pin.
Analog input channel 2.
A/D reference voltage (Low) input.
I/O
I
I
TTL
Analog
Analog
Bi-directional I/O pin.
Analog input channel 3.
A/D reference voltage (High) input.
I/O
I
I
ST
Analog
ST
Bi-directional I/O pin.
Analog input channel 4.
Clock input to the TMR0 timer/counter.
I
I
ST
ST
P
–
I/O
O
ST
–
O
–
I/O
I
I
ST
ST/CMOS(3)
–
26
27
28
1
Input pin.
Master Clear (Reset). Input/programming voltage
input. This pin is an active low RESET to the device.
Programming threshold voltage.
20
CLKO
RA7/OSC1/CLKI
RA7
OSC1
CLKI
TTL
Analog
24
VPP
RA6/OSC2/CLKO
RA6
OSC2
I/O
I
Bi-directional I/O pin.
Oscillator crystal output. Connects to crystal or
resonator in Crystal Oscillator mode.
In RC mode, this pin outputs CLKO signal, which has
1/4 the frequency of OSC1, and denotes the
instruction cycle rate.
21
Bi-directional I/O pin.
Oscillator crystal input.
External clock source input.
Legend: I = Input
O
= Output
I/O = Input/Output
P = Power
– = Not used
TTL = TTL Input
ST = Schmitt Trigger Input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 7
PIC16F818/819
TABLE 1-2:
PIC16F818/819 PINOUT DESCRIPTIONS (CONTINUED)
Pin Name
PDIP/
SSOP
SOIC
Pin#
Pin#
QFN
Pin#
I/O/P
Type
Buffer
Type
Description
PORTB is a bi-directional I/O port. PORTB can be
software programmed for internal weak pull-up on all
inputs.
RB0/INT
RB0
INT
6
RB1/SDI/SDA
RB1
SDI
SDA
7
RB2/SDO/CCP1
RB2
SDO
CCP1
8
RB3/CCP1/PGM
RB3
CCP1
PGM
9
RB4/SCK/SCL
RB4
SCK
SCL
10
RB5/SS
RB5
SS
11
RB6/T1OSO/T1CKI/PGC
RB6
T1OSO
T1CKI
PGC
12
RB7/T1OSI/PGD
RB7
T1OSI
PGD
13
VSS
5
VDD
14
7
8
9
10
11
12
13
14
5, 6
7
I/O
I
TTL
ST(1)
Bi-directional I/O pin.
External interrupt pin.
I/O
I
I/O
TTL
ST
ST
Bi-directional I/O pin.
SPI Data in.
I2C Data.
I/O
O
I/O
TTL
ST
ST
Bi-directional I/O pin.
SPI Data out.
Capture input, Compare output, PWM output.
I/O
I/O
I
TTL
ST
ST
Bi-directional I/O pin.
Capture input, Compare output, PWM output.
Low Voltage ICSP programming enable pin.
I/O
I/O
I
TTL
ST
ST
Bi-directional I/O pin. Interrupt-on-change pin.
Synchronous serial clock input/output for SPI.
Synchronous serial clock Input for I2C.
I/O
I
TTL
TTL
Bi-directional I/O pin. Interrupt-on-change pin.
Slave select for SPI in Slave mode.
I/O
O
I
I
TTL
ST
ST
ST(2)
Interrupt-on-change pin.
Timer1 Oscillator output.
Timer1 clock input.
In-circuit debugger and ICSP programming clock pin.
I/O
I
I
TTL
ST
ST(2)
Interrupt-on-change pin.
Timer1 Oscillator input.
In-circuit debugger and ICSP programming data pin.
P
–
Ground reference for logic and I/O pins.
P
–
Positive supply for logic and I/O pins.
8
9
10
12
13
15
16
3, 5
15, 16 17, 19
Legend: I = Input
O
= Output
I/O = Input/Output
P = Power
– = Not used
TTL = TTL Input
ST = Schmitt Trigger Input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
DS39598C-page 8
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
2.0
MEMORY ORGANIZATION
2.1
There are two memory blocks in the PIC16F818/819.
These are the program memory and the data memory.
Each block has its own bus, so access to each block
can occur during the same oscillator cycle.
The data memory can be further broken down into the
general purpose RAM and the Special Function
Registers (SFRs). The operation of the SFRs that
control the “core” are described here. The SFRs used
to control the peripheral modules are described in the
section discussing each individual peripheral module.
The data memory area also contains the data
EEPROM memory. This memory is not directly
mapped into the data memory, but is indirectly
mapped. That is, an indirect address pointer specifies
the address of the data EEPROM memory to read/
write. The PIC16F818’s 128 bytes of data EEPROM
memory have the address range 00h-7Fh, and the
PIC16F819’s 256 bytes of data EEPROM memory
have the address range 00h-FFh. More details on the
EEPROM memory can be found in Section 3.0.
Program Memory Organization
The PIC16F818/819 devices have a 13-bit program
counter capable of addressing an 8K x 14 program
memory space. For the PIC16F818, the first 1K x 14
(0000h-03FFh) is physically implemented (see
Figure 2-1). For the PIC16F819, the first 2K x 14 is
located at 0000h-07FFh (see Figure 2-2). Accessing a
location above the physically implemented address will
cause a wraparound. For example, the same instruction will be accessed at locations 020h, 420h, 820h,
C20h, 1020h, 1420h, 1820h, and 1C20h.
The RESET vector is at 0000h and the interrupt vector
is at 0004h.
Additional information on device memory may be found
in the PICmicro™ Mid-Range Reference Manual,
(DS33023).
FIGURE 2-1:
PROGRAM MEMORY MAP
AND STACK FOR
PIC16F818
FIGURE 2-2:
PC<12:0>
CALL, RETURN
RETFIE, RETLW
On-Chip
Program
Memory
PROGRAM MEMORY MAP
AND STACK FOR
PIC16F819
PC<12:0>
CALL, RETURN
RETFIE, RETLW
13
13
Stack Level 1
Stack Level 1
Stack Level 2
Stack Level 2
Stack Level 8
Stack Level 8
RESET Vector
0000h
Interrupt Vector
0004h
0005h
Page 0
03FFh
0400h
On-Chip
Program
Memory
0000h
Interrupt Vector
0004h
0005h
Page 0
07FFh
0800h
Wraps to
0000h - 03FFh
Wraps to
0000h - 07FFh
1FFFh
 2002 Microchip Technology Inc.
RESET Vector
1FFFh
Preliminary
DS39598C-page 9
PIC16F818/819
2.2
Data Memory Organization
The Data Memory is partitioned into multiple banks that
contain the General Purpose Registers and the Special
Function Registers. Bits RP1 (STATUS<6>) and RP0
(STATUS<5>) are the bank select bits.
RP1:RP0
Bank
00
0
01
1
10
2
11
3
Each bank extends up to 7Fh (128 bytes). The lower
locations of each bank are reserved for the Special
Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as
static RAM. All implemented banks contain SFRs.
Some “high use” SFRs from one bank may be mirrored
in another bank for code reduction and quicker access
(e.g., the STATUS register is in Banks 0 - 3).
Note:
2.2.1
EEPROM Data Memory description can be
found in Section 3.0 of this data sheet.
GENERAL PURPOSE REGISTER
FILE
The register file can be accessed either directly or
indirectly through the File Select Register FSR.
DS39598C-page 10
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
FIGURE 2-3:
PIC16F818 REGISTER FILE MAP
File
Address
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
ADRESH
ADCON0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
General
Purpose
Register
Indirect addr.(*) 80h
OPTION
81h
PCL
82h
STATUS
83h
FSR
84h
TRISA
85h
TRISB
86h
87h
88h
89h
PCLATH
8Ah
INTCON
8Bh
PIE1
8Ch
PIE2
8Dh
PCON
8Eh
OSCCON
8Fh
OSCTUNE
90h
91h
PR2
92h
SSPADD
93h
SSPSTAT
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
ADRESL
9Eh
9Fh
ADCON1
General
A0h
Purpose
Register
BFh
32 Bytes
C0h
accesses
40h-7Fh
96 Bytes
Bank 0
File
Address
7Fh
Bank 1
FFh
File
Address
File
Address
Indirect addr.(*) 100h
101h
TMR0
102h
PCL
103h
STATUS
104h
FSR
105h
106h
PORTB
107h
108h
109h
10Ah
PCLATH
10Bh
INTCON
10Ch
EEDATA
EEADR
10Dh
10Eh
EEDATH
10Fh
EEADRH
110h
Indirect addr.(*)
OPTION
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
EECON1
EECON2
Reserved(1)
Reserved(1)
11Fh
19Fh
1A0h
120h
accesses
20h -7Fh
accesses
20h-7Fh
Bank 2
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
17Fh
Bank 3
1FFh
Unimplemented data memory locations, read as ‘0’.
* Not a physical register.
Note 1: These registers are reserved; maintain these registers clear.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 11
PIC16F818/819
FIGURE 2-4:
PIC16F819 REGISTER FILE MAP
File
Address
Indirect addr.(*)
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
PIR1
PIR2
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
ADRESH
ADCON0
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
File
Address
Indirect addr.(*) 80h
OPTION
81h
PCL
82h
STATUS
83h
FSR
84h
TRISA
85h
TRISB
86h
87h
88h
89h
PCLATH
8Ah
INTCON
8Bh
PIE1
8Ch
PIE2
8Dh
PCON
8Eh
OSCCON
8Fh
OSCTUNE
90h
91h
PR2
92h
SSPADD
93h
SSPSTAT
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
ADRESL
9Eh
9Fh
ADCON1
Indirect addr.(*) 100h
101h
TMR0
102h
PCL
103h
STATUS
104h
FSR
105h
106h
PORTB
107h
108h
109h
10Ah
PCLATH
10Bh
INTCON
10Ch
EEDATA
EEADR
10Dh
10Eh
EEDATH
10Fh
EEADRH
110h
A0h
120h
General
Purpose
Register
80 Bytes
General
Purpose
Register
Bank 0
7Fh
accesses
70h-7Fh
Bank 1
EFh
F0h
FFh
Indirect addr.(*)
OPTION
PCL
STATUS
FSR
TRISB
PCLATH
INTCON
EECON1
EECON2
Reserved(1)
Reserved(1)
11Fh
General
Purpose
Register
80 Bytes
96 Bytes
File
Address
File
Address
accesses
70h-7Fh
Bank 2
180h
181h
182h
183h
184h
185h
186h
187h
188h
189h
18Ah
18Bh
18Ch
18Dh
18Eh
18Fh
190h
19Fh
1A0h
accesses
20h -7Fh
16Fh
170h
17Fh
Bank 3
1FFh
Unimplemented data memory locations, read as ‘0’.
* Not a physical register.
Note 1: These registers are reserved; maintain these registers clear.
DS39598C-page 12
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
2.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers can be classified into
two sets: core (CPU) and peripheral. Those registers
associated with the core functions are described in
detail in this section. Those related to the operation of
the peripheral features are described in detail in the
peripheral feature section.
The Special Function Registers are registers used by
the CPU and peripheral modules for controlling the
desired operation of the device. These registers are
implemented as static RAM. A list of these registers is
given in Table 2-1.
TABLE 2-1:
Address
Name
SPECIAL FUNCTION REGISTER SUMMARY
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details on
page:
Bank 0
00h(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
23
01h
TMR0
Timer0 Module’s Register
xxxx xxxx
53, 17
02h(1)
PCL
Program Counter's (PC) Least Significant Byte
0000 0000
23
03h(1)
STATUS
0001 1xxx
16
04h(1)
FSR
Indirect Data Memory Address Pointer
xxxx xxxx
23
05h
PORTA
PORTA Data Latch when written; PORTA pins when read
xxx0 0000
39
06h
PORTB
PORTB Data Latch when written; PORTB pins when read
xxxx xxxx
43
IRP
RP1
RP0
TO
PD
Z
DC
C
07h
—
Unimplemented
—
—
08h
—
Unimplemented
—
—
09h
—
Unimplemented
—
—
---0 0000
23
0Ah(1,2)
PCLATH
—
—
—
0Bh(1)
INTCON
0Ch
PIR1
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
18
—
ADIF
—
—
SSPIF
CCP1IF
TMR2IF
TMR1IF
-0-- 0000
20
0Dh
PIR2
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 register
—
—
—
EEIF
—
—
—
—
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 register
10h
T1CON
11h
TMR2
12h
T2CON
13h
SSPBUF
—
—
T1CKPS1
Write Buffer for the Upper 5 bits of the Program Counter
T1CKPS0
T1OSCEN
T1SYNC
TMR1CS
TMR1ON
Timer2 Module’s Register
—
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
Synchronous Serial Port Receive Buffer/Transmit Register
14h
SSPCON
15h
CCPR1L
Capture/Compare/PWM Register (LSB)
WCOL
SSPOV
SSPEN
CKP
Capture/Compare/PWM Register (MSB)
SSPM3
SSPM2
SSPM1
SSPM0
---0 ----
21
xxxx xxxx
57
xxxx xxxx
57
--00 0000
57
0000 0000
63
-000 0000
64
xxxx xxxx
71, 76
0000 0000
71
xxxx xxxx
66, 67, 68
xxxx xxxx
66, 67, 68
--00 0000
65
16h
CCPR1H
17h
CCP1CON
18h
—
Unimplemented
—
—
19h
—
Unimplemented
—
—
1Ah
—
Unimplemented
—
—
1Bh
—
Unimplemented
—
—
1Ch
—
Unimplemented
—
—
1Dh
—
Unimplemented
—
—
xxxx xxxx
81
0000 00-0
81
—
—
CCP1X
1Eh
ADRESH
A/D Result Register Higher 2 bits
1Fh
ADCON0
ADCS1
Legend:
Note 1:
2:
3:
ADCS0
CHS2
CCP1Y
CHS1
CCP1M3
CHS0
CCP1M2
GO/DONE
CCP1M1
—
CCP1M0
ADON
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are
transferred to the upper byte of the program counter.
Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 13
PIC16F818/819
TABLE 2-1:
Address
Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details on
page:
Bank 1
80h(1)
INDF
81h
OPTION
82h(1)
PCL
83h(1)
STATUS
Addressing this location uses contents of FSR to address data memory (not a physical register)
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
PD
Z
DC
C
Program Counter's (PC) Least Significant Byte
IRP
RP1
RP0
TO
84h(1)
FSR
Indirect Data Memory Address Pointer
85h
TRISA
TRISA7
PORTB Data Direction Register
TRISA6
TRISA5(3)
PORTA Data Direction Register (TRISA<4:0>
0000 0000
23
1111 1111
17
0000 0000
23
0001 1xxx
16
xxxx xxxx
23
1111 1111
39
86h
TRISB
1111 1111
43
87h
—
Unimplemented
—
—
88h
—
Unimplemented
—
—
89h
—
Unimplemented
—
—
---0 0000
23
0000 000x
18
19
8Ah(1,2)
PCLATH
—
—
—
8Bh(1)
INTCON
GIE
PEIE
TMR0IE
Write Buffer for the Upper 5 bits of the PC
INTE
RBIE
TMR0IF
INTF
RBIF
8Ch
PIE1
—
ADIE
—
—
SSPIE
CCP1IE
TMR2IE
TMR1IE
-0-- 0000
8Dh
PIE2
—
—
—
EEIE
—
—
—
—
---0 ----
21
8Eh
PCON
—
—
—
—
—
—
POR
BOR
---- --qq
22
8Fh
OSCCON
—
IRCF2
IRCF1
IRCF0
—
IOFS
—
—
-000 -0--
38
90h(1)
OSCTUNE
—
—
TUN5
TUN4
TUN3
TUN2
TUN1
TUN0
--00 0000
36
91h
—
Unimplemented
92h
PR2
Timer2 Period Register
93h
SSPADD
Synchronous Serial Port (I2C mode) Address Register
94h
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
—
—
1111 1111
68
0000 0000
71, 76
0000 0000
71
95h
—
Unimplemented
—
—
96h
—
Unimplemented
—
—
97h
—
Unimplemented
—
—
98h
—
Unimplemented
—
—
99h
—
Unimplemented
—
—
9Ah
—
Unimplemented
—
—
9Bh
—
Unimplemented
—
—
9Ch
—
Unimplemented
—
—
9Dh
—
9Eh
ADRESL
9Fh
ADCON1
Legend:
Note 1:
2:
3:
Unimplemented
A/D Result Register Lower Byte
ADFM
ADCS2
—
—
PCFG3
PCFG2
PCFG1
PCFG0
—
—
xxxx xxxx
81
00-- 0000
81
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are
transferred to the upper byte of the program counter.
Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
DS39598C-page 14
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
TABLE 2-1:
Address
Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Details on
page:
Bank 2
100h(1)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
23
101h
TMR0
Timer0 Module’s Register
xxxx xxxx
53
102h(1
PCL
Program Counter's (PC) Least Significant Byte
0000 0000
23
(1)
STATUS
(1)
FSR
103h
104h
105h
—
106h
IRP
RP1
RP0
TO
PD
Z
DC
C
Indirect Data Memory Address Pointer
PORTB
Unimplemented
PORTB Data Latch when written; PORTB pins when read
0001 1xxx
16
xxxx xxxx
23
—
—
xxxx xxxx
43
107h
—
Unimplemented
—
—
108h
—
Unimplemented
—
—
109h
—
Unimplemented
—
—
---0 0000
23
10Ah(1,2) PCLATH
—
—
—
GIE
PEIE
TMR0IE
Write Buffer for the Upper 5 bits of the Program Counter
10Bh(1)
INTCON
0000 000x
18
10Ch
EEDATA
EEPROM Data Register Low Byte
xxxx xxxx
25
10Dh
EEADR
EEPROM Address Register Low Byte
xxxx xxxx
25
10Eh
EEDATH
10Fh
EEADRH
—
—
—
INTE
RBIE
TMR0IF
INTF
RBIF
EEPROM Data Register High Byte
—
—
—
—
EEPROM Address Register High Byte
--xx xxxx
25
---- -xxx
25
0000 0000
23
1111 1111
17
0000 0000
23
0001 1xxx
16
xxxx xxxx
23
Bank 3
180h(1)
INDF
181h
OPTION
(1)
182h
PCL
183h(1)
STATUS
(1)
184h
Addressing this location uses contents of FSR to address data memory (not a physical register)
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
PD
Z
DC
C
Program Counter's (PC) Least Significant Byte
FSR
IRP
RP1
RP0
TO
Indirect Data Memory Address Pointer
185h
—
186h
TRISB
187h
—
188h
—
189h
—
18Ah(1,2) PCLATH
Unimplemented
—
—
1111 1111
43
Unimplemented
—
—
Unimplemented
—
—
Unimplemented
—
—
---0 0000
23
PORTB Data Direction Register
—
—
—
Write Buffer for the Upper 5 bits of the Program Counter
18Bh(1)
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
18
18Ch
EECON1
EEPGD
—
—
FREE
WRERR
WREN
WR
RD
x--x x000
25
18Dh
EECON2
EEPROM Control Register2 (not a physical register)
---- ----
25
18Eh
—
Reserved; maintain clear
0000 0000
—
18Fh
—
Reserved; maintain clear
0000 0000
—
Legend:
Note 1:
2:
3:
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
These registers can be addressed from any bank.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are
transferred to the upper byte of the program counter.
Pin 5 is an input only; the state of the TRISA5 bit has no effect and will always read ‘1’.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 15
PIC16F818/819
2.2.2.1
STATUS Register
The STATUS register, shown in Register 2-1, contains
the arithmetic status of the ALU, the RESET status and
the bank select bits for data memory.
The STATUS register can be the destination for any
instruction, as with any other register. If the STATUS
register is the destination for an instruction that affects
the Z, DC or C bits, then the write to these three bits is
disabled. These bits are set or cleared according to the
device logic. Furthermore, the TO and PD bits are not
writable. Therefore, the result of an instruction with the
STATUS register as destination may be different than
intended.
REGISTER 2-1:
For example, CLRF STATUS will clear the upper three
bits and set the Z bit. This leaves the STATUS register
as ‘000u u1uu’ (where u = unchanged).
It is recommended, therefore, that only BCF, BSF,
SWAPF and MOVWF instructions are used to alter the
STATUS register, because these instructions do not
affect the Z, C or DC bits from the STATUS register. For
other instructions not affecting any status bits, see
Section 13.0, "Instruction Set Summary".
Note:
The C and DC bits operate as a borrow
and digit borrow bit, respectively, in subtraction. See the SUBLW and SUBWF
instructions for examples.
STATUS REGISTER (ADDRESS 03h, 83h, 103h, 183h)
R/W-0
R/W-0
R/W-0
R-1
R-1
R/W-x
R/W-x
R/W-x
IRP
RP1
RP0
TO
PD
Z
DC
C
bit 7
bit 0
bit 7
IRP: Register Bank Select bit (used for indirect addressing)
1 = Bank 2, 3 (100h - 1FFh)
0 = Bank 0, 1 (00h - FFh)
bit 6-5
RP<1:0>: Register Bank Select bits (used for direct addressing)
11 = Bank 3 (180h - 1FFh)
10 = Bank 2 (100h - 17Fh)
01 = Bank 1 (80h - FFh)
00 = Bank 0 (00h - 7Fh)
Each bank is 128 bytes
bit 4
TO: Time-out bit
1 = After power-up, CLRWDT instruction, or SLEEP instruction
0 = A WDT time-out occurred
bit 3
PD: Power-down bit
1 = After power-up or by the CLRWDT instruction
0 = By execution of the SLEEP instruction
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit carry/borrow bit (ADDWF, ADDLW, SUBLW and SUBWF instructions)(1)
1 = A carry-out from the 4th low order bit of the result occurred
0 = No carry-out from the 4th low order bit of the result
bit 0
C: Carry/borrow bit (ADDWF, ADDLW, SUBLW and SUBWF instructions)(1,2)
1 = A carry-out from the Most Significant bit of the result occurred
0 = No carry-out from the Most Significant bit of the result occurred
Note 1: For borrow, the polarity is reversed. A subtraction is executed by adding the two’s
complement of the second operand.
2: For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order
bit of the source register.
Legend:
DS39598C-page 16
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Preliminary
x = Bit is unknown
 2002 Microchip Technology Inc.
PIC16F818/819
2.2.2.2
OPTION Register
Note:
The OPTION register is a readable and writable register that contains various control bits to configure the
TMR0 prescaler/WDT postscaler (single assignable
register known also as the prescaler), the External INT
Interrupt, TMR0, and the weak pull-ups on PORTB.
REGISTER 2-2:
To achieve a 1:1 prescaler assignment for
the TMR0 register, assign the prescaler to
the Watchdog Timer.
OPTION REGISTER (ADDRESS 81h, 181h)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
bit 7
RBPU: PORTB Pull-up Enable bit
1 = PORTB pull-ups are disabled
0 = PORTB pull-ups are enabled by individual port latch values
bit 6
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of RB0/INT pin
0 = Interrupt on falling edge of RB0/INT pin
bit 5
T0CS: TMR0 Clock Source Select bit
1 = Transition on RA4/T0CKI pin
0 = Internal instruction cycle clock (CLKO)
bit 4
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on RA4/T0CKI pin
0 = Increment on low-to-high transition on RA4/T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS2:PS0: Prescaler Rate Select bits
Bit Value
000
001
010
011
100
101
110
111
TMR0 Rate WDT Rate
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
1:1
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
 2002 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS39598C-page 17
PIC16F818/819
2.2.2.3
INTCON Register
The INTCON Register is a readable and writable register that contains various enable and flag bits for the
TMR0 register overflow, RB port change and external
RB0/INT pin interrupts.
REGISTER 2-3:
Note:
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
INTCON: INTERRUPT CONTROL REGISTER (ADDRESS 0Bh, 8Bh, 10Bh, 18Bh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-x
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
bit 7
bit 0
bit 7
GIE: Global Interrupt Enable bit
1 = Enables all unmasked interrupts
0 = Disables all interrupts
bit 6
PEIE: Peripheral Interrupt Enable bit
1 = Enables all unmasked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5
TMR0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 interrupt
0 = Disables the TMR0 interrupt
bit 4
INTE: RB0/INT External Interrupt Enable bit
1 = Enables the RB0/INT external interrupt
0 = Disables the RB0/INT external interrupt
bit 3
RBIE: RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2
TMR0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1
INTF: RB0/INT External Interrupt Flag bit
1 = The RB0/INT external interrupt occurred (must be cleared in software)
0 = The RB0/INT external interrupt did not occur
bit 0
RBIF: RB Port Change Interrupt Flag bit
A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch
condition and allow flag bit RBIF to be cleared.
1 = At least one of the RB7:RB4 pins changed state (must be cleared in software)
0 = None of the RB7:RB4 pins have changed state
Legend:
DS39598C-page 18
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Preliminary
x = Bit is unknown
 2002 Microchip Technology Inc.
PIC16F818/819
2.2.2.4
PIE1 Register
This register contains the individual enable bits for the
peripheral interrupts.
Note:
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
REGISTER 2-4:
PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ADDRESS 8Ch)
U-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
ADIE
—
—
SSPIE
CCP1IE
TMR2IE
TMR1IE
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D converter interrupt
0 = Disables the A/D converter interrupt
bit 5-4
Unimplemented: Read as ‘0’
bit 3
SSPIE: Synchronous Serial Port Interrupt Enable bit
1 = Enables the SSP interrupt
0 = Disables the SSP interrupt
bit 2
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
bit 1
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
bit 0
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
 2002 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS39598C-page 19
PIC16F818/819
2.2.2.5
PIR1 Register
Note:
This register contains the individual flag bits for the
Peripheral interrupts.
REGISTER 2-5:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit, or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
PIR1: PERIPHERAL INTERRUPT FLAG REGISTER 1 (ADDRESS 0Ch)
U-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
—
ADIF
—
—
SSPIF
CCP1IF
TMR2IF
TMR1IF
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6
ADIF: A/D Converter Interrupt Flag bit
1 = An A/D conversion completed
0 = The A/D conversion is not complete
bit 5-4
Unimplemented: Read as ‘0’
bit 3
SSPIF: Synchronous Serial Port (SSP) Interrupt Flag bit
1 = The SSP interrupt condition has occurred, and must be cleared in software before
returning from the Interrupt Service Routine.
The conditions that will set this bit are a transmission/reception has taken place.
0 = No SSP interrupt condition has occurred
bit 2
CCP1IF: CCP1 Interrupt Flag bit
Capture mode:
1 = A TMR1 register capture occurred (must be cleared in software)
0 = No TMR1 register capture occurred
Compare mode:
1 = A TMR1 register compare match occurred (must be cleared in software)
0 = No TMR1 register compare match occurred
PWM mode:
Unused in this mode
bit 1
TMR2IF: TMR2 to PR2 Match Interrupt Flag bit
1 = TMR2 to PR2 match occurred (must be cleared in software)
0 = No TMR2 to PR2 match occurred
bit 0
TMR1IF: TMR1 Overflow Interrupt Flag bit
1 = TMR1 register overflowed (must be cleared in software)
0 = TMR1 register did not overflow
Legend:
DS39598C-page 20
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Preliminary
x = Bit is unknown
 2002 Microchip Technology Inc.
PIC16F818/819
2.2.2.6
PIE2 Register
The PIE2 register contains the individual enable bit for
the EEPROM write operation interrupt.
REGISTER 2-6:
PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ADDRESS 8Dh)
U-0
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
—
—
—
EEIE
—
—
—
—
bit 7
bit 0
bit 7-5
Unimplemented: Read as '0'
bit 4
EEIE: EEPROM Write Operation Interrupt Enable bit
1 = Enable EE Write Interrupt
0 = Disable EE Write Interrupt
bit 3-0
Unimplemented: Read as '0'
Legend:
R = Readable bit
- n = Value at POR
2.2.2.7
W = Writable bit
‘1’ = Bit is set
PIR2 Register
.
The PIR2 register contains the flag bit for the EEPROM
write operation interrupt.
REGISTER 2-7:
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Note:
Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit, or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
PIR2: PERIPHERAL INTERRUPT FLAG REGISTER 2 (ADDRESS 0Dh)
U-0
U-0
U-0
R/W-0
U-0
U-0
U-0
U-0
—
—
—
EEIF
—
—
—
—
bit 7
bit 0
bit 7-5
Unimplemented: Read as '0'
bit 4
EEIF: EEPROM Write Operation Interrupt Enable bit
1 = Enable EE Write Interrupt
0 = Disable EE Write Interrupt
bit 3-0
Unimplemented: Read as '0'
Legend:
R = Readable bit
- n = Value at POR
 2002 Microchip Technology Inc.
W = Writable bit
‘1’ = Bit is set
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
DS39598C-page 21
PIC16F818/819
2.2.2.8
Note:
PCON Register
Note:
Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of
its corresponding enable bit or the global
enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an
interrupt.
BOR is unknown on Power-on Reset. It
must then be set by the user and checked
on subsequent RESETS to see if BOR is
clear, indicating a brown-out has occurred.
The BOR status bit is a ‘don't care’ and is
not necessarily predictable if the brown-out
circuit is disabled (by clearing the BOREN
bit in the Configuration word).
The Power Control (PCON) register contains a flag bit
to allow differentiation between a Power-on Reset
(POR), a Brown-out Reset, an external MCLR Reset
and WDT Reset.
REGISTER 2-8:
PCON: POWER CONTROL REGISTER (ADDRESS 8Eh)
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0
R/W-x
—
—
—
—
—
—
POR
BOR
bit 7
bit 0
bit 7-2
Unimplemented: Read as ‘0’
bit 1
POR: Power-on Reset Status bit
1 = No Power-on Reset occurred
0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs)
bit 0
BOR: Brown-out Reset Status bit
1 = No Brown-out Reset occurred
0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs)
Legend:
DS39598C-page 22
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Preliminary
x = Bit is unknown
 2002 Microchip Technology Inc.
PIC16F818/819
2.3
PCL and PCLATH
The program counter (PC) is 13 bits wide. The low byte
comes from the PCL register, which is a readable and
writable register. The upper bits (PC<12:8>) are not
readable, but are indirectly writable through the
PCLATH register. On any RESET, the upper bits of the
PC will be cleared. Figure 2-5 shows the two situations
for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL
(PCLATH<4:0> → PCH). The lower example in the figure shows how the PC is loaded during a CALL or GOTO
instruction (PCLATH<4:3> → PCH).
FIGURE 2-5:
LOADING OF PC IN
DIFFERENT SITUATIONS
PCH
PCL
12
8
7
0
PC
8
PCLATH<4:0>
5
Instruction with
PCL as
Destination
ALU
12
11 10
0
7
PC
GOTO,CALL
2
PCLATH<4:3>
11
Opcode <10:0>
PCLATH
2.3.1
COMPUTED GOTO
A computed GOTO is accomplished by adding an offset
to the program counter (ADDWF PCL). When doing a
table read using a computed GOTO method, care
should be exercised if the table location crosses a PCL
memory boundary (each 256-byte block). Refer to the
application note, “Implementing a Table Read”
(AN556).
2.3.2
2: There are no instructions/mnemonics
called PUSH or POP. These are actions
that occur from the execution of the
CALL, RETURN, RETLW and RETFIE
instructions, or the vectoring to an
interrupt address.
2.4
Indirect Addressing: INDF and
FSR Registers
The INDF register is not a physical register. Addressing
INDF actually addresses the register whose address is
contained in the FSR register (FSR is a pointer). This is
indirect addressing.
Register file 05 contains the value 10h
Register file 06 contains the value 0Ah
Load the value 05 into the FSR register
A read of the INDF register will return the value
of 10h
• Increment the value of the FSR register by one
(FSR = 06)
• A read of the INDF register now will return the
value of 0Ah
Reading INDF itself indirectly (FSR = 0) will produce
00h. Writing to the INDF register indirectly results in a
no operation (although STATUS bits may be affected).
A simple program to clear RAM locations 20h-2Fh
using indirect addressing is shown in Example 2-2.
EXAMPLE 2-2:
STACK
The PIC16F818/819 family has an 8-level deep x 13-bit
wide hardware stack. The stack space is not part of
either program or data space and the stack pointer is not
readable or writable. The PC is PUSHed onto the stack
when a CALL instruction is executed, or an interrupt
causes a branch. The stack is POPed in the event of a
RETURN, RETLW or a RETFIE instruction execution.
PCLATH is not affected by a PUSH or POP operation.
 2002 Microchip Technology Inc.
INDIRECT ADDRESSING
•
•
•
•
PCL
8
Note 1: There are no status bits to indicate stack
overflow or stack underflow conditions.
EXAMPLE 2-1:
PCLATH
PCH
The stack operates as a circular buffer. This means that
after the stack has been PUSHed eight times, the ninth
push overwrites the value that was stored from the first
push. The tenth push overwrites the second push (and
so on).
movlw
movwf
NEXT
clrf
incf
btfss
goto
CONTINUE
:
HOW TO CLEAR RAM
USING INDIRECT
ADDRESSING
0x20
FSR
INDF
FSR
FSR,4
NEXT
;initialize pointer
;to RAM
;clear INDF register
;inc pointer
;all done?
;NO, clear next
;YES, continue
An effective 9-bit address is obtained by concatenating
the 8-bit FSR register and the IRP bit (STATUS<7>), as
shown in Figure 2-6.
Preliminary
DS39598C-page 23
PIC16F818/819
FIGURE 2-6:
DIRECT/INDIRECT ADDRESSING
Direct Addressing
RP1:RP0
Bank Select
6
Indirect Addressing
From Opcode
0
IRP
7
FSR Register
Bank Select
Location Select
00
01
10
0
Location Select
11
00h
80h
100h
180h
7Fh
FFh
17Fh
1FFh
Data
Memory(1)
Bank 0
Note 1:
Bank 1
Bank 2
Bank 3
For register file map detail, see Figure 2-3 or Figure 2-4.
DS39598C-page 24
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
3.0
DATA EEPROM AND FLASH
PROGRAM MEMORY
3.1
The Data EEPROM and FLASH Program memory is
readable and writable during normal operation (over
the full VDD range). This memory is not directly mapped
in the register file space. Instead, it is indirectly
addressed through the Special Function Registers.
There are six SFRs used to read and write this
memory:
•
•
•
•
•
•
EEADR and EEADRH
The EEADRH:EEADR register pair can address up to
a maximum of 256 bytes of data EEPROM, or up to a
maximum of 8K words of program EEPROM. When
selecting a data address value, only the LSByte of the
address is written to the EEADR register. When selecting a program address value, the MSByte of the
address is written to the EEADRH register and the
LSByte is written to the EEADR register.
If the device contains less memory than the full address
reach of the address register pair, the Most Significant
bits of the registers are not implemented. For example,
if the device has 128 bytes of data EEPROM, the Most
Significant bit of EEADR is not implemented on access
to data EEPROM.
EECON1
EECON2
EEDATA
EEDATH
EEADR
EEADRH
When interfacing the data memory block, EEDATA
holds the 8-bit data for read/write, and EEADR holds
the address of the EEPROM location being accessed.
These devices have 128 or 256 bytes of data
EEPROM, with an address range from 00h to 0FFh.
Addresses from 80h to FFh are unimplemented on the
PIC16F818 device and will read 00h. When writing to
unimplemented locations, the charge pump will be
turned off.
When interfacing the program memory block, the
EEDATA and EEDATH registers form a two-byte word
that holds the 14-bit data for read/write, and the
EEADR and EEADRH registers form a two-byte word
that holds the 13-bit address of the EEPROM location
being accessed. These devices have 1K or 2K words
of program FLASH, with an address range from 0000h
to 03FFh for the PIC16F818, and 0000h to 07FFh for
the PIC16F819. Addresses above the range of the
respective device will wraparound to the beginning of
program memory.
The EEPROM data memory allows single byte read
and write. The FLASH program memory allows single
word reads and four-word block writes. Program memory writes must first start with a 32-word block erase,
then write in 4-word blocks. A byte write in data
EEPROM memory automatically erases the location
and writes the new data (erase before write).
3.2
EECON1 and EECON2 Registers
EECON1 is the control register for memory accesses.
Control bit EEPGD determines if the access will be a
program or data memory access. When clear, as it is
when RESET, any subsequent operations will operate
on the data memory. When set, any subsequent
operations will operate on the program memory.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
The WREN bit, when set, will allow a write or erase
operation. On power-up, the WREN bit is clear. The
WRERR bit is set when a write (or erase) operation is
interrupted by a MCLR, or a WDT Time-out Reset during normal operation. In these situations, following
RESET, the user can check the WRERR bit and rewrite
the location. The data and address will be unchanged
in the EEDATA and EEADR registers.
Interrupt flag bit, EEIF in the PIR2 register, is set when
write is complete. It must be cleared in software.
EECON2 is not a physical register. Reading EECON2
will read all '0's. The EECON2 register is used
exclusively in the EEPROM write sequence.
The write time is controlled by an on-chip timer. The
write/erase voltages are generated by an on-chip
charge pump, rated to operate over the voltage range
of the device for byte or word operations.
When the device is code protected, the CPU may
continue to read and write the data EEPROM memory.
Depending on the settings of the write protect bits, the
device may or may not be able to write certain blocks
of the program memory; however, reads of the program
memory are allowed. When code protected, the device
programmer can no longer access data or program
memory; this does NOT inhibit internal reads or writes.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 25
PIC16F818/819
REGISTER 3-1:
EECON1: EEPROM ACCESS CONTROL REGISTER 1 (ADDRESS 18Ch)
R/W-x
U-0
U-0
R/W-x
R/W-x
R/W-0
R/S-0
R/S-0
EEPGD
—
—
FREE
WRERR
WREN
WR
RD
bit 7
bit 0
bit 7
EEPGD: Program/Data EEPROM Select bit
1 = Accesses program memory
0 = Accesses data memory
Reads ‘0’ after a POR; this bit cannot be changed while a write operation is in progress.
bit 6-5
Unimplemented: Read as '0'
bit 4
FREE: EEPROM Forced Row Erase bit
1 = Erase the program memory row addressed by EEADRH:EEADR on the next WR command
0 = Perform write only
bit 3
WRERR: EEPROM Error Flag bit
1 = A write operation is prematurely terminated
(any MCLR or any WDT Reset during normal operation)
0 = The write operation completed
bit 2
WREN: EEPROM Write Enable bit
1 = Allows write cycles
0 = Inhibits write to the EEPROM
bit 1
WR: Write Control bit
1 = Initiates a write cycle. The bit is cleared by hardware once write is complete. The WR bit
can only be set (not cleared) in software.
0 = Write cycle to the EEPROM is complete
bit 0
RD: Read Control bit
1 = Initiates an EEPROM read, RD is cleared in hardware. The RD bit can only be set (not
cleared) in software.
0 = Does not initiate an EEPROM read
Legend:
R = Readable bit
W = Writable bit
- n = Value at POR ‘1’ = Bit is set
DS39598C-page 26
S = Set only
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
3.3
Reading Data EEPROM Memory
To read a data memory location, the user must write the
address to the EEADR register, clear the EEPGD control bit (EECON1<7>) and then set control bit, RD
(EECON1<0>). The data is available in the very next
cycle, in the EEDATA register; therefore, it can be read
in the next instruction (see Example 3-1). EEDATA will
hold this value until another read, or until it is written to
by the user (during a write operation).
The steps to reading the EEPROM data memory are:
1.
Write the address to EEADR. Make sure that the
address is not larger than the memory size of
the device.
Clear the EEPGD bit to point to EEPROM data
memory.
Set the RD bit to start the read operation.
Read the data from the EEDATA register.
2.
3.
4.
EXAMPLE 3-1:
BANKSEL EEADR
MOVF
ADDR,W
MOVWF
EEADR
DATA EEPROM READ
;
;
;
;
BANKSEL EECON1
;
BCF
EECON1,EEPGD ;
BSF
EECON1,RD
;
BANKSEL EEDATA
;
MOVF
EEDATA,W
;
3.4
Select Bank of EEADR
Data Memory Address
to read
Select Bank of EECON1
Point to Data memory
EE Read
Select Bank of EEDATA
W = EEDATA
Writing to Data EEPROM Memory
The steps to write to EEPROM data memory are:
1.
If step 10 is not implemented, check the WR bit
to see if a write is in progress.
2. Write the address to EEADR. Make sure that the
address is not larger than the memory size of
the device.
3. Write the 8-bit data value to be programmed in
the EEDATA register.
4. Clear the EEPGD bit to point to EEPROM data
memory.
5. Set the WREN bit to enable program operations.
6. Disable interrupts (if enabled).
7. Execute the special five instruction sequence:
• Write 55h to EECON2 in two steps (first to W,
then to EECON2)
• Write AAh to EECON2 in two steps (first to W,
then to EECON2)
• Set the WR bit
8. Enable interrupts (if using interrupts).
9. Clear the WREN bit to disable program
operations.
10. At the completion of the write cycle, the WR bit
is cleared and the EEIF interrupt flag bit is set
(EEIF must be cleared by firmware). If step 1 is
not implemented, then firmware should check
for EEIF to be set, or WR to clear, to indicate the
end of the program cycle.
EXAMPLE 3-2:
BANKSEL EECON1
;
;
BTFSC
EECON1,WR
;
GOTO
$-1
;
BANKSEL EEADR
;
;
MOVF
ADDR,W
;
MOVWF
EEADR
;
;
MOVF
VALUE,W
;
MOVWF
EEDATA
;
;
BANKSEL EECON1
;
;
BCF
EECON1,EEPGD;
;
BSF
EECON1,WREN ;
To write an EEPROM data location, the user must first
write the address to the EEADR register and the data
to the EEDATA register. Then, the user must follow a
specific write sequence to initiate the write for each
byte.
The write will not initiate if the write sequence is not
exactly followed (write 55h to EECON2, write AAh to
EECON2, then set WR bit) for each byte. We strongly
recommend that interrupts be disabled during this
code segment (see Example 3-2).
 2002 Microchip Technology Inc.
Required
Sequence
Additionally, the WREN bit in EECON1 must be set to
enable write. This mechanism prevents accidental
writes to data EEPROM due to errant (unexpected)
code execution (i.e., lost programs). The user should
keep the WREN bit clear at all times, except when
updating EEPROM. The WREN bit is not cleared
by hardware
After a write sequence has been initiated, clearing the
WREN bit will not affect this write cycle. The WR bit will
be inhibited from being set unless the WREN bit is set.
At the completion of the write cycle, the WR bit is
cleared in hardware and the EE Write Complete
Interrupt Flag bit (EEIF) is set. The user can either
enable this interrupt, or poll this bit. EEIF must be
cleared by software.
DATA EEPROM WRITE
Preliminary
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
BSF
BCF
INTCON,GIE
55h
EECON2
AAh
EECON2
EECON1,WR
;
;
;
;
;
;
;
INTCON,GIE ;
EECON1,WREN ;
Select Bank of
EECON1
Wait for write
to complete
Select Bank of
EEADR
Data Memory
Address to write
Data Memory Value
to write
Select Bank of
EECON1
Point to DATA
memory
Enable writes
Disable INTs.
Write 55h
Write AAh
Set WR bit to
begin write
Enable INTs.
Disable writes
DS39598C-page 27
PIC16F818/819
3.5
Reading FLASH Program Memory
3.6
Erasing FLASH Program Memory
To read a program memory location, the user must
write two bytes of the address to the EEADR and
EEADRH registers, set the EEPGD control bit
(EECON1<7>), and then set control bit RD
(EECON1<0>). Once the read control bit is set, the program memory FLASH controller will use the second
instruction cycle to read the data. This causes the second instruction immediately following the “BSF
EECON1,RD” instruction to be ignored. The data is
available in the very next cycle, in the EEDATA and
EEDATH registers; therefore, it can be read as two
bytes in the following instructions. EEDATA and
EEDATH registers will hold this value until another
read, or until it is written to by the user (during a write
operation).
The minimum erase block is 32 words. Only through
the use of an external programmer, or through ICSP
control, can larger blocks of program memory be bulk
erased. Word erase in the FLASH array is not
supported.
EXAMPLE 3-3:
For protection, the write initiate sequence for EECON2
must be used.
BANKSEL EEADRH
MOVF
ADDRH, W
MOVWF
EEADRH
FLASH PROGRAM READ
;
;
;
;
MOVF
ADDRL, W
;
MOVWF
EEADR
;
;
BANKSEL EECON1
;
BSF
EECON1, EEPGD;
;
BSF
EECON1, RD
;
;
NOP
;
;
NOP
;
;
;
BANKSEL EEDATA
;
MOVF
EEDATA, W
;
MOVWF
DATAL
;
MOVF
EEDATH, W
;
MOVWF
DATAH
;
Select Bank of EEADRH
MS Byte of Program
Address to read
LS Byte of Program
Address to read
Select Bank of EECON1
Point to PROGRAM
memory
EE Read
When initiating an erase sequence from the microcontroller itself, a block of 32 words of program memory is
erased. The Most Significant 11 bits of the
EEADRH:EEADR point to the block being erased.
EEADR< 4:0> are ignored.
The EECON1 register commands the erase operation.
The EEPGD bit must be set to point to the FLASH program memory. The WREN bit must be set to enable
write operations. The FREE bit is set to select an erase
operation.
After the “BSF EECON1,WR” instruction, the processor
requires two cycles to set up the erase operation. The
user must place two NOP instructions after the WR bit is
set. The processor will halt internal operations for the
typical 2 ms, only during the cycle in which the erase
takes place. This is not SLEEP mode, as the clocks and
peripherals will continue to run. After the erase cycle,
the processor will resume operation with the third
instruction after the EECON1 write instruction.
Any instructions
here are ignored as
program memory is
read in second cycle
after BSF EECON1,RD
Select Bank of EEDATA
DATAL = EEDATA
3.6.1
DATAH = EEDATH
2.
The sequence of events for erasing a block of internal
program memory location is:
1.
3.
4.
5.
6.
7.
DS39598C-page 28
FLASH PROGRAM MEMORY
ERASE SEQUENCE
Preliminary
Load EEADRH:EEADR with address of row
being erased.
Set EEPGD bit to point to program memory; set
WREN bit to enable writes, and set FREE bit to
enable the erase.
Disable interrupts.
Write 55h to EECON2.
Write AAh to EECON2.
Set the WR bit. This will begin the row erase
cycle.
The CPU will stall for duration of the erase.
 2002 Microchip Technology Inc.
PIC16F818/819
EXAMPLE 3-4:
ERASING A FLASH PROGRAM MEMORY ROW
BANKSEL EEADRH
MOVF
ADDRH, W
MOVWF
EEADRH
MOVF
ADDRL, W
MOVWF
EEADR
; Select Bank of EEADRH
;
; MS Byte of Program Address to Erase
;
; LS Byte of Program Address to Erase
ERASE_ROW
BANKSEL EECON1
; Select Bank of EECON1
BSF
EECON1, EEPGD; Point to PROGRAM memory
BSF
EECON1, WREN ; Enable Write to memory
BSF
EECON1, FREE ; Enable Row Erase operation
;
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
NOP
BCF
BSF
INTCON, GIE
55h
EECON2
AAh
EECON2
EECON1, WR
;
;
;
;
;
;
;
;
;
;
EECON1, WREN ;
INTCON, GIE ;
 2002 Microchip Technology Inc.
Disable interrupts (if using)
Write 55h
Write AAh
Start Erase (CPU stall)
Any instructions here are ignored as processor
halts to begin Erase sequence
processor will stop here and wait for Erase complete
after Erase processor continues with 3rd instruction
Disable writes
Enable interrupts (if using)
Preliminary
DS39598C-page 29
PIC16F818/819
3.7
Writing to FLASH Program
Memory
There are 4 buffer register words and all four locations
MUST be written to with correct data.
FLASH program memory may only be written to if the
destination address is in a segment of memory that is
not write protected, as defined in bits WRT1:WRT0 of
the device configuration word (Register 12-1). FLASH
program memory must be written in four-word blocks.
A block consists of four words with sequential
addresses, with a lower boundary defined by an
address, where EEADR<1:0> = 00. At the same time,
all block writes to program memory are done as write
only operations. The program memory must first be
erased. The write operation is edge-aligned, and
cannot occur across boundaries.
instruction,
if
After
the
“BSF EECON1,WR”
EEADR = xxxxxx11, then a short write will occur. This
short write only transfers the data to the buffer register.
The WR bit will be cleared in hardware after 1 cycle.
The core will not halt and there will be no EEWHLT
signal generated.
instruction,
if
After
the
“BSF EECON1,WR”
EEADR = xxxxxx11, then a long write will occur. This
will simultaneously transfer the data from
EEDATH:EEDATA to the buffer registers and begin the
write of all four words. The processor will execute the
next instruction and then ignore the subsequent
instruction. The user should place NOP instructions into
the second words. The processor will then halt internal
operations for typically 2 msec in which the write takes
place. This is not a SLEEP mode, as the clocks and
peripherals will continue to run. After the write cycle,
the processor will resume operation with the 3rd
instruction after the EECON1 write instruction.
To write to the program memory, the data must first be
loaded into the buffer registers. There are four 14-bit
buffer registers and they are addressed by the low
2 bits of EEADR.
Loading data into the buffer registers is accomplished
via the EEADR, EEADT, EECON1 and EECON2
registers as follows:
•
•
•
•
•
After each long write, the 4 buffer registers will be reset
to 3FFF.
Set EECON1 PGD, and WREN
Write address to EEADRH:EEADR
Write data to EEDATA:EEDATH
Write 55, AA to EECON2
Set WR bit in EECON1
FIGURE 3-1:
BLOCK WRITES TO FLASH PROGRAM MEMORY
7
5
0
0 7
EEDATH
EEDATA
6
8
14
14
All buffers are
transferred
to FLASH
automatically
after this word
is written
First word of block
to be written
14
EEADR<1:0>
= ‘00’
Buffer Register
EEADR<1:0>
= ‘01’
EEADR<1:0>
= ‘10’
Buffer Register
Buffer Register
14
EEADR<1:0>
= ‘11’
Buffer Register
Program Memory
DS39598C-page 30
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
An example of the complete four-word write sequence
is shown in Example 3-5. The initial address is loaded
into the EEADRH:EEADR register pair; the four words
of data are loaded using indirect addressing, assuming
that a row erase sequence has already been
performed.
EXAMPLE 3-5:
WRITING TO FLASH PROGRAM MEMORY
; This write routine assumes the following:
;
;
;
;
;
;
1.
2.
3.
4.
5.
6.
The 32 words in the erase block have already been erased.
A valid starting address (the least significant bits = '00') is loaded into EEADRH:EEADR
This example is starting at 0x100, this is an application dependent setting.
The 8 bytes (4 words) of data are loaded, starting at an address in RAM called ARRAY.
This is an example only, location of data to program is application dependent.
word_block is located in data memory.
BANKSEL EECON1
BSF
EECON1,EEPGD
BSF
EECON1,WREN
;prepare for WRITE procedure
;point to program memory
;allow write cycles
BANKSEL word_block
MOVLW
.4
MOVWF
word_block
;prepare for 4 words to be written
BANKSEL
MOVLW
MOVWF
MOVLW
MOVWF
BANKSEL
MOVLW
MOVWF
EEADRH
0x01
EEADRH
0x00
EEADR
ARRAY
ARRAY
FSR
BANKSEL
MOVF
MOVWF
INCF
MOVF
MOVWF
INCF
EEDATA
INDF,W
EEDATA
FSR,F
INDF,W
EEDATH
FSR,F
BANKSEL
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
NOP
EECON1
0x55
EECON2
0xAA
EECON2
EECON1,WR
BANKSEL
INCF
BANKSEL
DECFSZ
GOTO
EEADR
EEADR,f
word_block
word_block,f
loop
;Start writing at 0x100
;load HIGH address
;load LOW address
;initialize FSR to start of data
Required
Sequence
LOOP
BANKSEL EECON1
BCF
EECON1,WREN
BSF
INTCON,GIE
 2002 Microchip Technology Inc.
;indirectly load EEDATA
;increment data pointer
;indirectly load EEDATH
;increment data pointer
;required sequence
;set WR bit to begin write
;instructions here are ignored as processor
;load next word address
;have 4 words been written?
;NO, continue with writing
;YES, 4 words complete, disable writes
;enable interrupts
Preliminary
DS39598C-page 31
PIC16F818/819
3.8
Protection Against Spurious Write
3.9
There are conditions when the device should not write
to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been
built-in. On power-up, WREN is cleared. Also, the
Power-up Timer (72 ms duration) prevents an
EEPROM write.
When the data EEPROM is code protected, the microcontroller can read and write to the EEPROM normally.
However, all external access to the EEPROM is disabled. External write access to the program memory is
also disabled.
When program memory is code protected, the microcontroller can read and write to program memory normally, as well as execute instructions. Writes by the
device may be selectively inhibited to regions of the
memory, depending on the setting of bits WRT1:WRT0
of the configuration word (see Section 12.1 for additional information). External access to the memory is
also disabled.
The write initiate sequence and the WREN bit together,
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
TABLE 3-1:
Address
Operation During Code Protect
REGISTERS/BITS ASSOCIATED WITH DATA EEPROM AND
FLASH PROGRAM MEMORIES
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
Power-on
Reset
Value on
all other
RESETS
10Ch
EEDATA EEPROM/FLASH Data Register Low Byte
xxxx xxxx uuuu uuuu
10Dh
EEADR
xxxx xxxx uuuu uuuu
10Eh
EEDATH
—
—
10Fh
EEADRH
—
—
—
—
—
—
—
FREE
WRERR
EEPROM/FLASH Address Register Low Byte
EEPROM/FLASH Data Register High Byte
--xx xxxx --uu uuuu
EEPROM/FLASH Address
Register High Byte
WREN
18Ch
EECON1 EEPGD
18Dh
EECON2 EEPROM Control Register2 (not a physical register)
0Dh
PIR2
—
—
—
EEIF
—
8Dh
PIE2
—
—
—
EEIE
—
---- -xxx ---- -uuu
WR
RD
x--x x000 x--x q000
—
—
—
---0 ---- ---0 ----
—
—
—
---0 ---- ---0 ----
---- ---- ---- ----
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0', q = value depends upon condition.
Shaded cells are not used by Data EEPROM or FLASH Program Memory.
DS39598C-page 32
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
4.0
OSCILLATOR
CONFIGURATIONS
4.1
Oscillator Types
TABLE 4-1:
The PIC16F818/819 can be operated in eight different
Oscillator modes. The user can program three configuration bits (FOSC2:FOSC0) to select one of these eight
modes (modes 5 - 8 are new PIC16 oscillator
configurations):
1.
2.
3.
4.
LP
XT
HS
RC
5.
RCIO
6.
INTIO1
7.
INTIO2
8.
ECIO
4.2
Low Power Crystal
Crystal/Resonator
High Speed Crystal/Resonator
External Resistor/Capacitor with
FOSC/4 output on RA6
External Resistor/Capacitor with
I/O on RA6
Internal Oscillator with FOSC/4
output on RA6 and I/O on RA7
Internal Oscillator with I/O on RA6
and RA7
External Clock with I/O on RA6
HS
32 kHz
33 pF
33 pF
200 kHz
15 pF
15 pF
200 kHz
56 pF
56 pF
1 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
4 MHz
15 pF
15 pF
8 MHz
15 pF
15 pF
20 MHz
15 pF
15 pF
Note 1: Higher capacitance increases the stability
of oscillator, but also increases the
start-up time.
2: Since each crystal has its own characteristics, the user should consult the crystal
manufacturer for appropriate values of
external components.
SLEEP
3: Rs may be required in HS mode, as well
as XT mode, to avoid overdriving crystals
with low drive level specification.
4: Always verify oscillator performance over
the VDD and temperature range that is
expected for the application.
OSC2
C2(1)
C2
See the notes following this table for additional
information.
PIC16F818/819
RF(3)
C1
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
(1)
XTAL
Typical Capacitor Values
Tested:
These capacitors were tested with the crystals listed
below for basic start-up and operation. These values
were not optimized.
CRYSTAL OPERATION
(HS, XT, OR LP OSC
CONFIGURATION)
OSC1
Crystal
Freq
Capacitor values are for design guidance only.
In XT, LP or HS modes, a crystal or ceramic resonator
is connected to the OSC1/CLKI and OSC2/CLKO pins
to establish oscillation (see Figure 4-1 and Figure 4-2).
The PIC16F818/819 oscillator design requires the use
of a parallel cut crystal. Use of a series cut crystal may
give a frequency out of the crystal manufacturers
specifications.
C1
LP
XT
Crystal Oscillator/Ceramic
Resonators
FIGURE 4-1:
Osc Type
CAPACITOR SELECTION FOR
CRYSTAL OSCILLATOR
(FOR DESIGN GUIDANCE
ONLY)
RS(2)
To Internal
Logic
Note 1: See Table 4-1 for typical values of C1 and
C2.
2: A series resistor (RS) may be required for AT
strip cut crystals.
3: RF varies with the crystal chosen (typically
between 2 MΩ to 10 MΩ).
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 33
PIC16F818/819
FIGURE 4-2:
CERAMIC RESONATOR
OPERATION (HS OR XT
OSC CONFIGURATION)
OSC1
PIC16F818/819
C1(1)
RES
RF(3)
RS
External Clock Input
The ECIO Oscillator mode requires an external clock
source to be connected to the OSC1 pin. There is no
oscillator start-up time required after a Power-on
Reset, or after an exit from SLEEP mode.
In the ECIO Oscillator mode, the OSC2 pin becomes
an additional general purpose I/O pin. The I/O pin
becomes bit 6 of PORTA (RA6). Figure 4-3 shows the
pin connections for the ECIO Oscillator mode.
SLEEP
OSC2
C2(1)
4.3
(2)
To Internal
Logic
FIGURE 4-3:
EXTERNAL CLOCK INPUT
OPERATION
(ECIO CONFIGURATION)
Note 1: See Table 4-2 for typical values of C1 and
C2.
2: A series resistor (RS) may be required.
3: RF varies with the resonator chosen
(typically between 2 MΩ to 10 MΩ).
OSC1/CLKI
Clock from
Ext. System
PIC16F818/819
RA6
TABLE 4-2:
I/O (OSC2)
CERAMIC RESONATORS
(FOR DESIGN GUIDANCE
ONLY)
Typical Capacitor Values Used:
Mode
Freq
OSC1
OSC2
XT
455 kHz
2.0 MHz
4.0 MHz
56 pF
47 pF
33 pF
56 pF
47 pF
33 pF
HS
8.0 MHz
16.0 MHz
27 pF
22 pF
27 pF
22 pF
Capacitor values are for design guidance only.
These capacitors were tested with the resonators
listed below for basic start-up and operation. These
values were not optimized.
Different capacitor values may be required to produce
acceptable oscillator operation. The user should test
the performance of the oscillator over the expected
VDD and temperature range for the application.
See the notes following this table for additional
information.
Note:
When using resonators with frequencies
above 3.5 MHz, the use of HS mode,
rather than XT mode, is recommended. HS
mode may be used at any VDD for which
the controller is rated. If HS is selected, it is
possible that the gain of the oscillator will
overdrive the resonator. Therefore, a
series resistor should be placed between
the OSC2 pin and the resonator. As a good
starting point, the recommended value of
RS is 330Ω.
DS39598C-page 34
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
4.4
RC Oscillator
4.5
For timing insensitive applications, the “RC” and
“RCIO” device options offer additional cost savings.
The RC oscillator frequency is a function of the supply
voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this,
the oscillator frequency will vary from unit to unit due to
normal manufacturing variation. Furthermore, the difference in lead frame capacitance between package
types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take
into account variation due to tolerance of external R
and C components used. Figure 4-4 shows how the
R/C combination is connected.
In the RC Oscillator mode, the oscillator frequency
divided by 4 is available on the OSC2 pin. This signal may
be used for test purposes or to synchronize other logic.
FIGURE 4-4:
RC OSCILLATOR MODE
VDD
REXT
OSC1
The PIC16F818/819 devices include an internal oscillator block, which generates two different clock signals;
either can be used as the system’s clock source. This
can eliminate the need for external oscillator circuits on
the OSC1 and/or OSC2 pins.
The main output (INTOSC) is an 8 MHz clock source,
which can be used to directly drive the system clock. It
also drives the INTOSC postscaler, which can provide
a range of clock frequencies from 125 kHz to 4 MHz.
The other clock source is the internal RC oscillator
(INTRC), which provides a 31.25 kHz (32 µs nominal
period) output. The INTRC oscillator is enabled by
selecting the INTRC as the system clock source, or
when any of the following are enabled:
• Power-up Timer
• Watchdog Timer
These features are discussed in greater detail in
Section 12.0, “Special Features of the CPU”.
The clock source frequency (INTOSC direct, INTRC
direct, or INTOSC postscaler) is selected by configuring
the IRCF bits of the OSCCON register (page 38).
Internal
Clock
Note:
CEXT
PIC16F818/819
VSS
OSC2/CLKO
FOSC/4
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20 pF
The RCIO Oscillator mode (Figure 4-5) functions like
the RC mode, except that the OSC2 pin becomes an
additional general purpose I/O pin. The I/O pin
becomes bit 6 of PORTA (RA6).
FIGURE 4-5:
Internal Oscillator Block
Throughout this data sheet, when referring
specifically to a generic clock source, the
term “INTRC” may also be used to refer to
the Clock modes using the internal oscillator block. This is regardless of whether the
actual frequency used is INTOSC (8 MHz),
the INTOSC postscaler, or INTRC
(31.25 kHz).
RCIO OSCILLATOR MODE
VDD
REXT
OSC1
Internal
Clock
CEXT
PIC16F818/819
VSS
RA6
I/O (OSC2)
Recommended values: 3 kΩ ≤ REXT ≤ 100 kΩ
CEXT > 20 pF
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 35
PIC16F818/819
4.5.1
INTRC MODES
4.5.2
Using the internal oscillator as the clock source can
eliminate the need for up to two external oscillator pins,
which can then be used for digital I/O. Two distinct
configurations are available:
• In INTIO1 mode, the OSC2 pin outputs FOSC/4,
while OSC1 functions as RA7 for digital input and
output.
• In INTIO2 mode, OSC1 functions as RA7 and
OSC2 functions as RA6, both for digital input and
output.
REGISTER 4-1:
U-0
—
When the OSCTUNE register is modified, the INTOSC
frequency will begin shifting to the new frequency. The
INTOSC clock will reach the new frequency within
8 clock cycles (approximately 8 * 32 µs = 256 µs).
Code execution continues during this shift; there is no
indication that the shift has occurred. Operation of features that depend on the 31.25 kHz INTRC clock
source frequency, such as the WDT and peripherals,
will also be affected by the change in frequency.
R/W-0
TUN5
R/W-0
TUN4
R/W-0
TUN3
R/W-0
TUN2
R/W-0
TUN1
R/W-0
TUN0
bit 0
Unimplemented: Read as ‘0’
TUN<5:0>: Frequency Tuning bits
011111 = Maximum frequency
011110 =
•
•
•
000001 =
000000 = Center frequency. Oscillator Module is running at the calibrated frequency.
111111 =
•
•
•
100000 = Minimum frequency
Legend:
R = Readable bit
-n = Value at POR
DS39598C-page 36
The internal oscillator’s output has been calibrated at
the factory, but can be adjusted in the user's application. This is done by writing to the OSCTUNE register
(Register 4-1). The tuning sensitivity is constant
throughout the tuning range. See Section 15.0
(“Electrical Characteristics”) for further details.
OSCTUNE: OSCILLATOR TUNING REGISTER
U-0
—
bit 7
bit 7-6
bit 5-0
OSCTUNE REGISTER
W = Writable bit
‘1’ = Bit is set
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
 2002 Microchip Technology Inc.
PIC16F818/819
4.5.3
OSCILLATOR CONTROL REGISTER
4.5.5
The OSCCON register (Register 4-2) controls several
aspects of the system clock’s operation.
The Internal Oscillator Select bits, IRCF2:IRCF0, select
the frequency output of the internal oscillator block that
is used to drive the system clock. The choices are the
INTRC source (31.25 kHz), the INTOSC source
(8 MHz), or one of the six frequencies derived from the
INTOSC postscaler (125 kHz to 4 MHz). Changing the
configuration of these bits has an immediate change on
the internal oscillator’s output.
4.5.4
The following sequence is performed when the IRCF
bits are changed and the system clock is the internal
oscillator.
1.
2.
3.
MODIFYING THE IRCF BITS
The IRCF bits can be modified at any time, regardless
of which clock source is currently being used as the
system clock. The internal oscillator allows users to
change the frequency during run time. This is achieved
by modifying the IRCF bits in the OSCCON register.
The sequence of events that occur after the IRCF bits
are modified is dependent upon the initial value of the
IRCF bits before they are modified. The system clock,
in either case, will switch to the new internal oscillator
frequency after eight falling edges of the new clock. If
the INTRC (31.25 kHz) is running and the IRCF bits are
modified to any of the other high frequency values, a
1 ms clock switch delay is turned on. Code execution
continues at a higher than expected frequency while
the new frequency stabilizes. Time sensitive code
should wait for the IOFS bit in the OSCCON register to
become set before continuing. The user can monitor
this bit to ensure that the frequency is stable before
using the system clock in time critical applications.
CLOCK TRANSITION SEQUENCE
WHEN THE IRCF BITS ARE
MODIFIED
4.
5.
The IRCF bits are modified.
The clock switching circuitry waits for a falling
edge of the current clock, at which point CLKO
is held low.
The clock switching circuitry then waits for eight
falling edges of requested clock, after which it
switches CLKO to this new clock source.
If the INTRC (31.25 kHz) is enabled, the IOFS
bit is clear to indicate that the clock is unstable
and a 1 ms delay is started. If the internal oscillator frequency is anything other than INTRC
(31.25 kHz), this step is skipped. After the
appropriate number of clock periods have
passed, the IOFS bit is set to indicate to the
internal oscillator that the frequency is stable.
Oscillator switch over is complete.
If the IRCF bits are modified while the internal oscillator
is running at any other frequency than INTRC
(31.25 kHz), there is no need for a 1 ms clock switch
delay. The new INTOSC frequency will be stable immediately after the eight falling edges. The IOFS bit will
remain set after clock switching occurs.
Caution must be taken when modifying the IRCF bits
using BCF or BSF instructions. It is possible to modify
the IRCF bits to a frequency that may be out of the VDD
specification range; for example, VDD = 2.0V and
IRCF = 111 (8 MHz).
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 37
PIC16F818/819
FIGURE 4-6:
PIC16F818/819 CLOCK DIAGRAM
PIC18F818/819
CONFIG (FOSC2:FOSC0)
OSC2
SLEEP
LP, XT, HS, RC, EC
OSCCON<6:4>
4 MHz
Internal
Oscillator
Block
8 MHz
(INTOSC)
bit 3
bit 2
bit 1-0
31.25 kHz
R/W-0
IRCF2
CPU
101
100
011
010
001
000
WDT
R/W-0
IRCF1
R/W-0
IRCF0
U-0
—
R-0
IOFS
U-0
—
U-0
—
bit 0
Unimplemented: Read as ‘0’
IRCF2:IRCF0: Internal Oscillator Frequency Select bits
111 = 8 MHz (8 MHz source drives clock directly)
110 = 4 MHz
101 = 2 MHz
100 = 1 MHz
011 = 500 kHz
010 = 250 kHz
001 = 125 kHz
000 = 31.25 kHz (INTRC source drives clock directly)
Unimplemented: Read as ‘0’
IOFS: INTOSC Frequency Stable bit
1 = Frequency is stable
0 = Frequency is not stable
Unimplemented: Read as ‘0’
Legend:
R = Readable bit
- n = Value at POR
DS39598C-page 38
250 kHz
110
OSCCON REGISTER
U-0
—
bit 7
bit 7
bit 6-4
500 kHz
125 kHz
31.25 kHz
(INTRC)
REGISTER 4-2:
1 MHz
Postscaler
31.25 kHz
Source
2 MHz
111
MUX
8 MHz
Internal Oscillator
Peripherals
MUX
OSC1
W = Writable bit
‘1’ = Bit is set
Preliminary
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
 2002 Microchip Technology Inc.
PIC16F818/819
5.0
I/O PORTS
Pin RA4 is multiplexed with the Timer0 module clock
input and with analog input to become the RA4/AN4/
T0CKI pin. The RA4/AN4/T0CKI pin is a Schmitt
Trigger input and full CMOS output driver.
Some pins for these I/O ports are multiplexed with an
alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
Pin RA5 is multiplexed with the Master Clear module
input. The RA5/MCLR/VPP pin is a Schmitt Trigger
input.
Additional information on I/O ports may be found in the
PICmicro™ Mid-Range Reference Manual (DS33023).
5.1
Pin RA6 is multiplexed with the Oscillator module input
and External Oscillator output. Pin RA7 is multiplexed
with the Oscillator module input and External Oscillator
input. Pin RA6/OSC2/CLKO and pin RA7/OSC1/CLKI
are Schmitt Trigger inputs and full CMOS output drivers.
PORTA and the TRISA Register
PORTA is a 8-bit wide, bi-directional port. The corresponding data direction register is TRISA. Setting a
TRISA bit (= 1) will make the corresponding PORTA pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISA bit (= 0) will
make the corresponding PORTA pin an output (i.e., put
the contents of the output latch on the selected pin).
Note:
Pins RA<1:0> are multiplexed with analog inputs. Pins
RA<3:2> are multiplexed with analog inputs and VREF
inputs. Pins RA<3:0> have TTL inputs and full CMOS
output drivers.
EXAMPLE 5-1:
On a Power-on Reset, the pins
PORTA<4:0> are configured as analog
inputs and read as '0'.
BANKSEL PORTA
CLRF
PORTA
Reading the PORTA register, reads the status of the
pins, whereas writing to it will write to the port latch. All
write operations are read-modify-write operations.
Therefore, a write to a port implies that the port pins are
read, this value is modified, and then written to the port
data latch.
TABLE 5-1:
INITIALIZING PORTA
BANKSEL
MOVLW
MOVWF
MOVLW
ADCON1
0x06
ADCON1
0xFF
MOVWF
TRISA
;
;
;
;
;
;
;
;
;
;
;
select bank of PORTA
Initialize PORTA by
clearing output
data latches
Select Bank of ADCON1
Configure all pins
as digital inputs
Value used to
initialize data
direction
Set RA<7:0> as inputs
PORTA FUNCTIONS
Name
Bit#
Buffer
Function
RA0/AN0
bit 0
TTL
Input/output or analog input.
RA1/AN1
bit 1
TTL
Input/output or analog input.
RA2/AN2
bit 2
TTL
Input/output or analog input or VREF-.
RA3/AN3/VREF
bit 3
TTL
Input/output or analog input or VREF+.
RA4/AN4/T0CKI
bit 4
ST
Input/output, analog input or external clock input for Timer0.
RA5/MCLR/VPP
bit 5
ST
Input, Master Clear (Reset) or Programming voltage input.
RA6/OSC2/CLKO
bit 6
ST
Input/output, connects to Crystal or Resonator, Oscillator output, or 1/4 the
frequency of OSC1, and denotes the instruction cycle in RC mode.
RA7/OSC1/CLKI
bit 7
ST/CMOS(1) Input/output, connects to Crystal or Resonator or Oscillator input.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured in RC Oscillator mode and a CMOS input otherwise.
TABLE 5-2:
Address
SUMMARY OF REGISTERS ASSOCIATED WITH PORTA
Name
05h
PORTA(1)
85h
TRISA
9Fh
ADCON1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other RESETS
RA7
RA6
RA5
RA4
RA3
RA2
RA1
RA0
xxx0 0000
uuu0 0000
1111 1111
1111 1111
00-- 0000
00-- 0000
TRISA7 TRISA6 TRISA5 PORTA Data Direction Register
ADFM
ADCS2
—
—
PCFG3 PCFG2 PCFG1
PCFG0
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by PORTA.
Note 1: PORTA pin 5 is an input only, the state of the TRISA5 bit has no effect and will always read ‘1’.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 39
PIC16F818/819
FIGURE 5-1:
BLOCK DIAGRAM OF
RA0/AN0:RA1/AN1 PINS
FIGURE 5-3:
Data
Bus
Data
Bus
D
WR
PORTA
Q
CK
Q
D
WR
PORTA
VDD
VDD
P
CK
CK
Q
I/O pin
Analog
Input Mode
Q
N
WR
TRISA
CK
Q
I/O pin
VSS
VSS
Analog
Input Mode
VSS
TTL
Input Buffer
RD TRISA
Q
TRIS Latch
VSS
TRIS Latch
VDD
VDD
P
Q
D
Q
N
WR
TRISA
Q
Data Latch
Data Latch
D
BLOCK DIAGRAM OF
RA2/AN2/VREF- PIN
TTL
Input Buffer
RD TRISA
Q
D
D
EN
EN
RD PORTA
RD PORTA
To A/D Module VREF- Input
To A/D Module Channel Input
To A/D Module Channel Input
FIGURE 5-2:
Data
Bus
BLOCK DIAGRAM OF
RA3/AN3/VREF+ PIN
D
WR
PORTA
FIGURE 5-4:
Data
Bus
Q
CK
VDD
VDD
P
Q
D
WR
PORTA
Data Latch
D
WR
TRISA
CK
VDD
VDD
P
Q
D
I/O pin
N
Q
TRIS Latch
Q
Data Latch
Q
CK
BLOCK DIAGRAM OF
RA4/AN4/T0CKI PIN
WR
TRISA
VSS
Analog
Input Mode
VSS
Q
N
CK
Q
TRIS Latch
TTL
Input Buffer
RD TRISA
Q
Analog
Input Mode
RD TRISA
D
Schmitt Trigger
Input Buffer
D
EN
RD PORTA
RD PORTA
To A/D Module VREF+ Input
TMR0 Clock Input
To A/D Module Channel Input
To A/D Module Channel Input
DS39598C-page 40
VSS
VSS
Q
EN
I/O pin
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
FIGURE 5-5:
BLOCK DIAGRAM OF RA5/MCLR/VPP PIN
MCLRE
Schmitt Trigger
Buffer
MCLR Circuit
MCLR Filter
Data
Bus
RA5/MCLR/VPP
Schmitt Trigger
Input Buffer
RD TRIS VSS
Q
VSS
D
EN
MCLRE
RD Port
FIGURE 5-6:
BLOCK DIAGRAM OF RA6/OSC2/CLKO PIN
From OSC1 Oscillator
Circuit
CLKO (FOSC/4)
VDD
VDD
P
RA6/OSC2/CLKO
Data
Bus
D
WR
PORTA
VSS
N
(FOSC = 1x1)
Q
VSS
VDD
Q
CK
P
Data Latch
D
WR
TRISA
Q
N
CK
Q
(FOSC = 1x0,011)
TRIS Latch
VSS
Schmitt Trigger
Input Buffer
RD TRISA
Q
D
EN
RD PORTA
(FOSC = 1x0,011)
Note 1: I/O pins have protection diodes to VDD and VSS.
2: CLKO signal is 1/4 of the FOSC frequency.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 41
PIC16F818/819
FIGURE 5-7:
BLOCK DIAGRAM OF RA7/OSC1/CLKI PIN
From OSC2
Oscillator
Circuit
VDD
(FOSC = 011)
Data
Bus
D
WR
PORTA
CK
Q
VDD
Q
P
RA7/OSC1/CLKI
VSS
Data Latch
D
WR
TRISA
Q
CK
N
Q
FOSC = 10x
TRIS Latch
VSS
Schmitt Trigger
Input Buffer
RD TRISA
Q
D
EN
FOSC = 10x
RD PORTA
Note 1: I/O pins have protection diodes to VDD and VSS.
DS39598C-page 42
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
5.2
PORTB and the TRISB Register
PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a Hi-Impedance mode). Clearing a TRISB bit (= 0) will
make the corresponding PORTB pin an output (i.e., put
the contents of the output latch on the selected pin).
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (OPTION<7>). The weak
pull-up is automatically turned off when the port pin is
configured as an output. The pull-ups are disabled on a
Power-on Reset.
Four of PORTB’s pins, RB7:RB4, have an interrupt-onchange feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupton-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’d together to generate the RB Port Change
Interrupt with flag bit RBIF (INTCON<0>).
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
RB0/INT is an external interrupt input pin and is
configured using the INTEDG bit (OPTION<6>).
PORTB is multiplexed with several peripheral functions
(see Table 5-3). PORTB pins have Schmitt Trigger
input buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTB pin. Some
peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modifywrite instructions (BSF, BCF, XORWF) with TRISB as
destination should be avoided. The user should refer to
the corresponding peripheral section for the correct
TRIS bit settings.
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 43
PIC16F818/819
TABLE 5-3:
PORTB FUNCTIONS
Name
Bit#
Buffer
Function
TTL/ST(1) Input/output pin or external interrupt input.
Internal software programmable weak pull-up.
(5)
Input/output pin, SPI Data input pin or I2C Data I/O pin.
RB1/SDI/SDA
bit 1 TTL/ST
Internal software programmable weak pull-up.
(4)
Input/output
pin, SPI Data output pin or
RB2/SDO/CCP1
bit 2 TTL/ST
Capture input/Compare output/PWM output pin.
Internal software programmable weak pull-up.
bit 3 TTL/ST(2) Input/output pin, Capture input/Compare output/PWM output pin
RB3/CCP1/PGM(3)
or programming in LVP mode. Internal software programmable
weak pull-up.
RB4/SCK/SCL
bit 4 TTL/ST(5) Input/output pin or SPI and I2C clock pin (with interrupt-on-change).
Internal software programmable weak pull-up.
RB5/SS
bit 5
TTL
Input/output pin or SPI Slave select pin (with interrupt-on-change).
Internal software programmable weak pull-up.
RB6/T1OSO/T1CKI/
bit 6 TTL/ST(2) Input/output pin, Timer1 Oscillator output pin, Timer1 Clock input pin or
PGC
Serial Programming Clock (with interrupt-on-change).
Internal software programmable weak pull-up.
RB7/T1OSI/PGD
bit 7 TTL/ST(2) Input/output pin, Timer1 Oscillator input pin or
Serial Programming Data (with interrupt-on-change).
Internal software programmable weak pull-up.
Legend: TTL = TTL input, ST = Schmitt Trigger input
Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt.
2: This buffer is a Schmitt Trigger input when used in Serial Programming mode.
3: Low Voltage ICSP Programming (LVP) is enabled by default, which disables the RB3 I/O function. LVP must
be disabled to enable RB3 as an I/O pin and allow maximum compatibility to the other 18-pin mid-range
devices.
4: This buffer is a Schmitt Trigger input when configured for CCP or SSP mode.
5: This buffer is a Schmitt Trigger input when configured for SPI or I2C mode.
RB0/INT
bit 0
TABLE 5-4:
SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Value on
all other
RESETS
06h, 106h
PORTB
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
xxxx xxxx
uuuu uuuu
1111 1111
1111 1111
PSA
PS2
PS1
PS0
1111 1111
1111 1111
86h, 186h
TRISB
PORTB Data Direction Register
81h, 181h
OPTION
RBPU
INTEDG
T0CS T0SE
Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB.
DS39598C-page 44
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
FIGURE 5-8:
BLOCK DIAGRAM OF RB0 PIN
VDD
RBPU(2)
Weak
P Pull-up
Data Latch
D
Q
Data Bus
WR
PORTB
I/O pin(1)
CK
TRIS Latch
D
Q
WR
TRISB
TTL
Input
Buffer
CK
RD TRISB
Q
RD PORTB
D
EN
To INT0 or CCP
RD PORTB
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 45
PIC16F818/819
FIGURE 5-9:
BLOCK DIAGRAM OF RB1 PIN
I2C Mode
PORT/SSPEN Select
SDA Output
1
0
VDD
RBPU(2)
Data Bus
WR
PORTB
Weak
P Pull-up
VDD
Data Latch
D
Q
P
CK
N
I/O pin(1)
VSS
TRIS Latch
D
Q
WR
TRISB
CK
Q
RD TRISB
TTL
Input
Buffer
SDA Drive
Q
RD PORTB
D
EN
Schmitt Trigger
Buffer
RD PORTB
SDA(3)
SDI
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
3: The SDA Schmitt conforms to the I2C specification.
DS39598C-page 46
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
FIGURE 5-10:
BLOCK DIAGRAM OF RB2 PIN
CCPMX
Module Select
SDO
0
0
CCP
1
1
VDD
RBPU(2)
Data Bus
WR
PORTB
WR
TRISB
Weak
P Pull-up
Data Latch
D
Q
I/O pin(1)
CK
TRIS Latch
D
Q
TTL
Input
Buffer
CK
RD TRISB
D
Q
RD PORTB
EN
RD PORTB
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 47
PIC16F818/819
FIGURE 5-11:
BLOCK DIAGRAM OF RB3 PIN
CCP1<M3:M0> = 1000,1001,11xx and CCPMX = 0
CCP1<M3:M0> = 0100, 0101, 0110, 0111 and CCPMX = 0
CCP
0
or LVP = 1
1
VDD
RBPU(2)
Data Bus
WR
PORTB
WR
TRISB
Weak
P Pull-up
Data Latch
D
Q
I/O pin(1)
CK
TRIS Latch
D
Q
TTL
Input
Buffer
CK
RD TRISB
Q
RD PORTB
D
EN
To PGM or CCP
RD PORTB
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
DS39598C-page 48
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
FIGURE 5-12:
BLOCK DIAGRAM OF RB4 PIN
PORT/SSPEN
SCK/SCL
1
0
VDD
RBPU(2)
Weak
P Pull-up
VDD
SCL Drive
Data Bus
WR
PORTB
P
Data Latch
D
Q
I/O pin(1)
N
CK
TRIS Latch
WR
TRISB
D
VSS
Q
CK
TTL
Input
Buffer
RD TRISB
Latch
Q
Set RBIF
D
EN
RD PORTB
Q
From Other
RB7:RB4 pins
D
EN
Q1
RD PORTB
Q3
SCK
SCL(3)
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
3: The SCL Schmitt conforms to the I2C specification.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 49
PIC16F818/819
FIGURE 5-13:
BLOCK DIAGRAM OF RB5 PIN
RBPU(2)
VDD
PORT/SSPEN
Weak
P Pull-up
Data Latch
Data Bus
D
WR
PORTB
Q
I/O pin(1)
CK
TRIS Latch
D
WR
TRISB
Q
CK
TTL
Input
Buffer
RD TRISB
Latch
Q
EN
RD PORTB
Set RBIF
D
Q
From Other
RB7:RB4 pins
D
EN
Q1
RD PORTB
Q3
SS
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
DS39598C-page 50
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
FIGURE 5-14:
BLOCK DIAGRAM OF RB6 PIN
VDD
RBPU(2)
Data Bus
WR
PORTB
Weak
P Pull-up
Data Latch
D
Q
I/O pin(1)
CK
TRIS Latch
WR
TRISB
D
Q
CK
T1OSCEN
RD TRISB
T1OSCEN/ICD/PROG Mode
TTL
Input Buffer
Latch
Q
D
EN
RD PORTB
Q1
Set RBIF
Q
From Other
RB7:RB4 pins
D
EN
RD PORTB
Q3
PGC/T1CKI
From T1OSCO Output
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 51
PIC16F818/819
FIGURE 5-15:
BLOCK DIAGRAM OF RB7 PIN
PORT/Program Mode/ICD
PGD
1
0
VDD
RBPU(2)
Weak
P Pull-up
Data Latch
Data Bus
D
WR
PORTB
Q
I/O pin(1)
CK
TRIS Latch
D
WR
TRISB
Q
0
CK
1
RD TRISB
T1OSCEN
T1OSCEN
Analog
Input Mode
PGD DRVEN
TTL
Input Buffer
Latch
Q
D
EN
RD PORTB
Q1
Set RBIF
Q
From Other
RB7:RB4 pins
D
EN
RD PORTB
Q3
PGD
To T1OSCI Input
Note 1: I/O pins have diode protection to VDD and VSS.
2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
DS39598C-page 52
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
6.0
TIMER0 MODULE
increment is inhibited for the following two instruction
cycles. The user can work around this by writing an
adjusted value to the TMR0 register.
The Timer0 module timer/counter has the following
features:
•
•
•
•
•
•
Counter mode is selected by setting bit T0CS
(OPTION<5>). In Counter mode, Timer0 will increment, either on every rising or falling edge of pin RA4/
T0CKI. The incrementing edge is determined by the
Timer0 Source Edge Select bit T0SE (OPTION<4>).
Clearing bit T0SE selects the rising edge. Restrictions
on the external clock input are discussed in detail in
Section 6.3.
8-bit timer/counter
Readable and writable
8-bit software programmable prescaler
Internal or external clock select
Interrupt on overflow from FFh to 00h
Edge select for external clock
Additional information on the Timer0 module is
available in the PICmicro™ Mid-Range MCU Family
Reference Manual (DS33023).
The prescaler is mutually exclusively shared between
the Timer0 module and the Watchdog Timer. The prescaler is not readable or writable. Section 6.4 details the
operation of the prescaler.
Figure 6-1 is a block diagram of the Timer0 module and
the prescaler shared with the WDT.
6.1
6.2
Timer0 Operation
The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h. This overflow sets bit
TMR0IF (INTCON<2>). The interrupt can be masked
by clearing bit TMR0IE (INTCON<5>). Bit TMR0IF
must be cleared in software by the Timer0 module
Interrupt Service Routine, before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor
from SLEEP, since the timer is shut-off during SLEEP.
Timer0 operation is controlled through the OPTION
register (see Register 2-2). Timer mode is selected by
clearing bit T0CS (OPTION<5>). In Timer mode, the
Timer0 module will increment every instruction cycle
(without prescaler). If the TMR0 register is written, the
FIGURE 6-1:
Timer0 Interrupt
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
CLKO (= FOSC/4)
Data Bus
0
RA4/T0CKI
pin
1
T0SE
M
U
X
8
1
M
U
X
0
T0CS
SYNC
2
Cycles
TMR0 reg
Set Flag bit TMR0IF
on Overflow
PSA
PRESCALER
0
M
U
X
WDT Timer
1
31.25 kHz
8-bit Prescaler
8
8 - to - 1MUX
WDT Enable bit
PS2:PS0
PSA
1
0
MUX
PSA
WDT
Time-out
Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION<5:0>).
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 53
PIC16F818/819
6.3
Using Timer0 with an External
Clock
6.4
When no prescaler is used, the external clock input is
the same as the prescaler output. The synchronization
of T0CKI, with the internal phase clocks, is accomplished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T0CKI to be high for at least 2 TOSC (and
a small RC delay of 20 ns) and low for at least 2 TOSC
(and a small RC delay of 20 ns). Refer to the electrical
specification of the desired device.
There is only one prescaler available, which is mutually
exclusively shared between the Timer0 module and the
Watchdog Timer. A prescaler assignment for the
Timer0 module means that there is no prescaler for the
Watchdog Timer, and vice-versa. This prescaler is not
readable or writable (see Figure 6-1).
The PSA and PS2:PS0 bits (OPTION<3:0>) determine
the prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing to the TMR0 register (e.g., CLRF 1, MOVWF 1,
BSF
1,x....etc.) will clear the prescaler. When
assigned to WDT, a CLRWDT instruction will clear the
prescaler along with the Watchdog Timer. The
prescaler is not readable or writable.
Note:
REGISTER 6-1:
Prescaler
Writing to TMR0 when the prescaler is
assigned to Timer0, will clear the prescaler
count but will not change the prescaler
assignment.
OPTION_REG REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
bit 7
bit 0
bit 7
RBPU
bit 6
INTEDG
bit 5
T0CS: TMR0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (CLKO)
bit 4
T0SE: TMR0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
bit 3
PSA: Prescaler Assignment bit
1 = Prescaler is assigned to the WDT
0 = Prescaler is assigned to the Timer0 module
bit 2-0
PS2:PS0: Prescaler Rate Select bits
Bit Value TMR0 Rate WDT Rate
1:2
000
1:1
1:4
001
1:2
1:8
010
1:4
1 : 16
011
1:8
1 : 32
100
1 : 16
1 : 64
101
1 : 32
1 : 128
110
1 : 64
1 : 256
111
1 : 128
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Note:
DS39598C-page 54
x = Bit is unknown
To avoid an unintended device RESET, the instruction sequence shown in the
PICmicro™ Mid-Range MCU Family Reference Manual (DS33023) must be executed when changing the prescaler assignment from Timer0 to the WDT. This
sequence must be followed even if the WDT is disabled.
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
EXAMPLE 6-1:
BANKSEL
MOVLW
MOVWF
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
CLRWDT
MOVLW
MOVWF
CHANGING THE PRESCALER ASSIGNMENT FROM TIMER0 TO WDT
OPTION
b'xx0x0xxx'
OPTION
TMR0
TMR0
OPTION
b'xxxx1xxx'
OPTION
CHANGING THE PRESCALER ASSIGNMENT FROM WDT TO TIMER0
CLRWDT
BANKSEL OPTION
MOVLW
b'xxxx0xxx'
MOVWF
OPTION
TABLE 6-1:
01h,101h
;
;
;
;
Clear WDT and prescaler
Select Bank of OPTION
Select TMR0, new prescale
value and clock source
REGISTERS ASSOCIATED WITH TIMER0
Name
TMR0
0Bh,8Bh,
INTCON
10Bh,18Bh
81h,181h
Select Bank of OPTION
Select clock source and prescale value of
other than 1:1
Select Bank of TMR0
Clear TMR0 and prescaler
Select Bank of OPTION
Select WDT, do not change prescale value
; Clears WDT and prescaler
; Select new prescale value and WDT
b'xxxx1xxx'
OPTION
EXAMPLE 6-2:
Address
;
;
;
;
;
;
;
OPTION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timer0 Module Register
Value on
POR, BOR
Value on
all other
RESETS
xxxx xxxx
uuuu uuuu
GIE
PEIE
TMR0IE
INTE
RBIE TMR0IF INTF RBIF 0000 000x
0000 000u
RBPU
INTEDG
T0CS
T0SE
PSA
1111 1111
PS2
PS1
PS0
1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’. Shaded cells are not used by Timer0.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 55
PIC16F818/819
NOTES:
DS39598C-page 56
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
7.0
TIMER1 MODULE
The Timer1 module is a 16-bit timer/counter consisting
of two 8-bit registers (TMR1H and TMR1L), which are
readable and writable. The TMR1 Register pair
(TMR1H:TMR1L) increments from 0000h to FFFFh
and rolls over to 0000h. The TMR1 Interrupt, if enabled,
is generated on overflow, which is latched in interrupt
flag bit TMR1IF (PIR1<0>). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt
enable bit TMR1IE (PIE1<0>).
Timer1 can also be used to provide real-time clock
(RTC) functionality to applications with only a minimal
addition of external components or code overhead.
7.1
Timer1 Operation
Timer1 can operate in one of three modes:
In Timer mode, Timer1 increments every instruction
cycle. In Counter mode, it increments on every rising
edge of the external clock input.
Timer1 can be enabled/disabled by setting/clearing
control bit TMR1ON (T1CON<0>).
Timer1 also has an internal “RESET input”. This
RESET can be generated by the CCP1 module as the
special event trigger (see Section 9.1). Register 7-1
shows the Timer1 Control register.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RB6/T1OSO/T1CKI/PGC and RB7/T1OSI/
PGD pins become inputs. That is, the TRISB<7:6>
value is ignored and these pins read as ‘0’.
Additional information on timer modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023).
• as a timer
• as a synchronous counter
• as an asynchronous counter
REGISTER 7-1:
The Operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h)
U-0
U-0
R/W-0
R/W-0
—
—
T1CKPS1
T1CKPS0
R/W-0
R/W-0
R/W-0
R/W-0
T1OSCEN T1SYNC TMR1CS TMR1ON
bit 7
bit 0
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits
11 = 1:8 Prescale value
10 = 1:4 Prescale value
01 = 1:2 Prescale value
00 = 1:1 Prescale value
bit 3
T1OSCEN: Timer1 Oscillator Enable Control bit
1 = Oscillator is enabled
0 = Oscillator is shut-off (the oscillator inverter is turned off to eliminate power drain)
bit 2
T1SYNC: Timer1 External Clock Input Synchronization Control bit
TMR1CS = 1:
1 = Do not synchronize external clock input
0 = Synchronize external clock input
TMR1CS = 0:
This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0.
bit 1
TMR1CS: Timer1 Clock Source Select bit
1 = External clock from pin RB6/T1OSO/T1CKI/PGC (on the rising edge)
0 = Internal clock (FOSC/4)
bit 0
TMR1ON: Timer1 On bit
1 = Enables Timer1
0 = Stops Timer1
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
 2002 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS39598C-page 57
PIC16F818/819
7.2
Timer1 Operation in Timer Mode
7.4
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is FOSC/4. The synchronize control bit T1SYNC
(T1CON<2>) has no effect, since the internal clock is
always in sync.
7.3
Counter mode is selected by setting bit TMR1CS. In
this mode, the timer increments on every rising edge of
clock input on pin RB7/T1OSI/PGD, when bit
T1OSCEN is set, or on pin RB6/T1OSO/T1CKI/PGC,
when bit T1OSCEN is cleared.
Timer1 Counter Operation
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchronization is done after the prescaler stage. The
prescaler stage is an asynchronous ripple counter.
Timer1 may operate in Asynchronous or Synchronous
mode, depending on the setting of the TMR1CS bit.
When Timer1 is being incremented via an external
source, increments occur on a rising edge. After Timer1
is enabled in Counter mode, the module must first have
a falling edge before the counter begins to increment.
FIGURE 7-1:
Timer1 Operation in Synchronized
Counter Mode
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut-off. The
prescaler however, will continue to increment.
TIMER1 INCREMENTING EDGE
T1CKI
(Default High)
T1CKI
(Default Low)
Note: Arrows indicate counter increments.
FIGURE 7-2:
TIMER1 BLOCK DIAGRAM
Set Flag bit
TMR1IF on
Overflow
TMR1H
Synchronized
Clock Input
0
TMR1
TMR1L
1
T1OSC
TMR1ON
On/Off
T1SYNC
1
RB6/T1OSO/T1CKI/PGC
RB7/T1OSI/PGD
T1OSCEN FOSC/4
Enable
Internal
Oscillator(1) Clock
Synchronize
Prescaler
1, 2, 4, 8
det
0
2
T1CKPS1:T1CKPS0
TMR1CS
Q Clock
Note 1: When the T1OSCEN bit is cleared, the inverter is turned off. This eliminates power drain.
DS39598C-page 58
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
7.5
Timer1 Operation in
Asynchronous Counter Mode
7.5.1
If control bit T1SYNC (T1CON<2>) is set, the external
clock input is not synchronized. The timer continues to
increment asynchronous to the internal phase clocks.
The timer will continue to run during SLEEP and can
generate an interrupt on overflow, that will wake-up the
processor. However, special precautions in software
are needed to read/write the timer (Section 7.5.1).
In Asynchronous Counter mode, Timer1 cannot be
used as a time-base for capture or compare
operations.
READING AND WRITING TIMER1 IN
ASYNCHRONOUS COUNTER
MODE
Reading TMR1H or TMR1L while the timer is running
from an external asynchronous clock will ensure a valid
read (taken care of in hardware). However, the user
should keep in mind that reading the 16-bit timer in two
8-bit values itself, poses certain problems since the
timer may overflow between the reads.
For writes, it is recommended that the user simply stop
the timer and write the desired values. A write contention may occur by writing to the timer registers, while
the register is incrementing. This may produce an
unpredictable value in the timer register.
Reading the 16-bit value requires some care. The
example codes provided in Example 7-1 and
Example 7-2 demonstrate how to write to and read
Timer1 while it is running in Asynchronous mode.
EXAMPLE 7-1:
WRITING A 16-BIT FREE-RUNNING TIMER
; All interrupts are disabled
CLRF
TMR1L
; Clear Low byte, Ensures no rollover into TMR1H
MOVLW
HI_BYTE
; Value to load into TMR1H
MOVWF
TMR1H, F
; Write High byte
MOVLW
LO_BYTE
; Value to load into TMR1L
MOVWF
TMR1H, F
; Write Low byte
; Re-enable the Interrupt (if required)
CONTINUE
; Continue with your code
EXAMPLE 7-2:
READING A 16-BIT FREE-RUNNING TIMER
; All interrupts are disabled
MOVF
TMR1H, W
; Read high byte
MOVWF
TMPH
MOVF
TMR1L, W
; Read low byte
MOVWF
TMPL
MOVF
TMR1H, W
; Read high byte
SUBWF
TMPH, W
; Sub 1st read with 2nd read
BTFSC
STATUS,Z
; Is result = 0
GOTO
CONTINUE
; Good 16-bit read
; TMR1L may have rolled over between the read of the high and low bytes.
; Reading the high and low bytes now will read a good value.
MOVF
TMR1H, W
; Read high byte
MOVWF
TMPH
MOVF
TMR1L, W
; Read low byte
MOVWF
TMPL
; Re-enable the Interrupt (if required)
CONTINUE
; Continue with your code
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 59
PIC16F818/819
7.6
Timer1 Oscillator
7.7
A crystal oscillator circuit is built between pins T1OSI
(input) and T1OSO (amplifier output). It is enabled by
setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated up to 32.768 kHz. It
will continue to run during SLEEP. It is primarily
intended for a 32 kHz crystal. The circuit for a typical LP
oscillator is shown in Figure 7-3. Table 7-1 shows the
capacitor selection for the Timer1 oscillator.
The user must provide a software time delay to ensure
proper oscillator start-up.
FIGURE 7-3:
EXTERNAL COMPONENTS
FOR THE TIMER1 LP
OSCILLATOR
The Timer1 oscillator circuit draws very little power during operation. Due to the low power nature of the oscillator, it may also be sensitive to rapidly changing
signals in close proximity.
The oscillator circuit shown in Figure 7-3 should be
located as close as possible to the microcontroller.
There should be no circuits passing within the oscillator
circuit boundaries other than VSS or VDD.
If a high speed circuit must be located near the oscillator, a grounded guard ring around the oscillator circuit,
as shown in Figure 7-4, may be helpful when used on
a single sided PCB, or in addition to a ground plane.
FIGURE 7-4:
PIC16F818/819
C1
33 pF
T1OSI
XTAL
32.768 kHz
Note:
OSC1
OSC2
See the Notes with Table 7-1 for additional
information about capacitor selection.
TABLE 7-1:
OSCILLATOR CIRCUIT
WITH GROUNDED
GUARD RING
VSS
T1OSO
C2
33 pF
Timer1 Oscillator Layout
Considerations
RB7
CAPACITOR SELECTION FOR
THE TIMER1 OSCILLATOR
Osc Type
Freq
C1
C2
LP
32 kHz
33 pF
33 pF
RB6
RB5
Note 1: Microchip suggests this value as a starting
point in validating the oscillator circuit.
2: Higher capacitance increases the stability
of the oscillator, but also increases the
start-up time.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate
values
of
external
components.
4: Capacitor values are for design guidance
only.
7.8
Resetting Timer1 Using a CCP
Trigger Output
If the CCP1 module is configured in Compare mode to
generate
a
“special
event
trigger"
signal
(CCP1M3:CCP1M0 = 1011), the signal will reset
Timer1 and start an A/D conversion (if the A/D module
is enabled).
Timer1 must be configured for either Timer or Synchronized Counter mode to take advantage of this feature.
If Timer1 is running in Asynchronous Counter mode,
this RESET operation may not work.
In the event that a write to Timer1 coincides with a
special event trigger from CCP1, the write will take
precedence.
In this mode of operation, the CCPR1H:CCPR1L register pair effectively becomes the period register for
Timer1.
DS39598C-page 60
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
7.9
Resetting Timer1 Register Pair
(TMR1H, TMR1L)
7.11
TMR1H and TMR1L registers are not reset to 00h on a
POR, or any other RESET, except by the CCP1 special
event triggers.
T1CON register is reset to 00h on a Power-on Reset or
a Brown-out Reset, which shuts off the timer and
leaves a 1:1 prescale. In all other RESETS, the register
is unaffected.
7.10
Timer1 Prescaler
The prescaler counter is cleared on writes to the
TMR1H or TMR1L registers.
Using Timer1 as a Real-Time
Clock
Adding an external LP oscillator to Timer1 (such as the
one described in Section 7.6, above), gives users the
option to include RTC functionality to their applications.
This is accomplished with an inexpensive watch crystal
to provide an accurate time-base, and several lines of
application code to calculate the time. When operating
in SLEEP mode and using a battery or super capacitor
as a power source, it can completely eliminate the need
for a separate RTC device and battery backup.
The application code routine RTCisr, shown in
Example 7-3, demonstrates a simple method to increment a counter at one-second intervals using an Interrupt Service Routine. Incrementing the TMR1 register
pair to overflow triggers the interrupt and calls the routine, which increments the seconds counter by one;
additional counters for minutes and hours are
incremented as the previous counter overflow.
Since the register pair is 16-bits wide, counting up to
overflow the register directly from a 32.768 kHz clock
would take 2 seconds. To force the overflow at the
required one-second intervals, it is necessary to preload it; the simplest method is to set the MSbit of
TMR1H with a BSF instruction. Note that the TMR1L
register is never pre-loaded or altered; doing so may
introduce cumulative error over many cycles.
For this method to be accurate, Timer1 must operate in
Asynchronous mode, and the Timer1 Overflow Interrupt must be enabled (PIE1<0> = 1), as shown in the
routine RTCinit. The Timer1 oscillator must also be
enabled and running at all times.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 61
PIC16F818/819
EXAMPLE 7-3:
RTCinit
banksel
movlw
movwf
clrf
movlw
movwf
clrf
clrf
movlw
movwf
banksel
bsf
return
banksel
bsf
bcf
incf
movf
sublw
btfss
return
clrf
incf
movf
sublw
btfss
return
clrf
incf
movf
sublw
btfss
return
clrf
return
RTCisr
TABLE 7-2:
Address
IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE
TMR1H
0x80
TMR1H
TMR1L
b’00001111’
T1CON
secs
mins
.12
hours
PIE1
PIE1, TMR1IE
TMR1H
TMR1H,7
PIR1,TMR1IF
secs,F
secs,w
.60
STATUS,Z
; Preload TMR1 register pair
; for 1 second overflow
; Configure for external clock,
; Asynchronous operation, external oscillator
; Initialize timekeeping registers
; Enable Timer1 interrupt
; Preload for 1 sec overflow
; Clear interrupt flag
; Increment seconds
seconds
mins,f
mins,w
.60
STATUS,Z
mins
hours,f
hours,w
.24
STATUS,Z
hours
;
;
;
;
60 seconds elapsed?
No, done
Clear seconds
Increment minutes
;
;
;
;
60 seconds elapsed?
No, done
Clear minutes
Increment hours
;
;
;
;
24 hours elapsed?
No, done
Clear hours
Done
REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER
Name
0Bh,8Bh, INTCON
10Bh,18Bh
Value on
all other
RESETS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
PIR1
—
ADIF
—
—
SSPIF
CCP1IF
TMR2IF
TMR1IF -0-- 0000 -0-- 0000
8Ch
PIE1
—
ADIE
—
—
SSPIE
CCP1IE
TMR2IE
TMR1IE -0-- 0000 -0-- 0000
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
10h
T1CON
Legend:
—
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
DS39598C-page 62
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
8.0
TIMER2 MODULE
8.1
Timer2 is an 8-bit timer with a prescaler and a
postscaler. It can be used as the PWM time-base for
the PWM mode of the CCP1 module. The TMR2 register is readable and writable, and is cleared on any
device RESET.
The input clock (FOSC/4) has a prescale option of 1:1,
1:4
or
1:16,
selected
by
control
bits
T2CKPS1:T2CKPS0 (T2CON<1:0>).
The Timer2 module has an 8-bit period register, PR2.
Timer2 increments from 00h until it matches PR2 and
then resets to 00h on the next increment cycle. PR2 is
a readable and writable register. The PR2 register is
initialized to FFh upon RESET.
The match output of TMR2 goes through a 4-bit
postscaler (which gives a 1:1 to 1:16 scaling inclusive)
to generate a TMR2 interrupt (latched in flag bit
TMR2IF (PIR1<1>)).
Timer2 Prescaler and Postscaler
The prescaler and postscaler counters are cleared
when any of the following occurs:
• A write to the TMR2 register
• A write to the T2CON register
• Any device RESET (Power-on Reset, MCLR,
WDT Reset, or Brown-out Reset)
TMR2 is not cleared when T2CON is written.
8.2
Output of TMR2
The output of TMR2 (before the postscaler) is fed to the
Synchronous Serial Port module, which optionally uses
it to generate a shift clock.
FIGURE 8-1:
Sets Flag
bit TMR2IF
TIMER2 BLOCK DIAGRAM
TMR2
Output(1)
Timer2 can be shut-off by clearing control bit TMR2ON
(T2CON<2>) to minimize power consumption.
RESET
Register 8-1 shows the Timer2 control register.
Postscaler
1:1 to 1:16
Additional information on timer modules is available in
the PICmicro™ Mid-Range MCU Family Reference
Manual (DS33023).
4
EQ
TMR2 reg
Comparator
Prescaler
1:1, 1:4, 1:16
FOSC/4
2
PR2 reg
Note 1: TMR2 register output can be software
selected by the SSP module as a baud clock.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 63
PIC16F818/819
REGISTER 8-1:
T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
U-0
—
R/W-0
R/W-0
TOUTPS3 TOUTPS2
R/W-0
R/W-0
TOUTPS1
R/W-0
R/W-0
R/W-0
TOUTPS0 TMR2ON T2CKPS1 T2CKPS0
bit 7
bit 0
bit 7
Unimplemented: Read as ‘0’
bit 6-3
TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits
0000 = 1:1 Postscale
0001 = 1:2 Postscale
0010 = 1:3 Postscale
•
•
•
1111 = 1:16 Postscale
bit 2
TMR2ON: Timer2 On bit
1 = Timer2 is on
0 = Timer2 is off
bit 1-0
T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits
00 = Prescaler is 1
01 = Prescaler is 4
1x = Prescaler is 16
Legend:
TABLE 8-1:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER
Value on
all other
RESETS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
0Bh, 8Bh, INTCON GIE
10Bh, 18Bh
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
Address
Name
0Ch
PIR1
—
ADIF
—
—
SSPIF
CCP1IF
TMR2IF
TMR1IF -0-- 0000 -0-- 0000
8Ch
PIE1
—
ADIE
—
—
SSPIE
CCP1IE
TMR2IE
TMR1IE -0-- 0000 -0-- 0000
11h
TMR2
12h
T2CON
92h
PR2
Legend:
Timer2 Module Register
—
0000 0000 0000 0000
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Timer2 Period Register
1111 1111 1111 1111
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.
DS39598C-page 64
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
9.0
CAPTURE/COMPARE/PWM
(CCP) MODULE
The CCP module’s input/output pin (CCP1) can be
configured as RB2 or RB3. This selection is set in bit 12
(CCPMX) of the configuration word.
The Capture/Compare/PWM (CCP) module contains a
16-bit register that can operate as a:
• 16-bit capture register
• 16-bit compare register
• PWM master/slave duty cycle register.
Table 9-1 shows the timer resources of the CCP
module modes.
Additional information on the CCP module is available
in the PICmicro™ Mid-Range MCU Reference Manual,
(DS33023) and in Application Note AN594, “Using the
CCP Modules” (DS00594).
TABLE 9-1:
Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls
the operation of CCP1. The special event trigger is
generated by a compare match which will reset Timer1
and start an A/D conversion (if the A/D module is
enabled).
CCP MODE - TIMER
RESOURCE
CCP Mode
Timer Resource
Capture
Compare
PWM
Timer1
Timer1
Timer2
REGISTER 9-1: CCP1CON: CAPTURE/COMPARE/PWM CONTROL REGISTER 1 (ADDRESS 17h)
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
—
CCP1X
CCP1Y
CCP1M3
CCP1M2
CCP1M1
CCP1M0
bit 7
bit 0
bit 7-6
Unimplemented: Read as '0'
bit 5-4
CCP1X:CCP1Y: PWM Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0
CCP1M3:CCP1M0: CCP1 Mode Select bits
0000 = Capture/Compare/PWM disabled (resets CCP1 module)
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, set output on match (CCP1IF bit is set)
1001 = Compare mode, clear output on match (CCP1IF bit is set)
1010 = Compare mode, generate software interrupt on match (CCP1IF bit is set,
CCP1 pin is unaffected)
1011 = Compare mode, trigger special event (CCP1IF bit is set, CCP1 pin is unaffected);
CCP1 resets TMR1 and starts an A/D conversion (if A/D module is enabled)
11xx = PWM mode
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
 2002 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS39598C-page 65
PIC16F818/819
9.1
Capture Mode
9.1.2
In Capture mode, CCPR1H:CCPR1L captures the
16-bit value of the TMR1 register when an event occurs
on CCP1 pin. An event is defined as:
•
•
•
•
Every falling edge
Every rising edge
Every 4th rising edge
Every 16th rising edge
9.1.1
CCP PIN CONFIGURATION
In Capture mode, the CCP1 pin should be configured
as an input by setting the TRISB<x> bit
Note 1: If the CCP1 pin is configured as an
output, a write to the port can cause a
capture condition.
2: The TRISB bit (2 or 3) is dependent upon
the setting of configuration bit 12
(CCPMX).
FIGURE 9-1:
CAPTURE MODE
OPERATION BLOCK
DIAGRAM
CCPR1H
and
Edge Detect
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep bit
CCP1IE (PIE1<2>) clear to avoid false interrupts and
should clear the flag bit CCP1IF, following any such
change in operating mode.
9.1.4
CCP PRESCALER
There are four prescaler settings, specified by bits
CCP1M3:CCP1M0. Whenever the CCP module is
turned off, or the CCP module is not in Capture mode,
the prescaler counter is cleared. This means that any
RESET will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared, therefore, the first capture may be from
a non-zero prescaler. Example 9-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter
and will not generate the “false” interrupt.
CLRF
MOVLW
CCPR1L
MOVWF
CHANGING BETWEEN
CAPTURE PRESCALERS
CCP1CON
;Turn CCP module off
NEW_CAPT_PS ;Load the W reg with
;the new prescaler
;move value and CCP ON
CCP1CON
;Load CCP1CON with this
;value
Capture
Enable
TMR1H
Q’s
SOFTWARE INTERRUPT
EXAMPLE 9-1:
Set Flag bit CCP1IF
(PIR1<2>)
Prescaler
÷ 1, 4, 16
CCP1 Pin
Timer1 must be running in Timer mode or Synchronized Counter mode for the CCP module to use the
capture feature. In Asynchronous Counter mode, the
capture operation may not work.
9.1.3
An event is selected by control bits CCP1M3:CCP1M0
(CCP1CON<3:0>). When a capture is made, the interrupt request flag bit CCP1IF (PIR1<2>) is set. It must
be cleared in software. If another capture occurs before
the value in register CCPR1 is read, the old captured
value is overwritten by the new captured value.
TIMER1 MODE SELECTION
TMR1L
CCP1CON<3:0>
DS39598C-page 66
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
9.2
Compare Mode
9.2.1
The user must configure the CCP1 pin as an output by
clearing the TRISB<x> bit.
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the CCP1 pin is:
Note 1: Clearing the CCP1CON register will force
the CCP1 compare output latch to the
default low level. This is not the data
latch.
• Driven High
• Driven Low
• Remains Unchanged
2: The TRISB bit (2 or 3) is dependent upon
the setting of configuration bit 12
(CCPMX).
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
FIGURE 9-2:
9.2.2
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Set Flag bit CCP1IF
(PIR1<2>)
9.2.3
CCPR1H CCPR1L
CCP1 pin
S
R
TRISB<x>
Output Enable
Output
Logic
Match
CCP1CON<3:0>
Mode Select
TMR1L
9.2.4
SPECIAL EVENT TRIGGER
In this mode, an internal hardware trigger is generated
that may be used to initiate an action.
Special event trigger will:
• RESET Timer1, but not set interrupt flag bit TMR1IF
(PIR1<0>)
• Set bit GO/DONE (ADCON0<2>) bit, which starts an A/D
conversion
The special event trigger output of CCP1 resets the
TMR1 register pair and starts an A/D conversion (if the
A/D module is enabled). This allows the CCPR1 register to effectively be a 16-bit programmable period
register for Timer1.
Note:
TABLE 9-2:
SOFTWARE INTERRUPT MODE
When generate software interrupt is chosen, the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
Comparator
TMR1H
TIMER1 MODE SELECTION
Timer1 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
Special Event Trigger
Q
CCP PIN CONFIGURATION
The special event trigger from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE AND TIMER1
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
0Bh,8Bh
INTCON
10BH,18Bh
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
Address
0Ch
PIR1
—
ADIF
—
—
SSPIF
CCP1IF TMR2IF
8Ch
PIE1
—
ADIE
—
—
SSPIE
CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
86h
TRISB
PORTB Data Direction Register
1111 1111 1111 1111
0Eh
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
0Fh
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
xxxx xxxx uuuu uuuu
10h
T1CON
15h
CCPR1L
Capture/Compare/PWM Register1 (LSB)
xxxx xxxx uuuu uuuu
16h
CCPR1H
Capture/Compare/PWM Register1 (MSB)
xxxx xxxx uuuu uuuu
17h
Legend:
CCP1CON
—
—
—
—
TMR1IF -0-- 0000 -0-- 0000
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON --00 0000 --uu uuuu
CCP1X
CCP1Y
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by Capture and Timer1.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 67
PIC16F818/819
9.3
PWM Mode
9.3.1
In Pulse Width Modulation (PWM) mode, the CCP1 pin
produces up to a 10-bit resolution PWM output. Since
the CCP1 pin is multiplexed with the PORTB data latch,
the TRISB<x> bit must be cleared to make the CCP1
pin an output.
Note:
Clearing the CCP1CON register will force
the CCP1 PWM output latch to the default
low level. This is not the PORTB I/O data
latch.
Figure 9-3 shows a simplified block diagram of the
CCP module in PWM mode.
For a step by step procedure on how to set up the CCP
module for PWM operation, see Section 9.3.3.
FIGURE 9-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
PWM PERIOD
The PWM period is specified by writing to the PR2
register. The PWM period can be calculated using the
following formula.
EQUATION 9-1:
PWM period = [(PR2) + 1] • 4 • TOSC •
(TMR2 prescale value)
PWM frequency is defined as 1 / [PWM period].
When TMR2 is equal to PR2, the following three events
occur on the next increment cycle:
• TMR2 is cleared
• The CCP1 pin is set (exception: if PWM duty
cycle = 0%, the CCP1 pin will not be set)
• The PWM duty cycle is latched from CCPR1L into
CCPR1H
CCP1CON<5:4>
Duty Cycle Registers
Note:
CCPR1L
CCPR1H (Slave)
CCP1 pin
R
Comparator
TMR2
(Note 1)
Q
TRISB<x>
Clear Timer,
CCP1 pin and
latch D.C.
PR2
Note 1: 8-bit timer is concatenated with 2-bit internal Q clock
or 2 bits of the prescaler to create 10-bit time-base.
A PWM output (Figure 9-4) has a time-base (period)
and a time that the output stays high (duty cycle). The
frequency of the PWM is the inverse of the period
(1/period).
FIGURE 9-4:
PWM OUTPUT
PWM DUTY CYCLE
The PWM duty cycle is specified by writing to the
CCPR1L register and to the CCP1CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR1L contains
the eight MSbs and the CCP1CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR1L:CCP1CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time.
S
Comparator
9.3.2
The Timer2 postscaler (see Section 8.0) is
not used in the determination of the PWM
frequency. The postscaler could be used
to have a servo update rate at a different
frequency than the PWM output.
EQUATION 9-2:
PWM duty cycle = (CCPR1L:CCP1CON<5:4>) •
TOSC • (TMR2 prescale value)
CCPR1L and CCP1CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR1H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR1H is a read only register.
The CCPR1H register and a 2-bit internal latch are
used to double buffer the PWM duty cycle. This double
buffering is essential for glitchless PWM operation.
Period
When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the
TMR2 prescaler, the CCP1 pin is cleared.
Duty Cycle
TMR2 = PR2
TMR2 = Duty Cycle
TMR2 = PR2
DS39598C-page 68
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
9.3.3
The maximum PWM resolution (bits) for a given PWM
frequency is given by the following formula.
The following steps should be taken when configuring
the CCP module for PWM operation:
EQUATION 9-3:
Resolution
Note:
(
FOSC
log FPWM
=
log(2)
)
SETUP FOR PWM OPERATION
1.
2.
bits
Set the PWM period by writing to the PR2 register.
Set the PWM duty cycle by writing to the
CCPR1L register and CCP1CON<5:4> bits.
Make the CCP1 pin an output by clearing the
TRISB<x> bit.
Set the TMR2 prescale value and enable Timer2
by writing to T2CON.
Configure the CCP1 module for PWM operation.
3.
If the PWM duty cycle value is longer than
the PWM period, the CCP1 pin will not be
cleared.
4.
5.
Note:
TABLE 9-3:
The TRISB bit (2 or 3) is dependant upon
the setting of configuration bit 12
(CCPMX).
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz
PWM Frequency
1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz
Timer Prescaler (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
TABLE 9-4:
16
4
1
1
1
1
0xFF
0xFF
0xFF
0x3F
0x1F
0x17
10
10
10
8
7
5.5
REGISTERS ASSOCIATED WITH PWM AND TIMER2
Value on
all other
RESETS
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
0Bh,8Bh
10Bh,18Bh
INTCON
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
0Ch
PIR1
—
ADIF
—
—
SSPIF
CCP1IF
TMR2IF
TMR1IF
-0-- 0000 -0-- 0000
—
ADIE
—
—
SSPIE
CCP1IE
TMR2IE
TMR1IE -0-- 0000 -0-- 0000
8Ch
PIE1
86h
TRISB
PORTB Data Direction Register
1111 1111 1111 1111
11h
TMR2
Timer2 Module Register
0000 0000 0000 0000
92h
PR2
Timer2 Module Period Register
1111 1111 1111 1111
12h
T2CON
15h
CCPR1L
Capture/Compare/PWM Register1 (LSB)
16h
CCPR1H
Capture/Compare/PWM Register1 (MSB)
17h
CCP1CON
Legend:
—
TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
—
—
CCP1X
CCP1Y
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by PWM and Timer2.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 69
PIC16F818/819
NOTES:
DS39598C-page 70
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
10.0
10.1
SYNCHRONOUS SERIAL PORT
(SSP) MODULE
SSP Module Overview
The Synchronous Serial Port (SSP) module is a serial
interface useful for communicating with other peripheral or microcontroller devices. These peripheral
devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The SSP module can
operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I2C)
An overview of I2C operations and additional information on the SSP module can be found in the PICmicro™
Mid-Range
MCU
Family
Reference Manual
(DS33023).
Refer to Application Note AN578, “Use of the SSP
Module in the I 2C Multi-Master Environment”
(DS00578).
 2002 Microchip Technology Inc.
10.2
SPI Mode
This section contains register definitions
operational characteristics of the SPI module.
and
SPI mode allows 8 bits of data to be synchronously
transmitted and received simultaneously. To
accomplish communication, typically three pins are
used:
• Serial Data Out (SDO)
• Serial Data In (SDI)
• Serial Clock (SCK)
RB2/SDO/CCP1
RB1/SDI/SDA
RB4/SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select (SS)
RB5/SS
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits in the SSPCON register (SSPCON<5:0>)
and SSPSTAT<7:6>. These control bits allow the
following to be specified:
•
•
•
•
Master mode (SCK is the clock output)
Slave mode (SCK is the clock input)
Clock Polarity (IDLE state of SCK)
Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
Preliminary
DS39598C-page 71
PIC16F818/819
REGISTER 10-1:
SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER (ADDRESS 94h)
R/W-0
R/W-0
R-0
R-0
R-0
R-0
R-0
R-0
SMP
CKE
D/A
P
S
R/W
UA
BF
bit 7
bit 0
bit 7
SMP: SPI Data Input Sample Phase bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time (Microwire®)
SPI Slave mode:
This bit must be cleared when SPI is used in Slave mode
I2 C mode:
This bit must be maintained clear
bit 6
CKE: SPI Clock Edge Select bit
SPI mode, CKP = 0:
1 = Data transmitted on rising edge of SCK (Microwire alternate)
0 = Data transmitted on falling edge of SCK
SPI mode, CKP = 1:
1 = Data transmitted on falling edge of SCK (Microwire alternate)
0 = Data transmitted on rising edge of SCK
I2 C mode:
This bit must be maintained clear
bit 5
D/A: Data/Address bit (I2C mode only)
In I2 C Slave mode:
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was address
bit 4
P: STOP bit(1) (I2C mode only)
1 = Indicates that a STOP bit has been detected last
0 = STOP bit was not detected last
bit 3
S: START bit(1) (I2C mode only)
1 = Indicates that a START bit has been detected last (this bit is ‘0’ on RESET)
0 = START bit was not detected last
bit 2
R/W: Read/Write Information bit (I2C mode only)
Holds the R/W bit information following the last address match, and is only valid from address match
to the next START bit, STOP bit, or ACK bit
1 = Read
0 = Write
bit 1
UA: Update Address bit (10-bit I2C mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
bit 0
BF: Buffer Full Status bit
Receive (SPI and I2 C modes):
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
Transmit (In I2 C mode only):
1 = Transmit in progress, SSPBUF is full (8 bits)
0 = Transmit complete, SSPBUF is empty
Note 1: This bit is cleared when the SSP module is disabled (i.e., the SSPEN bit is cleared).
Legend:
DS39598C-page 72
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Preliminary
x = Bit is unknown
 2002 Microchip Technology Inc.
PIC16F818/819
REGISTER 10-2:
SSPCON: SYNCHRONOUS SERIAL PORT CONTROL REGISTER 1
(ADDRESS 14h)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0
bit 7
bit 0
bit 7
WCOL: Write Collision Detect bit
1 = An attempt to write the SSPBUF register failed because the SSP module is busy
(must be cleared in software)
0 = No collision
bit 6
SSPOV: Receive Overflow Indicator bit
In SPI mode:
1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. The user must read the
SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit
is not set since each new reception (and transmission) is initiated by writing to the SSPBUF
register.
0 = No overflow
In I2 C mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t
care" in Transmit mode. SSPOV must be cleared in software in either mode.
0 = No overflow
bit 5
SSPEN: Synchronous Serial Port Enable bit(1)
In SPI mode:
1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
In I2 C mode:
1 = Enables the serial port and configures the SDA and SCL pins as serial port pins
0 = Disables serial port and configures these pins as I/O port pins
bit 4
CKP: Clock Polarity Select bit
In SPI mode:
1 = Transmit happens on falling edge, receive on rising edge. IDLE state for clock is a high level.
0 = Transmit happens on rising edge, receive on falling edge. IDLE state for clock is a low level.
In I2 C Slave mode:
SCK release control
1 = Enable clock
0 = Holds clock low (clock stretch). (Used to ensure data setup time.)
bit 3-0
SSPM<3:0>: Synchronous Serial Port Mode Select bits
0000 = SPI Master mode, clock = OSC/4
0001 = SPI Master mode, clock = OSC/16
0010 = SPI Master mode, clock = OSC/64
0011 = SPI Master mode, clock = TMR2 output/2
0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled.
0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin.
0110 = I2C Slave mode, 7-bit address
0111 = I2C Slave mode, 10-bit address
1011 = I2C firmware controlled Master mode (Slave IDLE)
1110 = I2C Slave mode, 7-bit address with START and STOP bit interrupts enabled
1111 = I2C Slave mode, 10-bit address with START and STOP bit interrupts enabled
1000, 1001, 1010, 1100, 1101 = Reserved
Note 1: In both modes, when enabled, these pins must be properly configured as input or output.
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
 2002 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS39598C-page 73
PIC16F818/819
FIGURE 10-1:
SSP BLOCK DIAGRAM
(SPI MODE)
To enable the serial port, SSP enable bit SSPEN
(SSPCON<5>) must be set. To reset or reconfigure SPI
mode, clear bit SSPEN, re-initialize the SSPCON register, and then set bit SSPEN. This configures the SDI,
SDO, SCK, and SS pins as serial port pins. For the pins
to behave as the serial port function, they must have
their data direction bits (in the TRISB register)
appropriately programmed. That is:
Internal
Data Bus
Read
Write
SSPBUF reg
•
•
•
•
•
RB1/SDI/SDA
SSPSR reg
RB5/SS
Shift
Clock
bit0
RB2/SDO/CCP1
SDI must have TRISB<1> set
SDO must have TRISB<2> cleared
SCK (Master mode) must have TRISB<4> cleared
SCK (Slave mode) must have TRISB<4> set
SS must have TRISB<5> set
Note 1: When the SPI is in Slave mode with SS pin
control enabled, (SSPCON<3:0> = 0100)
the SPI module will reset if the SS pin is
set to VDD.
SS Control
Enable
Edge
Select
2: If the SPI is used in Slave mode with
CKE = ‘1’, then the SS pin control must be
enabled.
2
Clock Select
SSPM3:SSPM0
4
Edge
Select
RB4/SCK/
SCL
3: When the SPI is in Slave mode with SS pin
control enabled (SSPCON<3:0> = 0100),
the state of SS pin can affect the state
read back from the TRISB<5> bit. The
Peripheral OE signal from the SSP module into PORTB controls the state that is
read back from the TRISB<5> bit. If ReadModify-Write instructions, such as BSF are
performed on the TRISB register while the
SS pin is high, this will cause the
TRISB<5> bit to be set, thus disabling the
SDO output.
TMR2 Output
2
Prescaler TCY
4, 16, 64
TRISB<4>
TABLE 10-1:
REGISTERS ASSOCIATED WITH SPI OPERATION
Value on
all other
RESETS
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
0Bh,8Bh
INTCON
10Bh,18Bh
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x 0000 000u
Address
0Ch
PIR1
—
ADIF
—
—
SSPIF
CCP1IF TMR2IF TMR1IF -0-- 0000 -0-- 0000
8Ch
PIE1
—
ADIE
—
—
SSPIE
CCP1IE TMR2IE TMR1IE -0-- 0000 -0-- 0000
86h
TRISB
PORTB Data Direction Register
1111 1111 1111 1111
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx uuuu uuuu
14h
SSPCON
WCOL SSPOV SSPEN
94h
SSPSTAT
SMP
CKE
D/A
CKP
P
SSPM3 SSPM2
S
R/W
SSPM1
UA
SSPM0 0000 0000 0000 0000
BF
0000 0000 0000 0000
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the SSP in SPI mode.
DS39598C-page 74
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
FIGURE 10-2:
SPI MODE TIMING, MASTER MODE
SCK (CKP = 0,
CKE = 0)
SCK (CKP = 0,
CKE = 1)
SCK (CKP = 1,
CKE = 0)
SCK (CKP = 1,
CKE = 1)
bit7
SDO
bit6
bit5
bit2
bit3
bit4
bit1
bit0
SDI (SMP = 0)
bit7
bit0
SDI (SMP = 1)
bit7
bit0
SSPIF
FIGURE 10-3:
SPI MODE TIMING (SLAVE MODE WITH CKE = 0)
SS (Optional)
SCK (CKP = 0)
SCK (CKP = 1)
bit7
SDO
bit6
bit5
bit2
bit3
bit4
bit1
bit0
SDI (SMP = 0)
bit7
bit0
SSPIF
FIGURE 10-4:
SPI MODE TIMING (SLAVE MODE WITH CKE = 1)
SS
SCK (CKP = 0)
SCK (CKP = 1)
SDO
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SDI (SMP = 0)
bit7
bit0
SSPIF
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 75
PIC16F818/819
10.3
SSP I 2C Mode Operation
The SSP module in I 2C mode fully implements all slave
functions, except general call support, and provides
interrupts on START and STOP bits in hardware to
facilitate firmware implementations of the master functions. The SSP module implements the standard mode
specifications, as well as 7-bit and 10-bit addressing.
Two pins are used for data transfer. These are the
RB4/SCK/SCL pin, which is the clock (SCL), and the
RB1/SDI/SDA pin, which is the data (SDA). The user
must configure these pins as inputs or outputs through
the TRISB<4,1> bits.
The SSP module functions are enabled by setting SSP
Enable bit SSPEN (SSPCON<5>).
FIGURE 10-5:
SSP BLOCK DIAGRAM
(I2C MODE)
Internal
Data Bus
Read
Write
Shift
Clock
MSb
LSb
Match Detect
Addr Match
SSPADD Reg
START and
STOP Bit Detect
Set, RESET
S, P Bits
(SSPSTAT Reg)
The SSP module has five registers for I2C operation:
•
•
•
•
Selection of any I 2C mode with the SSPEN bit set,
forces the SCL and SDA pins to be open drain, provided these pins are programmed to inputs by setting
the appropriate TRISB bits. Pull-up resistors must be
provided externally to the SCL and SDA pins for proper
operation of the I2C module.
10.3.1
SSPSR Reg
RB1/
SDI/
SDA
• I 2C Slave mode (7-bit address)
• I 2C Slave mode (10-bit address)
• I 2C Slave mode (7-bit address), with START and
STOP bit interrupts enabled to support firmware
Master mode
• I 2C Slave mode (10-bit address), with START and
STOP bit interrupts enabled to support firmware
Master mode
• I 2C Firmware controlled Master operation with
START and STOP bit interrupts enabled, Slave is
IDLE
Additional information on SSP I2C operation may be
found in the PICmicro™ Mid-Range MCU Reference
Manual (DS33023).
SSPBUF Reg
RB4/SCK/SCL
The SSPCON register allows control of the I 2C operation. Four mode selection bits (SSPCON<3:0>) allow
one of the following I 2C modes to be selected:
SSP Control Register (SSPCON)
SSP Status Register (SSPSTAT)
Serial Receive/Transmit Buffer (SSPBUF)
SSP Shift Register (SSPSR) - Not directly
accessible
• SSP Address Register (SSPADD)
SLAVE MODE
In Slave mode, the SCL and SDA pins must be configured as inputs (TRISB<4,1> set). The SSP module will
override the input state with the output data, when
required (slave-transmitter).
When an address is matched, or the data transfer after
an address match is received, the hardware automatically will generate the Acknowledge (ACK) pulse, and
then load the SSPBUF register with the received value
currently in the SSPSR register.
Either or both of the following conditions will cause the
SSP module not to give this ACK pulse:
a)
b)
The buffer full bit BF (SSPSTAT<0>) was set
before the transfer was received.
The overflow bit SSPOV (SSPCON<6>) was set
before the transfer was received.
In this case, the SSPSR register value is not loaded
into the SSPBUF, but bit SSPIF (PIR1<3>) is set.
Table 10-2 shows what happens when a data transfer
byte is received, given the status of bits BF and
SSPOV. The shaded cells show the condition where
user software did not properly clear the overflow condition. Flag bit BF is cleared by reading the SSPBUF
register while bit SSPOV is cleared through software.
The SCL clock input must have a minimum high and
low for proper operation. The high and low times of the
I2C specification, as well as the requirement of the SSP
module, are shown in timing parameter #100 and
parameter #101.
DS39598C-page 76
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
10.3.1.1
Addressing
10.3.1.2
Once the SSP module has been enabled, it waits for a
START condition to occur. Following the START condition, the eight bits are shifted into the SSPSR register.
All incoming bits are sampled with the rising edge of the
clock (SCL) line. The value of register SSPSR<7:1> is
compared to the value of the SSPADD register. The
address is compared on the falling edge of the eighth
clock (SCL) pulse. If the addresses match, and the BF
and SSPOV bits are clear, the following events occur:
a)
b)
c)
d)
The SSPSR register value is loaded into the
SSPBUF register.
The buffer full bit, BF is set.
An ACK pulse is generated.
SSP interrupt flag bit, SSPIF (PIR1<3>) is set
(interrupt is generated if enabled) - on the falling
edge of the ninth SCL pulse.
In 10-bit Address mode, two address bytes need to be
received by the slave device. The five Most Significant
bits (MSbs) of the first address byte specify if this is a
10-bit address. Bit R/W (SSPSTAT<2>) must specify a
write so the slave device will receive the second
address byte. For a 10-bit address, the first byte would
equal ‘1111 0 A9 A8 0’, where A9 and A8 are the
two MSbs of the address.
The sequence of events for 10-bit address is as
follows, with steps 7- 9 for slave-transmitter:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Receive first (high) byte of address (bits SSPIF,
BF, and bit UA (SSPSTAT<1>) are set).
Update the SSPADD register with second (low)
byte of address (clears bit UA and releases the
SCL line).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive second (low) byte of address (bits
SSPIF, BF, and UA are set).
Update the SSPADD register with the first (high)
byte of Address, if match releases SCL line, this
will clear bit UA.
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
Receive Repeated START condition.
Receive first (high) byte of address (bits SSPIF
and BF are set).
Read the SSPBUF register (clears bit BF) and
clear flag bit SSPIF.
 2002 Microchip Technology Inc.
Reception
When the R/W bit of the address byte is clear and an
address match occurs, the R/W bit of the SSPSTAT
register is cleared. The received address is loaded into
the SSPBUF register.
When the address byte overflow condition exists, then
a no acknowledge (ACK) pulse is given. An overflow
condition is indicated if either bit BF (SSPSTAT<0>) is
set or bit SSPOV (SSPCON<6>) is set.
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF (PIR1<3>) must be cleared in software. The SSPSTAT register is used to determine the
status of the byte.
10.3.1.3
Transmission
When the R/W bit of the incoming address byte is set
and an address match occurs, the R/W bit of the
SSPSTAT register is set. The received address is
loaded into the SSPBUF register. The ACK pulse will
be sent on the ninth bit, and pin RB4/SCK/SCL is held
low. The transmit data must be loaded into the
SSPBUF register, which also loads the SSPSR register. Then pin RB4/SCK/SCL should be enabled by setting bit CKP (SSPCON<4>). The master device must
monitor the SCL pin prior to asserting another clock
pulse. The slave devices may be holding off the master
device by stretching the clock. The eight data bits are
shifted out on the falling edge of the SCL input. This
ensures that the SDA signal is valid during the SCL
high time (Figure 10-7).
An SSP interrupt is generated for each data transfer
byte. Flag bit SSPIF must be cleared in software, and
the SSPSTAT register is used to determine the status
of the byte. Flag bit SSPIF is set on the falling edge of
the ninth clock pulse.
As a slave-transmitter, the ACK pulse from the masterreceiver is latched on the rising edge of the ninth SCL
input pulse. If the SDA line was high (not ACK), then
the data transfer is complete. When the ACK is latched
by the slave device, the slave logic is RESET (RESETs
SSPSTAT register) and the slave device then monitors
for another occurrence of the START bit. If the SDA line
was low (ACK), the transmit data must be loaded into
the SSPBUF register, which also loads the SSPSR register. Then pin RB4/SCK/SCL should be enabled by
setting bit CKP.
Preliminary
DS39598C-page 77
PIC16F818/819
TABLE 10-2:
DATA TRANSFER RECEIVED BYTE ACTIONS
Status Bits as Data
Transfer is Received
SSPSR → SSPBUF
Generate ACK Pulse
Set bit SSPIF
(SSP Interrupt Occurs if Enabled)
BF
SSPOV
0
0
Yes
Yes
Yes
1
0
No
No
Yes
1
1
No
No
Yes
0
1
No
No
Yes
Note 1: Shaded cells show the conditions where the user software did not properly clear the overflow condition.
I 2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)
FIGURE 10-6:
Receiving Address R/W=0
Receiving Data
Receiving Data
ACK
ACK
ACK
A7 A6 A5 A4 A3 A2 A1
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
SDA
SCL
1
S
2
3
4
5
6
7
9
8
1
2
SSPIF (PIR1<3>)
3
4
5
6
7
8
9
1
2
3
5
4
8
7
6
9
Cleared in Software
BF (SSPSTAT<0>)
P
Bus Master
terminates
transfer.
SSPBUF Register is Read
SSPOV (SSPCON<6>)
Bit SSPOV is set because the SSPBUF register is still full.
ACK is not sent.
I 2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)
FIGURE 10-7:
Receiving Address
A7
SDA
SCL
S
A6
1
2
Data is
Sampled
R/W = 1
A5
A4
A3
A2
A1
3
4
5
6
7
8
9
ACK
Transmitting Data
ACK
D7
1
SCL held low
while CPU
responds to SSPIF
SSPIF (PIR1<3>)
D6
D5
D4
D3
D2
D1
D0
2
3
4
5
6
7
8
9
P
Cleared in Software
BF (SSPSTAT<0>)
From SSP Interrupt
SSPBUF is Written in Software Service Routine
CKP (SSPCON<4>)
Set bit after writing to SSPBUF
(the SSPBUF must be written to
before the CKP bit can be set).
DS39598C-page 78
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
10.3.2
MASTER MODE OPERATION
10.3.3
Master mode operation is supported in firmware using
interrupt generation on the detection of the START and
STOP conditions. The STOP (P) and START (S) bits
are cleared from a RESET, or when the SSP module is
disabled. The STOP (P) and START (S) bits will toggle
based on the START and STOP conditions. Control of
the I 2C bus may be taken when the P bit is set, or the
bus is IDLE and both the S and P bits are clear.
MULTI-MASTER MODE OPERATION
In Multi-Master mode operation, the interrupt generation on the detection of the START and STOP conditions allows the determination of when the bus is free.
The STOP (P) and START (S) bits are cleared from a
RESET, or when the SSP module is disabled. The
STOP (P) and START (S) bits will toggle based on the
START and STOP conditions. Control of the I 2C bus
may be taken when bit P (SSPSTAT<4>) is set, or the
bus is IDLE and both the S and P bits clear. When the
bus is busy, enabling the SSP interrupt will generate
the interrupt when the STOP condition occurs.
In Master mode operation, the SCL and SDA lines are
manipulated in firmware by clearing the corresponding
TRISB<4,1> bit(s). The output level is always low, irrespective of the value(s) in PORTB<4,1>. So when
transmitting data, a ‘1’ data bit must have the
TRISB<1> bit set (input) and a ‘0’ data bit must have
the TRISB<1> bit cleared (output). The same scenario
is true for the SCL line with the TRISB<4> bit. Pull-up
resistors must be provided externally to the SCL and
SDA pins for proper operation of the I2C module.
In Multi-Master mode operation, the SDA line must be
monitored to see if the signal level is the expected output level. This check only needs to be done when a
high level is output. If a high level is expected and a low
level is present, the device needs to release the SDA
and SCL lines (set TRISB<4,1>). There are two stages
where this arbitration can be lost:
The following events will cause the SSP Interrupt Flag
bit, SSPIF, to be set (SSP Interrupt if enabled):
• Address Transfer
• Data Transfer
• START condition
• STOP condition
• Data transfer byte transmitted/received
When the slave logic is enabled, the Slave device continues to receive. If arbitration was lost during the
address transfer stage, communication to the device
may be in progress. If addressed, an ACK pulse will be
generated. If arbitration was lost during the data transfer stage, the device will need to re-transfer the data at
a later time.
Master mode operation can be done with either the
Slave mode IDLE (SSPM3:SSPM0 = 1011), or with the
Slave mode active. When both Master mode operation
and Slave modes are used, the software needs to
differentiate the source(s) of the interrupt.
For more information on Multi-Master mode operation,
see AN578, “Use of the SSP Module in the of I2C
Multi-Master Environment”.
For more information on Master mode operation, see
AN554, “Software Implementation of I2C Bus Master”.
TABLE 10-3:
REGISTERS ASSOCIATED WITH I2C OPERATION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
RESETS
0Bh, 8Bh,
INTCON
10Bh,18Bh
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
0000 000u
Address
0Ch
PIR1
—
ADIF
—
—
SSPIF CCP1IF TMR2IF TMR1IF
-0-- 0000
-0-- 0000
8Ch
PIE1
—
ADIE
—
—
SSPIE CCP1IE TMR2IE TMR1IE
-0-- 0000
-0-- 0000
13h
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
xxxx xxxx
uuuu uuuu
93h
SSPADD
Synchronous Serial Port (I2C mode) Address Register
0000 0000
0000 0000
14h
SSPCON
WCOL
SSPOV
SSPSTAT
SMP(1)
CKE(1)
94h
86h
TRISB
SSPEN
D/A
CKP
P
SSPM3 SSPM2 SSPM1 SSPM0
S
R/W
PORTB Data Direction register
UA
BF
0000 0000
0000 0000
0000 0000
0000 0000
1111 1111
1111 1111
Legend: x = unknown, u = unchanged, - = unimplemented locations read as ‘0’.
Shaded cells are not used by SSP module in SPI mode.
Note 1: Maintain these bits clear in I2C mode.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 79
PIC16F818/819
NOTES:
DS39598C-page 80
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
11.0
ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE
The A/D module has four registers:
The Analog-to-Digital (A/D) converter module has five
inputs for 18/20 pin devices.
The conversion of an analog input signal results in a
corresponding 10-bit digital number. The A/D module
has high and low voltage reference input that is software selectable to some combination of VDD, VSS,
RA2, or RA3.
The A/D converter has a unique feature of being able
to operate while the device is in SLEEP mode. To operate in SLEEP, the A/D conversion clock must be
derived from the A/D’s internal RC oscillator.
REGISTER 11-1:
•
•
•
•
A/D Result High Register (ADRESH)
A/D Result Low Register (ADRESL)
A/D Control Register 0 (ADCON0)
A/D Control Register 1 (ADCON1)
The ADCON0 register, shown in Register 11-1, controls the operation of the A/D module. The ADCON1
register, shown in Register 11-2, configures the functions of the port pins. The port pins can be configured
as analog inputs (RA3 can also be a voltage reference),
or a digital I/O.
Additional information on using the A/D module can be
found in the PICmicro™ Mid-Range MCU Family
Reference Manual (DS33023).
ADCON0: A/D CONTROL REGISTER 0 (ADDRESS 1Fh)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
R/W-0
ADCS1
ADCS0
CHS2
CHS1
CHS0
GO/DONE
—
ADON
bit 7
bit 0
bit 7-6
ADCS1:ADCS0: A/D Conversion Clock Select bits
If ADSC2 = 0:
00 = FOSC/2
01 = FOSC/8
10 = FOSC/32
11 = FRC (clock derived from the internal A/D module RC oscillator)
If ADSC2 = 1:
00 = FOSC/4
01 = FOSC/16
10 = FOSC/64
11 = FRC (clock derived from the internal A/D module RC oscillator)
bit 5-3
CHS2:CHS0: Analog Channel Select bits
000 = Channel 0, (RA0/AN0)
001 = Channel 1, (RA1/AN1)
010 = Channel 2, (RA2/AN2)
011 = Channel 3, (RA3/AN3)
100 = Channel 4, (RA4/AN4)
bit 2
GO/DONE: A/D Conversion Status bit
If ADON = 1:
1 = A/D conversion in progress (setting this bit starts the A/D conversion)
0 = A/D conversion not in progress (this bit is automatically cleared by hardware when the A/D
conversion is complete)
bit 1
Unimplemented: Read as ‘0’
bit 0
ADON: A/D On bit
1 = A/D converter module is operating
0 = A/D converter module is shut-off and consumes no operating current
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
 2002 Microchip Technology Inc.
Preliminary
x = Bit is unknown
DS39598C-page 81
PIC16F818/819
REGISTER 11-2:
ADCON1: A/D CONTROL REGISTER 1 (ADDRESS 9Fh)
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
ADFM
ADCS2
—
—
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
bit 7
ADFM: A/D Result Format Select bit
1 = Right justified, 6 Most Significant bits of ADRESH are read as ‘0’
0 = Left justified, 6 Least Significant bits of ADRESL are read as ‘0’
bit 6
ADCS2: A/D Clock Divide by 2 Select bit
1 = A/D Clock source is divided by 2 when system clock is used
0 = Disabled
bit 5-4
Unimplemented: Read as ‘0’
bit 3-0
PCFG<3:0>: A/D Port Configuration Control bits
PCFG
AN4
AN3
AN2
AN1
AN0
VREF+
VREF-
C/R
0000
0001
0010
0011
0100
0101
011x
1000
1001
1010
1011
1100
1101
1110
1111
A
A
A
A
D
D
D
A
A
A
A
A
D
D
D
A
VREF+
A
VREF+
A
VREF+
D
VREF+
A
VREF+
VREF+
VREF+
VREF+
D
VREF+
A
A
A
A
D
D
D
A
A
A
A
A
A
D
A
A
A
A
A
A
D
D
A
A
A
A
A
A
D
A
A
A
A
A
A
A
A
AVDD
AN3
AVDD
AN3
AVDD
AN3
AVDD
AN3
AVDD
AN3
AN3
AN3
AN3
AVDD
AN3
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AVSS
AN2
AVSS
AVSS
AN2
AN2
AN2
AVSS
AN2
5/0
4/1
5/0
4/1
3/0
2/1
0/0
3/2
5/0
4/1
3/2
3/2
2/2
1/0
1/2
VREFA
A
VREFVREFVREFD
VREF-
A = Analog input
D = Digital I/O
C/R = Number of Analog input channels/Number of A/D Voltage references
Legend:
DS39598C-page 82
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
Preliminary
x = Bit is unknown
 2002 Microchip Technology Inc.
PIC16F818/819
The ADRESH:ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is complete, the result is loaded into the A/D result register
pair, the GO/DONE bit (ADCON0<2>) is cleared, and
A/D interrupt flag bit ADIF is set. The block diagram of
the A/D module is shown in Figure 11-1.
These steps should be followed for doing an A/D
conversion:
1.
After the A/D module has been configured as desired,
the selected channel must be acquired before the conversion is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
2.
To determine sample time, see Section 11.1. After this
sample time has elapsed the A/D conversion can be
started.
3.
4.
5.
6.
7.
Configure the A/D module:
• Configure analog pins/voltage reference and
digital I/O (ADCON1)
• Select A/D input channel (ADCON0)
• Select A/D conversion clock (ADCON0)
• Turn on A/D module (ADCON0)
Configure A/D interrupt (if desired):
• Clear ADIF bit
• Set ADIE bit
• Set GIE bit
Wait the required acquisition time.
Start conversion:
• Set GO/DONE bit (ADCON0)
Wait for A/D conversion to complete, by either:
• Polling for the GO/DONE bit to be cleared
(with interrupts disabled); OR
• Waiting for the A/D interrupt
Read A/D Result register pair
(ADRESH:ADRESL), clear bit ADIF if required.
For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before the next acquisition starts.
FIGURE 11-1: A/D BLOCK DIAGRAM
CHS<3:0>
100
011
010
A/D
Converter
VIN
(Input Voltage)
001
AVDD
000
RA4/AN4
RA3/AN3/VREF+
RA2/AN2/VREFRA1/AN1
RA0/AN0
VREF+
(Reference
Voltage)
PCFG<3:0>
VREF(Reference
Voltage)
AVSS
PCFG<3:0>
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 83
PIC16F818/819
11.1
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 11-2. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), see
Figure 11-2. The maximum recommended impedance for analog sources is 2.5 kΩ. As the impedance
is decreased, the acquisition time may be decreased.
EQUATION 11-1:
TACQ
TC
TACQ
After the analog input channel is selected (changed),
this acquisition must be done before the conversion
can be started.
To calculate the minimum acquisition time,
Equation 11-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
To calculate the minimum acquisition time, TACQ, see
the PICmicro™ Mid-Range Reference Manual
(DS33023).
ACQUISITION TIME
= Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
=
=
=
=
=
=
=
TAMP + TC + TCOFF
2 µs + TC + [(Temperature -25°C)(0.05 µs/°C)]
CHOLD (RIC + RSS + RS) In(1/2047)
-120 pF (1 kΩ + 7 kΩ + 10 kΩ) In(0.0004885)
16.47 µs
2 µs + 16.47 µs + [(50°C – 25°C)(0.05 µs/°C)
19.72 µs
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 kΩ. This is required to meet the pin
leakage specification.
4: After a conversion has completed, a 2.0 TAD delay must complete before acquisition can begin again.
During this time, the holding capacitor is not connected to the selected A/D input channel.
FIGURE 11-2:
ANALOG INPUT MODEL
VDD
Rs
VA
ANx
CPIN
5 pF
Sampling
Switch
VT = 0.6V
VT = 0.6V
RIC ≤ 1k
SS
RSS
CHOLD
= DAC capacitance
= 51.2 pF
I leakage
± 500 nA
VSS
Legend: CPIN
= input capacitance
VT
= threshold voltage
I leakage = leakage current at the pin due to
various junctions
RIC
= interconnect resistance
SS
= sampling switch
CHOLD
= sample/hold capacitance (from DAC)
DS39598C-page 84
Preliminary
6V
5V
VDD 4 V
3V
2V
5 6 7 8 9 10 11
Sampling Switch
(kΩ)
 2002 Microchip Technology Inc.
PIC16F818/819
11.2
Selecting the A/D Conversion
Clock
11.3
The A/D conversion time per bit is defined as TAD. The
A/D conversion requires 9.0 TAD per 8-bit conversion.
The source of the A/D conversion clock is software
selectable. The seven possible options for TAD are:
•
•
•
•
•
•
•
The ADCON1, and TRISA registers control the operation of the A/D port pins. The port pins that are desired
as analog inputs must have their corresponding TRIS
bits set (input). If the TRIS bit is cleared (output), the
digital output level (VOH or VOL) will be converted.
The A/D operation is independent of the state of the
CHS<2:0> bits and the TRIS bits.
2 TOSC
4 TOSC
8 TOSC
16 TOSC
32 TOSC
64 TOSC
Internal A/D module RC oscillator (2 - 6 µs)
For correct A/D conversions, the A/D conversion clock
(TAD) must be selected to ensure a minimum TAD time
as small as possible, but no less than 1.6 µs and not
greater than 6.4 µs.
Note 1: When reading the port register, all pins
configured as analog input channels will
read as cleared (a low level). Pins configured as digital inputs, will convert an analog input. Analog levels on a digitally
configured input will not affect the
conversion accuracy.
2: Analog levels on any pin that is defined as
a digital input (including the AN4:AN0
pins), may cause the input buffer to
consume current out of the device
specification.
Table 11-1 shows the resultant TAD times derived from
the device operating frequencies and the A/D clock
source selected.
TABLE 11-1:
Configuring Analog Port Pins
TAD vs. MAXIMUM DEVICE OPERATING FREQUENCIES (STANDARD DEVICES (C))
AD Clock Source (TAD)
Maximum Device Frequency
Operation
ADCS<2>
ADCS<1:0>
Max.
2 TOSC
0
00
1.25 MHz
TOSC
1
00
2.5 MHz
8 TOSC
0
01
5 MHz
16 TOSC
1
01
10 MHz
32 TOSC
0
10
20 MHz
64 TOSC
1
10
20 MHz
RC(1,2,3)
X
11
(Note 1)
4
Note 1: The RC source has a typical TAD time of 4 µs but can vary between 2 - 6 µs.
2: When the device frequencies are greater than 1 MHz, the RC A/D conversion clock source is only
recommended for SLEEP operation.
3: For extended voltage devices (LF), please refer to the Electrical Characteristics (Section 15.0 and
Section 15.4).
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 85
PIC16F818/819
11.4
A/D Conversions
11.4.1
A/D RESULT REGISTERS
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16-bits wide.
The A/D module gives the flexibility to left or right justify
the 10-bit result in the 16-bit result register. The A/D
Format Select bit (ADFM) controls this justification.
Figure 11-4 shows the operation of the A/D result justification. The extra bits are loaded with ‘0’s. When an
A/D result will not overwrite these locations (A/D disable), these registers may be used as two general
purpose 8-bit registers.
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D result register
pair will NOT be updated with the partially completed
A/D conversion sample. That is, the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers). After the A/D conversion
is aborted, a 2 TAD wait is required before the next
acquisition is started. After this 2 TAD wait, acquisition
on the selected channel is automatically started. The
GO/DONE bit can then be set to start the conversion.
In Figure 11-3, after the GO bit is set, the first time
segment has a minimum of TCY and a maximum of TAD.
Note:
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
FIGURE 11-3:
A/D CONVERSION TAD CYCLES
TCY to TAD TAD1
TAD2
TAD3
TAD4
TAD5
TAD6
TAD7
TAD8
b9
b8
b7
b6
b5
b4
b3
TAD9 TAD10 TAD11
b2
b1
b0
Conversion Starts
Holding Capacitor is Disconnected from Analog Input (typically 100 ns)
Set GO bit
FIGURE 11-4:
ADRES is Loaded,
GO bit is Cleared,
ADIF bit is set,
Holding Capacitor is Connected to Analog Input
A/D RESULT JUSTIFICATION
10-bit Result
ADFM = 0
ADFM = 1
7
0
2107
7
0765
0000 00
0000 00
ADRESH
ADRESL
ADRESH
ADRESL
10-bit Result
10-bit Result
Left Justified
Right Justified
DS39598C-page 86
0
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
11.5
A/D Operation During SLEEP
11.6
The A/D module can operate during SLEEP mode. This
requires that the A/D clock source be set to RC
(ADCS1:ADCS0 = 11). When the RC clock source is
selected, the A/D module waits one instruction cycle
before starting the conversion. This allows the SLEEP
instruction to be executed, which eliminates all digital
switching noise from the conversion. When the conversion is completed, the GO/DONE bit will be cleared and
the result loaded into the ADRES register. If the A/D
interrupt is enabled, the device will wake-up from
SLEEP. If the A/D interrupt is not enabled, the A/D module will then be turned off, although the ADON bit will
remain set.
A device RESET forces all registers to their RESET
state. The A/D module is disabled and any conversion
in progress is aborted. All A/D input pins are configured
as analog inputs.
The value that is in the ADRESH:ADRESL registers
is not modified for a Power-on Reset. The
ADRESH:ADRESL registers will contain unknown data
after a Power-on Reset.
11.7
Turning off the A/D places the A/D module in its lowest
current consumption state.
For the A/D module to operate in SLEEP,
the A/D clock source must be set to RC
(ADCS1:ADCS0 = 11). To perform an A/D
conversion in SLEEP, ensure the SLEEP
instruction immediately follows the
instruction that sets the GO/DONE bit.
TABLE 11-2:
Use of the CCP Trigger
An A/D conversion can be started by the “special event
trigger” of the CCP module. This requires that the
CCP1M3:CCP1M0 bits (CCP1CON<3:0>) be programmed as 1011 and that the A/D module is enabled
(ADON bit is set). When the trigger occurs, the
GO/DONE bit will be set, starting the A/D conversion,
and the Timer1 counter will be reset to zero. Timer1 is
reset to automatically repeat the A/D acquisition period
with minimal software overhead (moving the
ADRESH:ADRESL to the desired location). The appropriate analog input channel must be selected and the
minimum acquisition done before the “special event
trigger” sets the GO/DONE bit (starts a conversion).
When the A/D clock source is another clock option (not
RC), a SLEEP instruction will cause the present conversion to be aborted and the A/D module to be turned off,
though the ADON bit will remain set.
Note:
Effects of a RESET
If the A/D module is not enabled (ADON is cleared),
then the “special event trigger” will be ignored by the
A/D module, but will still reset the Timer1 counter.
REGISTERS/BITS ASSOCIATED WITH A/D
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
all other
RESETS
INTCON
0Bh,8Bh
10Bh,18Bh
GIE
PEIE
TMR0IE
INTE
RBIE
TMR0IF
INTF
RBIF
0000 000x
0000 000u
Address
0Ch
PIR1
—
ADIF
—
—
SSPIF
CCP1IF
TMR2IF TMR1IF -0-- 0000
-0-- 0000
8Ch
PIE1
—
ADIE
—
—
SSPIE
CCP1IE
TMR2IE TMR1IE -0-- 0000
-0-- 0000
1Eh
ADRESH
xxxx xxxx
uuuu uuuu
9Eh
ADRESL
A/D Result Register Low Byte
1Fh
ADCON0
ADCS1 ADCS0
9Fh
ADCON1
ADFM
05h
PORTA
RA7
85h
TRISA
A/D Result Register High Byte
CHS2
CHS1
ADCS2
—
—
PCFG3
RA6
RA5
RA4
RA3
xxxx xxxx
uuuu uuuu
—
ADON
0000 00-0
0000 00-0
PCFG2
PCFG1
PCFG0
00-- 0000
00-- 0000
RA2
RA1
RA0
xxx0 0000
uuu0 0000
1111 1111
1111 1111
CHS0 GO/DONE
TRISA7 TRISA6 TRISA5 PORTA Data Direction Register
Legend: x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 87
PIC16F818/819
NOTES:
DS39598C-page 88
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
12.0
SPECIAL FEATURES OF THE
CPU
These devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide Power Saving
Operating modes and offer code protection:
• RESET
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
• Interrupts
• Watchdog Timer (WDT)
• SLEEP
• Code Protection
• ID Locations
• In-Circuit Serial Programming
Several oscillator options are also made available to
allow the part to fit the application. The RC oscillator
option saves system cost while the LP crystal option
saves power. Configuration bits are used to select the
desired oscillator mode.
Additional information on special features is available
in the PICmicro™ Mid-Range Reference Manual
(DS33023).
12.1
Configuration Bits
The configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select various device configurations. These bits are mapped in
program memory location 2007h.
There are two timers that offer necessary delays on
power-up. One is the Oscillator Start-up Timer (OST),
intended to keep the chip in RESET until the crystal
oscillator is stable. The other is the Power-up Timer
(PWRT), which provides a fixed delay of 72 ms (nominal) on power-up only. It is designed to keep the part in
RESET while the power supply stabilizes, and is
enabled or disabled using a configuration bit. With
these two timers on-chip, most applications need no
external RESET circuitry.
 2002 Microchip Technology Inc.
SLEEP mode is designed to offer a very low current
Power-down mode. The user can wake-up from
SLEEP through external RESET, Watchdog Timer
Wake-up, or through an interrupt.
The user will note that address 2007h is beyond the
user program memory space, which can be accessed
only during programming.
Preliminary
DS39598C-page 89
PIC16F818/819
REGISTER 12-1:
R/P-1
CP
R/P-1
CONFIGURATION WORD (ADDRESS 2007h)(1)
R/P-1
R/P-1
R/P-1
R/P-1
CCPMX DEBUG WRT1
R/P-1
WRT0
CPD
LVP
R/P-1
R/P-1
R/P-1
R/P-1
BOREN MCLRE FOSC2 PWRTEN
R/P-1
R/P-1
R/P-1
WDTEN
F0SC1
F0SC0
bit13
bit0
bit 13
CP: Flash Program Memory Code Protection bit
1 = Code protection off
0 = All memory locations code protected
bit 12
CCPMX: CCP1 Pin Selection bit
1 = CCP1 function on RB2
0 = CCP1 function on RB3
bit 11
DEBUG: In-Circuit Debugger Mode bit
1 = In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins
0 = In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger
bit 10-9
WRT1:WRT0: FLASH Program Memory Write Enable bits
For PIC16F818:
11 = Write protection off
10 = 000h to 01FF write protected, 0200 to 03FF may be modified by EECON control
01 = 000h to 03FF write protected
For PIC16F819:
11 = Write protection off
10 = 0000h to 01FFh write protected, 0200h to 07FFh may be modified by EECON control
01 = 0000h to 03FFh write protected, 0400h to 07FFh may be modified by EECON control
00 = 0000h to 05FFh write protected, 0600h to 07FFh may be modified by EECON control
bit 8
CPD: Data EE Memory Code Protection bit
1 = Code protection off
0 = Data EE memory locations code protected
bit 7
LVP: Low Voltage Programming Enable bit
1 = RB3/PGM pin has PGM function, low voltage programming enabled
0 = RB3/PGM pin has digital I/O function, HV on MCLR must be used for programming
bit 6
BOREN: Brown-out Reset Enable bit
1 = BOR enabled
0 = BOR disabled
bit 5
MCLRE: RA5/MCLR Pin Function Select bit
1 = RA5/MCLR pin function is MCLR
0 = RA5/MCLR pin function is digital I/O, MCLR internally tied to VDD
bit 3
PWRTEN: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
bit 2
WDTEN: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled
bit 4, 1-0
FOSC2:FOSC0: Oscillator Selection bits
111 = EXTRC oscillator; CLKO function on RA6/OSC2/CLKO pin
110 = EXTRC oscillator; port I/O function on RA6/OSC2/CLKO pin
101 = INTRC oscillator; CLKO function on RA6/OSC2/CLKO pin and port I/O function on RA7/OSC1/CLKI pin
100 = INTRC oscillator; port I/O function on both RA6/OSC2/CLKO pin and RA7/OSC1/CLKI pin
011 = EXTCLK; port I/O function on RA6/OSC2/CLKO pin
010 = HS oscillator
001 = XT oscillator
000 = LP oscillator
Note 1: The erased (unprogrammed) value of the configuration word is 3FFFh.
Legend:
R = Readable bit
P = Programmable bit
- n = Value when device is unprogrammed
DS39598C-page 90
Preliminary
U = Unimplemented bit, read as ‘1’
u = Unchanged from programmed state
 2002 Microchip Technology Inc.
PIC16F818/819
12.2
RESET
The PIC16F818/819 differentiates between various
kinds of RESET:
•
•
•
•
•
•
Power-on Reset (POR)
MCLR Reset during normal operation
MCLR Reset during SLEEP
WDT Reset during normal operation
WDT Wake-up during SLEEP
Brown-out Reset (BOR)
Some registers are not affected in any RESET condition. Their status is unknown on POR and unchanged
in any other RESET. Most other registers are reset to a
“RESET state” on Power-on Reset (POR), on the
MCLR and WDT Reset, on MCLR Reset during
SLEEP, and Brown-out Reset (BOR). They are not
affected by a WDT Wake-up, which is viewed as the
resumption of normal operation. The TO and PD bits
are set or cleared differently in different RESET situations, as indicated in Table 12-3. These bits are used in
software to determine the nature of the RESET. Upon
a POR, BOR, or wake-up from SLEEP, the CPU
requires approximately 5 - 10 µs to become ready for
code execution. This delay runs in parallel with any
other timers. See Table 12-4 for a full description of
RESET states of all registers.
A simplified block diagram of the on-chip RESET circuit
is shown in Figure 12-1.
FIGURE 12-1:
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
External
RESET
MCLR
WDT
WDT
Module
SLEEP
Time-out
Reset
VDD Rise
Detect
Power-on Reset
VDD
Brown-out
Reset
S
BOREN
OST/PWRT
OST
Chip_Reset
10-bit Ripple Counter
R
Q
OSC1
PWRT
INTRC
31.25 kHz
10-bit Ripple Counter
Enable PWRT
Enable OST
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 91
PIC16F818/819
12.3
MCLR
12.5
PIC16F818/819 device has a noise filter in the MCLR
Reset path. The filter will detect and ignore small
pulses.
It should be noted that a WDT Reset does not drive
MCLR pin low.
The behavior of the ESD protection on the MCLR pin
has been altered from previous devices of this family.
Voltages applied to the pin that exceed its specification
can result in both MCLR and excessive current beyond
the device specification during the ESD event. For this
reason, Microchip recommends that the MCLR pin no
longer be tied directly to VDD. The use of an
RC network, as shown in Figure 12-2, is suggested.
The RA5/MCLR pin can be configured for MCLR
(default), or as an I/O pin (RA5). This is configured
through the MCLRE bit in the Configuration register.
FIGURE 12-2:
RECOMMENDED MCLR
CIRCUIT
VDD
PIC16F818/819
The Power-up Timer (PWRT) of the PIC16F818/819 is
a counter that uses the INTRC oscillator as the clock
input. This yields a count of 72 ms. While the PWRT is
counting, the device is held in RESET.
The power-up time delay depends on the INTRC, and
will vary from chip-to-chip due to temperature and
process variation. See DC parameter #33 for details.
The PWRT is enabled by clearing configuration bit
PWRTEN.
12.6
Oscillator Start-up Timer (OST)
The Oscillator Start-up Timer (OST) provides 1024
oscillator cycles (from OSC1 input) delay after the
PWRT delay is over (if enabled). This helps to ensure
that the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP and HS
modes and only on Power-on Reset, or wake-up from
SLEEP.
12.7
Brown-out Reset (BOR)
The configuration bit, BOREN, can enable or disable
the Brown-out Reset circuit. If VDD falls below VBOR
(parameter D005, about 4V) for longer than TBOR
(parameter #35, about 100 µs), the brown-out situation
will reset the device. If VDD falls below VBOR for less
than TBOR, a RESET may not occur.
R1
1 kΩ (or greater)
MCLR
C1
0.1 µF
(optional, not critical)
12.4
Power-up Timer (PWRT)
Power-on Reset (POR)
A Power-on Reset pulse is generated on-chip when
VDD rise is detected (in the range of 1.2V - 1.7V). To
take advantage of the POR, tie the MCLR pin to VDD as
described in Section 12.3. A maximum rise time for
VDD is specified. See the Electrical Specifications for
details.
When the device starts normal operation (exits the
RESET condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure
operation. If these conditions are not met, the device
must be held in RESET until the operating conditions
are met. For more information, see Application Note,
AN607 - “Power-up Trouble Shooting” (DS00607).
Once the brown-out occurs, the device will remain in
Brown-out Reset until VDD rises above VBOR. The
Power-up Timer (if enabled) will keep the device in
RESET for TPWRT (parameter #33, about 72 ms). If
VDD should fall below VBOR during TPWRT, the Brownout Reset process will restart when VDD rises above
VBOR, with the Power-up Timer Reset. Unlike previous
PIC16 devices, the PWRT is no longer automatically
enabled when the Brown-out Reset circuit is enabled.
The PWRTEN and BOREN configuration bits are
independent of each other.
12.8
Time-out Sequence
On power-up, the time-out sequence is as follows: the
PWRT delay starts (if enabled) when a POR occurs.
Then, OST starts counting 1024 oscillator cycles when
PWRT ends (LP, XT, HS). When the OST ends, the
device comes out of RESET.
If MCLR is kept low long enough, all delays will expire.
Bringing MCLR high will begin execution immediately.
This is useful for testing purposes or to synchronize
more than one PIC16F818/819 device operating in
parallel.
Table 12-3 shows the RESET conditions for the
STATUS, PCON and PC registers, while Table 12-4
shows the RESET conditions for all the registers.
DS39598C-page 92
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
12.9
Power Control/Status Register
(PCON)
if bit BOR cleared, indicating a Brown-out Reset
occurred. When the Brown-out Reset is disabled, the
state of the BOR bit is unpredictable.
The Power Control/Status Register, PCON, has two
bits to indicate the type of RESET that last occurred.
Bit1 is POR (Power-on Reset Status bit). It is cleared on
a Power-on Reset and unaffected otherwise. The user
must set this bit following a Power-on Reset.
Bit0 is Brown-out Reset Status bit, BOR. Bit BOR is
unknown on a Power-on Reset. It must then be set by
the user and checked on subsequent RESETS to see
TABLE 12-1:
TIME-OUT IN VARIOUS SITUATIONS
Power-up
XT, HS, LP
Brown-out Reset
PWRTE = 0
PWRTE = 1
PWRTE = 0
PWRTE = 1
Wake-up from
SLEEP
TPWRT +
1024 • TOSC
1024 • TOSC
TPWRT +
1024 • TOSC
1024 • TOSC
1024 • TOSC
TPWRT
5 - 10 µs(1)
TPWRT
5 - 10 µs(1)
5 - 10 µs(1)
Oscillator Configuration
EXTRC, EXTCLK, INTRC
Note 1: CPU start-up is always invoked on POR, BOR and wake-up from SLEEP.
TABLE 12-2:
STATUS BITS AND THEIR SIGNIFICANCE
POR
BOR
TO
PD
0
x
1
1
Power-on Reset
0
x
0
x
Illegal, TO is set on POR
0
x
x
0
Illegal, PD is set on POR
1
0
1
1
Brown-out Reset
1
1
0
1
WDT Reset
1
1
0
0
WDT Wake-up
1
1
u
u
MCLR Reset during normal operation
1
1
1
0
MCLR Reset during SLEEP or interrupt wake-up from SLEEP
Legend: u = unchanged, x = unknown
TABLE 12-3:
RESET CONDITION FOR SPECIAL REGISTERS
Program
Counter
STATUS
Register
PCON
Register
Power-on Reset
000h
0001 1xxx
---- --0x
MCLR Reset during normal operation
000h
000u uuuu
---- --uu
MCLR Reset during SLEEP
000h
0001 0uuu
---- --uu
WDT Reset
000h
0000 1uuu
---- --uu
PC + 1
uuu0 0uuu
---- --uu
000h
0001 1uuu
---- --u0
uuu1 0uuu
---- --uu
Condition
WDT Wake-up
Brown-out Reset
Interrupt wake-up from SLEEP
(1)
PC + 1
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0'
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 93
PIC16F818/819
TABLE 12-4:
Register
W
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PCLATH
INTCON
INITIALIZATION CONDITIONS FOR ALL REGISTERS
Power-on Reset,
Brown-out Reset
xxxx xxxx
N/A
xxxx xxxx
0000h
0001
xxxx
xxx0
xxxx
---0
0000
1xxx
xxxx
0000
xxxx
0000
000x
MCLR Reset,
WDT Reset
uuuu uuuu
N/A
uuuu uuuu
0000h
000q
uuuu
uuu0
uuuu
---0
0000
quuu(3)
uuuu
0000
uuuu
0000
000u
Wake-up via WDT or
Interrupt
uuuu uuuu
N/A
uuuu uuuu
PC + 1(2)
uuuq
uuuu
uuuu
uuuu
---u
uuuu
quuu(3)
uuuu
uuuu
uuuu
uuuu
uuuu(1)
PIR1
-0-- 0000
-0-- 0000
-u-- uuuu(1)
PIR2
---0 ------0 ------u ----(1)
TMR1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
TMR1H
xxxx xxxx
uuuu uuuu
uuuu uuuu
T1CON
--00 0000
--uu uuuu
--uu uuuu
TMR2
0000 0000
0000 0000
uuuu uuuu
T2CON
-000 0000
-000 0000
-uuu uuuu
SSPBUF
xxxx xxxx
uuuu uuuu
uuuu uuuu
SSPCON
0000 0000
0000 0000
uuuu uuuu
CCPR1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCPR1H
xxxx xxxx
uuuu uuuu
uuuu uuuu
CCP1CON
--00 0000
--00 0000
--uu uuuu
ADRESH
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON0
0000 00-0
0000 00-0
uuuu uu-u
OPTION
1111 1111
1111 1111
uuuu uuuu
TRISA
1111 1111
1111 1111
uuuu uuuu
TRISB
1111 1111
1111 1111
uuuu uuuu
PIE1
-0-- 0000
-0-- 0000
-u-- uuuu
PIE2
---0 ------0 ------u ---PCON
---- --qq
---- --uu
---- --uu
OSCCON
-000 -0--000 -0--uuu -u-OSCTUNE
--00 0000
--00 0000
--uu uuuu
PR2
1111 1111
1111 1111
1111 1111
SSPADD
0000 0000
0000 0000
uuuu uuuu
SSPSTAT
0000 0000
0000 0000
uuuu uuuu
ADRESL
xxxx xxxx
uuuu uuuu
uuuu uuuu
ADCON1
00-- 0000
00-- 0000
uu-- uuuu
EEDATA
xxxx xxxx
uuuu uuuu
uuuu uuuu
EEADR
xxxx xxxx
uuuu uuuu
uuuu uuuu
EEDATH
--xx xxxx
--uu uuuu
--uu uuuu
EEADRH
---- -xxx
---- -uuu
---- -uuu
EECON1
x--x x000
u--x u000
u--u uuuu
EECON2
---- ------- ------- ---Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition,
r = reserved maintain clear
Note 1: One or more bits in INTCON, PIR1 and PR2 will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector
(0004h).
3: See Table 12-3 for RESET value for specific condition.
DS39598C-page 94
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
FIGURE 12-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH
PULL-UP RESISTOR)
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 12-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH
RC NETWORK): CASE 1
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
FIGURE 12-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH
RC NETWORK): CASE 2
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 95
PIC16F818/819
FIGURE 12-6:
SLOW RISE TIME (MCLR TIED TO VDD THROUGH RC NETWORK)
5V
1V
0V
VDD
MCLR
INTERNAL POR
TPWRT
PWRT TIME-OUT
TOST
OST TIME-OUT
INTERNAL RESET
12.10 Interrupts
The PIC16F818/819 has up to nine sources of interrupt. The interrupt control register (INTCON) records
individual interrupt requests in flag bits. It also has
individual and global interrupt enable bits.
Note:
Individual interrupt flag bits are set, regardless of the status of their corresponding
mask bit or the GIE bit.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all unmasked interrupts, or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be disabled through their corresponding enable bits in various registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on RESET.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
FIGURE 12-7:
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
The peripheral interrupt flags are contained in the Special Function Register, PIR1. The corresponding interrupt enable bits are contained in Special Function
Register, PIE1, and the peripheral interrupt enable bit
is contained in Special Function Register, INTCON.
When an interrupt is serviced, the GIE bit is cleared to
disable any further interrupt, the return address is
pushed onto the stack, and the PC is loaded with
0004h. Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends on when the interrupt event occurs, relative to
the current Q cycle. The latency is the same for one or
two cycle instructions. Individual interrupt flag bits are
set, regardless of the status of their corresponding
mask bit, PEIE bit, or the GIE bit.
INTERRUPT LOGIC
EEIF
EEIE
TMR0IF
TMR0IE
ADIF
ADIE
INTF
INTE
SSPIF
SSPIE
CCP1IF
CCP1IE
TMR1IF
TMR1IE
Wake-up (If in SLEEP mode)
Interrupt to CPU
RBIF
RBIE
PEIE
GIE
TMR2IF
TMR2IE
DS39598C-page 96
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
12.10.1
INT INTERRUPT
12.10.3
External interrupt on the RB0/INT pin is edge triggered,
either rising, if bit INTEDG (OPTION<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge
appears on the RB0/INT pin, flag bit INTF
(INTCON<1>) is set. This interrupt can be disabled by
clearing enable bit INTE (INTCON<4>). Flag bit INTF
must be cleared in software in the Interrupt Service
Routine before re-enabling this interrupt. The INT interrupt can wake-up the processor from SLEEP, if bit INTE
was set prior to going into SLEEP. The status of global
interrupt enable bit GIE decides whether or not the
processor branches to the interrupt vector, following
wake-up. See Section 12.13 for details on SLEEP
mode.
12.10.2
TMR0 INTERRUPT
An overflow (FFh → 00h) in the TMR0 register will set
flag bit TMR0IF (INTCON<2>). The interrupt can be
enabled/disabled by setting/clearing enable bit
TMR0IE (INTCON<5>) (see Section 6.0).
EXAMPLE 12-1:
PORTB INTCON CHANGE
An input change on PORTB<7:4> sets flag bit RBIF
(INTCON<0>). The interrupt can be enabled/disabled
by setting/clearing enable bit RBIE (INTCON<4>) (see
Section 3.2).
12.11 Context Saving During Interrupts
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key registers during an interrupt (i.e., W, STATUS registers).
This will have to be implemented in software, as shown
in Example 12-1.
For the PIC16F818/819 devices, the register W_TEMP
must be defined in both banks 0 and 1 and must be
defined at the same offset from the bank base address
(i.e., if W_TEMP is defined at 20h in bank 0, it must also
be defined at A0h in bank 1). The register
STATUS_TEMP is only defined in bank 0.
SAVING STATUS AND W REGISTERS IN RAM
MOVWF
SWAPF
CLRF
MOVWF
:
:(ISR)
:
SWAPF
W_TEMP
STATUS,W
STATUS
STATUS_TEMP
MOVWF
SWAPF
SWAPF
STATUS
W_TEMP,F
W_TEMP,W
;Copy
;Swap
;bank
;Save
W to TEMP register
status to be saved into W
0, regardless of current bank, Clears IRP,RP1,RP0
status to bank zero STATUS_TEMP register
;Insert user code here
STATUS_TEMP,W
 2002 Microchip Technology Inc.
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
Preliminary
DS39598C-page 97
PIC16F818/819
12.12 Watchdog Timer (WDT)
WDT time-out period values may be found in the Electrical Specifications section under parameter #31. Values for the WDT prescaler (actually a postscaler, but
shared with the Timer0 prescaler) may be assigned
using the OPTION register.
For PIC16F818/819 devices, the WDT is driven by the
INTRC oscillator. When the WDT is enabled, the
INTRC (31.25 kHz) oscillator is enabled. The nominal
WDT period is 16 ms, and has the same accuracy as
the INTRC oscillator.
Note 1: The CLRWDT and SLEEP instructions
clear the WDT and the postscaler, if
assigned to the WDT, and prevent it from
timing out and generating a device
RESET condition.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watchdog
Timer Wake-up). The TO bit in the STATUS register will
be cleared upon a Watchdog Timer time-out.
2: When a CLRWDT instruction is executed
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but
the prescaler assignment is not changed.
The WDT can be permanently disabled by clearing
configuration bit WDTEN (see Section 12.1).
FIGURE 12-8:
WATCHDOG TIMER BLOCK DIAGRAM
From TMR0 Clock Source
(Figure 6-1)
0
1
INTRC
31.25 kHz
Postscaler
M
U
X
8
8 - to - 1 MUX
PS2:PS0
PSA
WDT
Enable Bit
To TMR0 (Figure 6-1)
0
1
MUX
PSA
WDT
Time-out
Note: PSA and PS2:PS0 are bits in the OPTION register.
TABLE 12-5:
Address
SUMMARY OF WATCHDOG TIMER REGISTERS
Name
81h,181h OPTION
2007h
Configuration bits
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
LVP
BOREN
MVCLRE
FOSC2
PWRTEN
WDTEN
FOSC1
FOSC0
Legend: Shaded cells are not used by the Watchdog Timer.
Note 1: See Register 12-1 for operation of these bits.
DS39598C-page 98
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
12.13 Power-down Mode (SLEEP)
Power-down mode is entered by executing a SLEEP
instruction.
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit (STATUS<3>) is cleared, the
TO (STATUS<4>) bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they had
before the SLEEP instruction was executed (driving
high, low, or hi-impedance).
For lowest current consumption in this mode, place all
I/O pins at either VDD or VSS, ensure no external circuitry is drawing current from the I/O pin, power-down
the A/D and disable external clocks. Pull all I/O pins
that are hi-impedance inputs, high or low externally, to
avoid switching currents caused by floating inputs. The
T0CKI input should also be at VDD or VSS for lowest
current consumption. The contribution from on-chip
pull-ups on PORTB should also be considered.
The MCLR pin must be at a logic high level (VIHMC).
12.13.1
WAKE-UP FROM SLEEP
The device can wake-up from SLEEP through one of
the following events:
1.
2.
3.
External RESET input on MCLR pin.
Watchdog Timer wake-up (if WDT was
enabled).
Interrupt from INT pin, RB port change or a
peripheral interrupt.
External MCLR Reset will cause a device RESET. All
other events are considered a continuation of program
execution and cause a "wake-up". The TO and PD bits
in the STATUS register can be used to determine the
cause of the device RESET. The PD bit, which is set on
power-up, is cleared when SLEEP is invoked. The TO
bit is cleared if a WDT time-out occurred and caused
wake-up.
The following peripheral interrupts can wake the device
from SLEEP:
1.
2.
3.
4.
5.
6.
7.
Other peripherals cannot generate interrupts, since
during SLEEP, no on-chip clocks are present.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up
occurs regardless of the state of the GIE bit. If the GIE
bit is clear (disabled), the device continues execution at
the instruction after the SLEEP instruction. If the GIE bit
is set (enabled), the device executes the instruction
after the SLEEP instruction and then branches to the
interrupt address (0004h). In cases where the execution of the instruction following SLEEP is not desirable,
the user should have a NOP after the SLEEP instruction.
12.13.2
WAKE-UP USING INTERRUPTS
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT
postscaler will not be cleared, the TO bit will not
be set and PD bit will not be cleared.
• If the interrupt occurs during or after the
execution of a SLEEP instruction, the device will
immediately wake-up from SLEEP. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT
postscaler will be cleared, the TO bit will be set
and the PD bit will be cleared.
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes. To
determine whether a SLEEP instruction executed, test
the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruction
should be executed before a SLEEP instruction.
TMR1 interrupt. Timer1 must be operating as an
asynchronous counter.
CCP Capture mode interrupt.
Special event trigger (Timer1 in Asynchronous
mode using an external clock).
SSP (START/STOP) bit detect interrupt.
SSP transmit or receive in Slave mode (SPI/I2C).
A/D conversion (when A/D clock source is RC).
EEPROM write operation completion.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 99
PIC16F818/819
FIGURE 12-9:
WAKE-UP FROM SLEEP THROUGH INTERRUPT
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
TOST(2)
CLKO(4)
INT pin
INTF Flag
(INTCON<1>)
Interrupt Latency
(Note 2)
GIE bit
(INTCON<7>)
Processor in
SLEEP
INSTRUCTION FLOW
PC
Instruction
Fetched
Instruction
Executed
Note
1:
2:
3:
4:
PC
PC+1
Inst(PC) = SLEEP
Inst(PC - 1)
PC+2
PC+2
Inst(PC + 1)
Inst(PC + 2)
SLEEP
Inst(PC + 1)
PC + 2
Dummy Cycle
0004h
0005h
Inst(0004h)
Inst(0005h)
Dummy Cycle
Inst(0004h)
XT, HS or LP Oscillator mode assumed.
TOST = 1024 TOSC (drawing not to scale) This delay will not be there for RC Osc mode.
GIE = ‘1' assumed. In this case, after wake-up, the processor jumps to the interrupt routine.
If GIE = ‘0', execution will continue in-line.
CLKO is not available in these Osc modes, but shown here for timing reference.
12.14 In-Circuit Debugger
When the DEBUG bit in the configuration word is programmed to a '0', the In-Circuit Debugger functionality
is enabled. This function allows simple debugging functions when used with MPLAB® ICD. When the microcontroller has this feature enabled, some of the
resources are not available for general use. Table 12-6
shows which features are consumed by the background
debugger.
TABLE 12-6:
DEBUGGER RESOURCES
I/O pins
Stack
RB6, RB7
1 level
Program Memory
Address 0000h must be NOP
Data Memory
0x070 (0x0F0, 0x170, 0x1F0)
0x1EB - 0x1EF
12.15 Program Verification/Code
Protection
If the code protection bit(s) have not been programmed, the on-chip program memory can be read
out for verification purposes.
12.16 ID Locations
Four memory locations (2000h - 2003h) are designated
as ID locations, where the user can store checksum or
other code identification numbers. These locations are
not accessible during normal execution, but are readable and writable during program/verify. It is recommended that only the four Least Significant bits of the
ID location are used.
Last 100h words
To use the In-Circuit Debugger function of the microcontroller, the design must implement In-Circuit Serial
Programming connections to MCLR/VPP, VDD, GND,
RB7 and RB6. This will interface to the In-Circuit
Debugger module available from Microchip, or one of
the third party development tool companies.
DS39598C-page 100
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
12.17 In-Circuit Serial Programming
12.18 Low Voltage ICSP Programming
PIC16F818/819 microcontrollers can be serially programmed while in the end application circuit. This is
simply done with two lines for clock and data and three
other lines for power, ground, and the programming
voltage (see Figure 12-10 for an example). This allows
customers to manufacture boards with unprogrammed
devices, and then program the microcontroller just
before shipping the product. This also allows the most
recent firmware or a custom firmware to be
programmed.
The LVP bit of the configuration word enables low voltage ICSP programming. This mode allows the microcontroller to be programmed via ICSP using a VDD
source in the operating voltage range. This only means
that VPP does not have to be brought to VIHH, but can
instead be left at the normal operating voltage. In this
mode, the RB3/PGM pin is dedicated to the programming function and ceases to be a general purpose I/O
pin. During programming, VDD is applied to the MCLR
pin. To enter Programming mode, VDD must be applied
to the RB3/PGM, provided the LVP bit is set. The LVP
bit defaults to on (‘1’) from the factory.
For general information of serial programming, please
refer to the In-Circuit Serial Programming™ (ICSP™)
Guide (DS30277).
FIGURE 12-10:
TYPICAL IN-CIRCUIT
SERIAL PROGRAMMING
CONNECTION
Note 1: The High Voltage Programming mode is
always available, regardless of the state
of the LVP bit, by applying VIHH to the
MCLR pin.
2: While in Low Voltage ICSP mode, the
RB3 pin can no longer be used as a
general purpose I/O pin.
To Normal
Connections
External
Connector
Signals
*
3: When using Low Voltage ICSP Programming (LVP) and the pull-ups on PORTB
are enabled, bit 3 in the TRISB register
must be cleared to disable the pull-up on
RB3 and ensure the proper operation of
the device.
PIC16F818/819
+5V
VDD
0V
VSS
VPP
MCLR/VPP
CLK
RB6
Data I/O
RB7
4: RB3 should not be allowed to float if LVP
is enabled. An external pull-down device
should be used to default the device to
normal Operating mode. If RB3 floats
high, the PIC16F818/819 device will
enter Programming mode.
RB3†
To Programmer
*
*
5: LVP mode is enabled by default on all
devices shipped from Microchip. It can be
disabled by clearing the LVP bit in the
CONFIG register.
*
VDD
To Normal
Connections
* Isolation devices (as required).
†
RB3 only used in LVP mode.
6: Disabling LVP will provide maximum
compatibility to other PIC16CXXX devices.
If Low Voltage Programming mode is not used, the LVP
bit can be programmed to a '0' and RB3/PGM becomes
a digital I/O pin. However, the LVP bit may only be programmed when programming is entered with VIHH on
MCLR. The LVP bit can only be charged when using
high voltage on MCLR.
It should be noted, that once the LVP bit is programmed
to 0, only the High Voltage Programming mode is available and only High Voltage Programming mode can be
used to program the device.
When using low voltage ICSP, the part must be supplied
at 4.5V to 5.5V, if a bulk erase will be executed. This
includes reprogramming of the code protect bits from an
on-state to off-state. For all other cases of low voltage
ICSP, the part may be programmed at the normal operating voltage. This means calibration values, unique
user IDs, or user code can be reprogrammed or added.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 101
PIC16F818/819
NOTES:
DS39598C-page 102
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
13.0
INSTRUCTION SET SUMMARY
The PIC16 instruction set is highly orthogonal and is
comprised of three basic categories:
• Byte-oriented operations
• Bit-oriented operations
For example, a “clrf PORTB” instruction will read
PORTB, clear all the data bits, then write the result
back to PORTB. This example would have the unintended result that the condition that sets the RBIF flag
would be cleared.
TABLE 13-1:
• Literal and control operations
Each PIC16 instruction is a 14-bit word divided into an
opcode, which specifies the instruction type, and one
or more operands, which further specify the operation
of the instruction. The formats for each of the categories are presented in Figure 13-1, while the various
opcode fields are summarized in Table 13-1.
Table 13-2 lists the instructions recognized by the
MPASMTM assembler. A complete description of each
instruction is also available in the PICmicro™
Mid-Range Reference Manual (DS33023).
For byte-oriented instructions, ‘f’ represents a file register designator and ‘d’ represents a destination designator. The file register designator specifies which file
register is to be used by the instruction.
The destination designator specifies where the result of
the operation is to be placed. If ‘d’ is zero, the result is
placed in the W register. If ‘d’ is one, the result is placed
in the file register specified in the instruction.
For bit-oriented instructions, ‘b’ represents a bit field
designator, which selects the bit affected by the operation, while ‘f’ represents the address of the file in which
the bit is located.
Field
Register file address (0x00 to 0x7F)
W
Working register (accumulator)
b
Bit address within an 8-bit file register
k
Literal field, constant data or label
x
Don't care location (= 0 or 1).
The assembler will generate code with x = 0.
It is the recommended form of use for
compatibility with all Microchip software tools.
d
Destination select; d = 0: store result in W,
d = 1: store result in file register f.
Default is d = 1.
PC
Program Counter
TO
Time-out bit
PD
Power-down bit
FIGURE 13-1:
One instruction cycle consists of four oscillator periods;
for an oscillator frequency of 4 MHz, this gives a normal
instruction execution time of 1 µs. All instructions are
executed within a single instruction cycle, unless a conditional test is true, or the program counter is changed
as a result of an instruction. When this occurs, the execution takes two instruction cycles, with the second
cycle executed as a NOP.
To maintain upward compatibility with
future PIC16F818/819 products, do not
use the OPTION and TRIS instructions.
All instruction examples use the format ‘0xhh’ to represent a hexadecimal number, where ‘h’ signifies a
hexadecimal digit.
13.1
GENERAL FORMAT FOR
INSTRUCTIONS
Byte-oriented file register operations
13
8 7 6
OPCODE
d
f (FILE #)
0
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
0
b = 3-bit bit address
f = 7-bit file register address
Literal and control operations
General
13
8
7
OPCODE
0
k (literal)
k = 8-bit immediate value
READ-MODIFY-WRITE
OPERATIONS
CALL and GOTO instructions only
Any instruction that specifies a file register as part of
the instruction performs a Read-Modify-Write (R-M-W)
operation. The register is read, the data is modified,
and the result is stored according to either the instruction, or the destination designator ‘d’. A read operation
is performed on a register even if the instruction writes
to that register.
 2002 Microchip Technology Inc.
Description
f
For literal and control operations, ‘k’ represents an
eight- or eleven-bit constant or literal value
Note:
OPCODE FIELD
DESCRIPTIONS
Preliminary
13
11
OPCODE
10
0
k (literal)
k = 11-bit immediate value
DS39598C-page 103
PIC16F818/819
TABLE 13-2:
PIC16F818/819 INSTRUCTION SET
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
MSb
LSb
Status
Affected
Notes
BYTE-ORIENTED FILE REGISTER OPERATIONS
ADDWF
ANDWF
CLRF
CLRW
COMF
DECF
DECFSZ
INCF
INCFSZ
IORWF
MOVF
MOVWF
NOP
RLF
RRF
SUBWF
SWAPF
XORWF
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
Add W and f
AND W with f
Clear f
Clear W
Complement f
Decrement f
Decrement f, Skip if 0
Increment f
Increment f, Skip if 0
Inclusive OR W with f
Move f
Move W to f
No Operation
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Swap nibbles in f
Exclusive OR W with f
1
1
1
1
1
1
1(2)
1
1(2)
1
1
1
1
1
1
1
1
1
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
00
0111
0101
0001
0001
1001
0011
1011
1010
1111
0100
1000
0000
0000
1101
1100
0010
1110
0110
dfff
dfff
lfff
0xxx
dfff
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0xx0
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
xxxx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
0000
ffff
ffff
ffff
ffff
ffff
00bb
01bb
10bb
11bb
bfff
bfff
bfff
bfff
ffff
ffff
ffff
ffff
111x
1001
0kkk
0000
1kkk
1000
00xx
0000
01xx
0000
0000
110x
1010
kkkk
kkkk
kkkk
0110
kkkk
kkkk
kkkk
0000
kkkk
0000
0110
kkkk
kkkk
kkkk
kkkk
kkkk
0100
kkkk
kkkk
kkkk
1001
kkkk
1000
0011
kkkk
kkkk
C,DC,Z
Z
Z
Z
Z
Z
Z
Z
Z
C
C
C,DC,Z
Z
1,2
1,2
2
1,2
1,2
1,2,3
1,2
1,2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
BIT-ORIENTED FILE REGISTER OPERATIONS
1
1
1 (2)
1 (2)
BCF
BSF
BTFSC
BTFSS
f, b
f, b
f, b
f, b
Bit Clear f
Bit Set f
Bit Test f, Skip if Clear
Bit Test f, Skip if Set
ADDLW
ANDLW
CALL
CLRWDT
GOTO
IORLW
MOVLW
RETFIE
RETLW
RETURN
SLEEP
SUBLW
XORLW
k
k
k
k
k
k
k
k
k
Add literal and W
AND literal with W
Call subroutine
Clear Watchdog Timer
Go to address
Inclusive OR literal with W
Move literal to W
Return from interrupt
Return with literal in W
Return from Subroutine
Go into Standby mode
Subtract W from literal
Exclusive OR literal with W
01
01
01
01
1,2
1,2
3
3
LITERAL AND CONTROL OPERATIONS
1
1
2
1
2
1
1
2
2
2
1
1
1
11
11
10
00
10
11
11
00
11
00
00
11
11
C,DC,Z
Z
TO,PD
Z
TO,PD
C,DC,Z
Z
Note 1:
When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present
on the pins themselves. For example, if the data latch is ‘1’ for a pin configured as input and is driven low by an external
device, the data will be written back with a ‘0’.
2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned
to the Timer0 Module.
3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is
executed as a NOP.
Note:
Additional information on the mid-range instruction set is available in the PICmicro™ Mid-Range MCU
Family Reference Manual (DS33023).
DS39598C-page 104
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
13.2
Instruction Descriptions
ADDLW
Add Literal and W
ANDWF
AND W with f
Syntax:
[ label ] ADDLW
Syntax:
[ label ] ANDWF
Operands:
0 ≤ k ≤ 255
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(W) + k → (W)
Status Affected:
C, DC, Z
Operation:
(W) .AND. (f) → (destination)
The contents of the W register
are added to the eight-bit literal ‘k’
and the result is placed in the W
register.
Status Affected:
Z
Description:
AND the W register with register
‘f’. If ‘d’ = ‘0’, the result is stored in
the W register. If ‘d’ = ‘1’, the
result is stored back in register ‘f’.
ADDWF
Add W and f
BCF
Bit Clear f
Syntax:
[ label ] ADDWF
Syntax:
[ label ] BCF
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
0≤b≤7
Operation:
(W) + (f) → (destination)
Operation:
0 → (f<b>)
Status Affected:
C, DC, Z
Status Affected:
None
Description:
Add the contents of the W register
with register ‘f’. If ‘d’ = ‘0’, the
result is stored in the W register. If
‘d’ = ‘1’, the result is stored back
in register ‘f’.
Description:
Bit ‘b’ in register ‘f’ is cleared.
ANDLW
AND Literal with W
BSF
Bit Set f
Syntax:
[ label ] ANDLW
Syntax:
[ label ] BSF
Operands:
0 ≤ f ≤ 127
0≤b≤7
Description:
k
f,d
k
f,d
f,b
f,b
Operands:
0 ≤ k ≤ 255
Operation:
(W) .AND. (k) → (W)
Status Affected:
Z
Operation:
1 → (f<b>)
Description:
The contents of W register are
AND’ed with the eight-bit literal
‘k’. The result is placed in the W
register.
Status Affected:
None
Description:
Bit ‘b’ in register ‘f’ is set.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 105
PIC16F818/819
BTFSS
Bit Test f, Skip if Set
CLRF
Clear f
Syntax:
[ label ] BTFSS f,b
Syntax:
[ label ] CLRF
Operands:
0 ≤ f ≤ 127
0≤b<7
Operands:
0 ≤ f ≤ 127
Operation:
Operation:
skip if (f<b>) = 1
00h → (f)
1→Z
Status Affected:
None
Status Affected:
Z
Description:
If bit ‘b’ in register ‘f’ = ‘0’, the next
instruction is executed.
If bit ‘b’ = ‘1’, then the next instruction is discarded and a NOP is
executed instead, making this a 2
TCY instruction.
Description:
The contents of register ‘f’ are
cleared and the Z bit is set.
BTFSC
Bit Test, Skip if Clear
CLRW
Clear W
Syntax:
[ label ] BTFSC f,b
Syntax:
[ label ] CLRW
Operands:
0 ≤ f ≤ 127
0≤b≤7
Operands:
None
Operation:
Operation:
skip if (f<b>) = 0
00h → (W)
1→Z
Status Affected:
None
Status Affected:
Z
Description:
If bit ‘b’ in register ‘f’ = ‘1’, the next
instruction is executed.
If bit ‘b’, in register ‘f’, = ‘0’, the
next instruction is discarded, and
a NOP is executed instead, making
this a 2 TCY instruction.
Description:
W register is cleared. Zero bit (Z)
is set.
CALL
Call Subroutine
CLRWDT
Clear Watchdog Timer
Syntax:
[ label ] CALL k
Syntax:
[ label ] CLRWDT
Operands:
0 ≤ k ≤ 2047
Operands:
None
Operation:
(PC) + 1 → TOS,
k → PC<10:0>,
(PCLATH<4:3>) → PC<12:11>
Operation:
Status Affected:
None
00h → WDT
0 → WDT prescaler,
1 → TO
1 → PD
Description:
Call subroutine. First, return
address (PC+1) is pushed onto
the stack. The eleven-bit immediate address is loaded into PC bits
<10:0>. The upper bits of the PC
are loaded from PCLATH. CALL is
a two-cycle instruction.
Status Affected:
TO, PD
Description:
CLRWDT instruction resets the
Watchdog Timer. It also resets the
prescaler of the WDT. Status bits
TO and PD are set.
DS39598C-page 106
Preliminary
f
 2002 Microchip Technology Inc.
PIC16F818/819
COMF
Complement f
Syntax:
[ label ] COMF
GOTO
Unconditional Branch
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ k ≤ 2047
Operation:
(f) → (destination)
Operation:
k → PC<10:0>
PCLATH<4:3> → PC<12:11>
Status Affected:
Z
Status Affected:
None
Description:
The contents of register ‘f’ are
complemented. If ‘d’ = ‘0’, the
result is stored in W. If ‘d’ = ‘1’, the
result is stored back in register ‘f’.
Description:
GOTO is an unconditional branch.
The eleven bit immediate value is
loaded into PC bits <10:0>. The
upper bits of PC are loaded
from PCLATH<4:3>. GOTO is a
two-cycle instruction.
DECF
Decrement f
INCF
Increment f
Syntax:
[ label ] DECF f,d
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) - 1 → (destination)
Operation:
(f) + 1 → (destination)
Status Affected:
Z
Status Affected:
Z
Description:
Decrement register ‘f’. If ‘d’ = ‘0’,
the result is stored in the W register. If ‘d’ = ‘1’, the result is stored
back in register ‘f’.
Description:
The contents of register ‘f’ are
incremented. If ‘d’ = ‘0’, the result
is placed in the W register. If
‘d’ = ‘1’, the result is placed back
in register ‘f’.
DECFSZ
Decrement f, Skip if 0
INCFSZ
Increment f, Skip if 0
Syntax:
[ label ] DECFSZ f,d
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) - 1 → (destination);
skip if result = 0
Operation:
(f) + 1 → (destination),
skip if result = 0
Status Affected:
None
Status Affected:
None
Description:
The contents of register ‘f’ are
decremented. If ‘d’ = ‘0’, the result
is placed in the W register. If
‘d’ = ‘1’, the result is placed back
in register ‘f’.
If the result is ‘1’, the next instruction is executed. If the result is ‘0’,
then a NOP is executed instead,
making it a 2 TCY instruction.
Description:
The contents of register ‘f’ are
incremented. If ‘d’ = ‘0’, the result
is placed in the W register. If
‘d’ = ‘1’, the result is placed back
in register ‘f’.
If the result is ‘1’, the next instruction is executed. If the result is ‘0’,
a NOP is executed instead, making
it a 2 TCY instruction.
 2002 Microchip Technology Inc.
f,d
Preliminary
GOTO k
INCF f,d
INCFSZ f,d
DS39598C-page 107
PIC16F818/819
IORLW
Inclusive OR Literal with W
MOVLW
Move Literal to W
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
Operands:
0 ≤ k ≤ 255
Operation:
(W) .OR. k → (W)
Operation:
k → (W)
Status Affected:
Z
Status Affected:
None
Description:
The contents of the W register are
OR’d with the eight-bit literal ‘k’.
The result is placed in the W
register.
Description:
The eight-bit literal ‘k’ is loaded
into W register. The don’t cares
will assemble as ‘0’s.
IORWF
Inclusive OR W with f
MOVWF
Move W to f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
Operation:
(W) → (f)
Operation:
(W) .OR. (f) → (destination)
Status Affected:
None
Status Affected:
Z
Description:
Description:
Inclusive OR the W register with
register ‘f’. If ‘d’ = ‘0’, the result is
placed in the W register. If ‘d’ = ‘1’,
the result is placed back in
register ‘f’.
Move data from W register to
register ‘f’.
MOVF
Move f
NOP
No Operation
IORLW k
IORWF
f,d
Syntax:
[ label ]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) → (destination)
Status Affected:
Z
Description:
The contents of register ‘f’ are
moved to a destination dependant
upon the status of ‘d’. If ‘d’ = ‘0’,
the destination is W register. If
‘d’ = ‘1’, the destination is file register ‘f’ itself. ‘d’ = ‘1’ is useful to
test a file register, since status
flag Z is affected.
DS39598C-page 108
MOVF f,d
MOVLW k
MOVWF
Syntax:
[ label ]
Operands:
None
Operation:
No operation
Status Affected:
None
Description:
No operation.
Preliminary
f
NOP
 2002 Microchip Technology Inc.
PIC16F818/819
RETFIE
Return from Interrupt
RLF
Rotate Left f through Carry
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
Operation:
TOS → PC,
1 → GIE
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
See description below
Status Affected:
None
Status Affected:
C
Description:
The contents of register ‘f’ are
rotated one bit to the left through
the Carry Flag. If ‘d’ = ‘0’, the
result is placed in the W register.
If ‘d’ = ‘1’, the result is stored
back in register ‘f’.
RETFIE
RLF
C
f,d
Register f
RETLW
Return with Literal in W
RRF
Rotate Right f through Carry
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
Operands:
Operation:
k → (W);
TOS → PC
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
See description below
Status Affected:
None
Status Affected:
C
Description:
The W register is loaded with the
eight-bit literal ‘k’. The program
counter is loaded from the top of
the stack (the return address).
This is a two-cycle instruction.
Description:
The contents of register ‘f’ are
rotated one bit to the right through
the Carry Flag. If ‘d’ = ‘0’, the
result is placed in the W register.
If ‘d’ = ‘1’, the result is placed back
in register ‘f’.
RETLW k
RRF f,d
C
Register f
RETURN
Return from Subroutine
SLEEP
Syntax:
[ label ]
Syntax:
Operands:
None
Operands:
None
TOS → PC
Operation:
00h → WDT,
0 → WDT prescaler,
1 → TO,
0 → PD
Status Affected:
TO, PD
Description:
The power-down status bit, PD is
cleared. Time-out status bit, TO
is set. Watchdog Timer and its
prescaler are cleared.
The processor is put into SLEEP
mode with the oscillator stopped.
Operation:
RETURN
Status Affected:
None
Description:
Return from subroutine. The stack
is POPed and the top of the stack
(TOS) is loaded into the program
counter. This is a two-cycle
instruction.
 2002 Microchip Technology Inc.
Preliminary
[ label ]
SLEEP
DS39598C-page 109
PIC16F818/819
SUBLW
Syntax:
Subtract W from Literal
[ label ]
SUBLW k
XORLW
Exclusive OR Literal with W
Syntax:
[ label ]
Operands:
0 ≤ k ≤ 255
Operands:
0 ≤ k ≤ 255
Operation:
k - (W) → (W)
XORLW k
Operation:
(W) .XOR. k → (W)
Status Affected: C, DC, Z
Status Affected:
Z
Description:
The W register is subtracted (2’s
complement method) from the
eight-bit literal ‘k’. The result is
placed in the W register.
Description:
The contents of the W register
are XOR’ed with the eight-bit
literal ‘k’. The result is placed in
the W register.
SUBWF
Syntax:
Subtract W from f
[ label ]
SUBWF f,d
XORWF
Syntax:
[ label ] XORWF
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f) - (W) → (destination)
Operation:
(W) .XOR. (f) → (destination)
Status Affected: C, DC, Z
Status Affected:
Z
Description:
Description:
Exclusive OR the contents of the
W register with register ‘f’. If
‘d’ = 0, the result is stored in the
W register. If ‘d’ = ‘1’, the result is
stored back in register ‘f’.
Subtract (2’s complement method)
W register from register ‘f’. If
‘d’ = ‘0’, the result is stored in the W
register. If ‘d’ = ‘1’, the result is
stored back in register ‘f’.
SWAPF
Swap Nibbles in f
Syntax:
[ label ] SWAPF f,d
Operands:
0 ≤ f ≤ 127
d ∈ [0,1]
Operation:
(f<3:0>) → (destination<7:4>),
(f<7:4>) → (destination<3:0>)
Status Affected:
None
Description:
The upper and lower nibbles of
register ‘f’ are exchanged. If
‘d’ = ‘0’, the result is placed in W
register. If ‘d’ = ‘1’, the result is
placed in register ‘f’.
DS39598C-page 110
Preliminary
Exclusive OR W with f
f,d
 2002 Microchip Technology Inc.
PIC16F818/819
14.0
DEVELOPMENT SUPPORT
The MPLAB IDE allows you to:
The PICmicro® microcontrollers are supported with a
full range of hardware and software development tools:
• Integrated Development Environment
- MPLAB® IDE Software
• Assemblers/Compilers/Linkers
- MPASMTM Assembler
- MPLAB C17 and MPLAB C18 C Compilers
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
• Simulators
- MPLAB SIM Software Simulator
• Emulators
- MPLAB ICE 2000 In-Circuit Emulator
- ICEPIC™ In-Circuit Emulator
• In-Circuit Debugger
- MPLAB ICD
• Device Programmers
- PRO MATE® II Universal Device Programmer
- PICSTART® Plus Entry-Level Development
Programmer
• Low Cost Demonstration Boards
- PICDEMTM 1 Demonstration Board
- PICDEM 2 Demonstration Board
- PICDEM 3 Demonstration Board
- PICDEM 17 Demonstration Board
- KEELOQ® Demonstration Board
14.1
The ability to use MPLAB IDE with multiple debugging
tools allows users to easily switch from the costeffective simulator to a full-featured emulator with
minimal retraining.
14.2
The MPASM assembler has a command line interface
and a Windows shell. It can be used as a stand-alone
application on a Windows 3.x or greater system, or it
can be used through MPLAB IDE. The MPASM assembler generates relocatable object files for the MPLINK
object linker, Intel® standard HEX files, MAP files to
detail memory usage and symbol reference, an absolute LST file that contains source lines and generated
machine code, and a COD file for debugging.
The MPASM assembler features include:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8-bit microcontroller market. The MPLAB IDE is a Windows®-based
application that contains:
 2002 Microchip Technology Inc.
MPASM Assembler
The MPASM assembler is a full-featured universal
macro assembler for all PICmicro MCU’s.
MPLAB Integrated Development
Environment Software
• An interface to debugging tools
- simulator
- programmer (sold separately)
- emulator (sold separately)
- in-circuit debugger (sold separately)
• A full-featured editor
• A project manager
• Customizable toolbar and key mapping
• A status bar
• On-line help
• Edit your source files (either assembly or ‘C’)
• One touch assemble (or compile) and download
to PICmicro emulator and simulator tools (automatically updates all project information)
• Debug using:
- source files
- absolute listing file
- machine code
• Integration into MPLAB IDE projects.
• User-defined macros to streamline assembly
code.
• Conditional assembly for multi-purpose source
files.
• Directives that allow complete control over the
assembly process.
14.3
MPLAB C17 and MPLAB C18
C Compilers
The MPLAB C17 and MPLAB C18 Code Development
Systems are complete ANSI ‘C’ compilers for
Microchip’s PIC17CXXX and PIC18CXXX family of
microcontrollers, respectively. These compilers provide
powerful integration capabilities and ease of use not
found with other compilers.
For easier source level debugging, the compilers provide symbol information that is compatible with the
MPLAB IDE memory display.
Preliminary
DS39598C-page 111
PIC16F818/819
14.4
MPLINK Object Linker/
MPLIB Object Librarian
14.6
The MPLINK object linker combines relocatable
objects created by the MPASM assembler and the
MPLAB C17 and MPLAB C18 C compilers. It can also
link relocatable objects from pre-compiled libraries,
using directives from a linker script.
The MPLIB object librarian is a librarian for precompiled code to be used with the MPLINK object
linker. When a routine from a library is called from
another source file, only the modules that contain that
routine will be linked in with the application. This allows
large libraries to be used efficiently in many different
applications. The MPLIB object librarian manages the
creation and modification of library files.
The MPLINK object linker features include:
• Integration with MPASM assembler and MPLAB
C17 and MPLAB C18 C compilers.
• Allows all memory areas to be defined as sections
to provide link-time flexibility.
The MPLIB object librarian features include:
• Easier linking because single libraries can be
included instead of many smaller files.
• Helps keep code maintainable by grouping
related modules together.
• Allows libraries to be created and modules to be
added, listed, replaced, deleted or extracted.
14.5
The MPLAB ICE universal in-circuit emulator is intended
to provide the product development engineer with a
complete microcontroller design tool set for PICmicro
microcontrollers (MCUs). Software control of the
MPLAB ICE in-circuit emulator is provided by the
MPLAB Integrated Development Environment (IDE),
which allows editing, building, downloading and source
debugging from a single environment.
The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring
features. Interchangeable processor modules allow the
system to be easily reconfigured for emulation of different processors. The universal architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new PICmicro microcontrollers.
The MPLAB ICE in-circuit emulator system has been
designed as a real-time emulation system, with
advanced features that are generally found on more
expensive development tools. The PC platform and
Microsoft® Windows environment were chosen to best
make these features available to you, the end user.
14.7
MPLAB SIM Software Simulator
The MPLAB SIM software simulator allows code development in a PC-hosted environment by simulating the
PICmicro series microcontrollers on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a file, or user-defined key press, to any of the pins. The
execution can be performed in single step, execute
until break, or trace mode.
MPLAB ICE High Performance
Universal In-Circuit Emulator with
MPLAB IDE
ICEPIC In-Circuit Emulator
The ICEPIC low cost, in-circuit emulator is a solution
for the Microchip Technology PIC16C5X, PIC16C6X,
PIC16C7X and PIC16CXXX families of 8-bit OneTime-Programmable (OTP) microcontrollers. The modular system can support different subsets of PIC16C5X
or PIC16CXXX products through the use of interchangeable personality modules, or daughter boards.
The emulator is capable of emulating without target
application circuitry being present.
The MPLAB SIM simulator fully supports symbolic debugging using the MPLAB C17 and the MPLAB C18 C compilers and the MPASM assembler. The software simulator
offers the flexibility to develop and debug code outside of
the laboratory environment, making it an excellent multiproject software development tool.
DS39598C-page 112
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
14.8
MPLAB ICD In-Circuit Debugger
Microchip's In-Circuit Debugger, MPLAB ICD, is a powerful, low cost, run-time development tool. This tool is
based on the FLASH PICmicro MCUs and can be used
to develop for this and other PICmicro microcontrollers.
The MPLAB ICD utilizes the in-circuit debugging capability built into the FLASH devices. This feature, along
with Microchip's In-Circuit Serial ProgrammingTM protocol, offers cost-effective in-circuit FLASH debugging
from the graphical user interface of the MPLAB
Integrated Development Environment. This enables a
designer to develop and debug source code by watching variables, single-stepping and setting break points.
Running at full speed enables testing hardware in realtime.
14.9
PRO MATE II Universal Device
Programmer
The PRO MATE II universal device programmer is a
full-featured programmer, capable of operating in
stand-alone mode, as well as PC-hosted mode. The
PRO MATE II device programmer is CE compliant.
The PRO MATE II device programmer has programmable VDD and VPP supplies, which allow it to verify
programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for instructions
and error messages, keys to enter commands and a
modular detachable socket assembly to support various
package types. In stand-alone mode, the PRO MATE II
device programmer can read, verify, or program
PICmicro devices. It can also set code protection in this
mode.
14.10 PICSTART Plus Entry Level
Development Programmer
The PICSTART Plus development programmer is an
easy-to-use, low cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB
Integrated Development Environment software makes
using the programmer simple and efficient.
The PICSTART Plus development programmer supports all PICmicro devices with up to 40 pins. Larger pin
count devices, such as the PIC16C92X and
PIC17C76X, may be supported with an adapter socket.
The PICSTART Plus development programmer is CE
compliant.
 2002 Microchip Technology Inc.
14.11 PICDEM 1 Low Cost PICmicro
Demonstration Board
The PICDEM 1 demonstration board is a simple board
which demonstrates the capabilities of several of
Microchip’s microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A),
PIC16C61, PIC16C62X, PIC16C71, PIC16C8X,
PIC17C42, PIC17C43 and PIC17C44. All necessary
hardware and software is included to run basic demo
programs. The user can program the sample microcontrollers provided with the PICDEM 1 demonstration
board on a PRO MATE II device programmer, or a
PICSTART Plus development programmer, and easily
test firmware. The user can also connect the
PICDEM 1 demonstration board to the MPLAB ICE incircuit emulator and download the firmware to the emulator for testing. A prototype area is available for the
user to build some additional hardware and connect it
to the microcontroller socket(s). Some of the features
include an RS-232 interface, a potentiometer for simulated analog input, push button switches and eight
LEDs connected to PORTB.
14.12 PICDEM 2 Low Cost PIC16CXX
Demonstration Board
The PICDEM 2 demonstration board is a simple demonstration board that supports the PIC16C62,
PIC16C64, PIC16C65, PIC16C73 and PIC16C74
microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample
microcontrollers provided with the PICDEM 2 demonstration board on a PRO MATE II device programmer,
or a PICSTART Plus development programmer, and
easily test firmware. The MPLAB ICE in-circuit emulator may also be used with the PICDEM 2 demonstration
board to test firmware. A prototype area has been provided to the user for adding additional hardware and
connecting it to the microcontroller socket(s). Some of
the features include a RS-232 interface, push button
switches, a potentiometer for simulated analog input, a
serial EEPROM to demonstrate usage of the I2CTM bus
and separate headers for connection to an LCD
module and a keypad.
Preliminary
DS39598C-page 113
PIC16F818/819
14.13 PICDEM 3 Low Cost PIC16CXXX
Demonstration Board
The PICDEM 3 demonstration board is a simple demonstration board that supports the PIC16C923 and
PIC16C924 in the PLCC package. It will also support
future 44-pin PLCC microcontrollers with an LCD Module. All the necessary hardware and software is
included to run the basic demonstration programs. The
user can program the sample microcontrollers provided with the PICDEM 3 demonstration board on a
PRO MATE II device programmer, or a PICSTART Plus
development programmer with an adapter socket, and
easily test firmware. The MPLAB ICE in-circuit emulator may also be used with the PICDEM 3 demonstration
board to test firmware. A prototype area has been provided to the user for adding hardware and connecting it
to the microcontroller socket(s). Some of the features
include a RS-232 interface, push button switches, a
potentiometer for simulated analog input, a thermistor
and separate headers for connection to an external
LCD module and a keypad. Also provided on the
PICDEM 3 demonstration board is a LCD panel, with 4
commons and 12 segments, that is capable of displaying time, temperature and day of the week. The
PICDEM 3 demonstration board provides an additional
RS-232 interface and Windows software for showing
the demultiplexed LCD signals on a PC. A simple serial
interface allows the user to construct a hardware
demultiplexer for the LCD signals.
DS39598C-page 114
14.14 PICDEM 17 Demonstration Board
The PICDEM 17 demonstration board is an evaluation
board that demonstrates the capabilities of several
Microchip microcontrollers, including PIC17C752,
PIC17C756A, PIC17C762 and PIC17C766. All necessary hardware is included to run basic demo programs,
which are supplied on a 3.5-inch disk. A programmed
sample is included and the user may erase it and
program it with the other sample programs using the
PRO MATE II device programmer, or the PICSTART
Plus development programmer, and easily debug and
test the sample code. In addition, the PICDEM 17 demonstration board supports downloading of programs to
and executing out of external FLASH memory on board.
The PICDEM 17 demonstration board is also usable
with the MPLAB ICE in-circuit emulator, or the
PICMASTER emulator and all of the sample programs
can be run and modified using either emulator. Additionally, a generous prototype area is available for user
hardware.
14.15 KEELOQ Evaluation and
Programming Tools
KEELOQ evaluation and programming tools support
Microchip’s HCS Secure Data Products. The HCS evaluation kit includes a LCD display to show changing
codes, a decoder to decode transmissions and a programming interface to program test transmitters.
Preliminary
 2002 Microchip Technology Inc.
Software Tools
Programmers Debugger Emulators
PIC12CXXX
PIC14000
PIC16C5X
PIC16C6X
PIC16CXXX
PIC16F62X
PIC16C7X
9
9
9
9
9
9
 2002 Microchip Technology Inc.
Preliminary
9
9
9
†
†
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
MCP2510
* Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB® ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77.
** Contact Microchip Technology Inc. for availability date.
† Development tool is available on select devices.
MCP2510 CAN Developer’s Kit
9
13.56 MHz Anticollision
microIDTM Developer’s Kit
9
125 kHz Anticollision microIDTM
Developer’s Kit
9
125 kHz microIDTM
Developer’s Kit
MCRFXXX
microIDTM Programmer’s Kit
9
†
9**
9
9*
9
9
9
9
9
9
9
9
9**
9**
PIC18FXXX
9
24CXX/
25CXX/
93CXX
KEELOQ® Transponder Kit
9
9
9
9
9
9
9
9
9
HCSXXX
KEELOQ® Evaluation Kit
PICDEMTM 17 Demonstration
Board
PICDEMTM 14A Demonstration
Board
PICDEMTM 3 Demonstration
Board
PICDEMTM 2 Demonstration
Board
PICDEMTM 1 Demonstration
Board
9
9
PRO MATE® II
Universal Device Programmer
9
9
9
9
PICSTART® Plus Entry Level
Development Programmer
9
9
9*
9
9
MPLAB® ICD In-Circuit
Debugger
9
9
9
9
9
9
9
9
ICEPICTM In-Circuit Emulator
9
9
PIC16C7XX
9
9
9
PIC16C8X/
PIC16F8X
9
9
9
PIC16F8XX
9
9
9
PIC16C9XX
MPLAB® ICE In-Circuit Emulator
9
9
PIC17C4X
9
9
9
PIC17C7XX
MPASMTM Assembler/
MPLINKTM Object Linker
9
PIC18CXX2
MPLAB® C18 C Compiler
MPLAB® C17 C Compiler
TABLE 14-1:
Demo Boards and Eval Kits
MPLAB® Integrated
Development Environment
PIC16F818/819
DEVELOPMENT TOOLS FROM MICROCHIP
DS39598C-page 115
PIC16F818/819
NOTES:
DS39598C-page 116
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
15.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Ambient temperature under bias............................................................................................................ -55°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on any pin with respect to VSS (except VDD and MCLR) ................................................... -0.3V to (VDD + 0.3V)
Voltage on VDD with respect to VSS ............................................................................................................ -0.3 to +7.5V
Voltage on MCLR with respect to VSS (Note 2) .............................................................................................-0.3 to +14V
Total power dissipation (Note 1) ..................................................................................................................................1W
Maximum current out of VSS pin ...........................................................................................................................200 mA
Maximum current into VDD pin ..............................................................................................................................200 mA
Input clamp current, IIK (VI < 0 or VI > VDD)..................................................................................................................... ± 20 mA
Output clamp current, IOK (VO < 0 or VO > VDD) ............................................................................................................. ± 20 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by PORTA ........................................................................................................................100 mA
Maximum current sourced by PORTA...................................................................................................................100 mA
Maximum current sunk by PORTB........................................................................................................................100 mA
Maximum current sourced by PORTB ..................................................................................................................100 mA
Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD - VOH) x IOH} + ∑(VOl x IOL)
2: Voltage spikes at the MCLR pin may cause latchup. A series resistor of greater than 1 kΩ should be used
to pull MCLR to VDD, rather than tying the pin directly to VDD.
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 117
PIC16F818/819
FIGURE 15-1:
PIC16F818/819 VOLTAGE-FREQUENCY GRAPH
6.0V
5.5V
Voltage
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
16 MHz
20 MHz
Frequency
FIGURE 15-2:
PIC16LF818/819 VOLTAGE-FREQUENCY GRAPH
6.0V
5.5V
Voltage
5.0V
4.5V
4.0V
3.5V
3.0V
2.5V
2.0V
4 MHz
10 MHz
Frequency
FMAX = (12 MHz/V) (VDDAPPMIN - 2.5V) + 4 MHz
Note 1: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application.
Note 2: FMAX has a maximum frequency of 10 MHz.
DS39598C-page 118
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
15.1
DC Characteristics: Supply Voltage
PIC16F818/819 (Industrial, Extended)
PIC16LF818/819 (Industrial)
PIC16LF818/819
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC16F818/819
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Symbol
VDD
Characteristic
Min
Typ
Max
Units
Conditions
Supply Voltage
D001
PIC16LF818/819
2.0
—
5.5
V
D001
PIC16F818/819
4.0
—
5.5
V
D002
VDR
RAM Data Retention
Voltage(1)
1.5
—
—
V
D003
VPOR
VDD Start Voltage
to ensure internal
Power-on Reset signal
—
—
0.7
V
D004
SVDD
VDD Rise Rate
to ensure internal
Power-on Reset signal
0.05
—
—
VBOR
Brown-out Reset Voltage
HS, XT, RC and LP Osc mode
See Section 12.4, "Power-on Reset (POR)" for
details
V/ms See Section 12.4, "Power-on Reset (POR)" for
details
D005
PIC16LF818/819
3.65
—
4.35
V
D005
PIC16F818/819
3.65
—
4.35
V
FMAX = 14 MHz(2)
Legend: Shading of rows is to assist in readability of the table.
Note 1: This is the limit to which VDD can be lowered in SLEEP mode, or during a device RESET, without losing RAM data.
2: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 119
PIC16F818/819
15.2
DC Characteristics: Power-down and Supply Current
PIC16F818/819 (Industrial, Extended)
PIC16LF818/819 (Industrial)
PIC16LF818/819
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC16F818/819
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Device
Typ
Max
Units
Conditions
0.2
TBD
µA
-40°C
0.2
TBD
µA
25°C
Power-down Current (IPD)(1)
PIC16LF818/819
PIC16LF818/819
All devices
0.3
TBD
µA
85°C
0.3
TBD
µA
-40°C
0.3
TBD
µA
25°C
0.4
TBD
µA
85°C
-40°C
0.4
TBD
µA
0.5
TBD
µA
25°C
0.6
TBD
µA
85°C
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with
the part in SLEEP mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active Operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
DS39598C-page 120
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
15.2
DC Characteristics: Power-down and Supply Current
PIC16F818/819 (Industrial, Extended)
PIC16LF818/819 (Industrial) (Continued)
PIC16LF818/819
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC16F818/819
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Device
Typ
Max
Units
Conditions
8
TBD
µA
-40°C
10
TBD
µA
25°C
14
TBD
µA
85°C
17
TBD
µA
-40°C
16
TBD
µA
25°C
15
TBD
µA
85°C
34
TBD
µA
-40°C
Supply Current (IDD)(2,3)
PIC16LF818/819
PIC16LF818/819
All devices
PIC16LF818/819
PIC16LF818/819
All devices
PIC16LF818/819
PIC16LF818/819
All devices
28
TBD
µA
25°C
25
TBD
µA
85°C
85
TBD
µA
-40°C
87
TBD
µA
25°C
83
TBD
µA
85°C
200
TBD
µA
-40°C
165
TBD
µA
25°C
150
TBD
µA
85°C
408
TBD
µA
-40°C
338
TBD
µA
25°C
300
TBD
µA
85°C
233
TBD
µA
-40°C
240
TBD
µA
25°C
243
TBD
µA
85°C
466
TBD
µA
-40°C
429
TBD
µA
25°C
416
TBD
µA
85°C
972
TBD
µA
-40°C
874
TBD
µA
25°C
835
TBD
µA
85°C
VDD = 2.0V
VDD = 3.0V
FOSC = 32 kHz
(LP Oscillator)
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
FOSC = 1 MHZ
(RC Oscillator)
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
FOSC = 4 MHz
(RC Oscillator)
VDD = 5.0V
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with
the part in SLEEP mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active Operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 121
PIC16F818/819
15.2
DC Characteristics: Power-down and Supply Current
PIC16F818/819 (Industrial, Extended)
PIC16LF818/819 (Industrial) (Continued)
PIC16LF818/819
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC16F818/819
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Device
Typ
Max
Units
Conditions
Supply Current (IDD)(2,3)
All devices
All devices
1.4
TBD
mA
-40°C
1.3
TBD
mA
25°C
1.0
TBD
mA
85°C
2.4
TBD
mA
-40°C
1.8
TBD
mA
25°C
1.6
TBD
mA
85°C
VDD = 4.0V
FOSC = 20 MHZ
(HS Oscillator)
VDD = 5.0V
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with
the part in SLEEP mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active Operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
DS39598C-page 122
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
15.2
DC Characteristics: Power-down and Supply Current
PIC16F818/819 (Industrial, Extended)
PIC16LF818/819 (Industrial) (Continued)
PIC16LF818/819
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC16F818/819
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Device
Typ
Max
Units
7
TBD
µA
Conditions
Supply Current (IDD)(2,3)
PIC16LF818/819
PIC16LF818/819
All devices
PIC16LF818/819
PIC16LF818/819
All devices
PIC16LF818/819
PIC16LF818/819
All devices
-40°C
7
TBD
µA
25°C
8
TBD
µA
85°C
16
TBD
µA
-40°C
14
TBD
µA
25°C
13
TBD
µA
85°C
35
TBD
µA
-40°C
28
TBD
µA
25°C
25
TBD
µA
85°C
111
TBD
µA
-40°C
116
TBD
µA
25°C
122
TBD
µA
85°C
164
TBD
µA
-40°C
162
TBD
µA
25°C
165
TBD
µA
85°C
278
TBD
µA
-40°C
266
TBD
µA
25°C
266
TBD
µA
85°C
288
TBD
µA
-40°C
294
TBD
µA
25°C
299
TBD
µA
85°C
441
TBD
µA
-40°C
428
TBD
µA
25°C
428
TBD
µA
85°C
791
TBD
µA
-40°C
752
TBD
µA
25°C
747
TBD
µA
85°C
VDD = 2.0V
VDD = 3.0V
FOSC = 31.25 kHz
(Internal RC Oscillator)
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
FOSC = 1 MHz
(Internal RC Oscillator)
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
FOSC = 4 MHz
(Internal RC Oscillator)
VDD = 5.0V
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with
the part in SLEEP mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active Operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 123
PIC16F818/819
15.2
DC Characteristics: Power-down and Supply Current
PIC16F818/819 (Industrial, Extended)
PIC16LF818/819 (Industrial) (Continued)
PIC16LF818/819
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC16F818/819
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Device
Typ
Max
Units
847
TBD
µA
Conditions
Supply Current (IDD)(2,3)
PIC16LF818/819
All devices
-40°C
796
TBD
µA
25°C
784
TBD
µA
85°C
1.6
TBD
mA
-40°C
1.5
TBD
mA
25°C
1.4
TBD
mA
85°C
VDD = 3.0V
FOSC = 8 MHz
(Internal RC Oscillator)
VDD = 5.0V
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with
the part in SLEEP mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active Operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
DS39598C-page 124
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
15.2
DC Characteristics: Power-down and Supply Current
PIC16F818/819 (Industrial, Extended)
PIC16LF818/819 (Industrial) (Continued)
PIC16LF818/819
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC16F818/819
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Device
Typ
Max
Units
Conditions
Module Differential Currents (∆IWDT, ∆IBOR, ∆ILVD, ∆IOSCB, ∆IAD)
D022
(∆IWDT)
Watchdog Timer
1.3
TBD
µA
-40°C
0.7
TBD
µA
25°C
0.2
TBD
µA
85°C
1.0
TBD
µA
-40°C
1.4
TBD
µA
25°C
2.4
TBD
µA
85°C
1.9
TBD
µA
-40°C
2.0
TBD
µA
25°C
3.0
TBD
µA
85°C
D022A
(∆IBOR)
Brown-out Reset
85
TBD
µA
-40°C to
+85°C
D025
(∆IOSCB)
Timer1 Oscillator
2.2
TBD
µA
-10°C
2.6
TBD
µA
25°C
3.6
TBD
µA
70°C
3.0
TBD
µA
-10°C
3.5
TBD
µA
25°C
4.7
TBD
µA
70°C
3.9
TBD
µA
-10°C
4.3
TBD
µA
25°C
70°C
D026
(∆IAD)
A/D Converter
VDD = 2.0V
VDD = 3.0V
VDD = 5.0V
VDD = 5.0V
VDD = 2.0V
VDD = 3.0V
32 kHz on Timer1
VDD = 5.0V
6.6
TBD
µA
44
TBD
µA
VDD = 2.0V
53
TBD
µA
VDD = 3.0V
61
TBD
µA
VDD = 5.0V
A/D on, not converting
Legend: Shading of rows is to assist in readability of the table.
Note 1: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with
the part in SLEEP mode, with all I/O pins in high-impedance state and tied to VDD or VSS, and all features that add delta
current disabled (such as WDT, Timer1 Oscillator, BOR, etc.).
2: The supply current is mainly a function of operating voltage, frequency and mode. Other factors, such as I/O pin loading
and switching rate, oscillator type and circuit, internal code execution pattern and temperature, also have an impact on
the current consumption.
The test conditions for all IDD measurements in active Operation mode are:
OSC1 = external square wave, from rail-to-rail; all I/O pins tri-stated, pulled to VDD;
MCLR = VDD; WDT enabled/disabled as specified.
3: For RC oscillator configurations, current through REXT is not included. The current through the resistor can be estimated
by the formula Ir = VDD/2REXT (mA) with REXT in kΩ.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 125
PIC16F818/819
15.3
DC Characteristics: Internal RC Accuracy
PIC16F818/819 (Industrial, Extended)
PIC16LF818/819 (Industrial)
PIC16F818
(Industrial)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
PIC16F818/819
(Industrial, Extended)
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Param
No.
Device
Min
Typ
Max
Units
Conditions
INTOSC Accuracy @ Freq = 8 MHz, 4 MHz, 2 MHz, 1 MHz, 500 kHz, 250 kHz, 125 kHz(1)
F1
PIC16LF818/819
TBD
+/-1
TBD
%
25°C
VDD = 2.0V
TBD
+/-1
TBD
%
25°C
VDD = 3.0V
TBD
+/-1
TBD
%
25°C
VDD = 5.0V
PIC16LF818/819 28.125 31.25 34.375
kHz
25°C
VDD = 2.0V
F5
28.125 31.25 34.375
kHz
25°C
VDD = 3.0V
F6
All devices 28.125 31.25 34.375
kHz
25°C
VDD = 5.0V
F2
F3
All devices
INTRC Accuracy @ Freq = 31.25 kHz(2)
F4
INTRC Stability(3)
F7
PIC16LF818/819
F8
F9
Legend:
Note 1:
2:
3:
All devices
TBD
1
TBD
%
25°C
VDD = 2.0V
TBD
1
TBD
%
25°C
VDD = 3.0V
TBD
1
TBD
%
25°C
VDD = 5.0V
Shading of rows is to assist in readability of the table.
Frequency calibrated at 25°C. OSCTUNE register can be used to compensate for temperature drift.
INTRC is used to calibrate INTOSC.
Change of INTRC frequency as VDD changes.
DS39598C-page 126
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
15.4
DC Characteristics:
PIC16F818/819 (Industrial, Extended)
PIC16LF818/819 (Industrial)
DC CHARACTERISTICS
Param
No.
Sym
VIL
Characteristic
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC Specification,
Section 15.1.
Min
Typ†
Max
Units
Conditions
Input Low Voltage
I/O ports:
D030
with TTL buffer
D030A
D031
with Schmitt Trigger buffer
VSS
—
0.15 VDD
V
For entire VDD range
VSS
—
0.8V
V
4.5V ≤ VDD ≤ 5.5V
VSS
—
0.2 VDD
V
D032
MCLR, OSC1 (in RC mode)
VSS
—
0.2 VDD
V
D033
OSC1 (in XT and LP mode)
VSS
—
0.3V
V
OSC1 (in HS mode)
VSS
—
0.3 VDD
V
VSS
—
0.3 VDD
V
For entire VDD range
2.0
—
VDD
V
4.5V ≤ VDD ≤ 5.5V
0.25 VDD
+ 0.8V
—
VDD
V
For entire VDD range
0.8 VDD
—
VDD
V
For entire VDD range
0.8 VDD
—
VDD
V
(Note 1)
Ports RB1 and RB4:
D034
with Schmitt Trigger buffer
VIH
Input High Voltage
I/O ports:
D040
with TTL buffer
D040A
D041
with Schmitt Trigger buffer
D042
MCLR
D042A
OSC1 (in XT and LP mode)
D043
1.6V
—
VDD
V
OSC1 (in HS mode)
0.7 VDD
—
VDD
V
OSC1 (in RC mode)
0.9 VDD
—
VDD
V
(Note 1)
0.7 VDD
—
VDD
V
For entire VDD range
50
250
400
µA
VDD = 5V, VPIN = VSS
—
±1
µA
Vss ≤ VPIN ≤ VDD, pin at
hi-impedance
Ports RB1 and RB4:
D044
with Schmitt Trigger buffer
IPURB PORTB Weak Pull-up Current
D070
IIL
Input Leakage Current (Notes 2, 3)
D060
I/O ports
—
D061
MCLR
—
—
±5
µA
Vss ≤ VPIN ≤ VDD
D063
OSC1
—
—
±5
µA
Vss ≤ VPIN ≤ VDD, XT, HS and LP
osc configuration
*
†
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PIC16F818/819 be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 127
PIC16F818/819
15.4
DC Characteristics:
PIC16F818/819 (Industrial, Extended)
PIC16LF818/819 (Industrial) (Continued)
DC CHARACTERISTICS
Param
No.
Sym
VOL
Characteristic
Standard Operating Conditions (unless otherwise stated)
Operating temperature
-40°C ≤ TA ≤ +85°C for industrial
-40°C ≤ TA ≤ +125°C for extended
Operating voltage VDD range as described in DC Specification,
Section 15.1.
Min
Typ†
Max
Units
Conditions
Output Low Voltage
D080
I/O ports
—
—
0.6
V
IOL = 8.5 mA, VDD = 4.5V,
-40°C to +125°C
D083
OSC2/CLKO (RC osc config)
—
—
0.6
V
IOL = 1.6 mA, VDD = 4.5V,
-40°C to +125°C
VOH
Output High Voltage
D090
I/O ports (Note 3)
VDD – 0.7
—
—
V
IOH = -3.0 mA, VDD = 4.5V,
-40°C to +125°C
D092
OSC2/CLKO (RC osc config)
VDD – 0.7
—
—
V
IOH = -1.3 mA, VDD = 4.5V,
-40°C to +125°C
In XT, HS and LP modes when
external clock is used to drive
OSC1
Capacitive Loading Specs on Output Pins
D100
COSC2 OSC2 pin
—
—
15
pF
D101
CIO
All I/O pins and OSC2
(in RC mode)
—
—
50
pF
D102
CB
SCL, SDA in I2C mode
—
—
400
pF
D120
ED
Endurance
100K
10K
1M
100K
—
—
D121
VDRW VDD for read/write
VMIN
—
5.5
V
D122
TDEW Erase/write cycle time
—
4
8
ms
Endurance
10K
1K
100K
10K
—
—
E/W -40°C to 85°C
E/W +85°C to +125°C
VDD for read
VMIN
—
5.5
V
VDD for erase/write
VMIN
—
5.5
V
Data EEPROM Memory
E/W -40°C to 85°C
E/W +85°C to +125°C
Using EECON to read/write,
VMIN = min. operating voltage
Program FLASH Memory
D130
EP
D131
VPR
D132A
D133
TPE
Erase cycle time
—
2
4
ms
D134
TPW
Write cycle time
—
2
4
ms
Using EECON to read/write,
VMIN = min. operating voltage
*
†
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the
PIC16F818/819 be driven with external clock in RC mode.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels
represent normal operating conditions. Higher leakage current may be measured at different input voltages.
3: Negative current is defined as current sourced by the pin.
DS39598C-page 128
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
15.5
Timing Parameter Symbology
The timing parameter symbols have been created
using one of the following formats:
1. TppS2ppS
3. TCC:ST
(I2C specifications only)
2. TppS
4. Ts
(I2C specifications only)
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKO
cs
CS
di
SDI
do
SDO
dt
Data in
io
I/O port
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (Hi-impedance)
L
Low
I2C only
AA
BUF
output access
Bus free
TCC:ST (I2C specifications only)
CC
HD
Hold
ST
DAT
DATA input hold
STA
START condition
FIGURE 15-3:
T
Time
osc
rd
rw
sc
ss
t0
t1
wr
OSC1
RD
RD or WR
SCK
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
Hi-impedance
High
Low
High
Low
SU
Setup
STO
STOP condition
LOAD CONDITIONS
Load Condition 2
Load Condition 1
VDD/2
RL
CL
Pin
VSS
RL = 464Ω
CL = 50 pF
15 pF
 2002 Microchip Technology Inc.
CL
Pin
VSS
for all pins except OSC2, but including PORTD and PORTE outputs as ports
for OSC2 output
Preliminary
DS39598C-page 129
PIC16F818/819
FIGURE 15-4:
EXTERNAL CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
OSC1
1
3
4
3
4
2
CLKO
TABLE 15-1:
Parameter
No.
EXTERNAL CLOCK TIMING REQUIREMENTS
Sym
FOSC
Characteristic
External CLKI Frequency
(Note 1)
Oscillator Frequency
(Note 1)
1
TOSC
Min
Typ†
Max
Units
DC
—
4
MHz XT and RC Osc mode
DC
—
20
MHz HS Osc mode
DC
—
200
DC
—
4
kHz
Conditions
LP Osc mode
MHz RC Osc mode
0.1
—
4
MHz XT Osc mode
4
5
—
—
20
200
MHz HS Osc mode
kHz LP Osc mode
External CLKI Period
(Note 1)
250
—
—
ns
XT and RC Osc mode
50
—
—
ns
HS Osc mode
5
—
—
µs
LP Osc mode
Oscillator Period
(Note 1)
250
—
—
ns
RC Osc mode
250
—
10,000
ns
XT Osc mode
100
—
250
ns
HS Osc mode
50
—
250
ns
HS Osc mode
5
—
—
µs
LP Osc mode
ns
TCY = 4/FOSC
2
TCY
Instruction Cycle Time
(Note 1)
200
TCY
DC
3
TosL,
TosH
External Clock in (OSC1) High or
Low Time
100
—
—
ns
XT oscillator
2.5
—
—
µs
LP oscillator
15
—
—
ns
HS oscillator
TosR,
TosF
External Clock in (OSC1) Rise or
Fall Time
—
—
25
ns
XT oscillator
4
—
—
50
ns
LP oscillator
—
—
15
ns
HS oscillator
†
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance
only and are not tested.
Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are
based on characterization data for that particular oscillator type under standard operating conditions, with
the device executing code. Exceeding these specified limits may result in an unstable oscillator operation
and/or higher than expected current consumption. All devices are tested to operate at "min." values with an
external clock applied to the OSC1/CLKI pin. When an external clock input is used, the "max." cycle time
limit is "DC" (no clock) for all devices.
DS39598C-page 130
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
FIGURE 15-5:
CLKO AND I/O TIMING
Q1
Q4
Q2
Q3
OSC1
11
10
CLKO
13
19
14
12
18
16
I/O Pin
(Input)
15
17
I/O Pin
(Output)
New Value
Old Value
20, 21
Note: Refer to Figure 15-3 for load conditions.
TABLE 15-2:
Param
No.
CLKO AND I/O TIMING REQUIREMENTS
Min
Typ†
Max
OSC1↑ to CLKO↓
—
75
200
ns
(Note 1)
11*
TosH2ckH OSC1↑ to CLKO↑
—
75
200
ns
(Note 1)
12*
TckR
CLKO rise time
—
35
100
ns
(Note 1)
13*
TckF
CLKO fall time
—
35
100
ns
(Note 1)
14*
TckL2ioV
CLKO ↓ to Port out valid
—
—
0.5 TCY + 20
ns
(Note 1)
10*
Symbol
TosH2ckL
Characteristic
Units Conditions
15*
TioV2ckH
Port in valid before CLKO ↑
TOSC + 200
—
—
ns
(Note 1)
16*
TckH2ioI
Port in hold after CLKO ↑
0
—
—
ns
(Note 1)
17*
TosH2ioV
OSC1↑ (Q1 cycle) to Port out valid
—
100
255
ns
18*
TosH2ioI
OSC1↑ (Q2 cycle) to
Port input invalid (I/O in
hold time)
PIC16F818/819
100
—
—
ns
PIC16LF818/819
200
—
—
ns
19*
TioV2osH
Port input valid to OSC1↑ (I/O in setup time)
0
—
—
ns
20*
TIOR
Port output rise time
PIC16F818/819
—
10
40
ns
PIC16LF818/819
—
—
145
ns
21*
TIOF
Port output fall time
PIC16F818/819
—
10
40
ns
—
—
145
ns
22††*
TINP
INT pin high or low time
TCY
—
—
ns
23††*
TRBP
RB7:RB4 change INT high or low time
TCY
—
—
ns
PIC16LF818/819
*
†
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
†† These parameters are asynchronous events, not related to any internal clock edges.
Note 1: Measurements are taken in RC mode where CLKO output is 4 x TOSC.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 131
PIC16F818/819
FIGURE 15-6:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING
VDD
MCLR
30
Internal
POR
33
PWRT
Time-out
32
OSC
Time-out
Internal
RESET
Watchdog
Timer
Reset
31
34
34
I/O Pins
Note: Refer to Figure 15-3 for load conditions.
FIGURE 15-7:
BROWN-OUT RESET TIMING
VBOR
VDD
35
TABLE 15-3:
Parameter
No.
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER,
AND BROWN-OUT RESET REQUIREMENTS
Sym
Characteristic
Min
30
TmcL
MCLR Pulse Width (Low)
31*
TWDT
Watchdog Timer Time-out Period
(No Prescaler)
32
TOST
Oscillation Start-up Timer Period
33*
TPWRT
Power-up Timer Period
34
TIOZ
I/O Hi-impedance from MCLR Low
or Watchdog Timer Reset
TBOR
Brown-out Reset Pulse Width
35
*
†
Typ†
Max
Units
Conditions
2
—
—
µs
VDD = 5V, -40°C to +85°C
TBD
16
TBD
ms
VDD = 5V, -40°C to +85°C
—
1024 TOSC
—
—
TOSC = OSC1 period
TBD
72
TBD
ms
VDD = 5V, -40°C to +85°C
—
—
2.1
µs
100
—
—
µs
VDD ≤ VBOR (D005)
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
DS39598C-page 132
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
FIGURE 15-8:
TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
RA4/T0CKI
41
40
42
RB6/T1OSO/T1CKI
46
45
47
48
TMR0 or TMR1
Note: Refer to Figure 15-3 for load conditions.
TABLE 15-4:
Param
No.
40*
41*
42*
45*
46*
47*
TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS
Symbol
Tt0H
Tt0L
Tt0P
Tt1H
Tt1L
Tt1P
Characteristic
T0CKI High Pulse Width
T0CKI Low Pulse Width
T0CKI Period
48
Typ†
Max
Units
Conditions
No Prescaler
0.5 TCY + 20
—
—
ns
With Prescaler
10
—
—
ns
Must also meet
parameter 42
No Prescaler
0.5 TCY + 20
—
—
ns
With Prescaler
10
—
—
ns
No Prescaler
TCY + 40
—
—
ns
Greater of:
20 or TCY + 40
N
—
—
ns
N = prescale
value (2, 4, ...,
256)
0.5 TCY + 20
Must also meet
parameter 47
—
—
ns
Synchronous,
PIC16F818/819
Prescaler = 2,4,8 PIC16LF818/819
15
—
—
ns
25
—
—
ns
Asynchronous
PIC16F818/819
30
—
—
ns
PIC16LF818/819
50
—
—
ns
0.5 TCY + 20
—
—
ns
Synchronous,
PIC16F818/819
Prescaler = 2,4,8 PIC16LF818/819
15
—
—
ns
25
—
—
ns
Asynchronous
PIC16F818/819
30
—
—
ns
PIC16LF818/819
50
—
—
ns
PIC16F818/819
Greater of:
30 or TCY + 40
N
—
—
ns
PIC16LF818/819
Greater of:
50 or TCY + 40
N
T1CKI Low Time Synchronous, Prescaler = 1
T1CKI Input
Period
Synchronous
60
—
—
ns
PIC16LF818/819
100
—
—
ns
DC
—
32.768
kHz
2 TOSC
—
7 TOSC
—
Timer1 Oscillator Input Frequency Range
(Oscillator enabled by setting bit T1OSCEN)
Must also meet
parameter 47
N = prescale
value (1, 2, 4, 8)
N = prescale
value (1, 2, 4, 8)
PIC16F818/819
TCKEZtmr1 Delay from External Clock Edge to Timer Increment
*
†
Must also meet
parameter 42
With Prescaler
T1CKI High Time Synchronous, Prescaler = 1
Asynchronous
Ft1
Min
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 133
PIC16F818/819
FIGURE 15-9:
CAPTURE/COMPARE/PWM TIMINGS (CCP1)
CCP1
(Capture Mode)
50
51
52
CCP1
(Compare or PWM Mode)
53
54
Note: Refer to Figure 15-3 for load conditions.
TABLE 15-5:
CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1)
Param
Symbol
No.
50*
TccL
Characteristic
CCP1
No Prescaler
Input Low Time
Min
PIC16F818/819
With Prescaler PIC16LF818/819
51*
TccH
CCP1
Input High
Time
No Prescaler
PIC16F818/819
With Prescaler PIC16LF818/819
Typ† Max Units
0.5 TCY + 20
—
—
ns
10
—
—
ns
20
—
—
ns
0.5 TCY + 20
—
—
ns
10
—
—
ns
20
—
—
ns
3 TCY + 40
N
—
—
ns
—
10
25
ns
52*
TccP
CCP1 Input Period
53*
TccR
CCP1 Output Rise Time
PIC16F818/819
PIC16LF818/819
—
25
50
ns
54*
TccF
CCP1 Output Fall Time
PIC16F818/819
—
10
25
ns
PIC16LF818/819
—
25
45
ns
*
†
Conditions
N = prescale
value (1,4 or 16)
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only
and are not tested.
DS39598C-page 134
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
FIGURE 15-10:
SPI MASTER MODE TIMING (CKE = 0, SMP = 0)
SS
70
SCK
(CKP = 0)
71
72
78
79
79
78
SCK
(CKP = 1)
80
Bit6 - - - - - -1
MSb
SDO
LSb
75, 76
SDI
Bit6 - - - -1
MSb In
LSb In
74
73
Note: Refer to Figure 15-3 for load conditions.
FIGURE 15-11:
SPI MASTER MODE TIMING (CKE = 1, SMP = 1)
SS
81
SCK
(CKP = 0)
71
72
79
73
SCK
(CKP = 1)
80
78
SDO
MSb
Bit6 - - - - - -1
LSb
Bit6 - - - -1
LSb In
75, 76
SDI
MSb In
74
Note: Refer to Figure 15-3 for load conditions.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 135
PIC16F818/819
FIGURE 15-12:
SPI SLAVE MODE TIMING (CKE = 0)
SS
70
SCK
(CKP = 0)
83
71
72
78
79
79
78
SCK
(CKP = 1)
80
Bit6 - - - - - -1
MSb
SDO
LSb
77
75, 76
SDI
MSb In
Bit6 - - - -1
LSb In
74
73
Note: Refer to Figure 15-3 for load conditions.
FIGURE 15-13:
SPI SLAVE MODE TIMING (CKE = 1)
82
SS
SCK
(CKP = 0)
70
83
71
72
SCK
(CKP = 1)
80
SDO
MSb
Bit6 - - - - - -1
LSb
75, 76
SDI
MSb In
77
Bit6 - - - -1
LSb In
74
Note: Refer to Figure 15-3 for load conditions.
DS39598C-page 136
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
TABLE 15-6:
Param
No.
SPI MODE REQUIREMENTS
Symbol
Characteristic
Min
Typ†
Max
Units
TCY
—
—
ns
70*
TssL2scH,
TssL2scL
SS↓ to SCK↓ or SCK↑ input
71*
TscH
SCK input high time (Slave mode)
TCY + 20
—
—
ns
72*
TscL
SCK input low time (Slave mode)
TCY + 20
—
—
ns
73*
TdiV2scH,
TdiV2scL
Setup time of SDI data input to SCK edge
100
—
—
ns
74*
TscH2diL,
TscL2diL
Hold time of SDI data input to SCK edge
100
—
—
ns
75*
TdoR
SDO data output rise time
—
—
10
25
25
50
ns
ns
ns
PIC16F818/819
PIC16LF818/819
76*
TdoF
SDO data output fall time
—
10
25
77*
TssH2doZ
SS↑ to SDO output hi-impedance
10
—
50
ns
78*
TscR
SCK output rise time
(Master mode)
—
—
10
25
25
50
ns
ns
79*
TscF
SCK output fall time (Master mode)
—
10
25
ns
80*
TscH2doV,
TscL2doV
SDO data output valid after SCK
edge
—
—
—
—
50
145
ns
ns
81*
TdoV2scH,
TdoV2scL
SDO data output setup to SCK edge
TCY
—
—
ns
—
—
50
ns
1.5 TCY + 40
—
—
ns
PIC16F818/819
PIC16LF818/819
PIC16F818/819
PIC16LF818/819
82*
TssL2doV
SDO data output valid after SS↓ edge
83*
TscH2ssH,
TscL2ssH
SS ↑ after SCK edge
*
†
Conditions
These parameters are characterized but not tested.
Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not
tested.
I2C BUS START/STOP BITS TIMING
FIGURE 15-14:
SCL
91
93
90
92
SDA
STOP
Condition
START
Condition
Note: Refer to Figure 15-3 for load conditions.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 137
PIC16F818/819
TABLE 15-7:
Param
No.
I2C BUS START/STOP BITS REQUIREMENTS
Symbol
90*
TSU:STA
91*
THD:STA
92*
TSU:STO
93
THD:STO
Characteristic
Min Typ Max Units
START condition
100 kHz mode
4700
—
—
Setup time
START condition
400 kHz mode
600
—
—
100 kHz mode
4000
—
—
Hold time
STOP condition
400 kHz mode
600
—
—
100 kHz mode
4700
—
—
Setup time
STOP condition
400 kHz mode
600
—
—
100 kHz mode
4000
—
—
Hold time
400 kHz mode
600
—
—
Conditions
ns
Only relevant for Repeated
START condition
ns
After this period the first clock
pulse is generated
ns
ns
* These parameters are characterized but not tested.
FIGURE 15-15:
I2C BUS DATA TIMING
103
102
100
101
SCL
90
106
107
91
92
SDA
In
109
109
110
SDA
Out
Note: Refer to Figure 15-3 for load conditions.
DS39598C-page 138
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
TABLE 15-8:
Param.
No.
100*
I2C BUS DATA REQUIREMENTS
Symbol
THIGH
Characteristic
Clock high time
100 kHz mode
400 kHz mode
TLOW
Clock low time
103*
90*
91*
106*
107*
92*
109*
110*
TR
TF
TSU:STA
THD:STA
THD:DAT
TSU:DAT
TSU:STO
TAA
TBUF
CB
Units
4.0
—
µs
µs
0.6
—
—
100 kHz mode
4.7
—
µs
400 kHz mode
1.3
—
µs
SSP Module
102*
Max
1.5 TCY
SSP Module
101*
Min
Conditions
1.5 TCY
—
SDA and SCL rise
time
100 kHz mode
—
1000
ns
400 kHz mode
20 + 0.1 CB
300
ns
SDA and SCL fall
time
100 kHz mode
—
300
ns
400 kHz mode
20 + 0.1 CB
300
ns
CB is specified to be from
10 - 400 pF
START condition
setup time
100 kHz mode
4.7
—
µs
400 kHz mode
0.6
—
µs
Only relevant for
Repeated START
condition
START condition
hold time
100 kHz mode
4.0
—
µs
400 kHz mode
0.6
—
µs
Data input hold time 100 kHz mode
0
—
ns
400 kHz mode
0
0.9
µs
Data input setup
time
100 kHz mode
250
—
ns
400 kHz mode
100
—
ns
STOP condition
setup time
100 kHz mode
4.7
—
µs
400 kHz mode
0.6
—
µs
Output valid from
clock
100 kHz mode
—
3500
ns
400 kHz mode
—
—
ns
Bus free time
100 kHz mode
4.7
—
µs
400 kHz mode
1.3
—
µs
—
400
pF
Bus capacitive loading
CB is specified to be from
10 - 400 pF
After this period, the first
clock pulse is generated
(Note 2)
(Note 1)
Time the bus must be free
before a new transmission
can start
* These parameters are characterized but not tested.
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A Fast mode (400 kHz) I2C bus device can be used in a Standard mode (100 kHz) I2C bus system, but the
requirement TSU:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it
must output the next data bit to the SDA line TR max. + TSU:DAT = 1000 + 250 = 1250 ns (according to the
Standard mode I2C bus specification), before the SCL line is released.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 139
PIC16F818/819
TABLE 15-9:
A/D CONVERTER CHARACTERISTICS: PIC16F818/819 (INDUSTRIAL, EXTENDED)
PIC16LF818/819 (INDUSTRIAL)
Param
Sym
No.
Characteristic
Min
Typ†
Max
Units
Conditions
A01
NR
Resolution
—
—
10 bits
bit
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A03
EIL
Integral linearity error
—
—
<±1
LSb
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A04
EDL
Differential linearity error
—
—
<±1
LSb
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A06
EOFF
Offset error
—
—
<±2
LSb
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A07
EGN
Gain error
—
—
<±1
LSb
VREF = VDD = 5.12V,
VSS ≤ VAIN ≤ VREF
A10
—
Monotonicity(3)
—
guaranteed
—
—
VSS ≤ VAIN ≤ VREF
A20
VREF
Reference Voltage
2.5
2.2
—
—
VDD + 0.3
VDD + 0.3
V
V
-40°C to +85°C
0°C to +85°C
A21
VREF+ Reference voltage high
AVDD – 2.5V
AVDD + 0.3V
V
AVSS – 0.3V
VREF+ – 2.0V
V
A22
VREF- Reference voltage low
A25
VAIN
Analog input voltage
A30
ZAIN
A50
IREF
VSS – 0.3V
—
VREF + 0.3V
V
Recommended impedance of
analog voltage source
—
—
2.5
kΩ
See Note 4.
VREF input current (Note 2)
—
—
5
µA
—
—
500
µA
During VAIN acquisition.
Based on differential of
VHOLD to VAIN to charge
CHOLD, see Section 11.1.
During A/D Conversion
cycle.
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
Note 1: When A/D is off, it will not consume any current other than minor leakage current.
The power-down current spec includes any such leakage from the A/D module.
2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input.
3: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes.
4: The maximum allowed impedance for analog voltage source is 10 kΩ. This requires higher acquisition times.
DS39598C-page 140
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
FIGURE 15-16:
A/D CONVERSION TIMING
BSF ADCON0, GO
1 TCY
(TOSC/2)(1)
131
Q4
130
A/D CLK
132
9
A/D DATA
8
...
7
...
2
1
NEW_DATA
OLD_DATA
ADRES
0
ADIF
GO
DONE
SAMPLING STOPPED
SAMPLE
Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the
SLEEP instruction to be executed.
TABLE 15-10: A/D CONVERSION REQUIREMENTS
Param
No.
130
Sym
TAD
Characteristic
A/D clock period
Min
Typ†
Max
Units
PIC16F818/819
1.6
—
—
µs
TOSC based, VREF ≥ 3.0V
PIC16LF818/819
3.0
—
—
µs
TOSC based, VREF ≥ 2.0V
PIC16F818/819
2.0
4.0
6.0
µs
A/D RC mode
PIC16LF818/819
3.0
6.0
9.0
µs
A/D RC mode
—
12
TAD
(Note 2)
10*
40
—
—
—
µs
µs
—
TOSC/2§
—
—
131
TCNV
Conversion time (not including S/H time)
(Note 1)
132
TACQ
Acquisition time
134
TGO
Q4 to A/D clock start
Conditions
The minimum time is the
amplifier settling time. This may be
used if the "new" input voltage has
not changed by more than 1 LSb (i.e.,
20.0 mV @ 5.12V) from the last
sampled voltage (as stated on
CHOLD).
If the A/D clock source is selected as
RC, a time of TCY is added before the
A/D clock starts. This allows the
SLEEP instruction to be executed.
* These parameters are characterized but not tested.
† Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are
not tested.
§ This specification ensured by design.
Note 1: ADRES register may be read on the following TCY cycle.
2: See Section 11.1 for minimum conditions.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 141
PIC16F818/819
NOTES:
DS39598C-page 142
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
16.0
DC AND AC
CHARACTERISTICS GRAPHS
AND TABLES
No Graphs and Tables are available at this time.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 143
PIC16F818/819
NOTES:
DS39598C-page 144
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
17.0
PACKAGING INFORMATION
17.1
Package Marking Information
18-Lead PDIP
Example
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
PIC16F818-I/P
0210017
18-Lead SOIC
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
PIC16F818-04
/SO
0210017
20-Lead SSOP
Example
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
PIC16F81820/SS
0210017
Example
28-Lead QFN
PIC16F81
8-I/ML
0210017
XXXXXXXX
XXXXXXXX
YYWWNNN
Legend:
Note:
*
XX...X
Y
YY
WW
NNN
Customer specific information*
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
Standard PICmicro device marking consists of Microchip part number, year code, week code, and
traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check
with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP
price.
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 145
PIC16F818/819
18-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
α
1
E
A2
A
L
c
A1
B1
β
p
B
eB
Units
Dimension Limits
n
p
MIN
INCHES*
NOM
18
.100
.155
.130
MAX
MILLIMETERS
NOM
18
2.54
3.56
3.94
2.92
3.30
0.38
7.62
7.94
6.10
6.35
22.61
22.80
3.18
3.30
0.20
0.29
1.14
1.46
0.36
0.46
7.87
9.40
5
10
5
10
MIN
Number of Pins
Pitch
Top to Seating Plane
A
.140
.170
Molded Package Thickness
A2
.115
.145
Base to Seating Plane
A1
.015
Shoulder to Shoulder Width
E
.300
.313
.325
Molded Package Width
E1
.240
.250
.260
Overall Length
D
.890
.898
.905
Tip to Seating Plane
L
.125
.130
.135
c
Lead Thickness
.008
.012
.015
Upper Lead Width
B1
.045
.058
.070
Lower Lead Width
B
.014
.018
.022
Overall Row Spacing
§
eB
.310
.370
.430
α
Mold Draft Angle Top
5
10
15
β
Mold Draft Angle Bottom
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-007
DS39598C-page 146
Preliminary
MAX
4.32
3.68
8.26
6.60
22.99
3.43
0.38
1.78
0.56
10.92
15
15
 2002 Microchip Technology Inc.
PIC16F818/819
18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC)
E
p
E1
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Chamfer Distance
Foot Length
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
A
A2
A1
E
E1
D
h
L
φ
c
B
α
β
MIN
.093
.088
.004
.394
.291
.446
.010
.016
0
.009
.014
0
0
A1
INCHES*
NOM
18
.050
.099
.091
.008
.407
.295
.454
.020
.033
4
.011
.017
12
12
MAX
.104
.094
.012
.420
.299
.462
.029
.050
8
.012
.020
15
15
MILLIMETERS
NOM
18
1.27
2.36
2.50
2.24
2.31
0.10
0.20
10.01
10.34
7.39
7.49
11.33
11.53
0.25
0.50
0.41
0.84
0
4
0.23
0.27
0.36
0.42
0
12
0
12
MIN
MAX
2.64
2.39
0.30
10.67
7.59
11.73
0.74
1.27
8
0.30
0.51
15
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-013
Drawing No. C04-051
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 147
PIC16F818/819
20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP)
E
E1
p
D
B
2
1
n
α
c
A2
A
φ
L
A1
β
Units
Dimension Limits
n
p
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff §
Overall Width
Molded Package Width
Overall Length
Foot Length
Lead Thickness
Foot Angle
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
A
A2
A1
E
E1
D
L
c
φ
B
α
β
MIN
.068
.064
.002
.299
.201
.278
.022
.004
0
.010
0
0
INCHES*
NOM
20
.026
.073
.068
.006
.309
.207
.284
.030
.007
4
.013
5
5
MAX
.078
.072
.010
.322
.212
.289
.037
.010
8
.015
10
10
MILLIMETERS
NOM
20
0.65
1.73
1.85
1.63
1.73
0.05
0.15
7.59
7.85
5.11
5.25
7.06
7.20
0.56
0.75
0.10
0.18
0.00
101.60
0.25
0.32
0
5
0
5
MIN
MAX
1.98
1.83
0.25
8.18
5.38
7.34
0.94
0.25
203.20
0.38
10
10
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MO-150
Drawing No. C04-072
DS39598C-page 148
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
28-Lead Plastic Quad Flat No Lead Package (ML) 6x6 mm Body (QFN)
EXPOSED
METAL
PADS
E
E1
Q
D1
D
D2
p
2
1
B
n
R
E2
CH x 45
TOP VIEW
L
BOTTOM VIEW
α
A2
A
A1
A3
Units
Dimension Limits
Number of Pins
INCHES
MIN
MILLIMETERS*
NOM
n
MIN
MAX
MAX
NOM
28
28
Pitch
p
Overall Height
A
.033
.039
0.85
1.00
Molded Package Thickness
A2
.026
.031
0.65
0.80
Standoff
A1
.0004
.002
0.01
0.05
Base Thickness
A3
.008 REF.
0.20 REF.
6.00 BSC
.026 BSC
.000
E
.236 BSC
Molded Package Width
E1
.226 BSC
Exposed Pad Width
E2
Overall Width
Overall Length
.140
.146
0.65 BSC
0.00
5.75 BSC
.152
3.55
.236 BSC
D
3.70
3.85
6.00 BSC
.226 BSC
5.75 BSC
Molded Package Length
D1
Exposed Pad Length
D2
.140
.146
.152
3.55
3.70
Lead Width
B
.009
.011
.014
0.23
0.28
0.35
Lead Length
L
.020
.024
.030
0.50
0.60
0.75
Tie Bar Width
R
.005
.007
.010
0.13
0.17
0.23
Tie Bar Length
Q
.012
.016
.026
0.30
0.40
0.65
CH
α
.009
.017
.024
0.24
0.42
0.60
Chamfer
Mold Draft Angle Top
12
3.85
12
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.
JEDEC equivalent: M0-220
Drawing No. C04-114
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 149
PIC16F818/819
28-Lead Plastic Quad Flat No Lead Package (ML) 6x6 mm Body (QFN)
Land Pattern and Solder Mask
M
B
L
M
p
PACKAGE
EDGE
SOLDER
MASK
Pitch
Pad Width
Pad Length
Pad to Solder Mask
Units
Dimension Limits
p
B
L
M
MIN
.009
.020
.005
INCHES
NOM
.026 BSC
.011
.024
MAX
.014
.030
.006
MILLIMETERS*
NOM
0.65 BSC
0.23
0.28
0.50
0.60
0.13
MIN
MAX
0.35
0.75
0.15
*Controlling Parameter
Drawing No. C04-2114
DS39598C-page 150
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
APPENDIX A:
REVISION HISTORY
Version
Date
A
May 2002
B
August 2002
C
Revision Description
This is a new data sheet.
Added INTRC section. PWRT and BOR are independent of each other. Revised
program memory text and code routine. Added QFN package. Modified PORTB
diagrams.
November 2002 Added various new feature descriptions. Added Internal RC Oscillator
specifications. Added Low Power Timer1 specifications and RTC application
example.
APPENDIX B:
DEVICE DIFFERENCES
The differences between the devices in this data sheet are listed in Table B-1.
TABLE B-1:
DIFFERENCES BETWEEN THE PIC16F818 AND PIC16F819
Features
PIC16F818
PIC16F819
FLASH Program Memory (14-bit words)
1K
2K
Data Memory (bytes)
128
256
EEPROM Data Memory (bytes)
128
256
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 151
PIC16F818/819
NOTES:
DS39598C-page 152
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
INDEX
A
A/D
Acquisition Requirements .......................................... 84
ADIF Bit ...................................................................... 83
Analog-to-Digital Converter ........................................ 81
Associated Registers ................................................. 87
Calculating Acquisition Time ...................................... 84
Configuring Analog Port Pins ..................................... 85
Configuring the Interrupt ............................................ 83
Configuring the Module .............................................. 83
Conversion Clock ....................................................... 85
Conversions ............................................................... 86
Converter Characteristics ........................................ 140
Delays ........................................................................ 84
Effects of a RESET .................................................... 87
GO/DONE Bit ............................................................. 83
Internal Sampling Switch (Rss) Impedance ............... 84
Operation During SLEEP ........................................... 87
Result Registers ......................................................... 86
Source Impedance ..................................................... 84
Time Delays ............................................................... 84
Using the CCP Trigger ............................................... 87
Absolute Maximum Ratings ............................................. 117
ACK .................................................................................... 77
ADCON0 Register .............................................................. 81
ADCON1 Register .............................................................. 81
ADRESH Register ........................................................ 13, 81
ADRESH, ADRESL Register Pair ...................................... 83
ADRESL Register ........................................................ 14, 81
Application Notes
AN556 (Implementing a Table Read) ........................ 23
AN578 (Use of the SSP Module in the
I2C Multi-Master Environment) ........................... 71
AN607 (Power-up Trouble Shooting) ......................... 92
Assembler
MPASM Assembler .................................................. 111
B
BF Bit ................................................................................. 76
Block Diagrams
A/D ............................................................................. 83
Analog Input Model .................................................... 84
Capture Mode Operation ........................................... 66
Compare Mode Operation ......................................... 67
In-Circuit Serial Programming Connections ............. 101
Interrupt Logic ............................................................ 96
On-Chip Reset Circuit ................................................ 91
PIC16F818/819 ............................................................ 6
PWM .......................................................................... 68
RA0/AN0:RA1/AN1 Pins ............................................ 40
RA2/AN2/VREF- Pin .................................................... 40
RA3/AN3/VREF+ Pin ................................................... 40
RA4/AN4/T0CKI Pin ................................................... 40
RA5/MCLR/VPP .......................................................... 41
RA6/OSC2/CLKO Pin ................................................ 41
RA7/OSC1/CLKI Pin .................................................. 42
RB0 Pin ...................................................................... 45
RB1 Pin ...................................................................... 46
RB2 Pin ...................................................................... 47
RB3 Pin ...................................................................... 48
RB4 Pin ...................................................................... 49
RB5 Pin ...................................................................... 50
RB6 Pin ...................................................................... 51
 2002 Microchip Technology Inc.
RB7 Pin ..................................................................... 52
Recommended MCLR Circuit .................................... 92
SSP in I2C Mode ........................................................ 76
SSP in SPI Mode ....................................................... 74
System Clock ............................................................. 38
Timer0/WDT Prescaler .............................................. 53
Timer1 ....................................................................... 58
Timer2 ....................................................................... 63
Watchdog Timer (WDT) ............................................. 98
BOR. See Brown-out Reset
Brown-out Reset (BOR) .............................. 89, 91, 92, 93, 94
C
Capture/Compare/PWM (CCP) ......................................... 65
Capture Mode ............................................................ 66
CCP Prescaler ................................................... 66
Software Interrupt .............................................. 66
Timer1 Mode Selection ...................................... 66
Capture, Compare and Timer1
Associated Registers ......................................... 67
CCP Timer Resources ............................................... 65
CCP1IF ...................................................................... 66
CCPR1 ...................................................................... 66
CCPR1H:CCPR1L ..................................................... 66
Compare Mode .......................................................... 67
CCP Pin Configuration ...................................... 67
Software Interrupt Mode .................................... 67
Special Event Trigger ........................................ 67
Special Trigger Output of CCP1 ........................ 67
Timer1 Mode Selection ...................................... 67
PWM and Timer2
Associated Registers ......................................... 69
PWM Mode ................................................................ 68
PWM, Example Frequencies/Resolutions ................. 69
CCP1M0 Bit ....................................................................... 65
CCP1M1 Bit ....................................................................... 65
CCP1M2 Bit ....................................................................... 65
CCP1M3 Bit ....................................................................... 65
CCP1X Bit .......................................................................... 65
CCP1Y Bit .......................................................................... 65
CCPR1H Register .............................................................. 65
CCPR1L Register .............................................................. 65
Code Examples
Changing Between Capture Prescalers ..................... 66
Changing Prescaler Assignment from
Timer0 to WDT .................................................. 55
Changing Prescaler Assignment from
WDT to Timer0 .................................................. 55
Clearing RAM Using Indirect Addressing .................. 23
Erasing a FLASH Program Memory Row .................. 29
Implementing a Real-Time Clock Using
a Timer1 Interrupt Service ................................. 62
Initializing PORTA ...................................................... 39
Reading a 16-bit Free-Running Timer ....................... 59
Reading Data EEPROM ............................................ 27
Reading FLASH Program Memory ............................ 28
Saving STATUS and W Registers in RAM ................ 97
Writing a 16-bit Free-Running Timer ......................... 59
Writing to Data EEPROM .......................................... 27
Writing to FLASH Program Memory .......................... 31
Code Protection ..........................................................89, 100
Computed GOTO ............................................................... 23
Configuration Bits .............................................................. 89
Crystal Oscillator and Ceramic Resonators ....................... 33
Preliminary
DS39598C-page 153
PIC16F818/819
I2C
D
Data EEPROM Memory ..................................................... 25
Associated Registers ................................................. 32
EEADR Register ........................................................ 25
EEADRH Register ...................................................... 25
EECON1 Register ...................................................... 25
EECON2 Register ...................................................... 25
EEDATA Register ...................................................... 25
EEDATH Register ...................................................... 25
Operation During Code Protect .................................. 32
Protection Against Spurious Writes ............................ 32
Reading ...................................................................... 27
Write Complete Flag (EEIF Bit) .................................. 25
Writing ........................................................................ 27
Data Memory
Special Function Registers ........................................ 13
DC and AC Characteristics
Graphs and Tables ................................................... 143
DC Characteristics
Internal RC Accuracy ............................................... 126
PIC16F818/819, PIC16LF818/819 ........................... 127
Power-down and Supply Current ............................. 120
Supply Voltage ......................................................... 119
Development Support ...................................................... 111
Device Differences ........................................................... 151
Device Overview .................................................................. 5
Direct Addressing ............................................................... 24
E
EEADR Register ................................................................ 25
EEADRH Register .............................................................. 25
EECON1 Register .............................................................. 25
EECON2 Register .............................................................. 25
EEDATA Register .............................................................. 25
EEDATH Register .............................................................. 25
Electrical Characteristics .................................................. 117
Endurance ............................................................................ 1
Errata ................................................................................... 3
External Clock Input ........................................................... 34
External Interrupt Input (RB0/INT). See Interrupt Sources
F
FLASH Program Memory ................................................... 25
Associated Registers ................................................. 32
EEADR Register ........................................................ 25
EEADRH Register ...................................................... 25
EECON1 Register ...................................................... 25
EECON2 Register ...................................................... 25
EEDATA Register ...................................................... 25
EEDATH Register ...................................................... 25
Erasing ....................................................................... 28
Reading ...................................................................... 28
Writing ........................................................................ 30
FSR Register .....................................................13, 14, 15, 23
I
I/O Ports ............................................................................. 39
PORTA ....................................................................... 39
PORTB ....................................................................... 43
TRISB Register .......................................................... 43
DS39598C-page 154
Addressing ................................................................. 77
Associated Registers ................................................. 79
Master Mode Operation ............................................. 79
Mode .......................................................................... 76
Mode Selection .......................................................... 76
Multi-Master Mode Operation .................................... 79
Reception ................................................................... 77
SCL and SDA Pins .................................................... 76
Slave Mode ................................................................ 76
Transmission ............................................................. 77
ICEPIC In-Circuit Emulator .............................................. 112
ID Locations ..................................................................... 100
In-Circuit Debugger .......................................................... 100
In-Circuit Serial Programming (ICSP) .............................. 101
INDF Register .........................................................14, 15, 23
Indirect Addressing .......................................................23, 24
Instruction Format ............................................................ 103
Instruction Set .................................................................. 103
ADDLW .................................................................... 105
ADDWF .................................................................... 105
ANDLW .................................................................... 105
ANDWF .................................................................... 105
BCF .......................................................................... 105
BSF .......................................................................... 105
BTFSC ..................................................................... 106
BTFSS ..................................................................... 106
CALL ........................................................................ 106
CLRF ....................................................................... 106
CLRW ...................................................................... 106
CLRWDT ................................................................. 106
COMF ...................................................................... 107
DECF ....................................................................... 107
DECFSZ .................................................................. 107
Descriptions ............................................................. 105
GOTO ...................................................................... 107
INCF ........................................................................ 107
INCFSZ .................................................................... 107
IORLW ..................................................................... 108
IORWF ..................................................................... 108
MOVF ...................................................................... 108
MOVLW ................................................................... 108
MOVWF ................................................................... 108
NOP ......................................................................... 108
Read-Modify-Write Operations ................................ 103
RETFIE .................................................................... 109
RETLW .................................................................... 109
RETURN .................................................................. 109
RLF .......................................................................... 109
RRF ......................................................................... 109
SLEEP ..................................................................... 109
SUBLW .................................................................... 110
SUBWF .................................................................... 110
Summary Table ....................................................... 104
SWAPF .................................................................... 110
XORLW .................................................................... 110
XORWF ................................................................... 110
INT Interrupt (RB0/INT). See Interrupt Sources
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
INTCON Register ............................................................... 15
GIE Bit ........................................................................ 18
INTE Bit ...................................................................... 18
INTF Bit ...................................................................... 18
RBIF Bit ...................................................................... 18
TMR0IE Bit ................................................................. 18
Internal Oscillator Block ..................................................... 35
INTRC Modes ............................................................ 36
Interrupt Sources .......................................................... 89, 96
RB0/INT Pin, External ................................................ 97
TMR0 Overflow .......................................................... 97
Interrupts
RB7:RB4 Port Change ............................................... 43
Synchronous Serial Port Interrupt .............................. 20
Interrupts, Context Saving During ...................................... 97
Interrupts, Enable Bits
Global Interrupt Enable (GIE Bit) ............................... 96
Interrupt-on-Change (RB7:RB4) Enable
(RBIE Bit) ........................................................... 97
RB0/INT Enable (INTE Bit) ........................................ 18
TMR0 Overflow Enable (TMR0IE Bit) ........................ 18
Interrupts, Enable bits
Global Interrupt Enable (GIE Bit) ............................... 18
Interrupts, Flag Bits
Interrupt-on-Change (RB7:RB4) Flag
(RBIF Bit) ..................................................... 18, 97
RB0/INT Flag (INTF Bit) ............................................. 18
TMR0 Overflow Flag (TMR0IF Bit) ............................. 97
INTRC Modes
Adjustment ................................................................. 36
K
KEELOQ Evaluation and Programming Tools ................... 114
L
Loading of PC .................................................................... 23
Low Voltage ICSP Programming ..................................... 101
M
Master Clear (MCLR)
MCLR Reset, Normal Operation .....................91, 93, 94
MCLR Reset, SLEEP ......................................91, 93, 94
Operation and ESD Protection ................................... 92
Memory Organization ........................................................... 9
Data Memory ............................................................. 10
Program Memory ......................................................... 9
MPLAB C17 and MPLAB C18 C Compilers ..................... 111
MPLAB ICD In-Circuit Debugger ...................................... 113
MPLAB ICE High Performance Universal
In-Circuit Emulator with MPLAB IDE ........................ 112
MPLAB Integrated Development
Environment Software .............................................. 111
MPLINK Object Linker/MPLIB Object Librarian ............... 112
O
OPCODE Field Descriptions ............................................ 103
OPTION Register ............................................................... 15
INTEDG Bit ................................................................ 17
PS2:PS0 Bits ............................................................. 17
PSA Bit ....................................................................... 17
RBPU Bit .................................................................... 17
T0CS Bit ..................................................................... 17
T0SE Bit ..................................................................... 17
 2002 Microchip Technology Inc.
Oscillator Configuration ..................................................... 33
ECIO .......................................................................... 33
EXTCLK ..................................................................... 93
EXTRC ...................................................................... 93
HS .........................................................................33, 93
INTIO1 ....................................................................... 33
INTIO2 ....................................................................... 33
INTRC ........................................................................ 93
LP .........................................................................33, 93
RC ........................................................................33, 35
RCIO .......................................................................... 33
XT .........................................................................33, 93
Oscillator Control Register ................................................. 37
Modifying IRCF Bits ................................................... 37
Clock Transition Sequence ................................ 37
Oscillator Start-up Timer (OST) ....................................89, 92
Oscillator, WDT .................................................................. 98
P
Packaging Information ..................................................... 145
Marking .................................................................... 145
PCFG0 Bit .......................................................................... 82
PCFG1 Bit .......................................................................... 82
PCFG2 Bit .......................................................................... 82
PCFG3 Bit .......................................................................... 82
PCL Register .................................................... 13, 14, 15, 23
PCLATH Register ............................................. 13, 14, 15, 23
PCON Register .................................................................. 93
POR Bit ...................................................................... 22
PICDEM 1 Low Cost PICmicro
Demonstration Board ............................................... 113
PICDEM 17 Demonstration Board ................................... 114
PICDEM 2 Low Cost PIC16CXX
Demonstration Board ............................................... 113
PICDEM 3 Low Cost PIC16CXXX
Demonstration Board ............................................... 114
PICSTART Plus Entry Level
Development Programmer ....................................... 113
Pinout Descriptions
PIC16F818/819 ........................................................... 7
Pointer, FSR ...................................................................... 23
POP ................................................................................... 23
POR. See Power-on Reset
PORTA ................................................................................ 7
Associated Register Summary .................................. 39
PORTA Register ................................................................ 13
PORTB ................................................................................ 8
Associated Register Summary .................................. 44
Pull-up Enable (RBPU Bit) ......................................... 17
RB0/INT Edge Select (INTEDG Bit) .......................... 17
RB0/INT Pin, External ................................................ 97
RB7:RB4 Interrupt-on-Change .................................. 97
RB7:RB4 Interrupt-on-Change Enable
(RBIE Bit) ........................................................... 97
RB7:RB4 Interrupt-on-Change Flag
(RBIF Bit) ......................................................18, 97
PORTB Register ...........................................................13, 15
Postscaler, WDT
Assignment (PSA Bit) ................................................ 17
Rate Select (PS2:PS0 Bits) ....................................... 17
Power-down Mode. See SLEEP
Preliminary
DS39598C-page 155
PIC16F818/819
Power-on Reset (POR) ...............................89, 91, 92, 93, 94
POR Status (POR Bit) ................................................ 22
Power Control (PCON) Register ................................ 93
Power-down (PD Bit) .................................................. 91
Time-out (TO Bit) ................................................. 16, 91
Power-up Timer (PWRT) .............................................. 89, 92
PR2 Register ...................................................................... 63
Prescaler, Timer0
Assignment (PSA Bit) ................................................. 17
Rate Select (PS2:PS0 Bits) ........................................ 17
PRO MATE II Universal Device Programmer ................... 113
Program Counter
RESET Conditions ..................................................... 93
Program Memory
Interrupt Vector ............................................................ 9
Map and Stack
PIC16F818 ........................................................... 9
PIC16F819 ........................................................... 9
RESET Vector .............................................................. 9
Program Verification ......................................................... 100
PUSH ................................................................................. 23
R
R/W Bit ............................................................................... 77
RA0/AN0 Pin ........................................................................ 7
RA1/AN1 Pin ........................................................................ 7
RA2/AN2/VREF- Pin .............................................................. 7
RA3/AN3/VREF+ Pin ............................................................. 7
RA4/AN4/T0CKI Pin ............................................................. 7
RA5/MCLR/VPP Pin .............................................................. 7
RA6/OSC2/CLKO Pin .......................................................... 7
RA7/OSC1/CLKI Pin ............................................................ 7
RB0/INT Pin ......................................................................... 8
RB1/SDI/SDA Pin ................................................................. 8
RB2/SDO/CCP1 Pin ............................................................. 8
RB3/CCP1/PGM Pin ............................................................ 8
RB4/SCK/SCL Pin ................................................................ 8
RB5/SS Pin .......................................................................... 8
RB6/T1OSO/T1CKI/PGC Pin ............................................... 8
RB7/T1OSI/PGD Pin ............................................................ 8
RBIF Bit .............................................................................. 43
RCIO Oscillator .................................................................. 35
Receive Overflow Indicator Bit, SSPOV ............................. 73
Register File ....................................................................... 10
Register File Map
PIC16F818 ................................................................. 11
PIC16F819 ................................................................. 12
Registers
ADCON0 (A/D Control 0) ........................................... 81
ADCON1 (A/D Control 1) ........................................... 82
CCP1CON (Capture/Compare/PWM Control 1) ........ 65
Configuration Word .................................................... 90
EECON1 (Data EEPROM Access Control 1) ............. 26
Initialization Conditions (table) ................................... 94
INTCON (Interrupt Control) ........................................ 18
OPTION ..................................................................... 17
OPTION_REG Register ............................................. 54
OSCCON (Oscillator Control) .................................... 38
OSCTUNE (Oscillator Tuning) ................................... 36
PCON (Power Control) ............................................... 22
PIE1 (Peripheral Interrupt Enable 1) .......................... 19
PIE2 (Peripheral Interrupt Enable 2) .......................... 21
PIR1 (Peripheral Interrupt Flag 1) .............................. 20
DS39598C-page 156
PIR2 (Peripheral Interrupt Flag 2) .............................. 21
SSPCON (Synchronous Serial Port Control 1) .......... 73
SSPSTAT (Synchronous Serial Port Status) ............. 72
STATUS ..................................................................... 16
T1CON (Timer1 Control) ........................................... 57
T2CON (Timer2 Control) ........................................... 64
RESET ..........................................................................89, 91
Brown-out Reset (BOR). See Brown-out Reset (BOR)
MCLR Reset. See MCLR
Power-on Reset (POR). See Power-on Reset (POR)
RESET Conditions for All Registers .......................... 94
RESET Conditions for PCON Register ...................... 93
RESET Conditions for Program Counter ................... 93
RESET Conditions for STATUS Register .................. 93
WDT Reset. See Watchdog Timer (WDT)
Revision History ............................................................... 151
RP0 Bit ............................................................................... 10
RP1 Bit ............................................................................... 10
S
Sales and Support ........................................................... 161
SCL .................................................................................... 76
Slave Mode
SCL ............................................................................ 76
SDA ........................................................................... 76
SLEEP ....................................................................89, 91, 99
Software Simulator (MPLAB SIM) .................................... 112
Special Event Trigger ......................................................... 87
Special Features of the CPU ............................................. 89
Special Function Register Summary .................................. 13
Special Function Registers ................................................ 13
SPI
Associated Registers ................................................. 74
Serial Clock ................................................................ 71
Serial Data In ............................................................. 71
Serial Data Out .......................................................... 71
Slave Select ............................................................... 71
SSP
ACK ........................................................................... 76
I2C
I2C Operation ..................................................... 76
SSPADD Register .............................................................. 14
SSPIF ................................................................................ 20
SSPOV .............................................................................. 73
SSPOV Bit ......................................................................... 76
SSPSTAT Register ............................................................ 14
Stack .................................................................................. 23
Overflows ................................................................... 23
Underflow ................................................................... 23
STATUS Register .........................................................13, 15
DC Bit ........................................................................ 16
IRP Bit ........................................................................ 16
PD Bit ......................................................................... 91
TO Bit ....................................................................16, 91
Z Bit ........................................................................... 16
Synchronous Serial Port (SSP) .......................................... 71
Overview .................................................................... 71
SPI Mode ................................................................... 71
Synchronous Serial Port Interrupt ...................................... 20
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
T
T1CKPS0 Bit ...................................................................... 57
T1CKPS1 Bit ...................................................................... 57
T1OSCEN Bit ..................................................................... 57
T1SYNC Bit ........................................................................ 57
T2CKPS0 Bit ...................................................................... 64
T2CKPS1 Bit ...................................................................... 64
TAD ..................................................................................... 85
Time-out Sequence ............................................................ 92
Timer0 ................................................................................ 53
Associated Registers ................................................. 55
Clock Source Edge Select (T0SE Bit) ........................ 17
Clock Source Select (T0CS Bit) ................................. 17
External Clock ............................................................ 54
Interrupt ...................................................................... 53
Operation ................................................................... 53
Overflow Enable (TMR0IE Bit) ................................... 18
Overflow Flag (TMR0IF Bit) ....................................... 97
Overflow Interrupt ...................................................... 97
Prescaler .................................................................... 54
T0CKI ......................................................................... 54
Timer1 ................................................................................ 57
Associated Registers ................................................. 62
Capacitor Selection .................................................... 60
Counter Operation ..................................................... 58
Operation ................................................................... 57
Operation in Asynchronous Counter Mode ................ 59
Operation in Synchronized Counter Mode ................. 58
Operation in Timer Mode ........................................... 58
Oscillator .................................................................... 60
Oscillator Layout Considerations ............................... 60
Prescaler .................................................................... 61
Resetting Timer1 Register Pair .................................. 61
Resetting Timer1 Using a CCP
Trigger Output .................................................... 60
TMR1H ....................................................................... 59
TMR1L ....................................................................... 59
Use as a Real-Time Clock ......................................... 61
Timer2 ................................................................................ 63
Associated Registers ................................................. 64
Output ........................................................................ 63
Postscaler .................................................................. 63
Prescaler .................................................................... 63
Prescaler and Postscaler ........................................... 63
Timing Diagrams
A/D Conversion ........................................................ 141
Brown-out Reset ...................................................... 132
Capture/Compare/PWM (CCP1) .............................. 134
CLKO and I/O .......................................................... 131
External Clock .......................................................... 130
I2C Bus Data ............................................................ 138
I2C Bus START/STOP Bits ...................................... 137
I2C Reception (7-bit Address) .................................... 78
I2C Transmission (7-bit Address) ............................... 78
PWM Output .............................................................. 68
RESET, Watchdog Timer, Oscillator Start-up
Timer and Power-up Timer .............................. 132
 2002 Microchip Technology Inc.
Slow Rise Time (MCLR Tied to VDD
Through RC Network) ........................................ 96
SPI Master Mode ....................................................... 75
SPI Master Mode (CKE = 0, SMP = 0) .................... 135
SPI Master Mode (CKE = 1, SMP = 1) .................... 135
SPI Slave Mode (CKE = 0) .................................75, 136
SPI Slave Mode (CKE = 1) .................................75, 136
Time-out Sequence on Power-up (MCLR Tied
to VDD Through Pull-up Resistor) ...................... 95
Time-out Sequence on Power-up (MCLR Tied
to VDD Through RC Network): Case 1 ............... 95
Time-out Sequence on Power-up (MCLR Tied
to VDD Through RC Network): Case 2 ............... 95
Timer0 and Timer1 External Clock .......................... 133
Timer1 Incrementing Edge ........................................ 58
Wake-up from SLEEP via Interrupt .......................... 100
Timing Parameter Symbology ......................................... 129
TMR0 Register ................................................................... 15
TMR1CS Bit ....................................................................... 57
TMR1H Register ................................................................ 13
TMR1L Register ................................................................. 13
TMR1ON Bit ...................................................................... 57
TMR2 Register ................................................................... 13
TMR2ON Bit ...................................................................... 64
TOUTPS0 Bit ..................................................................... 64
TOUTPS1 Bit ..................................................................... 64
TOUTPS2 Bit ..................................................................... 64
TOUTPS3 Bit ..................................................................... 64
TRISA Register .............................................................14, 39
TRISB Register .............................................................14, 15
V
VDD Pin ................................................................................ 8
VSS Pin ................................................................................ 8
W
Wake-up from SLEEP ...................................................89, 99
Interrupts ..............................................................93, 94
MCLR Reset .............................................................. 94
WDT Reset ................................................................ 94
Wake-up Using Interrupts .................................................. 99
Watchdog Timer (WDT) ................................................89, 98
Associated Registers ................................................. 98
Enable (WDTEN Bit) .................................................. 98
INTRC Oscillator ........................................................ 98
Postscaler. See Postscaler, WDT
Programming Considerations .................................... 98
Time-out Period ......................................................... 98
WDT Reset, Normal Operation ....................... 91, 93, 94
WDT Reset, SLEEP ........................................ 91, 93, 94
WCOL ................................................................................ 73
Write Collision Detect bit, WCOL ....................................... 73
WWW, On-Line Support ...................................................... 3
Preliminary
DS39598C-page 157
PIC16F818/819
NOTES:
DS39598C-page 158
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web site.
The web site is used by Microchip as a means to make
files and information easily available to customers. To
view the site, the user must have access to the Internet
and a web browser, such as Netscape® or Microsoft®
Internet Explorer. Files are also available for FTP
download from our FTP site.
Connecting to the Microchip Internet Web Site
SYSTEMS INFORMATION AND
UPGRADE HOT LINE
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive the most current upgrade kits.The Hot Line
Numbers are:
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
The Microchip web site is available at the following
URL:
www.microchip.com
092002
The file transfer site is available by using an FTP service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errata
• Job Postings
• Microchip Consultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Conferences for products, Development Systems,
technical information and more
• Listing of seminars and events
 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 159
PIC16F818/819
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
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Application (optional):
Would you like a reply?
Device: PIC16F818/819
Y
N
Literature Number: DS39598C
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
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6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS39598C-page 160
Preliminary
 2002 Microchip Technology Inc.
PIC16F818/819
PIC16F818/819 PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
Temperature
Range
/XX
XXX
Package
Pattern
Examples:
a)
b)
Device
PIC16F818: Standard VDD range
PIC16F818T: (Tape and Reel)
PIC16LF818: Extended VDD range
Temperature Range
I
Package
P
SO
SS
ML
=
=
PIC16F818-I/P = Industrial temp., PDIP
package, Extended VDD limits.
PIC16F818-I/SO = Industrial temp., SOIC
package, normal VDD limits.
0°C to +70°C
-40°C to +85°C
=
=
=
=
PDIP
SOIC
SSOP
QFN
Note 1:
Pattern
QTP, SQTP, ROM Code (factory specified) or
Special Requirements. Blank for OTP and
Windowed devices.
2:
F = CMOS FLASH
LF = Low Power CMOS FLASH
T = in tape and reel - SOIC, SSOP
packages only.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1.
2.
3.
Your local Microchip sales office
The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
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 2002 Microchip Technology Inc.
Preliminary
DS39598C-page 161
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
Corporate Office
Australia
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200 Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: http://www.microchip.com
Microchip Technology Australia Pty Ltd
Suite 22, 41 Rawson Street
Epping 2121, NSW
Australia
Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
Rocky Mountain
China - Beijing
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7966 Fax: 480-792-4338
Atlanta
3780 Mansell Road, Suite 130
Alpharetta, GA 30022
Tel: 770-640-0034 Fax: 770-640-0307
Boston
2 Lan Drive, Suite 120
Westford, MA 01886
Tel: 978-692-3848 Fax: 978-692-3821
Chicago
333 Pierce Road, Suite 180
Itasca, IL 60143
Tel: 630-285-0071 Fax: 630-285-0075
Dallas
4570 Westgrove Drive, Suite 160
Addison, TX 75001
Tel: 972-818-7423 Fax: 972-818-2924
Detroit
Tri-Atria Office Building
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Kokomo
2767 S. Albright Road
Kokomo, Indiana 46902
Tel: 765-864-8360 Fax: 765-864-8387
Los Angeles
18201 Von Karman, Suite 1090
Irvine, CA 92612
Tel: 949-263-1888 Fax: 949-263-1338
San Jose
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
Tel: 408-436-7950 Fax: 408-436-7955
Toronto
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699 Fax: 905-673-6509
Microchip Technology Consulting (Shanghai)
Co., Ltd., Beijing Liaison Office
Unit 915
Bei Hai Wan Tai Bldg.
No. 6 Chaoyangmen Beidajie
Beijing, 100027, No. China
Tel: 86-10-85282100 Fax: 86-10-85282104
China - Chengdu
Microchip Technology Consulting (Shanghai)
Co., Ltd., Chengdu Liaison Office
Rm. 2401-2402, 24th Floor,
Ming Xing Financial Tower
No. 88 TIDU Street
Chengdu 610016, China
Tel: 86-28-86766200 Fax: 86-28-86766599
China - Fuzhou
Microchip Technology Consulting (Shanghai)
Co., Ltd., Fuzhou Liaison Office
Unit 28F, World Trade Plaza
No. 71 Wusi Road
Fuzhou 350001, China
Tel: 86-591-7503506 Fax: 86-591-7503521
China - Shanghai
Microchip Technology Consulting (Shanghai)
Co., Ltd.
Room 701, Bldg. B
Far East International Plaza
No. 317 Xian Xia Road
Shanghai, 200051
Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
China - Shenzhen
Microchip Technology Consulting (Shanghai)
Co., Ltd., Shenzhen Liaison Office
Rm. 15-16, 13/F, Shenzhen Kerry Centre,
Renminnan Lu
Shenzhen 518001, China
Tel: 86-755-82350361 Fax: 86-755-82366086
China - Hong Kong SAR
Microchip Technology Hongkong Ltd.
Unit 901-6, Tower 2, Metroplaza
223 Hing Fong Road
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200 Fax: 852-2401-3431
India
Microchip Technology Inc.
India Liaison Office
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Japan
Microchip Technology Japan K.K.
Benex S-1 6F
3-18-20, Shinyokohama
Kohoku-Ku, Yokohama-shi
Kanagawa, 222-0033, Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Korea
Microchip Technology Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Tel: 82-2-554-7200 Fax: 82-2-558-5934
Singapore
Microchip Technology Singapore Pte Ltd.
200 Middle Road
#07-02 Prime Centre
Singapore, 188980
Tel: 65-6334-8870 Fax: 65-6334-8850
Taiwan
Microchip Technology (Barbados) Inc.,
Taiwan Branch
11F-3, No. 207
Tung Hua North Road
Taipei, 105, Taiwan
Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
EUROPE
Austria
Microchip Technology Austria GmbH
Durisolstrasse 2
A-4600 Wels
Austria
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
Denmark
Microchip Technology Nordic ApS
Regus Business Centre
Lautrup hoj 1-3
Ballerup DK-2750 Denmark
Tel: 45 4420 9895 Fax: 45 4420 9910
France
Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Batiment A - ler Etage
91300 Massy, France
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Germany
Microchip Technology GmbH
Steinheilstrasse 10
D-85737 Ismaning, Germany
Tel: 49-89-627-144 0 Fax: 49-89-627-144-44
Italy
Microchip Technology SRL
Centro Direzionale Colleoni
Palazzo Taurus 1 V. Le Colleoni 1
20041 Agrate Brianza
Milan, Italy
Tel: 39-039-65791-1 Fax: 39-039-6899883
United Kingdom
Microchip Ltd.
505 Eskdale Road
Winnersh Triangle
Wokingham
Berkshire, England RG41 5TU
Tel: 44 118 921 5869 Fax: 44-118 921-5820
11/15/02
DS39598C-page 162
Preliminary
 2002 Microchip Technology Inc.
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