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bq24630
SLUS894B – JANUARY 2010 – REVISED JULY 2015
bq24630 Standalone Synchronous Switched-Mode Lithium Phosphate Battery Charger
With System Power Selector and Low Iq
1 Features
2 Applications
•
•
•
•
•
•
1
•
•
•
•
•
•
•
•
•
•
•
300-kHz NMOS-NMOS Synchronous Buck
Converter
Stand-Alone Charger Specifically for Lithium
Phosphate
5-V–28-V VCC Input Operating Range, Supports
1–7 Battery Cells
High-Accuracy Voltage and Current Regulation
– ±0.5% Charge Voltage Accuracy
– ±3% Charge Current Accuracy
– ±3% Adapter Current Accuracy
Integration
– Automatic System Power Selection From
Adapter or Battery
– Internal Loop Compensation
– Internal Soft Start
– Dynamic Power Management (DPM)
Safety Protection
– Input Overvoltage Protection
– Battery Thermistor Sense Suspend Charge at
Hot/Cold and Automatically ICHARGE/8 at
Hot/Cold or Warm/Cool
– Battery Detection
– Reverse Protection Input FET
– Programmable Safety Timer
– Charge Overcurrent Protection
– Battery Short Protection
– Battery Overvoltage Protection
– Thermal Shutdown
Status Outputs
– Adapter Present
– Charger Operation Status
Charge Enable Pin
6-V Gate Drive for Synchronous Buck Converter
30-ns Driver Dead Time and 99.95% Max.
Effective Duty Cycle
24-Pin 4-mm × 4-mm QFN Package
Energy Star Low Quiescent Current Iq
– < 15-μA Off-State Battery Discharge Current
– < 1.5-mA Off-State Input Quiescent Current
Power Tool and Portable Equipment
Personal Digital Assistants
Handheld Terminals
Industrial and Medical Equipment
Netbook, Mobile Internet Device, and Ultra-Mobile
PC
3 Description
The bq24630 is a highly integrated lithium phosphate
switched-mode battery charge controller. The device
offers a constant-frequency synchronous switching
PWM controller with high-accuracy charge current
and voltage regulation, charge preconditioning,
termination, adapter current regulation, and charge
status monitoring.
The bq24630 charges the battery in three phases:
preconditioning, constant current, and constant
voltage. Charge is terminated when the current
reaches a minimum user-selectable level. A
programmable charge timer provides a safety
backup. The bq24630 automatically restarts the
charge cycle if the battery voltage falls below an
internal threshold and enters a low quiescent current
sleep mode when the input voltage falls below the
battery voltage.
Device Information(1)
PART NUMBER
bq24630
PACKAGE
VQFN (24)
BODY SIZE (NOM)
4.00 mm × 4.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
ADAPTER
SYSTEM
ACP
ACDRV
ACN
BATDRV
CE
HIDRV
VREF
PH
ISET1
ISET2
ACSET
LODRV
Battery
pack
bq24630
VREF
ADAPTER
STAT1
STAT2
PG
TS
SRP
SRN
VFB
TTC
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
bq24630
SLUS894B – JANUARY 2010 – REVISED JULY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
8
1
1
1
2
3
3
4
Absolute Maximum Ratings ...................................... 4
ESD Ratings ............................................................ 5
Recommended Operating Conditions....................... 5
Thermal Information .................................................. 5
Electrical Characteristics........................................... 5
Typical Characteristics ............................................ 10
Detailed Description ............................................ 13
8.1 Overview ................................................................. 13
8.2 Functional Block Diagram ....................................... 14
8.3 Feature Description................................................. 15
8.4 Device Functional Modes........................................ 24
9
Application and Implementation ........................ 25
9.1 Application Information............................................ 25
9.2 Typical Application ................................................. 25
10 Power Supply Recommendations ..................... 30
11 Layout................................................................... 30
11.1 Layout Guidelines ................................................. 30
11.2 Layout Example .................................................... 31
12 Device and Documentation Support ................. 32
12.1
12.2
12.3
12.4
12.5
12.6
Device Support......................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
32
32
32
32
32
32
13 Mechanical, Packaging, and Orderable
Information ........................................................... 32
4 Revision History
Changes from Revision A (October 2011) to Revision B
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Added text, equations and illustrations from Inductor Selection to PCB Layout .................................................................. 26
Changes from Original (January 2010) to Revision A
Page
•
Changed descriptions for PH and BTST pins......................................................................................................................... 4
•
Changed Equation 1 From: R1/R2 To: R2/R1...................................................................................................................... 15
•
Changed Equation 1 ............................................................................................................................................................ 15
•
Changed Equation 15 .......................................................................................................................................................... 26
2
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Product Folder Links: bq24630
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SLUS894B – JANUARY 2010 – REVISED JULY 2015
5 Device Comparison Table
Cell chemistry
bq24620
bq24630
Lithium phosphate
Lithium phosphate
1 to 7
1 to 7
1.8 to 26
1.8 to 26
5 to 28
5 to 28
32
32
Number of cells in series (minimum to
maximum, 4.2 V/cell)
Charge voltage (minimum to maximum) (V)
Input voltage range (minimum to maximum) (V)
Input overvoltage (V)
Maximum battery charging current (A)
10
10
Switching frequency (kHz)
300
300
JEITA charging temperature profile
No
No
DPM
No
IIN DPM
6 Pin Configuration and Functions
PH
LODRV
23
BTST
24
HIDRV
VCC
BATDRV
RGE Package
24-Pin VQFN
Top View
22
21
20
19
18 REGN
ACN 1
17 GND
ACP 2
OAT
(bq24630)
QFN-24
ACDRV 3
CE 4
16 ACSET
15 ISET 2
14 SRP
STAT1 5
13 SRN
7
8
9
10
11
12
TTC
PG
STAT2
VREF
ISET1
VFB
TS 6
Pin Functions
PIN
I/O
DESCRIPTION
3
O
AC adapter to system MOSFET driver output. Connect through a 1-kΩ resistor to the gate of the ACFET P-channel power
MOSFET and the reverse conduction blocking P-channel power MOSFET. The internal gate drive is asymmetrical, allowing a
quick turnoff and slow turnon, in addition to the internal break-before-make logic with respect to BATDRV. If needed, an
optional capacitor from gate to source of the ACFET is used to slow down the ON and OFF times.
ACN
1
I
Adapter-current sense resistor, negative input. A 0.1-μF ceramic capacitor is placed from ACN to ACP to provide differentialmode filtering. An optional 0.1-μF ceramic capacitor is placed from the ACN pin to GND for common-mode filtering.
ACP
2
I
Adapter-current sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from ACN to ACP to provide differentialmode filtering. A 0.1-μF ceramic capacitor is placed from the ACP pin to GND for common-mode filtering.
ACSET
16
I
Adapter-current set input. The voltage of ACSET pin programs the input current regulation set-point during dynamic power
management (DPM).
BATDRV
23
O
Battery-to-system MOSFET-driver output. Gate drive for the battery-to-system load BAT PMOS power FET to isolate the
system from the battery to prevent current flow from the system to the battery, while allowing a low-impedance path from
battery to system. Connect this pin through a 1-kΩ resistor to the gate of the input BAT P-channel MOSFET. Connect the
source of the FET to the system load voltage node. Connect the drain of the FET to the battery pack positive terminal. The
internal gate drive is asymmetrical to allow a quick turnoff and slow turnon, in addition to the internal break-before-make logic
with respect to ACDRV. If needed, an optional capacitor from gate to source of the BATFET is used to slow down the ON and
OFF times.
BTST
22
–
PWM high-side driver positive supply. Connect the 0.1-μF bootstrap capacitor from PH to BTST, and a bootstrap Schottky
diode from REGN to BTST.
NAME
NO.
ACDRV
CE
4
I
Charge-enable active-HIGH logic input. HI enables charge. LO disables charge. It has an internal 1-MΩ pulldown resistor.
GND
17
–
Low-current sensitive analog/digital ground. On PCB layout, connect with the thermal pad underneath the IC.
HIDRV
21
O
PWM high-side driver output. Connect to the gate of the high-side power MOSFET with a short trace.
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Pin Functions (continued)
PIN
I/O
DESCRIPTION
NAME
NO.
ISET1
11
I
Fast-charge current-set input. The voltage of ISET1 pin programs the fast-charge current-regulation set point.
ISET2
15
I
Termination-current set input. The voltage of ISET2 pin programs termination current trigger point.
LODRV
19
O
PWM low-side driver output. Connect to the gate of the low-side power MOSFET with a short trace.
PG
8
O
Open-drain power-good status output. Active-LOW when IC has a valid VCC (not in UVLO or ACOV or SLEEP mode). ActiveHIGH when IC has an invalid VCC. PG can be used to drive an LED or communicate with a host processor.
PH
20
–
PWM high-side driver negative supply. Connect to the phase-switching node (junction of the low-side power MOSFET drain,
high-side power MOSFET source, and output inductor).
REGN
18
O
PWM low-side driver positive 6-V supply output. Connect a 1-μF ceramic capacitor from REGN to the GND pin, close to the
IC. Use for low-side driver and high-side driver bootstrap voltage by connecting a small-signal Schottky diode from REGN to
BTST.
SRN
13
I
Charge-current sense resistor, negative input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide differentialmode filtering. An optional 0.1-μF ceramic capacitor is placed from the SRN pin to GND for common-mode filtering.
SRP
14
I
Charge-current sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from SRN to SRP to provide differentialmode filtering. A 0.1-μF ceramic capacitor is placed from the SRP pin to GND for common-mode filtering.
STAT1
5
–
Open-drain charge-status pin to indicate various charger operations.
STAT2
9
–
Open-drain charge-status pin to indicate various charger operations.
Thermal
pad
—
–
Exposed pad beneath the IC. Always solder the thermal pad to the board, and have vias on the thermal pad plane starconnecting to GND and ground plane for high-current power converter. It also serves as a thermal pad to dissipate the heat.
TS
6
I
Temperature qualification voltage input for battery pack negative-temperature-coefficient thermistor. Program the hot and cold
temperature window with a resistor divider from VREF to TS to GND.
TTC
7
I
SafetyTimer and termination control. Connect a capacitor from this node to GND to set the timer. When this input is LOW, the
timer and termination are disabled. When this input is HIGH, the timer is disabled but termination is allowed.
VCC
24
–
IC power positive supply. Connect through a 10-Ω resistor to the common-source (diode-OR) point: source of high-side Pchannel MOSFET and source of reverse-blocking P-channel power MOSFET. Place a 1-μF ceramic capacitor from VCC to
the GND pin close to the IC.
VFB
12
O
Output-voltage analog feedback adjustment. Connect the output of a resistive voltage divider from the battery terminals to this
node to adjust the output battery-regulation voltage.
VREF
10
O
3.3-V regulated voltage output. Place a 1-μF ceramic capacitor from VREF to the GND pin close to the IC. This voltage could
be used for programming of voltage and current regulation and for programming the TS threshold.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1) (2) (3)
VCC, ACP, ACN, SRP, SRN, BATDRV, ACDRV, CE, STAT1, STAT2, PG
MIN
MAX
UNIT
–0.3
33
V
PH
–2
36
V
VFB
–0.3
16
V
REGN, LODRV, ACSET, TS, TTC
–0.3
7
V
BTST, HIDRV with respect to GND
–0.3
39
V
VREF, ISET1, ISET2
–0.3
3.6
V
ACP–ACN, SRP–SRN
–0.5
0.5
V
Junction temperature range, TJ
–40
155
°C
Storage temperature range, Tstg
–55
155
°C
Voltage range
Maximum difference voltage
(1)
(2)
(3)
4
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages are with respect to GND if not specified. Currents are positive into, negative out of the specified terminal. Consult Packaging
Section of the data book for thermal limitations and considerations of packages.
Must have a series resistor between battery pack to VFB if Battery Pack voltage is expected to be greater than 16 V. Usually, the
resistor divider top resistor takes care of this.
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SLUS894B – JANUARY 2010 – REVISED JULY 2015
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2000
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
MIN
Voltage range
VCC, ACP, ACN, SRP, SRN, BATDRV, ACDRV, CE, STAT1, STAT2,
PG
PH
NOM
MAX
28
V
–2
30
V
VFB
–0.3
14
V
REGN, LODRV, ACSET, TS, TTC
–0.3
6.5
V
BTST, HIDRV with respect to GND
–0.3
34
V
ISET1, ISET2
–0.3
3.3
V
3.3
V
–0.2
0.2
V
0
125
°C
VREF
Maximum difference
voltage
UNIT
–0.3
ACP–ACN, SRP–SRN
TJ Junction temperature range
7.4 Thermal Information
bq24630
THERMAL METRIC (1)
RGE (VQFN)
UNIT
24 PINS
RθJA
Junction-to-ambient thermal resistance
RθJCt(op)
Junction-to-case (top) thermal resistance
43
°C/W
54.3
RθJB
°C/W
Junction-to-board thermal resistance
20
°C/W
ψJT
Junction-to-top characterization parameter
0.6
°C/W
ψJB
Junction-to-board characterization parameter
19
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
7.5 Electrical Characteristics
5 V ≤ VVCC ≤ 28 V, 0°C < TJ < 125°C, typical values are at TA = 25°C, with respect to GND unless otherwise noted
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OPERATING CONDITIONS
VVCC_OP
VCC input voltage operating range
5
28
V
QUIESCENT CURRENTS
IBAT
IAC
VFB
Total battery discharge current (sum of
currents into VCC, BTST, PH, ACP, ACN,
SRP, SRN, VFB), VFB ≤ 2.1 V
Battery discharge current (sum of currents
into BTST, PH, SRP, SRN, VFB), VFB ≤
2.1 V
Adapter supply current (current into
VCC,ACP,ACN pin)
VVCC < VSRN, VVCC > VUVLO (SLEEP)
15
VVCC > VSRN, VVCC > VUVLO CE = LOW
VVCC > VSRN, VVCC > VVCCLOW CE = HIGH, charge done
5
VVCC > VSRN, VVCC > VUVLO CE = LOW
1
1.5
VVCC > VSRN, VVCC > VVCCLOW , CE = HIGH, charge done
2
5
VVCC > VSRN, VVCC > VVCCLOW , CE = HIGH, charging,
Qg_total = 20 nC, VVCC= 20 V
1.8
–0.5%
0.5%
TJ = –40°C to 125°C
–0.7%
0.7%
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mA
V
TJ = 0°C to 125°C
Copyright © 2010–2015, Texas Instruments Incorporated
µA
12
Feedback regulation voltage
Charge voltage regulation accuracy
μA
5
5
bq24630
SLUS894B – JANUARY 2010 – REVISED JULY 2015
www.ti.com
Electrical Characteristics (continued)
5 V ≤ VVCC ≤ 28 V, 0°C < TJ < 125°C, typical values are at TA = 25°C, with respect to GND unless otherwise noted
PARAMETER
Input leakage current into VFB pin
MAX
UNIT
VFB = 1.8 V
TEST CONDITIONS
MIN
TYP
100
nA
100
CURRENT REGULATION – FAST CHARGE
VISET1
ISET1 voltage range
VIREG_CHG
SRP–SRN current sense voltage range
VIREG_CHG = VSRP – VSRN
K(ISET1)
Charger current set factor amps of charge
current per volt on ISET1 pin)
RSENSE = 10 mΩ
Charge current regulation accuracy
IISET1
Leakage current in to ISET1 Pin
2
5
V
mV
A/V
VIREG_CHG = 40 mV
–3%
VIREG_CHG = 20 mV
–4%
3%
4%
VIREG_CHG = 5 mV
–25%
25%
VIREG_CHG = 1.5 mV (VSRN > 3.1 V)
–40%
40%
VISET1 = 2 V
100
nA
200
mA
CURRENT REGULATION – PRECHARGE
Precharge current
RSENSE = 10 mΩ, VFB < VLOWV
50
125
CHARGE TERMINATION
VISET2
ISET2 voltage range
Termination current range
RSENSE = 10 mΩ
Termination current set factor (amps of
termination current per volt on ISET2 pin)
KTERM
Termination current accuracy
2
V
2
A
1
A/V
VITERM = 20 mV
–4%
4%
VITERM = 5 mV
–25%
25%
VITERM = <1.5 mV
–45%
Deglitch time for termination (both edge)
45%
100
tQUAL
Termination qualification time
VBAT > VRECH and ICHARGE < ITERM
IQUAL
Termination qualification time
Discharge current once termination is detected
IISET2
Leakage current into ISET2 pin
VISET2 = 2 V
ms
250
ms
2
mA
100
nA
INPUT CURRENT REGULATION
VACSET
ACSET voltage range
VIREG_DPM
ACP-ACN current sense voltage range
VIREG_DPM = VACP – VACN
K(ACSET)
Input current set factor (amps of input
current per volt on ACSET pin)
RSENSE = 10 mΩ
IACSET
Leakage current into ACSET pin
2
0
100
5
VIREG_DPM = 40 mV
Input current regulation accuracy
0
–3%
V
mV
A/V
3%
VIREG_DPM = 20 mV
–4%
4%
VIREG_DPM = 5 mV
–25%
25%
VACSET = 2 V
100
nA
INPUT UNDERVOLTAGE LOCKOUT COMPARATOR (UVLO)
VUVLO
AC undervoltage rising threshold
VUVLO_HYS
AC undervoltage hysteresis, falling
Measure on VCC
3.65
3.85
4
350
V
mV
VCC LOWV COMPARATOR
Falling threshold, disable charge
Measure on VCC
4.1
Rising threshold, resume charge
V
4.35
4.5
V
100
150
mV
SLEEP COMPARATOR (REVERSE DISCHARGING PROTECTION)
VSLEEP
_FALL
VSLEEP_HYS
SLEEP falling threshold
VVCC – VSRN to enter SLEEP
40
SLEEP hysteresis
500
mV
μs
SLEEP rising delay
VCC falling below SRN, delay to turn off ACFET
1
SLEEP falling delay
VCC rising above SRN, delay to turn on ACFET
30
μs
SLEEP rising shutdown deglitch
VCC falling below SRN, delay to enter SLEEP mode
100
ms
SLEEP falling powerup deglitch
VCC rising above SRN, delay to exit out of SLEEP mode
30
ms
ACN / SRN COMPARATOR
VACN-SRN_FALL
ACN to SRN falling threshold
VACN-SRN_HYS
ACN to SRN rising hysteresis
ACN to SRN rising deglitch
6
VACN – VSRN to turn on BATFET
VACN – VSRN > VACN-SRN_RISE
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100
200
310
mV
100
mV
2
ms
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SLUS894B – JANUARY 2010 – REVISED JULY 2015
Electrical Characteristics (continued)
5 V ≤ VVCC ≤ 28 V, 0°C < TJ < 125°C, typical values are at TA = 25°C, with respect to GND unless otherwise noted
PARAMETER
ACN to SRN falling deglitch
TEST CONDITIONS
MIN
VACN – VSRN < VACN-SRN_FALL
TYP
MAX
UNIT
μs
50
BAT LOWV COMPARATOR
VLOWV
Precharge to fastcharge transition (LOWV
threshold)
VLOWV_HYS
LOWV hysteresis
Measured on VFB pin, rising
0.333
0.35
0.367
V
100
mV
LOWV rising deglitch
VFB falling below VLOWV
25
ms
LOWV falling deglitch
VFB rising above VLOWV
25
ms
RECHARGE COMPARATOR
VRECHG
Recharge threshold (with respect to
VREG)
Measured on VFB pin, rising
Recharge rising deglitch
VFB decreasing below VRECHG
10
ms
Recharge falling deglitch
VFB increasing above VRECHG
10
ms
110
125
140
mV
BAT OVERVOLTAGE COMPARATOR
VOV_RISE
Overvoltage rising threshold
As percentage of VFB
108%
VOV_FALL
Overvoltage falling threshold
As percentage of VFB
105%
INPUT OVERVOLTAGE COMPARATOR (ACOV)
VACOV
AC overvoltage, rising threshold on VCC
VACOV_HYS
AC overvoltage, falling hysteresis
31.04
32
32.96
V
1
V
1
ms
AC overvoltage, deglitch (both edges)
Delay to changing the STAT pins
AC overvoltage, rising deglitch
Delay to disable charge
1
ms
AC overvoltage, falling deglitch
Delay to resume charge
20
ms
Temperature increasing
145
°C
15
°C
THERMAL SHUTDOWN COMPARATOR
TSHUT
Thermal shutdown, rising temperature
TSHUT_HYS
Thermal shutdown hysteresis
Thermal shutdown rising deglitch
Temperature increasing
100
μs
Thermal shutdown falling deglitch
Temperature decreasing
10
ms
THERMISTOR COMPARATOR
VLTF
Cold temperature, rising threshold
VLTF_HYS
Cold temperature hysteresis
VCOOL
Cool temperature rising threshold
VCOOL_HYS
Cool temperature hysteresis
VWARM
Warm temperature rising threshold
VWARM_HYS
Warm temperature hysteresis
Charger suspended below this temperature
72.5%
73.5%
74.5%
0.2%
0.4%
0.6%
Charger enabled, cuts back to ICHARGE/8 below this
temperature
70.2%
70.7%
71.2%
0.2%
0.6%
1.0%
Charger cuts back to ICHARGE/8 above this temperature
47.5%
48%
48.5%
VHTF
Hot temperature rising threshold
Charger suspended above this temperature before
initiating charge
VTCO
Cutoff temperature rising threshold
Charger suspended above this temperature during
initiating charge
Deglitch time for temperature out-of-range
detection
VTS > VLTF, or VTS < VTCO, or VTS < VHTF
Deglitch time for temperature in-validrange detection
1.0%
1.2%
1.4%
36.2%
37%
37.8%
33.7%
34.4%
35.1%
400
ms
VTS < VLTF – VLTF_HYS or VTS >VTCO or VTS > VHTF
20
ms
Deglitch time for current reduction to
ICHARGE/8 due to warm or cool temperature
VTS > VCOOL, or VTS < VWARM
25
ms
Deglitch time to charge at ICHARGE from
ICHARGE/8 when resuming from warm or
cool temperatures
VTS < VCOOL – VCOOL_HYS, or VTS > VWARM – VWARM_HYS
25
ms
Charge current due to warm or cool
temperatures
VCOOL < VTS < VLTF, or VWARM < VTS < VHTF, or VWARM <
VTS < VTCO
ICHARGE
/8
CHARGE OVERCURRENT COMPARATOR (CYCLE-BY-CYCLE)
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Electrical Characteristics (continued)
5 V ≤ VVCC ≤ 28 V, 0°C < TJ < 125°C, typical values are at TA = 25°C, with respect to GND unless otherwise noted
PARAMETER
Charge overcurrent falling threshold
VOC
TEST CONDITIONS
MIN
Current rising, in non-synchronous mode, mesure on
V(SRP-SRN), VSRP < 2 V
TYP
MAX
45.5
Current rising, as percentage of V(IREG_CHG), in
synchronous mode, VSRP > 2.2 V
UNIT
mV
160%
Charge overcurrent threshold floor
Minimum OCP threshold in synchronous mode, measure
on V(SRP-SRN), VSRP > 2.2 V
50
mV
Charge overcurrent threshold ceiling
Maximum OCP threshold in synchronous mode, measure
on V(SRP-SRN), VSRP > 2.2 V
180
mV
CHARGE UNDERCURRENT COMPARATOR (CYCLE-BY-CYCLE)
VISYNSET
Charge under-current falling threshold
Switch from SYNCH to NON-SYNCH, VSRP > 2.2 V
1
5
9
mV
BATTERY SHORTED COMPARATOR (BATSHORT)
VBATSHT
BAT short falling threshold, forced nonsynchronous mode
VBATSHT_HYS
BAT short rising hysteresis
VBATSHT_DEG
Deglitch on both edge
VSRP falling
2
V
200
mV
1
μs
1.25
mV
1.25
mV
1
μs
LOW CHARGE CURRENT COMPARATOR
VLC
Average low charge current falling
threshold
VLC_HYS
Low charge current rising hysteresis
VLC_DEG
Deglitch on both edge
Measure on V(SRP-SRN), forced into non-synchronous
mode
VREF REGULATOR
VVREF_REG
VREF regulator voltage
VVCC > VUVLO, (0 – 35 mA load)
IVREF_LIM
VREF current limit
VVREF = 0 V, VVCC > VUVLO
3.267
VREGN_REG
REGN regulator voltage
VVCC > 10 V, CE = HIGH (0–40 mA load)
5.7
IREGN_LIM
REGN current limit
VREGN = 0 V, VVCC > VUVLO
40
TPRECHG
Precharge safety timer range (1)
Precharge time before fault occurs
TCHARGE
Fast-charge saftey timer range, with ±10%
accuracy (1)
Tchg = CTTC × KTTC
Fast charge timer accuracy (1)
0.047 μF ≤ CTTC ≤ 0.47 μF
3.3
3.333
35
V
mA
REGN REGULATOR
6
6.3
V
mA
TTC INPUT
KTTC
1440
1
–10%
Timer multiplier
TTC low threshold
1800
2160
s
10
h
10%
1.4
VTTC below this threshold disables the safety timer and
termination
0.4
TTC comparator high threshold
TTC comparator low threshold
TTC source/sink current
min/nF
45
V
1.5
V
1
V
50
55
μA
BATTERY SWITCH (BATFET) DRIVER
RDS_BAT_OFF
BATFET turnoff resistance
VACN > 5 V
150
Ω
RDS_BAT_ON
BATFET turnon resistance
VACN > 5 V
20
kΩ
VBATDRV_REG
BATFET drive voltage
VBATDRV_REG = VACN – VBATDRV when VACN > 5 V and
BATFET is on
7
V
4.2
AC SWITCH (ACFET) DRIVER
RDS_AC_OFF
ACFET turnoff resistance
VVCC > 5 V
30
Ώ
RDS_AC_ON
ACFET turnon resistance
VVCC > 5 V
20
kΏ
VACDRV_REG
ACFET drive voltage
VACDRV_REG = VVCC – VACDRV when VVCC > 5 V and
ACFET is on
7
V
4.2
AC / BAT MOSFET DRIVERS TIMING
Driver dead time
Dead time when switching between AC and BAT
μs
10
BATTERY DETECTION
tWAKE
Wake timer
Max. time charge is enabled
IWAKE
Wake current
RSENSE = 10 mΩ
(1)
8
500
50
125
ms
200
mA
Verified by design.
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Electrical Characteristics (continued)
5 V ≤ VVCC ≤ 28 V, 0°C < TJ < 125°C, typical values are at TA = 25°C, with respect to GND unless otherwise noted
PARAMETER
tDISCHARGE
Discharge timer
IDISCHARGE
TEST CONDITIONS
MIN
Max time discharge current is applied
TYP
MAX
UNIT
1
sec
Discharge current
8
mA
IFAULT
Fault current after a timeout fault
2
mA
VWAKE
Wake threshold (with respect to VREG)
Voltage on VFB to detect battery absent during wake
125
mV
VDISCH
Discharge threshold
Voltage on VFB to detect battery absent during discharge
0.35
V
PWM HIGH SIDE DRIVER (HIDRV)
RDS_HI_ON
High Side driver (HSD) turnon resistance
VBTST – VPH = 5.5 V
3.3
6
Ω
RDS_HI_OFF
High Side driver turnoff resistance
VBTST – VPH = 5.5 V
1
1.3
Ω
VBTST_REFRESH
Bootstrap refresh comparator threshold
voltage
VBTST – VPH when low side refresh pulse is requested
4
4.2
V
PWM LOW SIDE DRIVER (LODRV)
RDS_LO_ON
Low side driver (LSD) turnon resistance
RDS_LO_OFF
Low side driver turnoff resistance
4.1
7
Ω
1
1.4
Ω
PWM DRIVERS TIMING
Driver dead time
Dead time when switching between LSD and HSD, no
load at LSD and HSD
30
ns
PWM OSCILLATOR
VRAMP_HEIGHT
PWM ramp height
As percentage of VCC
7%
PWM switching frequency (1)
255
300
345
kHz
INTERNAL SOFT START (8 Steps to Regulation Current ICHG)
Soft-start steps
Soft-start step time
8
step
1.6
ms
1.5
s
CHARGER SECTION POWER-UP SEQUENCING
Charge-enable delay after power up
Delay from when adapter is detected to when the charger
is allowed to turn on
LOGIC IO PIN CHARACTERISTICS
VIN_LO
CE input low threshold voltage
VIN_HI
CE input high threshold voltage
0.8
V
VBIAS_CE
CE input bias current
V = 3.3 V (CE has internal 1-MΩ pulldown resistor)
6
μA
VOUT_LO
STAT1, STAT2, PG output low saturation
voltage
Sink current = 5 mA
0.5
V
IOUT_HI
Leakage current
V = 32 V
1.2
µA
2.1
V
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7.6 Typical Characteristics
Table 1. Table of Graphs
FIGURE
Figure 1
Charge Enable
Figure 2
Current Soft-Start (CE,=,1)
Figure 3
Charge Disable
Figure 4
Continuous-Conduction-Mode Switching Waveforms
Figure 5
Cycle-by-Cycle Synchronous to Nonsynchronous
Figure 6
100% Duty and Refresh Pulse
Figure 7
Transient System Load (DPM)
Figure 8
Battery Insertion
Figure 9
Battery-to-Ground Short Protection
Figure 10
Battery-to-Ground Short Transition
Figure 11
Efficiency vs Output Current
Figure 12
Input ACOV Transition
Figure 13
Input ACOV Resume Normal Transition
Figure 14
10 V/div
10 V/div
REF, REGN, and PG Power Up (CE = 1)
PH
2 A/div
IBAT
REGN
5 V/div
CE
5 V/div
2 V/div
VREF
5 V/div
/PG
2 V/div
VCC
LODRV
t − Time = 200 ms/div
Figure 2. Charge Enable
10 V/div
10 V/div
t − Time = 4 ms/div
Figure 1. REF, REGN, and PG Power Up (CE = 1)
PH
5 V/div
LDRV
2 A/div
2 V/div
5 V/div
IBAT
5 V/div
LODRV
2 A/div
PH
CE
IL
CE
t − Time = 4 ms/div
Figure 3. Current Soft-Start (CE = 1)
10
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t − Time = 4 μs/div
Figure 4. Charge Disable
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LODRV
PH
2 A/div
2 A/div
5 V/div
20 V/div
HIDRV
5 V/div
5 V/div
PH
IL
LODRV
IL
t − Time = 200 ns/div
t – Time = 200 ns/div
Figure 6. Cycle-by-Cycle Synchronous to Nonsynchronous
10 V/div
2 A/div
Figure 5. Continuous-Conduction Mode Switching
Waveform
2 A/div
IIN
ISYS
LODRV
2 A/div
0.5 A/div 5 V/div
PH
IL
IBAT
t − Time = 200 μs/div
Figure 8. Transient System Load (DPM)
5 V/div
10 V/div
20 V/div
t − Time = 400 ns/div
Figure 7. 100% Duty and Refresh Pulse
2 A/div
2 A/div
PH
10 V/div
10 V/div
IL
VBAT
PH
LDRV
IL
VBAT
t – Time = 4 ms/div
t – Time = 200 ms/div
Figure 9. Battery Insertion
Figure 10. Battery-to-GND Short Protection
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96
PH
94
Efficiency - %
92
LDRV
2 A/div
5 V/div
20 V/div
98
90
24 Vin, 6 cell
88
24 Vin, 5 cell
86
12 Vin, 2 cell
10 V/div
IL
84
12 Vin, 1 cell
82
VBAT
80
0
1
t – Time = 8 μs/div
6
7
8
20 V/div
20 V/div
20 V/div
VCC
/ACDRV
/ACDRV
20 V/div
20 V/div
20 V/div
VCC
/BATDRV
2 V/div
/BATDRV
2 V/div
5
4
3
IBAT - Output Current - A
Figure 12. Efficiency vs Output Current
Figure 11. Battery-to-GND Short Transition
/PG
/PG
t – Time = 10 ms/div
t – Time = 20 ms/div
Figure 13. Input ACOV Transition
12
2
Figure 14. Input ACOV Resume Normal Transition
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8 Detailed Description
8.1 Overview
The bq24630 device is a stand-alone, integrated lithium phosphate battery charger. The device employs a
switched-mode synchronous buck PWM controller with constant switching frequency. The device controls
external switches to prevent battery discharge back to the input, connect the adapter to the system, and connect
the battery to the system using 6-V gate drives for better system efficiency. The bq24630 features Dynamic
Power Management (DPM) which reduces battery charge current when the input power limit is reached to avoid
overloading the AC adapter when supplying current to the system and the battery charger simultaneously. A
highly accurate current-sense amplifier enables precise measurement of input current from the AC adapter to
monitor the overall system power. The input current limit can be configured through the ACSET pin of the device.
The bq24630 has a battery detect scheme that allows it to automatically detect the presence and absence of a
battery. When the battery is detected, charging begins in one of three phases (depending upon battery voltage):
precharge, constant current (fast-charge current regulation), and constant voltage (fast-charge voltage
regulation). The device will terminate charging when the termination current threshold has been reached and will
begin a recharge cycle when the battery voltage has dropped below the recharge threshold (VRECHG). Precharge,
constant current, and termination current can be configured through the ISET1 and ISET2 pins, allowing for
flexibility in battery charging profile. During charging, the integrated fault monitors of the device, such as battery
overvoltage protection, battery short detection (VBATSHT), thermal shutdown (internal TSHUT and TS pin), safety
timer expiration (TTC pin), and input voltage protection (VACOV), ensure battery safety.
The bq24630 has three status pins (STAT1, STAT2, and PG) to indicate the charging status and input voltage
(AC adapter) status. These pins can be used to drive LEDs or communicate with a host processor.
Regulation Voltage
VRECH
Regulation Current
Fastcharge Current
Regulation Phase
Precharge
Current
Regulation
Phase
Fastcharge Voltage
Regulation Phase
Termination
Charge
Current
Charge
Voltage
VLOWV
IPRECH & ITERM
Precharge
Time
Fastcharge Safety Time
Figure 15. Typical Charging Profile
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8.2 Functional Block Diagram
VREF
VOLTAGE
REFERENCE
VCC- 6 V
REG
VREF
bq24630
VCC
ACN
3.3 V
LDO
ACN -6 V
VCC
-
SRN+100 mV
+
VCC
V UVLO
+
ACN
+
SRN+200 mV
-
SLEEP
UVLO
VCC
VCC- 6 V VCC- 6 V
REG
SLEEP
-
VCC
UVLO
SYSTEM
POWER
SELECTOR
LOGIC
ACN - SRN
ACDRV
VCC- 6 V
ACN
ACOV
BATDRV
CE
1M
ACN - 6 V
+
V(ACP-ACN)
20X
-
+
COMP
ERROR
AMPLIFIER
-
ACN
CE
BTST
-
ACSET
+
1V
PWM
-
VFB
+
ACP
+
LEVEL
SHIFTER
-
1.8 V
20 mA
SRP
+
SRP- SRN
SYNCH
V(SRP-SRN)
+
5mV -
+
IBAT_ REG
SRN
-
+
20X
-
HIDRV
BAT_OVP
VCC
CE
REFRESH
-
BTST
PH _ +
20 mA
PH
PWM
CONTROL
LOGIC
6 V LDO
REGN
+
4.2V
DISCHARGE
OR
CHARGE
FAULT
2 mA
8 mA
LODRV
V(SRP-SRN)
-
160% X IBAT_REG
+
Safety Timer
TTC
TTC
CHG_OCP
GND
FAULT
STAT1
30 minute
Precharge
timer
IC Tj
+
TSHUT
-
145 °C
ISET1
8
IBAT_ REG
1.25 mV
VFB
0.35V +-
BAT
108% X VBAT_REG
-
LOWV
+
-
BAT_OVP
LTF
TTC
-
0.4 V
+
VCC
+
VACOV +-
RCHRG
DISABLE
TMR/TERM
BATTERY
DETECTION
LOGIC
COOL
-
SUSPEND
PG
-
+
-
ACOV
HTF
+
TS
+
-
RCHRG
-
ISET2
TERM
TERM
TCO
+
-
+
100X V(SRP -SRN)
bq24630
-
+
1.675V +-
ISET2
STAT2
VREF
+
WARM
COOL
WARM
VFB
STATE
MACHINE
LOGIC
-
ISET1
+
ISET1
CHARGE
STAT1
STAT2
PG
DISCHARGE
TERMINATE CHARGE
14
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8.3 Feature Description
8.3.1 Battery Voltage Regulation
The bq24630 uses a high-accuracy voltage band gap and regulator for the high-accuracy charging voltage. The
charge voltage is programmed via a resistor divider from the battery to ground, with the midpoint tied to the VFB
pin. The voltage at the VFB pin is regulated to 1.8 V, giving Equation 1 for the regulation voltage:
é R2 ù
VBAT = 1.8 V ´ ê1 +
ú
ë R1 û
(1)
Where R2 is connected from VFB to the battery and R1 is connected from VFB to GND.
8.3.2 Battery Current Regulation
The ISET1 input sets the maximum fast-charge current. Battery charge current is sensed by resistor RSR
connected between SRP and SRN. The full-scale differential voltage between SRP and SRN is 100 mV. Thus,
for a 10-mΩ sense resistor, the maximum charging current is 10 A. Equation 2 is for charge current:
VISET1
ICHARGE =
20 ´ RSR
(2)
VISET1, the input voltage range of ISET1, is between 0 and 2 V. The SRP and SRN pins are used to sense
voltage across RSR with default value of 10 mΩ. However, resistors of other values can also be used. A larger
sense resistor gives a larger sense voltage and a higher regulation accuracy, but at the expense of higher
conduction loss.
8.3.3 Precharge
On powerup, if the battery voltage is below the VLOWV threshold, the bq24630 applies 125 mA precharge current
to the battery (1). The precharge feature is intended to revive deeply discharged cells. If the VLOWV threshold is
not reached within 30 minutes of initiating precharge, the charger turns off and a FAULT is indicated on the
status pins.
8.3.4 Input Adapter Current Regulation
The total input from an ac adapter or other dc source is a function of the system supply current and the battery
charging current. System current normally fluctuates as portions of the system are powered up or down. Without
dynamic power management (DPM), the source must be able to supply the maximum system current and the
maximum charger input current simultaneously. By using DPM, the input current regulator reduces the charging
current when the input current exceeds the input current limit set by ACSET. The current capability of the ac
adaptor can be lowered, reducing system cost.
Similar to setting battery regulation current, adaptor current is sensed by resistor RAC connected between ACP
and ACN. Its maximum value is set by ACSET using Equation 3:
VACSET
IDPM =
20 ´ RAC
(3)
VACSET, the input voltage range of ACSET is between 0 and 2 V. The ACP and ACN pins are used to sense
voltage across RAC with a default value of 10 mΩ. However, resistors of other values can also be used. A larger
the sense resistor gives a larger sense voltage and a higher regulation accuracy, but at the expense of higher
conduction loss.
8.3.5 Charge Termination, Recharge, and Safety Timer
The bq24630 monitors the charging current during the voltage regulation phase. When VTTC is valid, termination
is detected while the voltage on the VFB pin is higher than the VRECH threshold AND the charge current is less
than the ITERM threshold, as calculated in Equation 4:
VISET2
ITERM =
100 ´ RSR
(4)
(1)
Assuming a 10-mΩ sense resistor. 1.25 mV is regulated across SRP-SRN, regardless of the value of the sense resistor.
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Feature Description (continued)
VISET2, the input voltage of ISET2 is between 0 and 2 V. The minimum termination current is clamped to be
around 125 mA with a default 10-mΩ sensing resistor. To avoid early termination during WARM/COOL condition,
set ITERM ≤ ICHARGE/10. As a safety backup, the bq24630 also provides a programmable charge timer. The charge
time is programmed by the capacitor connected between the TTC pin and GND, and is given by Equation 5:
tCHARGE = CTTC ´ K TTC
(5)
Where CTTC (range from 0.047 µF to 0.47 µF to give 1-h to 10-h safety timer) is the capacitor connected from
TTC pin to GND, and KTTC is the constant multiplier (1.4 min/nF).
A
•
•
•
new charge cycle is initiated and the safety timer is reset when one of the following conditions occurs:
The battery voltage falls below the recharge threshold.
A power-on-reset (POR) event occurs.
CE is toggled.
The TTC pin may be taken LOW to disable termination and to disable the safety timer. If TTC is pulled to VREF,
the bq24630 continues to allow termination but disables the safety timer. TTC taken low resets the safety timer.
When ACOV, VCCLOWV, and SLEEP mode resume normal, the safety timer is reset.
8.3.6 Power Up
The bq24630 uses a SLEEP comparator to determine the source of power on the VCC pin, because VCC can be
supplied either from the battery or the adapter. If the VCC voltage is greater than the SRN voltage, the bq24630
enables ACFET and disables BATFET. If all other conditions are met for charging, the bq24630 then attempts to
charge the battery (see Enable and Disable Charging section). If the SRN voltage is greater than VCC, indicating
that the battery is the power source, the bq24630 enables the BATFET and enters a low-quiescent-current (<15μA) SLEEP mode to minimize current drain from the battery.
If VCC is below the UVLO threshold, the device is disabled, ACFET turns off ,and BATFET turns on.
8.3.7 Enable and Disable Charging
The following conditions must be valid before charge is enabled:
• CE is HIGH.
• The device is not in undervoltage lockout (UVLO) and not in VCCLOWV mode.
• The device is not in SLEEP mode.
• The VCC voltage is lower than the ac overvoltage threshold (VCC < VACOV).
• 30-ms delay is complete after initial power up.
• The REGN LDO and VREF LDO voltages are at the correct levels.
• Thermal shut (TSHUT) is not valid.
• TS fault is not detected.
Any of the following conditions stops ongoing charging:
• CE is LOW.
• Adapter is removed, causing the device to enter UVLO, VCCLOWV, or SLEEP mode.
• Adapter is over voltage.
• The REGN or VREF LDOs are overloaded.
• TSHUT IC temperature threshold is reached (145°C on rising edge with 15°C hysteresis).
• TS voltage goes out of range, indicating the battery temperature is too hot or too cold.
• TTC saftey timer times out.
8.3.8 System Power Selector
The bq24630 automatically switches adapter or battery power to the system load. The battery is connected to the
system by default during power up or during SLEEP mode. The battery is disconnected from the system and
then the adapter is connected to the system 30 ms after exiting SLEEP. Automatic break-before-make logic
prevents shoot-through currents when the selectors switch.
16
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Feature Description (continued)
ACDRV is used to drive a pair of back-to-back p-channel power MOSFETs between adapter and ACP with
sources connected together and to VCC. The FET connected to the adapter prevents reverse discharge from the
battery to the adapter when turned off. The p-channel FET with the drain connected to the adapter input provides
reverse battery discharge protection when off; and also minimizes system power dissipation, with its low rDS(on),
compared to a Schottky diode. The other p-channel FET connected to ACP separates the battery from the
adapter, and provides a limited dI/dt when connecting the adapter to the system by controlling the FET turnon
time. BATDRV controls a p-channel power MOSFET placed between BAT and the system.
When an adapter is not detected, ACDRV is pulled to VCC to keep ACFET off, disconnecting the adapter from
system. BATDRV stays at ACN-6V to connect the battery to the system.
Approximately 30 ms after the device comes out of SLEEP mode, the system begins to switch from battery to
adapter. The break-before-make logic keeps both ACFET and BATFET off for 10 µs before ACFET turns on.
This prevents shoot-through current or any large discharging current from going into the battery. BATDRV is
pulled up to ACN and the ACDRV pin is set to VCC-6V by an internal regulator to turn on p-channel ACFET,
connecting the adapter to the system.
When the adapter is removed, the system waits until VCC drops back to within 200 mV above SRN to switch
from the adapter back to the battery. The break-before-make logic still keeps 10-μs dead time. ACDRV is pulled
up to VCC and the BATDRV pin is set to ACN-6V by an internal regulator to turn on p-channel BATFET,
connecting the battery to the system.
Asymmetrical gate drive for the ACDRV and BATDRV drivers provides fast turnoff and slow turnon of ACFET
and BATFET to help the break-before-make logic and to allow a soft-start at turnon of either FET. The soft-start
time can be further increased by putting a capacitor from gate to source of the p-channel power MOSFETs.
8.3.9 Automatic Internal Soft-Start Charger Current
The charger automatically soft-starts the charger regulation current every time the charger goes into fast-charge
to ensure there is no overshoot or stress on the output capacitors or the power converter. The soft-start consists
of stepping up the charge regulation current in eight evenly divided steps up to the programmed charge current.
Each step lasts around 1.6 ms, for a typical rise time of 12.8 ms. No external components are needed for this
function.
8.3.10 Converter Operation
The synchronous buck PWM converter uses a fixed-frequency voltage mode with feed-forward control scheme. A
type-III compensation network allows using ceramic capacitors at the output of the converter. The compensation
input stage is connected internally between the feedback output (FBO) and the error amplifier input (EAI). The
feedback compensation stage is connected between the error amplifier input (EAI) and error amplifier output
(EAO). The LC output filter is selected to give a resonant frequency of 10 kHz to 15 kHz for the bq24630, where
the resonant frequency, fo, is given by Equation 6:
1
fo =
2 p L o Co
(6)
An internal saw-tooth ramp is compared to the internal EAO error control signal to vary the duty cycle of the
converter. The ramp height is 7% of the input adapter voltage making it always directly proportional to the input
adapter voltage. This cancels out any loop gain variation due to a change in input voltage, and simplifies the loop
compensation. The ramp is offset by 300 mV in order to allow zero-percent duty cycle when the EAO signal is
below the ramp. The EAO signal is also allowed to exceed the saw-tooth ramp signal in order to get a 100%
duty-cycle PWM request. Internal gate drive logic allows achieving 99.95% duty cycle while ensuring the Nchannel upper device always has enough voltage to stay fully on. If the BTST pin to PH pin voltage falls below
4.2 V for more than three cycles, then the high-side n-channel power MOSFET is turned off and the low-side nchannel power MOSFET is turned on to pull the PH node down and recharge the BTST capacitor. Then the highside driver returns to 100% duty-cycle operation until the BTST-to-PH voltage is detected to fall low again due to
leakage current discharging the BTST capacitor below 4.2 V, and the reset pulse is reissued.
The fixed-frequency oscillator keeps tight control of the switching frequency under all conditions of input voltage,
battery voltage, charge current, and temperature, simplifying output filter design and keeping it out of the audible
noise region. Also see the Application Information section for how to select the inductor, capacitor, and MOSFET.
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Feature Description (continued)
8.3.11 Synchronous and Non-Synchronous Operation
The charger operates in synchronous mode when the SRP-SRN voltage is above 5 mV (0.5-A inductor current
for a 10-mΩ sense resistor). During synchronous mode, the internal gate-drive logic ensures there is breakbefore-make complementary switching to prevent shoot-through currents. During the 30-ns dead time where both
FETs are off, the body diode of the low-side power MOSFET conducts the inductor current. Having the low-side
FET turn on keeps the power dissipation low, and allows safely charging at high currents. During synchronous
mode, the inductor current is always flowing and the converter operates in continuous-conduction mode (CCM),
creating a fixed two-pole system.
The charger operates in non-synchronous mode when the SRP-SRN voltage is below 5 mV (0.5-A inductor
current for a 10-mΩ sense resistor). The charger is forced into non-synchronous mode when battery voltage is
lower than 2 V or when the average SRP-SRN voltage is lower than 1.25 mV.
During non-synchronous operation, the body-diode of the low-side MOSFET can conduct the positive inductor
current after the high-side n-channel power MOSFET turns off. When the load current decreases and the
inductor current drops to zero, the body diode is be naturally turned off and the inductor current becomes
discontinuous. This mode is called discontinuous-conduction mode (DCM). During DCM, the low-side n-channel
power MOSFET turns on for around 80 ns when the bootstrap capacitor voltage drops below 4.2 V; then the lowside power MOSFET turns off and stays off until the beginning of the next cycle, where the high-side power
MOSFET is turned on again. The 80-ns low-side MOSFET on-time is required to ensure the bootstrap capacitor
is always recharged and able to keep the high-side power MOSFET on during the next cycle. This is important
for battery chargers, where unlike regular dc-dc converters, there is a battery load that maintains a voltage and
can both source and sink current. The 80-ns low-side pulse pulls the PH node (connection between high- and
low-side MOSFETs) down, allowing the bootstrap capacitor to recharge up to the REGN LDO value. After 80 ns,
the low-side MOSFET is kept off to prevent negative inductor current from occurring.
At very low currents during non-synchronous operation, there may be a small amount of negative inductor
current during the 80-ns recharge pulse. The charge should be low enough to be absorbed by the input
capacitance. Whenever the converter goes into zero-percent duty cycle, the high-side MOSFET does not turn on,
and the low-side MOSFET does not turn on (only 80-ns recharge pulse) either, and there is almost no discharge
from the battery.
During the DCM mode, the loop response automatically changes and has a single-pole system at which the pole
is proportional to the load current, because the converter does not sink current, and only the load provides a
current sink. This means at very low currents the loop response is slower, as there is less sinking current
available to discharge the output voltage.
8.3.12 Cycle-By-Cycle Charge Undercurrent Protection
If the SRP-SRN voltage decreases below 5 mV (the charger is also forced into non-synchronous mode when the
average SRP-SRN voltage is lower than 1.25 mV), the low-side FET is turned off for the remainder of the
switching cycle to prevent negative inductor current. During DCM, the low-side FET only turns on for at around
80 ns when the bootstrap capacitor voltage drops below 4.2 V to provide refresh charge for the bootstrap
capacitor. This is important to prevent negative inductor current from causing a boost effect in which the input
voltage increases as power is transferred from the battery to the input capacitors and leads to an overvoltage
stress on the VCC node and potentially causes damage to the system.
8.3.13 Input Overvoltage Protection (ACOV)
ACOV provides protection to prevent system damage due to high input voltage. Once the adapter voltage
reaches the ACOV threshold, charge is disabled and the battery is switched to the system instead of the adapter.
8.3.14 Input Undervoltage Lockout (UVLO)
The system must have a minimum VCC voltage to allow proper operation. This VCC voltage could come from
either the input adapter or the battery, because a conduction path exists from the battery to VCC through the
high-side NMOS body diode. When VCC is below the UVLO threshold, all circuits on the IC are disabled, and the
gate drive bias to ACFET and BATFET is disabled.
18
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Feature Description (continued)
8.3.15 Battery Overvoltage Protection
The converter does not allow the high-side FET to turn on until the BAT voltage goes below 105% of the
regulation voltage. This allows one-cycle response to an overvoltage condition, such as occurs when the load is
removed or the battery is disconnected. An 8-mA current sink from SRP to GND is on only during charge and
allows discharging the stored output inductor energy that is transferred to the output capacitors. BATOVP also
suspends the safety timer.
8.3.16 Cycle-By-Cycle Charge Overcurrent Protection
The charger has a secondary cycle-to-cycle overcurrent protection. It monitors the charge current, and prevents
the current from exceeding 160% of the programmed charge current. The high-side gate drive turns off when the
overcurrent is detected, and automatically resumes when the current falls below the overcurrent threshold.
8.3.17 Thermal Shutdown Protection
The QFN package has low thermal impedance, which provides good thermal conduction from the silicon to the
ambient, to keep junctions temperatures low. As an added level of protection, the charger converter turns off and
self-protects whenever the junction temperature exceeds the TSHUT threshold of 145°C. The charger stays off
until the junction temperature falls below 130°C. Then the charger soft-starts again if all other enable-charge
conditions are valid. Thermal shutdown also suspends the safety timer.
8.3.18 Temperature Qualification
The controller continuously monitors battery temperature by measuring the voltage between the TS pin and
GND. A negative-temperature-coefficient thermistor (NTC) and an external voltage divider typically develop this
voltage. The controller compares this voltage against its internal thresholds to determine if charging is allowed.
To initiate a charge cycle, the battery temperature must be within the VLTF to VHTF thresholds. If battery
temperature is outside of this range, the controller suspends charge and the safety timer, and waits until the
battery temperature is within the VLTF to VHTF range. During the charge cycle, the battery temperature must be
within the VLTF to VTCO thresholds. If the battery temperature is outside of this range, the controller suspends
charge and the safety timer, and waits until the battery temperature is within the VLTF to VHTF range. If the battery
temperature is between the VLTF and VCOOL thresholds or between the VHTF and VWARM thresholds, charge is
automatically reduced to ICHARGE/8. To avoid early termination during a COOL/WARM condition, set ITERM ≤
ICHARGE/10. The controller suspends charge by turning off the PWM charge FETs. Figure 16 and Figure 17
summarize the operation.
TEMPERATURE RANGE TO
INITIATE CHARGE
TEMPERATURE RANGE
DURING A CHARGE CYCLE
VREF
VREF
CHARGE SUSPENDED
CHARGE SUSPENDED
VLTF
VLTF_HYS
VLTF
CHARGE at ICHARGE/8
VCOOL
CHARGE at ICHARGE/8
VCOOL
VCOOL_HYS
CHARGE at ICHARGE
CHARGE at ICHARGE
VWARM
VWARM_HYS
VWARM
CHARGE at ICHARGE/8
CHARGE at ICHARGE/8
VHTF
VTCO
CHARGE SUSPENDED
CHARGE SUSPENDED
GND
GND
Figure 16. TS, Thermistor Sense Thresholds
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Feature Description (continued)
ICHARGE/8
Charge
Programmed
Charge Current
Charge
Suspended
ICHARGEG/8
Charge
Charge
Current
Charge at ICHG
Charge
Suspended
(ICHARGE)
1/8 x Programmed
Charge Current
(ICHARGE/8)
VWARM VHTF/VTCO Temperature
VLTF VCOOL
Figure 17. Typical Charge Current vs Temperature Profile
Assuming a 103AT NTC thermistor on the battery pack as shown in the Figure 22, the value RT1 and RT2 can
be determined by using Equation 7 and Equation 8:
æ 1
ö
1
VVREF ´ RTHCOOL ´ RTHWARM ´ ç
÷
V
V
WARM ø
è COOL
RT2 =
æV
ö
æ V
ö
RTHWARM ´ ç VREF - 1÷ - RTHCOOL ´ ç VREF - 1÷
è VWARM
ø
è VCOOL
ø
(7)
VVREF
-1
VCOOL
RT1 =
1
1
+
RT2
RTHCOOL
(8)
VREF
bq24630
RT1
TS
RT2
RTH
103 AT
Figure 18. TS Resistor Network
20
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Feature Description (continued)
For example, a 103AT NTC thermistor is used to monitor the battery pack temperature. Select TCOOL = 0ºC,
TWARM = 60ºC. From the calculation and select standard 5% resistor value, RT1 = 2.2 kΩ, RT2 = 6.8 kΩ, and
TCOLD is –17ºC (target –20ºC); THOT is 77ºC (target 75ºC), and TCUT-OFF is 86ºC (target 80ºC). A small RC filter is
suggested to protect the TS pin from system-level ESD.
8.3.19 Timer Fault Recovery
The bq24630 provides a recovery method to deal with timer fault conditions. The following summarizes this
method:
Condition 1: The battery voltage is above the recharge threshold and a time-out fault occurs.
Recovery Method: The timer fault clears when the battery voltage falls below the recharge threshold, and
battery detection begins. Taking CE low, or a POR condition, also clears the fault.
Condition 2: The battery voltage is below the RECHARGE threshold and a time-out fault occurs.
Recovery Method: Under this scenario, the bq24630 applies the IFAULT current to the battery. This small
current is used to detect a battery removal condition and remains on as long as the battery voltage stays below
the recharge threshold. If the battery voltage goes above the recharge threshold, the bq24630 disables the fault
current and executes the recovery method described in Condition 1. Taking CE low, or a POR condition, also
clears the fault.
8.3.20
PG Output
The open drain PG (power-good) output indicates whether the VCC voltage is valid or not. The open-drain FET
turns on whenever bq24630 has a valid VCC input (not in UVLO or ACOV or SLEEP mode). The PG pin can be
used to drive an LED or communicate with the host processor.
8.3.21 CE (Charge Enable)
The CE digital input is used to disable or enable the charge process. A high-level signal on this pin enables
charge, provided all the other conditions for charge are met (see Enable and Disable Charging). A high-to-low
transition on this pin also resets all timers and fault conditions. There is an internal 1-MΩ pulldown resistor on the
CE pin, so if CE is floated the charge does not turn on.
8.3.22 Charge Status Outputs
The open-drain STAT1 and STAT2 outputs indicate various charger operations as shown in Table 2. These
status pins can be used to drive LEDs or communicate with the host processor. Note that OFF indicates that the
open-drain transistor is turned off.
Table 2. Stat Pin Definition for bq24630
STAT1
STAT2
Charge in progress
CHARGE STATE
ON
OFF
Charge complete
OFF
ON
Charge suspend, timer fault, overvoltage, sleep mode, battery absent
OFF
OFF
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8.3.23 Battery Detection
For applications with removable battery packs, the bq24630 provides a battery-absent detection scheme to
reliably detect the insertion or removal of battery packs.
POR or RECHARGE
The battery detection routine runs on
power up , or if VFB falls below VRECH
due to removing a battery or
discharging a battery
Apply 8 mA discharge
current, start 1s timer
VFB < VLOWV
1s timer
expired
No
Yes
Yes
Disable 8 mA
discharge current
Battery Present,
Begin Charge
No
Enable 125 mA Charge,
Start 0.5s timer
VFB > VRECH
No
0.5s timer
expired
Yes
Yes
Disable 125 mA
Charge
No
Battery Present,
Begin Charge
Battery Absent
Figure 19. Battery Detection Flowchart
22
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Once the device has powered up, an 8-mA discharge current is applied to the SRN terminal. If the battery
voltage falls below the LOWV threshold within 1 second, the discharge source is turned off, and the charger is
turned on at low charge current (125 mA). If the battery voltage rises above the recharge threshold within 500
ms, there is no battery present and the cycle restarts. If either the 500-ms or 1-second timer times out before the
respective thresholds are hit, a battery is detected and a charge cycle is initiated.
Battery not Detected
VREG
VRECH
Battery
Inserted
(VWAKE)
VLOWV
Battery Detected
(VDISH)
tWAKE
tLOWV_DEG
tRECH_DEG
Figure 20. Battery Detect Timing Diagram
Care must be taken that the total output capacitance at the battery node is not so large that the discharge current
source cannot pull the voltage below the LOWV threshold during the 1-second discharge time. The maximum
output capacitance can be calculated as seen in Equation 9:
CMAX =
IDISCH ´ tDISCH
é R ù
1.425 ´ ê1+ 2 ú
ë R1 û
(9)
Where CMAX is the maximum output capacitance, IDISCH is the discharge current, tDISCH is the discharge time, and
R2 and R1 are the voltage feedback resistors from the battery to the VFB pin. The 1.425 factor is the difference
between the RECHARGE and the LOWV thresholds at the VFB pin.
EXAMPLE
For a 3-cell LiFePO4 charger, with R2 = 500 kΩ, R1 = 100 Ωk (giving 10.8 V for voltage regulation), IDISCH = 8
mA, tDISCH = 1 second,
8mA ´ 1sec
CMAX =
= 930 mF
é 500k ù
1.425 ´ ê1+
ú
ë 100k û
(10)
Based on these calculations, no more than 930 μF should be allowed on the battery node for proper operation of
the battery detection circuit.
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8.4 Device Functional Modes
Figure 21. Device Operational Flow Chart
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The bq24630 battery charger is ideal for high current charging (up to 10 A) and can charge battery packs
consisting of single cells or multiple cells in series. The bq24630EVM is a complete charge module for evaluating
the bq24630. The application curves were taken using the bq24630EVM. Refer to the EVM user's guide
(SLUU396) for EVM information.
9.2 Typical Application
Q1 (ACFET)
SI7617DN
R17
10Ω
SYSTEM
P
ADAPTER-
P
R14
100 kW
C16
2.2μF
RAC
0.010 W
Q2 (ACFET)
SI7617DN
C14
0.1 mF
C15
0.1 µF
ACN
C3
0.1 µF
C2
0.1 µF
VCC
BATDRV
ACDRV
R5
100 kW
R18
1 kΩ
R7
100 kW
R6
10 kW
R15
100 kW
PH
ISET2
BTST
R8
22.1 kW
REGN
bq24630
C6
0.1 µF
C5
1 µF
VREF
LODRV
C4
1 µF
RSR
0.010 W
C10
0.1 µF
C12
C13
10 µF* 10 µF*
STAT1
D3
STAT2
D4
PG
C11
0.1 µF
SRP
R12 10 kW
ADAPTER +
R13 10 kW
VREF
Pack
Thermistor
Sense
103AT
PACK+
PACK-
CE
D2
VBAT
8.2 µH*
Q5
SIS412DN
GND
R11 10 kW
Q4
SIS412DN
L1
D1
BAT54
P
Q3 (BATFET)
SI7617DN
R19
1 kΩ
HIDRV
ISET1
ACSET
R4
32.4 kW
C7
1 µF
ACP
VREF
R3
100 kW
C9
10 μF
C8
10 µF
N
R20
2Ω
N
ADAPTER+
R2
500kW
Cff
22 pF
R1
100 kW
SRN
VFB
R16
100 W
R9
2.2 kW
C1
0.1 μF
R10
6.8 kW
TS
TTC
PwrPad
CTTC
0.11 μF
NOTE: VIN = 19 V, BAT = 3-cell LiFePO4, Iadapter_limit = 4 A, Icharge= 3 A, Ipre-charge= 0.125 A, Iterm= 0.3 A, 2.5-h safety timer
Figure 22. Typical System Schematic
9.2.1 Design Requirements
For this design example, use the parameters listed in Table 3 as the input parameters.
Table 3. Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
AC adapter voltage (VIN)
19 V
AC adapter current limit
4A
Battery charge voltage (number of cells in series)
Battery charge current (during constant current phase)
10.8 V (3 cells)
3A
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Table 3. Design Parameters (continued)
DESIGN PARAMETER
Precharge current
EXAMPLE VALUE
0.125 A
Termination current
0.3 A
Safety timer
2.5 hours
9.2.2 Detailed Design Procedure
9.2.2.1 Inductor Selection
The bq24630 has 300-kHz switching frequency to allow the use of small inductor and capacitor values. Inductor
saturation current should be higher than the charging current (ICHARGE) plus half the ripple current (IRIPPLE):
ISAT ³ ICHG + (1/2) IRIPPLE
(11)
The inductor ripple current depends on input voltage (VIN), duty cycle (D = VOUT/VIN), switching frequency (fs) and
inductance (L):
V ´ D ´ (1 - D)
IRIPPLE = IN
fS ´ L
(12)
The maximum inductor ripple current happens with D = 0.5. For example, the battery charging voltage range is
from 2.8 V to 14.4 V for a 4-cell battery pack. For 20-V adapter voltage, 10-V battery voltage gives the maximum
inductor ripple current.
Usually, inductor ripple is designed in the range of 20%–40% of maximum charging current as a trade-off
between inductor size and efficiency for a practical design.
The bq24630 has cycle-by-cycle charge undercurrent protection (UCP) by monitoring the charge-current sensing
resistor to prevent negative inductor current. The typical UCP threshold is 5 mV falling edge, corresponding to
0.5-A falling edge for a 10-mΩ charge-current sensing resistor.
9.2.2.2 Input Capacitor
Input capacitor should have enough ripple-current rating to absorb the input switching-ripple current. The worstcase RMS ripple current is half of the charging current when the duty cycle is 0.5. If the converter does not
operate at 50% duty cycle, then the worst-case capacitor rms current ICIN occurs where the duty cycle is closest
to 50% and can be estimated by the following equation:
ICIN = ICHG ´
D ´ (1 - D)
(13)
A low-ESR ceramic capacitor such as X7R or X5R is preferred for the input decoupling capacitor and should be
placed as close as possible to the drain of the high-side MOSFET and source of the low-side MOSFET. The
voltage rating of the capacitor must be higher than the normal input voltage level. A 25-V rating or higher
capacitor is preferred for 20-V input voltage. A 20-µF capacitance is suggested for typical of 3-A to 4-A charging
current.
9.2.2.3 Output Capacitor
Output capacitor also should have enough ripple current rating to absorb output switching ripple current. The
output capacitor RMS current ICOUT is given:
I
ICOUT = RIPPLE » 0.29 ´ IRIPPLE
2 ´ 3
(14)
The output capacitor voltage ripple can be calculated as follows:
DVo =
1
8LCfs
2
æ
V 2
ç VBAT - BAT
ç
VIN
è
ö
÷
÷
ø
(15)
At certain input/output voltage and switching frequency, the voltage ripple can be reduced by increasing the
output filter LC.
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The bq24630 has internal loop compensator. To get good loop stability, the resonant frequency of the output
inductor and output capacitor should be designed between 10 kHz and 15 kHz. The preferred ceramic capacitor
is 25 V, X7R or X5R for 4-cell applications.
9.2.2.4 Power MOSFET Selection
Two external N-channel MOSFETs are used for a synchronous switching battery charger. The gate drivers are
internally integrated into the IC with 6 V of gate drive voltage. 30-V or higher voltage rating MOSFETs are
preferred for a 20-V input voltage and 40-V MOSFETs are prefered for 20-V to 28-V input voltage.
Figure of merit (FOM) is usually used for selecting the proper MOSFET based on a tradeoff between the
conduction loss and switching loss. For a top-side MOSFET, FOM is defined as the product of a MOSFET onresistance, rDS(on), and the gate-to-drain charge, QGD. For a bottom-side MOSFET, FOM is defined as the product
of the MOSFET on-resistance, rDS(on), and the total gate charge, QG.
FOM top = RDS(on) ´ QG D
FOMbottom = RDS(on) ´ QG
(16)
The lower the FOM value, the lower the total power loss. Usually, lower rDS(on) has higher cost with the same
package size.
The top-side MOSFET loss includes conduction loss and switching loss. It is a function of duty cycle (D =
VOUT/VIN), charging current (ICHARGE), MOSFET on-resistance (rDS(on)), input voltage (VIN), switching frequency
(fS), turnon time (ton) and turnoff time (toff):
1
Ptop = D ´ ICHG2 ´ RDS(on) +
´ VIN ´ ICHG ´ (t on + t off ) ´ fS
2
(17)
The first item represents the conduction loss. Usually, MOSFET rDS(on) increases by 50% with a 100ºC junction
temperature rise. The second term represents the switching loss. The MOSFET turnon and turnoff times are
given by:
Q
Q
ton = SW , t off = SW
Ion
Ioff
(18)
where Qsw is the switching charge, Ion is the turnon gate-driving current, and Ioff is the turnoff gate-driving current.
If the switching charge is not given in the MOSFET datasheet, it can be estimated by gate-to-drain charge (QGD)
and gate-to-source charge (QGS):
1
QSW = QGD +
´ QGS
2
(19)
Total gate-driving current can be estimated by the REGN voltage (VREGN), MOSFET plateau voltage (Vplt), total
turnon gate resistance (Ron), and turnoff gate resistance (Roff) of the gate driver:
VREG N - Vplt
Vplt
Ion =
, Ioff =
Ron
Roff
(20)
The conduction loss of the bottom-side MOSFET is calculated with the following equation when it operates in
synchronous continuous conduction mode:
Pbottom = (1 - D) ´ ICHG 2 ´ RDS(on)
(21)
If the SRP-SRN voltage decreases below 5 mV (the charger is also forced into non-synchronous mode when the
average SRP-SRN voltage is lower than 1.25 mV), the low-side FET is turned off for the remainder of the
switching cycle to prevent negative inductor current.
As a result, all the freewheeling current goes through the body diode of the bottom-side MOSFET. The maximum
charging current in non-synchronous mode can be up to 0.9 A (0.5 A typ.) for a 10-mΩ charging-current sensing
resistor, considering IC tolerance. Choose the bottom-side MOSFET with either an internal Schottky or body
diode capable of carrying the maximum non-synchronous mode charging current.
MOSFET gate driver power loss contributes to the dominant losses on the controller IC when the buck converter
is switching. Choosing a MOSFET with a small Qg_total reduces the IC power loss to avoid thermal shutdown.
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PICLoss_driver = VIN × Qg_total × fs
(22)
where Qg_total is the total gate charge for both upper and lower MOSFET at 6-V VREGN.
The VREF load current is another component of the VCC input current (Do not overload VREF.), where total IC
loss can be described by following equations:
PVREF = (VIN - VVREF ) × IVREF
PICLOSS = PICLOSS _ driver + PVREF + PQuiescent
(23)
9.2.2.5 Input Filter Design
During adapter hot plug-in, the parasitic inductance and input capacitor from the adapter cable form a secondorder system. The voltage spike at the VCC pin may be beyond the IC maximum voltage rating and damage the
IC. The input filter must be carefully designed and tested to prevent an overvoltage event on the VCC pin. The
ACP/ACN pin must be placed after the input ACFETs in order to avoid overvoltage stress and high dv/dt during
hot plug-in.
There are several methods for damping or limiting the overvoltage spike during adapter hot plug-in. An
electrolytic capacitor with high ESR as an input capacitor can damp the overvoltage spike well below the IC
maximum pin voltage rating. A high-current-capability TVS Zener diode can also limit the overvoltage level to an
IC-safe level. However, these two solutions may not have low cost or small size.
A cost-effective and small-size solution is shown in Figure 23. R1 and C1 comprise a damping RC network to
damp the hot plug-in oscillation. As a result, the overvoltage spike is limited to a safe level. D1 is used for
reverse voltage protection for the VCC pin (it can be the body diode of input ACFET). C2 is VCC pin-decoupling
capacitor and it should be placed as close as possible to the VCC pin. R2 and C2 form a damping RC network to
further protect the IC from high-dv/dt and high-voltage spikes. The C2 value should be less than the C1 value so
R1 can be dominant over the ESR of C1 to get enough damping effect for hot plug-in. The R1 and R2 packages
must be sized to handle static current and inrush current power loss according to the resistor manufacturer’s
datasheet. The values of filter components always must be verified with the real application, and minor
adjustments may be needed to fit in the real application circuit.
D1
Adapter
connector
R1
2W
C1
2.2 mF
(2010)
R2 (1206)
4.7 -30W
VCC pin
C2
0.1-1 mF
Figure 23. Input Filter
9.2.2.6 Inductor, Capacitor, and Sense Resistor Selection Guidelines
The bq24630 provides internal loop compensation. With this scheme, best stability occurs when the LC resonant
frequency, fo, is approximately 10 kHz to 15 kHz per Equation 24:
1
fo =
2 p L o Co
(24)
Table 4 provides a summary of typical LC components for various charge currents
Table 4. Typical Inductor, Capacitor, and Sense Resistor Values as a Function of Charge Current
CHARGE CURRENT
Output Inductor LO
2A
4A
6A
8A
10 A
8.2 μH
8.2 μH
5.6 μH
4.7 μH
4.7 μH
Output capacitor CO
20 μF
20 μF
30 μF
40 μF
40 μF
Sense resistor
10 mΩ
10 mΩ
10 mΩ
10 mΩ
10 mΩ
28
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9.2.2.7 Typical System Circuit Component List
The following table lists the components for the typical system circuit in Figure 22.
PART DESIGNATOR
QTY
DESCRIPTION
Q1, Q2, Q3
3
P-channel MOSFET, –30 V, –35 A, PowerPAK 1212-8, Vishay-Siliconix, Si7617DN
Q4, Q5
2
N-channel MOSFET, 30 V, 12 A, PowerPAK 1212-8, Vishay-Siliconix, Sis412DN
D1
1
Diode, dual Schottky, 30 V, 200 mA, SOT23, Fairchild, BAT54C
D2, D3, D4
3
LED diode, green, 2.1 V, 20 mA, LTST-C190GKT
RAC, RSR
2
Sense resistor, 10 mΩ, 2010, Vishay-Dale, WSL2010R0100F
L1
1
Inductor, 6.8 µH, 5.5 A, Vishay-Dale IHLP2525CZ
C2, C10
2
Capacitor, ceramic, 0.1 µF, 50 V, 10%, X7R
C7
1
Capacitor, ceramic, 1 µF, 50 V, 10%, X7R
C8, C9, C12, C13
4
Capacitor, ceramic, 10 µF, 35 V, 20%, X7R
C4, C5
2
Capacitor, ceramic, 1 µF, 25 V, 10%, X7R
C1, C3, C6, C11
4
Capacitor, ceramic, 0.1 µF, 16 V, 10%, X7R
C14, C15 (Optional)
2
Capacitor, ceramic, 0.1 µF, 50 V, 10%, X7R
C16
1
Capacitor, ceramic, 2.2 µF, 35 V, 10%, X7R
Cff
1
Capacitor, ceramic, 22 pF, 25 V, 10%, X7R
CTTC
1
Capacitor, ceramic, 0.11 µF, 25 V, 5%, X7R
R1, R3, R5, R7
4
Resistor, chip, 100 kΩ, 1/16W, 0.5%
R2
1
Resistor, Chip, 500 kΩ, 1/16W, 0.5%
R4
1
Resistor, chip, 32.4 kΩ, 1/16W, 0.5%
R6
1
Resistor, chip, 10 kΩ, 1/16W, 0.5%
R8
1
Resistor, chip, 22.1 kΩ, 1/16W, 0.5%
R9
1
Resistor, chip, 2.2 kΩ, 1/16W, 5%
R10
1
Resistor, chip, 6.8 kΩ, 1/16W, 5%
R11, R12, R13
3
Resistor, chip, 10 kΩ, 1/16W, 5%
R14, R15 (optional)
2
Resistor, chip, 100 kΩ, 1/16W, 5%
R16
1
Resistor, chip, 100 Ω, 1/16W, 5%
R17
1
Resistor, chip, 10 Ω, 1/4W, 5%
R18, R19
2
Resistor, chip, 1 kΩ, 1/16W, 5%
R20
1
Resistor, chip, 2 Ω, 1W, 5%
9.2.3 Application Curves
VIN: 24 V
VBAT: 16 V
ICHG = 3 A
VIN: 24 V
Figure 24. Continuous Conduction Mode Switching
Waveform
VBAT: 16 V
Figure 25. Battery Charging Soft Start
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10 Power Supply Recommendations
For proper operation of bq24630, VCC must be from 5 V to 28 V. To begin charging, VCC must be higher than
SRN by at least 500 mV (otherwise, the device will be in sleep mode). TI recommends an input voltage of at
least 1.5 V to 2 V higher than the battery voltage, taking into consideration the DC losses in the high-side FET
(Rdson), inductor (DCR), and input sense resistor (between ACP and ACN), the body diode drop of RBFET
between VCC and input power supply, and battery sense resistor (between SRP and SRN). Power limit for the
input supply must be greater than the maximum power required by either the system load or for battery charging
(the greater of the two).
11 Layout
11.1 Layout Guidelines
The switching node rise and fall times should be minimized for minimum switching loss. Proper layout of the
components to minimize the high-frequency current path loop (see Figure 26) is important to prevent electrical
and magnetic field radiation and high-frequency resonance problems. Here is a PCB layout priority list for proper
layout. Layout of the PCB according to this specific order is essential.
1. Place the input capacitor as close as possible to switching the MOSFET supply and ground connections and
use the shortest possible copper trace connection. These parts should be placed on the same layer of PCB
instead of on different layers using vias to make this connection.
2. The IC should be placed close to the switching MOSFET gate terminals, keeping the gate-drive signal traces
short for a clean MOSFET drive. The IC can be placed on the other side of the PCB from the switching
MOSFETs.
3. Place the inductor input terminal as close as possible to the switching MOSFET output terminal. Minimize the
copper area of this trace to lower electrical and magnetic field radiation, but make the trace wide enough to
carry the charging current. Do not use multiple layers in parallel for this connection. Minimize parasitic
capacitance from this area to any other trace or plane.
4. The charging-current sensing resistor should be placed right next to the inductor output. Route the sense
leads connected across the sensing resistor back to the IC in the same layer, close to each other (minimize
loop area), and do not route the sense leads through a high-current path (see Figure 27 for Kelvin
connection for best current accuracy). Place a decoupling capacitor on these traces next to the IC.
5. Place the output capacitor next to the sensing resistor output and ground.
6. Output capacitor ground connections must be tied to the same copper that connects to the input capacitor
ground before connecting to system ground.
7. Route the analog ground separately from the power ground and use a single ground connection to tie the
charger power ground to the charger analog ground. Just beneath the IC, use the copper pour for analog
ground, but avoid power pins to reduce inductive and capacitive noise coupling. Connect the analog ground
to GND. Connect the analog ground and power ground together using the power pad as the single ground
connection point. Or use a 0-Ω resistor to tie the analog ground to power ground (the thermal pad should tie
to analog ground in this case). A star-connection under the tharmal pad is highly recommended.
8. It is critical that the exposed thermal pad on the backside of the IC package be soldered to the PCB ground.
Ensure that there are sufficient thermal vias directly under the IC connecting to the ground plane on the other
layers.
9. Decoupling capacitors should be placed next to the IC pins; make the trace connections as short as possible.
10. All via sizes and numbers should be adequate for a given current path.
See the EVM design (SLUU396) for recommended component placement of trace and via locations.
For VQFN information, see SCBA017 and SLUA271.
30
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11.2 Layout Example
SW
L1
V BAT
R1
High
Frequency
VIN
BAT
Current
C1
Path
PGND
C2
C3
Figure 26. High Frequency Current Path
Current Direction
R SNS
Current Sensing Direction
To SRP - SRN pin or ACP - ACN pin
Figure 27. Sensing Resistor PCB Layout
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
12.2 Documentation Support
12.2.1 Related Documentation
bq2461x/bq2463x EVM (HPA422) Multi-Cell Synchronous Switch-Mode Charger EVM User's Guide
(SLUU396)
Quad Flatpack No-Lead Logic Packages Application Report (SCBA017)
QFN/SON PCB Attachment Application Report (SLUA271)
12.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
32
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PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
BQ24630RGER
ACTIVE
VQFN
RGE
24
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OAT
BQ24630RGET
ACTIVE
VQFN
RGE
24
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
OAT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
7-Apr-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Apr-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
BQ24630RGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
BQ24630RGER
VQFN
RGE
24
3000
330.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
BQ24630RGET
VQFN
RGE
24
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
BQ24630RGET
VQFN
RGE
24
250
180.0
12.4
4.25
4.25
1.15
8.0
12.0
Q2
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
7-Apr-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
BQ24630RGER
VQFN
RGE
24
3000
367.0
367.0
35.0
BQ24630RGER
VQFN
RGE
24
3000
367.0
367.0
35.0
BQ24630RGET
VQFN
RGE
24
250
210.0
185.0
35.0
BQ24630RGET
VQFN
RGE
24
250
210.0
185.0
35.0
Pack Materials-Page 2
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