ST STM32F7 Series Application notes
Below you will find brief information for microcontroller STM32F7 F769Ax, STM32F7 F768Ax, STM32F7 F767xx, STM32F7 F777xx, STM32F7 F72xxx. This document is intended for system designers who require an overview of the hardware implementation of a development board based on the STM32F7 Series devices. This document describes the minimum hardware resources required to develop an application based on the STM32F7 Series devices.
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AN4661
Application note
Getting started with STM32F7 Series MCU hardware development
Introduction
This application note is intended for system designers who require an hardware implementation overview of the development board, with a focus on the features:
• Power supply,
• Package selection,
• Clock management,
• Reset control,
• Boot mode settings,
• Debug management.
This document describes the minimum hardware resources required to develop an application based on the STM32F7 Series devices.
Reference documents
The following documents are available on
www.st.com
:
•
Oscillator design guide for STM8S, STM8A and STM32 microcontrollers
application note (AN2867),
•
STM32 microcontroller system memory boot mode
application note (AN2606).
February 2017 DocID027559 Rev 5 1/54
www.st.com
1
Contents
Contents
2/54
AN4661
Independent A/D converter supply and reference voltage . . . . . . . . . . . . 7
Independent USB transceivers supply . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Independent DSI supply for STM32F769xx/STM32F779xx devices . . . 10
Battery backup domain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Reset & power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Power-on reset (POR)/power-down reset (PDR) . . . . . . . . . . . . . . . . . . 17
Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . . 17
Regulator OFF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Regulator ON/OFF and internal reset ON/OFF availability . . . . . . . . . . 22
Alternate function mapping to pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
External user clock (HSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
External crystal/ceramic resonator (HSE crystal) . . . . . . . . . . . . . . . . . 25
External clock (LSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
External crystal/ceramic resonator (LSE crystal) . . . . . . . . . . . . . . . . . . 26
Clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
System bootloader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DocID027559 Rev 5
AN4661
Contents
Debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
SWJ debug port (serial wire and JTAG) . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
SWJ debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Flexible SWJ-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Internal pull-up and pull-down on JTAG pins . . . . . . . . . . . . . . . . . . . . . 31
SWJ debug port connection with standard JTAG connector . . . . . . . . . 32
Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Ground and power supply (VSS,VDD) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Unused I/Os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Recommendations for the WLCSP180 package in the
STM32F769Ax/STM32F768Ax devices . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Recommended PCB routing guidelines for
STM32F7 Series devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Power supply decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
SDMMC bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Flexible memory controller (FMC) interface . . . . . . . . . . . . . . . . . . . . . . 45
DocID027559 Rev 5 3/54
4
Contents AN4661
Quadrature serial parallel interface (Quad-SPI) . . . . . . . . . . . . . . . . . . 46
Embedded trace macrocell (ETM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Package layout recommendation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
BGA 216 0.8 mm pitch design example . . . . . . . . . . . . . . . . . . . . . . . . 47
WLCSP143 0.4 mm pitch design example . . . . . . . . . . . . . . . . . . . . . . 49
4/54 DocID027559 Rev 5
AN4661
List of tables
List of tables
DocID027559 Rev 5 5/54
5
List of figures
List of figures
AN4661
Example of bypass cap placed underneath the STM32F7 Series . . . . . . . . . . . . . . . . . . . 44
6/54 DocID027559 Rev 5
AN4661 Power supplies
1.1 Introduction
The device requires a 1.8 to 3.6 V operating voltage supply (V
DD
), which can be reduced down to 1.7 V with PDR OFF, as detailed in the product datasheets. The embedded linear voltage regulator is used to supply the internal 1.2 V digital power.
The real-time clock (RTC), the RTC backup registers, and the backup SRAM (BKP SRAM) can be powered from the V
BAT
voltage when the main V
DD
supply is powered off.
1.1.1
1.1.2
Independent A/D converter supply and reference voltage
To improve the conversion accuracy, the ADC has an independent power supply which can be separately filtered and shielded from noise on the PCB.
•
The ADC voltage supply input is available on a separate V
DDA
pin.
•
An isolated supply ground connection is provided on the pin V
SSA
.
To ensure a better accuracy of low voltage inputs, the user can connect a separate external reference voltage ADC input on V
REF
. The voltage on V
REF
ranges from 1.8 V to V
DDA
.
When available (depending on package), V
REF–
must be externally tied to V
SSA
.
Independent USB transceivers supply
The USB transceivers are supplied from a separated V
DDUSB
power supply pin.
The V
DDUSB
supply can be connected either to V
DD
or an external independent power
supply (3.0 to 3.6V) for the USB transceivers (refer to
and
when the device is powered at 1.8V, an independent power supply 3.3V can be connected to V
DDUSB
. When the V
DDUSB from V
DD
or V
DDA
is connected to a separated power supply, it is independent
but it must be the last supply to be provided and the first to disappear.
The following V
DDUSB conditions must be respected:
• During the power-on phase (V
DD
V
DD
.
< V
DD_MIN
), V
DDUSB
should be always lower than
•
During the power-down phase (V
DD
< V
DD_MIN
V
DD.
), V
DDUSB
should be always lower than
• The V
DDSUB
rising and falling time rate specifications must be respected (refer to
operating conditions at power-up / power-down (regulator ON)
table and
operating conditions at power-up / power-down (regulator OFF)
table provided in the product datasheet).
•
In operating mode phase, V
DDUSB
could be lower or higher than V
DD:
– If USB (USB OTG_HS/OTG_FS) is used, the associated GPIOs powered by
V
DDUSB are operating between V
DDUSB_MIN
and V
DDUSB_MAX
.
– The V
DDUSB
supplies both USB transceivers (USB OTG_HS and USB OTG_FS).
If only one USB transceiver is used in the application, the GPIOs associated to the other USB transceiver are still supplied by V
DDUSB
.
– If USB (USB OTG_HS/OTG_FS) is not used, the associated GPIOs powered by
V
DDUSB are operating between V
DD_MIN
and V
DD_MAX
.
DocID027559 Rev 5 7/54
53
Power supplies
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connected to V
DD
power supply
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connected to external power supply.
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In the STM32F7x3xx devices, the USB PHY HS sub-system uses an additional power supply pin:
•
The V
DD12OTGHS
pin is the output of the PHY HS regulator (1.2 V). An external capacitor of 2.2 µF must be connected on the V
DD12OTGHS
pin.
The PHY HS has another OTG_HS_REXT pin needed for calibration. This pin must be connected to gnd via an external precise resistor (3 Kohm +/- 1%).
8/54 DocID027559 Rev 5
AN4661 Power supplies
SDMMC2 and STM32F72xxx/STM32F73xxx devices
The V
DDSDMMC
is an independent power supply for SDMMC2 peripheral IOs (PD6, PD7,
PG9..12). It can be connected either to V
DD
or an external independent power supply.
For example, when the device is powered at 1.8V, an independent power supply 3.3V can be connected to V
DDSDMMC
. When the V
DDSDMMC supply, it is independent from V
DD
and V
DDA
but it must be the last supply to be provided and the first to disappear. The following V
is connected to a separated power
DDSDMMC
conditions must be respected:
•
During the power-on phase (V
DD
V
DD
.
•
During the power-down phase (V
DD than V
DD
.
< V
DD_MIN
), V
DDSDMMC
< V
DD_MIN
), V
should be always lower than
DDSDMMC
should be always lower
• The V
DDSDMMC
rising and falling time rate specifications must be respected.
•
In the operating mode phase, V
DDSDMMC associated GPIOs (PD6, PD7, PG9..12) powered by V
DDSDMMC
V
DDSDMMC_MIN powered by V
and V
DDSDMMC_MAX
DDSDMMC
could be lower or higher than V
DD
. If V
DDSDMMC
= V
DD
are operating between V
DD_MIN
and V
DD_MAX
.
: the
are operating between
, the associated GPIOs
Figure 3. V
DDSDMMC connected to external power supply
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DocID027559 Rev 5 9/54
53
Power supplies
1.1.4 Independent DSI supply for STM32F769xx/STM32F779xx devices
AN4661
The DSI (Display Serial Interface) sub-system uses several power supply pins which are independent from the other supply pins:
•
The V
DDDSI
is an independent DSI power supply dedicated for DSI Regulator and MIPI
DPHY. This supply must be connected to global V
DD
.
•
The V
CAPDSI
pin is the output of DSI Regulator (1.2V) which must be connected externally to V
DD12DSI
.
•
The V
DD12DSI
pin is used to supply the MIPI D-PHY, and to supply the clock and data lanes pins. An external capacitor of 2.2 uF must be connected on V
DD12DSI
pin.
•
The V
DDDSI
pin is an isolated supply ground used for DSI sub-system.
If the DSI functionality is not used at all, then:
•
The V
DDDSI
pin must be connected to global V
DD
.
•
The V
CAPDSI
pin must be connected externally to V
DD12DSI
but the external capacitor is no more needed.
•
The V
SSDSI pin must be grounded.
Backup domain description
To retain the content of the RTC backup registers, backup SRAM, and supply the RTC when
V
DD
is turned off, V
BAT
pin can be connected to an optional standby voltage supplied by a battery or by another source.
When the backup domain is supplied by V
BAT
V
DD
(analog switch connected to V
is not present), the following functions are available:
BAT
because
•
PC14 and PC15 can be used as LSE pins only.
• PC13 can be used as tamper pin (TAMP1).
•
PI8 can be used as tamper pin (TAMP2).
Note:
The voltage regulator is always enabled after reset. It works in three different modes depending on the application modes.
•
In Run mode, the regulator supplies full power to the 1.2 V domain (core, memories and digital peripherals).
•
In Stop mode, the regulator supplies low power to the 1.2 V domain, preserving the contents of the registers and SRAM.
•
In Standby mode, the regulator is powered down. The contents of the registers and
SRAM are lost except for those concerned with the standby circuitry and the backup domain.
Depending on the selected package, there are specific pins that should be connected either to V
SS
or V
DD
to activate or deactivate the voltage regulator. Refer to the voltage regulator section in the datasheet for more details.
10/54 DocID027559 Rev 5
AN4661 Power supplies
Note:
Note:
•
V
DD
= 1.7 to 3.6 V: external power supply for I/Os and the internal regulator (when enabled), provided externally through V
V
DD
DD
pins. The V
DD
pins must be connected to
with external decoupling capacitors: one single tantalum or ceramic capacitor
(min. 4.7 μ F) for the package + one 100 nF ceramic capacitor for each V
DD
pin.
•
V
SSA
, V
DDA
= 1.7 to 3.6 V: external analog power supplies for ADC, DAC, Reset blocks, RCs and PLL. V
DDA
and V
SSA
must be connected to V
DD
and V
SS
, respectively.
The V
DDA
pin must be connected to two external decoupling capacitors (100 nF ceramic + 1 μ F tantalum or ceramic).
•
V
DDUSB
can be connected either to V
DD
or an external independent power supply (3.0 to 3.6V) for USB transceivers. For example, when the device is powered at 1.8V, an independent power supply 3.3V can be connected to V
DDUSB
.
The V
DDUSB
pin must be connected to two external decoupling capacitors (100 nF ceramic + 1 μ F tantalum or ceramic).
•
V
BAT
= 1.65 to 3.6 V: power supply for the RTC, the external clock 32 kHz oscillator and backup registers (through power switch) when V
DD
is not present.
The V
BAT
pin can be connected to the external battery (1.65 V < V
BAT
< 3.6 V). If no external battery is used, it is recommended to connect this pin to V
DD external ceramic decoupling capacitor.
with a 100 nF
V
DD
/V
DDA
minimum value of 1.7 V is obtained when the internal reset is OFF (refer to
Section 1.3.5: Internal reset OFF
).
•
The V
REF+
pin can be connected to the V
DDA connected on this pin. In all cases, V
V
DDA
with minimum of 1.7 V.
REF+
external power supply. If a separate, external reference voltage is applied on V
REF+
, a 100 nF and a 1 μ F capacitors must be
must be kept between (V
DDA
-1.2 V) and
•
Additional precautions can be taken to filter analog noise:
– V
DDA
can be connected to V
DD
through a ferrite bead.
– The V
REF+
pin can be connected to V
DDA
through a resistor (typ. 47 Ω ).
•
For the voltage regulator configuration, there is a specific BYPASS_REG pin (not available on all the packages) that should be connected either to V
SS
or V or deactivate the voltage regulator specific.
DD
to activate
Refer to the voltage regulator section of the related device datasheet for more details.
•
When the voltage regulator is enabled, VCAP1 and VCAP2 pins must be connected to
2*2.2 μ F low ESR < 2 Ω ceramic capacitor. In the STM32F7x2Rx devices, only the
VCAP1 pin is available and must be connected to 4.7 µF low ESR between 0.1 Ω and
0.2 Ω ceramic capacitor.
DocID027559 Rev 5 11/54
53
Power supplies AN4661
Figure 4. Power supply overview (STM32F74xxx/STM32F75xxx)
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1. Optional. If a separate, external reference voltage is connected on V
μ F) must be connected.
REF+
, the two capacitors (100 nF and 1
2. V
REF+
is either connected to V
REF+
or to V
DDA
(depending on package).
3. V
REF-
is either connected to V
REF-
or to V
SSA
(depending on package).
4. 19 is the number of V
DD
and V
SS
inputs.
Section 1.3.7: Regulator ON/OFF and internal reset ON/OFF availability
BYPASS_REG and PDR_ON pins.
12/54 DocID027559 Rev 5
AN4661 Power supplies
Figure 5. STM32F769xx/STM32F779xx power supply scheme
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1. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is OFF.
2. The 4.7 µF ceramic capacitor must be connected to one of the V
DD
pin.
3. V
DDA
=V
DD
and V
SSA
=V
SS
.
DocID027559 Rev 5 13/54
53
Power supplies AN4661
Figure 6. STM32F767xx/STM32F777xx power supply scheme
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1. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is OFF.
2. The 4.7 µF ceramic capacitor must be connected to one of the V
DD
pin.
3. V
DDA
=V
DD
and V
SSA
=V
SS
.
14/54 DocID027559 Rev 5
AN4661 Power supplies
Figure 7. STM32F7x2xx power supply scheme
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1. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is OFF.
2. The 4.7 µF ceramic capacitor must be connected to one of the V
DD
pin.
3. V
DDA
=V
DD
and V
SSA
=V
SS
.
DocID027559 Rev 5 15/54
53
Power supplies
16/54
AN4661
Figure 8. STM32F7x3xx power supply scheme
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DDUSB
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06Y9
DocID027559 Rev 5
AN4661
1.3
Power supplies
2. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the voltage regulator is OFF.
3. The 4.7 µF ceramic capacitor must be connected to one of the V
DD
pin.
4. V
DDA
=V
DD
and V
SSA
=V
SS
.
Reset & power supply supervisor
The device has an integrated POR/PDR circuitry that allows a proper operation starting from
1.8 V.
The device remains in reset mode when V
DD
/V
DDA
is below a specified threshold,
VPOR/PDR, without the need for an external reset circuit. For more details concerning the power on/power-down reset threshold, refer to the electrical characteristics of the datasheet.
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Figure 9. Power on reset/power down reset waveform
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1. tRSTTEMPO is approximately 2.6 ms. VPOR/PDR rising edge is 1.74 V (typ.) and VPOR/PDR falling edge is 1.70 V (typ.). Refer to the product datasheets for the actual value.
On the packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On the other packages, the power supply supervisor is always enabled.
The PVD can be used to monitor the V
DD
power supply by comparing it to a threshold selected by the PLS[2:0] bits in the PWR power control register (PWR_CR1).
The PVD is enabled by setting the PVDE bit.
DocID027559 Rev 5 17/54
53
Power supplies AN4661
A PVDO flag is available, in the PWR power control/status register (PWR_CSR1), to indicate if V
DD
is higher or lower than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers.
The PVD output interrupt can be generated when V
DD and/or when V
DD
drops below the PVD threshold
rises above the PVD threshold depending on EXTI line16 rising/falling edge configuration. As an example the service routine could perform emergency shutdown tasks.
Figure 10. PVD threshold
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A system reset sets all the registers to their reset values except the reset flags in the clock controller CSR register and the registers in the backup domain (see
A system reset is generated when one of the following events occurs:
1.
A low level on the NRST pin (external reset).
2. Window watchdog end of count condition (WWDG reset).
3. Independent watchdog end of count condition (IWDG reset).
4. A software reset (Software reset).
5. A low-power management reset.
18/54 DocID027559 Rev 5
AN4661
([WHUQDO
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Power supplies
Figure 11. Reset circuit
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On the packages embedding the PDR_ON pin, the power supply supervisor is enabled by holding PDR_ON high. On the other packages, the power supply supervisor is always enabled.
For more details about the internal reset ON, refer to the datasheets (DS10915, DS10916).
This feature is available only on the packages featuring the PDR_ON pin. The internal power-on reset (POR) / power-down reset (PDR) circuitry is disabled through the PDR_ON pin.
An external power supply supervisor should monitor V
DD the device in reset mode as long as V
DD connected to V
SS
.
and NRST and should maintain
is below a specified threshold. PDR_ON should be
. Refer to
Figure 12: Power supply supervisor interconnection with internal
Figure 12. Power supply supervisor interconnection with internal reset OFF
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Power supplies AN4661
The supply ranges which never go below 1.8V minimum should be better managed by the internal circuitry (no additional component needed, thanks to the fully embedded reset controller).
When the internal reset is OFF, the following integrated features are no more supported:
•
The integrated power-on reset (POR) / power-down reset (PDR) circuitry is disabled.
•
The brownout reset (BOR) circuitry must be disabled.
•
The embedded programmable voltage detector (PVD) is disabled.
•
V
BAT
functionality is no more available and V
BAT
pin should be connected to V
DD
.
All the packages, except for the LQFP64 and the LQFP100, allow to disable the internal reset through the PDR_ON signal when connected to V
SS
.
Figure 13. NRST circuitry timing example
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20/54 DocID027559 Rev 5
AN4661 Power supplies
Refer to
Voltage regulator
section in the datasheet for details
.
•
When BYPASS_REG = V
DD and V
CAP2
, the core power supply should be provided through V
pins connected together.
CAP1
– The two V
CAP capacitors.
ceramic capacitors should be replaced by two 100 nF decoupling
– Since the internal voltage scaling is not managed internally, the external voltage value must be aligned with the targeted maximum frequency.
– When the internal regulator is OFF, there is no more internal monitoring on V12.
An external power supply supervisor should be used to monitor the V12 of the logic power domain (V
CAP
).
PA0 pin should be used for this purpose, and act as power-on reset on V12 power domain.
•
In regulator OFF mode, the following features are no more supported:
– PA0 cannot be used as a GPIO pin since it allows to reset a part of the V12 logic power domain which is not reset by the NRST pin.
– As long as PA0 is kept low, the debug mode cannot be used under power-on reset. As a consequence, PA0 and NRST pins must be managed separately if the debug connection under reset or pre-reset is required.
– The over-drive and under-drive modes are not available.
– The Standby mode is not available.
Figure 14. BYPASS_REG supervisor reset connection
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1. V
CAP2
is not available on all packages. In that case, a single 100 nF decoupling capacitor is connected to
V
CAP1.
DocID027559 Rev 5 21/54
53
Power supplies
1.3.7
AN4661
The following conditions must be respected:
•
V
DD
should always be higher than V domains.
CAP
to avoid a current injection between power
•
If the time for V
CAP
to reach V12 minimum value is smaller than the time for V
DD reach 1.7 V, then PA0 should be kept low to cover both conditions: until V
CAP
V12 minimum value and until V
DD
reaches 1.7 V.
to
reaches
•
Otherwise, if the time for V
CAP
V
DD
to reach V12 minimum value is smaller than the time for
to reach 1.7 V, then PA0 could be asserted low externally.
•
If V
CAP
goes below V12 minimum value and V
DD
is higher than 1.7 V, then PA0 must be asserted low externally.
Regulator ON/OFF and internal reset ON/OFF availability
Table 1. Regulator ON/OFF and internal reset ON/OFF availability
Package Regulator ON Regulator OFF Internal reset ON
Internal reset
OFF
LQFP64
(1)
LQFP100
WLCSP100
(2)
LQFP144,
LQFP208
(3)
LQFP176,
WLCSP143
(4)
,
UFBGA176,
TFBGA216
WLCSP180
Yes
Yes
BYPASS_REG set to V
SS
Yes
BYPASS_REG set to V
DD
Yes
(5)
No
Yes
Yes
PDR_ON set to
V
DD
No
Yes
PDR_ON set to
V
SS
1. Available only on the STM32F7x2xx devices.
2. Available only on the STM32F7x3xx devices.
3. Not available on the STM32F72xxx/73xxx devices.
4. Available only on the STM32F767xx/STM32F777xx devices.
5. Available only on dedicated part numbers. Refer to
ordering information
section of the datasheet.
22/54 DocID027559 Rev 5
AN4661
2
Alternate function mapping to pins
Alternate function mapping to pins
In order to easily explore the peripheral alternate functions mapping to the pins it is recommended to use the STM32CubeMX tool available on
www.st.com
.
Figure 15. STM32CubeMX example screen-shot
DocID027559 Rev 5 23/54
53
Clocks
3
Clocks
AN4661
Three different clock sources can be used to drive the system clock (SYSCLK):
•
HSI oscillator clock.
• HSE oscillator clock.
•
Main PLL (PLL) clock.
The devices have the two following secondary clock sources:
• 32 kHz low-speed internal RC (LSI RC) which drives the independent watchdog and, optionally, the RTC used for Auto-wakeup from the Stop/Standby mode.
•
32.768 kHz low-speed external crystal (LSE crystal) which optionally drives the RTC clock (RTCCLK).
Each clock source can be switched on or off independently when it is not used, to optimize power consumption.
Refer to the RM0385 reference manual for the description of the clock tree.
3.1
3.1.1
HSE OSC clock
The high speed external clock signal (HSE) can be generated from two possible clock sources:
•
•
HSE external crystal/ceramic resonator (see
).
The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize the output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the selected oscillator.
Figure 16. HSE external clock Figure 17. HSE crystal/ceramic resonators
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External user clock (HSE bypass)
In this mode, an external clock source must be provided. The user selects this mode by setting the HSEBYP and HSEON bits in the RCC clock control register (RCC_CR). The external clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the
OSC_IN pin while the OSC_OUT pin should be left HI-Z.
24/54 DocID027559 Rev 5
AN4661 Clocks
The external oscillator frequency ranges from 4 to 26 MHz. The external oscillator has the advantage of producing a very accurate rate on the main clock. The associated hardware
. Using a 25 MHz oscillator frequency is a good choice to
get accurate Ethernet, USB OTG high-speed peripheral, I2S and SAI.
The resonator and the load capacitors have to be connected as close as possible to the oscillator pins in order to minimize the output distortion and startup stabilization time. The load capacitance values must be adjusted according to the selected oscillator.
For CL1 and CL2 it is recommended to use high-quality ceramic capacitors in the 5 pF-to-
25 pF range (typ.), designed for high-frequency applications and selected to meet the requirements of the crystal or resonator. CL1 and CL2, are usually the same value. The crystal manufacturer typically specifies a load capacitance that is the series combination of
CL1 and CL2. The PCB and MCU pin capacitances must be included when sizing CL1 and
CL2 (10 pF can be used as a rough estimate of the combined pin and board capacitance).
The HSERDY flag in the RCC clock control register (RCC_CR) indicates if the high-speed external oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the RCC clock interrupt register
(RCC_CIR).
The HSE crystal can be switched on and off using the HSEON bit in the RCC clock control register (RCC_CR).
The low-speed external clock signal (LSE) can be generated from two possible clock sources:
•
LSE user external clock (see
)
.
•
LSE external crystal/ceramic resonator (see
Figure 18. LSE external clock Figure 19. LSE crystal/ceramic resonators
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Figure 19: LSE crystal/ceramic resonators
:
To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL ≤ 7 pF.
2.
Figure 19: LSE crystal/ceramic resonators
OSC32_IN and OSC32_OUT pins can be used also as GPIO, but it is recommended not to use them as both RTC and GPIO pins in the same application.
The LSE oscillator is switched on and off using the LSEON bit in RCC backup domain control register (RCC_BDCR).
DocID027559 Rev 5 25/54
53
Clocks
3.2.1
3.2.2
AN4661
The LSE oscillator includes new modes and has a configurable drive using the LSEDRV
[1:0] in RCC_BDCR register:
•
00: Low drive.
•
10: Medium low drive.
•
01: Medium high drive.
•
11: High drive.
The LSERDY flag in the RCC backup domain control register (RCC_BDCR) indicates if the
LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released until this bit is set by hardware. An interrupt can be generated if enabled in the RCC clock interrupt register (RCC_CIR).
External clock (LSE bypass)
In this mode, an external clock source must be provided. It must have a frequency up to
1 MHz. The user selects this mode by setting the LSEBYP and LSEON bits in the RCC backup domain control register (RCC_BDCR). The external clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin
External crystal/ceramic resonator (LSE crystal)
The LSE crystal is a 32.768 kHz low-speed external crystal or ceramic resonator. It has the advantage of providing a low-power, but highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions.
The resonator and the load capacitors have to be connected as close as possible to the oscillator pins in order to minimize the output distortion and startup stabilization time. The load capacitance values must be adjusted according to the selected oscillator.
The clock security system can be activated by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped.
•
If a failure is detected on the HSE clock, this oscillator is automatically disabled, a clock failure event is sent to the break inputs of advanced-control timers TIM1 and TIM8, and an interrupt is generated to inform the software about the failure (clock security system interrupt CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex
®
-M7 NMI (non-maskable interrupt) exception vector.
•
If the HSE oscillator is used directly or indirectly as the system clock (indirectly meaning that it is directly used as PLL input clock, and that PLL clock is the system clock) and a failure is detected, then the system clock switches to the HSI oscillator and the HSE oscillator is disabled.
•
If the HSE oscillator clock was the clock source of PLL used as the system clock when the failure occurred, PLL is also disabled. In this case, if the PLLI2S or PLLSAI was enabled, it is also disabled when the HSE fails.
26/54 DocID027559 Rev 5
AN4661 Boot configuration
In the STM32F7 Series, two different boot spaces can be selected through the BOOT pin and the boot base address programmed in the BOOT_ADD0 or BOOT_ADD1 option bytes
Table 2. Boot modes
Boot mode selection
BOOT pin
0
1
Boot address option bytes
Boot space
BOOT_ADD0 [15:0]
– Boot address defined by the user option byte BOOT_ADD0[15:0]
- ST programmed value: Flash on ITCM at 0x0020 0000
BOOT_ADD1 [15:0]
– Boot address defined by the user option byte BOOT_ADD1[15:0]
- ST programmed value: System bootloader at 0x0010 0000
The BOOT_ADD0 and BOOT_ADD1 address option bytes allow to program any boot memory address from 0x0000 0000 to 0x2004 FFFF which include:
• All the Flash memory address space mapped on ITCM or AXIM interface.
•
All the RAM address space: ITCM, DTCM RAMs and SRAMs mapped on AXIM interface.
• The system memory bootloader.
The BOOT_ADD0 / BOOT_ADD1 option bytes can be modified after the reset in order to boot from any other boot address after the next reset.
If the programmed boot memory address is out of the memory mapped area or a reserved area, the default boot fetch address is programmed as follows:
•
Boot address 0: ITCM-FLASH at 0x0020 0000
• Boot address 1: ITCM-RAM at 0x0000 0000
When the Flash level 2 protection is enabled, only boot from the Flash memory (on ITCM or
AXIM interface) or the system bootloader will be available. If the already programmed boot address in the BOOT_ADD0 and/or BOOT_ADD1 option bytes is out of the memory range of the RAM address (on ITCM or AXIM), the default fetch will be forced from the Flash memory on ITCM interface at the address 0x00200000.
DocID027559 Rev 5 27/54
53
Boot configuration
4.2 Boot pin connection
shows
the external connection required to select the boot memory of the
STM32F7 Series.
Figure 20. Boot mode selection implementation example
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System bootloader mode
The embedded bootloader code is located in the system memory. It is programmed by ST during production. It is used to reprogram the Flash memory using one of the following serial interfaces.
shows the supported communication peripherals by the system bootloader.
Table 3. STM32F7 Series bootloader communication peripherals
Bootloader peripherals STM32F7 Series
DFU
USART1
USART3
CAN1
(1)
CAN2
(2)
I2C1
I2C2
USB OTG FS (PA11 / PA12) in device mode
PA9 / PA10
PB10 / PB11 and PC10 / PC11
PB8/PB9
PB5 / PB13
PB6 / PB9
PF0 / PF1
28/54 DocID027559 Rev 5
AN4661 Debug management
Table 3. STM32F7 Series bootloader communication peripherals (continued)
Bootloader peripherals STM32F7 Series
I2C3
SPI1
PA8 / PC9
PA4 / PA5 / PA6 / PA7
SPI2 PI0 / PI1 / PI2 / PI3
SPI4 PE11 / PE12 / PE13 / PE14
1. Available on the STM32F72xxx/73xxx devices.
2. Available on the STM32F7 Series devices except the STM32F72xxx/73xxx devices.
5.1 Introduction
The host/target interface is the hardware equipment that connects the host to the application board. This interface is made of three components: a hardware debug tool, a JTAG or SW connector and a cable connecting the host to the debug tool.
shows the connection of the host to the evaluation board.
Figure 21. Host to board connection
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SWJ debug port (serial wire and JTAG)
The core of the STM32F7 Series integrates the Serial Wire / JTAG Debug Port (SWJ-DP). It is an ARM
®
standard CoreSight debug port that combines a JTAG-DP (5-pin) interface and a SW-DP (2-pin) interface.
•
The JTAG Debug Port (JTAG-DP) provides a 5-pin standard JTAG interface to the
AHP-AP port.
•
The Serial Wire Debug Port (SW-DP) provides a 2-pin (clock + data) interface to the
AHP-AP port.
DocID027559 Rev 5 29/54
53
Debug management AN4661
In the SWJ-DP, the two JTAG pins of the SW-DP are multiplexed with some of the five JTAG pins of the JTAG-DP.
For more details on the SWJ debug port refer to RM0385 SWJ debug port section (serial wire and JTAG).
5.3
5.3.1
5.3.2
Pinout and debug port pins
The STM32F7 Series devices are available in various packages with different numbers of available pins. As a result, some functionality related to the pin availability (TPIU parallel output interface) may differ between the packages.
SWJ debug port pins
Five pins are used as outputs from the STM32F7 Series for the SWJ-DP as alternate functions of general-purpose I/Os. These pins are available on all packages.
SWJ-DP pin name
Type
Table 4. SWJ debug port pins
JTAG debug port SW debug port
Description Type Debug assignment
Pin assignment
JTMS/SWDIO I
JTAG test mode
Selection
IO
Serial wire data input/output
PA13
JTCK/SWCLK
JTDI
JTDO/TRACESWO
NJTRST
I
I
O
I
JTAG test clock
JTAG test data input
JTAG test data output
JTAG test nReset
-
-
I
-
Serial wire clock
-
TRACESWO if async trace is enabled
-
PA14
PA15
PB3
PB4
Flexible SWJ-DP pin assignment
After RESET (SYSRESETn or PORESETn), all the five pins used for the SWJ-DP are assigned as dedicated pins immediately usable by the debugger host (note that the trace outputs are not assigned except if explicitly programmed by the debugger host).
However, the STM32F7 Series devices offer the possibility of disabling some or all of the
SWJ-DP ports and so, of releasing the associated pins for general-purpose IO (GPIO) usage.
30/54 DocID027559 Rev 5
AN4661 Debug management
shows the different possibilities to release some pins.
Table 5. Flexible SWJ-DP assignment
SWJ IO pin assigned
Available debug ports
Full SWJ (JTAG-DP + SW-DP) - reset state
Full SWJ (JTAG-DP + SW-DP) but without
NJTRST
JTAG-DP disabled and SW-DP enabled
JTAG-DP disabled and SW-DP disabled
PA13 /
JTMS /
SWDIO
PA14 /
JTCK /
SWCL
K
X X
PA15 /
JTDI
X
X
X
X
X
X
-
Released
PB3 /
JTDO
PB4 /
NJTRST
X
X
X
-
For more details on how to disable SWJ-DP port pins, please refer to RM0385 I/O pin alternate function multiplexer and mapping section.
Note:
It is necessary to ensure that the JTAG input pins are not floating since they are directly connected to flip-flops to control the debug mode features. A special care must be taken with the SWCLK/TCK pin which is directly connected to the clock of some of these flip-flops.
To avoid any uncontrolled IO levels, the device embeds internal pull-ups and pull-downs on the JTAG input pins:
•
NJTRST: internal pull-up.
•
JTDI: internal pull-up.
•
JTMS/SWDIO: internal pull-up.
•
TCK/SWCLK: internal pull-down.
Once a JTAG IO is released by the user software, the GPIO controller takes control again.
The reset states of the GPIO control registers put the I/Os in the equivalent state:
•
NJTRST: AF input pull-up.
•
JTDI: AF input pull-up.
•
JTMS/SWDIO: AF input pull-up.
•
JTCK/SWCLK: AF input pull-down.
•
JTDO: AF output floating.
The software can then use these I/Os as standard GPIOs.
The JTAG IEEE standard recommends to add pull-ups on TDI, TMS and nTRST but there is no special recommendation for TCK. However, for JTCK, the device needs an integrated pull-down.
Having embedded pull-ups and pull-downs removes the need to add external resistors.
DocID027559 Rev 5 31/54
53
Debug management
5.3.4 SWJ debug port connection with standard JTAG connector
AN4661
shows the connection between the STM32F7 Series and a standard JTAG connector.
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32/54 DocID027559 Rev 5
AN4661
6 Recommendations
6.1
Recommendations
Printed circuit board
For technical reasons, it is best to use a multilayer printed circuit board (PCB) with a separate layer dedicated to the ground (V
SS
) and another dedicated to the V
DD
supply. This provides a good decoupling and a good shielding effect. For many applications, economical reasons prohibit the use of this type of board. In this case, the major requirement is to ensure a good structure for the ground and for the power supply.
A preliminary layout of the PCB must separate the different circuits according to their EMI contribution in order to reduce the cross-coupling on the PCB, that is noisy, high-current circuits, low-voltage circuits, and digital components.
6.3 Ground and power supply (V
SS
,V
DD
)
Every block (noisy, low-level sensitive, digital, etc.) should be grounded individually and all ground returns should be to a single point. Loops must be avoided or have a minimum area.
The power supply should be implemented close to the ground line to minimize the area of the supply loop. This is due to the fact that the supply loop acts as an antenna, and is therefore the main transmitter and receiver of EMI. All component-free PCB areas must be filled with additional grounding to create a kind of shielding (especially when using singlelayer PCBs).
6.4 Decoupling
All the power supply and ground pins must be properly connected to the power supplies.
These connections, including pads, tracks and vias should have as low impedance as possible. This is typically achieved with thick track widths and, preferably, the use of dedicated power supply planes in multilayer PCBs.
In addition, each power supply pair should be decoupled with filtering ceramic capacitors
(100 nF) and one single tantalum or ceramic capacitor (min. 4.7 μ F) connected in parallel.
These capacitors need to be placed as close as possible to, or below, the appropriate pins on the underside of the PCB. Typical values are 10 nF to 100 nF, but the exact values depend on the application needs.
shows the typical layout of such a V
DD
/V
SS
pair.
DocID027559 Rev 5 33/54
53
Recommendations
Figure 23. Typical layout for V
DD
/V
SS
pair
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6.6
When designing an application, the EMC performance can be improved by closely studying:
•
Signals for which a temporary disturbance affects the running process permanently
(the case of interrupts and handshaking strobe signals, and not the case for LED commands). For these signals, a surrounding ground trace, shorter lengths and the absence of noisy and sensitive traces nearby (crosstalk effect) improve the EMC performance. For digital signals, the best possible electrical margin must be reached for the two logical states and slow Schmitt triggers are recommended to eliminate parasitic states.
• Noisy signals (clock, etc.).
•
Sensitive signals (high impedance, etc.).
Unused I/Os and features
All the microcontrollers are designed for a variety of applications and often a particular application does not use 100% of the MCU resources. To increase the EMC performance, unused clocks, counters or I/Os, should not be left free, e.g. I/Os should be set to “0” or “1”
(pull-up or pull-down to the unused I/O pins.) and unused features should be “frozen” or disabled.
34/54 DocID027559 Rev 5
AN4661
6.7
Recommendations
Recommendations for the WLCSP180 package in the
STM32F769Ax/STM32F768Ax devices
These recommendations are required for the WLCSP180 package in the
STM32F769Ax/STM32F768Ax devices:
1.
The NC (not-connected) balls must not be connected to GND nor to VDD.
2. The NC (not-connected) pins are not bounded. They must be configured by software to output push-pull and forced to 0 in the output data register to avoid an extra current consumption in low-power modes.
The list of NC pins is: PI8, PI12, PI13, PI14, PF6, PF7, PF8, PF9, PC2, PC3, PC4,
PC5, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PH6, PH7, PJ12, PJ13, PJ14, PJ15, PG14,
PK3, PK4, PK5, PK6 and PK7.
DocID027559 Rev 5 35/54
53
Reference design AN4661
7.1 Description
The reference design shown in
, is based on the STM32F756NGH6, a highly integrated microcontroller running at 216 MHz, that combines the Cortex
®
-M7 32-bit RISC
CPU core with 1 Mbyte of embedded Flash memory and system SRAM up to 320 Kbytes
(including Data TCM RAM 64 Kbytes), 16 Kbytes of instruction RAM (ITCM-RAM) and 4
Kbytes of backup SRAM.
7.1.1 Clocks
Two clock sources are used for the microcontroller:
•
LSE: X2– 32.768 kHz crystal for the embedded RTC.
•
HSE: X1– 25 MHz crystal.
.
7.1.2 Reset
The reset signal of STM32F74xxx/STM32F75xxx devices is low active and the reset sources include:
• Reset button B1
•
Debugging Tools from JTAG/SWD connector CN15 and ETM trace connector CN12
Section 1.3: Reset & power supply supervisor on page 17 .
Note:
The STM32F74xxx/STM32F75xxx devices can boot from any region from 0x0000 0000 to
0x2004 FFFF.
The boot space is configured by setting BOOT pin and the boot base address programmed in the BOOT_ADD0 and BOOT_ADD1 option bytes.
For more details refer to
Section 4: Boot configuration on page 27
In the Low-power mode (more specially in Standby mode), the boot mode is mandatory to be able to connect to tools (the device should boot from the SRAM).
Section 5: Debug management on page 29
.
Section 1: Power supplies on page 7 .
36/54 DocID027559 Rev 5
AN4661 Reference design
1
2
3
Microcontroller
Capacitor
Capacitor
Table 6. Mandatory components
Reference Quantity
STM32F756NGH6
100 nF
4.7 µF
1
19
1
Comments
TFBGA216 package
Ceramic capacitors
(decoupling capacitors)
Ceramic capacitor
(decoupling capacitor)
Id
1
2
3
4
5
6
7
8
9
10
Table 7. Optional components
Components name
Reference Quantity Comments
Resistor
Resistor
Capacitor
Capacitor
Capacitor
Capacitor
Capacitor
Quartz
Quartz
JTAG connector
10 k Ω
0 Ω
100 nF
1.5 pF
1 μ F
2.2 μ F
20 pF
25 MHz
32.768 kHz
HE10-20
6
2
5
2
3
2
2
1
1
1
Pull-up and pull-down for JTAG, BOOT pin, PDR and bypass regulator
– Used as star connection point between V
DDA
and
V
REF+
– Used as star connection point between V
DD_MCU and V
DDUSB
Ceramic capacitor.
Used for LSE: the value depends on the crystal characteristics.
Used for V
DDA
and V
REF
and V
DDUSB
.
Used for internal regulator when it is on.
Used for HSE: the value depends on the crystal characteristics.
Used for HSE.
Used for LSE.
-
11
Battery
12
Switch
13
Push-button
14
Jumper
15
Ferrite bead
3V
SPDT
B1
3 pins
FCM1608KF
-601T03
1
1
1
2
1
If no external battery is used in the application, it is recommended to connect V
BAT
externally to V
DD
.
Used to select the right boot mode.
Reset button
Used to select V
BAT
source, and BYPASS_REG pin.
Additional decoupling for V
DDA
DocID027559 Rev 5 37/54
53
Reference design
&
Figure 24. STM32F756NGH6 reference schematic
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D
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( &
D
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>
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>
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>
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DocID027559 Rev 5
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AN4661
Pin Name
Table 8. Reference connection for all packages
Reference design
PA13 (JTMS-SWDIO)
PA14 (JTCK-SWCLK)
PA15 (JTDI)
PB3 (JTDO/TRACESWO)
PB4 (NJTRST)
PC14 (PC14-OSC32_IN)
PH1 (PH1-OSC_OUT)
BOOT
NRST
BYPASS_REG
PDR_ON
V
DD
V
DD
V
DD
V
DDUSB
V
DD
V
DD
V
DD
V
DD
V
BAT
V
DDA
V
REF+
V
SSA
V
REF-
V
CAP1
V
CAP2
V
DD
V
DD
V
DD
-
-
-
-
-
27
11
50
75
100
-
19
-
48
73
21
20
-
6
13
94
14
-
90
8
9
12
72
76
77
89
L1
C5
E6
J8
-
-
J5
J6
C1
D7
G1
K10
-
N2
D1
A11
C11
L10
L11
H10
C9
H9
N11
C7
D11
E11
J11
D3
B1
C2
B7
K4
G3
N8
N9
J13
C8
C7
N10
G13
C5
H13
M1
N1
M10
F13
C6
C1
R1
P1
H1
D6
J1
L4
A9
E1
F1
G1
A15
A14
A13
A10
84
121
131
39
17
52
62
72
108
144
95
31
-
71
106
143
6
33
32
24
138
25
-
134
8
9
23
105
109
110
133
49
23
62
72
103
149
159
82
127
172
114
37
-
81
125
171
6
39
38
30
166
31
48
162
9
10
29
124
137
138
161
K5
H5
L8
L9
J11
E9
E8
L10
F11
E7
G11
M1
N1
L11
E11
E5
C1
R1
P1
H1
E6
J1
L5
A9
E1
F1
G1
A15
A14
A13
A10
52
26
73
83
115
171
185
94
150
204
137
40
-
92
148
203
6
42
41
33
197
34
-
193
9
10
32
147
159
160
192
DocID027559 Rev 5 39/54
53
Reference design AN4661
Table 8. Reference connection for all packages (continued)
Pin Name
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
PA0-WKUP
(3)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
74
99
26
10
7
-
49
22
-
-
-
-
-
-
-
-
148
158
-
-
61
71
102
113
90
135
-
-
126
-
-
22
8
7
-
40
-
-
-
-
36
15
91
136
-
-
D8
D7
M8
M9
-
G12
H12
D9
-
-
F12
D5
-
G2
-
N3
D1
D2
-
-
-
-
G3
F3
J12
C9
-
-
-
-
-
-
120
130
-
-
51
61
83
94
107
-
38
16
7
-
-
34
-
-
-
-
-
-
30
-
-
-
-
-
F5
-
-
-
-
-
-
-
H3
-
D2
D2
-
-
H7
H2
K9
D10
-
J7
-
-
-
G7
E10
-
A1
F8
F7
J6
F2
K7
K8
J10
G10
K10
F9
G6
F2
F10
F6
K6
H6
K9
N3
D1
C2
F5
G5
L7
H11
J5
F4
K11
E10
170
184
-
-
72
82
114
136
-
-
-
-
149
202
51
25
8
7
93
43
-
-
59
124
39
15
103
158
125 H10
40/54 DocID027559 Rev 5
AN4661 Reference design
1. PC13, PC14, PC15 and PI8 are supplied through the power switch. Since the switch only sinks a limited amount of current (3 mA), the use of GPIOs PC13 to PC15 and PI8 in output mode is limited:
- The speed should not exceed 2 MHz with a maximum load of 30 pF.
- These I/Os must not be used as a current source (e.g. to drive an LED).
2. 5 V tolerant except when in analog mode or oscillator mode for PC14, PC15, PH0 and PH1.
3. If the device is delivered in an WLCSP143, UFBGA176, LQFP176 or TFBGA216 package, and the
BYPASS_REG pin is set to VDD (Regulator OFF/internal reset ON mode), then PA0-WKUP is used as an internal reset (active low).
DocID027559 Rev 5 41/54
53
Recommended PCB routing guidelines for STM32F7 Series devices
8 Recommended PCB routing guidelines for
STM32F7 Series devices
AN4661
In order to reduce the reflections on high speed signals, it is necessary to match the impedance between the source, sink and transmission lines. The impedance of a signal trace depends on its geometry and its position with respect to any reference planes.
The trace width and spacing between differential pairs for a specific impedance requirement is dependent on the chosen PCB stack-up. As there are limitations in the minimum trace width and spacing which depend on the type of PCB technology and cost requirements, a
PCB stack-up needs to be chosen which allows all the required impedances to be realized.
The minimum configuration that can be used is 4 or 6 layers stack-up. An 8 layers boards may be required for a very dense PCBs that have multiple SDRAM/SRAM/NOR/LCD components.
The following stack-ups are intended as examples which can be used as a starting point for helping in a stack-up evaluation and selection. These stack-up configurations are using a
GND plane adjacent to the power plane to increase the capacitance and reduce the gap between GND and power plane. So high speed signals on top layer will have a solid GND reference plane which helps to reduce the EMC emissions, as going up in number of layers and having a GND reference for each PCB signal layer will improve further the radiated
EMC performance.
Figure 25. Four layer PCB stack-up example
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42/54 DocID027559 Rev 5
AN4661 Recommended PCB routing guidelines for STM32F7 Series devices
Figure 26. Six layer PCB stack-up example
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Use the application note:
Oscillator design guide for STM8S, STM8A and STM32 microcontrollers
(AN2867), for further guidance on how to layout and route crystal oscillator circuits.
An adequate power decoupling for STM32F7 Series is necessary to prevent an excessive
power noise and ground bounce noise. Please refer to
Section 1.2: Power supply scheme
.
shows an example of placing bypass capacitors underneath STM32F7 Series closer to pins and with less vias:
DocID027559 Rev 5 43/54
53
Recommended PCB routing guidelines for STM32F7 Series devices AN4661
Figure 27. Example of bypass cap placed underneath the STM32F7 Series
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•
Place the bypass capacitors as close as possible to the power and ground pins of the
MCU.
• Add the recommended bypass capacitors for as many V
DD
/GND pairs as possible.
•
Connect the bypass capacitor pad to the power and ground plane with a wider, short trace/via to reduce the serie inductance, allow a maximum current flow and reduce the transient voltage drops from the power plane. Which also reduces the possibility of ground bounce.
High speed signal layout
SDMMC bus interface
Interface connectivity
The SD/SDIO MMC card host interface (SDMMC) provides an interface between the APB2 peripheral bus and Multi Media Cards (MMCs), SD memory cards and SDIO cards. The
SDMMC interface is a serial data bus interface, that consists of a clock (CK), command signal (CMD) and 8 data lines (D[0:7]).
44/54 DocID027559 Rev 5
AN4661
Note:
8.4.2
Recommended PCB routing guidelines for STM32F7 Series devices
Interface signal layout guidelines:
•
Reference the plane using GND or PWR (if PWR, add 10nf switching cap between
PWR and GND)
•
Trace the impedance: 50
Ω
± 10%
•
The skew being introduced into the clock system by unequal trace lengths and loads, minimize the board skew, keep the trace lengths equal between the data and clock.
•
The maximum skew between data and clock should be below 250 ps @ 10mm
•
The maximum trace length should be below 120mm. If the signal trace exceeds this trace-length/speed criterion, then a termination should be used
•
The trace capacitance should not exceed 20 pF at 3.3V and 15pF at 1.8V
•
The maximum signal trace inductance should be less than 16nH
•
Use the recommended pull-up resistance for CMD and data signals to prevent bus floating.
•
The mismatch within data bus, data and CK or CK and CMD should be below 10mm.
•
Keep the same number of vias between the data signals
The total capacitance of the SD memory card bus is the sum of the bus master capacitance
C
HOST
, the bus capacitance C
BUS
itself and the capacitance C
CARD
of each card connected to this line. The total bus capacitance is C
L
= C
Host
+ C
Bus
+ N*C
STM32F7 Series, bus is all the signals and Card is SD card.
Card where Host is
Flexible memory controller (FMC) interface
Interface connectivity
The FMC controller and in particular SDRAM memory controller which has many signals, most of them have a similar functionality and work together. The controller I/O signals could be splitted in four groups as follow:
•
An address group which consists of row/column address and bank address
•
A command group which includes the row address strobe (NRAS), the column address strobe (NCAS), and the write enable (SDWE)
•
A control group which includes a chip select bank1 and bank2 (SDNE0/1), a clock enable bank1 and bank2 (SDCKE0/1), and an output byte mask for the write access
(DQM).
•
A data group/lane which contains 8 signals
(a)
(DQM).
: the eight D (D7–D0) and the data mask a.It depends of the used memory: SDRAM with x8 bus widths have only one data group, while x16 and x32 bus-width SDRAM have two and four lanes, respectively.
DocID027559 Rev 5 45/54
53
Recommended PCB routing guidelines for STM32F7 Series devices
8.4.3
AN4661
Interface signal layout guidelines:
•
Reference the plane using GND or PWR (if PWR, add 10nf stitching cap between PWR and GND
•
Trace the impedance: 50
Ω
± 10%
•
The maximum trace length should be below 120mm. If the signal trace exceeds this trace-length/speed criterion, then a termination should be used
•
Reduce the crosstalk, place data tracks on the different layers from the address and control lanes, if possible. However, when the data and address/control tracks coexist on the same layer they must be isolated from each other by at least 5 mm.
•
Match the trace lengths for the data group within ± 10 mm of each other to diminish the skew. Serpentine traces (back and forth traces in an “S” pattern to increase trace length) can be used to match the lengths.
•
Placing the clock (SDCLK) signal on an internal layer, minimizes the noise (EMI).
Route the clock signal at least 3x of the trace away from others signals. Use as less vias as possible to avoid impedance change and reflection. Avoid using serpentine routing.
•
Match the clock traces to the data/address group traces within ±10mm.
•
Match the clock traces to each signal trace in the address and command groups to within ±10mm (with maximum of <= 20mm).
•
Trace the capacitances:
– At 3.3 V keep the trace within 20 pF with overall capacitive loading (including Data,
Address, SDCLK and Control) no more than 30pF.
– At 1.8 V keep the trace within 15 pF with overall capacitive loading (including Data,
Address, SDCLK and Control) no more than 20pF.
Quadrature serial parallel interface (Quad-SPI)
Interface connectivity
The Quad-SPI is a specialized communication interface targeting single, dual or Quad-SPI
FLASH memories. The Quad-SPI interface is a serial data bus interface, that consists of a clock (SCLK), a chip select signal (nCS) and 4 data lines (IO[0:3]).
Interface signal layout guidelines
•
Reference the plane using GND or PWR (if PWR, add 10nf stitching cap between PWR and GND
•
Trace the impedance: 50
Ω
± 10%
•
The maximum trace length should be below 120mm. If the signal trace exceeds this trace-length/speed criterion, then a termination should be used
•
Avoid using multiple signal layers for the data signal routing.
•
Route the clock signal at least 3x of the trace away from other signals. Use as less vias as possible to avoid the impedance change and reflection. Avoid using a serpentine routing.
•
Match the trace lengths for the data group within ± 10 mm of each other to diminish skew. Serpentine traces (back and forth traces in an “S” pattern to increase trace length) can be used to match the lengths.
46/54 DocID027559 Rev 5
AN4661
8.4.4
Recommended PCB routing guidelines for STM32F7 Series devices
•
Avoid using a serpentine routing for the clock signal and as less via(s) as possible for the whole path. a via alters the impedance and adds a reflection to the signal.
Embedded trace macrocell (ETM)
Interface connectivity
The ETM enables the reconstruction of the program execution. The data are traced using the data watchpoint and trace (DWT) component or the instruction trace macrocell (ITM) whereas instructions are traced using the embedded trace macrocell (ETM). The ETM interface is synchronous with the data bus of 4 lines D[0:3] and the clock signal CLK.
Interface signals layout guidelines
• Reference the plane using GND or PWR (if PWR, add 10nf stitching cap between PWR and GND
•
Trace the impedance: 50
Ω
± 10%
• All the data trace should be as short as possible (<=25 mm),
•
Trace the lines which should run on the same layer with a solid ground plane underneath it without a via.
• Trace the clock which should have only point-to-point connection. Any stubs should be avoided.
•
It is strongly recommended also for other (data) lines to be point-to-point only. If any stubs are needed, they should be as short as possible. If longer are required, there should be a possibility to optionally disconnect them (e.g. by jumpers).
8.5.1 BGA 216 0.8 mm pitch design example
Table 9. BGA 216 0.8 mm pitch package information
Package information (mm) Design parameters (mm)
Ball pitch : 0.8
Ball size : 0.4
Number of rows/columns : 15x15
Package solder Pad: SMD
Via size : hole size
∅
= 0.2, pad size: 0.45, plane clearance: 0.65
Trace width : 0.10/0.125
Trace/trace space : 0.10/0.125
BGA land size (Ball pad): ∅ = 0.4, solder mask: 0.5
With 0.8 mm pitch BGA balls, fan-out vias are needed to route the balls to other layers on the PCB. Through-vias are used in this example, which cost less than blind, buried vias. For
four adjacent BGA land pads, it is possible to have only one via as showing in
. The traces are routed of two first row and two first colon without fan-out via. The current pitch size allows to route only one trace between two adjacent BGA land pads.
shows an example of ideal SDRAM signals fan-out vias with power and gnd signals. These signals can be optimized to achieve the routing and length matching in an another layer before connecting to an SDRAM IC.
DocID027559 Rev 5 47/54
53
Recommended PCB routing guidelines for STM32F7 Series devices
Figure 28. BGA 0.8mm pitch example of fan-out
48/54
AN4661
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DocID027559 Rev 5
AN4661
8.5.2
Recommended PCB routing guidelines for STM32F7 Series devices
WLCSP143 0.4 mm pitch design example
Table 10. Wafer level chip scale package information
Package information (mm) Design parameters (mm)
Bump pitch : 0.4
Bump size : 0.25
Number of rows/columns : 13x11
Non-solder mask defined via underbump allowed
Microvia size : hole size
∅
= 0.1, via land: 0.2
Trace width/space : 0.07/0.05 or 0.07/0.07
Bump pad size
∅
= 0.26 max – 0.22 recommended
Solder mask opening bump ∅ =0.3 min (for 0.26 diameter pad)
A better way to route this package and the fan-out signals is to use a through microvia technology. Microvia will route out internal bumps to a buried layers inside the PCB. To achieve this, the WLCSP package pads have to be connected to this internal layer through microvia. In case of four layers PCB, the first layer is WLCSP component, the second layer will be used as a signal layer, the third layer as the power and ground and the bottom layer for a signal layout.
shows an example of the layout for four layers PCB.
DocID027559 Rev 5 49/54
53
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Figure 31. 143-bumps WLCSP, 0.40 mm pitch routing example
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50/54 DocID027559 Rev 5
AN4661
9 Conclusion
Conclusion
This application note should be used as a starting reference for a new design with the
STM32F7 Series devices.
DocID027559 Rev 5 51/54
53
Revision history AN4661
Date
24-Mar-2015
08-Jun-2015
13-Apr-2016
Revision
Table 11. Document revision history
Changes
1
2
3
Initial release.
Added
Section 8: Recommended PCB routing guidelines for
Updated title and the whole document changing
STM32F746xx/STM32F756xx by STM32F74xxx/STM32F75xxx.
Updated Applicable products table adding STM32F745xx RPNs.
Section 1.1.2: Independent USB transceivers supply
to the corresponding datasheet.
Updated
Section 1.3.6: Regulator OFF mode
Updated
Figure 14: BYPASS_REG supervisor reset connection
the whole document changing BOOT0 by BOOT.
Updated
Section 1.1.1: Independent A/D converter supply and reference voltage
.
Updated
Section 1.1.3: Independent SDMMC2 supply for
STM32F767xx/STM32F777xx and STM32F72xxx/STM32F73xxx devices
Updated
Section 1.2: Power supply scheme
Updated
Section 1.3.5: Internal reset OFF
adding a paragraph, modifying
Figure 12: Power supply supervisor interconnection with internal reset OFF
Figure 13: NRST circuitry timing example
.
Updated
MHz.
Updated whole document with STM32F7 Series Root Part Number.
Updated cover page adding reference documents.
Added
Section 1.1.3: Independent SDMMC2 supply for
STM32F767xx/STM32F777xx and STM32F72xxx/STM32F73xxx devices
Added
Section 1.1.4: Independent DSI supply for
STM32F769xx/STM32F779xx devices
Updated
Figure 20: Boot mode selection implementation example
.
Added
Figure 5: STM32F769xx/STM32F779xx power supply scheme
Figure 6: STM32F767xx/STM32F777xx power supply scheme
.
52/54 DocID027559 Rev 5
AN4661 Revision history
Date
09-May-2016
03-Feb-2017
Table 11. Document revision history (continued)
Revision Changes
4
5
Updated
Table 1: Regulator ON/OFF and internal reset ON/OFF availability
adding the WLCSP180 package and notes.
Added
Figure 3: VDDSDMMC connected to external power supply
.
Updated
Section 1.1.4: Independent DSI supply for
STM32F769xx/STM32F779xx devices
SSDSI grounded.
pin must be
Added
Section 6.7: Recommendations for the WLCSP180 package in the STM32F769Ax/STM32F768Ax devices
Updated
Section 1.1.2: Independent USB transceivers supply
Updated
Section 1.2: Power supply scheme
Added
Figure 7: STM32F7x2xx power supply scheme
Added
Figure 8: STM32F7x3xx power supply scheme
Updated
Table 1: Regulator ON/OFF and internal reset ON/OFF availability
adding the LQFP64 and WLCSP100 packages and notes.
Updated
Table 3: STM32F7 Series bootloader communication peripherals
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Key Features
- Power Supply
- Package Selection
- Clock Management
- Reset Control
- Boot Mode Settings
- Debug Management