Transcend 16GB 40-pin PATA SLC Datasheet

T r r r a n s c e n d 4 0 P i i i n I I I D E F l l l a s h M o d u l l l e

T S 1 2 8 M ~ 1 6 G D O M 4 0 V S

With an IDE interface and strong data retention ability,

40-Pin IDE Flash Modules are ideal for use in the harsh environments where Industrial PCs, Set-Top

Boxes, etc. are used.

• RoHS compliant products

• Storage Capacity: 128MB ~ 16GB

• Operating Voltage: 3.3V ±5% or 5V ±10%

• Operating Temperature: 0°C ~ 70°C

• Operating Humidity (Non condensation): 0% to 95%

• Storage Humidity (Non condensation): 0% to 95%

• Endurance: 2,000,000 Program/Erase cycles

• MTBF: 1,000,000 hours

• Durability of Connector: 10,000 times

• Fully compatible with devices and OS that support the

IDE standard (pitch = 2.54mm)

• Built-in ECC function assures high reliability of data transfer

• Supports up to Ultra DMA Mode 4

• Supports PIO Mode 6

• Support Wear-Leveling to extend product life

Side

A

B

C

Millimeters

61.00 ± 0.40

27.10 ± 0.50

7.10 ± 0.20

Inches

2.402 ± 0.016

1.067 ± 0.020

0.280 ± 0.008

Transcend Information Inc.

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Pin

No.

Pin

Name

Pin

No.

Pin Pin

Name No.

Pin

Name

Pin

No.

Pin

Name

01 -RESET 11 HD3 21 DMARQ 31 IREQ

02 GND 12 HD12 22 GND 32 IOIS16B

03 HD7 13 HD2 23 IOWB 33 HA1

04 HD8 14 HD13 24 GND 34 PDIAGB

05 HD6 15 HD1 25 IORB 35 HA0

06 HD9 16 HD14 26 GND 36 HA2

07 HD5 17 HD0 27 IORDY 37 CE1B

08 HD10 18 HD15 28 NC 38 CE2B

09 HD4 19 GND 29 -DMACK 39 DASPB

10 HD11 20 VCC 30 GND 40 GND

The 40-Pin IDE Flash Module offers 2 ways to get input power, either via the small power cord or through

Pin 20 of the IDE connector. If Pin 20 of the IDE connector is defined as NC (No Connect), then the

40-Pin IDE Flash Module must be directly connected to your system’s power supply. If Pin 20 of the IDE connector is defined as VCC, then the 40-Pin IDE

Flash Module can get necessary power without use of the power cord.

Pin Layout

Pin1 Bulge Pin39

Symbol Function

HD0 ~ HD15 Data Bus (Bi-directional)

HA0 ~ HA2 Address Bus (Input)

-RESET Device Reset (Input)

IORB

IOWB

IOIS16B

Device I/O Read (Input)

Device I/O Write (Input)

Transfer Type 8/16 bit (Output)

CE1B, CE2B Chip Select (Input)

PDIAGB Pass Diagnostic (Bi-directional)

DASPB

DMARQ

DMACK-

IREQ

NC

Disk Active/Slave Present

(Bi-directional)

DMA request

DMA acknowledge

Interrupt Request (Output)

No Connection

GND

VCC

Ground

Vcc Power Input

Pin2 Pin40


2

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With 1 pcs of Flash Memory:

With 2 pcs of Flash Memory:


3

Ver 1.3


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Absolute Maximum Rating s

Symbol Parameter

VDD-VSS

Ta

Tst

DC Power Supply

Operating Temperature

Storage Temperature

Min

-0.6

0

-40

Symbol

VDD

VIN

Ta

Parameter

Power supply

Input voltage

Operating Temperature

(Ta=0 o

C to +70 o

Parameter

Supply Voltage

High level output voltage

Low level output voltage

High level input voltage

Symbol

V

CC

V

OH

V

OL

V

IH

V

IL

Min

4.5

V

CC

-0.8

--

4.0

2.92

--

--

Low level input voltage

(Ta=0 o

C to +70 o

Parameter

Supply Voltage

High level output voltage

Low level output voltage

High level input voltage

Low level input voltage

Symbol

V

CC

V

OH

V

OL

V

IH

V

IL

Min

3.135

V

CC

-0.8

--

2.4

2.05

--

--

Max

3.465

--

0.8

--

--

0.6

1.25

Max

5.5

--

0.8

--

--

0.8

1.70

Min

3.0

0

0

Unit

V

V

V

V

V

V

V

Unit

V

V

V

V

V

V

V

Max

+6

+70

+85

Max

5.5

VDD+0.3

+70

Remark

Non-schmitt trigger

Schmitt trigger

1

Non-schmitt trigger

Schmitt trigger

1

Remark

Non-schmitt trigger

Schmitt trigger

1

Non-schmitt trigger

Schmitt trigger

1

Unit

V

°C

°C

Units

V

V

°C


4

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5

Ver 1.3


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True IDE PIO Mode Read/Write Timing

t t

Mode Mode Mode Mode Mode Mode

Item

0 1 2 3 4 5 t

0

Cycle time (min)

1

600 383 240 180 120 100 t

1

Address Valid to -IORD/-IOWR setup (min) 70 t

2

-IORD/-IOWR (min)

1

165

50

125

30

100

30

80

25

70

15

65 t

2

2i

3

-IORD/-IOWR (min) Register (8 bit)

-IORD/-IOWR recovery time (min)

-IOWR data setup (min) t

4

-IOWR data hold (min) t

5

-IORD data setup (min)

290 290 290 80

--

60

30

50

--

45

20

35

--

30

15

20

70

30

10

20

70

25

20

10

20

65

25

20

5

15

Mode

6

80

10

55

55

20

15

5

10 t

6

-IORD data hold (min) t

6Z

-IORD data tristate (max)

2

5

30 t

7

Address valid to IOCS16 assertion (max)

4

90 t

8

Address valid to IOCS16 released (max)

4

60 t

9

-IORD/-IOWR to address valid hold 20

5

30

50

45

15

5

30

40

30

10

5

30

N/A

N/A

10

5

30

N/A

N/A

10

5

20

N/A

N/A

10

5

20

N/A

N/A

10 t

RD

Read Data Valid to IORDY active (min), if

0 0 0 0 0 0 0

IORDY initially low after tA t

A

IORDY Setup time

3 t

B

IORDY Pulse Width (max)

35

1250

35

1250

35

1250

35

1250

35 N/A

5

N/A

5

1250 N/A

5

N/A

5 t

C

IORDY assertion to release (max) 5 5 5 5 5 N/A

5

N/A

5

Notes: All timings are in nanoseconds. The maximum load on -IOCS16 is 1 LSTTL with a 50 pF (40pF below

120nsec Cycle Time) total load. All times are in nanoseconds. Minimum time from -IORDY high to -IORD high is 0 nsec, but minimum -IORD width shall still be met.

(1) t

0

is the minimum total cycle time, t

2

is the minimum command active time, and t

2i

is the minimum command recovery time or command inactive time. The actual cycle time equals the sum of the actual t command active time and the actual command inactive time. The three timing requirements of t0, t

2

2i shall be met. The minimum total cycle time requirement is greater than the sum of t

2

and t

2i

, and

. This means a host implementation can lengthen either or both t

2

or t

2i

to ensure that t

0

is equal to or greater than the value reported in the device’s identify device data.

(2) This parameter specifies the time from the negation edge of -IORD to the time that the data bus is released by the device.

(3) The delay from the activation of -IORD or -IOWR until the state of IORDY is first sampled. If IORDY is inactive then the host shall wait until IORDY is active before the PIO cycle can be completed. If the device is not driving IORDY negated at t

A

after the activation of -IORD or -IOWR, then t not applicable. If the device is driving IORDY negated at the time t

5

shall be met and t

RD

is

A after the activation of -IORD or -IOWR, then t

RD

shall be met and t5 is not applicable.

(4) t

7

and t

8

apply only to modes 0, 1 and 2. For other modes, this signal is not valid.

(5) IORDY is not supported in this mode.


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True IDE PIO Mode Timing Diagram

Figure 1: True IDE PIO Mode Timing Diagram

Notes:

(1) Device address consists of -CS0, -CS1, and A[02::00]

(2) Data consists of D[15::00] (16-bit) or D[07::00] (8 bit)

(3) -IOCS16 is shown for PIO modes 0, 1 and 2. For other modes, this signal is ignored.

(4) The negation of IORDY by the device is used to extend the PIO cycle. The determination of whether the cycle is to be extended is made by the host after t

A

from the assertion of -IORD or -IOWR. The assertion and negation of IORDY is described in the following three cases:

(4-1) Device never negates IORDY: No wait is generated.

(4-2) Device starts to drive IORDY low before t

A generated.

, but causes IORDY to be asserted before t

A

: No wait

(4-3) Device drives IORDY low before t

A

: wait generated. The cycle completes after IORDY is reasserted. For t cycles where a wait is generated and -IORD is asserted, the device shall place read data on D15-D00 for

RD

before causing IORDY to be asserted.


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True IDE Multiword DMA Mode Read/Write Timing Specification

Item

Mode 0

(ns) t

0

Cycle time (min)

1 t

D

-IORD / -IOWR asserted width(min)

1

480

215 t

E

-IORD data access (max) t

F

-IORD data hold (min) t

G

-IORD/-IOWR data setup (min) t

H

-IOWR data hold (min)

150

5

100

20 t

I

DMACK to –IORD/-IOWR setup (min) 0 t

J

-IORD / -IOWR to -DMACK hold (min) 20 t

KR

-IORD negated width (min)

1

50 t

KW

-IOWR negated width (min)

1

215 t

LR

-IORD to DMARQ delay (max) t

LW

-IOWR to DMARQ delay (max) t

M

CS(1:0) valid to –IORD / -IOWR t

N

CS(1:0) hold t

Z

-DMACK

120

40

50

15

20

Mode 1

(ns)

150

80

0

5

50

50

60

5

30

15

40

40

30

10

25

Mode 2

(ns)

120

70

0

5

25

25

50

5

20

10

35

35

25

10

25

Mode 3

(ns)

100

65

0

5

25

25

50

5

15

5

35

35

10

10

25

Mode 4

(ns)

80

55

0

5

20

20

45

5

10

5

35

35

5

10

25

Notes:

(1) t

0

is the minimum total cycle time and t

D

is the minimum command active time, while t

KR

and t

KW

are the minimum command recovery time or command inactive time for input and output cycles respectively. The actual cycle time equals the sum of the actual command active time and the actual command inactive time. The three timing requirements of t

0

, t

D

, t

KR

, and t

KW

shall be met. The minimum total cycle time requirement is greater than the sum of t

D

and t

KR

or t

KW

.for input and output cycles respectively. This means a host implementation can lengthen either or both of t

D

and either of t

KR

, and t

KW

as needed to ensure that t

0

is equal to or greater than the value reported in the device’s identify device data.


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True IDE Multiword DMA Mode Read/Write Timing Diagram

Figure 2: True IDE Multiword DMA Mode Read/Write Timing Diagram

Notes:

(1) If the Card cannot sustain continuous, minimum cycle time DMA transfers, it may negate DMARQ within the time specified from the start of a DMA transfer cycle to suspend the DMA transfers in progress and reassert the signal at a later time to continue the DMA operation.

(2) This signal may be negated by the host to suspend the DMA transfer in progress.


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Ultra DMA Mode Read/Write Timing Specification

Ultra DMA is an optional data transfer protocol used with the READ DMA, and WRITE DMA, commands. When this protocol is enabled, the Ultra DMA protocol shall be used instead of the Multiword

DMA protocol when these commands are issued by the host. This protocol applies to the Ultra DMA data burst only. When this protocol is used there are no changes to other elements of the ATA protocol.

UDMA Signal

DMARQ

DMACK

STOP

HDMARDY(R)

HSTROBE(W)

DDMARDY(W)

DSTROBE(R)

DATA

ADDRESS

CSEL

INTRQ

Card Select

Type

Output

Input

Input

Input

Output

Bidir

Input input

Output

Input

TRUE IDE MODE

UDMA

DMARQ

-DMACK

STOP

1

-HDMARDY

1,2

HSTROBE(W)

1,3,4

-DDMARDY(W)

1,3

DSTROBE(R)

1,2,4

D[15:00]

A[02:00]

5

-CSEL

INTRQ

-CS0

-CS1

Notes: 1) The UDMA interpretation of this signal is valid only during an Ultra DMA data burst.

2) The UDMA interpretation of this signal is valid only during and Ultra DMA data burst during a DMA Read command.

3) The UDMA interpretation of this signal is valid only during an Ultra DMA data burst during a DMA Write command.

4) The HSTROBE and DSTROBE signals are active on both the rising and the falling edge.

5) Address lines 03 through 10 are not used in True IDE mode.

Several signal lines are redefined to provide different functions during an Ultra DMA data burst.

These lines assume their UDMA definitions when:

1. an Ultra DMA mode is selected, and

2. a host issues a READ DMA, or a WRITE DMA command requiring data transfer, and

3. the device asserts (-)DMARQ, and

4. the host asserts (-)DMACK.

These signal lines revert back to the definitions used for non-Ultra DMA transfers upon the negation of -DMACK by the host at the termination of an Ultra DMA data burst.

With the Ultra DMA protocol, the STROBE signal that latches data from D[15:00] is generated by the


10

Ver 1.3


T S 1 2 8 M ~ 1 6 G D O M 4 0 V S same agent (either host or device) that drives the data onto the bus. Ownership of D[15:00] and this data strobe signal are given either to the device during an Ultra DMA data-in burst or to the host for an Ultra

DMA data-out burst.

During an Ultra DMA data burst a sender shall always drive data onto the bus, and, after a sufficient time to allow for propagation delay, cable settling, and setup time, the sender shall generate a STROBE edge to latch the data. Both edges of STROBE are used for data transfers so that the frequency of

STROBE is limited to the same frequency as the data.

Words in the IDENTIFY DEVICE data indicate support of the Ultra DMA feature and the Ultra DMA modes the device is capable of supporting. The Set transfer mode subcommand in the SET FEATURES command shall be used by a host to select the Ultra DMA mode at which the system operates. The Ultra

DMA mode selected by a host shall be less than or equal to the fastest mode of which the device is capable. Only one Ultra DMA mode shall be selected at any given time. All timing requirements for a selected Ultra DMA mode shall be satisfied. Devices supporting any Ultra DMA mode shall also support all slower Ultra DMA modes.

An Ultra DMA capable device shall retain the previously selected Ultra DMA mode after executing a software reset sequence or the sequence caused by receipt of a DEVICE RESET command if a SET

FEATURES disable reverting to defaults command has been issued. The device may revert to a

Multiword DMA mode if a SET FEATURES enable reverting to default has been issued. An Ultra DMA capable device shall clear any previously selected Ultra DMA mode and revert to the default non-Ultra

DMA modes after executing a power-on or hardware reset.

Both the host and device perform a CRC function during an Ultra DMA data burst. At the end of an

Ultra DMA data burst the host sends its CRC data to the device. The device compares its CRC data to the data sent from the host. If the two values do not match, the device reports an error in the error register. If an error occurs during one or more Ultra DMA data bursts for any one command, the device shall report the first error that occurred. If the device detects that a CRC error has occurred before data transfer for the command is complete, the device may complete the transfer and report the error or abort the command and report the error.

NOTE

− If a data transfer is terminated before completion, the assertion of INTRQ should be passed through to the host software driver regardless of whether all data requested by the command has been transferred.


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Ultra DMA Data Burst Timing Requirements

t

Name

2CYCTYP t

CYC

UDMA Mode 0 UDMA Mode 1 UDMA Mode 2 UDMA Mode 3

Min

240

112

Max Min

160

73

Max Min

120

54

Max Min

90

39

Max

UDMA Mode 4

Min Max

60

25

Measure location

(See Note 2)

Sender

Note 3 t

2CYC t

DS t

DH t

DVS t

DVH t

CS t

CH t

CVS t

CVH t

ZFS t

DZFS t

FS t

LI t

MLI t

UI t

AZ t

ZAH t

ZAD t

ENV t

RFS

230

15.0

5.0

70.0

6.2

15.0

5.0

70.0

6.2

0

70.0

0

20

0

20

0

20

230

150

10

70

75

153

10.0

5.0

48.0

6.2

10.0

5.0

48.0

6.2

0

48.0

0

20

0

20

0

20

200

150

10

70

70

115

7.0

5.0

31.0

6.2

7.0

5.0

31.0

6.2

0

31.0

0

20

0

20

0

20

170

150

10

70

60

86

7.0

5.0

20.0

6.2

7.0

5.0

20.0

6.2

0

20.0

0

20

0

20

0

20

130

100

10

55

60

57

5.0

5.0

6.7

6.2

5.0

5.0

6.7

6.2

0

6.7

0

20

0

20

0

20

120 Device

100 Note 4

10

55

60

Sender

Recipient

Recipient

Sender

Sender

Device

Device

Host

Host

Device

Sender

Host

Host

Note 5

Host

Device

Host

Sender t

RP t

IORDYZ t

ZIORDY t

ACK t

SS

160

0

20

50

20

125

0

20

50

20

100

0

20

50

20

100

0

20

50

20

100

0

20

50

20

Recipient

Device

Device

Host

Sender

Notes: All Timings in ns

(1) All timing measurement switching points (low to high and high to low) shall be taken at 1.5 V.

(2) All signal transitions for a timing parameter shall be measured at the connector specified in the measurement location column. For example, in the case of t

RFS

, both STROBE and -DMARDY transitions are measured at the sender connector.

(3) The parameter t

CYC

shall be measured at the recipient’s connector farthest from the sender.

(4) The parameter t

LI shall be measured at the connector of the sender or recipient that is responding to an incoming transition from the recipient or sender respectively. Both the incoming signal and the outgoing response shall be measured at the same connector.

(5) The parameter t

AZ

shall be measured at the connector of the sender or recipient that is driving the bus but must release the bus to allow for a bus turnaround.

(6) See Page 14 the AC Timing requirements in Ultra DMA AC Signal Requirements.


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Ultra DMA Data Burst Timing Descriptions

Name Comment t

2CYCTYP

Typical sustained average two cycle time t

CYC

Cycle time allowing for asymmetry and clock variations (from STROBE edge to STROBE edge) t

2CYC

Two cycle time allowing for clock variations (from rising edge to next rising edge or from falling edge to next falling edge of STROBE)

Notes t

DS

Data setup time at recipient (from data valid until STROBE edge) t

DH

Data hold time at recipient (from STROBE edge until data may become invalid) t

DVS

Data valid setup time at sender (from data valid until STROBE edge) t

DVH

Data valid hold time at sender (from STROBE edge until data may become invalid) t

CS

CRC word setup time at device t

CH

CRC word hold time device t

CVS

CRC word valid setup time at host (from CRC valid until -DMACK negation) t

CVH

CRC word valid hold time at sender (from -DMACK negation until CRC may become invalid)

2,

2,

3

3

2

2

3

3 t

ZFS

Time from STROBE output released-to-driving until the first transition of critical timing. t

DZFS

Time from data output released-to-driving until the first transition of critical timing. t

FS

First STROBE time (for device to first negate DSTROBE from STOP during a data in burst) t

LI

Limited interlock time 1 t

MLI

Interlock time with minimum t

UI

Unlimited interlock time t

AZ

Maximum time allowed for output drivers to release (from asserted or negated)

1

1 t t

ZAH

Minimum delay time required for output

ZAD drivers to assert or negate (from released) t

ENV

Envelope time (from -DMACK to STOP and -HDMARDY during data in burst initiation and from DMACK to STOP during data out burst initiation) t

RFS

Ready-to-final-STROBE time (no STROBE edges shall be sent this long after negation of

-DMARDY) t

RP

Ready-to-pause time (that recipient shall wait to pause after negating -DMARDY) t

IORDYZ

Maximum time before releasing IORDY t

ZIORDY

Minimum time before driving IORDY t

ACK

Setup and hold times for -DMACK (before assertion or negation) t

SS

Time from STROBE edge to negation of DMARQ or assertion of STOP (when sender terminates a burst)

4,

Notes:

(1) The parameters t

UI

, t

MLI

(in Page 19: Ultra DMA Data-In Burst Device Termination Timing and Page 20: Ultra DMA Data-In

Burst Host Termination Timing), and t

LI

indicate sender-to-recipient or recipient-to-sender interlocks,i.e., one agent (either sender or recipient) is waiting for the other agent to respond with a signal before proceeding.t

UI

is an unlimited interlock that has no maximum time value. t

ML

I is a limited time-out that has a defined minimum. t

LI

is a limited time-out that has a defined maximum.

(2) 80-conductor cabling (see see ATA specification :Annex A)) shall be required in order to meet setup (t

DS

, t

CS

) and hold (t

DH

, t

CH

) times in modes greater than 2.

(3) Timing for t

DVS

, t

DVH

, t

CVS

and t

CVH

shall be met for lumped capacitive loads of 15 and 40 pF at the connector where the

Data and STROBE signals have the same capacitive load value. Due to reflections on the cable, these timing measurements are not valid in a normally functioning system.

(4) For all timing modes the parameter t

ZIORDY

may be greater than t

ENV

due to the fact that the host has a pull-up on IORDY-


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Ultra DMA Sender and Recipient IC Timing Requirements

UDMA Mode 0 (ns) UDMA Mode 1 (ns) UDMA Mode 2 (ns) UDMA Mode 3 (ns) UDMA Mode 4 (ns)

Name

Min Max Min Max Min Max Min Max Min Max t

DSIC t

DHIC t

DVSIC t

DVHIC

14.7

4.8

72.9

9.0

9.7

4.8

50.9

9.0

6.8

4.8

33.9

9.0

6.8

4.8

22.6

9.0

4.8

4.8

9.5

9.0 t

DSIC

Recipient IC data setup time (from data valid until STROBE edge) (see note 2) t

DHIC

Recipient IC data hold time (from STROBE edge until data may become invalid) (see note 2) t

DVSIC

Sender IC data valid setup time (from data valid until STROBE edge) (see note 3) t

DVHIC

Sender IC data valid hold time (from STROBE edge until data may become invalid) (see note 3)

Notes:

(1) All timing measurement switching points(low to high and high to low) shall be taken at 1.5 V.

(2) The correct data value shall be captured by the recipient given input data with a slew rate of 0.4 V/ns rising and falling and the input STROBE with a slew rate of 0.4 V/ns rising and falling at t

DSIC

and t

DHIC

timing (as measured through 1.5 V).

(3) The parameters t

DVSIC

and t

DVHIC

shall be met for lumped capacitive loads of 15 and 40 pF at the IC where all signals have the same capacitive load value. Noise that may couple onto the output signals from external sources has not been included in these values.

Ultra DMA AC Signal Requirements

Name

S

RISE

S

FALL

Comment

Rising Edge Slew Rate for any signal

Falling Edge Slew Rate for any signal

Min[V/ns] Max [V/ns]

1.25

1.25

Note

1

1

Note:

(1) The sender shall be tested while driving an 18 inch long, 80 conductor cable with PVC insulation material. The signal under test shall be cut at a test point so that it has not trace, cable or recipient loading after the test point. All other signals should remain connected through to the recipient. The test point may be located at any point between the sender’s series termination resistor and one half inch or less of conductor exiting the connector. If the test point is on a cable conductor rather than the PCB, an adjacent ground conductor shall also be cut within one half inch of the connector.

The test load and test points should then be soldered directly to the exposed source side connectors. The test loads consist of a 15 pF or a 40 pF, 5%, 0.08 inch by 0.05 inch surface mount or smaller size capacitor from the test point to ground. Slew rates shall be met for both capacitor values.

Measurements shall be taken at the test point using a <1 pF, >100 Kohm, 1 Ghz or faster probe and a 500

MHz or faster oscilloscope. The average rate shall be measured from 20% to 80% of the settled VOH level with data transitions at least 120 nsec apart. The settled VOH level shall be measured as the average output


14

Ver 1.3


T S 1 2 8 M ~ 1 6 G D O M 4 0 V S high level under the defined testing conditions from 100 nsec after 80% of a rising edge until 20% of the subsequent falling edge.


15

Ver 1.3


T S 1 2 8 M ~ 1 6 G D O M 4 0 V S

Initiating an Ultra DMA Data-In Burst

(a) An Ultra DMA Data-In burst is initiated by following the steps lettered below. The timing diagram is shown in below: Ultra DMA Data-In Burst Initiation Timing. The associated timing parameters are specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra

DMA Data Burst Timing Descriptions.

(b) The following steps shall occur in the order they are listed unless otherwise specifically allowed:

(c) The host shall keep -DMACK in the negated state before an Ultra DMA data burst is initiated.

(d) The device shall assert DMARQ to initiate an Ultra DMA data burst. After assertion of DMARQ the device shall not negate DMARQ until after the first negation of DSTROBE.

(e) Steps (c), (d), and (e) may occur in any order or at the same time. The host shall assert STOP.

(f) The host shall negate -HDMARDY.

(g) In True IDE mode, the host shall not assert -CS0, -CS1 and A[02:00].

(h) Steps (c), (d), and (e) shall have occurred at least t

ACK

before the host asserts -DMACK. The host shall keep -DMACK asserted until the end of an Ultra DMA data burst.

(i) The host shall release D[15:00] within t

AZ

after asserting -DMACK.

(j) The device may assert DSTROBE t

ZIORDY

after the host has asserted -DMACK. While operating in True

IDE mode, once the device has driven DSTROBE, the device shall not release DSTROBE until after the host has negated -DMACK at the end of an Ultra DMA data burst.

(k) The host shall negate STOP and assert -HDMARDY within t

ENV

after asserting -DMACK. After negating STOP and asserting -HDMARDY, the host shall not change the state of either signal until after receiving the first transition of DSTROBE from the device (i.e., after the first data word has been received).

(l) The device shall drive D[15:00] no sooner than t

ZAD

after the host has asserted -DMACK, negated

STOP, and asserted -HDMARDY.

(m) The device shall drive the first word of the data transfer onto D[15:00]. This step may occur when the device first drives D[15:00] in step (j).

(n) To transfer the first word of data the device shall negate DSTROBE within t

FS

after the host has negated STOP and asserted -HDMARDY. The device shall negate DSTROBE no sooner than t

DVS after driving the first word of data onto D[15:00].


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ALL WAVEFORMS IN THIS DIAGRAM ARE SHOWN WITH THE ASSERTED STATE HIGH.

NEGATIVE TRUE SIGNALS APPEAR INVERTED ON THE BUS RELATIVE TO THE DIAGRAM.

Notes:

The definitions for the IORDY:-DDMARDY:DSTROBE, -IORD: -HDMARDY:HSTROBE, and -IOWR:STOP signal lines are not in effect until DMARQ and -DMACK are asserted. A[02:00], -CS0 & -CS1 are True IDE mode signal definitions.


17

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Sustaining an Ultra DMA Data-In Burst

An Ultra DMA Data-In burst is sustained by following the steps lettered below. The timing diagram is shown in below: Sustained Ultra DMA Data-In Burst Timing. The timing parameters are specified in

Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra DMA Data

Burst Timing Descriptions.

The following steps shall occur in the order they are listed unless otherwise specifically allowed: a) The device shall drive a data word onto D[15:00]. b) The device shall generate a DSTROBE edge to latch the new word no sooner than t

DVS after changing the state of D[15:00]. The device shall generate a DSTROBE edge no more frequently than t

CYC

for the selected Ultra DMA mode. The device shall not generate two rising or two falling DSTROBE edges more frequently than 2t cyc

for the selected Ultra DMA mode. c) The device shall not change the state of D[15:00] until at least t

DVH

after generating a DSTROBE edge to latch the data. d) The device shall repeat steps (a), (b), and (c) until the data transfer is complete or an Ultra DMA data burst is paused, whichever occurs first.

Notes: D[15:00] and DSTROBE signals are shown at both the host and the device to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device.


18

Ver 1.3


T S 1 2 8 M ~ 1 6 G D O M

Host Pausing an Ultra DMA Data-In Burst

4 0 V S

The host pauses a Data-In burst by following the steps lettered below. A timing diagram is shown in below: Ultra DMA Data-In Burst Host Pause Timing. The timing parameters are specified in Page 12:

Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra DMA Data Burst Timing

Descriptions.

The following steps shall occur in the order they are listed unless otherwise specifically allowed:

(a) The host shall not pause an Ultra DMA data burst until at least one data word of an Ultra DMA data burst has been transferred.

(b) The host shall pause an Ultra DMA data burst by negating -HDMARDY.

(c) The device shall stop generating DSTROBE edges within t

RFS

of the host negating -HDMARDY.

(d) While operating in Ultra DMA modes 2, 1, or 0 the host shall be prepared to receive zero, one or two additional data words after negating -HDMARDY. While operating in Ultra DMA modes 4 or 3 the host shall be prepared to receive zero, one, two or three additional data words. The additional data words are a result of cable round trip delay and t

RFS

timing for the device.

(e) The host shall resume an Ultra DMA data burst by asserting -HDMARDY.



Notes:

(1) The host may assert STOP to request termination of the Ultra DMA data burst no sooner than t

RP

after

-HDMARDY is negated.

(2) After negating -HDMARDY, the host may receive zero, one, two, or three more data words from the device.

(3) The bus polarity of the (-) DMARQ and (-)DMACK signals is dependent on the active interface mode.


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Device Terminating an Ultra DMA Data-In Burst

The device terminates an Ultra DMA Data-In burst by following the steps lettered below. The timing diagram is shown in below: Ultra DMA Data-In Burst Device Termination Timing. The timing parameters are specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra



(a) The device shall not pause an Ultra DMA data burst until at least one data word of an Ultra DMA data burst has been transferred.

(b) The device shall pause an Ultra DMA data burst by not generating DSTROBE edges.

(c) NOTE

− The host shall not immediately assert STOP to initiate Ultra DMA data burst termination when the device stops generating STROBE edges. If the device does not negate DMARQ, in order to initiate Ultra DMA data burst termination, the host shall negate -HDMARDY and wait t

RP asserting STOP.

before

(d) The device shall resume an Ultra DMA data burst by generating a DSTROBE edge.



Notes: The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. A[02:00], -CS0 & -CS1 are True IDE mode signal definitions.


20

Ver 1.3


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Host Terminating an Ultra DMA Data-In Burst

The host terminates an Ultra DMA Data-In burst by following the steps lettered below. The timing diagram is shown in below: Ultra DMA Data-In Burst Host Termination Timing. The timing parameters are specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra



(a) The host shall not initiate Ultra DMA data burst termination until at least one data word of an Ultra

DMA data burst has been transferred.

(b) The host shall initiate Ultra DMA data burst termination by negating -HDMARDY. The host shall continue to negate -HDMARDY until the Ultra DMA data burst is terminated.

(c) The device shall stop generating DSTROBE edges within t

RFS

of the host negating -HDMARDY

(d) While operating in Ultra DMA modes 2, 1, or 0 the host shall be prepared to receive zero, one or two additional data words after negating -HDMARDY. While operating in Ultra DMA modes 4 or 3 the host shall be prepared to receive zero, one, two or three additional data words. The additional data words are a result of cable round trip delay and t

RFS


(e) The host shall assert STOP no sooner than t

RP

after negating -HDMARDY. The host shall not negate

STOP again until after the Ultra DMA data burst is terminated.

(f) The device shall negate DMARQ within t

LI

after the host has asserted STOP. The device shall not assert DMARQ again until after the Ultra DMA data burst is terminated.

(g) If DSTROBE is negated, the device shall assert DSTROBE within t

LI

after the host has asserted STOP.

No data shall be transferred during this assertion. The host shall ignore this transition on DSTROBE.

DSTROBE shall remain asserted until the Ultra DMA data burst is terminated.

(h) The device shall release D[15:00] no later than t

AZ

after negating DMARQ.

(i) The host shall drive D[15:00] no sooner than t

ZAH

after the device has negated DMARQ. For this step, the host may first drive D[15:00] with the result of its CRC calculation (see ATA specification Ultra DMA

CRC Calculation).

(j) If the host has not placed the result of its CRC calculation on D[15:00] since first driving D[15:00] during (9), the host shall place the result of its CRC calculation on D[15:00] (see ATA specification Ultra

DMA CRC Calculation).

(k) The host shall negate -DMACK no sooner than t

MLI

after the device has asserted DSTROBE and negated DMARQ and the host has asserted STOP and negated -HDMARDY, and no sooner than t

DVS after the host places the result of its CRC calculation on D[15:00].

(l) The device shall latch the host’s CRC data from D[15:00] on the negating edge of -DMACK.

(m) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA data burst for any one command, at the end of the command, the device shall report the first error that occurred (see ATA specification Ultra DMA CRC Calculation)

(n) While operating in True IDE mode, the device shall release DSTROBE within t negates -DMACK.

IORDYZ

after the host

(o) The host shall neither negate STOP nor assert -HDMARDY until at least t

ACK negated -DMACK.

after the host has


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T S 1 2 8 M ~ 1 6 G D O M 4 0 V S

(p) In True IDE mode, the host shall not assert -IORD, -CS0, -CS1, nor A[02:00] until at least t

ACK negating DMACK.

after



Notes: The definitions for the STOP, HDMARDY, and DSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. A[02:00], -CS0 & -CS1 are True IDE mode signal definitions.


22

Ver 1.3


T S 1 2 8 M ~ 1 6 G D O M 4 0 V S

Initiating an Ultra DMA Data-Out Burst

An Ultra DMA Data-out burst is initiated by following the steps lettered below. The timing diagram is shown in below: Ultra DMA Data-Out Burst Initiation Timing. The timing parameters are specified in Page

12: Ultra DMA Data Burst Timing Requirements and are described in Page 13:Ultra DMA Data Burst

Timing Descriptions.


(a) The host shall keep -DMACK in the negated state before an Ultra DMA data burst is initiated.

(b) The device shall assert DMARQ to initiate an Ultra DMA data burst.

(c) Steps (c), (d), and (e) may occur in any order or at the same time. The host shall assert STOP.

(d) The host shall assert HSTROBE.

(e) In True IDE mode, the host shall not assert -CS0, -CS1, nor A[02:00].

(f) Steps (c), (d), and (e) shall have occurred at least t

ACK

before the host asserts -DMACK.The host shall keep -DMACK asserted until the end of an Ultra DMA data burst.

(g) The device may negate -DDMARDY t

ZIORDY

after the host has asserted -DMACK. While operating in

True IDE mode, once the device has negated -DDMARDY, the device shall not release -DDMARDY until after the host has negated DMACK at the end of an Ultra DMA data burst.

(h) The host shall negate STOP within t

ENV

after asserting -DMACK. The host shall not assert STOP until after the first negation of HSTROBE.

(i) The device shall assert -DDMARDY within t

LI after the host has negated STOP. After asserting

DMARQ and -DDMARDY the device shall not negate either signal until after the first negation of

HSTROBE by the host.

(j) The host shall drive the first word of the data transfer onto D[15:00]. This step may occur any time during Ultra DMA data burst initiation.

(k) To transfer the first word of data: the host shall negate HSTROBE no sooner than t

UI

after the device has asserted -DDMARDY. The host shall negate HSTROBE no sooner than t

DVS

after the driving the first word of data onto D[15:00].


23

Ver 1.3


T S 1 2 8 M ~ 1 6 G D O M 4 0 V S



Note: The definitions for the STOP, DDMARDY, and HSTROBE signal lines are not in effect until DMARQ and

DMACK are asserted. A[02:00], -CS0 & -CS1 are True IDE mode signal definitions.


24

Ver 1.3


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Sustaining an Ultra DMA Data-Out Burst

An Ultra DMA Data-Out burst is sustained by following the steps lettered below. The timing diagram is shown in below: Sustained Ultra DMA Data-Out Burst Timing. The associated timing parameters are specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra



(a) The host shall drive a data word onto D[15:00].

(b) The host shall generate an HSTROBE edge to latch the new word no sooner than t

DVS

after changing the state of D[15:00]. The host shall generate an HSTROBE edge no more frequently than t for the

CYC selected Ultra DMA mode. The host shall not generate two rising or falling HSTROBE edges more frequently than 2t cyc

for the selected Ultra DMA mode.

(c) The host shall not change the state of D[15:00] until at least t

DVH to latch the data.

after generating an HSTROBE edge

(d) The host shall repeat steps (a), (b), and (c) until the data transfer is complete or an Ultra DMA data burst is paused, whichever occurs first.

Note: Data (D[15:00]) and HSTROBE signals are shown at both the device and the host to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host.


25

Ver 1.3


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Device Pausing an Ultra DMA Data-Out Burst

The device pauses an Ultra DMA Data-Out burst by following the steps lettered below. The timing diagram is shown in below: Ultra DMA Data-Out Burst Device Pause Timing. The timing parameters are specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra



(a) The device shall not pause an Ultra DMA data burst until at least one data word of an Ultra DMA data burst has been transferred.

(b) The device shall pause an Ultra DMA data burst by negating -DDMARDY.

(c) The host shall stop generating HSTROBE edges within t

RFS

of the device negating -DDMARDY.

(d) While operating in Ultra DMA modes 2, 1, or 0 the device shall be prepared to receive zero, one or two additional data words after negating -HDMARDY. While operating in Ultra DMA modes 4 or 3 the device shall be prepared to receive zero, one, two or three additional data words. The additional data words are a result of cable round trip delay and t

RFS


(e) The device shall resume an Ultra DMA data burst by asserting -DDMARDY.



Notes:

(1) The device may negate DMARQ to request termination of the Ultra DMA data burst no sooner than t

RP

after -DDMARDY is negated.

(2) After negating -DDMARDY, the device may receive zero, one, two, or three more data words from the host.


26

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Device Terminating an Ultra DMA Data-Out Burst

The device terminates an Ultra DMA Data-Out burst by following the steps lettered below. The timing diagram for the operation is shown in below: Ultra DMA Data-Out Burst Device Termination Timing. The timing parameters are specified in Page 12: Ultra DMA Data Burst Timing Requirements and are described in Page 13: Ultra DMA Data Burst Timing Descriptions.


(a) The device shall not initiate Ultra DMA data burst termination until at least one data word of an Ultra

DMA data burst has been transferred.

(b) The device shall initiate Ultra DMA data burst termination by negating -DDMARDY.

(c) The host shall stop generating an HSTROBE edges within t

RFS

of the device negating -DDMARDY.

(d) While operating in Ultra DMA modes 2, 1, or 0 the device shall be prepared to receive zero, one or two additional data words after negating -HDMARDY. While operating in Ultra DMA modes 4 or 3 the device shall be prepared to receive zero, one, two or three additional data words. The additional data words are a result of cable round trip delay and t

RFS


(e) The device shall negate DMARQ no sooner than t

RP

after negating -DDMARDY. The device shall not assert DMARQ again until after the Ultra DMA data burst is terminated.

(f) The host shall assert STOP within t

LI

after the device has negated DMARQ. The host shall not negate

STOP again until after the Ultra DMA data burst is terminated.

(g) If HSTROBE is negated, the host shall assert HSTROBE within t

LI

after the device has negated

DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition of

HSTROBE. HSTROBE shall remain asserted until the Ultra DMA data burst is terminated.

(h) The host shall place the result of its CRC calculation on D[15:00] (see ATA specification Ultra DMA

CRC Calculation).

(i) The host shall negate -DMACK no sooner than t

MLI

after the host has asserted HSTROBE and STOP and the device has negated DMARQ and -DDMARDY, and no sooner than t

DVS

after placing the result of its CRC calculation on D[15:00].

(j) The device shall latch the host’s CRC data from D[15:00] on the negating edge of -DMACK.

(k) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA data bursts for any one command, the device shall report the first error that occurred (see ATA specification Ultra DMA CRC

Calculation).

(l) While operating in True IDE mode, the device shall release DSTROBE within t

IORDYZ

after the host negates -DMACK.

(m) The host shall not negate STOP nor assert –HDMARDY until at least t

ACK

after negating -DMACK.

(n) In True IDE mode, the host shall not assert -IOWR, -CS0, -CS1, nor A[02:00] until at least t

ACK

after negating DMACK.


27

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Note: The definitions for the STOP, DDMARDY, and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. A00-A02, -CS0 & -CS1 are True IDE mode signal definitions.


28

Ver 1.3


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Host Terminating an Ultra DMA Data-Out Burst

Termination of an Ultra DMA Data-Out burst by the host is shown in below: Ultra DMA Data-Out

Burst Host Termination Timing while timing parameters are specified in Page 12: Ultra DMA Data Burst

Timing Requirements and timing parameters are described in Page 13: Ultra DMA Data Burst Timing

Descriptions.


(a) The host shall initiate termination of an Ultra DMA data burst by not generating HSTROBE edges.

(b) The host shall assert STOP no sooner than t

SS after it last generated an HSTROBE edge.The host shall not negate STOP again until after the Ultra DMA data burst is terminated.

(c) The device shall negate DMARQ within t

LI

after the host asserts STOP. The device shall not assert

DMARQ again until after the Ultra DMA data burst is terminated.

(d) The device shall negate -DDMARDY within t

LI

after the host has negated STOP. The device shall not assert -DDMARDY again until after the Ultra DMA data burst termination is complete.

(e) If HSTROBE is negated, the host shall assert HSTROBE within t

LI

after the device has negated

DMARQ. No data shall be transferred during this assertion. The device shall ignore this transition on

HSTROBE. HSTROBE shall remain asserted until the Ultra DMA data burst is terminated.

(f) The host shall place the result of its CRC calculation on D[15:00] (see ATA specification Ultra DMA

CRC Calculation).

(g) The host shall negate -DMACK no sooner than t

MLI after the host has asserted HSTROBE and STOP and the device has negated DMARQ and -DDMARDY, and no sooner than t

DVS

after placing the result of its CRC calculation on D[15:00].

(h) The device shall latch the host’s CRC data from D[15:00] on the negating edge of -DMACK.

(i) The device shall compare the CRC data received from the host with the results of its own CRC calculation. If a miscompare error occurs during one or more Ultra DMA data bursts for any one command, at the end of the command, the device shall report the first error that occurred (see ATA specification Ultra DMA CRC Calculation).

(j) While operating in True IDE mode, the device shall release -DDMARDY within t

IORDYZ

after the host has negated -DMACK.

(k) The host shall neither negate STOP nor negate HSTROBE until at least t

ACK

after negating -DMACK.

(l) In True IDE mode, the host shall not assert -IOWR, -CS0, -CS1, nor A[02:00] until at least t

ACK

after negating DMACK..


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Notes: The definitions for the STOP, DDMARDY, and HSTROBE signal lines are no longer in effect after DMARQ and DMACK are negated. A[02:00], -CS0 & -CS1 are True IDE mode signal definitions.


30

Ver 1.3


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IDENTIFY DEVICE information

The Identify Device command enables the host to receive parameter information from the device.

This command has the same protocol as the Read Sector(s) command. The parameter words in the buffer have the arrangement and meanings defined in Table as below. All reserved bits or words are zero.

Hosts should not depend on Obsolete words in Identify Device containing 0. Table below specifies each field in the data returned by the Identify Device Command. In Table as below, X indicates a numeric nibble value specific to the card and aaaa indicates an ASCII string specific to the particular drive.

6

7-8

9

10-19

20

21

22

23-26

Word

Address

0

1

2

3

4

5

Default

Value

Total

Bytes

044Ah 2

XXXXh 2

0000h

00XXh

0000h

0000h

2

2

2

2

XXXXh 2

XXXXh 4

XXXXh 2 aaaa 20

0000h

0000h

0004h aaaa

2

2

2

8

27-46

47

48

49

50 aaaa 40

XXXXh 2

0000h 2

XX00h

0000h

2

2

Data Field Type Information

General configuration – Bit Significant with ATA-4 definitions.

Default number of cylinders

Reserved

Default number of heads

Obsolete

Obsolete

Default number of sectors per track

Number of sectors per card (Word 7 = MSW, Word 8 = LSW)

Obsolete

Serial number in ASCII (Right Justified)

Obsolete

Obsolete

Number of ECC bytes passed on Read/Write Long Commands

Firmware revision in ASCII. Big Endian Byte Order in Word

Model number in ASCII (Left Justified) Big Endian Byte Order in

Word

Maximum number of sectors on Read/Write Multiple command

Reserved

Capabilities

Reserved


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Word

Address

51

52

53

54

55

56

Default

Value

0200h

0000h

000Xh

Total

Bytes

2

2

2

XXXXh 2

XXXXh 2

XXXXh 2

Data Field Type Information

PIO data transfer cycle timing mode

Obsolete

Field Validity

Current numbers of cylinders

Current numbers of heads

Current sectors per track

Current capacity in sectors (LBAs)(Word 57 = LSW, Word 58 = 57-58 XXXXh 4

59 01XXh 2

60-61 XXXXh 4

62 0000h 2

63

64

0X0Xh

0003h

2

2

Total number of sectors addressable in LBA Mode

Reserved

65

66

XXXXh

XXXXh

2

2

67

68

XXXXh

XXXXh

2

2

69-79 0000h 20

80-81

82-84

85-87

88

89

90

91

92-127

128

129-159

160

161

162

0000h

XXXXh

XXXXh

XXXXh

0000h

XXXXh

0000h

4

6

6

001Fh 2

XXXXh 2

XXXXh 2

2

72

2

64

XXXXh 2

0000h 2

0000h 2

163

164

XXXXh

XXXXh

165-167 0000h

2

2

6

Multiword DMA transfer. In PC Card modes this value shall be 0h

Advanced PIO modes supported

Minimum Multiword DMA transfer cycle time per word. In PC Card modes this value shall be 0h

Recommended Multiword DMA transfer cycle time. In PC Card modes this value shall be 0h

Minimum PIO transfer cycle time without flow control

Minimum PIO transfer cycle time with IORDY flow control

Reserved

Reserved – CF cards do not return an ATA version

Features/command sets supported

Features/command sets enabled

Ultra DMA Mode Supported and Selected (UDMA mode 0 ~ 4)

Time required for Security erase unit completion

Time required for Enhanced security erase unit completion

Current Advanced power management value

Reserved

Security status

Vendor unique bytes

Power requirement description

Reserved for assignment by the CFA

Key management schemes supported

CF Advanced True IDE Timing Mode Capability and Setting

CF Advanced PC Card I/O and Memory Timing Mode Capability

Reserved for assignment by the CFA

168-255 0000h 158 Reserved


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Capacity Specifications:

Transcend P/N Capacity Cylinder (C) Head (H)

TS128MDOM40V-S

TS256MDOM40V-S

TS512MDOM40V-S

128MB

256MB

512MB

248

496

993

16

16

16

TS1GDOM40V-S

TS2GDOM40V-S

TS4GDOM40V-S

TS8GDOM40V-S

TS16GDOM40V-S

1GB

2GB

4GB

8GB

16GB

1942

3884

7769

15538

33149

16

16

16

16

15

Sector (S)

63

63

63

63

63

63

63

63


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Ver 1.3


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TS XXXX DOM 40 V-S

Transcend Product

Capacity:

128M-512M = 128 MB up to 512 MB

1G-16G = 1 GB up to 16 GB

IDE Flash Module

(Disk On Module)

Type:

V = Vertical

H = Horizontal

Pin Count:

40 = 40 pin

44 = 44 pin

The above technical information is based on industry standard data and has been tested to be reliable. However, Transcend makes no warranty, either expressed or implied, as to its accuracy and assumes no liability in connection with the use of this product. Transcend reserves the right to make changes to the specifications at any time without prior notice.

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United Kingdom

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35

Ver 1.3

Transcend 16GB 40-pin PATA SLC Datasheet

True IDE PIO Mode Read/Write Timing

True IDE PIO Mode Timing Diagram

True IDE Multiword DMA Mode Read/Write Timing Specification

True IDE Multiword DMA Mode Read/Write Timing Diagram

Ultra DMA Data Burst Timing Requirements

Ultra DMA Data Burst Timing Descriptions

Ultra DMA Sender and Recipient IC Timing Requirements

Ultra DMA AC Signal Requirements

Initiating an Ultra DMA Data-In Burst

Sustaining an Ultra DMA Data-In Burst

Host Pausing an Ultra DMA Data-In Burst

Device Terminating an Ultra DMA Data-In Burst

Host Terminating an Ultra DMA Data-In Burst

Initiating an Ultra DMA Data-Out Burst

Sustaining an Ultra DMA Data-Out Burst

Device Pausing an Ultra DMA Data-Out Burst

Device Terminating an Ultra DMA Data-Out Burst

Host Terminating an Ultra DMA Data-Out Burst

IDENTIFY DEVICE information

TS XXXX DOM 40 V-S

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