OPA827 Low-Noise, High-Precision, JFET-Input
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OPA827
SBOS376I – NOVEMBER 2006 – REVISED JULY 2016
OPA827 Low-Noise, High-Precision, JFET-Input
Operational Amplifier
1 Features
3 Description
•
The OPA827 series of JFET operational amplifiers
combine outstanding DC precision with excellent AC
performance. These amplifiers offer low offset voltage
(150 µV, maximum), very low drift over temperature
(0.5 µV/°C, typical), low-bias current (3 pA, typical),
and very low 0.1-Hz to 10-Hz noise (250 nVPP,
typical). The device operates over a wide supply
voltage range, ±4 V to ±18 V on a low supply current
(4.8 mA/Ch, typical).
Input Voltage Noise Density:
4 nV/√Hz at 1 kHz
Input Voltage Noise:
0.1 Hz to 10 Hz: 250 nVPP
Input Bias Current: 10 pA (Maximum)
Input Offset Voltage: 150 µV (Maximum)
Input Offset Drift: 2 µV/°C (Maximum)
Gain Bandwidth: 22 MHz
Slew Rate: 28 V/µs
Quiescent Current: 4.8 mA/Ch
Wide Supply Range: ±4 V to ±18 V
Packages: 8-Pin SOIC and 8-Pin VSSOP
1
•
•
•
•
•
•
•
•
•
Excellent AC characteristics, such as a 22-MHz gain
bandwidth product (GBW), a slew rate of 28 V/µs,
and precision DC characteristics make the OPA827
series well-suited for a wide range of applications
including 16-bit to 18-bit mixed signal systems,
transimpedance (I/V-conversion) amplifiers, filters,
precision ±10-V front ends, and professional audio
applications.
2 Applications
•
•
•
•
•
•
•
•
•
ADC Drivers
DAC Output Buffers
Test Equipment
Medical Equipment
PLL Filters
Seismic Applications
Transimpedance Amplifiers
Integrators
Active Filters
The OPA827 is available in both 8-pin SOIC and 8pin VSSOP surface-mount packages, and is specified
from –40°C to 125°C.
Device Information(1)
PART NUMBER
OPA827
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.91 mm
VSSOP (8)
3.00 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Input Voltage Noise Density vs Frequency
0.1-Hz to 10-Hz Noise
VS = ±18V
50nV/div
Voltage Noise Density (nV/√Hz)
100
10
1
0.1
1
10
100
1k
10k
Time (1s/div)
Frequency (Hz)
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA827
SBOS376I – NOVEMBER 2006 – REVISED JULY 2016
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
5
6.1
6.2
6.3
6.4
6.5
6.6
5
5
5
5
6
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Detailed Description ............................................ 15
7.1
7.2
7.3
7.4
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
15
15
15
20
8
Application and Implementation ........................ 21
8.1 Application Information............................................ 21
8.2 Typical Application .................................................. 21
8.3 System Examples .................................................. 22
9 Power Supply Recommendations...................... 24
10 Layout................................................................... 25
10.1 Layout Guidelines ................................................. 25
10.2 Layout Example .................................................... 25
11 Device and Documentation Support ................. 26
11.1
11.2
11.3
11.4
11.5
11.6
11.7
Device Support......................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resource............................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
26
26
12 Mechanical, Packaging, and Orderable
Information ........................................................... 27
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (May 2012) to Revision I
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
•
Deleted Package/Ordering Information table, see POA at the end of the data sheet............................................................ 4
•
Changed values in the Thermal Information table to align with JEDEC standards................................................................ 5
Changes from Revision G (February 2012) to Revision H
Page
•
Updated Figure 3.................................................................................................................................................................... 8
•
Updated Figure 4.................................................................................................................................................................... 8
Changes from Revision F (March 2009) to Revision G
Page
•
Changed Input bias current and Input offset drift Features bullets ........................................................................................ 1
•
Changed product status from Mixed Status to Production Data ............................................................................................ 1
•
Changed description of amplifier drift and bias current in first paragraph of Description section .......................................... 1
•
Deleted high grade (OPA827I) option and footnote 2 from Package/Ordering Information table.......................................... 4
•
Deleted high grade (OPA827I) option from Electrical Characteristics table........................................................................... 6
•
Changed Offset Voltage, Input Offset Voltage Drift parameter typical and maximum specifications in Electrical
Characteristics table ............................................................................................................................................................... 6
•
Changed Input Bias Current section specifications in Electrical Characteristics table........................................................... 6
•
Changed -40°C to +85°C Input Bias Current parameter unit ................................................................................................. 6
•
Added Frequency Response, Slew Rate parameter minimum specification to Electrical Characteristics table .................... 6
•
Added Output, Short-Circuit Current parameter minimum specification to Electrical Characteristics table ........................... 7
•
Updated Figure 7.................................................................................................................................................................... 8
•
Updated Figure 8.................................................................................................................................................................... 8
2
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•
Updated Figure 9.................................................................................................................................................................... 8
•
Updated Figure 11.................................................................................................................................................................. 8
•
Updated Figure 12.................................................................................................................................................................. 8
•
Updated Figure 14.................................................................................................................................................................. 9
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SBOS376I – NOVEMBER 2006 – REVISED JULY 2016
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5 Pin Configuration and Functions
D and DGK Packages
8-Pin SOIC and VSSOP
Top View
NC
(1)
(1)
(1)
1
8
NC
-In
2
7
V+
+In
3
6
Out
V-
4
5
NC
(1)
NC denotes no internal connection.
Pin Functions
PIN
NO.
NAME
+IN
3
I/O
DESCRIPTION
I
Noninverting input
Inverting input
–IN
2
I
NC
1, 5, 8
—
No internal connection (can be left floating)
OUT
6
O
Output
V+
7
—
Positive power supply
V–
4
—
Negative power supply
4
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
40
V
Supply voltage, VS = (V+) – (V–)
Input voltage (2)
(V–) – 0.5
(V+) + 0.5
V
±10
mA
±VS
V
150
°C
150
°C
150
°C
Input current (2)
Differential input voltage
Output short-circuit (3)
Continuous
Operating temperature, TA
–55
Junction temperature, TJ
Storage temperature, Tstg
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input terminals are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must
be current-limited to 10 mA or less.
Short-circuit to VS/2 (ground in symmetrical dual-supply setups).
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VS
Supply voltage
TA
Specified temperature
NOM
MAX
UNIT
±4
±18
V
–40
125
°C
6.4 Thermal Information
OPA827
THERMAL METRIC (1)
D (SOIC)
DGK (VSSOP)
UNIT
8 PINS
8 PINS
RθJA
Junction-to-ambient thermal resistance
160
180
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
75
55
°C/W
RθJB
Junction-to-board thermal resistance
60
130
°C/W
ψJT
Junction-to-top characterization parameter
9
—
°C/W
ψJB
Junction-to-board characterization parameter
50
120
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
at VS = ±4 V to ±18 V, TA = 25°C, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OFFSET VOLTAGE
VOS
Input offset voltage
VS = ±15 V, VCM = 0 V
75
150
dVOS/dT
Input offset voltage drift
TA = –40°C to 125°C
0.1
2
PSRR
Input offset voltage vs power
supply
TA = –40°C to 125°C
0.2
1
3
µV
µV/°C
µV/V
INPUT BIAS CURRENT
±3
IB
Input bias current
TA = –40°C to 85°C
TA = –40°C to 125°C
IOS
Input Offset Current
±3
±10
pA
±500
pA
±5
nA
±10
pA
NOISE
Input Voltage Noise:
en
Input Voltage Noise Density
in
Input current noise density
f = 0.1 Hz to 10 Hz, VS = ±18 V, VCM = 0 V
250
f = 1 kHz, VS = ±18 V, VCM = 0 V
nVPP
4
f = 10 kHz, VS = ±18 V, VCM = 0 V
3.8
f = 1 kHz, VS = ±18 V, VCM = 0 V
2.2
nV/√Hz
fA/√Hz
INPUT VOLTAGE RANGE
Common-mode voltage
range
VCM
Common-mode rejection
ratio
CMRR
(V–) + 3
(V+) – 3
(V−) + 3 V ≤ VCM ≤ (V+) − 3 V, VS < 10 V
104
114
(V−) + 3 V ≤ VCM ≤ (V+) − 3 V, VS ≥ 10 V
114
126
(V−) + 3 V ≤ VCM ≤ (V+) − 3 V, VS < 10 V
TA = –40°C to 125°C
100
(V−) + 3 V ≤ VCM ≤ (V+) − 3 V, VS ≥ 10 V
TA = –40°C to 125°C
110
V
dB
INPUT IMPEDANCE
1013 ∥ 9
Differential
13
Common-mode
10
∥9
Ω ∥ pF
Ω ∥ pF
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
(V–) + 3 V ≤ VO ≤ (V+) – 3 V, RL = 1 kΩ
120
(V–) + 3 V ≤ VO ≤ (V+) – 3 V, RL = 1 kΩ
TA = –40°C to 125°C
114
126
dB
FREQUENCY RESPONSE
GBW
Gain-bandwidth product
G = +1
SR
Slew rate
G = –1
tS
THD+N
6
22
MHz
28
V/µs
±0.01%, 10-V step, G = –1, CL = 100 pF
550
ns
Settling time
0.00075% (16-bit), 10-V step, G = –1,
CL = 100 pF
850
ns
Overload recovery time
Gain = –10
150
ns
Total Harmonic Distortion +
Noise
G = +1, f = 1 kHz
20
VO = 3 VRMS, RL = 600 Ω
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0.00004%
–128
dB
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Electrical Characteristics (continued)
at VS = ±4 V to ±18 V, TA = 25°C, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
OUTPUT
RL = 1 kΩ, AOL > 120 dB
(V–) + 3
(V+) – 3
Voltage output swing
RL = 1 kΩ, AOL > 114 dB
TA = –40°C to 125°C
(V–) + 3
(V+) – 3
IOUT
Output current
|VS – VOUT| < 3 V
ISC
Short-circuit current
CLOAD
Capacitive load drive
See Typical Characteristics
ZO
Open-loop output
impedance
See Typical Characteristics
±55
V
30
mA
±65
mA
POWER SUPPLY
VS
Specified voltage
IQ
Quiescent current
(per amplifier)
±4
IOUT = 0A
±18
4.8
TA = –40°C to 125°C
5.2
6
V
mA
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6.6 Typical Characteristics
At TA = 25°C, VS = ±18 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply, unless otherwise noted.
100
Input Voltage Noise (mV)
Voltage Noise Density (nV/ÖHz)
100
10
10
VPP
1
VRMS
0.1
Noise Bandwidth: 0.1Hz
to indicated frequency.
0.01
1
0.1
1
10
100
1k
10k
1
10
100
1k
Figure 1. Input Voltage Noise Density vs Frequency
G = 10
0.0001
G=1
20
100
10M
0.001
G=1
0.0001
VS = ± 15V
RL = 600 Ω
f = 1 kHz
0.00001
1M
Figure 2. Integrated Input Voltage Noise vs Bandwidth
VS = ± 15V
RL = 600Ω
VOUT = 3VRMS
0.001
100k
0.01
THD+N (%)
THD+N (%)
0.01
10k
Bandwidth (Hz)
Frequency (Hz)
1k
Frequency (Hz)
10k
20k
0.00001
10m
G = 10
100m
G000
Figure 3. Total Harmonic Distortion + Noise Ratio
vs Frequency
1
Voltage (Vrms)
10
20
G001
Figure 4. Total Harmonic Distortion + Noise Ratio
vs Amplitude
135
150
105
120
75
90
60
30
45
0
15
-15
-30
-45
-60
-90
-75
-105
-120
-135
Time (1s/div)
-150
50nV/div
Population
VS = ±15V
Offset Voltage (mV)
Figure 5. 0.1-Hz to 10-Hz Noise
8
Figure 6. Offset Voltage Production Distribution
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Typical Characteristics (continued)
At TA = 25°C, VS = ±18 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply, unless otherwise noted.
250
25
150
20
100
15
VOS (mV)
Pecentage of Amplifiers (%)
10 Typical Units Shown
VS = 8V
200
10
50
0
-50
-100
5
-150
-200
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2
-250
3.0
Offset Voltage Drift (µV/°C)
150
VOS Shift (mV)
VOS (mV)
100
50
0
-50
-100
-150
-200
-250
3
8
13
18
3.6
23
28
15
10
5
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
0
33
50
250
4.6
4.8
5.0
20 Typical Units Shown
100
150
200
250
300
100
Specified Temperature Range
-50
-100
-150
-200
− IB
+ IB
8
Input Bias Current (pA)
150
VOS (mV)
4.4
Figure 10. VOS Warmup
10
VS = ±15V
200
-250
-75
4.2
Time (s)
Figure 9. Offset Voltage vs Common-Mode Voltage
0
4.0
VS = ±15V
VCM (V)
50
3.8
Figure 8. Offset Voltage vs Common-Mode Voltage
10 Typical Units Shown
VS = 36V
200
3.4
VCM (V)
Figure 7. Offset Voltage Drift Production Distribution
250
3.2
G001
6
4
2
0
−2
−4
−6
−8
-50
-25
0
25
50
75
100
125
150
−10
4
Temperature (°C)
Figure 11. Offset Voltage vs Temperature
6
8
10
12
14
Supply Voltage (V)
16
18
G002
Figure 12. Input Bias Current and Offset Current
vs Supply Voltage
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Typical Characteristics (continued)
At TA = 25°C, VS = ±18 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply, unless otherwise noted.
12000
20
15
Input Bias Current (pA)
Specified Common-Mode
10
Voltage Range
IB (pA)
5
Unit 1
0
Unit 3
-5
Unit 2
-10
− IB
+ IB
IOS
10000
8000
6000
4000
2000
-15
-20
-18 -15 -12 -9
-6
-3
0
3
6
9
12
15
0
−50
18
−25
0
25
50
75
Temperature (°C)
VCM (V)
Figure 13. Input Bias Current vs Common-Mode Voltage
0.05
125
150
G002
Figure 14. Input Bias Current vs Temperature
6.0
10 Typical Units Shown
0
100
VS = ±18V
5.5
-0.05
IQ (mA)
I Q Shift (mA)
-0.10
-0.15
-0.20
-0.25
5.0
VS = ±5V
4.5
-0.30
4.0
-0.35
-0.40
3.5
-75
-0.45
0
50
100
150
200
250
300
-50
-25
Time (s)
0
25
50
75
100
Figure 15. Normalized Quiescent Current vs Time
Figure 16. Quiescent Current vs Temperature
4
4.95
VS = ±5V
-55°C
3
Output Swing (V)
4.90
4.85
IQ (mA)
150
5
5.00
4.80
4.75
4.70
-40°C
2
1
+150°C
+25°C
+125°C
+85°C -40°C
0
-1
-2
-55°C
-3
4.65
-4
-5
4.60
8
13
18
23
28
33
38
20
30
40
50
60
70
73
Output Current (mA)
VS (V)
Figure 17. Quiescent Current vs Supply Voltage
10
125
Temperature (°C)
Figure 18. Output Voltage Swing vs Output Current
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Typical Characteristics (continued)
At TA = 25°C, VS = ±18 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply, unless otherwise noted.
180
16
VS = ±18V
12
Positive
140
8
4
PSRR (dB)
Output Swing (V)
Referred to Input
160
+150°C +125°C +85°C
0
-40°C
+25°C
-55°C
-4
120
100
Negative
80
60
-8
40
-12
20
0
-16
48
53
58
63
68
1
0.1
73
10
100
Figure 19. Output Voltage Swing vs Output Current
140
10k 100k
1M
10M 100M
Figure 20. Power-Supply Rejection Ratio vs Frequency
0.30
VS ³ 10V
120
0.25
100
PSRR (mV/V)
CMRR (dB)
1k
Frequency (Hz)
Output Current (mA)
80
60
0.20
0.15
0.10
40
20
0.1
1
10
100
1k
10k
100k
1M
0.05
-75
10M 100M
-50
-25
0
Frequency (Hz)
25
50
75
100
125
150
Temperature (°C)
Figure 21. Common-Mode Rejection Ratio vs Frequency
Figure 22. Power-Supply Rejection Ratio vs Temperature
1.6
0
140
1.4
120
100
1.0
Gain (dB)
0.8
0.6
0.4
-45
80
Phase
-90
60
40
Phase (°)
CMRR (mV/V)
1.2
0.2
-135
20
0.0
-0.2
0
-0.4
-20
-75
-50
-25
0
25
50
75
100
125
150
Gain
1
10
Temperature (°C)
100
1k
10k
100k
1M
10M
-180
100M
Frequency (Hz)
Figure 23. Common-Mode Rejection Ratio vs Temperature
Figure 24. Open-Loop Gain and Phase vs Frequency
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Typical Characteristics (continued)
At TA = 25°C, VS = ±18 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply, unless otherwise noted.
50
1.2
RL = 1kW
G = +101
40
1.0
G = +11
20
AOL (mV/V)
Gain (dB)
30
10
G = +1
0
-10
0.8
0.6
0.4
-20
-30
100
1k
10k
100k
1M
10M
0.2
-75
100M
-50
Frequency (Hz)
0
25
50
75
100
125
150
Temperature (°C)
Figure 25. Closed-Loop Gain vs Frequency
Figure 26. Open-Loop Gain vs Temperature
1000
70
100mV Output Step
G = +1
60
100
Overshoot (%)
Open-Loop Output Impedance (ZO)
-25
10
50
40
G = -1
30
20
10
1
100
0
1k
100k
10k
1M
10M
100
0
100M
Frequency (Hz)
200 300 400 500 600 700 800 900 1000
Capacitive Load (pF)
Figure 27. Open-Loop Output Impedance vs Frequency
Figure 28. Small-Signal Overshoot vs Capacitive Load
G = -10
VOUT
+18V
OPA827
Output
5V/div
5V/div
Output
0V
10kW
VIN
OPA827
VOUT
VIN
-18V
37VPP
Sine Wave
(±18.5V)
0.5ms/div
Time (0.5ms/div)
Figure 29. No Phase Reversal
12
1kW
Figure 30. Positive Overload Recovery
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Typical Characteristics (continued)
At TA = 25°C, VS = ±18 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply, unless otherwise noted.
G = +1
RL = 1kW
CL = 100pF
G = -10
20mV/div
5V/div
VIN
0V
10kW
+18V
OPA827
1kW
OPA827
-18V
VOUT
RL
CL
VIN
VOUT
Time (0.1ms/div)
Time (0.5ms/div)
Figure 31. Negative Overload Recovery
Figure 32. Small-Signal Step Response
R1
1kW
2V/div
20mV/div
C1
5.6pF
R2
1kW
+18V
OPA827
G = +1
RL = 1kW
CL = 100pF
CL
G = -1
CL = 100pF
-18V
Time (0.1ms/div)
Time (0.5ms/div)
Figure 34. Large-Signal Step Response
2V/div
G = -1
CL = 100pF
1.0
0.010
0.8
0.008
0.6
0.006
0.4
0.004
16-Bit
Settling
0.2
0.002
0
0
-0.2
-0.002
(±1/2 LSB =
±0.00075%)
-0.4
-0.004
-0.6
-0.006
-0.8
-0.008
-1.0
0
100
Time (0.5ms/div)
200 300
400 500 600
Time (ns)
D From Final Value (%)
D From Final Value (mV)
Figure 33. Small-Signal Step Response
-0.010
700 800 900 1000
10 VPP, CL = 100 pF
Figure 35. Large-Signal Step Response
Figure 36. Large-Signal Positive Settling Time
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Typical Characteristics (continued)
1.0
0.010
0.008
0.8
0.008
0.6
0.006
0.6
0.006
0.4
0.004
16-Bit
Settling
0.2
0.002
0
0
-0.2
-0.002
(±1/2 LSB =
±0.00075%)
-0.4
-0.004
-0.6
-0.006
-0.8
-1.0
0
100
200 300
400 500 600
Time (ns)
D From Final Value (mV)
0.010
0.8
0.4
0
-0.2
-0.006
-0.008
-0.8
-0.008
-0.010
700 800 900 1000
-1.0
0
100
0.008
60
0.6
0.006
0.002
0
-0.002
(±1/2 LSB =
±0.00075%)
-0.004
0
-20
-40
-0.006
-0.8
-0.008
-60
-0.010
700 800 900 1000
-80
0
100
200 300
400 500 600
Time (ns)
Sourcing
20
-0.6
-1.0
-0.010
700 800 900 1000
40
ISC (mA)
0.004
D From Final Value (%)
D From Final Value (mV)
0.8
-0.4
400 500 600
Time (ns)
Figure 38. Large-Signal Negative Settling Time
80
0
200 300
10 VPP, CL = 100 pF
0.010
-0.2
-0.004
-0.6
Figure 37. Large-Signal Positive Settling Time
0.2
-0.002
(±1/2 LSB =
±0.00075%)
-0.4
1.0
16-Bit
Settling
0.002
0
10 VPP, CL = 10 pF
0.4
0.004
16-Bit
Settling
0.2
D From Final Value (%)
1.0
D From Final Value (%)
D From Final Value (mV)
At TA = 25°C, VS = ±18 V, RL = 10 kΩ connected to midsupply, and VCM = VOUT = midsupply, unless otherwise noted.
Sinking
-75
-25
25
75
125
175
Temperature (°C)
10 VPP, CL = 10 pF
Figure 39. Large-Signal Negative Settling Time
14
Figure 40. Short-Circuit Current vs Temperature
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7 Detailed Description
7.1 Overview
The OPA827 is a unity-gain stable, precision operational amplifier with very low noise, input bias current, and
input offset voltage. Applications with noisy or high-impedance power supplies require decoupling capacitors
placed close to the device pins. In most cases, 0.1-µF capacitors are adequate.
7.2 Functional Block Diagram
V+
IN+
IN-
OUT
V-
Copyright © 2016, Texas Instruments Incorporated
7.3 Feature Description
The OPA827 is a precision JFET amplifier with low input offset voltage, low input offset voltage drift and low
noise. High impedance inputs make the OPA827 ideal for high source impedance applications and
transimpedance applications.
7.3.1 Operating Voltage
The OPA827 series of op amps can be used with single or dual supplies from an operating range of
VS = 8 V (±4 V) and up to VS = 36 V (±18 V). This device does not require symmetrical supplies; it only requires
a minimum supply voltage of 8 V. Supply voltages higher than 40 V (±20 V) can permanently damage the device;
see Absolute Maximum Ratings. Key parameters are specified over the operating temperature range, TA = –40°C
to 125°C. Key parameters that vary over the supply voltage or temperature range are shown in Typical
Characteristics of this data sheet.
7.3.2 Noise Performance
Figure 41 shows the total circuit noise for varying source impedances with the operational amplifier in a unitygain configuration (with no feedback resistor network and therefore no additional noise contributions). The
OPA827 (GBW = 22 MHz) and OPA211 (GBW = 80 MHz) are both shown in this example with total circuit noise
calculated. The op amp itself contributes both a voltage noise component and a current noise component. The
voltage noise is commonly modeled as a time-varying component of the offset voltage. The current noise is
modeled as the time-varying component of the input bias current and reacts with the source resistance to create
a voltage component of noise. Therefore, the lowest noise op amp for a given application depends on the source
impedance. For low source impedance, current noise is negligible, and voltage noise generally dominates. The
OPA827 family has both low voltage noise and lower current noise because of the FET input of the op amp. Very
low current noise allows for excellent noise performance with source impedances greater than 10 kΩ. OPA211
has lower voltage noise and higher current noise. The low voltage noise makes the OPA211 a better choice for
low source impedances (less than 2 kΩ). For high source impedance, current noise may dominate, and makes
the OPA827 series amplifier the better choice.
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Feature Description (continued)
The equation in Figure 41 shows the calculation of the total circuit noise, with these parameters:
• en = voltage noise
• in = current noise
• RS = source impedance
• k = Boltzmann's constant = 1.38 × 10–23 J/K
• T = temperature in kelvins
For more details on calculating noise, see Basic Noise Calculations.
Votlage Noise Spectral Density, EO
10k
EO
1k
OPA211
RS
100
OPA827
Resistor Noise
10
2
2
2
EO = en + (in RS) + 4kTRS
1
100
1k
10k
100k
1M
Source Resistance, RS (W)
Figure 41. Noise Performance of the OPA827 and OPA211 in Unity-Gain Buffer Configuration
7.3.3 Basic Noise Calculations
Low-noise circuit design requires careful analysis of all noise sources. External noise sources can dominate in
many cases; consider the effect of source resistance on the overall noise performance of the op amp. Total noise
of the circuit is the root-sum-square combination of all noise components.
The resistive portion of the source impedance produces thermal noise proportional to the square root of the
resistance. This function is plotted in Figure 41. The source impedance is usually fixed; consequently, select the
op amp and the feedback resistors to minimize the respective contributions to the total noise.
Figure 42 illustrates both noninverting (A) and inverting (B) op amp circuit configurations with gain. In circuit
configurations with gain, the feedback network resistors also contribute noise. The current noise of the op amp
reacts with the feedback resistors to create additional noise components.
The feedback resistor values can generally be chosen to make these noise sources negligible.
NOTE
Low-impedance feedback resistors load the output of the amplifier. The equations for total
noise are shown for both configurations shown in both configurations in Figure 42.
16
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Feature Description (continued)
A) Noise in Noninverting Gain Configuration
Noise at the output:
R2
2
2
R1
EO = 1 +
R2
R1
2
2
2
2
2
2
en + e1 + e2 + (inR2) + eS + (inRS)
EO
R2
Where eS = Ö4kTRS ´ 1 +
R1
2
1+
R2
R1
= thermal noise of RS
RS
e1 = Ö4kTR1 ´
VS
R2
R1
= thermal noise of R1
e2 = Ö4kTR2 = thermal noise of R2
B) Noise in Inverting Gain Configuration
Noise at the output:
R2
2
2
EO
R1
= 1+
R2
2
EO
RS
2
2
2
en + e1 + e2 + (inR2) + eS
R 1 + RS
Where eS = Ö4kTRS ´
R2
R1 + RS
2
= thermal noise of RS
VS
e1 = Ö4kTR1 ´
R2
R1 + RS
= thermal noise of R1
e2 = Ö4kTR2 = thermal noise of R2
For the OPA827 series op amps at 1kHz, en = 4nV/ÖHz and in = 2.2fA/ÖHz.
Copyright © 2016, Texas Instruments Incorporated
Figure 42. Noise Calculation in Gain Configurations
7.3.4 Total Harmonic Distortion Measurements
The OPA827 series op amps have excellent distortion characteristics. THD + Noise is below 0.0001%
(G = +1, VO = 3 VRMS) throughout the audio frequency range, 20 Hz to 20 kHz, with a 600-Ω load (see Figure 3).
The distortion produced by the OPA827 series is below the measurement limit of many commercially available
testers. However, a special test circuit (illustrated in Figure 43) can be used to extend the measurement
capabilities.
Op amp distortion can be considered an internal error source that can be referred to the input. Figure 43 shows a
circuit that causes the op amp distortion to be 101 times greater than that distortion normally produced by the op
amp. The addition of R3 to the otherwise standard noninverting amplifier configuration alters the feedback factor
or noise gain of the circuit. The closed-loop gain is unchanged, but the feedback available for error correction is
reduced by a factor of 101, thus extending the resolution by 101.
NOTE
the input signal and load applied to the op amp are the same as with conventional
feedback without R3. The value of R3 must be kept small to minimize its effect on the
distortion measurements.
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Feature Description (continued)
The validity of this technique can be verified by duplicating measurements at high gain and high frequency where
the distortion is within the measurement capability of the test equipment. Measurements for this data sheet were
made with an Audio Precision System Two distortion and noise analyzer, which greatly simplifies such repetitive
measurements. This measurement technique, however, can be performed with manual distortion measurement
instruments.
R1
R2
SIGNAL DISTORTION
GAIN
GAIN
R3
OPA827
VO = 3VRMS
R
Signal Gain = 1+ 2
R1
Distortion Gain = 1+
R2
R1 II R3
Generator
Output
R1
R2
R3
1
101
¥
1kW
10W
11
101
100W
1kW
11W
Analyzer
Input
Audio Precision
System Two(1)
with PC Controller
RL
600W
NOTE: (1) Measurement BW = 80kHz.
Copyright © 2016, Texas Instruments Incorporated
Figure 43. Distortion Test Circuit
7.3.5 Capacitive Load and Stability
The combination of gain bandwidth product (GBW) and near constant open-loop output impedance (ZO) over
frequency gives the OPA827 the ability to drive large capacitive loads. Figure 44 shows the OPA827 connected
in a buffer configuration (G = +1) while driving a 2.2-µF ceramic capacitor (with an ESR value of approximately 0
Ω). The small overshoot and fast settling time are results of good phase margin. This feature provides superior
performance compared to the competition. Figure 44 and Figure 45 were taken without any resistive load in
parallel to shorten the ringing time.
In Figure 45, the OPA827 is driving a 2.2-µF tantalum capacitor. A relatively small ESR that is internal to the
capacitor additionally improves phase margin and provides an output waveform with no ringing and minimal
overshoot. Figure 45 shows a stable system that can be used in almost any application.
Capacitive load drive depends on the gain and overshoot requirements of the application. Capacitive loads limit
the bandwidth of the amplifier. Increasing the gain enhances the ability of the amplifier to drive greater capacitive
loads (see Figure 28).
7.3.6 Phase-Reversal Protection
The OPA827 family has internal phase-reversal protection. Many FET-input op amps exhibit a phase reversal
when the input is driven beyond its linear common-mode range. This condition is most often encountered in
noninverting circuits when the input is driven beyond the specified common-mode voltage range, causing the
output to reverse into the opposite rail. The input circuitry of the OPA827 prevents phase reversal with excessive
common-mode voltage; instead, the output limits into the appropriate rail (see Figure 29).
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50mV/div
100mV/div
Feature Description (continued)
VIN
VOUT
20ms/div
50mV/div
100mV/div
Figure 44. OPA827 Driving 2.2-µF Ceramic Capacitor
VIN
VOUT
20ms/div
Figure 45. OPA827 Driving 2.2-µF Tantalum Capacitor
7.3.7 Transimpedance Amplifier
The gain bandwidth, low voltage noise, and current noise of the OPA827 series make them ideal wide bandwidth
transimpedance amplifiers in a photo-conductive application. High transimpedance gains with feedback resistors
greater than 100 kΩ benefit from the low input current noise (2.2 fA/Hz) of the JFET input. Low voltage noise is
important because photodiode capacitance causes the effective noise gain in the circuit to increase at high
frequencies. Total input capacitance of the circuit limits the overall gain bandwidth of the amplifier and is
addressed below. Figure 46 shows a photodiode transimpedance application.
7.3.7.1 Key Transimpedance Points
• The total input capacitance (CTOT) consists of the photodiode junction capacitance, and both the commonmode and differential input capacitance of the operational amplifier.
• The desired transimpedance gain, VOUT = IDRF.
• The Unity Gain Bandwidth Product (UGBW) (22 MHz for the OPA827).
With these three variables set, the feedback capacitor value (CF) can be calculated to ensure stability. CSTRAY is
the parasitic capacitance of the PCB and passive components, which is approximately 0.5 pF.
To ensure 45° phase margin, the minimal amount of feedback capacitance can be calculated using Equation 1.
1
CF
1+ 1+ (8pCTOTRFUGBW
4pRFUGBW
(
)(
)
(1)
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Feature Description (continued)
Bandwidth (f–3dB) can be calculated using Equation 2.
f-3dB =
UGBW
Hz
2pRF(CTOT)
(2)
These equations result in maximum transimpedance bandwidth. For additional information, refer to Compensate
Transimpedance Amplifiers Intuitively, available for download at www.ti.com.
(1)
CF
< 1pF
RF
1MW
CSTRAY
(2)
+VS
OPA827
ID
CTOT
VOUT = IDRF
-VS
NOTES: (1) CF is optional to prevent gain peaking.
(2) CSTRAY is the stray capacitance of RF
(typically, 2pF for a surface-mount resistor).
Copyright © 2016, Texas Instruments Incorporated
Figure 46. Transimpedance Amplifier
V+
IN-
IN+
OUT
V-
Copyright © 2016, Texas Instruments Incorporated
Figure 47. Equivalent Schematic (Single-Channel)
7.4 Device Functional Modes
The OPA827 has a single functional mode and is operational when the power-supply voltage is greater than 4 V
(±2 V). The maximum power supply voltage for the OPA827 is 36 V (±18 V).
20
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPA827 is a unity-gain stable, operational amplifier with very low noise, input bias current, and input offset
voltage. Applications with noisy or high-impedance power supplies require decoupling capacitors placed close to
the device pins. In most cases, 0.1-µF capacitors are adequate. Designers can easily take advantage of the lownoise characteristics of JFET amplifiers while also interfacing to modern, single-supply, precision data
converters.
8.2 Typical Application
R4
2.94 k
C5
1 nF
R1
590
R3
499
Input
C2
39 nF
±
Output
+
OPA140
Copyright © 2016, Texas Instruments Incorporated
Figure 48. 25-kHz Low-Pass Filter
8.2.1 Design Requirements
Low-pass filters are commonly employed in signal processing applications to reduce noise and prevent aliasing.
The OPA827 is ideally suited to construct high-speed, high-precision active filters. Figure 48 shows a secondorder, low-pass filter commonly encountered in signal processing applications.
Use the following parameters for this design example:
• Gain = 5 V/V (inverting gain)
• Low-pass cutoff frequency = 25 kHz
• Second-order Chebyshev filter response with 3-dB gain peaking in the pass band
8.2.2 Detailed Design Procedure
The infinite-gain multiple-feedback circuit for a low-pass network function is shown in. Use Equation 3 to
calculate the voltage transfer function.
1 R1R3C2C5
Output
s
2
Input
s
s C2 1 R1 1 R3 1 R4 1 R3R4C2C5
(3)
This circuit produces a signal inversion. For this circuit, the gain at DC and the low-pass cutoff frequency are
calculated by Equation 4.
R4
Gain
R1
fC
1
2S
1 R3R 4 C2C5
(4)
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Typical Application (continued)
Software tools are readily available to simplify filter design. WEBENCH® Filter Designer is a simple, powerful,
and easy-to-use active filter design program. WEBENCH® Filter Designer lets you create optimized filter designs
using a selection of TI operational amplifiers and passive components from TI's vendor partners.
Available as a web based tool from the WEBENCH Design Center, WEBENCH Filter Designer allows you to
design, optimize, and simulate complete multistage active filter solutions within minutes.
8.2.3 Application Curve
20
Gain (db)
0
-20
-40
-60
100
1k
10k
Frequency (Hz)
100k
1M
Figure 49. OPA827 Second-Order, 25-kHz, Chebyshev, Low-Pass Filter
8.3 System Examples
The OPA827 is well-suited for phase-lock loop (PLL) applications because of the low voltage offset, low noise,
and wide gain bandwidth. Figure 50 illustrates an example of the OPA827 in this application. The first amplifier
(OPA827) provides the loop low-pass, active filter function, while the second amplifier (OPA211) serves as a
scaling amplifier. This second stage amplifies the DC error voltage to the appropriate level before it is applied to
the voltage-controlled oscillator (VCO).
Operational amplifiers used in PLL applications are often required to have low voltage offset. As with other DC
levels generated in the loop, a voltage offset applied to the VCO is interpreted as a phase error. An operational
amplifier with inherently low voltage offset helps reduce this source of error. Also, any noise produced by the
operational amplifiers modulates the voltage applied to the VCO and limits the spectral purity of the oscillator
output. The VCO generates noise-related, random phase variations of its own, but this characteristic becomes
worse when the input voltage source noise is included. This noise appears as random sideband energy that can
limit system performance. The very low flicker noise (1/f) and current noise (In) of the OPA827 help to minimize
the operational amplifier contribution to the phase noise.
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System Examples (continued)
Offset Voltage Generator
(Frequency Adjustment)
Scaling
Amplifier
Low-Pass Filter
Current
Source
Input Signal Phase Dector
Output Signal
OPA827
OPA211
Current
Source
VCO
Level Adjustment and
Buffer Amplifier
Divider
1/N
Copyright © 2016, Texas Instruments Incorporated
Figure 50. PLL Application
8.3.1 OPA827 Used as an I/V Converter
The OPA827 series of operation amplifiers have low current noise and offset voltage that make these devices a
great choice for an I/V converter. DAC8811 is a single-channel, current output, 16-bit digital-to-analog converter
(DAC). The IOUT terminal of the DAC is held at a virtual GND potential by the use of the OPA827 as an external
I/V converter op amp. The R-2R ladder is connected to an external reference input (VREF) that determines the
DAC full-scale current. The external reference voltage can vary in a range of –15 V to 15 V, thus providing
bipolar IOUT current operation. By using the OPA827 as an external I/V converter in conjunction with the internal
DAC8811 RFB resistor, output voltage ranges of –VREF to +VREF can be generated.
When using an external I/V converter and the DAC8811 RFB resistor, the DAC output voltage is given by
Equation 5.
-VREF ´ CODE
VOUT =
65536
(5)
NOTE
CODE is the digital input into the DAC.
The DAC output impedance as seen looking into the IOUT terminal changes versus code. The low offset voltage
of the OPA827 minimizes the error propagated from the DAC.
For a current-to-voltage design (see Figure 51), the DAC8811 IOUT pin and the inverting node of the OPA827
must be as short as possible and adhere to good PCB layout design. For each code change on the output of the
DAC, there is a step function. If the parasitic capacitance is excessive at the inverting node, then gain peaking is
possible. For circuit stability, two compensation capacitors, C1 and C2 (4 pF to 20 pF typical) can be added to the
design.
Some applications require full four-quadrant multiplying capabilities or a bipolar output swing. As shown in
Figure 51, the OPA827 is added as a summing amp and has a gain of 2x that widens the output span to 20 V. A
four-quadrant multiplying circuit is implemented by using a 10-V offset of the reference voltage to bias the
OPA827.
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System Examples (continued)
10kW
10kW
C2
5kW
VDD
RFB
+10V
VREF
OPA827
C1
VOUT
DAC8811
IOUT
OPA827
-10V £ VOUT £ +10V
GND
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Figure 51. I/V Converter
9 Power Supply Recommendations
The OPA827 is specified for operation from 4 V to 36 V (±2 V to ±18 V); many specifications apply from –40°C to
125°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are
presented in the Absolute Maximum Ratings.
CAUTION
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute Maximum Ratings.
Place 0.1-µF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or highimpedance power supplies. For more detailed information on bypass capacitor placement, see Layout.
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10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically
separate digital and analog grounds paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much
better as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in Figure 52, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
• For best performance, TI recommends cleaning the PCB following board assembly.
• Any precision integrated circuit may experience performance shifts due to moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, TI recommends baking the PCB
assembly to remove moisture introduced into the device packaging during the cleaning process. A low
temperature, post cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
10.2 Layout Example
Run the input traces
as far away from
the supply lines
as possible
Place components
close to device and to
each other to reduce
parasitic errors
VS+
RF
N/C
N/C
GND
±IN
V+
VIN
+IN
OUTPUT
V±
N/C
RG
Use low-ESR,
ceramic bypass
capacitor
GND
VS±
GND
Use low-ESR, ceramic
bypass capacitor
VOUT
Ground (GND) plane on another layer
Figure 52. Operational Amplifier Board Layout for Noninverting Configuration
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Copyright © 2006–2016, Texas Instruments Incorporated
Product Folder Links: OPA827
25
OPA827
SBOS376I – NOVEMBER 2006 – REVISED JULY 2016
www.ti.com
11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.1.2 Development Support
For development support see the following:
• WEBENCH® Filter Designer
• OPA211
• DAC8811
11.2 Documentation Support
11.2.1 Related Documentation
For related documentation see the following:
Compensate Transimpedance Amplifiers Intuitively (SBOA055)
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.4 Community Resource
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.5 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
26
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Copyright © 2006–2016, Texas Instruments Incorporated
Product Folder Links: OPA827
OPA827
www.ti.com
SBOS376I – NOVEMBER 2006 – REVISED JULY 2016
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Submit Documentation Feedback
Copyright © 2006–2016, Texas Instruments Incorporated
Product Folder Links: OPA827
27
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA827AID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
827
A
OPA827AIDG4
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
827
A
OPA827AIDGKR
ACTIVE
VSSOP
DGK
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
NSP
OPA827AIDGKT
ACTIVE
VSSOP
DGK
8
250
Green (RoHS
& no Sb/Br)
CU NIPDAU |
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
NSP
OPA827AIDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
827
A
OPA827AIDRG4
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
OPA
827
A
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
25-Oct-2016
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Jun-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
OPA827AIDGKR
VSSOP
DGK
8
OPA827AIDGKT
VSSOP
DGK
OPA827AIDR
SOIC
D
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
8
250
180.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
8
2500
330.0
12.4
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
28-Jun-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA827AIDGKR
VSSOP
DGK
8
2500
367.0
367.0
35.0
OPA827AIDGKT
VSSOP
DGK
8
250
210.0
185.0
35.0
OPA827AIDR
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
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