Arria V Device Handbook Volume 1: Device Interfaces and Integration

Arria V Device Handbook Volume 1: Device Interfaces and Integration
Arria V Device Handbook
Volume 1: Device Interfaces and Integration
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Arria V Device Handbook Volume 1: Device Interfaces and Integration
Contents
Logic Array Blocks and Adaptive Logic Modules in Arria V Devices................1-1
LAB ...............................................................................................................................................................1-1
MLAB ................................................................................................................................................1-2
Local and Direct Link Interconnects ............................................................................................1-4
LAB Control Signals........................................................................................................................1-5
ALM Resources ...............................................................................................................................1-7
ALM Output ....................................................................................................................................1-9
ALM Operating Modes ............................................................................................................................1-10
Normal Mode ................................................................................................................................1-10
Extended LUT Mode ....................................................................................................................1-11
Arithmetic Mode ...........................................................................................................................1-11
Shared Arithmetic Mode .............................................................................................................1-12
Document Revision History.....................................................................................................................1-14
Embedded Memory Blocks in Arria V Devices..................................................2-1
Types of Embedded Memory.....................................................................................................................2-1
Embedded Memory Capacity in Arria V Devices.......................................................................2-2
Embedded Memory Design Guidelines for Arria V Devices.................................................................2-2
Guideline: Consider the Memory Block Selection......................................................................2-2
Guideline: Implement External Conflict Resolution..................................................................2-3
Guideline: Customize Read-During-Write Behavior.................................................................2-3
Guideline: Consider Power-Up State and Memory Initialization............................................2-6
Guideline: Control Clocking to Reduce Power Consumption..................................................2-7
Embedded Memory Features.....................................................................................................................2-7
Embedded Memory Configurations.............................................................................................2-9
Mixed-Width Port Configurations................................................................................................2-9
Embedded Memory Modes......................................................................................................................2-11
Embedded Memory Clocking Modes.....................................................................................................2-13
Clocking Modes for Each Memory Mode..................................................................................2-13
Asynchronous Clears in Clocking Modes..................................................................................2-14
Output Read Data in Simultaneous Read/Write.......................................................................2-14
Independent Clock Enables in Clocking Modes.......................................................................2-14
Parity Bit in Memory Blocks....................................................................................................................2-15
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Arria V Device Handbook Volume 1: Device Interfaces and Integration
TOC-3
Byte Enable in Embedded Memory Blocks............................................................................................2-15
Byte Enable Controls in Memory Blocks....................................................................................2-15
Data Byte Output...........................................................................................................................2-16
RAM Blocks Operations...............................................................................................................2-16
Memory Blocks Packed Mode Support..................................................................................................2-16
Memory Blocks Address Clock Enable Support....................................................................................2-17
Memory Blocks Error Correction Code Support..................................................................................2-18
Error Correction Code Truth Table............................................................................................2-18
Document Revision History.....................................................................................................................2-19
Variable Precision DSP Blocks in Arria V Devices............................................3-1
Features.........................................................................................................................................................3-1
Supported Operational Modes in Arria V Devices.................................................................................3-2
Resources.......................................................................................................................................................3-5
Design Considerations................................................................................................................................3-5
Operational Modes..........................................................................................................................3-6
Internal Coefficient and Pre-Adder...............................................................................................3-6
Accumulator.....................................................................................................................................3-7
Chainout Adder................................................................................................................................3-7
Block Architecture.......................................................................................................................................3-7
Input Register Bank.......................................................................................................................3-10
Pre-Adder........................................................................................................................................3-15
Internal Coefficient........................................................................................................................3-16
Multipliers.......................................................................................................................................3-16
Adder...............................................................................................................................................3-16
Accumulator and Chainout Adder..............................................................................................3-16
Systolic Registers............................................................................................................................3-17
Double Accumulation Register....................................................................................................3-18
Output Register Bank....................................................................................................................3-18
Operational Mode Descriptions..............................................................................................................3-18
Independent Multiplier Mode.....................................................................................................3-18
Independent Complex Multiplier Mode....................................................................................3-25
Multiplier Adder Sum Mode........................................................................................................3-30
Sum of Square Mode.....................................................................................................................3-34
18 x 18 Multiplication Summed with 36-Bit Input Mode........................................................3-35
Systolic FIR Mode..........................................................................................................................3-36
Document Revision History.....................................................................................................................3-40
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TOC-4
Arria V Device Handbook Volume 1: Device Interfaces and Integration
Clock Networks and PLLs in Arria V Devices....................................................4-1
Clock Networks............................................................................................................................................4-1
Clock Resources in Arria V Devices..............................................................................................4-1
Types of Clock Networks................................................................................................................4-2
Clock Sources Per Quadrant..........................................................................................................4-5
Types of Clock Regions...................................................................................................................4-6
Clock Network Sources...................................................................................................................4-7
Clock Output Connections...........................................................................................................4-10
Clock Control Block......................................................................................................................4-10
Clock Power Down........................................................................................................................4-12
Clock Enable Signals......................................................................................................................4-13
Arria V PLLs...............................................................................................................................................4-14
PLL Physical Counters in Arria V Devices.................................................................................4-15
PLL Locations in Arria V Devices...............................................................................................4-16
PLL Migration Guidelines ...........................................................................................................4-20
Fractional PLL Architecture.........................................................................................................4-20
PLL Cascading................................................................................................................................4-21
PLL External Clock I/O Pins........................................................................................................4-21
PLL Control Signals.......................................................................................................................4-22
Clock Feedback Modes..................................................................................................................4-23
Clock Multiplication and Division..............................................................................................4-29
Programmable Phase Shift............................................................................................................4-30
Programmable Duty Cycle...........................................................................................................4-30
Clock Switchover...........................................................................................................................4-30
PLL Reconfiguration and Dynamic Phase Shift........................................................................4-35
Document Revision History.....................................................................................................................4-35
I/O Features in Arria V Devices..........................................................................5-1
I/O Resources Per Package for Arria V Devices......................................................................................5-1
I/O Vertical Migration for Arria V Devices.............................................................................................5-4
Verifying Pin Migration Compatibility........................................................................................5-5
I/O Standards Support in Arria V Devices...............................................................................................5-5
I/O Standards Support for FPGA I/O in Arria V Devices.........................................................5-6
I/O Standards Support for HPS I/O in Arria V Devices.............................................................5-7
I/O Standards Voltage Levels in Arria V Devices........................................................................5-8
MultiVolt I/O Interface in Arria V Devices...............................................................................5-10
I/O Design Guidelines for Arria V Devices............................................................................................5-11
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Arria V Device Handbook Volume 1: Device Interfaces and Integration
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Mixing Voltage-Referenced and Non-Voltage-Referenced I/O Standards...........................5-11
Guideline: Use the Same VCCPD for All I/O Banks in a Group...............................................5-12
Guideline: Ensure Compatible VCCIO and VCCPD Voltage in the Same Bank......................5-13
Guideline: VREF Pin Restrictions.................................................................................................5-13
Guideline: Observe Device Absolute Maximum Rating for 3.3 V Interfacing......................5-13
Guideline: Use PLL Integer Mode for LVDS Applications......................................................5-14
I/O Banks Locations in Arria V Devices.................................................................................................5-14
I/O Banks Groups in Arria V Devices....................................................................................................5-16
Modular I/O Banks for Arria V GX Devices..............................................................................5-16
Modular I/O Banks for Arria V GT Devices..............................................................................5-18
Modular I/O Banks for Arria V GZ Devices..............................................................................5-19
Modular I/O Banks for Arria V SX Devices...............................................................................5-20
Modular I/O Banks for Arria V ST Devices...............................................................................5-21
I/O Element Structure in Arria V Devices.............................................................................................5-21
I/O Buffer and Registers in Arria V Devices..............................................................................5-22
Programmable IOE Features in Arria V Devices..................................................................................5-23
Programmable Current Strength.................................................................................................5-24
Programmable Output Slew-Rate Control.................................................................................5-25
Programmable IOE Delay.............................................................................................................5-26
Programmable Output Buffer Delay...........................................................................................5-26
Programmable Pre-Emphasis......................................................................................................5-26
Programmable Differential Output Voltage..............................................................................5-27
I/O Pins Features for Arria V Devices....................................................................................................5-28
Open-Drain Output.......................................................................................................................5-28
Bus-Hold Circuitry........................................................................................................................5-29
Pull-up Resistor..............................................................................................................................5-29
On-Chip I/O Termination in Arria V Devices......................................................................................5-29
RS OCT without Calibration in Arria V Devices.......................................................................5-30
RS OCT with Calibration in Arria V Devices.............................................................................5-31
RT OCT with Calibration in Arria V Devices............................................................................5-33
Dynamic OCT in Arria V Devices...............................................................................................5-35
LVDS Input RD OCT in Arria V Devices...................................................................................5-36
OCT Calibration Block in Arria V Devices................................................................................5-36
External I/O Termination for Arria V Devices......................................................................................5-39
Single-ended I/O Termination.....................................................................................................5-40
Differential I/O Termination.......................................................................................................5-42
Document Revision History.....................................................................................................................5-47
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TOC-6
Arria V Device Handbook Volume 1: Device Interfaces and Integration
High-Speed Differential I/O Interfaces and DPA in Arria V Devices...............6-1
Dedicated High-Speed Circuitries in Arria V Devices...........................................................................6-1
SERDES and DPA Bank Locations in Arria V Devices..............................................................6-2
LVDS SERDES Circuitry.................................................................................................................6-3
True LVDS Buffers in Arria V Devices.........................................................................................6-4
Emulated LVDS Buffers in Arria V Devices................................................................................6-6
High-Speed I/O Design Guidelines for Arria V Devices........................................................................6-7
PLLs and Clocking for Arria V Devices........................................................................................6-7
LVDS Interface with External PLL Mode.....................................................................................6-7
Pin Placement Guidelines for DPA and Non-DPA Differential Channels...........................6-11
Differential Transmitter in Arria V Devices..........................................................................................6-17
Transmitter Blocks.........................................................................................................................6-17
Transmitter Clocking....................................................................................................................6-18
Serializer Bypass for DDR and SDR Operations.......................................................................6-19
Programmable Differential Output Voltage..............................................................................6-19
Programmable Pre-Emphasis......................................................................................................6-20
Differential Receiver in Arria V Devices................................................................................................6-21
Receiver Blocks in Arria V Devices.............................................................................................6-21
Receiver Modes in Arria V Devices.............................................................................................6-25
Receiver Clocking for Arria V Devices.......................................................................................6-27
Differential I/O Termination for Arria V Devices....................................................................6-28
Source-Synchronous Timing Budget......................................................................................................6-29
Differential Data Orientation.......................................................................................................6-29
Differential I/O Bit Position.........................................................................................................6-29
Transmitter Channel-to-Channel Skew.....................................................................................6-31
Receiver Skew Margin for Non-DPA Mode..............................................................................6-31
Document Revision History.....................................................................................................................6-33
External Memory Interfaces in Arria V Devices.................................................7-1
External Memory Performance..................................................................................................................7-2
HPS External Memory Performance.........................................................................................................7-2
Memory Interface Pin Support in Arria V Devices.................................................................................7-3
Guideline: Using DQ/DQS Pins....................................................................................................7-3
DQ/DQS Bus Mode Pins for Arria V Devices.............................................................................7-4
DQ/DQS Groups in Arria V GX....................................................................................................7-5
DQ/DQS Groups in Arria V GT....................................................................................................7-7
DQ/DQS Groups in Arria V GZ....................................................................................................7-8
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Arria V Device Handbook Volume 1: Device Interfaces and Integration
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DQ/DQS Groups in Arria V SX.....................................................................................................7-8
DQ/DQS Groups in Arria V ST.....................................................................................................7-9
External Memory Interface Features in Arria V Devices.......................................................................7-9
UniPHY IP......................................................................................................................................7-10
External Memory Interface Datapath.........................................................................................7-10
DQS Phase-Shift Circuitry............................................................................................................7-12
PHY Clock (PHYCLK) Networks...............................................................................................7-19
DQS Logic Block............................................................................................................................7-21
Leveling Circuitry for Arria V GZ Devices................................................................................7-23
Dynamic OCT Control.................................................................................................................7-25
IOE Registers..................................................................................................................................7-25
Delay Chains...................................................................................................................................7-28
I/O and DQS Configuration Blocks............................................................................................7-30
Hard Memory Controller.........................................................................................................................7-31
Features of the Hard Memory Controller..................................................................................7-31
Multi-Port Front End....................................................................................................................7-33
Bonding Support............................................................................................................................7-33
Hard Memory Controller Width for Arria V GX.....................................................................7-36
Hard Memory Controller Width for Arria V GT.....................................................................7-37
Hard Memory Controller Width for Arria V SX......................................................................7-37
Hard Memory Controller Width for Arria V ST.......................................................................7-38
Document Revision History.....................................................................................................................7-39
Configuration, Design Security, and Remote System Upgrades in Arria V
Devices.............................................................................................................8-1
Enhanced Configuration and Configuration via Protocol.....................................................................8-2
MSEL Pin Settings........................................................................................................................................8-3
Configuration Sequence..............................................................................................................................8-4
Power Up...........................................................................................................................................8-5
Reset...................................................................................................................................................8-6
Configuration...................................................................................................................................8-6
Configuration Error Handling.......................................................................................................8-7
Initialization......................................................................................................................................8-7
User Mode.........................................................................................................................................8-7
Device Configuration Pins..........................................................................................................................8-7
Configuration Pin Options in the Quartus II Software..............................................................8-9
Fast Passive Parallel Configuration.........................................................................................................8-10
Fast Passive Parallel Single-Device Configuration....................................................................8-11
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Arria V Device Handbook Volume 1: Device Interfaces and Integration
Fast Passive Parallel Multi-Device Configuration.....................................................................8-11
Active Serial Configuration......................................................................................................................8-13
DATA Clock (DCLK)....................................................................................................................8-13
Active Serial Single-Device Configuration.................................................................................8-14
Active Serial Multi-Device Configuration..................................................................................8-15
Estimating the Active Serial Configuration Time.....................................................................8-16
Using EPCS and EPCQ Devices..............................................................................................................8-16
Controlling EPCS and EPCQ Devices........................................................................................8-17
Trace Length and Loading............................................................................................................8-17
Programming EPCS and EPCQ Devices....................................................................................8-17
Passive Serial Configuration.....................................................................................................................8-21
Passive Serial Single-Device Configuration Using an External Host.....................................8-22
Passive Serial Single-Device Configuration Using an Altera Download Cable....................8-22
Passive Serial Multi-Device Configuration................................................................................8-23
JTAG Configuration..................................................................................................................................8-25
JTAG Single-Device Configuration.............................................................................................8-26
JTAG Multi-Device Configuration.............................................................................................8-28
CONFIG_IO JTAG Instruction...................................................................................................8-28
Configuration Data Compression...........................................................................................................8-29
Enabling Compression Before Design Compilation.................................................................8-29
Enabling Compression After Design Compilation...................................................................8-29
Using Compression in Multi-Device Configuration................................................................8-29
Remote System Upgrades.........................................................................................................................8-30
Configuration Images....................................................................................................................8-31
Configuration Sequence in the Remote Update Mode.............................................................8-31
Remote System Upgrade Circuitry..............................................................................................8-32
Enabling Remote System Upgrade Circuitry.............................................................................8-32
Remote System Upgrade Registers..............................................................................................8-33
Remote System Upgrade State Machine.....................................................................................8-35
User Watchdog Timer...................................................................................................................8-35
Design Security...........................................................................................................................................8-35
ALTCHIP_ID Megafunction.......................................................................................................8-36
JTAG Secure Mode........................................................................................................................8-36
Security Key Types.........................................................................................................................8-37
Security Modes...............................................................................................................................8-38
Design Security Implementation Steps.......................................................................................8-38
Document Revision History.....................................................................................................................8-39
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Arria V Device Handbook Volume 1: Device Interfaces and Integration
TOC-9
SEU Mitigation for Arria V Devices...................................................................9-1
Error Detection Features.............................................................................................................................9-1
Configuration Error Detection..................................................................................................................9-1
User Mode Error Detection........................................................................................................................9-1
Specifications................................................................................................................................................9-2
Minimum EMR Update Interval...................................................................................................9-2
Error Detection Frequency.............................................................................................................9-3
CRC Calculation Time....................................................................................................................9-3
Using Error Detection Features in User Mode........................................................................................9-4
Enabling Error Detection................................................................................................................9-4
CRC_ERROR Pin.............................................................................................................................9-5
Error Detection Registers................................................................................................................9-5
Error Detection Process..................................................................................................................9-7
Testing the Error Detection Block.................................................................................................9-8
Document Revision History.......................................................................................................................9-9
JTAG Boundary-Scan Testing in Arria V Devices............................................10-1
BST Operation Control ............................................................................................................................10-1
IDCODE .........................................................................................................................................10-1
Supported JTAG Instruction .......................................................................................................10-3
JTAG Secure Mode .......................................................................................................................10-6
JTAG Private Instruction .............................................................................................................10-7
I/O Voltage for JTAG Operation ............................................................................................................10-7
Performing BST .........................................................................................................................................10-8
Enabling and Disabling IEEE Std. 1149.1 BST Circuitry ....................................................................10-9
Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing.....................................................................10-9
IEEE Std. 1149.1 Boundary-Scan Register ..........................................................................................10-10
Boundary-Scan Cells of an Arria V Device I/O Pin................................................................10-10
IEEE Std. 1149.6 Boundary-Scan Register...........................................................................................10-12
Document Revision History...................................................................................................................10-14
Power Management in Arria V Devices............................................................11-1
Power Consumption..................................................................................................................................11-1
Dynamic Power Equation.............................................................................................................11-2
Programmable Power Technology..........................................................................................................11-2
Temperature Sensing Diode.....................................................................................................................11-3
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Arria V Device Handbook Volume 1: Device Interfaces and Integration
Internal Temperature Sensing Diode..........................................................................................11-3
External Temperature Sensing Diode.........................................................................................11-4
Hot-Socketing Feature..............................................................................................................................11-5
Hot-Socketing Implementation...............................................................................................................11-6
Arria V GX, GT, SX, and ST Power-Up Sequence................................................................................11-7
Arria V GZ Power-Up Sequence.............................................................................................................11-8
Power-On Reset Circuitry........................................................................................................................11-9
Power Supplies Monitored and Not Monitored by the POR Circuitry...............................11-11
Document Revision History...................................................................................................................11-12
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1
Logic Array Blocks and Adaptive Logic Modules
in Arria V Devices
2014.01.10
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This chapter describes the features of the logic array block (LAB) in the Arria® V core fabric.
The LAB is composed of basic building blocks known as adaptive logic modules (ALMs) that you can
configure to implement logic functions, arithmetic functions, and register functions.
You can use a quarter of the available LABs in the Arria V devices as a memory LAB (MLAB).
The Quartus® II software and other supported third-party synthesis tools, in conjunction with parameterized
functions such as the library of parameterized modules (LPM), automatically choose the appropriate mode
for common functions such as counters, adders, subtractors, and arithmetic functions.
This chapter contains the following sections:
• LAB
• ALM Operating Modes
Related Information
Arria V Device Handbook: Known Issues
Lists the planned updates to the Arria V Device Handbook chapters.
LAB
The LABs are configurable logic blocks that consist of a group of logic resources. Each LAB contains dedicated
logic for driving control signals to its ALMs.
MLAB is a superset of the LAB and includes all the LAB features.
© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words
and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other
words and logos identified as trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with
Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes
no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
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MLAB
Figure 1-1: LAB Structure and Interconnects Overview in Arria V Devices
This figure shows an overview of the Arria V LAB and MLAB structure with the LAB interconnects.
C2/C4
C12
Row Interconnects of
Variable Speed and Length
R14
R3/R6
ALMs
Connects to adjacent
LABs, memory blocks,
digital signal processing
(DSP) blocks, or I/O
element (IOE) outputs.
Direct-Link
Interconnect from
Adjacent Block
Direct-Link
Interconnect from
Adjacent Block
Direct-Link
Interconnect to
Adjacent Block
Direct-Link
Interconnect to
Adjacent Block
Local Interconnect
LAB
MLAB
Fast Local Interconnect Is Driven
from Either Sides by Column Interconnect
and LABs, and from Above by Row Interconnect
Column Interconnects of
Variable Speed and Length
MLAB
Each MLAB supports a maximum of 640 bits of simple dual-port SRAM.
You can configure each ALM in an MLAB in the following configurations:
• A 32 x 2 memory block, resulting in a configuration of 32 x 20 simple dual-port SRAM block for
Arria V GX, GT, SX, and ST devices
• Either a 64 × 1 or a 32 × 2 block, resulting in a configuration of either a 64 × 10 or a 32 × 20 simple dualport SRAM block for Arria V GZ devices
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MLAB
1-3
Figure 1-2: LAB and MLAB Structure for Arria V GX, GT, SX, and, ST Devices
You can use an MLAB
ALM as a regular LAB
ALM or configure it as a
dual-port SRAM.
LUT-Based-32 x 2
Simple Dual-Port SRAM
ALM
LUT-Based-32 x 2
Simple Dual-Port SRAM
ALM
LUT-Based-32 x 2
Simple Dual-Port SRAM
ALM
LUT-Based-32 x 2
Simple Dual-Port SRAM
ALM
LUT-Based-32 x 2
Simple Dual-Port SRAM
ALM
LAB Control Block
You can use an MLAB
ALM as a regular LAB
ALM or configure it as a
dual-port SRAM.
LUT-Based-32 x 2
Simple Dual-Port SRAM
ALM
LUT-Based-32 x 2
Simple Dual-Port SRAM
ALM
LUT-Based-32 x 2
Simple Dual-Port SRAM
ALM
LUT-Based-32 x 2
Simple Dual-Port SRAM
ALM
LUT-Based-32 x 2
Simple Dual-Port SRAM
ALM
MLAB
Logic Array Blocks and Adaptive Logic Modules in Arria V Devices
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LAB Control Block
LAB
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Local and Direct Link Interconnects
Figure 1-3: LAB and MLAB Structure for Arria V GZ Devices
You can use an MLAB
ALM as a regular LAB
ALM or configure it as a
dual-port SRAM.
LUT-Based-64 x 1
Simple Dual-Port SRAM
ALM
LUT-Based-64 x 1
Simple Dual-Port SRAM
ALM
LUT-Based-64 x 1
Simple Dual-Port SRAM
ALM
LUT-Based-64 x 1
Simple Dual-Port SRAM
ALM
LUT-Based-64 x 1
Simple Dual-Port SRAM
ALM
LAB Control Block
You can use an MLAB
ALM as a regular LAB
ALM or configure it as a
dual-port SRAM.
LAB Control Block
LUT-Based-64 x 1
Simple Dual-Port SRAM
ALM
LUT-Based-64 x 1
Simple Dual-Port SRAM
ALM
LUT-Based-64 x 1
Simple Dual-Port SRAM
ALM
LUT-Based-64 x 1
Simple Dual-Port SRAM
ALM
LUT-Based-64 x 1
Simple Dual-Port SRAM
ALM
MLAB
LAB
Local and Direct Link Interconnects
Each LAB can drive 30 ALMs through fast-local and direct-link interconnects. Ten ALMs are in any given
LAB and ten ALMs are in each of the adjacent LABs.
The local interconnect can drive ALMs in the same LAB using column and row interconnects and ALM
outputs in the same LAB.
Neighboring LABs, MLABs, M20K and M10K blocks, or digital signal processing (DSP) blocks from the left
or right can also drive the LAB’s local interconnect using the direct link connection.
The direct link connection feature minimizes the use of row and column interconnects, providing higher
performance and flexibility.
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LAB Control Signals
1-5
Figure 1-4: LAB Fast Local and Direct Link Interconnects for Arria V Devices
Direct Link Interconnect from
Left LAB, Memory Block,
DSP Block, or IOE Output
Direct Link Interconnect from
Right LAB, Memory Block,
DSP Block, or IOE Output
ALMs
ALMs
Direct Link
Interconnect
to Left
Direct Link
Interconnect
to Right
Fast Local
Interconnect
MLAB
LAB
LAB Control Signals
Each LAB contains dedicated logic for driving the control signals to its ALMs, and has two unique clock
sources and three clock enable signals.
The LAB control block generates up to three clocks using the two clock sources and three clock enable
signals. Each clock and the clock enable signals are linked.
De-asserting the clock enable signal turns off the corresponding LAB-wide clock.
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LAB Control Signals
Figure 1-5: LAB-Wide Control Signals for Arria V GX, GT, SX, and, ST Devices
This figure shows the clock sources and clock enable signals in a LAB.
There are two unique
clock signals per LAB.
6
Dedicated Row
LAB Clocks
6
6
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
labclk0
labclk1
labclkena0
or asyncload
or labpreset
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labclr1
syncload
labclk2
labclkena1
labclkena2
labclr0
synclr
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ALM Resources
Figure 1-6: LAB-Wide Control Signals for Arria V GZ Devices
This figure shows the clock sources and clock enable signals in a LAB.
There are two unique
clock signals per LAB.
6
Dedicated Row
LAB Clocks
6
6
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
Local Interconnect
labclk0
labclk1
labclkena0
or asyncload
or labpreset
labclr1
syncload
labclk2
labclkena1
labclkena2
labclr0
synclr
ALM Resources
One ALM contains four programmable registers. Each register has the following ports:
•
•
•
•
Data
Clock
Synchronous and asynchronous clear
Synchronous load
Global signals, general-purpose I/O (GPIO) pins, or any internal logic can drive the clock and clear control
signals of an ALM register.
GPIO pins or internal logic drives the clock enable signal.
For combinational functions, the registers are bypassed and the output of the look-up table (LUT) drives
directly to the outputs of an ALM.
Note: The Quartus II software automatically configures the ALMs for optimized performance.
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ALM Resources
Figure 1-7: ALM High-Level Block Diagram for Arria V GX, GT, SX, and, ST Devices
shared_arith_in
carry_in
Combinational/
Memory ALUT0
dataf0
6-Input
LUT
datae0
labclk
adder0
D
Q
dataa
reg0
datab
D
Q
reg1
Combinational/
Memory ALUT1
To General or
Local Routing
datac
adder1
datad
D
6-Input
LUT
datae1
Q
reg2
dataf1
D
shared_arith_out
Q
reg3
carry_out
Figure 1-8: ALM High-Level Block Diagram for Arria V GZ Devices
shared_arith_in
carry_in
Combinational/
Memory ALUT0
labclk
dataf0
datae0
6-Input LUT
adder0
dataa
reg0
datab
reg1
datac
adder1
datad
datae1
To General or
Local Routing
6-Input LUT
reg2
dataf1
Combinational/
Memory ALUT1
shared_arith_out
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reg3
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ALM Output
1-9
ALM Output
The general routing outputs in each ALM drive the local, row, and column routing resources. Two ALM
outputs can drive column, row, or direct link routing connections, and one of these ALM outputs can also
drive local interconnect resources.
The LUT, adder, or register output can drive the ALM outputs. The LUT or adder can drive one output
while the register drives another output.
Register packing improves device utilization by allowing unrelated register and combinational logic to be
packed into a single ALM. Another mechanism to improve fitting is to allow the register output to feed back
into the look-up table (LUT) of the same ALM so that the register is packed with its own fan-out LUT. The
ALM can also drive out registered and unregistered versions of the LUT or adder output.
Figure 1-9: ALM Connection Details for Arria V GX, GT, SX, and, ST Devices
syncload
aclr[1:0]
clk[2:0] sclr
shared_arith_in carry_in
dataf0
datae0
dataa
datab
datac0
GND
4-Input
LUT
+
D
3-Input
LUT
3-Input
LUT
D
CLR
Q
CLR
Q
Row, Column
Direct Link Routing
Row, Column
Direct Link Routing
Local
Interconnect
datac1
4-Input
LUT
D
+
CLR
Q
Row, Column
Direct Link Routing
3-Input
LUT
3-Input
LUT
VCC
D
CLR
Q
Row, Column
Direct Link Routing
Local
Interconnect
datae1
dataf1
shared_arith_out carry_out
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ALM Operating Modes
Figure 1-10: ALM Connection Details for Arria V GZ Devices
syncload
aclr[1:0]
shared_arith_in
carry_in
clk[2:0] sclr
dataf0
datae0
dataa
datab
datac0
GND
4-Input
LUT
+
D
CLR
Q
3-Input
LUT
Row, Column
Direct Link Routing
3
3-Input
LUT
D
4-Input
LUT
datac1
CLR
Q
Row, Column
Direct Link Routing
Q
Row, Column
Direct Link Routing
Q
Row, Column
Direct Link Routing
3
D
+
CLR
3-Input
LUT
3-Input
LUT
D
VCC
CLR
datae1
dataf1
shared_arith_out
carry_out
ALM Operating Modes
The Arria V ALM operates in any of the following modes:
•
•
•
•
Normal mode
Extended LUT mode
Arithmetic mode
Shared arithmetic mode
Normal Mode
Normal mode allows two functions to be implemented in one Arria V ALM, or a single function of up to
six inputs.
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Extended LUT Mode
1-11
Up to eight data inputs from the LAB local interconnect are inputs to the combinational logic.
The ALM can support certain combinations of completely independent functions and various combinations
of functions that have common inputs.
Extended LUT Mode
In this mode, if the 7-input function is unregistered, the unused eighth input is available for register packing.
Functions that fit into the template, as shown in the following figure, often appear in designs as “if-else”
statements in Verilog HDL or VHDL code.
Figure 1-11: Template for Supported 7-Input Functions in Extended LUT Mode for Arria V Devices
datae0
datac
dataa
datab
datad
dataf0
5-Input
LUT
combout0
D
datae1
5-Input
LUT
Q
To General or
Local Routing
reg0
dataf1
This input is available
for register packing.
Arithmetic Mode
The ALM in arithmetic mode uses two sets of two 4-input LUTs along with two dedicated full adders.
The dedicated adders allow the LUTs to perform pre-adder logic; therefore, each adder can add the output
of two 4-input functions.
The ALM supports simultaneous use of the adder’s carry output along with combinational logic outputs.
The adder output is ignored in this operation.
Using the adder with the combinational logic output provides resource savings of up to 50% for functions
that can use this mode.
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Shared Arithmetic Mode
Figure 1-12: ALM in Arithmetic Mode for Arria V Devices
carry_in
datae0
adder0
4-Input
LUT
dataf0
datac
datab
dataa
datad
datae1
dataf1
reg0
4-Input
LUT
adder1
4-Input
LUT
reg1
To General or
Local Routing
reg2
4-Input
LUT
carry_out
reg3
Carry Chain
The carry chain provides a fast carry function between the dedicated adders in arithmetic or shared arithmetic
mode.
The two-bit carry select feature in Arria V devices halves the propagation delay of carry chains within the
ALM. Carry chains can begin in either the first ALM or the fifth ALM in a LAB. The final carry-out signal
is routed to an ALM, where it is fed to local, row, or column interconnects.
To avoid routing congestion in one small area of the device when a high fan-in arithmetic function is
implemented, the LAB can support carry chains that only use either the top half or bottom half of the LAB
before connecting to the next LAB. This leaves the other half of the ALMs in the LAB available for
implementing narrower fan-in functions in normal mode. Carry chains that use the top five ALMs in the
first LAB carry into the top half of the ALMs in the next LAB in the column. Carry chains that use the bottom
five ALMs in the first LAB carry into the bottom half of the ALMs in the next LAB within the column. You
can bypass the top-half of the LAB columns and bottom-half of the MLAB columns.
The Quartus II Compiler creates carry chains longer than 20 ALMs (10 ALMs in arithmetic or shared
arithmetic mode) by linking LABs together automatically. For enhanced fitting, a long carry chain runs
vertically, allowing fast horizontal connections to the TriMatrix memory and DSP blocks. A carry chain can
continue as far as a full column.
Shared Arithmetic Mode
The ALM in shared arithmetic mode can implement a 3-input add in the ALM.
This mode configures the ALM with four 4-input LUTs. Each LUT either computes the sum of three inputs
or the carry of three inputs. The output of the carry computation is fed to the next adder using a dedicated
connection called the shared arithmetic chain.
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Shared Arithmetic Mode
1-13
Figure 1-13: ALM in Shared Arithmetic Mode for Arria V Devices
shared_arith_in
carry_in
labclk
4-Input
LUT
datae0
datac
datab
dataa
reg0
4-Input
LUT
reg1
datad
datae1
4-Input
LUT
To General or
Local Routing
reg2
4-Input
LUT
reg3
shared_arith_out
carry_out
Shared Arithmetic Chain
The shared arithmetic chain available in enhanced arithmetic mode allows the ALM to implement a 3-input
adder. This significantly reduces the resources necessary to implement large adder trees or correlator
functions.
The shared arithmetic chain can begin in either the first or sixth ALM in a LAB.
Similar to carry chains, the top and bottom half of the shared arithmetic chains in alternate LAB columns
can be bypassed. This capability allows the shared arithmetic chain to cascade through half of the ALMs in
an LAB while leaving the other half available for narrower fan-in functionality. In every LAB, the column
is top-half bypassable; while in MLAB, columns are bottom-half bypassable.
The Quartus II Compiler creates shared arithmetic chains longer than 20 ALMs (10 ALMs in arithmetic or
shared arithmetic mode) by linking LABs together automatically. To enhance fitting, a long shared arithmetic
chain runs vertically, allowing fast horizontal connections to the TriMatrix memory and DSP blocks. A
shared arithmetic chain can continue as far as a full column.
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Document Revision History
Document Revision History
Date
Version
January 2014
2014.01.10
Changes
Added multiplexers for the bypass paths and register outputs in the
following diagrams:
• ALM High-Level Block Diagram for Arria V GX, GT, SX, and ST Devices
• ALM High-Level Block Diagram for Arria V GZ Devices
• Template for Supported 7-Input Functions in Extended LUT Mode for
Arria V Devices
• ALM in Arithmetic Mode for Arria V Devices
• ALM in Shared Arithmetic Mode for Arria V Devices
May 2013
2013.05.06
• Added link to the known document issues in the Knowledge Base.
• Updated local and direct link interconnects section to add M20K
memory block.
• Removed register chain outputs information in ALM output section.
• Removed reg_chain_in and reg_chain_out ports in ALM high-level
block diagram and ALM connection details diagram for Arria V GX,
GT, SX, and ST devices.
November 2012
2012.11.19
•
•
•
•
•
June 2012
2.0
Added MLAB structure for Arria V GZ devices.
Added LAB-wide control signals diagram for Arria V GZ devices.
Added ALM high level block diagram for Arria V GZ devices.
Added ALM connection details diagram for Arria V GZ devices.
Reorganized content and updated template.
Updated for the Quartus II software v12.0 release:
• Restructured chapter.
• Updated Figure 1–6.
November 2011
1.1
Restructured chapter.
May 2011
1.0
Initial release.
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The embedded memory blocks in the devices are flexible and designed to provide an optimal amount of
small- and large-sized memory arrays to fit your design requirements.
Related Information
Arria V Device Handbook: Known Issues
Lists the planned updates to the Arria V Device Handbook chapters.
Types of Embedded Memory
The Arria V devices contain two types of memory blocks:
• 20 Kb M20K or 10 Kb M10K blocks—blocks of dedicated memory resources. The M20K and M10K
blocks are ideal for larger memory arrays while still providing a large number of independent ports.
• 640 bit memory logic array blocks (MLABs)—enhanced memory blocks that are configured from dualpurpose logic array blocks (LABs). The MLABs are ideal for wide and shallow memory arrays. The MLABs
are optimized for implementation of shift registers for digital signal processing (DSP) applications, wide
shallow FIFO buffers, and filter delay lines. Each MLAB is made up of ten adaptive logic modules (ALMs).
In the Arria V devices, you can configure these ALMs as ten 32 x 2 blocks, giving you one 32 x 20 simple
dual-port SRAM block per MLAB. You can also configure these ALMs, in Arria V GZ devices, as ten
64 x 1 blocks, giving you one 64 x 10 simple dual-port SRAM block per MLAB.
© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words
and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other
words and logos identified as trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with
Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes
no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
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Embedded Memory Capacity in Arria V Devices
Embedded Memory Capacity in Arria V Devices
Table 2-1: Embedded Memory Capacity and Distribution in Arria V Devices
M20K
Variant
Arria V GX
Arria V GT
Arria V GZ
Arria V SX
Arria V ST
M10K
MLAB
Member
Code
Block
RAM Bit
(Kb)
Block
RAM Bit
(Kb)
Block
RAM Bit
(Kb)
Total RAM Bit
(Kb)
A1
—
—
800
8,000
741
463
8,463
A3
—
—
1,051
10,510
1538
961
11,471
A5
—
—
1,180
11,800
1877
1,173
12,973
A7
—
—
1,366
13,660
2317
1,448
15,108
B1
—
—
1,510
15,100
2964
1,852
16,952
B3
—
—
1,726
17,260
3357
2,098
19,358
B5
—
—
2,054
20,540
4052
2,532
23,072
B7
—
—
2,414
24,140
4650
2,906
27,046
C3
—
—
1,051
10,510
1538
961
11,471
C7
—
—
1,366
13,660
2317
1,448
15,108
D3
—
—
1,726
17,260
3357
2,098
19,358
D7
—
—
2,414
24,140
4650
2,906
27,046
E1
585
11,700
—
—
4,151
2,594
14,294
E3
957
19,140
—
—
6,792
4,245
23,385
E5
1,440
28,800
—
—
7,548
4,718
33,518
E7
1,700
34,000
—
—
8,490
5,306
39,306
B3
—
—
1,729
17,290
3223
2,014
19,304
B5
—
—
2,282
22,820
4253
2,658
25,478
D3
—
—
1,729
17,290
3223
2,014
19,304
D5
—
—
2,282
22,820
4253
2,658
25,478
Embedded Memory Design Guidelines for Arria V Devices
There are several considerations that require your attention to ensure the success of your designs. Unless
noted otherwise, these design guidelines apply to all variants of this device family.
Guideline: Consider the Memory Block Selection
The Quartus II software automatically partitions the user-defined memory into the memory blocks based
on your design's speed and size constraints. For example, the Quartus II software may spread out the memory
across multiple available memory blocks to increase the performance of the design.
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Guideline: Implement External Conflict Resolution
2-3
To assign the memory to a specific block size manually, use the RAM megafunction in the MegaWizard™
Plug-In Manager.
For the memory logic array blocks (MLAB), you can implement single-port SRAM through emulation using
the Quartus II software. Emulation results in minimal additional use of logic resources.
Because of the dual-purpose architecture of the MLAB, only data input and output registers are available in
the block. The MLABs gain read address registers from the ALMs. However, the write address and read data
registers are internal to the MLABs.
Guideline: Implement External Conflict Resolution
In the true dual-port RAM mode, you can perform two write operations to the same memory location.
However, the memory blocks do not have internal conflict resolution circuitry. To avoid unknown data
being written to the address, implement external conflict resolution logic to the memory block.
Guideline: Customize Read-During-Write Behavior
Customize the read-during-write behavior of the memory blocks to suit your design requirements.
Figure 2-1: Read-During-Write Data Flow
This figure shows the difference between the two types of read-during-write operations available—same
port and mixed port.
FPGA Device
Port A
data in
Port B
data in
Mixed-port
data flow
Same-port
data flow
Port A
data out
Port B
data out
Same-Port Read-During-Write Mode
The same-port read-during-write mode applies to a single-port RAM or the same port of a true dual-port
RAM.
Table 2-2: Output Modes for Embedded Memory Blocks in Same-Port Read-During-Write Mode
This table lists the available output modes if you select the embedded memory blocks in the same-port
read-during-write mode.
Output Mode
"new data"
Memory Type
M20K, M10K
(flow-through)
"don't care"
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Description
The new data is available on the rising edge of
the same clock cycle on which the new data is
written.
The RAM outputs "don't care" values for a
read-during-write operation.
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Mixed-Port Read-During-Write Mode
Figure 2-2: Same-Port Read-During-Write: New Data Mode
This figure shows sample functional waveforms of same-port read-during-write behavior in the “new data”
mode.
clk_a
0A
address
0B
rden
wren
byteena
data_a
11
B456
A123
q_a (asynch)
A123
DDDD
C789
B456
C789
EEEE
DDDD
FFFF
EEEE
FFFF
Mixed-Port Read-During-Write Mode
The mixed-port read-during-write mode applies to simple and true dual-port RAM modes where two ports
perform read and write operations on the same memory address using the same clock—one port reading
from the address, and the other port writing to it.
Table 2-3: Output Modes for RAM in Mixed-Port Read-During-Write Mode
Output Mode
"new data"
Memory Type
MLAB
Description
A read-during-write operation to different ports causes the
MLAB registered output to reflect the “new data” on the
next rising edge after the data is written to the MLAB
memory.
This mode is available only if the output is registered.
"old data"
M20K, M10K,
MLAB
A read-during-write operation to different ports causes the
RAM output to reflect the “old data” value at the particular
address.
For MLAB, this mode is available only if the output is
registered.
"don't care"
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M20K, M10K,
MLAB
The RAM outputs “don’t care” or “unknown” value.
• For M20K or M10K memory, the Quartus II software
does not analyze the timing between write and read
operations.
• For MLAB, the Quartus II software analyzes the timing
between write and read operations by default. To disable
this behavior, turn on the Do not analyze the timing
between write and read operation. Metastability issues
are prevented by never writing and reading at the
same address at the same time option.
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Mixed-Port Read-During-Write Mode
Output Mode
Memory Type
"constrained don't care"
MLAB
2-5
Description
The RAM outputs “don’t care” or “unknown” value. The
Quartus II software analyzes the timing between write and
read operations in the MLAB.
Figure 2-3: Mixed-Port Read-During-Write: New Data Mode
This figure shows a sample functional waveform of mixed-port read-during-write behavior for the “new
data” mode.
clk_a&b
wren_a
A0
address_a
data_a
AAAA
A1
BBBB
CCCC
DDDD
EEEE
FFFF
11
byteena_a
rden_b
address_b
q_b (registered)
A0
A1
AAAA
XXXX
BBBB
CCCC
DDDD
EEEE
FFFF
Figure 2-4: Mixed-Port Read-During-Write: Old Data Mode
This figure shows a sample functional waveform of mixed-port read-during-write behavior for the “old data”
mode.
clk_a&b
wren_a
address_a
data_a
A0
AAAA
A1
BBBB
CCCC
byteena_a
DDDD
FFFF
EEEE
11
rden_b
address_b
q_b (asynch)
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A0
A0 (old data)
A1
AAAA
BBBB
A1 (old data)
DDDD
EEEE
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Guideline: Consider Power-Up State and Memory Initialization
Figure 2-5: Mixed-Port Read-During-Write: Don’t Care or Constrained Don’t Care Mode
This figure shows a sample functional waveform of mixed-port read-during-write behavior for the “don’t
care” or “constrained don’t care” mode.
clk_a&b
wren_a
address_a
data_a
byteena_a
A1
A0
AAAA
BBBB
CCCC
11
01
10
DDDD
EEEE
FFFF
11
rden_b
address_b
q_b (asynch)
A1
A0
XXXX (unknown data)
In the dual-port RAM mode, the mixed-port read-during-write operation is supported if the input registers
have the same clock. The output value during the operation is “unknown.”
Related Information
Internal Memory (RAM and ROM) User Guide
Provides more information about the RAM megafunction that controls the read-during-write behavior.
Guideline: Consider Power-Up State and Memory Initialization
Consider the power up state of the different types of memory blocks if you are designing logic that evaluates
the initial power-up values, as listed in the following table.
Table 2-4: Initial Power-Up Values of Embedded Memory Blocks
Memory Type
MLAB
M20K, M10K
Output Registers
Power Up Value
Used
Zero (cleared)
Bypassed
Read memory contents
Used
Zero (cleared)
Bypassed
Zero (cleared)
By default, the Quartus II software initializes the RAM cells in Arria V devices to zero unless you specify a
.mif.
All memory blocks support initialization with a .mif. You can create .mif files in the Quartus II software
and specify their use with the RAM megafunction when you instantiate a memory in your design. Even if a
memory is pre-initialized (for example, using a .mif), it still powers up with its output cleared.
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Guideline: Control Clocking to Reduce Power Consumption
2-7
Related Information
• Internal Memory (RAM and ROM) User Guide
Provides more information about .mif files.
• Quartus II Handbook
Provides more information about .mif files.
Guideline: Control Clocking to Reduce Power Consumption
Reduce AC power consumption in your design by controlling the clocking of each memory block:
• Use the read-enable signal to ensure that read operations occur only when necessary. If your design does
not require read-during-write, you can reduce your power consumption by deasserting the read-enable
signal during write operations, or during the period when no memory operations occur.
• Use the Quartus II software to automatically place any unused memory blocks in low-power mode to
reduce static power.
Embedded Memory Features
Table 2-5: Memory Features in Arria V Devices
This table summarizes the features supported by the embedded memory blocks.
Features
Maximum operating frequency
M20K, M10K
M20K—600 MHz
M10K—400 MHz
MLAB
Arria V GX, GT, SX, and
ST—500 MHz
Arria V GZ—600 MHz
Total RAM bits (including parity bits)
M20K—20,480
M10K—10,240
Parity bits
Supported
Supported
Byte enable
Supported
Supported
Packed mode
Supported
—
Address clock enable
Supported
Supported
Simple dual-port mixed width
Supported
—
True dual-port mixed width
Supported
—
FIFO buffer mixed width
Supported
—
Memory Initialization File (.mif)
Supported
Supported
Mixed-clock mode
Supported
Supported
Fully synchronous memory
Supported
Supported
—
Only for flow-through read memory
operations.
Asynchronous memory
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Embedded Memory Features
Features
M20K, M10K
MLAB
Power-up state
Output ports are
cleared.
• Registered output
ports—Cleared.
• Unregistered output ports—Read
memory contents.
Asynchronous clears
Output registers and
output latches
Output registers and output latches
Write/read operation triggering
Rising clock edges
Rising clock edges
Same-port read-during-write
• M20K—output
Output ports set to "don't care".
ports set to new
data
• M10K—output
ports set to "new
data" or "don't care"
(The "don't care" mode
applies only for the
single-port RAM
mode).
Mixed-port read-during-write
Output ports set to "old Output ports set to "old data", "new
data" or "don't care". data", "don't care", or "constrained
don't care".
ECC support
Soft IP support using
the Quartus II
software.
Soft IP support using the Quartus II
software.
Built-in support in
x32-wide simple dualport mode (M20K
only).
Related Information
Internal Memory (RAM and ROM) User Guide
Provides more information about the embedded memory features.
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Embedded Memory Configurations
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Embedded Memory Configurations
Table 2-6: Supported Embedded Memory Block Configurations for Arria V Devices
This table lists the maximum configurations supported for the embedded memory blocks. The information is
applicable only to the single-port RAM and ROM modes.
Memory Block
MLAB
M20K
M10K
Depth (bits)
Programmable Width
32
x16, x18, or x20
(1)
x10
512
x40
1K
x20
2K
x10
4K
x5
8K
x2
16K
x1
256
x40 or x32
512
x20 or x16
1K
x10 or x8
2K
x5 or x4
4K
x2
8K
x1
64
Mixed-Width Port Configurations
The mixed-width port configuration is supported in the simple dual-port RAM and true dual-port RAM
memory modes.
Note: MLABs do not support mixed-width port configurations.
Related Information
Internal Memory (RAM and ROM) User Guide
Provides more information about dual-port mixed width support.
M20K Blocks Mixed-Width Configurations
The following table lists the mixed-width configurations of the M20K blocks in the simple dual-port RAM
mode.
(1)
Available for Arria V GZ devices only.
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M10K Blocks Mixed-Width Configurations
Table 2-7: M20K Block Mixed-Width Configurations (Simple Dual-Port RAM Mode)
Read Port
Write Port
16K x 1
8K x 2
4K x 4
4K x 5
2K x 8
2K x 10
1K x 16
1K x 20 512 x 32
512 x 40
16K x 1
Yes
Yes
Yes
—
Yes
—
Yes
—
Yes
—
8K x 2
Yes
Yes
Yes
—
Yes
—
Yes
—
Yes
—
4K x 4
Yes
Yes
Yes
—
Yes
—
Yes
—
Yes
—
4K x 5
—
—
—
Yes
—
Yes
—
Yes
—
Yes
2K x 8
Yes
Yes
Yes
—
Yes
—
Yes
—
Yes
—
2K x 10
—
—
—
Yes
—
Yes
—
Yes
—
Yes
1K x 16
Yes
Yes
Yes
—
Yes
—
Yes
—
Yes
—
1K x 20
—
—
—
Yes
—
Yes
—
Yes
—
Yes
512 x 32
Yes
Yes
Yes
—
Yes
—
Yes
—
Yes
—
512 x 40
—
—
—
Yes
—
Yes
—
Yes
—
Yes
The following table lists the mixed-width configurations of the M20K blocks in true dual-port mode.
Table 2-8: M20K Block Mixed-Width Configurations (True Dual-Port Mode)
Port A
Port B
16K x 1
8K x 2
4K x 4
4K x 5
2K x 8
2K x 10
1K x 16
1K x 20
16K x 1
Yes
Yes
Yes
—
Yes
—
Yes
—
8K x 2
Yes
Yes
Yes
—
Yes
—
Yes
—
4K x 4
Yes
Yes
Yes
—
Yes
—
Yes
—
4K x 5
—
—
—
Yes
—
Yes
—
Yes
2K x 8
Yes
Yes
Yes
—
Yes
—
Yes
—
2K x 10
—
—
—
Yes
—
Yes
—
Yes
1K x 16
Yes
Yes
Yes
—
Yes
—
Yes
—
1K x 20
—
—
—
Yes
—
Yes
—
Yes
M10K Blocks Mixed-Width Configurations
Table 2-9: M10K Block Mixed-Width Configurations in Simple Dual-Port RAM Mode
Read Port
Write Port
8K x 1
4K x 2
2K x 4
2K x 5
1K x 8
8K x 1
Yes
Yes
Yes
—
Yes
—
Yes
—
Yes
—
4K x 2
Yes
Yes
Yes
—
Yes
—
Yes
—
Yes
—
2K x 4
Yes
Yes
Yes
—
Yes
—
Yes
—
Yes
—
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1k x 10 512 x 16 512 x 20 256 x 32
256 x 40
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Embedded Memory Modes
Read Port
Write Port
8K x 1
4K x 2
2K x 4
2K x 5
1K x 8
1k x 10 512 x 16 512 x 20 256 x 32
256 x 40
2K x 5
—
—
—
Yes
—
Yes
—
Yes
—
Yes
1K x 8
Yes
Yes
Yes
—
Yes
—
Yes
—
Yes
—
1K x 10
—
—
—
Yes
—
Yes
—
Yes
—
Yes
512 x 16
Yes
Yes
Yes
—
Yes
—
Yes
—
Yes
—
512 x 20
—
—
—
Yes
—
Yes
—
Yes
—
Yes
256 x 32
Yes
Yes
Yes
—
Yes
—
Yes
—
Yes
—
256 x 40
—
—
—
Yes
—
Yes
—
Yes
—
Yes
Table 2-10: M10K Block Mixed-Width Configurations in True Dual-Port Mode
Port B
Port A
8K x 1
4K x 2
2K x 4
2K x 5
1K x 8
1K x 10
512 x 16
512 x 20
8K x 1
Yes
Yes
Yes
—
Yes
—
Yes
—
4K x 2
Yes
Yes
Yes
—
Yes
—
Yes
—
2K x 4
Yes
Yes
Yes
—
Yes
—
Yes
—
2K x 5
—
—
—
Yes
—
Yes
—
Yes
1K x 8
Yes
Yes
Yes
—
Yes
—
Yes
—
1K x 10
—
—
—
Yes
—
Yes
—
Yes
512 x 16
Yes
Yes
Yes
—
Yes
—
Yes
—
512 x 20
—
—
—
Yes
—
Yes
—
Yes
Embedded Memory Modes
Caution: To avoid corrupting the memory contents, do not violate the setup or hold time on any of the
memory block input registers during read or write operations. This is applicable if you use the
memory blocks in single-port RAM, simple dual-port RAM, true dual-port RAM, or ROM mode.
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Embedded Memory Modes
Table 2-11: Memory Modes Supported in the Embedded Memory Blocks
This table lists and describes the memory modes that are supported in the Arria V embedded memory blocks.
Memory Mode
Single-port RAM
M20K and
M10K
Support
MLAB
Support
Yes
Yes
Description
You can perform only one read or one write operation at a time.
Use the read enable port to control the RAM output ports
behavior during a write operation:
• To retain the previous values that are held during the most
recent active read enable—create a read-enable port and
perform the write operation with the read enable port
deasserted.
• To show the new data being written, the old data at that
address, or a "Don't Care" value when read-during-write occurs
at the same address location—do not create a read-enable
signal, or activate the read enable during a write operation.
Simple dual-port
RAM
Yes
Yes
You can simultaneously perform one read and one write
operations to different locations where the write operation
happens on port A and the read operation happens on port B.
True dual-port
RAM
Yes
—
You can perform any combination of two port operations: two
reads, two writes, or one read and one write at two different clock
frequencies.
Shift-register
Yes
Yes
You can use the memory blocks as a shift-register block to save
logic cells and routing resources.
This is useful in DSP applications that require local data storage
such as finite impulse response (FIR) filters, pseudo-random
number generators, multi-channel filtering, and auto- and crosscorrelation functions. Traditionally, the local data storage is
implemented with standard flip-flops that exhaust many logic
cells for large shift registers.
The input data width (w), the length of the taps (m), and the
number of taps (n) determine the size of a shift register
(w × m × n). You can cascade memory blocks to implement larger
shift registers.
ROM
Yes
Yes
You can use the memory blocks as ROM.
• Initialize the ROM contents of the memory blocks using a .mif
or .hex.
• The address lines of the ROM are registered on M20K or M10K
blocks but can be unregistered on MLABs.
• The outputs can be registered or unregistered.
• The output registers can be asynchronously cleared.
• The ROM read operation is identical to the read operation in
the single-port RAM configuration.
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Embedded Memory Clocking Modes
Memory Mode
FIFO
M20K and
M10K
Support
MLAB
Support
Yes
Yes
Description
You can use the memory blocks as FIFO buffers. Use the SCFIFO
and DCFIFO megafunctions to implement single- and dual-clock
asynchronous FIFO buffers in your design.
For designs with many small and shallow FIFO buffers, the
MLABs are ideal for the FIFO mode. However, the MLABs do
not support mixed-width FIFO mode.
Related Information
• Internal Memory (RAM and ROM) User Guide
Provides more information memory modes.
• RAM-Based Shift Register (ALTSHIFT_TAPS) Megafunction User Guide
Provides more information about implementing the shift register mode.
• SCFIFO and DCFIFO Megafunctions User Guide
Provides more information about implementing FIFO buffers.
Embedded Memory Clocking Modes
This section describes the clocking modes for the Arria V memory blocks.
Caution: To avoid corrupting the memory contents, do not violate the setup or hold time on any of the
memory block input registers during read or write operations.
Clocking Modes for Each Memory Mode
Table 2-12: Memory Blocks Clocking Modes Supported for Each Memory Mode
Memory Mode
Clocking Mode
Single-Port
Simple DualPort
True DualPort
ROM
FIFO
Single clock mode
Yes
Yes
Yes
Yes
Yes
Read/write clock mode
—
Yes
—
—
Yes
Input/output clock mode
Yes
Yes
Yes
Yes
—
Independent clock mode
—
—
Yes
Yes
—
Note: The clock enable signals are not supported for write address, byte enable, and data input registers
on MLAB blocks.
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Single Clock Mode
Single Clock Mode
In the single clock mode, a single clock, together with a clock enable, controls all registers of the memory
block.
Read/Write Clock Mode
In the read/write clock mode, a separate clock is available for each read and write port. A read clock controls
the data-output, read-address, and read-enable registers. A write clock controls the data-input, write-address,
write-enable, and byte enable registers.
Input/Output Clock Mode
In input/output clock mode, a separate clock is available for each input and output port. An input clock
controls all registers related to the data input to the memory block including data, address, byte enables,
read enables, and write enables. An output clock controls the data output registers.
Independent Clock Mode
In the independent clock mode, a separate clock is available for each port (A and B). Clock A controls all
registers on the port A side; clock B controls all registers on the port B side.
Note: You can create independent clock enable for different input and output registers to control the shut
down of a particular register for power saving purposes. From the parameter editor, click More
Options (beside the clock enable option) to set the available independent clock enable that you prefer.
Asynchronous Clears in Clocking Modes
In all clocking modes, asynchronous clears are available only for output latches and output registers. For
the independent clock mode, this is applicable on both ports.
Output Read Data in Simultaneous Read/Write
If you perform a simultaneous read/write to the same address location using the read/write clock mode, the
output read data is unknown. If you require the output read data to be a known value, use single-clock or
input/output clock mode and select the appropriate read-during-write behavior in the MegaWizard™ PlugIn Manager.
Independent Clock Enables in Clocking Modes
Independent clock enables are supported in the following clocking modes:
• Read/write clock mode—supported for both the read and write clocks.
• Independent clock mode—supported for the registers of both ports.
To save power, you can control the shut down of a particular register using the clock enables.
Related Information
Guideline: Control Clocking to Reduce Power Consumption on page 2-7
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Parity Bit in Memory Blocks
Table 2-13: Parity Bit Support for the Embedded Memory Blocks
This table describes the parity bit support for the memory blocks.
M20K, M10K
MLAB
• The parity bit is the fifth bit associated with each • The parity bit is the ninth bit associated with each
4 data bits in data widths of 5, 10, 20, and 40 (bits
byte.
4, 9, 14, 19, 24, 29, 34, and 39).
• The ninth bit can store a parity bit or serve as an
• In non-parity data widths, the parity bits are
additional bit.
skipped during read or write operations.
• Parity function is not performed on the parity bit.
• Parity function is not performed on the parity bit.
Byte Enable in Embedded Memory Blocks
The embedded memory blocks support byte enable controls:
• The byte enable controls mask the input data so that only specific bytes of data are written. The unwritten
bytes retain the values written previously.
• The write enable (wren) signal, together with the byte enable (byteena) signal, control the write operations
on the RAM blocks. By default, the byteena signal is high (enabled) and only the wren signal controls
the writing.
• The byte enable registers do not have a clear port.
• If you are using parity bits, on the M20K and M10K blocks, the byte enable function controls 8 data bits
and 2 parity bits; on the MLABs, the byte enable function controls all 10 bits in the widest mode.
• The MSB and LSB of the byteena signal correspond to the MSB and LSB of the data bus, respectively.
• The byte enables are active high.
Byte Enable Controls in Memory Blocks
Table 2-14: byteena Controls in x20 Data Width
byteena[1:0]
Data Bits Written
11 (default)
[19:10]
[9:0]
10
[19:10]
—
01
—
[9:0]
Table 2-15: byteena Controls in x40 Data Width
byteena[3:0]
Data Bits Written
1111 (default)
[39:30]
[29:20]
[19:10]
[9:0]
1000
[39:30]
—
—
—
0100
—
[29:20]
—
—
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Data Byte Output
byteena[3:0]
Data Bits Written
0010
—
—
[19:10]
—
0001
—
—
—
[9:0]
Note: If you use the ECC feature on the M20K blocks, you cannot use the byte enable feature.
Data Byte Output
In M10K blocks, the corresponding masked data byte output appears as a “don’t care” value.
In M20K blocks or MLABs, when you de-assert a byte-enable bit during a write cycle, the corresponding
data byte output appears as either a “don't care” value or the current data at that location. You can control
the output value for the masked byte in the M20K blocks or MLABs by using the Quartus II software.
RAM Blocks Operations
Figure 2-6: Byte Enable Functional Waveform
This figure shows how the wren and byteena signals control the operations of the RAM blocks. For the
M10K blocks, the write-masked data byte output appears as a “don’t care” value because the “current data”
value is not supported.
inclock
wren
address
data
byteena
contents at a0
contents at a1
an
a0
a1
XXXXXXXX
a2
a3
a4
a0
XXXXXXXX
ABCDEF12
XXXX
1000
0100
0010
1111
FFFFFFFF
FFCDFFFF
FFFFFFFF
contents at a3
XXXX
ABFFFFFF
FFFFFFFF
contents at a2
0001
FFFFEFFF
FFFFFFFF
contents at a4
FFFFFF12
FFFFFFFF
ABCDEF12
don’t care: q (asynch)
doutn
ABXXXXXX
XXCDXXXX
XXXXEFXX
XXXXXX12
ABCDEF12
ABFFFFFF
current data: q (asynch)
doutn
ABFFFFFF
FFCDFFFF
FFFFEFFF
FFFFFF12
ABCDEF12
ABFFFFFF
Memory Blocks Packed Mode Support
The M20K and M10K memory blocks support packed mode.
The packed mode feature packs two independent single-port RAM blocks into one memory block. The
Quartus II software automatically implements packed mode where appropriate by placing the physical RAM
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Memory Blocks Address Clock Enable Support
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block in true dual-port mode and using the MSB of the address to distinguish between the two logical RAM
blocks. The size of each independent single-port RAM must not exceed half of the target block size.
Memory Blocks Address Clock Enable Support
The embedded memory blocks support address clock enable, which holds the previous address value for as
long as the signal is enabled (addressstall = 1). When the memory blocks are configured in dual-port
mode, each port has its own independent address clock enable. The default value for the address clock enable
signal is low (disabled).
Figure 2-7: Address Clock Enable
This figure shows an address clock enable block diagram. The address clock enable is referred to by the port
name addressstall.
address[0]
1
0
address[N]
1
0
address[0]
register
address[0]
address[N]
register
address[N]
addressstall
clock
Figure 2-8: Address Clock Enable During Read Cycle Waveform
This figure shows the address clock enable waveform during the read cycle.
inclock
rdaddress
a0
a1
a2
a3
a4
a5
a6
rden
addressstall
latched address
(inside memory)
an
q (synch) doutn-1
q (asynch)
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doutn
a1
a0
doutn
dout0
dout0
a4
dout4
dout1
dout1
a5
dout4
dout5
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Memory Blocks Error Correction Code Support
Figure 2-9: Address Clock Enable During the Write Cycle Waveform
This figure shows the address clock enable waveform during the write cycle.
inclock
wraddress
a0
a1
a2
a3
a4
a5
a6
00
01
02
03
04
05
06
data
wren
addressstall
latched address
(inside memory)
contents at a0
an
a1
a0
a5
00
XX
contents at a1
a4
XX
01
contents at a2
XX
contents at a3
XX
contents at a4
03
02
04
XX
XX
contents at a5
05
Memory Blocks Error Correction Code Support
ECC allows you to detect and correct data errors at the output of the memory. ECC can perform single-error
correction, double-adjacent-error correction, and triple-adjacent-error detection in a 32-bit word. However,
ECC cannot detect four or more errors.
The M20K blocks have built-in support for ECC when in x32-wide simple dual-port mode:
• The M20K runs slower than non-ECC simple-dual port mode when ECC is engaged. However, you can
enable optional ECC pipeline registers before the output decoder to achieve the same performance as
non-ECC simple-dual port mode at the expense of one cycle of latency.
• The M20K ECC status is communicated with two ECC status flag signals—e (error) and ue (uncorrectable
error). The status flags are part of the regular output from the memory block. When ECC is engaged,
you cannot access two of the parity bits because the ECC status flag replaces them.
Error Correction Code Truth Table
Table 2-16: ECC Status Flags Truth Table
e (error)
ue (uncorrectable error)
eccstatus[1]
eccstatus[0]
0
0
No error.
0
1
Illegal.
1
0
A correctable error occurred and the
error has been corrected at the outputs;
however, the memory array has not
been updated.
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Document Revision History
e (error)
ue (uncorrectable error)
eccstatus[1]
eccstatus[0]
1
1
2-19
Status
An uncorrectable error occurred and
uncorrectable data appears at the
outputs.
If you engage ECC:
• You cannot use the byte enable feature.
• Read-during-write old data mode is not supported.
Figure 2-10: ECC Block Diagram for M20K Memory
2
Status Flag
Generation
40
8
32
40
32
Input
Register
ECC
Encoder
8
Memory
Array
40
Optional
Pipeline
Register
40
ECC
Decoder
40
Output
Register
Document Revision History
Date
May 2013
Version
2013.05.06
Embedded Memory Blocks in Arria V Devices
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Changes
• Moved all links to the Related Information section of respective topics
for easy reference.
• Added link to the known document issues in the Knowledge Base.
• Corrected the description about the "don't care" output mode for RAM
in mixed-port read-during-write.
• Reorganized the structure of the supported memory configurations
topics (single-port and mixed-width dual-port) to improve clarity about
maximum data widths supported for each configuration.
• Added a description to the table listing the maximum embedded memory
configurations to clarify that the information applies only to the single
port or ROM mode.
• Removed the topic about mixed-width configurations for MLABs and
added a note to clarify that MLABs do not support mixed-width
configuration.
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Document Revision History
Date
Version
Changes
2012.11.19
• Reorganized content and updated template.
• Added information for Arria V GZ including M20K memory, memory
features, and memory capacity.
• Added and updated memory capacity information from the Arria V
Device Overview for easy reference.
• Moved information about supported memory block configurations into
its own table.
• Added short descriptions of each clocking mode.
• Added topic about the packed mode support.
• Added topic about the address clock enable support.
• Added topic about ECC support and the ECC truth table.
June 2012
2.0
• Restructured the chapter.
• Updated the “Memory Modes”, “Clocking Modes”, and “Design
Considerations” sections.
• Updated Table 2–1.
• Added the “Parity Bit” and “Byte Enable” sections.
• Moved the memory capacity information to the Arria V Device Overview.
November 2011
1.1
• Updated Table 2–1.
• Restructured chapter.
May 2011
1.0
Initial release.
November 2012
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Variable Precision DSP Blocks in Arria V Devices
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This chapter describes how the variable-precision digital signal processing (DSP) blocks in Arria V devices
are optimized to support higher bit precision in high-performance DSP applications.
Related Information
Arria V Device Handbook: Known Issues
Lists the planned updates to the Arria V Device Handbook chapters.
Features
The Arria V variable precision DSP blocks offer the following features:
•
•
•
•
•
•
High-performance, power-optimized, and fully registered multiplication operations
9-bit, 18-bit, 27-bit, and 36-bit word lengths
18 x 19 and 18 x 25 complex multiplications
Built-in addition, subtraction, and 64-bit accumulation unit to combine multiplication results
Cascading 19-bit or 27-bit to form the tap-delay line for filtering applications
Cascading 64-bit output bus to propagate output results from one block to the next block without external
logic support
• Hard pre-adder supported in 18-bit, 19-bit, and 27-bit mode for symmetric filters
• Internal coefficient register bank for filter implementation
• 18-bit and 27-bit systolic finite impulse response (FIR) filters with distributed output adder
Related Information
Arria V Device Overview
Provides more information about the number of multipliers in each Arria V device.
© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words
and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other
words and logos identified as trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with
Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes
no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
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Supported Operational Modes in Arria V Devices
Supported Operational Modes in Arria V Devices
Table 3-1: Variable Precision DSP Blocks Operational Modes for Arria V GX, GT, SX, and ST Devices
Variable-Precision
DSP Block Resource
1 variable
precision DSP
block
2 variable
precision DSP
blocks
(2)
Supported
Instance
Pre-Adder
Support
Coefficient
Support
Input
Cascade
(2)
Support
Chainout Support
Independent
9x9
multiplication
3
No
No
No
No
Independent
18 x 18
multiplication
2
Yes
Yes
Yes
No
Independent
18 x 19
multiplication
2
Yes
Yes
Yes
No
Independent
18 x 25
multiplication
1
Yes
Yes
Yes
Yes
Independent
20 x 24
multiplication
1
Yes
Yes
Yes
Yes
Independent
27 x 27
multiplication
1
Yes
Yes
Yes
Yes
Two 18 x 19
multiplier adder
mode
1
Yes
Yes
Yes
Yes
18 x 18
multiplier adder
summed with
36-bit input
1
Yes
No
No
Yes
Complex 18 x 19
multiplication
1
No
No
Yes
No
Operation Mode
When you enable the pre-adder feature, the input cascade support is not available.
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Supported Operational Modes in Arria V Devices
Table 3-2: Variable Precision DSP Blocks Operational Modes for Arria V GZ Devices
Variable Precision
DSP Block Resources
1 variable
precision DSP
block
(3)
Operational
Mode
Supported
Instance
Pre-adder
Support
Coefficient
Support
Input
Cascade
Support
Chainout Support
Independent
9x9
multiplication
3
No
No
No
No
Independent
16 x 16
multiplication
2
Yes
Yes
Yes
No
Independent
18 x 18
partial
multiplication
(32-bit)
2
Yes
Yes
Yes
No
Independent
18 x 18
multiplication
1
Yes
Yes
Yes
No
Independent
27 x 27
multiplication
1
Yes
Yes
Yes
Yes
Independent
36 x 18
multiplication
1
No
Yes
No
Yes
Two 18 x 18
multiplier
adder
1
Yes
Yes
Yes
Yes
Two 16 x 16
multiplier
adder
1
Yes
Yes
Yes
Yes
Sum of 2
square
1
Yes(3)
No
No
Yes
18 x 18
multiplication
summed
with 36-bit
input
1
No
No
No
Yes
The pre-adder feature for this mode is automatically enabled.
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Supported Operational Modes in Arria V Devices
Operational
Mode
Supported
Instance
Pre-adder
Support
Coefficient
Support
Input
Cascade
Support
Chainout Support
Independent
18 x 18
multiplication
3
No
No
No
No
Independent
36 x 36
multiplication
1
No
No
No
No
Complex
18 x 18
multiplication
1
Yes
Yes
Yes
Yes
Four 18 x 18
multiplier
adder
1
Yes
Yes
Yes
No
Two 27 x 27
multiplier
adder
1
Yes
Yes
Yes
No
Two 18 x 36
multiplier
adder
1
No
Yes
No
No
3 variable
precision DSP
blocks
Complex
18 x 25
multiplication
1
Yes(3)
No
No
No
4 variable
precision DSP
blocks
Complex
27 x 27
multiplication
1
Yes
Yes
Yes
No
Variable Precision
DSP Block Resources
2 variable
precision DSP
blocks
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Resources
Resources
Table 3-3: Number of Multipliers in Arria V Devices
The table lists the variable-precision DSP resources by bit precision for each Arria V device.
Variant
Arria V GX
Arria V GT
Arria V GZ
Arria V SX
Arria V ST
Independent Input and Output Multiplications
Operator
36 x 36
Multiplier
18 x 18
Multiplier
Adder
Mode
18 x 18 Multiplier
Adder Summed
with 36 bit Input
240
—
240
240
792
396
—
396
396
1,800
1,200
600
—
600
600
800
2,400
1,600
800
—
800
800
B1
920
2,760
1,840
920
—
920
920
B3
1,045
3,135
2,090
1,045
—
1,045
1,045
B5
1,092
3,276
2,184
1,092
—
1,092
1,092
B7
1,156
3,468
2,312
1,156
—
1,156
1,156
C3
396
1,188
792
396
—
396
396
C7
800
2,400
1,600
800
—
800
800
D3
1,045
3,135
2,090
1,045
—
1,045
1,045
D7
1,156
3,468
2,312
1,156
—
1,156
1,156
E1
800
2,400
1,600
800
400
800
800
E3
1,044
3,132
2,088
1,044
522
1,044
1,044
E5
1,092
3,276
2,184
1,092
546
1,092
1,092
E7
1,139
3,417
2,278
1,139
569
1,139
1,139
B3
809
2,427
1,618
809
—
809
809
B5
1,090
3,270
2,180
1,090
—
1,090
1,090
D3
809
2,427
1,618
809
—
809
809
D5
1,090
3,270
2,180
1,090
—
1,090
1,090
Member
Code
Variableprecision
DSP Block
9x9Multiplier
18 x 18
Multiplier
27 x 27
Multiplier
A1
240
720
480
A3
396
1,188
A5
600
A7
Design Considerations
You should consider the following elements in your design:
•
•
•
•
Operational modes
Internal coefficient and pre-adder
Accumulator
Chainout adder
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Operational Modes
Operational Modes
The Quartus II software includes megafunctions that you can use to control the operation mode of the
multipliers. After entering the parameter settings with the MegaWizard Plug-In Manager, the Quartus II
software automatically configures the variable precision DSP block.
Altera provides two methods for implementing various modes of the Arria V variable precision DSP block
in a design—using the Quartus II DSP megafunction and HDL inferring.
The following Quartus II megafunctions are supported for the Arria V variable precision DSP blocks
implementation:
•
•
•
•
LPM_MULT
ALTMULT_ADD
ALTMULT_ACCUM
ALTMULT_COMPLEX
Related Information
• Introduction to Megafunction User Guide
• Integer Arithmetic Megafunctions User Guide
• Floating-Point Megafunctions User Guide
• Quartus II Software Help
Internal Coefficient and Pre-Adder
To use the pre-adder feature, all input data and multipliers must have the same clock setting.
The input cascade support is not available when you enable the pre-adder feature.
Table 3-4: Internal Coefficient and Pre-Adder Features in Arria V Devices
Mode
Arria V GX, GT, SX, and ST
Arria V GZ
18-bit
The coefficient feature and pre-adder feature The coefficient feature must be enabled
can be used independently.
when the pre-adder feature is enabled.
27-bit
The coefficient feature and pre-adder feature The coefficient feature and pre-adder
feature can be used independently.
can be used independently.
With pre-adder enabled:
• If the multiplicand input comes from
dynamic input due to width limitation
in the input registers—the input data
width is restricted to 22 bits.
• If the multiplicand input comes from
the internal coefficients—the data
width of the multiplicand is 27 bits.
Note: When you enable the pre-adder feature, all input data must have the same clock setting.
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Accumulator
3-7
Accumulator
The accumulator in the Arria V GX, GT, SX, and ST devices supports double accumulation by enabling the
64-bit double accumulation registers located between the output register bank and the accumulator.
The double accumulation registers are set statically in the programming file.
The accumulator in the Arria V GZ devices does not support double accumulation. The accumulator feature
is not available in multi-block modes.
Chainout Adder
You can use the output chaining path to add results from other DSP blocks.
Block Architecture
The Arria V variable precision DSP block consists of the following elements:
•
•
•
•
•
•
•
•
•
Input register bank
Pre-adder
Internal coefficient
Multipliers
Adder
Accumulator and chainout adder
Systolic registers
Double accumulation register
Output register bank
If the variable precision DSP block is not configured in systolic FIR mode, both systolic registers are bypassed.
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Block Architecture
Figure 3-1: Variable Precision DSP Block Architecture in 18 x 19 Mode for Arria V GX, GT, SX, and ST Devices
CLK[2..0]
scanin
chainin[63..0]
ENA[2..0]
ACLR[1..0]
LOADCONST
ACCUMULATE
NEGATE
SUB_COMPLEX
dataa_z0[17..0]
dataa_x0[17..0]
COEFSELA[2..0]
Input Register Bank
dataa_y0[18..0]
Systolic
Registers
(1)
+/-
Constant
Systolic
Register (1)
Multiplier
Pre-Adder
x
+/-
Internal
Coefficient
+/-
Adder
Multiplier
+
Chainout adder/
accumulator
datab_y1[18..0]
+/-
datab_z1[17..0]
x
datab_x1[17..0]
COEFSELB[2..0]
Output Register Bank
Pre-Adder
Double
Accumulation
Register
Result[73..0]
Internal
Coefficient
scanout
chainout[63..0]
Note:
1. When enabled, systolic registers are clocked with the same clock source as the output register bank.
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Block Architecture
Figure 3-2: Variable Precision DSP Block Architecture in 27 x 27 Mode for Arria V GX, GT, SX, and ST Devices
chainin[63..0]
LOADCONST
ACCUMULATE
Constant
NEG
dataa_y0[26..0]
dataa_z0[25..0]
Pre-Adder
+/-
Input
Register
Bank
Double
Accumulation
Register
Chainout Adder/
Accumulator
Multiplier
x
+
+/-
dataa_x0[26..0]
COEFSELA[2..0]
Output
Register
Bank
Internal
Coefficients
Result[63..0]
64
chainout[63..0]
Figure 3-3: Variable Precision DSP Block Architecture in 18 x 18 Mode for Arria V GZ Devices
CLK[2..0]
ENA[2..0]
scanin [17..0]
chainin[63..0]
ACLR[1..0]
ACCUMULATE
LOADCONST
NEGATE
SUB
+/-
18
COEFSELA[2..0]
Systolic
Registers
x
+/-
Internal
Coefficient
Multiplier
+/-
Pre-Adder
datab_y1[17..0]
datab_x1[17..0]
+/-
+
Chainout adder/
accumulator
Output Register Bank
dataa_x0[17..0]
18
Input Register Bank
dataa_y0[17..0]
Constant
Systolic
Register
Multiplier
Pre-Adder
18
x
+/-
18
64
Result[65..0]
Adder
COEFSELB[2..0]
Internal
Coefficient
scanout[17..0]
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Input Register Bank
Figure 3-4: Variable Precision DSP Block Architecture in 27 x 27 Mode for Arria V GZ Devices
CLK[2..0]
ENA[2..0]
scanin [26..0]
chainin[63..0]
ACLR[1..0]
ACCUMULATE
LOADCONST
NEGATE
Constant
Multiplier
Pre-Adder
datac_0[24..0]
27
25
COEFSELA[2..0]
+/x
+/Internal
Coefficient
+
Chainout adder/
accumulator
Output Register Bank
dataa_0[26..0]
27
Input Register Bank
datab_0[26..0]
64
Result[65..0]
scanout[26..0]
chainout[63..0]
Input Register Bank
The input register bank consists of data, dynamic control signals, and two sets of delay registers.
All the registers in the DSP blocks are positive-edge triggered and cleared on power up. Each multiplier
operand can feed an input register or a multiplier directly, bypassing the input registers.
The following variable precision DSP block signals control the input registers within the variable precision
DSP block:
• CLK[2..0]
• ENA[2..0]
• ACLR[0]
In 18 x 18 and 18 x 19 mode, you can use the delay registers to balance the latency requirements when you
use both the input cascade and chainout features.
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Input Register Bank
3-11
The tap-delay line feature allows you to drive the top leg of the multiplier inputs from general routing or
from the cascade chain. The following inputs can be driven from either the general routing or from the
cascade chain:
• For Arria V GX, GT, SX, and ST devices:
• dataa_y0 and datab_y1 in 18 x 19 mode
• dataa_y0 in 27 x 27 mode
• For Arria V GZ devices:
• dataa_y0[17..0] and datab_y1[17..0] in 18 x 18 mode
• dataa_y0 in 27 x 27 mode
The Arria V GZ variable precision DSP block support 18-bit and 27-bit input cascading.
These figures show the input registers for Arria V devices.
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Input Register Bank
Figure 3-5: Input Register of a Variable Precision DSP Block in 18 x 19 Mode for Arria V GX, GT, SX, and ST
Devices
The figures show the data registers only. Registers for the control signals are not shown.
CLK[2..0]
ENA[2..0]
scanin[18..0]
ACLR[0]
dataa_y0[18..0]
dataa_z0[17..0]
dataa_x0[17..0]
Delay registers
datab_y1[18..0]
datab_z1[17..0]
datab_x1[17..0]
Delay registers
scanout[18..0]
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Input Register Bank
3-13
Figure 3-6: Input Register of a Variable Precision DSP Block in 27 x 27 Mode for Arria V GX, GT, SX, and ST
Devices
The figures show the data registers only. Registers for the control signals are not shown.
CLK[2..0]
ENA[2..0]
scanin[26..0]
ACLR[0]
dataa_y0[26..0]
dataa_z0[25..0]
dataa_x0[26..0]
scanout[26..0]
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Input Register Bank
Figure 3-7: Input Register of a Variable Precision DSP Block in 18 x 18 Mode for Arria V GZ Devices
The figures show the data registers only. Registers for the control signals are not shown.
CLK[2..0]
ENA[2..0]
scanin[17..0]
ACLR[0]
dataa_y0[17..0]
dataa_x0[17..0]
Delay registers
datab_y1[17..0]
datab_x1[17..0]
Delay registers
scanout[17..0]
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Pre-Adder
3-15
Figure 3-8: Input Register of a Variable Precision DSP Block in 27 x 27 Mode for Arria V GZ Devices
The figures show the data registers only. Registers for the control signals are not shown.
CLK[2..0]
ENA[2..0]
scanin[26..0]
ACLR[0]
dataa_y0[26..0]
dataa_x0[26..0]
dataa_z0[24..0]
scanout[26..0]
Pre-Adder
Arria V GX, GT, SX, and ST Devices
Each variable precision DSP block has two 19-bit pre-adders. You can configure these pre-adders in the
following configurations:
• Two independent 19-bit pre-adders
• One 27-bit pre-adder
The pre-adder supports both addition and subtraction in the following input configurations:
• 18-bit (signed) addition or subtraction for 18 x 19 mode
• 17-bit (unsigned) addition or subtraction for 18 x 19 mode
• 26-bit addition or subtraction for 27 x 27 mode
Arria V GZ Devices
Each variable precision DSP block has two 18-bit pre-adders. You can configure these pre-adders in the
following configurations:
• Two independent 18-bit adders
• One 26-bit adder
The pre-adder supports both addition and subtraction in the following input configurations:
• 17-bit addition or subtraction for 18-bit applications
• 25-bit addition or subtraction for 27-bit applications
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Internal Coefficient
Internal Coefficient
The Arria V variable precision DSP block has the flexibility of selecting the multiplicand from either the
dynamic input or the internal coefficient.
The internal coefficient can support up to eight constant coefficients for the multiplicands in 18-bit and
27-bit modes. When you enable the internal coefficient feature, COEFSELA/COEFSELB are used to control the
selection of the coefficient multiplexer.
Multipliers
A single variable precision DSP block can perform many multiplications in parallel, depending on the data
width of the multiplier.
There are two multipliers per variable precision DSP block. You can configure these two multipliers in
several operational modes.
For Arria V GX, GT, SX, and ST devices:
• One 27 x 27 multiplier
• Two 18 (signed)/(unsigned) x 19 (signed) multipliers
• Three 9 x 9 multipliers
For Arria V GZ devices:
•
•
•
•
•
•
•
One 27 x 27 multiplier
Two individual 16 x 16 multipliers
Two individual 18 x 18 partial multipliers, with only 32-bit LSB multiplication result for each multiplication
One individual 18 x 18 multiplier, with full 36-bit multiplication result
One individual 27 x 27 multiplier
One individual 36 x 18 multiplier
There individual 9 x 9 multipliers
For Arria V GZ devices, you can use two adjacent DSP blocks to construct an individual 36-bit multiplier.
Related Information
Operational Mode Descriptions on page 3-18
Provides more information about the operational modes of the multipliers.
Adder
You can use the adder in various sizes, depending on the operational mode:
• One 64-bit adder with the 64-bit accumulator
• Two 18 x 19 modes—the adder is divided into two 37-bit adders to produce the full 37-bit result of each
independent 18 x 19 multiplication
• Three 9 x 9 modes—you can use the adder as three 18-bit adders to produce three 9 x 9 multiplication
results independently
Accumulator and Chainout Adder
The Arria V variable precision DSP block supports a 64-bit accumulator and a 64-bit adder.
For Arria V GX, GT, SX, and ST devices, the accumulator and chainout adder features are not supported in
two independent 18 x 19 modes and three independent 9 x 9 modes.
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Systolic Registers
3-17
For Arria V GZ devices, you can use the 64-bit adder as full adder.
The following signals can dynamically control the function of the accumulator:
• NEGATE
• LOADCONST
• ACCUMULATE
Table 3-5: Accumulator Functions and Dynamic Control Signals
This table lists the dynamic signals settings and description for each function. In this table, X denotes a "don't care"
value.
Function
Description
NEGATE
LOADCONST
ACCUMULATE
Zeroing
Disables the
accumulator.
0
0
0
Preload
Loads an initial value
to the accumulator.
Only one bit of the
64-bit preload value
can be “1”. It can be
used as rounding the
DSP result to any
position of the 64-bit
result.
0
1
0
Accumulation
Adds the current
result to the previous
accumulate result.
0
X
1
Decimation
This function takes
the current result,
converts it into two’s
complement, and adds
it to the previous
result.
1
X
1
Systolic Registers
There are two systolic registers per variable precision DSP block. If the variable precision DSP block is not
configured in systolic FIR mode, both systolic registers are bypassed.
The first set of systolic registers consists of the following registers:
• 18-bit and 19-bit registers that are used to register the 18-bit and 19-bit inputs of the upper multiplier
respectively for Arria V GX, GT, SX, and ST devices
• 18-bit registers that are used to register the 18-bit inputs of the upper multiplier for Arria V GZ devices
The second set of systolic registers are used to delay the chainout output to the next variable precision DSP
block.
You must clock all the systolic registers with the same clock source as the output register bank.
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Double Accumulation Register
Double Accumulation Register
The double accumulation register is an extra register in the feedback path of the accumulator. Enabling the
double accumulation register will cause an extra clock cycle delay in the feedback path of the accumulator.
This register has the same CLK, ENA, and ACLR settings as the output register bank.
By enabling this register, you can have two accumulator channels using the same number of variable precision
DSP block.
Double accumulation register is not available in Arria V GZ devices.
Output Register Bank
The positive edge of the clock signal triggers the 64-bit bypassable output register bank and is cleared after
power up.
The following variable precision DSP block signals control the output register per variable precision DSP
block:
• CLK[2..0]
• ENA[2..0]
• ACLR[1]
Operational Mode Descriptions
This section describes how you can configure an Arria V variable precision DSP block to efficiently support
the following operational modes:
•
•
•
•
•
•
Independent Multiplier Mode
Independent Complex Multiplier Mode
Multiplier Adder Sum Mode
Sum of Square Mode (Arria V GZ only)
18 x 18 Multiplication Summed with 36-Bit Input Mode
Systolic FIR Mode
Independent Multiplier Mode
In independent input and output multiplier mode, the variable precision DSP blocks perform individual
multiplication operations for general purpose multipliers.
Table 3-6: Variable Precision DSP Block Independent Multiplier Mode Configurations for Arria V Devices
Configuration
Multipliers per block
Device Variant Support
9x9
3
All
16 x 16
1
Arria V GZ
18 x 18 (partial)
1
Arria V GZ
18 x 18
1
Arria V GZ
18 (signed) x 18 (unsigned)
2
Arria V GX, GT, SX, ST
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9 x 9 Independent Multiplier
Configuration
Multipliers per block
Device Variant Support
18 (unsigned) x 18 (unsigned)
2
Arria V GX, GT, SX, ST
18 (signed) x 19 (signed)
2
Arria V GX, GT, SX, ST
18 (unsigned) x 19 (signed)
2
Arria V GX, GT, SX, ST
18 x 25
1
Arria V GX, GT, SX, ST
20 x 24
1
Arria V GX, GT, SX, ST
27 x 27
1
All
36 x 18
1
Arria V GZ
3-19
Table 3-7: Independent Multiplier Mode Configurations with Multiple Variable Precision DSP Blocks for Arria V
Devices
Configuration
Number of DSP Blocks
Required
Device Variant Support
3 independent 18 x 18 multipliers
2
Arria V GZ
36 x 36 multiplier
2
Arria V GZ
9 x 9 Independent Multiplier
Figure 3-9: Three 9 x 9 Independent Multiplier Mode per Variable Precision DSP Block for Arria V Devices
Three pairs of data are packed into the ax and ay ports; result contains three 18-bit products.
Variable-Precision DSP Block
27
ax[x2, x1, x0]
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x
Output Register Bank
27
ay[y2, y1, y0]
Input Register Bank
Multiplier
54
Result[53..0]
(p2, p1, p0)
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18 x 18 Independent Multiplier
18 x 18 Independent Multiplier
datab_0[17..0]
18
Multiplier
Input Register Bank
dataa_0[17..0]
18
x
Output Register Bank
Figure 3-10: One 18 x 18 Independent Multiplier Mode with One Variable Precision DSP Block for Arria V
GZ Devices
36
result[35..0]
Variable Precision DSP Block
Figure 3-11: Three 18 x 18 Independent Multiplier Mode with Two Variable Precision DSP Blocks for Arria V
GZ Devices
Multiplier
18
x
36
datab_2[17..0]
dataa_2[17..0]
Multiplier
18
Output Register Bank
dataa_0[17..0]
Input Register Bank
datab_0[17..0]
18
18
result_0[35..0]
result_2[17..0]
x
18
Variable Precision DSP Block 1
Multiplier
x
18
Input Register Bank
dataa_2[17..0]
18
datab_1[17..0]
dataa_1[17..0]
Multiplier
18
Output Register Bank
datab_2[17..0]
36
result_2[35..18]
result_1[35..0]
18
18
x
Variable Precision DSP Block 2
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18 x 18 or 18 x 19 Independent Multiplier
3-21
18 x 18 or 18 x 19 Independent Multiplier
Figure 3-12: Two 18 x 18 or 18 x 19 Independent Multiplier Mode per Variable Precision DSP Block for
Arria V GX, GT, SX, and ST Devices
In this figure, the variables are defined as follows:
• n = 19 and m = 37 for 18 x 19 mode
• n = 18 and m = 36 for 18 x 18 mode
Variable-Precision DSP Block
Multiplier
n
data_b1[(n-1)..0]
m
x
[(m-1)..0]
n
Input Register Bank
data_a1[17..0]
Multiplier
data_b0[(n-1)..0]
x
Output Register Bank
18
m
[(m-1)..0]
18
data_a0[17..0]
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16 x 16 Independent Multiplier or 18 x 18 Independent Partial Multiplier
16 x 16 Independent Multiplier or 18 x 18 Independent Partial Multiplier
Figure 3-13: Two 16 x 16 Independent Multiplier Mode or Two 18 x 18 Independent Partial Multiplier Mode
for Arria V GZ Devices
In this figure, the inputs for 16-bit independent multiplier mode are data[15..0]. The unused input bits
require padding with zero.
For two independent 18 x 18 partial multiplier mode, only 32-bit LSB result for each multiplication operation
is routed to the output. The output has full precision if the total width of the multiplicand input is less than
or equal to 32 bits for each multiplier.
Multiplier
datab_0[17..0]
x
result_0[31..0]
datab_1[17..0]
Output Register Bank
Input Register Bank
dataa_0[17..0]
Multiplier
x
result_1[31..0]
dataa_1[17..0]
Variable Precision DSP Block
18 x 25 Independent Multiplier
Figure 3-14: One 18 x 25 Independent Multiplier Mode per Variable Precision DSP Block for Arria V GX, GT,
SX, and ST Devices
In this mode, the result can be up to 52 bits when combined with a chainout adder or accumulator.
Variable-Precision DSP Block
25
dataa_a0[24..0]
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x
Output Register Bank
18
dataa_b0[17..0]
Input Register Bank
Multiplier
43
Result[42..0]
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20 x 24 Independent Multiplier
3-23
20 x 24 Independent Multiplier
Figure 3-15: One 20 x 24 Independent Multiplier Mode per Variable Precision DSP Block for Arria V GX, GT,
SX, and ST Devices
In this mode, the result can be up to 52 bits when combined with a chainout adder or accumulator.
24
dataa_a0[23..0]
x
Output Register Bank
20
dataa_b0[19..0]
Input Register Bank
Variable-Precision DSP Block
Multiplier
44
Result[43..0]
27 x 27 Independent Multiplier
Figure 3-16: One 27 x 27 Independent Multiplier Mode per Variable Precision DSP Block for Arria V Devices
In this mode, the result can be up to 64 bits when combined with a chainout adder or accumulator.
Variable-Precision DSP Block
27
dataa_a0[26..0]
Variable Precision DSP Blocks in Arria V Devices
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x
Output Register Bank
dataa_b0[26..0]
Input Register Bank
Multiplier
27
54
Result[53..0]
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36 x 18 Independent Multiplier
36 x 18 Independent Multiplier
Figure 3-17: One 36 x 18 Independent Multiplier Mode for Arria V GZ Devices
Multiplier
dataa_0[17..0]
18
x
+
Multiplier
datab_0[17..0]
dataa_0[35..18]
18
18
Output Register Bank
18
Input Register Bank
datab_0[17..0]
54
result[53..0]
x
Variable Precision DSP Block
36-Bit Independent Multiplier
You can efficiently construct an individual 36-bit multiplier with two adjacent variable precision DSP blocks.
The 36 x 36 multiplication consists of four 18 x 18 multipliers.
The 36-bit multiplier is useful for applications requiring more than 18-bit precision; for example, for the
mantissa multiplication portion of very high precision fixed-point arithmetic applications.
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Independent Complex Multiplier Mode
3-25
Figure 3-18: 36-Bit Independent Multiplier Mode with Two Variable Precision DSP Blocks for Arria V GZ
Devices
Multiplier
x
18
Input Register Bank
dataa_0[17..0]
Adder
datab_0[17..0]
dataa_0[35..18]
+
Multiplier
Output Register Bank
datab_0[17..0]
18
18
result[17..0]
18
x
18
Variable Precision DSP Block 1
Multiplier
datab_0[35..18]
dataa_0[35..18]
Adder
x
18
18
18
+
Multiplier
Output Register Bank
dataa_0[17..0]
Input Register Bank
datab_0[35..18]
18
54
result[71..18]
xx
Variable Precision DSP Block 2
Independent Complex Multiplier Mode
The Arria V variable precision DSP block provides the means for a complex multiplication.
Figure 3-19: Sample of Complex Multiplication Equation
Table 3-8: Variable Precision DSP Block Independent Complex Multiplier Mode Configurations for Arria V Devices
Configuration
Number of DSP Blocks Required
Device Variant Support
18 x 18
2
Arria V GZ
18 x 19
2
Arria V GX, GT, SX, ST
18 x 25
3
Arria V GZ
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18 x 18 Complex Multiplier
Configuration
Number of DSP Blocks Required
Device Variant Support
27 x 27
4
Arria V GZ
18 x 18 Complex Multiplier
For 18 x 18 complex multiplication mode, you require two variable precision DSP blocks to perform this
multiplication.
You can implement the imaginary part [(a × d) + (b × c)] in the first variable precision DSP block, and you
can implement the real part [(a × c) – (b × d)] in the second variable precision DSP block.
Figure 3-20: 18 x 18 Complex Multiplier with Two Variable Precision DSP Blocks for Arria V GZ Devices
Multiplier
Adder
x
d
a
18
Input Register Bank
18
+
Multiplier
Output Register Bank
c
b
18
37
Imaginary part
(ad + bc)
x
18
Variable Precision DSP Block 1
Multiplier
d
Adder
18
x
b
a
18
Multiplier
x
Output Register Bank
c
Input Register Bank
18
37
Real part
(ac - bd )
18
Variable Precision DSP Block 2
18 x 19 Complex Multiplier
For 18 x 19 complex multiplication mode, you require two variable precision DSP blocks to perform this
multiplication.
The imaginary part [(a × d) + (b × c)] is implemented in the first variable precision DSP block, while the
real part [(a × c) - (b × d)] is implemented in the second variable precision DSP block.
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18 x 25 Complex Multiplier
3-27
Figure 3-21: One 18 x 19 Complex Multiplier with Two Variable Precision DSP Blocks for Arria V GX, GT,
SX, and ST Devices
Variable-Precision DSP Block 1
Multiplier
19
x
Adder
b[17..0]
19
d[18..0]
Input Register Bank
18
18
Multiplier
+
Output Register Bank
c[18..0]
38
Imaginary Part
(ad+bc)
x
a[17..0]
Variable-Precision DSP Block 2
Multiplier
x
Adder
Multiplier
-
b[17..0]
19
c[18..0]
18
Input Register Bank
18
Output Register Bank
19
d[18..0]
38
Real Part
(ac-bd)
x
a[17..0]
18 x 25 Complex Multiplier
Arria V GZ devices support an individual 18 x 25 complex multiplication mode.
A 27 x 27 multiplier allows you to implement an individual 18 x 25 complex multiplication mode with three
variable precision DSP blocks only. The pre-adder feature is automatically enabled for you to implement an
individual 18 x 25 complex multiplication mode efficiently.
Figure 3-22: 18 x 25 Complex Multiplication Equation
Variable Precision DSP Blocks in Arria V Devices
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27 x 27 Complex Multiplier
Figure 3-23: 18 x 25 Complex Multiplier with Three Variable Precision DSP Blocks for Arria V GZ Devices
Multiplier
d[17..0]
25
Pre-adder &
Coefficient Select
a[24..0]
x
Input Register Bank
b[24..0]
25
x
18
Variable Precision DSP Block 1
b[24..0]
18
Pre-adder &
Coefficient Select
c[17..0]
Input Register Bank
d[17..0]
Chainout
Adder
+
x
Output Register Bank
Multiplier
18
44
[(c + d) b + (a - b) d]
25
Variable Precision DSP Block 2
a[24..0]
18
Pre-adder &
Coefficient Select
c[17..0]
Input Register Bank
d[17..0]
Chainout
Adder
+
x
Output Register Bank
Multiplier
18
44
[(c - d) a + (a - b) d]
25
Variable Precision DSP Block 3
27 x 27 Complex Multiplier
Arria V GZ devices support an individual 27 x 27 complex multiplication mode. You require four variable
precision DSP blocks to implement an individual 27 x 27 complex multiplication mode.
You can implement the imaginary part [(a x d) + (b x c)] in the first and second variable precision DSP
blocks, and you can implement the real part [(a x c) - (b x d)] in the third and fourth variable precision DSP
blocks.
You can achieve the difference of two 27 x 27 multiplications by enabling the NEGATE control signal in the
fourth variable precision DSP block.
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27 x 27 Complex Multiplier
3-29
Figure 3-24: 27 x 27 Complex Multiplier with Four Variable Precision Blocks for Arria V GZ Devices
d[26..0]
a[26..0]
27
Input Register Bank
Multiplier
27
x
Variable Precision DSP Block 1
b[26..0]
27
Chainout
Adder
Input Register Bank
c[26..0]
x
+
Output Register Bank
Multiplier
27
55
[(a × d) + (b × c)]
Variable Precision DSP Block 2
Multiplier
a[26..0]
27
Input Register Bank
c[26..0]
27
x
Variable Precision DSP Block 3
27
Input Register Bank
b[26..0]
27
Chainout
Adder
x
+
Output Register Bank
Multiplier
d[26..0]
55
[(a × c) - (b × d)]
Variable Precision DSP Block 4
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Multiplier Adder Sum Mode
Multiplier Adder Sum Mode
Table 3-9: Variable Precision DSP Block Multiplier Adder Sum Mode Configurations for Arria V Devices
Mode
Two-multiplier Adder Sum
Four-multiplier Adder Sum
Configuration
Number of DSP Blocks
Required
Device Variant Support
16 x 16
1
Arria V GZ
18 x 18
1
Arria V GZ
18 x 19
1
Arria V GX, GT, SX, ST
27 x 27
2
Arria V GZ
36 x 18
2
Arria V GZ
18 x 18
2
Arria V GZ
One Sum of Two 18 x 18 Multipliers or Two 16 x 16 Multipliers
Figure 3-25: One Sum of Two 18 x 18 Multipliers or Two 16 x 16 Multipliers with One Variable Precision
DSP Block for Arria V GZ Devices
In this figure, for 18-bit multiplier adder sum mode, the input data width is 18 bits and the output data width
is 37 bits.
For 16-bit multiplier adder sum mode, the input data width is 16 bits and the unused input bit requires
padding with zeroes. The output data width is 33 bits.
SUB
Multiplier
datab_0[ ]
x
+/Multiplier
Output Register Bank
datab_1[ ]
Input Register Bank
dataa_0[ ]
Result[]
x
dataa_1[ ]
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One Sum of Two 18 x 19 Multipliers
3-31
One Sum of Two 18 x 19 Multipliers
Figure 3-26: One Sum of Two 18 x 19 Multipliers with One Variable Precision DSP Block for Arria V GX, GT,
SX, and ST Devices
Variable-Precision DSP Block
SUB_COMPLEX
Multiplier
19
dataa_y0[18..0]
Chainout adder or
accumulator
x
18
datab_y1[18..0]
+/Multiplier
+
Output Register Bank
19
Input Register Bank
dataa_x0[17..0]
38
Result[37..0]
Adder
x
18
datab_x1[17..0]
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One Sum of Two 27 x 27 Multipliers
One Sum of Two 27 x 27 Multipliers
Figure 3-27: One Sum of Two 27 x 27 Multipliers with Two Variable Precision DSP Blocks for Arria V GZ
Devices
datab_0[26..0]
dataa_0[26..0]
27
27
Input Register Bank
Multiplier
x
Chainout[53..0]
Variable Precision DSP Block 1
dataa_1[26..0]
27
27
x
Chainout adder
+/-
+
Output Register Bank
datab_1[26..0]
Input Register Bank
Multiplier
55
Result[54..0]
NEGATE
Variable Precision DSP Block 2
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One Sum of Two 36 x 18 Multipliers
3-33
One Sum of Two 36 x 18 Multipliers
Figure 3-28: One Sum of Two 36 x 18 Multipliers with Two Variable Precision DSP Blocks for Arria V GZ
Devices
Multiplier
dataa_0[17..0]
datab_0[17..0]
dataa_0[35..18]
18
Input Register Bank
datab_0[17..0]
18
18
x
18
Variable Precision DSP Block 1
Multiplier
Chainout
Adder
18
Input Register Bank
dataa_1[17..0]
18
datab_1[17..0]
dataa_1[35..18]
+
+/x
18
Output Register Bank
datab_1[17..0]
55
result[54..0]
18
NEGATE
Variable Precision DSP Block 2
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One Sum of Four 18 x 18 Multipliers
One Sum of Four 18 x 18 Multipliers
Figure 3-29: One Sum of Four 18 x 18 Multipliers with Two Variable Precision DSP Blocks for Arria V GZ
Devices
SUB
Multiplier
18
datab_0[17..0]
x
dataa_0[17..0]
18
Input Register Bank
18
+/Multiplier
datab_1[17..0]
x
18
Adder
dataa_1[17..0]
Variable Precision DSP Block 1
SUB
Multiplier
18
datab_2[17..0]
x
18
Input Register Bank
dataa_2[17..0]
+/Multiplier
+/-
+
Output Register Bank
Chainout adder
18
38
result[37..0]
datab_3[17..0]
x
18
dataa_3[17..0]
Adder
NEGATE
Variable Precision DSP Block 2
Sum of Square Mode
The Arria V variable precision DSP block can implement one sum of square mode.
Figure 3-30: One Sum of Square Mode Equation
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18 x 18 Multiplication Summed with 36-Bit Input Mode
You can feed the four 18-bit inputs into the pre-adder block to convert b and d input as two’s complement
numbers to perform subtraction, if required.
You can feed each 18-bit pre-adder block output into both multiplicand and multiplier inputs of an 18 x 18
multiplier to generate a square result.
Figure 3-31: One Sum of Square Mode in a Variable Precision DSP Block for Arria V GZ Devices
SUB
Pre-Adder
Multiplier
18
+/-
b[17..0]
18
a[17..0]
18
Input Register Bank
18
c[17..0]
x
Adder
+/-
Pre-Adder
Multiplier
+/-
x
Output Register Bank
d[17..0]
37
result[36..0]
Variable Precision DSP Block
18 x 18 Multiplication Summed with 36-Bit Input Mode
Arria V variable precision DSP blocks support one 18 x 18 multiplication summed to a 36-bit input.
Use the upper multiplier to provide the input for an 18 x 18 multiplication, while the bottom multiplier is
bypassed.
The following signals are concatenated to produce a 36-bit input:
• Arria V GX, GT, SX, and ST devices: datab_y1[17..0] and datab_y1[35..18]
• Arria V GZ devices: data1[17..0] and data1[35..18]
Figure 3-32: One 18 x 18 Multiplication Summed with 36-Bit Input Mode for Arria V GX, GT, SX, and ST
Devices
Variable-Precision DSP Block
SUB_COMPLEX
Multiplier
18
18
datab_y1[35..18]
x
Chainout adder or
accumulator
+/-
+
Output Register Bank
18
dataa_x0[17..0]
Input Register Bank
dataa_y0[17..0]
37
Result[36..0]
18
datab_y1[17..0]
Adder
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Systolic FIR Mode
Figure 3-33: One 18 x 18 Multiplication Summed with 36-Bit Input Mode for Arria V GZ Devices
SUB
Multiplier
data_1[17..0]
18
18
Output Register Bank
dataa_0[17..0]
18
x
Input Register Bank
datab_0[17..0]
37
Result[36..0]
+/-
data_1[35..18]
18
Adder
Variable Precision DSP Block
Systolic FIR Mode
The basic structure of a FIR filter consists of a series of multiplications followed by an addition.
Figure 3-34: Basic FIR Filter Equation
Depending on the number of taps and the input sizes, the delay through chaining a high number of adders
can become quite large. To overcome the delay performance issue, the systolic form is used with additional
delay elements placed per tap to increase the performance at the cost of increased latency.
Figure 3-35: Systolic FIR Filter Equivalent Circuit
y[ n ]
w 2[ n ]
w 1[ n ]
c1
c2
w k[ n ]
w k−1[ n ]
c k −1
ck
x[ n ]
Arria V variable precision DSP blocks support the following systolic FIR structures:
• 18-bit
• 27-bit
In systolic FIR mode, the input of the multiplier can come from four different sets of sources:
•
•
•
•
Two dynamic inputs
One dynamic input and one coefficient input
One coefficient input and one pre-adder output
One dynamic input and one pre-adder output (for Arria V GX, GT, SX, and ST devices only)
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18-Bit Systolic FIR Mode
3-37
18-Bit Systolic FIR Mode
In 18-bit systolic FIR mode, the adders are configured as dual 44-bit adders, thereby giving 8 bits of overhead
when using an 18-bit operation (36-bit products). This allows a total of 256 multiplier products.
Figure 3-36: 18-Bit Systolic FIR Mode for Arria V GX, GT, SX, and ST Devices
chainin[43..0]
44
dataa_x0[17..0]
COEFSELA[2..0]
datab_y1[17..0]
datab_z1[17..0]
+/-
18
Systolic
Registers (1)
18
3
x
Internal
Coefficient
+/-
+
Adder
Chainout adder or
accumulator
Multiplier
Pre-Adder
18
18
datab_x1[17..0]
18
COEFSELB[2..0]
3
Output Register Bank
dataa_z0[17..0]
18
Input Register Bank
dataa_y0[17..0]
Systolic
Register (1)
Multiplier
Pre-Adder
+/x
44
Internal
Coefficient
Result[43..0]
18-bit Systolic FIR
44
chainout[43..0]
Note:
1. The systolic registers have the same clock source as the output register bank.
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27-Bit Systolic FIR Mode
Figure 3-37: 18-Bit Systolic FIR Mode with Two Dynamic Inputs for Arria V GZ Devices
chainin[43..0]
44
dataa_0[17..0]
+/-
18
datab_1[17..0]
dataa_1[17..0]
COEFSELB[2..0]
Systolic
Registers
x
+/-
+
Adder
Chainout adder/
accumulator
3
Input Register Bank
COEFSELA[2..0]
18
Internal
Coefficient
Multiplier
Pre-Adder
18
18
Output Register Bank
datab_0[17..0]
Systolic
Register
Multiplier
Pre-Adder
x
+/-
44
Result[43..0]
3
Internal
Coefficient
18-bit Systolic FIR
44
chainout[43..0]
27-Bit Systolic FIR Mode
In 27-bit systolic FIR mode, the chainout adder or accumulator is configured for a 64-bit operation, providing
10 bits of overhead when using a 27-bit data (54-bit products). This allows a total of 1,024 multiplier products.
The 27-bit systolic FIR mode allows the implementation of one stage systolic filter per DSP block.
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27-Bit Systolic FIR Mode
Figure 3-38: 27-Bit Systolic FIR Mode for Arria V GX, GT, SX, and ST Devices
chainin[63..0]
64
Multiplier
Pre-Adder
26
+/-
dataa_x0[26..0]
27
COEFSELA[2..0]
3
Input Register Bank
26
dataa_z0[25..0]
27
Output Register Bank
dataa_y0[25..0]
x
Internal
Coefficient
+/-
+
Adder
Chainout adder or
accumulator
27-bit Systolic FIR
64
chainout[63..0]
Figure 3-39: 27-Bit Systolic FIR Mode for Arria V GZ Devices
chainin[63..0]
64
Multiplier
Pre-Adder
27
datac_0[24..0]
25
COEFSELA[2..0]
3
+/27
x
+
Internal
Coefficient
Chainout adder or
accumulator
Output Register Bank
dataa_0[26..0]
27
Input Register Bank
datab_0[26..0]
64
chainout[63..0]
27-bit Systolic FIR
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Document Revision History
Document Revision History
Date
Version
Changes
May 2013
2013.05.06
• Added link to the known document issues in the Knowledge Base.
• Moved all links to the Related Information section of respective topics
for easy reference.
• Updated the variable DSP blocks and multipliers counts for the Arria V
SX and ST device variants.
• Updated Figure 3-21, changed 37 to 38.
• Updated Figure 3-22 by changing the Complex Multiplication Equation.
• Update Figure 3-26, changed 37 to 38.
November 2012
2012.11.29
• Added resources for Arria V devices.
• Updated design considerations for Arria V devices in operational modes.
• Added DSP block architecture in 27 x 27 mode for Arria V GX, GT, SX,
and ST devices.
• Added DSP block architecture in 18 x 18 and 27 x 27 modes for
Arria V GZ devices.
• Updated DSP block architecture information on input register bank,
pre-adder, multipliers, accumulator and chainout adder, and systolic
registers for Arria V GZ devices.
• Added 16 x 16, 18 x 18 (partial), 18 x 18, 36 x 18, and 36-bit independent
multiplier modes for Arria V GZ devices.
• Added 18 x 18, 18 x 25, and 27 x 27 independent complex multiplier
modes for Arria V GZ devices.
• Added 16 x 16, 18 x 18, 27 x 27, and 36 x 18 multiplier adder sum modes
for Arria V GZ devices.
• Added sum of square mode for Arria V GZ devices.
• Added 18 x 18 multiplication summed with 36-bit input mode for
Arria V GZ devices.
• Added 18-bit and 27-bit systolic FIR modes for Arria V GZ devices.
• Reorganized content and updated template.
June 2012
2.0
Updated for the Quartus II software v12.0 release:
• Restructured chapter.
• Added “Design Considerations”, “Adder”, and “Double Accumulation
Register” sections.
• Updated Figure 3–1 and Figure 3–13.
• Added Table 3–3.
• Updated “Systolic Registers” and “Systolic FIR Mode” sections.
• Added Equation 3–2.
• Added Figure 3–12.
May 2011
Altera Corporation
1.0
Initial release.
Variable Precision DSP Blocks in Arria V Devices
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Clock Networks and PLLs in Arria V Devices
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This chapter describes the advanced features of hierarchical clock networks and phase-locked loops (PLLs)
in Arria V devices. The Quartus II software enables the PLLs and their features without external devices.
Related Information
Arria V Device Handbook: Known Issues
Lists the planned updates to the Arria V Device Handbook chapters.
Clock Networks
The Arria V devices contain the following clock networks that are organized into a hierarchical structure:
• Global clock (GCLK) networks
• Regional clock (RCLK) networks
• Periphery clock (PCLK) networks
Clock Resources in Arria V Devices
Table 4-1: Clock Resources in Arria V Devices
Clock Resource
Clock input pins
Device
Number of
Resources Available
Source of Clock Resource
• Arria V GX A1 and A3
• Arria V GT C3
40 single-ended or CLK[0..7][p,n] and
20 differential
CLK[12..23][p,n] pins
• Arria V SX B3 and B5
• Arria V ST D3 and D5
40 single-ended or CLK[0..11][p,n] and
20 differential
CLK[16..23][p,n] pins
• Arria V GX A5, A7, B1,
B3, B5, and B7
• Arria V GT C7, D3, and
D7
• Arria V GZ E1, E3, E5,
and E7
48 single-ended or
CLK[0..23][p,n] pins
24 differential
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Types of Clock Networks
Clock Resource
GCLK and RCLK
networks
PCLK networks
Device
Number of
Resources Available
• Arria V GX A1 and A3
• Arria V GT C3
76
• Arria V SX B3 and B5
• Arria V ST D3 and D5
82
• Arria V GX A5, A7, B1,
B3, B5, and B7
• Arria V GT C7, D3, and
D7
88
Arria V GZ E1, E3, E5, and
E7
92
• Arria V GX A1 and A3
• Arria V GT C3
120
• Arria V GX A5 and A7
• Arria V GT C7
184
• Arria V SX B3 and B5
• Arria V ST D3 and D5
208
Arria V GZ E1 and E3
210
• Arria V GX B1 and B3
• Arria V GT D3
224
• Arria V GX B5 and B7
• Arria V GT D7
248
Arria V GZ E5 and E7
282
Source of Clock Resource
CLK[0..7][p,n] and
CLK[12..23][p,n] pins, PLL
clock outputs, and logic array
CLK[0..11][p,n] and
CLK[16..23][p,n] pins, PLL
clock outputs, and logic array
CLK[0..23][p,n] pins, PLL
clock outputs, and logic array
DPA clock outputs, PLDtransceiver interface clocks,
I/O pins, and logic array
For more information about the clock input pins connections, refer to the pin connection guidelines.
Related Information
• Arria V GT and GX Device Family Pin Connection Guidelines
• Arria V GZ Device Family Pin Connection Guidelines
Types of Clock Networks
Global Clock Networks
Arria V devices provide GCLKs that can drive throughout the device. The GCLKs serve as low-skew clock
sources for functional blocks, such as adaptive logic modules (ALMs), digital signal processing (DSP),
embedded memory, and PLLs. Arria V I/O elements (IOEs) and internal logic can also drive GCLKs to
create internally-generated global clocks and other high fan-out control signals, such as synchronous or
asynchronous clear and clock enable signals.
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Regional Clock Networks
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Figure 4-1: GCLK Networks in Arria V Devices
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
GCLK[12..15]
GCLK[0..3]
Q1
Q4
Q2
Q3
GCLK[8..11]
GCLK[4..7]
Regional Clock Networks
RCLK networks are only applicable to the quadrant they drive into. RCLK networks provide the lowest clock
insertion delay and skew for logic contained within a single device quadrant. The Arria V IOEs and internal
logic within a given quadrant can also drive RCLKs to create internally generated regional clocks and other
high fan-out control signals.
Figure 4-2: RCLK Networks in Arria V GX, GT, SX, and ST Devices
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
RCLK[0..9]
RCLK[10..19]
RCLK[40..45]
RCLK[46..51]
RCLK[64..69]
RCLK[70..75]
RCLK[46..51] pins are not available
for Arria V GX A1 and A3 devices,
Arria V GT devices, Arria V SX B3
and B5 devices, and Arria V ST D3
and D5 devices.
Q1 Q2
Q4 Q3
RCLK[82..87]
RCLK[76..81]
RCLK[58..63]
RCLK[52..57]
RCLK[30..39]
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RCLK[52..57] pins are not available
for Arria V GX A1 and A3 devices,
and Arria V GT devices.
RCLK[20..29]
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Periphery Clock Networks
Figure 4-3: RCLK Networks in Arria V GZ Devices
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
RCLK[0..9]
RCLK[10..19]
RCLK[40..45]
RCLK[46..51]
RCLK[64..70]
RCLK[71..77]
Q1 Q2
Q4 Q3
RCLK[85..91]
RCLK[78..84]
RCLK[58..63]
RCLK[52..57]
RCLK[30..39]
RCLK[20..29]
Periphery Clock Networks
Depending on the routing direction, Arria V devices provide vertical PCLKs from the top and bottom
periphery, and horizontal PCLKs from the left and right periphery.
Clock outputs from the dynamic phase aligner (DPA) block, programmable logic device (PLD)-transceiver
interface clocks, I/O pins, and internal logic can drive the PCLK networks.
PCLKs have higher skew when compared with GCLK and RCLK networks. You can use PCLKs for general
purpose routing to drive signals into and out of the Arria V device.
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Clock Sources Per Quadrant
4-5
Figure 4-4: PCLK Networks in Arria V Devices
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
Vertical
PCLK
Horizontal
PCLK
Vertical
PCLK
Q2
Q4
Q3
Vertical PCLK
Horizontal
PCLK
Q1
Vertical PCLK
Horizontal
PCLK
Horizontal
PCLK
Vertical PCLK
Vertical PCLK
Horizontal
PCLK
Vertical
PCLK
Horizontal
PCLK
Horizontal
PCLK
Horizontal
PCLK
Vertical
PCLK
Clock Sources Per Quadrant
The Arria V devices provide 30 section clock (SCLK) networks in each spine clock per quadrant. The SCLK
networks can drive six row clocks in each logic array block (LAB) row, nine column I/O clocks, and two
core reference clocks. The SCLKs are the clock resources to the core functional blocks, PLLs, and I/O interfaces
of the device.
A spine clock is another layer of routing between the GCLK, RCLK, and PCLK networks before each clock
is connected to the clock routing for each LAB row. The settings for spine clocks are transparent. The
Quartus II software automatically routes the spine clock based on the GCLK, RCLK, and PCLK networks.
The following figure shows SCLKs driven by the GCLK, RCLK, PCLK, or the PLL feedback clock networks
in each spine clock per quadrant. The GCLK, RCLK, PCLK, and PLL feedback clocks share the same routing
to the SCLKs. To ensure successful design fitting in the Quartus II software, the total number of clock
resources must not exceed the SCLK limits in each region.
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Types of Clock Regions
Figure 4-5: Hierarchical Clock Networks in Each Spine Clock Per Quadrant
Clock output from the PLL that
drives into the SCLKs.
GCLK
PLL Feedback Clock
PCLK
RCLK
9
Column I/O clock: clock that drives
the I/O column core registers and I/O interfaces.
2
Core reference clock: clock that feeds
into the PLL as the PLL reference clock.
6
Row clock: clock source to the LAB,
memory blocks, and row I/O interfaces
in the core row.
16
5
72
SCLK
30
23
There are up to 72 PCLKs that can
drive the SCLKs in each spine clock
per quadrant in the largest device.
There are up to 23 RCLKs that can
drive the SCLKs in each spine clock
per quadrant in the largest device.
Types of Clock Regions
This section describes the types of clock regions in Arria V devices.
Entire Device Clock Region
To form the entire device clock region, a source drives a signal in a GCLK network that can be routed through
the entire device. The source is not necessarily a clock signal. This clock region has the maximum insertion
delay when compared with other clock regions, but allows the signal to reach every destination in the device.
It is a good option for routing global reset and clear signals or routing clocks throughout the device.
Regional Clock Region
To form a regional clock region, a source drives a signal in a RCLK network that you can route throughout
one quadrant of the device. This clock region provides the lowest skew in a quadrant. It is a good option if
all the destinations are in a single quadrant.
Dual-Regional Clock Region
To form a dual-regional clock region, a single source (a clock pin or PLL output) generates a dual-regional
clock by driving two RCLK networks (one from each quadrant). This technique allows destinations across
two adjacent device quadrants to use the same low-skew clock. The routing of this signal on an entire side
has approximately the same delay as a RCLK region. Internal logic can also drive a dual-regional clock
network.
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Clock Network Sources
4-7
Figure 4-6: Dual-Regional Clock Region for Arria V Devices
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
Clock pins or PLL outputs can
drive half of the device to create
dual-regional clocking regions
for improved interface timing.
Clock Network Sources
In Arria V devices, clock input pins, PLL outputs, high-speed serial interface (HSSI) outputs, DPA outputs,
and internal logic can drive the GCLK, RCLK, and PCLK networks.
Dedicated Clock Input Pins
You can use the dedicated clock input pins (CLK[0..23][p,n]) for high fan-out control signals, such as
asynchronous clears, presets, and clock enables, for protocol signals through the GCLK or RCLK networks.
CLK pins can be either differential clocks or single-ended clocks. When you use the CLK pins as single-ended
clock inputs, only the CLK<#>p pins have dedicated connections to the PLL. The CLK<#>n pins drive the PLLs
over global or regional clock networks and do not have dedicated routing paths to the PLLs.
Driving a PLL over a global or regional clock can lead to higher jitter at the PLL input, and the PLL will not
be able to fully compensate for the global or regional clock. Altera recommends using the CLK<#>p pins for
optimal performance when you use single-ended clock inputs to drive the PLLs.
Internal Logic
You can drive each GCLK, RCLK, and horizontal PCLK network using LAB-routing and row clock to enable
internal logic to drive a high fan-out, low-skew signal.
Note: Internally-generated GCLKs, RCLKs, or PCLKs cannot drive the Arria V PLLs. The input clock to
the PLL has to come from dedicated clock input pins, PLL-fed GCLKs, or PLL-fed RCLKs.
DPA Outputs
Every DPA generates one PCLK to the core.
Related Information
High-Speed I/O Design Guidelines for Arria V Devices on page 6-7
Provides more information about DPA and HSSI outputs.
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HSSI Outputs
HSSI Outputs
Every three HSSI outputs generate a group of six PCLKs to the core.
Related Information
High-Speed I/O Design Guidelines for Arria V Devices on page 6-7
Provides more information about DPA and HSSI outputs.
PLL Clock Outputs
The Arria V PLL clock outputs can drive both GCLK and RCLK networks.
Clock Input Pin Connections to GCLK and RCLK Networks
Table 4-2: Dedicated Clock Input Pin Connectivity to the GCLK Networks for Arria V Devices
Clock Resources
CLK (p/n Pins)
GCLK[0,1,2,3]
CLK[0,1,2,3,20,21,22,23]
GCLK[4,5,6,7]
CLK[4,5,6,7]
GCLK[8,9,10,11]
CLK[8,9,10,11]
GCLK[12,13,14,15]
CLK[16,17,18,19]
(4)
and CLK[12,13,14,15](5)
Table 4-3: Dedicated Clock Input Pin Connectivity to the RCLK Networks for Arria V GX, GT, SX, and ST Devices
A given clock input pin can drive two adjacent RCLK networks to create a dual-regional clock network.
Clock Resources
(4)
(5)
CLK (p/n Pins)
RCLK[58,59,60,61,62,63,64,68,82,86]
CLK[0]
RCLK[58,59,60,61,62,63,65,69,83,87]
CLK[1]
RCLK[58,59,60,61,62,63,66,84]
CLK[2]
RCLK[58,59,60,61,62,63,67,85]
CLK[3]
RCLK[20,24,28,30,34,38]
CLK[4]
RCLK[21,25,29,31,35,39]
CLK[5]
RCLK[22,26,32,36]
CLK[6]
RCLK[23,27,33,37]
CLK[7]
(4)
RCLK[52,53,54,55,56,57,70,74,76,80]
CLK[8]
RCLK[52,53,54,55,56,57,71,75,77,81]
CLK[9]
RCLK[52,53,54,55,56,57,72,78]
CLK[10]
RCLK[52,53,54,55,56,57,73,79]
CLK[11]
(4)
(4)
(4)
CLK[8,9,10,11] are not available for Arria V GX A1 and A3 devices, and Arria V GT devices.
CLK[12,13,14,15] are not available for Arria V SX B3 and B5 devices, and Arria V ST D3 and D5 devices.
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Clock Input Pin Connections to GCLK and RCLK Networks
Clock Resources
CLK (p/n Pins)
RCLK[46,47,48,49,50,51,70,74,76,80]
(6)
(6)
RCLK[46,47,48,49,50,51,71,75,77,81]
RCLK[46,47,48,49,50,51,72,78]
RCLK[46,47,48,49,50,51,73,79]
4-9
(6)
(6)
CLK[12]
CLK[13]
CLK[14]
CLK[15]
(5)
(5)
(5)
(5)
RCLK[0,4,8,10,14,18]
CLK[16]
RCLK[1,5,9,11,15,19]
CLK[17]
RCLK[2,6,12,16]
CLK[18]
RCLK[3,7,13,17]
CLK[19]
RCLK[40,41,42,43,44,45,64,68,82,86]
CLK[20]
RCLK[40,41,42,43,44,45,65,69,83,87]
CLK[21]
RCLK[40,41,42,43,44,45,66,84]
CLK[22]
RCLK[40,41,42,43,44,45,67,85]
CLK[23]
Table 4-4: Dedicated Clock Input Pin Connectivity to the RCLK Networks for Arria V GZ Devices
A given clock input pin can drive two adjacent RCLK networks to create a dual-regional clock network.
Clock Resources
(6)
CLK (p/n Pins)
RCLK[58,59,60,61,62,63,64,68,85,89]
CLK[0]
RCLK[58,59,60,61,62,63,65,69,86,90]
CLK[1]
RCLK[58,59,60,61,62,63,66,70,87,91]
CLK[2]
RCLK[58,59,60,61,62,63,67,88]
CLK[3]
RCLK[20,24,28,30,34,38]
CLK[4]
RCLK[21,25,29,31,35,39]
CLK[5]
RCLK[22,26,32,36]
CLK[6]
RCLK[23,27,33,37]
CLK[7]
RCLK[52,53,54,55,56,57,71,75,78,82]
CLK[8]
RCLK[52,53,54,55,56,57,72,76,79,83]
CLK[9]
RCLK[52,53,54,55,56,57,73,77,80,84]
CLK[10]
RCLK[52,53,54,55,56,57,74,81]
CLK[11]
RCLK[46,47,48,49,50,51,71,75,78,82]
CLK[12]
RCLK[46,47,48,49,50,51,72,76,79,83]
CLK[13]
RCLK[46,47,48,49,50,51,73,77,80,84]
CLK[14]
RCLK[46,47,48,49,50,51,74,81]
CLK[15]
RCLK[46..51] are not available for Arria V GX A1 and A3 devices, and Arria V GT devices.
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Clock Output Connections
Clock Resources
CLK (p/n Pins)
RCLK[0,4,8,10,14,18]
CLK[16]
RCLK[1,5,9,11,15,19]
CLK[17]
RCLK[2,6,12,16]
CLK[18]
RCLK[3,7,13,17]
CLK[19]
RCLK[40,41,42,43,44,45,64,68,85,89]
CLK[20]
RCLK[40,41,42,43,44,45,65,69,86,90]
CLK[21]
RCLK[40,41,42,43,44,45,66,70,87,91]
CLK[22]
RCLK[40,41,42,43,44,45,67,88]
CLK[23]
Clock Output Connections
For Arria V PLL connectivity to GCLK and RCLK networks, refer to the PLL connectivity to GCLK and
RCLK networks spreadsheet.
Related Information
PLL Connectivity to GCLK and RCLK Networks for Arria V Devices
Clock Control Block
Every GCLK, RCLK, and PCLK network has its own clock control block. The control block provides the
following features:
• Clock source selection (dynamic selection available only for GCLKs)
• Global clock multiplexing
• Clock power down (static or dynamic clock enable or disable available only for GCLKs and RCLKs)
Pin Mapping in Arria V Devices
Table 4-5: Mapping Between the Input Clock Pins, PLL Counter Outputs, and Clock Control Block Inputs
Clock
Fed by
inclk[0] and inclk[1]
Any of the four dedicated clock pins on the same side of the Arria V device.
inclk[2]
PLL counters C0 and C2 from the two center PLLs on the same side of the
Arria V devices.
inclk[3]
PLL counters C1 and C3 from the two center PLLs on the same side of the
Arria V devices.
Note: You cannot use corner PLLs for dynamic clock control selection.
GCLK Control Block
You can select the clock source for the GCLK select block either statically or dynamically using internal logic
to drive the multiplexer-select inputs.
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RCLK Control Block
4-11
When selecting the clock source dynamically, you can select either PLL outputs (such as C0 or C1), or a
combination of clock pins or PLL outputs.
Figure 4-7: GCLK Control Block for Arria V Devices
The CLKn pin is not a dedicated
clock input when used as a
single-ended PLL clock input. The
CLKn pin can drive the PLL using
the GCLK.
CLKp
Pins
PLL Counter
Outputs
When the device is in user mode,
you can dynamically control the
clock select signals through
internal logic.
2
2
CLKn
Pin
Internal
Logic
2
CLKSELECT[1..0]
Static Clock
Select
This multiplexer
supports user-controllable
dynamic switching
Enable/
Disable
GCLK
When the device is in user mode, you can
only set the clock select signals through a
configuration file (SRAM object file [.sof] or
programmer object file [.pof]) because the
signals cannot be controlled dynamically.
Internal
Logic
RCLK Control Block
You can only control the clock source selection for the RCLK select block statically using configuration bit
settings in the configuration file (.sof or .pof) generated by the Quartus II software.
Figure 4-8: RCLK Control Block for Arria V Devices
CLKp
Pin
PLL Counter
Outputs
The CLKn pin is not a dedicated
clock input when used as a
single-ended PLL clock input. The
CLKn pin can drive the PLL using
the RCLK.
CLKn
Pin
2
Internal Logic
Static Clock Select
Enable/
Disable
When the device is in user mode,
you can only set the clock select
signals through a configuration file
(.sof or .pof); they cannot be
controlled dynamically.
Internal
Logic
RCLK
You can set the input clock sources and the clkena signals for the GCLK and RCLK network multiplexers
through the Quartus II software using the ALTCLKCTRL megafunction.
Note: When selecting the clock source dynamically using the ALTCLKCTRL megafunction, choose the
inputs using the CLKSELECT[0..1] signal. The inputs from the clock pins feed the inclk[0..1]
ports of the multiplexer, and the PLL outputs feed the inclk[2..3] ports.
Related Information
Clock Control Block (ALTCLKCTRL) Megafunction User Guide
Provides more information about ALTCLKCTRL megafunction.
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PCLK Control Block
PCLK Control Block
To drive the HSSI horizontal PCLK control block, select the HSSI output or internal logic .
To drive the DPA vertical PCLK, select the DPA clock output or internal logic . You can only use the DPA
clock output to generate the vertical PCLK to the core.
Figure 4-9: Horizontal PCLK Control Block for Arria V Devices
HSSI Output or
DPA Clock Output
Internal Logic
Static Clock Select
Horizontal PCLK
External PLL Clock Output Control Block
You can enable or disable the dedicated external clock output pins using the ALTCLKCTRL megafunction.
Figure 4-10: External PLL Output Clock Control Block for Arria V Devices
PLL Counter
Outputs
18
Static Clock Select
Enable/
Disable
Internal
Logic
The clock control block feeds to a multiplexer
within the FPLL_<#>_CLKOUT pin’s IOE. The
FPLL_<#>_CLKOUT pin is a dual-purpose pin.
Therefore, this multiplexer selects either an
internal signal or the output of the clock control
block.
IOE
When the device is in user mode,
you can only set the clock select
signals through a configuration file
(.sof or .pof); they cannot be
controlled dynamically.
Internal
Logic
Static Clock
Select
FPLL_<#>_CLKOUT pin
Related Information
Clock Control Block (ALTCLKCTRL) Megafunction User Guide
Provides more information about ALTCLKCTRL megafunction.
Clock Power Down
You can power down the GCLK and RCLK clock networks using both static and dynamic approaches.
When a clock network is powered down, all the logic fed by the clock network is in off-state, reducing the
overall power consumption of the device. The unused GCLK, RCLK, and PCLK networks are automatically
powered down through configuration bit settings in the configuration file (.sof or .pof) generated by the
Quartus II software.
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Clock Enable Signals
4-13
The dynamic clock enable or disable feature allows the internal logic to control power-up or power-down
synchronously on the GCLK and RCLK networks, including dual-regional clock regions. This feature is
independent of the PLL and is applied directly on the clock network.
Note: You cannot dynamically enable or disable GCLK or RCLK networks that drive PLLs.
Clock Enable Signals
You cannot use the clock enable and disable circuit of the clock control block if the GCLK or RCLK output
drives the input of a PLL.
Figure 4-11: clkena Implementation with Clock Enable and Disable Circuit
This figure shows the implementation of the clock enable and disable circuit of the clock control block.
The R1 and R2 bypass paths
are not available for the PLL
external clock outputs.
clkena
Clock Select
Multiplexer Output
D
Q
R1
D
Q
R2
GCLK/
RCLK/
FPLL_<#>_CLKOUT
The select line is statically
controlled by a bit setting in
the .sof or .pof.
The clkena signals are supported at the clock network level instead of at the PLL output counter level. This
allows you to gate off the clock even when you are not using a PLL. You can also use the clkena signals to
control the dedicated external clocks from the PLLs.
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Arria V PLLs
Figure 4-12: Example of clkena Signals
This figure shows a waveform example for a clock output enable. The clkena signal is synchronous to the
falling edge of the clock output.
Clock Select
Multiplexer Output
Use the clkena signals to
enable or disable the GCLK
and RCLK networks or the
FPLL_<#>_CLKOUT pins.
clkena
AND Gate Output
with R2 Bypassed
(ena Port Registered as
Falling Edge of Input Clock)
AND Gate Output
with R2 Not Bypassed
(ena Port Registered as Double
Register with Input Clock)
Arria V devices have an additional metastability register that aids in asynchronous enable and disable of the
GCLK and RCLK networks. You can optionally bypass this register in the Quartus II software.
The PLL can remain locked, independent of the clkena signals, because the loop-related counters are not
affected. This feature is useful for applications that require a low-power or sleep mode. The clkena signal
can also disable clock outputs if the system is not tolerant of frequency overshoot during resynchronization.
Arria V PLLs
PLLs provide robust clock management and synthesis for device clock management, external system clock
management, and high-speed I/O interfaces.
The Arria V device family contains fractional PLLs that can function as fractional PLLs or integer PLLs. The
output counters in Arria V devices are dedicated to each fractional PLL that support integer or fractional
frequency synthesis.
Two adjacent PLLs share 18 C output counters. Any number of C counters can be assigned to each PLL, as
long as the total number used by the two PLLs is 18 or less.
The Arria V devices offer up to 16 fractional PLLs in the larger densities. All Arria V fractional PLLs have
the same core analog structure and features support.
Table 4-6: PLL Features in Arria V Devices
Feature
Integer PLL
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Support
Yes
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PLL Physical Counters in Arria V Devices
Feature
Support
Fractional PLL
Yes
C output counters
18
M, N, C counter sizes
Dedicated external clock outputs
1 to 512
4 single-ended or 2 single-ended and 1 differential
Dedicated clock input pins
4 single-ended or 4 differential
External feedback input pin
Single-ended or differential
Spread-spectrum input clock tracking
Yes (7)
Source synchronous compensation
Yes
Direct compensation
Yes
Normal compensation
Yes
Zero-delay buffer compensation
Yes
External feedback compensation
Yes
LVDS compensation
Yes
Voltage-controlled oscillator (VCO) output drives
the DPA clock
Yes
Phase shift resolution
4-15
78.125 ps (8)
Programmable duty cycle
Yes
Power down mode
Yes
PLL Physical Counters in Arria V Devices
The physical counters for the fractional PLLs are arranged in the following sequences:
• Up-to-down
• Down-to-up
(7)
(8)
Provided input clock jitter is within input jitter tolerance specifications. The modulation frequency of the input
clock is below the PLL bandwidth which is specified in the Fitter report.
The smallest phase shift is determined by the VCO period divided by eight. For degree increments, the Arria V
device can shift all output frequencies in increments of at least 45°. Smaller degree increments are possible
depending on the frequency and divide parameters.
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PLL Locations in Arria V Devices
Figure 4-13: PLL Physical Counters Orientation for Arria V Devices
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
Physical Counter C0
Physical Counter C17
Physical Counter C1
Physical Counter C16
PLL1
PLL0
Physical Counter C8
Physical Counter C9
Physical Counter C9
Physical Counter
C0 to C17
(Up-to-Down
Dequence)
Physical Counter
C17 to C0
(Down-to-Up
Sequence)
Physical Counter C8
PLL0
PLL1
Physical Counter C16
Physical Counter C1
Physical Counter C17
Physical Counter C0
PLL Locations in Arria V Devices
Arria V devices provide PLLs for the transceiver channels. These PLLs are located in a strip, where the strip
refers to an area in the FPGA.
The total number of PLLs in the Arria V devices includes the PLLs in the PLL strip. However, the transceivers
can only use the PLLs located in the strip.
The following figures show the physical locations of the fractional PLLs. Every index represents one fractional
PLL in the device. The physical locations of the fractional PLLs correspond to the coordinates in the Quartus II
Chip Planner.
Figure 4-14: PLL Locations for Arria V GX A1 and A3 Devices, and Arria V GT C3 Device
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
CLK[16..19][p,n]
Pins
FRACTIONALPLL_XO_Y60
FRACTIONALPLL_XO_Y51
4
FRACTIONALPLL_XO_Y18
FRACTIONALPLL_XO_Y9
4
FRACTIONALPLL_X43_Y65
FRACTIONALPLL_X43_Y56
FRACTIONALPLL_X43_Y11
FRACTIONALPLL_X43_Y2
4 Logical Clocks
Pins
CLK[12..15][p,n]
PLL Strip
4 Logical Clocks
4 Logical Clocks
4 Logical Clocks
FRACTIONALPLL_X97_Y40
FRACTIONALPLL_X97_Y31
CLK[20..23][p,n]
Pins
4 Logical Clocks
Pins
CLK[0..3][p,n]
Pins
CLK[4..7][p,n]
Note:
1. Fractional PLL coordinates for Arria V GT C3 devices will be finalized in a future release of the Quartus II software.
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Figure 4-15: PLL Locations for Arria V GX A5 and A7 Devices, and Arria V GT C7 Device
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
CLK[20..23][p,n]
Pins
CLK[16..19][p,n]
Pins
4 Logical Clocks
PLL Strip
FRACTIONALPLL_XO_Y65
FRACTIONALPLL_XO_Y56
4
FRACTIONALPLL_XO_Y23
FRACTIONALPLL_XO_Y14
4
CLK[12..15][p,n]
Pins
4 Logical Clocks
4 Logical Clocks
PLL Strip
FRACTIONALPLL_X58_Y76
FRACTIONALPLL_X58_Y67
4
FRACTIONALPLL_X132_Y65
FRACTIONALPLL_X132_Y56
4
FRACTIONALPLL_X132_Y23
FRACTIONALPLL_X132_Y14
FRACTIONALPLL_X58_Y11
FRACTIONALPLL_X58_Y2
4 Logical Clocks
4 Logical Clocks
4 Logical Clocks
Pins
Pins
Pins
CLK[0..3][p,n]
CLK[4..7][p,n]
CLK[8..11][p,n]
Note:
1. Fractional PLL coordinates for Arria V GT C7 device will be finalized in the future release of the Quartus II software.
Figure 4-16: PLL Locations for Arria V GX B1 and B3 Devices, and Arria V GT D3 Device
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
CLK[20..23][p,n]
Pins
CLK[16..19][p,n]
Pins
4 Logical Clocks
PLL Strip
FRACTIONALPLL_XO_Y69
FRACTIONALPLL_XO_Y60
4
FRACTIONALPLL_XO_Y27
FRACTIONALPLL_XO_Y18
4
4 Logical Clocks
PLL Strip
4
FRACTIONALPLL_X169_Y69
FRACTIONALPLL_X169_Y60
4
FRACTIONALPLL_X169_Y27
FRACTIONALPLL_X169_Y18
FRACTIONALPLL_X81_Y11
FRACTIONALPLL_X81_Y2
Pins
CLK[0..3][p,n]
Send Feedback
4 Logical Clocks
FRACTIONALPLL_X81_Y86
FRACTIONALPLL_X81_Y77
4 Logical Clocks
Clock Networks and PLLs in Arria V Devices
CLK[12..15][p,n]
Pins
4 Logical Clocks
Pins
CLK[4..7][p,n]
4 Logical Clocks
Pins
CLK[8..11][p,n]
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PLL Locations in Arria V Devices
Figure 4-17: PLL Locations for Arria V GX B5 and B7 Devices, and Arria V GT D7 Device
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
CLK[20..23][p,n]
Pins
CLK[16..19][p,n]
Pins
4 Logical Clocks
CLK[12..15][p,n]
Pins
4 Logical Clocks
PLL Strip
4 Logical Clocks
FRACTIONALPLL_X81_Y112
FRACTIONALPLL_X81_Y103
FRACTIONALPLL_XO_Y105
FRACTIONALPLL_XO_Y96
4
4
CLK2, CLK3, CLK20, and CLK21
clock pins feed into
FRACTIONALPLL_X0_Y54 and
FRACTIONALPLL_X0_Y63.
2
FRACTIONALPLL_XO_Y63
FRACTIONALPLL_XO_Y54
FRACTIONALPLL_XO_Y19
FRACTIONALPLL_XO_Y10
PLL Strip
2
CLK10, CLK11, CLK12, and
CLK13 clock pins feed into
FRACTIONALPLL_X183_Y54 and
FRACTIONALPLL_X183_Y63.
2
2
4
4
FRACTIONALPLL_X81_Y11
FRACTIONALPLL_X81_Y2
4 Logical Clocks
4 Logical Clocks
Pins
CLK[0..3][p,n]
FRACTIONALPLL_X183_Y105
FRACTIONALPLL_X183_Y96
FRACTIONALPLL_X183_Y63
FRACTIONALPLL_X183_Y54
FRACTIONALPLL_X183_Y19
FRACTIONALPLL_X183_Y10
4 Logical Clocks
Pins
CLK[8..11][p,n]
Pins
CLK[4..7][p,n]
Figure 4-18: PLL Locations for Arria V GZ E1 and E3 Devices
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
CLK[20..23][p,n]
Pins
Logical Clocks
FRACTIONALPLL_X0_Y81
FRACTIONALPLL_X0_Y72
4
CLK[16..19][p,n]
Pins
CLK[12..15][p,n]
Pins
4 Logical Clocks
4
4 Logical Clocks
FRACTIONALPLL_X185_Y81
FRACTIONALPLL_X185_Y72
4
FRACTIONALPLL_X86_Y77
FRACTIONALPLL_X86_Y68
PLL Strip
PLL Strip
FRACTIONALPLL_X0_Y55
FRACTIONALPLL_X0_Y46
4
4
FRACTIONALPLL_X185_Y55
FRACTIONALPLL_X185_Y46
FRACTIONALPLL_X0_Y33
FRACTIONALPLL_X0_Y24
4
4
FRACTIONALPLL_X185_Y33
FRACTIONALPLL_X185_Y24
FRACTIONALPLL_X0_Y10
FRACTIONALPLL_X0_Y1
4
4
FRACTIONALPLL_X185_Y10
FRACTIONALPLL_X185_Y1
Logical Clocks
FRACTIONALPLL_X86_Y11
FRACTIONALPLL_X86_Y2
4
Pins
CLK[0..3][p,n]
Altera Corporation
4 Logical Clocks
Pins
CLK[4..7][p,n]
4 Logical Clocks
Pins
CLK[8..11][p,n]
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4-19
Figure 4-19: PLL Locations for Arria V GZ E5 and E7 Devices
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
CLK[20..23][p,n]
Pins
Logical Clocks
FRACTIONALPLL_X0_Y100
FRACTIONALPLL_X0_Y91
CLK[16..19][p,n]
Pins
CLK[12..15][p,n]
Pins
4 Logical Clocks
4
4
4 Logical Clocks
FRACTIONALPLL_X92_Y96
FRACTIONALPLL_X92_Y87
FRACTIONALPLL_X202_Y100
FRACTIONALPLL_X202_Y91
4
PLL Strip
PLL Strip
FRACTIONALPLL_X0_Y77
FRACTIONALPLL_X0_Y68
FRACTIONALPLL_X0_Y55
FRACTIONALPLL_X0_Y46
4
FRACTIONALPLL_X202_Y77
FRACTIONALPLL_X202_Y68
4
CLK0, CLK1, CLK22, and
CLK23 clock pins feed into
FRACTIONALPLL_X0_Y46
and
FRACTIONALPLL_X0_Y55.
2
2
FRACTIONALPLL_X0_Y31
FRACTIONALPLL_X0_Y22
4
FRACTIONALPLL_X0_Y10
FRACTIONALPLL_X0_Y1
4
CLK8, CLK9, CLK14, and
CLK15 clock pins feed into
FRACTIONALPLL_X202_Y46
and
FRACTIONALPLL_X202_Y55.
2
FRACTIONALPLL_X92_Y11
FRACTIONALPLL_X92_Y2
Logical Clocks
4 Logical Clocks
4
Pins
CLK[0..3][p,n]
Pins
CLK[4..7][p,n]
2
FRACTIONALPLL_X202_Y55
FRACTIONALPLL_X202_Y46
4
FRACTIONALPLL_X202_Y31
FRACTIONALPLL_X202_Y22
4
FRACTIONALPLL_X202_Y10
FRACTIONALPLL_X202_Y1
4 Logical Clocks
Pins
CLK[8..11][p,n]
Figure 4-20: PLL Locations for Arria V SX B3 and B5 Devices, and Arria V ST D3 and D5 Devices
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
CLK[20..23][p,n]
Pins
CLK[16..19][p,n]
Pins
4 Logical Clocks
PLL Strip
FRACTIONALPLL_XO_Y105
FRACTIONALPLL_XO_Y96
4
4 Logical Clocks
FRACTIONALPLL_X81_Y112
FRACTIONALPLL_X81_Y103
PLL Strip
2
FRACTIONALPLL_XO_Y63
FRACTIONALPLL_XO_Y54
FRACTIONALPLL_XO_Y19
FRACTIONALPLL_XO_Y10
2
CLK2, CLK3, CLK20, and CLK21
clock pins feed into
FRACTIONALPLL_X0_Y54 and
FRACTIONALPLL_X0_Y63.
4
2
4
FRACTIONALPLL_X81_Y11
FRACTIONALPLL_X81_Y2
4 Logical Clocks
Pins
CLK[0..3][p,n]
4 Logical Clocks
Pins
CLK[4..7][p,n]
FRACTIONALPLL_X183_Y63
FRACTIONALPLL_X183_Y54
FRACTIONALPLL_X183_Y19
FRACTIONALPLL_X183_Y10
4 Logical Clocks
Pins
CLK[8..11][p,n]
Related Information
PLL Migration Guidelines on page 4-20
Provides more information about PLL migration between Arria V GX A5, A7, B1, B3, B5, and B7 devices,
and Arria V GT C7, D3, and D7 devices.
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PLL Migration Guidelines
PLL Migration Guidelines
If you plan to migrate your design between Arria V GX A5, A7, B1, B3, B5, and B7 devices, and Arria V GT C7,
D3, and D7 devices, and your design requires a PLL to drive the HSSI and clock network (GCLK or RCLK),
use the PLLs on the left and right side of the device.
Table 4-7: Location of PLLs for PLL Migration
Variant
PLL Location
Member Code
Arria V GX
Arria V GT
Left Side
Right Side
A5, A7
FRACTIONALPLL_X0_Y14,
FRACTIONALPLL_X0_Y23
FRACTIONALPLL_X132_Y14,
FRACTIONALPLL_X132_Y23
B1, B3
FRACTIONALPLL_X0_Y18,
FRACTIONALPLL_X0_Y27
FRACTIONALPLL_X169_Y18,
FRACTIONALPLL_X169_Y27
B5, B7
FRACTIONALPLL_X0_Y10,
FRACTIONALPLL_X0_Y19
FRACTIONALPLL_X183_Y10,
FRACTIONALPLL_X183_Y19
C7
FRACTIONALPLL_X0_Y14,
FRACTIONALPLL_X0_Y23
FRACTIONALPLL_X132_Y14,
FRACTIONALPLL_X132_Y23
D3
FRACTIONALPLL_X0_Y18,
FRACTIONALPLL_X0_Y27
FRACTIONALPLL_X169_Y18,
FRACTIONALPLL_X169_Y27
D7
FRACTIONALPLL_X0_Y10,
FRACTIONALPLL_X0_Y19
FRACTIONALPLL_X183_Y10,
FRACTIONALPLL_X183_Y19
Related Information
PLL Locations in Arria V Devices on page 4-16
Provides more information about CLKIN pin connectivity to the PLLs.
Fractional PLL Architecture
Figure 4-21: Fractional PLL High-Level Block Diagram for Arria V Devices
To DPA Block
For single-ended clock inputs, only the CLK<#>p pin
has a dedicated connection to the PLL. If you use the
CLK<#>n pin, a global or regional clock is used.
Dedicated
Clock Inputs
GCLK/RCLK
locked
÷2, ÷4
4
inclk0
Clock
inclk1 Switchover
Block
÷N
PFD
CP
LF
VCO
8
8
÷2
8
VCO Post Divider
÷C3
Cascade Input
from Adjacent PLL
RCLKs
External Clock Outputs
TX Serial Clock
TX Load Enable
FBOUT
÷C17
Dedicated refclk
Delta Sigma
Modulator
÷M
Direct Compensation Mode
ZDB, External Feedback Modes
LVDS Compensation Mode
Source Synchronous, Normal Modes
Altera Corporation
GCLKs
÷C1
÷C2
clkswitch
clkbad0
clkbad1
activeclock
Casade Output
to Adjacent PLL
÷C0
PLL Output Multiplexer
Lock
Circuit
pfdena
Only C0, C2, C15, and C17
can drive the TX serial clock
and C1, C3, C14, and C16
can drive the TX load enable.
This FBOUT port is fed by
the M counter in the PLLs.
External Memory
Interface DLL
PMA Clocks
FBIN
DIFFIOCLK Network
GCLK/RCLK Network
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Fractional PLL Usage
You can configure the fractional PLL to function either in the integer or in the enhanced fractional mode.
One fractional PLL can use up to 18 output counters and all external clock outputs. Two adjacent fractional
PLLs share the 18 output counters.
Fractional PLLs can be used as follows:
• Reduce the number of required oscillators on the board
• Reduce the clock pins used in the FPGA by synthesizing multiple clock frequencies from a single reference
clock source
• Compensate clock network delay
• Zero delay buffering
• Transmit clocking for transceivers
PLL Cascading
Arria V devices support two types of PLL cascading.
PLL-to-PLL Cascading
This cascading mode synthesizes a more precise output frequency than a single PLL in integer mode.
Cascading two PLLs in integer mode expands the effective range of the pre-scale counter, N and the multiply
counter, M.
Arria V devices use two types of input clock sources.
• The adjpllin input clock source is used for inter-cascading between fracturable fractional PLLs.
• The cclk input clock source is used for intra-cascading within fracturable fractional PLLs.
Altera recommends using a low bandwidth setting for the source (upstream) PLL and a high bandwidth
setting for destination (downstream) PLL.
Counter-Output-to-Counter-Output Cascading
This cascading mode synthesizes a lower frequency output than a single post-scale counter, C. Cascading
two C counters expands the effective range of C counters.
PLL External Clock I/O Pins
Two adjacent fractional PLLs share four dual-purpose clock I/O pins, organized as one of the following
combinations:
• Four single-ended clock outputs
• Two single-ended outputs and one differential clock output
• Four single-ended clock outputs and two single-ended feedback inputs in the I/O driver feedback for
zero delay buffer (ZDB) mode support
• Two single-ended clock outputs and two single-ended feedback inputs for single-ended external feedback
(EFB) mode support
• One differential clock output and one differential feedback input for differential EFB support (only one
of the two adjacent fractional PLLs can support differential EFB at one time while the other fractional
PLL can be used for general-purpose clocking)
Note: The middle fractional PLLs on the left and right sides of Arria V GX B5 and B7 devices, and
Arria V GT D7 device do not support external clock outputs.
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PLL Control Signals
The following figure shows that any of the output counters (C[0..17]) or the M counter on the PLLs can
feed the dedicated external clock outputs. Therefore, one counter or frequency can drive all output pins
available from a given PLL.
Figure 4-22: Dual-Purpose Clock I/O Pins Associated with PLL for Arria V Devices
Fractional PLL0
VCO 0
Fractional PLL1
VCO 1
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
I/O / FPLL_<#>_CLKOUT0/ FPLL_<#>_CLKOUTp/
FPLL_<#>_FB0
EXTCLKOUT[0]
fbin0
EXTCLKOUT[3..0]
20
mux
C14
C15
C16
C17
M0
M1
You can feed these clock output pins using any one
of the C[17..0] or M counters. When not used as
external clock outputs, these clock output pins can
be used as
regular user I/Os.
EXTCLKOUT[1]
I/O / FPLL_<#>CLKOUT1/
FPLL_<#>_CLKOUTn
EXTCLKOUT[2]
I/O / FPLL_<#>_CLKOUT2 /
FPLL<#>_FBp / FPLL_<#>_FB1
4
fbin1
The FPLL_<#>_CLKOUT0, FPLL_<#>_CLKOUT1,
FPLL_<#>_CLKOUT2, and FPLL_<#>_CLKOUT3
pins are single-ended clock output pins.
The FPLL_<#>_CLKOUTp and
FPLL_<#>_CLKOUTn pins are differential output
pins while the FPLL_<#>_FBp and FPLL_<#>_FBn
pins are differential feedback input pins to support
differential EFB only in VCO 1.
EXTCLKOUT[3]
I/O / FPLL_<#>_CLKOUT3 /
FPLL_<#>_FBn
The FPLL_<#>_FB0 and
FPLL_<#>_FB1 pins are single-ended
feedback input pins.
Each pin of a single-ended output pair can be either in-phase or 180° out-of-phase. To implement the 180°
out-of-phase pin in a pin pair, the Quartus II software places a NOT gate in the design into the IOE.
The clock output pin pairs support the following I/O standards:
•
•
•
•
Same I/O standard for the pin pairs
LVDS
Differential high-speed transceiver logic (HSTL)
Differential SSTL
Arria V PLLs can drive out to any regular I/O pin through the GCLK or RCLK network. You can also use
the external clock output pins as user I/O pins if you do not require external PLL clocking.
Related Information
• I/O Features in Arria V Devices
Provides more information about I/O standards supported by the PLL clock input and output pins.
• Zero-Delay Buffer Mode on page 4-26
• External Feedback Mode on page 4-27
PLL Control Signals
You can use the areset signal to control PLL operation and resynchronization, and use the locked signal
to observe the status of the PLL.
areset
The areset signal is the reset or resynchronization input for each PLL. The device input pins or internal
logic can drive these input signals.
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locked
4-23
When areset is driven high, the PLL counters reset, clearing the PLL output and placing the PLL out-oflock. The VCO is then set back to its nominal setting. When areset is driven low again, the PLL
resynchronizes to its input as it re-locks.
You must assert the areset signal every time the PLL loses lock to guarantee the correct phase relationship
between the PLL input and output clocks. You can set up the PLL to automatically reset (self-reset) after a
loss-of-lock condition using the Quartus II MegaWizard Plug-In Manager.
You must include the areset signal if either of the following conditions is true:
• PLL reconfiguration or clock switchover is enabled in the design
• Phase relationships between the PLL input and output clocks must be maintained after a loss-of-lock
condition
Note: If the input clock to the PLL is not toggling or is unstable after power up, assert the areset signal
after the input clock is stable and within specifications.
locked
The locked signal output of the PLL indicates the following conditions:
• The PLL has locked onto the reference clock.
• The PLL clock outputs are operating at the desired phase and frequency set in the MegaWizard Plug-In
Manager.
The lock detection circuit provides a signal to the core logic. The signal indicates when the feedback clock
has locked onto the reference clock both in phase and frequency.
Clock Feedback Modes
This section describes the following clock feedback modes:
•
•
•
•
•
•
Source synchronous
LVDS compensation
Direct
Normal compensation
ZDB
EFB
Each mode allows clock multiplication and division, phase shifting, and programmable duty cycle.
The input and output delays are fully compensated by a PLL only when using the dedicated clock input pins
associated with a given PLL as the clock source.
The input and output delays may not be fully compensated in the Quartus II software for the following
conditions:
• When a GCLK or RCLK network drives the PLL
• When the PLL is driven by a dedicated clock pin that is not associated with the PLL
For example, when you configure a PLL in ZDB mode, the PLL input is driven by an associated dedicated
clock input pin. In this configuration, a fully compensated clock path results in zero delay between the clock
input and one of the clock outputs from the PLL. However, if the PLL input is fed by a non-dedicated input
(using the GCLK network), the output clock may not be perfectly aligned with the input clock.
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Source Synchronous Mode
Source Synchronous Mode
If the data and clock arrive at the same time on the input pins, the same phase relationship is maintained at
the clock and data ports of any IOE input register. Data and clock signals at the IOE experience similar buffer
delays as long as you use the same I/O standard.
Altera recommends source synchronous mode for source synchronous data transfers.
Figure 4-23: Example of Phase Relationship Between Clock and Data in Source Synchronous Mode
Data Pin
PLL Reference Clock
at the Input Pin
Data at the Register
Clock at the Register
The source synchronous mode compensates for the delay of the clock network used and any difference in
the delay between the following two paths:
• Data pin to the IOE register input
• Clock input pin to the PLL phase frequency detector (PFD) input
The Arria V PLL can compensate multiple pad-to-input-register paths, such as a data bus when it is set to
use source synchronous compensation mode.
LVDS Compensation Mode
The purpose of LVDS compensation mode is to maintain the same data and clock timing relationship seen
at the pins of the internal serializer/deserializer (SERDES) capture register, except that the clock is inverted
(180° phase shift). Thus, LVDS compensation mode ideally compensates for the delay of the LVDS clock
network, including the difference in delay between the following two paths:
• Data pin-to-SERDES capture register
• Clock input pin-to-SERDES capture register
The output counter must provide the 180° phase shift.
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Direct Mode
4-25
Figure 4-24: Example of Phase Relationship Between the Clock and Data in LVDS Compensation Mode
Data Pin
PLL Reference Clock
at the Input Pin
Data at the Register
Clock at the Register
Direct Mode
In direct mode, the PLL does not compensate for any clock networks. This mode provides better jitter
performance because the clock feedback into the PFD passes through less circuitry. Both the PLL internaland external-clock outputs are phase-shifted with respect to the PLL clock input.
Figure 4-25: Example of Phase Relationship Between the PLL Clocks in Direct Mode
Phase Aligned
PLL Reference
Clock at the
Input Pin
The PLL clock outputs
lag the PLL input clocks
depending on routing
delays.
PLL Clock at the
Register Clock Port
External PLL
Clock Outputs
Normal Compensation Mode
An internal clock in normal compensation mode is phase-aligned to the input clock pin. The external clock
output pin has a phase delay relative to the clock input pin if connected in this mode. The Quartus II
TimeQuest Timing Analyzer reports any phase difference between the two. In normal compensation mode,
the delay introduced by the GCLK or RCLK network is fully compensated.
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Zero-Delay Buffer Mode
Figure 4-26: Example of Phase Relationship Between the PLL Clocks in Normal Compensation Mode
Phase Aligned
PLL Reference
Clock at the Input Pin
PLL Clock at the
Register Clock Port
Dedicated PLL
Clock Outputs
The external clock output
can lead or lag the PLL
internal clock signals.
Zero-Delay Buffer Mode
In ZDB mode, the external clock output pin is phase-aligned with the clock input pin for zero delay through
the device. This mode is supported on all Arria V PLLs.
When using this mode, you must use the same I/O standard on the input clocks and clock outputs to guarantee
clock alignment at the input and output pins. You cannot use differential I/O standards on the PLL clock
input or output pins.
To ensure phase alignment between the clk pin and the external clock output (CLKOUT) pin in ZDB mode,
instantiate a bidirectional I/O pin in the design. The bidirectional I/O pin serves as the feedback path
connecting the fbout and fbin ports of the PLL. The bidirectional I/O pin must always be assigned a singleended I/O standard. The PLL uses this bidirectional I/O pin to mimic and compensate for the output delay
from the clock output port of the PLL to the external clock output pin.
Note: To avoid signal reflection when using ZDB mode, do not place board traces on the bidirectional I/O
pin.
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External Feedback Mode
4-27
Figure 4-27: ZDB Mode in Arria V PLLs
C0
C1
C2
C3
C4
C5
C6
inclk
÷N
PFD
CP/LF
VCO 0
EXTCLKOUT[0]
fbin0
Bidirectional
I/O Pin
EXTCLKOUT[1]
C7
C8
C9
C10
fbout0
Multiplexer
20
4
C11
C12
C13
inclk
÷N
PFD
CP/LF
VCO 1
EXTCLKOUT[2]
fbout1
fbin1
C14
Bidirectional
I/O Pin
C15
C16
C17
M0
EXTCLKOUT[3]
M1
Figure 4-28: Example of Phase Relationship Between the PLL Clocks in ZDB Mode
Phase Aligned
PLL Reference
Clock at the Input Pin
The internal PLL clock
output can lead or lag
the external PLL clock
outputs.
PLL Clock at the
Register Clock Port
Dedicated PLL
Clock Outputs
Related Information
PLL External Clock I/O Pins on page 4-21
Provides more information about PLL clock outputs.
External Feedback Mode
In EFB mode, the output of the M counter (fbout) feeds back to the PLL fbin input (using a trace on the
board) and becomes part of the feedback loop.
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External Feedback Mode
One of the dual-purpose external clock outputs becomes the fbin input pin in this mode. The external
feedback input pin, fbin is phase-aligned with the clock input pin. Aligning these clocks allows you to
remove clock delay and skew between devices.
When using EFB mode, you must use the same I/O standard on the input clock, feedback input, and clock
outputs.
Figure 4-29: EFB Mode in Arria V Devices
C0
C1
C2
C3
C4
C5
C6
inclk
÷N
PFD
CP/LF
VCO 0
Only one of the two VCOs can support
differential EFB mode at one time while
you can use the other VCO for general
purpose clocking.
EXTCLKOUT[0]
C7
C8
C9
Multiplexer
C10 20
4
C11
EXTCLKOUT[1]
CP/LF
VCO 1
EXTCLKOUT[2]
C14
External board connection for
one differential clock output
and one differential feedback
input for differential EFB
support.
External
Board Trace
C13
PFD
fbout[n]
fbout0
C12
inclk
÷N
fbout[p]
fbin0
fbin[p]
fbin1
C15
C16
C17
M0
M1
EXTCLKOUT[3]
fbin[n]
fbout1
External board connection for two
single-ended clock outputs and two
single-ended feedback inputs for
single-ended EFB support.
Figure 4-30: Example of Phase Relationship Between the PLL Clocks in EFB Mode
Phase Aligned
PLL Reference
Clock at the
Input Pin
The PLL clock outputs
can lead or lag the fbin
clock input.
PLL Clock at
the Register
Clock Port
Dedicated PLL
Clock Outputs
fbin Clock Input Pin
Related Information
PLL External Clock I/O Pins on page 4-21
Provides more information about PLL clock outputs.
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Clock Multiplication and Division
4-29
Clock Multiplication and Division
Each Arria V PLL provides clock synthesis for PLL output ports using the M/(N × C) scaling factors. The
input clock is divided by a pre-scale factor, N, and is then multiplied by the M feedback factor. The control
loop drives the VCO to match fin × (M/N).
The Quartus II software automatically chooses the appropriate scaling factors according to the input frequency,
multiplication, and division values entered into the ALTERA_PLL megafunction.
VCO Post Divider
A VCO post divider is inserted after the VCO. When you enable the VCO post divider, the VCO post divider
divides the VCO frequency by two. When the VCO post divider is bypassed, the VCO frequency goes to the
output port without being divided by two.
Post-Scale Counter, C
Each output port has a unique post-scale counter, C, that divides down the output from the VCO post divider.
For multiple PLL outputs with different frequencies, the VCO is set to the least common multiple of the
output frequencies that meets its frequency specifications. For example, if the output frequencies required
from one PLL are 33 and 66 MHz, the Quartus II software sets the VCO to 660 MHz (the least common
multiple of 33 and 66 MHz within the VCO range). Then the post-scale counters, C, scale down the VCO
frequency for each output port.
Pre-Scale Counter, N and Multiply Counter, M
Each PLL has one pre-scale counter, N, and one multiply counter, M, with a range of 1 to 512 for both M and
N. The N counter does not use duty-cycle control because the only purpose of this counter is to calculate
frequency division. The post-scale counters have a 50% duty cycle setting. The high- and low-count values
for each counter range from 1 to 256. The sum of the high- and low-count values chosen for a design selects
the divide value for a given counter.
Delta-Sigma Modulator
The delta-sigma modulator (DSM) is used together with the M multiply counter to enable the PLL to operate
in fractional mode. The DSM dynamically changes the M counter divide value on a cycle to cycle basis. The
different M counter values allow the "average" M counter value to be a non-integer.
Fractional Mode
In fractional mode, the M counter divide value equals to the sum of the "clock high" count, "clock low" count,
and the fractional value. The fractional value is equal to K/2^X, where K is an integer between 0 and (2^X – 1),
and X = 8, 16, 24, or 32.
Integer Mode
For PLL operating in integer mode, M is an integer value and DSM is disabled.
Related Information
Altera Phase-Locked Loop (ALTERA_PLL) Megafunction User Guide
Provides more information about PLL software support in the Quartus II software.
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Programmable Phase Shift
Programmable Phase Shift
The programmable phase shift feature allows the PLLs to generate output clocks with a fixed phase offset.
The VCO frequency of the PLL determines the precision of the phase shift. The minimum phase shift
increment is 1/8 of the VCO period. For example, if a PLL operates with a VCO frequency of 1000 MHz,
phase shift steps of 125 ps are possible.
The Quartus II software automatically adjusts the VCO frequency according to the user-specified phase shift
values entered into the megafunction.
Programmable Duty Cycle
The programmable duty cycle allows PLLs to generate clock outputs with a variable duty cycle. This feature
is supported on the PLL post-scale counters.
The duty-cycle setting is achieved by a low and high time-count setting for the post-scale counters. To
determine the duty cycle choices, the Quartus II software uses the frequency input and the required multiply
or divide rate.
The post-scale counter value determines the precision of the duty cycle. The precision is defined as 50%
divided by the post-scale counter value. For example, if the C0 counter is 10, steps of 5% are possible for
duty-cycle choices from 5% to 90%. If the PLL is in external feedback mode, set the duty cycle for the counter
driving the fbin pin to 50%.
Combining the programmable duty cycle with programmable phase shift allows the generation of precise
non-overlapping clocks.
Clock Switchover
The clock switchover feature allows the PLL to switch between two reference input clocks. Use this feature
for clock redundancy or for a dual-clock domain application where a system turns on the redundant clock
if the previous clock stops running. The design can perform clock switchover automatically when the clock
is no longer toggling or based on a user control signal, clkswitch.
The following clock switchover modes are supported in Arria V PLLs:
• Automatic switchover—The clock sense circuit monitors the current reference clock. If the current
reference clock stops toggling, the reference clock automatically switches to inclk0 or inclk1 clock.
• Manual clock switchover—Clock switchover is controlled using the clkswitch signal. When the clkswitch
signal goes from logic low to logic high, and stays high for at least three clock cycles, the reference clock
to the PLL is switched from inclk0 to inclk1, or vice-versa.
• Automatic switchover with manual override—This mode combines automatic switchover and manual
clock switchover. When the clkswitch signal goes high, it overrides the automatic clock switchover
function. As long as the clkswitch signal is high, further switchover action is blocked.
Automatic Switchover
Arria V PLLs support a fully configurable clock switchover capability.
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Automatic Switchover
4-31
Figure 4-31: Automatic Clock Switchover Circuit Block Diagram
This figure shows a block diagram of the automatic switchover circuit built into the PLL.
clkbad[0]
clkbad[1]
activeclock
Clock
Sense
Switchover
State Machine
clksw
Clock Switch
Control Logic
clkswitch
inclk0
N Counter
inclk1
Multiplexer
Out
PFD
refclk
fbclk
When the current reference clock is not present, the clock sense block automatically switches to the backup
clock for PLL reference. You can select a clock source as the backup clock by connecting it to the inclk1
port of the PLL in your design.
The clock switchover circuit sends out three status signals—clkbad[0], clkbad[1], and activeclock—from
the PLL to implement a custom switchover circuit in the logic array.
In automatic switchover mode, the clkbad[0] and clkbad[1] signals indicate the status of the two clock
inputs. When they are asserted, the clock sense block detects that the corresponding clock input has stopped
toggling. These two signals are not valid if the frequency difference between inclk0 and inclk1 is greater
than 20%.
The activeclock signal indicates which of the two clock inputs (inclk0 or inclk1) is being selected as the
reference clock to the PLL. When the frequency difference between the two clock inputs is more than 20%,
the activeclock signal is the only valid status signal.
Note: Glitches in the input clock may cause the frequency difference between the input clocks to be more
than 20%.
Use the switchover circuitry to automatically switch between inclk0 and inclk1 when the current reference
clock to the PLL stops toggling. You can switch back and forth between inclk0 and inclk1 any number of
times when one of the two clocks fails and the other clock is available.
For example, in applications that require a redundant clock with the same frequency as the reference clock,
the switchover state machine generates a signal (clksw) that controls the multiplexer select input. In this
case, inclk1 becomes the reference clock for the PLL.
When using automatic clock switchover mode, the following requirements must be satisfied:
• Both clock inputs must be running when the FPGA is configured.
• The period of the two clock inputs can differ by no more than 20%.
If the current clock input stops toggling while the other clock is also not toggling, switchover is not initiated
and the clkbad[0..1] signals are not valid. If both clock inputs are not the same frequency, but their period
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Automatic Switchover with Manual Override
difference is within 20%, the clock sense block detects when a clock stops toggling. However, the PLL may
lose lock after the switchover is completed and needs time to relock.
Note: Altera recommends resetting the PLL using the areset signal to maintain the phase relationships
between the PLL input and output clocks when using clock switchover.
Figure 4-32: Automatic Switchover After Loss of Clock Detection
This figure shows an example waveform of the switchover feature in automatic switchover mode. In this
example, the inclk0 signal is stuck low. After the inclk0 signal is stuck at low for approximately two clock
cycles, the clock sense circuitry drives the clkbad[0] signal high. Since the reference clock signal is not
toggling, the switchover state machine controls the multiplexer through the clkswitch signal to switch to
the backup clock, inclk1.
inclk0
inclk1
muxout
clkbad0
clkbad1
activeclock
Switchover is enabled on the falling
edge of inclk0 or inclk1, depending
on which clock is available. In this
figure, switchover is enabled on the
falling edge of inclk1.
Automatic Switchover with Manual Override
In automatic switchover with manual override mode, you can use the clkswitch signal for user- or systemcontrolled switch conditions. You can use this mode for same-frequency switchover, or to switch between
inputs of different frequencies.
For example, if inclk0 is 66 MHz and inclk1 is 200 MHz, you must control switchover using the clkswitch
signal. The automatic clock-sense circuitry cannot monitor clock input (inclk0 and inclk1) frequencies
with a frequency difference of more than 100% (2×).
This feature is useful when the clock sources originate from multiple cards on the backplane, requiring a
system-controlled switchover between the frequencies of operation.
You must choose the backup clock frequency and set the M, N, C, and K counters so that the VCO operates
within the recommended operating frequency range. The ALTERA_PLL MegaWizard Plug-in Manager
notifies you if a given combination of inclk0 and inclk1 frequencies cannot meet this requirement.
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Manual Clock Switchover
4-33
Figure 4-33: Clock Switchover Using the clkswitch (Manual) Control
This figure shows a clock switchover waveform controlled by the clkswitch signal. In this case, both clock
sources are functional and inclk0 is selected as the reference clock; the clkswitch signal goes high, which
starts the switchover sequence. On the falling edge of inclk0, the counter’s reference clock, muxout, is gated
off to prevent clock glitching. On the falling edge of inclk1, the reference clock multiplexer switches from
inclk0 to inclk1 as the PLL reference. The activeclock signal changes to indicate the clock which is
currently feeding the PLL.
inclk0
inclk1
muxout
clkswitch
activeclock
clkbad0
clkbad1
To initiate a manual clock switchover event,
both inclk0 and inclk1 must be running when
the clkswitch signal goes high.
In automatic override with manual switchover mode, the activeclock signal mirrors the clkswitch signal.
Since both clocks are still functional during the manual switch, neither clkbad signal goes high. Because the
switchover circuit is positive-edge sensitive, the falling edge of the clkswitch signal does not cause the
circuit to switch back from inclk1 to inclk0. When the clkswitch signal goes high again, the process
repeats.
The clkswitch signal and automatic switch work only if the clock being switched to is available. If the clock
is not available, the state machine waits until the clock is available.
Related Information
Altera Phase-Locked Loop (ALTERA_PLL) Megafunction User Guide
Provides more information about PLL software support in the Quartus II software.
Manual Clock Switchover
In manual clock switchover mode, the clkswitch signal controls whether inclk0 or inclk1 is selected as
the input clock to the PLL. By default, inclk0 is selected.
A clock switchover event is initiated when the clkswitch signal transitions from logic low to logic high,
and being held high for at least three inclk cycles.
You must bring the clkswitch signal back low again to perform another switchover event. If you do not
require another switchover event, you can leave the clkswitch signal in a logic high state after the initial
switch.
Pulsing the clkswitch signal high for at least three inclk cycles performs another switchover event.
If inclk0 and inclk1 are different frequencies and are always running, the clkswitchsignal minimum high
time must be greater than or equal to three of the slower frequency inclk0 and inclk1 cycles.
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Guidelines
Figure 4-34: Manual Clock Switchover Circuitry in Arria V PLLs
clkswitch
Clock Switch
Control Logic
inclk0
N Counter
inclk1
muxout
PFD
refclk
fbclk
You can delay the clock switchover action by specifying the switchover delay in the ALTERA_PLL
megafunction. When you specify the switchover delay, the clkswitch signal must be held high for at least
three inclk cycles plus the number of the delay cycles that has been specified to initiate a clock switchover.
Related Information
Altera Phase-Locked Loop (ALTERA_PLL) Megafunction User Guide
Provides more information about PLL software support in the Quartus II software.
Guidelines
When implementing clock switchover in Arria V PLLs, use the following guidelines:
• Automatic clock switchover requires that the inclk0 and inclk1 frequencies be within 20% of each
other. Failing to meet this requirement causes the clkbad[0] and clkbad[1] signals to not function
properly.
• When using manual clock switchover, the difference between inclk0 and inclk1 can be more than 100%
(2×). However, differences in frequency, phase, or both, of the two clock sources will likely cause the PLL
to lose lock. Resetting the PLL ensures that you maintain the correct phase relationships between the
input and output clocks.
• Both inclk0 and inclk1 must be running when the clkswitch signal goes high to initiate the manual
clock switchover event. Failing to meet this requirement causes the clock switchover to not function
properly.
• Applications that require a clock switchover feature and a small frequency drift must use a low-bandwidth
PLL. When referencing input clock changes, the low-bandwidth PLL reacts more slowly than a highbandwidth PLL. When switchover happens, a low-bandwidth PLL propagates the stopping of the clock
to the output more slowly than a high-bandwidth PLL. However, be aware that the low-bandwidth PLL
also increases lock time.
• After a switchover occurs, there may be a finite resynchronization period for the PLL to lock onto a new
clock. The time it takes for the PLL to relock depends on the PLL configuration.
• The phase relationship between the input clock to the PLL and the output clock from the PLL is important
in your design. Assert areset for at least 10 ns after performing a clock switchover. Wait for the locked
signal to go high and be stable before re-enabling the output clocks from the PLL.
• The VCO frequency gradually decreases when the current clock is lost and then increases as the VCO
locks on to the backup clock, as shown in the following figure.
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PLL Reconfiguration and Dynamic Phase Shift
4-35
Figure 4-35: VCO Switchover Operating Frequency
Primary Clock Stops Running
Switchover Occurs
VCO Tracks Secondary Clock
∆Fvco
PLL Reconfiguration and Dynamic Phase Shift
For more information about PLL reconfiguration and dynamic phase shifting, refer to AN661.
Related Information
AN661: Implementing Fractional PLL Reconfiguration with ALTERA_PLL and
ALTERA_PLL_RECONFIG Megafunctions
Document Revision History
Date
Version
January 2014
2014.01.10
Clock Networks and PLLs in Arria V Devices
Send Feedback
Changes
• Removed Preliminary tags for clock resources, clock input pin
connections to GCLK and RCLK networks, and PLL features tables.
• Updated clock resources table.
• Added availability for RCLK[46..51] and RCLK[52..57] pins in RCLK
networks diagram.
• Added notes to dedicated clock input pin connectivity to GCLK and
RCLK tables.
• Added label for PLL strip in PLL locations diagrams.
• Added descriptions for PLLs located in a strip.
• Added PLL locations diagram for Arria V SX B3 and B5 devices, and
Arria V ST D3 and D5 devices.
• Added information on PLL migration guidelines.
• Updated VCO post-scale counter, K, to VCO post divider.
• Added information on PLL cascading.
• Added information on programmable phase shift.
• Updated automatic clock switchover mode requirement.
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Document Revision History
Date
May 2013
Version
2013.05.06
Changes
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
November 2012
Altera Corporation
2012.11.19
Added link to the known document issues in the Knowledge Base.
Updated RCLK and PCLK clock sources per device quadrant.
Added link to Arria V GZ Device Family Pin Connection Guidelines.
Updated RCLK and PCLK clock sources in hierarchical clock networks
in each spine clock per quadrant diagram.
Added PCLK networks in clock network sources section.
Updated dedicated clock input pins in clock network sources section.
Updated information on clock power down.
Added information on C output counters for PLLs.
Added power down mode in PLL features table.
Added PLL physical counters information and diagram.
Marked PLL physical counters orientation in PLL locations diagrams.
Updated the fractional PLL architecture diagram to add dedicated
refclk input port and connections.
Removed information on pfdena PLL control signal.
Updated the scaling factors for PLL output ports.
Updated the fractional value for PLL in fractional mode.
Moved all links to the Related Information section of respective topics
for easy reference.
Reorganized content.
• Added note to indicate that the figures shown are the top view of the
silicon die.
• Updated clock resources for Arria V GZ devices.
• Added RCLK networks diagram for Arria V GZ devices.
• Restructured tables for clock input pin connectivity to the GCLK and
RCLK networks.
• Added table for clock input pin connectivity to the RCLK networks for
Arria V GZ devices.
• Updated PCLK control block information.
• Added PLL locations diagrams for Arria V GZ E1, E3, E5, and E7
devices.
• Removed information on PLL Compensation assignment in the
Quartus II software.
• Updated the fractional value for PLL in fractional mode.
• Reorganized content and updated template.
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Document Revision History
Date
Version
4-37
Changes
June 2012
2.0
• Restructured chapter.
• Updated Figure 4–4, Figure 4–6, Figure 4–7, Figure 4–11, Figure 4–12,
Figure 4–13, Figure 4–14, Figure 4–15, Figure 4–16, Figure 4–18, and
Figure 4–19.
• Updated Table 4–1, Table 4–2, Table 4–3, Table 4–4, and Table 4–5.
• Added “Clock Regions”, “Clock Network Sources”, “Clock Output
Connections”, “Clock Enable Signals”, “PLL Control Signals”, “Clock
Multiplication and Division”, “Programmable Duty Cycle”, “Clock
Switchover”, and “PLL Reconfiguration and Dynamic Phase Shift”.
November 2011
1.1
Restructured chapter.
May 2011
1.0
Initial release.
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I/O Features in Arria V Devices
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This chapter provides details about the features of the Arria V I/O elements (IOEs) and how the IOEs work
in compliance with current and emerging I/O standards and requirements.
The Arria V I/Os support the following features:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Single-ended, non-voltage-referenced, and voltage-referenced I/O standards
Low-voltage differential signaling (LVDS), RSDS, mini-LVDS, HSTL, HSUL, and SSTL I/O standards
Serializer/deserializer (SERDES)
Programmable output current strength
Programmable slew-rate
Programmable bus-hold
Programmable pull-up resistor
Programmable pre-emphasis
Programmable I/O delay
Programmable voltage output differential (VOD)
Open-drain output
On-chip series termination (RS OCT) with and without calibration
On-chip parallel termination (RT OCT)
On-chip differential termination (RD OCT)
Note: The information in this chapter is applicable to all Arria V variants, unless noted otherwise.
Related Information
Arria V Device Handbook: Known Issues
Lists the planned updates to the Arria V Device Handbook chapters.
I/O Resources Per Package for Arria V Devices
The following package plan tables for the different Arria V variants list the maximum I/O resources available
for each package.
© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words
and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other
words and logos identified as trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with
Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes
no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
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I/O Resources Per Package for Arria V Devices
Table 5-1: Package Plan for Arria V GX Devices
F672
Member Code
F896
F1152
F1517
GPIO
XCVR
GPIO
XCVR
GPIO
XCVR
GPIO
XCVR
A1
336
9
416
9
—
—
—
—
A3
336
9
416
9
—
—
—
—
A5
336
9
384
18
544
24
—
—
A7
336
9
384
18
544
24
—
—
B1
—
—
384
18
544
24
704
24
B3
—
—
384
18
544
24
704
24
B5
—
—
—
—
544
24
704
36
B7
—
—
—
—
544
24
704
36
Table 5-2: Package Plan for Arria V GT Devices
F672
Member
Code
F896
XCVR
F1152
XCVR
F1517
XCVR
XCVR
GPIO
6-Gbps
10Gbps
GPIO
6-Gbps
10Gbps
GPIO
6-Gbps
10Gbps
GPIO
6-Gbps
10-Gbps
C3
336
3 (9)
4
416
3 (9)
4
—
—
—
—
—
—
C7
—
—
—
384
6 (18)
8
544
6 (24)
12
—
—
—
D3
—
—
—
384
6 (18)
8
544
6 (24)
12
704
6 (24)
12
D7
—
—
—
—
—
—
544
6 (24)
12
704
6 (36)
20
Table 5-3: Package Plan for Arria V GZ Devices
H780
Member Code
F1152
F1517
GPIO
XCVR
GPIO
XCVR
GPIO
XCVR
E1
342
12
414
24
—
—
E3
342
12
414
24
—
—
E5
—
—
534
24
674
36
E7
—
—
534
24
674
36
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I/O Resources Per Package for Arria V Devices
Table 5-4: Package Plan for Arria V SX Devices
The HPS I/O counts are the number of I/Os in the HPS and does not correlate with the number of HPS-specific I/O
pins in the FPGA. Each HPS-specific pin in the FPGA may be mapped to several HPS I/Os.
F896
Member Code
F1152
F1517
FPGA
GPIO
HPS I/O
XCVR
FPGA
GPIO
HPS I/O
XCVR
FPGA
GPIO
HPS I/O
XCVR
B3
250
208
12
385
208
18
540
208
30
B5
250
208
12
385
208
18
540
208
30
Table 5-5: Package Plan for Arria V ST Devices
The HPS I/O counts are the number of I/Os in the HPS and does not correlate with the number of HPS-specific I/O
pins in the FPGA. Each HPS-specific pin in the FPGA may be mapped to several HPS I/Os.
F896
Member
Code
F1152
XCVR
FPGA
GPIO
HPS
I/O
6 Gbps
10
Gbps
D3
250
208
12
D5
250
208
12
F1517
XCVR
FPGA
GPIO
HPS
I/O
6 Gbps
10
Gbps
6
385
208
18
6
385
208
18
XCVR
FPGA
GPIO
HPS
I/O
6 Gbps
10 Gbps
8
540
208
30
16
8
540
208
30
16
For more information about each device variant, refer to the device overview.
Related Information
• True LVDS Buffers in Arria V Devices on page 6-4
Lists the number of LVDS channels in each device package.
• Arria V Device Overview
I/O Features in Arria V Devices
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I/O Vertical Migration for Arria V Devices
I/O Vertical Migration for Arria V Devices
Figure 5-1: Vertical Migration Capability Across Arria V Device Packages and Densities
The arrows indicate the vertical migration paths. Some packages have several migration paths. The devices
included in each vertical migration path are shaded. You can also migrate your design across device densities
in the same package option if the devices have the same dedicated pins, configuration pins, and power pins.
Variant
Member
Code
Package
F672
F780
F896
F1152
F1517
A1
A3
A5
Arria V GX
A7
B1
B3
B5
B7
C3
Arria V GT
C7
D3
D7
E1
Arria V GZ
E3
E5
E7
Arria V SX
Arria V ST
B3
B5
D3
D5
You can achieve the vertical migration shaded in red if you use only up to 320 GPIOs, up to nine 6 Gbps
transceiver channels, and up to four 10 Gbps transceiver (for Arria V GT devices). This migration path is
not shown in the Quartus II software Pin Migration View.
Note: To verify the pin migration compatibility, use the Pin Migration View window in the Quartus II
software Pin Planner.
Note: Except for Arria V GX A5 and A7, and Arria V GT C7 devices, all other Arria V GX and GT devices
require a specific power-up sequence. If you plan to migrate your design from Arria V GX A5 and
A7, and Arria V GT C7 devices to other Arria V devices, your design must adhere to the same required
power-up sequence.
Related Information
• Arria V GX, GT, SX, and ST Power-Up Sequence on page 11-7
• Verifying Pin Migration Compatibility on page 5-5
• I/O Management chapter, Quartus II Handbook
Provides more information about vertical I/O migrations.
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Verifying Pin Migration Compatibility
5-5
• What is the difference between pin-to-pin compatibility and drop-in compatibility?
Verifying Pin Migration Compatibility
You can use the Pin Migration View window in the Quartus II software Pin Planner to assist you in verifying
whether your pin assignments migrate to a different device successfully. You can vertically migrate to a
device with a different density while using the same device package, or migrate between packages with
different densities and ball counts.
1. Open Assignments > Pin Planner and create pin assignments.
2. If necessary, perform one of the following options to populate the Pin Planner with the node names in
the design:
• Analysis & Elaboration
• Analysis & Synthesis
• Fully compile the design
3. Then, on the menu, click View > Pin Migration View.
4. To select or change migration devices:
a. Click Device to open the Device dialog box.
b. Under Migration compatibility click Migration Devices.
5. To show more information about the pins:
a. Right-click anywhere in the Pin Migration View window and select Show Columns.
b. Then, click the pin feature you want to display.
6. If you want to view only the pins, in at least one migration device, that have a different feature than the
corresponding pin in the migration result, turn on Show migration differences.
7. Click Pin Finder to open the Pin Finder dialog box and find and highlight pins with specific functionality.
If you want to view only the pins found and highlighted by the most recent query in the Pin Finder dialog
box, turn on Show only highlighted pins.
8. To export the pin migration information to a Comma-Separated Value File (.csv), click Export.
Related Information
• I/O Vertical Migration for Arria V Devices on page 5-4
• I/O Management chapter, Quartus II Handbook
Provides more information about vertical I/O migrations.
I/O Standards Support in Arria V Devices
This section lists the I/O standards supported in the FPGA I/Os and HPS I/Os of Arria V devices, the typical
power supply values for each I/O standard, and the MultiVolt I/O interface feature.
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I/O Standards Support for FPGA I/O in Arria V Devices
Table 5-6: Supported I/O Standards in FPGA I/O for Arria V Devices
I/O Standard
(9)
Device Variant Support
Standard Support
3.3 V LVTTL/3.3 V LVCMOS
All
JESD8-B
3.0 V LVTTL/3.0 V LVCMOS
GX, GT, SX, and ST
JESD8-B
3.0 V PCI
GX, GT, SX, and ST
PCI Rev. 2.2
3.0 V PCI-X (9)
GX, GT, SX, and ST
PCI-X Rev. 1.0
2.5 V LVCMOS
All
JESD8-5
1.8 V LVCMOS
All
JESD8-7
1.5 V LVCMOS
All
JESD8-11
1.2 V LVCMOS
All
JESD8-12
SSTL-2 Class I
All
JESD8-9B
SSTL-2 Class II
All
JESD8-9B
SSTL-18 Class I
All
JESD8-15
SSTL-18 Class II
All
JESD8-15
SSTL-15 Class I
All
—
SSTL-15 Class II
All
—
1.8 V HSTL Class I
All
JESD8-6
1.8 V HSTL Class II
All
JESD8-6
1.5 V HSTL Class I
All
JESD8-6
1.5 V HSTL Class II
All
JESD8-6
1.2 V HSTL Class I
All
JESD8-16A
1.2 V HSTL Class II
All
JESD8-16A
Differential SSTL-2 Class I
All
JESD8-9B
Differential SSTL-2 Class II
All
JESD8-9B
Differential SSTL-18 Class I
All
JESD8-15
Differential SSTL-18 Class II
All
JESD8-15
Differential SSTL-15 Class I
All
—
Differential SSTL-15 Class II
All
—
Differential 1.8 V HSTL Class I
All
JESD8-6
Differential 1.8 V HSTL Class II
All
JESD8-6
Differential 1.5 V HSTL Class I
All
JESD8-6
PCI-X does not meet the PCI-X I–V curve requirement at the linear region.
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I/O Standards Support for HPS I/O in Arria V Devices
I/O Standard
Device Variant Support
Standard Support
Differential 1.5 V HSTL Class II
All
JESD8-6
Differential 1.2 V HSTL Class I
All
JESD8-16A
Differential 1.2 V HSTL Class II
All
JESD8-16A
LVDS
All
ANSI/TIA/EIA-644
RSDS
(10)
All
—
Mini-LVDS(11)
All
—
LVPECL
All
—
SSTL-15
All
JESD79-3D
SSTL-135
All
—
SSTL-125
All
—
SSTL-12
GZ only
—
HSUL-12
All
—
Differential SSTL-15
All
JESD79-3D
Differential SSTL-135
All
—
Differential SSTL-125
All
—
Differential SSTL-12
GZ only
—
Differential HSUL-12
All
—
5-7
I/O Standards Support for HPS I/O in Arria V Devices
Table 5-7: Supported I/O Standards in HPS I/O for Arria V SX and ST Devices
I/O Standard
(10)
(11)
Standard Support
HPS Column I/O
HPS Row I/O
3.3 V LVTTL/3.3 V LVCMOS
JESD8-B
Yes
—
3.0 V LVTTL/3.0 V LVCMOS
JESD8-B
Yes
—
2.5 V LVCMOS
JESD8-5
Yes
—
1.8 V LVCMOS
JESD8-7
Yes
Yes
1.5 V LVCMOS
JESD8-11
Yes
—
SSTL-18 Class I
JESD8-15
—
Yes
SSTL-18 Class II
JESD8-15
—
Yes
SSTL-15 Class I
—
—
Yes
SSTL-15 Class II
—
—
Yes
The Arria V devices support true RSDS output standard with data rates of up to 360 Mbps using true LVDS
output buffer types on all I/O banks.
The Arria V devices support true mini-LVDS output standard with data rates of up to 400 Mbps using true
LVDS output buffer types on all I/O banks.
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I/O Standard
Standard Support
HPS Column I/O
HPS Row I/O
1.5 V HSTL Class I
JESD8-6
Yes
—
1.5 V HSTL Class II
JESD8-6
Yes
—
SSTL-135
—
—
Yes
HSUL-12
—
—
Yes
I/O Standards Voltage Levels in Arria V Devices
Table 5-8: Arria V I/O Standards Voltage Levels
This table lists the typical power supplies for each supported I/O standards in Arria V devices.
I/O Standard
3.3 V LVTTL/3.3 V
LVCMOS
3.0 V LVTTL/3.0 V
LVCMOS
3.0 V PCI
Device
Variant
Support
GZ
GX, GT, SX,
and ST
(13)
VCCPD (V)
VREF (V)
(12)
VTT (V)
Output
(Pre-Driver
Voltage)
(Input Ref
Voltage)
(Board Termination
Voltage)
3.3
3.3
—
—
3.0/2.5
3.0
3.0
—
—
3.0/2.5
3.0
3.0
—
—
3.0
3.0
3.0
—
—
3.0
3.0
3.0
—
—
Input
(13)
GX, GT, SX,
3.3/3.0/2.5
and ST
3.0 V PCI-X
(12)
VCCIO (V)
2.5 V LVCMOS
All
3.0/2.5
2.5
2.5
—
—
1.8 V LVCMOS
All
1.8/1.5
1.8
2.5
—
—
1.5 V LVCMOS
All
1.8/1.5
1.5
2.5
—
—
1.2 V LVCMOS
All
1.2
1.2
2.5
—
—
SSTL-2 Class I
All
VCCPD
2.5
2.5
1.25
1.25
SSTL-2 Class II
All
VCCPD
2.5
2.5
1.25
1.25
SSTL-18 Class I
All
VCCPD
1.8
2.5
0.9
0.9
SSTL-18 Class II
All
VCCPD
1.8
2.5
0.9
0.9
SSTL-15 Class I
All
VCCPD
1.5
2.5
0.75
0.75
SSTL-15 Class II
All
VCCPD
1.5
2.5
0.75
0.75
1.8 V HSTL Class I
All
VCCPD
1.8
2.5
0.9
0.9
1.8 V HSTL Class II
All
VCCPD
1.8
2.5
0.9
0.9
1.5 V HSTL Class I
All
VCCPD
1.5
2.5
0.75
0.75
You cannot assign SSTL, HSTL, and HSUL outputs on VREF pins, even if there are no SSTL, HSTL, and HSUL
inputs in the bank.
Input buffers for the SSTL, HSTL, Differential SSTL, Differential HSTL, LVDS, RSDS, Mini-LVDS, LVPECL,
HSUL, and Differential HSUL are powered by VCCPD
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I/O Standards Voltage Levels in Arria V Devices
I/O Standard
Device
Variant
Support
1.5 V HSTL Class II
All
1.2 V HSTL Class I
VCCIO (V)
VCCPD (V)
VREF (V)
(12)
VTT (V)
Output
(Pre-Driver
Voltage)
(Input Ref
Voltage)
(Board Termination
Voltage)
VCCPD
1.5
2.5
0.75
0.75
All
VCCPD
1.2
2.5
0.6
0.6
1.2 V HSTL Class II
All
VCCPD
1.2
2.5
0.6
0.6
Differential SSTL-2
Class I
All
VCCPD
2.5
2.5
—
1.25
Differential SSTL-2
Class II
All
VCCPD
2.5
2.5
—
1.25
Differential SSTL-18
Class I
All
VCCPD
1.8
2.5
—
0.9
Differential SSTL-18
Class II
All
VCCPD
1.8
2.5
—
0.9
Differential SSTL-15
Class I
All
VCCPD
1.5
2.5
—
0.75
Differential SSTL-15
Class II
All
VCCPD
1.5
2.5
—
0.75
Differential 1.8 V
HSTL Class I
All
VCCPD
1.8
2.5
—
0.9
Differential 1.8 V
HSTL Class II
All
VCCPD
1.8
2.5
—
0.9
Differential 1.5 V
HSTL Class I
All
VCCPD
1.5
2.5
—
0.75
Differential 1.5 V
HSTL Class II
All
VCCPD
1.5
2.5
—
0.75
Differential 1.2 V
HSTL Class I
All
VCCPD
1.2
2.5
—
0.6
Differential 1.2 V
HSTL Class II
All
VCCPD
1.2
2.5
—
0.6
LVDS
All
VCCPD
2.5
2.5
—
—
RSDS
All
VCCPD
2.5
2.5
—
—
Mini-LVDS
All
VCCPD
2.5
2.5
—
—
LVPECL (Differential
clock input only)
All
VCCPD
—
2.5
—
—
Input
(13)
You cannot assign SSTL, HSTL, and HSUL outputs on VREF pins, even if there are no SSTL, HSTL, and HSUL
inputs in the bank.
Input buffers for the SSTL, HSTL, Differential SSTL, Differential HSTL, LVDS, RSDS, Mini-LVDS, LVPECL,
HSUL, and Differential HSUL are powered by VCCPD
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I/O Standard
Device
Variant
Support
VCCIO (V)
Input
(13)
VCCPD (V)
VREF (V)
(12)
Output
(Pre-Driver
Voltage)
(Input Ref
Voltage)
SSTL-15
All
VCCPD
1.5
2.5
0.75
SSTL-135
All
VCCPD
1.35
2.5
0.675
SSTL-125
All
VCCPD
1.25
2.5
0.625
SSTL-12
GZ only
VCCPD
1.2
2.5
0.6
HSUL-12
All
VCCPD
1.2
2.5
0.6
Differential SSTL-15
All
VCCPD
1.5
2.5
—
Differential SSTL-135
All
VCCPD
1.35
2.5
—
Differential SSTL-125
All
VCCPD
1.25
2.5
—
Differential SSTL-12
GZ only
VCCPD
1.2
2.5
—
Differential HSUL-12
All
VCCPD
1.2
2.5
—
VTT (V)
(Board Termination
Voltage)
Typically does not
require board
termination
Typically does not
require board
termination
Related Information
Guideline: Observe Device Absolute Maximum Rating for 3.3 V Interfacing on page 5-13
Provides more information about the 3.3 V LVTTL/LVCMOS I/O standard supported in Arria V GZ devices.
MultiVolt I/O Interface in Arria V Devices
The MultiVolt I/O interface feature allows Arria V devices in all packages to interface with systems of different
supply voltages.
Table 5-9: MultiVolt I/O Support in Arria V Devices
(12)
(13)
VCCIO (V)
Device Variant
Support
VCCPD (V)
Input Signal (V)
Output Signal (V)
1.2
All
2.5
1.2
1.2
1.25
All
2.5
1.25
1.25
1.35
All
2.5
1.35
1.35
1.5
All
2.5
1.5, 1.8
1.5
1.8
All
2.5
1.5, 1.8
1.8
2.5
All
2.5
2.5, 3.0, 3.3
2.5
3.0
2.5, 3.0, 3.3
3.0
3.0
GX, GT, SX, and
ST
GZ
3.0
2.5, 3.0, 3.3
3.0, 3.3
You cannot assign SSTL, HSTL, and HSUL outputs on VREF pins, even if there are no SSTL, HSTL, and HSUL
inputs in the bank.
Input buffers for the SSTL, HSTL, Differential SSTL, Differential HSTL, LVDS, RSDS, Mini-LVDS, LVPECL,
HSUL, and Differential HSUL are powered by VCCPD
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VCCIO (V)
Device Variant
Support
VCCPD (V)
Input Signal (V)
Output Signal (V)
3.3
GX, GT, SX, and
ST
3.3
2.5, 3.0, 3.3
3.3
The pin current may be slightly higher than the default value. Verify that the VOL maximum and VOH
minimum voltages of the driving device do not violate the applicable VIL maximum and VIH minimum
voltage specifications of the Arria V device.
The VCCPD power pins must be connected to a 2.5 V, 3.0 V, or 3.3 V power supply. Using these power pins
to supply the pre-driver power to the output buffers increases the performance of the output pins.
Note: If the input signal is 3.0 V or 3.3 V, Altera recommends that you use a clamping diode on the I/O
pins. Use the on-chip clamping diode for the Arria V GX, GT, SX, and ST devices, and an external
clamping diode for the Arria V GZ devices.
I/O Design Guidelines for Arria V Devices
There are several considerations that require your attention to ensure the success of your designs. Unless
noted otherwise, these design guidelines apply to all variants of this device family.
Mixing Voltage-Referenced and Non-Voltage-Referenced I/O Standards
Each I/O bank can simultaneously support multiple I/O standards. The following sections provide guidelines
for mixing non-voltage-referenced and voltage-referenced I/O standards in the devices.
Non-Voltage-Referenced I/O Standards
Each Arria V I/O bank has its own VCCIO pins and supports only one VCCIO of 1.2, 1.25, 1.35, 1.5, 1.8, 2.5,
3.0, or 3.3 V(14). An I/O bank can simultaneously support any number of input signals with different I/O
standard assignments if the I/O standards support the VCCIO level of the I/O bank.
For output signals, a single I/O bank supports non-voltage-referenced output signals that drive at the same
voltage as VCCIO. Because an I/O bank can only have one VCCIO value, it can only drive out the value for
non-voltage-referenced signals.
For example, an I/O bank with a 2.5 V VCCIO setting can support 2.5 V standard inputs and outputs, and
3.0 V LVCMOS inputs only.
Voltage-Referenced I/O Standards
To accommodate voltage-referenced I/O standards:
• Each Arria V GX, GT, SX, or ST I/O bank contains a dedicated VREF pin.
• Each Arria V GZ I/O bank supports multiple dedicated VREF pins feeding a common VREF bus.
• Each bank can have only a single VCCIO voltage level and a single voltage reference (VREF) level.
An I/O bank featuring single-ended or differential standards can support different voltage-referenced
standards if the VCCIO and VREF are the same levels.
(14)
Arria V GZ devices do not support 3.3 V
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For performance reasons, voltage-referenced input standards use their own VCCPD level as the power source.
This feature allows you to place voltage-referenced input signals in an I/O bank with a VCCIO of 2.5 V or
below. For example, you can place HSTL-15 input pins in an I/O bank with 2.5 V VCCIO. However, the
voltage-referenced input with RT OCT enabled requires the VCCIO of the I/O bank to match the voltage of
the input standard. RT OCT cannot be supported for the HSTL-15 I/O standard when VCCIO is 2.5 V.
Voltage-referenced bidirectional and output signals must be the same as the VCCIO voltage of the I/O bank.
For example, you can place only SSTL-2 output pins in an I/O bank with a 2.5 V VCCIO.
Mixing Voltage-Referenced and Non-Voltage Referenced I/O Standards
An I/O bank can support voltage-referenced and non-voltage-referenced pins by applying each of the rule
sets individually.
Examples:
• An I/O bank can support SSTL-18 inputs and outputs, and 1.8 V inputs and outputs with a 1.8 V VCCIO
and a 0.9 V VREF.
• An I/O bank can support 1.5 V standards, 1.8 V inputs (but not outputs), and 1.5 V HSTL I/O standards
with a 1.5 V VCCIO and 0.75 V VREF.
Guideline: Use the Same VCCPD for All I/O Banks in a Group
One VCCPD is shared in a group of I/O banks. If one I/O bank in a group uses 3.0 V VCCPD, other I/O banks
in the same group must also use 3.0 V VCCPD.
The I/O banks with the same bank number form a group. For example, I/O banks 8A, 8B, 8C, and 8D form
a group and share the same VCCPD. This sharing is applicable to all I/O banks, with the following exceptions:
• Arria V GX, GT, SX, and ST devices—No VCCPD sharing in bank 4A and 7A. Each of these I/O banks
has their own individual VCCPD.
• Arria V GZ devices—No VCCPD sharing across banks 3A, 3B, 3C, and 3D. Banks 3A and 3B form a group
with one VCCPD while bank 3C (if available) and 3D form another group with its own VCCPD.
For the Arria V GZ devices, if you are using an output or bidirectional pin with the 3.3 V LVTTL or 3.3 V
LVCMOS I/O standard, you must adhere to this restriction manually with location assignments.
For more information about the I/O banks available in each device package, refer to the related information.
Related Information
• Modular I/O Banks for Arria V GX Devices on page 5-16
• Modular I/O Banks for Arria V GT Devices on page 5-18
• Modular I/O Banks for Arria V GZ Devices on page 5-19
• Modular I/O Banks for Arria V SX Devices on page 5-20
• Modular I/O Banks for Arria V ST Devices on page 5-21
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5-13
Guideline: Ensure Compatible VCCIO and VCCPD Voltage in the Same Bank
When planning I/O bank usage for Arria V GX, GT, SX, and ST devices, you must ensure the VCCIO voltage
is compatible with the VCCPD voltage of the same bank. Some banks may share the same VCCPD power pin.
This limits the possible VCCIO voltages that can be used on banks that share VCCPD power pins.
Examples:
• VCCPD4BCD is connected to 2.5 V—VCCIO pins for banks 4B, 4C, and 4D can be connected 1.2 V, 1.25 V,
1.35 V, 1.5 V, 1.8 V, or 2.5 V.
• VCCPD4BCD is connected to 3.0 V—VCCIO pins for banks 4B, 4C, and 4D must be connected to 3.0 V.
Guideline: VREF Pin Restrictions
For the Arria V GX, GT, SX, and ST devices, consider the following VREF pins guidelines:
• You cannot assign shared VREF pins as LVDS or external memory interface pins.
• SSTL, HSTL, and HSUL I/O standards do not support shared VREF pins. For example, if a particular B1p
or B1n pin is a shared VREF pin, the corresponding B1p/B1n pin pair do not have LVDS transmitter
support.
• Shared VREF pins will have reduced performance when used as normal I/Os.
• You must perform signal integrity analysis using your board design when using a shared VREF pin to
determine the FMAX for your system.
For more information about pin capacitance of the VREF pins, refer to the device datasheet.
Related Information
Arria V Device Datasheet
Guideline: Observe Device Absolute Maximum Rating for 3.3 V Interfacing
To ensure device reliability and proper operation when you use the device for 3.3 V I/O interfacing, do not
violate the absolute maximum ratings of the device. For more information about absolute maximum rating
and maximum allowed overshoot during transitions, refer to the device datasheet.
Tip: Perform IBIS or SPICE simulations to make sure the overshoot and undershoot voltages are within
the specifications.
Transmitter Application
If you use the Arria V device as a transmitter, use slow slew-rate and series termination to limit the overshoot
and undershoot at the I/O pins. Transmission line effects that cause large voltage deviations at the receiver
are associated with an impedance mismatch between the driver and the transmission lines. By matching the
impedance of the driver to the characteristic impedance of the transmission line, you can significantly reduce
overshoot voltage. You can use a series termination resistor placed physically close to the driver to match
the total driver impedance to the transmission line impedance.
Receiver Application
If you use the Arria V device as a receiver, to limit the overshoot and undershoot voltage at the I/O pins:
• Arria V GX, GT, SX, or ST—use the on-chip clamping diode.
• Arria V GZ device—use an off-chip clamping diode.
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Guideline: Use PLL Integer Mode for LVDS Applications
The 3.3 V I/O standard is supported using the bank supply voltage (VCCIO) at 3.0 V and a VCCPD voltage of
3.0 V. In this method, the clamping diode can sufficiently clamp overshoot voltage to within the DC and
AC input voltage specifications. The clamped voltage is expressed as the sum of the VCCIO and the diode
forward voltage.
Related Information
Arria V Device Datasheet
Guideline: Use PLL Integer Mode for LVDS Applications
For LVDS applications, you must use the phase-locked loops (PLLs) in integer PLL mode.
Related Information
Guideline: Use PLLs in Integer PLL Mode for LVDS on page 6-7
I/O Banks Locations in Arria V Devices
The number of Arria V I/O banks in a particular device depends on the device density.
Figure 5-2: I/0 Banks for Arria V GX A1 and A3 Devices, and Arria V GT C3 Devices
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
Bank 5A
Bank 5B
Bank 5C
Transceiver Block
Bank 6C
Bank 6B
Bank 6A
Bank 8A Bank 8B Bank 8C Bank 7C Bank 7B Bank 7A
Bank 3A Bank 3B Bank 3C Bank 4C Bank 4B Bank 4A
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I/O Banks Locations in Arria V Devices
5-15
Figure 5-3: I/0 Banks for Arria V GX A5, A7, B1, B3, B5, and B7 Devices, Arria V GT C7, D3, and D7 Devices,
and Arria V GZ Devices
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
Transceiver Block
Transceiver Block
Bank 8A Bank 8B Bank 8C Bank 8D Bank 7D Bank 7C Bank 7B Bank 7A
Bank 3A Bank 3B Bank 3C Bank 3D Bank 4D Bank 4C Bank 4B Bank 4A
Figure 5-4: I/0 Banks for Arria V SX B3 and B5 Devices, and Arria V ST D3 and D5 Devices
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.
HPS Column I/O
Transceiver Block
Transceiver Block
HPS Core
HPS Row I/O
Bank 8A Bank 8B Bank 8C Bank 8D
Bank 3A Bank 3B Bank 3C Bank 3D Bank 4D Bank 4C Bank 4B Bank 4A
Related Information
• Modular I/O Banks for Arria V GX Devices on page 5-16
• Modular I/O Banks for Arria V GT Devices on page 5-18
I/O Features in Arria V Devices
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I/O Banks Groups in Arria V Devices
• Modular I/O Banks for Arria V GZ Devices on page 5-19
• Modular I/O Banks for Arria V SX Devices on page 5-20
• Modular I/O Banks for Arria V ST Devices on page 5-21
I/O Banks Groups in Arria V Devices
The I/O pins in Arria V devices are arranged in groups called modular I/O banks:
• Modular I/O banks have independent power supplies that allow each bank to support different I/O
standards.
• Each modular I/O bank can support multiple I/O standards that use the same VCCIO and VCCPD voltages.
Modular I/O Banks for Arria V GX Devices
Table 5-10: Modular I/O Banks for Arria V GX A1, A3, A5, and A7 Devices
Member Code
Package
Bank
Total
Altera Corporation
A1
A3
A5
A7
F672
F896
F672
F896
F672
F896
F1152
F672
F896
F1152
3A
24
32
24
32
24
32
48
24
32
48
3B
—
—
—
—
—
—
32
—
—
32
3C
—
—
—
—
—
—
32
—
—
32
3D
32
32
32
32
20
32
32
20
32
32
4A
16
16
16
16
28
32
32
28
32
32
4B
—
16
—
16
32
32
32
32
32
32
4C
32
32
32
32
32
32
32
32
32
32
4D
32
32
32
32
32
32
32
32
32
32
5A
32
48
32
48
—
—
—
—
—
—
6A
32
48
32
48
—
—
—
—
—
—
7A
16
16
16
16
28
32
32
28
32
32
7B
—
16
—
16
32
32
32
32
32
32
7C
32
32
32
32
32
32
32
32
32
32
7D
32
32
32
32
32
32
32
32
32
32
8A
24
32
24
32
24
32
48
24
32
48
8B
—
—
—
—
—
—
32
—
—
32
8C
—
—
—
—
—
—
32
—
—
32
8D
32
32
32
32
20
32
32
20
32
32
336
416
336
416
336
384
544
336
384
544
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Table 5-11: Modular I/O Banks for Arria V GX B1, B3, B5, and B7 Devices
Member Code
Package
Bank
B1
B3
B5
B7
F896
F1152
F1517
F896
F1152
F1517
F1152
F1517
F1152
F1517
3A
32
48
48
32
48
48
48
48
48
48
3B
—
32
32
—
32
32
32
32
32
32
3C
—
32
48
—
32
48
32
48
32
48
3D
32
32
48
32
32
48
32
48
32
48
4A
32
32
48
32
32
48
32
48
32
48
4B
32
32
48
32
32
48
32
48
32
48
4C
32
32
32
32
32
32
32
32
32
32
4D
32
32
48
32
32
48
32
48
32
48
7A
32
32
48
32
32
48
32
48
32
48
7B
32
32
48
32
32
48
32
48
32
48
7C
32
32
32
32
32
32
32
32
32
32
7D
32
32
48
32
32
48
32
48
32
48
8A
32
48
48
32
48
48
48
48
48
48
8B
—
32
32
—
32
32
32
32
32
32
8C
—
32
48
—
32
48
32
48
32
48
8D
32
32
48
32
32
48
32
48
32
48
384
544
704
384
544
704
544
704
544
704
Total
Related Information
• I/O Banks Locations in Arria V Devices on page 5-14
• Guideline: Use the Same VCCPD for All I/O Banks in a Group on page 5-12
Provides guidelines about VCCPD and I/O banks groups.
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Modular I/O Banks for Arria V GT Devices
Modular I/O Banks for Arria V GT Devices
Table 5-12: Modular I/O Banks for Arria V GT Devices
Member Code
Package
Bank
Total
C3
C7
D3
D7
F672
F896
F896
F1152
F896
F1152
F1517
F1152
F1517
3A
24
32
32
48
32
48
48
48
48
3B
—
—
—
32
—
32
32
32
32
3C
—
—
—
32
—
32
48
32
48
3D
32
32
32
32
32
32
48
32
48
4A
16
16
32
32
32
32
48
32
48
4B
—
16
32
32
32
32
48
32
48
4C
32
32
32
32
32
32
32
32
32
4D
32
32
32
32
32
32
48
32
48
5A
32
48
—
—
—
—
—
—
—
6A
32
48
—
—
—
—
—
—
—
7A
16
16
32
32
32
32
48
32
48
7B
—
16
32
32
32
32
48
32
48
7C
32
32
32
32
32
32
32
32
32
7D
32
32
32
32
32
32
48
32
48
8A
24
32
32
48
32
48
48
48
48
8B
—
—
—
32
—
32
32
32
32
8C
—
—
—
32
—
32
48
32
48
8D
32
32
32
32
32
32
48
32
48
336
416
384
544
384
544
704
544
704
Related Information
• I/O Banks Locations in Arria V Devices on page 5-14
• Guideline: Use the Same VCCPD for All I/O Banks in a Group on page 5-12
Provides guidelines about VCCPD and I/O banks groups.
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Modular I/O Banks for Arria V GZ Devices
5-19
Modular I/O Banks for Arria V GZ Devices
Table 5-13: Modular I/O Banks for Arria V GZ Devices
Member Code
Package
Bank
E1
E3
E5
E7
F780
F1152
F780
F1152
F1152
F1517
F1152
F1517
3A
36
36
36
36
36
36
36
36
3B
48
48
48
48
48
48
48
48
3C
—
—
—
—
48
48
48
48
3D
24
24
24
24
24
48
24
48
4A
24
24
24
24
24
24
24
24
4B
—
48
—
48
48
48
48
48
4C
—
—
—
—
48
48
48
48
4D
24
24
24
24
24
48
24
48
7A
24
24
24
24
24
24
24
24
7B
—
24
—
24
48
48
48
48
7C
48
48
48
48
48
48
48
48
7D
36
36
36
36
36
48
36
48
8A
24
24
24
24
24
36
24
36
8B
—
—
—
—
—
48
—
48
8C
48
48
48
48
48
48
48
48
8D
24
24
24
24
24
48
24
48
360
432
360
432
552
696
552
696
Total
Related Information
• I/O Banks Locations in Arria V Devices on page 5-14
• Guideline: Use the Same VCCPD for All I/O Banks in a Group on page 5-12
Provides guidelines about VCCPD and I/O banks groups.
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Modular I/O Banks for Arria V SX Devices
Modular I/O Banks for Arria V SX Devices
Table 5-14: Modular I/O Banks for Arria V SX Devices
Member Code
B3
Package
FPGA I/O Bank
HPS Row I/O
Bank
HPS Column I/O
Bank
FPGA I/O Bank
B5
F896
F1152
F1517
F896
F1152
F1517
3A
44
44
48
44
44
48
3B
28
28
32
28
28
32
3C
—
38
48
—
38
48
3D
13
13
48
13
13
48
4A
42
42
48
42
42
48
4B
—
38
48
—
38
48
4C
—
26
32
—
26
32
4D
—
32
48
—
32
48
6A
56
56
56
56
56
56
6B
44
44
44
44
44
44
7A
32
32
32
32
32
32
7B
22
22
22
22
22
22
7C
12
12
12
12
12
12
7D
20
20
20
20
20
20
7E
8
8
8
8
8
8
7G
—
—
12
—
—
12
8A
44
44
48
44
44
48
8B
28
28
32
28
28
32
8C
38
38
48
38
38
48
8D
13
14
48
13
14
48
444
579
734
444
579
734
Total
Related Information
• I/O Banks Locations in Arria V Devices on page 5-14
• Guideline: Use the Same VCCPD for All I/O Banks in a Group on page 5-12
Provides guidelines about VCCPD and I/O banks groups.
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I/O Features in Arria V Devices
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Modular I/O Banks for Arria V ST Devices
Modular I/O Banks for Arria V ST Devices
Table 5-15: Modular I/O Banks for Arria V ST Devices
Member Code
D3
Package
FPGA I/O Bank
HPS Row I/O
Bank
HPS Column I/O
Bank
FPGA I/O Bank
D5
F896
F1152
F1517
F896
F1152
F1517
3A
44
44
48
44
44
48
3B
28
28
32
28
28
32
3C
—
38
48
—
38
48
3D
13
13
48
13
13
48
4A
42
42
48
42
42
48
4B
—
38
48
—
38
48
4C
—
26
32
—
26
32
4D
—
32
48
—
32
48
6A
56
56
56
56
56
56
6B
44
44
44
44
44
44
7A
32
32
32
32
32
32
7B
22
22
22
22
22
22
7C
12
12
12
12
12
12
7D
20
20
20
20
20
20
7E
8
8
8
8
8
8
7G
—
—
12
—
—
12
8A
44
44
48
44
44
48
8B
28
28
32
28
28
32
8C
38
38
48
38
38
48
8D
13
14
48
13
14
48
444
579
734
444
579
734
Total
Related Information
• I/O Banks Locations in Arria V Devices on page 5-14
• Guideline: Use the Same VCCPD for All I/O Banks in a Group on page 5-12
Provides guidelines about VCCPD and I/O banks groups.
I/O Element Structure in Arria V Devices
The I/O elements (IOEs) in Arria V devices contain a bidirectional I/O buffer and I/O registers to support
a complete embedded bidirectional single data rate (SDR) or double data rate (DDR) transfer.
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I/O Buffer and Registers in Arria V Devices
The IOEs are located in I/O blocks around the periphery of the Arria V device.
The Arria V SX and ST devices also have I/O elements for the HPS.
I/O Buffer and Registers in Arria V Devices
I/O registers are composed of the input path for handling data from the pin to the core, the output path for
handling data from the core to the pin, and the output enable (OE) path for handling the OE signal to the
output buffer. These registers allow faster source-synchronous register-to-register transfers and resynchronization.
Table 5-16: Input and Output Paths in Arria V Devices
This table summarizes the input and output path in the Arria V devices.
Input Path
Output Path
Consists of:
Consists of:
• DDR input registers
• Alignment and synchronization registers
• Half data rate blocks
• Output or OE registers
• Alignment registers
• Half data rate blocks
You can bypass each block in the input path. The
You can bypass each block of the output and OE paths.
input path uses the deskew delay to adjust the input
register clock delay across process, voltage, and
temperature (PVT) variations.
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Programmable IOE Features in Arria V Devices
5-23
Figure 5-5: IOE Structure for Arria V Devices
This figure shows the Arria V FPGA IOE structure. In the figure, one dynamic on-chip termination (OCT)
control is available for each DQ/DQS group.
From Core
DQS Logic Block
OE Register
OE
from
Core
2
Half Data
Rate Block
D
D5_OCT
PRN
Q
Dynamic OCT Control
OE Register
D
PRN
Q
D5 Delay
VCCIO
VCCIO
Programmable
Current
Strength and
Slew Rate
Control
Output Register
Write
Data
from
Core
4
Half Data
Rate Block
D
PRN
Q
Optional
PCI Clamp
Programmable
Pull-Up Resistor
From OCT
Calibration
Block
Output
Buffer
On-Chip
Termination
D5 Delay
Output Register
Open Drain
PRN
D
Q
Input Buffer
D3_0
Delay
clkout
To
Core
Bus-Hold
Circuit
D1
Delay
D3_1
Delay
To
Core
Same avalaible settings in
the Quartus II software
Input Register
PRN
D
Read
Data
to
Core
4
Q
Read
FIFO
Input Register
Input Register
PRN
D
DQS
CQn
PRN
Q
D
Q
D4 Delay
clkin
Programmable IOE Features in Arria V Devices
Table 5-17: Summary of Supported Arria V Programmable IOE Features and Settings
Feature
Setting (Default
setting in bold)
Condition
Slew Rate Control
0 (Slow), 1 (Fast)
Disabled if you use
the RS OCT feature.
Yes
I/O Delay
Refer to the device
datasheet
—
—
Open-Drain Output
On, Off
—
Yes
Bus-Hold
On, Off
Disabled if you use
the weak pull-up
resistor feature.
Yes
Weak Pull-up Resistor
On, Off
Disabled if you use
the bus-hold feature.
Yes
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Supported in HPS I/O
(SoC Devices Only)
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Programmable Current Strength
Feature
Setting (Default
setting in bold)
Condition
0 (disabled) and 1
(enabled)
—
—
Arria V GX, GT,
SX, and ST—0
(low), 1 (medium)
, 2 (high)
•
Arria V GZ—0
(low), 1 (medium
low), 2 (medium
high), 3 (high)
—
—
On, Off
—
Yes
Pre-Emphasis
Differential Output Voltage
•
On-Chip Clamp Diode
Supported in HPS I/O
(SoC Devices Only)
(GX, GT, SX, and ST only)
Note: The on-chip clamp diode is available on all general purpose I/O (GPIO) pins in the Arria V GX, GT,
SX, and ST device variants.
Related Information
• Arria V Device Datasheet
• Programmable Current Strength on page 5-24
• Programmable Output Slew-Rate Control on page 5-25
• Programmable IOE Delay on page 5-26
• Programmable Output Buffer Delay on page 5-26
• Programmable Pre-Emphasis on page 5-26
• Programmable Differential Output Voltage on page 5-27
Programmable Current Strength
You can use the programmable current strength to mitigate the effects of high signal attenuation that is
caused by a long transmission line or a legacy backplane.
Table 5-18: Programmable Current Strength Settings for Arria V Devices
The output buffer for each Arria V device I/O pin has a programmable current strength control for the I/O standards
listed in this table.
IOH / IOL Current Strength Setting (mA)
(Default setting in bold)
I/O Standard
3.3-V LVTTL
Altera Corporation
Arria V GX, GT, SX, and ST
Arria V GZ
8, 4
16, 12, 8, 4
Supported in HPS
(SoC Devices Only)
Yes
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IOH / IOL Current Strength Setting (mA)
(Default setting in bold)
I/O Standard
Supported in HPS
(SoC Devices Only)
Arria V GX, GT, SX, and ST
Arria V GZ
2
16, 12, 8, 4
Yes
3.0-V LVTTL
16, 12, 8, 4
—
Yes
3.0-V LVCMOS
16, 12, 8, 4
—
Yes
2.5-V LVCMOS
16, 12, 8, 4
16, 12, 8, 4
Yes
1.8-V LVCMOS
12, 10, 8, 6, 4, 2
12, 10, 8, 6, 4, 2
Yes
1.5-V LVCMOS
12, 10, 8, 6, 4, 2
12, 10, 8, 6, 4, 2
Yes
1.2-V LVCMOS
8, 6, 4, 2
8, 6, 4, 2
—
SSTL-2 Class I
12, 10, 8
12, 10, 8
—
SSTL-2 Class II
16
16
—
SSTL-18 Class I
12, 10, 8, 6, 4
12, 10, 8, 6, 4
Yes
SSTL-18 Class II
16
16, 8
Yes
SSTL-15 Class I
12, 10, 8, 6, 4
12, 10, 8, 6, 4
Yes
SSTL-15 Class II
16
16, 8
Yes
1.8-V HSTL Class I
12, 10, 8, 6, 4
12, 10, 8, 6, 4
—
1.8-V HSTL Class II
16
16
—
1.5-V HSTL Class I
12, 10, 8, 6, 4
12, 10, 8, 6, 4
Yes
1.5-V HSTL Class II
16
16
Yes
1.2-V HSTL Class I
12, 10, 8, 6, 4
12, 10, 8, 6, 4
—
1.2-V HSTL Class II
16
16
—
3.3-V LVCMOS
5-25
For the Arria V GZ devices, the 3.3 V LVTTL and 3.3 V LVCMOS I/O standards are supported using VCCIO
and VCCPD at 3.0 V.
Note: Altera recommends that you perform IBIS or SPICE simulations to determine the best current
strength setting for your specific application.
Related Information
Programmable IOE Features in Arria V Devices on page 5-23
Programmable Output Slew-Rate Control
The programmable output slew-rate control in the output buffer of each regular- and dual-function I/O pin
allows you to configure the following:
• Fast slew-rate—provides high-speed transitions for high-performance systems.
• Slow slew-rate—reduces system noise and crosstalk but adds a nominal delay to the rising and falling
edges.
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Programmable IOE Delay
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You can specify the slew-rate on a pin-by-pin basis because each I/O pin contains a slew-rate control.
Note: Altera recommends that you perform IBIS or SPICE simulations to determine the best slew rate
setting for your specific application.
Related Information
Programmable IOE Features in Arria V Devices on page 5-23
Programmable IOE Delay
You can activate the programmable IOE delays to ensure zero hold times, minimize setup times, or increase
clock-to-output times. This feature helps read and write timing margins because it minimizes the
uncertainties between signals in the bus.
Each pin can have a different input delay from pin-to-input register or a delay from output register-to-output
pin values to ensure that the signals within a bus have the same delay going into or out of the device.
For more information about the programmable IOE delay specifications, refer to the device datasheet.
Related Information
• Arria V Device Datasheet
• Programmable IOE Features in Arria V Devices on page 5-23
Programmable Output Buffer Delay
The delay chains are built inside the single-ended output buffer. There are four levels of output buffer delay
settings. By default, there is no delay.
The delay chains can independently control the rising and falling edge delays of the output buffer, allowing
you to:
•
•
•
•
Adjust the output-buffer duty cycle
Compensate channel-to-channel skew
Reduce simultaneous switching output (SSO) noise by deliberately introducing channel-to-channel skew
Improve high-speed memory-interface timing margins
For more information about the programmable output buffer delay specifications, refer to the device datasheet.
Related Information
• Arria V Device Datasheet
• Programmable IOE Features in Arria V Devices on page 5-23
Programmable Pre-Emphasis
The VOD setting and the output impedance of the driver set the output current limit of a high-speed
transmission signal. At a high frequency, the slew rate may not be fast enough to reach the full VOD level
before the next edge, producing pattern-dependent jitter. With pre-emphasis, the output current is boosted
momentarily during switching to increase the output slew rate.
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Programmable Differential Output Voltage
5-27
Pre-emphasis increases the amplitude of the high-frequency component of the output signal, and thus helps
to compensate for the frequency-dependent attenuation along the transmission line. The overshoot introduced
by the extra current happens only during a change of state switching to increase the output slew rate and
does not ring, unlike the overshoot caused by signal reflection. The amount of pre-emphasis required depends
on the attenuation of the high-frequency component along the transmission line.
Figure 5-6: Programmable Pre-Emphasis
This figure shows the LVDS output with pre-emphasis.
Voltage boost
from pre-emphasis
OUT
VP
VOD
OUT
VP
Differential output
voltage (peak–peak)
Table 5-19: Quartus II Software Assignment Editor—Programmable Pre-Emphasis
This table lists the assignment name for programmable pre-emphasis and its possible values in the Quartus II software
Assignment Editor.
Field
Assignment (Default setting in bold)
To
tx_out
Assignment name
Programmable Pre-emphasis
Allowed values
0 (disabled) and 1 (enabled)
Related Information
Programmable IOE Features in Arria V Devices on page 5-23
Programmable Differential Output Voltage
The programmable VOD settings allow you to adjust the output eye opening to optimize the trace length
and power consumption. A higher VOD swing improves voltage margins at the receiver end, and a smaller
VOD swing reduces power consumption. You can statically adjust the VOD of the differential signal by
changing the VOD settings in the Quartus II software Assignment Editor.
I/O Features in Arria V Devices
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I/O Pins Features for Arria V Devices
Figure 5-7: Differential VOD
This figure shows the VOD of the differential LVDS output.
Single-Ended Waveform
Positive Channel (p)
VOD
Negative Channel (n)
VCM
Ground
Differential Waveform
VOD (diff peak - peak) = 2 x VOD (single-ended)
VOD
p-n=0V
VOD
Table 5-20: Quartus II Software Assignment Editor—Programmable VOD
This table lists the assignment name for programmable VOD and its possible values in the Quartus II software
Assignment Editor.
Field
Assignment (Default setting in bold)
To
tx_out
Assignment name
Programmable Differential Output Voltage (VOD)
Allowed values
• Arria V GX, GT, SX, and ST—0 (low), 1 (medium)
, 2 (high)
• Arria V GZ—0 (low), 1 (medium low), 2 (medium
high), 3 (high)
Related Information
Programmable IOE Features in Arria V Devices on page 5-23
I/O Pins Features for Arria V Devices
Open-Drain Output on page 5-28
Bus-Hold Circuitry on page 5-29
Pull-up Resistor on page 5-29
Open-Drain Output
The optional open-drain output for each I/O pin is equivalent to an open collector output. If it is configured
as an open drain, the logic value of the output is either high-Z or logic low.
Use an external resistor to pull the signal to a logic high.
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Bus-Hold Circuitry
5-29
Bus-Hold Circuitry
Each I/O pin provides an optional bus-hold feature that is active only after configuration. When the device
enters user mode, the bus-hold circuit captures the value that is present on the pin by the end of the
configuration.
The bus-hold circuitry uses a resistor with a nominal resistance (RBH), approximately 7 kΩ, to weakly pull
the signal level to the last-driven state of the pin. The bus-hold circuitry holds this pin state until the next
input signal is present. Because of this, you do not require an external pull-up or pull-down resistor to hold
a signal level when the bus is tri-stated.
For each I/O pin, you can individually specify that the bus-hold circuitry pulls non-driven pins away from
the input threshold voltage—where noise can cause unintended high-frequency switching. To prevent overdriving signals, the bus-hold circuitry drives the voltage level of the I/O pin lower than the VCCIO level.
If you enable the bus-hold feature, you cannot use the programmable pull-up option. To configure the I/O
pin for differential signals, disable the bus-hold feature.
Pull-up Resistor
Each I/O pin provides an optional programmable pull-up resistor during user mode. The pull-up resistor,
typically 25 kΩ, weakly holds the I/O to the VCCIO level.
The Arria V device supports programmable weak pull-up resistors only on user I/O pins but not on dedicated
configuration pins, dedicated clock pins, or JTAG pins .
If you enable this option, you cannot use the bus-hold feature.
On-Chip I/O Termination in Arria V Devices
Dynamic RS and RT OCT provides I/O impedance matching and termination capabilities. OCT maintains
signal quality, saves board space, and reduces external component costs.
The Arria V devices support OCT in all FPGA I/O banks. For the HPS I/Os, the column I/Os do not support
OCT.
Table 5-21: OCT Schemes Supported in Arria V Devices
Direction
Output
Input
Bidirectional
I/O Features in Arria V Devices
Send Feedback
OCT Schemes
Supported in HPS Row I/Os
RS OCT with calibration
Yes
RS OCT without calibration
Yes
RT OCT with calibration
Yes
RD OCT (LVDS I/O
standard only)
—
Dynamic RS OCT and RT
OCT
Yes
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RS OCT without Calibration in Arria V Devices
RS OCT without Calibration in Arria V Devices
The Arria V devices support RS OCT for single-ended and voltage-referenced I/O standards. RS OCT without
calibration is supported on output only.
Table 5-22: Selectable I/O Standards for RS OCT Without Calibration
This table lists the output termination settings for uncalibrated OCT on different I/O standards.
I/O Standard
Device Variant Support
Uncalibrated OCT (Output)
RS (Ω)
3.3 V LVTTL/3.3 V LVCMOS
GZ only
25/50
3.0 V LVTTL/3.0 V LVCMOS
GX, GT, SX, and ST
25/50
2.5 V LVCMOS
All
25/50
1.8 V LVCMOS
All
25/50
1.5 V LVCMOS
All
25/50
1.2 V LVCMOS
All
25/50
SSTL-2 Class I
All
50
SSTL-2 Class II
All
25
SSTL-18 Class I
All
50
SSTL-18 Class II
All
25
SSTL-15 Class I
All
50
SSTL-15 Class II
All
25
1.8 V HSTL Class I
All
50
1.8 V HSTL Class II
All
25
1.5 V HSTL Class I
All
50
1.5 V HSTL Class II
All
25
1.2 V HSTL Class I
All
50
1.2 V HSTL Class II
All
25
Differential SSTL-2 Class I
All
50
Differential SSTL-2 Class II
All
25
Differential SSTL-18 Class I
All
50
Differential SSTL-18 Class II
All
25
Differential SSTL-15 Class I
All
50
Differential SSTL-15 Class II
All
25
Differential 1.8 V HSTL Class I
All
50
Differential 1.8 V HSTL Class II
All
25
Differential 1.5 V HSTL Class I
All
50
Differential 1.5 V HSTL Class II
All
25
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I/O Standard
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Uncalibrated OCT (Output)
Device Variant Support
RS (Ω)
Differential 1.2 V HSTL Class I
All
50
Differential 1.2 V HSTL Class II
All
25
SSTL-15
GZ only
25, 34, 40, 50
SSTL-135
GZ only
34, 40
SSTL-125
GZ only
34, 40
SSTL-12
GZ only
40, 60, 240
HSUL-12
GZ only
34.3, 40, 48, 60, 80
Driver-impedance matching provides the I/O driver with controlled output impedance that closely matches
the impedance of the transmission line. As a result, you can significantly reduce signal reflections on PCB
traces.
If you select matching impedance, current strength is no longer selectable.
Figure 5-8: RS OCT Without Calibration
This figure shows the RS as the intrinsic impedance of the output transistors.
Receiving
Device
Driver
Series Termination
VCCIO
RS
Z0 = 50 Ω
RS
GND
RS OCT with Calibration in Arria V Devices
The Arria V devices support RS OCT with calibration in all banks.
Table 5-23: Selectable I/O Standards for RS OCT With Calibration
This table lists the output termination settings for calibrated OCT on different I/O standards.
I/O Standard
Device Variant
Support
Calibrated OCT (Output)
RS (Ω)
RZQ (Ω)
3.3 V LVTTL/3.3 V LVCMOS
GZ only
25/50
100
3.0 V LVTTL/3.0 V LVCMOS
GX, GT, SX, and ST
25/50
100
2.5 V LVCMOS
All
25/50
100
1.8 V LVCMOS
All
25/50
100
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I/O Standard
Device Variant
Support
Calibrated OCT (Output)
RS (Ω)
RZQ (Ω)
1.5 V LVCMOS
All
25/50
100
1.2 V LVCMOS
All
25/50
100
SSTL-2 Class I
All
50
100
SSTL-2 Class II
All
25
100
SSTL-18 Class I
All
50
100
SSTL-18 Class II
All
25
100
SSTL-15 Class I
All
50
100
SSTL-15 Class II
All
25
100
1.8 V HSTL Class I
All
50
100
1.8 V HSTL Class II
All
25
100
1.5 V HSTL Class I
All
50
100
1.5 V HSTL Class II
All
25
100
1.2 V HSTL Class I
All
50
100
1.2 V HSTL Class II
All
25
100
Differential SSTL-2 Class I
All
50
100
Differential SSTL-2 Class II
All
25
100
Differential SSTL-18 Class I
All
50
100
Differential SSTL-18 Class II
All
25
100
Differential SSTL-15 Class I
All
50
100
Differential SSTL-15 Class II
All
25
100
Differential 1.8 V HSTL Class I
All
50
100
Differential 1.8 V HSTL Class II
All
25
100
Differential 1.5 V HSTL Class I
All
50
100
Differential 1.5 V HSTL Class II
All
25
100
Differential 1.2 V HSTL Class I
All
50
100
Differential 1.2 V HSTL Class II
All
25
100
All
25, 50(15)
100
All
34, 40(15)
240
All
34, 40
(15)
240
34, 40
(15)
240
SSTL-15
SSTL-135
SSTL-125
SSTL-12
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RS OCT with Calibration in Arria V Devices
All
GZ only
40, 60, 240
(15)
240
Final values are pending silicon characterization.
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RT OCT with Calibration in Arria V Devices
Calibrated OCT (Output)
Device Variant
Support
I/O Standard
HSUL-12
All
RS (Ω)
RZQ (Ω)
34, 40, 48, 60, 80(15)
240
25, 50
(15)
100
All
34, 40
(15)
240
Differential SSTL-135
All
34, 40(15)
240
Differential SSTL-125
All
34, 40(15)
240
Differential SSTL-12
GZ only
40, 60, 240(15)
240
Differential HSUL-12
All
34, 40, 48, 60, 80(15)
240
All
Differential SSTL-15
5-33
The RS OCT calibration circuit compares the total impedance of the I/O buffer to the external reference
resistor connected to the RZQ pin and dynamically enables or disables the transistors until they match.
Calibration occurs at the end of device configuration. When the calibration circuit finds the correct impedance,
the circuit powers down and stops changing the characteristics of the drivers.
Figure 5-9: RS OCT with Calibration
This figure shows the RS as the intrinsic impedance of the output transistors.
Driver
Series Termination
Receiving
Device
VCCIO
RS
Z0 = 50 Ω
RS
GND
RT OCT with Calibration in Arria V Devices
The Arria V devices support RT OCT with calibration in all banks. RT OCT with calibration is available only
for configuration of input and bidirectional pins. Output pin configurations do not support RT OCT with
calibration. If you use RT OCT, the VCCIO of the bank must match the I/O standard of the pin where you
enable the RT OCT.
Table 5-24: Selectable I/O Standards for RT OCT With Calibration
This table lists the input termination settings for calibrated OCT on different I/O standards.
I/O Standard
Device Variant Support
Calibrated OCT (Input)
RT (Ω)
RZQ (Ω)
SSTL-2 Class I
All
50
100
SSTL-2 Class II
All
50
100
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RT OCT with Calibration in Arria V Devices
Device Variant Support
Calibrated OCT (Input)
RT (Ω)
RZQ (Ω)
SSTL-18 Class I
All
50
100
SSTL-18 Class II
All
50
100
SSTL-15 Class I
All
50
100
SSTL-15 Class II
All
50
100
1.8 V HSTL Class I
All
50
100
1.8 V HSTL Class II
All
50
100
1.5 V HSTL Class I
All
50
100
1.5 V HSTL Class II
All
50
100
1.2 V HSTL Class I
All
50
100
1.2 V HSTL Class II
All
50
100
Differential SSTL-2 Class I
All
50
100
Differential SSTL-2 Class II
All
50
100
Differential SSTL-18 Class I
All
50
100
Differential SSTL-18 Class II
All
50
100
Differential SSTL-15 Class I
All
50
100
Differential SSTL-15 Class II
All
50
100
Differential 1.8 V HSTL Class
I
All
50
100
Differential 1.8 V HSTL Class
II
All
50
100
Differential 1.5 V HSTL Class
I
All
50
100
Differential 1.5 V HSTL Class
II
All
50
100
Differential 1.2 V HSTL Class
I
All
50
100
Differential 1.2 V HSTL Class
II
All
50
100
SSTL-15
All
20, 30, 40, 60,120 (16)
240
SSTL-135
All
20, 30, 40, 60, 120(16)
240
SSTL-125
All
20, 30, 40, 60, 120(16)
240
SSTL-12
GZ only
60, 120(16)
240
HSUL-12
GZ only
TBD(16)
TBD
Final values are pending silicon characterization.
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I/O Standard
Calibrated OCT (Input)
Device Variant Support
Differential SSTL-15
Differential SSTL-135
5-35
RT (Ω)
RZQ (Ω)
All
20, 30, 40, 60,120(16)
240
All
20, 30, 40, 60, 120
(16)
240
20, 30, 40, 60, 120
(16)
240
Differential SSTL-125
All
Differential SSTL-12
GZ only
60, 120(16)
240
Differential HSUL-12
GZ only
TBD(16)
TBD
The RT OCT calibration circuit compares the total impedance of the I/O buffer to the external resistor
connected to the RZQ pin. The circuit dynamically enables or disables the transistors until the total impedance
of the I/O buffer matches the external resistor.
Calibration occurs at the end of the device configuration. When the calibration circuit finds the correct
impedance, the circuit powers down and stops changing the characteristics of the drivers.
Figure 5-10: RT OCT with Calibration
VCCIO FPGA OCT
100 Ω
Z0 = 50 Ω
VREF
100 Ω
GND
Transmitter
Receiver
Dynamic OCT in Arria V Devices
Dynamic OCT is useful for terminating a high-performance bidirectional path by optimizing the signal
integrity depending on the direction of the data. Dynamic OCT also helps save power because device
termination is internal—termination switches on only during input operation and thus draw less static
power.
Note: If you use the SSTL-15, SSTL-135, and SSTL-125 I/O standards with the DDR3 memory interface,
Altera recommends that you use dynamic OCT with these I/O standards to save board space and
cost. Dynamic OCT reduces the number of external termination resistors used.
Table 5-25: Dynamic OCT Based on Bidirectional I/O
Dynamic RT OCT or RS OCT is enabled or disabled based on whether the bidirectional I/O acts as a receiver or
driver.
Dynamic OCT
Dynamic RT OCT
I/O Features in Arria V Devices
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Bidirectional I/O
State
Acts as a receiver
Enabled
Acts as a driver
Disabled
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LVDS Input RD OCT in Arria V Devices
Dynamic OCT
Dynamic RS OCT
Bidirectional I/O
State
Acts as a receiver
Disabled
Acts as a driver
Enabled
Figure 5-11: Dynamic RT OCT in Arria V Devices
VCCIO
VCCIO
Transmitter
Receiver
100 Ω
100 Ω
50 Ω
Z0 = 50 Ω
100 Ω
100 Ω
GND
50 Ω
GND
FPGA OCT
FPGA OCT
VCCIO
VCCIO
Receiver
Transmitter
100 Ω
100 Ω
50 Ω
Z0 = 50 Ω
100 Ω
100 Ω
GND
50 Ω
GND
FPGA OCT
FPGA OCT
LVDS Input RD OCT in Arria V Devices
The Arria V devices support RD OCT in all I/O banks.
You can only use RD OCT if you set the VCCPD to 2.5 V.
Figure 5-12: Differential Input OCT
The Arria V devices support OCT for differential LVDS input buffers with a nominal resistance value of
100 Ω, as shown in this figure.
Transmitter
Receiver
Z0 = 50 Ω
100 Ω
Z0 = 50 Ω
OCT Calibration Block in Arria V Devices
You can calibrate the OCT using any of the available four OCT calibration blocks for each device. Each
calibration block contains one RZQ pin.
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You can use RS and RT OCT in the same I/O bank for different I/O standards if the I/O standards use the
same VCCIO supply voltage. You cannot configure the RS OCT and the programmable current strength for
the same I/O buffer.
The OCT calibration process uses the RZQ pin that is available in every calibration block in a given I/O bank
for series- and parallel-calibrated termination:
• Connect the RZQ pin to GND through an external 100 Ω or 240 Ω resistor (depending on the RS or RT
OCT value).
• The RZQ pin shares the same VCCIO supply voltage with the I/O bank where the pin is located.
Arria V devices support calibrated RS and calibrated RT OCT on all I/O pins except for dedicated configuration
pins.
Calibration Block Locations in Arria V Devices
Figure 5-13: OCT Calibration Block and RZQ Pin Location
This figure shows the location of I/O banks with OCT calibration blocks and RZQ pins in the Arria V device.
This figure represents the top view of the silicon die that corresponds to a reverse view of the device package
and illustrates the highest density device in the device family.
RZQ pin
RZQ pin
Transceiver Block
Transceiver Block
Bank 8A Bank 8B Bank 8C Bank 8D Bank 7D Bank 7C Bank 7B Bank 7A
I/O bank with OCT calibration
block and RZQ pin
Bank 3A Bank 3B Bank 3C Bank 3D Bank 4D Bank 4C Bank 4B Bank 4A
RZQ pin
RZQ pin
Sharing an OCT Calibration Block on Multiple I/O Banks
An OCT calibration block has the same VCCIO as the I/O bank that contains the block. All I/O banks with
the same VCCIO can share one OCT calibration block, even if that particular I/O bank has an OCT calibration
block.
I/O banks that do not have calibration blocks share the calibration blocks in the I/O banks that have
calibration blocks.
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OCT Calibration Block Sharing Example
All I/O banks support OCT calibration with different VCCIO voltage standards, up to the number of available
OCT calibration blocks.
You can configure the I/O banks to receive calibration codes from any OCT calibration block with the same
VCCIO. If a group of I/O banks has the same VCCIO voltage, you can use one OCT calibration block to calibrate
the group of I/O banks placed around the periphery.
Related Information
• OCT Calibration Block Sharing Example on page 5-38
• Dynamic Calibrated On-Chip Termination (ALTOCT) Megafunction User Guide
Provides more information about the OCT calibration block.
OCT Calibration Block Sharing Example
Figure 5-14: Example of Calibrating Multiple I/O Banks with One Shared OCT Calibration Block
As an example, this figure shows a group of I/O banks that has the same VCCIO voltage. The figure does not
show transceiver calibration blocks. This figure represents the top view of the silicon die that corresponds
to a reverse view of the device package and illustrates the highest density device in the device family.
CB7
Transceiver Block
Transceiver Block
Bank 8A Bank 8B Bank 8C Bank 8D Bank 7D Bank 7C Bank 7B Bank 7A
I/O bank with different VCCIO
I/O bank with the same VCCIO
Bank 3A Bank 3B Bank 3C Bank 3D Bank 4D Bank 4C Bank 4B Bank 4A
Because banks 3B, 4C, and 7B have the same VCCIO as bank 7A, you can calibrate all four I/O banks (3B,
4C, 7A, and 7B) with the OCT calibration block (CB7) located in bank 7A.
To enable this calibration, serially shift out the RS OCT calibration codes from the OCT calibration block
in bank 7A to the I/O banks around the periphery.
Related Information
• Sharing an OCT Calibration Block on Multiple I/O Banks on page 5-37
• Dynamic Calibrated On-Chip Termination (ALTOCT) Megafunction User Guide
Provides more information about the OCT calibration block.
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External I/O Termination for Arria V Devices
5-39
External I/O Termination for Arria V Devices
Table 5-26: External Termination Schemes for Different I/O Standards
I/O Standard
External Termination Scheme
3.3 V LVTTL/3.3 V LVCMOS
3.0 V LVVTL/3.0 V LVCMOS
3.0 V PCI
3.0 V PCI-X
2.5 V LVCMOS
No external termination required
1.8 V LVCMOS
1.5 V LVCMOS
1.2 V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
Single-Ended SSTL I/O Standard Termination
SSTL-15 Class I
SSTL-15 Class II
1.8 V HSTL Class I
1.8 V HSTL Class II
1.5 V HSTL Class I
1.5 V HSTL Class II
Single-Ended HSTL I/O Standard Termination
1.2 V HSTL Class I
1.2 V HSTL Class II
Differential SSTL-2 Class I
Differential SSTL-2 Class II
Differential SSTL-18 Class I
Differential SSTL-18 Class II
Differential SSTL I/O Standard Termination
Differential SSTL-15 Class I
Differential SSTL-15 Class II
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Single-ended I/O Termination
I/O Standard
External Termination Scheme
Differential 1.8 V HSTL Class I
Differential 1.8 V HSTL Class II
Differential 1.5 V HSTL Class I
Differential 1.5 V HSTL Class II
Differential HSTL I/O Standard Termination
Differential 1.2 V HSTL Class I
Differential 1.2 V HSTL Class II
LVDS
RSDS
Mini-LVDS
LVPECL
LVDS I/O Standard Termination
RSDS/mini-LVDS I/O Standard Termination
Differential LVPECL I/O Standard Termination
SSTL-15 (17)
SSTL-135 (17)
SSTL-125 (17)
SSTL-12
HSUL-12
Differential SSTL-15 (17)
No external termination required
Differential SSTL-135 (17)
Differential SSTL-125 (17)
Differential SSTL-12
Differential HSUL-12
Single-ended I/O Termination
Voltage-referenced I/O standards require an input VREF and a termination voltage (VTT). The reference
voltage of the receiving device tracks the termination voltage of the transmitting device.
The supported I/O standards such as SSTL-12, SSTL-125, SSTL-135, and SSTL-15 typically do not require
external board termination.
Altera recommends that you use dynamic OCT with these I/O standards to save board space and cost.
Dynamic OCT reduces the number of external termination resistors used.
Note: You cannot use RS and RT OCT simultaneously. For more information, refer to the related
information.
(17)
Altera recommends that you use dynamic OCT with these I/O standards to save board space and cost. Dynamic
OCT reduces the number of external termination resistors used.
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Single-ended I/O Termination
5-41
Figure 5-15: SSTL I/O Standard Termination
This figure shows the details of SSTL I/O termination on Arria V devices.
Termination
SSTL Class I
SSTL Class II
VTT
VTT
50 Ω
25 Ω
VTT
50 Ω 50 Ω
50 Ω
External
On-Board
Termination
50 Ω
25 Ω
VREF
VREF
Transmitter
Receiver
Transmitter
Receiver
VTT
VTT
Series OCT 50 Ω
VTT
Series OCT 25 Ω
50 Ω
OCT Transmit
50 Ω
VREF
VREF
Transmitter
Receiver
Transmitter
Receiver
VTT
FPGA
Parallel OCT
VCCIO
100 Ω
50 Ω
50 Ω
25 Ω
VREF
VREF
100 Ω
GND
Transmitter
100 Ω
GND
Transmitter
VCCIO
Series
OCT 25 Ω
VREF
100 Ω
100 Ω
GND
FPGA
Send Feedback
Receiver
VCCIO
100 Ω
100 Ω
50 Ω
100 Ω
VREF
Receiver
VREF
50 Ω
OCT in
Bidirectional
Pins
I/O Features in Arria V Devices
100 Ω
VCCIO
VCCIO
Series
OCT 50 Ω
FPGA
Parallel OCT
VCCIO
50 Ω
100 Ω
25 Ω
OCT Receive
50 Ω
50 Ω
50 Ω
GND
100 Ω
Series
OCT 50 Ω
FPGA
GND
FPGA
100 Ω
VREF
GND
Series
OCT 25 Ω
FPGA
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Figure 5-16: HSTL I/O Standard Termination
This figure shows the details of HSTL I/O termination on the Arria V devices.
Termination
HSTL Class I
HSTL Class II
VTT
VTT
50 Ω
VTT
50 Ω
50 Ω
50 Ω
External
On-Board
Termination
50 Ω
VREF
VREF
Transmitter
Receiver
Transmitter
Receiver
VTT
VTT
VTT
Series OCT 50 Ω
Series OCT 25 Ω
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
VREF
VREF
OCT Transmit
Transmitter
Receiver
VCCIO
Transmitter
Receiver
VTT
FPGA
Parallel OCT
100 Ω
100 Ω
50 Ω
VREF
VREF
100 Ω
Transmitter
GND
VCCIO
Series
OCT 50 Ω
100 Ω
Receiver
Transmitter
VCCIO
Series
OCT 25 Ω
100 Ω
100 Ω
VREF
100 Ω
50 Ω
100 Ω
GND
VCCIO
100 Ω
50 Ω
OCT in
Bidirectional
Pins
Receiver
GND
VCCIO
VREF
100 Ω
FPGA
Parallel OCT
50 Ω
50 Ω
OCT Receive
VCCIO
GND
VREF
FPGA
100 Ω
Series
OCT 50 Ω
FPGA
100 Ω
GND
GND
VREF
FPGA
Series
OCT 25 Ω
FPGA
Related Information
Dynamic OCT in Arria V Devices on page 5-35
Differential I/O Termination
The I/O pins are organized in pairs to support differential I/O standards. Each I/O pin pair can support
differential input and output buffers.
The supported I/O standards such as Differential SSTL-12, Differential SSTL-15, Differential SSTL-125, and
Differential SSTL-135 typically do not require external board termination.
Altera recommends that you use dynamic OCT with these I/O standards to save board space and cost.
Dynamic OCT reduces the number of external termination resistors used.
Differential HSTL, SSTL, and HSUL Termination
Differential HSTL, SSTL, and HSUL inputs use LVDS differential input buffers. However, RD support is
only available if the I/O standard is LVDS.
Differential HSTL, SSTL, and HSUL outputs are not true differential outputs. These I/O standards use two
single-ended outputs with the second output programmed as inverted.
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Figure 5-17: Differential SSTL I/O Standard Termination
This figure shows the details of Differential SSTL I/O termination on Arria V devices.
Termination
Differential SSTL Class I
VTT
Differential SSTL Class II
VTT
50 Ω
VTT
50 Ω
VTT
50 Ω
VTT
50 Ω
50 Ω
VTT
50 Ω
25 Ω
50 Ω
50 Ω
25 Ω
External
On-Board
Termination
25 Ω
25 Ω
50 Ω
50 Ω
Transmitter
Receiver
Transmitter
VCCIO
Receiver
VCCIO
VTT
Series OCT 50 Ω
Series OCT 25 Ω
50 Ω
100 Ω
100 Ω
Z0 = 50 Ω
Z0 = 50 Ω
VCCIO
OCT
VCCIO
VTT
100 Ω
100 Ω
50 Ω
100 Ω
GND
Z0 = 50 Ω
100 Ω
GND
Z0 = 50 Ω
100 Ω
Transmitter
100 Ω
Receiver
GND
Transmitter
Receiver
GND
Figure 5-18: Differential HSTL I/O Standard Termination
This figure shows the details of Differential HSTL I/O standard termination on Arria V devices.
Termination
Differential HSTL Class I
Differential HSTL Class II
VTT VTT
50 Ω
VTT VTT
50 Ω
50 Ω
VTT VTT
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
50 Ω
External
On-Board
Termination
Transmitter
Receiver
Transmitter
VCCIO
Series OCT 50 Ω
Receiver
VTT
VCCIO
Series OCT 25 Ω
50 Ω
100 Ω
Z0 = 50 Ω
VCCIO
OCT
100 Ω
Z0 = 50 Ω
VCCIO
VTT
100 Ω
100 Ω
50 Ω
100 Ω
GND
Z0 = 50 Ω
GND
GND
Z0 = 50 Ω
100 Ω
Transmitter
100 Ω
100 Ω
Receiver
Transmitter
GND
Receiver
LVDS, RSDS, and Mini-LVDS Termination
All I/O banks have dedicated circuitry to support the true LVDS, RSDS, and mini-LVDS I/O standards by
using true LVDS output buffers without resistor networks.
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Figure 5-19: LVDS I/O Standard Termination
This figure shows the LVDS I/O standard termination. The on-chip differential resistor is available in all
I/O banks.
Termination
LVDS
Differential Outputs
Differential Inputs
50 Ω
External
On-Board
Termination
100 Ω
50 Ω
Differential Outputs
OCT Receiver
(True LVDS
Output)
Differential Inputs
OCT
50 Ω
100 Ω
50 Ω
Receiver
Emulated LVDS, RSDS, and Mini-LVDS Termination
The I/O banks also support emulated LVDS, RSDS, and mini-LVDS I/O standards.
Emulated LVDS, RSDS and mini-LVDS output buffers use two single-ended output buffers with an external
single-resistor or three-resistor network, and can be tri-stated.
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Figure 5-20: Emulated LVDS, RSDS, or Mini-LVDS I/O Standard Termination
The output buffers, as shown in this figure, are available in all I/O banks. RS and RP values are pending
characterization.
Termination
Emulated LVDS, RSDS, and mini-LVDS
≤ 1 inch
50 Ω
RS
External
On-Board
Termination
(RSDS_E_3R)
100 Ω
RP
RS
50 Ω
External Resistor
Transmitter
Receiver
OCT
≤ 1 inch
50 Ω
RS
OCT
100 Ω
RP
(RSDS_E_3R)
RS
50 Ω
External Resistor
Transmitter
Receiver
Single-Ended Outputs
Differential Inputs
OCT
OCT Receive
(Single-Ended
Output with
Single Resistor
LVDS_E_1R)
50 Ω
External
Resistor
100 Ω
RP
50 Ω
Transmitter
Receiver
Single-Ended Outputs
Differential Inputs
OCT
≤ 1 inch
OCT Receive
(Single-Ended
Output with
Three-Resistor
Network,
LVDS_E_3R)
50 Ω
RS
100 Ω
RP
RS
50 Ω
External Resistor
Transmitter
Receiver
To meet the RSDS or mini-LVDS specifications, you require a resistor network to attenuate the outputvoltage swing.
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LVPECL Termination
You can modify the three-resistor network values to reduce power or improve the noise margin. Choose
resistor values that satisfy the following equation.
Figure 5-21: Resistor Network Calculation
Note: Altera recommends that you perform additional simulations with IBIS or SPICE models to validate
that the custom resistor values meet the RSDS or mini-LVDS I/O standard requirements.
For information about the data rates supported for external single resistor or three-resistor network, refer
to the device datasheet.
Related Information
• Arria V Device Datasheet
• National Semiconductor (www.national.com)
For more information about the RSDS I/O standard, refer to the RSDS Specification on the National
Semiconductor web site.
LVPECL Termination
The Arria V devices support the LVPECL I/O standard on input clock pins only:
• LVPECL input operation is supported using LVDS input buffers.
• LVPECL output operation is not supported.
Use AC coupling if the LVPECL common-mode voltage of the output buffer does not match the LVPECL
input common-mode voltage.
Note: Altera recommends that you use IBIS models to verify your LVPECL AC/DC-coupled termination.
Figure 5-22: LVPECL AC-Coupled Termination
LVPECL
Output Buffer
LVPECL
Input Buffer
0.1 µF
Z0 = 50 Ω
VICM
50 Ω
0.1 µF
Z0 = 50 Ω
50 Ω
Support for DC-coupled LVPECL is available if the LVPECL output common mode voltage is within the
Arria V LVPECL input buffer specification.
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Figure 5-23: LVPECL DC-Coupled Termination
LVPECL
Output Buffer
LVPECL
Input Buffer
Z0 = 50 Ω
100 Ω
Z0 = 50 Ω
For information about the VICM specification, refer to the device datasheet.
Related Information
Arria V Device Datasheet
Document Revision History
Date
Version
January 2014
2014.01.10
• Updated statements in several topics to clarify that each modular I/O
bank can support multiple I/O standards that use the same voltages.
• Updated the guideline topic about using the same VCCPD for I/O banks
in the same VCCPD group to improve clarity.
• Added the optional PCI clamp diode to the figure showing the IOE
structure.
• Changed all "SoC FPGA" to "SoC".
• Removed SSTL-125 from the list of supported I/O standards for the
HPS I/O.
• Removed all "preliminary" marks.
• Removed the statement specifying that value "0" of the programmable
VOD is only available for RSDS and mini-LVDS I/O standards only. The
value is now available for the LVDS I/O standards.
• Clarified that you can only use RD OCT if VCCPD is 2.5 V.
• Added link to Knowledge Base article that clarifies about vertical
migration (drop-in compatibility).
• Corrected the modular I/O banks tables for Arria V SX and ST devices.
Bank 7G, available in the F1517 package, is an FPGA I/O bank instead
of an HPS column I/O bank. The number of I/O pins remain the same.
August 2013
2013.08.19
Added 3.3 V input signal for 2.5 V VCCIO in the table listing the MultiVolt
I/O support.
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Document Revision History
Date
Version
Changes
June 2013
2013.06.21
• Removed 3.3 V input signal for 2.5 V VCCIO in the table listing the
MultiVolt I/O support.
• Updated the topic about LVDS input RD OCT to remove the requirement for setting the VCCIO to 2.5 V. RD OCT now requires only that the
VCCPD is 2.5 V.
• Updated the topic about LVPECL termination to improve clarity.
May 2013
2013.05.06
• Moved all links to the Related Information section of respective topics
for easy reference.
• Added link to the known document issues in the Knowledge Base.
• Added note about the power-up sequence requirement if you plan to
migrate your design to devices that require the specific power-up
sequence.
• Updated the RT OCT input termination settings for the 1.5 V SSTL I/O
standards.
• Updated the maximum speed of RSDS and mini-LVDS to 360 Mbps
and 400 Mbps, respectively, in the notes for the supported FPGA I/O
standards table.
December 2012
2012.12.04
• Added LVVTL and LVCMOS voltage levels for the Arria V GZ variant,
and corrected the LVVTL and LVCMOS voltage levels for the
Arria V GX, GT, SX, and ST devices.
• Updated the SSTL and HSTL I/O termination figures to add VREF
inputs for OCT in bidirectional pins.
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Date
November 2012
June 2012
Version
2012.11.19
2.0
5-49
Changes
• Reorganized content and updated template.
• Added the I/O resources per package and I/O vertical migration sections
for easy reference.
• Added the steps to verify pin migration compatibility using the
Quartus II software.
• Updated the I/O standards support table with Arria V GZ and HPS I/
O information.
• Updated the guideline about mixing voltage-referenced and non-voltagereferenced I/O standards to include Arria V GZ information.
• Updated the guideline about observing device absolute maximum rating
for 3.3 V interfacing, specifically the off-chip clamping diode usage for
Arria V GZ.
• Updated the VREF pin restrictions guideline to specify that it applies
only to Arria V GX, GT, SX, and ST, but not Arria V GZ.
• Added the I/O bank locations for Arria V GZ devices.
• Rearranged the I/O banks groups tables for easier reference.
• Added modular I/O banks for Arria V GZ devices.
• Restructured the information in the topic about I/O buffers and registers
to improve clarity and for faster reference.
• Added Arria V GZ and HPS information to the topic on programmable
IOE features.
• Rearranged the tables about on-chip I/O termination for clarity and
topic-based reference.
• Added Arria V GZ OCT information to all on-chip I/O termination
tables.
• Added all I/O standards and external termination schemes supported
by all Arria V devices to the external I/O termination table.
Updated for the Quartus II software v12.0 release:
• Restructured chapter.
• Added “Design Considerations”, “VCCIO Restriction”, “LVDS
Channels”, “Modular I/O Banks”, and “OCT Calibration Block” sections.
• Added Figure 5–1, Figure 5–2, and Figure 5–3
• Updated Table 5–1, Table 5–6, and Table 5–8.
• Updated Figure 5–19 with emulated LVDS with external single resistor.
February 2012
1.2
Updated Table 5–3.
November 2011
1.1
• Restructured chapter.
• Updated Table 5–3.
May 2011
1.0
Initial release.
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The high-speed differential I/O interfaces and dynamic phase alignment (DPA) features in Arria V devices
provide advantages over single-ended I/Os and contribute to the achievable overall system bandwidth.
Arria V devices support low-voltage differential signaling (LVDS), mini-LVDS, and reduced swing
differential signaling (RSDS) differential I/O standards.
The following figure shows the I/O bank support for high-speed differential I/O in the Arria V devices.
Figure 6-1: I/O Bank Support for High-Speed Differential I/O
LVDS I/Os
I/Os with
Dedicated
SERDES Circuitry
LVDS Interface
with 'Use External PLL'
Option Enabled
LVDS Interface
with 'Use External PLL'
Option Disabled
Related Information
• I/O Standards Support for FPGA I/O in Arria V Devices on page 5-6
Provides information about the supported differential I/O standards.
• Arria V Device Handbook: Known Issues
Lists the planned updates to the Arria V Device Handbook chapters.
Dedicated High-Speed Circuitries in Arria V Devices
The following dedicated circuitries are available in the Arria V device family to support high-speed
differential I/O:
•
•
•
•
Differential I/O buffer
Transmitter serializer
Receiver deserializer
Data realignment (Bit-slip)
© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words
and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other
words and logos identified as trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with
Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes
no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
www.altera.com
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9001:2008
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SERDES and DPA Bank Locations in Arria V Devices
• DPA
• Synchronizer (FIFO buffer)
• Phase-locked loops (PLLs)
SERDES and DPA Bank Locations in Arria V Devices
The dedicated serializer/deserializer (SERDES) and DPA circuitry that supports high-speed differential I/Os
is located in the top and bottom banks of the Arria V devices.
The following figures show the high-level location of SERDES/DPA in the Arria V devices.
Figure 6-2: High-Speed Differential I/Os with DPA Locations in Arria V GX A1 and A3 Devices, and Arria V GT
C3 Device.
General Purpose I/O
General Purpose I/O and High-Speed
LVDS I/O with DPA and Soft-CDR
Fractional PLL
FPGA Fabric
(Logic Elements, DSP,
Embedded Memory,
Clock Networks)
Transceiver Block
Figure 6-3: High-Speed Differential I/Os with DPA Locations in Arria V GX A5, A7, B1, and B3 Devices, and
Arria V GT C7, D3, and D7 Devices
General Purpose I/O and High-Speed
LVDS I/O with DPA and Soft-CDR
Fractional PLL
Transceiver Block
FPGA Fabric
(Logic Elements, DSP,
Embedded Memory,
Clock Networks)
Figure 6-4: High-Speed Differential I/Os with DPA Locations in Arria V GX B5 and B7 Devices
General Purpose I/O and High-Speed
LVDS I/O with DPA and Soft-CDR
Fractional PLL
Transceiver Block
Altera Corporation
FPGA Fabric
(Logic Elements, DSP,
Embedded Memory,
Clock Networks)
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Figure 6-5: High-Speed Differential I/Os with DPA Locations in Arria V GZ Devices
Left Clock
Region
General Purpose I/O and High-Speed
LVDS I/O with DPA and Soft-CDR
Right Clock
Region
FPGA Fabric
(Logic Elements, DSP,
Embedded Memory,
Clock Networks)
Fractional PLL
Transceiver Block
Left Clock
Region
Right Clock
Region
Related Information
PLLs and Clocking for Arria V Devices on page 6-7
LVDS SERDES Circuitry
The Arria V devices have built-in serializer/deserializer (SERDES) circuitry that supports high-speed LVDS
interfaces. You can configure the SERDES circuitry to support source-synchronous communication protocols
such as RapidIO®, XSBI, serial peripheral interface (SPI), and asynchronous protocols such as Gigabit
Ethernet (GbE).
The following figure shows a transmitter and receiver block diagram for the LVDS SERDES circuitry with
the interface signals of the transmitter and receiver data paths.
Figure 6-6: LVDS SERDES
2
Serializer
tx_in
10 bits
maxiumum
data width
10
IOE
IOE supports SDR, DDR, or non-registered datapath
LVDS Transmitter
tx_coreclock
3
(LVDS_LOAD_EN, diffioclk, tx_coreclock)
IOE supports SDR, DDR, or non-registered datapath
rx_out
tx_out
+
–
DIN DOUT
2
10
LVDS Receiver
IOE
Deserializer
Bit Slip
Synchronizer
+
–
rx_in
DPA Circuitry
10
DOUT
DIN
FPGA
Fabric
DOUT
DIN
DOUT
Retimed
Data
DIN
DIN
(LOAD_EN,
diffioclk) Clock Mux
rx_divfwdclk
rx_outclock
LVDS_diffioclk
diffioclk
DPA_diffioclk
DPA Clock
2
3
(DPA_LOAD_EN,
DPA_diffioclk, rx_divfwdclk)
3 (LVDS_LOAD_EN,
LVDS_diffioclk, rx_outclock)
DPA Clock Domain
LVDS Clock Domain
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Fractional PLL
8 Serial LVDS
Clock Phases
rx_inclock / tx_inclock
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True LVDS Buffers in Arria V Devices
The preceding figure shows a shared PLL between the transmitter and receiver. If the transmitter and receiver
do not share the same PLL, you require two fractional PLLs. In single data rate (SDR) and double data rate
(DDR) modes, the data width is 1 and 2 bits, respectively.
The ALTLVDS transmitter and receiver requires various clock and load enable signals from a fractional
PLL. The Quartus II software configures the PLL settings automatically. The software is also responsible for
generating the various clock and load enable signals based on the input reference clock and selected data
rate.
Note: For the maximum data rate supported by the Arria V devices, refer to the device overview.
Related Information
• Arria V Device Overview
• LVDS SERDES Transmitter/Receiver (ALTLVDS_TX and ALTLVDS_RX) Megafunction User Guide
Provides a list of the LVDS transmitter and receiver ports and settings using ALTLVDS.
• Guideline: Use PLLs in Integer PLL Mode for LVDS on page 6-7
True LVDS Buffers in Arria V Devices
The following tables list the number of true LVDS buffers supported in Arria V devices with these conditions:
• The LVDS channel count does not include dedicated clock pins.
• Dedicated SERDES and DPA is available for top and bottom banks only.
• Each I/O sub-bank can support up to two independent ALTLVDS interfaces. For example, you can place
two ALTLVDS interfaces in bank 8A driven by two different PLLs, provided that the LVDS channels are
not interleaved.
Table 6-1: LVDS Channels Supported in Arria V GX Devices
Member Code
Package
672-pin FineLine BGA, Flip
Chip
A1 and A3
896-pin FineLine BGA, Flip
Chip
672-pin FineLine BGA, Flip
Chip
A5 and A7
896-pin FineLine BGA, Flip
Chip
1152-pin FineLine BGA, Flip
Chip
Altera Corporation
Side
TX
RX
Top
28
34
Bottom
29
34
Top
33
40
Bottom
34
40
Top
34
44
Bottom
34
44
Top
42
48
Bottom
42
48
Top
60
68
Bottom
60
68
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Member Code
Package
896-pin FineLine BGA, Flip
Chip
B1 and B3
1152-pin FineLine BGA, Flip
Chip
1517-pin FineLine BGA, Flip
Chip
1152-pin FineLine BGA, Flip
Chip
B5 and B7
1517-pin FineLine BGA, Flip
Chip
Side
TX
RX
Top
42
48
Bottom
42
48
Top
60
68
Bottom
60
68
Top
80
88
Bottom
80
88
Top
60
68
Bottom
60
68
Top
80
88
Bottom
80
88
Side
TX
RX
Top
26
34
Bottom
26
34
Top
34
40
Bottom
34
40
Top
42
48
Bottom
42
48
Top
60
68
Bottom
60
68
Top
42
48
Bottom
42
48
Top
60
68
Bottom
60
68
Top
80
88
Bottom
80
88
Top
60
68
Bottom
60
68
Top
80
88
Bottom
80
88
6-5
Table 6-2: LVDS Channels Supported in Arria V GT Devices
Member Code
Package
672-pin FineLine BGA, Flip
Chip
C3
896-pin FineLine BGA, Flip
Chip
896-pin FineLine BGA, Flip
Chip
C7
1152-pin FineLine BGA, Flip
Chip
896-pin FineLine BGA, Flip
Chip
D3
1152-pin FineLine BGA, Flip
Chip
1517-pin FineLine BGA, Flip
Chip
1152-pin FineLine BGA, Flip
Chip
D7
1517-pin FineLine BGA, Flip
Chip
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Table 6-3: LVDS Channels Supported in Arria V GZ Devices
Member Code
Package
780-pin FineLine BGA, Flip
Chip
E1 and E3
1152-pin FineLine BGA, Flip
Chip
1152-pin FineLine BGA, Flip
Chip
E5 and E7
1517-pin FineLine BGA, Flip
Chip
Side
TX
RX
Top
42
51
Bottom
39
39
Top
48
57
Bottom
51
51
Top
54
63
Bottom
75
75
Top
79
81
Bottom
87
87
Side
TX
RX
Top
14
37
Bottom
20
37
Top
14
37
Bottom
30
77
Top
40
48
Bottom
80
88
Side
TX
RX
Top
14
37
Bottom
20
37
Top
14
37
Bottom
30
77
Top
40
48
Bottom
80
88
Table 6-4: LVDS Channels Supported in Arria V SX Devices
Member Code
Package
896-pin FineLine BGA, Flip
Chip
B3 and B5
1152-pin FineLine BGA, Flip
Chip
1517-pin FineLine BGA, Flip
Chip
Table 6-5: LVDS Channels Supported in Arria V ST Devices
Member Code
Package
896-pin FineLine BGA, Flip
Chip
D3 and D5
1152-pin FineLine BGA, Flip
Chip
1517-pin FineLine BGA, Flip
Chip
Emulated LVDS Buffers in Arria V Devices
The Arria V device family supports emulated LVDS:
• You can use unutilized true LVDS input channels as emulated LVDS output buffers (eTX).
• The emulated differential output buffers support tri-state capability.
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High-Speed I/O Design Guidelines for Arria V Devices
6-7
High-Speed I/O Design Guidelines for Arria V Devices
There are several considerations that require your attention to ensure the success of your designs. Unless
noted otherwise, these design guidelines apply to all variants of this device family.
PLLs and Clocking for Arria V Devices
To generate the parallel clocks (rx_outclock and tx_outclock) and high-speed clocks (diffioclk), the
Arria V devices provide fractional PLLs in the high-speed differential I/O receiver and transmitter channels.
Related Information
• Guideline: Use PLLs in Integer PLL Mode for LVDS on page 6-7
• SERDES and DPA Bank Locations in Arria V Devices on page 6-2
Provides information about the PLL locations available for each Arria V device.
• Guideline: Use High-Speed Clock from PLL to Clock LVDS SERDES Only on page 6-7
Guideline: Use PLLs in Integer PLL Mode for LVDS
To drive the LVDS channels, you must use the PLLs in integer PLL mode. The center or corner PLLs can
drive the LVDS receiver and transmitter channels.
However, in Arria V GZ devices, the clock tree network cannot cross over to different I/O regions. For
example, the top left corner PLL cannot cross over to drive the LVDS receiver and transmitter channels on
the top right I/O bank.
Related Information
Pin Placement Guidelines for DPA and Non-DPA Differential Channels on page 6-11
Provides more information about the fractional PLL clocking restrictions.
Guideline: Use High-Speed Clock from PLL to Clock LVDS SERDES Only
The high-speed clock generated from the PLL is intended to clock the LVDS SERDES circuitry only. Do not
use the high-speed clock to drive other logic because the allowed frequency to drive the core logic is restricted
by the PLL FOUT specification.
For more information about the FOUT specification, refer to the device datasheet.
LVDS Interface with External PLL Mode
The MegaWizard Plug-In Manager provides an option for implementing the LVDS interface with the Use
External PLL option. With this option enabled you can control the PLL settings, such as dynamically
reconfiguring the PLL to support different data rates, dynamic phase shift, and other settings. You must also
instantiate the an Altera_PLL megafunction to generate the various clock and load enable signals.
If you enable the Use External PLL option with the ALTLVDS transmitter and receiver, the following signals
are required from the Altera_PLL megafunction:
• Serial clock input to the SERDES of the ALTLVDS transmitter and receiver
• Load enable to the SERDES of the ALTLVDS transmitter and receiver
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Altera_PLL Signal Interface with ALTLVDS Megafunction
• Parallel clock used to clock the transmitter FPGA fabric logic and parallel clock used for the receiver
• Asynchronous PLL reset port of the ALTLVDS receiver
Altera_PLL Signal Interface with ALTLVDS Megafunction
Table 6-6: Signal Interface Between Altera_PLL and ALTLVDS Megafunctions
This table lists the signal interface between the output ports of the Altera_PLL megafunction and the input ports of
the ALTLVDS transmitter and receiver. As an example, the table lists the serial clock output, load enable output,
and parallel clock output generated on ports outclk0, outclk1, and outclk2, along with the locked signal of the
Altera_PLL instance. You can choose any of the PLL output clock ports to generate the interface clocks.
From the Altera_PLL Megafunction
Serial clock output (outclk0)
The serial clock output (outclk0) can
only drive tx_inclock on the
ALTLVDS transmitter, and rx_
inclock and rx_dpaclock on the
ALTLVDS receiver. This clock cannot
drive the core logic.
To the ALTLVDS Transmitter
tx_inclock (serial clock
input to the transmitter)
To the ALTLVDS Receiver
rx_inclock (serial clock input)
rx_dpaclock
Load enable output (outclk1)
tx_enable (load enable to rx_enable (load enable for the
the transmitter)
deserializer)
Parallel clock output (outclk2)
Parallel clock used inside rx_syncclock (parallel clock input)
the transmitter core logic in and parallel clock used inside the
the FPGA fabric
receiver core logic in the FPGA fabric
~(locked)
—
pll_areset (asynchronous PLL reset
port)
The pll_areset signal is automatically
enabled for the LVDS receiver in
external PLL mode. This signal does
not exist for LVDS transmitter
instantiation when the external PLL
option is enabled.
Note: With soft SERDES, a different clocking requirement is needed.
Related Information
LVDS SERDES Transmitter/Receiver (ALTLVDS_RX/TX) Megafunction User Guide
More information about the different clocking requirement for soft SERDES.
Altera_PLL Parameter Values for External PLL Mode
The following examples show the clocking requirements to generate output clocks for ALTLVDS_TX and
ALTLVDS_RX using the Altera_PLL megafunction. The examples set the phase shift with the assumption
that the clock and data are edge aligned at the pins of the device.
Note: For other clock and data phase relationships, Altera recommends that you first instantiate your
ALTLVDS_RX and ALTLVDS_TX interface without using the external PLL mode option. Compile
the megafunctions in the Quartus II software and take note of the frequency, phase shift, and duty
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Altera_PLL Parameter Values for External PLL Mode
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cycle settings for each clock output. Enter these settings in the Altera_PLL megafunction parameter
editor and then connect the appropriate output to the ALTLVDS_RX and ALTLVDS_TX
megafunctions.
Table 6-7: Example: Generating Output Clocks Using an Altera_PLL Megafunction (No DPA and Soft-CDR Mode)
This table lists the parameter values that you can set in the Altera_PLL parameter editor to generate three output
clocks using an Altera_PLL megafunction if you are not using DPA and soft-CDR mode.
Parameter
outclk0
outclk1
outclk2
(Connects to the tx_inclock (Connects to the tx_enable (Used as the core clock for the
port of ALTLVDS_TX and the
port of ALTLVDS_TX and the parallel data registers for both
rx_inclock port of ALTLVDS_ rx_enable port of ALTLVDS_ transmitter and receiver, and
connects to the rx_synclock
RX)
RX)
port of ALTLVDS_RX)
Frequency
data rate
data rate/serialization factor data rate/serialization
factor
Phase shift
–180°
[(deserialization factor – 2)/ –180/serialization factor
deserialization factor] x 360°
(outclk0 phase shift
divided by the serialization
factor)
Duty cycle
50%
100/serialization factor
50%
Figure 6-7: Phase Relationship for External PLL Interface Signals
inclk0
VCO clk
(internal PLL clk)
outclk0
(-180° phase shift)
outclk1
(288° phase shift)
outclk2
(-18° phase shift)
RX serial data
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
tx_outclk
TX serial data
D1
D2
D3
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D5
D6
D7
D8
D9
D10
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Connection between Altera_PLL and ALTLVDS
Table 6-8: Example: Generating Output Clocks Using an Altera_PLL Megafunction (With DPA and Soft-CDR
Mode)
This table lists the parameter values that you can set in the Altera_PLL parameter editor to generate four output
clocks using an Altera_PLL megafunction if you are using DPA and soft-CDR mode. The locked output port of
Altera_PLL must be inverted and connected to the pll_areset port of the ALTLVDS_RX megafunction if you are
using DPA and soft-CDR mode.
Parameter
outclk0
outclk1
outclk2
outclk3
(Connects to the tx_
inclock port of
ALTLVDS_TX and the
rx_inclock port of
ALTLVDS_RX)
(Connects to the tx_
enable port of
ALTLVDS_TX and the
rx_enable port of
ALTLVDS_RX)
(Used as the core clock
for the parallel data
registers for both
transmitter and
receiver, and connects
to the rx_synclock
port of ALTLVDS_RX)
(Connects to the rx_
dpaclock port of
ALTLVDS_RX)
Frequency
data rate
data rate/serialization data rate/serialization data rate
factor
factor
Phase shift
–180°
[(deserialization factor –180/serialization
- 2)/deserialization
factor
factor] x 360°
(outclk0 phase shift
divided by the
serialization factor)
–180°
Duty cycle
50%
100/serialization factor 50%
50%
Connection between Altera_PLL and ALTLVDS
Figure 6-8: LVDS Interface with the Altera_PLL Megafunction (Without DPA and Soft-CDR Mode)
This figure shows the connections between the Altera_PLL and ALTLVDS megafunction if you are not using
DPA and soft-CDR mode.
FPGA Fabric
Transmitter
Core Logic
D
Q
LVDS Transmitter
(ALTLVDS)
tx_in
tx_inclock
tx_enable
tx_coreclk
outclk0
outclk1
outclk2
LVDS Receiver
(ALTLVDS)
rx_coreclk
Receiver
Core Logic
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Q
locked
Altera_PLL
inclk0
pll_areset
D
rx_out
rx_inclock
rx_enable
rx_syncclock
pll_areset
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Pin Placement Guidelines for DPA and Non-DPA Differential Channels
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Figure 6-9: LVDS Interface with the Altera_PLL Megafunction (With DPA)
This figure shows the connections between the Altera_PLL and ALTLVDS megafunction if you are using
DPA. The locked output port must be inverted and connected to the pll_areset port.
FPGA Fabric
D
Transmitter
Core Logic
Q
LVDS Transmitter
(ALTLVDS)
tx_in
tx_inclock
tx_enable
tx_coreclk
outclk0
outclk1
outclk2
outclk3
LVDS Receiver
(ALTLVDS)
rx_coreclk
Q
Receiver
Core Logic
D
locked
Altera_PLL
inclk0
pll_areset
rx_inclock
rx_out rx_dpaclock
rx_enable
rx_syncclock
pll_areset
Figure 6-10: LVDS Interface with the Altera_PLL Megafunction (With Soft-CDR Mode)
This figure shows the connections between the Altera_PLL and ALTLVDS megafunction if you are using
soft-CDR mode. The locked output port must be inverted and connected to the pll_areset port.
FPGA Fabric
Transmitter
Core Logic
D
Q
LVDS Transmitter
(ALTLVDS)
tx_in
tx_inclock
tx_enable
tx_coreclk
outclk0
outclk1
outclk2
outclk3
LVDS Receiver
(ALTLVDS)
rx_coreclk
Receiver
Core Logic
Q
D
locked
Altera_PLL
inclk0
pll_areset
rx_inclock
rx_dpaclock
rx_out
rx_divfwdclk rx_enable
rx_syncclock
pll_areset
When generating the Altera_PLL megafunction, the Left/Right PLL option is configured to set up the PLL
in LVDS mode. Instantiation of pll_areset is optional.
The rx_syncclock port is automatically enabled in an LVDS receiver in external PLL mode. The Quartus II
compiler output error messages if this port is not connected as shown in the preceding figures.
Pin Placement Guidelines for DPA and Non-DPA Differential Channels
DPA usage adds some constraints on the placement of high-speed differential channels. If DPA-enabled or
DPA-disabled differential channels(18) in the differential banks are used, you must adhere to the differential
(18)
DPA-enabled differential channels refer to DPA mode or soft-CDR mode while DPA disabled channels refer
to non-DPA mode.
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Guideline: Using DPA-Enabled Differential Channels
pin placement guidelines to ensure the proper high-speed operation. The Quartus II compiler automatically
checks the design and issues an error message if the guidelines are not followed.
Note: The figures in this section show guidelines for using corner and center PLLs but do not necessarily
represent the exact locations of the high-speed LVDS I/O banks.
Related Information
Guideline: Use PLLs in Integer PLL Mode for LVDS on page 6-7
Guideline: Using DPA-Enabled Differential Channels
Each differential receiver in an I/O block has a dedicated DPA circuit to align the phase of the clock to the
data phase of its associated channel. If you enable a DPA channel in a bank, you can use both single-ended
I/Os and differential I/O standards in the bank.
You can place double data rate I/O (DDIO) output pins within I/O modules that have the same pad group
number as a SERDES differential channel. However, you cannot place SDR I/O output pins within I/O
modules that have the same pad group number as a receiver SERDES differential channel. You must
implement the input register within the FPGA fabric logic.
If you use DPA-enabled channels in differential banks, adhere to the following guidelines.
Using Center and Corner PLLs
If two PLLs drive the DPA-enabled channels in a bank—the corner and center PLL drive one group
each—there must be at least one row (one differential channel) of separation between the two groups of
DPA-enabled channels, as shown in the following figure.
Figure 6-11: Center and Corner PLLs Driving DPA-enabled Differential I/Os in the Same Bank
Corner PLL
Reference CLK
DPA-enabled Diff I/O
DPA-enabled Diff I/O
Channels Driven by Corner PLL
DPA-enabled Diff I/O
DPA-enabled Diff I/O
DPA-enabled Diff I/O
Diff I/O
One Unused Channel for Buffer
DPA-enabled Diff I/O
DPA-enabled Diff I/O
DPA-enabled Diff I/O
Channels Driven by Center PLL
DPA-enabled Diff I/O
Reference CLK
Center PLL
This separation prevents noise mixing because the two groups can operate at independent frequencies. No
separation is necessary if a single PLL is driving both the DPA-enabled channels and DPA-disabled channels.
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Guideline: Using DPA-Enabled Differential Channels
6-13
Using Both Center PLLs
You can use center PLLs to drive DPA-enabled channels simultaneously, if they drive these channels in their
adjacent banks only, as shown in the previous figure. If one of the center PLLs drives the DPA-enabled
channels in the left and right I/O banks in Arria V GX, GT, SX, or ST devices, you cannot use the other
center PLL for DPA-enabled channels. If the center left PLL drives the DPA-enabled channels in the right
I/O bank, the right center PLL cannot drive the DPA-enabled channels in the left I/O bank, and vice versa.
The center PLLs cannot drive cross-banks simultaneously in Arria V GZ devices. Refer to the following
figures.
Figure 6-12: Center PLLs Driving DPA-enabled Differential I/Os in Arria V GX, GT, SX, and ST Devices
DPA-enabled Diff I/O
DPA-enabled Diff I/O
DPA-enabled Diff I/O
DPA-enabled Diff I/O
DPA-enabled Diff I/O
DPA-enabled Diff I/O
DPA-enabled Diff I/O
DPA-enabled Diff I/O
Reference CLK
Reference CLK
Center PLL
Center PLL
Center PLL
Center PLL
Reference CLK
Reference CLK
DPA-enabled Diff I/O
DPA-enabled Diff I/O
DPA-enabled Diff I/O
DPA-enabled Diff I/O
DPA-enabled Diff I/O
DPA-enabled Diff I/O
DPA-enabled Diff I/O
DPA-enabled Diff I/O
Unused PLL
Figure 6-13: Center PLLs Driving DPA-enabled Differential I/Os in Arria V GZ Devices
DPA-enabled Diff I/O
DPA-enabled Diff I/O
DPA-enabled Diff I/O
DPA-enabled Diff I/O
Reference CLK
Center PLL
Center PLL
Reference CLK
DPA-enabled Diff I/O
DPA-enabled Diff I/O
DPA-enabled Diff I/O
DPA-enabled Diff I/O
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Guideline: Using DPA-Enabled Differential Channels
Figure 6-14: Invalid Placement of DPA-enabled Differential I/Os Driven by Both Center PLLs
DPA-enabled Diff I/O
DPA-enabled Diff I/O
DPA-enabled Diff I/O
DPA-enabled Diff I/O
Reference CLK
Center PLL
Center PLL
Reference CLK
DPA-enabled Diff I/O
DPA-enabled Diff I/O
DPA-enabled Diff I/O
DPA-enabled Diff I/O
Using Both Corner PLLs
You can use both corner PLLs to drive DPA-enabled channels simultaneously, if they drive the channels in
their adjacent banks only. There must be at least one row of separation between the two groups of DPAenabled channels.
If one of the corner PLLs drives DPA-enabled channels in the left and right I/O banks, you cannot use the
center PLLs to drive DPA-enabled channels. You can use the other corner PLL to drive DPA-enabled channels
in their adjacent bank only. There must be at least one row of separation between the two groups of DPAenabled channels.
If the left corner PLL drives DPA-enabled channels in the right I/O bank, the right corner PLL cannot drive
DPA-enabled channels in the left I/O bank, and vice versa. In other words, the corner PLLs cannot drive
cross-banks simultaneously, as shown in the following figure.
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Guideline: Using DPA-Disabled Differential Channels
6-15
Figure 6-15: Corner PLLs Driving DPA-enabled Differential I/Os
Right Corner PLL
Reference CLK
DPA-enabled Diff I/O
DPA-enabled Diff I/O
Right I/O Bank
Diff I/O
DPA-enabled Diff I/O
DPA-enabled Diff I/O
Center PLL
Center PLL
Unused PLLs
DPA-enabled Diff I/O
DPA-enabled Diff I/O
Left I/O Bank
DPA-enabled Diff I/O
Reference CLK
Left Corner PLL
DPA Restrictions
Because there is only a single DPA clock bus, a PLL drives a continuous series of DPA channels.
To prevent noise mixing, use one row of separation between two groups of DPA channels.
Guideline: Using DPA-Disabled Differential Channels
If you use DPA-disabled channels, adhere to the following guidelines.
DPA-Disabled Channel Driving Distance
Each PLL can drive all the DPA-disabled channels in the entire bank.
Using Corner and Center PLLs
You can use a corner PLL to drive all transmitter channels and a center PLL to drive all DPA-disabled receiver
channels in the same I/O bank. You can drive a transmitter channel and a receiver channel in the same LAB
row by two different PLLs. A corner PLL and a center PLL can drive duplex channels in the same I/O bank
if the channels that are driven by each PLL are not interleaved. You do not require separation between the
group of channels that are driven by the corner and center, left and right PLLs. Refer to the following figures.
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Guideline: Using DPA-Disabled Differential Channels
Figure 6-16: Corner and Center PLLs Driving DPA-Disabled Differential I/Os in the Same Bank
Corner PLL
Corner PLL
Reference CLK
Reference CLK
Diff RX
Diff TX
DPA-disabled Diff I/O
Diff RX
Diff TX
DPA-disabled Diff I/O
Diff RX
Diff TX
DPA-disabled Diff I/O
Diff RX
Diff TX
DPA-disabled Diff I/O
Diff RX
Diff TX
DPA-disabled Diff I/O
Diff RX
Diff TX
DPA-disabled Diff I/O
Diff RX
Diff TX
DPA-disabled Diff I/O
Diff RX
Diff TX
DPA-disabled Diff I/O
Diff RX
Diff TX
DPA-disabled Diff I/O
Diff RX
Diff TX
DPA-disabled Diff I/O
Reference CLK
Reference CLK
Center PLL
Center PLL
Channels Driven
by Corner PLL
No Separation
Buffer Needed
Channels Driven
by Center PLL
Figure 6-17: Invalid Placement of DPA-disabled Differential I/Os Due to Interleaving of Channels Driven by
the Corner and Center PLLs
Corner PLL
Reference CLK
DPA-disabled Diff I/O
DPA-disabled Diff I/O
DPA-disabled Diff I/O
DPA-disabled Diff I/O
DPA-disabled Diff I/O
DPA-disabled Diff I/O
DPA-disabled Diff I/O
DPA-disabled Diff I/O
DPA-disabled Diff I/O
DPA-disabled Diff I/O
Reference CLK
Center PLL
Using Both Center PLLs
You can use both center PLLs simultaneously to drive DPA-disabled channels on left and right I/O banks.
Unlike DPA-enabled channels, the center PLLs can drive DPA-disabled channels cross-banks in the Arria V
GX, GT, SX, and ST devices. For example, the left center PLL can drive the right I/O bank at the same time
the right center PLL is driving the left I/O bank, and vice versa, as shown in the following figure.
Note: In the Arria V GZ devices, the center PLLs cannot drive DPA-disabled channels cross-banks.
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Differential Transmitter in Arria V Devices
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Figure 6-18: Both Center PLLs Driving Cross-Bank DPA-Disabled Channels Simultaneously in Arria V GX, GT,
SX, and ST Devices
DPA-disabled Diff I/O
DPA-disabled Diff I/O
DPA-disabled Diff I/O
DPA-disabled Diff I/O
Reference CLK
Center PLL
Center PLL
Reference CLK
DPA-disabled Diff I/O
DPA-disabled Diff I/O
DPA-disabled Diff I/O
DPA-disabled Diff I/O
Using Both Corner PLLs
You can use both corner PLLs to drive DPA-disabled channels simultaneously. You can use a corner PLL
to drive all the transmitter channels and the other corner PLL to drive all the DPA-disabled receiver channels
in the same I/O bank. Both corner PLLs can drive duplex channels in the same I/O bank if the channels that
are driven by each PLL are not interleaved. You do not require separation between the groups of channels
that are driven by both corner PLLs.
Differential Transmitter in Arria V Devices
The Arria V transmitter contains dedicated circuitry to support high-speed differential signaling. The
differential transmitter buffers support the following features:
• LVDS signaling that can drive out LVDS, mini-LVDS, and RSDS signals
• Programmable VOD and programmable pre-emphasis
Transmitter Blocks
The dedicated circuitry consists of a true differential buffer, a serializer, and fractional PLLs that you can
share between the transmitter and receiver. The serializer takes up to 10 bits wide parallel data from the
FPGA fabric, clocks it into the load registers, and serializes it using shift registers that are clocked by the
fractional PLL before sending the data to the differential buffer. The MSB of the parallel data is transmitted
first.
Note: To drive the LVDS channels, you must use the PLLs in integer PLL mode.
The following figure shows a block diagram of the transmitter. In SDR and DDR modes, the data width is
1 and 2 bits, respectively.
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Transmitter Clocking
Figure 6-19: LVDS Transmitter
2
FPGA
Fabric
10 bits
maximum
data width
tx_in
Serializer
10
IOE
IOE supports SDR, DDR, or non-registered datapath
+
–
DIN DOUT
tx_out
LVDS Transmitter
tx_coreclock
3
(LVDS_LOAD_EN, diffioclk, tx_coreclock)
Fractional PLL
LVDS Clock Domain
tx_inclock
Related Information
Guideline: Use PLLs in Integer PLL Mode for LVDS on page 6-7
Transmitter Clocking
The fractional PLL generates the load enable (LVDS_LOAD_EN) signal and the diffioclk signal (the clock
running at serial data rate) that clocks the load and shift registers. You can statically set the serialization
factor to x3, x4, x5, x6, x7, x8, x9, or x10 using the Quartus II software. The load enable signal is derived
from the serialization factor setting.
You can configure any Arria V transmitter data channel to generate a source-synchronous transmitter clock
output. This flexibility allows the placement of the output clock near the data outputs to simplify board
layout and reduce clock-to-data skew.
Different applications often require specific clock-to-data alignments or specific data-rate-to-clock-rate
factors. You can specify these settings statically in the Quartus II MegaWizard Plug-In Manager:
• The transmitter can output a clock signal at the same rate as the data—with a maximum output clock
frequency that each speed grade of the device supports.
• You can divide the output clock by a factor of 1, 2, 4, 6, 8, or 10, depending on the serialization factor.
• You can set the phase of the clock in relation to the data using internal PLL option of the ALTLVDS
megafunction. The fractional PLLs provide additional support for other phase shifts in 45° increments.
The following figure shows the transmitter in clock output mode. In clock output mode, you can use an
LVDS channel as a clock output channel.
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Serializer Bypass for DDR and SDR Operations
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Figure 6-20: Transmitter in Clock Output Mode
Transmitter Circuit
Parallel
Series
Txclkout+
Txclkout–
FPGA
Fabric
diffioclk
Fractional
PLL
LVDS_LOAD_EN
Related Information
Guideline: Use PLLs in Integer PLL Mode for LVDS on page 6-7
Serializer Bypass for DDR and SDR Operations
You can bypass the serializer to support DDR (x2) and SDR (x1) operations to achieve a serialization factor
of 2 and 1, respectively. The I/O element (IOE) contains two data output registers that can each operate in
either DDR or SDR mode.
Figure 6-21: Serializer Bypass
This figure shows the serializer bypass path. In DDR mode, tx_inclock clocks the IOE register. In SDR
mode, data is passed directly through the IOE. In SDR and DDR modes, the data width to the IOE is 1 and
2 bits, respectively.
2
FPGA
Fabric
tx_in
Serializer
2
IOE
IOE supports SDR, DDR, or non-registered datapath
+
–
DIN DOUT
tx_out
LVDS Transmitter
tx_coreclock
3
(LVDS_LOAD_EN, diffioclk, tx_coreclock)
Fractional PLL
Note: Disabled blocks and signals are grayed out
Programmable Differential Output Voltage
The programmable VOD settings allow you to adjust the output eye opening to optimize the trace length
and power consumption. A higher VOD swing improves voltage margins at the receiver end, and a smaller
VOD swing reduces power consumption. You can statically adjust the VOD of the differential signal by
changing the VOD settings in the Quartus II software Assignment Editor.
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Programmable Pre-Emphasis
Figure 6-22: Differential VOD
This figure shows the VOD of the differential LVDS output.
Single-Ended Waveform
Positive Channel (p)
VOD
Negative Channel (n)
VCM
Ground
Differential Waveform
VOD (diff peak - peak) = 2 x VOD (single-ended)
VOD
p-n=0V
VOD
Table 6-9: Quartus II Software Assignment Editor—Programmable VOD
This table lists the assignment name for programmable VOD and its possible values in the Quartus II software
Assignment Editor.
Field
Assignment (Default setting in bold)
To
tx_out
Assignment name
Programmable Differential Output Voltage (VOD)
Allowed values
• Arria V GX, GT, SX, and ST—0 (low), 1 (medium)
, 2 (high)
• Arria V GZ—0 (low), 1 (medium low), 2 (medium
high), 3 (high)
Related Information
Programmable IOE Features in Arria V Devices on page 5-23
Programmable Pre-Emphasis
The VOD setting and the output impedance of the driver set the output current limit of a high-speed
transmission signal. At a high frequency, the slew rate may not be fast enough to reach the full VOD level
before the next edge, producing pattern-dependent jitter. With pre-emphasis, the output current is boosted
momentarily during switching to increase the output slew rate.
Pre-emphasis increases the amplitude of the high-frequency component of the output signal, and thus helps
to compensate for the frequency-dependent attenuation along the transmission line. The overshoot introduced
by the extra current happens only during a change of state switching to increase the output slew rate and
does not ring, unlike the overshoot caused by signal reflection. The amount of pre-emphasis required depends
on the attenuation of the high-frequency component along the transmission line.
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Figure 6-23: Programmable Pre-Emphasis
This figure shows the LVDS output with pre-emphasis.
Voltage boost
from pre-emphasis
OUT
VP
VOD
OUT
VP
Differential output
voltage (peak–peak)
Table 6-10: Quartus II Software Assignment Editor—Programmable Pre-Emphasis
This table lists the assignment name for programmable pre-emphasis and its possible values in the Quartus II software
Assignment Editor.
Field
Assignment (Default setting in bold)
To
tx_out
Assignment name
Programmable Pre-emphasis
Allowed values
0 (disabled) and 1 (enabled)
Related Information
Programmable IOE Features in Arria V Devices on page 5-23
Differential Receiver in Arria V Devices
The receiver has a differential buffer and fractional PLLs that you can share among the transmitter and
receiver, a DPA block, a synchronizer, a data realignment block, and a deserializer. The differential buffer
can receive LVDS, mini-LVDS, and RSDS signal levels. You can statically set the I/O standard of the receiver
pins to LVDS, mini-LVDS, or RSDS in the Quartus II software Assignment Editor.
Note: To drive the LVDS channels, you must use the PLLs in integer PLL mode.
Related Information
Guideline: Use PLLs in Integer PLL Mode for LVDS on page 6-7
Receiver Blocks in Arria V Devices
The Arria V differential receiver has the following hardware blocks:
•
•
•
•
DPA block
Synchronizer
Data realignment block (bit slip)
Deserializer
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DPA Block
The following figure shows the hardware blocks of the receiver. In SDR and DDR modes, the data width
from the IOE is 1 and 2 bits, respectively. The deserializer includes shift registers and parallel load registers,
and sends a maximum of 10 bits to the internal logic.
Figure 6-24: Receiver Block Diagram
10 bits
maximum
data width
rx_out
IOE supports SDR, DDR, or non-registered datapath
2
LVDS Receiver
IOE
10
Deserializer
Bit Slip
Synchronizer
+
–
rx_in
DPA Circuitry
10
DOUT
DIN
DOUT
Retimed
Data
DIN
DIN
DOUT
FPGA
Fabric
DIN
rx_divfwdclk
rx_outclock
DPA_diffioclk
diffioclk
2
(LOAD_EN,
diffioclk)
Clock Mux
LVDS_diffioclk
DPA Clock
3
(DPA_LOAD_EN,
DPA_diffioclk, rx_divfwdclk)
3 (LVDS_LOAD_EN,
LVDS_diffioclk, rx_outclock)
DPA Clock Domain
LVDS Clock Domain
Fractional PLL
8 Serial LVDS
Clock Phases
rx_inclock
DPA Block
The DPA block takes in high-speed serial data from the differential input buffer and selects one of the eight
phases that the fractional PLLs generate to sample the data. The DPA chooses a phase closest to the phase
of the serial data. The maximum phase offset between the received data and the selected phase is 1/8 UI,
which is the maximum quantization error of the DPA. The eight phases of the clock are equally divided,
offering a 45° resolution.
The following figure shows the possible phase relationships between the DPA clocks and the incoming serial
data.
Figure 6-25: DPA Clock Phase to Serial Data Timing Relationship
rx_in
D0
D1
D2
D3
D4
Dn
0°
45°
90°
135°
180°
225°
270°
315°
Tvco
0.125Tvco
Altera Corporation
TVCO = PLL serial clock period
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Synchronizer
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The DPA block continuously monitors the phase of the incoming serial data and selects a new clock phase
if it is required. You can prevent the DPA from selecting a new clock phase by asserting the optional
RX_DPLL_HOLD port, which is available for each channel.
DPA circuitry does not require a fixed training pattern to lock to the optimum phase out of the eight phases.
After reset or power up, the DPA circuitry requires transitions on the received data to lock to the optimum
phase. An optional output port, RX_DPA_LOCKED, is available to indicate an initial DPA lock condition to the
optimum phase after power up or reset. This signal is not deasserted if the DPA selects a new phase out of
the eight clock phases to sample the received data. Do not use the rx_dpa_locked signal to determine a
DPA loss-of-lock condition. Use data checkers such as a cyclic redundancy check (CRC) or diagonal
interleaved parity (DIP-4) to validate the data.
An independent reset port, RX_RESET, is available to reset the DPA circuitry. You must retrain the DPA
circuitry after reset.
Note: The DPA block is bypassed in non-DPA mode.
Related Information
Guideline: Use PLLs in Integer PLL Mode for LVDS on page 6-7
Synchronizer
The synchronizer is a 1 bit wide and 6 bit deep FIFO buffer that compensates for the phase difference between
DPA_diffioclk—the optimal clock that the DPA block selects—and the LVDS_diffioclk that the fractional
PLLs produce. The synchronizer can only compensate for phase differences, not frequency differences,
between the data and the receiver’s input reference clock.
An optional port, RX_FIFO_RESET, is available to the internal logic to reset the synchronizer. The synchronizer
is automatically reset when the DPA first locks to the incoming data. Altera recommends using RX_FIFO_RESET
to reset the synchronizer when the data checker indicates that the received data is corrupted.
Note: The synchronizer circuit is bypassed in non-DPA and soft-CDR mode.
Related Information
Guideline: Use PLLs in Integer PLL Mode for LVDS on page 6-7
Data Realignment Block (Bit Slip)
Skew in the transmitted data along with skew added by the link causes channel-to-channel skew on the
received serial data streams. If you enable the DPA, the received data is captured with different clock phases
on each channel. This difference may cause misalignment of the received data from channel to channel. To
compensate for this channel-to-channel skew and establish the correct received word boundary at each
channel, each receiver channel has a dedicated data realignment circuit that realigns the data by inserting
bit latencies into the serial stream.
An optional RX_CHANNEL_DATA_ALIGN port controls the bit insertion of each receiver independently controlled
from the internal logic. The data slips one bit on the rising edge of RX_CHANNEL_DATA_ALIGN. The requirements
for the RX_CHANNEL_DATA_ALIGN signal include the following items:
• The minimum pulse width is one period of the parallel clock in the logic array.
• The minimum low time between pulses is one period of the parallel clock.
• The signal is an edge-triggered signal.
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Deserializer
• The valid data is available two parallel clock cycles after the rising edge of RX_CHANNEL_DATA_ALIGN.
Figure 6-26: Data Realignment Timing
This figure shows receiver output (RX_OUT) after one bit slip pulse with the deserialization factor set to 4.
rx_inclock
rx_in
3
2
1
0
3
2
1
0
3
2
1
0
rx_outclock
rx_channel_data_align
rx_out
3210
321x
xx21
0321
The data realignment circuit can have up to 11 bit-times of insertion before a rollover occurs. The
programmable bit rollover point can be from 1 to 11 bit-times, independent of the deserialization factor.
Set the programmable bit rollover point equal to, or greater than, the deserialization factor—allowing enough
depth in the word alignment circuit to slip through a full word. You can set the value of the bit rollover point
using the MegaWizard Plug-In Manager. An optional status port, RX_CDA_MAX, is available to the FPGA
fabric from each channel to indicate the reaching of the preset rollover point.
Figure 6-27: Receiver Data Realignment Rollover
This figure shows a preset value of four bit-times before rollover occurs. The rx_cda_max signal pulses for
one rx_outclock cycle to indicate that rollover has occurred.
rx_inclock
rx_channel_data_align
rx_outclock
rx_cda_max
Deserializer
You can statically set the deserialization factor to x3, x4, x5, x6, x7, x8, x9, or x10 by using the Quartus II
software. You can bypass the deserializer in the Quartus II MegaWizard Plug-In Manager to support DDR
(x2) or SDR (x1) operations, as shown in the following figure.
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Figure 6-28: Deserializer Bypass
rx_out
IOE supports SDR, DDR, or non-registered datapath
2
LVDS Receiver
IOE
2
Deserializer
Bit Slip
Synchronizer
+
–
rx_in
DPA Circuitry
10
DOUT
DIN
DOUT
Retimed
Data
DIN
DOUT
FPGA
Fabric
DIN
DIN
diffioclk
rx_divfwdclk
rx_outclock
DPA_diffioclk
2
(LOAD_EN,
diffioclk)
Clock Mux
LVDS_diffioclk
DPA Clock
3
(DPA_LOAD_EN,
DPA_diffioclk, rx_divfwdclk)
3 (LVDS_LOAD_EN,
LVDS_diffioclk, rx_outclock)
Fractional PLL
8 Serial LVDS
Clock Phases
Note: Disabled blocks and signals are grayed out
The IOE contains two data input registers that can operate in DDR or SDR mode. In DDR mode, rx_inclock
clocks the IOE register. In SDR mode, data is directly passed through the IOE. In SDR and DDR modes, the
data width from the IOE is 1 and 2 bits, respectively.
You cannot use the DPA and data realignment circuit when you bypass the deserializer.
Receiver Modes in Arria V Devices
The Arria V devices support the following receiver modes:
• Non-DPA mode
• DPA mode
• Soft-CDR mode
Non-DPA Mode
The non-DPA mode disables the DPA and synchronizer blocks. Input serial data is registered at the rising
edge of the serial LVDS_diffioclk clock that is produced by the left and right PLLs.
You can select the rising edge option with the Quartus II MegaWizard Plug-In Manager. The LVDS_diffioclk
clock that is generated by the left and right PLLs clocks the data realignment and deserializer blocks.
The following figure shows the non-DPA datapath block diagram. In SDR and DDR modes, the data width
from the IOE is 1 and 2 bits, respectively.
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DPA Mode
Figure 6-29: Receiver Data Path in Non-DPA Mode
10 bits
maximum
data width
rx_out
IOE supports SDR, DDR, or non-registered datapath
2
LVDS Receiver
IOE
10
Deserializer
Bit Slip
Synchronizer
+
–
rx_in
DPA Circuitry
10
DOUT
DIN
DOUT
Retimed
Data
DIN
DIN
DOUT
FPGA
Fabric
DIN
rx_divfwdclk
rx_outclock
DPA_diffioclk
diffioclk
2
(LOAD_EN,
diffioclk)
Clock Mux
LVDS_diffioclk
DPA Clock
3
(DPA_LOAD_EN,
DPA_diffioclk, rx_divfwdclk)
3 (LVDS_LOAD_EN,
LVDS_diffioclk, rx_outclock)
Fractional PLL
LVDS Clock Domain
8 Serial LVDS
Clock Phases
rx_inclock
Note: All disabled blocks and signals are grayed out
DPA Mode
The DPA block chooses the best possible clock (DPA_diffioclk) from the eight fast clocks that the fractional
PLL sent. This serial DPA_diffioclk clock is used for writing the serial data into the synchronizer. A serial
LVDS_diffioclk clock is used for reading the serial data from the synchronizer. The same LVDS_diffioclk
clock is used in data realignment and deserializer blocks.
The following figure shows the DPA mode datapath. In the figure, all the receiver hardware blocks are active.
Figure 6-30: Receiver Datapath in DPA Mode
In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
10 bits
maximum
data width
rx_out
IOE supports SDR, DDR, or non-registered datapath
2
LVDS Receiver
IOE
10
Deserializer
Bit Slip
Synchronizer
+
–
rx_in
DPA Circuitry
10
DOUT
DIN
DOUT
Retimed
Data
DIN
DIN
DOUT
FPGA
Fabric
DIN
diffioclk
rx_divfwdclk
rx_outclock
DPA_diffioclk
2
(LOAD_EN,
diffioclk)
Clock Mux
LVDS_diffioclk
DPA Clock
3
(DPA_LOAD_EN,
DPA_diffioclk, rx_divfwdclk)
3 (LVDS_LOAD_EN,
LVDS_diffioclk, rx_outclock)
DPA Clock Domain
LVDS Clock Domain
Fractional PLL
8 Serial LVDS
Clock Phases
rx_inclock
Note: All disabled blocks and signals are grayed out
Related Information
• Guideline: Use PLLs in Integer PLL Mode for LVDS on page 6-7
• Receiver Blocks in Arria V Devices on page 6-21
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Soft-CDR Mode
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Soft-CDR Mode
The Arria V LVDS channel offers the soft-CDR mode to support the GbE and SGMII protocols. A receiver
PLL uses the local clock source for reference.
The following figure shows the soft-CDR mode datapath. In SDR and DDR modes, the data width from the
IOE is 1 and 2 bits, respectively.
Figure 6-31: Receiver Datapath in Soft-CDR Mode
10 bits
maximum
data width
rx_out
IOE supports SDR, DDR, or non-registered datapath
2
LVDS Receiver
IOE
10
Deserializer
Bit Slip
Synchronizer
+
–
rx_in
DPA Circuitry
10
DOUT
DIN
DOUT
Retimed
Data
DIN
DIN
DOUT
FPGA
Fabric
DIN
rx_divfwdclk
rx_outclock
DPA_diffioclk
diffioclk
2
(LOAD_EN,
diffioclk)
Clock Mux
LVDS_diffioclk
DPA Clock
3
(DPA_LOAD_EN,
DPA_diffioclk, rx_divfwdclk)
3 (LVDS_LOAD_EN,
LVDS_diffioclk, rx_outclock)
DPA Clock Domain
LVDS Clock Domain
Fractional PLL
8 Serial LVDS
Clock Phases
rx_inclock
Note: All disabled blocks and signals are grayed out
In soft-CDR mode, the synchronizer block is inactive. The DPA circuitry selects an optimal DPA clock phase
to sample the data. Use the selected DPA clock for bit-slip operation and deserialization. The DPA block
also forwards the selected DPA clock, divided by the deserialization factor called rx_divfwdclk, to the FPGA
fabric, along with the deserialized data. This clock signal is put on the periphery clock (PCLK) network.
If you use the soft-CDR mode, do not assert the rx_reset port after the DPA has trained. The DPA
continuously chooses new phase taps from the PLL to track parts per million (PPM) differences between
the reference clock and incoming data.
You can use every LVDS channel in soft-CDR mode and drive the FPGA fabric using the PCLK network in
the Arria V device family. The rx_dpa_locked signal is not valid in soft-CDR mode because the DPA
continuously changes its phase to track PPM differences between the upstream transmitter and the local
receiver input reference clocks. The parallel clock, rx_outclock, generated by the left and right PLLs, is also
forwarded to the FPGA fabric.
Related Information
Periphery Clock Networks on page 4-4
Provides more information about PCLK networks.
Receiver Clocking for Arria V Devices
The fractional PLL receives the external clock input and generates different phases of the same clock. The
DPA block automatically chooses one of the clocks from the fractional PLL and aligns the incoming data
on each channel.
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Differential I/O Termination for Arria V Devices
The synchronizer circuit is a 1 bit wide by 6 bit deep FIFO buffer that compensates for any phase difference
between the DPA clock and the data realignment block. If necessary, the user-controlled data realignment
circuitry inserts a single bit of latency in the serial bit stream to align to the word boundary.
The physical medium connecting the transmitter and receiver LVDS channels may introduce skew between
the serial data and the source-synchronous clock. The instantaneous skew between each LVDS channel and
the clock also varies with the jitter on the data and clock signals as seen by the receiver. The three different
modes—non-DPA, DPA, and soft-CDR—provide different options to overcome skew between the source
synchronous clock (non-DPA, DPA) /reference clock (soft-CDR) and the serial data.
Non-DPA mode allows you to statically select the optimal phase between the source synchronous clock and
the received serial data to compensate skew. In DPA mode, the DPA circuitry automatically chooses the
best phase to compensate for the skew between the source synchronous clock and the received serial data.
Soft-CDR mode provides opportunities for synchronous and asynchronous applications for chip-to-chip
and short reach board-to-board applications for SGMII protocols.
Note: Only the non-DPA mode requires manual skew adjustment.
Related Information
Guideline: Use PLLs in Integer PLL Mode for LVDS on page 6-7
Differential I/O Termination for Arria V Devices
The Arria V devices provide a 100 Ω, on-chip differential termination option on each differential receiver
channel for LVDS standards. On-chip termination saves board space by eliminating the need to add external
resistors on the board. You can enable on-chip termination in the Quartus II software Assignment Editor.
All I/O pins and dedicated clock input pins support on-chip differential termination, RD OCT.
Figure 6-32: On-Chip Differential I/O Termination
Differential Receiver
with On-Chip 100 Ω
Termination
LVDS
Transmitter
Z0 = 50 Ω
RD
Z0 = 50 Ω
Table 6-11: Quartus II Software Assignment Editor—On-Chip Differential Termination
This table lists the assignment name for on-chip differential termination in the Quartus II software Assignment
Editor.
Field
Assignment
To
rx_in
Assignment name
Input Termination
Value
Differential
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Source-Synchronous Timing Budget
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Source-Synchronous Timing Budget
The topics in this section describe the timing budget, waveforms, and specifications for source-synchronous
signaling in the Arria V device family.
The LVDS I/O standard enables high-speed transmission of data, resulting in better overall system
performance. To take advantage of fast system performance, you must analyze the timing for these highspeed signals. Timing analysis for the differential block is different from traditional synchronous timing
analysis techniques.
The basis of the source synchronous timing analysis is the skew between the data and the clock signals instead
of the clock-to-output setup times. High-speed differential data transmission requires the use of timing
parameters provided by IC vendors and is strongly influenced by board skew, cable skew, and clock jitter.
This section defines the source-synchronous differential data orientation timing parameters, the timing
budget definitions for the Arria V device family, and how to use these timing parameters to determine the
maximum performance of a design.
Differential Data Orientation
There is a set relationship between an external clock and the incoming data. For operations at 1 Gbps and
a serialization factor of 10, the external clock is multiplied by 10. You can set phase-alignment in the PLL
to coincide with the sampling window of each data bit. The data is sampled on the falling edge of the multiplied
clock.
Figure 6-33: Bit Orientation in the Quartus II Software
This figure shows the data bit orientation of the x10 mode.
incloc k/outcloc k
data in
MSB
9
10 LVDS Bits
8
7
6
5
4
3
2
1
LSB
0
Differential I/O Bit Position
Data synchronization is necessary for successful data transmission at high frequencies.
The following figure shows the data bit orientation for a channel operation and is based on the following
conditions:
• The serialization factor is equal to the clock multiplication factor.
• The phase alignment uses edge alignment.
• The operation is implemented in hard SERDES.
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Differential Bit Naming Conventions
Figure 6-34: Bit-Order and Word Boundary for One Differential Channel
Transmitter Channel Operation (x8 Mode)
tx_outclock
tx_out
X
X X
Previous Cycle
X X X X
7 6
MSB
X
Current Cycle
5 4 3 2
1
X
X
0
LSB
Next Cycle
X X X X X
X
X
X
Receiver Channel Operation (x8 Mode)
rx_inclock
rx_in
7
6
5
4
3
2
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
rx_outclock
rx_out [7..0]
XXXXXXXX
XXXXXXXX
XXXX7654
3210XXXX
Note: These waveforms are only functional waveforms and do not convey timing information
For other serialization factors, use the Quartus II software tools to find the bit position within the word.
Differential Bit Naming Conventions
The following table lists the conventions for differential bit naming for 18 differential channels. The MSB
and LSB positions increase with the number of channels used in a system.
Table 6-12: Differential Bit Naming
This table lists the conventions for differential bit naming for 18 differential channels. The MSB and LSB positions
increase with the number of channels used in a system.
Receiver Channel Data Number
Altera Corporation
Internal 8-Bit Parallel Data
MSB Position
LSB Position
1
7
0
2
15
8
3
23
16
4
31
24
5
39
32
6
47
40
7
55
48
8
63
56
9
71
64
10
79
72
11
87
80
12
95
88
13
103
96
14
111
104
15
119
112
16
127
120
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Transmitter Channel-to-Channel Skew
Receiver Channel Data Number
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Internal 8-Bit Parallel Data
MSB Position
LSB Position
17
135
128
18
143
136
Transmitter Channel-to-Channel Skew
The receiver skew margin calculation uses the transmitter channel-to-channel skew (TCCS)—an important
parameter based on the Arria V transmitter in a source-synchronous differential interface:
• TCCS is the difference between the fastest and slowest data output transitions, including the TCO variation
and clock skew.
• For LVDS transmitters, the TimeQuest Timing Analyzer provides the TCCS value in the TCCS report
(report_TCCS) in the Quartus II compilation report, which shows TCCS values for serial output ports.
• You can also get the TCCS value from the device datasheet.
Note: For the Arria V GZ devices, perform PCB trace compensation to adjust the trace length of each LVDS
channel to improve channel-to-channel skew when interfacing with non-DPA receivers at data rate
above 840 Mbps.
The Quartus II software Fitter Report panel reports the amount of delay you must add to each trace for the
Arria V device. You can use the recommended trace delay numbers published under the LVDS
Transmitter/Receiver Package Skew Compensation panel and manually compensate the skew on the PCB
board trace to reduce channel-to-channel skew, thus meeting the timing budget between LVDS channels.
Related Information
• Arria V Device Datasheet
• LVDS SERDES Transmitter/Receiver (ALTLVDS_TX and ALTLVDS_RX) Megafunction User Guide
More information about the LVDS Transmitter/Receiver Package Skew Compensation report panel.
Receiver Skew Margin for Non-DPA Mode
Different modes of LVDS receivers use different specifications, which can help in deciding the ability to
sample the received serial data correctly:
• In DPA mode, use DPA jitter tolerance instead of the receiver skew margin (RSKM).
• In non-DPA mode, use RSKM, TCCS, and sampling window (SW) specifications for high-speed sourcesynchronous differential signals in the receiver data path.
The following equation expresses the relationship between RSKM, TCCS, and SW.
Figure 6-35: RSKM Equation
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Receiver Skew Margin for Non-DPA Mode
Conventions used for the equation:
• RSKM—the timing margin between the receiver’s clock input and the data input sampling window.
• Time unit interval (TUI)—time period of the serial data.
• SW—the period of time that the input data must be stable to ensure that data is successfully sampled by
the LVDS receiver. The SW is a device property and varies with device speed grade.
• TCCS—the timing difference between the fastest and the slowest output edges, including tCO variation
and clock skew, across channels driven by the same PLL. The clock is included in the TCCS measurement.
You must calculate the RSKM value to decide whether the LVDS receiver can sample the data properly or
not, given the data rate and device. A positive RSKM value indicates that the LVDS receiver can sample the
data properly, whereas a negative RSKM indicates that it cannot sample the data properly.
The following figure shows the relationship between the RSKM, TCCS, and the SW of the receiver.
Figure 6-36: Differential High-Speed Timing Diagram and Timing Budget for Non-DPA Mode
Timing Diagram
External
Input Clock
Time Unit Interval (TUI)
Internal
Clock
TCCS
Receiver
Input Data
TCCS
RSKM
SW
tSW (min)
Bit n
Timing Budget
Internal
Clock
Falling Edge
RSKM
tSW (max)
Bit n
TUI
External
Clock
Clock Placement
Internal
Clock
Synchronization
Transmitter
Output Data
TCCS
RSKM
RSKM
TCCS
2
Receiver
Input Data
SW
For LVDS receivers, the Quartus II software provides an RSKM report showing the SW, TUI, and RSKM
values for non-DPA LVDS mode:
• You can generate the RSKM report by executing the report_RSKM command in the TimeQuest Timing
Analyzer. You can find the RSKM report in the Quartus II compilation report in the TimeQuest Timing
Analyzer section.
• To obtain the RSKM value, assign the input delay to the LVDS receiver through the constraints menu of
the TimeQuest Timing Analyzer. The input delay is determined according to the data arrival time at the
LVDS receiver port, with respect to the reference clock.
• If you set the input delay in the settings parameters for the Set Input Delay option, set the clock name
to the clock that reference the source synchronous clock that feeds the LVDS receiver.
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Assigning Input Delay to LVDS Receiver Using TimeQuest Timing Analyzer
6-33
• If you do not set any input delay in the TimeQuest Timing Analyzer, the receiver channel-to-channel
skew defaults to zero.
• You can also directly set the input delay in a Synopsys Design Constraint file (.sdc) using the
set_input_delay command.
Related Information
• LVDS SERDES Transmitter/Receiver (ALTLVDS_TX and ALTLVDS_RX) Megafunction User Guide
More information about the RSKM equation and calculation.
• Quartus II TimeQuest Timing Analyzer chapter, Quartus II Development Software Handbook
Provides more information about .sdc commands and the TimeQuest Timing Analyzer.
Assigning Input Delay to LVDS Receiver Using TimeQuest Timing Analyzer
To obtain the RSKM value, assign an appropriate input delay to the LVDS receiver from the TimeQuest
Timing Analyzer constraints menu.
1. On the menu in the TimeQuest Timing Analyzer, select Constraints > Set Input Delay.
2. In the Set Input Delay window, select the desired clock using the pull-down menu. The clock name must
reference the source synchronous clock that feeds the LVDS receiver.
3. Click the Browse button (next to the Targets field).
4. In the Name Finder window, click List to view a list of all available ports. Select the LVDS receiver serial
input ports according to the input delay you set, and click OK.
5. In the Set Input Delay window, set the appropriate values in the Input delay options and Delay value
fields.
6. Click Run to incorporate these values in the TimeQuest Timing Analyzer.
7. Repeat from step 1 to assign the appropriate delay for all the LVDS receiver input ports. If you have
already assigned Input Delay and you need to add more delay to that input port, turn on the Add Delay
option.
Document Revision History
Date
Version
January 2014
2014.01.10
Changes
• Updated the statement about setting the phase of the clock in relation
to data in the topic about transmitter clocking.
• Added a figure that shows the phase relationship for the external PLL
interface signals.
• Clarified that "one row of separation" between two groups of DPAenabled channels means a separation of one differential channel.
• Clarified that "internal PLL option" refers to the option in the ALTLVDS
megafunction.
• Updated the topic about emulated LVDS buffers to clarify that you can
use unutilized true LVDS input channels (instead "buffers") as emulated
LVDS output buffers.
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Document Revision History
Date
Version
August 2013
2013.08.19
Updated the number of LVDS channels of the Arria V GZ E5 and E7 devices
(1517-pin package) from 80 to 79 (top banks TX) and 82 to 81 (top banks
RX).
June 2013
2013.06.21
Updated the figure about data realignment timing to correct the data pattern
after a bit slip.
May 2013
2013.05.06
• Moved all links to the Related Information section of respective topics
for easy reference.
• Added link to the known document issues in the Knowledge Base.
• Clarified that the clock tree network cannot cross over to different I/O
regions only applies to Arria V GZ.
• Added a figure to show the center PLLs driving the DPA-enabled
differential I/Os in Arria V GZ devices.
• Changed the color of the transceiver blocks in the high-speed differential
I/O location diagrams for clarity.
• Reorganized contents under the differential receiver topic.
• Added a topic about emulated LVDS buffers.
• Edited the topic about true LVDS buffers.
• Corrected references to upper and lower I/O banks to left and right I/
O banks, respectively.
• Updated the data realignment timing figure to improve clarity.
• Updated the receiver data realignment rollover figure to improve clarity.
November 2012
2012.11.19
• Reorganized content and updated template.
• Added Arria V GZ information.
• Added Altera_PLL settings for external PLL usage in DPA and nonDPA modes.
• Updated clocking examples. Altera_PLL now supports entering negative
phase shift.
• Rearranged the LVDS channel counts table into several tables according
to device variant for ease of reference.
• Updated the Arria V GX A1 and A3 LVDS channel counts, and added
the channel counts for Arria V GZ.
• Removed references to ALTPLL and added information about Altera_
PLL. Altera_PLL now replaces ALTPLL for Arria V devices.
• Added design guidelines for using LVDS interface with the external
PLL mode. These include information on the signal interfaces, the
parameter values, and the connection between Altera_PLL and
ALTLVDS in external PLL mode.
• Updated the programmable VOD allowed values for Arria V GX, GT,
SX, and ST, and added the values for Arria V GZ.
• Moved the PLL and clocking section into design guideline topics.
• Added steps to assign input delay to LVDS receiver using the TimeQuest
Timing Analyzer.
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Document Revision History
Date
Version
Changes
June 2012
2.0
•
•
•
•
•
•
November 2011
1.1
• Updated Table 6–1.
• Restructured chapter.
May 2011
1.0
Initial release.
Restructured the chapter.
Updated Table 6–1.
Updated Figure 6–1 and Figure 6–2.
Added Figure 6–3.
Added “Design Considerations” section.
Updated the “Differential Pin Placement” section.
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External Memory Interfaces in Arria V Devices
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Subscribe
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The Arria V devices provide an efficient architecture that allows you to fit wide external memory interfaces
to support a high level of system bandwidth within the small modular I/O bank structure. The I/Os are
designed to provide high-performance support for existing and emerging external memory standards.
Table 7-1: Supported External Memory Standards in Arria V Devices
Memory Standard
Hard Memory
Controller
Soft Memory Controller
Arria V GX, GT, SX, and Arria V GX, GT, SX, and
ST
ST
Arria V GZ
DDR3 SDRAM
Full rate
Half rate and quarter
rate
Half rate and quarter rate
DDR2 SDRAM
Full rate
Half rate
Full rate and half rate
LPDDR2 SDRAM
—
Half rate
—
RLDRAM 3
—
—
Half rate and quarter rate
RLDRAM II
—
Half rate
Full rate and half rate
QDR II+ SRAM
—
Half rate
Full rate and half rate
QDR II SRAM
—
Half rate
Full rate and half rate
Related Information
• External Memory Interface Spec Estimator
For the latest information and to estimate the external memory system performance specification, use
Altera's External Memory Interface Spec Estimator tool.
• External Memory Interface Handbook
Provides more information about the memory types supported, board design guidelines, timing analysis,
simulation, and debugging information.
• Arria V Device Handbook: Known Issues
Lists the planned updates to the Arria V Device Handbook chapters.
© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words
and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other
words and logos identified as trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with
Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes
no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
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External Memory Performance
External Memory Performance
Table 7-2: External Memory Interface Performance in Arria V Devices
Voltage
(V)
Interface
Hard Controller
(MHz)
Soft Controller (MHz)
Arria V GX, GT, SX,
and ST
Arria V GX, GT, SX,
and ST
Arria V GZ
1.5
533
667
800
1.35
533
600
800
DDR2 SDRAM
1.8
400
400
400
LPDDR2 SDRAM
1.2
—
400
—
RLDRAM 3
1.2
—
—
667
1.8
—
400
533
1.5
—
400
533
1.8
—
400
500
1.5
—
400
500
1.8
—
400
333
1.5
—
400
333
1.8
—
400
—
1.5
—
400
—
DDR3 SDRAM
RLDRAM II
QDR II+ SRAM
QDR II SRAM
DDR II+ SRAM(19)
Related Information
External Memory Interface Spec Estimator
For the latest information and to estimate the external memory system performance specification, use Altera's
External Memory Interface Spec Estimator tool.
HPS External Memory Performance
Table 7-3: HPS External Memory Interface Performance
The hard processor system (HPS) is available in Arria V SoC devices only.
Interface
DDR3 SDRAM
LPDDR2 SDRAM
(19)
Voltage (V)
HPS Hard Controller (MHz)
1.5
533
1.35
533
1.2
333
Not available as Altera® IP.
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Memory Interface Pin Support in Arria V Devices
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Related Information
External Memory Interface Spec Estimator
For the latest information and to estimate the external memory system performance specification, use Altera's
External Memory Interface Spec Estimator tool.
Memory Interface Pin Support in Arria V Devices
In the Arria V devices, the memory interface circuitry is available in every I/O bank that does not support
transceivers. The devices offer differential input buffers for differential read-data strobe and clock operations.
The memory clock pins are generated with double data rate input/output (DDRIO) registers.
Related Information
Planning Pin and FPGA Resources chapter, External Memory Interface Handbook
Provides more information about which pins to use for memory clock pins and pin location requirements.
Guideline: Using DQ/DQS Pins
The following list provides guidelines on using the DQ/DQS pins:
• The devices support DQ and DQS signals with DQ bus modes of x4/x8/x9, x16/x18, or x32/x36.
• You can use the DQSn or CQn pins that are not used for clocking as DQ pins.
• If you do not use the DQ/DQS pins for memory interfacing, you can use these pins as user I/Os. However,
unused HPS DQ/DQS pins on the Arria V SX and ST devices cannot be used as user I/Os.
• Some pins have multiple functions such as RZQ or DQ. If you need extra RZQ pins, you can use some
of the DQ pins as RZQ pins instead.
Note: For the x8, x16/x18, or x32/x36 DQ/DQS groups whose members are used as RZQ pins, Altera
recommends that you assign the DQ and DQS pins manually. Otherwise, the Quartus II software
might not be able to place the DQ and DQS pins, resulting in a “no-fit” error.
Reading the Pin Table
For the maximum number of DQ pins and the exact number per group for a particular Arria V device, refer
to the relevant device pin table.
In the pin tables, the DQS and DQSn pins denote the differential data strobe/clock pin pairs, while the CQ
and CQn pins denote the complementary echo clock signals. The pin table lists the parity, DM, BWSn,
NWSn, ECC, and QVLD pins as DQ pins.
Related Information
• Planning Pin and FPGA Resources chapter, External Memory Interface Handbook
Provides more information about read clock pins usage for QDR II and QDR II+ SRAM, and RLDRAM II
interfaces in Arria V GX, GT, SX, and ST devices
• Arria V Device Pin-Out Files
Download the relevant pin tables from this web page.
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DQ/DQS Bus Mode Pins for Arria V Devices
DQ/DQS Bus Mode Pins for Arria V Devices
The following tables list the pin support per DQ/DQS bus mode, including the DQS/CQ/CQn/QK# and
DQSn pins. The maximum number of data pins per group listed in the tables may vary according to the
following conditions:
• Single-ended DQS signaling—the maximum number of DQ pins includes parity, data mask, and QVLD
pins connected to the DQS bus network.
• Differential or complementary DQS signaling—the maximum number of data pins per group decreases
by one. This number may vary per DQ/DQS group in a particular device. Check the pin table for the
exact number per group.
• DDR3 and DDR2 interfaces—the maximum number of pins is further reduced for an interface larger
than x8 because you require one DQS pin for each x8/x9 group to form the x16/x18 and x32/x36 groups.
Table 7-4: DQ/DQS Bus Mode Pins for Arria V GX, GT, SX, and ST Devices
Mode
DQSn
Support
Parity or
Data Pins per Group
Data
(20)
Mask QVLD
CQn
Support (Optional) (Optional)
Typical
Maximum
Notes
x4/x8/x9
Yes
Yes
Yes
Yes
4, 8, or 9
11
The x4 mode uses x8/x9 groups.
x16/x18
Yes
Yes
Yes
Yes
16 or 18
23
Two x8 DQ/DQS groups are
stitched to create a x16/x18 group,
so there are 24 pins in this group.
x32/x36
Yes
Yes
Yes
Yes
32 or 36
47
Four x8 DQ/DQS groups are
stitched to create a x32/x36 group,
so there are 48 pins in this group.
Table 7-5: DQ/DQS Bus Mode Pins for Arria V GZ Devices
Mode
(20)
DQSn
Support
Parity or
Data Pins per Group
Data
(20)
Mask QVLD
CQn
Support (Optional) (Optional)
Typical
Maximum
Notes
x4
Yes
—
—
—
4
5
If you do not use differential DQS
and the group does not have
additional signals, the data mask
(DM) pin is supported.
x8/x9
Yes
Yes
Yes
Yes
8 or 9
11
Two x4 DQ/DQS groups are
stitched to create a x8/x9 group, so
there are a total of 12 pins in this
group.
x16/x18
Yes
Yes
Yes
Yes
16 or 18
23
Four x4 DQ/DQS groups are
stitched to create a x16/x18 group;
so there are a total of 24 pins in this
group.
The QVLD pin is not used in the UniPHY megafunction.
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DQ/DQS Groups in Arria V GX
Mode
DQSn
Support
x32/x36
Yes
Parity or
Data Pins per Group
Data
(20)
Mask QVLD
CQn
Support (Optional) (Optional)
Yes
Yes
Yes
Typical
Maximum
32 or 36
47
Notes
Eight x4 DQ/DQS groups are
stitched to create a x32/x36 group,
so there are a total of 48 pins in this
group.
DQ/DQS Groups in Arria V GX
Table 7-6: Number of DQ/DQS Groups Per Side in Arria V GX Devices
This table lists the DQ/DQS groups for the soft memory controller. For the hard memory controller, you can get the
DQ/DQS groups from the pin table of the specific device.
Member Code
Package
672-pin FineLine BGA, Flip Chip
A1
896-pin FineLine BGA, Flip Chip
672-pin FineLine BGA, Flip Chip
A3
896-pin FineLine BGA, Flip Chip
672-pin FineLine BGA, Flip Chip
A5
896-pin FineLine BGA, Flip Chip
1152-pin FineLine BGA, Flip Chip
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Side
x8/x9
x16/x18
x32/x36
Top
8
3
—
Bottom
8
3
—
Right
4
2
—
Top
10
3
—
Bottom
10
3
—
Right
6
2
—
Top
8
3
—
Bottom
8
3
—
Right
4
2
—
Top
10
3
—
Bottom
10
3
—
Right
6
2
—
Top
8
3
1
Bottom
8
3
1
Top
12
5
1
Bottom
12
5
1
Top
17
8
2
Bottom
17
8
2
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DQ/DQS Groups in Arria V GX
Member Code
Package
672-pin FineLine BGA, Flip Chip
A7
896-pin FineLine BGA, Flip Chip
1152-pin FineLine BGA, Flip Chip
896-pin FineLine BGA, Flip Chip
B1
1517-pin FineLine BGA, Flip Chip
1152-pin FineLine BGA, Flip Chip
896-pin FineLine BGA, Flip Chip
B3
1152-pin FineLine BGA, Flip Chip
1517-pin FineLine BGA, Flip Chip
1152-pin FineLine BGA, Flip Chip
B5
1517-pin FineLine BGA, Flip Chip
1152-pin FineLine BGA, Flip Chip
B7
1517-pin FineLine BGA, Flip Chip
Side
x8/x9
x16/x18
x32/x36
Top
8
3
1
Bottom
8
3
1
Top
12
5
1
Bottom
12
5
1
Top
17
8
2
Bottom
17
8
2
Top
12
5
1
Bottom
12
5
1
Top
22
10
4
Bottom
22
10
4
Top
17
8
2
Bottom
17
8
2
Top
12
5
1
Bottom
12
5
1
Top
17
8
2
Bottom
17
8
2
Top
22
10
4
Bottom
22
10
4
Top
17
8
2
Bottom
17
8
2
Top
22
10
4
Bottom
22
10
4
Top
17
8
2
Bottom
17
8
2
Top
22
10
4
Bottom
22
10
4
Related Information
Arria V Device Pin-Out Files
Download the relevant pin tables from this web page.
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DQ/DQS Groups in Arria V GT
DQ/DQS Groups in Arria V GT
Table 7-7: Number of DQ/DQS Groups Per Side in Arria V GT Devices
This table lists the DQ/DQS groups for the soft memory controller. For the hard memory controller, you can get the
DQ/DQS groups from the pin table of the specific device.
Member Code
Package
672-pin FineLine BGA, Flip Chip
C3
896-pin FineLine BGA, Flip Chip
896-pin FineLine BGA, Flip Chip
C7
1152-pin FineLine BGA, Flip Chip
896-pin FineLine BGA, Flip Chip
D3
1152-pin FineLine BGA, Flip Chip
1517-pin FineLine BGA, Flip Chip
1152-pin FineLine BGA, Flip Chip
D7
1517-pin FineLine BGA, Flip Chip
Side
x8/x9
x16/x18
x32/x36
Top
8
3
—
Bottom
8
3
—
Right
4
2
—
Top
10
3
—
Bottom
10
3
—
Right
6
2
—
Top
12
5
1
Bottom
12
5
1
Top
17
8
2
Bottom
17
8
2
Top
12
5
1
Bottom
12
5
1
Top
17
8
2
Bottom
17
8
2
Top
22
10
4
Bottom
22
10
4
Top
17
8
2
Bottom
17
8
2
Top
22
10
4
Bottom
22
10
4
Related Information
Arria V Device Pin-Out Files
Download the relevant pin tables from this web page.
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DQ/DQS Groups in Arria V GZ
DQ/DQS Groups in Arria V GZ
Table 7-8: Number of DQ/DQS Groups Per Side in Arria V GZ Devices
Member Code
Package
780-pin FineLine BGA, Flip Chip
E1
1152-pin FineLine BGA, Flip Chip
780-pin FineLine BGA, Flip Chip
E3
1152-pin FineLine BGA, Flip Chip
1152-pin FineLine BGA, Flip Chip
E5
1517-pin FineLine BGA, Flip Chip
1152-pin FineLine BGA, Flip Chip
E7
1517-pin FineLine BGA, Flip Chip
Side
x4
x8/x9
x16/x18
x32/x36
Top
28
13
6
2
Bottom
26
13
6
1
Top
32
15
7
2
Bottom
34
17
8
2
Top
28
13
6
2
Bottom
26
13
6
1
Top
32
15
7
2
Bottom
34
17
8
2
Top
36
17
8
3
Bottom
50
25
12
4
Top
52
26
12
6
Bottom
58
29
14
6
Top
36
17
8
3
Bottom
50
25
12
4
Top
52
26
12
6
Bottom
58
29
14
6
DQ/DQS Groups in Arria V SX
Table 7-9: Number of DQ/DQS Groups Per Side in Arria V SX Devices
This table lists the DQ/DQS groups for the soft memory controller. For the hard memory controller, you can get the
DQ/DQS groups from the pin table of the specific device.
Member Code
Package
896-pin FineLine BGA, Flip Chip
B3
1152-pin FineLine BGA, Flip Chip
1517-pin FineLine BGA, Flip Chip
Altera Corporation
Side
x8/x9
x16/x18
x32/x36
Top
7
3
1
Bottom
6
2
—
Top
7
3
1
Bottom
16
7
2
Top
11
5
2
Bottom
22
10
4
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DQ/DQS Groups in Arria V ST
Member Code
Package
896-pin FineLine BGA, Flip Chip
B5
1152-pin FineLine BGA, Flip Chip
1517-pin FineLine BGA, Flip Chip
Side
x8/x9
x16/x18
x32/x36
Top
7
3
1
Bottom
6
2
—
Top
7
3
1
Bottom
16
7
2
Top
11
5
2
Bottom
22
10
4
Related Information
Arria V Device Pin-Out Files
Download the relevant pin tables from this web page.
DQ/DQS Groups in Arria V ST
Table 7-10: Number of DQ/DQS Groups Per Side in Arria V ST Devices
This table lists the DQ/DQS groups for the soft memory controller. For the hard memory controller, you can get the
DQ/DQS groups from the pin table of the specific device.
Member Code
Package
896-pin FineLine BGA, Flip Chip
D3
1152-pin FineLine BGA, Flip Chip
1517-pin FineLine BGA, Flip Chip
896-pin FineLine BGA, Flip Chip
D5
1152-pin FineLine BGA, Flip Chip
1517-pin FineLine BGA, Flip Chip
Side
x8/x9
x16/x18
x32/x36
Top
7
3
1
Bottom
6
2
—
Top
7
3
1
Bottom
16
7
2
Top
11
5
2
Bottom
22
10
4
Top
7
3
1
Bottom
6
2
—
Top
7
3
1
Bottom
16
7
2
Top
11
5
2
Bottom
22
10
4
Related Information
Arria V Device Pin-Out Files
Download the relevant pin tables from this web page.
External Memory Interface Features in Arria V Devices
The Arria V I/O elements (IOE) provide built-in functionality required for a rapid and robust implementation
of external memory interfacing.
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UniPHY IP
The following device features are available for external memory interfaces:
•
•
•
•
•
•
•
•
DQS phase-shift circuitry
PHY Clock (PHYCLK) networks
DQS logic block
Dynamic on-chip termination (OCT) control
IOE registers
Delay chains
Hard memory controllers (Arria V GX, GT, SX, and ST only)
Read- and write-leveling support (Arria V GZ only)
UniPHY IP
The high-performance memory interface solution includes the self-calibrating UniPHY IP that is optimized
to take advantage of the Arria V I/O structure and the Quartus II software TimeQuest Timing Analyzer.
The UniPHY IP helps set up the physical interface (PHY) best suited for your system. This provides the total
solution for the highest reliable frequency of operation across process, voltage, and temperature (PVT)
variations.
The UniPHY IP instantiates a PLL to generate related clocks for the memory interface. The UniPHY IP can
also dynamically choose the number of delay chains that are required for the system. The amount of delay
is equal to the sum of the intrinsic delay of the delay element and the product of the number of delay steps
and the value of the delay steps.
The UniPHY IP and the Altera memory controller MegaCore® functions can run at half the I/O interface
frequency of the memory devices, allowing better timing management in high-speed memory interfaces.
The Arria V devices contain built-in circuitry in the IOE to convert data from full rate (the I/O frequency)
to half rate (the controller frequency) and vice versa.
Related Information
Reference Material volume, External Memory Interface Handbook
Provides more information about the UniPHY IP.
External Memory Interface Datapath
The following figures show overviews of the memory interface datapath that uses the Arria V I/O elements.
In the figures, the DQ/DQS read and write signals may be bidirectional or unidirectional, depending on the
memory standard. If the signal is bidirectional, it is active during read and write operations.
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Figure 7-1: External Memory Interface Datapath Overview for Arria V GX, GT, SX, and ST Devices
FPGA
Memory
DQS Postamble
Circuitry
DQS Enable
Control
Circuit
Postamble Enable
Postamble Clock
DQS
Enable
Circuit
DQS Delay
Chain
DLL
4n or 2n
2n
DDR Input
Registers
Read FIFO
4n
Clock
Management
and Reset
Full-Rate Clock
4
DQ Write Clock
Half-Rate Clock
DQS Write Clock
DQS (Read)
Half Data
Rate
Output
Registers
2n
Half Data
Rate
Output
Registers
2
DDR Output
and Output
Enable
Registers
n
n
DDR Output
and Output
Enable
Registers
DQ (Read)
DQ (Write)
DQS (Write)
Note: There are slight block differences for different memory interface standards. The shaded blocks are part of the I/O elements.
Figure 7-2: External Memory Interface Datapath Overview for Arria V GZ Devices
Memory
FPGA
DQS Enable
Control
Circuit
Postamble Enable
Postamble Clock
DQS
Enable
Circuit
DQS Logic
Block
DLL
4n
2n
DDR Input
Registers
Read FIFO
4n
4
Clock
Management
and Reset
DQ Write Clock
Half-Rate Clock
Alignment Clock
DQS Write Clock
DQS (Read)
Half Data
Rate
Output
Registers
2n
Half Data
Rate
Output
Registers
2
2n
Alignment
Registers
2
Alignment
Registers
DDR Output
and Output
Enable
Registers
DDR Output
and Output
Enable
Registers
n
n
DQ (Read)
DQ (Write)
DQS (Write)
Note: There are slight block differences for different memory interface standards. The shaded blocks are part of the I/O elements.
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DQS Phase-Shift Circuitry
DQS Phase-Shift Circuitry
The Arria V DLL provides phase shift to the DQS/CQ/CQn/QK# pins on read transactions if the
DQS/CQ/CQn/QK# pins are acting as input clocks or strobes to the FPGA.
The following figures show how the DLLs are connected to the DQS/CQ/CQn/QK# pins in the various
Arria V variants.
DQS/CQ/CQn/QK#
Pin
DQS/CQ/CQn/QK#
Pin
DLL
Reference
Clock
DQS/CQ/CQn/QK#
Pin
DQS/CQ/CQn/QK#
Pin
Figure 7-3: DQS/CQ/CQn/QK# Pins and DLLs in Arria V GX (A1 and A3) Devices
Δt
Δt
Δt
Δt
to IOE
to IOE
to IOE
to IOE
DQS Logic
Blocks
DLL
Transceiver Blocks
DLL
to IOE
to
IOE
Δt
DQS/CQ/CQn/QK#
Pin
to
IOE
Δt
DQS/CQ/CQn/QK#
Pin
to IOE
to IOE
to
IOE
Δt
DQS/CQ/CQn/QK#
Pin
to
IOE
Δt
DQS/CQ/CQn/QK#
Pin
DLL
Reference
Clock
to IOE
DLL
Δt
DQS/CQ/CQn/QK#
Pin
Δt
DQS/CQ/CQn/QK#
Pin
Δt
DQS/CQ/CQn/QK#
Pin
DQS/CQ/CQn/QK#
Pin
Δt
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DQS Logic
Blocks
DLL
DLL
DLL
Reference
Clock
DLL
Reference
Clock
DLL
Reference
Clock
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7-13
DQS/CQ/CQn/QK#
Pin
DQS/CQ/CQn/QK#
Pin
DQS/CQ/CQn/QK#
Pin
DLL
Reference
Clock
DQS/CQ/CQn/QK#
Pin
Figure 7-4: DQS/CQ/CQn/QK# Pins and DLLs in Arria V GX (A5, A7, B1, B3, B5, and B7), GT, and GZ Devices
Δt
Δt
Δt
Δt
to IOE
to IOE
to IOE
to IOE
DQS Logic
Blocks
DLL
Transceiver Blocks
Transceiver Blocks
DLL
to IOE
to IOE
to IOE
to IOE
DLL
DLL
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Δt
DQS/CQ/CQn/QK#
Pin
Δt
DQS/CQ/CQn/QK#
Pin
Δt
DQS/CQ/CQn/QK#
Pin
DQS/CQ/CQn/QK#
Pin
Δt
DLL
Reference
Clock
DLL
Reference
Clock
DLL
Reference
Clock
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Delay-Locked Loop
DQS/CQ/CQn/QK#
Pin
DLL
Reference
Clock
DQS/CQ/CQn/QK#
Pin
Figure 7-5: DQS/CQ/CQn/QK# Pins and DLLs in Arria V SX and ST Devices
Δt
Δt
to IOE
to IOE
DLL
HPS I/O
DLL
DQS Logic
Blocks
Transceiver Blocks
HPS
PLL
HPS Block
DQS
Pin
Δt
DQS
Pin
Transceiver Blocks
to IOE
to IOE
to IOE
to IOE
to IOE
DLL
DLL
Δt
DQS/CQ/CQn/QK#
Pin
Δt
DQS/CQ/CQn/QK#
Pin
Δt
DQS/CQ/CQn/QK#
Pin
DQS/CQ/CQn/QK#
Pin
Δt
DLL
Reference
Clock
Δt
to IOE
DLL
Reference
Clock
Delay-Locked Loop
The delay-locked loop (DLL) uses a frequency reference to dynamically generate control signals for the delay
chains in each of the DQS/CQ/CQn/QK# pins, allowing the delay to compensate for process, voltage, and
temperature (PVT) variations. The DQS delay settings are gray-coded to reduce jitter if the DLL updates
the settings.
There are a maximum of five DLLs in Arria V devices. You can clock each DLL using different frequencies.
Some of the DLLs can access the two adjacent sides from its location in the device. You can have two different
interfaces with the same frequency on the two sides adjacent to a DLL, where the DLL controls the DQS
delay settings for both interfaces.
I/O banks between two DLLs have the flexibility to create multiple frequencies and multiple-type interfaces.
These banks can use settings from either or both adjacent DLLs. For example, DQS1R can get its phase-shift
settings from DLL_TR, while DQS2R can get its phase-shift settings from DLL_BR.
The reference clock for each DLL may come from the PLL output clocks or clock input pins.
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DLL Reference Clock Input for Arria V Devices
Note: If you have a dedicated PLL that only generates the DLL input reference clock, set the PLL mode to
No Compensation to achieve better performance (or the Quartus II software automatically changes
it). Because the PLL does not use any other outputs, it does not have to compensate for any clock
paths.
DLL Reference Clock Input for Arria V Devices
Table 7-11: DLL Reference Clock Input from PLL Counter Outputs for Arria V GX A1 and A3, and Arria V GT C3
Devices—Preliminary
PLL
DLL
1L
0L
RC
TC
BC
DLL_T0
plldout[1:0]
—
—
plldout[1:0]
—
DLL_T1
—
—
—
plldout[1:0]
—
DLL_B0
—
plldout[1:0]
—
—
plldout[1:0]
DLL_B1
—
—
—
—
plldout[1:0]
DLL_R0
—
—
plldout[1:0]
—
—
Table 7-12: DLL Reference Clock Input from PLL Counter Outputs for Arria V GX A5, A7, B1, and B3, and Arria V
GT C7 and D3 Devices—Preliminary
DLL
PLL
TL
TR
BR
BL
TC
BC
DLL_T0
plldout[1:0]
—
—
—
plldout[1:0]
—
DLL_T1
—
plldout[1:0]
—
—
plldout[1:0]
—
DLL_B0
—
—
—
plldout[1:0]
—
plldout[1:0]
DLL_B1
—
—
plldout[1:0]
—
—
plldout[1:0]
Table 7-13: DLL Reference Clock Input from PLL Counter Outputs for Arria V GX B5 and B7, and Arria V GT D7
Devices—Preliminary
DLL
PLL
2L
2R
0R
0L
TC
BC
DLL_T0
plldout[1:0]
—
—
—
plldout[1:0]
—
DLL_T1
—
plldout[1:0]
—
—
plldout[1:0]
—
DLL_B0
—
—
—
plldout[1:0]
—
plldout[1:0]
DLL_B1
—
—
plldout[1:0]
—
—
plldout[1:0]
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DLL Reference Clock Input for Arria V Devices
Table 7-14: DLL Reference Clock Input for Arria V GZ E1 and E3 Devices
DLL
DLL_TL
DLL_TR
DLL_BR
DLL_BL
PLL
CLKIN
Center
Corner
Left
Center
Right
CEN_X84_Y77
COR_X0_Y81
CLK20P
CLK16P
—
CEN_X84_Y68
COR_X0_Y72
CLK21P
CLK17P
CLK22P
CLK18P
CLK23P
CLK19P
—
CLK16P
CLK12P
CLK17P
CLK13P
CLK18P
CLK14P
CLK19P
CLK15P
CLK4P
CLK8P
CLK5P
CLK9P
CLK6P
CLK10P
CLK7P
CLK11P
—
CEN_X84_Y77
COR_X185_Y81
CEN_X84_Y68
COR_X185_Y72
CEN_X84_Y11
COR_X185_Y10
CEN_X84_Y2
COR_X185_Y1
—
CEN_X84_Y11
COR_X0_Y10
CLK0P
CLK4P
CEN_X84_Y2
COR_X0_Y1
CLK1P
CLK5P
CLK2P
CLK6P
CLK3P
CLK7P
Table 7-15: DLL Reference Clock Input for Arria V GZ E5 and E7 Devices
DLL
DLL_TL
DLL_TR
PLL
CLKIN
Center
Corner
Left
Center
Right
CEN_X92_Y96
COR_X0_Y100
CLK20P
CLK16P
—
CEN_X92_Y87
COR_X0_Y91
CLK21P
CLK17P
CLK22P
CLK18P
CLK23P
CLK19P
—
CLK16P
CLK12P
CLK17P
CLK13P
CLK18P
CLK14P
CLK19P
CLK15P
CEN_X92_Y96
CEN_X92_Y87
COR_X202_
Y100
COR_X202_Y91
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DLL Phase-Shift
DLL
DLL_BR
DLL_BL
PLL
7-17
CLKIN
Center
Corner
Left
Center
Right
CEN_X92_Y11
COR_X202_Y10
—
CLK4P
CLK8P
CEN_X92_Y2
COR_X202_Y1
CLK5P
CLK9P
CLK6P
CLK10P
CLK7P
CLK11P
—
CEN_X92_Y11
COR_X0_Y10
CLK0P
CLK4P
CEN_X92_Y1
COR_X0_Y1
CLK1P
CLK5P
CLK2P
CLK6P
CLK3P
CLK7P
Table 7-16: DLL Reference Clock Input from PLL Counter Outputs for Arria V SX B3 and B5, and Arria V ST D3
and D5 Devices—Preliminary
DLL
PLL
2L
0R
0L
TC
BC
DLL_T0
plldout[1:0]
—
—
plldout[1:0]
—
DLL_B0
—
—
plldout[1:0]
—
plldout[1:0]
DLL_B1
—
plldout[1:0]
—
—
plldout[1:0]
DLL Phase-Shift
The DLL can shift the incoming DQS signals by 0° or 90° by using two delay cells in the DQS logic block.
The shifted DQS signal is then used as the clock for the DQ IOE input registers.
All DQS/CQ/CQn/QK# pins referenced to the same DLL, can have their input signal phase shifted by a
different degree amount but all must be referenced at one particular frequency. However, not all phase-shift
combinations are supported.
The 7-bit DQS delay settings from the DLL vary with PVT to implement the phase-shift delay. For example,
with a 0° shift, the DQS/CQ/CQn/QK# signal bypasses both the DLL and DQS logic blocks. The Quartus II
software automatically sets the DQ input delay chains, so that the skew between the DQ and
DQS/CQ/CQn/QK# pins at the DQ IOE registers is negligible if a 0° shift is implemented. You can feed the
DQS delay settings to the DQS logic block and logic array.
The shifted DQS/CQ/CQn/QK# signal goes to the DQS bus to clock the IOE input registers of the DQ pins.
The signal can also go into the logic array for resynchronization if you are not using IOE read FIFO for
resynchronization.
For Arria V SoC devices, you can feed the hard processor system (HPS) DQS delay settings to the HPS DQS
logic block only.
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DLL Phase-Shift
Figure 7-6: Simplified Diagram of the DQS Phase-Shift Circuitry (Arria V GX, GT, SX, and ST)
This figure shows a simple block diagram of the DLL in Arria V GZ devices. All features of the DQS phase-shift
circuitry are accessible from the UniPHY megafunction in the Quartus II software.
DLL
aload
Input Reference
Clock
upndnin
clk
Phase
Comparator
This clock can
come from a PLL
output clock or an
input clock pin
upndninclkena
DQS delay settings
can go to the logic
array and DQS logic
block
Up/Down
Counter
7
delayctrlout [6:0]
DQS Delay
Settings
7
Delay Chains
7
dqsupdate
Figure 7-7: Simplified Diagram of the DQS Phase-Shift Circuitry (Arria V GZ)
This figure shows a simple block diagram of the DLL in Arria V GZ devices. All features of the DQS phase-shift
circuitry are accessible from the UniPHY megafunction in the Quartus II software.
addnsub
Phase offset settings
from the logic array
(offset[6:0])
7
DLL
Input Reference
Clock
clk
offsetdelayctrlin[6:0]
aload
Phase
Up/Down
Comparator upndninclkena
Counter
Phase offset
settings can only
go to the DQS
logic blocks
7
Phase
Offset
Control
B
offsetdelayctrlout[6:0]
offsetdelayctrlin[6:0]
7
delayctrlout[6:0]
7
7
Phase offset
settings to DQS pins
(offsetctrlout[6:0])
addnsub
Phase offset settings
from the logic array( offset [6:0] )
upndnin
Delay Chains
7
(dll_offset_ctrl_a)
offsetdelayctrlout[6:0]
This clock can
come from a PLL
output clock or an
input clock pin
Phase
Offset
Control
A
dqsupdate
7
Phase offset
settings to DQS pin
(offsetctrlout[6:0])
(dll_offset_ctrl_b)
DQS Delay
Settings
DQS delay settings can go to the
logic array and DQS logic block
The input reference clock goes into the DLL to a chain of up to eight delay elements. The phase comparator
compares the signal coming out of the end of the delay chain block to the input reference clock. The phase
comparator then issues the upndn signal to the Gray-code counter. This signal increments or decrements a
7-bit delay setting (DQS delay settings) that increases or decreases the delay through the delay element chain
to bring the input reference clock and the signals coming out of the delay element chain in phase.
The DLL can be reset from either the logic array or a user I/O pin. Each time the DLL is reset, you must wait
for 2,560 clock cycles for the DLL to lock before you can capture the data properly. The DLL phase comparator
requires 2,560 clock cycles to lock and calculate the correct input clock period.
For the frequency range of each DLL frequency mode, refer to the device datasheet.
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PHY Clock (PHYCLK) Networks
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Related Information
Arria V Device Datasheet
PHY Clock (PHYCLK) Networks
The PHYCLK network is a dedicated high-speed, low-skew balanced clock tree designed for a highperformance external memory interface.
The top and bottom sides of the Arria V devices have up to four PHYCLK networks. There are up to two
PHYCLK networks on the left and right side I/O banks. Each PHYCLK network spans across one I/O bank
and is driven by one of the PLLs located adjacent to the I/O bank.
The following figures show the PHYCLK networks available in the Arria V devices.
Figure 7-8: PHYCLK Networks in Arria V GX A1 and A3 Devices
I/O Bank 8
Sub-Bank
Sub-Bank
Left
PLL
I/O Bank 7
Center
PLL Sub-Bank
Sub-Bank
Sub-Bank Center Sub-Bank
Sub-Bank
PLL
I/O Bank 6
I/O Bank 5
Sub-Bank
FPGA Device
PHYCLK Networks
Transceiver Banks
PHYCLK Networks
PHYCLK Networks
Left
PLL
Sub-Bank
Sub-Bank Center Sub-Bank
Sub-Bank
PLL
I/O Bank 4
I/O Bank 3
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PHY Clock (PHYCLK) Networks
Figure 7-9: PHYCLK Networks in Arria V GX A5, A7, B1, B3, B5, and B7 Devices, and Arria V GZ E1, E3, E5,
and E7 Devices
I/O Bank 8
Sub-Bank
Sub-Bank
Left
PLL
I/O Bank 7
Center
PLL Sub-Bank
Sub-Bank
Right
PLL
Transceiver Banks
Transceiver Banks
PHYCLK Networks
FPGA Device
PHYCLK Networks
Left
PLL
Sub-Bank
Right
PLL
Sub-Bank Center Sub-Bank
Sub-Bank
PLL
I/O Bank 4
I/O Bank 3
Figure 7-10: PHYCLK Networks in Arria V SX B3 and B5 Devices, and Arria V ST D3 and D5 Devices
I/O Bank 8
Sub-Bank
I/O Bank 7
Center
PLL Sub-Bank
Sub-Bank
PHYCLK Networks
HPS PHYCLK Networks
HPS
PLL
Transceiver Banks
HPS Block
HPS I/O
Left
PLL
Sub-Bank
Transceiver Banks
FPGA Device
PHYCLK Networks
Left
PLL
Sub-Bank
Right
PLL
Sub-Bank Center Sub-Bank
Sub-Bank
PLL
I/O Bank 4
I/O Bank 3
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DQS Logic Block
The PHYCLK network can be used to drive I/O sub-banks in each I/O bank. Each I/O sub-bank can be
driven by only one PHYCLK network—all I/O pins in an I/O sub-bank are driven by the same PHYCLK
network.
DQS Logic Block
Each DQS/CQ/CQn/QK# pin is connected to a separate DQS logic block, which consists of the update enable
circuitry, DQS delay chains, and DQS postamble circuitry.
The following figure shows the DQS logic block.
Figure 7-11: DQS Logic Block in Arria V GX, GT, SX, and ST Devices
DQS Enable
dqsin
D Q
PRE
dqsenable
DQS Enable Control Circuit
Postamble
Enable
dqsenablein
D
Q
0
1
D Q
dqsenableout
0
1
2
D Q
<delay dqs enable>
D Q
zerophaseclk
(Postamble clock)
1
Bypass
dqsbusout
0
dqsin
dqsdisablen
enaphasetransferreg
DQS delay settings from the DLL
The dqsenable
signal can also
come from the
FPGA fabric
DQS Delay Chain
Applicable only if the DQS
delay settings come from a
side with two DLLs
DQS delay settings from the DLL
DQS/CQ/CQn/QK#
Pin
Core Logic
DQS Postamble Circuitry
<dqs delay chain bypass>
7
delayctrlin [6:0]
7
7
delayctrlin [6:0] 7
7
levelingclk
(Read-leveled postamble clock)
1
0
7
7
7
0
1
2
D Q
dqsupdateen
This clock can come from a PLL
output clock or an input clock pin
Input Reference
Clock
Update
Enable
Circuitry
Figure 7-12: DQS Logic Block in Arria V GZ Devices
DQS Delay Chain
DQS Enable
00
01
10
11
dqsin
DQS/CQ or
CQn Pin
dqsbusout
D Q
dqsin
The dqsenable
signal can also
come from the
FPGA fabric
<use_alternate_input_for
first_stage_delay_control>
dqsenable
0
1
7
zerophaseclk
Postamble clock
0
1
D Q
0
1
enaphasetransferreg
D Q
dqsenablein
D Q
D Q
leveling clk
<bypass_output_register>
Read-leveled
postamble clock
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7
0
1
<dqs_ctrl_latches_enable>
offsetctrlin [6..0] 7
7
1
D Q
D Q
Phase offset
0
dqsupdateen
dqsenableout settings from the
DQS phase-shift
<dqs_offsetctrl_enable>
0
circuitry
7
1
DQS delay
delayctrlin [6..0]
Input Reference
settings from the
Clock
DQS phase-shift
circuitry
<delay_dqs_enable_by_half_cycle>
DQS Postamble Circuit
7
7
0
1
7
Postamble
Enable
phasectrlin[1..0]
PRE
Update
Enable
Circuitry
This clock can come from a PLL
output clock or an input clock pin
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Update Enable Circuitry
Update Enable Circuitry
The update enable circuitry enables the registers to allow enough time for the DQS delay settings to travel
from the DQS phase-shift circuitry or core logic to all the DQS logic blocks before the next change.
Both the DQS delay settings and the phase-offset settings pass through a register before going into the DQS
delay chains. The registers are controlled by the update enable circuitry to allow enough time for any changes
in the DQS delay setting bits to arrive at all the delay elements, which allows them to be adjusted at the same
time.
The circuitry uses the input reference clock or a user clock from the core to generate the update enable
output. The UniPHY intellectual property (IP) uses this circuit by default.
Figure 7-13: DQS Update Enable Waveform
This figure shows an example waveform of the update enable circuitry output.
DLL Counter Update
(Every 8 cycles)
DLL Counter Update
(Every 8 cycles)
System Clock
DQS Delay Settings
Updated every 8 cycles
7 bit
Update Enable
Circuitry Output
DQS Delay Chain
DQS delay chains consist of a set of variable delay elements to allow the input DQS/CQ/CQn/QK# signals
to be shifted by the amount specified by the DQS phase-shift circuitry or the logic array.
There are two delay elements in the DQS delay chain that have the same characteristics:
• Delay elements in the DQS logic block
• Delay elements in the DLL
The DQS/CQ/CQn/QK# pin is shifted by the DQS delay settings.
The number of delay chains required is transparent because the UniPHY IP automatically sets it when you
choose the operating frequency.
In Arria V GX, GT, and GZ devices, if you do not use the DLL to control the DQS delay chains, you can
input your own gray-coded 7 bit settings using the delayctrlin[6..0] signals available in the UniPHY IP.
In the Arria V SX and ST devices, the DQS delay chain is controlled by the DQS phase-shift circuitry only.
Related Information
• ALTDQ_DQS2 Megafunction User Guide
Provides more information about programming the delay chains.
• Delay Chains on page 7-28
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DQS Postamble Circuitry
There are preamble and postamble specifications for both read and write operations in DDR3 and DDR2
SDRAM. The DQS postamble circuitry ensures that data is not lost if there is noise on the DQS line during
the end of a read operation that occurs while DQS is in a postamble state.
The Arria V devices contain dedicated postamble registers that you can control to ground the shifted DQS
signal that is used to clock the DQ input registers at the end of a read operation. This function ensures that
any glitches on the DQS input signal during the end of a read operation and occurring while DQS is in a
postamble state do not affect the DQ IOE registers.
• For preamble state, the DQS is low, just after a high-impedance state.
• For postamble state, the DQS is low, just before it returns to a high-impedance state.
For external memory interfaces that use a bidirectional read strobe (DDR3 and DDR2 SDRAM), the DQS
signal is low before going to or coming from a high-impedance state.
Half Data Rate Block
The Arria V devices contain a half data rate (HDR) block in the postamble enable circuitry.
The HDR block is clocked by the half-rate resynchronization clock, which is the output of the I/O clock
divider circuit. There is an AND gate after the postamble register outputs to avoid postamble glitches from
a previous read burst on a non-consecutive read burst. This scheme allows half-a-clock cycle latency for
dqsenable assertion and zero latency for dqsenable deassertion.
Using the HDR block as the first stage capture register in the postamble enable circuitry block is optional.
Altera recommends using these registers if the controller is running at half the frequency of the I/Os.
Figure 7-14: Avoiding Glitch on a Non-Consecutive Read Burst Waveform
This figure shows how to avoid postamble glitches using the HDR block.
Postamble glitch
Postamble
Preamble
DQS
Postamble Enable
dqsenable
Delayed by
1/2T logic
Leveling Circuitry for Arria V GZ Devices
DDR3 SDRAM unbuffered modules use a fly-by clock distribution topology for better signal integrity. This
means that the CK/CK# signals arrive at each DDR3 SDRAM device in the module at different times. The
difference in arrival time between the first DDR3 SDRAM device and the last device on the module can be
as long as 1.6 ns.
The following figure shows the clock topology in DDR3 SDRAM unbuffered modules.
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Figure 7-15: DDR3 SDRAM Unbuffered Module Clock Topology
DQS/DQ
DQS/DQ
DQS/DQ
DQS/DQ CK/CK#
DQS/DQ
DQS/DQ
DQS/DQ
DQS/DQ
FPGA
Because the data and read strobe signals are still point-to-point, take special care to ensure that the timing
relationship between the CK/CK# and DQS signals (tDQSS, tDSS, and tDSH) during a write is met at every
device on the modules. In a similar way, read data coming back into the FPGA from the memory is also
staggered.
The Arria V GZ devices have leveling circuitry to address these two situations. There is one leveling circuit
per I/O sub-bank (for example, I/O sub-bank 1A, 1B, and 1C each has one leveling circuitry). These delay
chains are PVT-compensated by the same DQS delay settings as the DLL and DQS delay chains.
The DLL uses eight delay chain taps, such that each delay chain tap generates a 45° delay. The generated
clock phases are distributed to every DQS logic block that is available in the I/O sub-bank. The delay chain
taps then feed a multiplexer controlled by the UniPHY megafunction to select which clock phases are to be
used for that x4 or x 8 DQS group. Each group can use a different tap output from the read-leveling and
write-leveling delay chains to compensate for the different CK/CK# delay going into each device on the
module.
Figure 7-16: Write-Leveling Delay Chains and Multiplexers
There is one leveling delay chain per I/O sub-bank (for example, I/O sub-banks 1A, 1B, and 1C). You can
only have one memory interface in each I/O sub-bank when you use the leveling delay chain.
Write clk
(-900)
Write-Leveled DQS Clock
Write-Leveled DQ Clock
The –90° write clock of the UniPHY IP feeds the write-leveling circuitry to produce the clock to generate
the DQS and DQ signals. During initialization, the UniPHY IP picks the correct write-leveled clock for the
DQS and DQ clocks for each DQ/DQS group after sweeping all the available clocks in the write calibration
process. The DQ clock output is –90° phase-shifted compared to the DQS clock output.
The UniPHY IP dynamically calibrates the alignment for read and write leveling during the initialization
process.
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Dynamic OCT Control
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Related Information
• Reference Material volume, External Memory Interface Handbook
Provides more information about the UniPHY IP.
• DDR2 and DDR3 SDRAM Board Design Guidelines chapter, External Memory Interface Handbook
Provides layout guidelines for DDR3 SDRAM interface.
Dynamic OCT Control
The dynamic OCT control block includes all the registers that are required to dynamically turn the on-chip
parallel termination (RT OCT) on during a read and turn RT OCT off during a write.
Figure 7-17: Dynamic OCT Control Block for Arria V Devices
OCT Control Path
OCT Control
Q
D
Q
D
DFF
DFF
0
1
OCT Control
1
0
OCT Enable
Q
D
D
DFF
Q
DFF
OCT Half-Rate Clock
Write Clock
The full-rate write clock comes from the PLL. The DQ write
clock and DQS write clock have a 90° offset between them
Related Information
Dynamic OCT in Arria V Devices on page 5-35
Provides more information about dynamic OCT control.
IOE Registers
The IOE registers are expanded to allow source-synchronous systems to have faster register-to-FIFO transfers
and resynchronization. All top, bottom, and right IOEs have the same capability.
Input Registers
The input path consists of the DDR input registers and the read FIFO block. You can bypass each block of
the input path.
There are three registers in the DDR input registers block. Registers A and B capture data on the positive
and negative edges of the clock while register C aligns the captured data. Register C uses the same clock as
Register A.
The read FIFO block resynchronizes the data to the system clock domain and lowers the data rate to half
rate.
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Output Registers
The following figure shows the registers available in the Arria V input path. For DDR3 and DDR2 SDRAM
interfaces, the DQS and DQSn signals must be inverted. If you use Altera’s memory interface IPs, the DQS
and DQSn signals are automatically inverted.
Figure 7-18: IOE Input Registers for Arria V Devices
Double Data Rate Input Registers
DQ
D
datain [0]
Q
The input
clock can be
from the DQS
logic block or
from a global
clock line.
DQS/CQ
D
Q
Q
DFF
Input Reg B
To core
Read FIFO
DFF
Input Reg A
D
dataout[3..0]
D
Q
datain [1]
This half-rate or
full-rate read clock
comes from a PLL
through the clock
network
DFF
Input Reg C
wrclk
rdclk
Half-rate or
full-rate clock
Output Registers
The Arria V output and output-enable path is divided into the HDR block, and output and output-enable
registers. The device can bypass each block of the output and output-enable path.
The output path is designed to route combinatorial or registered single data rate (SDR) outputs and full-rate
or half-rate DDR outputs from the FPGA core. Half-rate data is converted to full-rate with the HDR block,
clocked by the half-rate clock from the PLL.
The output-enable path has a structure similar to the output path—ensuring that the output-enable path
goes through the same delay and latency as the output path.
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Output Registers
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Figure 7-19: IOE Output and Output-Enable Path Registers for Arria V GX, GT, SX, and ST Devices
The following figure shows the registers available in the Arria V GX, GT, SX, and ST output and output-enable
paths.
Data coming from the FPGA core are at half the frequency of the
memory interface clock frequency in half-rate mode
Double Data Rate
Output-Enable Registers
Half Data Rate to Single
Data Rate Output-Enable
Registers
From Core
Q
D
DFF
Q
D
0
1
DFF
OE Reg AOE
From Core
Q
D
OR2
1
0
Q
D
DFF
DFF
OE Reg BOE
Half Data Rate to Single
Data Rate Output Registers
Double Data Rate
Output Registers
From Core
(wdata2)
Q
D
DFF
DFF
From Core
(wdata0)
0
1
TRI
DQ or DQS
OE Reg AO
Q
D
Q
D
0
1
DFF
From Core
(wdata3)
Q
D
DFF
0
1
DFF
From Core
(wdata1)
OE Reg BO
Q
D
Q
D
DFF
Half-Rate Clock
from PLL
Write Clock
The full-rate write clock can come from the PLL. The DQ
write clock have a 90° offset to the DQS write clock.
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Delay Chains
Figure 7-20: IOE Output and Output-Enable Path Registers for Arria V GZ Devices
The following figure shows the registers available in the Arria V GZ output and output-enable paths. You
can bypass each register block of the output and output-enable paths.
Data coming from the FPGA core are at half the
frequency of the memory interface clock frequency in
half-rate mode
Used in DDR3 SDRAM interfaces
for write-leveling purposes
Half Data Rate to
Single Data Rate
Output-Enable
Registers
From Core
D Q
DFF
0
1
D Q
D Q
D Q
DFF
DFF
DFF
000
001
010
011
100
101
110
111
Alignment Registers
D Q
0
1
Double Data Rate
Output-Enable Registers
dataout
DFF
From Core
DFF
enaphasetransferreg
D Q
DFF
D Q
OE Reg AOE
OR2
1
0
<add_output_cycle_delay> enaoutputcycledelay[2..0]
D Q
DFF
From Core
(wdata2)
Half Data Rate to
Single Data Rate
Output Registers
D Q
DFF
0
1
D Q
D Q
D Q
DFF
DFF
DFF
000
001
010
011
100
101
110
111
Alignment Registers
D Q
0
1
Double Data Rate
Output Registers
dataout
D Q
DFF
DFF
From Core
(wdata0)
OE Reg BOE
enaphasetransferreg
0
1
TRI
DQ or DQS
OE Reg AO
D Q
<add_output_cycle_delay> enaoutputcycledelay[2..0]
DFF
From Core
(wdata3)
D Q
DFF
0
1
D Q
D Q
D Q
DFF
DFF
DFF
From Core
(wdata1)
000
001
010
011
100
101
110
111
D Q
0
1
dataout
DFF
D Q
DFF
enaphasetransferreg
OE Reg BO
D Q
DFF
Half-Rate Clock
From the PLL
Alignment Clock
From write-leveling delay chains
<add_output_cycle_delay>
enaoutputcycledelay[2..0]
The write clock can come from either the Write Clock
PLL or from the write-leveling delay chain.
The DQ write clock and DQS write clock
have a 90° offset between them
Delay Chains
The Arria V devices contain run-time adjustable delay chains in the I/O blocks and the DQS logic blocks.
You can control the delay chain setting through the I/O or the DQS configuration block output.
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Delay Chains
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Every I/O block contains a delay chain between the following elements:
•
•
•
•
The output registers and output buffer
The input buffer and input register
The output enable and output buffer
The R T OCT enable-control register and output buffer
Figure 7-21: Delay Chains in an I/O Block in the Arria V GX, GT, SX, and ST Devices
OCT Enable Output Enable
D5 OCT
delay
chain
D5
output-enable
delay chain
D5 Delay
delay
chain
DQ or DQS
0
1
D1 Delay
delay chain
Figure 7-22: Delay Chains in an I/O Block in Arria V GZ Devices
rtena
oe
octdelaysetting1
D5 OCT
delay chain
D5 Ouput
Enable
delay chain
octdelaysetting2
D6 OCT
delay chain
D6 Ouput
Enable
delay chain
outputdelaysetting1
outputdelaysetting2
DQ
D6 Delay
delay chain
D1 Delay
delay chain
D1 Rise/Fall
Balancing
delay chain
D2 Delay
delay chain
D5 Delay
delay chain
0
1
D3 Delay
delay chain
padtoinputregisterdelaysetting
padtoinputregisterrisefalldelaysetting[5..0]
Each DQS logic block contains a delay chain after the dqsbusout output and another delay chain before the
dqsenable input.
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I/O and DQS Configuration Blocks
Figure 7-23: Delay Chains in the DQS Input Path
DQS
Enable
dqsin
DQS
DQS delay
chain
D4
delay
chain
dqsbusout
dqsenable
T11
delay
chain
DQS
Enable
Control
Related Information
• ALTDQ_DQS2 Megafunction User Guide
Provides more information about programming the delay chains.
• DQS Delay Chain on page 7-22
I/O and DQS Configuration Blocks
The I/O and DQS configuration blocks are shift registers that you can use to dynamically change the settings
of various device configuration bits.
• The shift registers power-up low.
• Every I/O pin contains one I/O configuration register.
• Every DQS pin contains one DQS configuration block in addition to the I/O configuration register.
Figure 7-24: Configuration Block (I/O and DQS)
This figure shows the I/O configuration block and the DQS configuration block circuitry.
MSB
datain
update
ena
rankselectread
rankselectwrite
bit2
bit1
bit0
dataout
clk
Related Information
ALTDQ_DQS2 Megafunction User Guide
Provides details about the I/O and DQS configuration block bit sequence.
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Hard Memory Controller
The Arria V GX, GT, SX, and ST devices feature dedicated hard memory controllers. You can use the hard
memory controllers for DDR2 and DDR3 SDRAM interfaces. Compared to the memory controllers
implemented using core logic, the hard memory controllers allow support for higher memory interface
frequencies with shorter latency cycles.
The hard memory controllers use dedicated I/O pins as data, address, command, control, clock, and ground
pins for the SDRAM interface. If you do not use the hard memory controllers, you can use these dedicated
pins as regular I/O pins.
Note: There is no hard memory controller in the Arria V GZ devices.
Related Information
• Functional Description—HPC II Controller chapter, External Memory Interface Handbook
The hard memory controller is functionally similar to the High-Performance Controller II (HPC II).
• Functional Description—Hard Memory Interface chapter, External Memory Interface Handbook
Provides detailed information about application of the hard memory interface.
Features of the Hard Memory Controller
Table 7-17: Features of the Arria V Hard Memory Controller
Feature
Description
Memory Interface
Data Width
• 8, 16, and 32 bit data
• 16 bit data + 8 bit ECC
• 32 bit data + 8bit ECC
Memory Density
The controller supports up to four gigabits density parts and two chip selects.
Memory Burst Length • DDR3—Burst length of 8 and burst chop of 4
• DDR2—Burst lengths of 4 and 8
Command and Data
Reordering
The controller increases efficiency through the support for out-of-order execution
of DRAM commands—with address collision detection-and in-order return of results.
Starvation Control
A starvation counter ensures that all requests are served after a predefined time-out
period. This function ensures that data with low priority access are not left behind
when reordering data for efficiency.
User-Configurable
Priority Support
When the controller detects a high priority request, it allows the request to bypass
the current queuing request. This request is processed immediately and thus reduces
latency.
Avalon®-MM Data
By default, the controller supports the Avalon Memory-Mapped protocol.
Slave Local Interface
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Features of the Hard Memory Controller
Feature
Bank Management
Description
By default, the controller provides closed-page bank management on every access.
The controller intelligently keeps a row open based on incoming traffic. This feature
improves the efficiency of the controller especially for random traffic.
Streaming Reads and The controller can issue reads or writes continuously to sequential addresses every
clock cycle if the bank is open. This function allows for very high efficiencies with
Writes
large amounts of data.
Bank Interleaving
The controller can issue reads or writes continuously to 'random' addresses.
Predictive Bank
Management
The controller can issue bank management commands early so that the correct row
is open when the read or write occurs. This increases efficiency.
Multiport Interface
The interface allows you to connect up to six data masters to access the memory
controller through the local interface. You can update the multiport scheduling
configuration without interrupting traffic on a port.
Built-in Burst
Adaptor
The controller can accept bursts of arbitrary sizes on its local interface and map these
bursts to efficient memory commands.
Run-time Configura- This feature provides support for updates to the timing parameters without requiring
tion of the Controller reconfiguration of the FPGA, apart from the standard compile-time setting of the
timing parameters.
On-Die Termination The controller controls the on-die termination (ODT) in the memory, which improves
signal integrity and simplifies your board design.
User-Controlled
Refresh Timing
You can optionally control when refreshes occur—allowing the refreshes to avoid
clashing of important reads or writes with the refresh lock-out time.
Low Power Modes
You can optionally request the controller to put the memory into the self-refresh or
deep power-down modes.
Partial Array SelfRefresh
You can select the region of memory to refresh during self-refresh through the mode
register to save power.
ECC
Standard Hamming single error correction, double error detection (SECDED) error
correction code (ECC) support:
• 32 bit data + 8 bit ECC
• 16 bit data + 8 bit ECC
Additive Latency
With additive latency, the controller can issue a READ/WRITE command after the
ACTIVATE command to the bank prior to t RCD to increase the command efficiency.
Caution: Efficiency degradation may occur when using the additive latency
feature with the hard memory controller for DDR3 SDRAM interfaces
at 533 MHz.
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Multi-Port Front End
Feature
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Description
Write Acknowledgment
The controller supports write acknowledgment on the local interface.
User Control of
Memory Controller
Initialization
The controller supports initialization of the memory controller under the control of
user logic—for example, through the software control in the user system if a processor
is present.
Controller Bonding
Support
You can bond two controllers to achieve wider data width for higher bandwidth
applications.
Multi-Port Front End
The multi-port front end (MPFE) and its associated fabric interface provide up to six command ports, four
read-data ports and four write-data ports, through which user logic can access the hard memory controller.
Figure 7-25: Simplified Diagram of the Arria V Hard Memory Interface
This figure shows a simplified diagram of the Arria V hard memory interface with the MPFE.
FPGA
FPGA
Core Logic
MPFE
Avalon-MM Interface
Memory
Controller
PHY
Memory
AFI
Bonding Support
Note: Bonding is supported only for hard memory controllers configured with one port. Do not use the
bonding configuration when there is more than one port in each hard memory controller.
You can bond one port of any data width (64, 128, or 256 bits) from two hard memory controllers to support
wider data widths.
If you bond two hard memory controllers, the data going out of the controllers to the user logic is synchronized. However, the data going out of the controllers to the memory is not synchronized.
The bonding controllers are not synchronized and remain independent with two separate address buses and
two independent command buses. These buses are calibrated separately.
If you require ECC support for a bonded interface, you must implement the ECC logic external to the hard
memory controllers.
Note: Only one bonding feature is available per package through the core fabric. A memory interface that
uses the bonding feature has higher average latency.
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Bonding Support
Figure 7-26: Hard Memory Controllers Bonding Support in Arria V GX A1 and A3 Devices
This figure shows the bonding of two opposite hard memory controllers through the core fabric.
16-bit Interface
Bank 8
Bank 7
Bank 5
Bonding
(Core Routing)
Bank 6
Hard Memory Controller
Hard Memory Controller
Bank 3
Bank 4
16-bit Interface
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Bonding Support
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Figure 7-27: Hard Memory Controllers Bonding Support in Arria V GX A5, A7, B1, B3, B5, and B7 Devices,
and Arria V GT D3 and D7 Devices
This figure shows the bonding of opposite and same side hard memory controllers through the core fabric.
32-bit Interface
32-bit Interface
Bank 8
Bank 7
Hard Memory Controller
Hard Memory Controller
Core routing is enabled only
for single hard memory
controller bond out per side.
This bonding is available only
if you do not use the hard
memory controllers in banks
4 and 7 for bonding with other
banks.
Bonding
(Core Routing)
Bonding
(Core Routing)
Bonding
(Core Routing)
Bonding
(Core Routing)
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Hard Memory Controller
Bank 3
Bank 4
32-bit Interface
32-bit Interface
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Hard Memory Controller Width for Arria V GX
Figure 7-28: Hard Memory Controllers in Arria V SX B3 and B5 Devices, and Arria V ST D3 and D5 Devices
This figure shows the bonding of opposite and same side hard memory controllers through the core fabric.
32-bit DDR3 Interface
Bank 8
HPS I/O
Bonding
(Core Routing)
No bonding support for
the HPS hard memory
controller.
32-bit DDR3 Interface
HPS Block
HPS I/O
HPS Hard Memory Controller
Hard Memory Controller
Enabled only for single hard memory
controller bond out per side. This
bonding is available only if you do not
use the hard memory controllers in
bank 3 for bonding with other banks.
Bonding
(Core Routing)
Hard Memory Controller
Hard Memory Controller
Bank 3
Bank 4
32-bit DDR3 Interface
32-bit DDR3 Interface
Related Information
• Bonding Does Not Work for Multiple MPFE Ports in Hard Memory Controller
• Arria V GT and GX Device Family Pin Connection Guidelines
Provides more information about the dedicated pins.
Hard Memory Controller Width for Arria V GX
Table 7-18: Hard Memory Controller Width Per Side in Arria V GX A1, A3, A5, and A7 Devices—Preliminary
Member Code
Package
A1
A3
A5
A7
Top
Bottom
Top
Bottom
Top
Bottom
Top
Bottom
F672
16
16
16
16
32
32
32
32
F896
24
24
24
24
32
32
32
32
F1152
—
—
—
—
64
64
64
64
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Hard Memory Controller Width for Arria V GT
Table 7-19: Hard Memory Controller Width Per Side in Arria V GX B1, B3, B5, and B7 Devices—Preliminary
Member Code
Package
B1
B3
B5
B7
Top
Bottom
Top
Bottom
Top
Bottom
Top
Bottom
F896
32
32
32
32
—
—
—
—
F1152
64
64
64
64
64
64
64
64
F1517
72
72
72
72
72
72
72
72
Hard Memory Controller Width for Arria V GT
Table 7-20: Hard Memory Controller Width Per Side in Arria V GT Devices—Preliminary
Member Code
Package
C3
C7
D3
D7
Top
Bottom
Top
Bottom
Top
Bottom
Top
Bottom
F672
16
16
—
—
—
—
—
—
F896
24
24
32
32
32
32
—
—
F1152
—
—
64
64
64
64
64
64
F1157
—
—
—
—
72
72
72
72
Hard Memory Controller Width for Arria V SX
Table 7-21: FPGA Hard Memory Controller Width Per Side in Arria V SX Devices—Preliminary
Member Code
Package
B3
B5
Top
Bottom
Top
Bottom
F896
40
16
40
16
F1152
40
80
40
80
F1517
40
80
40
80
Table 7-22: HPS Hard Memory Controller Width in Arria V SX Devices—Preliminary
Package
Member Code
B3
B5
F896
40
40
F1152
40
40
F1517
40
40
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Hard Memory Controller Width for Arria V ST
Hard Memory Controller Width for Arria V ST
Table 7-23: FPGA Hard Memory Controller Width Per Side in Arria V ST Devices—Preliminary
Member Code
Package
D3
D5
Top
Bottom
Top
Bottom
F896
40
16
40
16
F1152
40
80
40
80
F1517
40
80
40
80
Table 7-24: HPS Hard Memory Controller Width in Arria V ST Devices—Preliminary
Package
Member Code
D3
D5
F896
40
40
F1152
40
40
F1517
40
40
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Document Revision History
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Document Revision History
Date
Version
January 2014
2014.01.10
• Reduced the soft memory controller performance for DDR3 1.35 V in
Arria V GX, GT, SX, and ST devices from 667 MHz to 600 MHz.
• Removed support for DDR2 in the HPS hard memory controller.
• Updated the figure that shows the delay chains in the Arria V GZ I/O
block.
• Added related information link to ALTDQ_DQS2 Megafunction User
Guide for more information about using the delay chains.
• Changed all "SoC FPGA" to "SoC".
• Updated the figure that shows the DQS/CQ/CQn/QK# Pins and DLLs
in Arria V GX A1 and A3 to add the DLL reference clock to the left side
DLL.
• Updated the topic about delay-locked loop (DLL) to specify that there
is a maximum of five DLLs (instead of four).
• Updated the topic about the PHYCLK networks to add information
about using the PHYCLK network to drive the I/O sub-banks in each
I/O bank.
• Added links to Altera's External Memory Spec Estimator tool to the
topics listing the external memory interface performance.
• Updated topic about hard memory controller bonding support to specify
that bonding is supported only for hard memory controllers configured
with one port.
May 2013
2013.05.06
• Moved all links to the Related Information section of respective topics
for easy reference.
• Added link to the known document issues in the Knowledge Base.
• Updated the topic about Arria V GZ leveling circuitry.
• Removed the Arria V GZ phase offset control topic.
• Added the I/O and DQS configuration blocks topic.
• Updated the DQ/DQS groups for Arria V GX.
• Added the DQ/DQS groups for Arria V GT C3 and C7.
• Added the DLL reference clock input tables for all Arria V devices.
• Added the FPGA hard memory controller widths for Arria V GX, GT,
SX, and ST.
• Added the HPS hard memory controller widths for Arria V SX and ST.
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Document Revision History
Date
November 2012
June 2012
Version
2012.11.19
2.0
Changes
• Reorganized content and updated template.
• Added information for Arria V GZ, including a topic on the leveling
circuitry.
• Added a list of supported external memory interface standards using
the hard memory controller and soft memory controller.
• Added performance information for external memory interfaces and
the HPS external memory interfaces.
• Separated the DQ/DQS groups tables into separate topics for each device
variant for easy reference.
• Moved the PHYCLK networks pin placement guideline to the Planning
Pin and FPGA Resources chapter of the External Memory Interface
Handbook.
• Moved information from the "Design Considerations" section into
relevant topics.
• Removed the "DDR2 SDRAM Interface" and "DDR3 SDRAM DIMM"
sections. Refer to the relevant sections in the External Memory Interface
Handbook for the information.
• Updated the diagram for DQS/CQ/CQn/QK# pins and DLLs in Arria
V GX A1 and A3 devices to add DLLs on the right, top left, and bottom
left, and update the DLL connections to the pins.
• Updated the term "Multiport logic" to "multi-port front end" (MPFE).
Updated for the Quartus II software v12.0 release:
• Restructured chapter.
• Updated “Design Considerations”, “DQS Postamble Circuitry”, and
“IOE Registers”sections.
• Added SoC devices information.
• Added Figure 7–4, Figure 7–8, and Figure 7–20.
November 2011
1.1
• Updated Table 7–2.
• Added “PHY Clock (PHYCLK) Networks” and “UniPHY IP” sections.
• Restructured chapter.
May 2011
1.0
Initial release.
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This chapter describes the configuration schemes, design security, and remote system upgrade that are
supported by the Arria V devices.
Related Information
• Arria V Device Handbook: Known Issues
Lists the planned updates to the Arria V Device Handbook chapters.
• Arria V Device Overview
Provides more information about configuration features supported for each configuration scheme.
• Arria V Device Datasheet
Provides more information about the estimated uncompressed .rbf file sizes, FPP DCLK-to-DATA[] ratio,
and timing parameters.
• Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide
Provides more information about the CvP configuration scheme.
• Hard Processor System Technical Reference Manual
Provides more information about configuration via HPS configuration scheme.
• Design Planning for Partial Reconfiguration
Provides more information about partial reconfiguration.
© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words
and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other
words and logos identified as trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with
Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes
no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published
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Enhanced Configuration and Configuration via Protocol
Enhanced Configuration and Configuration via Protocol
Table 8-1: Configuration Modes and Features of Arria V Devices
Arria V devices support 1.8 V, 2.5 V, 3.0 V, and 3.3 V(21) programming voltages and several configuration modes.
Mode
Data
Width
Max Clock Max Data Decompression
Rate
Rate
(MHz)
(Mbps)
Design
Security
Partial
(22)
Reconfiguration
Remote System
Update
AS through the
EPCS and EPCQ
serial configuration device
1 bit, 4
bits
100
—
Yes
Yes
—
Yes
PS through CPLD
or external
microcontroller
1 bit
125
125
Yes
Yes
—
—
8 bits
125
—
Yes
Yes
—
16 bits
125
—
Yes
Yes
Yes(23)
32 bits(24)
100
—
Yes
Yes
—
x1, x2, x4,
and x8
lanes
—
—
Yes
Yes
Yes
—
1 bit
33
33
—
—
—
—
16 bits
125
—
Yes
Yes
Yes(23)
32 bits
100
—
Yes
Yes
—
FPP
CvP (PCIe)
JTAG
Configuration via
HPS
Parallel flash loader
Parallel flash loader
Instead of using an external flash or ROM, you can configure the Arria V devices through PCIe using CvP.
The CvP mode offers the fastest configuration rate and flexibility with the easy-to-use PCIe hard IP block
interface. The Arria V CvP implementation conforms to the PCIe 100 ms power-up-to-active time requirement.
Note: Although Arria V GZ devices support PCIe Gen3, you can use only PCIe Gen1 and PCIe Gen2 for
CvP configuration scheme.
Related Information
Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide
Provides more information about the CvP configuration scheme.
(21)
(22)
(23)
(24)
Arria V GZ does not support 3.3 V.
Partial reconfiguration is an advanced feature of the device family. If you are interested in using partial
reconfiguration, contact Altera for support.
Supported at a clock rate of 50-62.5 MHz.
Arria V GZ only
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MSEL Pin Settings
8-3
MSEL Pin Settings
To select a configuration scheme, hardwire the MSEL pins to VCCPGM or GND without pull-up or pull-down
resistors.
Note: Do not drive the MSEL pins with a microprocessor or another device.
Table 8-2: MSEL Pin Settings for Each Configuration Scheme of Arria V Devices
Configuration
Scheme
VCCPGM (V)
(25)
Power-On
Reset (POR)
Delay
Valid
MSEL[4..0]
Device Variant Support
Disabled
1.8/2.5/3.0/ Fast
3.3
Standard
10100
All
11000
All
Disabled
Enabled
1.8/2.5/3.0/ Fast
3.3
Standard
10101
All
11001
All
Enabled
Enabled/
Disabled
1.8/2.5/3.0/ Fast
3.3
Standard
10110
All
11010
All
Disabled
Disabled
1.8/2.5/3.0/ Fast
3.3
Standard
00000
All
00100
All
Disabled
Enabled
1.8/2.5/3.0/ Fast
3.3
Standard
00001
All
00101
All
Enabled
Enabled/
Disabled
1.8/2.5/3.0/ Fast
3.3
Standard
00010
All
00110
All
Disabled
Disabled
1.8/2.5/3.0
Fast
01000
Arria V GZ
Standard
01100
Arria V GZ
Disabled
Enabled
1.8/2.5/3.0
Fast
01001
Arria V GZ
Standard
01101
Arria V GZ
Enabled
Enabled/
Disabled
1.8/2.5/3.0
Fast
01010
Arria V GZ
Standard
01110
Arria V GZ
PS
Enabled/
Disabled
Enabled/
Disabled
1.8/2.5/3.0/ Fast
3.3
Standard
10000
All
10001
All
AS (x1 and x4)
Enabled/
Disabled
Enabled/
Disabled
3.0/3.3
Fast
10010
All
Standard
10011
All
FPP x16
FPP x32
(26)
Design
Security
Feature
Disabled
FPP x8
(25)
Compression
Feature
(26)
(26)
The Arria V GZ device does not support 3.3 V.
For configuration with HPS in SoC FPGA devices, refer to the FPGA Manager for the related MSEL pin settings.
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Configuration Sequence
Configuration
Scheme
Compression
Feature
JTAG-based
configuration
Disabled
Design
Security
Feature
Disabled
VCCPGM (V)
(25)
—
Power-On
Reset (POR)
Delay
—
Valid
MSEL[4..0]
Device Variant Support
Use any
All
valid MSEL
pin settings
above
Note: You must also select the configuration scheme in the Configuration page of the Device and Pin
Options dialog box in the Quartus II software. Based on your selection, the option bit in the
programming file is set accordingly.
Related Information
• FPGA Manager
Provides more information about the MSEL pin settings for configuration with hard processor system
(HPS) in system on a chip (SoC) FPGA devices.
• Arria V GT and GX Device Family Pin Connection Guidelines
Provides more information about JTAG pins voltage-level connection.
• Arria V GZ Device Family Pin Connection Guidelines
Provides more information about JTAG pins voltage-level connection.
Configuration Sequence
Describes the configuration sequence and each configuration stage.
(25)
The Arria V GZ device does not support 3.3 V.
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Power Up
8-5
Figure 8-1: Configuration Sequence for Arria V Devices
Power Up
• nSTATUS and CONF_DONE
driven low
• All I/Os pins are tied to an
internal weak pull-up
• Clears configuration RAM bits
Power supplies including VCCPD and VCCPGM reach
recommended operating voltage
Reset
• nSTATUS and CONF_DONE
remain low
• All I/Os pins are tied to an
internal weak pull-up
• Samples MSEL pins
nSTATUS and nCONFIG released high
CONF_DONE pulled low
Configuration Error Handling
• nSTATUS pulled low
• CONF_DONE remains low
• Restarts configuration if option
enabled
Configuration
Writes configuration data to
FPGA
CONF_DONE released high
Initialization
• Initializes internal logic and
registers
• Enables I/O buffers
INIT_DONE released high
(if option enabled)
User Mode
Executes your design
You can initiate reconfiguration by pulling the nCONFIG pin low to at least the minimum tCFG low-pulse
width except for configuration using the partial reconfiguration operation. When this pin is pulled low, the
nSTATUS and CONF_DONE pins are pulled low and all I/O pins are tied to an internal weak pull-up.
Power Up
Power up all the power supplies that are monitored by the POR circuitry. All power supplies, including
VCCPGM and VCCPD, must ramp up from 0 V to the recommended operating voltage level within the rampup time specification. Otherwise, hold the nCONFIG pin low until all the power supplies reach the recommended
voltage level.
VCCPGM Pin
The configuration input buffers do not have to share power lines with the regular I/O buffers in Arria V
devices.
The operating voltage for the configuration input pin is independent of the I/O banks power supply, VCCIO,
during configuration. Therefore, Arria V devices do not require configuration voltage constraints on VCCIO.
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Reset
VCCPD Pin
Use the VCCPD pin, a dedicated programming power supply, to power the I/O pre-drivers and JTAG I/O
pins (TCK, TMS, TDI, and TDO).
The supported configuration voltages are 2.5, 3.0, and 3.3 V for all Arria V devices except for Arria V GZ
devices. The supported configuration voltages for Arria V GZ devices are 2.5 and 3.0 V.
If VCCIO of the bank is set to 2.5 V or lower, VCCPD must be powered up at 2.5 V. If VCCIO is set greater than
2.5 V, VCCPD must be greater than VCCIO. For example, when VCCIO is set to 3.0 V, VCCPD must be set at
3.0 V or above. When VCCIO is set to 3.3 V, VCCPD must be set at 3.3 V.
Related Information
• Arria V Device Datasheet
Provides more information about the ramp-up time specifications.
• Arria V GT and GX Device Family Pin Connection Guidelines
Provides more information about configuration pin connections.
• Arria V GZ Device Family Pin Connection Guidelines
Provides more information about configuration pin connections.
• Device Configuration Pins on page 8-7
Provides more information about configuration pins.
• I/O Standards Voltage Levels in Arria V Devices on page 5-8
Provides more information about typical power supplies for each supported I/O standards in Arria V
devices.
Reset
POR delay is the time frame between the time when all the power supplies monitored by the POR circuitry
reach the recommended operating voltage and when nSTATUS is released high and the Arria V device is
ready to begin configuration.
Set the POR delay using the MSEL pins.
The user I/O pins are tied to an internal weak pull-up until the device is configured.
Related Information
• MSEL Pin Settings on page 8-3
• Arria V Device Datasheet
Provides more information about the POR delay specification.
Configuration
For more information about the DATA[] pins for each configuration scheme, refer to the appropriate
configuration scheme.
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Configuration Error Handling
8-7
Configuration Error Handling
To restart configuration automatically, turn on the Auto-restart configuration after error option in the
General page of the Device and Pin Options dialog box in the Quartus II software.
If you do not turn on this option, you can monitor the nSTATUS pin to detect errors. To restart configuration,
pull the nCONFIG pin low for at least the duration of tCFG.
Related Information
Arria V Device Datasheet
Provides more information about tSTATUS and tCFG timing parameters.
Initialization
The initialization clock source is from the internal oscillator, CLKUSR pin, or DCLK pin. By default, the internal
oscillator is the clock source for initialization. If you use the internal oscillator, the Arria V device will be
provided with enough clock cycles for proper initialization.
Note: If you use the optional CLKUSR pin as the initialization clock source and the nCONFIG pin is pulled
low to restart configuration during device initialization, ensure that the CLKUSR or DCLK pin continues
toggling until the nSTATUS pin goes low and then goes high again.
The CLKUSR pin provides you with the flexibility to synchronize initialization of multiple devices or to delay
initialization. Supplying a clock on the CLKUSR pin during initialization does not affect configuration. After
the CONF_DONE pin goes high, the CLKUSR or DCLK pin is enabled after the time specified by tCD2CU. When
this time period elapses, Arria V devices require a minimum number of clock cycles as specified by Tinit to
initialize properly and enter user mode as specified by the tCD2UMC parameter.
Related Information
Arria V Device Datasheet
Provides more information about tCD2CU, tinit, and tCD2UMC timing parameters, and initialization clock
source.
User Mode
You can enable the optional INIT_DONE pin to monitor the initialization stage. After the INIT_DONE pin is
pulled high, initialization completes and your design starts executing. The user I/O pins will then function
as specified by your design.
Device Configuration Pins
Configuration Pins Summary
The following table lists the Arria V configuration pins and their power supply.
Note: The TDI, TMS, TCK, and TDO pins are powered by VCCPD of the bank in which the pin resides.
Note: The CLKUSR, DEV_OE, DEV_CLRn, DATA[15..5], and DATA[31..16] pins are powered by VCCPGM
during configuration and by VCCIO of the bank in which the pin resides if you use it as a user I/O
pin.
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Device Configuration Pins
Table 8-3: Configuration Pin Summary for Arria V Devices
Configuration Pin
Configuration
Scheme
Input/Output
User Mode
TDI
JTAG
Input
—
VCCPD
TMS
JTAG
Input
—
VCCPD
TCK
JTAG
Input
—
VCCPD
TDO
JTAG
Output
—
VCCPD
CLKUSR
All
schemes
Input
I/O
VCCPGM/VCCIO (29)
CRC_ERROR
Optional, Output
all schemes
I/O
Pull-up
CONF_DONE
All
schemes
—
VCCPGM/Pull-up
FPP and PS Input
—
VCCPGM
AS
—
VCCPGM
Bidirectional
DCLK
Output
DEV_OE
Optional, Input
all schemes
I/O
VCCPGM/VCCIO (29)
DEV_CLRn
Optional, Input
all schemes
I/O
VCCPGM/VCCIO (29)
INIT_DONE
Optional, Output
all schemes
I/O
Pull-up
MSEL[4..0]
All
schemes
Input
—
VCCPGM
nSTATUS
All
schemes
Bidirectional
—
VCCPGM/Pull-up
nCE
All
schemes
Input
—
VCCPGM
nCEO
All
schemes
Output
I/O
Pull-up
nCONFIG
All
schemes
Input
—
VCCPGM
nIO_PULLUP
All
schemes
Input
—
VCCPGM
DATA[15..5]
FPP x8 and Input
x16
I/O
VCCPGM/VCCIO (29)
FPP x32
I/O
VCCPGM/VCCIO (29)
(27)
DATA[31..16]
(27)
Powered By
(27)
Input
These pins are applicable for Arria V GZ devices only.
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Configuration Pin Options in the Quartus II Software
Configuration Pin
(27)
Configuration
Scheme
Input/Output
User Mode
Powered By
FPP x8,
x16, and
x32
Input
I/O
VCCPGM/VCCIO (29)
AS
Output
—
VCCPGM
FPP
Input
—
VCCPGM
AS
Bidirectional
—
VCCPGM
FPP
Input
—
VCCPGM
AS
Bidirectional
—
VCCPGM
FPP and PS Input
—
VCCPGM
(27)
AS
Bidirectional
—
VCCPGM
AS_DATA[3..1]
(27)
AS
Bidirectional
—
VCCPGM
PR_REQUEST
Partial
Input
Reconfiguration
I/O
VCCPGM/VCCIO (29)
PR_READY
Partial
Output
Reconfiguration
I/O
VCCPGM/VCCIO (29)
PR_ERROR
Partial
Output
Reconfiguration
I/O
VCCPGM/VCCIO (29)
PR_DONE
Partial
Output
Reconfiguration
I/O
VCCPGM/VCCIO (29)
DATA[4..0]
nCSO/DATA4
(28)
AS_DATA[3..1]/DATA[3..1]
(28)
AS_DATA0/DATA0/ASDO
(28)
AS_DATA0/ASDO
8-9
Related Information
• Arria V GT and GX Device Family Pin Connection Guidelines
Provides more information about each configuration pin.
• Arria V GZ Device Family Pin Connection Guidelines
Provides more information about each configuration pin.
Configuration Pin Options in the Quartus II Software
The following table lists the dual-purpose configuration pins available in the Device and Pin Options dialog
box in the Quartus II software.
Table 8-4: Configuration Pin Options
Configuration Pin
CLKUSR
(28)
(29)
Category Page
General
Option
Enable user-supplied start-up clock
(CLKUSR)
These pins are applicable for all Arria V devices except for Arria V GZ devices.
This pin is powered by VCCPGM during configuration and powered by VCCIO of the bank in which the pin
resides when you use this pin as a user I/O pin.
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Fast Passive Parallel Configuration
Configuration Pin
Category Page
Option
DEV_CLRn
General
Enable device-wide reset (DEV_CLRn)
DEV_OE
General
Enable device-wide output enable
(DEV_OE)
INIT_DONE
General
Enable INIT_DONE output
nCEO
General
Enable nCEO pin
Enable Error Detection CRC_ERROR
pin
CRC_ERROR
Error Detection CRC
Enable open drain on CRC_ERROR
pin
Enable internal scrubbing
PR_REQUEST
PR_READY
General
Enable PR pin
PR_ERROR
PR_DONE
Related Information
Reviewing Printed Circuit Board Schematics with the Quartus II Software
Provides more information about the device and pin options dialog box setting.
Fast Passive Parallel Configuration
The FPP configuration scheme uses an external host, such as a microprocessor, MAX® II device, or MAX V
device. This scheme is the fastest method to configure Arria V devices. The FPP configuration scheme
supports 8- and 16-bits data width.
You can use an external host to control the transfer of configuration data from an external storage such as
flash memory to the FPGA. The design that controls the configuration process resides in the external host.
You can store the configuration data in Raw Binary File (.rbf), Hexadecimal (Intel-Format) File (.hex), or
Tabular Text File (.ttf) formats.
You can use the PFL megafunction with a MAX II or MAX V device to read configuration data from the
flash memory device and configure the Arria V device.
Note: Two DCLK falling edges are required after the CONF_DONE pin goes high to begin the initialization of
the device for both uncompressed and compressed configuration data in an FPP configuration.
Related Information
• Parallel Flash Loader Megafunction User Guide
• Arria V Device Datasheet
Provides more information about the FPP configuration timing.
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Fast Passive Parallel Single-Device Configuration
8-11
Fast Passive Parallel Single-Device Configuration
To configure an Arria V device, connect the device to an external host as shown in the following figure.
Figure 8-2: Single Device FPP Configuration Using an External Host
Connect the resistor to a supply that
provides an acceptable input signal
for the FPGA device. VCCPGM must be
high enough to meet the VIH
specification of the I/O on the device
and the external host. Altera
recommends powering up all
configuration system I/Os with VCCPGM.
Memory
ADDR DATA[7..0]
VCCPGM VCCPGM
10 kΩ
10 kΩ
FPGA Device
For more information, refer to
the MSEL pin settings.
MSEL[4..0]
External Host
(MAX II Device,
MAX V Device, or
Microprocessor)
CONF_DONE
nSTATUS
nCEO
nCE
GND
N.C.
DATA[]
nCONFIG
DCLK
You can leave the nCEO pin
unconnected or use it as a user
I/O pin when it does not feed
another device’s nCE pin.
Fast Passive Parallel Multi-Device Configuration
You can configure multiple Arria V devices that are connected in a chain.
Pin Connections and Guidelines
Observe the following pin connections and guidelines for this configuration setup:
• Tie the following pins of all devices in the chain together:
•
•
•
•
•
nCONFIG
nSTATUS
DCLK
DATA[]
CONF_DONE
By tying the CONF_DONE and nSTATUS pins together, the devices initialize and enter user mode at the same
time. If any device in the chain detects an error, configuration stops for the entire chain and you must
reconfigure all the devices. For example, if the first device in the chain flags an error on the nSTATUS pin,
it resets the chain by pulling its nSTATUS pin low.
• Ensure that DCLK and DATA[] are buffered for every fourth device to prevent signal integrity and clock
skew problems.
• All devices in the chain must use the same data width.
• If you are configuring the devices in the chain using the same configuration data, the devices must be of
the same package and density.
Using Multiple Configuration Data
To configure multiple Arria V devices in a chain using multiple configuration data, connect the devices to
an external host as shown in the following figure.
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Using One Configuration Data
Figure 8-3: Multiple Device FPP Configuration Using an External Host When Both Devices Receive a Different
Set of Configuration Data
Connect the resistor to a supply
that provides an acceptable input
signal for the FPGA device.
VCCPGM must be high enough to
meet the VIH specification of the
I/O on the device and the external
host. Altera recommends
powering up all configuration
system I/Os with VCCPGM.
For more information, refer to
the MSEL pin settings.
Memory
VCCPGM VCCPGM
ADDR DATA[7..0]
10 kΩ
10 kΩ
FPGA Device Master
VCCPGM
FPGA Device Slave
MSEL[4..0]
External Host
(MAX II Device,
MAX V Device, or
Microprocessor)
nCE
MSEL[4..0]
10 kΩ
CONF_DONE
nSTATUS
nCEO
CONF_DONE
nSTATUS
nCE
GND
DATA[]
DATA[]
nCONFIG
DCLK
nCONFIG
DCLK
nCEO
N.C.
You can leave the nCEO pin
unconnected or use it as a user
I/O pin when it does not feed
another device’s nCE pin.
Buffers
Connect the repeater buffers between the
FPGA master and slave device for DATA[]
and DCLK for every fourth device.
When a device completes configuration, its nCEO pin is released low to activate the nCE pin of the next device
in the chain. Configuration automatically begins for the second device in one clock cycle.
Using One Configuration Data
To configure multiple Arria V devices in a chain using one configuration data, connect the devices to an
external host as shown in the following figure.
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Active Serial Configuration
8-13
Figure 8-4: Multiple Device FPP Configuration Using an External Host When Both Devices Receive the Same
Data
Connect the resistor to a supply that
provides an acceptable input signal for the
FPGA device. VCCPGM must be high
enough to meet the VIH specification of
the I/O on the device and the external
host. Altera recommends powering up all
configuration system I/Os with VCCPGM.
Memory
For more information, refer to
the MSEL pin settings.
VCCPGM VCCPGM
ADDR DATA[7..0]
10 kΩ
External Host
(MAX II Device,
MAX V Device, or
Microprocessor)
FPGA Device Slave
FPGA Device Master
10 kΩ
MSEL[4..0]
MSEL[4..0]
CONF_DONE
nSTATUS
nCEO
nCE
CONF_DONE
nSTATUS
nCEO
nCE
N.C.
GND
GND
DATA[]
nCONFIG
DCLK
DATA[]
nCONFIG
DCLK
N.C.
You can leave the nCEO pin
unconnected or use it as a user
I/O pin when it does not feed
another device’s nCE pin.
Buffers
Connect the repeater buffers between the
FPGA master and slave device for DATA[]
and DCLK for every fourth device.
The nCE pins of the device in the chain are connected to GND, allowing configuration for these devices to
begin and end at the same time.
Active Serial Configuration
The AS configuration scheme supports AS x1 (1-bit data width) and AS x4 (4-bit data width) modes. The
AS x4 mode provides four times faster configuration time than the AS x1 mode. In the AS configuration
scheme, the Arria V device controls the configuration interface.
Related Information
Arria V Device Datasheet
Provides more information about the AS configuration timing.
DATA Clock (DCLK)
Arria V devices generate the serial clock, DCLK, that provides timing to the serial interface. In the AS
configuration scheme, Arria V devices drive control signals on the falling edge of DCLK and latch the
configuration data on the following falling edge of this clock pin.
The maximum DCLK frequency supported by the AS configuration scheme is 100 MHz except for the AS
multi-device configuration scheme. You can source DCLK using CLKUSR or the internal oscillator. If you use
the internal oscillator, you can choose a 12.5, 25, 50, or 100 MHz clock under the Device and Pin Options
dialog box, in the Configuration page of the Quartus II software.
After power-up, DCLK is driven by a 12.5 MHz internal oscillator by default. The Arria V device determines
the clock source and frequency to use by reading the option bit in the programming file.
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Active Serial Single-Device Configuration
Related Information
Arria V Device Datasheet
Provides more information about the DCLK frequency specification in the AS configuration scheme.
Active Serial Single-Device Configuration
To configure an Arria V device, connect the device to a serial configuration (EPCS) device or quad-serial
configuration (EPCQ) device, as shown in the following figures.
Figure 8-5: Single Device AS x1 Mode Configuration
Connect the pull-up resistors to
VCCPGM at 3.0- or 3.3-V power supply.
VCCPGM
VCCPGM VCCPGM
10 kΩ
10 kΩ
10 kΩ
EPCS or EPCQ Device
FPGA Device
nSTATUS
CONF_DONE
nCONFIG
nCE
nCEO
N.C.
For more information,
refer to the MSEL pin
settings.
MSEL[4..0]
GND
DATA
DCLK
nCS
ASDI
AS_DATA1
DCLK
nCSO
ASDO
CLKUSR
Use the CLKUSR pin to
supply the external clock
source to drive DCLK
during configuration.
Figure 8-6: Single Device AS x4 Mode Configuration
Connect the pull-up resistors to
VCCPGM at 3.0- or 3.3-V power supply.
VCCPGM
VCCPGM VCCPGM
10 kΩ
10 kΩ
EPCQ Device
10 kΩ
FPGA Device
nSTATUS
CONF_DONE
nCONFIG
nCE
GND
DATA2
AS_DATA0/
ASDO
MSEL[4..0]
AS_DATA1
CLKUSR
AS_DATA2
DATA3
AS_DATA3
DATA0
DATA1
DCLK
nCS
Altera Corporation
nCEO
DCLK
nCSO
N.C.
For more information,
refer to the MSEL pin
settings.
Use the CLKUSR pin to
supply the external clock
source to drive DCLK
during configuration.
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Active Serial Multi-Device Configuration
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Active Serial Multi-Device Configuration
You can configure multiple Arria V devices that are connected to a chain. Only AS x1 mode supports
multi-device configuration.
The first device in the chain is the configuration master. Subsequent devices in the chain are configuration
slaves.
Pin Connections and Guidelines
Observe the following pin connections and guidelines for this configuration setup:
• Hardwire the MSEL pins of the first device in the chain to select the AS configuration scheme. For
subsequent devices in the chain, hardwire their MSEL pins to select the PS configuration scheme. Any
other Altera devices that support the PS configuration can also be part of the chain as a configuration
slave.
• Tie the following pins of all devices in the chain together:
•
•
•
•
•
nCONFIG
nSTATUS
DCLK
DATA[]
CONF_DONE
By tying the CONF_DONE, nSTATUS, and nCONFIG pins together, the devices initialize and enter user mode
at the same time. If any device in the chain detects an error, configuration stops for the entire chain and
you must reconfigure all the devices. For example, if the first device in the chain flags an error on the
nSTATUS pin, it resets the chain by pulling its nSTATUS pin low.
• Ensure that DCLK and DATA[] are buffered every fourth device to prevent signal integrity and clock skew
problems.
Using Multiple Configuration Data
To configure multiple Arria V devices in a chain using multiple configuration data, connect the devices to
an EPCS or EPCQ device, as shown in the following figure.
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Estimating the Active Serial Configuration Time
Figure 8-7: Multiple Device AS Configuration When Both Devices in the Chain Receive Different Sets of
Configuration Data
Connect the pull-up resistors to
VCCPGM at a 3.0- or 3.3-V power
supply.
VCCPGM
VCCPGM
VCCPGM
VCCPGM
10 kΩ
10 kΩ
10 kΩ
10 kΩ
EPCS or EPCQ Device
FPGA Device Master
FPGA Device Slave
nSTATUS
nSTATUS
CONF_DONE
CONF_DONE
nCONFIG
nCE
nCONFIG
nCEO
nCE
nCEO
You can leave the nCEO pin
unconnected or use it as a user I/O
pin when it does not feed another
device’s nCE pin.
GND
DATA
DCLK
AS_DATA1
DCLK
nCS
ASDI
nCSO
ASDO
MSEL[4..0]
CLKUSR
DATA0
DCLK
MSEL [4..0]
For the appropriate MSEL settings
based on POR delay settings, set the
slave device MSEL setting to the PS
scheme.
Buffers
For more information, refer to the
MSEL pin settings.
Connect the repeater buffers between the
FPGA master and slave device for AS_DATA1
Use the CLKUSR pin to supply the
external clock source to drive DCLK
during configuration.
or DATA0 and DCLK for every fourth device.
When a device completes configuration, its nCEO pin is released low to activate the nCE pin of the next device
in the chain. Configuration automatically begins for the second device in one clock cycle.
Estimating the Active Serial Configuration Time
The AS configuration time is mostly the time it takes to transfer the configuration data from an EPCS or
EPCQ device to the Arria V device.
Use the following equations to estimate the configuration time:
• AS x1 mode
.rbf Size x (minimum DCLK period / 1 bit per DCLK cycle) = estimated minimum configuration time.
• AS x4 mode
.rbf Size x (minimum DCLK period / 4 bits per DCLK cycle) = estimated minimum configuration time.
Compressing the configuration data reduces the configuration time. The amount of reduction varies depending
on your design.
Using EPCS and EPCQ Devices
EPCS devices support AS x1 mode and EPCQ devices support AS x1 and AS x4 modes.
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Controlling EPCS and EPCQ Devices
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Related Information
• Serial Configuration (EPCS) Devices Datasheet
• Quad-Serial Configuration (EPCQ) Devices Datasheet
Controlling EPCS and EPCQ Devices
During configuration, Arria V devices enable the EPCS or EPCQ device by driving its nCSO output pin low,
which connects to the chip select (nCS) pin of the EPCS or EPCQ device. Arria V devices use the DCLK and
ASDO pins to send operation commands and read address signals to the EPCS or EPCQ device. The EPCS
or EPCQ device provides data on its serial data output (DATA[]) pin, which connects to the AS_DATA[] input
of the Arria V devices.
Note: If you wish to gain control of the EPCS pins, hold the nCONFIG pin low and pull the nCE pin high.
This causes the device to reset and tri-state the AS configuration pins.
Trace Length and Loading
The maximum trace length and loading apply to both single- and multi-device AS configuration setups as
listed in the following table. The trace length is the length from the Arria V device to the EPCS or EPCQ
device.
Table 8-5: Maximum Trace Length and Loading for AS x1 and x4 Configurations for Arria V Devices
Maximum Board Trace Length (Inches)
Arria V Device AS Pins
12.5/ 25/ 50 MHz
Maximum Board Load (pF)
100 MHz
DCLK
10
6
5
DATA[3..0]
10
6
10
nCSO
10
6
10
Programming EPCS and EPCQ Devices
You can program EPCS and EPCQ devices in-system using a USB-Blaster™, EthernetBlaster, EthernetBlaster II,
or ByteBlaster™ II download cable. Alternatively, you can program the EPCS or EPCQ using a microprocessor
with the SRunner software driver.
In-system programming (ISP) offers you the option to program the EPCS or EPCQ either using an AS
programming interface or a JTAG interface. Using the AS programming interface, the configuration data
is programmed into the EPCS by the Quartus II software or any supported third-party software. Using the
JTAG interface, an Altera IP called the serial flash loader (SFL) must be downloaded into the Arria V device
to form a bridge between the JTAG interface and the EPCS or EPCQ. This allows the EPCS or EPCQ to be
programmed directly using the JTAG interface.
Related Information
• AN 370: Using the Serial FlashLoader with the Quartus II Software
• AN 418: SRunner: An Embedded Solution for Serial Configuration Device Programming
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Programming EPCS Using the JTAG Interface
Programming EPCS Using the JTAG Interface
To program an EPCS device using the JTAG interface, connect the device as shown in the following figure.
Figure 8-8: Connection Setup for Programming the EPCS Using the JTAG Interface
VCCPGM
VCCPGM VCCPGM
10 kΩ
10 kΩ
EPCS Device
Connect the pull-up
resistors to VCCPGM at a
3.0- or 3.3-V power supply.
10 kΩ
VCCPD VCCPD
FPGA Device
nSTATUS
CONF_DONE
nCONFIG
nCE
TCK
TDO
VCCPD
TMS
TDI
Pin 1
GND
DATA
DCLK
nCS
ASDI
For more information, refer to
the MSEL pin settings.
Use the CLKUSR pin to supply
the external clock source to drive
DCLK during configuration.
The resistor value can vary
from 1 kΩ to 10 kΩ. Perform
signal integrity analysis to
select the resistor value for
your setup.
AS_DATA1
DCLK
nCSO
ASDO
Serial
Flash
Loader
MSEL[4..0]
CLKUSR
Instantiate SFL in your
design to form a bridge
between the EPCS and the
10-pin header.
1 kΩ
Download Cable
GND10-Pin Male Header GND
(JTAG Mode) (Top View)
Programming EPCQ Using the JTAG Interface
To program an EPCQ device using the JTAG interface, connect the device as shown in the following figure.
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Figure 8-9: Connection Setup for Programming the EPCQ Using the JTAG Interface
VCCPGM VCCPGM VCCPGM
10 kΩ
10 kΩ
10 kΩ
EPCQ Device
Connect the pull-up resistors to
VCCPGM at a 3.0- or 3.3-V
power supply.
VCCPD VCCPD
FPGA Device
nSTATUS
CONF_DONE
nCONFIG
nCE
TCK
TDO
VCCPD
TMS
TDI
Pin 1
GND
DATA0
AS_DATA0/ASDO
DATA1
AS_DATA1
DATA2
DATA3
DCLK
AS_DATA2
AS_DATA3
DCLK
nCS
nCSO
Serial
Flash
Loader
MSEL[4..0]
CLKUSR
Instantiate SFL in your
design to form a bridge
between the EPCQ and
the 10-pin header.
The resistor value can vary
from 1 kΩ to 10 kΩ. Perform
signal integrity analysis to
select the resistor value for your
setup.
1 kΩ
Download Cable
GND 10-Pin Male Header GND
(JTAG Mode) (Top View)
For more information, refer to
the MSEL pin settings.
Use the CLKUSR pin to supply the external clock
source to drive DCLK during configuration.
Programming EPCS Using the Active Serial Interface
To program an EPCS device using the AS interface, connect the device as shown in the following figure.
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Figure 8-10: Connection Setup for Programming the EPCS Using the AS Interface
Connect the pull-up resistors to VCCPGM
at a 3.0- or 3.3-V power supply.
VCCPGM
VCCPGM
VCCPGM
10 kΩ 10 kΩ 10 kΩ
FPGA Device
CONF_DONE
nCEO
nSTATUS
nCONFIG
N.C.
EPCS Device
nCE
10 kΩ
DATA
DCLK
nCS
ASDI
AS_DATA1
DCLK
nCSO
ASDO
Pin 1
VCCPGM
For more information, refer
to the MSEL pin settings.
MSEL[4..0]
CLKUSR
Use the CLKUSR pin to
supply the external clock
source to drive DCLK
during configuration.
Power up the USB-Blaster,
ByteBlaster II, EthernetBlaster, or
EthernetBlaster II cable’s VCC(TRGT)
to VCCPGM.
USB-Blaster or ByteBlaster II
(AS Mode)
GND
10-Pin Male Header
Programming EPCQ Using the Active Serial Interface
To program an EPCQ device using the AS interface, connect the device as shown in the following figure.
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Figure 8-11: Connection Setup for Programming the EPCQ Using the AS Interface
Using the AS header, the programmer serially transmits the operation commands and configuration bits to
the EPCQ on DATA0. This is equivalent to the programming operation for the EPCS.
Connect the pull-up resistors to VCCPGM
at a 3.0- or 3.3-V power supply.
VCCPGM
VCCPGM
VCCPGM
10 kΩ 10 kΩ 10 kΩ
FPGA Device
CONF_DONE
nSTATUS
nCONFIG
nCE
EPCQ Device
nCEO
N.C.
10 kΩ
DATA0
DATA1
AS_DATA0/ASDO
AS_DATA1
DATA2
DATA3
AS_DATA2
AS_DATA3
DCLK
nCS
DCLK
nCSO
Pin 1
VCCPGM
For more information, refer to
the MSEL pin settings.
MSEL[4..0]
CLKUSR
Use the CLKUSR pin to supply
the external clock source to
drive DCLK during
configuration.
Power up the USB-Blaster, ByteBlaster II,
EthernetBlaster, or EthernetBlaster II cable’s
VCC(TRGT) to VCCPGM.
USB-Blaster or ByteBlaster II
GND
(AS Mode)
10-Pin Male Header
When programming the EPCS and EPCQ devices, the download cable disables access to the AS interface
by driving the nCE pin high. The nCONFIG line is also pulled low to hold the Arria V device in the reset stage.
After programming completes, the download cable releases nCE and nCONFIG, allowing the pull-down and
pull-up resistors to drive the pin to GND and VCCPGM, respectively.
During the EPCQ programming using the download cable, DATA0 transfers the programming data, operation
command, and address information from the download cable into the EPCQ. During the EPCQ verification
using the download cable, DATA1 transfers the programming data back to the download cable.
Passive Serial Configuration
The PS configuration scheme uses an external host. You can use a microprocessor, MAX II device, MAX V
device, or a host PC as the external host.
You can use an external host to control the transfer of configuration data from an external storage such as
flash memory to the FPGA. The design that controls the configuration process resides in the external host.
You can store the configuration data in Programmer Object File (.pof), .rbf, .hex, or .ttf. If you are using
configuration data in .rbf, .hex, or .ttf, send the LSB of each data byte first. For example, if the .rbf contains
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Passive Serial Single-Device Configuration Using an External Host
the byte sequence 02 1B EE 01 FA, the serial data transmitted to the device must be 0100-0000 1101-1000
0111-0111 1000-0000 0101-1111.
You can use the PFL megafunction with a MAX II or MAX V device to read configuration data from the
flash memory device and configure the Arria V device.
For a PC host, connect the PC to the device using a download cable such as the Altera USB-Blaster USB
port, ByteBlaster II parallel port, EthernetBlaster, and EthernetBlaster II download cables.
The configuration data is shifted serially into the DATA0 pin of the device.
If you are using the Quartus II programmer and the CLKUSR pin is enabled, you do not need to provide a
clock source for the pin to initialize your device.
Related Information
• Parallel Flash Loader Megafunction User Guide
• Arria V Device Datasheet
Provides more information about the PS configuration timing.
Passive Serial Single-Device Configuration Using an External Host
To configure an Arria V device, connect the device to an external host, as shown in the following figure.
Figure 8-12: Single Device PS Configuration Using an External Host
Memory
ADDR
VCCPGM VCCPGM
DATA0
10 kΩ
External Host
(MAX II Device,
MAX V Device, or
Microprocessor
Connect the resistor to a power supply that provides an acceptable
input signal for the FPGA device. VCCPGM must be high enough to
meet the VIH specification of the I/O on the device and the external
host. Altera recommends powering up all the configuration system
I/Os with VCCPGM.
FPGA Device
10 kΩ
CONF_DONE
nSTATUS
nCE
GND
nCEO
N.C.
You can leave the nCEO pin
unconnected or use it as a user
I/O pin when it does not feed
another device’s nCE pin.
DATA0
nCONFIG
DCLK
MSEL[4..0]
For more information, refer to
the MSEL pin settings.
Passive Serial Single-Device Configuration Using an Altera Download Cable
To configure an Arria V device, connect the device to a download cable, as shown in the following figure.
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Figure 8-13: Single Device PS Configuration Using an Altera Download Cable
VCCPGM
10 kΩ
VCCPGM
VCCPGM
10 kΩ
VCCPGM
10 kΩ
VCCPGM
10 kΩ
FPGA Device
CONF_DONE
nSTATUS
10 kΩ
Connect the pull-up resistor to the
same supply voltage (VCCIO) as the
USB-Blaster, ByteBlaster II,
EthernetBlaster, or EthernetBlaster II
cable.
MSEL[4..0]
nCE
GND
nCEO
N.C.
DCLK
DATA0
nCONFIG
Download Cable
10-Pin Male Header
(PS Mode)
Pin 1
VCCIO
VIO
You only need the pull-up resistors on
DATA0 and DCLK if the download
cable is the only configuration scheme
used on your board. This ensures that
DATA0 and DCLK are not left floating
after configuration. For example, if you
are also using a MAX II device, MAX V
device, or microprocessor, you do not
need the pull-up resistors on DATA0
and DCLK.
For more information,
refer to the MSEL pin
settings.
Shield
GND
GND
In the USB-Blaster and
ByteBlaster II cables, this
pin is connected to nCE
when you use it for AS
programming. Otherwise,
this pin is a no connect.
Passive Serial Multi-Device Configuration
You can configure multiple Arria V devices that are connected in a chain.
Pin Connections and Guidelines
Observe the following pin connections and guidelines for this configuration setup:
• Tie the following pins of all devices in the chain together:
•
•
•
•
•
nCONFIG
nSTATUS
DCLK
DATA0
CONF_DONE
By tying the CONF_DONE and nSTATUS pins together, the devices initialize and enter user mode at the same
time. If any device in the chain detects an error, configuration stops for the entire chain and you must
reconfigure all the devices. For example, if the first device in the chain flags an error on the nSTATUS pin,
it resets the chain by pulling its nSTATUS pin low.
• If you are configuring the devices in the chain using the same configuration data, the devices must be of
the same package and density.
Using Multiple Configuration Data
To configure multiple Arria V devices in a chain using multiple configuration data, connect the devices to
the external host as shown in the following figure.
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Figure 8-14: Multiple Device PS Configuration when Both Devices Receive Different Sets of Configuration
Data
Connect the resistor to a power supply that provides an acceptable input signal for
the FPGA device. VCCPGM must be high enough to meet the VIH specification of the
I/O on the device and the external host. Altera recommends powering up all the
configuration system I/Os with VCCPGM.
Memory
ADDR
VCCPGM VCCPGM
DATA0
10 kΩ
FPGA Device 1 VCCPGM
10 kΩ
CONF_DONE
nSTATUS
nCEO
nCE
External Host
(MAX II Device,
MAX V Device, or
Microprocessor
10 kΩ
FPGA Device 2
CONF_DONE
nSTATUS
nCE
GND
DATA0
nCONFIG
MSEL[4..0]
DCLK
nCEO
You can leave the nCEO pin
unconnected or use it as a
user I/O pin when it does not
feed another device’s nCE
pin.
N.C.
DATA0
nCONFIG
DCLK
MSEL[4..0]
For more information, refer
to the MSEL pin settings.
After a device completes configuration, its nCEO pin is released low to activate the nCE pin of the next device
in the chain. Configuration automatically begins for the second device in one clock cycle.
Using One Configuration Data
To configure multiple Arria V devices in a chain using one configuration data, connect the devices to an
external host, as shown in the following figure.
Figure 8-15: Multiple Device PS Configuration When Both Devices Receive the Same Set of Configuration
Data
Connect the resistor to a power supply that provides an acceptable input
signal for the FPGA device. VCCPGM must be high enough to meet the VIH
specification of the I/O on the device and the external host. Altera
recommends powering up all the configuration system I/Os with VCCPGM.
Memory
ADDR
VCCPGM VCCPGM
DATA0
10 kΩ
External Host
(MAX II Device,
MAX V Device, or
Microprocessor
10 kΩ
FPGA Device 1
CONF_DONE
nSTATUS
nCEO
nCE
GND
FPGA Device 2
CONF_DONE
nSTATUS
nCE
N.C.
GND
DATA0
nCONFIG
MSEL[4..0]
DCLK
nCEO
N.C.
DATA0
nCONFIG
DCLK
MSEL[4..0]
For more information,
refer to the MSEL pin
settings.
You can leave the nCEO
pin unconnected or use it
as a user I/O pin.
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Using PC Host and Download Cable
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The nCE pins of the devices in the chain are connected to GND, allowing configuration for these devices to
begin and end at the same time.
Using PC Host and Download Cable
To configure multiple Arria V devices, connect the devices to a download cable, as shown in the following
figure.
Figure 8-16: Multiple Device PS Configuration Using an Altera Download Cable
Connect the pull-up resistor to the
same supply voltage (VCCIO) as the
USB-Blaster, ByteBlaster II,
EthernetBlaster, or EthernetBlaster II
cable.
VCCPGM
10 kΩ
10 kΩ
FPGA Device 1
VCCPGM
VCCPGM
CONF_DONE
10 kΩ
MSEL[4..0]
Download Cable
10-Pin Male Header
VCCPGM
10 kΩ (2)
(PS Mode)
Pin 1
VCCPGM
nSTATUS
DCLK
GND
VIO
VCCPGM
nCEO
nCE
10 kΩ
You only need the pull-up resistors on
DATA0 and DCLK if the download cable
is the only configuration scheme used
on your board. This ensures that
DATA0 and DCLK are not left floating
after configuration. For example, if you
are also using a configuration device,
you do not need the pull-up resistors on
DATA0 and DCLK.
GND
DATA0
nCONFIG
GND
In the USB-Blaster and
ByteBlaster II cables, this
pin is connected to nCE
when you use it for AS
programming. Otherwise,
this pin is a no connect.
FPGA Device 2
CONF_DONE
nSTATUS
MSEL[4..0]
DCLK
For more information, refer to
the MSEL pin settings.
nCEO
N.C.
nCE
DATA0
nCONFIG
When a device completes configuration, its nCEO pin is released low to activate the nCE pin of the next device.
Configuration automatically begins for the second device.
JTAG Configuration
In Arria V devices, JTAG instructions take precedence over other configuration schemes.
The Quartus II software generates an SRAM Object File (.sof) that you can use for JTAG configuration using
a download cable in the Quartus II software programmer. Alternatively, you can use the JRunner software
with .rbf or a JAM™ Standard Test and Programming Language (STAPL) Format File (.jam) or JAM Byte
Code File (.jbc) with other third-party programmer tools.
Related Information
• JTAG Boundary-Scan Testing in Arria V Devices on page 10-1
Provides more information about JTAG boundary-scan testing.
• Device Configuration Pins on page 8-7
Provides more information about JTAG configuration pins.
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JTAG Single-Device Configuration
• JTAG Secure Mode on page 8-36
• AN 425: Using the Command-Line Jam STAPL Solution for Device Programming
• JTAG Boundary-Scan Testing in Arria V Devices
• Arria V Device Datasheet
Provides more information about the JTAG configuration timing.
• Programming Support for Jam STAPL Language
• USB-Blaster Download Cable User Guide
• ByteBlaster II Download Cable User Guide
• EthernetBlaster Communications Cable User Guide
• EthernetBlaster II Communications Cable User Guide
JTAG Single-Device Configuration
To configure a single device in a JTAG chain, the programming software sets the other devices to the bypass
mode. A device in a bypass mode transfers the programming data from the TDI pin to the TDO pin through
a single bypass register. The configuration data is available on the TDO pin one clock cycle later.
The Quartus II software can use the CONF_DONE pin to verify the completion of the configuration process
through the JTAG port:
• CONF_DONE pin is low—indicates that configuration has failed.
• CONF_DONE pin is high—indicates that configuration was successful.
After the configuration data is transmitted serially using the JTAG TDI port, the TCK port is clocked an
additional 1,222 cycles to perform device initialization.
To configure an Arria V device using a download cable, connect the device as shown in the following figure.
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Figure 8-17: JTAG Configuration of a Single Device Using a Download Cable
VCCPD
VCCPGM
VCCPGM
10 kΩ
10 kΩ
GND
The resistor value can vary
from 1 kΩ to 10 kΩ. Perform
signal integrity analysis to
select the resistor value for
your setup.
VCCPD
FPGA Device
nCE
N.C. nCEO
TCK
TDO
Connect the pull-up
resistor VCCPD.
TMS
TDI
nSTATUS
CONF_DONE
nCONFIG
MSEL[4..0]
DCLK
Download Cable
10-Pin Male Header
(JTAG Mode) (Top View)
Pin 1
VCCPD
If you only use the JTAG configuration, connect
nCONFIG to VCCPGM and MSEL[4..0] to GND.
Pull DCLK either high or low whichever is
convenient on your board. If you are using JTAG
in conjunction with another configuration scheme,
connect MSEL[4..0], nCONFIG, and DCLK based
on the selected configuration scheme.
GND
1 kΩ
GND
GND
To configure an Arria V device using a microprocessor, connect the device as shown in the following figure.
You can use JRunner as your software driver.
Figure 8-18: JTAG Configuration of a Single Device Using a Microprocessor
Connect the pull-up resistor to a supply that
provides an acceptable input signal for all
FPGA devices in the chain. VCCPGM must be
high enough to meet the VIH specification of
the I/O on the device.
Memory
ADDR
VCCPGM VCCPGM
DATA
10 kΩ
10 kΩ
FPGA Device
nSTATUS
CONF_DONE
Microprocessor
TDI
TCK
TMS
TDO
DCLK
nCONFIG
MSEL[4..0]
nCEO
nCE
N.C.
GND
The microprocessor must use
the same I/O standard as
VCCPD to drive the JTAG pins.
If you only use the JTAG configuration,
connect nCONFIG to VCCPGM and
MSEL[4..0] to GND. Pull DCLK high or
low. If you are using JTAG in conjunction
with another configuration scheme, set
the MSEL[4..0] pins and tie nCONFIG and
DCLK based on the selected
configuration scheme.
Related Information
AN 414: The JRunner Software Driver: An Embedded Solution for PLD JTAG Configuration
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JTAG Multi-Device Configuration
JTAG Multi-Device Configuration
You can configure multiple devices in a JTAG chain.
Pin Connections and Guidelines
Observe the following pin connections and guidelines for this configuration setup:
• Isolate the CONF_DONE and nSTATUS pins to allow each device to enter user mode independently.
• One JTAG-compatible header is connected to several devices in a JTAG chain. The number of devices
in the chain is limited only by the drive capability of the download cable.
• If you have four or more devices in a JTAG chain, buffer the TCK, TDI, and TMS pins with an on-board
buffer. You can also connect other Altera devices with JTAG support to the chain.
• JTAG-chain device programming is ideal when the system contains multiple devices or when testing
your system using the JTAG boundary-scan testing (BST) circuitry.
Using a Download Cable
The following figure shows a multi-device JTAG configuration.
Figure 8-19: JTAG Configuration of Multiple Devices Using a Download Cable
Connect the pull-up
resistor VCCPD.
Download Cable
10-Pin Male Header
(JTAG Mode)
Pin 1
If you only use the JTAG configuration, connect nCONFIG to VCCPGM and MSEL[4..0]
to GND. Pull DCLK either high or low, whichever is convenient on your board. If you are
using JTAG in conjunction with another configuration scheme, connect MSEL[4..0],
nCONFIG, and DCLK based on the selected configuration scheme.
FPGA Device
VCCPGM
VCCPGM VCCPGM
10 kΩ
10 kΩ
nSTATUS
nCONFIG
DCLK CONF_DONE
MSEL[4..0]
nCE
VCCPD
VCCPD
GND
VIO
1 kΩ
TDO
TMS
TCK
FPGA Device
VCCPGM VCCPGM
10 kΩ
10 kΩ
nSTATUS
nCONFIG
DCLK CONF_DONE
MSEL[4..0]
nCE
GND
TDI
VCCPD
FPGA Device
VCCPGM
10 kΩ
10 kΩ
nSTATUS
nCONFIG
DCLK CONF_DONE
MSEL[4..0]
nCE
GND
TDI
TMS
TDO
TCK
TDI
TMS
TCK
TDO
The resistor value can vary from 1 kΩ to 10
kΩ. Perform signal integrity analysis to
select the resistor value for your setup.
Related Information
AN 656: Combining Multiple Configuration Schemes
Provides more information about combining JTAG configuration with other configuration schemes.
CONFIG_IO JTAG Instruction
The CONFIO_IO JTAG instruction allows you to configure the I/O buffers using the JTAG port before or
during device configuration. When you issue this instruction, it interrupts configuration and allows you to
issue all JTAG instructions. Otherwise, you can only issue the BYPASS, IDCODE, and SAMPLE JTAG instructions.
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Configuration Data Compression
8-29
You can use the CONFIO_IO JTAG instruction to interrupt configuration and perform board-level testing.
After the board-level testing is completed, you must reconfigure your device. Use the following methods to
reconfigure your device:
• JTAG interface—issue the PULSE_NCONFIG JTAG instruction.
• FPP, PS, or AS configuration scheme—pulse the nCONFIG pin low.
Configuration Data Compression
Arria V devices can receive compressed configuration bitstream and decompress the data in real-time during
configuration. Preliminary data indicates that compression typically reduces the configuration file size by
30% to 55% depending on the design.
Decompression is supported in all configuration schemes except the JTAG configuration scheme.
You can enable compression before or after design compilation.
Enabling Compression Before Design Compilation
To enable compression before design compilation, follow these steps:
1. On the Assignment Menu, click Device.
2. Select your Arria V device and then click Device and Pin Options.
3. In the Device and Pin Options window, select Configuration under the Category list and turn on
Generate compressed bitstreams.
Enabling Compression After Design Compilation
To enable compression after design compilation, follow these steps:
1. On the File menu, click Convert Programming Files.
2. Select the programming file type (.pof, .sof, .hex, .hexout, .rbf, or .ttf). For POF output files, select a
configuration device.
3. Under the Input files to convert list, select SOF Data.
4. Click Add File and select an Arria V device .sof.
5. Select the name of the file you added to the SOF Data area and click Properties.
6. Turn on the Compression check box.
Using Compression in Multi-Device Configuration
The following figure shows a chain of two Arria V devices. Compression is only enabled for the first device.
This setup is supported by the AS or PS multi-device configuration only.
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Remote System Upgrades
Figure 8-20: Compressed and Uncompressed Serial Configuration Data in the Same Configuration File
Serial Configuration Data
Compressed
Configuration
Data
Decompression
Controller
Uncompressed
Configuration
Data
FPGA
Device 1
nCE
EPCS, EPCQ, or
External Host
FPGA
Device 2
nCEO
nCE
nCEO
N.C.
GND
For the FPP configuration scheme, a combination of compressed and uncompressed configuration in the
same multi-device configuration chain is not allowed because of the difference on the DCLK-to-DATA[] ratio.
Remote System Upgrades
Arria V devices contain dedicated remote system upgrade circuitry. You can use this feature to upgrade your
system from a remote location.
Figure 8-21: Arria V Remote System Upgrade Block Diagram
2
1
Development
Location
3
Data
Data
Data
FPGA
Remote System
Upgrade Circuitry
Configuration
Memory
FPGA Configuration
4
You can design your system to manage remote upgrades of the application configuration images in the
configuration device. The following list is the sequence of the remote system upgrade:
1. The logic (embedded processor or user logic) in the Arria V device receives a configuration image from
a remote location. You can connect the device to the remote source using communication protocols such
as TCP/IP, PCI, user datagram protocol (UDP), UART, or a proprietary interface.
2. The logic stores the configuration image in non-volatile configuration memory.
3. The logic starts reconfiguration cycle using the newly received configuration image.
4. When an error occurs, the circuitry detects the error, reverts to a safe configuration image, and provides
error status to your design.
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Configuration Images
8-31
Configuration Images
Each Arria V device in your system requires one factory image. The factory image is a user-defined
configuration image that contains logic to perform the following:
• Processes errors based on the status provided by the dedicated remote system upgrade circuitry.
• Communicates with the remote host, receives new application images, and stores the images in the local
non-volatile memory device.
• Determines the application image to load into the Arria V device.
• Enables or disables the user watchdog timer and loads its time-out value.
• Instructs the dedicated remote system upgrade circuitry to start a reconfiguration cycle.
You can also create one or more application images for the device. An application image contains selected
functionalities to be implemented in the target device.
Store the images at the following locations in the EPCS or EPCQ devices:
• Factory configuration image—PGM[23..0] = 24'h000000 start address on the EPCS or EPCQ device.
• Application configuration image—any sector boundary. Altera recommends that you store only one
image at one sector boundary.
Configuration Sequence in the Remote Update Mode
Figure 8-22: Transitions Between Factory and Application Configurations in Remote Update Mode
Configuration Error
Set Control Register
and Reconfigure
Power Up
Configuration
Error
Factory
Configuration
(page 0)
Application 1
Configuration
Reload a
Different Application
Reload a
Different Application
Set Control Register
and Reconfigure
Application n
Configuration
Configuration Error
Related Information
Remote System Upgrade State Machine on page 8-35
A detailed description of the configuration sequence in the remote update mode.
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Remote System Upgrade Circuitry
Remote System Upgrade Circuitry
The remote system upgrade circuitry contains the remote system upgrade registers, watchdog timer, and a
state machine that controls these components.
Note: If you are using the ALTREMOTE_UPDATE megafunction, the megafunction controls the RU_DOUT,
RU_SHIFTnLD, RU_CAPTnUPDT, RU_CLK, RU_DIN, RU_nCONFIG, and RU_nRSTIMER signals internally to
perform all the related remote system upgrade operations.
Figure 8-23: Remote System Upgrade Circuitry
Internal Oscillator
Status Register (SR)
[4..0]
Control Register
[37..0]
Logic Array
Update Register
[37..0]
update
Remote
System
Upgrade
State
Machine
Shift Register
dout
Bit [4..0]
din
dout
din
Bit [37..0]
capture
capture
Timeout
User
Watchdog
Timer
clkout capture update
Logic Array clkin
RU_DOUT
RU_SHIFTnLD
RU_CAPTnUPDT
RU_CLK
RU_DIN
RU_nCONFIG
RU_nRSTIMER
Logic Array
Related Information
Arria V Device Datasheet
Provides more information about remote system upgrade circuitry timing specifications.
Enabling Remote System Upgrade Circuitry
To enable the remote system upgrade feature, follow these steps:
1. Select Active Serial x1/x4 or Configuration Device from the Configuration scheme list in the Configuration page of the Device and Pin Options dialog box in the Quartus II software.
2. Select Remote from the Configuration mode list in the Configuration page of the Device and Pin Options
dialog box in the Quartus II software.
Enabling this feature automatically turns on the Auto-restart configuration after error option.
Altera-provided ALTREMOTE_UPDATE megafunction provides a memory-like interface to the remote
system upgrade circuitry and handles the shift register read and write protocol in the Arria V device logic.
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Remote System Upgrade Registers
8-33
Related Information
Remote System Upgrade (ALTREMOTE_UPDATE) Megafunction User Guide
Remote System Upgrade Registers
Table 8-6: Remote System Upgrade Registers
Register
Shift
Description
Accessible by the logic array and clocked by RU_CLK.
• Bits[4..0]—Contents of the status register are shifted into these bits.
• Bits[37..0]—Contents of the update and control registers are shifted into
these bits.
Control
This register is clocked by the 10-MHz internal oscillator. The contents of this
register are shifted to the shift register for the user logic in the application
configuration to read. When reconfiguration is triggered, this register is updated
with the contents of the update register.
Update
This register is clocked by RU_CLK. The factory configuration updates this register
by shifting data into the shift register and issuing an update. When reconfiguration is triggered, the contents of the update register are written to the control
register.
Status
After each reconfiguration, the remote system upgrade circuitry updates this
register to indicate the event that triggered the reconfiguration. This register is
clocked by the 10-MHz internal oscillator.
Related Information
• Control Register on page 8-34
• Status Register on page 8-34
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Control Register
Control Register
Table 8-7: Control Register Bits
Bit
Name
0
Reset
(30)
Value
1'b0
AnF
Description
Application not Factory bit. Indicates the
configuration image type currently loaded in
the device; 0 for factory image and 1 for
application image. When this bit is 1, the access
to the control register is limited to read only
and the watchdog timer is enabled.
Factory configuration design must set this bit
to 1 before triggering reconfiguration using an
application configuration image.
1..24
PGM[0..23]
24'h000000 Upper 24 bits of AS configuration start address
(StAdd[31..8]), the 8 LSB are zero.
25
Wd_en
1'b0
26..37
Wd_timer[11..0]
12'b000000000000 User watchdog time-out value.
User watchdog timer enable bit. Set this bit to
1 to enable the watchdog timer.
Status Register
Table 8-8: Status Register Bits
Bit
(30)
(31)
Name
Reset
(31)
Value
Description
0
CRC
1'b0
When set to 1, indicates CRC error during application
configuration.
1
nSTATUS
1'b0
When set to 1, indicates that nSTATUS is asserted by an
external device due to error.
2
Core_nCONFIG
1'b0
When set to 1, indicates that reconfiguration has been
triggered by the logic array of the device.
3
nCONFIG
1'b0
When set to 1, indicates that nCONFIG is asserted.
4
Wd
1'b0
When set to 1, indicates that the user watchdog
time-out.
This is the default value after the device exits POR and during reconfiguration back to the factory configuration
image.
After the device exits POR and power-up, the status register content is 5'b00000.
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Remote System Upgrade State Machine
8-35
Remote System Upgrade State Machine
The operation of the remote system upgrade state machine is as follows:
1. After power-up, the remote system upgrade registers are reset to 0 and the factory configuration image
is loaded.
2. The user logic sets the AnF bit to 1 and the start address of the application image to be loaded. The user
logic also writes the watchdog timer settings.
3. When the configuration reset (RU_CONFIG) goes low, the state machine updates the control register with
the contents of the update register, and triggers reconfiguration using the application configuration
image.
4. If error occurs, the state machine falls back to the factory image. The control and update registers are
reset to 0, and the status register is updated with the error information.
5. After successful reconfiguration, the system stays in the application configuration.
User Watchdog Timer
The user watchdog timer prevents a faulty application configuration from stalling the device indefinitely.
You can use the timer to detect functional errors when an application configuration is successfully loaded
into the device. The timer is automatically disabled in the factory configuration; enabled in the application
configuration.
Note: If you do not want this feature in the application configuration, you need to turn off this feature by
setting the Wd_en bit to 1'b0 in the update register during factory configuration user mode operation.
You cannot disable this feature in the application configuration.
The counter is 29 bits wide and has a maximum count value of 229. When specifying the user watchdog timer
value, specify only the most significant 12 bits. The granularity of the timer setting is 217 cycles. The cycle
time is based on the frequency of the user watchdog timer internal oscillator.
The timer begins counting as soon as the application configuration enters user mode. When the timer expires,
the remote system upgrade circuitry generates a time-out signal, updates the status register, and triggers the
loading of the factory configuration image. To reset the time, assert RU_nRSTIMER.
Related Information
Arria V Device Datasheet
Provides more information about the operating range of the user watchdog internal oscillator's frequency.
Design Security
The Arria V design security feature supports the following capabilities:
• Enhanced built-in advanced encryption standard (AES) decryption block to support 256-bit key
industry-standard design security algorithm (FIPS-197 Certified)
• Volatile and non-volatile key programming support
• Secure operation mode for both volatile and non-volatile key through tamper protection bit setting
• Limited accessible JTAG instruction during power-up in the JTAG secure mode
• Supports board-level testing
• Supports in-socket key programming for non-volatile key
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ALTCHIP_ID Megafunction
• Available in all configuration schemes except JTAG
• Supports both remote system upgrades and compression features
The Arria V design security feature provides the following security protection for your designs:
• Security against copying—the security key is securely stored in the Arria V device and cannot be read
out through any interface. In addition, as configuration file read-back is not supported in Arria V devices,
your design information cannot be copied.
• Security against reverse engineering—reverse engineering from an encrypted configuration file is very
difficult and time consuming because the Arria V configuration file formats are proprietary and the file
contains millions of bits that require specific decryption.
• Security against tampering—After you set the tamper protection bit, the Arria V device can only accept
configuration files encrypted with the same key. Additionally, programming through the JTAG interface
and configuration interface is blocked.
When you use compression with the design security feature, the configuration file is first compressed and
then encrypted using the Quartus II software. During configuration, the device first decrypts and then
decompresses the configuration file.
When you use design security with Arria V devices in an FPP configuration scheme, it requires a different
DCLK-to-DATA[] ratio.
ALTCHIP_ID Megafunction
The ALTCHIP_ID megafunction provides the following features:
• Acquiring the chip ID of an FPGA device.
• Allowing you to identify your device in your design as part of a security feature to protect your design
from an unauthorized device.
Related Information
ALTCHIP_ID Megafunction User Guide
JTAG Secure Mode
When you enable the tamper-protection bit, Arria V devices are in the JTAG secure mode after power-up.
During this mode, many JTAG instructions are disabled. Arria V devices only allow mandatory JTAG 1149.1
instructions to be exercised. These JTAG instructions are SAMPLE/PRELOAD, BYPASS, EXTEST, and optional
instructions such as IDCODE and SHIFT_EDERROR_REG.
To enable the access of other JTAG instructions such as USERCODE, HIGHZ, CLAMP, PULSE_nCONFIG, and
CONFIG_IO, you must issue the UNLOCK instruction to deactivate the JTAG secure mode. You can issue the
LOCK instruction to put the device back into JTAG secure mode. You can only issue both the LOCK and UNLOCK
JTAG instructions during user mode.
Related Information
• Supported JTAG Instruction on page 10-3
Provides more information about JTAG binary instruction code related to the LOCK and UNLOCK
instructions.
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Security Key Types
8-37
• JTAG Boundary-Scan Testing in Arria V Devices
Provides more information about JTAG binary instruction code related to the LOCK and UNLOCK
instructions.
Security Key Types
Arria V devices offer two types of keys—volatile and non-volatile. The following table lists the differences
between the volatile key and non-volatile keys.
Table 8-9: Security Key Types
Key Types
Key Programmability
Power Supply for Key
Storage
Programming Method
Volatile
• Reprogrammable Required external
battery, VCCBAT (32)
• Erasable
On-board
Non-volatile
One-time
programming
On-board and in-socket
programming (33)
Does not require an
external battery
Both non-volatile and volatile key programming offers protection from reverse engineering and copying. If
you set the tamper-protection bit, the design is also protected from tampering.
You can perform key programming through the JTAG pins interface. Ensure that the nSTATUS pin is released
high before any key-programming attempts.
Note: To clear the volatile key, issue the KEY_CLR_VREG JTAG instruction. To verify the volatile key has
been cleared, issue the KEY_VERIFY JTAG instruction.
Related Information
• Supported JTAG Instruction on page 10-3
Provides more information about the KEY_CLR_VREG and KEY_VERIFY instructions.
• JTAG Boundary-Scan Testing in Arria V Devices
Provides more information about the KEY_CLR_VREG and KEY_VERIFY JTAG instructions.
• Arria V GT and GX Device Family Pin Connection Guidelines
Provides more information about the VCCBAT pin connection recommendations.
• Arria V GZ Device Family Pin Connection Guidelines
Provides more information about the VCCBAT pin connection recommendations.
• Arria V Device Datasheet
Provides more information about battery specifications.
(32)
(33)
VCCBAT is a dedicated power supply for volatile key storage. VCCBAT continuously supplies power to the volatile
register regardless of the on-chip supply condition.
Third-party vendors offer in-socket programming.
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Security Modes
Security Modes
Table 8-10: Supported Security Modes
Security Mode
Tamper Protection
Bit Setting
Device Accepts
Unencrypted File
Device Accepts
Encrypted File
Security Level
No key
—
Yes
No
—
Volatile Key
—
Yes
Yes
Secure
Volatile Key with
Tamper Protection Bit
Set
Set
No
Yes
Secure with tamper
resistant
Non-volatile Key
—
Yes
Yes
Secure
Non-volatile Key with
Tamper Protection Bit
Set
Set
No
Yes
Secure with tamper
resistant
The use of unencrypted configuration bitstream in the volatile key and non-volatile key security modes is
supported for board-level testing only.
Note: For the volatile key with tamper protection bit set security mode, Arria V devices do not accept the
encrypted configuration file if the volatile key is erased. If the volatile key is erased and you want to
reprogram the key, you must use the volatile key security mode.
Enabling the tamper protection bit disables the test mode in Arria V devices and disables programming
through the JTAG interface. This process is irreversible and prevents Altera from carrying out failure analysis.
Design Security Implementation Steps
Figure 8-24: Design Security Implementation Steps
AES Key
Programming File
Step 3
Key Storage
Step 1
256-bit User-Defined
Key
AES Decryption
Quartus II Software
AES Encryptor
Step 4
Step 1
Encrypted
Configuration
File
Altera Corporation
FPGA Device
Step 2
Memory or
Configuration
Device
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Document Revision History
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To carry out secure configuration, follow these steps:
1. The Quartus II software generates the design security key programming file and encrypts the configuration
data using the user-defined 256-bit security key.
2. Store the encrypted configuration file in the external memory.
3. Program the AES key programming file into the Arria V device through a JTAG interface.
4. Configure the Arria V device. At the system power-up, the external memory device sends the encrypted
configuration file to the Arria V device.
Document Revision History
Date
Version
Changes
January 2014
2014.01.10
• Added a link to the FPGA Manager chapter for details about the MSEL
pin settings for the HPS in SoC FPGA devices.
• Updated the VCCPD Pin section.
• Updated the Enabling Remote System Upgrade Circuitry section.
• Updated the Configuration Pin Summary section.
• Updated Figure 8-3, Figure 8-7, and Figure 8-14.
June 2013
2013.06.11
Updated the Configuration Error Handling section.
May 2013
2013.05.10
Removed support for active serial multi-device configuration using the
same configuration data.
May 2013
2013.05.06
• Added link to the known document issues in the Knowledge Base.
• Added the ALTCHIP_ID megafunction section.
• Updated "Connection Setup for Programming the EPCS Using the JTAG
Interface" and "Connection Setup for Programming the EPCQ Using
the JTAG Interface" figures.
• Added the nIO_PULLUP pin in Table 8-3: Configuration Pin Summary
for Arria V Devices.
• Added links for AS, PS, FPP, and JTAG configuration timing to device
datasheet.
• Moved all links to the Related Information section of respective topics
for easy reference.
November 2012
2012.11.19
•
•
•
•
Added configuration modes and features for Arria V devices.
Added FPP x32 for Arria V GZ devices.
Added DATA[31..16] for Arria V GZ devices.
Reorganized content and updated template.
June 2012
2.0
Restructured the chapter.
November 2011
1.1
Minor text edits.
October 2011
1.0
Initial release.
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SEU Mitigation for Arria V Devices
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This chapter describes the error detection features in Arria V devices. You can use these features to mitigate
single event upset (SEU) or soft errors.
Related Information
Arria V Device Handbook: Known Issues
Lists the planned updates to the Arria V Device Handbook chapters.
Error Detection Features
The on-chip error detection CRC circuitry allows you to perform the following operations without any
impact on the fitting or performance of the device:
• Auto-detection of CRC errors during configuration.
• Optional CRC error detection and identification in user mode.
• Testing of error detection functions by deliberately injecting errors through the JTAG interface.
Configuration Error Detection
When the Quartus II software generates the configuration bitstream, the software also computes a 16-bit
CRC value for each frame. A configuration bitstream can contain more than one CRC values depending on
the number of data frames in the bitstream. The length of the data frame varies for each device.
When a data frame is loaded into the FPGA during configuration, the precomputed CRC value shifts into
the CRC circuitry. At the same time, the CRC engine in the FPGA computes the CRC value for the data
frame and compares it against the precomputed CRC value. If both CRC values do not match, the nSTATUS
pin is set to low to indicate a configuration error.
You can test the capability of this feature by modifying the configuration bitstream or intentionally corrupting
the bitstream during configuration.
User Mode Error Detection
In user mode, the contents of the configured CRAM bits may be affected by soft errors. These soft errors,
which are caused by an ionizing particle, are not common in Altera devices. However, high-reliability
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Specifications
applications that require the device to operate error-free may require that your designs account for these
errors.
You can enable the error detection circuitry to detect soft errors. Each data frame stored in the CRAM
contains a 32-bit precomputed CRC value. When this feature is enabled, the error detection circuitry
continuously computes a 32-bit CRC value for each frame in the CRAM and compares the CRC value against
the precomputed value.
• If the CRC values match, the 32-bit CRC signature in the syndrome register is set to zero to indicate that
no error is detected.
• Otherwise, the resulting 32-bit CRC signature in the syndrome register is non-zero to indicate a CRC
error. The CRC_ERROR pin is pulled high, and the error type and location are identified.
Within a frame, the error detection circuitry can detect all single-, double-, triple-, quadruple-, and quintuplebit errors. When a single-bit or double-adjacent error is detected, the error detection circuitry reports the
bit location and determines the error type for single-bit and double-adjacent errors. The probability of other
error patterns is very low and the reporting of bit location is not guaranteed. The probability of more than
five CRAM bits being flipped by soft errors is very low. In general, the probability of detection for all error
patterns is 99.9999%. The process of error detection continues until the device is reset by setting the nCONFIG
signal low.
Specifications
This section lists the EMR update interval, error detection frequencies, and CRC calculation time for error
detection in user mode.
Minimum EMR Update Interval
The interval between each update of the error message register depends on the device and the frequency of
the error detection clock. Using a lower clock frequency increases the interval time, hence increasing the
time required to recover from a single event upset (SEU).
Table 9-1: Estimated Minimum EMR Update Interval in Arria V Devices
Variant
Arria V GX
Altera Corporation
Member Code
Timing Interval (µs)
A1
2.55
A3
2.55
A5
2.87
A7
2.87
B1
3.13
B3
3.13
B5
3.83
B7
3.83
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Error Detection Frequency
Variant
Member Code
Timing Interval (µs)
C3
2.55
C7
2.87
D3
3.13
D7
3.83
E1
2.43
E3
2.43
E5
2.99
E7
2.99
B3
3.83
B5
3.83
D3
3.83
D5
3.83
Arria V GT
Arria V GZ
Arria V SX
Arria V ST
9-3
Error Detection Frequency
You can control the speed of the error detection process by setting the division factor of the clock frequency
in the Quartus II software. The divisor is 2n, where n can be any value listed in the following table.
The speed of the error detection process for each data frame is determined by the following equation:
Figure 9-1: Error Detection Frequency Equation
Error Detection Frequency =
Internal Oscillator Frequency
2n
Table 9-2: Error Detection Frequency Range for Arria V Devices
The following table lists the frequencies and valid values of n.
Internal Oscillator Frequency
100 MHz
Error Detection Frequency
Maximum
100 MHz
Minimum
390 kHz
n
Divisor Range
0, 1, 2, 3, 4, 5, 6, 7, 8 1 – 256
CRC Calculation Time
The time taken by the error detection circuitry to calculate the CRC for each frame is determined by the
device in use and the frequency of the error detection clock.
You can calculate the minimum and maximum time for any number of divisor based on the following
formula:
Maximum time (n) = 2^(n-8) * maximum time
Minimum time (n) = 2^n * minimum time
where the range of n is from 0 to 8.
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Using Error Detection Features in User Mode
Table 9-3: CRC Calculation Time in Arria V Devices
The following table lists the minimum and maximum time taken to calculate the CRC value:
• The minimum time is derived using the maximum clock frequency with a divisor of 0.
• The maximum time is derived using the minimum clock frequency with a divisor of 8.
Variant
Arria V GX
Arria V GT
Arria V GZ
Arria V SX
Arria V ST
Member Code
Minimum Time (ms)
Maximum Time (s)
A1
13.74
8.80
A3
13.74
8.80
A5
21.42
13.71
A7
21.42
13.71
B1
30.45
19.49
B3
30.45
19.49
B5
40.70
26.05
B7
40.70
26.05
C3
13.74
8.80
C7
21.42
13.71
D3
30.45
19.49
D7
40.70
26.05
E1
43.00
22.29
E3
67.00
34.81
E5
67.00
34.81
E7
67.00
34.81
B3
40.70
26.05
B5
40.70
26.05
D3
40.70
26.05
D5
40.70
26.05
Using Error Detection Features in User Mode
This section describes the pin, registers, process flow, and procedures for error detection in user mode.
Enabling Error Detection
To enable user mode error detection in the Quartus II software, follow these steps:
1.
2.
3.
4.
On the Assignments menu, click Device.
In the Device dialog box, click Device and Pin Options.
In the Category list, click Error Detection CRC.
Turn on Enable Error Detection CRC_ERROR pin.
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CRC_ERROR Pin
9-5
5. To set the CRC_ERROR pin as output open drain, turn on Enable open drain on CRC_ERROR pin. Turning
off this option sets the CRC_ERROR pin as output.
6. In the Divide error check frequency by list, select a valid divisor.
7. Click OK.
CRC_ERROR Pin
Table 9-4: Pin Description
Pin Name
Pin Type
Description
An active-high signal, when driven high indicates that an
I/O or output/
output open-drain error is detected in the CRAM bits. This pin is only used
when you enable error detection in user mode. Otherwise,
the pin is used as a user I/O pin.
CRC_ERROR
When using the WYSIWYG function, you can route the
crcerror port from the WYSIWYG atom to the dedicated
CRC_ERROR pin or any user I/O pin. To route the crcerror
port to a user I/O pin, insert a D-type flipflop between
them.
Error Detection Registers
This section describes the registers used in user mode.
Figure 9-2: Block Diagram for Error Detection in User Mode
The block diagram shows the registers and data flow in user mode.
Readback
Bitstream with
Expected CRC
Error
Detection
State
Machine
32-bit Error Detection
CRC Calculation and
Error Search Engine
Syndrome
Register
Control
Signals
Error
Message
Register
CRC_ERROR
Error Injection
Block
Fault
Injection
Register
JTAG
Fault
Injection
Register
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Update
Register
User
Update
Register
JTAG
Shift
Register
User
Shift
Register
JTAG TDO
General Routing
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Error Detection Registers
Table 9-5: Error Detection Registers
Name
Width (Bits)
Description
Syndrome register
32
Contains the 32-bit CRC signature calculated for the current
frame. If the CRC value is 0, the CRC_ERROR pin is driven
low to indicate no error. Otherwise, the pin is pulled high.
Error message register (EMR)
67
Contains error details for single-bit and double-adjacent
errors. The error detection circuitry updates this register
each time the circuitry detects an error. Figure 9-3 shows
the fields in this register and Table 9-6 lists the possible error
types.
JTAG update register
67
This register is automatically updated with the contents of
the EMR one clock cycle after the content of this register is
validated. The JTAG update register includes a clock enable,
which must be asserted before its contents are written to the
JTAG shift register. This requirement ensures that the JTAG
update register is not overwritten when its contents are being
read by the JTAG shift register.
JTAG shift register
67
This register allows you to access the contents of the JTAG
update register via the JTAG interface using the SHIFT_
EDERROR_REG JTAG instruction.
User update register
67
This register is automatically updated with the contents of
the EMR one clock cycle after the contents of this register
are validated. The user update register includes a clock
enable, which must be asserted before its contents are written
to the user shift register. This requirement ensures that the
user update register is not overwritten when its contents are
being read by the user shift register.
User shift register
67
This register allows user logic to access the contents of the
user update register via the core interface.
JTAG fault injection register
46
You can use this register with the EDERROR_INJECT JTAG
instruction to inject errors in the bitstream. Table 9-7 lists
the fields in this register.
Fault injection register
46
This register is updated with the contents of the JTAG fault
injection register.
Figure 9-3: Error Message Register Map
MSB
Altera Corporation
LSB
Syndrome
Frame Address
Double Word
Location
32 bits
16 bits
10 bits
Byte Offset
Bit Offset
Error Type
2 bits
3 bits
4 bits
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Error Detection Process
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Table 9-6: Error Type in EMR
The following table lists the possible error types reported in the error type field in the EMR.
Error Type
Bit 3
Bit 2
Bit 1
Description
Bit 0
0
0
0
0
No CRC error.
0
0
0
1
Location of a single-bit error is identified.
0
0
1
0
Location of a double-adjacent error is identified.
1
1
1
1
Error types other than single-bit and double-adjacent errors.
Table 9-7: JTAG Fault Injection Register Map
Field Name
Bit Range
Description
Error Byte
Value
31:0
Contains the location of the bit error that
corresponds to the error injection type to this
field.
Byte Location
41:32
Contains the location of the injected error in
the first data frame.
45:42
Specifies the following error types.
Bit 45
Bit 44
Bit 43
Bit 42
0
0
0
0
No error
0
0
0
1
Single-bit error
0
0
1
0
Double adjacent error
Error Type
Error Detection Process
When enabled, the user mode error detection process activates automatically when the FPGA enters user
mode. The process continues to run until the device is reset even when an error is detected in the current
frame.
Figure 9-4: Error Detection Process Flow in User Mode
Receive
Data Frame
Calculate and
Compare
CRC Values
Error
Detected?
No
Pull CRC_ERROR
Signal Low for
32 Clock Cycles
Yes
Update Error
Message Register
(Overwrite)
Search for
Error Location
Drive
CRC_ERROR
Signal High
Timing
The CRC_ERROR pin is always driven low during CRC calculation for a minimum of 32 clock cycles. When
an error occurs, the pin is driven high once the EMR is updated or 32 clock cycles have lapsed, whichever
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Testing the Error Detection Block
comes last. Therefore, you can start retrieving the contents of the EMR at the rising edge of the CRC_ERROR
pin. The pin stays high until the current frame is read and then driven low again for a minimum of 32 clock
cycles. To ensure information integrity, complete the read operation within one frame of the CRC verification.
The following diagram shows the timing of these events.
Figure 9-5: Timing Requirements
Frame
Data Integrity
N
N+1
No CRC Error
CRC Error
N+2
CRC Error
N+3
N+4
No CRC Error
CRC Error
N+5
No CRC Error
Read Data Frame
CRC ERROR Pin
CRC Calculation
(minimum 32 clock
cycles)
Read Error Message
Register (allowed time)
Read Error Message
for frame N+1
Read Error Message
for frame N+2
Read Error Message
for frame N+4
Retrieving Error Information
You can retrieve the error information via the core interface or the JTAG interface using the
SHIFT_EDERROR_REG JTAG instruction.
Recovering from CRC Errors
The system that hosts the FPGA must control device reconfiguration. To recover from a CRC error, drive
the nCONFIG signal low. The system waits for a safe time before reconfiguring the device. When reconfiguration
completes successfully, the FPGA operates as intended.
Related Information
• Error Detection Frequency on page 9-3
Provides more information about the minimum and maximum error detection frequencies.
• Minimum EMR Update Interval on page 9-2
Provides more information about the duration of each Arria Vdevice.
• Test Methodology of Error Detection and Recovery using CRC in Altera FPGA Devices
Provides more information about how to retrieve the error information.
Testing the Error Detection Block
You can inject errors into the configuration data to test the error detection block. This error injection
methodology provides design verification and system fault tolerance characterization.
Testing via the JTAG Interface
You can intentionally inject single or double-adjacent errors into the configuration data using the
EDERROR_INJECT JTAG instruction.
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9-9
Table 9-8: EDERROR_INJECT instruction
JTAG Instruction
Instruction Code
00 0001 0101
EDERROR_INJECT
Description
Use this instruction to inject errors into the
configuration data. This instruction controls the
JTAG fault injection register, which contains the
error you want to inject into the bitstream.
You can only inject errors into the first frame of the configuration data. However, you can monitor the error
information at any time. Altera recommends that you reconfigure the FPGA after the test completes.
Automating the Testing Process
You can automate the testing process by creating a Jam™ file (.jam). Using this file, you can verify the CRC
functionality in-system and on-the-fly without reconfiguring the device. You can then switch to the CRC
circuitry to check for real errors caused by an SEU.
Related Information
Test Methodology of Error Detection and Recovery using CRC in Altera FPGA Devices
Provides more information about how to test the error detection block.
Document Revision History
Date
Version
Changes
November 2013
2013.11.12
• Updated the CRC Calculation Time section to include a formula to
calculate the minimum and maximum time.
• Removed preliminary for the Minimum EMR Update Interval and CRC
Calculation Time.
• Removed related information for the Internal Scrubbing feature.
May 2013
2013.05.06
• Added link to the known document issues in the Knowledge Base.
• Moved all links to the Related Information section of respective topics
for easy reference.
November 2012
2012.11.19
• Added the following specifications for Arria V GZ—Minimum EMR
update interval, error detection frequency, and CRC calculation time.
• Updated the width of the JTAG fault injection and fault injection
registers.
• Reorganized content and updated template.
June 2012
2.0
• Added the “Basic Description”, “Error Detection Features”, “Types of
Error Detection”, “Error Detection Components”, “Using the Error
Detection Feature”, and “Testing the Error Detection Block” sections.
• Updated Table 9–4, Table 9–5, and Table 9–6.
• Restructured the chapter.
November 2011
1.1
Restructured chapter.
May 2011
1.0
Initial release.
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This chapter describes the boundary-scan test (BST) features in Arria V devices.
Related Information
• JTAG Configuration on page 8-25
Provides more information about JTAG configuration.
• Arria V Device Handbook: Known Issues
Lists the planned updates to the Arria V Device Handbook chapters.
BST Operation Control
Arria V GX, GT, SX, and ST devices support IEEE Std. 1149.1 BST. Arria V GZ devices support
IEEE Std. 1149.1 and IEEE Std. 1149.6 BST. You can perform BST on Arria V devices before, after, and
during configuration.
IDCODE
The IDCODE is unique for each Arria V device. Use this code to identify the devices in a JTAG chain.
© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words
and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other
words and logos identified as trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with
Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes
no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
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9001:2008
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IDCODE
Table 10-1: IDCODE Information for Arria V Devices
IDCODE (32 Bits)
Variant
Arria V GX
Arria V GT
Arria V GZ
Altera Corporation
Member Code
Version (4 Bits)
Part Number
(16 Bits)
Manufacture
Identity
(11 Bits)
LSB (1 Bit)
A1
0000
0010 1010 0001 000 0110 1110
0001
1
A3
0000
0010 1010 0000 000 0110 1110
0001
1
A5
0000
0010 1010 0001 000 0110 1110
0010
1
A7
0000
0010 1010 0000 000 0110 1110
0010
1
B1
0000
0010 1010 0001 000 0110 1110
0011
1
B3
0000
0010 1010 0000 000 0110 1110
0011
1
B5
0000
0010 1010 0001 000 0110 1110
0110
1
B7
0000
0010 1010 0000 000 0110 1110
0110
1
C3
0000
0010 1010 0000 000 0110 1110
0001
1
C7
0000
0010 1010 0000 000 0110 1110
0010
1
D3
0000
0010 1010 0000 000 0110 1110
0011
1
D7
0000
0010 1010 0000 000 0110 1110
0110
1
E1
0000
0010 1001 0011 000 0110 1110
0001
1
E3
0000
0010 1001 0111 000 0110 1110
0001
1
E5
0000
0010 1001 0111 000 0110 1110
0111
1
E7
0000
0010 1001 1111 000 0110 1110
0111
1
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Supported JTAG Instruction
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IDCODE (32 Bits)
Variant
Member Code
Version (4 Bits)
B3
0000
0010 1101 0001 000 0110 1110
0011
1
B5
0000
0010 1101 0000 000 0110 1110
0011
1
D3
0000
0010 1101 0001 000 0110 1110
0011
1
D5
0000
0010 1101 0000 000 0110 1110
0011
1
Arria V SX
Arria V ST
Part Number
(16 Bits)
Manufacture
Identity
(11 Bits)
LSB (1 Bit)
Supported JTAG Instruction
Table 10-2: JTAG Instructions Supported by Arria V Devices
JTAG Instruction
Instruction Code
Description
SAMPLE/PRELOAD
00 0000 0101
• Allows you to capture and examine
a snapshot of signals at the device
pins during normal device
operation and permits an initial
data pattern to be an output at the
device pins.
• Use this instruction to preload the
test data into the update registers
before loading the EXTEST instruction.
• Used by the SignalTap™ II
Embedded Logic Analyzer.
EXTEST
00 0000 1111
• Allows you to test the external
circuit and board-level interconnects by forcing a test pattern at the
output pins, and capturing the test
results at the input pins. Forcing
known logic high and low levels on
output pins allows you to detect
opens and shorts at the pins of any
device in the scan chain.
• The high-impedance state of EXTEST
is overridden by bus hold and weak
pull-up resistor features.
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Supported JTAG Instruction
JTAG Instruction
Instruction Code
Description
BYPASS
11 1111 1111
Places the 1-bit bypass register between
the TDI and TDO pins. During normal
device operation, the 1-bit bypass
register allows the BST data to pass
synchronously through the selected
devices to adjacent devices.
USERCODE
00 0000 0111
• Examines the user electronic
signature (UES) within the devices
along a JTAG chain.
• Selects the 32-bit USERCODE register
and places it between the TDI and
TDO pins to allow serial shifting of
USERCODE out of TDO.
• The UES value is set to default value
before configuration and is only
user-defined after the device is
configured.
IDCODE
00 0000 0110
• Identifies the devices in a JTAG
chain. If you select IDCODE, the
device identification register is
loaded with the 32-bit
vendor-defined identification code.
• Selects the IDCODE register and
places it between the TDI and TDO
pins to allow serial shifting of
IDCODE out of TDO.
• IDCODE is the default instruction at
power up and in the TAP RESET
state. Without loading any instructions, you can go to the SHIFT_DR
state and shift out the JTAG device
ID.
HIGHZ
00 0000 1011
• Sets all user I/O pins to an inactive
drive state.
• Places the 1-bit bypass register
between the TDI and TDO pins.
During normal operation, the 1-bit
bypass register allows the BST data
to pass synchronously through the
selected devices to adjacent devices
while tri-stating all I/O pins until a
new JTAG instruction is executed.
• If you are testing the device after
configuration, the programmable
weak pull-up resistor or the bus
hold feature overrides the HIGHZ
value at the pin.
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Supported JTAG Instruction
JTAG Instruction
Instruction Code
10-5
Description
CLAMP
00 0000 1010
• Places the 1-bit bypass register
between the TDI and TDO pins.
During normal operation, the 1-bit
bypass register allows the BST data
to pass synchronously through the
selected devices to adjacent devices
while holding the I/O pins to a state
defined by the data in the
boundary-scan register.
• If you are testing the device after
configuration, the programmable
weak pull-up resistor or the bus
hold feature overrides the CLAMP
value at the pin. The CLAMP value is
the value stored in the update
register of the boundary-scan cell
(BSC).
PULSE_NCONFIG
00 0000 0001
Emulates pulsing the nCONFIG pin low
to trigger reconfiguration even though
the physical pin is not affected.
CONFIG_IO
00 0000 1101
Allows I/O reconfiguration (after or
during reconfigurations) through the
JTAG ports using I/O configuration
shift register (IOCSR) for JTAG testing.
You can issue the CONFIG_IO instruction only after the nSTATUS pin goes
high.
LOCK
01 1111 0000
Put the device in JTAG secure mode.
In this mode, only BYPASS, SAMPLE/
PRELOAD, EXTEST, IDCODE,
SHIFT_EDERROR_REG, and UNLOCK
instructions are supported. This
instruction can only be accessed
through JTAG core access in user
mode. It cannot be accessed through
external JTAG pins in test or user
mode.
UNLOCK
11 0011 0001
Release the device from the JTAG
secure mode to enable access to all
other JTAG instructions. This instruction can only be accessed through
JTAG core access in user mode. It
cannot be accessed through external
JTAG pins in test or user mode.
KEY_CLR_VREG
00 0010 1001
Clears the volatile key.
KEY_VERIFY
00 0001 0011
Verifies the non-volatile key has been
cleared.
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JTAG Secure Mode
JTAG Instruction
EXTEST_PULSE
(34)
Instruction Code
00 1000 1111
Description
Enables board-level connectivity
checking between the transmitters and
receivers that are AC coupled by
generating three output transitions:
• Driver drives data on the falling
edge of TCK in the UPDATE_IR/DR
state.
• Driver drives inverted data on the
falling edge of TCK after entering the
RUN_TEST/IDLE state.
• Driver drives data on the falling
edge of TCK after leaving the
RUN_TEST/IDLE state.
The EXTEST_PULSE JTAG instruction
is only supported in user mode for
Arria V GZ devices.
EXTEST_TRAIN
(34)
00 0100 1111
Behaves the same as the EXTEST_PULSE
instruction except that the output
continues to toggle on the TCK falling
edge as long as the TAP controller is in
the RUN_TEST/IDLE state.
The EXTEST_TRAIN JTAG instruction
is only supported in user mode for
Arria V GZ devices.
Note: If the device is in a reset state and the nCONFIG or nSTATUS signal is low, the device IDCODE might
not be read correctly. To read the device IDCODE correctly, you must issue the IDCODE JTAG
instruction only when the nCONFIG and nSTATUS signals are high.
Note: If you use DC coupling on HSSI signals, execute the EXTEST instruction. If you use AC coupling on
HSSI signals, execute the EXTEST_PULSE instruction. AC-coupled and DC-coupled HSSI are only
supported in post-configuration mode.
Related Information
• JTAG Secure Mode on page 8-36
Provides more information about PULSE_NCONFIG, CONFIG_IO, LOCK, and UNLOCK JTAG instructions.
• Configuration, Design Security, and Remote System Upgrades in Arria V Devices
Provides more information about PULSE_NCONFIG, CONFIG_IO, LOCK, and UNLOCK JTAG instructions.
JTAG Secure Mode
If you enable the tamper-protection bit, the Arria V device is in JTAG secure mode after power up. In the
JTAG secure mode, the JTAG pins support only the BYPASS, SAMPLE/PRELOAD, EXTEST, IDCODE,
(34)
This instruction is only supported by Arria V GZ devices.
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JTAG Private Instruction
10-7
SHIFT_EDERROR_REG, and UNLOCK instructions. Issue the UNLOCK JTAG instruction to enable support for
other JTAG instructions.
JTAG Private Instruction
Caution: Never invoke the following instruction codes. These instructions can damage and render the
device unusable:
•
•
•
•
•
•
•
1100010000
0011001001
0000101011(35)
1100010111
1100010011 (36)
1010100001
0101011110
I/O Voltage for JTAG Operation
The Arria V device operating in IEEE Std. 1149.1 BST mode uses four dedicated JTAG pins—TDI, TDO, TMS,
and TCK. Arria V devices do not support the optional TRST pin.
The TCK pin has an internal weak pull-down resistor, while the TDI and TMS pins have internal weak pull-up
resistors. The 3.3-, 3.0-, or 2.5-V VCCPD supply of I/O bank 3A powers the TDO, TDI, TMS, and TCK pins. All
user I/O pins are tri-stated during JTAG configuration.
The JTAG chain supports several different devices. Use the supported TDO and TDI voltage combinations
listed in the following table if the JTAG chain contains devices that have different VCCIO levels. The output
voltage level of the TDO pin must meet the specification of the TDI pin it drives.
Note: Arria V GZ devices do not support 3.3-V VCCPD supply.
Table 10-3: Supported TDO and TDI Voltage Combinations
The TDO output buffer for VCCPD of 3.3 V or 3.0 V meets VOH (MIN) of 2.4 V, and the TDO output buffer for VCCPD
of 2.5 V meets VOH (MIN) of 2.0 V.
Device
Arria V
(35)
(36)
TDI Input Buffer
Power (V)
Arria V TDO VCCPD
VCCPD = 3.3 V
VCCPD = 3.0 V
VCCPD = 2.5 V
VCCPD = 3.3
Yes
Yes
Yes
VCCPD = 3.0
Yes
Yes
Yes
VCCPD = 2.5
Yes
Yes
Yes
This JTAG private instruction is not applicable for Arria V GZ devices.
This JTAG private instruction is only applicable for Arria V GZ devices.
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Performing BST
Device
Non-Arria V(37)
TDI Input Buffer
Power (V)
Arria V TDO VCCPD
VCCPD = 3.3 V
VCCPD = 3.0 V
VCCPD = 2.5 V
VCC = 3.3
Yes
Yes
Yes
VCC = 2.5
Yes
Yes
Yes
VCC = 1.8
Yes
Yes
Yes
VCC = 1.5
Yes
Yes
Yes
Performing BST
You can issue BYPASS, IDCODE, and SAMPLE JTAG instructions before, after, or during configuration without
having to interrupt configuration.
To issue other JTAG instructions, follow these guidelines:
• To perform testing before configuration, hold the nCONFIG pin low.
• To perform BST during configuration, issue CONFIG_IO JTAG instruction to interrupt configuration.
While configuration is interrupted, you can issue other JTAG instructions to perform BST. After BST is
completed, issue the PULSE_CONFIG JTAG instruction or pulse nCONFIG low to reconfigure the device.
The chip-wide reset (DEV_CLRn) and chip-wide output enable (DEV_OE) pins on Arria V devices do not
affect JTAG boundary-scan or configuration operations. Toggling these pins does not disrupt BST operation
(other than the expected BST behavior).
If you design a board for JTAG configuration of Arria V devices, consider the connections for the dedicated
configuration pins.
Note: Do not cascade JTAG chains for FPGA and HPS together when you are performing BST. The JTAG
for HPS does not support BST.
Related Information
• Arria V GT and GX Device Family Pin Connection Guidelines
Provides more information about pin connections.
• Arria V GZ Device Family Pin Connection Guidelines
Provides more information about pin connections.
• Configuration, Design Security, and Remote System Upgrades in Arria V Devices
Provides more information about JTAG configuration.
• Arria V Device Datasheet
Provides more information about JTAG configuration timing.
(37)
The input buffer must be tolerant to the TDO VCCPD voltage.
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Enabling and Disabling IEEE Std. 1149.1 BST Circuitry
10-9
Enabling and Disabling IEEE Std. 1149.1 BST Circuitry
The IEEE Std. 1149.1 BST circuitry is enabled after the Arria V device powers up. However for Arria V SoC
FPGAs, you must power up both HPS and FPGA to perform BST.
To ensure that you do not inadvertently enable the IEEE Std. 1149.1 circuitry when it is not required, disable
the circuitry permanently with pin connections as listed in the following table.
Table 10-4: Pin Connections to Permanently Disable the IEEE Std. 1149.1 Circuitry for Arria V Devices
(38)
JTAG Pins
Connection for Disabling
TMS
VCCPD supply of Bank 3A
TCK
GND
TDI
VCCPD supply of Bank 3A
TDO
Leave open
Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing
Consider the following guidelines when you perform BST with IEEE Std. 1149.1 devices:
• If the “10...” pattern does not shift out of the instruction register through the TDO pin during the first
clock cycle of the SHIFT_IR state, the TAP controller did not reach the proper state. To solve this problem,
try one of the following procedures:
• Verify that the TAP controller has reached the SHIFT_IR state correctly. To advance the TAP controller
to the SHIFT_IR state, return to the RESET state and send the 01100 code to the TMS pin.
• Check the connections to the VCC, GND, JTAG, and dedicated configuration pins on the device.
• Perform a SAMPLE/PRELOAD test cycle before the first EXTEST test cycle to ensure that known data is
present at the device pins when you enter EXTEST mode. If the OEJ update register contains 0, the data
in the OUTJ update register is driven out. The state must be known and correct to avoid contention with
other devices in the system.
• Do not perform EXTEST testing during in-circuit reconfiguration because EXTEST is not supported during
in-circuit reconfiguration. To perform testing, wait for the configuration to complete or issue the
CONFIG_IO instruction to interrupt configuration.
• After configuration, you cannot test any pins in a differential pin pair. To perform BST after configuration,
edit and redefine the BSC group that correspond to these differential pin pairs as an internal cell.
Related Information
IEEE 1149.1 BSDL Files
Provides more information about the BSC group definitions.
(38)
The JTAG pins are dedicated. Software option is not available to disable JTAG in Arria V devices.
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IEEE Std. 1149.1 Boundary-Scan Register
IEEE Std. 1149.1 Boundary-Scan Register
The boundary-scan register is a large serial shift register that uses the TDI pin as an input and the TDO pin
as an output. The boundary-scan register consists of 3-bit peripheral elements that are associated with Arria V
I/O pins. You can use the boundary-scan register to test external pin connections or to capture internal data.
Figure 10-1: Boundary-Scan Register
This figure shows how test data is serially shifted around the periphery of the IEEE Std. 1149.1 device.
Each peripheral
element is either an
I/O pin, dedicated
input pin, or
dedicated
configuration pin.
Internal Logic
TAP Controller
TDI
TMS
TCK
TDO
Boundary-Scan Cells of an Arria V Device I/O Pin
The Arria V device 3-bit BSC consists of the following registers:
• Capture registers—Connect to internal device data through the OUTJ, OEJ, and PIN_IN signals.
• Update registers—Connect to external data through the PIN_OUT and PIN_OE signals.
The TAP controller generates the global control signals for the IEEE Std. 1149.1 BST registers (shift, clock,
and update) internally. A decode of the instruction register generates the MODE signal.
The data signal path for the boundary-scan register runs from the serial data in (SDI) signal to the serial data
out (SDO) signal. The scan register begins at the TDI pin and ends at the TDO pin of the device.
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10-11
Figure 10-2: User I/O BSC with IEEE Std. 1149.1 BST Circuitry for Arria V Devices
Capture
Registers
SDO
Update
Registers
INJ
PIN_IN
0
1
D
Q
INPUT
From or
To Device
I/O Cell
Circuitry
And/Or
Logic
Array
D
0
1
Q
INPUT
OEJ
D
0
1
Q
D
OE
Q
OE
VCC
0
1
0
1
PIN_OE
0
1
PIN_OUT
OUTJ
0
1
D
Q
D
Q
Pin
Output
Buffer
OUTPUT
OUTPUT
CLOCK
UPDATE HIGHZ MODE
SDI
SHIFT
Global
Signals
Note: TDI, TDO, TMS, and TCK pins, all VCC and GND pin types, and VREF pins do not have BSCs.
Table 10-5: Boundary-Scan Cell Descriptions for Arria V Devices
This table lists the capture and update register capabilities of all BSCs within Arria V devices.
Captures
Output
Capture
Register
Pin Type
(39)
OE Capture
Register
Drives
Input
Capture
Register
Output
Update
Register
OE Update
Register
Input
Update
Register
Comments
User I/O pins OUTJ
OEJ
PIN_IN
PIN_OUT
PIN_OE
INJ
—
Dedicated
clock input
0
1
PIN_IN
No
Connect
(N.C.)
N.C.
N.C.
PIN_IN drives
Dedicated
input(39)
0
N.C.
N.C.
1
PIN_IN
to the clock
network or
logic array
N.C.
PIN_IN drives
to the control
logic
This includes the nCONFIG, MSEL0, MSEL1, MSEL2, MSEL3, MSEL4, and nCE pins.
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IEEE Std. 1149.6 Boundary-Scan Register
Captures
Output
Capture
Register
Pin Type
Dedicated
bidirectional
(open drain)
0
Drives
OE Capture
Register
OEJ
Input
Capture
Register
PIN_IN
Output
Update
Register
N.C.
OE Update
Register
N.C.
Input
Update
Register
N.C.
Comments
PIN_IN drives
to the configuration control
(40)
Dedicated
bidirectional(41)
OUTJ
Dedicated
output(42)
OUTJ
OEJ
PIN_IN
N.C.
N.C.
N.C.
PIN_IN drives
to the configuration control
and OUTJ
drives to the
output buffer
0
0
N.C.
N.C.
N.C.
OUTJ drives to
the output
buffer
IEEE Std. 1149.6 Boundary-Scan Register
The BSCs for HSSI transmitters (GXB_TX[p,n]) and receivers/input clock buffers
(GXB_RX[p,n])/(REFCLK[p,n]) in Arria V GZ devices are different from the BSCs for the I/O pins.
(40)
(41)
(42)
This includes the CONF_DONE and nSTATUS pins.
This includes the DCLK pin.
This includes the nCEO pin.
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10-13
Figure 10-3: HSSI Transmitter BSC with IEEE Std. 1149.6 BST Circuitry for Arria V GZ Devices
PMA
SDOUT
BSCAN
AC JTAG
Output Buffer
0
BSTX1
OE
0
D
D
Q
Q
1
1
Pad
Mission
0
(DATAOUT)
D
D
Q
Q
Tx Output
Buffer
0
1
BSOEB
1
TX_BUF_OE
nOE
Pad
OE Logic
MORHZ
ACJTAG_BUF_OE
0
0
OE
BSTX0
D
Q
D
Q
1
1
MEM_INIT SDIN
AC JTAG
Output Buffer
SHIFT
CLK
UPDATE
HIGHZ
AC_TEST
AC_MODE
MODE
Capture
Registers
Update
Registers
Figure 10-4: HSSI Receiver/Input Clock Buffer with IEEE Std. 1149.6 BST Circuitry for Arria V GZ Devices
SDOUT
BSCAN
PMA
BSRX1
AC JTAG Test
Receiver
Hysteretic
Memory
0
BSOUT1
D
Q
Pad
Mission (DATAIN)
Optional INTEST/RUNBIST
not supported
1
RX Input
Buffer
Pad
BSRX0
AC JTAG Test
Receiver
0
D
BSOUT0
Q
Hysteretic
Memory
1
HIGHZ
SDIN
SHIFT
CLK
UPDATE
AC_TEST
MODE
Capture
Registers
AC_MODE
Update
Registers
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Document Revision History
Document Revision History
Date
Version
Changes
January 2014
2014.01.10
• Added a note to the Performing BST section.
• Updated the Supported JTAG Instruction section.
• Updated the KEY_CLR_VREG JTAG instruction.
May 2013
2013.05.06
• Added link to the known document issues in the Knowledge Base.
• Updated the description for EXTEST_TRAIN and EXTEST_PULSE JTAG
instructions.
• Moved all links to the Related Information section of respective topics
for easy reference.
November 2012
2012.11.19
• Added IDCODE for Arria V GZ devices.
• Added EXTEST_PULSE and EXTEST_TRAIN JTAG instructions for
Arria V GZ devices.
• Added the IEEE Std. 1149.6 Boundary-Scan Register section for
Arria V GZ devices.
• Reorganized content and updated template.
June 2012
2.0
• Restructured the chapter.
• Updated Table 10-1 and Table 10-2.
February 2012
1.2
Updated Table 10-2.
November 2011
1.1
Minor text edits.
May 2011
1.0
Initial release.
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Power Management in Arria V Devices
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This chapter describes the hot-socketing feature, power-on reset (POR) requirements, power-up sequencing
recommendation, temperature sensing diode (TSD), and their implementation in Arria V devices.
Related Information
• Arria V Device Handbook: Known Issues
Lists the planned updates to the Arria V Device Handbook chapters.
• PowerPlay Power Analysis
Provides more information about the Quartus®II PowerPlay Power Analyzer tool in volume 3 of the
Quartus II Handbook.
• Arria V Device Datasheet
Provides more information about the recommended operating conditions of each power supply.
• Arria V GT and GX Device Family Pin Connection Guidelines
Provides more detailed information about power supply pin connection guidelines and power regulator
sharing.
• Arria V GZ Device Family Pin Connection Guidelines
Provides more detailed information about power supply pin connection guidelines and power regulator
sharing.
• Board Design Resource Center
Provides more detailed information about power supply design requirements.
Power Consumption
The total power consumption of an Arria V device consists of the following components:
• Static power—the power that the configured device consumes when powered up but no clocks are
operating.
• Dynamic power— the additional power consumption of the device due to signal activity or toggling.
© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words
and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other
words and logos identified as trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with
Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes
no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
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101 Innovation Drive, San Jose, CA 95134
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9001:2008
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11-2
Dynamic Power Equation
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Dynamic Power Equation
Figure 11-1: Dynamic Power
The following equation shows how to calculate dynamic power where P is power, C is the load capacitance,
and V is the supply voltage level.
The equation shows that power is design-dependent and is determined by the operating frequency of your
design. Arria V devices minimize static and dynamic power using advanced process optimizations. This
technology allows Arria V designs to meet specific performance requirements with the lowest possible power.
Programmable Power Technology
Arria V GZ devices offer the ability to configure portions of the core, called tiles, for high-speed or lowpower mode of operation performed by the Quartus II software without user intervention. Setting a tile to
high-speed or low-power mode is accomplished with on-chip circuitry and does not require extra power
supplies brought into the Arria V GZ device. In a design compilation, the Quartus II software determines
whether a tile should be in high-speed or low-power mode based on the timing constraints of the design.
Arria VGZ tiles consist of the following:
• Memory logic array block (MLAB)/ logic array block (LAB) pairs with routing to the pair
• MLAB/LAB pairs with routing to the pair and to adjacent digital signal processing (DSP)/ memory block
routing
• TriMatrix memory blocks
• DSP blocks
• PCI Express® (PCIe®) hard IP
• Physical coding sublayer (PCS)
All blocks and routing associated with the tile share the same setting of either high-speed or low-power
mode. By default, tiles that include DSP blocks or memory blocks are set to high-speed mode for optimum
performance. Unused DSP blocks and memory blocks are set to low-power mode to minimize static power.
Clock networks do not support programmable power technology.
With programmable power technology, faster speed grade FPGAs may require less power because there are
fewer high-speed MLAB and LAB pairs, when compared with slower speed grade FPGAs. The slower speed
grade device may have to use more high-speed MLAB and LAB pairs to meet performance requirements.
The Quartus II software sets unused device resources in the design to low-power mode to reduce the static
power. It also sets the following resources to low-power mode when they are not used in the design:
• LABs and MLABs
• TriMatrix memory blocks
• DSP blocks
If a phase-locked loop (PLL) is instantiated in the design, you may assert the areset pin high to keep the
PLL in low-power mode.
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Temperature Sensing Diode
11-3
Altera recommends that you power down unused PCIe HIPs, per side, by connecting the PCIe HIP power
to GND on the PCB for additional power savings. All of the HIPs on a side of the device must be unused to
be powered down. For additional information refer to the pin connection guidelines.
Table 11-1: Programmable Power Capabilities for Arria V GZ Devices
This table lists the available Arria V GZ programmable power capabilities. Speed grade considerations can add to
the permutations to give you flexibility in designing your system.
Feature
Programmable Power Technology
LAB
Yes
Routing
Yes
Memory Blocks
Fixed setting(43)
DSP Blocks
Fixed setting(43)
Clock Networks
No
Related Information
• Arria V GT and GX Device Family Pin Connection Guidelines
Provides more information about powering down PCIe HIPs.
• Arria V GZ Device Family Pin Connection Guidelines.
Provides more information about powering down PCIe HIPs.
Temperature Sensing Diode
The Arria V TSD uses the characteristics of a PN junction diode to determine die temperature. Knowing
the junction temperature is crucial for thermal management. You can calculate junction temperature using
ambient or case temperature, junction-to-ambient (ja) or junction-to-case (jc) thermal resistance, and device
power consumption. Arria V devices monitor its die temperature with the internal TSD with built-in
analog-to-digital converter (ADC) circuitry or the external TSD with an external temperature sensor. This
allows you to control the air flow to the device.
All Arria V devices support internal TSD only except for Arria V GZ devices that support both internal and
external TSDs.
Internal Temperature Sensing Diode
You can use the Arria V internal TSD in the following operations:
• Power-up mode—to read the die's temperature during configuration, enable the ALTTEMP_SENSE
megafunction in your design.
• User mode—to read the die's temperature during user mode, assert the clken signal to the internal TSD
circuitry.
Note: To reduce power consumption, disable the Arria V internal TSD when you are not using it.
(43)
Tiles with DSP blocks and memory blocks that are used in the design are always set to high-speed mode. By
default, unused DSP blocks and memory blocks are set to low-power mode.
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External Temperature Sensing Diode
Related Information
• Temperature Sensor (ALTTEMP_SENSE) Megafunction User Guide
Provides more information about using the ALTTEMP_SENSE megafunction.
• Arria V Device Datasheet
Provides more information about the Arria V internal TSD specification.
External Temperature Sensing Diode
The Arria V GZ external TSD requires two pins for voltage reference. The following figure shows how to
connect the external TSD with an external temperature sensor device, allowing external sensing of the
Arria V GZ die temperature. For example, you can connect external temperature sensing devices, such as
MAX1619, MAX1617A, MAX6627, and ADT7411 to the two external TSD pins for Arria V GZ device die
temperature reading.
Figure 11-2: TSD External Pin Connections
External TSD
TEMPDIODEP
External
Temperature
Sensor
FPGA
TEMPDIODEN
The TSD is a very sensitive circuit that can be influenced by noise coupled from other traces on the board
or within the device package itself, depending on your device usage. The interfacing signal from the Arria V GZ
device to the external temperature sensor is based on millivolts (mV) of difference, as seen at the external
TSD pins. Switching the I/O near the TSD pins can affect the temperature reading. Altera recommends
taking temperature readings during periods of inactivity in the device or use the internal TSD with built-in
ADC circuitry.
The following are board connection guidelines for the TSD external pin connections:
•
•
•
•
•
•
•
•
•
•
•
The maximum trace lengths for the TEMPDIODEP/TEMPDIODEN traces must be less than eight inches.
Route both traces in parallel and place them close to each other with grounded guard tracks on each side.
Altera recommends 10-mils width and space for both traces.
Route traces through a minimum number of vias and crossunders to minimize the thermocouple effects.
Ensure that the number of vias are the same on both traces.
Ensure both traces are approximately the same length.
Avoid coupling with toggling signals (for example, clocks and I/O) by having the GND plane between
the diode traces and the high frequency signals.
For high-frequency noise filtering, place an external capacitor (close to the external chip) between the
TEMPDIODEP/TEMPDIODEN trace. For Maxim devices, use an external capacitor between 2200 pF to
3300 pF.
Place a 0.1 uF bypass capacitor close to the external device.
You can use the internal TSD with built-in ADC circuitry and external TSD at the same time.
If you only use internal ADC circuitry, the external TSD pins (TEMPDIODEP/TEMPDIODEN) can be
connected to GND because the external TSD pins are not used.
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For details about device specification and connection guidelines, refer to the external temperature sensor
device datasheet from the device manufacturer.
Related Information
• Arria V Device Datasheet
Provides more information about the external TSD specification.
• Arria V GT and GX Device Family Pin Connection Guidelines
Provides details about the TEMPDIODEP/TEMPDIODEN pin connection when you are not using an
external TSD.
• Arria V GZ Device Family Pin Connection Guidelines.
Provides details about the TEMPDIODEP/TEMPDIODEN pin connection when you are not using an
external TSD.
Hot-Socketing Feature
Arria V devices support hot socketing—also known as hot plug-in or hot swap.
The hot-socketing circuitry monitors the following power supplies and banks:
• Arria V GX, GT, SX, and ST devices—VCCIO, VCCPD, VCC, and VCCP power supplies and all VCCIO and
VCCPD banks.
• Arria V GZ devices—VCCIO, VCCPD, and VCC power supplies and all VCCIO and VCCPD banks.
When powering up or powering down these power supplies, refer to the Power-Up Sequence section of this
handbook.
During the hot-socketing operation, the I/O pin capacitance is less than 15 pF and the clock pin capacitance
is less than 20 pF.
The hot-socketing capability removes some of the difficulty that designers face when using the Arria V
devices on PCBs that contain a mixture of devices with different voltage requirements.
The hot-socketing capability in Arria V devices provides the following advantages:
• You can drive signals into the I/O, dedicated input, and dedicated clock pins before or during power up
or power down without damaging the device. External input signals to the I/O pins of the unpowered
device will not power the power supplies through internal paths within the device.
• The output buffers are tri-stated during system power up or power down. Because the Arria V device
does not drive signals out before or during power up, the device does not affect the other operating buses.
• You can insert or remove an Arria V device from a powered-up system board without damaging or
interfering with the system board's operation. This capability allows you to avoid sinking current through
the device signal pins to the device power supply, which can create a direct connection to GND that
causes power supply failures.
• During hot socketing, Arria V devices are immune to latch up that can occur when a device is hot-socketed
into an active system.
Altera uses GND as a reference for hot-socketing and I/O buffer circuitry designs. To ensure proper operation,
connect GND between boards before connecting the power supplies. This prevents GND on your board
from being pulled up inadvertently by a path to power through other components on your board. A pulled
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up GND could otherwise cause an out-of-specification I/O voltage or over current condition in the Altera
device.
Related Information
• Arria V GX, GT, SX, and ST Power-Up Sequence on page 11-7
• Arria V GZ Power-Up Sequence on page 11-8
• Arria V Device Datasheet
Provides details about the Arria V hot-socketing specifications.
Hot-Socketing Implementation
The hot-socketing feature tri-state the output buffer during power up and power down of the power supplies.
When these power supplies are below the threshold voltage, the hot-socketing circuitry generates an internal
HOTSCKT signal.
Hot-socketing circuitry prevents excess I/O leakage during power up. When the voltage ramps up very
slowly, I/O leakage is still relatively low, even after the release of the POR signal and configuration is complete.
Note: The output buffer cannot flip from the state set by the hot-socketing circuitry at very low voltage.
To allow the CONF_DONE and nSTATUS pins to operate during configuration, the hot-socketing feature
is not applied to these configuration pins. Therefore, these pins will drive out during power up and
power down.
Figure 11-3: Hot-Socketing Circuitry for Arria V Devices
Power-On
Reset (POR)
Monitor
VCCIO
Weak
Pull-Up
Resistor
PAD
R
Output Enable
Voltage
Tolerance
Control
Hot-Socket
Output
Pre-Driver
Input Buffer
to Logic Array
The POR circuitry monitors the voltage level of the power supplies and keeps the I/O pins tri-stated until
the device is in user mode. The weak pull-up resistor (R) in the Arria V input/output element (IOE) is enabled
during configuration download to keep the I/O pins from floating.
The 3.3-V tolerance control circuit allows the I/O pins to be driven by 3.3 V before the power supplies are
powered and prevents the I/O pins from driving out before the device enters user mode.
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Arria V GX, GT, SX, and ST Power-Up Sequence
11-7
Arria V GX, GT, SX, and ST Power-Up Sequence
Caution: To ensure minimum current consumption during power up, and to avoid functionality issue,
follow the power-up sequence shown in the following figure. This power-up sequence is required
for all Arria V GX and GT devices, except Arria V GX A5 and A7, and Arria V GT C7 devices.
However, to ensure minimum current consumption during power up, Altera recommends that
you also follow the power-up sequence for the Arria V GX A5 and A7, and Arria VGT C7 devices.
Note: If you plan to migrate your design from Arria V GX A5 and A7, and Arria V GT C7 devices to other
Arria V devices, your design must adhere to the power-up sequence required for the other Arria V
devices.
Figure 11-4: Power-Up Sequence Requirement for Arria V GX and GT Devices
Power up VCCBAT at any time. Ramp up the power rails in each group to a minimum of 80% of their full rail
before the next group starts. Power up VCCP, VCCR_GXB, VCCT_GXB, and VCCL_GXB together with VCC.
Group 1
VCC
VCCP
VCCR_GXB
VCCT_GXB
VCCL_GXB
Group 2
VCCPGM
VCCIO
VCCPD
VCCA_FPLL
VCCA_GXB
VCC_AUX
Group 3
VCCD_FPLL
VCCH_GXB
Figure 11-5: Power-Up Sequence Recommendation for Arria V SX and ST Devices
Power up the Vccbat at any time. Ramp up the power rails in each group to a minimum of 80% of their
recommended operating range before the next group starts.
Group 1
VCC
VCCP
VCCR_GXB
VCCT_GXB
VCCL_GXB
VCC_HPS
Group 2
VCCPGM
VCCIO
VCCPD
VCCA_FPLL
VCCA_GXB
VCC_AUX
VCCPD_HPS
VCCIO_HPS
VCCRSTCLK_HPS
VCCPLL_HPS
VCC_AUX_SHARED
Group 3
VCCD_FPLL
VCCH_GXB
Table 11-2 lists the current transient that you may observe at the indicated power rails after powering up
the Arria V device, and before configuration starts. These transients have a finite duration bounded by the
time at which the device enters configuration mode. For Arria V SX and ST devices, you may observe the
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current transient in Table 11-2 after powering up the device, and before all the power supplies reach the
recommended operating range.
Table 11-2: Maximum Power Supply Current Transient and Typical Duration
Power Rail
Maximum Power Supply
Current Transient (mA)
Typical Duration (µs)
VCCPD(45), (46)
1250
50
VCCIO(46), (47)
350
200
450
10
700
100
VCCPD_HPS(49), (50), (51)
400
50
VCCIO_HPS(49), (52), (51)
100
200
VCC_HPS(48), (49)
420
100
VCC_AUX
VCC
(48)
(48)
(44)
For details about the minimum current requirements, refer to the PowerPlay Early Power Estimator (EPE),
and compare to the information listed in Table 11-2. If the current transient exceeds the minimum current
requirements in the PowerPlay EPE, you need to take the information into consideration for your power
regulator design.
Related Information
PowerPlay Early Power Estimators (EPE) and Power Analyzer
Provides more information about the PowerPlay EPE support for Arria V devices.
Arria V GZ Power-Up Sequence
The Arria V GZ devices require a power-up sequence as shown in the following figure to prevent excessive
inrush current. This power-up sequence is divided into four power groups. Group 1 contains the first power
rails to ramp. The VCC, VCCHIP, and VCCHSSI power rails in this group must ramp to a minimum of 80% of
their full rail before any other power rails may start. Group 1 power rails can continue to ramp to full rail.
(44)
(45)
(46)
(47)
(48)
(49)
(50)
(51)
(52)
Only typical duration is provided as it may vary on the board design.
You may observe the current transient at VCCPD only when you do not follow the recommended power-up
sequence. To avoid the current transient at VCCPD, follow the recommended power-up sequence.
The maximum current for VCCIO and VCCPD applies to all voltage levels supported by the Arria V device.
You may observe the current transient at VCCIO if you power up VCCIO before VCCPD. To avoid the current
transient at VCCIO, follow the recommended power-up sequence by powering up VCCIO and VCCPD together.
You may observe the current transient at VCC_AUX, VCC and VCC_HPS with any power-up sequence.
These power rails are only available on Arria V SX and ST devices.
You may observe the current transient at VCCPD_HPS only when you do not follow the recommended powerup sequence. To avoid the current transient at VCCPD_HPS, follow the recommended power-up sequence.
The maximum current for VCCIO_HPS and VCCPD_HPS applies to all voltage levels supported by the Arria V
device.
You may observe the current transient at VCCIO_HPS if you power up VCCIO_HPS before VCCPD_HPS. To avoid
the current transient at VCCIO_HPS, follow the recommended power-up sequence by powering up VCCIO_HPS
and VCCPD_HPS together.
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The power rails in Group 2 and Group 4 can start to ramp in any order after Group 1 has reached its minimum
80% threshold. When the last power rail in Group 2 reaches 80% of its full rail, the remaining power rails
in Group 3 may start their ramp. During this time, Group 2 power rails may continue to ramp to full rail.
Power rails in Group 3 may ramp in any order. All power rails must ramp monotonically. The complete
power-up sequence must meet either the standard or fast POR delay time, depending on the POR delay
setting that is used.
Figure 11-6: Power-Up Sequence Requirement for Arria V GZ Devices
Power up VCCBAT at any time. If VCC, VCCR_GXB, and VCCT_GXB have the same voltage level, they can be
powered by the same regulator in Group 1 and ramp simultaneously.
Group 4
Group 1
Group 1
Group 2
Group 3
Group 4
VCC
VCCHIP
VCCHSSI
VCCPD
VCCPGM
VCCA_FPLL
VCC_AUX
VCCA_GXB
Group 2
Group 3
80% VCC
80% of Last Rail in Group 2
VCCPT
VCCH_GXB
VCCD_FPLL
VCCT_GXB
VCCR_GXB
VCCIO
Arria V GZ devices may power down all power rails simultaneously. However, all rails must reach 0 V within
100 ms from the start of power-down.
Power-On Reset Circuitry
The POR circuitry keeps the Arria V device in the reset state until the power supply outputs are within the
recommended operating range.
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Power-On Reset Circuitry
A POR event occurs when you power up the Arria V device until the power supplies reach the recommended
operating range within the maximum power supply ramp time, tRAMP. If tRAMP is not met, the Arria V device
I/O pins and programming registers remain tri-stated, during which device configuration could fail.
Figure 11-7: Relationship Between tRAMP and POR Delay
Volts
POR trip level
first power
supply
last power
supply
Time
POR delay
tRAMP
configuration
time
The Arria V POR circuitry uses an individual detecting circuitry to monitor each of the configuration-related
power supplies independently. The main POR circuitry is gated by the outputs of all the individual detectors.
The main POR signal is asserted when the power starts to ramp up. This signal is released after the last rampup power reaches the POR trip level during power up.
In user mode, the main POR signal is asserted when any of the monitored power goes below its POR trip
level. Asserting the POR signal forces the device into the reset state.
The POR circuitry checks the functionality of the I/O level shifters powered by the VCCPD and VCCPGM
power supplies during power-up mode. The main POR circuitry waits for all the individual POR circuitries
to release the POR signal before allowing the control block to start programming the device.
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Power Supplies Monitored and Not Monitored by the POR Circuitry
11-11
Figure 11-8: Simplified POR Diagram for Arria V Devices
VCC
VCC POR
VCCP
VCCP POR
VCC_AUX
Modular
Main POR
VCC_AUX POR
Main POR
VCCPD
VCCPGM
Related Information
Arria V Device Datasheet
Provides more information about the POR delay specification and tRAMP.
Power Supplies Monitored and Not Monitored by the POR Circuitry
Table 11-3: Power Supplies Monitored and Not Monitored by the Arria V POR Circuitry
Devices
Power Supplies
Monitored
Power Supplies Not Monitored
Arria V
GX and GT
•
•
•
•
•
•
VCC_AUX
VCCBAT
VCC
VCCP
VCCPD
VCCPGM
•
•
•
•
•
•
•
•
VCCT_GXB
VCCH_GXB
VCCR_GXB
VCCA_GXB
VCCL_GXB
VCCA_FPLL
VCCD_FPLL
VCCIO
Arria V GZ
•
•
•
•
•
•
VCC_AUX
VCCBAT
VCC
VCCPT
VCCPD
VCCPGM
•
•
•
•
•
•
•
•
VCCT_GXB
VCCH_GXB
VCCR_GXB
VCCA_GXB
VCCA_FPLL
VCCD_FPLL
VCCIO
VCCHIP
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Devices
Arria V
SX and ST
Power Supplies
Monitored
•
•
•
•
•
•
•
•
•
VCC_AUX
VCCBAT
VCC
VCCP
VCCPD
VCCPGM
VCC_HPS
VCCPD_HPS
VCCRSTCLK_HPS
Power Supplies Not Monitored
•
•
•
•
•
•
•
•
•
•
VCCT_GXB
VCCH_GXB
VCCR_GXB
VCCA_GXB
VCCL_GXB
VCCA_FPLL
VCCD_FPLL
VCCIO
VCCIO_HPS
VCCPLL_HPS
Note: For the device to exit POR, you must power the VCCBAT power supply even if you do not use the
volatile key.
Related Information
Configuration, Design Security, and Remote System Upgrades in Arria V Devices
Provides information about the MSEL pin settings for each POR delay.
Document Revision History
Date
Version
January 2014
2014.01.10
Updated the note to the VCCPD_HPS power rail that current transient at
VCCPD_HPS is observed only when the recommended power-up sequence
is not followed. To avoid the current transient at VCCPD_HPS, follow the
recommended power-up sequence.
June 2013
2013.06.28
• Added power-up sequences for Arria V SX and ST devices.
• Added the current transient that occurs on HPS power rails during
power-up
May 2013
2013.05.06
• Added link to the known document issues in the Knowledge Base.
• Moved all links to the Related Information section of respective topics
for easy reference.
• Updated dynamic power in Power Consumption for improve clarity.
• Added description on powering down unused PCIe HIPS in
Programmable Power Technology
• Updated Hot-Socketing Feature with 'When powering up these power
supplies, refer to the Power-Up Sequence section of this handbook.'
• Updated description about power-up sequence requirement for device
migration to improve clarity.
• Updated Figure 11-5 by renaming VCCA_GXB/GTB, VCCT_GXB/GTB,
VCCR_GXB/GTB to VCCA_GXB, VCCT_GXB, VCCR_GXB and deleting
VCCL_GTB.
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Document Revision History
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Date
Version
Changes
January 2013
2013.01.11
Updated the power-up sequence for Arria V GX and GT devices.
November 2012
2012.11.19
• Added the Programmable Power Technology section for Arria V GZ
devices.
• Added the External TSD section for Arria V GZ devices.
• Added the Power-up sequence section for Arria V GZ devices.
• Added the power supplies monitored and not monitored by the
Arria V GZ devices.
• Reorganized content and updated template.
June 2012
2.1
Updated the "Power-Up Sequence" section.
June 2012
2.0
• Restructured the chapter.
• Added the "Power-Up Sequencing" section.
February 2012
1.3
Updated VCCP description.
December 2011
1.2
• Added VCCP information.
• Updated Table 11-1.
November 2011
1.1
Restructured chapter.
May 2011
1.0
Initial release.
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Arria V Device Handbook
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TOC-2
Arria V Device Handbook Volume 2: Transceivers
Contents
Transceiver Architecture in Arria V Devices......................................................1-1
Architecture Overview................................................................................................................................1-2
Transceiver Banks............................................................................................................................1-2
10-Gbps Support Capability in GT and ST Devices....................................................................1-7
Transceiver Channel Architecture.................................................................................................1-7
PMA Architecture........................................................................................................................................1-8
Transmitter PMA Datapath...........................................................................................................1-9
Receiver PMA Datapath................................................................................................................1-14
Transmitter PLL.............................................................................................................................1-23
Clock Divider..................................................................................................................................1-25
Calibration Block...........................................................................................................................1-26
PCS Architecture........................................................................................................................................1-28
Transmitter PCS Datapath for Arria V GX, SX, GT, and ST Devices and Arria V GZ
Standard PCS............................................................................................................................1-29
Receiver PCS Datapath for Arria V GX, SX, GT, and ST Devices and Arria V GZ Standard
PCS.............................................................................................................................................1-33
10G PCS Architecture for Arria V GZ Devices.........................................................................1-48
PCIe Gen 3 PCS Architecture......................................................................................................1-55
Channel Bonding.......................................................................................................................................1-58
Bonded Channel Configurations.................................................................................................1-58
Non-Bonded Channel Configurations.......................................................................................1-58
PLL Sharing................................................................................................................................................1-58
Document Revision History.....................................................................................................................1-58
Transceiver Clocking in Arria V Devices............................................................2-1
Input Reference Clocking...........................................................................................................................2-1
Reference Clock Network...............................................................................................................2-5
Dual-Purpose RX/refclk Pin...........................................................................................................2-5
Fractional PLL (fPLL)......................................................................................................................2-6
Internal Clocking.........................................................................................................................................2-7
Transmitter Clock Network...........................................................................................................2-7
Transmitter Clocking....................................................................................................................2-18
Receiver Clocking..........................................................................................................................2-31
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Arria V Device Handbook Volume 2: Transceivers
TOC-3
FPGA Fabric–Transceiver Interface Clocking.......................................................................................2-39
Transceiver Datapath Interface Clocking...................................................................................2-41
Transmitter Datapath Interface Clocking..................................................................................2-41
Receiver Datapath Interface Clock..............................................................................................2-46
GXB 0 PPM Core Clock Assignment for GZ Devices..............................................................2-50
Document Revision History.....................................................................................................................2-50
Transceiver Reset Control in Arria V Devices....................................................3-1
PHY IP Embedded Reset Controller.........................................................................................................3-2
Embedded Reset Controller Signals..............................................................................................3-2
Resetting the Transceiver with the PHY IP Embedded Reset Controller during Device
Power-Up.....................................................................................................................................3-4
Resetting the Transceiver with the PHY IP Embedded Reset Controller during Device
Operation.....................................................................................................................................3-5
User-Coded Reset Controller.....................................................................................................................3-6
User-Coded Reset Controller Signals............................................................................................3-7
Resetting the Transmitter with the User-Coded Reset Controller during Device Power-Up
.......................................................................................................................................................3-8
Resetting the Transmitter with the User-Coded Reset Controller during Device
Operation.....................................................................................................................................3-9
Resetting the Receiver with the User-Coded Reset Controller during Device Power-Up
Configuration............................................................................................................................3-10
Resetting the Receiver with the User-Coded Reset Controller during Device
Operation...................................................................................................................................3-11
Transceiver Reset Using Avalon Memory Map Registers....................................................................3-12
Transceiver Reset Control Signals Using Avalon Memory Map Registers............................3-12
Resetting the Transceiver in CDR Manual Lock Mode........................................................................3-13
Control Settings for CDR Manual Lock Mode..........................................................................3-13
Resetting the Transceiver in CDR Manual Lock Mode............................................................3-13
Resetting the Transceiver During Dynamic Reconfiguration.............................................................3-14
Guidelines for Dynamic Reconfiguration if Transmitter Duty Cycle Distortion Calibration
is Required during Device Operation....................................................................................3-15
Transceiver Blocks Affected by the Reset and Powerdown Signals....................................................3-15
Transceiver Power-Down.........................................................................................................................3-17
Document Revision History.....................................................................................................................3-17
Transceiver Protocol Configurations in Arria V Devices..................................4-1
PCI Express...................................................................................................................................................4-2
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TOC-4
Arria V Device Handbook Volume 2: Transceivers
PIPE Transceiver Datapath............................................................................................................4-3
PCIe Supported Features................................................................................................................4-4
PIPE Transceiver Channel Placement Guidelines......................................................................4-7
PCIe Supported Configurations and Placement Guidelines......................................................4-9
PIPE Transceiver Clocking...........................................................................................................4-12
Gigabit Ethernet.........................................................................................................................................4-15
Gigabit Ethernet Transceiver Datapath......................................................................................4-17
XAUI............................................................................................................................................................4-20
Transceiver Datapath in a XAUI Configuration.......................................................................4-21
XAUI Supported Features............................................................................................................4-23
Transceiver Clocking and Channel Placement Guidelines in XAUI Configuration...........4-26
10GBASE-R................................................................................................................................................4-28
10GBASE-R Transceiver Datapath Configuration...................................................................4-30
10GBASE-R Supported Features.................................................................................................4-31
10GBASE-R Transceiver Clocking..............................................................................................4-33
Serial Digital Interface...............................................................................................................................4-33
Configurations Supported in SDI Mode.....................................................................................4-34
Serial Digital Interface Transceiver Datapath............................................................................4-35
Gigabit-Capable Passive Optical Network (GPON).............................................................................4-35
Serial Data Converter (SDC) JESD204...................................................................................................4-36
SATA and SAS Protocols..........................................................................................................................4-37
Deterministic Latency Protocols—CPRI and OBSAI...........................................................................4-40
Latency Uncertainty Removal with the Phase Compensation FIFO in Register Mode.......4-40
Channel PLL Feedback for Deterministic Relationship...........................................................4-40
CPRI and OBSAI............................................................................................................................4-41
CPRI Enhancements......................................................................................................................4-43
Serial RapidIO............................................................................................................................................4-43
Document Revision History.....................................................................................................................4-45
Transceiver Custom Configurations in Arria V Devices...................................5-1
Standard PCS Configuration......................................................................................................................5-1
Custom Configuration Channel Options.....................................................................................5-2
Rate Match FIFO in Custom Configuration................................................................................5-5
Standard PCS in Low Latency Configuration........................................................................................5-10
Low Latency Custom Configuration Channel Options............................................................5-11
PMA Direct.................................................................................................................................................5-13
Document Revision History.....................................................................................................................5-14
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Arria V Device Handbook Volume 2: Transceivers
TOC-5
Transceiver Configurations in Arria V GZ Devices...........................................6-1
10GBASE-R and 10GBASE-KR.................................................................................................................6-1
10GBASE-R and 10GBASE-KR Transceiver Datapath Configuration....................................6-3
10GBASE-R and 10GBASE-KR Supported Features..................................................................6-7
1000BASE-X and 1000BASE-KX Transceiver Datapath..........................................................6-10
1000BASE-X and 1000BASE-KX Supported Features.............................................................6-10
Synchronization State Machine Parameters in 1000BASE-X and 1000BASE-KX
Configurations..........................................................................................................................6-13
Transceiver Clocking in 10GBASE-R, 10GBASE-KR, 1000BASE-X, and 1000BASE-KX
Configurations..........................................................................................................................6-13
Interlaken....................................................................................................................................................6-13
Transceiver Datapath Configuration..........................................................................................6-14
Supported Features........................................................................................................................6-15
Transceiver Clocking.....................................................................................................................6-17
PCI Express (PCIe)—Gen1, Gen2, and Gen3........................................................................................6-19
Transceiver Datapath Configuration..........................................................................................6-19
Supported Features for PCIe Configurations............................................................................6-22
Supported Features for PCIe Gen3..............................................................................................6-26
Transceiver Clocking and Channel Placement Guidelines......................................................6-29
Advanced Channel Placement Guidelines for PIPE Configurations.....................................6-37
Transceiver Clocking for PCIe Gen3..........................................................................................6-42
XAUI............................................................................................................................................................6-49
Transceiver Datapath in a XAUI Configuration.......................................................................6-50
Supported Features........................................................................................................................6-52
Transceiver Clocking and Channel Placement Guidelines......................................................6-55
CPRI and OBSAI—Deterministic Latency Protocols...........................................................................6-56
Transceiver Datapath Configuration..........................................................................................6-56
Phase Compensation FIFO in Register Mode............................................................................6-58
Channel PLL Feedback..................................................................................................................6-58
CPRI and OBSAI............................................................................................................................6-58
Transceiver Configurations......................................................................................................................6-61
Standard PCS Configurations—Custom Datapath...................................................................6-61
Standard PCS Configurations—Low Latency Datapath..........................................................6-66
Transceiver Channel Placement Guidelines..............................................................................6-70
10G PCS Configurations...............................................................................................................6-72
Merging Instances..........................................................................................................................6-78
Native PHY IP Configuration..................................................................................................................6-79
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TOC-6
Arria V Device Handbook Volume 2: Transceivers
Protocols and Transceiver PHY IP Support..............................................................................6-80
Native PHY Transceiver Datapath Configuration....................................................................6-83
Standard PCS Features..................................................................................................................6-85
10G PCS Supported Features.......................................................................................................6-86
10G Datapath Configurations with Native PHY IP..................................................................6-88
PMA Direct Supported Features..................................................................................................6-90
Channel and PCS Datapath Dynamic Switching Reconfiguration.........................................6-91
Document Revision History.....................................................................................................................6-91
Transceiver Loopback Support in Arria V Devices............................................7-1
Serial Loopback............................................................................................................................................7-1
Forward Parallel Loopback.........................................................................................................................7-2
PIPE Reverse Parallel Loopback................................................................................................................7-3
Reverse Serial Loopback..............................................................................................................................7-3
Reverse Serial Pre-CDR Loopback............................................................................................................7-4
Document Revision History.......................................................................................................................7-6
Dynamic Reconfiguration in Arria V Devices....................................................8-1
Dynamic Reconfiguration Features...........................................................................................................8-1
Offset Cancellation......................................................................................................................................8-3
Transmitter Duty Cycle Distortion Calibration......................................................................................8-3
PMA Analog Controls Reconfiguration...................................................................................................8-4
Dynamic Reconfiguration of Loopback Modes.......................................................................................8-4
Transceiver PLL Reconfiguration .............................................................................................................8-5
Transceiver Channel Reconfiguration......................................................................................................8-5
Transceiver Interface Reconfiguration ....................................................................................................8-6
Reduced .mif Reconfiguration ..................................................................................................................8-7
On-Chip Signal Quality Monitoring (EyeQ)...........................................................................................8-7
Adaptive Equalization.................................................................................................................................8-7
Decision Feedback Equalization................................................................................................................8-8
Unsupported Reconfiguration Modes......................................................................................................8-8
Document Revision History.......................................................................................................................8-9
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Describes the Arria® V transceiver architecture, channels, and transmitter and receiver channel datapaths.
Altera® 28-nm Arria V FPGAs provide integrated transceivers with the lowest power requirement at 12.5-,
10-, and 6-Gigabits per second (Gbps). These transceivers comply with a wide range of protocols and data
rate standards.
Table 1-1: Arria V Variants
Variants
Hard Processor System (HPS)
Up to 6.5536 Gbps
Beyond 6.5536 Gbps
GX
N/A
Backplane
N/A
GT
N/A
Backplane
N/A
GZ
N/A
Backplane
Up to 12.5 Gbps with backplane
support
SX
Yes
Backplane
N/A
ST
Yes
Backplane
N/A
Related Information
Arria V Device Handbook: Known Issues
Lists the planned updates to the Arria V Device Handbook chapters.
© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words
and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other
words and logos identified as trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with
Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes
no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
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Architecture Overview
Architecture Overview
Figure 1-1: Basic Layout of Transceivers in Arria V Devices
Hard
PCS
Hard
PCS
Hard
PCS
Hard
PCS
Clock Networks
Transceiver
PMA
Transceiver
PMA
Transceiver
PMA
Transceiver
PMA
Fractional Fractional
PLL
PLL
Transceiver PMA Blocks
PCIe Hard IP Blocks
Hard PCS Blocks
Fractional PLLs
Fractional PLLs
Hard PCS Blocks
PCIe Hard IP Blocks
Transceiver PMA Blocks
I/O, LVDS, and Memory Interface
Hard Memory Controller
Transceiver
Individual Channels
Distributed Memory
Core Logic Fabric and MLABs
M10K or M20K
Internal Memory Blocks
Hard Memory Controller
I/O, LVDS, and Memory Interface
Variable-Precision DSP Blocks
Notes:
1. This figure represents one variant of an Arria V device. Other variants may have transceivers and PCI Express (PCIe)
hard IP only on the left side of the device.
2. This figure is a graphical representation of a top view of the silicon die, which corresponds to a reverse view for flip
chip packages.
The Arria V hard IP for PCIe implements the PCIe protocol stack including the following layers:
• Physical interface/media access control (PHY/MAC) layer
• Data link layer
• Transaction layer
The embedded hard IP saves significant FPGA resources, reduces design risk, and reduces the time required
to achieve timing closure. The hard IP complies with the PCI Express Base Specification 1.1, 2.0, and 3.0 for
Gen1, Gen2, and Gen3 signaling data rates, respectively. In addition, the Arria V GZ variant supports PCI
Express Base Specification 3.0 for Gen3 signaling datarates.
Related Information
For more information about the PCIe hard IP block architecture, see the Arria V Hard IP for PCI Express
User Guide.
Transceiver Banks
The columns of Arria V transceivers are categorized in banks of six channels. The transceiver bank boundaries
are important for clocking resources, bonding channels, and fitting. In some package variations, some
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Transceiver Banks
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transceiver banks are reduced to three channels. In the Arria V GX/GT/SX/ST, there are fundamentally two
types of transceiver channels; 6-Gbps and 10-Gbps. By contrast, every Arria V GZ transceiver channel
supports operation up to 12.5 Gbps data rates.
Figure 1-2: Transceiver Bank and PCIe HIP Location for GX Devices
36 Ch
GXB_L2
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
24 Ch
GXB_L1
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
9 Ch
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
GXB_L0
18 Ch
HIP (1)
HIP (1)
(1), (2)
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
GXB_R2
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
GXB_R1
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
GXB_R0
Notes:
1. PCIe HIP availability varies with device variants.
2. Blue blocks are 6 Gbps channels.
Table 1-2: HIP and Channel Resources in GX Variants
GX Variants
Left HIP
Right HIP
Total Channels
Base
None
None
9
Mainstream
1
None
9, 18
Extended Feature
1
1
24, 36
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Transceiver Banks
Figure 1-3: Transceiver Bank and PCIe HIP Location for GT Devices
36 Ch
GXB_L2
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
24 Ch
GXB_L1
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
9 Ch
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
GXB_L0
18 Ch
PCIe
Hard IP
with
CvP
PCIe
Hard
IP
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
GXB_R2
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
GXB_R1
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
GXB_R0
Table 1-3: HIP and Channel Resources in GT Variants
GT Variants
Left HIP
Right HIP
Total Channels
Mainstream
1
None
9, 18
Extended Feature
1
1
24, 36
Figure 1-4: Transceiver Bank and PCIe HIP Location for GZ Devices
36 Channels
GXB_L2
6 Ch
6 Ch
GXB_R2
GXB_L1
6 Ch
6 Ch
GXB_R1
PCIe
Hard
IP
GXB_L0
6 Ch
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
24
Channels
6 Ch
GXB_R0
Notes:
1. 12-channel devices use banks L0 and L1.
2. All channels capable of backplane support up to 12.5 Gbps.
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1-5
Figure 1-5: Transceiver Bank Location for SX Devices (9 channels)
SX devices with 9 channels do not have PCIe HIP blocks.
GXB_L2
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
GXB_L1
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
GXB_L0
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
9 Ch
F1517
9 Ch
F896
Ch2
Ch1
Ch0
9 Ch
F1152
GXB_R0
Note: Blue blocks are 6 Gbps channels.
Figure 1-6: Transceiver Bank and PCIe HIP Location for SX Devices (12,18, 30 channels)
GXB_L2
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
GXB_L1
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
GXB_L0
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
30 Ch
18 Ch
F1517
18 Ch
F1152
12 Ch
HIP (1)
(1)
HIP (1)
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
GXB_R1
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
GXB_R0
Notes:
1. PCIe HIP availability varies with device variants.
2. Blue blocks are 6 Gbps channels.
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Transceiver Banks
Table 1-4: HIP and Channel Resources in SX Variants
SX Variants
Left HIP
Mainstream
Extended Feature
Right HIP
Total Channels
None
1
12
1
None
18 (F1517 package)
1
1
18 (F1152 package)
1
1
30
(1), (2), (3)
Figure 1-7: Transceiver Bank and PCIe HIP Location for ST Devices
GXB_L2
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
GXB_L1
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
GXB_L0
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
30 Ch
18 Ch
12 Ch
HIP (1)
HIP
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
GXB_R1
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
GXB_R0
Notes:
1. PCIe HIP availability varies with device variants.
2. Green blocks are 10-Gbps channels.
3. Blue blocks are 6-Gbps channels. With the exception of Ch0 to Ch2 in GXB_L0 and GXB_R0,
the 6-Gbps channels can be used for TX-only or RX-only 10-Gbps channels.
Table 1-5: HIP and Channel Resources in ST Variants
ST Variants
Mainstream
Extended Feature
Altera Corporation
Left HIP
Right HIP
Total Channels
None
1
12
1
1
18
1
1
30
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10-Gbps Support Capability in GT and ST Devices
1-7
Table 1-6: Usage Restrictions on Specific Channels Across Device Variants
Device Variants
GX, SX
Channel Location
Ch1, Ch2 of GXB_L0(1)
Ch1, Ch2 of GXB_R0(1)
Usage Restriction
No support for PCS with phase compensation
FIFO in registered mode (for example, CPRI
or deterministic latency)
No support for PCS with phase compensation
FIFO in registered mode (for example, CPRI
or deterministic latency)
ST, GT
Ch1, Ch2 of GXB_L0 and
GXB_R0(1)
ST
Ch0, Ch1, Ch2 of GXB_L0 and No PMA Direct Support
GXB_R0
GT
Ch0, Ch1, Ch2 of GXB_L0 and No PMA Direct Support
GXB_R0(1)
10-Gbps Support Capability in GT and ST Devices
Arria V GT/ST devices support up to four full duplex 10-Gbps channels in each transceiver bank. The bottom
transceiver banks, and transceiver banks with only three transceiver channels, support up to two full duplex
10-Gbps channels.
Enhanced Small Form-Factor Pluggable (SFP+) Interface
Arria V GT devices are compliant to SFF 8431 with considerations to the number of channel requirements
and board designs. Please contact you local Altera sales representative for details.
10GBase-KR Support
For 10GBase-KR support, please contact Altera.
9.8 Gbps CPRI Application
For 9.8 Gbps CPRI support, please contact Altera.
Transceiver Channel Architecture
The Arria V transceivers are comprised of a transmitter and receiver that can operate individually or
simultaneously—providing a full-duplex physical layer implementation for high-speed serial interfacing.
Each transmitter and receiver are divided into two blocks: PMA and PCS. The PMA block connects the
FPGA to the channel, generates the required clocks, and converts the data from parallel to serial or serial to
parallel. The PCS block performs digital processing logic between the PMA and the FPGA core.
(1)
The PMA clock of Channel 1 and Channel 2 of GBX_L0 and GXB_R0 cannot be routed out of the FPGA fabric
for Arria V GX, GT, ST, and SX devices.
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PMA Architecture
Figure 1-8: Full Duplex Channel Interface Architecture
Up to 12.5 Gbps in AVGZ or
up to 10.3125 Gbps in AVGT/ST (1)
Up to 12.5Gbps in AVGZ or
up to 6.5536 Gbps in AVGX/GT/SX/ST
PCIe with Soft IP
PCIe with HIP (2)
HIP
PIPE
FPGA Fabric
PCS
PMA
Transceiver Resources
tx_serial_data
rx_serial_data
Serial Interface
Notes:
1. 10-Gbps channel is available in GT and ST variants.
2. See the Related Information for specific channels that support interfaces with the HIP.
3. GX and GT can support up to 6.5536 Gbps.
4. GZ can support up to 12.5 Gbps.
Table 1-7: Architecture Differences Between 6- and 10-Gbps Arria V GT/ST Channels and Arria V GZ Channels
Architecture Differences
(2)
6-Gbps Channel
10-Gbps Channel
Arria V GZ Channel
Transmitter PCS
Capability
Up to 6.5536 Gbps Up to 6.5536 Gbps Up to 12.5 Gbps
Receiver PCS Capability
Up to 6.5536 Gbps Up to 6.5536 Gbps Up to 12.5 Gbps
(3)
Transmitter/Receiver PMA Up to 6.5536 Gbps Up to 10.3125 Gbps Up to 12.5 Gbps
Capability
PMA Direct (PMA-Fabric Not supported
Interface)
Supported
Serialization Factor
8, 10, 16, 20, 64, 80 8, 10, 16, 20, 32, 40, 64, 80
8, 10, 16, 20
Supported
Related Information
Arria V Hard IP for PCI Express User Guide
PMA Architecture
The PMA includes the transmitter and receiver datapaths, CMU PLL (configured from the channel PLL),
the ATX PLL, and the clock divider. The analog circuitry and differential on-chip termination (OCT) in the
PMA requires the calibration block to compensate for process, voltage, and temperature variations (PVT).
(2)
(3)
10-Gbps channel is only available in GT and ST variants.
Arria V GT/ST devices cannot use the PCS when running at 10 Gbps.
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Transmitter PMA Datapath
1-9
Figure 1-9: Transceiver Channel PMA for Arria V Devices
Transmitter PMA
From the Transmitter PCS
or FPGA Fabric (1)
Serializer
Transmitter
Buffer
High-speed
Clock
Networks
Clock
Divider
From ATX PLL
(3)
Physical
Transmission
Medium
(2)
To the Receiver PCS
or FPGA Fabric (1)
Deserializer
(3) Channel PLL
(CMU PLL or
CDR)
Receiver
Buffer
Receiver PMA
Notes:
1. The channel PLL provides the serial clock when configured as a CMU PLL.
2. The channel PLL recovers the clock and serial data stream when configured as a CDR.
3. ATX PLL available only in GZ devices.
Transmitter PMA Datapath
Table 1-8: Functional Blocks in the Transmitter PMA Datapath
Block
Functionality
Serializer
• Converts the incoming low-speed parallel data from the transmitter PCS to
high-speed serial data and sends the data LSB first to the transmitter buffer.
• Supports the optional polarity inversion and bit reversal features.
• Supports 8, 10, 16, and 20-bit serialization factors in Arria V GX, SX, GT, ST,
and GZ devices.
• Additionally supports 64 and 80-bit serialization factors for 10-Gbps transceiver
channels in Arria V ST and GT devices.
• Additionally supports 32, 40, 64, and 80-bit serialization factors in Arria V GZ
devices.
Transmitter Buffer
• The 1.4-V (Arria V GZ Only) and 1.5-V pseudo current mode logic (PCML)
output buffer conditions the high-speed serial data for transmission into the
physical medium. Arria GZ supports 1.4 and 1.5V PCML.
• Supports the following features:
• Programmable differential output voltage (VOD )
• Programmable pre-emphasis
• Programmable VCM current strength
• Programmable slew rate
• On-chip biasing for common-mode voltage (TX VCM )
• Differential OCT (85, 100, 120 and 150 Ω )
• Transmitter output tristate
• Receiver detect (for the PCIe receiver detection function)
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Serializer
Serializer
The serializer provides parallel-to-serial data conversion and sends the data LSB first from the transmitter
physical coding sublayer (PCS) to the transmitter buffer. Additionally, the serializer provides the polarity
inversion and bit reversal features.
Polarity Inversion
The positive and negative signals of a serial differential link might accidentally be swapped during board
layout.
The polarity inversion feature of the transmitter corrects this error without requiring a board respin or major
updates to the logic in the FPGA fabric. The polarity inversion feature inverts the polarity of every bit at the
input to the serializer, which has the same effect as swapping the positive and negative signals of the serial
differential link.
Polarity inversion is controlled dynamically with the tx_invpolarity register. When you enable the polarity
inversion feature, it may cause initial disparity errors at the receiver with 8B/10B-coded data. The downstream
system at the receiver must be able to tolerate these disparity errors.
Caution: Enabling polarity inversion midway through a serialized word corrupts the word.
Bit Reversal
You can reverse the transmission bit order to achieve MSB-to-LSB ordering using the bit reversal feature at
the transmitter.
Table 1-9: Bit Reversal Feature
Transmission Bit Order
Bit Reversal Option
8- or 10-bit Serialization
Factor
16- or 20-bit Serialization Factor
Disabled (default)
LSB to MSB
LSB to MSB
Enabled
MSB to LSB
MSB to LSB
For example:
For example:
8-bit—D[7:0] rewired to
16-bit—D[15:0] rewired to D[0:15]
D[0:7]
20-bit—D[19:0] rewired to D[0:19]
10-bit—D[9:0] rewired to
D[0:9]
Transmitter Buffer
The transmitter buffer includes additional circuitry to improve signal integrity, such as the programmable
differential output voltage (VOD), programmable three-tap pre-emphasis circuitry, internal termination
circuitry, and PCIe receiver detect capability to support a PCIe configuration.
Modifying programmable values within transmitter output buffers can be performed by a single reconfiguration controller for the entire FPGA, or multiple reconfiguration controllers if desired. Within each
transceiver bank a maximum of two reconfiguration controllers is allowed; one for the three-transceiver
triplet in the upper-half of the bank, and one for the lower-half. This is due to a single slave interface to all
PLLs and PMAs within each triplet. Therefore, many triplets can be connected to a single reconfiguration
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Transmitter Buffer
1-11
controller, but only one reconfiguration controller can be connected to the three transceivers within any
triplet.
Note: A maximum of one reconfiguration controller is allowed per transceiver bank upper-half or lowerhalf triplet.
Note: The Arria V GT transmitter buffer has only one tap for the pre-emphasis.
Transmitter
Output
Tri-State
From Serializer
Programmable
Pre-Emphasis
and VOD
Differential OCT
(85, 100, 120, or 150 Ω)
Figure 1-10: Transmitter Buffer in Arria V Devices
+ Tx –
VCM
High-speed
Differential
Transmitter
Channel
Output Pins
Receiver
Detect
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Transmitter Buffer
Table 1-10: Description of the Transmitter Buffer Features
Category
Features
Description
Controls the current mode drivers for signal amplitude to
Programmable
Differential Output handle different trace lengths, various backplanes, and receiver
requirements. The actual VOD level is a function of the current
Voltage (VOD)
setting and the transmitter termination value.
Improve Signal
Integrity
Programmable Pre- Boosts the high-frequency components of the transmitted
signal, which may be attenuated when propagating through
Emphasis
the transmission medium. The physical transmission medium
can be represented as a low-pass filter in the frequency domain.
Variation in the signal frequency response that is caused by
attenuation significantly increases the data-dependent jitter
and other intersymbol interference (ISI) effects at the receiver
end. Using the pre-emphasis feature maximizes the data
opening at the far-end receiver.
Arria V GZ channels provide three pre-emphasis taps: pre-tap
(16 settings), first post-tap (32 settings), and second post-tap
(16 settings). Arria V GX, SX, GT and ST provides only one
pre-emphasis tap which is first post-tap (32 settings).The pretap sets the pre-emphasis on the data bit before the transition.
The first post-tap and second post-tap set the pre-emphasis
on the transition bit and the following bit, respectively. The
pre-tap and second post-tap also provide inversion control,
shown by negative values.
Programmable Slew Controls the rate of change for the signal transition.
Rate
On-Chip Biasing
Save Board Space and
Differential OCT
Cost
Reduce Power
Altera Corporation
Establishes the required transmitter common-mode voltage
(TX VCM) level at the transmitter output. The circuitry is
available only if you enable on-chip termination (OCT). When
you disable OCT, you must implement off-chip biasing
circuitry to establish the required TX VCM level.
The termination resistance is adjusted by the calibration
circuitry, which compensates for the process, voltage, and
temperature variations (PVT). You can disable OCT and use
external termination. However, you must implement off-chip
biasing circuitry to establish the required TX VCM level. TX
VCM is tri-stated when using external termination.
Programmable VCM Controls the impedance of VCM. A higher impedance setting
Current Strength
reduces current consumption from the on-chip biasing
circuitry.
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Transmitter Buffer
Category
Features
1-13
Description
Transmitter Output Enables the transmitter differential pair voltages to be held
constant at the same value determined by the TX VCM level
Tri-State
with the transmitter in the high impedance state.
The transmitter output tri-state feature is compliant with
differential and common-mode voltage levels and operation
time requirements for transmitter electrical idle, as specified
in the PCI Express Base Specification 2.0 for Gen1 and Gen2
signaling rates, and PCI Express Base Specification 3.0 for Gen3
signaling rates (Arria V GZ only).
Receiver Detect
Protocol-Specific
Function
Provides link partner detection capability at the transmitter
end using an analog mechanism for the receiver detection
sequence during link initialization in the Detect state of the
PCI Express® (PCIe) Link Training and Status State Machine
(LTSSM) states. The circuit detects if there is a receiver
downstream by changing the transmitter VCM to create a step
voltage and measuring the resulting voltage rise time.
For proper functionality, the series capacitor (AC-coupled
link) and receiver termination values must comply with the
PCI Express Base Specification 2.0 for Gen1 and Gen2 signaling
rates and PCI Express Base Specification 3.0 for Gen3 signaling
rates (Arria V GZ only). The circuit is clocked using fixedclk
and requires that the transmitter OCT be enabled with the
output tri-stated.
Figure 1-11: Example of Pre-Emphasis Effect on Signal Transmission at Transmitter Output
Shows the signal transmission at the transmitter output with and without applying pre-emphasis post-tap
for a 5 Gigabit per second (Gbps) signal with an alternating data pattern of five 1s and five 0s.
VOD Differential
Peak-to-Peak
Output
Voltage
With Pre-Emphasis
Without Pre-Emphasis
1-bit period
The receiver can be AC- or DC-coupled to a transmitter. In an AC-coupled link, the AC-coupling capacitor
blocks the transmitter VCM. At the receiver end, the termination and biasing circuitry restores the VCM level
that is required by the receiver.
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Receiver PMA Datapath
Figure 1-12: AC-Coupled Link with Arria V Transmitter
AC-Coupling
Capacitor
–
VCM
RX
VCM
Differential Termination
+ TX –
+
Transmitter
Differential Termination
Physical Medium
Receiver
Physical Medium
AC-Coupling
Capacitor
(1)
Notes:
1. When you disable OCT, you must implement external termination and off-chip biasing circuitry to establish the required TX V CM level.
When used in a DC-coupled link, the transmitter Vcm is fixed to 0.7 V. The receiver Vcm is required to be
at 0.7 V. DC coupling is supported for serial data rates up to 3.2 Gbps.
You can DC-couple the Arria V GZ channel transmitter only to another Arria V GZ channel receiver for
the entire datarate range from 600 Mbps to 12.5 Gbps so long as the same VCM value is observed.
Figure 1-13: DC-Coupled Link with Arria V Transmitter
–
VCM
RX
VCM
Differential Termination
+ TX –
+
Transmitter
Differential Termination
Physical Medium
Receiver
Physical Medium
Related Information
• Arria V Device Datasheet
• Altera Transceiver PHY IP Core User Guide
Receiver PMA Datapath
Describes the receiver buffer, channel phase-locked loop (PLL) configured for clock data recovery (CDR)
operation, and deserializer blocks in the receiver PMA datapath.
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Receiver Buffer
1-15
Table 1-11: Functional Blocks in the Receiver PMA Datapath
Block
Receiver Buffer
Functionality
• Receives the serial data stream and feeds the stream to the channel PLL
if you configure the channel PLL as a CDR.
• Supports the following features:
•
•
•
•
•
Programmable CTLE (Continuous Time Linear Equalization)
Programmable DC gain
Programmable VCM current strength
On-chip biasing for common-mode voltage (RX VCM )
I/O standard (1.4 V (Arria V GZ), PCML, 1.5 V PCML, 2.5 V PCML,
LVDS, LVPECL )
• Differential OCT (85, 100, 120 and 150 Ω )
• Signal detect
Channel PLL
• Recovers the clock and serial data stream if you configure the channel
PLL as a CDR.
• Requires offset cancellation to correct the analog offset voltages.
• If you do not use the channel PLL as a CDR, you can configure the
channel PLL as a CMU PLL for clocking the transceivers. For more
information about the channel PLL configured as a CMU PLL, refer to
CMU PLL on page 1-24.
Deserializer
• Converts the incoming high-speed serial data from the receiver buffer
to low-speed parallel data for the receiver PCS.
• Receives serial data in LSB-to-MSB order.
• Supports the optional clock-slip feature for applications with stringent
latency uncertainty requirement.
• Supports 8, 10, 16, and 20-bit deserialization factors in Arria V GX, SX,
GT, ST, and GZ devices.
• Additionally supports the 64 and 80-bit serialization factor for 10-Gbps
transceiver channels Arria V ST and GT devices.
• Additionally supports the 32, 40, 64, and 80-bit serialization factor in
Arria V GZ devices.
Receiver Buffer
The receiver input buffer receives serial data from the rx_serial_data port and feeds the serial data to the
channel PLL configured as a CDR PLL.
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Receiver Buffer
Figure 1-14: Receiver Buffer
To CDR/EyeQ (1)
DFE (1)
To Signal Detect
CTLE
and DC Gain
Circuitry
Differential OCT
(85, 100, 120, or 150 Ω)
Channel PLL configured as a CDR.
+ Rx –
VCM
High-speed
Differential
Receiver
Channel
Input Pins
Signal
Detect
Circuitry
Note:
1. Available only in Arria V GZ devices. Arria V GX,SX,GT and ST devices do not have the
decision feedback equalizer (DFE) feature.
Modifying programmable values within receiver input buffers can be performed by a single reconfiguration
controller for the entire FPGA, or multiple reconfiguration controllers if desired. Within each transceiver
bank a maximum of two reconfiguration controllers is allowed; one for the three-transceiver triplet in the
upper-half of the bank, and one for the lower-half. This is due to a single slave interface to all PLLs and
PMAs within each triplet. Therefore, many triplets can be connected to a single reconfiguration controller,
but only one reconfiguration controller can be connected to the three transceivers within any triplet.
Note: A maximum of one reconfiguration controller is allowed per transceiver bank upper-half or lowerhalf triplet.
Receiver Analog Settings
Arria V GZ channels have two receiver analog modes: half-bandwidth and full-bandwidth. The half-bandwidth
data rate is up to 6.25 Gbps; the full-bandwidth data rate is from 6.25 Gbps to 12.5 Gbps. You can select
which mode to use in the Assignment Editor of the Quartus II software (Receiver Equalizer Gain Bandwidth
Select).
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1-17
Table 1-12: Arria V Receiver Buffer Features
Category
Features
Programmable
CTLE (Continuous
Time Linear
Equalization)
Description
Boosts the high-frequency components of the received signal,
which may be attenuated when propagating through the
transmission medium. The physical transmission medium can be
represented as a low-pass filter in the frequency domain. Variation
in the signal frequency response that is caused by attenuation
leads to data-dependent jitter and other ISI effects, causing
incorrect sampling on the input data at the receiver. The amount
of the high-frequency boost required at the receiver to overcome
signal attenuation depends on the loss characteristics of the
physical medium.
Programmable DC Provides equal boost to the received signal across the frequency
Gain
spectrum.
Improve Signal
Integrity
Decision Feedback The decision feedback equalization feature consists of a 5-tap
Equalization (DFE) equalizer, which boosts the high frequency components of a signal
without noise amplification by compensating for inter-symbol
interference (ISI). There are two decision feedback equalization
modes: manual and auto-adaptation.
The DFE is supported only in Arria V GZ devices.
EyeQ
The EyeQ feature is a debug and diagnosis tool that helps you
analyze the received data by measuring the horizontal and vertical
eye opening.
The EyeQ is supported only in Arria V GZ devices, and not
supported in Arria V GX, SX, ST and GT devices.
There are two multiplexers for the data and clock which select
one path to feed to the deserializer.
Save Board Space
and Cost
Reduce Power
On-Chip Biasing
Establishes the required receiver common-mode voltage (RX VCM)
level at the receiver input. The circuitry is available only if you
enable OCT. When you disable OCT, you must implement offchip biasing circuitry to establish the required RX VCM level.
Differential OCT
The termination resistance is adjusted by the calibration circuitry,
which compensates for the PVT. You can disable OCT and use
external termination. However, you must implement off-chip
biasing circuitry to establish the required RX VCM level. RX VCM
is tri-stated when using external termination.
Programmable
VCM Current
Strength
Controls the impedance of VCM. A higher impedance setting
reduces current consumption from the on-chip biasing circuitry.
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Note: There is no programmable option for Arria V GX, SX,
GT and ST devices because only one VCM value is
offered for AC coupled link in non-PCIe mode.
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Receiver Buffer
Category
Protocol-Specific
Function
Features
Signal Detect
Description
Senses if the signal level present at the receiver input is above or
below the threshold voltage that you specified. The detection
circuitry has a hysteresis response that asserts the status signal
only when a number of data pulses exceeding the threshold voltage
are detected and deasserts the status signal when the signal level
below the threshold voltage is detected for a number of recovered
parallel clock cycles. The circuitry requires the input data stream
to be 8B/10B-coded.
Signal detect is compliant to the threshold voltage and detection
time requirements for electrical idle detection conditions as
specified in the PCI Express Base Specification 2.0 for Gen1 and
Gen2 signaling rates and PCI Express Base Specification 3.0 for
Gen3 signaling rates (Arria V GZ only).
Figure 1-15: Receiver and EyeQ Architecture
Receiver
Input
CTLE/DFE
CDR
Data
Clock
Recovered Data
Deserializer
Control
Eye Q
Data
Recovered Clock
Clock
The receiver can be AC- or DC-coupled to a transmitter. In an AC-coupled link, the AC-coupling capacitor
blocks the transmitter VCM. At the receiver end, the termination and biasing circuitry restores the VCM level
that is required by the receiver.
Figure 1-16: AC-Coupled Link with Arria V Receiver
+ TX –
–
VCM
RX
VCM
Differential Termination
Physical Medium
+
Transmitter
Differential Termination
AC-Coupling
Capacitor
Receiver
Physical Medium
AC-Coupling
Capacitor
(1)
Note:
1. When you disable OCT, you must implement external termination and off-chip biasing circuitry to
establish the required RX VCM level.
When used in a DC-coupled link, the transmitter Vcm is fixed to 0.7V. The receiver Vcm is required to be at
0.7V. DC coupling is supported for serial data rates up to 3.2 Gbps.
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Continuous Time Linear Equalization (CTLE)
1-19
You can DC-couple the Arria V GZ channel transmitter only to another Arria V GZ channel receiver for
the entire datarate range from 600 Mbps to 12.5 Gbps so long as the same VCM value is observed.
+ TX –
VCM
RX
VCM
Differential Termination
Physical Medium
+
–
Transmitter
Differential Termination
Figure 1-17: DC-Coupled Link with Arria V Receiver
Receiver
Physical Medium
Related Information
• For more information about the EyeQ feature, refer to the Altera Transceiver PHY IP Core User
Guide.
• For more information about the Receiver Buffer and electrical specifications, see the Arria V Device
Datasheet.
Continuous Time Linear Equalization (CTLE)
Each receiver buffer has five independently programmable equalization circuits that boost the high-frequency
gain of the incoming signal, thereby compensating for the low-pass characteristics of the physical medium.
The CTLE operates in two modes: manual mode and adaptive equalization (AEQ) mode
Manual Mode
Manual mode allows you to manually adjust the continuous time linear equalization to improve signal
integrity. You can statically set the equalizer settings in the IP or you can dynamically change the equalizer
settings with the reconfiguration controller IP.
Adaptive Equalization Mode
AEQ mode eliminates the need for manual tuning by enabling the Arria V device to automatically tune the
receiver equalization settings based on the frequency content of the incoming signal and comparing that
with internally generated reference signals. The AEQ block resides within the PMA of the receiver channel
and is available on all GX channels.
Note: AEQ is supported by Arria V GZ devices, but not Arria V GX, GT, SX, and ST devices.
There are three AEQ modes: continuous, one-time, and powerdown:
• Continuous mode—The AEQ continuously monitors the frequency content of the received signal and
adapts to the received signal by providing dynamically changing equalizer settings to the receiver.
• One-time mode—The AEQ finds a stable setting of the receiver equalizer and locks to that value. After
the stable setting is locked, the equalizer values do not.
• Powerdown mode—The AEQ of the specific channel is placed in standby mode and the CTLE uses the
manually set value. Note that the CTLE cannot be bypassed.
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Channel PLL
You can dynamically switch between these modes.
Related Information
For more information about enabling different options and using them to control the AEQ hardware,
see the Altera Transceiver PHY IP Core User Guide.
Channel PLL
If you configure the channel PLL as a CDR PLL, the channel PLL recovers the clock and data from the serial
data stream. If you do not use the channel PLL as a CDR PLL, you can configure it as a clock multiplier unit
(CMU) PLL for clocking the transceivers.
Related Information
CMU PLL on page 1-24
Refer to this section for more information about the channel PLL operation when configured as a CMU
PLL.
Channel PLL Architecture
The channel PLL supports operation in either lock-to-reference (LTR) or lock-to-data (LTD) mode.
Figure 1-18: Channel PLL Block Diagram
Channel PLL
rx_is_lockedtodata
From Signal
Detect Circuit (1)
LTR/LTD
Controller
Manual Lock
Controls
Phase
Detector
(PD)
rx_serial_data
refclk
/N
Phase
Frequency
Detector
(PFD)
Down
LTD Mode
Up
Charge Pump
&
Loop Filter
Up
Voltage
Controlled
Oscilator
(VCO)
/L(PD)
Recovered Clock
to Deserializer (2)
/L(PFD)
Serial Clock (3)
Down
LTR Mode
Lock
Detect
rx_is_lockedtoref
/M
Notes:
1. Applicable in a PCIe configuration only.
2. Applicable when configured as a CDR PLL.
3. Applicable when configured as a CMU PLL.
4. The PCIe rateswitch control allows dynamic switching between Gen3, Gen2, and Gen1 line rates in a PCIe Gen2 and Gen3 design.
In addition, the Arria V GZ PCIe rateswitch control allows dynamic switching between Gen3, Gen2, and Gen1 line rates in a PCIe
Gen3 design.
In LTR mode, the channel PLL tracks the input reference clock. The phase-frequency detector (PFD) compares
the phase and frequency of the voltage controlled oscillator (VCO) output and the input reference clock.
The resulting PFD output controls the VCO output frequency to half the data rate with the appropriate
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Channel PLL Counters
1-21
counter (M or L) value given an input reference clock frequency. The lock detect determines whether the
PLL has achieved lock to the phase and frequency of the input reference clock.
During normal operation, the CDR must be in LTD mode to recover the clock from the incoming serial
data. In LTD mode, the phase detector (PD) in the CDR tracks the incoming serial data at the receiver input.
Depending on the phase difference between the incoming data and the CDR output clock, the PD controls
the CDR charge pump that tunes the voltage controlled oscillator (VCO).
Note: The phase frequency detector (PFD) is inactive in LTD mode. rx_is_lockedtoref toggles randomly
and is not significant in LTD mode.
Use the LTR/LTD controller only when you configure the channel PLL as a CDR PLL.
Channel PLL Counters
Table 1-13: Channel PLL Counters
The Quartus ® II software automatically selects the appropriate counter values for each transceiver configuration.
Counter
Description
Values
N
Pre-scale counter to divide the input reference clock
frequency to the PFD by the N factor
1, 2, 4, 8
M
Feedback loop counter to multiply the VCO frequency above 1, 4, 5, 8, 10, 12, 16, 20, 25
the input reference frequency to the PFD by the M factor
L (PFD)
VCO post-scale counter to divide the VCO output frequency 1, 2, 4, 8
by the L factor in the LTR loop
L (PD)
VCO post-scale counter to divide the VCO output frequency 1, 2, 4, 8
by the L factor in the LTD loop
CDR PLL Operation
Description of Arria V CDR PLL operation modes.
The CDR PLL independently recovers the clock and data from the incoming serial data and sends the clock
and data to the deserializer. The CDR PLL supports the full range of data rates.
The CDR PLL requires offset cancellation to correct the analog offset voltages that may exist from process
variations between the positive and negative differential signals in the CDR circuitry.
The CDR PLL operates either in LTR mode or LTD mode. After power-up or reset of the receiver PMA, the
CDR PLL must first operate in LTR mode to keep the VCO output frequency close to the optimum recovered
clock rate.
In LTR mode, the phase detector is not active. When the CDR PLL locks to the input reference clock, you
can switch the CDR PLL to LTD mode to recover the clock and data from the incoming serial data.
In LTD mode, the PFD output is not valid and may cause the lock detect status indicator to toggle randomly.
When there is no transition on the incoming serial data for an extended duration, you must switch the CDR
PLL to LTR mode to wait for the real serial data.
The time needed for the CDR PLL to lock to data depends on the transition density and jitter of the incoming
serial data and the parts per million (ppm) difference between the receiver input reference clock and the
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upstream transmitter reference clock. The receiver PCS must be held in reset until the CDR PLL locks to
data and produces a stable recovered clock.
The LTR/LTD controller directs the CDR PLL transition between the LTR and LTD modes. The controller
supports operation in both automatic lock mode and manual lock mode.
Related Information
For a detailed description of the offset cancellation process, see Dynamic Reconfiguration in Arria V
Devices.
CDR PLL in Automatic Lock Mode
In automatic lock mode, the LTR/LTD controller directs the transition between the LTR and LTD modes
when a set of conditions are met to ensure proper CDR PLL operation. The mode transitions are indicated
by the rx_is_lockedtodata signal. In Arria V GZ devices, the mode transitions are indicated by the
pma_rx_is_lockedtodata signal.
After power-up or reset of the receiver PMA, the CDR PLL is directed into LTR mode. The controller
transitions the CDR PLL from LTR to LTD mode when all the following conditions are met:
• The frequency of the CDR PLL output clock and input reference clock is within the configured ppm
frequency threshold setting.
• The phase of the CDR PLL output clock and input reference clock is within approximately 0.08 unit
interval (UI) of difference.
• In PCIe configurations only—the signal detect circuitry must also detect the presence of the signal level
at the receiver input above the threshold voltage specified in the PCI Express Base Specification 2.0 and
PCI Express Base Specification 3.0 (Arria V GZ only).
The controller transitions the CDR PLL from LTD to LTR mode when either of the following conditions is
met:
• The difference in between frequency of the CDR PLL output clock and input reference clock exceeds the
configured ppm frequency threshold setting.
• In PCIe configurations only—the signal detect circuitry detects the signal level at the receiver input below
the threshold voltage specified in the PCI Express Base Specification 2.0 and PCI Express Base Specification
3.0 (Arria V GZ only).
• In Arria V GZ, after switching to LTD mode, the rx_is_lockedtodata status signal is asserted. Lock to
data takes a minimum of 4 µs, however the actual lock time depends on the transition density of the
incoming data and the parts per million (ppm) difference between the receiver input reference clock and
the upstream transmitter reference clock. The receiver PCS logic must be held in reset until the CDR
produces a stable recovered clock.
If there is no transition on the incoming serial data for an extended duration, the CDR output clock may
drift to a frequency exceeding the configured ppm threshold when compared with the input reference clock.
In such a case, the LTR/LTD controller transitions the CDR PLL from LTD to LTR mode.
CDR PLL in Manual Lock Mode
In manual lock mode, the LTR/LTD controller directs the transition between the LTR and LTD modes based
on user-controlled settings in the pma_rx_set_locktodata and pma_rx_set_locktoref registers. Manual
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Deserializer
1-23
lock mode provides the flexibility to manually control the CDR PLL mode transitions bypassing the ppm
detection as required by certain applications that include, but not limited to, the following:
• Link with frequency differences between the upstream transmitter and the local receiver clocks exceeding
the CDR PLL ppm threshold detection capability. For example, a system with asynchronous spreadspectrum clocking (SSC) downspread of –0.5% where the SSC modulation results in a ppm difference of
up to 5000.
• Link that requires a faster CDR PLL transition to LTD mode, avoiding the duration incurred by the ppm
detection in automatic lock mode.
In manual lock mode, your design must include a mechanism—similar to a ppm detector—that ensures the
CDR PLL output clock is kept close to the optimum recovered clock rate before recovering the clock and
data. Otherwise, the CDR PLL might not achieve locking to data. If the CDR PLL output clock frequency is
detected as not close to the optimum recovered clock rate in LTD mode, direct the CDR PLL to LTR mode.
Related Information
For information about the proper sequence after power-up reset, see Transceiver Reset Control and
Power-Down in Arria V Devices.
Deserializer
The deserializer provides serial-to-parallel data conversion and assumes the data is received LSB first from
the receiver buffer. Additionally, the deserializer provides the clock-slip feature.
Clock-Slip
Word alignment in the PCS may contribute up to one parallel clock cycle of latency uncertainty. The clockslip feature allows word alignment operation with a reduced latency uncertainty by performing the word
alignment function in the deserializer. Use the clock slip feature for applications that require deterministic
latency.
The deterministic latency state machine in the word aligner from the PCS automatically controls the clockslip operation. After completing the clock-slip process, the deserialized data is word-aligned into the receiver
PCS.
Transmitter PLL
In Arria V GX/GT/SX/ST devices, there are two transmitter PLL sources: CMU PLL and fPLL. In Arria V
GZ devices, there are three transmitter PLL sources: ATX PLL, CMU PLL, and fPLL.
Table 1-14: Transmitter PLL Capability and Availability
Transmitter PLL
(4)
Serial Data Range
Availability
ATX PLL (4)
0.600 Gbps to 12.5 Gbps
Two transceivers per bank.
CMU PLL
0.611 Gbps to 10.3125
Gbps
Every channel when not used as receiver CDR (only two
per transceiver bank capable to drive other channels)
fPLL
0.611 Gbps to 3.125 Gbps Two per transceiver bank
ATX PLL only available in Arria V GZ devices.
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Auxiliary Transmit (ATX) PLL Architecture
Auxiliary Transmit (ATX) PLL Architecture
Arria V GZ devices contain two ATX PLLs per transceiver bank that can generate the high-speed clocks for
the transmitter channels.
Compared with CMU PLLs, ATX PLLs have lower jitter and do not consume a transceiver channel; however
an ATX PLL’s frequency range is more limited.
The serial clock from the ATX PLL is routed to the transmitter clock dividers and can be further divided
down to half the data rate of the individual channels. For best performance you should use the reference
clock input that resides in the same transceiver block as your channel. However, you can use any dedicated
reference clocks along the same side of the device to clock the ATX PLL.
Note: Altera recommends that all Arria V GZ devices use the ATX PLL for channels operating between 8
to 12.5 Gbps data rates and to use the dedicated reference clock input residing in the same transceiver
bank for the selected ATX PLL for best performance
Figure 1-19: ATX PLL Architecture
ATX PLL
Reference
Clock
/N = 1, 2, 4
Lock
Detect
/2
Phase Up
Frequency Down Charge Pump &
Loop Filter
Detector
(PFD)
VCO
8 - 12.5 Ghz
pll_is_locked
/L = 2,
4, 8
Serial
Clock
/M = 4, 5, 8, 10,
12, 16, 20, 25,
32, 40, 80
Related Information
For ATX PLL specifications such as input clock frequency or supported output data ranges, refer to the
Arria V Device Datasheet.
CMU PLL
In Arria V devices, if you do not use the channel PLL as a CDR, you can independently configure every
channel PLL as a CMU PLL for clocking the transceivers.
Note: CDR functionality for the receiver is not available when you configure the channel PLL as a CMU
PLL—you can use the transceiver channel only as a transmitter.
The CMU PLL operates only in lock-to-reference (LTR) mode and supports the full range of data rates.
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Figure 1-20: CMU PLL in Arria V Devices
Channel PLL
rx_is_lockedtodata
From Signal
Detect Circuit
LTR/LTD
Controller
Manual Lock
Controls
Phase
Detector
(PD)
rx_serial_data
refclk
/N
Phase
Frequency
Detector
(PFD)
Down
Up
Up
Charge Pump
+
Loop Filter
Voltage
Controlled
Oscilator
(VCO)
/L(PD)
Recovered Clock
to Deserializer
/L(PFD)
Serial Clock
Down
Lock
Detect
pll_locked
/M
Using the input reference clock, the CMU PLL synthesizes the serial clock with a frequency that is half of
the data rate. The CMU PLL output serial clock feeds the clock divider that resides in the transmitter of the
same transceiver channel. Depending on the channel location in a transceiver bank, the CMU PLL of channels
1 and 4 feeds the output clock to the x1 clock lines.
Note: Transmitter PLLs within the upper-half or lower-half of a transceiver bank must be connected to the
same Reconfiguration Controller.
Related Information
• Receiver PMA Datapath on page 1-14
• For more information about the input reference clock and transmit PLL, see Transceiver Clocking in
Arria V Devices.
fPLL as Transmitter PLL
In addition to CMU PLL, the fPLL located adjacent to the transceiver banks are available for clocking the
transmitters for serial data rates up to 3.125 Gbps.
Related Information
Clock Networks and PLLs in Arria V Devices
Clock Divider
Each Arria V transmitter channel has a clock divider.
There are two types of clock dividers, depending on the channel location in a transceiver bank:
• Local clock divider—channels 0, 2, 3, and 5 provide serial and parallel clocks to the PMA
• Central clock divider—channels 1 and 4 can drive the x6 and xN clock lines
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Calibration Block
Figure 1-21: Clock Divider for a Transceiver Channel in Arria V Devices
x6 Clock Lines (1)
xN Clock Lines (1)
x1 Clock Lines (1)
Fractional PLL
CMU PLL (2)
To Serializer
/N
(1, 2, 4, 8)
PCIe Rateswitch
Circuit
/S
(4, 5, 8, 10, 32, 40)
Serial Clock
Serial and Parallel
Clocks
(5)
PCIe Rateswitch
Control (4)
To x6 Clock Lines (3)
Notes:
1. For information about the x1, x6, and xN clock lines, see the Related Information.
2. Only from the channel PLL in the same transceiver channel configured as a CMU PLL.
3. Applicable for central clock dividers only (clock dividers in channels 1 and 4).
4. The PCIe rateswitch circuit allows dynamic switching between Gen2 and Gen1 line rates in a PCIe Gen2 design.
5. The divider settings are configured automatically depending on the serialization factor. The selected divider setting is half
of the serialization factor. The 32 and 40 divider settings are only available for 10-Gbps channels.
Both types of clock dividers can divide the serial clock input to provide the parallel and serial clocks for the
serializer in the channel if you use clocks from the clock lines or transmit PLLs. The central clock divider
can additionally drive the x6 clock lines used to bond multiple channels.
In bonded channel configurations, both types of clock dividers can feed the serializer with the parallel and
serial clocks directly, without dividing them from the x6 or xN clock lines.
Related Information
Transceiver Clocking in Arria V Devices
Calibration Block
The calibration block calibrates the differential OCT resistance and analog circuitry in the transceiver PMA
to ensure the functionality is independent of PVT. It is also used for duty cycle calibration of the clock line
at serial data rates above 4.9152 Gbps.
Up to two calibration blocks are available for the Arria V transceiver PMA.
Figure 1-22: Calibration Block Location and Connections in Arria V Devices with Transceivers on the Left
Side of the Device Only
2 kΩ (1)
RREF
Left Calibration
Block
GXB_L1
GXB_L0
Note:
1. In Arria V GZ devices, you must use a 1.8 kΩ (maximum tolerance ± 1%)
external resistor.
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Figure 1-23: Calibration Block Location and Connections in Arria V Devices with Transceivers on Both Sides
of the Device
2 kΩ (2)
RREF
Left Calibration
Block
GXB_L2 (1)
GXB_R2 (1)
GXB_L1
GXB_R1
GXB_L0
GXB_R0
Right Calibration
Block
2 kΩ (2)
RREF
Notes:
1. GXB_L2 and GXB_R2 banks are only available in some device variants.
2. In Arria V GZ devices, you must use a 1.8 kΩ (maximum tolerance ± 1%)
external resistor.
The calibration block generates a constant internal reference voltage that is independent of PVT variations
using the external reference resistor. The resulting reference currents are used to calibrate the transceiver
banks.
Note: You must connect a separate 2 kΩ (tolerance maximum of ±1%) external resistor on each RREF pin
to ground, except for Arria GZ devices. In Arria V GZ devices, you must use a 1.8 kΩ (maximum
tolerance +/- 1%) external resistor. To ensure the calibration block operates properly, the RREF resistor
connection in the board must be free from external noise.
Offset Cancellation in the Receiver Buffer and Receiver CDR
Process variation in smaller process silicon can lead to a VCM offset between the p and n signals within the
differential buffers. Arria V GZ devices have an automatic calibration in their receiver buffers to remove
this VCM offset.
You must use the reconfiguration controller IP for offset cancellation to take place. Calibration does not
occur during transceiver reset, only during device configuration. Any signals that may appear on the receiver
pin do not affect calibration because the receiver buffers are disconnected during calibration.
Note: A maximum of one reconfiguration controller is allowed per transceiver bank upper-half or lowerhalf triplet.
ATX PLL Calibration for Arria V GZ Devices
ATX PLL calibration optimizes the ATX PLL VCO settings for the desired output frequency. The reconfiguration controller IP must be instantiated for this calibration to run. The calibration occurs one time after
device initialization.
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PCS Architecture
PCS Architecture
The PCS architecture of Arria V GX/GT/SX/ST devices are slightly different from the GZ devices.
The GZ has three types of PCS blocks: standard PCS block, a 10G PCS block and a PCIe Gen3 PCS block.
The GX, SX, GT and ST devices have only one type of PCS block, which is similar to the GZ standard PCS
block, except for the data rate support. The GX and GT PCS supports up to 6.5536 Gbps while the GZ
supports up to 9.8 Gbps. The 10G PCS of the GZ supports 12.5 Gbps, and the PCIe Gen3 PCS supports the
PCIe Gen 3 Base specification.
Figure 1-24: Transceiver Channel PCS in Arria V Devices
FPGA Fabric
TX Phase
Compensation
FIFO
Byte Serializer
TX Bit Slip
8B/10B Encoder
Transmitter PCS
Serializer
tx_serial_data
Transmitter PMA
tx_parallel data
tx_coreclkin
Serial
Clock (1)
/2
RX Phase
Compensation
FIFO
Byte Ordering
Byte Deserializer
8B/10B Decoder
Rate Match FIFO
Deserializer
CDR
Word Aligner
Receiver PCS
Receiver PMA
rx_serial_data
tx_clkout
rx_parallel data
rx_coreclkin
/2
rx_clkout
Serial Clock
Parallel Clock
Parallel Clock (1)
Note:
1. The serial and parallel clocks are sourced from the clock divider.
Note: For Arria V GT and ST devices, the PCS is not available when using the 10-Gbps channels; only the
PMA is available. You must implement the PCS functions required for the interface using user logic
in the FPGA fabric with an 80-bit FPGA fabric-transceiver width.
Arria V GZ transceiver PCS blocks fully support data rates up to 12.5 Gbps You have the option to bypass
the PCS using the PMA direct mode.
Table 1-15: PCS Datapath Configurations
Parameter
PMA–PCS Interface Width
Altera Corporation
Single-Width
8 or 10 bit
Double-Width
16 or 20 bit
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Transmitter PCS Datapath for Arria V GX, SX, GT, and ST Devices and Arria V GZ Standard PCS
Parameter
Single-Width
1-29
Double-Width
FPGA Fabric–Transceiver Interface
Width
8 or 10 bit
16 or 20 bit
16 or 20 bit (5)
32 or 40 bit (5)
Supported configurations
PCIe Gen1, Gen2, and Gen3 Custom
XAUI
Custom
Data rate range in a custom configura- 0.6 to 3.75 Gbps
tion
1.0 to 11 Gbps
Transmitter PCS Datapath for Arria V GX, SX, GT, and ST Devices and Arria V GZ Standard
PCS
This section describes the transmitter phase compensation FIFO, byte serializer, 8B/10B encoder, and
transmitter bit-slip blocks in the transmitter PCS datapaths.
Table 1-16: Functional Blocks in the Transmitter PCS Datapath
Block
(5)
Functionality
Transmitter Phase Compensation
FIFO
• Compensates for the phase difference between the low-speed
parallel clock and the FPGA fabric interface clock when interfacing
the transmitter PCS with the FPGA fabric directly or with the PCIe
hard IP block
• Supports operation in phase compensation and registered modes
Byte Serializer
• Divides the FPGA fabric–transceiver interface frequency in half
at the transmitter channel by doubling the transmitter input
datapath width
• Allows the transmitter channel to operate at higher data rates with
the FPGA fabric–transceiver interface frequency that is within the
maximum limit
• Supports operation in double-width modes
8B/10B Encoder
• Generates 10-bit code groups from 8-bit data and 1-bit control
identifier, in compliance with Clause 36 of the IEEE 802.3 specification
• Supports operation in single- and double-width modes, and
running disparity control
Transmitter Bit-Slip
• Enables user-controlled, bit-level delay in the data prior to
serialization for serial transmission
• Supports operation in single- and double-width modes
The byte serializer and deserializer are enabled.
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Transmitter Phase Compensation FIFO
Transmitter Phase Compensation FIFO
The transmitter phase compensation FIFO is four words deep and interfaces the control and data signals
between the transmitter PCS and FPGA fabric or PCIe hard IP block.
The FIFO supports the following operations:
• Phase compensation mode with various clocking modes on the read clock and write clock
• Registered mode with only one clock cycle of datapath latency
Phase Compensation Mode
The transmitter phase compensation FIFO compensates any phase difference between the read and write
clocks for the transmitter control and data signals.
The low-speed parallel clock feeds the read clock; the FPGA fabric interface clock feeds the write clock. The
clocks must have 0 ppm difference in frequency or a FIFO underrun or overflow condition may result.
The transmitter phase compensation FIFO supports various clocking modes on the read and write clocks
depending on the transceiver configuration.
Related Information
For a detailed description of transmitter datapath interface clocking modes when using the transmitter
phase compensation FIFO, see Transceiver Clocking in Arria V Devices.
Registered Mode
To eliminate the FIFO latency uncertainty for applications with stringent datapath latency uncertainty
requirements, bypass the FIFO functionality in registered mode to incur only one clock cycle of datapath
latency when interfacing the transmitter channel to the FPGA fabric. Configure the FIFO to registered mode
when interfacing the transmitter channel to the PCIe hard IP block to reduce datapath latency. In registered
mode, the low-speed parallel clock that is used in the transmitter PCS clocks the FIFO.
Byte Serializer
The byte serializer allows the transmitter channel to operate at higher data rates in a configuration that
exceeds the FPGA fabric–transceiver interface frequency limit.
The byte serializer supports operation in single- and double-width modes. The datapath clock rate at the
output of the byte serializer is twice the FPGA fabric–transmitter interface clock frequency. The byte serializer
forwards the least significant word first followed by the most significant word.
Note: You must use the byte serializer in configurations that exceed the maximum frequency limit of the
FPGA fabric–transceiver interface.
Table 1-17: Transmitter Input Datapath Conversion
Mode
Single Width
Altera Corporation
Transmitter Input Datapath
Width
Byte Serializer Output Datapath
Width
Byte Serializer Output Ordering
16
8
Least significant 8 bits of the
16-bit input first
20
10
Least significant 10 bits of the
20-bit input first
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8B/10B Encoder
Mode
Double
Width
1-31
Transmitter Input Datapath
Width
Byte Serializer Output Datapath
Width
Byte Serializer Output Ordering
32
16
Least significant 16 bits of the
32-bit input first
40
20
Least significant 20 bits of the
40-bit input first
8B/10B Encoder
The 8B/10B encoder supports operation in single- and double-width modes with the running disparity
control feature.
8B/10B Encoder in Single-Width Mode
In single-width mode, the 8B/10B encoder generates 10-bit code groups from 8-bit data and 1-bit control
identifier with proper disparity according to the PCS reference diagram in Clause 36 of the IEEE 802.3
specification. The 10-bit code groups are generated as valid data code-groups (/Dx.y/) or special control
code-groups (/Kx.y/), depending on the 1-bit control identifier.
Figure 1-25: 8B/10B Encoder Diagram in Single-Width Mode
datain[7:0]
control identifier
disparity controls
8B/10B Encoder
dataout[9:0]
The IEEE 802.3 specification identifies only 12 sets of 8-bit characters as /Kx.y/. If other sets of 8-bit characters
are set to encode as special control code-groups, the 8B/10B encoder may encode the output 10-bit code as
an invalid code (it does not map to a valid /Dx.y/ or /Kx.y/ code), or unintended valid /Dx.y/ code, depending
on the value entered.
8B/10B Encoder in Double-Width Mode
In double-width mode, two 8B/10B encoders are cascaded to generate two sets of 10-bit code groups from
16-bit data and two 1-bit control identifiers.
When receiving the 16-bit data, the 8-bit LSByte is encoded first, followed by the 8-bit MSByte.
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Running Disparity Control
Figure 1-26: 8B/10B Encoder Diagram in Double-Width Mode
datain[15:8]
MSB control identifier
MSB disparity controls
8B/10B Encoder
(MSB Encoding)
dataout[19:10]
8B/10B Encoder
(LSB Encoding)
dataout[9:0]
datain[7:0]
LSB control identifier
LSB disparity controls
Running Disparity Control
The 8B/10B encoder automatically performs calculations that meet the running disparity rules when generating
the 10-bit code groups.
The running disparity control feature provides user-controlled signals (tx_dispval and tx_forcedisp) to
manually force encoding into a positive or negative current running disparity code group. When enabled,
the control overwrites the current running disparity value in the encoder based on user-controlled signals,
regardless of the internally-computed current running disparity in that cycle.
Note: Using the running disparity control may temporarily cause a running disparity error at the receiver.
Encoder Output During Reset Sequence
Figure 1-27: 8B/10B Encoder Output During and After Reset Conditions
(a) Single-Width Mode
clock
tx_digitalreset
dataout[9:0]
K28.5-
K28.5-
K28.5-
XXX
XXX
XXX
K28.5-
K28.5+
K28.5-
Dx.y+
(b) Double-Width Mode
clock
tx_digitalreset
Altera Corporation
dataout[19:10]
K28.5+
K28.5+
K28.5+
XXX
XXX
XXX
K28.5+
K28.5+
K28.5+
Dx.y+
dataout[9:0]
K28.5-
K28.5-
K28.5-
XXX
XXX
XXX
K28.5-
K28.5-
K28.5-
Dx.y-
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Table 1-18: 8B/10B Encoder Output During and After Reset Conditions
Operation Mode
During 8B/10B Reset
After 8B/10B Reset Release
Single Width
Continuously sends the /K28.5/ Some “don’t cares” due to pipelining in the
transmitter channel, followed by three /K28.5/ codes
code from the RD– column
with proper disparity—starts with negative
disparity—before sending encoded 8-bit data at its
input.
Double Width
Continuously sends the /K28.5/ Some “don't cares” due to pipelining in the transmitter
code from the RD– column on channel, followed by:
LSByte and the /K28.5/ code
• Three /K28.5/ codes from the RD– column before
from the RD+ column on
sending encoded 8-bit data at its input on LSByte.
MSByte
• Three /K28.5/ codes from the RD+ column before
sending encoded 8-bit data at its input on MSByte.
Transmitter Bit-Slip
The transmitter bit-slip enables a bit-level delay insertion to the data prior to serialization for the serial
transmission. The transmitter bit-slip supports operation in single- and double-width modes. Each bit slipped
at the transmitter incurs one serial bit of datapath latency.
Table 1-19: Bits Slip Allowed with the tx_bitslipboundaryselect Signal
Operation Mode
Maximum Bit-Slip Setting
Singe width (8- or 10-bit)
9
Double width (16- or 20-bit)
19
Receiver PCS Datapath for Arria V GX, SX, GT, and ST Devices and Arria V GZ Standard
PCS
Table 1-20: Functional Blocks in the Arria V GX/GT/SX/ST 6-Gbps Receiver PCS and Arria V GZ Standard PCS
Datapaths
Block
Word Aligner
Functionality
• Searches for a predefined alignment pattern in the deserialized data to identify the
correct boundary and restores the word boundary during link synchronization
• Supports an alignment pattern length of 7, 8, 10, 16, 20, or 32 bits
• Supports operation in four modes—manual alignment, bit-slip, automatic synchronization state machine, and deterministic latency state machine—in single- and doublewidth configurations
• Supports the optional programmable run-length violation detection, polarity inversion,
bit reversal, and byte reversal features
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Block
Functionality
Rate Match FIFO • Compensates for small clock frequency differences of up to ±300 ppm—600 ppm
total—between the upstream transmitter and the local receiver clocks by inserting or
deleting skip symbols when necessary
• Supports operation that is compliant to the clock rate compensation function in
supported protocols
8B/10B Decoder • Receives 10-bit data and decodes the data into an 8-bit data and a 1-bit control
identifier—in compliance with Clause 36 of the IEEE 802.3 specification
• Supports operation in single- and double-width modes
Byte Deserializer • Divides the FPGA fabric–transceiver interface frequency in half at the receiver channel
by doubling the receiver output datapath width
• Allows the receiver channel to operate at higher data rates with the FPGA
fabric–transceiver interface frequency that is within the maximum limit
• Supports operation in double-width modes
Byte Ordering
• Searches for a predefined pattern that must be ordered to the LSByte position in the
parallel data going to the FPGA fabric when you enable the byte deserializer
Receiver Phase
Compensation
FIFO
• Compensates for the phase difference between the low-speed parallel clock and the
FPGA fabric interface clock when interfacing the receiver PCS with the FPGA fabric
directly or with the PCIe hard IP block
• Supports operation in phase compensation and registered modes
Word Aligner
The Word Aligner provides word boundary restoration during link synchronization.
Parallel data at the input of the receiver PCS loses the word boundary of the upstream transmitter from the
serial-to-parallel conversion in the deserializer. The word aligner provides word boundary restoration during
link synchronization with the following four modes:
•
•
•
•
Manual alignment mode
Bit-slip mode
Automatic synchronization state machine mode
Deterministic latency state machine mode
The word aligner searches for a predefined alignment pattern in the deserialized data to identify the correct
boundary and restores the word boundary during link synchronization. The alignment pattern is predefined
for standard serial protocols according to the respective protocol specifications to achieve synchronization
or you can specify the settings with a custom word alignment pattern for proprietary protocol implementations. Except for bit-slip mode, after completing word alignment, the deserialized data is synchronized to
have the word alignment pattern at the LSB portion of the aligned data.
In addition to restoring the word boundary, the word aligner also supports optional features.
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Table 1-21: Optional Word Aligner Features
Feature
Availability
Programmable Run-Length Violation Detection
All transceiver configurations
Receiver Polarity Inversion
All transceiver configurations except PCIe
Receiver Bit Reversal
Custom single- and double-width configurations only
Receiver Byte Reversal
Custom double-width configuration only
The operation mode and alignment pattern length support varies depending on the word aligner configurations.
Table 1-22: Word Aligner Operation Mode and Pattern Length Support
PCS Mode
PMA–PCS Interface
Width
8 bits
Single Width
10 bits
Word Aligner Mode
Alignment Pattern Length
Manual alignment
8 bits or 16 bits
Bit-slip
–
Manual alignment
7 or 10 bits
Bit-slip
–
Automatic
7 or 10 bits (6)
synchronization state
machine
Deterministic latency 10 bits (7)
state machine
16 bits
Double Width
20 bits
Manual alignment
8, 16, or 32 bits
Bit-slip
–
Manual alignment
7, 10, 20, or 40 bits
Bit-slip
–
Deterministic latency 10 bits (7)
state machine
When the 8B/10B encoder/decoder is enabled, the word aligner detects both positive and negative disparities
of the alignment pattern. For example, if you specify a /K28.5/ (b’0011111010) pattern as the comma,
rx_patterndetect is asserted if b’0011111010 or b’1100000101 is detected in the incoming data.
(6)
(7)
For PCIe implementation, the word aligner is configured using the automatic synchronization state machine
with alignment pattern length of 10 bits.
For more information about CPRI in deterministic latency state machine, refer to the CPRI Enhancements
section of the Transceiver Protocol Configurations in Arria V Devices chapter.
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Word Aligner in Manual Alignment Mode
Word Aligner in Manual Alignment Mode
In manual alignment mode, the word alignment operation is manually controlled with the
rx_std_wa_patternalign input signal or the rx_enapatternalign register.
Depending on the configuration, controlling the rx_std_wa_patternalign signal enables the word aligner
to look for the predefined word alignment pattern in the received data stream. A value 1 at the
rx_patterndetect register indicates that the word alignment pattern is detected . A value 1 at the
rx_syncstatus register indicates that the word aligner has successfully synchronized to the new word
boundary.
Manual word alignment can be also triggered by writing a value 1 to rx_enapatternalign register. The
word alignment is triggered in the next parallel clock cycle when a 0 to 1 transition occurs on the
rx_enapatternalign register.
Table 1-23: Word Aligner Operations in Manual Alignment Mode
PCS Mode
Single Width
Altera Corporation
PMA–PCS
Interface
Width
8 bits or
10 bits
Word Alignment Operation
1. After the rx_digitalreset signal deasserts, assert rx_std_wa_
patternalign signal for one parallel clock cycle for the word aligner to
look for the predefined word alignment pattern in the received data stream
and synchronize to the new word boundary.
2. Any alignment pattern found thereafter in a different word boundary does
not cause the word aligner to resynchronize to this new word boundary if
the rx_std_wa_patternalign signal is deasserted.
3. To resynchronize to a new word boundary, assert the rx_std_wa_
patternalign signal for another parallel clock cycle.
4. If you keep the rx_std_wa_patternalign signal asserted continuously,
before the signal rx_digitalreset is deasserted, the word aligner updates
the word boundary when the first alignment pattern is found, even though
rx_std_wa_patternalign signal was not asserted for one parallel clock
cycle to trigger the word alignment operation.
5. If you keep the rx_std_wa_patternalign signal deasserted, the word
aligner maintains the current word boundary even when it finds the
alignment pattern in a new word boundary.
6. When the word aligner synchronizes to the new word boundary, the rx_
syncstatus register will have a value 1 for one parallel clock cycle. The
rx_patterndetect register will have a value 1 whenever a word alignment
pattern is found for one parallel clock cycle regardless of whether the word
aligner is triggered to align to the new word boundary or not.
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Word Aligner in Manual Alignment Mode
PCS Mode
Double Width
PMA–PCS
Interface
Width
Word Alignment Operation
16 bits or 1. After the rx_digitalreset signal deasserts, regardless of whether rx_std_
wa_patternalign status signal is asserted or deasserted, the word aligner
20 bits
synchronizes to the first predefined alignment pattern found.
2. Any alignment pattern found thereafter in a different word boundary does
not cause the word aligner to resynchronize to this new word boundary.
3. To resynchronize to the new word boundary, assert the rx_std_wa_
patternalign signal for one parallel clock cycle.
4. When the word aligner synchronizes to the new word boundary, the rx_
syncstatus register will have a value 1 till the rx_digitalreset signal is
deasserted or rx_std_wa_patternalign signal is asserted again. The rx_
patterndetect register will have a value 1 whenever a word alignment
pattern is found for one parallel clock cycle regardless of whether the word
aligner is triggered to align to the new word boundary or not.
The configuration selected for this example is word aligner operation in single width with 10-bit PMA-PCS
interface mode. In this example, a /K28.5/ (10'b0101111100) is specified as the word alignment pattern. The
word aligner aligns to the /K28.5/ alignment pattern in the nth cycle because the rx_std_wa_patternalign
signal is asserted during the nth cycle. The rx_syncstatus register has a value 1 in the next parallel clock
cycle, indicating alignment to a new word boundary. The rx_patterndetect signal also goes high for one
clock cycle indicating word alignment pattern detection. At time n + 1, the rx_std_wa_patternalign signal
is deasserted to instruct the word aligner to lock the current word boundary. The alignment pattern is
detected again in a new word boundary across cycles n + 2 and n + 3. The word aligner does not align to
this new word boundary because the rx_std_wa_patternalign signal is set to 0. The /K28.5/ word alignment
pattern is detected again in the current word boundary during cycle n + 5, causing the rx_patterndetect
to have a value 1 in the next parallel clock cycle.
Figure 1-28: Word Aligner in Manual Alignment Mode
n
n+1
n+2
n+3
n+4
n+5
rx_c lkout
rx_dataout[9:0]
111110000
0101111100
111110000
1111001010
1000000101
111110000
0101111100
rx_patterndetect bit
register read data
0
0
1
0
0
0
0
1
rx_syncstatus bit
register read data
0
0
1
0
0
0
0
0
rx_std_wa_patternalign
Note: If the word alignment pattern is known to be unique and does not appear between word boundaries,
you can continuously assert rx_std_wa_patternalign signal or set the rx_enapatternalign register
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Bit-Slip Mode
to 1 at all times because there is no possibility of false word alignment. If there is a possibility of the
word alignment pattern occurring across word boundaries, you must control the number of clock
cycles that the rx_std_wa_patternalign is asserted or the number of clock cycles the
rx_enapatternalign register is set to 1 to avoid re-alignment to an incorrect word boundary.
Bit-Slip Mode
In bit-slip mode, the word alignment is achieved by manually controlling the data slip with the
rx_std_bitslip signal.
Slipping the received data by one bit effectively shifts the word boundary by one bit. You can implement a
controller in the FPGA fabric to iteratively control the rx_std_bitslip signal until the word aligner output
matches the predefined word alignment pattern to achieve synchronization.
Table 1-24: Word Aligner in Bit-Slip Mode
PCS Mode
Single Width
PMA–PCS Interface Width
(bits)
8
10
16
20
Double Width
Word Alignment Operation
1. At every rising edge to the rx_std_bitslip signal, the word
aligner slips one bit into the received data.
2. When bit-slipping shifts a complete round of the data bus
width, the word boundary is back to the original boundary.
3. Check the received data, rx_parallel_data after every bit slip
operation whether the predefined word alignment pattern
is visible in the new word boundary. When the word
alignment pattern is visible in the new word boundary, the
alignment process is completed and the bit-slip operation
can be stopped.
Note: For every bit slipped in the word aligner, the earliest bit received is lost.
For this example, consider that 8'b11110000 is received back-to-back and 16'b0000111100011110 is the
predefined word alignment pattern. A rising edge on the rx_std_bitslip signal at time n + 1 slips a single
bit 0 at the MSB position, forcing the rx_parallel_data to 8'b01111000. Another rising edge on the
rx_std_bitslip signal at time n + 5 forces rx_parallel_data to 8'b00111100. Another rising edge on the
rx_std_bitslip signal at time n + 9 forces rx_parallel_data to 8'b00011110. Another rising edge on the
rx_std_bitslip signal at time n + 13 forces the rx_parallel_data to 8'b00001111. At this instance,
rx_parallel_data in cycles n + 12 and n + 13 is 8'b00011110 and 8'b00001111, respectively, which matches
the specified 16-bit alignment pattern 16'b0000111100011110.
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Figure 1-29: Word Aligner Configured in Bit Slip Mode
n
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 n + 10 n + 11 n + 12 n + 13 n + 14
rx_std_clkout
rx_parallel_data[7:0]
11110000
01111000
00111100
00011110
00001111
rx_std_bitslip
Note: Bit slip operation can also be triggered by a 0 to 1 transition in the rx_bitslip register.
Word Aligner in Automatic Synchronization State Machine Mode
In automatic synchronization state machine mode, a programmable state machine determines the moment
that the word aligner has either achieved synchronization or lost synchronization.
You can configure the state machine to provide hysteresis control during link synchronization and throughout
normal link operation. Depending on your protocol configurations, the state machine parameters are
automatically configured so they are compliant with the synchronization state machine in the respective
protocol specification.
Table 1-25: State Machine Parameters for the Word Aligner in Automatic Synchronization State Machine Mode
Parameter
Values
Number of valid synchronization code groups or ordered sets received to 1–256
achieve synchronization
Number of erroneous code groups received to lose synchronization
1–64
Number of continuous good code groups received to reduce the error
count by one
1–256
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Word Aligner in Deterministic Latency State Machine Mode
Table 1-26: Word Aligner Operation in Automatic Synchronization State Machine Mode
PCS Mode
Single Width
PMA–PCS Interface
Width
10 bits
Word Alignment Operation
1. After the rx_digitalreset signal deasserts, the word aligner
starts looking for the predefined word alignment pattern, or its
complement, in the received data stream and automatically aligns
to the new word boundary.
2. Synchronization is achieved only after the word aligner receives
the programmed number of valid synchronization code groups
in the same word boundary and is indicated by the value 1 in
rx_syncstatus register. The rx_syncstatus register contains
a value 0 if the word aligner has lost synchronization.
3. Loss of synchronization occurs when the word aligner receives
the programmed number of erroneous code groups without
receiving the intermediate good code groups and is indicated by
the value 0 in the rx_syncstatus register.
4. The word aligner may achieve synchronization again after
receiving a new programmed number of valid synchronization
code groups in the same word boundary.
Word Aligner in Deterministic Latency State Machine Mode
In deterministic latency state machine mode, word alignment is achieved by performing a clock-slip in the
deserializer until the deserialized data coming into the receiver PCS is word-aligned.
The state machine controls the clock-slip process in the deserializer after the word aligner has found the
alignment pattern and identified the word boundary. Deterministic latency state machine mode offers a
reduced latency uncertainty in the word alignment operation for applications that require deterministic
latency.
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Programmable Run-Length Violation Detection
PCS Mode
PMA–PCS
Interface Width
Single Width
10 bits
1-41
Word Alignment Operation
1. After rx_digitalreset deasserts, the word aligner starts looking for
the predefined word alignment pattern, or its complement, in the
received data stream and automatically aligns to the new word
boundary.
2. After the pattern is found and the word boundary is identified, the state
machine controls the clock-slip process in the deserializer.
3. When the clock-slip is complete, the deserialized data coming into the
receiver PCS is word-aligned and is indicated by the value 1 in the
rx_syncstatus register until rx_digitalreset is deasserted.
4. To resynchronize to the new word boundary, the Avalon-MM register
rx_enapatternalign (not available as a signal) must be reasserted to
initiate another pattern alignment. Asserting rx_enapatternalign
may cause the extra shifting in the RX datapath if
rx_enablepatternalign is asserted while bit slipping is in progress.
Consequently, rx_enapatternalign should only be asserted under
the following conditions:
Double Width 20 bits
• rx_syncstatus is asserted
• rx_bitslipboundaryselectout changes from a non-zero value to
zero or 1
5. When the word aligner synchronizes to the new word boundary,
rx_syncstatus has a value of 1 until rx_digitalreset is deasserted
or rx_enapatternalign is set to 1. rx_patterndetect has a value of
1 whenever a word alignment pattern is found for one parallel clock
cycle regardless of whether or not the word aligner is triggered to align
to the new word boundary.
Programmable Run-Length Violation Detection
The programmable run-length violation detection circuit detects if the number of consecutive 1s or 0s in
the received data exceeds the user-specified threshold.
Table 1-27: Detection Capabilities of the Run-Length Violation Circuit
Single Width
Double Width
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Run-Length Violation Detector Range
PMA–PCS Interface
Width (bits)
PCS Mode
Minimum
Maximum
8
4
128
10
5
160
16
8
512
20
10
640
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Receiver Polarity Inversion
Receiver Polarity Inversion
The positive and negative signals of a serial differential link might erroneously be swapped during board
layout. Solutions such as board re-spin or major updates to the PLD logic can be expensive. The polarity
inversion feature at the receiver corrects the swapped signal error without requiring board re-spin or major
updates to the logic in the FPGA fabric. The polarity inversion feature inverts the polarity of every bit at the
input to the word aligner, which has the same effect as swapping the positive and negative signals of the
serial differential link.
Inversion is controlled dynamically with the rx_invpolarity register. When you enable the polarity inversion
feature, initial disparity errors may occur at the receiver with the 8B/10B-coded data. The receiver must be
able to tolerate these disparity errors.
Caution: If you enable polarity inversion midway through a word, the word will be corrupted.
Bit Reversal
You can reverse the bit order at the output of the word aligner for receiving a MSB-to-LSB transmission
using the bit reversal feature at the receiver.
Table 1-28: Bit Reversal Feature
Transmission Bit Order
Bit Reversal Option
8- or 10-bit Serialization
Factor
16- or 20-bit Serialization Factor
Disabled (default)
LSB to MSB
LSB to MSB
Enabled
MSB to LSB
MSB to LSB
For example:
For example:
8-bit—D[7:0] rewired to
16-bit—D[15:0] rewired to D[0:15]
D[0:7]
20-bit—D[19:0] rewired to D[0:19]
10-bit—D[9:0] rewired to
D[0:9]
Note: When receiving the MSB-to-LSB transmission, the word aligner receives the data in reverse order.
The word alignment pattern must be reversed accordingly to match the MSB-first incoming data
ordering.
You can dynamically control the bit reversal feature using the rx_bitreversal_enable register with the
word aligner in bit-slip mode. When you dynamically enable the bit reversal feature in bit-slip mode, you
can ignore the pattern detection function in the word aligner because the word alignment pattern cannot
be dynamically reversed to match the MSB-first incoming data ordering.
Receiver Byte Reversal
The two symbols of incoming data at the receiver in double-width mode may be accidentally swapped during
transmission.
For a 16-bit input data width at the word aligner, the two symbols are bits[15:8] and bits[7:0]. For a
20-bit input data width at the word aligner, the two symbols are bits[19:10] and bits[9:0]. The byte
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reversal feature at the word aligner output can correct this error by swapping the two symbols in doublewidth mode at the word aligner output.
Table 1-29: Byte Reversal Feature
Byte Reversal Option
Word Aligner Output
16-bit Data Width
20-bit Data Width
Disabled
D[15:0]
D[19:0]
Enabled
D[7:0], D[15:8]
D[9:0], D[19:10]
The reversal is controlled dynamically using the rx_bytereversal_enable register. Enabling the byte
reversal option may cause initial disparity errors at the receiver with 8B/10B-coded data. The receiver must
be able to tolerate these disparity errors.
Note: When receiving swapped symbols, the word alignment pattern must be byte-reversed to match the
incoming byte-reversed data.
Rate Match FIFO
The Rate Match FIFO compensates for the small clock frequency differences between the upstream transmitter
and the local receiver clocks.
In a link where the upstream transmitter and local receiver can be clocked with independent reference clock
sources, the data can be corrupted by any frequency differences (in ppm count) when crossing the data from
the recovered clock domain—the same clock domain as the upstream transmitter reference clock—to the
local receiver reference clock domain.
The rate match FIFO is 20 words deep, which compensates for the small clock frequency differences of up
to ±300 ppm (600 ppm total) between the upstream transmitter and the local receiver clocks by performing
symbol insertion or deletion, depending on the ppm difference on the clocks.
The rate match FIFO operation requires that the transceiver channel is in duplex configuration (both transmit
and receive functions) and a predefined 20-bit pattern (consisting of a 10-bit control pattern and a 10-bit
skip pattern). The 10-bit skip pattern must be chosen from a code group with neutral disparity.
The FIFO operates by looking for the 10-bit control pattern, followed by the 10-bit skip pattern in the data
after the word aligner has restored the word boundary. After finding the pattern, the FIFO performs the
following operations to ensure the FIFO does not underflow or overflow:
• Inserts the 10-bit skip pattern when the local receiver reference clock frequency is greater than the
upstream transmitter reference clock frequency
• Deletes the 10-bit skip pattern when the local receiver reference clock frequency is less than the upstream
transmitter reference clock frequency
The rate match FIFO supports operations in single- and double-width modes. You can define the 20-bit
pattern for custom configurations. For protocol configurations, the FIFO is automatically configured to
support a clock rate compensation function as required by the following specifications:
• The PCIe protocol per clock tolerance compensation requirement, as specified in the PCI Express Base
Specification 2.0 for Gen1 and Gen2 signaling rates and PCI Express Base Specification 3.0 for Gen1,
Gen2, and Gen3 signaling rates (Arria V GZ only).
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8B/10B Decoder
• The Gbps Ethernet (GbE) protocol per clock rate compensation requirement using an idle ordered set,
as specified in Clause 36 of the IEEE 802.3 specification
Note: For the Gigabit Ethernet protocol, if you enabled rate match FIFO in the autonegotiation state
machine in an FPGA core, refer to the "Rate Match FIFO" section in the "Gigabit Ethernet" section
in the Transceiver Protocol Configurations in Arria V Devices chapter.
Related Information
• Transceiver Custom Configurations in Arria V Devices
For more information about the rate match FIFO operation in custom-specific configurations.
• Transceiver Protocol Configurations in Arria V Devices
For more information about the rate match FIFO operation in protocol-specific configurations.
8B/10B Decoder
The 8B/10B decoder supports operation in single- and double-width modes.
8B/10B Decoder in Single-Width Mode
In single-width mode, the 8B/10B decoder decodes the received 10-bit code groups into an 8-bit data and a
1-bit control identifier in compliance with Clause 36 in the IEEE 802.3 specification. The 1-bit control
identifier indicates if the decoded 8-bit code is a valid data or special control code.
Figure 1-30: 8B/10B Decoder Block Diagram in Single-Width Mode
datain[9:0]
dataout[7:0]
8B/10B Decoder
control identifier
error status
8B/10B Decoder in Double-Width Mode
In double-width mode, two 8B/10B decoders are cascaded to decode the 20-bit code groups into two sets of
8-bit data and two 1-bit control identifiers. When receiving the 20-bit code group, the 10-bit LSByte is
decoded first and the ending running disparity is forwarded to the other 8B/10B decoder for decoding the
10-bit MSByte.
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Figure 1-31: 8B/10B Decoder Block Diagram in Double-Width Mode
dataout[15:8]
datain[19:10]
8B/10B Decoder
(MSByte Decoding)
control identifier
error status
Current Running Disparity
datain[9:0]
dataout[7:0]
8B/10B Decoder
(LSByte Decoding)
control identifier
error status
Byte Deserializer
The byte deserializer allows the receiver channel to operate at higher data rates in a configuration that exceeds
the FPGA fabric–transceiver interface frequency limit.
The byte deserializer supports operation in single- and double-width modes. The datapath clock rate at the
input of the byte deserializer is twice the FPGA fabric–receiver interface clock frequency.
Note: You must use the byte deserializer in configurations that exceed the maximum frequency limit of
the FPGA fabric–transceiver interface.
After byte deserialization, the word alignment pattern may be ordered in the MSByte or LSByte position.
Table 1-30: Byte Deserializer Input Datapath Width Conversion
Data is assumed to be received as LSByte first—the least significant 8 or 10 bits in single-width mode or the least
significant 16 or 20 bits in double-width mode.
Mode
Single Width
Double Width
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Byte Deserializer Input
Datapath Width
Receiver Output Datapath Width
8
16
10
20
16
32
20
40
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Byte Ordering
Byte Ordering
When you enable the byte deserializer, the output byte order may not match the originally transmitted
ordering. For applications that require a specific pattern to be ordered at the LSByte position of the data,
byte ordering can restore the proper byte order of the byte-deserialized data before forwarding it to the
FPGA fabric.
Byte ordering operates by inserting a predefined pad pattern to the byte-deserialized data if the predefined
byte ordering pattern found is not in the LSByte position.
Byte ordering requires the following:
• A receiver with the byte deserializer enabled
• A predefined byte ordering pattern that must be ordered at the LSByte position of the data
• A predefined pad
Byte ordering supports operation in single- and double-width modes. Both modes support operation in
word aligner-based and manual ordering modes.
Byte Ordering in Single-Width Mode
Byte ordering is supported only when you enable the byte deserializer.
Table 1-31: Byte Ordering Operation in Single-Width Mode
PMA–PCS Interface Width
8 bits
FPGA
Fabric–Transceiver
Interface Width
16 bits
10 bits
8B/10B Decoder
Disabled
Byte Ordering
Pattern Length
8 bits
Pad Pattern Length
8 bits
(8)
16 bits
Enabled
9 bits
9 bits (8)
20 bits
Disabled
10 bits
10 bits
Figure 1-32: Byte Ordering Operation Example in Single-Width Mode
An example of a byte ordering operation in single-width mode (8-bit PMA-PCS interface width) where A
is the predefined byte ordering pattern and P is the predefined pad pattern.
Transmitter
datain[15:8]
D2
D3
D5
datain[7:0]
D1
A
D4
Channel
Byte
Serializer
Receiver
Byte
Deserializer
D1
A
D4
XX
D2
D3
Byte
Ordering
D1
P
D3
D5 dataout[15:8]
XX
D2
A
D4 dataout[7:0]
Byte Ordering in Double-Width Mode
Byte ordering is supported only when you enable the byte deserializer.
(8)
The MSB of the 9-bit pattern represents the 1-bit control identifier of the 8B/10B-decoded data. The lower 8
bits represent the 8-bit decoded code.
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Table 1-32: Byte Ordering Operation in Double-Width Mode
PMA–PCS Interface Width
FPGA
Fabric–Transceiver
Interface Width
16 bits
20 bits
8B/10B Decoder
Byte Ordering
Pattern Length
Pad Pattern Length
32 bits
Disabled
8 or 16 bits
8 bits
32 bits
Enabled
9(9) or 18 bits(10)
9 bits(9)
40 bits
Disabled
10 or 20 bits
10 bits
Figure 1-33: Byte Ordering Operation Example in Double-Width Mode
An example of a byte ordering operation in double-width mode (16-bit PMA-PCS interface width) where
A1A2 is the predefined byte ordering pattern and P is the predefined pad pattern.
Transmitter
datain[31:16]
(MSByte) D2D3 D4D5 D8D9
datain[15:0] D0D1 B1B2 D6D7
(LSByte)
Byte
Serializer
Channel
Receiver
Byte
Deserializer
D0D1 A1A2 D6D7
xxxx D2D3 D4D5
Byte
Ordering
dataout[31:16]
D4D5 D8D9 (MSByte)
dataout[15:0]
xxxx D2D3 A1A2 D6D7
(LSByte)
D0D1
PP
Word Aligner-Based Ordering Mode
In word aligner-based ordering mode, the byte ordering operation is controlled by the word aligner
synchronization status signal, rx_syncstatus.
After a rising edge on the rx_syncstatus signal, byte ordering looks for the byte ordering pattern in the
byte-deserialized data.
When the first data byte that matches the byte ordering pattern is found, the byte ordering performs the
following operations:
• If the pattern is not in the LSByte position—byte ordering inserts the appropriate number of pad patterns
to push the byte ordering pattern to the LSByte position and indicates the byte alignment.
• If the pattern is in the LSByte position—byte ordering indicates the byte alignment.
Any byte misalignment found thereafter is ignored unless another rising edge on the rx_syncstatus signal,
indicating resynchronization, is observed.
Manual Ordering Mode
In manual ordering mode, the byte ordering operation is controlled using the rx_enabyteord signal.
A rising edge on the rx_enabyteord signal triggers byte ordering to look for the byte ordering pattern in
the byte-deserialized data.
(9)
(10)
The MSB of the 9-bit pattern represents the 1-bit control identifier of the 8B/10B-decoded data. The lower 8
bits represent the 8-bit decoded code.
The 18-bit pattern consists of two sets of 9-bit patterns, individually represented as in the previous note.
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Receiver Phase Compensation FIFO
When the first data byte that matches the byte ordering pattern is found, the byte ordering performs the
following operations:
• If the pattern is not in the LSByte position—byte ordering inserts the appropriate number of pad patterns
to push the byte ordering pattern to the LSByte position and indicates the byte alignment.
• If the pattern is in the LSByte position—byte ordering indicates the byte alignment.
Any byte misalignment found thereafter is ignored unless another rising edge on the rx_enabyteord signal
is observed.
Receiver Phase Compensation FIFO
The receiver phase compensation FIFO is four words deep and interfaces the status and data signals between
the receiver PCS and the FPGA fabric or the PCIe hard IP block. The FIFO supports the following operations:
• Phase compensation mode with various clocking modes on the read clock and write clock
• Registered mode with only one clock cycle of datapath latency
Phase Compensation Mode
The receiver phase compensation FIFO compensates for any phase difference between the read and write
clocks for the receiver status and data signals.
The low-speed parallel clock feeds the write clock; the FPGA fabric interface clock feeds the read clock. The
clocks must have 0 ppm difference in frequency or a FIFO underrun or overflow condition may result.
The receiver phase compensation FIFO supports various clocking modes on the read and write clocks
depending on the transceiver configuration.
Related Information
For a detailed description of the receiver datapath interface clocking modes when using the receiver
phase compensation FIFO, seeTransceiver Clocking in Arria V Devices.
Registered Mode
To eliminate the FIFO latency uncertainty for applications with stringent datapath latency uncertainty
requirements, bypass the FIFO functionality in registered mode to incur only one clock cycle of datapath
latency when interfacing the receiver channel to the FPGA fabric. Configure the FIFO to registered mode
when interfacing the receiver channel to the PCIe hard IP block to reduce datapath latency. In registered
mode, the low-speed parallel clock that is used in the receiver PCS clocks the FIFO.
10G PCS Architecture for Arria V GZ Devices
The 10G PCS architecture offers a full duplex (transmitter and receiver) transceiver channel that supports
serial data rates up to 12.5 Gbps for Arria V GZ devices.
Several functional blocks are customized for various protocols. The different datapath configurations for
these protocols are available through the different PHY IPs instantiated through the MegaWizard™ PlugIn Managers. Currently, the only supported configurations for the 10G PCS are Interlaken, 10GBASE-R and
low-latency 10G PCS.
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Figure 1-34: 10G PCS Datapath in Arria V GZ Channels
Not all the blocks shown in the 10G PCS datapath are available in every configuration.
tx_serial_data
TX
Gear Box
Disparity
Generator
Scrambler
64B/66B Encoder
and TX SM
CRC32
Generator
Frame Generator
tx_coreclkin
TX
FIFO
Transmitter PMA
Serializer
Transmitter 10G PCS
FPGA
Fabric
tx_clkout
rx_coreclkin
rx_serial_data
CDR
Receiver PMA
Deserializer
RX
Gear Box
Block
Synchronizer
Disparity Checker
Descrambler
Frame Sync
64B/66B Decoder
and RX SM
RX
FIFO
CRC32
Checker
Receiver 10G PCS
BER
Monitor
rx_clkout
Central/ Local Clock Divider
CMU PLL
Clock Divider
Serial Clock
Parallel and Serial Clocks
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Input Reference Clock
(From Dedicated Input Reference Clock Pin)
Related Information
Altera Transceiver PHY IP Core User Guide
Transmitter 10G PCS Datapath
The sub-blocks in the transmitter 10G PCS datapath are described in order from the transmitter FIFO to
the transmitter gearbox.
Transmitter FIFO
The transmitter FIFO provides an interface between the transmitter channel PCS and the FPGA fabric.
In 10GBASE-R configurations, the transmitter FIFO receives data from the FPGA fabric. The data output
from the transmitter FIFO block goes to the 64B/66B encoder.
In Interlaken configurations, the transmitter FIFO sends a control signal to indicate whether it is ready to
receive data from the FPGA fabric. The user logic sends the data to the transmitter FIFO only if this control
signal is asserted. In this configuration, data output from the transmitter FIFO block goes to the frame
generator.
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Frame Generator
Frame Generator
The frame generator block supports the Interlaken protocol. The frame generator block takes the data from
the transmitter FIFO and encapsulates the payload and burst/idle control words from the FPGA fabric with
the framing layer’s control words, such as the synchronization word, scrambler state word, skip word, and
diagnostic word, to form a metaframe. The Interlaken PHY IP MegaWizard Plug-In Manager interface
allows you to set the metaframe length.
Note: The frame generator is used only in Interlaken configurations.
Figure 1-35: Frame Generator
From TX FIFO
64-Bit Data
1-Bit Control
Frame
Generator
66-Bit Blocks
To CRC-32 Generator
Payload
Scrambler
Synchronization
Skip Word 66 65 64 63
State Word
0 66
0 66
Data
Sync Header
Inversion Bit (Place Holder for Bit Inversion Information)
Used for Clock Compensation in a Repeater
Used to Synchronize the Scrambler
Used to Align the Lanes of the Bundle
0 Di
Provides Per
Lane Error Check
and Optional Status
Message
CRC-32 Generator
The CRC-32 generator block receives data from the frame generator and calculates the cyclic redundancy
check (CRC) code for each block of data. This CRC code value is stored in the CRC32 field of the diagnostic
word.
Note: The CRC-32 generator is used only in Interlaken configurations.
The CRC-32 calculation covers most of the metaframe, including the diagnostic word, except the following:
• bits [66:64] of each word
• 58-bit scrambler state within the scrambler state word
• 32-bit CRC-32 field within the diagnostic word
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64B/66B Encoder
Figure 1-36: CRC-32 Generator
Metaframes with Embedded
CRC-32 Code to Scrambler
CRC-32
Generator
From the Frame Generator
Di
Metaframe
Sy
67
SB
0 67
SK
Payload
Di
0 67
67
Total Data for CRC-32 Calculation
Sy
SB
SK
Sy
SB
SK
Payload
Sy
0
66
31
SB
SK
0
Total Data for CRC-32 Calculation
Calculated CRC-32 Value
Inserted in the 32 Bits
of Diagnostic Word
64B/66B Encoder
The 64B/66B encoder conforms to the 10GBASE-R protocol specification as described in IEEE 802.3-2008
clause-49.
Note: The 64B/66B encoder is used only in 10GBASE-R configurations.
This block contains the 64B/66B encoder sub-block and the transmitter state machine sub-block. The 64B/66B
encoder sub-block receives data from the transmitter FIFO and encodes the 64-bit data and 8-bit control
characters to the 66-bit data block required by the 10GBASE-R configuration. The transmit state machine
in the 64B/66B encoder sub-block checks the validity of the 64-bit data from the MAC layer and ensures
proper block sequencing.
Scrambler
The scrambler operates in frame synchronous mode and self synchronous mode. Frame synchronous mode
operates in Interlaken configurations. Self synchronous mode operates in 10GBASE-R configurations, as
specified in IEEE 802.3-2008 clause-49.
Disparity Generator
The disparity generator block conforms to the Interlaken protocol specification and provides a DC-balanced
data output. The disparity generator receives data from the scrambler and inverts the running disparity to
stay within the ±96-bit boundary. To ensure this running disparity requirement, the disparity generator
inverts bits [63:0] and sets bit [66] to indicate the inversion.
Note: The disparity generator is used only in Interlaken configurations.
Table 1-33: Interpretation of the MSB in the 67-Bit Payload for Arria V Devices
MSB
0
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Bits [63:0] are not inverted; the disparity generator
processes the word without modification
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Transmitter Gearbox
MSB
Interpretation
1
Bits [63:0] are inverted; the disparity generator
inverts the word before processing it
Transmitter Gearbox
The transmitter gearbox adapts the PCS data width to a smaller bus width for interfacing with the PMA.
Because of the transmitter gearbox, the difference in the bus widths between the PCS and the PMA is
transparent to the logic in the FPGA fabric.
Figure 1-37: Transmitter Gearbox
66-Bit in 10GBASE-R
67-Bit in Interlaken
40-Bit Data to Transceiver Channel PMA
TX gearbox
data_valid
TX
Bit
Reversal
In addition to providing bus width adaptation, the transmitter gearbox provides the transmitter polarity
inversion, bit reversal and bit-slip features.
Transmitter Bit Reversal
The transmitter gearbox can reverse the order of transmitted bits. By default, the transmitter first sends out
the LSB of a word. Some protocols, such as Interlaken, require that the MSB of a word (bit 66 in a word
[66:0]) is transmitted first. When you enable the transmitter bit reversal, the parallel input to the gearbox
is swapped and the MSB is sent out first. The Quartus® II software automatically sets the bit reversal for
Interlaken configurations.
Transmitter Polarity Inversion
Transmitter polarity can be used to reverse the positive and negative differential buffer signals. This is useful
if these signals are reversed on the board or backplane layout.
A high value on the tx_invpolarity register, which is accessed via the Avalon-MM PHY management
interface, inverts the polarity of every bit of the input data word to the serializer in the transmitter datapath.
Because inverting the polarity of each bit has the same effect as swapping the positive and negative signals
of the differential link, correct data is sent to the receiver. Dynamically changing the tx_invpolarity register
value might cause initial disparity errors at the receiver of an 8B/10B encoded link. The downstream system
must be able to tolerate these disparity errors.
If polarity inversion is asserted midway through a serializer word, the word will be corrupted.
Transmitter Bit-Slip
The transmitter bit-slip allows you to compensate for the channel-to-channel skew between multiple
transmitter channels by slipping the data sent to the PMA. The maximum number of bits slipped is controlled
from the FPGA fabric and is equal to the width of the PMA-PCS interface, minus one.
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Receiver 10G PCS Datapath
The sub-blocks in the receiver 10G PCS datapath are described in order from the receiver gearbox to the
receiver FIFO.
Receiver Gearbox
The receiver gearbox adapts the PMA data width to a larger bus width to interface with the PCS. The PMA
bus width is smaller than the PCS bus width; therefore, the receiver gearbox expands the data bus width
from the PMA to the PCS. Because bus width adaptation is transparent, you can continuously feed data to
the receiver gearbox. In addition to providing bus width adaptation, the receiver gearbox provides the receiver
bit reversal feature.
Receiver Polarity Inversion
The receiver gearbox can invert the polarity of the incoming data. This is useful if the receive signals are
reversed on the board or backplane layout.
Receiver Bit Reversal
The receiver gearbox allows bit reversal of the received data. Some protocols, such as Interlaken, require the
bit reversal feature.
Related Information
Transmitter Bit Reversal on page 1-52
Block Synchronizer
The block synchronizer determines the block boundary of a 66-bit word in the case of the 10GBASE-R
protocol or a 67-bit word in the case of the Interlaken protocol. The incoming data stream is slipped one
bit at a time until a valid synchronization header (bits 65 and 66) is detected in the received data stream.
After the predefined number of synchronization headers (as required by the protocol specification) is detected,
the block synchronizer asserts the status signal to other receiver PCS blocks down the receiver datapath and
to the FPGA fabric.
The block synchronizer is designed in accordance with both the Interlaken protocol specification and the
10GBASE-R protocol specification as described in IEEE 802.3-2008 clause-49.
Disparity Checker
The design of the disparity checker is based on the Interlaken protocol specifications. After word
synchronization is achieved, the disparity checker monitors the status of the 67th bit of the incoming word
and determines whether or not to invert bits [63:0] of the received word.
Note: The disparity checker is only used in Interlaken configurations.
Table 1-34: Interpretation of the MSB in the 67-Bit Payload for Arria V Devices
MSB
0
Bits [63:0] are not inverted; the disparity checker
processes the word without modification
1
Bits [63:0] are inverted; the disparity checker inverts
the word to achieve the original word before
processing it
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Descrambler
Descrambler
The descrambler descrambles data per the protocol specifications supported by the 10G PCS. The descrambler
operates either in frame synchronous or self synchronous mode.
Frame Synchronous Mode
Frame synchronous mode is used in Interlaken configurations only. When block synchronization is achieved,
the descrambler uses the scrambler seed from the received scrambler state word. This block also forwards
the current descrambler state to the frame synchronizer.
Self Synchronous Mode
Self synchronous mode is used in 10GBASE-R configurations only.
Frame Synchronizer
The frame synchronizer block achieves lock by looking for four synchronization words in consecutive
metaframes. After synchronization, the frame synchronizer monitors the scrambler word in the metaframe
and deasserts the lock signal after three consecutive mismatches and starts the synchronization process
again. Lock status is available to the FPGA fabric.
Note: The frame synchronizer is only used in Interlaken configurations.
Bit-Error Rate (BER) Monitor
The BER monitor block conforms to the 10GBASE-R protocol specification as described in IEEE 802.3-2008
clause-49. After block lock is achieved, the BER monitor starts to count the number of invalid synchronization
headers within a 125-ms period. If more than 16 invalid synchronization headers are observed in a 125-ms
period, the BER monitor provides the status signal to the FPGA fabric, indicating a high bit error rate
condition.
64B/66B Decoder
The 64B/66B decoder block contains a 64B/66B decoder sub-block and a receiver state machine sub-block.
The 64B/66B decoder sub-block converts the received data from the descrambler into 64-bit data and 8-bit
control characters. The receiver state machine sub-block monitors the status signal from the BER monitor.
If the status signal is asserted, the receiver state machine sends local fault ordered sets to the FPGA interface.
Note: The 64B/66B encoder is used only in 10GBASE-R configurations.
The 64B/66B decoder block is designed towards the 10GBASE-R protocol specification as described in IEEE
802.3-2008 clause-49.
CRC-32 Checker
The CRC-32 checker block supports the Interlaken protocol. The CRC-32 checker calculates the CRC from
the incoming data and compares the result to the CRC value sent in the diagnostic word. The CRC error
signal is sent to the FPGA fabric.
Receiver FIFO
The receiver FIFO block operates in different modes based on the transceiver datapath configuration.
The Quartus II software automatically selects receiver FIFO mode for the configuration you use.
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Clock Compensation Mode
The receiver FIFO is configured in clock compensation mode for the 10GBASE-R configuration. In clock
compensation mode, the FIFO deletes idles or ordered sets and inserts only idles to compensate up to a ±100
ppm clock difference between the remote transmitter and the local receiver.
Generic Mode
The receiver FIFO is configured in generic mode for the Interlaken configuration. In generic mode, the
receiver FIFO provides the FIFO partially empty and FIFO full status signals to the FPGA fabric to control
the read side of the FIFO.
Phase Compensation Mode
The receiver FIFO is configured in phase compensation mode for the 10G custom configuration. In phase
compensation mode, the FIFO compensates for the phase difference between the FIFO write clock and the
read clock.
XAUI Mode
In XAUI mode, the receiver FIFO compensates for up to ±100 ppm (200 ppm total) difference between the
upstream transmitter and the local receiver reference clock. The XAUI protocol requires the transmitter to
send /R/ (/K28.0/) code groups simultaneously on all four lanes (denoted as ||R|| column) during inter-packet
gaps (IPGs), conforming to the IEEE P802.3ae specification. The receiver FIFO operation in XAUI mode is
compliant with the IEEE P802.3ae specification.
PCIe Mode
In PCIe mode, the receiver FIFO compensates for up to ±300 ppm (total 600 ppm) difference between the
upstream transmitter and the local receiver. The PCIe protocol requires the transmitter to send SKP ordered
sets during IPGs, conforming to the PCIe base specification 2.0. The SKP ordered set is defined as a /K28.5/
COM symbol followed by three consecutive /K28.0/ SKP symbol groups.
The PCIe protocol requires the receiver to recognize a SKP ordered set as a /K28.5/ COM symbol followed
by one to five consecutive /K28.0/ SKP symbols. The rate match FIFO operation is compliant with PCIe
Base Specification 2.0.
PCIe Gen 3 PCS Architecture
Arria V supports the PCIe Gen3 Base specification. The PCIe Gen3 uses a 128/130 bit block encoding/decoding
scheme which is different from the 8B/10B scheme used in Gen 1 and Gen 2. The 130-bit block contains a
2-bit sync header and 128-bit data payload. For this reason, the PCIe Gen3 PCS has a separate data path as
compared to the PCIe Gen1 or Gen2 PCS. The PCIe Gen3 PCS supports the PHY Interface for the PCI
Express (PIPE) interface with the hard IP (HIP) enabled and with the HIP bypassed.
This PIPE interface supports the seamless switching of Data and Clock between the Gen1, Gen2, and Gen3
PCS, and provides support for PIPE 3.0 features.
The overall simplified PCIe Gen3 PCS the following architecture diagram. Note that the RX/TX Phase Comp
FIFOs are physically placed in, and shared with the standard 8GB PCS.
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Transmitter PCIe Gen 3 PCS Datapath
Figure 1-38: PCIe Gen3 PCS Top Level Block Diagram
TX PCIe Gen 3 PCS
8GB PCS
Phase
Comp
FIFO
Encoder
Scrambler
TX Bit
Slip
Gearbox
PLD_TX_CLK
32
TX_CLK
TX
PMA
PCS_DLG_CLK
TXPMA_CLK
/4
Auto-Speed Negotiation
Gen3 x1, x2, x4, x8
Gen3 PIPE Control &
Status Interface
CDR
Control
RX PCIe Gen 3 PCS
32
Phase
Comp
FIFO
DeScrambler
Rate
Match
FIFO
Decoder
TX_CLK
Block
Sync
32
RCVD_CLK_MX
RX
PMA
PLD_RX_CLK
RCVD_CLK
Transmitter PCIe Gen 3 PCS Datapath
This section describes the transmitter channel PCIe Gen 3 PCS datapath architecture.
Phase Compensation FIFO (Shared with Standard PCS)
Scrambler
The Scrambler is an additive scrambler on a per-lane basis with degree 23 polynomial linear feedback shift
register (LFSR), with different taps for the 8 adjacent lanes. The scrambler is used to provide enough edge
density, since there is no 8B/10B encoding in PCIe Gen 3, so that the RX PMA CDR can lock to the incoming
data stream and generate the recovered clock.
Encoder
The PCIe Gen 3 base specification defines that the data packets have to be scrambled and descrambled,
whereas the Ordered Set packets (except the first symbol of TS1 and TS2 Ordered Set) do not have to be
scrambled or descrambled. The Encoder/Decoder continuously checks the header and payload of the packet
and generates a signal to enable the scrambler/descrambler based upon whether the payload is an ordered
set, or data packet. It also generates a signal to reset the scrambler/descrambler to the initial seed value if an
Electrical Idle Exit Ordered Set or a Fast Training Sequence Ordered Set is received or transmitted. In
addition, the encoder/decoder logic monitors the Ordered Set and the header for invalid values, and generates
an error flag if they do.
Gearbox
The PCIe 3.0 base specification specifies a block size of 130 bits, with the exception of SKP Ordered Sets
which can be variable length. An implementation of a 130-bit data path would take up significant resources,
so the PCIe Gen 3 PCS data path is implemented as 32 bits wide. As the TX PMA data width is fixed to 32
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bits, and the block size is 130 bits with variations, a gearbox is needed to convert the 130 bits to 32 bits. This
gearbox has a transmitter bit-slip feature.
Receiver PCIe Gen 3 PCS Datapath
This section describes the receiver channel PCIe Gen 3 PCS datapath architecture.
Block Sync
PMA parallelization occurs at arbitrary word boundaries. Consequently, the parallel data from the RX PMA
CDR needs to be realigned to meaningful character boundaries. The Block Sync module searches for the
Electrical Idle Exit Sequence Ordered Set (or the last number of fast training sequences (NFTS) Ordered
Set) and skip (SKP) Ordered Set to identify the correct boundary for the incoming stream and achieve the
block alignment. The block is realigned to the new block boundary following the receipt of a SKP Ordered
Set, as it can be of variable length.
Rate Match FIFO
The Rate Match FIFO (or clock compensation FIFO) compensates for minute frequency differences between
the local clock (sometimes referred to as PLD soft IP clock, or PLD system clock) and the recovered clock.
This is achieved by inserting and deleting SKP characters in the data stream to keep the FIFO from going
empty or full respectively.
Decoder
The Decoder checks for decode errors in the data stream. It also enables or disables the Descrambler based
on the Data and Ordered Set received.
Descrambler
The Descrambler descrambles data per the PCIe Gen 3 specification.
PIPE Interface
The PIPE Interface block provides PIPE Gen 3 compliant control and status interfaces between the high-speed
serial interface (HSSI) and upper layer logic. It is PIPE 3.0 compliant.
Auto Speed Negotiation Block
The Auto Speed Negotiation block controls the operating speed of the HSSI when operating under PIPE 3.0
modes. By monitoring the rate control signal from the PhyMac, this block will change the HSSI from PCIe
Gen 1 operation mode, to Gen 2 operation mode, or from PCIe Gen 1 operation mode to Gen 2 operation
mode to Gen 3 operation mode, or vice versa, with all the appropriate settings.
Electrical Idle Inference Block
In conjunction with side band signals from the PLD side, the Electrical Idle Inference Block infers Electrical
Idle assuming that the signal detect is not reliable. This is based on the PCIe Base Specification Revision
2.0/3.0.
Clock Data Recovery (CDR) Control Block
The CDR control block is used for Rx.L0s fast exit when operating in PIPE/PCIe Gen 3 mode. Upon detecting
an Electrical Idle Ordered Set (EIOS), it takes manual control of the CDR by forcing it into a lock to reference
mode. When an exit from electrical idle is detected, this block moves the CDR into lock to data mode to
achieve fast data lock.
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Channel Bonding
Channel Bonding
The following factors contribute to the transmitter channel-to-channel skew:
• High-speed serial and low-speed parallel clock skew between channels
• Unequal latency in the transmitter phase compensation FIFO
Bonded transmitter datapath clocking provides low channel-to-channel skew when compared with nonbonded channel configurations.
Related Information
For more information about the bonded and non-bonded channel clocking, see Transceiver Clocking in
Arria V Devices.
Bonded Channel Configurations
In bonded channel configurations, the serial and parallel clocks are generated by the transmit PLL and the
central clock divider.
There is equal latency in the transmitter phase compensation FIFO of all bonded channels because they
share common pointers and control logic generated in the central clock divider.
The lower transceiver clock skew and equal latency in the transmitter phase compensation FIFO in all
channels result in a lower channel-to-channel skew.
Note: Bonded channel configurations are available only for serial data rates up to 6.5536 Gbps in Arria V
GX/GT/SX/ST devices and up to 12.5 Gbps in Arria V GZ devices. You can bond (up to) all channels
on the same side.
Non-Bonded Channel Configurations
In a non-bonded channel configuration, the parallel clock in each channel is generated independently by its
local clock divider.
There may be unequal latency in the transmitter phase compensation FIFO of each channel because each
channel has its own pointers and control logic. The higher transceiver clock skew and unequal latency in
the transmitter phase compensation FIFO in each channel may result in a higher channel-to-channel skew.
PLL Sharing
In a Quartus II design, you can merge two different protocol configurations to share the same CMU PLL
resources. These configurations must fit in the same transceiver bank. The input refclk and PLL output
frequencies must be identical.
Document Revision History
The revision history for this chapter.
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Table 1-35: Document Revision History
Date
Version
Changes
March 2014
2014.03.07
•
•
•
•
October 2013
2013.10.18
• Updated the Transceiver Architecture in Arria V Devices
section.
• Updated the Enhanced Small Form-Factor Pluggable
(SFP+) Interface section.
• Updated the Channel PLL Architecture section.
• Updated Table 1-1.
• Updated Table 1-6.
• Updated Table 1-22.
May 2013
2013.05.06
• Added link to the known document issues in the
Knowledge Base
• Updated Figure 1-1.
• Updated Table 1-6.
• Updated the Adaptive Equalization Mode section.
• Updated the Transmitter Buffer section.
• Updated the Receiver Buffer section.
• Updated the Clock Divider section.
• Updated the Word Aligner in Manual Alignment Mode
section.
• Updated the Bit Slip Mode section.
• Updated the Auxiliary Transmit (ATX) PLL Architecture
section.
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Updated the Transmitter Buffer section
Updated the Word Aligner section.
Updated the Word Aligner in Deterministic Latency State
Machine Mode section.
• Updated the Clock Divider section.
• Updated Figure 1-28.
• Added a note to the Rate Match FIFO section.
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Document Revision History
Date
Version
Changes
March 2013
2013.03.15
• Updated Figure 1-2.
• Updated Figure 1-3, and clarified the data rate for rxonly channels.
• Updated Figure 1-7, and clarified the data rate for rxonly channels.
• Updated Transceiver Banks .
• Added 10-Gbps Support Capability in GT and ST
Devices.
• Added Enhanced Small Form-Factor Pluggable (SFP+)
Modules.
• Added 10GBase-KR Support.
• Added 9.8 Gbps CPRI Application.
• Added Transceiver Channel Architecture.
November 2012
2012.11.19
Reorganized content and updated template
June 2012
1.2
• Merged information from Transceiver Basics for Arria
V Devices, version 1.1 into this chapter.
• Updated
• Updated and
• Updated , , , , and
• Added
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This chapter provides information about the Arria V transceiver clocking architecture. The chapter describes
the clocks that are required for operation, internal clocking architecture, and clocking options when the
transceiver interfaces with the FPGA fabric.
Figure 2-1: Transceiver Clocking Architecture Overview
Transceivers
Input Reference Clock
Transmit PLL
or CDR (1)
Internal Clocks
Transceiver
Channels
FPGA Fabric-Transceiver
Interface Clocks
FPGA
Fabric
Note: (1) The transmit phase-locked loop (PLL) can be a CMU PLL (channel PLL), fPLL (fractional PLL Clock) or an ATX PLL (for Arria V GZ devices only.)
Related Information
Arria V Device Handbook: Known Issues
Lists the planned updates to the Arria V Device Handbook chapters.
Input Reference Clocking
The reference clock for the transmitter PLL and CDR generates the clocks required for transceiver operation.
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Input Reference Clocking
Table 2-1: Input Reference Clock Sources
Transmitter PLL
Sources
ATX PLL
(11)
CMU PLL > 6.5536 Gbps
(13)
CMU PLL <= 6.5536 Gbps fPLL CDR
Jitter
(12)
Performance
Dedicated
refclk pin
Yes
Yes
Yes
Yes
Yes
1
REFCLK
network
Yes
Yes
Yes
Yes
Yes
2
Dual-purpose
RX/REFCLK pin
Yes
No(14)
Yes
Yes
Yes
3
Fractional PLL
No
No
Yes
Yes
Yes
4
Generic CLK
pin
No
No
No
No
No
5
Core clock
network
(GCLK, RCLK,
PCLK)
No
No
No
No
No
6
Figure 2-2: Dedicated refclk Pin and Reference Clock Network
The following figure shows the dedicated refclk pin connection to channel PLL. The direct refclk pin
connection to channel PLL (which can either be configured as CMU PLL or CDR) is only available in channel
1 and 4 in a bank.
Reference
Clock Network
Dedicated refclk Pin
N (1)
CH2 Channel PLL
CH1 Channel PLL
fPLL
0
CH0 Channel PLL
Note (1): N is the number of dedicated refclk pins, which is equal to the number of transceiver channels on a side divided by 3.
(11)
(12)
(13)
(14)
ATX PLL is available only in Arria V GZ devices.
The lower number indicates better jitter performance.
Applicable for 10 Gbps channels only in GT and ST devices and for 12.5 Gbps channels in GZ devices. For
better jitter performance, use dedicated refclk pins for data rates > 6.5536 Gbps.
For Arria V GZ devices, the dual-purpose RX/REFCLK pin can be used as a reference clock source for CMU PLL
with data rates > 6.5536 Gbps.
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Figure 2-3: Dedicated refclk Pin and Reference Clock Network for Arria V GZ Devices
Reference
Clock Network
Dedicated refclk Pin
/2
N (1)
CH2 Channel PLL
fPLL
0
CH1 Channel PLL
CH0 Channel PLL
ATX
PLL
Note (1): N is the number of dedicated refclk pins, which is equal to the number of transceiver channels on a side divided by 3.
Note: ATX PLL is available only for Arria V GZ devices.
Figure 2-4: Input Reference Clock Source for CMU PLL Driving Channels with Serial Data Rates Beyond
6.5536 Gbps
Reference
Clock Network
Dedicated refclk Pin
CH2 Channel PLL
CH1 Channel PLL
CH0 Channel PLL
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Table 2-2: Electrical Specifications for the Input Reference Clock for Arria V GZ Devices
Protocol
I/O Standard
PCI Express (PCIe)
All other protocols
Coupling
Termination
• 1.2V PCML, 1.4
PCML
• 1.4V PCML
• 1.5V PCML
• 2.5V PCML
• Differential
LVPECL
• LVDS
AC
On - Chip (15)
• HCSL (16)
DC
Off - Chip (17)
• 1.2V PCML, 1.4
PCML
• 1.4V PCML
• 1.5V PCML
• 2.5V PCML
• Differential
LVPECL
• LVDS
AC
On - Chip (15)
Note: If you select the HCSL I/O standard for the PCIe reference clock, add the following assignment to
your project's quartus settings file (.qsf):
set_instance_assignment -name XCVR_REFCLK_PIN_TERMINATION_DC_COUPLING_EXTERNAL_RESISTOR -to <refclk_pin_name>
Figure 2-5: Termination Scheme for a Reference Clock Signal When Configured as HCSL for Arria V GZ
Devices
PCI Express
(HCSL)
refclk
Source
refclk +
Rs
refclk -
R p = 50 Ω
(15)
(16)
(17)
Arria V GZ
Rs
R p = 50 Ω
For more information about termination values supported, refer to the DC Characteristics section in Arria V
Device Datasheet.
In PCIe mode, you have the option of selecting the HCSL standard for the reference clock if compliance to the
PCIe protocol is required. You can select this I/O standard option only if you have configured the transceiver
in PCIe mode.
For an example termination scheme refer to Figure 2-5
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Note: • No biasing is required if the reference clock signals are generated from a clock source that conforms
to the PCIe specification.
• Select Rs and / or Rp resistor values as recommended by the PCIe clock source vendor.
Related Information
Arria V Device Datasheet
Reference Clock Network
The dedicated refclk pin can provide the reference clock to multiple channel PLLs, fractional PLLs or an
ATX PLL (for Arria V GZ devices).
Designs that use multiple transmitter PLL and CDRs with the same input reference clock frequency can
share the same dedicated refclk pin. Each dedicated refclk pin can drive any transmitter PLL or CDR on the
same side of device through the reference clock network.
Dual-Purpose RX/refclk Pin
When not used as receiver, an RX differential pair can be used as an additional input reference clock source.
The clock from the RX pins feed the RX clock network that spans all the channels on one side of the device.
Only one RX differential pair for every three channels can be used as input reference clock at a time. The
following figure shows the use of dual-purpose RX/refclk differential pin as input reference clock source
and the RX clock network.
Note: • An RX differential pair from another bank can be used as an input reference clock pin on the
same side of the device.
• refclk switching cannot be performed when dual-purpose RX differential pins are used as refclk
pins.
Figure 2-6: Dual-Purpose RX/refclk Pin as an Input Reference Clock
RX Clock
Network
N (1)
CH2 Channel PLL
fPLL
0
Dual-Purpose RX/refclk Pin
CH1 Channel PLL
Dual-Purpose RX/refclk Pin
CH0 Channel PLL
Dual-Purpose RX/refclk Pin
Note (1): N is the number of transceiver channels on a side divided by 3.
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Fractional PLL (fPLL)
Figure 2-7: Dual-Purpose RX/refclk Pin as an Input Reference Clock for GZ Devices
RX Clock
Network
N (1)
CH2 Channel PLL
fPLL
0
Dual-Purpose RX/refclk Pin
CH1 Channel PLL
Dual-Purpose RX/refclk Pin
ATX
PLL(2)
CH0 Channel PLL
Dual-Purpose RX/refclk Pin
Note (1): N is the number of transceiver channels on a side divided by 3.
Note (2): ATX PLL is available only for Arria V GZ devices.
Fractional PLL (fPLL)
The fPLL clock output can be used as input reference clock source to transmitter PLL or CDR.
Cascading the fPLL to transmitter PLL or CDR enables you to use an input reference clock that is not
supported by the transmitter PLL or CDR. The fPLL synthesizes a supported input reference clock for the
transmitter PLL or CDR.
A fPLL is available for each group of three transceiver channels. Each fPLL drives one of two fPLL cascade
clock network lines that can provide an input reference clock to any transmitter PLL or CDR on the same
side of a device. fPLLs support fractional and integer modes. The fractional mode allows you to synthesize
a clock of any supported frequency, and the integer mode allows you to synthesize an output clock that is
an integer multiple or factor of the input clock. For example, fPLLs allow you to take a 100 MHz clock and
synthesize a clock of 50 or 200 MHz in integer mode, or 614.4 MHz in fractional mode.
Note: An fPLL can also be used as a transmit PLL.
Figure 2-8: fPLL Clock Output as Input Reference Clock
fPLL Cascade
Clock Network
2
CH2 Channel PLL
CH1 Channel PLL
fPLL
0
CH0 Channel PLL
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2-7
Internal Clocking
In the internal clocking architecture, different physical coding sublayer (PCS) configurations and channel
bonding options result in various transceiver clock paths.
Table 2-3: Internal Clocking Subsections
The labels listed in the following table and shown in the figure following mark the three sections of the transceiver
internal clocking.
Label
Scope
Description
A
Transmitter Clock Network
Clock distribution from transmitter PLLs to channels
B
Transmitter Clocking
Clocking architecture within transmitter channel datapath
C
Receiver Clocking
Clocking architecture within receiver channel datapath
Figure 2-9: Internal Clocking
Transmitter
Clock
Network
A
Transceiver Channel
B
Transmitter
C
tx_serial_data
CDR
rx_serial_data
Receiver
Input
Reference Clock
Transmit
PLL
Transceiver Channel
Clock Lines
×1 ×6 ×N
tx_serial_data
Transmitter
CDR
(1)
rx_serial_data
Receiver
Input
Reference Clock
Note:
(1) The x6 and xN clock lines are supported only by the Arria V 6-Gbps transceivers.
Note: For Arria V GZ devices, the x6 clock lines can support data rates up to 12.5 Gbps and the xN clock
lines can support data rates up to 9.8304 Gbps.
Transmitter Clock Network
The transmitter PLL is comprised of the ATX PLL, (for GZ devices only) CMU PLL, and fPLL.
All CMU PLLs are identical in architecture, but vary on the following:
• Usage capability: CMU PLL in channel 1 and 4 are capable of distributing a clock with accessibility to
the transmitter clock network, while the rest only are able to clock the transmitter in the same channel
only.
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Transmitter Clock Network
• Performance: Up to 6.5536 Gbps in GX and SX, except for the CMU PLL of channel 1 and 4 in GT and
ST devices, which are capable of up to 10.3125 Gbps. In GZ devices, the CMU PLL in channel 1 and
channel 4 can drive any transceiver channel up to 12.5 Gbps.
Table 2-4: Usage Capability of Each ATX PLL (for GZ devices) and CMU PLL Within a Transceiver Bank
CMU PLL Location in a
Transceiver Bank
Maximum
ATX / CMU
PLL
Clock
Performance
Network
(Gbps)
Access
GZ Devices
only
Maximum CMU PLL
Performance (Gbps)
Usage Capability
GX and SX GT and ST
Devices
Devices
CH 0
No
12.5
6.5536
6.5536
Clock transmitter within same
channel only
CH 1
Yes
12.5
6.5536
10.3125
Clock transmitter within same
channel only and other channels via
clock network
CH 2
No
12.5
6.5536
6.5536
Clock transmitter within same
channel only
CH 3
No
12.5
6.5536
6.5536
Clock transmitter within same
channel only
CH 4
Yes
12.5
6.5536
10.3125
Clock transmitter within same
channel only and other channels via
clock network
CH 5
No
12.5
6.5536
6.5536
Clock transmitter within same
channel only
The fPLLs adjacent to the transceiver banks provide an additional transmitter PLL source for clocking
transceivers up to 3.125 Gbps. Two fPLLs are available as the transmitter PLL for every transceiver bank of
six channels, or one fPLL for a bank of three channels.
The transmitter clock network routes the clock from the transmitter PLL to the transmitter channel. As
shown in Figure 2-9, the transmitter clock network routes the clock from the transmit PLL to the transmitter
channel. A clock divider provides two clocks to the transmitter channel:
• Serial clock—high-speed clock for the serializer
• Parallel clock—low-speed clock for the serializer and the PCS
Arria V transceivers support non-bonded and bonded transceiver clocking configurations:
• Non-bonded configuration—Only the serial clock from the transmit PLL is routed to the transmitter
channel. The clock divider of each channel generates the local parallel clock. The x1 and xN (for Native
PHY IP only) clock lines are used for non-bonded configurations. This configuration is available for both
the 6-Gbps, 10-Gbps and 12.5 Gbps (GZ devices only) transceivers.
• Bonded configuration—Both the serial clock and parallel clock are routed from the central clock divider
in channel 1 or 4 to the bonded transmitter channels. The x6 and xN clock lines are used for bonded
configurations. This configuration is only available for 6 Gbps transceivers. Arria V GZ devices can
support data rates upto 12.5 Gbps on the x6 clock lines and 8 Gbps using PCIe or 9.8304 Gbps using
Native PHY IP on the xN clock lines.
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The transmitter clock network is comprised of x1 (x1 and x1_fPLL), x6 and xN clock lines.
Table 2-5: Characteristics of x1, x6, and xN Clock Lines
Characteristics
x1
x1_fPLL
x6
x6_fPLL
Clock Source
CMU PLL from
CH 1 or CH 4
in a bank (serial
clock only)
fPLL adjacent
to transceivers
(serial clock
only)
Central clock
divider from
Ch 1 or Ch 4
in a bank
(serial and
parallel clock)
Max Data Rate
(Gbps)
10.3125 (GT
and ST) 6.5536
(GX and SX)
3.125
6.5536
Clock Line Span
Within a
transceiver
bank
Within a
Within a
group of 3
transceiver
channels (0, 1, bank
2 or 3, 4, 5)
xN
fPLL through x6 clock lines (serial
the x1_fPLL and parallel clock)
line. The
central clock
divider
resource of
Ch 1 or Ch 4
in a bank is
used (serial
and parallel
clock).
However, the
Ch 1 or Ch 4
can still be
used as the
receiver CDR.
3.125
Within a
transceiver
bank
3.25(18)
Across all channels in
the same side of device
Non-bonded
Configuration
Yes
Yes
Yes
No
Yes
Bonded Configuration
No
No
Yes
Yes
Yes
Table 2-6: Data Rates and Spans Supported by Clock Sources and Clock Networks in Arria V GZ Devices
Clock Network
x1
Transceiver
Channel
GX
Clock Source
Max Data
Rate
ATX PLLs in a transceiver bank
12.5
Gbps(19)
CMU PLLs in a transceiver
bank
12.5
Gbps(19)
Fractional PLLs in a transceiver 3.125 Gbps
bank
(18)
(19)
Bonding
Span
Transceiver bank
Transceiver bank
No
fPLLs can only span
upper or lower 3
channels in a transceiver
bank.
Only for PCIe Gen2 configurations, xN clock lines can support maximum data rate of 5 Gbps.
For the fastest speed grade only. For the remaining speed grades, refer to the Arria V Device Datasheet.
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Transmitter Clock Network
Clock Network
Transceiver
Channel
Clock Source
Max Data
Rate
Bonding
Span
ATX PLLs in a transceiver bank 8 Gbps
provide a serial clock to the
central clock dividers of Ch1
and Ch4. The central clock
dividers in the transceiver bank
drive the x6 clock lines. The xN
clock lines receive only the serial
clock from the x6 clock lines.
xN (Native PHY)
GX
Channel PLLs in a transceiver 7.99
bank provide a serial clock to Gbps
the central clock dividers of Ch1
and Ch4. The central clock
dividers in the transceiver bank
drive the x6 clock lines. The xN
clock lines receive only the serial
clock from the x6 clock lines.
No
xN lines span a side of
the device. Specified
datarate can drive up to
13 data channels above
and up to 13 data
channels below TX PLL.
Fractional PLLs in a transceiver 3.125
bank provide a serial clock to Gbps
the central clock dividers of Ch1
and Ch4. The central clock
dividers in the transceiver bank
drive the x6 clock lines. The xN
clock lines receive only the serial
clock from the x6 clock lines.
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Clock Network
Transceiver
Channel
Clock Source
Max Data
Rate
Bonding
2-11
Span
ATX PLLs in a transceiver bank 12.5
provide a serial clock to the
Gbps(19)
central clock dividers of Ch1
and Ch4. The central clock
dividers in the transceiver bank
drive the x6 clock lines. The x6
clock lines receive both the
serial and parallel clock from
the central clock dividers.
The channel (CMU) PLLs
12.5
provide a serial clock to the
Gbps(19)
central clock dividers of Ch1
and Ch4. The central clock
dividers in the transceiver bank
drive the x6 clock lines. The x6
clock lines receive both the
serial and parallel clock from
the central clock dividers.
x6
GX
x6 PLL Feedback
Compensation (20)
Yes
Transceiver bank
Yes
x6 lines span a
transceiver bank. The x6
lines across multiple
transceiver banks can be
bonded together
through PLL feedback
compensation path to
span the entire side of
the device.
Fractional PLLs provide a serial 3.125
clock to the central clock
Gbps
dividers of Ch1 and Ch4. The
central clock dividers in the
transceiver bank drive the x6
clock lines. The x6 clock lines
receive both the serial and
parallel clock from the central
clock dividers.
One ATX PLL per bonded
12.5
transceiver bank provides a
Gbps(19)
serial clock to the central clock
dividers of Ch 1 and Ch 4. The
central clock dividers in the
transceiver bank drive the x6
clock lines and provide feedback
path to the ATX PLL. The x6
clock lines receive both the
serial and parallel clocks from
the central clock dividers.
12.5 (19)
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Clock Network
Transceiver
Channel
Clock Source
Max Data
Rate
Bonding
8 Gbps
Yes
Span
One CMU PLL per bonded
transceiver bank provides a
serial clock to the central clock
dividers of Ch 1 and Ch 4. The
central clock dividers in the
transceiver bank drive the x6
clock lines and provide feedback
path to the CMU PLL. The x6
clock lines receive both the
serial and parallel clocks from
the central clock dividers.
xN (PCIe)(21)
(20)
(21)
GX
The ATX or channel (CMU)
PLL provides a serial clock to
the central clock dividers of Ch1
and Ch4. The central clock
dividers in the transceiver bank
drive the x6 clock lines. The xN
clock lines receive the serial and
parallel clocks from the x6 clock
lines.
xN lines span a side of
the device, but can bond
only up to eight
contiguous data
channels.
The input reference clock frequency of the transmit PLL must be the same as the parallel clock frequency which
clock the PCS bonded channels.
For more information about PCIe x8 configurations, refer to the Transceiver Configurations in Arria V GZ
Devices chapter.
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Clock Network
Transceiver
Channel
Clock Source
ATX PLLs in a transceiver bank
provide a serial clock to the
central clock dividers of Ch1
and Ch4. The central clock
dividers in the transceiver bank
drive the x6 clock lines. The xN
clock lines receive the serial and
parallel clocks from the x6 clock
lines.
xN (Native
PHY)
GX
Max Data
Rate
Bonding
9.8304
Gbps
Yes
xN lines span a side of
the device. Specified
datarate can bond up to
7 contiguous data
channels above and up
to 7 contiguous data
channels below TX PLL.
8 Gbps
Yes
xN lines span a side of
the device. Specified
datarate can bond up to
13 contiguous data
channels above and up
to 13 contiguous data
channels below TX PL
Channel (CMU) PLLs in a
7.99 Gbps
transceiver bank provide a serial
clock to the central clock
dividers of Ch1 and Ch4. The
central clock dividers in the
transceiver bank drive the x6
clock lines. The xN clock lines
receive the serial and parallel
clocks from the x6 clock lines.
Fractional PLLs (fPLLs) in a
3.125 Gbps
transceiver bank provide a serial
clock to the central clock
dividers of Ch1 and Ch4. The
central clock dividers in the
transceiver bank drive the x6
clock lines. The xN clock lines
receive the serial and parallel
clocks from the x6 clock lines.
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Yes
Span
xN lines span a side of
the device. Specified
datarate can bond up to
13 contiguous data
channels above and up
to 13 contiguous data
channels below TX PL
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Transmitter Clock Network
Figure 2-10: x1 Clock Line Architecture (up to 6.5536 Gbps)
x1_top x1_bot x1_fPLL
CMU PLL
CH5
Local Clock Divider
CMU PLL
CH4
fPLL 1
Local Clock Divider
CMU PLL
CH3
Local Clock Divider
CMU PLL
CH2
Local Clock Divider
CMU PLL
CH1
fPLL 0
Local Clock Divider
CMU PLL
CH0
Local Clock Divider
x1_fPLL
Note: All clock lines shown in this figure carry the serial clock only. x1_fPLL can support data rates upto 3.125 Gbps only.
The x1 clock lines are driven by serial clocks of CMU PLLs from channels 1 and 4. The serial clock in the
x1 clock line is then distributed to the local and central clock dividers of every channel within a transceiver
bank.
The x1_fPLL clock lines are driven by the serial clocks of the adjacent fPLL. The serial clock in the x1_fPLL
clock lines, is then distributed to the local and central clock dividers of channels within a group of three
channels (0, 1, 2 or 3, 4, 5).
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Figure 2-11: x1 Clock Line Architecture (more than 6.5536 Gbps)
x1_top x1_bot
CMU PLL
CH5
Local Clock Divider
CMU PLL
CH4
Local Clock Divider
CMU PLL
CH3
Local Clock Divider
CMU PLL
CH2
Local Clock Divider
CMU PLL
CH1
Local Clock Divider
CMU PLL
CH0
Local Clock Divider
Note: All clock lines shown in this figure carry the serial clock only.
For serial data rates beyond 6.5536 Gbps (10-Gbps channels only in GT and ST devices). The x1 clock lines
are driven by the serial clocks of CMU PLLs from channels 1 and 4. The serial clock in the x1 clock line is
then distributed to the local and central clock dividers of every channel within a transceiver bank.
Note: When you configure the channel PLL as a CMU PLL to drive the local clock divider, or the central
clock divider of its own channel, you cannot use the channel PLL as a CDR. Without a CDR, you
can use the channel only as a transmitter channel.
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Transmitter Clock Network
Figure 2-12: x1 Clock Line Architecture (up to 12.5 Gbps) for GZ Devices
x1
CMU PLL
CH5
Local Clock Divider
CMU PLL
CH4
x1
x1
x1
x1_fPLL
ATX
PLL
fPLL 1
Local Clock Divider
CMU PLL
CH3
Local Clock Divider
CMU PLL
CH2
Local Clock Divider
CMU PLL
CH1
ATX
PLL
fPLL 0
Local Clock Divider
CMU PLL
CH0
Local Clock Divider
x1_fPLL
Note: All clock lines shown in this figure carry the serial clock only. In Arria V GZ devices, fPLLs support data rate up to 3.125 Gbps only.
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Figure 2-13: x6 and xN Clock Line Architecture
x6_top x6_bot xN_top
xN_bot
CH5 Local Clock Divider
CH4
Central Clock
CH3 Local Clock Divider
CH2 Local Clock Divider
CH1
Central Clock
CH0 Local Clock Divider
xN_top
xN_bot
x6_top x6_bot
CH5 Local Clock Divider
CH4
Central Clock
CH3 Local Clock Divider
CH2 Local Clock Divider
CH1
Central Clock
CH0 Local Clock Divider
xN_top
xN_bot
x6_top x6_bot
CH5 Local Clock Divider
CH4
Central Clock
CH3 Local Clock Divider
CH2 Local Clock Divider
CH1
Central Clock
CH0 Local Clock Divider
xN_top
xN_bot
Note: All the clock lines shown in this figure carry both the serial and parallel clocks.
The x6 clock lines are driven by serial and parallel clocks from the central clock divider in channels 1 and
4. For channels within a bank, the serial and parallel clocks in the x6 clock line is then distributed to every
channel within a transceiver bank.
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Transmitter Clocking
The xN clock lines extend the clocking reach of the x6 clock line to all channels within the same side of the
device. To reach a xN clock line, the clocks must be provided on the x6 clock line. The serial and parallel
clocks in the x6 clock line is distributed to every channel within a transceiver bank. The serial and parallel
clocks are distributed to other channels beyond the bank using the xN clock line.
In bonded configurations, serial and parallel clocks from the x6 or xN clock lines are received by the clock
divider of every bonded channel and fed directly to the serializer. In a non-bonded configuration, the clock
divider of every non-bonded channel receives the serial clock from the x6 or xN clock lines and generates
the individual parallel clock to the serializer.
Note: • In a bonded configuration, bonded channels must be placed contiguously without leaving a gap
between the channels, except when the gap channel is a CMU PLL.
• xN bonded configuration is only supported by PIPE and Native PHY IP.
Related Information
Transceiver Configurations in Arria V GZ Devices
Arria V Device Datasheet
Transmitter Clocking
Transmitter (TX) clocking refers to the clocking architecture that is internal to the TX channel of a transceiver.
The following figure shows how the clock divider provides the serial clock to the serializer, and the parallel
clock to the serializer and TX PCS. When the byte serializer is not used, the parallel clock is used to clock
all the blocks up to the read side of the TX phase compensation FIFO. For configurations with the byte
serializer, the parallel clock is divided by a factor of two for the byte serializer and the read side of the TX
phase compensation FIFO. The read side clock of the TX phase compensation FIFO is also forwarded to the
FPGA fabric to interface the FPGA fabric with the transceiver.
Figure 2-14: Clocking Architecture for Transmitter PCS and PMA Configuration
Local/Central
clock divider
TX Phase
Compensation
FIFO
Byte Serializer
8B/10B Encoder
FPGA Fabric
TX Bit Slip
Transmitter PCS
Serializer
tx_serial_data
Transmitter PMA
/2
tx_parallel_data
tx_coreclkin /
tx_std_coreclkin
tx_clkout /
tx_std_clkout
Both Parallel and Serial Clocks
Serial Clock
Parallel Clock
Data Path
Transmitter
Table 2-7: Clock Sources for All TX PCS Blocks
PCS Block
TX Phase Compensation
FIFO
Altera Corporation
Side
Clock Source
Write
FPGA fabric write clock, driven either by tx_clkout or tx_
coreclkin
Read
Parallel clock (divided). Clock forwarded to FPGA fabric as tx_
clkout
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PCS Block
Side
2-19
Clock Source
Write
Parallel clock (divided) either by factor of 1 (not enabled), or
factor of 2 (enabled)
Read
Parallel clock
8B/10B Encoder
—
Parallel clock
TX Bit Slip
—
Parallel clock
Byte Serializer
The following figure shows how the clock divider provides the serial and parallel clock to the serializer in a
transmitter PMA configuration. The parallel clock is forwarded to the FPGA fabric to interface the FPGA
fabric with the TX PMA directly, bypassing the PCS blocks.
Figure 2-15: Clocking Architecture for Transmitter PMA Only Configuration
Transmitter PCS (Not Enabled)
Serializer
tx_serial_data
Transmitter PMA
FPGA Fabric
tx_pma_parallel data
tx_pma_clkout
Local/Central
Clock Divider
Both Parallel and Serial Clocks
Serial Clock
Parallel Clock
Data Path
Transmitter 10G PCS Clocking for GZ Devices
The following figure shows the clocking scheme for the transmitter 10G PCS and transmitter physical
medium attachment (PMA). The clock divider block provides the serial clock to the serializer of the transmitter
PMA and the parallel clock to the transmitter PCS. In the 10G PCS channel, the parallel clock is used by all
the blocks up to the read side of the transmitter (TX) FIFO.
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Figure 2-16: Transmitter 10G PCS Clocking for GZ Devices
Transmitter 10G PCS
TX
FIFO
Frame Generator
CRC32
Generator
Scrambler
64B/66B Encoder
and TX SM
FPGA
Fabric
Disparity
Generator
Serializer
TX Gear Box
and Bitslip
Transmitter PMA
tx_coreclkin /
tx_10g_coreclkin
tx_clkout /
tx_10g_clkout
Parallel and Serial Clocks
(To the ×6 clock lines) (1)
Central/ Local Clock Divider
CMU PLL
Clock Divider
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Serial Clock
(From the ×1 Clock Lines)
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines) (2)
Notes: (1) Available only in the central clock dividers of channel 1 and channel 4 in a transceiver bank.
(2) x1 clock lines can be driven by a CMU PLL, ATX PLL, or a fractional PLL.
Non-Bonded Channel Configurations
The channel clock path for non-bonded configurations can be driven by the x1, or the x6 and xN clock lines.
Table 2-8: Clock Path for Non-Bonded Configurations
The following table describes the clock path for non-bonded configuration with the ATX PLL, CMU PLL, and fPLL
as TX PLL using various clock lines.
Clock Line
Transmitter PLL
(22)
ATX PLL
x1
CMU
fPLL » x1_fPLL » individual clock divider » serializer
(22)
(22)
(23)
ATX PLL » x1 » individual clock divider » serializer
CMU PLL » x1 » individual clock divider » serializer
fPLL
x6, xN
Clock Path
ATX PLL
ATX PLL » central clock divider » x6 » xN » individual clock divider
» serializer
CMU
CMU PLL » central clock divider » x6 » xN » individual clock divider
» serializer (23)
fPLL
fPLL » x1_fPLL » central clock divider » x6 » individual clock divider
» serializer (23)
ATX PLL is available only for GZ devices.
Non-bonded channels within same bank as TX PLL are driven by clocks from x6 clock line, and channels
in other banks are driven from xN clock line.
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Figure 2-17: Three Non-Bonded Transmitter Channels Driven by CMU PLL using x1 Clock Line Within a
Transceiver Bank
x1_top
TX PCS Ch5
Serializer
tx_serial_data
TX PMA Ch5
Local Clock Divider
Clock Divider
TX PCS Ch4
Serializer
tx_serial_data
TX PMA Ch4
CMU PLL
Central Clock Divider
Clock Divider
TX PCS Ch3
Serializer
tx_serial_data
TX PMA Ch3
CMU PLL
Local Clock Divider
Clock Divider
CMU PLL
Channels 0, 1, 2
Both Parallel and Serial Clocks
Data Path
Serial Clock
Unused Resources
Parallel Clock
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Figure 2-18: Three Non-Bonded Transmitter Channels Driven by fPLL using x1 Clock Line Within a Transceiver
Bank
x1_fPLL
TX PCS Ch5
Serializer
tx_serial_data
TX PMA Ch5
Local Clock Divider
Clock Divider
TX PCS Ch4
Serializer
tx_serial_data
TX PMA Ch4
CMU PLL
fPLL 1
Central Clock Divider
Clock Divider
TX PCS Ch3
Serializer
tx_serial_data
TX PMA Ch3
CMU PLL
Local Clock Divider
Clock Divider
Both Parallel and Serial Clocks
Data Path
Serial Clock
Unused Resources
CMU PLL
Parallel Clock
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Figure 2-19: Three Non-Bonded Transmitter Channels Driven by ATX PLL using x1 Clock Line Within a
Transceiver Bank for GZ Devices.
x1 clock line
TX PCS Ch5
Serializer
tx_serial_data
TX PMA Ch5
ATX
PLL(1)
Local Clock Divider
Clock Divider
TX PCS Ch4
Serializer
tx_serial_data
TX PMA Ch4
CMU PLL
Central Clock Divider
Clock Divider
TX PCS Ch3
Serializer
tx_serial_data
TX PMA Ch3
CMU PLL
Local Clock Divider
Clock Divider
Both Parallel and Serial Clocks
Data Path
Serial Clock
Unused Resources
CMU PLL
Parallel Clock
Note : (1) ATX PLL is available only for Arria V GZ devices.
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Figure 2-20: Three Non-Bonded Transmitter Channels Driven by CMU PLL using x6 and xN Clock Lines Across
Multiple Transceiver Banks
tx_serial_data
TX PCS Ch0
Serializer
TX PMA Ch0
xN_top x6_bot x6_top
Local Clock Divider
Clock Divider
TX PCS Ch5
Serializer
x6_bot x6_top
tx_serial_data
TX PMA Ch5
CMU PLL
Local Clock Divider
TX PMA Ch4
CMU PLL
TX PCS Ch4
Serializer
tx_serial_data
Clock Divider
Central Clock Divider
Clock Divider
TX PCS Ch3
Serializer
tx_serial_data
TX PMA Ch3
CMU PLL
Local Clock Divider
Clock Divider
xN_top Channels 0, 1, 2
CMU PLL
Both Parallel and Serial Clocks
Data Path
Serial Clock
Unused Resources
Parallel Clock
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Figure 2-21: Three Non-Bonded Transmitter Channels Driven by fPLL using x6 and xN Clock Line Across
Multiple Transceiver Banks
tx_serial_data
TX PCS Ch0
Serializer
TX PMA Ch0
xN_top x6_bot x6_top
Local Clock Divider
Clock Divider
TX PCS Ch5
Serializer
x6_bot x6_top
tx_serial_data
TX PMA Ch5
CMU PLL
x1_fPLL
Local Clock Divider
Clock Divider
TX PCS Ch4
Serializer
tx_serial_data
TX PMA Ch4
CMU PLL
fPLL 1
Central Clock Divider
Clock Divider
TX PCS Ch3
Serializer
tx_serial_data
TX PMA Ch3
CMU PLL
Local Clock Divider
Clock Divider
xN_top Channels 0, 1, 2
CMU PLL
Both Parallel and Serial Clocks
Data Path
Serial Clock
Unused Resources
Parallel Clock
When the fPLL is used to drive more than three non-bonded channels, the channel where the central clock
divider resides adjacent to the fPLL cannot be used as a transmitter. The fPLL uses a central clock divider
to access the x6 clock network when driving more than three non-bonded channels, so the divider is no
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Bonded Channel Configurations
longer available to implement a transmitter. For xN non-bonded configurations, the ch 1 or ch 4 transceiver
bank where the central clock divider resides cannot be used as a data channel since the parallel clock cannot
be generated in this channel.
Bonded Channel Configurations
The channel clock path for bonded configurations is driven by the x6 and xN clock lines.
Table 2-9: Clock Path for Bonded Configurations
The following table describes the clock path for a bonded configuration with ATX PLL, CMU PLL, or fPLL as TX
PLL using various clock lines.
Clock Line
Transmitter PLL
ATX PLL(25)
x6, xN
x6 PLL Feedback Compensation (26)
(24)
(25)
(26)
Clock Path
CMU PLL » central clock divider » x6 » xN » serializer
CMU
CMU PLL » central clock divider » x6 » xN » serializer (24)
fPLL
fPLL » x1_fPLL » central clock divider » x6 » serializer (24)
ATX PLL (25)
ATX PLL » central clock divider » x6 » serializer
CMU
CMU PLL » central clock divider » x6 » serializer
Bonded channels within same bank as the TX PLL are driven by clocks from the x6 clock line, and channels in
other banks are driven from the xN clock line.
ATX PLL is available for GZ devices only.
x6 PLL Feedback Compensation is available for GZ devices only.
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Figure 2-22: Four Bonded Transmitter Channels Driven by CMU PLL using x6 and xN Clock Lines Across
Multiple Transceiver Banks
tx_serial_data
TX PCS Ch0
Serializer
TX PMA Ch0
xN_top x6_bot x6_top
Local Clock Divider
Clock Divider
TX PCS Ch5
Serializer
x6_bot x6_top
tx_serial_data
TX PMA Ch5
CMU PLL
Local Clock Divider
Clock Divider
TX PCS Ch4
Serializer
tx_serial_data
TX PMA Ch4
CMU PLL
Central Clock Divider
Clock Divider
TX PCS Ch3
Serializer
tx_serial_data
TX PMA Ch3
CMU PLL
Local Clock Divider
Clock Divider
xN_top Channels 0, 1, 2
CMU PLL
Both Parallel and Serial Clocks
Data Path
Serial Clock
Unused Resources
Parallel Clock
Note: When channel PLL is configured as a CMU PLL to drive the local clock divider or the central clock
divider of its own channel, the channel PLL cannot be used as a CDR. Without a CDR, the channel
can be used only as a transmitter.
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Figure 2-23: Four Bonded Transmitter Channels Driven by fPLL using x6 Clock Line Within a Transceiver
Bank
TX PCS Ch3
Serializer
xN_top x6_bot x6_top
tx_serial_data
TX PMA Ch5
x1_fPLL
Local Clock Divider
Clock Divider
TX PCS Ch2
Serializer
tx_serial_data
TX PMA Ch4
CMU PLL
Central Clock Divider
Clock Divider
TX PCS Ch1
Serializer
tx_serial_data
TX PMA Ch1
CMU PLL
fPLL 1
Local Clock Divider
Clock Divider
TX PCS Ch0
Serializer
tx_serial_data
TX PMA Ch0
CMU PLL
Local Clock Divider
Clock Divider
CMU PLL
Both Parallel and Serial Clocks
Data Path
Serial Clock
Unused Resources
Parallel Clock
Note: • When using the fPLL to drive bonded channels, assign logical channel 0 to the channel where the
central clock divider is used for fPLL clocks to access the x6 clock line. Using the preceding figure
as an example, assign tx_serial_data[0] to the transmitter channel 4 pin location.
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• For xN bonded configurations, the channel where the central clock divider resides (ch 1 or ch 4)
can be used as a data channel as the parallel clock can be generated in this channel.
Bonded Channel Configurations Using the PLL Feedback Compensation Path for GZ Devices
You can bond channels across multiple banks by using the PLL feedback compensation path.
The PLL feedback compensation path loops the parallel clock, which is used by the PCS blocks, back to the
transmitter PLL. The PLL feedback compensation path synchronizes the parallel clock used to clock the PCS
blocks in all transceiver banks with the refclk. You can use the PLL feedback compensation path to reduce
channel-to-channel skew, which is introduced by the clock divider in each transceiver bank.
To bond channels using the PLL feedback compensation path, the input reference clock frequency used by
the transmitter PLL must be the same as the parallel clock that clocks the PCS of the same channel.
Note: If the input reference clock frequency is not equal to the parallel clock frequency, use a fractional
PLL to synthesize an input reference clock with the same frequency as the parallel clock.
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Figure 2-24: Three Transceiver Bank Channels Bonded Using the PLL Feedback Compensation Path for GZ
Devices
Reference
Clock
Network
PMA
PMA
PMA
PMA
PMA
PMA
Transceiver
Bank
PCS
PCS
PCS
PCS
FPGA
Fabric
PCS
PCS
tx_clkout (2)
Parallel Clock
/n
Transmitter
PLL (1)
Serial Clock
PMA
PMA
PMA
PMA
PMA
PMA
PLL Feedback
Compensation
Path
Transceiver
Bank
PCS
PCS
PCS
PCS
PCS
PCS
tx_clkout (2)
Parallel Clock
/n
Compatible
Input
Reference
Clock
Transmitter
PLL (1)
Serial Clock
PLL Feedback
Compensation
Path
Fractional
PLL
Incompatible
Input
Reference
Clock
PMA
PMA
PMA
PMA
PMA
PMA
Transceiver
Bank
PCS
PCS
PCS
PCS
PCS
PCS
tx_clkout (2)
/n
Parallel Clock
Serial Clock
Transmitter
PLL (1)
PLL Feedback
Compensation
Path
Notes: (1) The transmitter PLL can be an ATX PLL, CMU PLL, or a fractional PLL. You can have up to six channels per bank
with an ATX PLL and five channels per bank with a CMU PLL.
(2) tx_clkout from any of the banks can be used with the FPGA fabric-transceiver interface for all the bonded channels.
Note: • Every transceiver bank with a bonded channel configured using the PLL feedback compensation
path consumes a transmit PLL.
• fPLL does not support PLL feedback compensation when used as a TX PLL.
Transceiver Channel Placement Guidelines for fPLL in Transmit PLL Bonded Configuration (Except GZ Devices)
The fPLL as transmit PLL, when configured in bonded configuration, has placement restrictions. All channels
need to be placed within one transceiver bank. For the example shown in the following figure, all four
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channels must be placed within one transceiver bank. A link cannot span across two banks. The channel
placement must also be contiguous.
Figure 2-25: Transceiver Channel Placement for fPLL in a Transmit PLL Bonded Configuration
The following figure shows the allowed channel placement when using a x4 bonded configuration. The
logical lane 0 must be placed in either Ch1 or Ch4.
Xcvr Ch 5
Xcvr Ch 4
Xcvr Ch 3
Xcvr Ch 2
Xcvr Ch 1
Xcvr Ch 0
fPLL Bonding
Logical Lane 0
Xcvr Ch 5
Xcvr Ch 4
Xcvr Ch 3
Xcvr Ch 2
Xcvr Ch 1
Xcvr Ch 0
fPLL Bonding
Logical Lane 0
Note: A QSF assignment statement can be used to change the Logical Lane 0 assignment to a different
transceiver channel.
Receiver Clocking
Receiver clocking refers to the clocking architecture internal to the receiver channel of a transceiver.
Figure 2-26: Clocking Architecture for Receiver PCS and PMA Configuration
Parallel Clock
(Recovered)
Input
Reference
Clock
Parallel Clock (from the Clock Divider)
RX Phase
Compensation
FIFO
Byte Ordering
Byte Deserializer
8B/10B Decoder
FPGA Fabric
Rate Match FIFO
Word Aligner
Receiver PCS
Deserializer
CDR
rx_serial_data
Receiver PMA
/2
rx_parallel_data
rx_coreclkin /
rx_std_coreclkin
rx_clkout /
rx_std_clkout
Data Path
Serial Clock
Parallel Clock
The CDR in the PMA of each channel recovers the serial clock from the incoming data and generates the
parallel clock (recovered) by dividing the serial clock (recovered). The deserializer uses both clocks. The
receiver PCS can use the following clocks depending on the configuration of the receiver channel:
• Parallel clock (recovered) from the CDR in the PMA
• Parallel clock from the clock divider that is used by the channel’s transmitter PCS
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Receiver Clocking
Table 2-10: Clock Sources for All Receiver PCS Blocks
PCS
Block
Word aligner
Rate match FIFO
8B/10B decoder
Side
-
Parallel clock (recovered)
Write
Parallel clock (recovered)
Read
Parallel clock from the clock divider
-
• Rate match FIFO is not used-Parallel clock
(recovered)
• Rate match FIFO is used-Parallel clock from
the clock divider
Write
• Rate match FIFO is not used-Parallel clock
(recovered)
• Rate match FIFO is used-Parallel clock from
the clock divider
Read
Divided down version of the write side clock
depending on the deserialization factor of 1 or
2, also called the parallel clock (divided)
Standard
Byte deserializer
Byte ordering
Receiver (RX)
phase
compensation
FIFO
10G(27)
(27)
(28)
All other PCS blocks
Clock Source
-
Parallel clock (divided)
Write
Parallel clock (divided). This clock is also
forwarded to the FPGA fabric.
Read
Clock sourced from the FPGA fabric
• Regular mode: parallel clock (recovered)
• Loopback mode: parallel clock from the clock
divider.(28)
Available for Arria V GZ devices only.
For more information about loopback mode, refer to the Transceiver Loopback Support chapter in Arria V
Devices.
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Receiver Non-Bonded Channel Configurations
Figure 2-27: Clocking Architecture for Receiver PMA Only Configuration
The parallel recovered clock from the CDR and deserializer is forwarded to the FPGA fabric to interface
FPGA fabric with the receiver PMA directly, bypassing the PCS blocks.
Receiver PCS (Not enabled)
FPGA Fabric
Deserializer
CDR
rx_serial_data
Receiver PMA
rx_pma_parallel_data
rx_pma_clkout
Parallel Clock
(Recovered)
Input
Reference
Clock
Data Path
Serial Clock
Parallel Clock
Clocking Architecture for Receiver 10G PCS and the Receiver PMA for GZ Devices.
Figure 2-28: Clocking Architecture for 10G PCS and the Receiver PMA for GZ Devices
Input
Reference
Clock
RX
FIFO
CRC32
Checker
FPGA
Fabric
64B/66B Decoder
and RX SM
Frame Synchronizer
Descrambler
Disparity Checker
CDR
Recovered
Clocks
Block Synchronizer
RX Gear Box
and Bitslip
Receiver 10G PCS
Deserializer
Receiver PMA
rx_10g_coreclkin /
rx_coreclkin
Parallel Clock (Recovered)
Parallel Clock (from the clock divider)
rx_10g_clkout /
tx_10g_clkout
Parallel and Serial Clocks
(To the ×6 clock lines) (1)
Central/ Local Clock Divider
Clock Divider
To Transmitter
Channel
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
CMU PLL
Serial Clock
(From the ×1 Clock Lines)
Note: (1) Available only in the central clock dividers of channel 1 and channel 4 in a transceiver bank.
Related Information
• Transceiver Loopback Support in Arria V Devices
Receiver Non-Bonded Channel Configurations
The receiver clocking in non-bonded mode varies, depending on whether the rate match FIFO is enabled.
When the rate match FIFO is not enabled, the receiver PCS in every channel uses the parallel recovered
clock. When the rate match FIFO is enabled, the receiver PCS in every channel uses both the parallel recovered
clock and parallel clock from the clock divider.
For Arria V GZ devices, in non-bonded configurations the receiver 10G PCS uses only the parallel clock
(recovered) for all its blocks.
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Receiver Non-Bonded Channel Configurations
Figure 2-29: Three Non-Bonded Receiver Channels without Rate Match FIFO Enabled
Receiver PCS Ch5
Deserializer
CDR
rx_serial_data
Receiver PMA Ch5
Parallel Clock
(Recovered)
Input
Reference
Clock
Local Clock Divider
Parallel Clock
(from the
Clock Divider)
Clock Divider
CMU PLL
To Transmitter Channel
From the x6 or xN Clock Lines
Receiver PCS Ch4
Deserializer
CDR
rx_serial_data
Receiver PMA Ch4
Parallel Clock
(Recovered)
Input
Reference
Clock
Central Clock Divider
Parallel Clock
(from the
Clock Divider)
Clock Divider
CMU PLL
To Transmitter Channel
From the x6 or xN Clock Lines
Receiver PCS Ch3
Deserializer
CDR
rx_serial_data
Receiver PMA Ch3
Parallel Clock
(Recovered)
Input
Reference
Clock
Local Clock Divider
Parallel Clock
(from the
Clock Divider)
Clock Divider
CMU PLL
To Transmitter Channel
From the x6 or xN Clock Lines
Both Parallel and Serial Clocks
Data Path
Serial Clock
Unused Resources
Parallel Clock
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Figure 2-30: Two Non-Bonded Receiver Channels with Rate Match FIFO Enabled
x1_top
Receiver PCS Ch5
Deserializer
CDR
rx_serial_data
Receiver PMA Ch5
Parallel Clock
(Recovered)
Input
Reference
Clock
Parallel Clock
(from the
Clock Divider)
Local Clock Divider
Clock Divider
CMU PLL
Clock Divider
CMU PLL
Clock Divider
CMU PLL
To Transmitter Channel
Receiver PCS Ch4
Deserializer
CDR
rx_serial_data
Receiver PMA Ch4
Parallel Clock
(Recovered)
Input
Reference
Clock
Parallel Clock
(from the
Clock Divider)
Local Clock Divider
To Transmitter Channel
Receiver PCS Ch3
Deserializer
CDR
rx_serial_data
Receiver PMA Ch3
Parallel Clock
(Recovered)
Input
Reference
Clock
Parallel Clock
(from the
Clock Divider)
Local Clock Divider
To Transmitter Channel
Channels 0, 1, 2
Both Parallel and Serial Clocks
Data Path
Serial Clock
Unused Resources
Parallel Clock
Receiver Bonded Channel Configurations
Receiver channels can only be bonded in configurations where rate match FIFOs are enabled. When bonded,
the receiver PCS requires the parallel clock (recovered) and, the parallel clock from the central clock divider
in channel 1 or 4.
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Receiver Bonded Channel Configurations
For Arria V GZ devices, in bonded configurations the receiver 10G PCS uses only the parallel clock (recovered)
for all its blocks.
rx_serial_data
Figure 2-31: Five Bonded Receiver Channels with Rate Match FIFO Enabled
Receiver PMA Ch5
CDR
Receiver PCS Ch5
Deserializer
Parallel Clock
(Recovered)
Input
Reference
Clock
Parallel Clock
(from the
Clock Divider)
Local Clock Divider
Clock Divider
CMU PLL
To Transmitter Channel
rx_serial_data
From the x1
Clock Lines
Receiver PMA Ch4
CDR
Receiver PCS Ch4
Deserializer
Parallel Clock
(Recovered)
Input
Reference
Clock
Parallel Clock
(from the
Clock Divider)
Central Clock Divider
Clock Divider
From the x1
Clock Lines
rx_serial_data
To Transmitter Channel
Receiver PMA Ch3
CDR
CMU PLL
Receiver PCS Ch3
Deserializer
Parallel Clock
(Recovered)
Input
Reference
Clock
Parallel Clock
(from the
Clock Divider)
Local Clock Divider
Clock Divider
CMU PLL
To Transmitter Channel
rx_serial_data
From the x1
Clock Lines
Receiver PMA Ch2
CDR
Receiver PCS Ch2
Deserializer
Parallel Clock
(Recovered)
Input
Reference
Clock
Parallel Clock
(from the
Clock Divider)
Local Clock Divider
Clock Divider
CMU PLL
To Transmitter Channel
rx_serial_data
From the x1
Clock Lines
Receiver PMA Ch1
CDR
Receiver PCS Ch1
Deserializer
Parallel Clock
(Recovered)
Input
Reference
Clock
Parallel Clock
(from the
Clock Divider)
Central Clock Divider
Clock Divider
CMU PLL
To Transmitter Channel
rx_serial_data
From the x1
Clock Lines
Receiver PMA Ch0
CDR
Receiver PCS Ch0
Deserializer
Parallel Clock
(Recovered)
Input
Reference
Clock
Parallel Clock
(from the
Clock Divider)
Local Clock Divider
Clock Divider
CMU PLL
To Transmitter Channel
From the x1
Clock Lines
x6 Clock Lines
Altera Corporation
Both Parallel and Serial Clocks
Data Path
Serial Clock
Unused Resources
Parallel Clock
Receiver
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Figure 2-32: Six Bonded Receiver Channels with Rate Match FIFO Enabled Using Fractional PLL
rx_serial_data
All six channels in the transceiver bank are in a bonded configuration. This configuration is possible because
the fractional PLL is used as a transmit PLL instead of a channel PLL in the transceiver bank. Using the
fractional PLL enables you to configure the channel PLLs of both channels 1 and 4 as CDRs to perform
receiver operations.
Receiver PMA Ch5
CDR
Receiver PCS Ch5
Deserializer
Parallel Clock
(Recovered)
Input
Reference
Clock
Parallel Clock
(from the
Clock Divider)
Local Clock Divider
Clock Divider
CMU PLL
To Transmitter Channel
rx_serial_data
From the x1
Clock Lines
Fractional
PLL
Receiver PMA Ch4
CDR
Receiver PCS Ch4
Deserializer
Parallel Clock
(Recovered)
Input
Reference
Clock
Parallel Clock
(from the
Clock Divider)
Central Clock Divider
Clock Divider
CMU PLL
rx_serial_data
To Transmitter Channel
Receiver PMA Ch3
CDR
Receiver PCS Ch3
Deserializer
Parallel Clock
(Recovered)
Input
Reference
Clock
Parallel Clock
(from the
Clock Divider)
Local Clock Divider
Clock Divider
CMU PLL
To Transmitter Channel
rx_serial_data
From the x1
Clock Lines
Receiver PMA Ch2
CDR
Receiver PCS Ch2
Deserializer
Parallel Clock
(Recovered)
Input
Reference
Clock
Parallel Clock
(from the
Clock Divider)
Local Clock Divider
Clock Divider
CMU PLL
To Transmitter Channel
rx_serial_data
From the x1
Clock Lines
Fractional
PLL
Receiver PMA Ch1
CDR
Receiver PCS Ch1
Deserializer
Parallel Clock
(Recovered)
Input
Reference
Clock
Parallel Clock
(from the
Clock Divider)
Central Clock Divider
Clock Divider
CMU PLL
To Transmitter Channel
rx_serial_data
From the x1
Clock Lines
Receiver PMA Ch0
CDR
Receiver PCS Ch0
Deserializer
Parallel Clock
(Recovered)
Input
Reference
Clock
Parallel Clock
(from the
Clock Divider)
Local Clock Divider
Clock Divider
CMU PLL
To Transmitter Channel
From the x1
Clock Lines
x1 Clock Lines
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Both Parallel and Serial Clocks
Data Path
Serial Clock
Unused Resources
Parallel Clock
Receiver
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Receiver Bonded Channel Configurations
Figure 2-33: Six Channels Configured in Bonded Configuration Using ATX PLL for GZ Devices
rx_serial_data
All six channels in the transceiver bank in a bonded configuration. Six channel bonding is possible because
the ATX PLL is used as a transmitter PLL instead of a channel PLL in the transceiver bank. Using the ATX
PLL or fractional PLL allows you to use the channel PLLs of both channels 1 and 4 as CDRs to perform
receiver operations.
Receiver PMA Ch5
CDR
Receiver PCS Ch5
Deserializer
Parallel Clock
(Recovered)
Input
Reference
Clock
Parallel Clock
(from the
Clock Divider)
Local Clock Divider
Clock Divider
CMU PLL
To Transmitter Channel
rx_serial_data
From the x1
Clock Lines
Fractional
PLL
Receiver PMA Ch4
CDR
Receiver PCS Ch4
Deserializer
Parallel Clock
(Recovered)
Input
Reference
Clock
ATX
PLL
Parallel Clock
(from the
Clock Divider)
Central Clock Divider
Clock Divider
CMU PLL
rx_serial_data
To Transmitter Channel
Receiver PMA Ch3
CDR
Receiver PCS Ch3
Deserializer
Parallel Clock
(Recovered)
Input
Reference
Clock
Parallel Clock
(from the
Clock Divider)
Local Clock Divider
Clock Divider
CMU PLL
To Transmitter Channel
rx_serial_data
From the x1
Clock Lines
Receiver PMA Ch2
CDR
Receiver PCS Ch2
Deserializer
Parallel Clock
(Recovered)
Input
Reference
Clock
Parallel Clock
(from the
Clock Divider)
Local Clock Divider
Clock Divider
CMU PLL
To Transmitter Channel
rx_serial_data
From the x1
Clock Lines
Fractional
PLL
Receiver PMA Ch1
CDR
Receiver PCS Ch1
Deserializer
Parallel Clock
(Recovered)
Input
Reference
Clock
ATX
PLL
Parallel Clock
(from the
Clock Divider)
Central Clock Divider
Clock Divider
CMU PLL
To Transmitter Channel
rx_serial_data
From the x1
Clock Lines
Receiver PMA Ch0
CDR
Receiver PCS Ch0
Deserializer
Parallel Clock
(Recovered)
Input
Reference
Clock
Parallel Clock
(from the
Clock Divider)
Local Clock Divider
Clock Divider
CMU PLL
To Transmitter Channel
From the x1
Clock Lines
x1 Clock Lines
Altera Corporation
x6 Clock Lines
Both Parallel and Serial Clocks
Data Path
Serial Clock
Unused Resources
Parallel Clock
Receiver
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FPGA Fabric–Transceiver Interface Clocking
2-39
Related Information
• Transceiver Protocol Configurations in Arria V Devices
• Transceiver Custom Configurations in Arria V Devices
• Transceiver Configurations in Arria V GZ Devices
Information about the clocking scheme used in different configurations.
FPGA Fabric–Transceiver Interface Clocking
This section describes the clocking options available when the transceiver interfaces with the FPGA fabric.
The FPGA fabric–transceiver interface clocks can be subdivided into the following three categories:
• Input reference clocks—Can be an FPGA fabric–transceiver interface clock. This may occur when the
FPGA fabric-transceiver interface clock is forwarded to the FPGA fabric, where it can then clock logic.
Note: The input reference clock can only be routed into the FPGA fabric if a transceiver is also
instantiated.
• Transceiver datapath interface clocks—Used to transfer data, control, and status signals between the
FPGA fabric and the transceiver channels. The transceiver channel forwards the tx_clkout signal to the
FPGA fabric to clock the data and control signals into the transmitter. The transceiver channel also
forwards the recovered rx_clkout clock (in configurations without the rate matcher) or the tx_clkout
clock (in configurations with the rate matcher) to the FPGA fabric to clock the data and status signals
from the receiver into the FPGA fabric.
• Other transceiver clocks—The following transceiver clocks form a part of the FPGA fabric–transceiver
interface clocks:
• phy_mgmt_clk—Avalon®-MM interface clock used for controlling the transceivers, dynamic
reconfiguration, and calibration
• fixed_clk—the 125 MHz fixed-rate clock used in the PCIe (PIPE) receiver detect circuitry
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FPGA Fabric–Transceiver Interface Clocking
Table 2-11: FPGA Fabric–Transceiver Interface Clocks
Clock Name
Clock Description
tx_pll_refclk, rx_cdr_
refclk
Input reference clock
used for clocking logic
in the FPGA fabric
tx_clkout, tx_pma_clkout
rx_clkout, rx_pma_clkout
Clock forwarded by
the transceiver for
clocking the
transceiver datapath
interface
Interface Direction
FPGA Fabric Clock Resource
Utilization
Transceiver-to-FPGA
fabric
Clock forwarded by
the receiver for
clocking the receiver
datapath interface
tx_coreclkin
User-selected clock for
clocking the transmitter
datapath interface
rx_coreclkin
User-selected clock
for clocking the
receiver datapath
interface
GCLK, RCLK, PCLK
FPGA fabric-totransceiver
PCIe receiver detect
clock
fixed_clk
(29)
phy_mgmt_clk
Avalon-MM
interface
management clock
Note: • For Arria V GZ devices, you can forward the pll_refclk, tx_clkout, and rx_clkout clocks
to a fractional PLL so that the fractional PLL can synthesize a clock for the FPGA logic. A second
fractional PLL can be reached by periphery clocks, depending on your device and channel
placement, and may require using a RGCLK or GCLK.
• For more information about the GCLK, RCLK, and PCLK resources available in each device, refer
to the Clock Networks and PLLs in Arria V Devices chapter
Table 2-12: Configuration Specific Port Names for tx_clkout and rx_clkout
(29)
(30)
Configuration
Port Name for tx_clkout
Port Name for rx_clkout
Custom
tx_clkout
rx_clkout
Native - 10G PCS(30)
tx_10g_clkout
rx_10g_clkout
The phy_mgmt_clk is a free-running clock that is not derived from the transceiver blocks.
Available for Arria V GZ devices only.
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Configuration
Port Name for tx_clkout
Port Name for rx_clkout
Native - Standard PCS
tx_std_clkout
rx_std_clkout
Native - PMA Direct
tx_pma_clkout
rx_pma_clkout
Interlaken (30)
tx_clkout
rx_clkout
Low Latency
tx_clkout
rx_clkout
PCIe
pipe_pclk
pipe_pclk
XAUI
xgmii_tx_clk
xgmii_rx_clk
2-41
Related Information
Clock Networks and PLLs in Arria V Devices chapter
Transceiver Datapath Interface Clocking
There are two types of design considerations for clock optimization when interfacing the transceiver datapath
to the FPGA fabric:
• PCS with FIFO in phase compensation mode – share clock network for identical channels
• PCS with FIFO in registered mode or PMA direct mode – refer to AN580: Achieving Timing Closure in
Basic (PMA Direct) Functional Mode for additional timing closure techniques between transceiver and
FPGA fabric
Note: For Arria V (GX, GT, ST and SX) devices, the PMA clock for channel 1 and channel 2 of GXB_L0
and GXB_R0 cannot be routed out of the FPGA fabric.
Related Information
AN580: Achieving Timing Closure in Basic (PMA Direct) Functional Mode
Transmitter Datapath Interface Clocking
In 6-Gbps transceivers, the write side of the transmitter phase compensation FIFO makes up the transmitter
datapath interface.
For the 6-Gbps transceivers, the write side of the transmitter phase compensation FIFO makes up the
transmitter datapath interface. This interface is clocked with the transmitter datapath interface clock.
The following figure shows the 6-Gbps transmitter datapath interface clocking. The transmitter PCS forwards
the following clocks to the FPGA fabric:
• tx_clkout—for each transmitter channel in a non-bonded configuration
• tx_clkout[0]—for all transmitter channels in a bonded configuration
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Quartus II-Software Selected Transmitter Datapath Interface Clock
Figure 2-34: Transmitter Datapath Interface Clocking for 6-Gbps Transceivers
Transmitter PCS
Transmitter Data
FPGA Fabric
TX
Phase
Compensation
FIFO
tx_coreclkin
(User Selected Clock)
Transmitter Data
tx_clkout
(Quartus II Selected Clock)
tx_clkout
Parallel Clock
All configurations that use the PCS channel must have a 0 parts per million (ppm) difference between write
and read clocks of the transmitter phase compensation FIFO.
For the 10-Gbps transceivers Arria V GT/ST devices, there are no PCS blocks. The only transmit datapath
available is a direct connection from the FPGA fabric to the serializer of the transmitter PMA.
The following figure shows the 10-Gbps transmitter datapath interface clocking. For each transmitter channel
in a non-bonded configuration, the FPGA fabric forwards the following tx_clkout clock to the transmitter
PMA.
Figure 2-35: Transmitter Datapath Interface Clocking for 10-Gbps Transceivers (for Arria V GT/ST Devices)
Transmitter PMA
Transmitter PCS (Unavailable)
FPGA Fabric
Transmitter Data
Serializer
Parallel Clock
tx_clkout
You can clock the transmitter datapath interface by one of the following options:
• The Quartus II-selected transmitter datapath interface clock
• The user-selected transmitter datapath interface clock
Note: To reduce GCLK, RCLK, and PCLK resource utilization in your design, you can select the userselection option to share the transceiver datapath interface clocks.
Related Information
• Transceiver Custom Configurations in Arria V Devices.
• Transceiver Protocol Configurations in Arria V Devices.
Information about interface clocking for each configuration.
Quartus II-Software Selected Transmitter Datapath Interface Clock
The Quartus II software automatically picks the appropriate clock from the FPGA fabric to clock the
transmitter datapath interface.
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2-43
Figure 2-36: 6-Gbps Transmitter Datapath Interface Clocking for Non-Bonded Channels
The figure shows the transmitter datapath interface of two 6 Gbps transceiver non-bonded channels clocked
by their respective transmitter PCS clocks which are forwarded to the FPGA fabric.
Channel 1
FPGA Fabric
Transmitter Data
TX
Phase
Compensation
FIFO
Transmitter Data
Channel 1 Transmitter
Data and Control Logic
tx_coreclkin[1]
Parallel Clock
tx_clkout[1]
Channel 0
Transmitter Data
TX
Phase
Compensation
FIFO
Transmitter Data
Channel 0 Transmitter
Data and Control Logic
tx_coreclkin[0]
Parallel Clock
tx_clkout[0]
Figure 2-37: Arria V GT/ST 10-Gbps Transmitter Datapath Interface Clocking for Non-Bonded Channels
The figure shows the Arria V GT/ST transmitter datapath interface of two 10-Gbps transceiver non-bonded
channels clocked by their respective transmitter PMA clocks, which are forwarded to the FPGA fabric.
Transmitter PMA
Ch1
PCS Ch1 Unavailable
Transmitter Data
Serializer
Serializer
Parallel Clock
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Channel 1 Transmitter
Data and Control Logic
tx_clkout[1]
Parallel Clock
Transmitter PMA
Ch0
FPGA Fabric
PCS Ch0 Unavailable
Transmitter Data
Channel 0 Transmitter
Data and Control Logic
tx_clkout[0]
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Selecting a Transmitter Datapath Interface Clock
Figure 2-38: 6-Gbps Transmitter Datapath Interface Clocking for Three Bonded Channels
The following figure shows the 6-Gbps transmitter datapath interface of three bonded channels clocked by
the tx_clkout[0] clock. The tx_clkout[0] clock is derived from the central clock divider of channel 1 or
4 in a transceiver bank.
Channel 2
FPGA Fabric
Transmitter Data
TX
Phase
Compensation
FIFO
Transmitter Data
Channel 2 Transmitter
Data and Control Logic
tx_coreclkin[2]
Parallel Clock
Channel 1
Transmitter Data
TX
Phase
Compensation
FIFO
Transmitter Data
Channel 1 Transmitter
Data and Control Logic
tx_coreclkin[1]
tx_clkout[0]
Parallel Clock
Channel 0
Transmitter Data
TX
Phase
Compensation
FIFO
Transmitter Data
Channel 0 Transmitter
Data and Control Logic
tx_coreclkin[0]
Parallel Clock
Selecting a Transmitter Datapath Interface Clock
Multiple non-bonded transmitter channels use a large portion of GCLK, RCLK, and PCLK resources.
Selecting a common clock driver for the transmitter datapath interface of all identical transmitter channels
saves clock resources.
Multiple transmitter channels that are non-bonded lead to high utilization of GCLK, RCLK, and PCLK
resources (one clock resource per channel). You can significantly reduce GCLK, RCLK, and PCLK resource
use for transmitter datapath clocks if the transmitter channels are identical.
Note: Identical transmitter channels have the same input reference clock source, transmit PLL configuration,
transmitter PMA, and PCS configuration, but may have different analog settings, such as transmitter
voltage output differential (VOD), transmitter common-mode voltage (VCM), or pre-emphasis.
To achieve the clock resource savings, select a common clock driver for the transmitter datapath interface
of all identical transmitter channels. The following figure shows eight identical channels clocked by a single
clock (tx_clkout of channel 4).
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2-45
Figure 2-39: Eight Identical Channels with a Single User-Selected Transmitter Interface Clock
Transceivers
FPGA Fabric
tx_coreclkin[7]
Channel 7
tx_coreclkin[6]
Channel 6
tx_coreclkin[5]
Channel 5
tx_coreclkin[4]
Channel 4
Channel [7:0] Transmitter
Data and Control Logic
tx_clkout[4]
tx_coreclkin[3]
Channel 3
tx_coreclkin[2]
Channel 2
tx_coreclkin[1]
Channel 1
tx_coreclkin[0]
Channel 0
To clock eight identical channels with a single clock, perform these steps:
1. Instantiate the tx_coreclkin port for all the identical transmitter channels (tx_coreclkin[7:0]).
2. Connect tx_clkout[4] to the tx_coreclkin[7:0] ports.
3. Connect tx_clkout[4] to the transmitter data and control logic for all eight channels.
Note: Resetting or powering down channel 4 causes a loss of the clock for all eight channels.
The common clock must have a 0 ppm difference for the read side of the transmitter phase compensation
FIFO of all the identical channels. A frequency difference causes the FIFO to under run or overflow, depending
on whether the common clock is slower or faster, respectively.
You can drive the 0 ppm common clock by one of the following sources:
• tx_clkout of any channel in non-bonded channel configurations
• tx_clkout[0] in bonded channel configurations
• Dedicated refclk pins
Note: The Quartus II software does not allow gated clocks or clocks that are generated in the FPGA logic
to drive the tx_coreclkin ports.
You must ensure a 0 ppm difference. The Quartus II software is unable to ensure a 0 ppm difference because
it allows you to use external pins, such as dedicated refclk pins.
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Receiver Datapath Interface Clock
Receiver Datapath Interface Clock
The 6-Gbps receiver datapath interface is comprised of the read side RX phase compensation FIFO.
The read side of the RX phase compensation FIFO makes up the 6-Gbps receiver datapath interface. The
receiver datapath interface clock clocks this interface. The receiver PCS forwards the following clocks to the
FPGA fabric:
• rx_clkout—for each receiver channel in a non-bonded configuration when you do not use a rate matcher
• tx_clkout—for each receiver channel in a non-bonded configuration when you use a rate matcher
• single rx_clkout[0]—for all receiver channels in a bonded configuration
Figure 2-40: 6-Gbps Receiver Datapath Interface Clocking
FPGA Fabric
Receiver PCS
Receiver Data
RX
Phase
Compensation
FIFO
rx_coreclkin
(User Selected Clock)
Receiver Data
rx_clkout/tx_clkout
(Quartus II Selected Clock)
Parallel Clock (Recovered Clock)
rx_clkout
All configurations that use the PCS channel must have a 0 ppm difference between the receiver datapath
interface clock and the read side clock of the RX phase compensation FIFO.
For the 10-Gbps transceivers in Arria V GT/ST devices, there are no PCS blocks. The only receiver datapath
available is a direct connection from the receiver PMA deserializer to the FPGA fabric.
For each receiver channel in a non-bonded configuration, the receiver PMA forwards the rx_clkout clock
to the FPGA fabric.
Figure 2-41: Arria V GT/ST 10-Gbps Receiver Datapath Interface Clocking
Receiver PMA
Deserializer
Receiver PCS Unavailable
FPGA Fabric
Receiver Data
Parallel Clock (Recovered Clock)
rx_clkout
Note: For more information about interface clocking for each configuration, refer to the Transceiver Custom
Configuration in Arria V Devices and Transceiver Protocol Configurations in Arria V Devices
chapters.
You can clock the receiver datapath interface by one of the following options:
• The Quartus II-selected receiver datapath interface clock
• The user-selected receiver datapath interface clock
Note: To reduce GCLK, RCLK, and PCLK resource utilization in your design, you can select the userselection option to share the transceiver datapath interface clocks.
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Quartus II Software-Selected Receiver Datapath Interface Clock
2-47
Related Information
• Transceiver Custom Configurations in Arria V Devices
• Transceiver Protocol Configurations in Arria V Devices
Quartus II Software-Selected Receiver Datapath Interface Clock
Quartus II automatically picks the appropriate clock from the FPGA fabric to clock the receiver datapath
interface.
Figure 2-42: 6-Gbps Receiver Datapath Interface Clocking for Non-Bonded Channels
The figure shows receiver datapath interface of two 6-Gbps transceiver non-bonded channels clocked by
their respective receiver PCS clocks, which are forwarded to the FPGA fabric.
Channel 1
FPGA Fabric
RX
Phase
Compensation
FIFO
Receiver Data
Receiver Data
Channel 1 Receiver
Data and Status Logic
rx_coreclkin[1]
Parallel Clock (Recovered Clock)
rx_clkout[1]/tx_clkout[1] (1)
Channel 0
RX
Phase
Compensation
FIFO
Receiver Data
Receiver Data
Channel 0 Receiver
Data and Status Logic
rx_coreclkin[0]
Parallel Clock (Recovered Clock)
rx_clkout[0]/tx_clkout[0] (1)
Note: (1) If you use a rate matcher, the tx_clkout clock is used.
Figure 2-43: Arria V GT/ST 10-Gbps Receiver Datapath Interface Clocking for Non-Bonded Channels
The figure shows Arria V GT/ST receiver datapath interface of two 10-Gbps transceiver non-bonded channels
clocked by their respective receiver CDR recovered PMA clocks, which are forwarded to the FPGA fabric.
Receiver PMA Ch1
PCS Ch1 Unavailable
Receiver Data
Deserializer
Deserializer
Parallel Clock (Recovered Clock)
Transceiver Clocking in Arria V Devices
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Channel 1 Receiver
Data and Status Logic
rx_clkout[1]
Parallel Clock (Recovered Clock)
Receiver PMA Ch0
FPGA Fabric
PCS Ch0 Unavailable
Receiver Data
Channel 0 Receiver
Data and Status Logic
rx_clkout[0]
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Selecting a Receiver Datapath Interface Clock
Figure 2-44: 6-Gbps Receiver Datapath Interface Clocking for Three Bonded Channels
The figure shows the 6-Gbps receiver datapath interface of three bonded channels clocked by the
rx_clkout[0] clock. The rx_clkout[0] clock is derived from the central clock divider of channel 1 or 4 in
a transceiver bank.
Channel 2
FPGA Fabric
Receiver Data
RX
Phase
Compensation
FIFO rdclk
wrclk
Receiver Data
Channel 2 Receiver
Data and Status Logic
rx_coreclkin[2]
Low Speed Parallel Clock from 6-Gbps
Channel CMU1 or CMU4 Clock Divider
Channel 1
Receiver Data
RX
Phase
Compensation
FIFO
wrclk
Receiver Data
Channel 1 Receiver
Data and Status Logic
rdclk
rx_coreclkin[1]
Low Speed Parallel Clock from 6-Gbps
Channel CMU1 or CMU4 Clock Divider
rx_clkout[0]
Channel 0
Receiver Data
RX
Phase
Compensation
FIFO
wrclk
Receiver Data
Channel 0 Receiver
Data and Status Logic
rdclk
rx_coreclkin[0]
Low Speed Parallel Clock from 6-Gbps
Channel CMU1 or CMU4 Clock Divider
Selecting a Receiver Datapath Interface Clock
Multiple non-bonded receiver channels use a large portion of GCLK, RCLK, and PCLK resources. Selecting
a common clock driver for the receiver datapath interface of all identical receiver channels saves clock
resources.
Non-bonded multiple receiver channels lead to high utilization of GCLK, RCLK, and PCLK resources—one
clock resource per channel. You can significantly reduce GCLK, RCLK, and PCLK resource use for the
receiver datapath clocks if the receiver channels are identical.
Note: Identical receiver channels are defined as channels that have the same input reference clock source
for the CDR and the same receiver PMA and PCS configuration. These channels may have different
analog settings, such as receiver common mode voltage (VICM), equalization, or DC gain setting.
To achieve clock resource savings, select a common clock driver for the receiver datapath interface of all
identical receiver channels. To select a common clock driver, perform these steps:
1. Instantiate the rx_coreclkin port for all the identical receiver channels.
2. Connect the common clock driver to their receiver datapath interface, and receiver data and control
logic.
The following figure shows eight identical channels that are clocked by a single clock (rx_clkout of channel
4).
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Figure 2-45: Eight Identical Channels with a Single User-Selected Receiver Interface Clock
Receiver Standard PCS
FPGA Fabric
rx_coreclkin[7]
Channel 7
rx_coreclkin[6]
Channel 6
rx_coreclkin[5]
Channel 5
rx_coreclkin[4]
Channel 4
Channel [7:0] Receiver
Data and Control Logic
rx_clkout[4]
rx_coreclkin[3]
Channel 3
rx_coreclkin[2]
Channel 2
rx_coreclkin[1]
Channel 1
rx_coreclkin[0]
Channel 0
To clock eight identical channels with a single clock, perform these steps:
• Instantiate the rx_coreclkin port for all the identical receiver channels (rx_coreclkin[7:0]).
• Connect rx_clkout[4] to the rx_coreclkin[7:0] ports.
• Connect rx_clkout[4] to the receiver data and control logic for all eight channels.
Note: Resetting or powering down channel 4 leads to a loss of the clock for all eight channels.
The common clock must have a 0 ppm difference for the write side of the RX phase compensation FIFO of
all the identical channels. A frequency difference causes the FIFO to under run or overflow, depending on
whether the common clock is faster or slower, respectively.
You can drive the 0 ppm common clock driver from one of the following sources:
•
•
•
•
tx_clkout of any channel in non-bonded receiver channel configurations with the rate matcher
rx_clkout of any channel in non-bonded receiver channel configurations without the rate matcher
tx_clkout[0] in bonded receiver channel configurations
Dedicated refclk pins
Note: The Quartus II software does not allow gated clocks or clocks generated in the FPGA logic to drive
the rx_coreclkin ports.
Note: You must ensure a 0 ppm difference. The Quartus II software is unable to ensure a 0 ppm difference
because it allows you to use external pins, such as dedicated refclk pins.
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GXB 0 PPM Core Clock Assignment for GZ Devices
GXB 0 PPM Core Clock Assignment for GZ Devices
The common clock should have a 0 PPM difference with respect to the read side of the TX FIFO (in the 10G
PCS channel) or TX phase compensation FIFO (in the Standard PCS channel) of all the identical channels.
A frequency difference causes the FIFO to under-run or overflow, depending on whether the common clock
is slower or faster, respectively.
The 0 PPM common clock driver can be driven by one of the following sources:
•
•
•
•
tx_clkout in non-bonded channel configurations
tx_clkout[0] in bonded channel configurations
rx_clkout in non-bonded channel configurations
refclk when there is 0 PPM difference between refclk and tx_clkout
Table 2-13: 0 PPM Core Clock Settings
The following table lists the 0 PPM core clock settings that you make in the Quartus II Assignment Editor.
(31)
Assignments
To
Assignment Name
Value
Description
tx_dataout/rx_datain pins of all channels whose tx/rx_coreclk ports
are connected together and driven by the 0 PPM clock driver.
0 PPM coreclk setting
ON
Note: For more information about QSF assignments and how 0 PPM is used with various transceiver PHYs,
refer to the Altera Transceiver PHY IP Core User Guide.
Related Information
Altera Transceiver PHY IP Core User Guide
Document Revision History
The table below lists the revision history for this chapter.
(31)
You can find the full hierarchy name of the 0 PPM clock driver using the Node Finder feature in the Quartus
II Assignment Editor.
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Table 2-14: Document Revision History
Date
Version
Changes
March 2014
2014.03.07
• Updated the Table "Input Reference Clock Sources ".
• Updated the Figure "Input Reference Clock Source for CMU PLL
Driving Channels with Serial Data Rates Beyond 6.5536 Gbps.
• Updated the Table " Characteristics of x1, x6, and xN Clock Lines"".
• Updated the Figure "Four Bonded Transmitter Channels Driven
by fPLL using x6 Clock Line Within a Transceiver Bank" to indicate
that when fPLL is used as a transmit PLL, all transceiver channels
need to be placed in one transceiver bank.
• Updated the tables "Clock Path for Non-Bonded Configurations"
and "Clock Path for Bonded Configurations".
• Corrected an error in the "Quartus II-Software Selected
Transmitter Datapath Interface Clock" section.
October 2013
2013.10.18
• Updated "Input Reference Clocking" section.
May 2013
2013.05.06
• Updated for Quartus II software version 13.0 feature support.
• Updated "Input Reference Clocking" section for Arria V GZ
devices.
• Updated "Internal Clocking" section for Arria V GZ devices.
• Updated "FPGA Fabric Transceiver Interface Clocking" section
for Arria V GZ devices.
• Added link to the known document issues in the Knowledge Base.
March 2013
2013.03.15
• Updated Table 2-1: Input Reference Clock Sources
• Updated Table 2-4: Characteristics of x1, x6, and xN Clock Lines
• Updated Figure 2-8: x1 Clock Line Architecture (more than 6.5536
Gbps)
• Updated "Transmitter Clock Network".
November 2012
2012.11.19
• Reorganized content and updated template.
• Updated for the Quartus II software version 12.1.
June 2012
1.2
• Updated for the Quartus II software version 12.0.
• Added basic clocking information from obsoleted “basics” chapter.
November 2011
1.1
Updated chapter for clarity and Quartus II software version 11.1.
August 2011
1.0
Initial release.
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Altera’s recommended reset sequence ensures that both the physical coding sublayer (PCS) and physical
medium attachment (PMA) in each transceiver channel are initialized and functioning correctly.
There are multiple reset options available to reset the analog and digital portions of the transmitter and
receiver.
Table 3-1: Available Reset Options
Transceiver PHY IP Core
Embedded Reset
Controller
User-Coded Reset Transceiver PHY
Controller
Reset Controller IP
Avalon Memory-Mapped
Reset Registers
XAUI
X
X
PCIe
X
X
10GBASE-R
X
X
X
X
Interlaken
For Arria V GZ
Custom
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Low Latency
For Arria V GZ
Deterministic Latency
Native PHY
Related Information
• Arria V Device Handbook: Known Issues
Lists the planned updates to the Arria V Device Handbook chapters.
• Altera Transceiver PHY IP Core User Guide
© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words
and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other
words and logos identified as trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with
Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes
no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
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9001:2008
Registered
3-2
PHY IP Embedded Reset Controller
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PHY IP Embedded Reset Controller
The embedded reset controller in the PHY IP enables you to initialize the transceiver physical coding sublayer
(PCS) and physical medium attachment (PMA) blocks.
To simplify your transceiver-based design, the embedded reset controller provides an option that requires
only one control input to implement an automatic reset sequence. Only one embedded reset controller is
available for all the channels in a PHY IP instance.
The embedded reset controller automatically performs the entire transceiver reset sequence whenever the
phy_mgmt_clk_reset signal is triggered. In case of loss-of-link or loss-of-data, the embedded reset controller
asserts the appropriate reset signals. You must monitor tx_ready and rx_ready. A high on these status
signals indicates the transceiver is out of reset and ready for data transmission and reception.
Note: Deassert the mgmt_rst_reset signal of the transceiver reconfiguration controller at the same time
as phy_mgmt_clk_reset to start calibration.
Note: You must have a valid and stable ATX PLL reference clock before deasserting the phy_mgmt_clk_reset
and mgmt_rst_reset signals for successful ATX PLL calibration.
ATX PLLs are available in Arria V GZ devices.
Note: The PHY IP embedded reset controller is enabled by default in all transceiver PHY IP cores except
the Native PHY IP core.
Embedded Reset Controller Signals
The following figure shows the embedded reset controller and signals in the PHY IP instance. These signals
reset your transceiver when you use the embedded reset controller.
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Embedded Reset Controller Signals
Figure 3-1: Embedded Reset Controller
Transceiver PHY
Receiver
PCS
Transmitter
PCS
rx_digitalreset
Receiver
PMA
Transmitter
PMA
CDR
Transmitter
PLL
rx_is_lockedtodata
tx_digitalreset
pll_is_locked
pll_powerdown
tx_analogreset
rx_analogreset
tx_ready
phy_mgmt_clk
phy_mgmt_clk_reset
rx_ready
Embedded Reset Controller
pll_locked
rx_is_lockedtodata
rx_is_lockedtoref
reconfig_busy
PCS and PMA Control
and Status Register
Memory Map
Avalon-MM
Interface
Avalon-MM
PHY Management
S
reconfig_to_xcvr
Transceiver
Reconfiguration
Controller
S
reconfig_from_xcvr
M
mgmt_rst_reset
mgmt_clk_clk
Table 3-2: Embedded Reset Controller Reset Control and Status Signals
Signal Name
Signal
Description
phy_mgmt_clk
Control Input
Clock for the embedded reset controller.
phy_mgmt_clk_reset
Control Input
A high-to-low transition of this asynchronous reset
signal initiates the automatic reset sequence control.
Hold this signal high to keep the reset signals asserted.
tx_ready
Status Output
A continuous high on this signal indicates that the
transmitter (TX) channel is out of reset and is ready
for data transmission. This signal is synchronous to
phy_mgmt_clk.
rx_ready
Status Output
A continuous high on this signal indicates that the
receiver (RX) channel is out of reset and is ready for
data reception. This signal is synchronous to phy_
mgmt_clk.
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Signal Name
reconfig_busy
Signal
Status Output
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Description
An output from the Transceiver Reconfiguration
Controller block indicates the status of the dynamic
reconfiguration controller. At the first mgmt_clk_clk
clock cycle after power-up, reconfig_busy remains
low.
This signal is asserted from the second mgmt_clk_clk
clock cycle to indicate that the calibration process is
in progress . When the calibration process is
completed, the reconfig_busy signal is deasserted.
This signal is also routed ®to the embedded reset
controller by the Quartus II software by embedding
the signal in the reconfig_to_xcvr bus between the
PHY IP and the Transceiver Reconfiguration
Controller.
pll_locked
Status Output
This signal is asserted when the TX PLL achieves lock
to the input reference clock. When this signal is
asserted high, the embedded reset controller deasserts
the tx_digitalreset signal.
rx_is_lockedtodata
Status Output
This signal is an optional output status port. When
asserted, this signal indicates that the CDR is locked
to the RX data and the CDR has changed from lockto-reference (LTR) to lock-to-data (LTD) mode.
rx_is_lockedtoref
Status Output
This is an optional output status port. When asserted,
this signal indicates that the CDR is locked to the
reference clock.
mgmt_clk_clk
Clock
Clock for the Transceiver Reconfiguration Controller.
This clock must be stable before releasing mgmt_rst_
reset.
mgmt_rst_reset
Reset
Reset for the Transceiver Reconfiguration Controller
Resetting the Transceiver with the PHY IP Embedded Reset Controller during Device
Power-Up
Follow this reset sequence to ensure a reliable link initialization after the initial power-up.
The numbers in the following figure correspond to the following numbered list, which guides you through
the transceiver reset sequence during device power-up.
1. During device power-up, mgmt_rst_reset and phy_mgmt_clk_reset must be asserted to initialize the
reset sequence. phy_mgmt_clk_reset holds the transceiver blocks in reset and mgmt_rst_reset is required
to start the calibration IPs. Both these signals should be held asserted for a minimum of two phy_mgmt_clk
clock cycles. Deassert phy_mgmt_clk_reset at the same time as mgmt_rst_reset.
2. After the transmitter calibration and reset sequence are complete, the tx_ready status signal is asserted
and remains asserted to indicate that the transmitter is ready to transmit data.
3. After the receiver calibration and reset sequence are complete, the rx_ready status signal is asserted and
remains asserted to indicate that the receiver is ready to receive data.
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3-5
Note: If the tx_ready and rx_ready signals do not stay asserted, the reset sequence did
not complete successfully and the link will be down.
Figure 3-2: Reset Sequence Timing Diagram Using Embedded Reset Controller during Device
Power-Up
Control Signals
mgmt_rst_reset
1
phy_mgmt_clk_reset
1
tx_ready
rx_ready
2
3
Status Signals
reconfig_busy
pll_locked
rx_is_lockedtodata
Resetting the Transceiver with the PHY IP Embedded Reset Controller during Device
Operation
Follow this reset sequence to reset the entire transceiver at any point during the device operation, to
re-establishing a link, or after certain dynamic reconfigurations.
The numbers in the following figure correspond to the numbered list, which guides you through the
transceiver reset sequence during device operation.
1. Assert phy_mgmt_clk_reset for two phy_mgmt_clk clock cycles to re-start the entire transceiver reset
sequence.
2. After the transmitter reset sequence is complete, the tx_ready status signal is asserted and remains
asserted to indicate that the transmitter is ready to transmit data.
3. After the receiver reset sequence is complete, the rx_ready status signal is asserted and remains asserted
to indicate that the receiver is ready to receive data.
Note: If the tx_ready and rx_ready signals do not stay asserted, the reset sequence did
not complete successfully and the link will be down.
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User-Coded Reset Controller
Figure 3-3: Reset Sequence Timing Diagram Using Embedded Reset Controller during Device
Operation
Control Signals
phy_mgmt_clk_reset
tx_ready
rx_ready
1
2
3
Status Signals
reconfig_busy
pll_locked
rx_is_lockedtodata
Note: To reset the transmitter and receiver analog and digital blocks separately without
repeating the entire reset sequence, use the Avalon Memory Map registers.
User-Coded Reset Controller
You must implement external reset controller logic (user-coded reset controller) if you disable the embedded
reset controller to initialize the transceiver physical coding sublayer (PCS) and physical medium attachment
(PMA) blocks.
You can implement a user-coded reset controller with one of the following:
• Using your own Verilog/VHDL code to implement the reset sequence
• Using the Quartus II MegaWizard Plug-In Manager, which provides a ready-made reset controller IP to
place your own verilog/vhdl code
Note: You must disable the embedded reset controller before using the user-coded reset controller.
Note: The embedded reset controller can only be disabled for non-protocol transceiver PHY IPs, such as
custom PHY, low latency PHY and deterministic latency PHY. Native PHY IP does not have an
embedded reset controller, so you must implement your own reset logic.
If you implement your own reset controller, consider the following:
•
•
•
•
•
The user-coded reset controller must be level sensitive (active high)
The user-coded reset controller does not depend on phy_mgmt_clk_reset
You must provide a clock and reset to the reset controller logic
The internal signals of the PHY IP embedded reset controller are configured as ports
You can hold the transceiver channels in reset by asserting the appropriate reset control signals
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User-Coded Reset Controller Signals
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Note: You must have a valid and stable ATX PLL reference clock before deasserting the pll_powerdown
and mgmt_rst_reset signals for successful ATX PLL calibration.
ATX PLLs are available in Arria V GZ devices.
Related Information
"Transceiver PHY Reset Controller IP Core" chapter of the Altera Transceiver PHY IP Core User Guide.
For information about the transceiver PHY reset controller.
User-Coded Reset Controller Signals
Use the signals in the following figure and table with a user-coded reset controller.
Figure 3-4: Interaction Between the Transceiver PHY Instance, Transceiver Reconfiguration Controller, and
the User-Coded Reset Controller
User-Coded
Reset Controller
Transceiver PHY Instance
pll_powerdown
tx_digitalreset
tx_analogreset
clock
reset
rx_digitalreset
Receiver
PCS
Transmitter
PCS
rx_analogreset
Receiver
PMA
Transmitter
PMA
CDR
Transmitter
PLL
pll_locked
tx_cal_busy
rx_cal_busy
rx_is_lockedtoref
rx_is_lockedtodata
reconfig_from_xcvr
mgmt_rst_reset
mgmt_clk_clk
reconfig_to_xcvr
Transceiver
Reconfiguration
Controller
reconfig_busy
Table 3-3: Signals Used by the Transceiver PHY instance, Transceiver Reconfiguration Controller, and User-Coded
Reset Controller
Signal Name
Signal Type
Description
mgmt_clk_clk
Clock
Clock for the Transceiver Reconfiguration Controller.
This clock must be stable before releasing mgmt_rst_
reset.
mgmt_rst_reset
Reset
Reset for the Transceiver Reconfiguration Controller
pll_powerdown
Control
Resets the TX PLL when asserted high
tx_analogreset
Control
Resets the TX PMA when asserted high
tx_digitalreset
Control
Resets the TX PCS when asserted high
rx_analogreset
Control
Resets the RX PMA when asserted high
rx_digitalreset
Control
Resets the RX PCS when asserted high
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Signal Name
Signal Type
Description
reconfig_busy
Status
A high on this signal indicates that reconfiguration is
active
tx_cal_busy
Status
A high on this signal indicates that TX calibration is
active
rx_cal_busy
Status
A high on this signal indicates that RX calibration is
active
pll_locked
Status
A high on this signal indicates that the TX PLL is
locked
rx_is_lockedtoref
Status
A high on this signal indicates that the RX CDR is in
the lock to reference (LTR) mode
rx_is_lockedtodata
Status
A high on this signal indicates that the RX CDR is in
the lock to data (LTD) mode
Resetting the Transmitter with the User-Coded Reset Controller during Device Power-Up
Follow this reset sequence when designing your User-Coded Reset Controller to ensure a reliable transmitter
initialization after the initial power-up.
The numbers in the figure correspond to the following numbered list, which guides you through the
transmitter reset sequence during device power-up.
1. To reset the transmitter, begin with:
• Assert mgmt_rst_reset at power-up to start the calibration IPs. Hold mgmt_rst_reset active for a
minimum of two reset controller clock cycles.
• Assert and hold pll_powerdown, tx_analogreset, and tx_digitalreset at power-up to reset the
transmitter. You can deassert tx_analogreset at the same time as pll_powerdown.
• Assert pll_powerdown for a minimum duration of 1 μs (tpll_powerdown). If you use ATX PLL calibration
(available in Arria V GZ devices), deassert pll_powerdown before mgmt_rst_reset so that the ATX
PLL is not powered down during calibration. Otherwise, pll_powerdown can be deasserted anytime
after mgmt_rst_reset is deasserted.
• Make sure there is a stable reference clock to the PLL before deasserting pll_powerdown and
mgmt_rst_reset.
2. After the transmitter PLL locks, the pll_locked status gets asserted after tpll_lock.
3. After the transmitter calibration completes, the tx_cal_busy status is deasserted. Depending on the
transmitter calibrations, this could happen before or after the pll_locked is asserted.
4. Deassert tx_digitalreset after the gating conditions occur for a minimum duration of ttx_digitalreset.
The gating conditions are:
• pll_powerdown is deasserted
• pll_locked is asserted
• tx_cal_busy is deasserted
The transmitter is out of reset and ready for operation.
Note: During calibration, pll_locked might assert and deassert as the calibration IP runs.
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Figure 3-5: Reset Sequence Timing Diagram for Transmitter using the User-Coded Reset Controller
during Device Power-Up
mgmt_rst_reset
1
pll_powerdown
1
tx_analogreset
1
tx_digitalreset
1
4
pll_locked
tx_cal_busy
ttx_digitalreset min 20 ns
2
tpll_lock max 10 μs
3
Table 3-4: Guidelines for Resetting the PLL, TX PMA, and TX PCS
To Reset
PLL
You Must Reset
pll_powerdown
tx_analogreset
tx_digitalreset
TX PMA
tx_analogreset
tx_digitalreset
TX PCS
tx_digitalreset
Resetting the Transmitter with the User-Coded Reset Controller during Device Operation
Follow this reset sequence if you want to reset the PLL, or analog or digital blocks of the transmitter at any
point during device operation. This might be necessary for re-establishing a link or after certain dynamic
reconfigurations.
The numbers in the following figure correspond to the following numbered list, which guides you through
the transmitter reset sequence during device operation.
1. To reset the transmitter:
• Assert pll_powerdown, tx_analogreset and tx_digitalreset. tx_digitalreset must be asserted
every time pll_powerdown and tx_analogreset are asserted to reset the PCS blocks.
• Hold pll_powerdown asserted for a minimum duration of tpll_powerdown.
• Deassert tx_analogreset at the same time or after pll_powerdown is deasserted.
2. After the transmitter PLL locks, the pll_locked status is asserted after tpll_lock. While the TX PLL locks,
the pll_locked status signal may toggle. It is asserted after tpll_lock.
3. Deassert tx_digitalreset after a minimum duration of ttx_digitalreset, and after all the gating conditions
are removed:
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Resetting the Receiver with the User-Coded Reset Controller during Device Power-Up Configuration
• pll_powerdown is deasserted
• pll_locked is deasserted
• tx_cal_busy is deasserted
Figure 3-6: Reset Sequence Timing Diagram for Transmitter using the User-Coded Reset Controller
during Device Operation
mgmt_rst_reset
1
1
pll_powerdown
tpll_powerdown min 1 μs
tx_analogreset
1
tx_digitalreset
1
3
pll_locked
ttx_digitalreset min 20ns
2
tpll_lock max 10 μs
tx_cal_busy
Resetting the Receiver with the User-Coded Reset Controller during Device Power-Up
Configuration
Follow this reset sequence to ensure a reliable receiver initialization after the initial power-up.
The numbers in the following figure correspond to the following numbered list, which guides you through
the receiver reset sequence during device power-up.
1. Assert mgmt_rst_reset at power-up to start the calibration IPs. Hold mgmt_rst_reset active for a
minimum of two mgmt_clk_clock cycles. Hold rx_analogreset and rx_digitalreset active at powerup to hold the receiver in reset. You can deassert them after all the gating conditions are removed.
2. After the receiver calibration completes, the rx_cal_busy status is deasserted.
3. Deassert rx_analogreset after a minimum duration of trx_analogreset after rx_cal_busy is deasserted.
4. rx_is_lockedtodata is a status signal from the receiver CDR indicating that the CDR is in the lock to
data (LTD) mode. Ensure rx_is_lockedtodata is asserted and stays asserted for a minimum duration
of tLTD before deasserting rx_digitalreset. If rx_is_lockedtodata is asserted and toggles, you must
wait another additional tLTD duration before deasserting rx_digitalreset.
5. Deassert rx_digitalreset after a minimum duration of tLTD after rx_is_lockedtodata stays asserted.
Ensure rx_analogreset and rx_cal_busy are deasserted before deasserting rx_digitalreset.
The receiver is now out of reset and ready for operation.
Note: rx_is_lockedtodata might toggle when there is no data at the receiver
input.
Note: rx_is_lockedtoref is a don't care when rx_is_lockedtodata is
asserted.
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3-11
Note: rx_analogreset must always be followed by
rx_digitalreset.
Figure 3-7: Reset Sequence Timing Diagram for Receiver using the User-Coded Reset Controller
during Device Power-Up
mgmt_rst_reset
1
rx_analogreset
1
rx_digitalreset
1
3
trx_analogreset two clock cycles of the user reset control
5
tLTD
4
rx_is_lockedtodata
rx_cal_busy
2
Related Information
Transceiver Architecture in Arria V Devices
For information about CDR lock modes.
Resetting the Receiver with the User-Coded Reset Controller during Device Operation
Follow this reset sequence to reset the analog or digital blocks of the receiver at any point during the device
operation. This might be necessary for re-establishing a link or after certain dynamic reconfigurations.
The numbers in the following figure correspond to the following numbered list, which guides you through
the receiver reset sequence during device operation.
1. Assert rx_analogreset and rx_digitalreset at any point independently. However, you must assert
rx_digitalreset every time rx_analogreset is asserted to reset the PCS blocks.
2. Deassert rx_analogreset after a minimum duration of 40 ns (trx_analogreset).
3. rx_is_lockedtodata is a status signal from the receiver CDR that indicates that the CDR is in the lock
to data (LTD) mode. Ensure rx_is_lockedtodata is asserted and stays asserted before deasserting
rx_digitalreset.
4. Deassert rx_digitalreset after a minimum duration of tLTD after rx_is_lockedtodata stays asserted.
Ensure rx_analogreset is deasserted.
Note: rx_is_lockedtodata might toggle when there is no data at the receiver input.
rx_is_lockedtoref is a don't care when rx_is_lockedtodata is asserted.
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Figure 3-8: Reset Sequence Timing Diagram for Receiver using the User-Coded Reset Controller
during Device Operation
mgmt_rst_reset
2
rx_analogreset
1
rx_digitalreset
1
trx_analogreset two clock cycles of user control reset
4
tLTD
3
rx_is_lockedtodata
rx_cal_busy
Related Information
Transceiver Architecture in Arria V Devices
For information about CDR lock modes.
Transceiver Reset Using Avalon Memory Map Registers
You can use Memory Map registers within the PHY IP instance to control the reset signals through the
Avalon Memory Map interface.
This gives the flexibility of resetting the PLL, and transmitter and receiver analog and digital blocks separately
without repeating the entire reset sequence.
Transceiver Reset Control Signals Using Avalon Memory Map Registers
The following table lists the memory map registers for CDR lock mode and channel reset. These signals
help you reset your transceiver when you use Memory Map registers within the PHY IP.
Table 3-5: Transceiver Reset Control Using Memory Map Registers
Register Name
Description
pma_rx_set_locktodata
This register is for CDR manual lock mode only. When you set
the register to high, the RX CDR PLL is in the lock to data (LTD)
mode. The default is low when both registers have the CDR in
auto lock mode.
pma_rx_set_locktoref
This register is for CDR manual lock mode only. When you set
the register to high, the RX CDR PLL is in the lock to reference
(LTR) mode if pma_rx_set_lockedtodata is not asserted. The
default is low when both registers have the CDR in auto lock
mode.
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Register Name
3-13
Description
reset_tx_digital
When you set this register to high, the tx_digitalreset signal
is asserted in every channel that is enabled for reset control
through the reset_ch_bitmask register. To deassert the tx_
digitalreset signal, set the reset_tx_digital register to 0.
reset_rx_analog
When you set this register to high, the rx_analogreset signal
is asserted in every channel that is enabled for reset control
through the reset_ch_bitmask register. To deassert the rx_
analogreset signal, set the reset_rx_analog register to 0.
reset_rx_digital
When you set this register to high, the rx_digitalreset signal
is asserted in every channel that is enabled for reset control
through the reset_ch_bitmask register. To deassert the rx_
digitalreset signal, set the reset_rx_digital register to 0.
reset_ch_bitmask
The registers provide an option to enable or disable certain
channels in a PHY IP instance for reset control. By default, all
channels in a PHY IP instance are enabled for reset control.
pll_powerdown
When asserted, the TX phase-locked loop (PLL) is turned off.
Related Information
Altera Transceiver PHY IP Core User Guide
For information about register addresses.
Resetting the Transceiver in CDR Manual Lock Mode
You can use the clock data recovery (CDR) manual lock mode to override the default CDR automatic lock
mode depending on your design requirements. The two control signals to enable and control the CDR in
manual lock mode are rx_set_locktoref and rx_set_locktodata. Follow this sequence to reset your
transceiver when the CDR is in manual lock mode.
Control Settings for CDR Manual Lock Mode
Use the following control settings to set the CDR lock mode:
Table 3-6: Control Settings for the CDR in Manual Lock Mode
rx_set_locktoref
rx_set_locktodata
CDR Lock Mode
0
0
Automatic
1
0
Manual-RX CDR LTR
X
1
Manual-RX CDR LTD
Resetting the Transceiver in CDR Manual Lock Mode
You can use the clock data recovery (CDR) manual lock mode to override the default CDR automatic lock
mode depending on your design requirements. The two control signals to enable and control the CDR in
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manual lock mode are rx_set_locktoref and rx_set_locktodata. Follow this sequence to reset your
transceiver when the CDR is in manual lock mode.
The numbers in the following figure correspond to the numbered list, which guides you through the steps
to put the CDR in manual lock mode.
1. Make sure that the calibration is complete (rx_cal_busy is low) and the transceiver goes through the
initial reset sequence. The rx_digitalreset and rx_analogreset signals should be low. The
rx_is_lockedtoref is a don't care and can be either high or low. The rx_is_lockedtodata and rx_ready
signals should be high, indicating that the transceiver is out of reset. Alternatively, you can start directly
with the CDR in manual lock mode after the calibration is complete.
2. Assert the rx_set_locktoref signal high to switch the CDR to the lock-to-reference mode. The
rx_is_lockedtodata status signal is deasserted. Assert the rx_digitalreset signal high at the same
time or after rx_set_lockedtoref is asserted if you use the user-coded reset. When the Transceiver
PHY reset controller is used, the rx_digitalreset is automatically asserted.
3. After the rx_digitalreset signal gets asserted, the rx_ready status signal is deasserted.
4. Assert the rx_set_locktodata signal high after tLTR_LTD_manual to switch the CDR to the lock-to-data
mode. The rx_is_lockedtodata status signal gets asserted, which indicates that the CDR is now set to
LTD mode. The rx_is_lockedtoref status signal can be a high or low and can be ignored.
5. Deassert the rx_digitalreset signal after tLTD_Manual.
6. After the rx_digitalreset signal is deasserted, the rx_ready status signal gets asserted if you are using
the Transceiver PHY Reset Controller, indicating that the receiver is now ready to receive data with the
CDR in manual mode.
Figure 3-9: Reset Sequence Timing Diagram for Transceiver when CDR is in Manual Lock Mode
Control Signals
tLTR_LTD_manual min 15 μs
2
rx_set_locktoref
4
rx_set_locktodata
rx_digitalreset
rx_analogreset
1
5
2
tLTD_Manual min 4 μs
1
Status Signals
rx_is_lockedtoref
1
rx_is_lockedtodata
1
rx_ready
1
2
4
6
3
Resetting the Transceiver During Dynamic Reconfiguration
Reset is required for transceiver during dynamic reconfiguration except in the PMA Analog Control
Reconfiguration mode.
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Guidelines for Dynamic Reconfiguration if Transmitter Duty Cycle Distortion Calibration is Required during
Device Operation
In general, follow these guidelines when dynamically reconfiguring the transceiver:
1. Hold the targeted channel and PLL in the reset state before dynamic reconfiguration starts.
2. Repeat the sequence as needed after dynamic reconfiguration is complete, which is indicated by
deassertion of the reconfig_busy, tx_cal_busy, rx_cal_busy signals.
Guidelines for Dynamic Reconfiguration if Transmitter Duty Cycle Distortion Calibration
is Required during Device Operation
If transmitter duty cycle distortion calibration is required during device operation, ensure the general
guidelines for transceiver dynamic reconfiguration are followed. Additionally, use the following
recommendations:
1. Do not connect tx_cal_busy to the transceiver Reset Controller IP.
2. Disable the embedded reset controller and use an external reset controller.
Note: If channel reconfiguration is required before TX DCD calibration, ensure the following:
• The TX PLL, TX channel, and Transceiver Reconfiguration Controller blocks must not be in
the reset state during TX DCD calibration. Ensure the following signals are not asserted during
TX DCD calibration:
•
•
•
•
pll_powerdown
tx_digitalreset
tx_analogreset
mgmt_rst_reset
Repeat the reset sequence when TX DCD calibration is complete.
Arria V GZ devices do not require channel reconfiguration before TX dynamic reconfiguration
calibration.
Note: Reset signals for the PMA are required only in PMA-direct mode.
Transceiver Blocks Affected by the Reset and Powerdown Signals
The following table lists blocks that are affected by specific reset and powerdown signals.
Table 3-7: Transceiver Blocks Affected
Transceiver Block
pll_
powerdown
rx_digitalreset
rx_analogreset tx_digitalreset
tx_analogreset
PLL
CMU PLL
Yes
—
—
—
—
ATX PLL for Arria V GZ
Yes
—
—
—
—
—
—
Receiver Standard PCS
Receiver Word Aligner
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—
Yes
—
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Transceiver Blocks Affected by the Reset and Powerdown Signals
pll_
powerdown
rx_digitalreset
Receiver Deskew FIFO
—
Yes
—
—
—
Receiver Rate Match FIFO
—
Yes
—
—
—
Receiver 8B/10B Decoder
—
Yes
—
—
—
Receiver Byte Deserializer
—
Yes
—
—
—
Receiver Byte Ordering
—
Yes
—
—
—
Receiver Phase Compensation FIFO
—
Yes
—
—
—
Transceiver Block
rx_analogreset tx_digitalreset
tx_analogreset
Receiver 10G PCS in Arria V GZ Devices
Receiver Gear Box
—
Yes
—
—
—
Receiver Block Synchronizer
—
Yes
—
—
—
Receiver Disparity Checker
—
Yes
—
—
—
Receiver Descrambler
—
Yes
—
—
—
Receiver Frame Sync
—
Yes
—
—
—
Receiver 64B/66B Decoder
—
Yes
—
—
—
Receiver CRC32 Checker
—
Yes
—
—
—
Receiver FIFO
—
Yes
—
—
—
Receiver PMA
Receiver Buffer
—
—
Yes
—
—
Receiver CDR
—
—
Yes
—
—
Receiver Deserializer
—
—
Yes
—
—
Transmitter Standard PCS
Transmitter Phase
Compensation FIFO
—
—
—
Yes
—
Byte Serializer
—
—
—
Yes
—
8B/10B Encoder
—
—
—
Yes
—
Transmitter Bit-Slip
—
—
—
Yes
—
Transmitter 10G PCS in Arria V GZ Devices
Transmitter FIFO
—
—
—
Yes
—
Transmitter Frame
Generator
—
—
—
Yes
—
Transmitter CRC32
Generator
—
—
—
Yes
—
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Transceiver Power-Down
pll_
powerdown
rx_digitalreset
Transmitter 64B/66B
Encoder
—
—
—
Yes
—
Transmitter Scrambler
—
—
—
Yes
—
Transmitter Disparity
Generator
—
—
—
Yes
—
Transmitter Gear Box
—
—
—
Yes
—
Transceiver Block
rx_analogreset tx_digitalreset
tx_analogreset
Transmitter PMA
Transmitter CGB
—
—
—
—
Yes
Serializer
—
—
—
—
Yes
Transmitter Buffer
—
—
—
—
Yes
Transceiver Power-Down
To maximize power savings, enable PMA hard power-down across all channels on a side of the device where
you do not use the transceivers.
The hard power-down granularity control of the transceiver PMA is per side (Arria V GX & Arria V GT)
or per transceiver bank (Arria V GZ). To enable PMA hard power-down on the left or right side of the
device, ground the transceiver power supply of the respective side.
Related Information
• Arria V Device Datasheet
For information about the transceiver power supply operating conditions of Arria V devices.
• Arria V Device Family Pin Connection Guidelines
Document Revision History
Date
Version
Changes
March 2014
2014.03.07
• Changed "User-Controlled Reset Controller" term to
"User-Coded Reset Controller".
• Updated the "Resetting the Transceiver in CDR Manual
Lock Mode" section.
May 2013
2013.05.06
• Updated the guidelines for Dynamic Reconfiguration
if TX DCD Calibration is required during device
operation
• Added link to the known document issues in the
Knowledge Base.
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Document Revision History
Date
Version
Changes
November 2012
2012.11.19
• Rewritten and reorganized content, and updated
template
• Updated reset sequence procedures
• Included sequences for resetting transceiver during
device operation
• Included information for Arria V GZ transceiver reset
June 2012
1.2
• Added “User-Controlled Reset Controller” section.
• Updated Figure 3–1 and Table 3–1.
November 2011
1.1
• Updated all figures and tables.
• Reorganized and updated the “Transceiver Reset
Sequence” section.
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Transceiver Protocol Configurations in Arria V
Devices
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The dedicated transceiver physical coding sublayer (PCS) and physical medium attachment (PMA) circuitry
supports the following communication protocols.
Table 4-1: Transceiver PCS Features for Arria V Devices
PCS Support
(32)
Data Rates (Gbps)
Transmitter Datapath
Receiver Datapath
PCI Express® (PCIe®) Gen1 2.5 (Gen1), 5 (Gen2) The same as custom
(x1, x2, x4, and x8) and Gen2
single- and double(x1, x2, x4, and x8)
width modes, plus the
PHY interface for PCI
Express (PIPE) 2.0
interface to the core
logic
The same as custom singleand double-width modes, plus
the rate match FIFO and PIPE
2.0 interface to the core logic
Gbps Ethernet (GbE)
The same as custom singleand double-width modes, plus
the rate match FIFO
1.25, 3.125
The same as custom
single- and doublewidth modes
Serial Digital Interface (SDI) 0.27(32), 1.485, and
2.97
Phase compensation Phase compensation FIFO and
FIFO and byte
byte deserializer
serializer
SATA
Phase compensation Phase compensation FIFO,
FIFO, byte serializer, byte deserializer, word aligner,
and 8B/10B encoder and 8B/10B decoder
1.5, 3.0, and 6.0
The 0.27 gigabits per second (Gbps) data rate is supported using oversampling user logic that must be
implemented by the user in the FPGA core.
© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words
and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other
words and logos identified as trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with
Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes
no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
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PCI Express
PCS Support
Data Rates (Gbps)
Transmitter Datapath
Receiver Datapath
The same as custom singleand double-width modes, plus
the receiver (RX) deterministic
latency
Common Public Radio
Interface (CPRI)
The same as custom
0.6144, 1.2288,
2.4576, 3.072, 4.9152, single- and doublewidth modes, plus the
6.144, 9.8304(33)
transmitter (TX)
deterministic latency
OBSAI
0.768, 1.536, 3.072,
6.144
The same as custom The same as custom singlesingle- and double- and double-width modes, plus
width modes, plus the the RX deterministic latency
TX deterministic
latency
Serial RapidIO ® (SRIO)
1.25, 2.5, 3.125
The same as custom
single- and doublewidth modes
The same as custom singleand double-width modes
XAUI
3.125
Implemented using
soft PCS
Implemented using soft PCS
10GBASE-R
10.3125
Implemented using
soft PCS
Implemented using soft PCS
Related Information
• Arria V Device Handbook: Known Issues
Lists the planned updates to the Arria V Device Handbook chapters.
• Use this chapter along with the Altera Transceiver PHY IP Core User Guide.
• Upcoming Arria V Device Features
PCI Express
The Arria Vdevices have PCIe Hard IP that is designed for performance, ease-of-use, and increased
functionality. The Hard IP consists of the media access control (MAC) lane, data link, and transaction layers.
The PCIe Hard IP supports the PCIe Gen1 end point and root port up to x8 lane configurations. The PCIe
endpoint support includes multifunction support for up to eight functions and Gen2 x4 lane configurations.
(33)
The 9.8304 Gbps CPRI implementation (supported with 10-Gbps channels only) is implemented using PMA
Direct mode. The PMA interfaces with the FPGA fabric directly, so you must implement the required PCS
functionality in user logic (soft PCS).
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PIPE Transceiver Datapath
4-3
Figure 4-1: PCIe Multifunction for Arria V Devices
External System
PCIe Link
Local
Peripheral 2
ATA
USB
Bridge
to PCIe
Local
Peripheral 1
GbE
CAN
Root
Complex
PCIe EP
PCIe RP
Memory
Controller
SPI
GPIO
Host CPU
I ²C
FPGA Device
The Arria V PCIe Hard IP operates independently from the core logic, which allows the PCIe link to wake
up and complete link training in less than 100 ms while the Arria V device completes loading the programming
file for the rest of the device.
In addition, the Arria V device PCIe Hard IP has improved end-to-end datapath protection using error
correction code (ECC).
PIPE Transceiver Datapath
Figure 4-2: Transceivers in a PCIe Hard IP Configuration
The PCIe Gen2 is supported only through the PCS–hard IP interface.
Functional Mode
Data Rate (Gbps)
PIPE
2.5 for Gen1
Number of Bonded Channels
x1, x2, x4, x8
PMA–PCS Interface Width
Word Aligner (Pattern)
10-Bit
Automatic Synchronization
State Machine (/K28.5+/K28.5-/)
8B/10B Encoder/Decoder
Enabled
Rate Match FIFO
Enabled
PCIe Hard IP
Byte SERDES
PCS–Hard IP or
PCS–FPGA Fabric Interface Width
(Per lane)
PCS–Hard IP or
PCS–FPGA Fabric Interface Frequency
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5 for Gen2
Disabled
Enabled
Disabled
Enabled
8-Bit
16-Bit
250 MHz
Gen 1 - 125 MHz,
Gen 2 - 250 MHz
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The transceiver datapath clocking varies between non-bonded (x1) and bonded (x2, x4, and x8) configurations.
Transceiver Channel Datapath
Figure 4-3: Transceiver Channel Datapath in a PIPE Configuration
rx_serial_data
CDR
Deserializer
Word Aligner
Deskew FIFO
Receiver PMA
Rate Match FIFO
8B/10B Decoder
Byte Deserializer
Byte Ordering
RX Phase
Compensation
FIFO
Receiver PCS
tx_serial_data
TX Bit
Slip
Serializer
Transmitter PMA
8B/10B Encoder
Byte Serializer
TX Phase
Compensation
FIFO
PIPE Interface
FPGA
Fabric
PCI Express Hard IP
Transmitter PCS
Related Information
Transceiver Architecture in Arria V Devices
PCIe Supported Features
The PIPE configuration for the 2.5 Gbps (Gen1) and 5 Gbps (Gen2) data rates supports these features:
•
•
•
•
•
•
•
•
•
PCIe-compliant synchronization state machine
±300 parts per million (ppm)—total 600 ppm—clock rate compensation
8-bit FPGA fabric–transceiver interface
16-bit FPGA fabric–transceiver interface
Transmitter buffer electrical idle
Receiver detection
8B/10B encoder disparity control when transmitting compliance pattern
Power state management (Electrical Idle only)
Receiver status encoding
PIPE Interface
In a PIPE configuration, each channel has a PIPE interface block that transfers data, control, and status
signals between the PHY-MAC layer and the transceiver channel PCS and PMA blocks.
The PIPE interface block complies with version 2.0 of the PIPE specification. If you use the PIPE hard IP
block, the PHY-MAC layer is implemented in the hard IP block. Otherwise, you can implement the PHYMAC layer using soft IP in the FPGA fabric.
If you use the PIPE hard IP block, the PHY-MAC layer is implemented in the hard IP block. Otherwise, you
can implement the PHY-MAC layer using soft IP in the FPGA fabric, which will be supported in future
versions of the Quartus II software.
Note: The PIPE interface block is used in a PIPE configuration and cannot be bypassed.
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In addition to transferring data, control, and status signals between the PHY-MAC layer and the transceiver,
the PIPE interface block implements the following functions that are required in a PCIe-compliant physical
layer device:
•
•
•
•
•
Forces the transmitter buffer into an electrical idle state
Initiates the receiver detect sequence
Controls the 8B/10B encoder disparity when transmitting a compliance pattern
Manages the PCIe power states (Electrical Idle only)
Indicates the completion of various PHY functions, such as receiver detection and power state transitions
on the pipe_phystatus signal
• Encodes the receiver status and error conditions on the pipe_rxstatus[2:0] signal, as specified in the
PCIe specification
Transmitter Electrical Idle Generation
The PIPE interface block places the channel transmitter buffer in an electrical idle state when the electrical
idle input signal is asserted.
During electrical idle, the transmitter buffer differential and common configuration output voltage levels
are compliant to the PCIe Base Specification 2.1 for the PCIe Gen2 data rate.
The PCIe specification requires that the transmitter buffer be placed in electrical idle in certain power states.
Power State Management
The PCIe specification defines four power states: P0, P0s, P1, and P2.
The physical layer device must support these power states to minimize power consumption:
• P0 is the normal operating state during which packet data is transferred on the PCIe link.
• P0s, P1, and P2 are low-power states into which the physical layer must transition as directed by the
PHY-MAC layer to minimize power consumption.
The PIPE interface in the transceivers provides an input port for each transceiver channel configured in a
PIPE configuration.
Note: When transitioning from the P0 power state to lower power states (P0s, P1, and P2), the PCIe
specification requires that the physical layer device implements power saving measures. The
transceivers do not implement these power saving measures except to place the transmitter buffer
in electrical idle in the lower power states.
8B/10B Encoder Usage for Compliance Pattern Transmission Support
The PCIe transmitter transmits a compliance pattern when the Link Training and Status State Machine
(LTSSM) enters a polling compliance substate. The polling compliance substate assesses if the transmitter
is electrically compliant with the PCIe voltage and timing specifications.
Receiver Status
The PCIe specification requires that the PHY encode the receiver status on a 3-bit status signal
(pipe_rxstatus[2:0]).
This status signal is used by the PHY-MAC layer for its operation. The PIPE interface block receives the
status signals from the transceiver channel PCS and PMA blocks, and encodes the status on the
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Receiver Detection
pipe_rxstatus[2:0] signal to the FPGA fabric. The encoding of the status signals on the
pipe_rxstatus[2:0] signal is compliant with the PCIe specification.
Receiver Detection
The PIPE interface block in Arria V transceivers provides an input signal (pipe_txdetectrx_loopback)
for the receiver detect operation that is required by the PCIe protocol during the detect substate of the
LTSSM.
When the pipe_txdetectrx_loopback signal is asserted in the P1 power state, the PCIe interface block
sends a command signal to the transmitter buffer in that channel to initiate a receiver detect sequence. In
the P1 power state, the transmitter buffer must always be in the electrical idle state.
After receiving this command signal, the receiver detect circuitry creates a step voltage at the output of the
transmitter buffer. If an active receiver that complies with the PCIe input impedance requirements is present
at the far end, the time constant of the step voltage on the trace is higher than if the receiver is not present.
The receiver detect circuitry monitors the time constant of the step signal that is seen on the trace to determine
if a receiver was detected. The receiver detect circuitry monitor requires a 125-MHz clock for operation that
you must drive on the fixedclk port.
Note: For the receiver detect circuitry to function reliably, the AC-coupling capacitor on the serial link and
the receiver termination values used in your system must be compliant with the PCIe Base Specification
2.1.
The PCI Express PHY (PIPE) IP core provides a 1-bit PHY status (pipe_phystatus) and a 3-bit receiver
status signal (pipe_rxstatus[2:0]) to indicate whether a receiver was detected or not, in accordance to
the PIPE 2.0 specifications.
Clock Rate Compensation Up to ±300 ppm
In compliance with the PCIe protocol, the receiver channels are equipped with a rate match FIFO to
compensate for the small clock frequency differences of up to ± 300 ppm between the upstream transmitter
and local receiver clocks.
Related Information
Transceiver Architecture in Arria V Devices
PCIe Reverse Parallel Loopback
The PCIe reverse parallel loopback is only available in the PCIe functional configuration for the Gen1 data
rate. The received serial data passes through the receiver CDR, deserializer, word aligner, and rate matching
FIFO buffer. It is then looped back to the transmitter serializer and transmitted out through the transmitter
buffer. The received data is also available to the FPGA fabric through the port.
This loopback mode is compliant with the PCIe specification 2.1.
Arria V devices provide the pipe_txdetectrx_loopback input signal to enable this loopback mode. If the
pipe_txdetectrx_loopback signal is asserted in the P1 power state, receiver detection is performed. If the
signal is asserted in the P0 power state, reverse parallel loopback is performed.
Note: The PCIe reverse parallel loopback is the only loopback option that is supported in PIPE configurations.
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PIPE Transceiver Channel Placement Guidelines
4-7
Figure 4-4: PIPE Reverse Parallel Loopback Mode Datapath
Serializer
8B10B Encoder
Byte Serializer
Reverse Parallel
Loopback Path
CDR
Word Aligner
Deskew FIFO
Rate Match FIFO
8B/10B Decoder
Byte Deserializer
Byte Ordering
Receiver PMA
Deserializer
TX Phase
Compensation
FIFO
Transmitter PMA
Receiver PCS
RX Phase
Compensation
FIFO
PIPE Interface
FPGA
Fabric
PCI Express Hard IP
Transmitter PCS
PIPE Transceiver Channel Placement Guidelines
Table 4-2: PIPE Channel Placement for PCIe Gen1
Placement by the Quartus II software may vary with design, resulting in higher channel utilization.
Configuration
Data Channel
Placement
Minimum Channel
Utilization
Default Logical Data Channel Number for
Master
x1
Any channel
2 (1 data channel, 1 Data_channel[0]
clock channel)
x2
2 contiguous
channels
3 (2 data channels, Data_channel[1]
1 clock channel)
x4
4 contiguous
channels
5 (4 data channels, Data_channel[1]
1 clock channel)
x8
8 contiguous
channels
9 (8 data channels, Data_channel[0]
1 clock channel)
To override the default data channel number for the Master channel, do following:
1. Assign the Master channel to the same bank of CMU PLL.
2. Apply the following Quartus II QSF assignment:
set_parameter -name master_ch_number <logical_data_channel_number>
-to <"test:pcie_i|altera_xcvr_pipe:test_inst|av_xcvr_pipe_nr:pipe_nr_inst|
av_xcvr_pipe_native:transceiver_core">
To support PIPE placement identical to PCIe HIP x8, use following two Quartus II QSF assignments:
set_parameter -name master_ch_number 4 -to
<"test:pcie_i|altera_xcvr_pipe:test_inst|av_xcvr_pipe_nr:pipe_nr_inst|
av_xcvr_pipe_native:transceiver_core”>
set_parameter -name dummy_ch_required 1 -to
<"test:pcie_i|altera_xcvr_pipe:test_inst|av_xcvr_pipe_nr:pipe_nr_inst|
av_xcvr_pipe_native:transceiver_core">
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PIPE Transceiver Channel Placement Guidelines
Note: For more information about the hard IP implementation of PCIe and restrictions, refer to the
“Transceiver Banks” section of the Transceiver Architecture in Arria V Devices chapter.
The following four figures show examples of channel placement for PIPE x1, x2, x4, and x8 configurations.
Figure 4-5: Example of PIPE x1 Channel Placement
Channels shaded in blue provide the high-speed serial clock. Channels shaded in gray are data channels.
You can place the PIPE data channels in any available channel in the transceiver bank.
Arria V Device
Transceiver Bank
Transceiver Bank
Ch5
Ch5
Ch4
PIPE x1
Ch3
Ch3
Ch2
Ch2
Ch1
Ch1
Ch0
Ch0
Transceiver Bank
Ch5
Ch4
Ch4
Ch3
Ch3
Ch2
Ch2
PIPE x1
CMU PLL
Transceiver Bank
Ch5
Ch1
PIPE x1
Ch4
CMU PLL
Ch1
CMU PLL
CMU PLL
PIPE x1
Ch0
Ch0
Figure 4-6: Example of PIPE x2 Channel Placement
Arria V Device
Transceiver Bank
Transceiver Bank
Ch5
Ch5
Ch5
Ch4
Ch4
Ch4
Ch3
Ch3
Ch3
Ch2
Ch2
Ch2
Ch1PCS Master Master CGB
Ch1
Ch1
Ch0
Ch0
Ch0
Transceiver Bank
CMU PLL
Data Ch1 Ch5
Transceiver Bank
Ch5
Ch4PCS Master Master CGB
Ch2
Ch3
Ch1
Ch2
Ch0
Ch1
Slave CGB
Data Ch0 Ch4PCS Master Master CGB
Ch3
Ch5
Data Ch0 Ch4PCS Master Master CGB
Slave CGB
Data Ch1 Ch3
Ch2
CMU PLL
Ch1
CMU PLL
Ch0
CMU PLL
Ch0
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PCIe Supported Configurations and Placement Guidelines
Figure 4-7: Example of PIPE x4 Channel Placement
Channels shaded in blue provide the high-speed serial clock. Channels shaded in gray are data channels.
Arria V Device
Transceiver Bank
Transceiver Bank
Ch5
Ch4
Ch5
Ch4
CMU PLL
Ch3
Ch3
Ch2
PIPE x4
Ch1
Ch2
Ch1
Master
Ch0
Ch0
PIPE x4
Transceiver Bank
Transceiver Bank
Ch5
Ch4
Ch5
Ch4
Master
Ch3
Ch2
PIPE x4
Ch1
Master
Ch3
Ch2
Ch1
CMU PLL
Ch0
CMU PLL
Ch0
Figure 4-8: Example of PIPE x8 Channel Placement
Channels shaded in blue provide the high-speed serial clock. Channels shaded in gray are data channels.
Arria V Device
Transceiver Bank
Arria V Device
Transceiver Bank
Transceiver Bank
Transceiver Bank
Ch5
Ch5
Ch5
Ch5
Ch4
Ch4
Ch4
Ch4 CMU PLL / Master
Ch3
Ch3
Ch3
Ch3
Ch2
Ch2
Ch2
Ch2
Ch1
Ch1
Ch1
Ch1
Ch0
Ch0
Ch0
Ch0
PIPE x8
PIPE x8
Transceiver Bank
Transceiver Bank
Ch5
Ch5
Ch4
Ch3
Transceiver Bank
PIPE x8
Transceiver Bank
Ch5
Ch5
Ch4
Ch4 CMU PLL / Master
Ch4
Ch3
Ch3
Ch3
Ch2
Ch2
Ch2
Ch2
Ch1 CMU PLL / Master
Ch1 CMU PLL / Master
Ch1
Ch1
Ch0
Ch0
Ch0
Ch0
PIPE x8
Related Information
Transceiver Architecture in Arria V Devices
PCIe Supported Configurations and Placement Guidelines
Placement by the Quartus II software may vary with design and device. The following figures show examples
of transceiver channel and PCIe Hard IP block locations, supported x1, x2, x4, and x8 bonding configurations,
and channel placement guidelines. The Quartus II software automatically places the CMU PLL in a channel
different from that of the data channels.
Note: This section shows the supported PCIe channel placement if you use both the top
and bottom PCIe Hard IP blocks in the device separately.
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PCIe Supported Configurations and Placement Guidelines
In the following figures, channels shaded in blue provide the high-speed serial clock. Channels
shaded in gray are data channels.
Figure 4-9: PCIe HIP Supported x1 Guidelines
Transceiver Bank GXB_L0/R0
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
Transceiver Bank GXB_L0/R0
Ch5
Ch4
Ch3
Ch2
PCIe x1
Altera Corporation
Ch1
CMU PLL
Ch0
Master
PCIe
Hard IP
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Figure 4-10: PCIe HIP Supported x2 and x4 Guidelines
Transceiver Bank GXB_L0/R0
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
Transceiver Bank GXB_L0/R0
Ch5
Ch4
CMU PLL
Ch3
Ch2
PCIe x4
Ch1
PCIe x2
PCIe
Hard IP
Master
Ch0
Figure 4-11: PCIe HIP Supported x8 Guidelines
Transceiver Bank GXB_L1/R1
Ch5
Ch4
Ch3
Ch2
Ch1
Ch0
Transceiver Bank GXB_L0/R0
PCIe x8
Ch5
Ch4 CMU PLL
Master
Ch3
Ch2
Ch1
PCIe
Hard IP
Ch0
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PIPE Transceiver Clocking
For PCIe Gen1 and Gen2, there are restrictions on the achievable x1 and x4 bonding configurations
if you intend to use both top and bottom Hard IP blocks in the device.
Related Information
Transceiver Architecture in Arria V Devices
PIPE Transceiver Clocking
This section describes transceiver clocking for PIPE configurations.
PIPE x1 Configuration
The serial clock in the transceiver clocking configuration is provided by the CMU PLL in a channel different
from that of the data channel. The local clock divider block in the data channel generates a parallel clock
from this high-speed clock and distributes both clocks to the PMA and PCS of the data channel.
Figure 4-12: Transceiver Clocking Configuration in a PIPE x1 Configuration
Transmitter PMA
x1 Clock Line
Serializer
8B/10B Encoder
Byte Serializer
TX Phase
Compensation
FIFO
PCIe hard IP
PIPE Interface
tx_coreclk
TX Bit Slip
Transmitter Standard PCS
FPGA
Fabric
/2
Central/ Local Clock Divider
CMU PLL
Clock Divider
Parallel and Serial Clocks (From the x6 or xN Clock Lines)
PIPE Interface
PCIe hard IP
Serializer
TX Bit Slip
Transmitter PMA
/2
Central/ Local Clock Divider
CMU PLL
Parallel Clock
Serial Clock
Parallel and Serial Clocks
8B/10B Encoder
tx_coreclk
Byte Serializer
TX Phase
Compensation
FIFO
Transmitter Standard PCS
Clock Divider
Parallel and Serial Clocks (From the x6 or xN Clock Lines)
PIPE x4 Configuration
In a PIPE x4 bonded configuration, clocking is independent for the receiver channels. The clocking and
control signals are bonded only for the transmitter channels.
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4-13
Figure 4-13: Transceiver Clocking Configuration in a PIPE x4 Configuration
Clock Divider
Serializer
Transmitter PMA
/2
Central/ Local Clock Divider
CMU PLL
Clock Divider
TX Bit Slip
Byte Serializer
TX Phase
Compensation
FIFO
PIPE Interface
tx_coreclk
8B/10B Encoder
Transmitter Standard PCS
Transmitter PMA
Serializer
Ch3
/2
Central/ Local Clock Divider
CMU PLL
Clock Divider
Transmitter PMA
/2
Central/ Local Clock Divider
CMU PLL
Clock Divider
TX Bit Slip
Byte Serializer
TX Phase
Compensation
FIFO
PIPE Interface
tx_coreclk
8B/10B Encoder
(Master) Transmitter Standard PCS
Transmitter PMA
Serializer
Ch1
/2
Central/ Local Clock Divider
CMU PLL
Clock Divider
Byte Serializer
TX Phase
Compensation
FIFO
PIPE Interface
8B/10B Encoder
Transmitter Standard PCS
Transmitter PMA
Serializer
Ch0
tx_coreclk
TX Bit Slip
Byte Serializer
TX Phase
Compensation
FIFO
PIPE Interface
tx_coreclk
8B/10B Encoder
Transmitter Standard PCS
Serializer
Ch2
TX Bit Slip
PCIe hard IP
TX Bit Slip
TX Phase
Compensation
FIFO
Byte Serializer
8B/10B Encoder
Transmitter Standard PCS
PIPE Interface
PCIe hard IP
tx_coreclk
PCIe hard IP
×6 Clock Line ×1 Clock Line
Central/ Local Clock Divider
Ch4
PCIe hard IP
Transmitter PMA
/2
CMU PLL
PCIe hard IP
TX Bit Slip
Byte Serializer
TX Phase
Compensation
FIFO
PIPE Interface
PCIe hard IP
tx_coreclk
8B/10B Encoder
Transmitter Standard PCS
Serializer
Transceiver Bank
Ch5
FPGA
Fabric
/2
Central/ Local Clock Divider
CMU PLL
Clock Divider
Parallel Clock
Serial Clock
Parallel and Serial Clocks
PIPE x8 Configuration
In a PIPE x8 bonded configuration, the clocking for the PMA and PCS blocks is independent for the receiver
channels. The clocking and control signals are bonded only for the transmitter channels.
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PIPE Transceiver Clocking
For more information about clocking in Arria V devices, refer to the Transceiver Clocking in Arria V Devices
chapter.
Figure 4-14: Transceiver Clocking Configuration in a PIPE x8 Configuration
Transceiver Bank
FPGA
Fabric
×N Clock Line ×1 Clock Line
Ch5
Transmitter PCS
Transmitter PMA
Serializer
Local Clock Divider
CMU PLL
Clock Divider
Transmitter PCS
Ch4
Transmitter PMA
Serializer
Central Clock Divider
CMU PLL
Clock Divider
Transmitter PCS
Ch3
Transmitter PMA
Serializer
Local Clock Divider
PIPE INTERFACE
CMU PLL
Ch2
Clock Divider
Low-Speed Parallel Clock
High-Speed Serial Clock
Transmitter PCS
Transmitter PMA
Serializer
Local Clock Divider
CMU PLL
Clock Divider
(Master) Transmitter PCS
Ch1
Transmitter PMA
Serializer
Central Clock Divider
CMU PLL
Clock Divider
Transmitter PCS
Ch0
Transmitter PMA
Serializer
Local Clock Divider
CMU PLL
Clock Divider
Transceiver Bank
Ch5
×1 Clock Line
Transmitter PCS
Transmitter PMA
Serializer
Local Clock Divider
CMU PLL
Ch4
Clock Divider
Low-Speed Parallel Clock
High-Speed Serial Clock
Transmitter PCS
Transmitter PMA
Serializer
Central Clock Divider
CMU PLL
Clock Divider
Transmitter PCS
Ch3
Transmitter PMA
Serializer
Local Clock Divider
PIPE INTERFACE
CMU PLL
Ch2
Clock Divider
Low-Speed Parallel Clock
High-Speed Serial Clock
Transmitter PCS
Transmitter PMA
Serializer
Local Clock Divider
CMU PLL
Ch1
Clock Divider
Low-Speed Parallel Clock
High-Speed Serial Clock
Transmitter PCS
Transmitter PMA
Serializer
Central Clock Divider
CMU PLL
Ch0
Clock Divider
Transmitter PCS
Transmitter PMA
Serializer
Local Clock Divider
CMU PLL
Clock Divider
Parallel Clock
Serial Clock
Parallel and Serial Clocks
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Related Information
• "PCI Express PHY IP Core" chapter in the Altera Transceiver PHY IP Core User Guide
• Transceiver Clocking in Arria V Devices
Gigabit Ethernet
The IEEE 802.3 specification defines the 1000BASE-X PHY as an intermediate, or transition layer that
interfaces various physical media with the MAC in a gigabit ethernet (GbE) system, shielding the MAC layer
from the specific nature of the underlying medium. The 1000BASE-X PHY is divided into the PCS, PMA,
and PMD sublayers.
The PCS sublayer interfaces with the MAC through the gigabit media independent interface (GMII). The
1000BASE-X PHY defines a physical interface data rate of 1 Gbps and 2.5 Gbps.
Figure 4-15: 1000BASE-X PHY in a GbE OSI Reference Model
OSI Reference
Model Layers
LAN
CSMA/CD Layers
Higher Layers
LLC
Application
MAC (Optional)
Presentation
MAC
Session
Reconciliation
Transport
GMII
Network
PCS
Data Link
PMA
Physical
PMD
1000 Base-X PHY
The transceivers, when configured in GbE functional mode, have built-in circuitry to support the following
PCS and PMA functions, as defined in the IEEE 802.3 specification:
•
•
•
•
8B/10B encoding and decoding
Synchronization
Clock recovery from the encoded data forwarded by the receiver PMD
Serialization and deserialization
Note: If you enabled the autonegotiation state machine in the FPGA core with the rate match FIFO, refer
to the "Rate Match FIFO" section in the "Gigabit Ethernet Transceiver Datapath" section.
Note: The transceivers do not have built-in support for other PCS functions, such as the autonegotiation
state machine, collision-detect, and carrier-sense functions. If you require these functions, implement
them in the FPGA fabric or in external circuits.
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Gigabit Ethernet
Figure 4-16: Transceiver Blocks in a GbE Configuration
Functional Mode
PMA-PCS Interface Width
Data Rate (Gbps)
Number of Bonded Channels
Low Latency PCS
Word Aligner (Pattern Length)
8B/10B Encoder/Decoder
GbE-1.25 Gbps
GbE-3.125 Gbps
10 bit
10 bit
1.25
3.125
x1
x1
Disabled
Disabled
Automatic Synchronization
State Machine
(7-bit Comma, 10-bit /K28.5/)
Automatic Synchronization
State Machine
(7-bit Comma, 10-bit /K28.5/)
Enabled
Enabled
Enabled
Enabled
Byte SERDES
Disabled
Enabled
Byte Ordering
Disabled
Disabled
8-bit
16-bit
125
156.25
Rate Match FIFO
FPGA Fabric-Transceiver
Interface Width
FPGA Fabric-Transceiver
Interface Frequency (MHz)
Related Information
Gigabit Ethernet Transceiver Datapath on page 4-17
Refer to the "Rate Match FIFO" section.
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Gigabit Ethernet Transceiver Datapath
Figure 4-17: Transceiver Datapath in GbE-1.25 Gbps Configuration
FPGA Fabric
Transmitter Channel PMA
Transmitter Channel PCS
TX Phase
Compensation
FIFO
wrclk rdclk
8B/10B
Encoder
Serializer
tx_coreclk[0]
High-Speed Serial Clock
Low-Speed Parallel Clock
Local Clock
Divider
tx_clkout[0]
FPGA Fabric–Transceiver Interface Clock
Receiver Channel PCS
RX Phase
Compensation
FIFO
rx_coreclk[0]
Rate
Match
FIFO
8B/10B
Decoder
Word
Aligner
Receiver Channel PMA
Deserializer
CDR
Parallel Recovered Clock
Low-Speed Parallel Clock
Figure 4-18: Transceiver Datapath in GbE-3.125 Gbps Configuration
FPGA Fabric
Transmitter Channel PMA
Transmitter Channel PCS
TX Phase
Compensation
FIFO
wrclk rdclk
Byte
SERDES
8B/10B
Encoder
Serializer
tx_coreclk[0]
High-Speed Serial Clock
Low-Speed Parallel Clock
Local Clock
Divider
tx_clkout[0]
FPGA Fabric–Transceiver Interface Clock
Receiver Channel PCS
rx_coreclk[0]
RX Phase
Compensation
FIFO
Byte
SERDES
8B/10B
Decoder
Rate
Match
FIFO
Word
Aligner
Receiver Channel PMA
Deserializer
CDR
Parallel Recovered Clock
Low-Speed Parallel Clock
Table 4-3: Transceiver Datapath Clock Frequencies in GbE Configuration
Functional Mode
Data Rate
High-Speed Serial
Clock Frequency
Parallel Recovered
Clock and Low-Speed
Parallel Clock
Frequency
FPGA Fabric-Transceiver Interface
Clock Frequency
GbE-1.25
Gbps
1.25 Gbps
625 MHz
125 MHz
125 MHz
GbE-3.125
Gbps
3.125 Gbps
1562.5 MHz
312.5 MHz
156.25 MHz
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Gigabit Ethernet Transceiver Datapath
8B/10B Encoder
In GbE configuration, the 8B/10B encoder clocks in 8-bit data and 1-bit control identifiers from the transmitter
phase compensation FIFO and generates 10-bit encoded data. The 10-bit encoded data is fed to the serializer.
For more information about the 8B/10B encoder functionality, refer to the Transceiver Architecture for
Arria V Devices chapter.
Rate Match FIFO
In GbE configuration, the rate match FIFO is capable of compensating for up to ±100 ppm (200 ppm total)
difference between the upstream transmitter and the local receiver reference clock. The GbE protocol requires
that the transmitter send idle ordered sets /I1/ (/K28.5/D5.6/) and /I2/ (/K28.5/D16.2/) during interpacket
gaps, adhering to the rules listed in the IEEE 802.3 specification.
The rate match operation begins after the synchronization state machine in the word aligner indicates that
the synchronization is acquired-by driving the rx_syncstatus signal high. The rate matcher always deletes
or inserts both symbols (/K28.5/ and /D16.2/) of the /I2/ ordered sets, even if only one symbol needs to be
deleted to prevent the rate match FIFO from overflowing or underrunning. The rate matcher can insert or
delete as many /I2/ ordered sets as necessary to perform the rate match operation.
Two flags are forwarded to the FPGA fabric:
• rx_rmfifodatadeleted—Asserted for two clock cycles for each deleted /I2/ ordered set to indicate the
rate match FIFO deletion event
• rx_rmfifodatainserted—Asserted for two clock cycles for each inserted /I2/ ordered set to indicate
the rate match FIFO insertion event
Note: If you have the autonegotiation state machine in the FPGA, note that the rate match FIFO is capable
of inserting or deleting the first two bytes (/K28.5//D2.2/) of /C2/ ordered sets during autonegotiation.
However, the insertion or deletion of the first two bytes of /C2/ ordered sets can cause the
autonegotiation link to fail. For more information, refer to the Altera Knowledge Base Support
Solution.
For more information about the rate match FIFO, refer to the Transceiver Architecture for Arria V Devices
chapter.
GbE Protocol-Ordered Sets and Special Code Groups
Table 4-4: GIGE Ordered Sets
The following ordered sets and special code groups are specified in the IEEE 802.3-2008 specification.
Code
(34)
Ordered Set
Number of Code
Groups
Encoding
/C/
Configuration
—
Alternating /C1/ and /C2/
/C1/
Configuration 1
4
/K28.5/D21.5/ Config_Reg (34)
/C2/
Configuration 2
4
/K28.5/D2.2/ Config_Reg
/I/
IDLE
—
Correcting /I1/, Preserving /I2/
/I1/
IDLE 1
2
/K28.5/D5.6/
Two data code groups represent the Config_Reg value.
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Code
Ordered Set
Number of Code
Groups
4-19
Encoding
/I2/
IDLE 2
2
/K28.5/D16.2/
-
Encapsulation
—
—
/R/
Carrier_Extend
1
/K23.7/
/S/
Start_of_Packet
1
/K27.7/
/T/
End_of_Packet
1
/K29.7/
/V/
Error_Propagation
1
/K30.7/
Table 4-5: Synchronization State Machine Parameters in GbE Mode
Synchronization State Machine Parameters
Setting
Number of valid {/K28.5/, /Dx,y/} ordered sets received to achieve
synchronization
3
Number of errors received to lose synchronization
4
Number of continuous good code groups received to reduce the error
count by 1
4
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XAUI
Figure 4-19: Synchronization State Machine in GbE Mode
This figure is from “Figure 36–9” in the IEEE 802.3-2008 specification. For more details about the 1000BASE-X
implementation, refer to Clause 36 of the IEEE 802.3-2008 specification.
power_on=TRUE + mr_main_reset=TRUE +
(signal_detectChange=TRUE
mr_loopback=FALSE PUDI)
LOSS_OF_SYNC
(PUDI * signal_detect=FAIL *
mr_loopback=FALSE +
PUDI(![/COMMA/])
PUDI(![/D/])
sync_status ⇐FAIL
rx_even ⇐! rx_even
SUDI
(signal_detect=OK + mr_loopback=TRUE)
PUDI([/COMMA/])
COMMA_DETECT_1
rx_even ⇐TRUE
SUDI
PUDI([/D/])
ACQUIRE_SYNC_1
PUDI(![/COMMA/] ∉[/INVALID/])
rx_even ⇐! rx_even
SUDI
cgbad
rx_even=FALSE PUDI([/COMMA/])
COMMA_DETECT_2
rx_even ⇐TRUE
SUDI
PUDI(![/D/])
PUDI([/D/])
ACQUIRE_SYNC_2
PUDI(![/COMMA/] ∉[/INVALID/])
rx_even ⇐! rx_even
SUDI
cgbad
rx_even=FALSE PUDI([/COMMA/])
COMMA_DETECT_3
rx_even ⇐TRUE
SUDI
PUDI(![/D/])
SYNC_ACQUIRED_1
PUDI([/D/])
sync_status ⇐OK
rx_even ⇐! rx_even
SUDI
cgbad
2
cggood
cggood
SYNC_ACQUIRED_2
SYNC_ACQUIRED_2A
rx_even ⇐! rx_even
SUDI
good_cgs ⇐good_cgs + 1
rx_even ⇐! rx_even
SUDI
good_cgs ⇐0
cgbad
cgbad
3
cggood
good_cgs ≠ 3
good_cgs = 3 cggood
cggood
SYNC_ACQUIRED_3
SYNC_ACQUIRED_3A
rx_even ⇐! rx_even
SUDI
good_cgs ⇐good_cgs + 1
rx_even ⇐! rx_even
SUDI
good_cgs ⇐0
cgbad
cgbad
cggood
good_cgs ≠ 3
2 cggood good_cgs = 3
cggood
SYNC_ACQUIRED_4
rx_even ⇐! rx_even
SUDI
good_cgs ⇐0
cgbad
SYNC_ACQUIRED_4A
rx_even ⇐! rx_even
SUDI
good_cgs ⇐good_cgs + 1
cgbad
cggood
good_cgs ≠ 3
3 cggood good_cgs = 3
Related Information
Refer to the "Custom PHY IP Core" and "Native PHY IP Core" chapters in the Altera Transceiver PHY
IP Core User Guide
XAUI
In a XAUI configuration, the transceiver channel data path is configured using soft PCS. It provides the
transceiver channel datapath description, clocking, and channel placement guidelines. With the MegaWizard
Plug-In Manager, you can implement a XAUI link. Under Ethernet in the Interfaces menu, select the XAUI
PHY IP core. The XAUI PHY IP core implements the XAUI PCS in soft logic.
XAUI is a specific physical layer implementation of the 10 Gigabit Ethernet link defined in the IEEE 802.3ae2002 specification. The XAUI PHY uses the XGMII interface to connect to the IEEE802.3 MAC and
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Reconciliation Sublayer (RS). The IEEE 802.3ae-2002 specification requires the XAUI PHY link to support
a 10 Gbps data rate at the XGMII interface and four lanes each at 3.125 Gbps at the PMD interface.
Figure 4-20: XAUI and XGMII Layers
LAN Carrier Sense Multiple
Access/Collision Detect (CSMA/CD)
Layers
Higher Layers
Logical Link Control (LLC)
OSI
Reference
Model Layers
MAC Control (Optional)
Media Access Control (MAC)
Application
Reconciliation
Presentation
Session
Transport
10 Gigabit Media Independent Interface
Optional
XGMII
Extender
XGMII Extender Sublayer
10 Gigabit Attachment Unit Interface
XGMII Extender Sublayer
10 Gigabit Media Independent Interface
Network
PCS
Data Link
PMA
Physical Layer Device
PMD
Physical
Medium Dependent Interface
Medium
10 Gbps
Related Information
Refer to the "XAUI PHY IP Core" chapter in the Altera Transceiver PHY IP Core User Guide.
Transceiver Datapath in a XAUI Configuration
The XAUI PCS is implemented in soft logic inside the FPGA core when using the XAUI PHY IP core. You
must ensure that your channel placement is compatible with the soft PCS implementation.
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Transceiver Datapath in a XAUI Configuration
Figure 4-21: XAUI Configuration Datapath
Transceiver PHY IP
Lane Data Rate
Number of Bonded Channels
PCS-PMA Interface Width
Word Aligner (Pattern Length) (1)
8B/10B Encoder/Decoder (1)
Deskew FIFO (1)
Rate Match FIFO (1)
Byte SERDES (1)
Byte Ordering (1)
FPGA Fabric-to-Transceiver
Interface Width
FPGA Fabric-to-Transceiver
Interface Frequency
XAUI PHY IP
3.125 Gbps
×4
10-Bit
10-Bit/K28.5
Enabled
Enabled
Enabled
Enabled
Disabled
16-Bit
156.25 MHz
Note:
1. Implemented in soft logic.
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XAUI Supported Features
Figure 4-22: Transceiver Channel Datapath for XAUI Configuration
Standard PCS in a low latency configuration is used in this configuration. Additionally, a portion of the PCS
is implemented in soft logic.
FPGA Fabric
TX Phase
Compensation
FIFO
8B/10B Encoder
16
Channel 1
20
Transmitter Standard PCS
Channel 0
Transmitter Standard PCS
20
Transmitter PMA Ch2
Transmitter PMA Ch1
Transmitter PMA Ch0
10
10
Receiver PMA
Deserializer
20
Byte
Deserializer
20
RX Phase
Compensation
FIFO
20
Word Aligner
20
Deskew FIFO
20
Rate Match FIFO
8B/10B
Decoder
Receiver Standard PCS
16
tx_serial_data
Soft PCS
Soft PCS
Transmitter PMA Ch3
Transmitter Standard PCS
Transmitter Standard PCS
rx_serial_data
Channel 1
Channel 0
Channel 3
Channel 2
Serializer
Soft PCS
CDR
Soft PCS
Channel 2
Byte Serializer
Channel 3
XAUI Supported Features
64-Bit SDR Interface to the MAC/RS
Clause 46 of the IEEE 802.3-2008 specification defines the XGMII interface between the XAUI PCS and the
Ethernet MAC/RS. The specification requires each of the four XAUI lanes to transfer 8-bit data and 1-bit
wide control code at both the positive and negative edge (DDR) of the 156.25 MHz interface clock.
Arria V transceivers and soft PCS solution in a XAUI configuration do not support the XGMII interface to
the MAC/RS as defined in IEEE 802.3-2008 specification. Instead, they allow the transferring of 16-bit data
and 2-bit control code on each of the four XAUI lanes, only at the positive edge (SDR) of the 156.25 MHz
interface clock
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Figure 4-23: Implementation of the XGMII Specification in Arria V Devices Configuration
XGMII Transfer (DDR)
Interface Clock (156.25 MHz)
8-bit
Lane 0
D0
D1
D2
D3
Lane 1
D0
D1
D2
D3
Lane 2
D0
D1
D2
D3
Lane 3
D0
D1
D2
D3
Arria V Soft PCS Interface (SDR)
Interface Clock (156.25 MHz)
16-bit
Lane 0
{D1, D0}
{D3, D2}
Lane 1
{D1, D0}
{D3, D2}
Lane 2
{D1, D0}
{D3, D2}
Lane 3
{D1, D0}
{D3, D2}
8B/10B Encoding/Decoding
Each of the four lanes in a XAUI configuration support an independent 8B/10B encoder/decoder as specified
in Clause 48 of the IEEE802.3-2008 specification. 8B/10B encoding limits the maximum number of
consecutive 1s and 0s in the serial data stream to five, thereby ensuring DC balance as well as enough
transitions for the receiver CDR to maintain a lock to the incoming data.
The XAUI PHY IP core provides status signals to indicate running disparity as well as the 8B/10B code group
error.
Transmitter and Receiver State Machines
In a XAUI configuration, the Arria V soft PCS implements the transmitter and receiver state diagrams shown
in Figure 48-6 and Figure 48-9 of the IEEE802.3-2008 specification.
In addition to encoding the XGMII data to PCS code groups, in conformance with the 10GBASE-X PCS,
the transmitter state diagram performs functions such as converting Idle ||I|| ordered sets into Sync ||K||,
Align ||A||, and Skip ||R|| ordered sets.
In addition to decoding the PCS code groups to XGMII data, in conformance with the 10GBASE-X PCS,
the receiver state diagram performs functions such as converting Sync ||K||, Align ||A||, and Skip ||R|| ordered
sets to Idle ||I|| ordered sets.
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Synchronization
The word aligner block in the receiver PCS of each of the four XAUI lanes implements the receiver
synchronization state diagram shown in Figure 48-7 of the IEEE802.3-2008 specification.
The XAUI PHY IP core provides a status signal per lane to indicate if the word aligner is synchronized to a
valid word boundary.
Deskew
The lane aligner block in the receiver PCS implements the receiver deskew state diagram shown in Figure
48-8 of the IEEE 802.3-2008 specification.
The lane aligner starts the deskew process only after the word aligner block in each of the four XAUI lanes
indicates successful synchronization to a valid word boundary.
The XAUI PHY IP core provides a status signal to indicate successful lane deskew in the receiver PCS.
Clock Compensation
The rate match FIFO in the receiver PCS datapath compensates up to ±100 ppm difference between the
remote transmitter and the local receiver. It does so by inserting and deleting Skip ||R|| columns, depending
on the ppm difference.
The clock compensation operation begins after:
• The word aligner in all four XAUI lanes indicates successful synchronization to a valid word boundary.
• The lane aligner indicates a successful lane deskew.
The rate match FIFO provides status signals to indicate the insertion and deletion of the Skip ||R|| column
for clock rate compensation.
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Transceiver Clocking and Channel Placement Guidelines in XAUI Configuration
Transceiver Clocking and Channel Placement Guidelines in XAUI Configuration
Transceiver Clocking
Figure 4-24: Transceiver Clocking for XAUI Configuration
One of the two channel PLLs configured as a CMU PLL in a transceiver bank generates the transmitter serial
and parallel clocks for the four XAUI channels. The x6 clock line carries the transmitter serial and parallel
clocks to the PMA and PCS of each of the four channels.
FPGA Fabric
20
Transmitter PMA Ch 1
Transmitter Standard PCS
TX Phase
Compensation
FIFO
8B/10B Encoder
16
Transmitter Standard PCS
Channel 0
20
10
Parallel Clock
/2
xgmii_tx_clk
Transmitter PMA Ch 0
tx_serial_data
Channel 1
Soft PCS
Soft PCS
Transmitter PMA Ch 3
Transmitter PMA Ch 2
Transmitter Standard PCS
xgmii_rx_clk
Parallel Clock
/2
Parallel Clock
(Recovered) from Channel 0
10
CDR
20
Receiver PMA
Deserializer
Byte Deserializer
RX Phase
Compensation
FIFO
Word Aligner
Deskew FIFO
20
Rate Match FIFO
16
8B/10B
Decoder
Receiver Standard PCS
rx_serial_data
Channel 2
Serializer
Channel 1
Channel 0
Transmitter Standard PCS
Channel 3
Soft PCS
Soft PCS
Channel 2
Byte Serializer
Channel 3
Parallel Clock (Recovered)
Central/ Local Clock Divider
(1)
CMU PLL /
fPLL
Serial Clock
(From the ×1 Clock Lines)
Clock Divider
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Note:
1. fPLL or CMU PLL can be used as the transmit PLL for XAUI support in Arria V devices. Take note of channel placement guidelines when using fPLL as a TX PLL for XAUI.
Table 4-6: Input Reference Clock Frequency and Interface Speed Specifications for XAUI Configurations
Input Reference Clock Frequency
(MHz)
156.25
FPGA Fabric-Transceiver Interface Width
16-bit data, 2-bit control
FPGA Fabric-Transceiver Interface
Frequency (MHz)
156.25
Transceiver Clocking Guidelines for Soft PCS Implementation
In the soft PCS implementation in the XAUI configuration, you must route xgmii_rx_clk to xgmii_tx_clk
as shown in the following figure.
This method uses xgmii_rx_clk to compensate for the phase difference on the TX side.
Without this method, the tx_digitalreset signal may experience intermittent failure.
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Figure 4-25: Transceiver Clocking for XAUI Soft PCS Implementation
FPGA Fabric
20
Transmitter Standard PCS
Transmitter PMA Ch 1
Transmitter Standard PCS
20
xgmii_tx_clk
/2
Transmitter PMA Ch 0
tx_serial_data
8B/10B Encoder
16
Channel 1
Channel 0
10
Parallel Clock
xgmii_rx_clk
Parallel Clock
/2
Parallel Clock
(Recovered) from Channel 0
10
CDR
20
Receiver PMA
Deserializer
Byte Deserializer
RX Phase
Compensation
FIFO
Word Aligner
Deskew FIFO
20
Rate Match FIFO
16
8B/10B
Decoder
Receiver Standard PCS
rx_serial_data
Soft PCS
Soft PCS
Transmitter PMA Ch 3
Transmitter PMA Ch 2
Transmitter Standard PCS
Serializer
Channel 1
Channel 0
Transmitter Standard PCS
Channel 3
Channel 2
Byte Serializer
Soft PCS
Soft PCS
Channel 2
TX Phase
Compensation
FIFO
Channel 3
Parallel Clock (Recovered)
Central/ Local Clock Divider
(1)
CMU PLL /
fPLL
Serial Clock
(From the ×1 Clock Lines)
Clock Divider
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Note:
1. fPLL or CMU PLL can be used as the transmit PLL for XAUI support in Arria V devices. Take note of channel placement guidelines when using fPLL as a TX PLL for XAUI.
Transceiver Channel Placement Guidelines
In the soft PCS implementation of the XAUI configuration, all four channels must be placed contiguously.
The channels may all be placed in one bank or they may span two banks. Only the placements shown in the
following figure are allowed.
The soft PCS implementation of the XAUI configuration has the following channel placement restrictions
when the fPLL is used as the TX PLL:
• The channels must be contiguous and placed within one bank.
• Ch1 or Ch4 must be selected as logical channel 0.
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10GBASE-R
Figure 4-26: Transceiver Channel Placement Guidelines in a XAUI Configuration
Use one of the two allowed channel placements when using the CMU PLL to drive the XAUI link. The
Quartus II software implements the XAUI PCS in soft logic.
Bank 1
Placement 1
Placement 2
XCVR Channel 5
XCVR Channel 5
XCVR Channel 4
XCVR Channel 4
XCVR Channel 3
XCVR Channel 3
XCVR Channel 2
XCVR Channel 2
XCVR Channel 1
CMU PLL
XCVR Channel 0
Bank 0
XCVR Channel 0
XCVR Channel 5
XCVR Channel 4
XCVR Channel 3
XCVR Channel 2
CMU PLL
Bank 0
XCVR Channel 0
Related Information
• To implement the QSF assignment workaround using the Assignment Editor, refer to the "XAUI
PHY IP Core" chapter in the Altera Transceiver PHY IP Core User Guide.
• To use the fPLL as a TX PLL, refer to the "Transceiver Channel Placement Guidelines for fPLL in
Transmit PLL Bonded Configuration" section of the Transceiver Clocking in Arria V Devices chapter.
10GBASE-R
Arria V GT and ST devices support 10GBASE-R in PMA direct mode using soft PCS. 10GBASE-R is a
specific physical layer implementation of the 10 Gigabit Ethernet link defined in clause 49 of the IEEE
802.3-2008 specification. The 10GBASE-R PHY uses the XGMII interface to connect to the IEEE802.3 media
access control (MAC) and reconciliation sublayer (RS). The IEEE 802.3-2008 specification requires each
10GBASE-R link to support a 10 Gbps data rate at the XGMII interface and a 10.3125 Gbps serial line rate
with 64B/66B encoding.
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The 10-Gbps transceivers transmitter in Arria V GT and ST devices are compliant with the 10GBASE-KR
specification under the following conditions:
• A maximum of three full duplex channels within a bank are used. These three channels do not include
a CMU PLL.
• The transmitted signal is 64B/66B encoded.
Figure 4-27: 10GBASE-R PHY Connection to IEEE802.3 MAC and RS
LAN
CSMA/CD
LAYERS
Higher Layers
LLC (Logical Link Control) or other MAC Client
OSI
Reference
Model
Layers
MAC Control (Optional)
Media Access Control (MAC)
Reconciliation
Application
Presentation
32-bit data, 4-bit control (DDR @ 156.25 MHz)
XGMII
Session
10GBASE-R PCS
Transport
Network
10GBASE-R
PHY
Serial PMA
PMD
Data Link
Physical
MDI
10.3125 Gbps
Medium
10GBASE-LR, -SR, -ER, or -lRM
In the MegaWizard™ Plug-In Manager, you can implement a 10GBASE-R link by instantiating the 10GBASER PHY IP core under Ethernet in the Interfaces menu.
Related Information
Refer to the 10GBASE-R PHY IP Core chapter in the Altera Transceiver PHY IP Core User Guide.
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10GBASE-R Transceiver Datapath Configuration
10GBASE-R Transceiver Datapath Configuration
Figure 4-28: 10GBASE-R Datapath Configuration for Arria V GT and ST Devices
Transceiver PHY IP
Lane Data Rate
10GBASE-R PHY IP
10.3125 Gbps
Number of Bonded Channels
None
PMA Direct
64-Bit
Gear Box (1)
Enabled (66:64 Ratio)
Block Synchronizer (1)
Scrambler, Descrambler (Mode) (1)
Enabled
Enabled
(Self Synchronous Mode)
64B/66B Encoder/Decoder (1)
Enabled
BER Monitor (1)
Enabled
RX FIFO (Mode) (1)
Enabled
(Clock Compensation Mode)
TX FIFO (Mode) (1)
Enabled
(Phase Compensation Mode)
TX/RX 10G Soft PCS Latency (Parallel Clock Cycles)
TX: 28
RX: 33
FPGA Fabric-to-Soft PCS
Interface Width
64-bit Data
8-bit Control
FPGA Fabric-to-Soft PCS
Interface Frequency
156.25 MHz
Note:
1. Implemented in soft logic.
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Figure 4-29: Transceiver Channel Datapath for a 10GBASE-R Configuration for Arria V GT and ST Devices
66
tx_serial_data
xgmii_tx_clk
(156.25MHz)
(1)
66
Transmitter PMA
Serializer
64-Bit Data
8-Bit Control
Scrambler
64B/66B Encoder
and TX SM
TX
FIFO
64-Bit Data
8-Bit Control
TX Gear Box
Transmitter Soft PCS
FPGA
Fabric
64
Parallel Clock (161.1328 MHz)
BER
Monitor
xgmii_rx_clk
(156.25MHz)
Div 40
Parallel Clock (Recovered) (161.1328 MHz)
fPLL
Input
Reference
Clock
Parallel and Serial Clocks
(Only from the Central Clock Divider)
156.25MHz
from fPLL
Central/ Local Clock Divider
CMU PLL
644.53125MHz/
322.26525MHz
rx_serial_data
64
CDR
66
Receiver PMA
Deserializer
66
RX Gear Box
66
Block Synchronizer
De-Scrambler
64-Bit Data
8-Bit Control
64B/66B Decoder
and RX SM
64-Bit Data
8-Bit Control
RX FIFO
Receiver Soft PCS
Clock Divider
Parallel Clock
Serial Clock
Parallel and Serial Clock
(1) The xgmii_tx_clk requires 0 ppm difference from the xgmii_rx_clk or the Input Reference Clock
10GBASE-R Supported Features
64-Bit Single Data Rate (SDR) Interface to the MAC/RS
Clause 46 of the IEEE 802.3-2008 specification defines the XGMII interface between the 10GBASE-R soft
PCS and the Ethernet MAC/RS. The XGMII interface defines the 32-bit data and 4-bit wide control character
clocked between the MAC/RS and the soft PCS at both the positive and negative edge (double data rate –
DDR) of the 156.25 MHz interface clock.
Arria V soft PCS does not support the XGMII interface to the MAC/RS as defined in the IEEE 802.3-2008
specification. Instead, they support a 64-bit data and 8-bit control SDR interface between the MAC/RS and
the soft PCS.
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Figure 4-30: XGMII Interface (DDR) versus Arria V Soft PCS Interface (SDR) for 10GBASE-R
XGMII Transfer (DDR)
Interface Clock (156.25 MHz)
TXD/RXD[31:0]
D0
D1
D2
D3
D4
D5
D6
TXC/RXC/[3:0]
C0
C1
C2
C3
C4
C5
C6
Arria V Soft PCS Interface (SDR)
Interface Clock (156.25 MHz)
TXD/RXD[63:0]
{D1, D0}
{D3, D2}
{D5, D4}
TXC/RXC/[7:0]
{C1, C0}
{C3, C2}
{C5, C4}
64B/66B Encoding/Decoding
Arria V soft PCS in a 10GBASE-R configuration supports 64B/66B encoding and decoding as specified in
Clause 49 of the IEEE802.3-2008 specification. The 64B/66B encoder receives 64-bit data and 8-bit control
code from the transmitter FIFO and converts it into 66-bit encoded data. The 66-bit encoded data contains
two overhead sync header bits that the receiver soft PCS uses for block synchronization and bit-error rate
(BER) monitoring.
The 64B/66B encoding also ensures enough transitions on the serial data stream for the receiver clock data
recovery (CDR) to maintain its lock on the incoming data.
Transmitter and Receiver State Machines
Arria V soft PCS in a 10GBASE-R configuration implement the transmitter and receiver state diagrams
shown in Figure 49-14 and Figure 49-15 of the IEEE802.3-2008 specification.
Besides encoding the raw data specified in the 10GBASE-R soft PCS, the transmitter state diagram performs
functions such as transmitting local faults (LBLOCK_T) under reset, as well as transmitting error codes
(EBLOCK_T) when the 10GBASE-R soft PCS rules are violated.
Besides decoding the incoming data specified in the 10GBASE-R soft PCS, the receiver state diagram performs
functions such as sending local faults (LBLOCK_R) to the MAC/RS under reset and substituting error codes
(EBLOCK_R) when the 10GBASE-R soft PCS rules are violated.
Block Synchronizer
The block synchronizer in the receiver soft PCS determines when the receiver has obtained lock to the
received data stream. It implements the lock state diagram shown in Figure 49-12 of the IEEE 802.3-2008
specification.
The block synchronizer provides a status signal to indicate whether it has achieved block synchronization
or not.
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Self-Synchronous Scrambling/Descrambling
The scrambler/descrambler blocks in the transmitter/receiver soft PCS implements the self-synchronizing
scrambler/descrambler polynomial 1 + x39 + x58, as described in clause 49 of the IEEE 802.3-2008 specification. The scrambler/descrambler blocks are self-synchronizing and do not require an initialization seed.
Barring the two sync header bits in each 66-bit data block, the entire payload is scrambled or descrambled.
BER Monitor
The BER monitor block in the receiver soft PCS implements the BER monitor state diagram shown in Figure
49-13 of the IEEE 802.3-2008 specification. The BER monitor provides a status signal to the MAC whenever
the link BER threshold is violated.
The 10GBASE-R PHY IP core provides a status flag to indicate a high BER whenever 16 synchronization
header errors are received within a 125 µs window.
Clock Compensation
The receiver FIFO in the receiver soft PCS datapath compensates up to ±100 ppm difference between the
remote transmitter and the local receiver. The receiver FIFO does so by inserting Idles (/I/) and deleting
Idles (/I/) or Ordered Sets (/O/), depending on the ppm difference.
Idle Insertion -- The receiver FIFO inserts eight /I/ codes following an /I/ or /O/ to compensate for clock
rate disparity.
Idle (/I/) or Sequence Ordered Set (/O/) Deletion -- The receiver FIFO deletes either four /I/ codes or
ordered sets (/O/) to compensate for the clock rate disparity. The receiver FIFO implements the following
IEEE802.3-2008 deletion rules:
• Deletes the lower four /I/ codes of the current word when the upper four bytes of the current word do
not contain a Terminate /T/ control character.
• Deletes the upper four /I/ codes of the current word when the previous word’s lower four bytes do not
contain a Terminate /T/ control character.
• Deletes one /O/ ordered set only when the receiver FIFO receives two consecutive /O/ ordered sets.
Related Information
Refer to the 10GBASE-R PHY IP Core chapter in the Altera Transceiver PHY IP Core User Guide
10GBASE-R Transceiver Clocking
The CMU PLL can be used as a TX PLL for Arria V GT and ST devices. Arria V GZ devices can use either
the CMU PLL or the ATX PLL as a TX PLL.
Table 4-7: Input Reference Clock Frequency and Interface Speed Specifications for 10GBASE-R Configurations
Input Reference Clock Frequency
(MHz)
644.53125, 322.265625
FPGA Fabric-Soft PCS Interface Width
64-bit data, 8-bit control
FPGA Fabric-Soft PCS Interface Frequency
(MHz)
156.25
Serial Digital Interface
The Society of Motion Picture and Television Engineers (SMPTE) defines various Serial Digital Interface
(SDI) standards for transmission of uncompressed video.
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Configurations Supported in SDI Mode
The following SMPTE standards are popular in video broadcasting applications:
• SMPTE 259M standard - more popularly known as the standard-definition (SD) SDI; defined to carry
video data at 270 Mbps
• SMPTE 292M standard - more popularly known as the high-definition (HD) SDI; defined to carry video
data at either 1485 Mbps or 1483.5 Mbps
• SMPTE 424M standard - more popularly known as the third-generation (3G) SDI; defined to carry video
data at either 2970 Mbps or 2967 Mbps
Configurations Supported in SDI Mode
Table 4-8: Configurations Supported in SDI Mode
Configuration
Data Rate (Mbps)
REFCLK Frequencies
(MHz)
FPGA Fabric-Transceiver Interface
Width
1,485
74.25, 148.5
10 bit and 20 bit
1,483.5
74.175, 148.35
10 bit and 20 bit
2,970
148.5, 297
Only 20-bit interfaces allowed in
3G
2,967
148.35, 296.7
Only 20-bit interfaces allowed in
3G
HD
3G
Figure 4-31: SDI Mode
Functional Mode
SDI
PMA-PCS Interface Width
Data Rate (Gbps)
10 bit
HD-SDI (1.485/1.4835)
3G-SDI (2.97/2.967)
x1
x1
Disabled
Disabled
Bit-Slip
Bit-Slip
Disabled
Disabled
Disabled
Disabled
Number of Bonded Channels
Low Latency PCS
Word Aligner (Pattern Length)
8B/10B Encoder/Decoder
Rate Match FIFO
Byte SERDES
Disabled
Enabled
Enabled
Byte Ordering
Disabled
Disabled
Disabled
10-bit
20-bit
20-bit
74.25/74.175
148.5/148.35
FPGA Fabric-Transceiver
Interface Width
FPGA Fabric-Transceiver
Interface Frequency (MHz)
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Serial Digital Interface Transceiver Datapath
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Serial Digital Interface Transceiver Datapath
Figure 4-32: SDI Mode Transceiver Datapath
FPGA Fabric
TX Phase
Compensation
FIFO
wrclk rdclk
tx_coreclk
FPGA
Fabric–Transceiver
Interface Clock
Transmitter Channel PMA
Transmitter Channel PCS
Byte
Serializer
Serializer
wrclk rdclk
/2
Low-Speed Parallel Clock
High-Speed Serial Clock
Local Clock
Divider
tx_clkout
Receiver Channel PCS
RX Phase
Compensation
FIFO
Byte
Deserializer
Word
Aligner
Receiver Channel PMA
Deserializer
CDR
rx_coreclk
/2
Parallel Recovered Clock
rx_clkout
Transmitter Datapath
The transmitter datapath in the HD-SDI configuration with a 10-bit wide FPGA fabric-transceiver interface
consists of the transmitter phase compensation FIFO and the 10:1 serializer. In HD-SDI and 3G-SDI
configurations with 20-bit wide FPGA fabric-transceiver interface, the transmitter datapath also includes
the byte serializer.
Note: In SDI mode, the transmitter is purely a parallel-to-serial converter. You must implement the SDI
transmitter functions, such as the scrambling and cyclic redundancy check (CRC) code generation,
in the FPGA logic array.
Receiver Datapath
In the 10-bit channel width SDI configuration, the receiver datapath consists of the clock recovery unit
(CRU), 1:10 deserializer, word aligner in bit-slip mode, and receiver phase compensation FIFO. In the 20bit channel width SDI configuration, the receiver datapath also includes the byte deserializer.
Note: You must implement the SDI receiver functions, such as descrambling, framing, and CRC checker,
in the FPGA logic array.
Receiver Word Alignment and Framing
In SDI systems, the word aligner in the receiver datapath is not useful because the word alignment and
framing happen after descrambling. Altera recommends that you drive the rx_bitslip of the PHY
MegaWizard™ signal low to avoid having the word aligner insert bits in the received data stream.
Gigabit-Capable Passive Optical Network (GPON)
The GPON protocol network provides optical fiber cabling and signals to the home and office using a
point-to-multipoint scheme. GPON data rates of 155.52 Mbps, 622.08 Mbps, 1.24416 Gbps, and 2.48832
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Serial Data Converter (SDC) JESD204
Gbps, with a reference clock of 155.52 MHz are supported. The minimum supported data rate is 600 Mbps,
so a 5x oversampling factor is used for the GPON data rate of 155.52 Mbps, resulting in a data rate of 777.6
Mbps.
Note: You must build the oversampling at the PLD.
Figure 4-33: Configurations for the GPON Protocol
Configuration options for
data rates 155.52 Mbps,
622.08 Mbps, and 1.24416 Gbps
Configuration options for
data rates 1.24416 Gbps
and 2.48832 Gpbs
Single Width
Double Width
8-bit
16-bit
Functional Modes
Basic Single Width
8-bit PMA-PCS
Interface Width
Basic Double Width
16-bit PMA-PCS
Interface Width
Data Rate (Gbps)
0.7776 - 1.24416
Functional Modes
PMA-PCS Interface Width
Reference Clock (MHz)
1.24416 - 2.48832
38.88 - 622.08 @ 777.6 Mbps
31.104 - 622.08 @ 1.24416 Gbps
31.104 - 622.08 @ 1.24416 Gbps
49.76 - 622.08 @ 2.48832 Gbps
Channel Bonding
x1
x1
Low Latency PCS
Disabled
Disabled
Word Aligner (Pattern Length)
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Byte SERDES
Disabled
Disabled
Byte Ordering
Disabled
Disabled
8-bit
16-bit
97.2, 77.76,
155.52
77.76,
155.52
8B/10B Encoder/Decoder
Rate Match FIFO
FPGA Fabric-Transceiver
Interface Width
FPGA Fabric-Transceiver
Interface Frequency (MHz)
Serial Data Converter (SDC) JESD204
The SDC (JESD204) protocol conforms to JESD204, a JEDEC standard that enables a high-speed serial
connection between analog-to-digital converters and logic devices using only a two-wire high-speed serial
interface. SDC (JESD204) data rate ranges of 312.5 Mbps to 3.125 Gbps are supported. The minimum
supported data rate is 611 Mbps, so a 5x oversampling factor is used for the SDC (JESD204) data rate of
312.5 Mbps, resulting in a data rate of 1.5625 Gbps.
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Figure 4-34: Configurations for the SDC (JESD204) Protocol
Configuration option for
data rate range of
312.5 Mbps - 1.5625 Gbps
Single Width
Configuration option for
data rate range of
1.5625 Gbps - 3.125 Gpbs
Single Width
Functional Modes
10-bit
PMA-PCS Interface Width
Functional Modes
Data Rate (Gbps)
Channel Bonding
Word Aligner (Pattern Length)
8B/10B Encoder/Decoder
Basic Single-Width
10-bit PMA-PCS
Interface Width
1.5625
Basic Single-Width
10-bit PMA-PCS
Interface Width
1.5625 - 3.125
x1
x1
Enabled (Manual)
Enabled (Manual)
Enabled
Enabled
Disabled
Disabled
Byte SERDES
Disabled
Enabled
Byte Ordering
Disabled
Enabled
8-bit
16-bit
156.25
78.125 156.25
Rate Match FIFO
FPGA Fabric-Transceiver
Interface Width
FPGA Fabric-Transceiver
Interface Frequency (MHz)
SATA and SAS Protocols
Serial ATA (SATA) and Serial Attached SCSI (SAS) are data storage protocol standards that have the primary
function of transferring data (directly or otherwise) between the host system and mass storage devices, such
as hard disk drives, optical drives, and solid-state disks.
These serial storage protocols offer several advantages over older parallel storage protocol (ATA and SCSI)
interfaces:
•
•
•
•
Faster data transfer
Hot swapping (when supported by the operating system)
Thinner cables for more efficient air cooling
Increased operation reliability
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Table 4-9: Serial Data Rates for SATA and SAS Protocols
Protocol
SATA (Gbps)
SAS (Gbps)
Gen1
1.5
3.0
Gen2
3.0
6.0
Gen3
6.0
-
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Figure 4-35: Configurations for the SATA and SAS Protocols
If you are configuring the SATA channel to support up to Gen3, set the base data rate to 6 Gbps and use the
TX local clock divider to divide down to the Gen2 and Gen1 data rate.
Arria V Configurations
Basic
Functional Modes
Single
Width
Double
Width
PMA-PCS Interface
Width
10-Bit
20-Bit
Functional Modes
Basic Single-Width
10-Bit PMA-PCS
Interface Width
Basic Single-Width
10-Bit PMA-PCS
Interface Width
Basic Double-Width
20-Bit PMA-PCS
Interface Width
Basic Double-Width
20-Bit PMA-PCS
Interface Width
Basic Double-Width
20-Bit PMA-PCS
Interface Width
Data Rate (Gbps)
1.5
3.0
1.5
3.0
6.0
Reference Clock (MHz)
150
150
150
150
150
Channel Bonding
x1
x1
x1
x1
x1
Low Latency PCS
Disabled
Disabled
Disabled
Disabled
Disabled
Word Aligner
(Pattern Length)
Enabled
(Manual, 10-Bit)
Enabled
(Manual, 10-Bit)
Enabled
(Manual, 10-Bit)
Enabled
(Manual, 10-Bit)
Enabled
(Manual, 10-Bit)
8B/10B Encoder/
Decoder
Enabled
Enabled
Enabled
Enabled
Enabled
Rate Match FIFO
Disabled
Disabled
Disabled
Disabled
Disabled
Byte SERDES
Disabled
Enabled
Enabled
Disabled
Enabled
Disabled
Enabled
Enabled
Byte Ordering
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
FPGA Fabric-Transceiver
Interface Width
8-Bit
16-Bit
16-Bit
16-Bit
16-Bit
16-Bit
16-Bit
16-Bit
FPGA Fabric-Transceiver
Interface Frequency (MHz)
150
75
150
37.5
150
75
150
Configuration Option
for SATA/SAS
1.5 Gbps Data Rate
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Configuration Option
for SATA/SAS
3.0 Gbps Data Rate
75
Configuration Option
for SATA/SAS
1.5 Gbps Data Rate
Configuration Option
for SATA/SAS
3.0 Gbps Data Rate
Configuration Option
for SATA/SAS
6.0 Gbps Data Rate
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Deterministic Latency Protocols—CPRI and OBSAI
Deterministic Latency Protocols—CPRI and OBSAI
A deterministic latency option is available for use in high-speed serial interfaces such as the Common Public
Radio Interface (CPRI) and OBSAI Reference Point 3 (OBSAI RP3). Both CPRI and OBSAI RP3 protocols
place stringent requirements on the amount of latency variation that is permissible through a link that
implements these protocols.
Arria V GT devices also support 9.8304 Gbps CPRI with PMA direct configuration; PCS is implemented in
soft logic.
Figure 4-36: Transceiver Datapath in Deterministic Latency Mode
8B/10B Encoder
rdclk
CDR
Deserializer
Word Aligner
Deskew FIFO
Receiver Channel
PMA
Rate Match FIFO
8B/10B Decoder
Byte Deserializer
Byte Ordering
Receiver Channel PCS
rx_datain
wrclk
rdclk
Serializer
Byte Serializer
wrclk
RX Phase
Compensation
FIFO
PIPE Interface
PCIe hard IP
FPGA
Fabric
TX Phase
Compensation
FIFO
tx_dataout
Transmitter Channel
PMA
Transmitter Channel PCS
Transmitter Channel Datapath
Receiver Channel Datapath
Related Information
Implementing 9.8G CPRI in Arria V GT and ST FPGAs
Describes a soft PCS implementation for 9.8G CPRI.
Latency Uncertainty Removal with the Phase Compensation FIFO in Register Mode
To remove the latency uncertainty through the receiver's phase compensation FIFO, the receiver and
transmitter phase compensation FIFOs are always set to register mode. In register mode, the phase
compensation FIFO acts as a register and thereby removes the uncertainty in latency. The latency through
the transmitter and receiver phase compensation FIFO in register mode is one clock cycle.
The following options are available:
• Single-width mode with 8-bit channel width and 8B/10B encoder enabled or 10-bit channel width with
8B/10B disabled
• Double-width mode with 16-bit channel width and 8B/10B encoder enabled or 20-bit channel width with
8B/10B disabled
Channel PLL Feedback for Deterministic Relationship
To implement the deterministic latency functional mode, the phase relationship between the low-speed
parallel clock and channel PLL input reference clock must be deterministic. A feedback path is enabled to
ensure a deterministic relationship between the low-speed parallel clock and channel PLL input reference
clock.
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To achieve deterministic latency through the transceiver, the reference clock to the channel PLL must be
the same as the low-speed parallel clock. For example, if you need to implement a data rate of 1.2288 Gbps
for the CPRI protocol, which places stringent requirements on the amount of latency variation, you must
choose a reference clock of 122.88 MHz to allow the usage of a feedback path from the channel PLL. This
feedback path reduces the variations in latency.
When you select this option, provide an input reference clock to the channel PLL that has the same frequency
as the low-speed parallel clock.
CPRI and OBSAI
Use the deterministic latency functional mode to implement protocols such as CPRI and OBSAI.
The CPRI interface defines a digital point-to-point interface between the Radio Equipment Control (REC)
and the Radio Equipment (RE), allowing flexibility in either co-locating the REC and the RE, or a remote
location of the RE.
Figure 4-37: CPRI Topologies
In most cases, CPRI links are between REC and RE modules or between two RE modules in a chain
configuration.
RE
RE
RE
Ring
RE
RE
Tree and Branch
RE
REC
Radio Equipment
Control
RE
RE
Chain
Point-to-Point
RE
RE
If the destination for the high-speed serial data that leaves the REC is the first RE, it is a single-hop connection.
If the serial data from the REC must traverse through multiple REs before reaching the destination RE, it is
a multi-hop connection.
Remotely locating the RF transceiver from the main base station introduces a complexity with overall system
delay. The CPRI specification requires that the accuracy of measurement of roundtrip delay on single-hop
and multi-hop connections be within ±16.276 ns to properly estimate the cable delay.
For a single-hop system, this allows a variation in roundtrip delay of up to ±16.276 ns. However, for multihop systems, the allowed delay variation is divided among the number of hops in the connection—typically,
equal to ±16.276 ns/(the number of hops) but not always equally divided among the hops.
Deterministic latency on a CPRI link also enables highly accurate triangulation of the location of the caller.
OBSAI was established by several OEMs to develop a set of specifications that can be used for configuring
and connecting common modules into base transceiver stations (BTS).
The BTS has four main modules:
• Radio frequency (RF)
• Baseband
• Control
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CPRI and OBSAI
• Transport
In a typical BTS, the radio frequency module (RFM) receives signals using portable devices and converts
the signals to digital data. The baseband module processes the encoded signal and brings it back to the
baseband before transmitting it to the terrestrial network using the transport module. A control module
maintains the coordination between these three functions.
Figure 4-38: Example of the OBSAI BTS Architecture
System Software
Transport Module
RP2 (1)
Interface
Proprietary
Module(s)
Baseband
Module
RF Module
RP3 (1)
BB
Switch
Control
& Clock
RFM
Control
Module
Clock and Sync
RP1 (1)
Power System
(1) RP = Reference Point
Using the deterministic latency option, you can implement the CPRI data rates in the following modes:
• Single-width mode—with 8/10-bit channel width
• Double-width mode—with 16/20-bit channel width
Table 4-10: Sample Channel Width Options for Supported Serial Data Rates
Channel Width (FPGA-PCS Fabric)
Serial Data Rate (Mbps)
(35)
Single Width
Double-Width
8-Bit
16-Bit
16-Bit
32-Bit
614.4
Yes
Yes
No
No
1228.8
Yes
Yes
Yes
Yes
2457.6
No
Yes
Yes
Yes
3072
No
Yes
Yes
Yes
4915.2
No
No
No
Yes
6144
No
No
No
Yes
9830.4 (35)
N/A
N/A
N/A
N/A
CPRI 9830.4 Mbps uses PMA direct mode with 80-bits PMA-PLD data width and is available only in 10-Gbps
channels. For transmit jitter compliance, refer to the Transceiver Architecture in Arria V Devices chapter for
maximum channel conditions.
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Related Information
Transceiver Architecture in Arria V Devices
CPRI Enhancements
The deterministic latency state machine in the word aligner reduces the known delay variation from the
word alignment process and automatically synchronizes and aligns the word boundary by slipping a clock
cycle in the deserializer. Incoming data to the word aligner is aligned to the boundary of the word alignment
pattern (K28.5). User logic is not required to manipulate the TX bit slipper for constant round-trip delay.
In manual mode, the TX bit slipper is able to compensate one unit interval (UI).
The word alignment pattern (K28.5) position varies in byte deserialized data. Delay variation is up to ½
parallel clock cycle. You must add in extra user logic to manually check the K28.5 position in byte deserialized
data for the actual latency.
Figure 4-39: Deterministic Latency State Machine in the Word Aligner
Clock-slip Control
To 8B/10B Decoder
Deterministic Latency
Synchronization State Machine
From RX CDR
Deserializer
Word Aligner
Table 4-11: Methods to Achieve Deterministic Latency Mode in Arria V Devices
Existing Feature
Description
Manual alignment with bit
position indicator provides
deterministic latency. Delay
variation up to 1 parallel clock
cycle
(36)
Enhanced Feature
Requirement
Extra user logic to
manipulate the TX bit
slipper with a bit
position indicator
from the word aligner
for constant total
round-trip delay
Description
(37)
Requirement
Deterministic latency None
state machine
alignment reduces the
known delay variation
in word alignment
operation
Related Information
Refer to the "Deterministic Latency PHY IP Core" chapter in the Altera Transceiver PHY IP Core User
Guide
Serial RapidIO
The RapidIO Trade Association defines a high-performance, packet-switched interconnect standard to pass
data and control information between microprocessors, digital signal, communications, and network
processors, system memories, and peripheral devices.
(36)
(37)
Backward compatible with CPRI designs in Arria II devices.
Enhanced deterministic latency feature in Arria V devices.
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Serial RapidIO
Figure 4-40: Transceiver Datapath in Serial RapidIO (SRIO) Mode
FPGA Fabric
Transmitter Channel PMA
Transmitter Channel PCS
TX Phase
Compensation
FIFO
wrclk rdclk
Byte
Serializer
tx_coreclk[0]
8B/10B
Encoder
Serializer
High-Speed Serial Clock
/2
Low-Speed Parallel Clock
tx_clkout[0]
Local Clock
Divider
FPGA Fabric–Transceiver Interface Clock
RX Phase
Compensation
FIFO
Byte
Deserializer
Receiver Channel PCS
Rate
Word
Match
Aligner
FIFO
8B/10B
Decoder
Receiver Channel PMA
Deserializer
CDR
rx_coreclk[0]
/2
Parallel Recovered Clock
Low-Speed Parallel Clock
Arria V transceivers support SRIO physical layer specifications, versions 1.3 and 2.1, from 1.25 Gbps to 6.25
Gbps. The transceivers are compliant with x4 channel bonding, deskew state machine, and rate match FIFO.
Synchronization State Machine
The word aligner has a synchronization state machine that handles the receiver lane synchronization.
The synchronization state machine indicates synchronization when the receiver receives 127 K28.5
(10'b0101111100 or 10'b1010000011) synchronization code groups without receiving an intermediate invalid
code group. After synchronization, the state machine indicates loss of synchronization when it detects three
invalid code groups separated by less than 255 valid code groups, or when it is reset.
The rx_syncstatus port of each channel indicates the receiver synchronization:
• High—the lane is synchronized
• Low—the lane has fallen out of synchronization
Table 4-12: Synchronization State Machine Parameters in Serial RapidIO Mode
Parameters
Number
Number of valid K28.5 code groups received to achieve synchronization
Number of errors received to lose synchronization
127
3
Number of continuous good code groups received to reduce the error
count by one
255
Rate Match FIFO
In SRIO mode, the rate match FIFO is capable of compensating for up to ±100 ppm (200 ppm total) difference
between the upstream transmitter and the local receiver reference clock.
The rate match FIFO operation begins after the word aligner synchronization status, rx_syncstatus, goes
high. When the rate matcher receives either of the two 10-bit control patterns followed by the respective 10bit skip pattern, it inserts or deletes the 10-bit skip pattern as necessary to avoid the rate match FIFO from
overflowing or under-running.
In SRIO mode, the rate match FIFO can delete or insert a maximum of one skip pattern from a cluster.
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Related Information
Refer to “Chapter 4: PCS and PMA Layers” of Part 6: LP-Serial Physical Layer Specification in the
RapidIO Interconnect Specification
Document Revision History
Table 4-13: Document Revision History
Date
Version
Changes
March 2014
2014.03.07
• Updated the "Gigabit Ethernet" section.
• Updated the "Rate Match FIFO" section in the "Gigabit
Ethernet Transceiver Datapath" section.
• Updated the XAUI "Transceiver Channel Placement
Guidelines" section.
• Added link to external reference in the "Deterministic
Latency Protocols—CPRI and OBSAI" section.
May 2013
2013.05.06
• Added link to the known document issues in the
Knowledge Base.
• Added x2 information to the "PIPE Transceiver Channel
Placement Guidelines" section.
• Removed the "Receiver Electrical Idle Inference" section.
• Updated the figures in the "PCIe Supported Configurations and Placement Guidelines" section.
• Added the "Transceiver Clocking Guidelines for Soft
PCS Implementation" section.
March 2013
2013.03.15
• Removed references to x2 channel configuration.
• Changed references to the PCIe Specification to version
2.1.
• Updated Table 4-1.
• Updated Figure 4 -27.
• Updated the "XAUI" section.
• Updated the "XAUI Supported Features" section.
• Updated the "Transceiver Clocking and Channel
Placement Guidelines in XAUI Configuration" section.
• Updated the "10GBASE-R" section.
• Updated Figure 4-30.
• Updated Figure 4-31.
• Updated Figure 4-32.
• Updated the "10GBASE-R Supported Features" section.
• Updated the "10GBASE-R Transceiver Clocking"
section.
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Document Revision History
Date
Version
Changes
November 2012
2012.11.19
• Reorganized content and updated template.
• Added the "XAUI" section.
• Added the "PCI Express" section.
June 2012
1.2
• Updated for the Quartus II software version 12.0.
• Added the “Serial Digital Interface” section.
• Added the “Gigabit-Capable Passive Optical Network
(GPON)” section.
• Added the “Serial Data Converter (SDC) JESD204”
section.
• Added the “SATA and SAS Protocols” section.
• Updated Figure 4–2 and Figure 4–18.
• Added Figure 4–19.
• Updated Table 4–1, Table 4–8, and Table 4–9.
• Updated the “CPRI Enhancements in Arria V Devices”
section.
• Added the “Serial RapidIO” section.
November 2011
1.1
Updated for the Quartus II software version 11.1.
August 2011
1.0
Initial release.
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Transceiver Custom Configurations in Arria V
Devices
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For integration with the FPGA fabric, the full-duplex transceiver channel supports custom configuration
with physical medium attachment (PMA), physical coding sublayer (PCS), and low latency custom
configurations with the PMA and low latency PCS.
You can customize the transceiver with one of the following configurations:
• Standard PCS— Physical coding sublayer (PCS) and physical medium attachment (PMA)
• Standard PCS in low latency mode— Low latency PCS and PMA
• PMA Direct— PMA only
Figure 5-1: Custom Configuration Options
Up to 10.3125 Gbps in 10-Gbps channel
(in GT and ST device variants)
Up to 6.5536 Gbps with PCS (Standard PCS and low latency)
HIP
FPGA Fabric
PIPE
PCS
Transceiver Resources
PMA
tx_serial_data
rx_serial_data
Serial Interface
Related Information
Arria V Device Handbook: Known Issues
Lists the planned updates to the Arria V Device Handbook chapters.
Standard PCS Configuration
In this configuration, you can customize the transceiver channel to include a PMA and PCS with functions
that your application requires. The transceiver channel interfaces with the FPGA fabric through the PCS.
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and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other
words and logos identified as trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with
Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes
no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published
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9001:2008
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Custom Configuration Channel Options
Figure 5-2: Complete Datapath in a Custom Configuration
Based on your application requirements, you can enable, modify, or disable the blocks, as shown in the
following figure.
Byte Serializer
TX Bit Slip
TX Phase
Compensation
FIFO
FPGA Fabric
8B/10B Encoder
Transmitter PCS
Serializer
tx_seializer_data
Transmitter PMA
tx_parallel data
tx_coreclkin
Serial
Clock
tx_clkout
/2
rx_parallel data
rx_coreclkin
rx_clkout
/2
Serial Clock
Parallel Clock
Parallel Clock
RX Phase
Compensation
FIFO
Byte Ordering
Byte Deserializer
8B/10B Decoder
Rate Match FIFO
Word Aligner
Receiver PCS
Deserializer
CDR
rx_seializer_data
Receiver PMA
The serial and parallel clocks are
sourced from the clock divider.
Custom Configuration Channel Options
There are multiple channel options when you use Custom Configuration.
The supported interface width varies depending on the usage of the byte serializer/deserializer (SERDES),
and the 8B/10B encoder or decoder. The byte serializer or deserializer is assumed to be enabled. Otherwise,
the maximum data rate supported is half of the specified value.
The maximum supported data rate varies depending on the customization.
Table 5-1: Maximum Supported Data Rate for Fastest Speed Grade Device (–4 Commercial) in Custom
Configuration
The following table lists an example of the maximum supported data rate in various custom configurations with the
PMA and PCS using the fastest speed grade device.
Data Configuration
8B/10B Enabled
8
—
Single-width
10
Altera Corporation
PCS-FPGA Fabric Interface Width
PMA-PCS Interface
Width
8B/10B Disabled
Maximum Data Rate (Mbps)
8
1,500
16
3,000
8
10
1,875
16
20
3,750
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Custom Configuration Channel Options
Data Configuration
PCS-FPGA Fabric Interface Width
PMA-PCS Interface
Width
8B/10B Enabled
16
—
Double-width
20
8B/10B Disabled
5-3
Maximum Data Rate (Mbps)
16
2,621.44
32
5,242.88
16
20
3,276.8
32
40
6,553.6
In all the supported configuration options of the channel, the transmitter bit-slip function is optional,
where:
• The blocks shown as “Disabled” are not used but incur latency.
• The blocks shown as “Bypassed” are not used and do not incur any latency.
• The transmitter bit-slip is disabled.
Figure 5-3: Configuration Options for Custom Single-Width Mode (8-bit PMA–PCS Interface Width)
Manual Alignment
or Bit-Slip
Word Aligner (Pattern Length)
8B/10B Encoder/Decoder
Disabled
Rate Match FIFO
Disabled
Byte SERDES
Byte Ordering
FPGA Fabric–Transceiver
Interface Width
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Disabled
Enabled
Disabled
Enabled/Disabled
8-Bit
16-Bit
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Custom Configuration Channel Options
Figure 5-4: Configuration Options for Custom Single-Width Mode (10-bit PMA–PCS Interface Width)
Manual Alignment
or Bit-Slip
Word Aligner (Pattern Length)
Automatic Synchronization
State Machine
8B/10B Encoder/Decoder
Disabled
Enabled
Disabled
Enabled
Rate Match FIFO
Disabled
Disabled
Enabled/
Disabled
Enabled/
Disabled
Byte SERDES
Byte Ordering
FPGA Fabric–Transceiver
Interface Width
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled/
Disabled
Disabled
Enabled/
Disabled
Disabled
Enabled/
Disabled
Disabled
Enabled/
Disabled
10-Bit
20-Bit
8-Bit
16-Bit
10-Bit
20-Bit
8-Bit
16-Bit
Figure 5-5: Configuration Options for Custom Double-Width Mode (16-bit PMA–PCS Interface Width)
Manual Alignment
or Bit-Slip
Word Aligner (Pattern Length)
8B/10B Encoder/Decoder
Disabled
Rate Match FIFO
Disabled
Byte SERDES
Byte Ordering
FPGA Fabric–Transceiver
Interface Width
Altera Corporation
Disabled
Enabled
Disabled
Enabled/
Disabled
16-Bit
32-Bit
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Figure 5-6: Configuration Options for Custom Double-Width Mode (20-bit PMA–PCS Interface Width)
Manual Alignment
or Bit-Slip
Word Aligner (Pattern Length)
8B/10B Encoder/Decoder
Disabled
Enabled
Rate Match FIFO
Disabled
Disabled
Byte SERDES
Byte Ordering
FPGA Fabric–Transceiver
Interface Width
Disabled
Enabled
Disabled
Enabled
Disabled
Enabled/
Disabled
Disabled
Enabled/
Disabled
20-Bit
40-Bit
16-Bit
32-Bit
Rate Match FIFO in Custom Configuration
In a custom configuration, the 20-bit pattern for the rate match FIFO is user-defined. The FIFO operates
by looking for the 10-bit control pattern followed by the 10-bit skip pattern in the data, after the word aligner
restores the word boundary. After finding the pattern, the FIFO performs a skip pattern insertion or deletion
to ensure that the FIFO does not underflow or overflow a given parts per million (ppm) difference between
the clocks.
The rate match FIFO operation requires 8B/10B-coded data.
Rate Match FIFO Behaviors in Custom Single-Width Mode
The different operations available in custom single-width mode for the rate match FIFO are symbol insertion,
symbol deletion, full condition, and empty condition.
Table 5-2: Rate Match FIFO Behaviors in Custom Single-Width Mode (10-bit PMA–PCS Interface Width)
Operation
Behavior
Symbol Insertion
Inserts a maximum of four skip patterns in a cluster,
only if there are no more than five skip patterns in the
cluster after the symbol insertion.
Symbol Deletion
Deletes a maximum of four skip patterns in a cluster,
only if there is one skip pattern left in the cluster after
the symbol deletion.
Full Condition
Deletes the data byte that causes the FIFO to go full.
Empty Condition
Inserts a /K30.7/ (9'h1FE) after the data byte that
caused the FIFO to go empty.
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In this example, /K28.5/ is the control pattern and neutral disparity /K28.0/ is the skip pattern. The
first skip cluster has a /K28.5/ control pattern followed by two /K28.0/ skip patterns. The second
skip cluster has a /K28.5/ control pattern followed by four /K28.0/ skip patterns. The rate match
FIFO deletes only one /K28.0/ skip pattern from the first skip cluster to maintain at least one skip
pattern in the cluster after deletion. Two /K28.0/ skip patterns are deleted from the second cluster
for the three skip pattern deletion requirement.
Figure 5-7: Rate Match Deletion in Custom Single-Width Mode
The following figure shows an example of rate match FIFO deletion in the case where three skip
patterns are required to be deleted.
First Skip Cluster
datain
K28.5
K28.0
Second Skip Cluster
K28.0
K28.5
K28.0
K28.0
K28.0
K28.0
Three Skip
Patterns Deleted
dataout
K28.5
K28.0
K28.5
K28.0
K28.0
K28.0
rx_rmfifodatadeleted
In this example, /K28.5/ is the control pattern and neutral disparity /K28.0/ is the skip pattern. The
first skip cluster has a /K28.5/ control pattern followed by three /K28.0/ skip patterns. The second
skip cluster has a /K28.5/ control pattern followed by one /K28.0/ skip pattern. The rate match FIFO
inserts only two /K28.0/ skip patterns into the first skip cluster to maintain a maximum of five skip
patterns in the cluster after insertion. One /K28.0/ skip pattern is inserted into the second cluster
for a total of three skip patterns to meet the insertion requirement.
Figure 5-8: Rate Match Insertion in Custom Single-Width Mode
The following figure shows an example of rate match FIFO insertion in the case where three skip
patterns are required to be inserted.
First Skip Cluster
Second Skip Cluster
datain
K28.5
K28.0
K28.0
K28.0
K28.5
K28.0
K28.0
Dx.y
dataout
K28.5
K28.0
K28.0
K28.0
K28.0
K28.0
K28.5
K28.0
K28.0
K28.0
Dx.y
Three Skip
Patterns Inserted
rx_rmfifoinserted
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Figure 5-9: Rate Match FIFO Full Condition in Custom Single-Width Mode
The following figure shows the rate match FIFO full condition in custom single-width mode. The
rate match FIFO becomes full after receiving data byte D4.
datain
D1
D2
D3
D4
D5
D6
D7
D8
dataout
D1
D2
D3
D4
D6
D7
D8
xx
xx
xx
rx_rmfifofull
Figure 5-10: Rate Match FIFO Empty Condition in Custom Single-Width Mode
The following figure shows the rate match FIFO empty condition in custom single-width mode.
The rate match FIFO becomes empty after reading out data byte D3.
datain
D1
D2
D3
D4
D5
D6
dataout
D1
D2
D3
/K30.7/
D4
D5
rx_rmfifoempty
Rate Match FIFO Behaviors in Custom Double-Width Mode
The different operations available in custom double-width mode for the rate match FIFO are symbol insertion,
symbol deletion, full condition, and empty condition.
Table 5-3: Rate Match FIFO Behaviors in Custom Double-Width Mode (20-bit PMA–PCS Interface Width)
Operation
Behavior
Symbol Insertion
Inserts as many pairs (10-bit skip patterns at the
LSByte and MSByte of the 20-bit word at the same
clock cycle) of skip patterns as needed.
Symbol Deletion
Deletes as many pairs (10-bit skip patterns at the
LSByte and MSByte of the 20-bit word at the same
clock cycle) of skip patterns as needed.
Full Condition
Deletes the pair (20-bit word) of data bytes that causes
the FIFO to go full.
Empty Condition
Inserts a pair of /K30.7/ ({9'h1FE, 9'h1FE}) after the
data byte that causes the FIFO to go empty.
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Rate Match FIFO Behaviors in Custom Double-Width Mode
In this example, /K28.5/ is the control pattern and neutral disparity /K28.0/ is the skip pattern. The
first skip cluster has a /K28.5/ control pattern in the LSByte and /K28.0/ skip pattern in the MSByte
of a clock cycle followed by one /K28.0/ skip pattern in the LSByte of the next clock cycle. The rate
match FIFO cannot delete the two skip patterns in this skip cluster because they do not appear in
the same clock cycle. The second skip cluster has a /K28.5/ control pattern in the MSByte of a clock
cycle followed by two pairs of /K28.0/ skip patterns in the next two cycles. The rate match FIFO
deletes both pairs of /K28.0/ skip patterns (for a total of four skip patterns deleted) from the second
skip cluster to meet the three skip pattern deletion requirement.
Figure 5-11: Rate Match Deletion in Custom Double-Width Mode
The following figure shows an example of rate match FIFO deletion in the case where three skip
patterns are required to be deleted.
First Skip Cluster
Second Skip Cluster
datain[19:10]
Dx.y
K28.0
Dx.y
K28.5
K28.0
K28.0
Dx.y
datain[9:0]
Dx.y
K28.5
K28.0
Dx.y
K28.0
K28.0
Dx.y
Two Pairs of Skip Patterns Deleted
dataout[19:0]
Dx.y
K28.0
Dx.y
K28.0
Dx.y
dataout[9:0]
Dx.y
K28.5
K28.0
Dx.y
Dx.y
rx_rmfifodeleted
In this example, /K28.5/ is the control pattern and neutral disparity /K28.0/ is the skip pattern. The
first skip cluster has a /K28.5/ control pattern in the LSByte and /K28.0/ skip pattern in the MSByte
of a clock cycle followed by one /K28.0/ skip pattern in the LSByte of the next clock cycle. The rate
match FIFO inserts pairs of skip patterns in this skip cluster to meet the three skip pattern insertion
requirement.
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Figure 5-12: Rate Match Insertion in Custom Double-Width Mode
The following figure shows an example of rate match FIFO insertion in the case where three skip
patterns are required to be inserted.
First Skip Cluster
Second Skip Cluster
dataout[19:0]
Dx.y
K28.0
Dx.y
K28.5
K28.0
K28.0
dataout[9:0]
Dx.y
K28.5
Dx.y
Dx.y
K28.0
K28.0
datain[19:10]
Dx.y
K28.0
K28.0
K28.0
Dx.y
K28.5
K28.0
K28.0
datain[9:0]
Dx.y
K28.5
K28.0
K28.0
Dx.y
Dx.y
K28.0
K28.0
Two Pairs of Skip Patterns Inserted
rx_rmfifoinserted
Figure 5-13: Rate Match FIFO Full Condition in Custom Double-Width Mode
The following figure shows the rate match FIFO full condition in custom double-width mode. The
rate match FIFO becomes full after receiving the 20-bit word D5D6.
datain[19:10]
D2
D4
D6
D8
D10
D12
datain[9:0]
D1
D3
D5
D7
D9
D11
dataout[19:0]
D2
D4
D6
D10
D12
xx
dataout[9:0]
D1
D3
D5
D9
D11
xx
rx_rmfifofull
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Standard PCS in Low Latency Configuration
Figure 5-14: Rate Match FIFO Empty Condition in Custom Double-Width Mode
The following figure shows the rate match FIFO empty condition in custom double-width mode.
The rate match FIFO becomes empty after reading out the 20-bit word D5D6.
datain[19:10]
D2
D4
D6
D8
D10
D12
datain[9:0]
D1
D3
D5
D7
D9
D11
dataout[19:0]
D2
D4
D6
/K30.7/
D8
D10
dataout[9:0]
D1
D3
D5
/K30.7/
D7
D9
rx_rmfifoempty
Standard PCS in Low Latency Configuration
In this configuration, you can customize the transceiver channel to include a PMA and PCS that bypasses
most of the PCS logical functionality for a low latency datapath.
To provide a low latency datapath, the PCS includes only the phase compensation FIFO in phase
compensation mode, and optionally, the byte serializer and byte deserializer blocks, as shown in the following
figure. The transceiver channel interfaces with the FPGA fabric through the PCS.
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Low Latency Custom Configuration Channel Options
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Figure 5-15: Datapath in Low Latency Custom Configuration
Byte Serializer
TX Bit Slip
TX Phase
Compensation
FIFO
FPGA Fabric
8B/10B Encoder
Transmitter PCS
Serializer
tx_seializer_data
Transmitter PMA
tx_parallel data
tx_coreclkin
Serial
Clock
tx_clkout
/2
RX Phase
Compensation
FIFO
Byte Ordering
Byte Deserializer
8B/10B Decoder
Rate Match FIFO
Receiver PCS
Word Aligner
Deserializer
CDR
rx_seializer_data
Receiver PMA
rx_coreclkin
rx_clkout
/2
Parallel Clock
rx_parallel data
Serial Clock
Parallel Clock
The serial and parallel clocks are
sourced from the clock divider.
The maximum supported data rate varies depending on the customization and is identical to the custom
configuration except that the 8B/10B block is disabled
Low Latency Custom Configuration Channel Options
There are multiple channel options when you use Low Latency Custom Configuration.
In the following figures:
• The blocks shown as “Disabled” are not used but incur latency.
• The blocks shown as “Bypassed” are not used and do not incur any latency.
• The transmitter bit-slip is disabled.
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Low Latency Custom Configuration Channel Options
Figure 5-16: Configuration Options for Low Latency Custom Single-Width Mode (8-bit PMA–PCS
Interface Width)
Word Aligner (Pattern Length)
Disabled
8B/10B Encoder/Decoder
Disabled
Rate Match FIFO
Bypassed
Byte SERDES
Byte Ordering
FPGA Fabric–Transceiver
Interface Width
Bypassed
Enabled
Bypassed
Bypassed
8-Bit
16-Bit
Figure 5-17: Configuration Options for Low Latency Custom Single-Width Mode (10-bit PMA–PCS
Interface Width)
Word Aligner (Pattern Length)
Disabled
8B/10B Encoder/Decoder
Disabled
Rate Match FIFO
Bypassed
Byte SERDES
Byte Ordering
FPGA Fabric–Transceiver
Interface Width
Altera Corporation
Bypassed
Enabled
Bypassed
Bypassed
10-Bit
20-Bit
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PMA Direct
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Figure 5-18: Configuration Options for Low Latency Custom Double-Width Mode (16-bit PMA–PCS
Interface Width)
Word Aligner (Pattern Length)
Disabled
8B/10B Encoder/Decoder
Disabled
Rate Match FIFO
Bypassed
Byte SERDES
Byte Ordering
FPGA Fabric–Transceiver
Interface Width
Bypassed
Enabled
Bypassed
Bypassed
16-Bit
32-Bit
Figure 5-19: Configuration Options for Low Latency Custom Double-Width Mode (20-bit PMA–PCS
Interface Width)
Word Aligner (Pattern Length)
Disabled
8B/10B Encoder/Decoder
Disabled
Rate Match FIFO
Bypassed
Byte SERDES
Byte Ordering
FPGA Fabric–Transceiver
Interface Width
Bypassed
Enabled
Bypassed
Bypassed
20-Bit
40-Bit
PMA Direct
You can customize the transceiver channel to include only the PMA, in a PMA Direct configuration for
serial data rates up to 10.3125 Gbps.
In this configuration, the serializer and deserializer interface directly to the FPGA fabric, bypassing the PCS.
The serializer and deserializer support 8-, 10-, 16-, 20-, 64-, and 80-bit configurations. You must implement
the PCS functions in the FPGA fabric.
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Document Revision History
Figure 5-20: Transceiver Datapath in a PMA Direct Configuration
Transmitter PMA
Receiver PMA
Transmitter PCS
FPGA Fabric
Receiver PCS
Document Revision History
Table 5-4: Document Revision History
Date
Version
Changes
March 2014
2014.03.07
Updated "Maximum Supported Data
Rate for Fastest Speed Grade Device
(–4 Commercial) in Custom
Configuration" table.
May 2013
2013.05.06
Added link to the known document
issues in the Knowledge Base.
November 2012
2012.11.19
Reorganized content and updated
template.
June 2012
1.2
• Updated for the Quartus II
software version 12.0.
• Updated the “PCS Datapath
Latency” section.
• Updated the “PMA Direct
Configuration” section.
• Updated Figure 5–1 and Figure
5–14.
November 2011
1.1
Updated for the Quartus II software
version 11.1.
August 2011
1.0
Initial release.
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Transceiver Configurations in Arria V GZ Devices
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Arria® V GZ devices have a dedicated transceiver physical coding sublayer (PCS) and physical medium
attachment (PMA) circuitry.
To implement a protocol, use a PHY IP listed in Table 6-12.
Arria V GZ devices support the following communication protocols:
•
•
•
•
•
10GBASE-R and 10GBASE-KR
Interlaken
PCI Express® (PCIe®)—Gen1, Gen2, and Gen3
CPRI and OBSAI—Deterministic Latency Protocols
XAUI
Support for other communication protocols or user-defined protocols can be enabled with the following
PHY IPs:
• Native PHY IP using standard PCS and 10G PCS hardware options including reconfigurability between
different PCS options
• Custom PHY IP using the standard PCS in a custom datapath
• Low Latency PHY IP using the standard or 10G PCS in a low latency datapath configuration
Related Information
• Arria V Device Handbook: Known Issues
Lists the planned updates to the Arria V Device Handbook chapters.
• Upcoming Arria V Device Features
• Altera Transceiver PHY IP Core User Guide
10GBASE-R and 10GBASE-KR
10GBASE-R is used in optical module LAN applications such as optical routers, servers, and switches, and
10GBASE-KR is used in electrical backplane applications such as blade servers using Arria V GZ transceivers.
10GBASE-R is a specific physical layer implementation of the 10 Gigabit Ethernet link defined in clause 49
of the IEEE 802.3-2008 specification. The 10GBASE-R PHY uses the XGMII interface to connect to the
IEEE802.3 media access control (MAC) and reconciliation sublayer (RS). The IEEE 802.3-2008 specification
© 2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words
and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other
words and logos identified as trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance with
Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes
no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly
agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published
information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
Registered
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10GBASE-R and 10GBASE-KR
requires each 10GBASE-R link to support a 10 Gbps data rate at the XGMII interface and a 10.3125 Gbps
serial line rate with 64B/66B encoding.
Figure 6-1: 10GBASE-R PHY Connection to IEEE802.3 MAC and RS
LAN
CSMA/CD
LAYERS
Higher Layers
LLC (Logical Link Control) or other MAC Client
OSI
Reference
Model
Layers
MAC Control (Optional)
Media Access Control (MAC)
Reconciliation
Application
Presentation
32-bit data, 4-bit control (DDR @ 156.25 MHz)
XGMII
Session
10GBASE-R PCS
Transport
Network
10GBASE-R
PHY
Serial PMA
PMD
Data Link
Physical
10.3125 Gbps
MDI
Medium
10GBASE-LR, -SR, -ER, or -lRM
Note: In the MegaWizard™ Plug-In Manager, you can implement a 10GBASE-R link by instantiating the
10GBASE-R PHY IP core under Ethernet in the Interfaces menu.
The IEEE 802.3ap-2007 specification also requires each backplane link to support multi-data rates of 1Gbps
and 10 Gbps speeds. 10GBASE-KR and 1000BASE-KX is the electrical backplane physical layer implementation for the 10 Gigabit and 1 Gigabit Ethernet link defined in clause 72 and clause 70 respectively of the
IEEE 802.3ap-2007 specification. The 10 Gbps backplane ethernet 10GBASE-KR implementation uses the
XGMII interface to connect to the reconciliation sublayer (RS) with 64B/66B PCS encoding, the optional
Forward Error Correction (FEC), and Auto-Negotiation (AN) support to the Highest Common Denominator
(HCD) technology with the partner link. The optional FEC, LT, and AN logic is implemented in the core
fabric. The 1Gbps backplane ethernet 1000BASE-KX implementation uses the GMII interface to connect
to the reconciliation sublayer (RS) with 8B/10B PCS encoding and Auto-Negotiation support to the HCD
technology with the partner link.
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6-3
Figure 6-2: 10GBASE-KR PHY Connection to IEEE802.3 MAC and RS
LAN
CSMA/CD
LAYERS
Higher Layers
LLC (Logical Link Control) or other MAC Client
OSI
Reference
Model
Layers
MAC Control (Optional)
Media Access Control (MAC)
Reconciliation
Application
Presentation
GMII
XGMII
XGMII
64B/66B PCS
Session
Transport
Network
Data Link
Physical
8B/10B PCS
8B/10B PCS
FEC
PMA
PMA
PMA
PMD
PMD
PMD
AN
AN
AN
MDI
MDI
PHY
MDI
Medium
Medium
Medium
1000BASE-KX
10GBASE-KX4
10GBASE-KR
Note: In the MegaWizard Plug-In Manager, you can implement a 10GBASE-KR link with 1000BASE-KX
support by instantiating the 1G/10GbE and 10GBASE-KR PHY IP Core under the Ethernet in the
Interfaces menu.
An Altera license is required in order to use the 1G/10GbE and 10GBASE-KR PHY IP Core which also
supports 10GBASE-R and 1000BASE-X links and auto-negotiation between the 10 Gigabit and 1 Gigabit
Ethernet data rates.
Related Information
• Altera Transceiver PHY IP Core User Guide
• 10-Gbps Ethernet MAC MegaCore Function User Guide
10GBASE-R and 10GBASE-KR Transceiver Datapath Configuration
The following figures show the transceiver blocks and settings enabled in 10GBASE-R and 10GBASE-KR
configurations.
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10GBASE-R
Figure 6-3: 10GBASE-R Datapath Configuration
The blocks shown as "Disabled" are not used, but incur latency. The blocks shown as "Bypassed" are not used
and do not incur latency.
Transceiver PHY IP
Lane Data Rate
10.3125 Gbps
Number of Bonded Channels
None
PCS-PMA Interface Width
40-Bit
Gear Box
Block Synchronizer
Disparity Generator/Checker
Scrambler, Descrambler (Mode)
Enabled (66:40 Ratio)
Enabled
Bypassed
Enabled
(Self Synchronous Mode)
64B/66B Encoder/Decoder
Enabled
BER Monitor
Enabled
CRC32 Generator, Checker
Frame Generator, Synchronizer
Bypassed
Bypassed
RX FIFO (Mode)
Enabled
(Clock Compensation Mode)
TX FIFO (Mode)
Enabled
(Phase Compensation Mode)
TX/RX 10G PCS Latency (Parallel Clock Cycles)
Altera Corporation
10GBASE-R PHY IP
TX: 8-12
RX: 15-34
FPGA Fabric-to-Transceiver
Interface Width
64-bit Data
8-bit Control
FPGA Fabric-to-Transceiver
Interface Frequency
156.25 MHz
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Figure 6-4: Transceiver Channel Datapath for a 10GBASE-R Configuration
64-Bit Data
8-Bit Control
66
tx_serial_data
TX Gear Box
66
Disparity
Generator
Scrambler
64B/66B Encoder
and TX SM
xgmii_tx_clk
(156.25MHz)
(from core)
CRC32
Generator
Frame Generator
TX
FIFO
64-Bit Data
8-Bit Control
Transmitter PMA
Serializer
Transmitter 10G PCS
FPGA
Fabric
40
Parallel Clock (257.8125 MHz)
BER
Monitor
rx_coreclkin
CDR
40
rx_serial_data
Receiver PMA
Deserializer
RX Gear Box
Block Synchronizer
Disparity Checker
De-Scrambler
66
Frame Synchronizer
64-Bit Data
8-Bit Control
64B/66B Decoder
and RX SM
CRC32
Checker
64-Bit
Data
8-Bit
Control
RX FIFO
Receiver 10G PCS
Parallel Clock (Recovered) (257.8125 MHz)
Div 40
xgmii_rx_clk
(156.25MHz)
Parallel and Serial Clocks
(Only from the Central Clock Divider)
fPLL
Central/ Local Clock Divider
Input
Reference
Clock
CMU PLL
Clock Divider
Parallel Clock
Serial Clock
(From the ×1 Clock Lines)
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Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
Parallel and Serial Clock
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10GBASE-R and 10GBASE-KR Transceiver Datapath Configuration
10GBASE-KR
Figure 6-5: 10GBASE-R/KR and 1000Base-X/KX Datapath Configuration
Transceiver PHY IP
Link
Link
10GBASE-R/KR
1000BASE-X/KX
10.3125 Gbps
1.25 Gbps
None
None
10G PCS
Standard PCS
40-Bit
10-Bit
Enabled (66:40 Ratio)
Bypassed
Enabled
Automatic Synchronization
State Machine (7-Bit Comma,
10-Bit/K28.5/)
Bypassed
Enabled
Enabled
(Self Synchronous Mode)
Bypassed
Deskew FIFO
64B/66B Encoder/Decoder
Enabled
Enabled
8B/10B Encoder/Decoder
BER Monitor
Enabled
Disabled
Byte Serializer, Deserializer
Bypassed
Disabled
Bypassed
Enabled
RX FIFO (Mode)
Enabled
(Clock Compensation Mode)
Enabled
(Phase Compensation Mode)
RX FIFO (Mode)
TX FIFO (Mode)
Enabled
(Phase Compensation Mode)
Enabled
(Phase Compensation Mode)
TX FIFO (Mode)
TX: 8-12
RX: 15-34
TX: 5-6
RX: 20-24
FPGA Fabric-to-Transceiver
Interface Width
64-bit Data
8-bit Control
8-bit Data
1-bit Control
FPGA Fabric-to-Transceiver
Interface Width
FPGA Fabric-to-Transceiver
Interface Frequency - XGMII Clock
156.25 MHz
125.00 MHz
FPGA Fabric-to-Transceiver
Interface Frequency - GMII Clock
Lane Data Rate
Number of Bonded Channels
PCS Datapath
PCS-PMA Interface Width
Gear Box
Block Synchronizer
Disparity Generator/Checker
Scrambler, Descrambler (Mode)
CRC32 Generator, Checker
Frame Generator, Synchronizer
TX/RX 10G PCS Latency
(Parallel Clock Cycles)
Altera Corporation
Transceiver PHY IP
1G/10Gbe and 10GBASE-KR
Lane Data Rate
Number of Bonded Channels
PCS Datapath
PCS-PMA Interface Width
TX Bitslip
Word Aligner (Pattern Length)
Run Length Violation Checker
Byte Ordering
Rate Match FIFO
TX/RX Standard PCS Latency
(Parallel Clock Cycles)
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10GBASE-R and 10GBASE-KR Supported Features
Figure 6-6: Transceiver Channel Datapath for 10GBASE-R/KR and 1000BASE-X/KX Configuration
Transmitter 10G PCS
66
TX Gear Box
and Bitslip
Disparity
Generator
Scrambler
64B/66B Encoder
and TX SM
CRC32
Generator
TX
FIFO
64-bit data
8-bit control
xgmii_tx_clk
(156.25 MHz)
from Core
Frame Generator
FPGA
Fabric
Transmitter PMA
40
TX Bit Slip
TX Phase
Compensation
FIFO
Byte Serializer
8B/10B Encoder
Serializer
Transmitter Standard PCS
8-bit data and
GMII controls
tx_serial_data
tx_clkout_10g
tx_coreclkin_10g
10
tx_coreclkin_lg
/2
tx_clkout_lg
Receiver PMA
RX Gear Box
Block Synchronizer
Disparity Checker
De-Scrambler
Frame Synchronizer
64B/66B Decoder
and RX SM
CRC32
Checker
64-bit data
8-bit control
RX
FIFO
xgmii_rx_clk (156.25 MHz)
Receiver 10G PCS
66
40
rx_clkout_lg
Word Aligner
Deskew FIFO
Rate Match FIFO
Byte
Deserializer
Byte Ordering
8B/10B Decoder
rx_coreclkin_lg
RX Phase
Compensation
FIFO
8-bit data and
GMII status
rx_serial_data
Receiver Standard PCS
fractional
PLL
CDR
Deserializer
BER
Monitor
rx_coreclkin_l0g
10
/2
Parallel and Serial Clocks
(Only from the Central Clock Divider)
rx_recovered_clk
10G Input
Reference Clock
1G Input
Reference Clock
Central/ Local Clock Divider
CMU PLL,
ATX PLL,
or both PLLs
Clock Divider
Parallel Clock
Serial Clock
(From the ×1 Clock Lines)
Serial Clock
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
Parallel and Serial Clock
10GBASE-R and 10GBASE-KR Supported Features
The following features are supported by the transceivers in 10GBASE-R and 10GBASE-KR configurations.
64-Bit Single Data Rate (SDR) Interface to the MAC/RS in 10GBASE-R and 10GBASE-KR Configurations
Clause 46 of the IEEE 802.3-2008 specification defines the XGMII interface between the 10GBASE-R and
10GBASE-KR PCS and the Ethernet MAC/RS. The XGMII interface defines the 32-bit data and 4-bit wide
control character clocked between the MAC/RS and the PCS at both the positive and negative edge (double
data rate – DDR) of the 156.25 MHz interface clock.
The transceivers do not support the XGMII interface to the MAC/RS as defined in the IEEE 802.3-2008
specification. Instead, they support a 64-bit data and 8-bit control SDR interface between the MAC/RS and
the PCS.
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Figure 6-7: XGMII Interface (DDR) versus Arria V GZ Transceiver Interface (SDR) for 10GBASE-R and
10GBASE-KR Configurations
XGMII Transfer (DDR)
Interface Clock (156.25) MHz
TXD/RXD[31:0]
D0
D1
D2
D3
D4
D5
D6
TXC/RXC[3:0]
C0
C1
C2
C3
C4
C5
C6
Transceiver Interface (SDR)
Interface Clock (156.25) MHz
TXD/RXD[63:0]
{D1, D0}
{D3, D2}
{D5, D4}
TXC/RXC[7:0]
{C1, C0}
{C3, C2}
{C5, C4}
64B/66B Encoding/Decoding in 10GBASE-R and 10GBASE-KR Configurations
The transceivers in 10GBASE-R and 10GBASE-KR configurations support 64B/66B encoding and decoding
as specified in Clause 49 of the IEEE802.3-2008 specification. The 64B/66B encoder receives 64-bit data and
8-bit control code from the transmitter FIFO and converts it into 66-bit encoded data. The 66-bit encoded
data contains two overhead sync header bits that the receiver PCS uses for block synchronization and biterror rate (BER) monitoring.
The 64B/66B encoding also ensures enough transitions on the serial data stream for the receiver clock data
recovery (CDR) to maintain its lock on the incoming data.
Transmitter and Receiver State Machines in 10GBASE-R and 10GBASE-KR Configurations
The transceivers in 10GBASE-R and 10GBASE-KR configurations implement the transmitter and receiver
state diagrams shown in Figure 49-14 and Figure 49-15 of the IEEE802.3-2008 specification.
Besides encoding the raw data specified in the 10GBASE-R and 10GBASE-KR PCS, the transmitter state
diagram performs functions such as transmitting local faults (LBLOCK_T) under reset, as well as transmitting
error codes (EBLOCK_T) when the 10GBASE-R PCS rules are violated.
Besides decoding the incoming data specified in the 10GBASE-R and 10GBASE-KR PCS, the receiver state
diagram performs functions such as sending local faults (LBLOCK_R) to the MAC/RS under reset and
substituting error codes (EBLOCK_R) when the 10GBASE-R and 10GBASE-KR PCS rules are violated.
Block Synchronizer in 10GBASE-R and 10GBASE-KR Configurations
The block synchronizer in the receiver PCS determines when the receiver has obtained lock to the received
data stream. It implements the lock state diagram shown in Figure 49-12 of the IEEE 802.3-2008 specification.
The block synchronizer provides a status signal to indicate whether it has achieved block synchronization
or not.
Self-Synchronous Scrambling/Descrambling in 10GBASE-R and 10GBASE-KR Configurations
The scrambler/descrambler blocks in the transmitter/receiver PCS implements the self-synchronizing
scrambler/descrambler polynomial 1 + x39 + x58, as described in clause 49 of the IEEE 802.3-2008 specifi-
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cation. The scrambler/descrambler blocks are self-synchronizing and do not require an initialization seed.
Barring the two sync header bits in each 66-bit data block, the entire payload is scrambled or descrambled.
BER Monitor in 10GBASE-R and 10GBASE-KR Configurations
The BER monitor block in the receiver PCS implements the BER monitor state diagram shown in Figure
49-13 of the IEEE 802.3-2008 specification. The BER monitor provides a status signal to the MAC whenever
the link BER threshold is violated.
The 10GBASE-R core and the 1G/10GbE and 10GBASE-KR PHY IP core (10GBASE-KR mode) provide a
status flag to indicate a high BER whenever 16 synchronization header errors are received within a 125 μs
window.
Clock Compensation in 10GBASE-R and 10GBASE-KR Configurations
The receiver FIFO in the receiver PCS datapath compensates up to ±100 ppm difference between the remote
transmitter and the local receiver. The receiver FIFO does so by inserting Idles (/I/) and deleting Idles (/I/)
or Ordered Sets (/O/), depending on the ppm difference.
• Idle Insertion — The receiver FIFO inserts eight /I/ codes following an /I/ or /O/ to compensate for clock
rate disparity.
• Idle (/I/) or Sequence Ordered Set (/O/) Deletion — The receiver FIFO deletes either four /I/ codes or
ordered sets (/O/) to compensate for the clock rate disparity. The receiver FIFO implements the following
IEEE802.3-2008 deletion rules:
• Deletes the lower four /I/ codes of the current word when the upper four bytes of the current word
do not contain a Terminate /T/ control character.
• Deletes one /O/ ordered set only when the receiver FIFO receives two consecutive /O/ ordered sets.
10GBASE-KR and 1000BASE-KX Link Training
The Link Training function defined in clause 72 of IEEE 802.3ap-2007 specification is implemented in the
core fabric. The 1G/10GbE and 10GBASE-KR PHY IP Link Training logic includes the Training Frame
Generator, Training Frame Synchronizer, PRBS11 generator, control channel codec, Local Device (LD)
transceiver transmit PMA pre-emphasis coefficient status reporting, the Link Partner (LP) transmit PMA
pre-emphasis coefficient update request, and the receiver link training status.
Arria V GZ channels employ three PMA transmit driver pre-emphasis taps: pre-tap, main tap, and first posttap as required and defined by clause 72, Section 72.7.1.10 Transmitter output waveform for 10GBASE-KR
PHY operation. The pre-emphasis coefficients is dynamically adjusted by the PHY IP during the Link
Training process.
10GBASE-KR and 1000BASE-KX Auto-Negotiation
The Auto-Negotiation function defined in clause 73 of IEEE 802.3ap-2007 specification must be implemented
in the core fabric. The 1G/10GbE and 10GBASE-KR PHY IP Auto-Negotiation logic includes the Differential
Manchester Encoding (DME) page codec, AN page lock and synchronizer, and the Transmit, Receive, and
Arbitration logic state machines.
10GBASE-KR Forward Error Correction
The FEC function defined in clause 74 of IEEE 802.3ap-2007 specification must be implemented in the core
fabric. In Arria V GZ devices, the hard PCS does not support applications that require FEC functionality.
To implement a 10GBASE-KR link with FEC support, the entire PCS functionality and the FEC logic must
be implemented in the core fabric and the transceiver configured in Low Latency Configuration using the
Native PHY IP.
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1000BASE-X and 1000BASE-KX Transceiver Datapath
Related Information
Native PHY IP Configuration on page 6-79
1000BASE-X and 1000BASE-KX Transceiver Datapath
The following figure shows the transceiver datapath and clock frequencies in 1000BASE-X and 1000BASE-KX
configurations.
Figure 6-8: 1000BASE-X and 1000BASE-KX Datapath Configurations
Transmitter Standard PCS
tx_coreclkin_1g
Serializer
TX Bit Slip
tx_serial_data
Transmitter PMA
8B/10B Encoder
TX Phase
Compensation
FIFO
Byte Serializer
FPGA
Fabric
(125 MHz)
/2
tx_clkout_1g
rx_serial_data
CDR
Deserializer
Word Aligner
Deskew FIFO
Receiver PMA
Rate Match FIFO
8B/10B Decoder
Byte
Deserializer
Byte Ordering
rx_coreclkin_1g
RX Phase
Compensation
FIFO
Receiver Standard PCS
(125 MHz)
rx_clkout_1g
/2
Parallel and Serial Clocks
(Only from the Central Clock Divider)
Central/ Local Clock Divider
CMU PLL
Clock Divider
Parallel Clock
Serial Clock
(From the ×1 Clock Lines)
Serial Clock
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
Parallel and Serial Clock
1000BASE-X and 1000BASE-KX Supported Features
The following features are supported by the transceivers in 1000BASE-X and 1000BASE-KX configurations.
8B/10B Encoder in 1000BASE-X and 1000BASE-KX Configurations
In 1000BASE-X and 1000BASE-KX modes, the 8B/10B encoder clocks in 8-bit data and 1-bit control
identifiers from the transmitter phase compensation FIFO and generates 10-bit encoded data. The 10-bit
encoded data is fed to the serializer.
Idle Ordered-Set Generation in 1000BASE-X and 1000BASE-KX Configurations
The IEEE 802.3 specification requires the 1000BASE-X and 1000BASE-KX PHY to transmit idle ordered
sets (/I/) continuously and repetitively whenever the GMII is idle. This ensures that the receiver maintains
bit and word synchronization whenever there is no active data to be transmitted.
In 1000BASE-X and 1000BASE-KX functional modes, any /Dx.y/ following a /K28.5/ comma is replaced by
the transmitter with either a /D5.6/ (/I1/ ordered set) or a /D16.2/ (/I2/ ordered set), depending on the
current running disparity. The exception is when the data following the /K28.5/ is /D21.5/ (/C1/ ordered
set) or /D2.2/ (/C2/) ordered set. If the running disparity before the /K28.5/ is positive, an /I1/ ordered set
is generated. If the running disparity is negative, a /I2/ ordered set is generated. The disparity at the end of
a /I1/ is the opposite of that at the beginning of the /I1/. The disparity at the end of a /I2/ is the same as the
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beginning running disparity (right before the idle code). This ensures a negative running disparity at the
end of an idle ordered set. A /Kx.y/ following a /K28.5/ is not replaced.
Note: /D14.3/, /D24.0/, and /D15.8/ are replaced by /D5.6/ or /D16.2/ (for /I1/, /I2/ ordered sets). /D21.5/
(part of the /C1/ order set) is not replaced.
Figure 6-9: Example of Automatic Ordered Set Generation
clock
tx_datain [ ]
K28.5
D14.3
K28.5
D24.0
K28.5
D15.8
K28.5
D21.5
Dx.y
tx_dataout
Dx.y
K28.5
D5.6
K28.5
D16.2
K28.5
D16.2
K28.5
D21.5
/I1/
Ordered Set
/I2/
/I2/
/C2/
Reset Condition in 1000BASE-X and 1000BASE-KX Configurations
After deassertion of tx_digitalreset, the 1000BASE-X and 1000BASE-KX transmitters automatically
transmit three /K28.5/ comma code groups before transmitting user data on the tx_datain port. This could
affect the synchronization state machine behavior at the receiver.
Depending on when you start transmitting the synchronization sequence, there could be an even or odd
number of /Dx.y/ code groups transmitted between the last of the three automatically sent /K28.5/ code
groups and the first /K28.5/ code group of the synchronization sequence. If there is an even number of /Dx.y/
code groups received between these two /K28.5/ code groups, the first /K28.5/ code group of the synchronization sequence begins at an odd code group boundary (rx_even = FALSE). An IEEE802.3-compliant
1000BASE-X or 1000BASE-KX synchronization state machine treats this as an error condition and goes
into the loss of sync state.
The following figure shows an example of even numbers of /Dx.y/ between the last automatically sent /K28.5/
and the first user-sent /K28.5/. The first user-sent /K28.5/ code group received at an odd code group boundary
in cycle n + 3 takes the receiver synchronization state machine in the loss of sync state. The first synchronization ordered set /K28.5/Dx.y/ in cycles n + 3 and n + 4 is discounted and three additional ordered sets are
required for successful synchronization.
Figure 6-10: Example of Reset Condition in 1000BASE-X and 1000BASE-KX Configurations
n
n+1
n+2
n+3
n+4
Dx.y
Dx.y
K28.5
Dx.y
clock
tx_digitalreset
tx_dataout
K28.5
xxx
K28.5
K28.5
K28.5
K28.5
Dx.y
K28.5
Dx.y
Rate Match FIFO in 1000BASE-X and 1000BASE-KX Configurations
In 1000BASE-X and 1000BASE-KX modes, the rate match FIFO is capable of compensating for up to ±100
ppm (200 ppm total) difference between the upstream transmitter and the local receiver reference clock.
The 1000BASE-X and 1000BASE-KX protocols require the transmitter to send idle ordered sets /I1/
(/K28.5/D5.6/) and /I2/ (/K28.5/D16.2/) during inter-packet gaps adhering to the rules listed in the IEEE
802.3 specification.
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The rate match operation begins after the synchronization state machine in the word aligner indicates
synchronization is acquired by driving the rx_syncstatus signal high. The rate matcher deletes or inserts
both symbols (/K28.5/ and /D16.2/) of the /I2/ ordered sets even if it requires deleting only one symbol to
prevent the rate match FIFO from overflowing or under-running. It can insert or delete as many /I2/ ordered
sets as necessary to perform the rate match operation.
The following figure shows an example of rate match FIFO deletion where three symbols are required to be
deleted. Because the rate match FIFO can only delete /I2/ ordered set, it deletes two /I2/ ordered sets (four
symbols deleted).
Figure 6-11: Example of Rate Match Deletion in 1000BASE-X and 1000BASE-KX Configurations
/I2/ SKIP Symbol Deleted
First /I2/ Skip Ordered Set
Second /I2/ Skip Ordered Set
datain
Dx.y
K28.5
D16.2
K28.5
dataout
Dx.y
K28.5
D16.2
Dx.y
D16.2
Third /I2/ Skip Ordered Set
K28.5
D16.2
Dx.y
rx_rmfifodatadeleted
The following figure shows an example of rate match FIFO insertion in the case where one symbol is required
to be inserted. Because the rate match FIFO can only delete /I2/ ordered set, it inserts one /I2/ ordered set
(two symbols inserted).
Figure 6-12: Example Rate Match Insertion in 1000BASE-X and 1000BASE-KX Configurations
First /I2/ Ordered Set
Second /I2/ Ordered Set
datain
Dx.y
K28.5
D16.2
K28.5
D16.2
dataout
Dx.y
K28.5
D16.2
K28.5
D16.2
K28.5
D16.2
Dx.y
rx_rmfifodatainserted
Two register bits, rx_rmfifodatadeleted and rx_rmfifodatainserted, indicate rate match FIFO deletion
and insertion events. Both the rx_rmfifodatadeleted and rx_rmfifodatainserted status flags are latched
High during deleted and inserted /I2/ ordered sets.
Word Aligner in 1000BASE-X and 1000BASE-KX Configurations
The word aligner in 1000BASE-X and 1000BASE-KX functional modes is configured in automatic
synchronization state machine mode. The Quartus II software automatically configures the synchronization
state machine to indicate synchronization when the receiver receives three consecutive synchronization
ordered sets. A synchronization ordered set is a /K28.5/ code group followed by an odd number of valid
/Dx.y/ code groups. The fastest way for the receiver to achieve synchronization is to receive three continuous
{/K28.5/, /Dx.y/} ordered sets.
Receiver synchronization is indicated on the rx_syncstatus port of each channel. A high on the
rx_syncstatus port indicates that the lane is synchronized; a low on the rx_syncstatus port indicates that
the lane has fallen out of synchronization. The receiver loses synchronization when it detects four invalid
code groups separated by less than three valid code groups or when it is reset.
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6-13
Synchronization State Machine Parameters in 1000BASE-X and 1000BASE-KX
Configurations
Table 6-1: Synchronization State Machine Parameters in 1000BASE-X or 1000BASE-KX Mode
Synchronization State Machine Parameters
Settings
Number of valid {/K28.5/, /Dx,y/} ordered sets received to achieve synchronization
3
Number of errors received to lose synchronization
4
Number of continuous good code groups received to reduce the error count by
1
4
Transceiver Clocking in 10GBASE-R, 10GBASE-KR, 1000BASE-X, and 1000BASE-KX
Configurations
The CMU PLL or the auxiliary transmit (ATX) PLLs in a transceiver bank generate the transmitter serial
and the fractional PLL for the parallel clocks for the 10GBASE-R, 10GBASE-KR, 1000BASE-X, and
1000BASE-KX channels. The following table lists the configuration details.
Table 6-2: Input Reference Clock Frequency and Interface Speed Specifications for 10GBASE-R, 10GBASE-KR,
and 1000BASE-KX Configurations
PHY IP Type
PHY Type
Input Reference
Clock Frequency
(MHz)
FPGA FabricTransceiver
Interface Width
FPGA Fabric-Transceiver
Interface Frequency (MHz)
10GBASE-R PHY IP
10GBASE-R
644.53125,
322.265625
64-bit data, 8-bit 156.25
control
1G/10GbE and
10GBASE-KR PHY IP
10GBASE-R and 644.53125,
10GBASE-KR
322.265625
64-bit data, 8-bit 156.25
control
1G/10GbE and
10GBASE-KR PHY IP
1000BASE-X and 125, 62.5
1000BASE-KX
8-bit data, gmii_ 125
tx_en and gmii_
tx_err control
Interlaken
Interlaken is a scalable, chip-to-chip interconnect protocol that enables transmission speeds from 10 to more
than 100 Gbps.
Arria V GZ devices support a transmission speed of up to 12.5 Gbps per lane in an Interlaken configuration.
All the PCS blocks in the Interlaken configuration conform to the Interlaken Protocol Definition, Rev 1.2.
In the MegaWizard Plug-In Manager, you can implement an Interlaken link by instantiating the Interlaken
PHY IP under Interlaken in the Interfaces menu.
Related Information
Refer to the Interlaken PHY IP Core chapter in the Altera Transceiver PHY IP Core User Guide
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Transceiver Datapath Configuration
Transceiver Datapath Configuration
Figure 6-13: Interlaken Datapath Configuration
Blocks shown as “Disabled” are not used but incur latency. Blocks shown as “Bypassed” are not used and
do not incur any latency. The maximum data rates and frequencies are for the fastest speed grade devices.
Transceiver PHY IP
Interlaken PHY IP
Lane Data Rate
3.125 - 12.5 Gbps
Number of Channels
1-24
PCS-PMA Interface Width
40-Bit
Gear Box
Block Synchronizer
Disparity Generator/Checker
Scrambler, Descrambler (Mode)
Enabled
Enabled
Enabled
(Frame Synchronous Mode)
64B/66B Encoder/Decoder
Bypassed
BER Monitor
Bypassed
CRC32 Generator, Checker
Frame Generator, Synchronizer (Interlaken)
TX FIFO, RX FIFO (Mode)
TX/RX 10G PCS Latency (Parallel Clock Cycles)
FPGA Fabric-to-Transceiver
Interface Width
FPGA Fabric-to-Transceiver
Interface Frequency
Altera Corporation
Enabled (67:40 Ratio)
Enabled
Enabled
Enabled
(Elastic Buffer Mode)
TX: 7-28
RX: 14-21
64-bit Data
1-bit Control/Data
FIFO flow control signals
78.125 - 312.5 MHz
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Figure 6-14: Transceiver Channel Datapath for Interlaken Configuration
tx_serial_data
Transmitter PMA
Serializer
TX
Gear Box
Disparity
Generator
Scrambler
64B/66B Encoder
and TX SM
CRC32
Generator
TX FIFO
Controls and Status(1)
TX
FIFO
64-Bit Data
Frame Generator
Transmitter 10G PCS
1-Bit
Control
40
tx_coreclkin
tx_clkout/tx_user_clkout
Parallel Clock (Lane Data Rate/40)
rx_serial_data
40
Receiver PMA
CDR
RX
Gear Box
Block
Synchronizer
Descrambler
Frame Synchronizer
64B/66B Decoder
and RX SM
RX FIFO
Controls and Status(2), (3)
CRC32
Checker
RX
FIFO
1-Bit Control
Disparity Checker
Receiver 10G PCS
64-Bit Data
Deserializer
FPGA
Fabric
rx_coreclkin
Parallel Clock (Recovered - Lane Data Rate/40)
rx_clkout/rx_user_clkout
Central/ Local Clock Divider
CMU PLL
Clock Divider
Serial Clock
(From the ×1 Clock Lines)
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Notes:
(1) TX FIFO Control and Status (transmit backpressure and datavalid, synchronization done)
(2) RX FIFO Control (receive FIFO read enable and datavalid)
(3) RX FIFO Status (receive FIFO overflow and partially empty)
Supported Features
The Interlaken protocol supports a number of framing layer functions. The functions are defined in the
Interlaken Protocol Definition, Rev 1.2.
Table 6-3: Supported Features in Interlaken Configuration
Feature
Supported
Metaframe generation and payload insertion
Yes
Block synchronization (word alignment) and metaframe synchronization (frame
synchronization)
Yes
64B/67B framing
Yes
±96 bits disparity maintenance
Yes
Frame synchronous scrambling and descrambling
Yes
Diagnostic word generation
Yes
Framing Layer Control Word Forwarding
Yes
CRC-32 generation and checking of lane data integrity
Yes
Multi-lane deskew alignment
No
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Supported Features
Feature
Transmit and receive FIFO backpressure control and handshake
Supported
Yes
Block Synchronizer
The block synchronizer in the receiver PCS achieves and maintains a 64B/67B word boundary lock. This
block searches for valid synchronization header bits within the data stream and achieves lock after 64
consecutive legal synchronization patterns are found. After a 64B/67B word boundary lock is achieved, the
block synchronizer continuously monitors and flags for invalid synchronization header bits. If 16 or more
invalid synchronization header bits are found within 64 consecutive word boundaries, the block synchronizer
deasserts the lock state and searches again for valid synchronization header bits.
The block synchronizer implements the flow diagram shown in Figure 13 of Interlaken Protocol Definition
v1.2 and provides the word lock status to the FPGA fabric.
64B/67B Frame Generator
The transmit frame generator implements 64B/67B encoding, as explained in Interlaken Protocol Definition
v1.2. The Interlaken metaframe generator synchronously generates the framing layer control words, frame
synchronizer, scrambler state, skip words, and diagnostic word, and maps the transmitter data into the
payload of the metaframes. The metaframe length is programmable from 5 to a maximum value of 8191, 8byte words.
Note: Ensure that the metaframe length is programmed to the same value for both the transmitter and
receiver.
Frame Synchronizer
The receive frame synchronizer delineates the metaframe boundaries and searches for each of the framing
layer control words: Synchronization, Scrambler State, Skip, and Diagnostic. When four consecutive
synchronization words have been identified, the frame synchronizer achieves the frame locked state.
Subsequent metaframes are then checked for valid synchronization and scrambler state words. If four
consecutive invalid synchronization words or three consecutive mismatched scrambler state words are
received, the frame synchronizer loses frame lock. In addition, the frame synchronizer provides a receiver
metaframe lock status to the FPGA fabric.
Running Disparity
The disparity generator inverts the sense of bits in each transmitted word to maintain a running disparity
of ± 96 bit boundary. It supplies a framing bit in bit position 66 as explained in Table 4 of Interlaken Protocol
Definition Revision 1.2. The framing bit enables the disparity checker to identify whether bits[63:0] for that
word are inverted.
Frame Synchronous Scrambling/Descrambling
The scrambler/descrambler block in the transmitter/receiver PCS implements the scrambler/descrambler
polynomial x58 + x39 + 1 per Interlaken Protocol Definition Revision 1.2. Synchronization and Scrambler
State Words, as well as the 64B/67B framing bits are not scrambled/descrambled. The Interlaken PHY IP
core automatically programs random linear feedback shift register (LFSR) initialization seed values per lane.
The receiver PCS synchronizes the scrambler with the metaframe as described in the state flow shown in
Figure 1 of Interlaken Protocol Definition Revision 1.2.
The frame synchronizer features a whole set of error and performance monitoring ports to the FPGA fabric
interface and register status bits when using the Avalon® Memory-Mapped Management Interface. A receiver
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ready port, frame lock status, and cyclic redundancy check (CRC)-32 error detection port is available to the
FPGA fabric. The Avalon Memory-Mapped Management Interface provides additional functionality with
word boundary lock, frame lock status, synchronization word error detection, scrambler mismatch error,
and CRC-32 error detection status register bits.
Skip Word Insertion
The frame generator generates the mandatory fixed location skip words with every metaframe following the
scrambler state word and generates additional skip words based on the transmitter FIFO capacity state.
Skip Word Deletion
The frame synchronizer does not delete skip words. Instead, the frame synchronizer forwards the skip words
it receives to the MAC layer so the MAC can maintain and perform deskew alignment.
Diagnostic Word Generation and Checking of Lane Data Integrity (CRC-32)
The CRC-32 generator calculates the CRC for each metaframe and appends it to the diagnostic word of the
metaframe. An optional CRC-32 error flag is also provided to the FPGA fabric.
Framing Layer Control Word Forwarding
The four metaframe framing layer control words-Synchronization, Scrambler State, Skip, and Diagnostic
Words-are not deleted but forwarded to the MAC layer. This action enables the MAC layer to employ multilane deskew alignment within the FPGA fabric.
Multi-Lane Deskew Alignment
The Interlaken PHY IP does not support multi-lane deskew alignment. You must implement the multi-lane
deskew alignment state machine in the core fabric or the Altera Interlaken MegaCore® function within the
FPGA fabric.
Transmit and Receive FIFO Control and Status
The Interlaken PCS configures the transmit and receive FIFOs in elastic buffer mode. In this mode of
operation, a lane synchronization, backpressure and FIFO control, and status port signals are provided to
the MAC layer for handshaking.
Transceiver Multi-Lane Bonding and Transmit Skew
A soft-bonding IP is used for Interlaken bonding in the transceivers. The transceiver clocking in each lane
is configured as non-bonded. For multi-lane designs, a dedicated PLL reference clock pin that is equidistant
from the transmit PLLs in each bank must be selected. You must tightly match lane board traces to minimize
lane-to-lane skew.
Related Information
• For more information about Interlaken PHY IP control and status signals associated with each
feature, refer to the Interlaken PHY IP Core chapter in the Altera Transceiver PHY IP Core User Guide
• Interlaken MegaCore Function User Guide
Transceiver Clocking
Describes the transceiver clocking for the Interlaken protocol.
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Transceiver Clocking
Figure 6-15: Clocking Resources Available in a Four-Lane Interlaken Configuration
×6 Clock Lines
Ch5
Receiver PCS
Deserializer
Clock Divider
Ch4
Receiver PCS
To Transmitter Channel
Receiver PMA
Deserializer
Clock Divider
Ch3
Receiver PCS
To Transmitter Channel
Receiver PMA
Deserializer
Clock Divider
Ch2
Receiver PCS
To Transmitter Channel
Receiver PMA
Deserializer
Clock Divider
Ch1
Receiver PCS (Master)
To Transmitter Channel
Receiver PMA
Deserializer
Clock Divider
Ch0
Receiver PCS
To Transmitter Channel
Receiver PMA
Deserializer
Local Clock Divider
CMU PLL
Clock Divider
CDR
Input
Reference
Clock
Central Clock Divider
CMU PLL
CDR
Input
Reference
Clock
Local Clock Divider
CMU PLL
CDR
Input
Reference
Clock
Local Clock Divider
CMU PLL
CDR
(2)
Input
Reference
Clock
Central Clock Divider
CMU PLL
CDR
Input
Reference
Clock
Local Clock Divider
CMU PLL
×1 Clock Lines
Receiver PMA
CDR
Input
Reference
Clock
To Transmitter Channel
Parallel Clock
Serial Clock
Parallel and Serial Clocks
A CMU PLL may provide a clock for up to five Interlaken lanes within a transceiver bank. If an ATX PLL
is used, the PLL can clock up to six Interlaken lanes in a transceiver bank.
Note: To enable the ATX PLL, you must select ATX PLL for the PLL type parameter in the Interlaken
PHY IP.
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PCI Express (PCIe)—Gen1, Gen2, and Gen3
6-19
PCI Express (PCIe)—Gen1, Gen2, and Gen3
The PCIe specification (version 3.0) provides implementation details for a PCIe-compliant physical layer
device at Gen1 (2.5 Gbps), Gen2 (5 Gbps), and Gen3 (8 Gbps) signaling rates.
The devices have built-in PCIe hard IP blocks to implement the PHY MAC layer, data link layer, and
transaction layer of the PCIe protocol stack. Up to four PCIe hard IP block reside within an Arria V GZ
device. If you enable the PCIe hard IP block, the transceiver interfaces with the hard IP block. Otherwise,
the transceiver interfaces directly through the PIPE interface. You must then implement a Soft-IP MAC
layer, data link layer, and transaction layer to the PIPE interface from the core fabric.
You can configure the transceivers in a PCIe functional configuration using one of the following methods:
• Arria V GZ Hard IP for PCI Express
• PHY IP core for PCI Express (PIPE)
The following table shows the two methods supported by transceivers in a PCIe functional configuration.
Table 6-4: Support for Transceivers
Support
Gen1, Gen2, and Gen3 data rates
Arria V GZ Hard IP for PCI
Express
Yes
MAC, data link, and transaction layer Yes
Transceiver interface
PHY IP Core for PCI Express (PIPE)
Yes
—
Hard IP through PIPE 3.0- PIPE 2.0 for Gen1 and Gen2
like
PIPE 3.0-like for Gen3 with Gen1/Gen2
support
In the MegaWizard Plug-In Manager, you can implement the PHY IP Core for PCI Express (PIPE)
configuration by instantiating the PHY IP Core for PCI Express (PIPE) under PCI Express in the Interfaces
menu.
Arria V GZ transceivers support x1, x2, x4, and x8 lane configurations. In a PCIe x1 configuration, the PCS
and PMA blocks of each channel are clocked and reset independently. PCIe x2, x4, and x8 configurations
support channel bonding for two-lane, four-lane, and eight-lane PCIe links. In these bonded channel
configurations, the PCS and PMA blocks of all bonded channels share common clock and reset signals.
Related Information
• Arria V Hard IP for PCI Express User Guide
• Refer to the PHY IP Core for PCI Express (PIPE) chapter in the Altera Transceiver PHY IP Core
User Guide
Transceiver Datapath Configuration
The transceiver datapaths for PCI Express are different depending on whether or not Gen3 is enabled.
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Transceiver Datapath Configuration
Figure 6-16: PCIe Gen1 and Gen2 PIPE Datapath Configuration
This transceiver datapath configuration is for a configuration without Gen3 enabled.
IP
PHY IP Core for PCI Express (PIPE)
Bonded Data Rate
2.5 Gpbs for Gen1
5.0 Gbps for Gen2
100/125 MHz
100/125 MHz
Reference Clock
Number of Bonded Channels
x1, x2, x4, x8
x1, x2, x4, x8
10-Bit
10-Bit
Automatic
Synchronization
State Machine
(/K28.5/K28.5-/)
Automatic
Synchronization
State Machine
(/K28.5/K28.5-/)
Rate Match FIFO
Enabled
Enabled
8B/10B Encoder/Decoder
Enabled
Enabled
PMA-PCS Interface Width
Word Aligner (Pattern)
PCIe hard IP
Byte Serializer/Deserializer
Disabled
Disabled
Enabled
Enabled
TX/RX Standard PCS Latency
(Parallel Clock Cycles)
5 / 22
4-4.5 /
14-14.5
4-4.5 /
14-14.5
PCS-PIPE 2.0 Interface Width
8-Bit
16-Bit
16-Bit
125 MHz
250 MHz
PCS-PIPE 2.0 Interface
Frequency
Altera Corporation
Disabled
250 MHz
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Figure 6-17: PCIe Gen1, Gen2, and Gen3 Hard IP and PHY IP Core for PCI Express Datapath Configuration
This transceiver datapath configuration is for a configuration with Gen3 enabled.
Hard IP for PCI Express and
PHY IP Core for PCI Express with Gen3 enabled
IP
Bonded Data Rate
2.5 Gpbs for Gen1
5.0 Gbps for Gen2
8.0 Gbps for Gen3
Hard
Hard
Soft
100/125 MHz
100/125 MHz
100/125 MHz
x1, x2, x4, x8
x1, x2, x4, x8
x1, x2, x4, x8
10-Bit
10-Bit
32-Bit
Automatic
Synchronization
State Machine
(/K28.5/K28.5-/)
Automatic
Synchronization
State Machine
(/K28.5/K28.5-/)
8B/10B Encoder/Decoder
Enabled
Enabled
Disabled
Gear Box and Block Synchronizer
Disabled
Disabled
Enabled
128B/130B Encoder/Decoder
Disabled
Disabled
Enabled
Scrambler/Descrambler
Disabled
Disabled
Enabled
Byte Serializer/Deserializer
Enabled
Enabled
Disabled
1.5-2.25 /
6.5-7.25
1.5-2.25 /
6.5-7.25
1.5-2.25 /
6.5-7.25
32-Bit
32-Bit
32-Bit
Reset Controller (1)
Reference Clock
Number of Bonded Channels
PMA-PCS Interface Width
Word Aligner (Pattern)
TX/RX Standard PCS Latency
(Parallel Clock Cycles)
PIPE 3.0-like Width
Hard IP Avalon ST Interface Width (2)
Hard IP Avalon ST
Interface Width (2)
64-Bit, 128-Bit
125 MHz, 250 MHz
64-Bit, 128-Bit
125 MHz, 250 MHz
Disabled
64-Bit, 128-Bit,
256-Bit
125 MHz, 250 MHz
Notes:
(1) The PHY IP Core for PCI Express (PIPE configuration) employs the Embedded Reset Controller IP.
It does not use the Hard or Soft Reset Controller employed in the Hard IP for PCI Express (HIP
configuration).
(2) Does not apply to PHY IP Core for PCI Express configuration. Applies only to Hard IP for PCI
Express configuration.
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Supported Features for PCIe Configurations
Transceiver Channel Datapath
The following figure shows the Arria V GZ transmitter and receiver channel datapath for PCIe Gen1/Gen2
configurations when using PIPE configuration with Gen3 disabled. In this configuration, the transceiver
connects to a PIPE 2.0 compliant interface.
Figure 6-18: Transceiver Channel Datapath for PCIe Gen1/Gen2 in PIPE Configuration with Gen3 Disabled
Transmitter Standard PCS
rx_serial_data
CDR
Deserializer
Word Aligner
Deskew FIFO
Rate Match FIFO
Byte Deserializer
Byte Ordering
Receiver PMA
8B/10B Decoder
Receiver Standard PCS
RX Phase
Compensation
FIFO
tx_serial_data
Serializer
TX Bit
Slip
8B/10B Encoder
Byte Serializer
TX Phase
Compensation
FIFO
PIPE Interface
PCI Express Hard IP
FPGA
Fabric
Transmitter PMA
The following figure shows the Arria V GZ transmitter and receiver channel datapath for PCIe
Gen1/Gen2/Gen3 configurations with a 32-bit PIPE 3.0-like interface and PCI Express Base Specification
Version 3.0 is enabled.
Figure 6-19: Transceiver Channel Datapath for PCIe Gen1/Gen2/Gen3 Configurations
Receiver PMA
Word Aligner
Deskew FIFO
Rate Match FIFO
8B/10B Decoder
Byte Deserializer
Byte Ordering
RX Phase
Compensation
FIFO
Receiver Standard PCS
rx_serial_data
Deserializer
Block
Synchronizaer
Rate Match FIFO
128B/130B
Decoder
Descrambler
Receiver Gen3 PCS
CDR
PIPE Interface
FPGA
Fabric
PCI Express Hard IP
TX Phase
Compensation
FIFO
Byte Serializer
Transmitter Standard PCS
tx_serial_data
Gear Box
TX Bit
Slip
Serializer
Scrambler
Transmitter PMA
8B/10B Encoder
128B/130B
Encoder
Transmitter Gen3 PCS
Related Information
Transceiver Architecture in Arria V Devices
Supported Features for PCIe Configurations
The features supported for a PCIe configuration are different for the 2.5 Gbps, 5 Gbps, and 8 Gbps data rate
configurations.
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Supported Features for PCIe Configurations
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Table 6-5: Supported Features for PCIe Configurations
Feature
Gen1
Gen2
Gen3
(2.5 Gbps)
(5 Gbps)
(8 Gbps)
x1, x2, x4, x8 link configurations
Yes
Yes
Yes
PCIe-compliant synchronization state machine
Yes
Yes
Yes
±300 ppm (total 600 ppm) clock rate compensation
Yes
Yes
Yes
8-bit FPGA fabric-transceiver interface (PIPE 2.0)
Yes
—
—
16-bit FPGA fabric-transceiver interface (PIPE 2.0)
Yes
Yes
—
32-bit FPGA fabric-transceiver interface (PIPE 3.0-like)
—
—
Yes
64-bit Hard IP Avalon-ST interface width (Hard IP only)
Yes
Yes
Yes
128-bit Hard IP Avalon-ST interface width (Hard IP only)
Yes
Yes
Yes
256-bit Hard IP Avalon-ST interface width (Hard IP only)
—
Yes
Yes
Transmitter driver electrical idle
Yes
Yes
Yes
Receiver Detection
Yes
Yes
Yes
8B/10B encoder/decoder disparity control
Yes
Yes
—
128B/130B encoder/decoder
—
—
Yes
Power state management
Yes
Yes
Yes
Receiver PIPE status encoding ( pipe_rxstatus[2:0] )
Yes
Yes
Yes
Dynamic switching between 2.5 Gbps and 5 Gbps
signaling rate
—
Yes
—
Dynamic switching between 2.5 Gbps, 5 Gbps, and 8 Gbps
signaling rate
—
—
Yes
Dynamic transmitter margining for differential output
voltage control
—
Yes
Yes
Dynamic transmitter buffer de-emphasis of -3.5 dB and
-6 dB
—
Yes
Yes
Dynamic Gen3 transceiver pre-emphasis, de-emphasis,
and equalization
—
—
Yes
PIPE 2.0 Interface
In a PCIe PIPE configuration, each channel has a PIPE interface block that transfers data, control, and status
signals between the PHY-MAC layer and the transceiver channel PCS and PMA blocks. The PIPE configuration complies with the PIPE 2.0 specification. If you use a PIPE configuration, you must implement the
PHY-MAC layer using soft IP in the FPGA fabric.
Besides transferring data, control, and status signals between the PHY-MAC layer and the transceiver, the
PIPE interface block implements the following functions required in a PCIe-compliant physical layer device:
• Forcing the transmitter driver into the electrical idle state
• Initiating the receiver detect sequence
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Supported Features for PCIe Configurations
•
•
•
•
•
Controlling the 8B/10B encoder/decoder
Controlling the 128B/130B encoder/decoder
Managing the PCIe power states
Indicating the completion of various PHY functions
Encoding the receiver status and error conditions on the pipe_rxstatus[2:0] signal, conforming to
the PCIe PIPE 3.0 specification
Transceiver datapath clocking varies between non-bonded (x1) and bonded (x2, x4, and x8) configurations.
Dynamic Switching Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) Signal Rates
In a PIPE configuration, the PIPE MegaWizard Plug-In Manager provides an input signal (pipe_rate) that
is functionally equivalent to the RATE signal specified in the PCIe specification. A low-to-high transition
on this input signal (pipe_rate) initiates a data rate switch from Gen1 to Gen2. A high-to-low transition
on the input signal initiates a data rate switch from Gen2 to Gen1. The signaling rate switch between Gen1
and Gen2 is achieved by changing the transceiver datapath clock frequency between 250 MHz and 500 MHz,
while maintaining a constant, 16-bit width transceiver interface.
Transmitter Electrical Idle Generation
The PIPE interface block in Arria V GZ devices puts the transmitter buffer in the channel in an electrical
idle state when the electrical idle input signal is asserted. During electrical idle, the transmitter buffer
differential and common configuration output voltage levels are compliant to the PCIe Base Specification
2.0 for both PCIe Gen1 and Gen2 data rates.
The PCIe specification requires the transmitter driver to be in electrical idle in certain power states. For
more information about input signal levels required in different power states, refer to “Power State
Management”.
Power State Management
The PCIe specification defines four power states—P0, P0s, P1, and P2—that the physical layer device must
support to minimize power consumption:
• P0 is the normal operating state during which packet data is transferred on the PCIe link.
• P0s, P1, and P2 are low-power states into which the physical layer must transition as directed by the
PHY-MAC layer to minimize power consumption.
The PIPE interface in Arria V GZ transceivers provides an input port for each transceiver channel configured
in a PIPE configuration.
Note: When transitioning from the P0 power state to lower power states (P0s, P1, and P2), the PCIe
specification requires the physical layer device to implement power saving measures. Arria V GZ
transceivers do not implement these power saving measures except for putting the transmitter buffer
in electrical idle in the lower power states.
8B/10B Encoder Usage for Compliance Pattern Transmission Support
The PCIe transmitter transmits a compliance pattern when the Link Training and Status State Machine
(LTSSM) enters the Polling.Compliance substate. The Polling.Compliance substate is used to assess if the
transmitter is electrically compliant with the PCIe voltage and timing specifications.
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Receiver Electrical Idle Inference
The PCIe protocol allows inferring the electrical idle condition at the receiver instead of detecting the electrical
idle condition with analog circuitry.
In all PIPE configurations, (x1, x2, x4, and x8), each receiver channel PCS has an optional Electrical Idle
Inference module that implements the electrical idle inference conditions specified in the PCIe Base
Specification 2.0.
Receiver Status
The PCIe specification requires the PHY to encode the receiver status on a 3-bit status signal
(pipe_rxstatus[2:0]). This status signal is used by the PHY-MAC layer for its operation. The PIPE interface
block receives status signals from the transceiver channel PCS and PMA blocks, and encodes the status on
the pipe_rxstatus[2:0] signal to the FPGA fabric. The encoding of the status signals on the
pipe_rxstatus[2:0] signal conforms to the PCIe specification.
Receiver Detection
The PIPE interface block in Arria V GZ transceivers provides an input signal (pipe_txdetectrx_loopback)
for the receiver detect operation required by the PCIe protocol during the Detect state of the LTSSM. When
the pipe_txdetectrx_loopback signal is asserted in the P1 power state, the PCIe interface block sends a
command signal to the transmitter driver in that channel to initiate a receiver detect sequence. In the P1
power state, the transmitter buffer must always be in the electrical idle state. After receiving this command
signal, the receiver detect circuitry creates a step voltage at the output of the transmitter buffer. If an active
receiver (that complies with the PCIe input impedance requirements) is present at the far end, the time
constant of the step voltage on the trace is higher when compared with the time constant of the step voltage
when the receiver is not present. The receiver detect circuitry monitors the time constant of the step signal
seen on the trace to determine if a receiver was detected. The receiver detect circuitry requires a 125-MHz
clock for operation that you must drive on the fixedclk port.
Note: For the receiver detect circuitry to function reliably, the transceiver on-chip termination must be
used and the AC-coupling capacitor on the serial link and the receiver termination values used in
your system must be compliant with the PCIe Base Specification 2.0.
The PIPE core provides a 1-bit PHY status (pipe_phystatus) and a 3-bit receiver status signal
(pipe_rxstatus[2:0]) to indicate whether a receiver was detected or not, as per the PIPE 2.0 specifications.
Gen1 and Gen2 Rate Match FIFO
In compliance with the PCIe protocol, Arria V GZ receiver channels have a rate match FIFO to compensate
for small clock frequency differences up to ±300 ppm between the upstream transmitter and the local receiver
clocks.
PCIe Reverse Parallel Loopback
PCIe reverse parallel loopback is only available in a PCIe functional configuration for Gen1, Gen2, and Gen3
data rates. The received serial data passes through the receiver CDR, deserializer, word aligner, and rate
matching FIFO buffer. The data is then looped back to the transmitter serializer and transmitted out through
the transmitter buffer. The received data is also available to the FPGA fabric through the port. This loopback
mode is compliant with the PCIe specification 2.0. Arria V GZ devices provide an input signal to enable this
loopback mode.
Note: This is the only loopback option supported in PIPE configurations.
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Supported Features for PCIe Gen3
Figure 6-20: PCIe Reverse Parallel Loopback Mode Datapath
The grayed-out blocks are Inactive.
Serializer
8B10B Encoder
Transmitter PMA
Byte Serializer
Reverse Parallel
Loopback Path
CDR
Word Aligner
Deskew FIFO
Receiver PMA
Rate Match FIFO
8B/10B Decoder
Byte Deserializer
Byte Ordering
RX Phase
Compensation
FIFO
Receiver Standard PCS
Deserializer
TX Phase
Compensation
FIFO
PIPE Interface
FPGA
Fabric
PCI Express Hard IP
Transmitter Standard PCS
Related Information
• Refer to the PHY IP Core for PCI Express (PIPE) chapter in the Altera Transceiver PHY IP Core
User Guide
• Refer to the “PCS Architecture” section in the Transceiver Architecture in Arria V Devices chapter
• For the power state requirements when switching between Gen1 and Gen2 data rates, refer to the
PCIe Base Specification 2.0.
Supported Features for PCIe Gen3
The PCIe Gen3 hard PCS supports the Gen3 base specification. PCIe Gen3 operations can be configured
using the Arria V GZ Hard IP for PCI Express IP or PHY IP Core for PCI Express.
In Arria V GZ Hard IP for PCI Express, selecting PCIe Base Specification Version 3.0 or PCI Express Base
Specification Version 2.1 enables a 32-bit wide PIPE 3.0-like interface for Gen1, Gen2, and Gen3 operations.
In PHY IP Core for PCI Express, selecting Gen3 enables the 32-bit wide PIPE 3.0-like interface and selecting
Gen1 or Gen2 enables the 16-bit/8-bit wide PIPE 2.0 interface for Gen1 and Gen2 operation.
Block Synchronization (Word Aligner)
The block synchronizer aligns the recovered serial data coming from the CDR to 130-bit word boundaries.
The block synchronizer delineates the word boundaries by searching and identifying the Electrical IDLE
Exit Sequence Ordered Set (EIEOS) or the Last FTS OS and SKP ordered set to correctly identify the word
boundary from the incoming serial data stream. The block synchronizer continues to realign to a new block
boundary following the receipt of an SKP ordered set because of varying word lengths.
Gen3 Rate Match FIFO
To accommodate PCIe protocol requirements and to compensate for clock frequency differences of up to
±300 ppm between source and termination equipment, receiver channels have a rate match FIFO. The rate
match FIFO adds or deletes four SKP characters (32 bits) to keep the FIFO from becoming empty or full. It
monitors the block synchronizer for a skip_found signal. If the rate match FIFO is almost full, the FIFO
deletes four SKP characters. If the rate match FIFO is nearly empty, the FIFO inserts an SKP character at
the start of the next available SKP ordered set.
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128B/130B Encoder/Decoder
Unlike PCIe Gen1 and Gen2, the PCIe Gen3 encoder/decoder does not use 8B/10B encoding. The PCIe
Gen3 encoder/decoder uses a 2-bit sync header and a 128-bit data word. The PCS encoder appends the two
sync header bits to every 128 bits of data and enables scrambling for the data packets except for ordered set
packets and the first symbol of a TS1/TS2 ordered set. The encoder/decoder continuously enables or disables
scrambling, based on whether the payload being processed is an ordered set or a data packet. If an Electrical
IDLE Exit Ordered Set or a Fast Training Sequence Ordered Set is received, the scrambler is reset to the
initial seed value. The encoder/decoder also monitors the data stream for ordered set and sync header bit
violations.
Gen3 Gear Box
The PCIe 3.0 base specification requires a block size of 130 bits with the exception of SKP ordered sets, which
can be 66, 98, 130, 162, or 194 bits in length. The 130-bit block of data generated by the 128B/130B encoder
and variable length SKP characters must be reordered in 32-bit parallel data segments that the PMA serializer
can accept. The transceivers employ a gear box to accommodate this fractional bit difference between the
130-bit data word and a fixed 32-bit serialization PMA factor for Gen3.
Scrambler/Descrambler
Scrambling and descrambling are used during PCIe Gen3 operation to guarantee adequate transitions for
the receiver in order to correctly regenerate the recovered clock. The 2-bit sync header bit, ordered set, and
the first symbol of the TS1/TS2 ordered set are never scrambled.
PIPE 3.0-Like Gen3 Interface
PCIe Gen3 is a new feature added to the transceivers. The PCS supports PCI Express 3.0 base specification.
The PIPE interface has been expanded to a 32-bit wide PIPE 3.0-like interface. The PIPE interface controls
PHY functions such as transmission of electrical idle, receiver detection, and speed negotiation and control.
In summary, the Gen3 PIPE 3.0-like interface block performs the following:
•
•
•
•
•
•
Dynamic clock selection between Gen1, Gen2, and Gen3 speeds
Gen3 auto speed negotiation (ASN)
Controlling the 128B/130B encoder/decoder
Gen3 Electrical Idle Entry and Exit detections/CDR Control Block
Dynamic Gen3 and Gen2/Gen1 PCS data rate Auto Speed Negotiation
Dynamic transceiver PMA data rate and PLL switching
Auto-Speed Negotiation Block
PCIe Gen3 mode enables ASN (auto-speed negotiation) between Gen1 (2.5 Gbps), Gen2 (5.0 Gbps), and
Gen3 (8.0 Gbps) signaling data rates. The signaling rate switch is accomplished through frequency scaling
and configuration of the PMA and PCS blocks using a fixed 32-bit wide PIPE 3.0-like Interface.
The PMA switches clocks between Gen1, Gen2, and Gen3 data rates in a glitch-free manner. For a nonbonded x1 channel, an ASN module facilitates speed negotiation in that channel. For bonded x2, x4, and x8
channels, the ASN module selects the master channel to control the rate switch. The master channel distributes
the speed change request to the other PMA and PCS channels.
Table 6-6: PIPE Gen3 32-Bit PCS Clock Rates
PCIe Gen3 Capability Mode Enabled
Lane data rate
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2.5G
Gen2
5G
Gen3
8G
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Supported Features for PCIe Gen3
PCIe Gen3 Capability Mode Enabled
Gen1
Gen2
Gen3
PCS clock frequency
250 MHz
500 MHz
250 MHz
FPGA Core IP clock frequency
62.5 MHz
125 MHz
250 MHz
PIPE interface width
32-bit
32-bit
32-bit
Rate[1:0]
00
01
10
The PCIe Gen3 speed negotiation process is initiated by writing a 1 to bit 5 of the Link Control register of
the root port, causing a PIPE rate signal change from the hard IP. The ASN then places the PCS in reset,
dynamically shuts down the clock paths to disengage the current active state PCS (either Standard PCS or
Gen3 PCS). If a switch to or from Gen3 is requested, the ASN automatically selects the correct PCS clock
paths and datapath selection in the multiplexers. The ASN block then sends a request to the PMA block to
switch the data rate change and waits for a rate change done signal for confirmation. When the PMA
completes the rate change and sends confirmation to the ASN block, ASN enables the clock paths to engage
the new PCS block and releases the PCS reset. Successful completion of this process is indicated by assertion
of the pipe_phystatus signal by the ASN block to the hard IP block.
Note: In PHY IP Core for PCI Express configuration, the Core IP must set the values to pipe_rate[1:0]
to initiate the transceiver datarate switch sequence.
Note: When you switch speeds to either Gen2 or Gen3, hold the LTSSM steady for 700 µs in
Recovery.RCVRLOCK. The rx_is_lockedtodata signal from the CDR must be stable during this
time. The PHY MAC interface should not look at rxvalid during this time because its contents may
be invalid.
Transmitter Electrical IDLE Generation
The PIPE 3.0-like interface under the control of the hard IP block in Hard IP for PCIe or the user Core IP
in PHY IP Core for PCIe may place the transmitter in electrical idle during low power states and the ASN
process. Before the transmitter enters electrical idle, the HIP sends an electrical idle order set (EIOS) to the
PHY. For Gen1 and Gen2, the order set format is COM, IDL, IDL, IDL. For Gen3, the order set format
consists of 16 symbols with value 0x66.
During electrical idle, the transmitter differential and common mode voltage levels are compliant to the
PCIe Base Specification 3.0.
Receiver Electrical IDLE Inference
If there is no activity on the link for a period of time or during the ASN process, the Inferring Electrical Idle
condition is detected by the receiver PHY. These conditions are specified according to Table 4-11 of the PCI
Express Base Specification, Rev 3.0.
Gen3 Power State Management
The PCIe base specification defines low power states for PHY layer devices to minimize power consumption.
The Gen3 PCS does not implement these power saving measures, except when placing the transmitter driver
in electrical idle state in the low power states. In P2 low power state, the transceivers do not disable the PIPE
block clock.
CDR Control Block
The CDR control block controls the PMA CDR to obtain bit and symbol alignment and deskew within the
allocated time, and generates status signals for other PCS blocks. The PCIe base specification requires that
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the receiver L0s power state exit time be a maximum of 4 ms for Gen1, 2 ms for Gen2, and 4 ms for Gen3
signaling rates. The transceivers have an improved CDR control block to accommodate fast lock times when
the CDR must relock to the new multiplier/divider settings when entering or exiting Gen3 speeds.
Transceiver Clocking and Channel Placement Guidelines
This section describes the transceiver clocking for Gen1 and Gen2 Hard IP and PIPE configurations. The
channel placement guidelines are only described for Gen1 and Gen2 PIPE configuration. The channel
placement guidelines for Gen1 and Gen2 Hard IP configuration are not included.
Transceiver Clocking for PCIe Gen1 and Gen2
PIPE x1 Configuration
The high-speed serial clock is provided by the CMU PLL in a channel different from that of the data channel.
The local clock divider block in the data channel generates a parallel clock from this high-speed clock and
distributes both clocks to the PMA and PCS of the data channel.
Figure 6-21: Transceiver Clocking in a Gen1/Gen2 PIPE x1 Configuration
Serializer
TX Bit Slip
Byte Serializer
TX Phase
Compensation
FIFO
Receiver PMA
Parallel Clock (Recovered)
Parallel Clock (from the clock divider)
rx_clkout
/2
CDR
Deserializer
Word Aligner
Deskew FIFO
Rate Match FIFO
Byte
Deserializer
8B/10B Decoder
Receiver Standard PCS
Byte Ordering
rx_coreclkin
Transmitter PMA
/2
RX Phase
Compensation
FIFO
FPGA
Fabric
PIPE Interface
tx_clkout
PCIe hard IP
tx_coreclkin
8B/10B Encoder
Transmitter Standard PCS
Recovered
Clocks
Input
Reference
Clock
Parallel and Serial Clocks
(To the ×6 clock lines) (1)
Central/Local Clock Divider
CMU PLL
Serial Clock
(From the ×1 Clock Lines)
Clock Divider
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
Parallel Clock
Serial Clock
Parallel and Serial Clocks
PIPE x2 Configuration
In a PIPE x2 bonded configuration, clocking within the PCS is independent for each receiver channel.
Clocking is bonded only for transmitter channels, while the control signals are bonded for both transmitter
and receiver channels. The Quartus II software automatically places the transmit CMU PLL and master
channel in either channel 1 or channel 4 within a transceiver bank
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Figure 6-22: Transmitter Clocking in a Gen1/Gen2 PIPE x2 Configuration
×6 Clock Lines
Ch5
Transmitter PCS
×1 Clock Lines
Transmitter PMA
Serializer
Local Clock Divider
CMU PLL
Clock Divider
(1)
Ch4
Transmitter PCS
Transmitter PMA
Serializer
Central Clock Divider
CMU PLL
Clock Divider
(1)
Ch3
Transmitter PCS
Transmitter PMA
Serializer
Local Clock Divider
CMU PLL
Clock Divider
(1)
Ch2
Transmitter PCS
Low-Speed Parallel Clock
High-Speed Serial Clock
Transmitter PMA
Serializer
Local Clock Divider
CMU PLL
Clock Divider
(1)
Ch1
Transmitter PCS (Master)
Low-Speed Parallel Clock
High-Speed Serial Clock
Transmitter PMA
Serializer
Central Clock Divider
CMU PLL
Clock Divider
Ch0
Transmitter PCS
Transmitter PMA
Serializer
Local Clock Divider
CMU PLL
Clock Divider
(1)
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Note:
(1) Serial clock and parallel clock from the x6 clock lines.
PIPE x4 Configuration
In a PIPE x4 bonded configuration, clocking within the PCS is independent for each receiver channel.
Clocking is bonded only for transmitter channels, while the control signals are bonded for both transmitter
and receiver channels. The Quartus II software automatically places the transmit CMU PLL and master
channel in either channel 1 or channel 4 within a transceiver bank.
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Figure 6-23: Transmitter Clocking in a Gen1/Gen2 PIPE x4 Configuration
×6 Clock Lines
Ch5
Transmitter PCS
×1 Clock Lines
Transmitter PMA
Serializer
Local Clock Divider
CMU PLL
Clock Divider
(1)
Ch4
Transmitter PCS
Transmitter PMA
Serializer
Central Clock Divider
CMU PLL
Clock Divider
(1)
Ch3
Transmitter PCS
Transmitter PMA
Serializer
Local Clock Divider
CMU PLL
Clock Divider
(1)
Ch2
Transmitter PCS
Low-Speed Parallel Clock
High-Speed Serial Clock
Transmitter PMA
Serializer
Local Clock Divider
CMU PLL
Clock Divider
(1)
Ch1
Transmitter PCS (Master)
Low-Speed Parallel Clock
High-Speed Serial Clock
Transmitter PMA
Serializer
Central Clock Divider
CMU PLL
Clock Divider
Ch0
Transmitter PCS
Transmitter PMA
Serializer
Local Clock Divider
CMU PLL
Clock Divider
(1)
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Note:
(1) Serial clock and parallel clock from the x6 clock lines.
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Figure 6-24: Receiver Clocking in a Gen1/Gen2 PIPE x4 Configuration
×6 Clock Lines
Ch5
Receiver PCS
Deserializer
Clock Divider
CDR
Input
Reference
Clock
Local Clock Divider
CMU PLL
×1 Clock Lines
Receiver PMA
To Transmitter Channel
(1)
Ch4
Receiver PCS
Receiver PMA
Deserializer
Input
Reference
Clock
Central Clock Divider
CMU PLL
Clock Divider
CDR
(2)
To Transmitter Channel
(1)
Ch3
Receiver PCS
Receiver PMA
Deserializer
Input
Reference
Clock
Local Clock Divider
CMU PLL
Clock Divider
CDR
To Transmitter Channel
(1)
Ch2
Receiver PCS
Receiver PMA
Deserializer
Input
Reference
Clock
Local Clock Divider
CMU PLL
Clock Divider
CDR
To Transmitter Channel
(1)
Ch1
Receiver PCS (Master)
Receiver PMA
Deserializer
Input
Reference
Clock
Central Clock Divider
CMU PLL
Clock Divider
Ch0
Receiver PCS
To Transmitter Channel
Receiver PMA
Deserializer
Local Clock Divider
CMU PLL
Clock Divider
CDR
CDR
Input
Reference
Clock
To Transmitter Channel
(1)
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Note:
(1) Serial clock and parallel clock from the x6 clock lines.
PIPE x8 Configuration
In the x8 PCIe bonded configuration, clocking is independent for receiver channels. Clocking and control
signals are bonded only for transmitter channels.
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Figure 6-25: Transceiver Clocking in a Gen1/Gen2 PIPE x8 Configuration
Transceiver Bank A
FPGA
Fabric
×1 Clock Line ×6 Clock Line ×N Clock Line Top
Ch5
Transmitter PCS
Transmitter PMA
Serializer
Local Clock Divider
CMU PLL
Clock Divider
Transmitter PCS
Ch4
Transmitter PMA
Serializer
Central Clock Divider
CMU PLL
Clock Divider
Transmitter PCS
Ch3
Transmitter PMA
Serializer
Local Clock Divider
PIPE INTERFACE
CMU PLL
Ch2
Clock Divider
Low-Speed Parallel Clock
High-Speed Serial Clock
Transmitter PCS
Transmitter PMA
Serializer
Local Clock Divider
CMU PLL
Clock Divider
Ch1
Transmitter PCS (Master)
Transmitter PMA
Serializer
Central Clock Divider
CMU PLL
Clock Divider
Transmitter PCS
Ch0
Transmitter PMA
Serializer
Local Clock Divider
CMU PLL
Clock Divider
Transceiver Bank B
Ch5
Transmitter PCS
Transmitter PMA
×1 Clock Line ×6 Clock Line
Serializer
Local Clock Divider
CMU PLL
Ch4
Clock Divider
Low-Speed Parallel Clock
High-Speed Serial Clock
Transmitter PCS
Transmitter PMA
Serializer
Central Clock Divider
CMU PLL
Clock Divider
Transmitter PCS
Ch3
Transmitter PMA
PIPE INTERFACE
Serializer
Local Clock Divider
CMU PLL
Ch2
Clock Divider
Low-Speed Parallel Clock
High-Speed Serial Clock
Transmitter PCS
Transmitter PMA
Serializer
Local Clock Divider
CMU PLL
Ch1
Clock Divider
Low-Speed Parallel Clock
High-Speed Serial Clock
Transmitter PCS
Transmitter PMA
Serializer
Central Clock Divider
CMU PLL
Ch0
Clock Divider
Transmitter PCS
Transmitter PMA
Serializer
Local Clock Divider
CMU PLL
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Clock Divider
×N Clock Line Top
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Transceiver Channel Placement Guidelines for Gen1, Gen2, and Gen3 PIPE Configurations
Note: The channel placement guidelines are only described for Gen1, Gen2, and Gen3 x1, x2, x4, and x8
PIPE configurations. The channel placement guidelines for Gen1, Gen2, and Gen3 Hard IP
configuration are not included.
The following table lists the physical placement of PIPE channels in x1, x2, x4, and x8 bonding configurations.
The Quartus® II software automatically places the CMU PLL in a channel different from that of the data
channels.
Table 6-7: PIPE Configuration Channel Placement
Placement by the Quartus II software may vary with design, thus resulting in higher channel usage.
Configuration
Data Channel
Placement
Channel Utilization
Using CMU PLL in
Gen1 and Gen2
Channel Utilization Channel Utilization Using CMU and
Using ATX PLL in Gen1
ATX PLL in Gen3
and Gen2
x1
Any channel
2
1
2
x2
Contiguous
channels
3
2
3
x4
Contiguous
channels
5
4
5
x8
Contiguous
channels
9
8
9
Channel Placement for Gen1, Gen2, and Gen3 x1 PIPE Configuration
For PIPE x1 configurations, the channel can be placed anywhere within a transceiver bank that contains the
transmitter PLL. In Gen1 and Gen2 configurations, you can select either the ATX PLL or the CMU PLL as
the transmitter PLL. In Gen3 configurations, a CMU PLL is used for Gen1 and Gen2 datarates and an ATX
PLL is used for Gen3 datarates.
Channel Placement for Gen1, Gen2, and Gen3 x2 and x4 PIPE Configuration
The following two figures show examples of channel placement for PIPE x2 and x4 configurations. In a PIPE
x2 or x4 configuration, the two or four channels must be contiguous and within the same transceiver bank,
but they can be placed in any order as long as Logical Lane 1 is placed on the master channel. In Gen1 and
Gen2 configurations, you can select either the ATX PLL or the CMU PLL as the transmitter PLL. In Gen3
configurations, a CMU PLL is used for Gen1 and Gen2 datarates and an ATX PLL is used for Gen3 datarates.
The CMU PLL and/or ATX PLL must be within the same transceiver bank as the master channel.
In the figures, channels shaded in blue provide the transmit CMU PLL generating the high-speed serial
clock. Channels shaded in gray are data channels. The Quartus II software automatically selects one of the
following within a transceiver bank:
• The CMU PLL in either channel 1 or channel 4.
• The upper or lower ATX PLL if the ATX PLL is selected as the transmitter PLL within the transceiver
bank containing the master channel.
Gen3 channel placement requires both a CMU and an ATX PLL in the same transceiver bank as the master
channel.
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Figure 6-26: Example of PIPE x2 Gen1, Gen2, and Gen3 Channel Placement Using an ATX PLL, a CMU PLL,
or Both
Device
Transceiver Bank
Ch5
Ch4
ATX
PLL 1
CMU PLL
Ch3
Ch2
ATX
PLL 0
Ch1
Master
Ch0
×1
Logical Lane 1
PCI Express PHY (PIPE) ×2
×6/xN
Transceiver Bank
Ch5
ATX
PLL 1
Ch4
Master
PCI Express PHY (PIPE) ×2
Logical Lane 1
Ch3
Ch2
ATX
PLL 0
Ch1
CMU PLL
Ch0
×1
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Figure 6-27: Example of PIPE x4 Gen1, Gen2, and Gen3 Channel Placement Using an ATX PLL, a CMU PLL,
or Both
Channels shaded in blue provide the transmit CMU PLL generating the high-speed serial clock. Channels
shaded in gray are data channels. The Quartus II software automatically selects the CMU PLL in either
channel 1 or channel 4 within a transceiver bank. Gen3 channel placement requires an additional ATX PLL
in the same transceiver bank as the master channel.
Device
Transceiver Bank
Ch5
Ch4
ATX
PLL 1
CMU PLL
Ch3
Ch2
ATX
PLL 0
Ch1
PCI Express PHY (PIPE) ×4
Master
Logical Lane 1
Ch0
×1
×6/xN
Transceiver Bank
Ch5
Ch4
ATX
PLL 1
Master
Logical Lane 1
PCI Express PHY (PIPE) ×4
Ch3
Ch2
ATX
PLL 0
Ch1
CMU PLL
Ch0
×1
×6/xN
Channel Placement for Gen1, Gen2, and Gen3 x8 PIPE Configuration
In a PIPE x8 configuration, the eight channels must be contiguous, but they can be placed in any order as
long as Logical Lane 0 is placed on the master channel.
The Quartus II software automatically selects one of the following within a transceiver bank:
• The CMU PLL in either channel 1 or channel 4.
• The upper or lower ATX PLL if the ATX PLL is selected as the transmitter PLL within the transceiver
bank containing the master channel.
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In Gen1 and Gen2 configurations, you can select either the ATX PLL or the CMU PLL as the transmitter
PLL. In Gen3 configurations, a CMU PLL is used for Gen1 and Gen2 datarates and an ATX PLL is used for
Gen3 datarates. The CMU PLL and/or ATX PLL must be within the same transceiver bank.
Figure 6-28: Example of PIPE x8 Gen1, Gen2, and Gen3 Channel Placement Using an ATX PLL, a CMU PLL,
or Both
Channels shaded in blue provide the transmit CMU PLL generating the high-speed serial clock. Channels
shaded in gray are data channels. Gen3 channel placement requires both a CMU and ATX PLL in the same
transceiver bank as the master channel.
Device
Device
Transceiver Bank
Transceiver Bank
Ch5
Ch5
Ch4
ATX
PLL 1
ATX
PLL 0
Ch4
ATX
PLL 1
CMU PLL
Ch3
Ch3
Ch2
Ch2
Ch1
Ch1
ATX
PLL 0
Master
Logical Lane 0
Ch0
Ch0
×1
×1
PCI Express
PHY (PIPE) ×8
Transceiver Bank
ATX
PLL 1
ATX
PLL 0
×1
Transceiver Bank
Ch5
Ch5
Ch4
Ch4
Ch3
Ch3
Ch2
Ch2
Ch1
Ch1
Ch0
Ch0
ATX
PLL 1
Master
Logical Lane 0
ATX
PLL 0
CMU PLL
×6/xN
×6/xN
×1
Related Information
For channel placement guidelines for PCIe hard IP configuration using the Hard IP for PCI Express,
refer to the Arria V Hard IP for PCI Express User Guide.
Advanced Channel Placement Guidelines for PIPE Configurations
Advanced channel placement options for PIPE configurations are enabled through Quartus Settings File
(QSF) assignments. A QSF assignment allows you to override the master channel assignment. By using a
QSF assignment, master channels can be assigned any logical channel number instead of the default Quartus II
logical lane assignment. Any PIPE channel placement can also be made compatible with the HIP configuration
channel placement.
In the following figures, channels shaded in blue provide the transmit CMU PLL generating the high-speed
serial clock. Channels shaded in gray are data channels. An ATX PLL shaded in green can be substituted for
the CMU PLL for Gen1 and Gen2 configurations only. Gen3 channel placement requires both the CMU
PLL for Gen1/Gen2 datarates and the ATX PLL for Gen3 datarates to be located in the same transceiver
bank as the master channel. The Quartus II software automatically selects the CMU PLL in either channel
1 or channel 4 and/or the upper or lower ATX PLL within a transceiver bank.
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Advanced Channel Placement for PIPE x2 Gen1, Gen2, and Gen3 Configurations
Figure 6-29: PIPE x2 Gen1, Gen2, and Gen3 Advanced Channel Placement Using CMU and/or ATX PLL
Device
Transceiver Bank
Ch5
ATX
PLL 1
Ch4
CMU PLL
Ch3
Ch2
ATX
PLL 0
Ch1
Master
Ch0
Logical Lane 0 (via QSF Assignment)
PCI Express PHY (PIPE) ×2
x1 x6/xN
Transceiver Bank
Ch5
ATX
PLL 1
Ch4
Master
Ch3
Logical Lane 0 (via QSF Assignment)
PCI Express PHY (PIPE) ×2
Ch2
ATX
PLL 0
Ch1
CMU PLL
Ch0
x1 x6/xN
Advanced Channel Placement for PIPE x4 Gen1, Gen2, and Gen3 Configurations
Figure 6-30: PIPE x4 Gen1, Gen2, and Gen3 Advanced Channel Placement Using CMU and/or ATX PLL in the
Same Transceiver Bank
Device
Transceiver Bank
Ch5
ATX
PLL 1
Ch4
Master
Ch3
Logical Lane 2 (via QSF Assignment)
PCI Express PHY (PIPE) ×4
Ch2
ATX
PLL 0
Ch1
CMU PLL
Ch0
x1 x6/xN
Transceiver Bank
Ch5
ATX
PLL 1
Ch4
CMU PLL
Ch3
Ch2
ATX
PLL 0
Ch1
Master
PCI Express PHY (PIPE) ×4
Logical Lane 2 (via QSF Assignment)
Ch0
x1 x6/xN
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Figure 6-31: PIPE x4 Gen1, Gen2, and Gen3 Advanced Channel Placement Using CMU and/or ATX PLL Across
Two Transceiver Banks – example 1
Device
Transceiver Bank
Ch5
ATX
PLL 1
Ch4
Ch3
Ch2
ATX
PLL 0
Ch1
Ch0
x1
PCI Express PHY (PIPE) ×4
Transceiver Bank
Ch5
ATX
PLL 1
Ch4
Master
Logical Lane 0 (via QSF Assignment)
Ch3
Ch2
ATX
PLL 0
Ch1
CMU PLL
Ch0
x1 x6/xN
Figure 6-32: PIPE x4 Gen1, Gen2, and Gen3 Advanced Channel Placement Using CMU and/or ATX PLL Across
Two Transceiver Banks – example 2
Device
Transceiver Bank
Ch5
ATX
PLL 1
Ch4
CMU PLL
Ch3
Ch2
ATX
PLL 0
Ch1
Master
Logical Lane 3 (via QSF Assignment)
Ch0
x1
PCI Express PHY (PIPE) ×4
Transceiver Bank
Ch5
ATX
PLL 1
Ch4
Ch3
Ch2
ATX
PLL 0
Ch1
Ch0
x1 x6/xN
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Advanced Channel Placement Guidelines for PIPE Configurations
Advanced Channel Placement for PIPE x8 Gen1, Gen2, and Gen3 Configurations
For PCIe x8 advanced channel placement where the master channel resides between the contiguous data
channel assignments, a second QSF assignment is required that allows the master channel to be placed
between data channels.
For a HIP-compatible PCIe x8 channel placement, the master channel must be assigned logical channel 4
in the lower transceiver bank and the second QSF assignment for the reserve channel that allow master
channel placement between contiguous data channel assignments are required.
Figure 6-33: PIPE x8 Gen1, Gen2, and Gen3 Advanced Channel Placement That is Compatible with HIP x8
Channel Placement
Device
Transceiver Bank
Ch5
ATX
PLL 1
Ch4
Ch3
ATX
PLL 0
Ch2
Logical Lane 7
Ch1
Logical Lane 6
Ch0
Logical Lane 5
x1
Transceiver Bank
Ch5
ATX
PLL 1
Ch4 Master/CMU PLL
Ch3
Ch2
ATX
PLL 0
Logical Lane 4
PCI Express PHY (PIPE) ×8
QSF Assignment Master Channel = 4
QSF Assignment Reserve Channel = true
Logical Lane 3
Logical Lane 2
Ch1
Logical Lane 1
Ch0
Logical Lane 0
x1 x6/xN
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Figure 6-34: PIPE x8 Gen1, Gen2, and Gen3 Advanced Channel Placement That is Not Compatible with HIP
x8 Channel Placement
Device
Transceiver Bank
ATX
PLL 1
ATX
PLL 0
Ch5
Logical Lane 7
Ch4
Logical Lane 6
Ch3
Logical Lane 5
Ch2
Logical Lane 4
Ch1 Master/CMU PLL
Ch0
x1
QSF Assignment Master Channel = 4
QSF Assignment Reserve Channel = true
Logical Lane 3
PCI Express PHY (PIPE) ×8
Transceiver Bank
ATX
PLL 1
Ch5
Logical Lane 2
Ch4
Logical Lane 1
Ch3
Logical Lane 0
Ch2
ATX
PLL 0
Ch1
Ch0
x1 x6/xN
The following figures show PIPE x8 Gen1, Gen2, and Gen3 advanced channel placement that requires only
a master channel QSF assignment.
Figure 6-35: PIPE x8 Gen1, Gen2, and Gen3 Advanced Channel Placement – example 1
Device
Transceiver Bank
Ch5
ATX
PLL 1
Ch4
CMU PLL
Ch3
Ch2
ATX
PLL 0
Ch1
Master
Logical Lane 7 (via QSF Assignment)
Ch0
x1
Transceiver Bank
Ch5
ATX
PLL 1
PCI Express PHY (PIPE) ×8
Ch4
Ch3
Ch2
ATX
PLL 0
Ch1
Ch0
x1 x6/xN
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Transceiver Clocking for PCIe Gen3
Figure 6-36: PIPE x8 Gen1, Gen2, and Gen3 Advanced Channel Placement – example 2
Device
Transceiver Bank
Ch5
ATX
PLL 1
Ch4
CMU PLL
Ch3
Ch2
ATX
PLL 0
Ch1
Master
Logical Lane 2 (via QSF Assignment)
Ch0
x1
PCI Express PHY (PIPE) ×8
Transceiver Bank
Ch5
ATX
PLL 1
Ch4
Ch3
Ch2
ATX
PLL 0
Ch1
Ch0
x1 x6/xN
Figure 6-37: PIPE x8 Gen1, Gen2, and Gen3 Advanced Channel Placement – example 3
Device
Transceiver Bank
Ch5
ATX
PLL 1
Ch4
Ch3
Ch2
ATX
PLL 0
Ch1
Ch0
x1
Transceiver Bank
PCI Express PHY (PIPE) ×8
Ch5
ATX
PLL 1
Ch4
Master
Logical Lane 2 (via QSF Assignment)
Ch3
Ch2
ATX
PLL 0
Ch1
CMU PLL
Ch0
x1 x6/xN
Transceiver Clocking for PCIe Gen3
This section describes the transceiver clocking topology for both the PCIe Gen3 Hard IP and PIPE
configuration.
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Transceiver Clocking for PCIe Gen3
In a PCIe x1, x2, x4, and x8 Gen3 Mode, both a channel PLL (CMU PLL) from transceiver physical channel
1 or 4 of the transceiver bank and either the top or bottom ATX PLL are used to generate the high-speed
serial clock and support ASN. The CMU PLL supports Gen1 and Gen2 data rates while the ATX PLL supports
Gen3 data rates. To enable rapid switching between Gen1, Gen2, and Gen3 data rates, a multiplexer selects
either the free running CMU PLL for Gen1 and Gen2 data rates or the free running ATX PLL for Gen3 data
rates. PLL reconfiguration is not used to support ASN.
Gen3 x1 Configuration
Figure 6-38: Transceiver Clocking in a Gen1/Gen2/Gen3 PCIe x1 Hard IP and PIPE Configuration
For Gen1 and Gen2, use the CMU PLL. For Gen3, use the ATX PLL.
Transmitter Gen3 PCS
Serializer
TX Bit
Slip
8B/10B Encoder
32
64/128/256
Byte Serializer
TX Phase
Compensation
FIFO
Transmitter Standard PCS
tx_coreclkin
tx_serial_data
Gear Box
128B/130B
Encoder
Scrambler
Transmitter PMA
Deserializer
Word Aligner
Deskew FIFO
Rate
Match FIFO
8B/10B Decoder
Byte
Deserializer
32
Byte Ordering
64/128/256
rx_coreclkin
RX Phase
Compensation
FIFO
Receiver Standard PCS
rx_serial_data
Block
Synchronizer
Receiver PMA
Rate
Match FIFO
FPGA
Fabric
128B/130B
Decoder
Descrambler
Receiver Gen3 PCS
CDR
PIPE Interface
PCI Express Hard IP
/2
tx_clkout
/2
rx_clkout
Parallel and Serial Clocks
(To the ×6 clock lines)
Central / Local Clock Divider
CMU PLL (1)
Clock Divider
Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)
Serial Clock from ATX PLL
(From the x1 Clock Lines) (2)
Parallel Clock
Serial Clock
Parallel and Serial Clocks
For PCIe x1 Gen3 using Hard IP configuration, the CMU PLL (transceiver physical channel 1) and the
bottom ATX PLL of the transceiver bank are configured to generate the high-speed serial clock for the
transmitter datapath clock and the rate matcher side of the FIFO in the receiver datapath if rate matching
is enabled for the data channel. Two transceiver channels are needed to implement PCIe x1 Gen3, one for
the data channel and one for the CMU PLL. The local clock divider block in the data channel generates a
parallel clock from this high-speed serial clock and distributes both clocks to the PMA and PCS of the data
channel.
For PCIe x1 Gen3 using PIPE configuration, the CMU PLL (transceiver physical channel 1 or 4) and the
top or bottom ATX PLL of the transceiver bank are configured to generate the high-speed serial clock for
the transmitter datapath clock and the rate matcher side of the FIFO in the receiver datapath if rate matching
is enabled for the data channel. Two transceiver channels are needed to implement PCIe x1 Gen3, one for
Transceiver Configurations in Arria V GZ Devices
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Transceiver Clocking for PCIe Gen3
AV53008
2014.03.07
the data channel and one for the CMU PLL. The local clock divider block in the data channel generates a
parallel clock from this high-speed serial clock and distributes both clocks to the PMA and PCS of the data
channel.
Altera Corporation
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AV53008
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Transceiver Clocking for PCIe Gen3
6-45
Gen3 x2 Configuration
Figure 6-39: Transmitter Clocking in a Gen1/Gen2/Gen3 PCIe x2 Hard IP and PIPE Configuration
Unlike the Hard IP configuration, the PIPE configuration has the additional flexibility of using the top four
transceiver channels in a transceiver bank or spanning the four lanes across two banks.
×6 Clock Lines
Ch5
Transmitter PCS
×1 Clock Lines
Transmitter PMA
Serializer
Local Clock Divider
CMU PLL
Clock Divider
(1)
Ch4
Transmitter PCS
Transmitter PMA
Serializer
ATX PLL
Central Clock Divider
CMU PLL
Clock Divider
(1)
Ch3
Transmitter PCS
Transmitter PMA
Serializer
Local Clock Divider
CMU PLL
Clock Divider
(1)
Ch2
Transmitter PCS
Transmitter PMA
Serializer
Central Clock Divider
CMU PLL
Clock Divider
(1)
Ch1
Transmitter PCS (Master)
Low-Speed Parallel Clock
High-Speed Serial Clock
Transmitter PMA
Serializer
ATX PLL
Central Clock Divider
CMU PLL
Clock Divider
Ch0
Transmitter PCS
Transmitter PMA
Serializer
Local Clock Divider
CMU PLL
Clock Divider
(1)
Parallel Clock
Serial Clock
Parallel and Serial Clocks
Transceiver Configurations in Arria V GZ Devices
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Altera Corporation
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Transceiver Clocking for PCIe Gen3
AV53008
2014.03.07
For PCIe x2 Gen3 using Hard IP configuration, the CMU PLL (transceiver physical channel 4) and the top
ATX PLL of the transceiver bank are configured to generate the high-speed serial clock. A total of three
transceiver channels are required to impl