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SNAS255L – MARCH 2005 – REVISED MAY 2013

LM4845 Boomer™ Audio Power Amplifier Series Output Capacitor-less Audio Subsystem with Programmable National 3D

Check for Samples: LM4845

1

FEATURES

23

• I

2

C/SPI Control Interface

I

2

C/SPI Programmable National 3D Audio

I

2

C/SPI Controlled 32 Step Digital Volume

Control (-54dB to +18dB)

Three Independent Volume Channels (Left,

Right, Mono)

Eight Distinct Output Modes

DSBGA Surface Mount Packaging

“Click and Pop” Suppression Circuitry

Thermal Shutdown Protection

Low Shutdown Current (0.1uA, typ)

APPLICATIONS

Moblie Phones

PDAs

KEY SPECIFICATIONS

THD+N at 1kHz, 500mW

– into 8 Ω BTL (3.3V): 1.0% (typ)

THD+N at 1kHz, 30mW

– into 32 Ω SE (3.3V): 1.0% (typ)

Single Supply Operation (V

DD

): 2.7 to 5.5V

I

2

C/SPI Single Supply Operation, 2.2 to 5.5V

DESCRIPTION

The LM4845 is an audio power amplifier capable of delivering 500mW of continuous average power into a mono 8 Ω bridged-tied load (BTL) with 1% THD+N,

25mW per channel of continuous average power into stereo 32 Ω single-ended (SE) loads with 1% THD+N, or an output capacitor-less (OCL) configuration with identical specification as the SE configuration, from a

3.3V power supply.

The LM4845 features a 32-step digital volume control and eight distinct output modes. The digital volume control, 3D enhancement, and output modes

I

(mono/SE/OCL) are programmed through a two-wire

2

C or a three-wire SPI compatible interface that allows flexibility in routing and mixing audio channels.

The LM4845 has three input channels: one pair for a two-channel stereo signal and the third for a singlechannel mono input.

The LM4845 is designed for cellular phone, PDA, and other portable handheld applications. It delivers high quality output power from a surface-mount package and requires only seven external components in the

OCL mode (two additional components in SE mode).

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2

Boomer is a trademark of Texas Instruments.

3

All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright © 2005–2013, Texas Instruments Incorporated

LM4845

SNAS255L – MARCH 2005 – REVISED MAY 2013

Typical Application

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AUDIO

INPUT

C

IN

3

Phone In

AUDIO

INPUT

0.22 P F

C

IN

2

R

IN

0.22

P

F

AUDIO

INPUT

C

IN

1

L

IN

0.22 P F

I

2

CSPI_V

DD

SDA

SCL

ID_ENB

I

2

CSPI_SEL

Volume Control

-54 dB to +18 dB

Volume Control

-54 dB to +18 dB

Volume Control

-54 dB to +18 dB

I

2

C/SPI

Interface

Mixer &

Output

Mode

Select

C

S

V

DD

1 P F

6 dB

Mono+

Mono-

0 dB

National

3D

0 dB

0 dB

Bias

C

B

Bypass

2.2 P F

Handsfree

Speaker

8 :

R

OUT

32 :

L

OUT

32

:

C

3DL

C

3DR

Figure 1. Typical Audio Amplifier Application Circuit-Output Capacitor-less

2

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AUDIO

INPUT

C

IN

3

Phone In

0.22

P

F

AUDIO

INPUT

C

IN

2

R

IN

0.22 P F

AUDIO

INPUT

C

IN

1

0.22

P

F

I

2

CSPI_V

DD

SDA

SCL

ID_ENB

I

2

CSPI_SEL

L

IN

Volume Control

-54 dB to +18 dB

Volume Control

-54 dB to +18 dB

Volume Control

-54 dB to +18 dB

I

2

C/SPI

Interface

Mixer &

Output

Mode

Select

C

S

V

DD

1 P F

National

3D

6 dB

0 dB

Handsfree

Speaker

MONO+

8 :

MONO-

C

O R

OUT

100 P F

32

:

0 dB

0 dB

Bias

C

O

L

OUT

100 P F

C

B

Bypass

2.2

P

F

32 :

C

3DL

C

3DR

Figure 2. Typical Audio Amplifier Application Circuit-Single Ended

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SNAS255L – MARCH 2005 – REVISED MAY 2013

Connection Diagrams

A

5

V

OC

B C D E

NC GND R

OUT

L

OUT

4

R

HP3D1

MONO_IN V

DD

R

IN

L

IN

3

R

HP3D2

ID_ENB

V

DD

L

HP3D1

L

HP3D2

2

I

2

CSPI_V

DD

SCL V

DD

NC C

BYPASS

1

SDA MONOGND MONO+ I

2

CSPI_SEL

Figure 3. 25-Bump DSBGA (Top View)

See Package Number TLA25CBA

XYTT

GE5 www.ti.com

Bump A1

4

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Figure 4. Top View

XY - Date Code

TT - Die Traceability

G - Boomer Family

E5 - LM4845ITL

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SNAS255L – MARCH 2005 – REVISED MAY 2013

1

2

22

23

24

25

19

20

21

14

15

16

17

18

7

8

9

10

11

12

13

3

4

5

6

E2

E3

E4

E5

D4

D5

E1

C4

C5

D1

D2

D3

B2

B3

B4

B5

C1

C2

C3

A3

A4

A5

B1

Bump

A1

A2

PIN DESCRIPTIONS

Name

SDA

I

2

CSPIV

DD

R

HP3D2

R

HP3D1

VOC

MONO-

SCL

ID_ENB

Phone_In

NC

GND

V

DD

V

DD

V

DD

GND

MONO+

NC

L

HP3D1

R

IN

R

OUT

I

2

C SPI_SEL

C

BYPASS

L

HP3D2

L

IN

L

OUT

Description

I

2

C or SPI Data

I

2

C or SPI Interface Power

Supply

Right Headphone 3D Input 2

Right Headphone 3D Input 1

Center Amplifier Output

Loudspeaker Negative Output

I

2

C or SPI Clock

Address Identification/Enable Bar

Mono Input

No Connect

Ground

Power Supply

Power Supply

Power Supply

GND

Loudspeaker Positive Output

No Connect

Left Headphone 3D Input 1

Right Input Channel

Right Headphone Output

I

2

C or SPI Select

Half-Supply Bypass

Left Headphone 3D Input 2

Left Input Channel

Left Headphone Output

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

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Absolute Maximum Ratings

(1)

Supply Voltage

Storage Temperature

Input Voltage

ESD Susceptibility

(2)

ESD Machine model

(3)

Junction Temperature (T

J

)

Solder Information

Thermal Resistance

Vapor Phase (60 sec.)

Infrared (15 sec.)

θ

JA

(typ) - YZR0025

6.0V

− 65°C to +150°C

− 0.3 to V

DD

+0.3

2.0kV

200V

150°C

215°C

220°C

65°C/W

(4)

(1)

(2)

(3)

(4)

Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.

Some performance characteristics may degrade when the device is not operated under the listed test conditions.

Human body model, 100pF discharged through a 1.5k

Ω resistor.

Machine Model ESD test is covered by specification EIAJ IC-121-1981. A 200pF cap is charged to the specified voltage, then discharged directly into the IC with no external series resistor (resistance of discharge path must be under 50 Ω ).

The given θ

JA for an LM4845ITL mounted on a demonstration board with a 9in

2 area of 1oz printed circuit board copper ground plane.

Operating Ratings

(1)

Temperature Range

Supply Voltage (V

DD

)

Supply Voltage (I

2

C/SPI)

− 40°C to 85°C

2.7V

≤ V

DD

≤ 5.5V

2.2V

≤ V

DD

≤ 5.5V

(1) Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.

Some performance characteristics may degrade when the device is not operated under the listed test conditions.

6

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SNAS255L – MARCH 2005 – REVISED MAY 2013

Electrical Characteristics 3.3V

(1) (2)

The following specifications apply for V

DD

= 3.3V, T

A

= 25°C unless otherwise specified. [A

V

= 2 (BTL), A

V

= 1 (SE)]

Symbol Parameter Conditions LM4845

Typical

(3)

Limits

(4)

Units

(Limits)

I

DD

I

SD

V

OS

P

O

THD+N

N

OUT

PSRR

Supply Current

Output Modes 2, 4, 6

V

IN

= 0V; No load,

OCL = 0 (

Table 2 )

Output Modes 1, 3, 5, 7

V

IN

= 0V; No load, BTL,

OCL = 0 (

Table 2 )

Shutdown Current

Output Offset Voltage

Output Mode 0

V

IN

= 0V, Mode 5

(5)

MONO

OUT

; R

L

= 8 Ω

THD+N = 1%; f = 1kHz, BTL, Mode 1

Output Power

Total Harmonic Distortion Plus Noise

Output Noise

Power Supply Rejection Ratio

MONO

OUT

R

OUT and L

OUT

; R

L

= 32 Ω

THD+N = 1%; f = 1kHz, SE, Mode 4

MONO

OUT f = 20Hz to 20kHz

P

OUT

= 250mW; R

L

= 8 Ω , BTL, Mode 1

R

OUT and L

OUT f = 20Hz to 20kHz

P

OUT

= 12mW; R

L

= 32 Ω , SE, Mode 4

A-weighted

(6)

, Mode 5, BTL input referred

V

RIPPLE

C

B

= 200mV

= 2.2µF, BTL

PP

; f = 217Hz,

All audio inputs terminated into 50 Ω ; output referred gain = 6dB (BTL)

Output Mode 1,7

Output Mode 3

Power Supply Rejection Ratio

R

OUT and L

OUT

Output Mode 5

V

RIPPLE

= 200mV

PP

; f = 217Hz

C

B

= 2.2µF, SE, C

O

= 100 μ F

All audio inputs terminated into 50

; output referred gain,

OCL = 0 (

Table 2 )

Output Mode 2

Output Mode 4

Output Mode 6, 7

3.3

6

0.1

10

500

42

0.5

0.5

26

88

76

76

71

68

63

6.5

11

1

50

400

20 mA (max) mA (max)

µA (max) mV (max) mW (min) mW (min)

%

%

µV dB dB dB

Digital Volume Range

(R

IN and L

IN

)

Mute Attenuation

MONO_IN Input Impedance

R

IN and L

IN

Input Impedance

Input referred maximum attenuation

Input referred maximum gain

Output Mode 1, 3, 5

Maximum gain setting

Maximum attenuation setting

-54

18

80

11

100

–53.25

–54.75

17.25

18.75

8

14

75

125 dB dB dB dB (min) dB (max) dB (min) dB (max) dB k Ω k Ω

(min)

(max) k Ω k Ω

(min)

(max)

T

WU

Wake-Up Time from Shutdown

C

B

C

B

= 2.2

μ F, OCL

= 2.2

μ F, SE

90

138 ms

(1)

(2)

(3)

(4)

(5)

(6)

Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.

Some performance characteristics may degrade when the device is not operated under the listed test conditions.

All voltages are measured with respect to the ground pin, unless otherwise specified.

Typical specifications are specified at +25°C and represent the most likely parametric norm.

Tested limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level).

Potentially worse case: All three input stages are DC coupled to the BTL output stage.

Datasheet min/max specifications are specified by design, test, or statistical analysis.

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Electrical Characteristics 5.0V

(1) (2)

The following specifications apply for V

DD

= 5.0V, T

A

= 25°C unless otherwise specified. [A

V

= 2 (BTL), A

V

= 1 (SE)].

Symbol Parameter Conditions LM4845

Typical

(3)

Limits

(4) (5)

Units

(Limits)

I

DD

I

SD

V

OS

P

O

THD+N

N

OUT

PSRR

Supply Current

Output Modes 2, 4, 6

V

IN

= 0V; No load,

OCL = 0 (

Table 2 )

Output Modes 1, 3, 5, 7

V

IN

= 0V; No Load,

OCL = 0 (

Table 2 )

Shutdown Current

Output Offset Voltage

Output Mode 0

V

IN

= 0V, Mode 5

(5)

MONO

OUT

; R

L

= 8 Ω

THD+N = 1%; f = 1kHz, BTL, Mode 1

Output Power

Total Harmonic Distortion Plus Noise

Output Noise

R

OUT and L

OUT

; R

L

= 32 Ω

THD+N = 1%; f = 1kHz, SE, Mode 4

MONO

OUT f = 20Hz to 20kHz

P

OUT

= 500mW; R

L

= 8 Ω , BTL, Mode 1

R

OUT and L

OUT f = 20Hz to 20kHz

P

OUT

= 30mW; R

L

= 32 Ω ,SE, Mode 4

A-weighted

(6) input referred

, Mode 5, BTL

Power Supply Rejection Ratio

MONO

OUT

Power Supply Rejection Ratio

R

OUT and L

OUT

V

RIPPLE

C

B

= 200mV

= 2.2µF, BTL

PP

; f = 217Hz,

All audio inputs terminated into 50 Ω ; output referred gain = 6dB (BTL)

Output Mode 1, 7

Output Mode 3

Output Mode 5

V

RIPPLE

C

B

= 200mV

PP

= 2.2µF, SE, C

O

; f = 217Hz,

= 100 μ F

All audio inputs terminated into 50 Ω ; output referred gain,

OCL = 0 (

Table 2 )

Output Mode 2

Output Mode 4

Output Mode 6, 7

Digital Volume Range

(R

IN and L

IN

)

Input referred maximum attenuation

Input referred maximum gain

Mute Attenuation Output Mode 1, 3, 5

Maximum gain setting

MONO_IN Input Impedance

R

IN and L

IN

Input Impedance

Minimum gain setting

T

WU

Wake-Up Time from Shutdown

C

B

C

B

= 2.2

μ F, OCL

= 2.2

μ

, SE

(1)

(2)

(3)

(4)

(5)

(6)

Human body model, 100pF discharged through a 1.5k

Ω resistor.

All voltages are measured with respect to the ground pin, unless otherwise specified.

Typical specifications are specified at +25°C and represent the most likely parametric norm.

Tested limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level).

Potentially worse case: All three input stages are DC coupled to the BTL output stage.

Datasheet min/max specifications are specified by design, test, or statistical analysis.

3.6

6.8

0.1

10

1.15

75

0.5

0.5

26

71

68

63

88

76

76

-54

18

80

11

100

122

184

–53.25

–54.75

17.25

18.75

mA mA

µA mV

W mW

%

%

µV dB dB dB dB dB k Ω k Ω k Ω k Ω dB dB dB dB dB dB ms

8

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I

2

C/SPI

(1) (2)

t

ES t

DH t

EH t

CL t

CH t

4 t

5 f

SPI t

EL t

DS t

CS

V

IH t

1 t

2 t

3

The following specifications apply for V

DD

= 5.0V and 3.3V, T

A

= 25°C unless otherwise specified.

Symbol Parameter Conditions LM4845

Typical

(3)

Limits

(4) (5)

I

2

C Clock Period

I

2

C Clock Setup Time

I

2

C Data Hold Time

2.5

100

100

Start Condition Time

Stop Condition Time

100

100

V

IL

Maximum SPI Frequency

SPI ENB Low Time

SPI Data Setup Time

SPI ENB Setup Time

SPI Data Hold Time

SPI Enable Hold Time

SPI Clock Low Time

SPI Clock High Time

SPI Clock Transition Time

I

2

C/SPI Input Voltage High

I

2

C/SPI Input Voltage Low

1000

100

100

100

100

100

500

500

100

0.7xI

2

CSPI

V

DD

0.3xI

2

CSPI

V

DD

Units

(Limits)

V (max)

(1)

(2)

(3)

(4)

(5)

Operating Ratings indicate conditions for which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the Electrical Characteristics. The ensured specifications apply only for the test conditions listed.

Some performance characteristics may degrade when the device is not operated under the listed test conditions.

All voltages are measured with respect to the ground pin, unless otherwise specified.

Typical specifications are specified at +25°C and represent the most likely parametric norm.

Tested limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level).

Potentially worse case: All three input stages are DC coupled to the BTL output stage.

µs (max) ns (min) ns (min) ns (min) ns (min) kHz (max) ns (min)

µs (max) ns (min) ns (min) ns (min) ns (min) ns (min) ns (min)

V (min)

External Components Description

1

8

9

4

5

2

3

6

7

10

Components

C

IN

C

SUPPLY

C

BYPASS

C

3DL

C

3DR

C

OL

C

OR

C

I2CSPI_SUPPLY

R

3DL

R

3DR

Functional Description

This is the input coupling capacitor. It blocks the DC voltage and couples the input signal to the amplifier's input terminals. C

IN also creates a highpass filter with the internal resistor R i

(Input Impedance) at f c

= 1/(2 π R i

C

IN

).

This is the supply bypass capacitor. It filters the supply voltage applied to the V

DD pin.

This is the BYPASS pin capacitor. It filters the 1/2V

DD voltage.

This is the left channel 3D capacitor.

This is the right channel 3D capacitor.

This is the left channel DC blocking output capacitor.

This is the right channel DC blocking output capacitor.

This is the I

2

C/SPI supply bypass capacitor. It filters the I

2

C/SPI supply voltage applied to the I

2

C/SPI_V

DD pin.

This is the left channel 3D external resistor. OPTIONAL.

This is the right channel 3D external resistor. OPTIONAL.

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Typical Performance Characteristics

10

V

DD

THD+N vs Frequency

= 3.3V, R

L

= 8 Ω , P

O

Mode 1, BTL

= 250mW

10

V

DD

THD+N vs Frequency

= 3.3V, R

L

= 32 Ω , P

Mode 4, OCL

O

= 12mW www.ti.com

1

1

0.1

0.01

20 100 1k

FREQUENCY (Hz)

Figure 5.

10k 20k

10

V

DD

THD+N vs Frequency

= 3.3V, R

L

= 32 Ω , P

Mode 6, OCL

O

= 12mW

1

0.1

0.01

20 100 1k

FREQUENCY (Hz)

Figure 6.

10k 20k

10

V

DD

THD+N vs Frequency

= 3.3V, R

L

= 32 Ω , P

Mode 4, SE

O

= 12mW

1

0.1

0.1

0.01

20 100 1k

FREQUENCY (Hz)

Figure 7.

10k 20k

10

V

DD

THD+N vs Frequency

= 3.3V, R

L

= 32 Ω , P

Mode 6, SE

O

= 12mW

1

0.01

20 100 1k

FREQUENCY (Hz)

Figure 8.

10k 20k

10

V

DD

THD+N vs Frequency

= 3.3V, R

L

= 8 Ω , P

Mode 5

O

= 250mW

1

0.1

0.1

0.01

20 100 1k

FREQUENCY (Hz)

Figure 9.

10k 20k

10

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0.01

20 100 1k

FREQUENCY (Hz)

Figure 10.

10k 20k

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10

V

DD

Typical Performance Characteristics (continued)

THD+N vs Frequency

= 5V, R

L

= 8 Ω , P

O

Mode 1, BTL

= 500mW V

DD

THD+N vs Frequency

= 5V, R

L

= 32 Ω , P

Mode 4, OCL

O

= 30mW

10

1

1

0.1

0.01

20 100 1k

FREQUENCY (Hz)

Figure 11.

10k 20k

10

V

DD

THD+N vs Frequency

= 5V, R

L

= 32 Ω , P

Mode 4, SE

O

= 30mW

1

0.1

1

0.1

0.01

20 100 1k

FREQUENCY (Hz)

Figure 13.

10k 20k

10

V

DD

THD+N vs Frequency

= 5V, R

L

= 32 Ω , P

Mode 6, SE

O

= 30mW

0.01

20 100 1k

FREQUENCY (Hz)

Figure 15.

10k 20k

0.1

0.01

20 100 1k

FREQUENCY (Hz)

Figure 12.

10k 20k

10

V

DD

THD+N vs Frequency

= 5V, R

L

= 32 Ω , P

Mode 6, OCL

O

= 30mW

1

0.1

0.01

20 100 1k

FREQUENCY (Hz)

Figure 14.

10k 20k

10

V

DD

THD+N vs Frequency

= 5V, R

L

= 8 Ω , P

Mode 5

O

= 500mW

1

0.1

0.01

20 100 1k

FREQUENCY (Hz)

Figure 16.

10k 20k

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Typical Performance Characteristics (continued)

V

THD+N vs Output Power

DD

= 3.3V, R

L

= 8 Ω , f = 1kHz

Mode 1, BTL

V

THD+N vs Output Power

DD

= 3.3V, R

L

= 8 Ω , f = 1kHz

Mode 5, BTL

10

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1 1

1

0.1

0.1

0.01

10m 100m

OUTPUT POWER (W)

Figure 17.

10

THD+N vs Output Power

V

DD

= 3.3V, R

L

= 32 Ω , f = 1kHz

Mode 4, OCL

1

1

0.1

0.1

0.01

10m 100m

OUTPUT POWER (W)

Figure 18.

10

THD+N vs Output Power

V

DD

= 3.3V, R

L

= 32 Ω , f = 1kHz

Mode 4, SE

1

1

0.1

0.01

10m

OUTPUT POWER (W)

Figure 19.

10

THD+N vs Output Power

V

DD

= 3.3V, R

L

= 32 Ω , f = 1kHz

Mode 6, OCL

100m

0.01

10m

OUTPUT POWER (W)

Figure 21.

100m

1

0.1

0.01

10m

OUTPUT POWER (W)

Figure 20.

10

THD+N vs Output Power

V

DD

= 3.3V, R

L

= 32 Ω , f = 1kHz

Mode 6, SE

100m

0.01

10m

OUTPUT POWER (W)

Figure 22.

100m

12

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10

SNAS255L – MARCH 2005 – REVISED MAY 2013

Typical Performance Characteristics (continued)

V

THD+N vs Output Power

DD

= 5V, R

L

= 8 Ω , f = 1kHz

Mode 1, BTL

10

V

THD+N vs Output Power

DD

= 5V, R

L

= 8 Ω , f = 1kHz

Mode 5, BTL

1 1

1

0.1

0.1

0.01

20m 200 m

OUTPUT POWER (W)

Figure 23.

V

THD+N vs Output Power

DD

= 5V, R

L

= 32 Ω , f = 1kHz

Mode 4, OCL

10

2

0.01

10m

OUTPUT POWER (W)

Figure 25.

V

THD+N vs Output Power

DD

= 5V, R

L

= 32 Ω , f = 1kHz

Mode 6, OCL

10

100m

1

0.1

0.01

10m

OUTPUT POWER (W)

Figure 27.

100m

1

0.1

0.1

0.01

20m 200m

OUTPUT POWER (W)

Figure 24.

V

THD+N vs Output Power

DD

= 5V, R

L

= 32 Ω , f = 1kHz

Mode 4, SE

10

2

1

0.1

0.01

10m

OUTPUT POWER (W)

Figure 26.

V

THD+N vs Output Power

DD

= 5V, R

L

= 32 Ω , f = 1kHz

Mode 6, SE

10

100m

0.01

10m

OUTPUT POWER (W)

Figure 28.

100m

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SNAS255L – MARCH 2005 – REVISED MAY 2013

-60

-70

-80

-90

-100

20

0

-10

-20

-30

-40

-50

Typical Performance Characteristics (continued)

PSRR vs Frequency

V

DD

= 3.3V, 0dB

Mode 4, OCL

PSRR vs Frequency

V

DD

= 3.3V, 0dB

Mode 4, SE

0

200 2k 20k

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

20

FREQUENCY (Hz)

Figure 29.

200 2k

FREQUENCY (Hz)

Figure 30.

PSRR vs Frequency

V

DD

= 3.3V, 0dB

Mode 6, OCL

PSRR vs Frequency

V

DD

= 3.3V, 0dB

Mode 6, SE

-50

-60

-70

-80

-90

-100

20

0

-10

-20

-30

-40

20k

-50

-60

-70

-80

-90

-100

20

0

-10

-20

-30

-40

200 2k

FREQUENCY (Hz)

Figure 31.

PSRR vs Frequency

V

DD

= 3.3V, 6dB

Mode 1, BTL

200 2k

FREQUENCY (Hz)

Figure 32.

PSRR vs Frequency

V

DD

= 3.3V, 6dB

Mode 5, BTL

-50

-60

-70

-80

-90

0

-10

-20

-30

-40

-100

20 20k

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

20 200 2k

FREQUENCY (Hz)

Figure 33.

200 2k

FREQUENCY (Hz)

Figure 34.

20k

20k

20k

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60

50

40

30

20

100

90

80

70

10

0

20

40

30

20

10

0

20

100

90

80

70

60

50

100

90

80

70

60

50

40

30

20

10

0

20

SNAS255L – MARCH 2005 – REVISED MAY 2013

V

DD

Typical Performance Characteristics (continued)

Noise

= 3.3V, Mode 4, OCL V

DD

100

Noise

= 3.3V, Mode 4, SE

90

80

200 2k 20k

70

60

50

40

30

20

10

0

20 200 2k

FREQUENCY (Hz)

Figure 35.

FREQUENCY (Hz)

Figure 36.

20k

V

DD

Noise

= 3.3V, Mode 6, SE

200 2k

FREQUENCY (Hz)

Figure 37.

V

DD

Noise

= 3.3V, Mode 1, BTL

200 2k

FREQUENCY (Hz)

Figure 39.

20k

20k

300

250

200

150

100

50

0

0

V

DD

Noise

= 3.3V, Mode 5, BTL

60

50

40

30

20

100

90

80

70

10

0

20 200 2k

FREQUENCY (Hz)

Figure 38.

20k

350

Power Dissipation vs Output Power

V

DD

= 3.3V, R

L

= 8 Ω f = 1kHz, BTL, Mode 1, BTL

100 200 300 400

OUTPUT POWER (mW)

Figure 40.

500 600

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LM4845

SNAS255L – MARCH 2005 – REVISED MAY 2013

Typical Performance Characteristics (continued)

350

Power Dissipation vs Output Power

V

DD

= 3.3V, R

L

= 8 Ω f = 1kHz, BTL, Mode 5

60

Power Dissipation vs Output Power

V

DD

= 3.3V, R

L

= 32 Ω f = 1kHz, OCL, Mode 4 www.ti.com

300

50

250

200

40

30

150

100

20

10

50

0

0

0

0 12

100 200 300 400

OUTPUT POWER (mW)

Figure 41.

500 600

2 4 6 8

OUTPUT POWER (mW)

Figure 42.

10

25

Power Dissipation vs Output Power

V

DD

= 3.3V, R

L

= 32 Ω f = 1kHz, OCL, Mode 6

60

Power Dissipation vs Output Power

V

DD

= 3.3V, R

L

= 32 Ω f = 1kHz, SE, Mode 4

50

20

15

40

30

10

5

20

10

25

20

15

10

5

0

0

0

0 10 20 30

OUTPUT POWER (mW)

Figure 43.

40

30

Power Dissipation vs Output Power

V

DD

= 3.3V, R

L

= 32 Ω f = 1kHz, SE, Mode 6

50

50 10 20 30

OUTPUT POWER (mW)

Figure 45.

40

0

0

2 4 6 8

OUTPUT POWER (mW)

Figure 44.

10 12

700

Power Dissipation vs Output Power

V

DD

= 5V, R

L

= 8 Ω f = 1kHz, BTL, Mode 1

600

500

400

300

200

100

0

0 0.5

1.0

OUTPUT POWER (mW)

Figure 46.

1.5

16

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SNAS255L – MARCH 2005 – REVISED MAY 2013

Typical Performance Characteristics (continued)

700

Power Dissipation vs Output Power

V

DD

= 5V, R

L

= 8 Ω f = 1kHz, BTL, Mode 5

700

Power Dissipation vs Output Power

V

DD

= 5V, R

L

= 32 Ω f = 1kHz, OCL, Mode 4

600

600

500

400

300

200

500

400

300

200

100

100

0

0 1.5

0

0 1.5

0.5

1.0

OUTPUT POWER (mW)

Figure 47.

0.5

1. 0

OUTPUT POWER (mW)

Figure 48.

450

Power Dissipation vs Output Power

V

DD

= 5V, R

L

= 32 Ω f = 1kHz, OCL, Mode 6

400

200

150

100

50

350

300

250

0

0 20 40 60 80 100

OUTPUT POWER (mW)

Figure 49.

60

Power Dissipation vs Output Power

V

DD

= 5V, R

L

= 32

Ω f = 1kHz, SE, Mode 6

50

40

30

20

10

0

0 2 4 6 8

OUTPUT POWER (mW)

Figure 51.

10 12

140

Power Dissipation vs Output Power

V

DD

= 5V, R

L

= 32 Ω f = 1kHz, SE, Mode 4

120

100

40

20

80

60

0

0 5 10 15 20 25

OUTPUT POWER (mW)

Figure 50.

30 35

0

V

DD

Crosstalk vs Frequency

= 3.3V, R

L

= 32

, P

O

= 12mW

Right-Left, OCL, Mode 4

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

20 200 2k 20k

FREQUENCY (Hz)

Figure 52.

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LM4845

SNAS255L – MARCH 2005 – REVISED MAY 2013

-10

0

V

DD

Typical Performance Characteristics (continued)

Crosstalk vs Frequency

= 3.3V, R

L

= 32 Ω , P

O

= 12mW

Right-Left, OCL, Mode 6

V

DD

Crosstalk vs Frequency

= 3.3V, R

L

= 32 Ω , P

O

= 12mW

Right-Left, SE, Mode 4

0

-10

-20

-20

-30

-40

-30

-40

-50

-50

-60

-70

-60

-70

-80

-80

-90

-100

20 200 2k 20k

-90

-100

20 200 2k 20k

FREQUENCY (Hz)

Figure 53.

FREQUENCY (Hz)

Figure 54.

www.ti.com

0

V

DD

Crosstalk vs Frequency

= 3.3V, R

L

= 32 Ω , P

O

= 12mW

Right-Left, SE, Mode 6

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

20 200 2k 20k

FREQUENCY (Hz)

Figure 55.

400

Supply Current vs Supply Voltage

R

L

= 8

, Mode 5

350

300

250

200

150

100

50

0

3 4

V

DD

(V)

Figure 57.

5 6

450

Supply Current vs Supply Voltage

R

L

= 8 Ω , Mode 1

400

350

150

100

50

300

250

200

0

3 4

V

DD

(V)

Figure 56.

5 6

90

Supply Current vs Supply Voltage

R

L

= 32

, OCL, Mode 4

80

30

20

10

0 b

70

60

50

40

4

V

DD

(V)

Figure 58.

5 6

18

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SNAS255L – MARCH 2005 – REVISED MAY 2013

30

20

10

70

60

50

40

90

Typical Performance Characteristics (continued)

Supply Current vs Supply Voltage

R

L

= 32 Ω , OCL, Mode 6

60

Supply Current vs Supply Voltage

R

L

= 32 Ω , SE, Mode 4

80

50

40

30

20

10

0

3 6

0

3 4

V

DD

(V)

Figure 59.

5 4

V

DD

(V)

Figure 60.

5 6

60

Supply Current vs Supply Voltage

R

L

= 32 Ω , SE, Mode 6

50

40

30

20

10

0

3 4

V

DD

(V)

Figure 61.

5 6

1.2

1.0

0.8

0.6

0.4

0.2

1.6

Output Power vs Supply Voltage

R

L

= 8 Ω , Mode 5

1.4

0

3 4

V

DD

(V)

Figure 63.

5 6

1.6

Output Power vs Supply Voltage

R

L

= 8 Ω , Mode 1

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

3 4

V

DD

(V)

Figure 62.

5 6

90

Output Power vs Supply Voltage

R

L

= 32 Ω , Mode 4

80

70

60

50

40

30

20

10

0

3 4

V

DD

(V)

Figure 64.

5 6

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LM4845

SNAS255L – MARCH 2005 – REVISED MAY 2013

60

Typical Performance Characteristics (continued)

Output Power vs Supply Voltage

R

L

= 32 Ω , OCL, Mode 6

90

Output Power vs Supply Voltage

R

L

= 32 Ω , SE, Mode 4

80

50

40

70

60

50

30

20

40

30

10

0

3 6

20

10

0

3 4

V

DD

(V)

Figure 65.

5 4

V

DD

(V)

Figure 66.

5 6

www.ti.com

90

Output Power vs Supply Voltage

R

L

= 32 Ω , SE, Mode 6

80

70

60

50

40

30

20

10

0

3 4

V

DD

(V)

Figure 67.

5 6

20

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APPLICATION INFORMATION

I

2

C PIN DESCRIPTION

SDA: This is the serial data input pin.

SCL: This is the clock input pin.

ID_ENB: This is the address select input pin.

I

2

CSPI_SEL: This is tied LOW for I

2

C mode.

SNAS255L – MARCH 2005 – REVISED MAY 2013

I

2

C COMPATIBLE INTERFACE

The LM4845 uses a serial bus which conforms to the I

2

C protocol to control the chip's functions with two wires: clock (SCL) and data (SDA). The clock line is uni-directional. The data line is bi-directional (open-collector). The maximum clock frequency specified by the I

2

C standard is 400kHz. In this discussion, the master is the controlling microcontroller and the slave is the LM4845.

The I

2

C address for the LM4845 is determined using the ID_ENB pin. The LM4845's two possible I

2

C chip addresses are of the form 111110X

1 logic HIGH. If the I

2

0 (binary), where X

1

= 0, if ID_ENB is logic LOW; and X

1

= 1, if ID_ENB is

C interface is used to address a number of chips in a system, the LM4845's chip address can be changed to avoid any possible address conflicts.

The bus format for the I

2

C interface is shown in sections:

Figure 68 . The bus format diagram is broken up into six major

The "start" signal is generated by lowering the data signal while the clock signal is HIGH. The start signal will alert all devices attached to the I

2

C bus to check the incoming address against their own address.

The 8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the clock.

Each address bit must be stable while the clock level is HIGH.

For I

2

C interface operation, the I

2

CSPI_SEL pin needs to be tied LOW (and tied high for SPI operation).

After the last bit of the address bit is sent, the master releases the data line HIGH (through a pull-up resistor).

Then the master sends an acknowledge clock pulse. If the LM4845 has received the address correctly, then it holds the data line LOW during the clock pulse. If the data line is not held LOW during the acknowledge clock pulse, then the master should abort the rest of the data transfer to the LM4845.

The 8 bits of data are sent next, most significant bit first. Each data bit should be valid while the clock level is stable HIGH.

After the data byte is sent, the master must check for another acknowledge to see if the LM4845 received the data.

If the master has more data bytes to send to the LM4845, then the master can repeat the previous two steps until all data bytes have been sent.

The "stop" signal ends the transfer. To signal "stop", the data signal goes HIGH while the clock signal is HIGH.

The data line should be held HIGH when not in use.

I

2

C INTERFACE POWER SUPPLY PIN (I

2

CV

DD

)

The LM4845's I

2

C interface is powered up through the I

2

CV

DD pin. The LM4845's I

2

C interface operates at a voltage level set by the I

2

CV

DD pin which can be set independent to that of the main power supply pin V is ideal whenever logic levels for the I

2

DD

. This

C interface are dictated by a microcontroller or microprocessor that is operating at a lower supply voltage than the main battery of a portable system.

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LM4845

SNAS255L – MARCH 2005 – REVISED MAY 2013

Figure 68. I

2

C Bus Format www.ti.com

Figure 69. I

2

C Timing Diagram

SPI DESCRIPTION

0. I

2

CSPI_SEL: This pin is tied HIGH for SPI mode.

1. The data bits are transmitted with the MSB first.

2. The maximum clock rate is 1MHz for the CLK pin.

3. CLK must remain HIGH for at least 500ns (t

CH least 500ns (t

CL

) after the falling edge of CLK.

) after the rising edge of CLK, and CLK must remain LOW for at

4. The serial data bits are sampled at the rising edge of CLK. Any transition on DATA must occur at least 100ns

(t

DS

) before the rising edge of CLK. Also, any transition on DATA must occur at least 100ns (t

DH

) after the rising edge of CLK and stabilize before the next rising edge of CLK.

5.ID_ENB should be LOW only during serial data transmission.

6. ID_ENB must be LOW at least 100ns (t

ES

LOW at least 100ns (t

EH

) before the first rising edge of CLK, and ID_ENB has to remain

) after the eighth rising edge of CLK.

7. If ID_ENB remains HIGH for more than 100ns before all 8 bits are transmitted then the data latch will be aborted.

8. If ID_ENB is LOW for more than 8 CLK pulses then only the first 8 data bits will be latched and activated when

ID_ENB transitions to logic-high.

9. ID_ENB must remain HIGH for at least 100ns (t

EL

) to latch in the data.

10. Coincidental rising or falling edges of CLK and ID_ENB are not allowed. If CLK is to be held HIGH after the data transmission, the falling edge of CLK must occur at least 100ns (t

CS the next set of data.

) before ID_ENB transitions to LOW for

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ID_ENB t

CS t

ES t

CH t

CL t

EH

CLK

DATA t

DS t

DH

Data 7 Data 6 Data 1 Data 0 t

EL

Figure 70. SPI Timing Diagram

Chip Address

ID_ENB = 0

ID_ENB = 1

A7

1

1

1

A6

1

1

1

A5

1

1

1

Table 1. Chip Address

A4

1

1

1

A3

1

1

1

A2

0

0

0

A1

EC

0

1

Mode Control

Programmable 3D

Mono Volume Control

Left Volume Control

Right Volume Control

D7

0

0

1

1

1

D6

0

1

0

1

1

D5

0

0

0

0

1

Table 2. Control Registers

(1)

D4

0

0

MVC4

LVC4

RVC4

D3

OCL

N3D3

MVC3

LVC3

RVC3

D2

MC2

N3D2

MVC2

LVC2

RVC2

D1

MC1

N3D1

MVC1

LVC1

RVC1

(1) 1. Bits MVC0 — MVC4 control 32 step volume control for MONO input

2. Bits LVC0 — LVC4 control 32 step volume control for LEFT input

3. Bits RVC0 — RVC4 control 32 step volume control for RIGHT input

4. Bits MC0 — MC2 control 8 distinct modes

5. Bits N3D3, N3D2, N3D1, N3D0 control programmable 3D function

6. N3D0 turns the 3D function ON (N3D0 = 1) or OFF (N3D0 = 0), and N3D1 = 0 provides a “wider” aural effect or N3D1 = 1 a

“narrower” aural effect

7. Bit OCL selects between SE with output capacitor (OCL = 0) or SE without output capacitors (OCL = 1). Default is OCL = 0

8. N3D1 selects between two different 3D configurations

D0

MC0

N3D0

MVC0

LVC0

RVC0

A0

0

0

0

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LM4845

SNAS255L – MARCH 2005 – REVISED MAY 2013

Low

Medium

High

Maximum

Table 3. Programmable National 3D Audio

N3D3

0

0

1

1

MC0

Table 4. Output Mode Selection

(1)

Handsfree Speaker Output Right HP Output Output Mode

Number

0

1

2

3

4

5

MC2

0

0

0

0

1

1

MC1

0

0

1

1

0

0

0

1

0

1

0

1

6

7

1

1

1

1

0

1

(1) On initial POWER ON, the default mode is 000

P = Phone in

R = R

IN

L = L

IN

SD = Shutdown

MUTE = Mute Mode

G

P

G

R

G

L

= Phone In (Mono) volume control gain

= Right stereo volume control gain

= Left stereo volume control gain

SD

2 x G

P x P

SD

2 x (G

L x L + G

R x R)

SD

2 x (G

L x L + G

R

P) x R + G

P x

SD

2 x G

P x P

SD

MUTE

G

P x P

MUTE

G

R x R

MUTE

G

R x R + G

P x P

G

R x R + G

P x P

N3D2

0

1

0

1

www.ti.com

Left HP Output

SD

MUTE

G

P x P

MUTE

G

L x L

MUTE

G

L x L + G

P x P

G

L x L + G

P x P

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Volume Step xVC4

17

18

19

20

21

12

13

14

15

16

7

8

9

5

6

10

11

1

2

3

4

30

31

32

27

28

29

22

23

24

25

26

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

1

1

1

1

1

0

0

1

0

0

1

1

0

0

0

0

1

1

1

1

1

1

0

0

0

1

1

(1) 1.

2.

x = M, L, or R

Gain / Attenuation is from input to output

SNAS255L – MARCH 2005 – REVISED MAY 2013 xVC3

Table 5. Volume Control Table

(1)

xVC2 xVC1 xVC0

0

0

0

0

1

0

1

1

1

1

1

1

0

1

1

0

0

0

0

0

0

1

1

1

0

0

1

1

1

1

0

0

0

1

0

1

0

1

0

1

0

1

0

1

0

0

1

1

0

0

1

0

1

1

0

1

0

1

0

1

0

1

0

1

0

0

1

1

0

1

0

0

1

1

1

1

0

0

0

0

1

0

0

1

1

0

1

1

1

1

0

0

1

1

0

0

–12.00

–10.50

–9.00

–7.50

–6.00

–4.50

–3.00

–1.50

0.00

1.50

Headphone

Gain, dB

–54.00

–46.50

–40.50

–34.50

–30.00

–27.00

–24.00

–21.00

–18.00

–15.00

–13.50

10.50

12.00

13.50

15.00

16.50

18.00

3.00

4.50

6.00

7.50

9.00

1.50

3.00

4.50

6.00

7.50

–6.00

–4.50

–3.00

–1.50

0.00

Speaker Gain, dB (BTL)

–48.00

–40.50

–34.50

–28.50

–24.00

–21.00

–18.00

–15.00

–12.00

–9.00

–7.50

9.00

10.50

12.00

13.50

15.00

16.50

18.00

19.50

21.00

22.50

24.00

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TEXAS INSTRUMENTS 3D ENHANCEMENT

The LM4845 features a stereo headphone, 3D audio enhancement effect that widens the perceived soundstage from a stereo audio signal. The 3D audio enhancement creates a perceived spatial effect optimized for stereo headphone listening. The LM4845 can be programmed for a “narrow” or “wide” soundstage perception. The narrow soundstage has a more focused approaching sound direction, while the wide soundstage has a spatial, theater-like effect. Within each of these two modes, four discrete levels of 3D effect that can be programmed:

low, medium, high, and maximum ( Table 2

), each level with an ever increasing aural effect, respectively. The difference between each level is 3dB.

The external capacitors, shown in

Figure 71 , are required to enable the 3D effect. The value of the capacitors set

the cutoff frequency of the 3D effect, as shown by

Equation 1

and

Equation 2 . Note that the internal 20k

Ω resistor is nominal (±25%).

20 k : (internal resistor )

LM4845

C

3DL

C

3DR

Figure 71. External 3D Effect Capacitors

f

3DL(-3dB)

= 1 / 2 π f

3DR(-3dB)

= 1 / 2

π

* 20k Ω * C

3DL

* 20k

* C

3DR

Optional resistors R

3DL and R

3DR can also be added (

Figure 72 ) to affect the -3dB frequency and 3D magnitude.

(1)

(2)

20 k

:

(internal resistor )

LM4845

C

3DL

C

3DR

R

3DL

R

3DR

Figure 72. External RC Network with Optional R

3DL and R

3DR

Resistors

f

3DL(-3dB)

= 1 / 2 π * (20k Ω + R

3DL

) * C

3DL f

3DR(-3dB)

= 1 / 2 π * 20k Ω + R

3DR

) * C

3DR

(3)

(4)

Δ AV (change in AC gain) = 1 / 1 + M, where M represents some ratio of the nominal internal resistor, 20k Ω example below).

(see f

3dB

(3D) = 1 / 2 π (1 + M)(20k Ω * C

3D

)

C

Equivalent

(new) = C

3D

/ 1 + M

(5)

(6)

R

3D

(k Ω )

(optional)

C

3D

(nF) M

Table 6. Pole Locations

Δ AV (dB) f-3dB (3D)

(Hz)

Value of C

3D to keep same pole location

(nF) new Pole

Location

(Hz)

0

1

5

10

20

68

68

68

68

68

0

0.05

0.25

0.50

1.00

0

–0.4

–1.9

–3.5

–6.0

117

111

94

78

59

64.8

54.4

45.3

34.0

117

117

117

117

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PCB LAYOUT AND SUPPLY REGULATION CONSIDERATIONS FOR DRIVING 8

LOAD

Power dissipated by a load is a function of the voltage swing across the load and the load's impedance. As load impedance decreases, load dissipation becomes increasingly dependent on the interconnect (PCB trace and wire) resistance between the amplifier output pins and the load's connections. Residual trace resistance causes a voltage drop, which results in power dissipated in the trace and not in the load as desired. For example, 0.1

Ω trace resistance reduces the output power dissipated by an 8 Ω load from 158.3mW to 156.4mW. The problem of decreased load dissipation is exacerbated as load impedance decreases. Therefore, to maintain the highest load dissipation and widest output voltage swing, PCB traces that connect the output pins to a load must be as wide as possible.

Poor power supply regulation adversely affects maximum output power. A poorly regulated supply's output voltage decreases with increasing load current. Reduced supply voltage causes decreased headroom, output signal clipping, and reduced output power. Even with tightly regulated supplies, trace resistance creates the same effects as poor supply regulation. Therefore, making the power supply traces as wide as possible helps maintain full output voltage swing.

BRIDGE CONFIGURATION EXPLANATION

The LM4845 drives a load, such as a speaker, connected between outputs, MONO+ and MONO-.

This results in both amplifiers producing signals identical in magnitude, but 180° out of phase. Taking advantage of this phase difference, a load is placed between MONO- and MONO+ and driven differentially (commonly referred to as ”bridge mode”). This results in a differential or BTL gain of:

A

VD

= 2(R f

/ R i

) = 2 (7)

Bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single amplifier's output and ground. For a given supply voltage, bridge mode has a distinct advantage over the singleended configuration: its differential output doubles the voltage swing across the load. Theoretically, this produces four times the output power when compared to a single-ended amplifier under the same conditions. This increase in attainable output power assumes that the amplifier is not current limited and that the output signal is not clipped.

Another advantage of the differential bridge output is no net DC voltage across the load. This is accomplished by biasing MONO- and MONO+ outputs at half-supply. This eliminates the coupling capacitor that single supply, single-ended amplifiers require. Eliminating an output coupling capacitor in a typical single-ended configuration forces a single-supply amplifier's half-supply bias voltage across the load. This increases internal IC power dissipation and may permanently damage loads such as speakers.

POWER DISSIPATION

Power dissipation is a major concern when designing a successful single-ended or bridged amplifier.

A direct consequence of the increased power delivered to the load by a bridge amplifier is higher internal power dissipation. The LM4845 has a pair of bridged-tied amplifiers driving a handsfree speaker, MONO. The maximum internal power dissipation operating in the bridge mode is twice that of a single-ended amplifier. From

Equation 8 ,

assuming a 5V power supply and an 8 Ω load, the maximum MONO power dissipation is 634mW.

P

DMAX-SPKROUT

= 4(V

DD

)

2

/ (2 π

2

R

L

): Bridge Mode (8)

The LM4845 also has a pair of single-ended amplifiers driving stereo headphones, R

OUT internal power dissipation for R

OUT and L

OUT is given by

Equation 9

and

Equation 10

and L

OUT

. From

. The maximum

Equation 9

and

Equation 10 , assuming a 5V power supply and a 32

Ω load, the maximum power dissipation for L

OUT and R

OUT is

40mW, or 80mW total.

P

DMAX-LOUT

P

DMAX-ROUT

= (V

DD

)

2

= (V

DD

)

2

/ (2 π

2

/ (2 π

2

R

L

): Single-ended Mode

R

L

): Single-ended Mode

(9)

(10)

The maximum internal power dissipation of the LM4845 occurs when all 3 amplifiers pairs are simultaneously on; and is given by

Equation 11 .

P

DMAX-TOTAL

= P

DMAX-SPKROUT

+ P

DMAX-LOUT

+ P

DMAX-ROUT

(11)

The maximum power dissipation point given by

Equation 12

:

P

DMAX

= (T

JMAX

- T

A

) / θ

JA

Equation 11

must not exceed the power dissipation given by

(12)

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The LM4845's T

JMAX temperature T

A

, use

= 150°C. In the ITL package, the LM4845's

Equation 12

θ

JA is 65°C/W. At any given ambient to find the maximum internal power dissipation supported by the IC packaging.

Rearranging

Equation 12

and substituting P

DMAX-TOTAL for P

DMAX

' results in

Equation 13 . This equation gives the

maximum ambient temperature that still allows maximum stereo power dissipation without violating the LM4845's maximum junction temperature.

T

A

= T

JMAX

- P

DMAX-TOTAL

θ

JA

(13)

For a typical application with a 5V power supply and an 8 Ω load, the maximum ambient temperature that allows maximum stereo power dissipation without exceeding the maximum junction temperature is approximately 104°C for the ITL package.

T

JMAX

= P

DMAX-TOTAL

θ

JA

+ T

A

(14)

Equation 14

gives the maximum junction temperature T

JMAX

. If the result violates the LM4845's 150°C, reduce the maximum junction temperature by reducing the power supply voltage or increasing the load resistance.

Further allowance should be made for increased ambient temperatures.

The above examples assume that a device is a surface mount part operating around the maximum power dissipation point. Since internal power dissipation is a function of output power, higher ambient temperatures are allowed as output power or duty cycle decreases. If the result of

Equation 11

is greater than that of

Equation 12 ,

then decrease the supply voltage, increase the load impedance, or reduce the ambient temperature. If these measures are insufficient, a heat sink can be added to reduce θ

JA

. The heat sink can be created using additional copper area around the package, with connections to the ground pin(s), supply pin and amplifier output pins.

External, solder attached SMT heatsinks such as the Thermalloy 7106D can also improve power dissipation.

When adding a heat sink, the

θ

CS

θ

JA is the sum of

Typical Performance Characteristics

θ is the case-to-sink thermal impedance, and

JC

,

θ

θ

SA

CS

, and θ

SA

. ( θ

JC is the junction-to-case thermal impedance, is the sink-to-ambient thermal impedance). Refer to the curves for power dissipation information at lower output power levels.

POWER SUPPLY BYPASSING

As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. Applications that employ a 5V regulator typically use a 1µF in parallel with a 0.1µF filter capacitors to stabilize the regulator's output, reduce noise on the supply line, and improve the supply's transient response.

However, their presence does not eliminate the need for a local 1.1µF tantalum bypass capacitance connected between the LM4845's supply pins and ground. Keep the length of leads and traces that connect capacitors between the LM4845's power supply pin and ground as short as possible. Connecting a 2.2µF capacitor, C

B

, between the BYPASS pin and ground improves the internal bias voltage's stability and improves the amplifier's

PSRR. The PSRR improvements increase as the bypass pin capacitor value increases. Too large, however, increases turn-on time and can compromise the amplifier's click and pop performance. The selection of bypass capacitor values, especially C

B

, depends on desired PSRR requirements, click and pop performance (as explained in the section, Proper Selection of External Components), system cost, and size constraints.

SELECTING EXTERNAL COMPONENTS

Input Capacitor Value Selection

Amplifying the lowest audio frequencies requires high value input coupling capacitor (C i in

Figure 1

&

Figure 2 ).

A high value capacitor can be expensive and may compromise space efficiency in portable designs. In many cases, however, the speakers used in portable systems, whether internal or external, have little ability to reproduce signals below 150Hz. Applications using speakers with this limited frequency response reap little improvement by using large input capacitor.

The internal input resistor (R i

), nominal 20k Ω , and the input capacitor (C i

) produce a high pass filter cutoff frequency that is found using

Equation 15 .

f c

= 1 / (2 π R i

C i

) (15)

As an example when using a speaker with a low frequency limit of 150Hz, C i

0.22µF C i shown in

Figure 1

, using

Equation 15

is 0.053µF. The allows the LM4845 to drive high efficiency, full range speaker whose response extends below 40Hz.

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Bypass Capacitor Value Selection

Besides minimizing the input capacitor size, careful consideration should be paid to value of C

B connected to the BYPASS bump. Since C

B

, the capacitor determines how fast the LM4845 settles to quiescent operation, its value is critical when minimizing turn-on pops. The slower the LM4845's outputs ramp to their quiescent DC voltage (nominally V

DD

/2), the smaller the turn-on pop. Choosing C

B equal to 1.0µF along with a small value of C i

(in the range of 0.1µF to 0.39µF), produces a click-less and pop-less shutdown function. As discussed above, choosing C i no larger than necessary for the desired bandwidth helps minimize clicks and pops. C

B

's value should be in the range of 5 times to 7 times the value of C i

. This ensures that output transients are eliminated when power is first applied or the LM4845 resumes operation after shutdown.

LM4845 ITL DEMO BOARD ARTWORK

Figure 73. Top Overlay

Figure 74. Top Layer

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Rev

1.0

1.1

1.2

1.3

1.4

REVISION HISTORY

Date

11/08/05

12/21/05

01/10/06

01/11/06

07/06/06

Description

Fixed some typos, then re-released D/S to the WEB (per Allan).

Edited the X1, X2, and X3 in the mktg outline, then re-released D/S to the WEB.

Fixed typo, then re-released doc to the WEB.

Fixed more typo, then re-released doc to the

WEB.

Added the Twu row in the 3.3V and 5.0V EC tables ( per Allan S.), then re-released D/S to the WEB.

Changes from Revision K (May 2013) to Revision L Page

• Changed layout of National Data Sheet to TI format ..........................................................................................................

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PACKAGE OPTION ADDENDUM

www.ti.com

2-May-2013

PACKAGING INFORMATION

Orderable Device

LM4845ITL/NOPB

Status

(1)

ACTIVE

Package Type Package

Drawing

Pins Package

Qty

DSBGA YZR 25 250

Eco Plan

(2)

Green (RoHS

& no Sb/Br)

Lead/Ball Finish

SNAGCU

MSL Peak Temp

(3)

Level-1-260C-UNLIM

Op Temp (°C)

-40 to 85 GE5

Top-Side Markings

(4)

LM4845ITLX/NOPB ACTIVE DSBGA YZR 25 3000 Green (RoHS

& no Sb/Br)

SNAGCU Level-1-260C-UNLIM -40 to 85

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

GE5

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)

Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Samples

Addendum-Page 1

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TAPE AND REEL INFORMATION

PACKAGE MATERIALS INFORMATION

8-May-2013

*All dimensions are nominal

Device Package

Type

Package

Drawing

Pins

LM4845ITL/NOPB

LM4845ITLX/NOPB

DSBGA

DSBGA

YZR

YZR

25

25

SPQ

250

3000

Reel

Diameter

(mm)

Reel

Width

W1 (mm)

178.0

8.4

178.0

8.4

A0

(mm)

2.69

2.69

B0

(mm)

2.69

2.69

K0

(mm)

P1

(mm)

W

(mm)

Pin1

Quadrant

0.76

0.76

4.0

4.0

8.0

8.0

Q1

Q1

Pack Materials-Page 1

www.ti.com

PACKAGE MATERIALS INFORMATION

8-May-2013

*All dimensions are nominal

Device

LM4845ITL/NOPB

LM4845ITLX/NOPB

Package Type

DSBGA

DSBGA

Package Drawing

YZR

YZR

Pins

25

25

SPQ

250

3000

Length (mm)

210.0

210.0

Width (mm)

185.0

185.0

Height (mm)

35.0

35.0

Pack Materials-Page 2

MECHANICAL DATA

YZR0025xxx

0.600±0.075

D

E

TLA25XXX (Rev D)

D: Max = 2.581 mm, Min = 2.52 mm

E: Max = 2.561 mm, Min = 2.5 mm

NOTES:

A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.

B. This drawing is subject to change without notice.

4215055/A 12/12

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed.

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