ADM7151 (Rev. A)

Data Sheet

FEATURES

Input voltage range: 4.5 V to 16 V

Maximum output current: 800 mA

Adjustable output from 1.5 V to 5.1 V

Low noise

1.0 μV rms total integrated noise from 100 Hz to 100 kHz

1.6 μV rms total integrated noise from 10 Hz to 100 kHz

Noise spectral density: 1.7 nV√Hz from 10 kHz to 1 MHz

Power supply rejection ratio (PSRR) at 400 mA load

>90 dB from 1 kHz to 100 kHz, V

OUT

= 5 V

>60 dB at 1 MHz, V

OUT

= 5 V

Dropout voltage: 0.6 V at V

OUT

= 5 V, 800 mA load

Initial voltage accuracy: ±1%

Voltage accuracy over line, load and temperature: ±2%

Quiescent current (I

GND

): 4.3 mA at no load

Low shutdown current: 0.1 μA

Stable with a 10 μF ceramic output capacitor

8-lead LFCSP package and 8-lead SOIC package

APPLICATIONS

Regulated power noise sensitive applications

RF mixers, phase-locked loops (PLLs), voltage-controlled oscillators (VCOs), and PLLs with integrated VCOs

Clock distribution circuits

Ultrasound and other imaging applications

High speed RF transceivers

High speed, 16-bit or greater ADCs

Communications and infrastructure

Cable digital-to-analog converter (DAC) drivers

GENERAL DESCRIPTION

The ADM7151 is a low dropout (LDO) linear regulator that operates from 4.5 V to 16 V and provides up to 800 mA of output current. Using an advanced proprietary architecture, it provides high power supply rejection (>90 dB from 1 kHz to 1 MHz), ultralow noise (1.7 nV√Hz from 10 kHz to 1 MHz), and excellent line and load transient response with a 10 μF ceramic output capacitor. The output voltage can be set to any voltage between

1.5 V and 5.1 V with two resistors.

The ADM7151 is available in two models that optimize power dissipation and PSRR performance as a function of input and

output voltage. See Table 6 and Table 7 for selection guides.

The ADM7151 regulator output noise is 1.0 μV rms from

100 Hz to 100 kHz, and the noise spectral density is 1.7 nV/√Hz from 10 kHz to 1 MHz.

The ADM7151 is available in 8-lead, 3 mm × 3 mm LFCSP and

8-lead SOIC packages, making it not only a very compact solution,

Rev. A Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registered trademarks are the property of their respective owners.

800 mA Ultralow Noise,

High PSRR, RF Linear Regulator

ADM7151

V

IN

= 6.2V

TYPICAL APPLICATION CIRCUIT

ADM7151-04

C

IN

10µF

VIN VOUT

V

OUT

= 5.0V

C

OUT

10µF

ON

EN REF

OFF

V

BYP

C

BYP

1µF

BYP

REF_SENSE

C

REF

1µF

R1

V

OUT

= 1.5V × (R1 + R2)/R2

V

REG

C

REG

10µF

VREG

GND

R2

1kΩ < R2 < 200kΩ

Figure 1. ADM7151-04 with V

OUT

= 5 V

but also providing excellent thermal performance for applications requiring up to 800 mA of output current in a small, low profile footprint.

100k

10k

C

BYP

C

BYP

C

BYP

C

BYP

= 1µF

= 10µF

= 100µF

= 1mF

1k

100

10

1

0.1

1 10 100 1k

FREQUENCY (Hz)

10k 100k 1M

Figure 2. Noise Spectral Density (NSD) vs. Frequency for Various C

BYP

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ADM7151* PRODUCT PAGE QUICK LINKS

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COMPARABLE PARTS

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EVALUATION KITS

• ADM7150 and ADM7151 Evaluation Board

DOCUMENTATION

Data Sheet

• ADM7151: 800 mA Ultralow Noise, High PSRR, RF Linear

Regulator Data Sheet

TOOLS AND SIMULATIONS

• ADI Linear Regulator Design Tool and Parametric Search

• ADIsimPower™ Voltage Regulator Design Tool

REFERENCE MATERIALS

Press

• Ultra-Low-Noise RF Low-Dropout Regulators Reduce

Phase Noise in Wideband Communication Systems

Solutions Bulletins & Brochures

• Ultralow Noise, High Rejection Low Dropout Regulators

DESIGN RESOURCES

• ADM7151 Material Declaration

• PCN-PDN Information

• Quality And Reliability

• Symbols and Footprints

DISCUSSIONS

View all ADM7151 EngineerZone Discussions.

SAMPLE AND BUY

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ADM7151

TABLE OF CONTENTS

Features........................................................................................... 1

Applications ................................................................................... 1

Typical Application Circuit ........................................................... 1

General Description ...................................................................... 1

Revision History ............................................................................ 2

Specifications ................................................................................. 3

Input and Output Capacitor, Recommended Specifications .. 4

Absolute Maximum Ratings ......................................................... 5

Thermal Data ............................................................................. 5

Thermal Resistance ................................................................... 5

ESD Caution............................................................................... 5

Pin Configurations and Function Descriptions .......................... 6

Typical Performance Characteristics............................................ 7

REVISION HISTORY

4/15—Rev. 0 to Rev. A

Change to Figure 4..........................................................................6

Change to Figure 39......................................................................12

9/13—Revision 0: Initial Version

Data Sheet

Theory of Operation.................................................................... 15

Applications Information............................................................ 16

Model Selection ....................................................................... 16

Capacitor Selection.................................................................. 16

Enable (EN) and Undervoltage Lockout (UVLO) ................ 18

Start-Up Time .......................................................................... 19

REF, BYP, and VREG Pins....................................................... 19

Current-Limit and Thermal Overload Protection ................ 19

Thermal Considerations ......................................................... 19

Printed Circuit Board Layout Considerations....................... 22

Outline Dimensions .................................................................... 23

Ordering Guide........................................................................ 24

Rev. A | Page 2 of 24

Data Sheet ADM7151

SPECIFICATIONS

V

IN

= 4.5 V, V

OUT

= 1.5 V, V

REF

= V

REF_SENSE

(unity gain), V

EN

= V

IN

, I

OUT

= 10 mA, C

IN

= C

OUT

= C

REG

= 10 µF, C

REF

= C for typical specifications. T

J

= −40°C to +125°C for minimum/maximum specifications, unless otherwise noted.

BYP

= 1 µF. T

A

= 25°C

Table 1.

Parameter

INPUT VOLTAGE RANGE

OPERATING SUPPLY CURRENT

SHUTDOWN CURRENT

OUTPUT NOISE

Symbol

V

IN

I

GND

I

IN-SD

OUT

NOISE

Test Conditions/Comments

I

I

OUT

OUT

= 0 µA

= 800 mA

V

EN

= GND

10 Hz to 100 kHz, independent of output voltage

100 Hz to 100 kHz, independent of output voltage

Min Typ Max Unit

4.5 16 V

4.3 7.0

8.6 12

0.1 3

1.6

1.0 mA mA

µA

µV rms

µV rms

NOISE SPECTRAL DENSITY

POWER SUPPLY REJECTION RATIO

ADM7151-04

ADM7151-02

V

OUT

VOLTAGE ACCURACY

Voltage Accuracy

V

OUT

REGULATION

Line Regulation

Load Regulation 1

CURRENT-LIMIT THRESHOLD

V

REF

Current Limit Threshold

V

OUT

Current Limit Threshold

2

DROPOUT VOLTAGE

3

PULL-DOWN RESISTANCE

V

OUT

Pull-Down Resistance

V

REG

Pull-Down Resistance

V

REF

Pull-Down Resistance

V

BYP

Pull-Down Resistance

START-UP TIME 4

V

OUT

Start-Up Time

V

REG

Start-Up Time

V

REF

Start-Up Time

THERMAL SHUTDOWN

Thermal Shutdown Threshold

Thermal Shutdown Hysteresis

UNDERVOLTAGE THRESHOLDS

Input Voltage Rising

Input Voltage Falling

Hysteresis t

START-UP t

REG-START-UP t

REF-START-UP

TS

SD

TS

SD-HYS

UVLO

RISE

UVLO

FALL

UVLO

HYS

ΔV

OUT

/ΔV

IN

ΔV

OUT

/ΔI

OUT

I

LIMIT

V

DROPOUT

V

OUT-PULL

V

REG-PULL

V

REF-PULL

V

BYP-PULL

NSD

PSRR

V

OUT

10 kHz to 1 MHz, independent of output voltage

1 kHz to 100 kHz, V

IN

= 6.2 V, V

OUT

= 5 V at 800 mA

1 MHz, V

IN

= 6.2 V, V

OUT

= 5 V at 800 mA

1 kHz to 100 kHz, V

IN

= 6.2 V, V

OUT

= 5 V at 400 mA

1 MHz, V

IN

= 6.2 V, V

OUT

= 5 V at 400 mA

1 kHz to 100 kHz, V

IN

= 5.2 V, V

OUT

= 4 V at 800 mA

1 MHz, V

IN

= 5.2 V, V

OUT

= 4 V at 800 mA

1 kHz to 100 kHz, V

IN

= 5.2 V, V

OUT

= 4 V at 400 mA

1 MHz, V

IN

= 5.2 V, V

OUT

= 4 V at 400 mA

V

OUT

= V

REF

I

OUT

= 10 mA

1 mA < I

OUT

< 800 mA, over line, load and temperature

−1

−2

V

IN

= 4.5 V to 16 V

I

OUT

= 1 mA to 800 mA

I

OUT

= 400 mA, V

OUT

= 5 V

I

OUT

= 800 mA, V

OUT

= 5 V

V

EN

= 0 V, V

OUT

= 1 V

V

EN

= 0 V, V

REG

= 1 V

V

EN

= 0 V, V

REF

= 1 V

V

EN

= 0 V, V

BYP

= 1 V

V

OUT

= 5 V

T

J

rising

T

J

= −40°C to +125°C

T

J

= −40°C to +125°C

1.7

84

53

94

67

91

50

94

58

+1

+2

−0.01

0.5 1.0

+0.01 %/V

%/A

1.0

20

1.3 1.6 mA

A

0.30 0.60 V

0.60 1.20 V

600

34

800

Ω kΩ

Ω

500

2.8

1.0

1.8

155

15

°C

°C

3.85

240

4.49 V

V mV

Ω ms ms ms

%

% nV/√Hz dB dB dB dB dB dB dB dB

Rev. A | Page 3 of 24

ADM7151 Data Sheet

Parameter

V

REG

5 UNDERVOLTAGE THRESHOLDS

V

REG

Rise

V

REG

Fall

Hysteresis

EN INPUT

EN Input Logic High

EN Input Logic Low

EN Input Logic Hysteresis

Symbol Test Conditions/Comments

VREGUVLO

RISE

T

J

= −40°C to +125°C

VREGUVLO

FALL

T

J

= −40°C to +125°C

VREGUVLO

HYS

EN

EN

EN

HIGH

LOW

HYS

4.5 V ≤ V

IN

≤ 16 V

V

IN

= 5 V

Min Typ Max Unit

3.1 V

2.55

210

3.2

225

0.8

V mV

V

V mV

EN Input Leakage Current I

EN-LKG

V

EN

= V

IN

or GND 0.1 1.0 µA

1

Based on an end-point calculation using

1 mA

and 800 mA loads. See Figure 6 and Figure 13 for typical load regulation performance for loads less than

1 mA

.

2

Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 5.0 V output voltage is defined as the current that causes the output voltage to drop to 90% of 5.0 V, or 4.5 V.

3 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to achieve the nominal output voltage. Dropout applies only for

4 output voltages above 4.5 V.

Start-up time is defined as the time between the rising edge of V , V

REG

5

The output voltage is turned off until the V

REG

EN

to V

OUT

, or V

UVLO rise threshold is crossed. The V

REF

being at 90% of its nominal value.

REG

output is turned off until the input voltage UVLO rising threshold is crossed.

INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS

Table 2.

Parameter

CAPACITANCE

Minimum Input

1

Minimum Regulator

1

Minimum Output

1

Symbol

C

IN

C

REG

C

OUT

Test Conditions/Comments

T

A

= −40°C to +125°C

Min

7.0

7.0

7.0

Typ Max Unit

µF

µF

µF

Minimum Bypass

Minimum Reference

C

C

BYP

REF

0.1

0.7

µF

µF

CAPACITOR EQUIVALENT SERIES RESISTANCE (ESR) R

ESR

T

A

= −40°C to +125°C

C

REG

, C

OUT

, C

IN

, C

REF

0.001 0.2 Ω

C

BYP

0.001 2.0 Ω

1 The minimum input, regulator, and output capacitance must be greater than 7.0 µF over the full range of operating conditions. The full range of operating conditions in the application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended; however, Y5V and Z5U capacitors are not recommended for use with any LDO.

Rev. A | Page 4 of 24

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VIN to GND

VREG to GND

VOUT to GND

VOUT to BYP

EN to GND

BYP to GND

REF to GND

REF_SENSE to GND

Storage Temperature Range

−0.3 V to +18 V

−0.3 V to VIN, or +6 V

(whichever is less)

−0.3 V to VREG, or +6 V

(whichever is less)

±0.3 V

−0.3 V to18 V

−0.3 V to VREG, or +6 V

(whichever is less)

−0.3 V to VREG, or +6 V

(whichever is less)

−0.3 V to +6 V

−65°C to +150°C

Junction Temperature 150°C

Operating Ambient Temperature Range –40°C to +125°C

Soldering Conditions JEDEC J-STD-020

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability.

THERMAL DATA

Absolute maximum ratings apply individually only, not in combination. The

ADM7151

can be damaged when the junction temperature limits are exceeded. Monitoring ambient temperature does not guarantee that T

J

is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the maximum ambient temperature may have to be derated.

In applications with moderate power dissipation and low printed circuit board (PCB) thermal resistance, the maximum ambient temperature can exceed the maximum limit as long as the junction temperature is within specification limits. The junction temperature (T ambient temperature (T

A

J

) of the device is dependent on the

), the power dissipation of the device

(P

D

), and the junction to ambient thermal resistance of the package (θ

JA

).

Maximum junction temperature (T ambient temperature (T

A formula

J

) is calculated from the

) and power dissipation (P

D

) using the

T

J

= T

A

+ (P

D

× θ

JA

)

ADM7151

Junction to ambient thermal resistance (θ

JA

) of the package is based on modeling and calculation using a 4-layer board. The junction to ambient thermal resistance is highly dependent on the application and board layout. In applications where high maximum power dissipation exists, close attention to thermal board design is required. The value of θ

JA

may vary, depending on

PCB material, layout, and environmental conditions. The specified values of θ

JA

are based on a 4-layer, 4 in. × 3 in. circuit board.

See JESD51-7 and JESD51-9 for detailed information on the board construction.

Ψ

JB

is the junction to board thermal characterization parameter with units of °C/W. Ψ

JB

of the package is based on modeling and the calculation using a 4-layer board. The JESD51-12, Guidelines for

Reporting and Using Electronic Package Thermal Information, states that thermal characterization parameters are not the same as thermal resistances. Ψ

JB

measures the component power flowing through multiple thermal paths rather than a single path as in thermal resistance (θ

JB

). Therefore, Ψ

JB

thermal paths include convection from the top of the package as well as radiation from the package, factors that make Ψ

JB

more useful in real-world applications. Maximum junction temperature (T

J

) is calculated from the board temperature (T

B

) and power dissipation (P

D

) using the formula

T

J

= T

B

+ (P

D

× Ψ

JB

)

See JESD51-8 and JESD51-12 for more detailed information about Ψ

JB

.

THERMAL RESISTANCE

θ

JA

, θ

JC

, and Ψ

JB

are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type θ

JA

8-Lead LFCSP

8-Lead SOIC

36.7

36.9

ESD CAUTION

θ

JC

23.5

27.1

Ψ

JB

13.3

18.6

Unit

°C/W

°C/W

Rev. A | Page 5 of 24

ADM7151

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

VREG 1

VOUT 2

BYP 3

GND 4

ADM7151

TOP VIEW

(Not to Scale)

8 VIN

7 EN

6 REF

5 REF_SENSE

NOTES

1. EXPOSED PAD ON THE BOTTOM OF THE PACKAGE.

EXPOSED PAD ENHANCES THERMAL PERFORMANCE AND IS

ELECTRICALLY CONNECTED TO GND INSIDE THE PACKAGE.

CONNECT THE EXPOSED PAD TO THE GROUND PLANE ON

THE BOARD TO ENSURE PROPER OPERATION.

Figure 3. 8-Lead LFCSP Pin Configuration

Data Sheet

VREG

1

VOUT

2

BYP

3

GND

4

ADM7151

TOP VIEW

(Not to Scale)

6

5

8

7

VIN

EN

REF

REF_SENSE

NOTES

1. EXPOSED PAD ON THE BOTTOM OF THE PACKAGE.

EXPOSED PAD ENHANCES THERMAL PERFORMANCE AND IS

ELECTRICALLY CONNECTED TO GND INSIDE THE PACKAGE.

CONNECT THE EXPOSED PAD TO THE GROUND PLANE ON

THE BOARD TO ENSURE PROPER OPERATION.

Figure 4. 8-Lead SOIC Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 VREG Regulated Input Supply to LDO Amplifier. Bypass VREG to GND with a 10 μF or greater capacitor. Do not connect a load to ground.

2

3

VOUT

BYP

Regulated Output Voltage. Bypass VOUT to GND with a 10 μF or greater capacitor.

Low Noise Bypass Capacitor. Connect a 1 μF capacitor to GND to reduce noise. Do not connect a load to ground.

5 REF_SENSE External Resistor Divider Used to Set the Output Voltage. V

OUT

= V

REF

× (R1 + R2)/R2, where V

REF

= 1.5 V.

6 REF Low Noise Reference Voltage Output. Bypass REF to GND with a 1 μF capacitor. Short REF_SENSE to REF for fixed output voltages. Do not connect a load to ground.

7 EN Enable. Drive EN high to turn on the regulator and drive EN low to turn off the regulator. For automatic startup, connect EN to VIN.

8 VIN Regulator Input Supply. Bypass VIN to GND with a 10 μF or greater capacitor.

EP EP Exposed Pad on the Bottom of the Package. Exposed pad enhances thermal performance and is electrically connected to GND inside the package. Connect the exposed pad to the ground plane on the board to ensure proper operation.

Rev. A | Page 6 of 24

Data Sheet ADM7151

TYPICAL PERFORMANCE CHARACTERISTICS

V

IN

= V

OUT

+ 1.2 V or V

IN

= 4.5 V, whichever is greater, EN = V

IN

, I

OUT

= 10 mA, C

IN

= C unless otherwise noted.

OUT

= C

REG

= 10 µF, C

REF

= C

BYP

= 1 µF, T

A

= 25°C,

4.04

4.03

4.02

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 400mA

LOAD = 800mA

10

9

8

7

4.01

6

4.00

5

4

3.99

3.98

3.97

3.96

–40 –5 25 85 125

JUNCTION TEMPERATURE (°C)

Figure 5. Output Voltage (V

OUT

) vs. Junction Temperature (T

J

V

OUT

= 4 V

), ADM7151-02 ,

3

2

1

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 400mA

LOAD = 800mA

0

–40 –5 25 85 125

JUNCTION TEMPERATURE (°C)

Figure 8. Ground Current vs. Junction Temperature (T

J

V

OUT

= 4 V

), ADM7151-02 ,

4.04

4.03

4.02

4.01

4.00

3.99

3.98

3.97

3.96

1 10 100 1000

I

LOAD

(mA)

Figure 6. Output Voltage (V

OUT

V

) vs. Load Current (I

OUT

= 4 V

LOAD

), ADM7151-02 ,

4.04

4.03

4.02

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 400mA

LOAD = 800mA

4.01

4.00

3.99

3.98

3.97

3.96

5 6 7 8 9 10 11 12 13 14 15 16

V

IN

(V)

Figure 7. Output Voltage (V

OUT

V

) vs. Input Voltage (V

OUT

= 4 V

IN

), ADM7151-02 ,

10

9

8

7

6

5

4

3

2

1

0

1 10 100 1000

I

LOAD

(mA)

Figure 9. Ground Current vs. Load Current (I

LOAD

), ADM7151-02 , V

OUT

= 4 V

10

9

8

7

6

5

4

3

2

1

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 400mA

LOAD = 800mA

0

5 6 7 8 9 10 11 12 13 14 15 16

V

IN

(V)

Figure 10. Ground Current vs. Input Voltage (V

IN

), ADM7151-02 , V

OUT

= 4 V

Rev. A | Page 7 of 24

ADM7151

10

1

V

IN

= 6.2V

V

IN

= 6.5V

V

IN

= 7.0V

V

IN

= 10V

V

IN

= 16V

0.1

0.01

0.001

0.0001

–40 –5 25 85 125

TEMPERATURE (°C)

Figure 11. Shutdown Current vs. Temperature at Various Input Voltages

5.00

4.99

4.98

4.97

4.96

4.95

4.94

4.93

4.92

4.91

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 400mA

LOAD = 800mA

4.90

–40 –5 25 85 125

JUNCTION TEMPERATURE (°C)

Figure 12. Output Voltage (V

OUT

) vs. Junction Temperature (T

J

V

OUT

= 5 V

), ADM7151-04 ,

5.00

4.99

4.98

4.97

4.96

4.95

4.94

4.93

4.92

4.91

4.90

1 10 100 1000

I

LOAD

(mA)

Figure 13. Output Voltage (V

OUT

V

) vs. Load Current (I

OUT

= 5 V

LOAD

), ADM7151-04 ,

Data Sheet

5.00

4.99

4.98

4.97

4.96

4.95

4.94

4.93

4.92

4.91

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 400mA

LOAD = 800mA

4.90

6 8 10 12 14 16

Figure 14. Output Voltage (V

V

IN

(V)

OUT

) vs. Input Voltage (V

V

OUT

= 5 V

IN

), ADM7151-04 ,

10

9

8

7

6

5

4

3

2

1

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 400mA

LOAD = 800mA

0

–40 –5 25 85 125

JUNCTION TEMPERATURE (°C)

Figure 15. Ground Current vs. Junction Temperature (T

J

V

OUT

= 5 V

), ADM7151-04 ,

10

9

8

7

6

5

4

3

2

1

0

1 10 100 1000

I

LOAD

(mA)

Figure 16. Ground Current vs. Load Current (I

LOAD

V

OUT

= 5 V

), ADM7151-04 ,

Rev. A | Page 8 of 24

Data Sheet

10

9

8

7

6

5

4

3

2

1

LOAD = 1mA

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 400mA

LOAD = 800mA

0

6 8 10 12 14 16

V

IN

(V)

Figure 17. Ground Current vs. Input Voltage (V

IN

), ADM7151-04 , V

OUT

= 5 V

700

600

500

400

300

200

100

0

1 10 100 1000

I

LOAD

(mA)

Figure 18. Dropout Voltage vs. Load Current (I

LOAD

), ADM7151-04 , V

OUT

= 5 V

5.2

5.0

4.8

4.6

4.4

4.2

V

DROPOUT

V

DROPOUT

V

DROPOUT

= 5mA

= 10mA

= 100mA

V

DROPOUT

= 200mA

V

DROPOUT

= 400mA

V

DROPOUT

= 800mA

4.0

4.6

4.8

5.0

5.2

5.4

5.6

5.8

6.0

V

IN

(V)

Figure 19. Output Voltage (V

OUT

) vs. Input Voltage (V

ADM7151-04 , V

OUT

= 5 V

IN

) in Dropout,

ADM7151

8

6

12

10

4

2

I

GND

= 5mA

I

GND

= 10mA

I

GND

= 100mA

I

GND

= 200mA

I

GND

I

GND

= 400mA

= 800mA

0

4.6

4.8

5.0

5.2

5.4

5.6

5.8

6.0

V

IN

(V)

Figure 20. Ground Current vs. Input Voltage (V

IN

V

OUT

= 5 V

) in Dropout, ADM7151-04 ,

–80

–90

–100

–110

–40

–50

–60

–70

0

–10

–20

–30

LOAD = 800mA

LOAD = 400mA

LOAD = 200mA

LOAD = 100mA

LOAD = 10mA

–120

1 10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 21. Power Supply Rejection Ratio (PSRR) vs. Frequency, ADM7151-02 ,

V

OUT

= 4 V

–80

–90

–100

–110

–40

–50

–60

–70

0

–10

–20

–30

LOAD = 800mA

LOAD = 400mA

LOAD = 200mA

LOAD = 100mA

LOAD = 10mA

–120

1 10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 22. Power Supply Rejection Ratio (PSRR) vs. Frequency, ADM7151-04 ,

V

OUT

= 5 V

Rev. A | Page 9 of 24

ADM7151

0

–10

–20

600mV

700mV

800mV

900mV

–30

1.0V

1.1V

1.2V

1.3V

1.4V

–80

–90

–100

–110

–40

–50

–60

–70

–120

1 10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 23. Power Supply Rejection Ratio (PSRR) vs. Frequency for Various

Headroom Voltages, ADM7151-02 , V

OUT

= 4 V, 400 mA Load

0

–10

–20

–80

–90

–100

–110

–30

–40

–50

–60

–70

600mV

700mV

800mV

900mV

1.0V

1.1V

1.2V

1.4V

1.6V

1.8V

–120

1 10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 24. Power Supply Rejection Ratio (PSRR) vs. Frequency for Various

Headroom Voltages, ADM7151-04 , V

OUT

= 5 V, 400 mA Load

0

–20

10Hz

100Hz

1kHz

10kHz

100kHz

1MHz

10MHz

–40

–60

–80

–100

–120

0.5

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

HEADROOM (V)

Figure 25. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,

ADM7151-02 , V

OUT

= 4 V, 100 mA Load

Data Sheet

0

–20

–40

–60

–80

–100

10Hz

100Hz

1kHz

10kHz

100kHz

1MHz

10MHz

–120

0.6

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

HEADROOM (V)

Figure 26. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,

ADM7151-02 , V

OUT

= 4 V, 400 mA Load

0

–20

–40

–60

–80

–100

10Hz

100Hz

1kHz

10kHz

100kHz

1MHz

10MHz

–120

0.7

0.8

0.9

1.0

1.1

1.2

1.3

1.4

1.5

1.6

HEADROOM (V)

Figure 27. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,

ADM7151-02 , V

OUT

= 4 V, 800 mA Load

0

–20

–40

–60

–80

–100

–120

10Hz

100Hz

1kHz

10kHz

100kHz

1MHz

10MHz

–140

0.3

0.5

0.7

0.9

1.1

1.3

1.5

HEADROOM (V)

Figure 28. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,

ADM7151-04 , V

OUT

= 5 V, 100 mA Load

Rev. A | Page 10 of 24

Data Sheet

0

10Hz

100Hz

1kHz

10kHz

100kHz

1MHz

10MHz

–20

–40

–60

–80

–100

–120

0.6

0.8

1.0

1.2

1.4

1.6

1.8

HEADROOM (V)

Figure 29. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,

ADM7151-04 , V

OUT

= 5 V, 400 mA Load

0

–20

10Hz

100Hz

1kHz

10kHz

100kHz

1MHz

10MHz

–40

–60

–80

–100

–120

0.7

0.9

1.1

1.3

1.5

1.7

HEADROOM (V)

Figure 30. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,

ADM7151-04 , V

OUT

= 5 V, 800 mA Load

2.0

0.8

0.4

1.6

1.2

10Hz TO 100kHz

0

10 100 1000

LOAD CURRENT (mA)

Figure 31. RMS Output Noise vs. Load Current (I

ADM7151-04 , V

OUT

= 5 V

LOAD

), 10 Hz to 100 kHz,

ADM7151

1.2

0.8

2.0

1.6

0.4

100Hz TO 100kHz

0

10 100 1000

LOAD CURRENT (mA)

Figure 32. RMS Output Noise vs. Load Current (I

LOAD

ADM7151-04 , V

OUT

= 5 V

), 100 Hz to 100 kHz,

2.0

0.8

0.4

1.6

1.2

0.8

0.4

1.6

1.2

10Hz TO 100kHz

0

10 100 1000

LOAD CURRENT (mA)

Figure 33. RMS Output Noise vs. Load Current (I

LOAD

ADM7151-02 , V

OUT

= 4 V

), 10 Hz to 100 kHz,

2.0

100Hz TO 100kHz

0

10 100 1000

LOAD CURRENT (mA)

Figure 34. RMS Output Noise vs. Load Current (I

LOAD

ADM7151-02 , V

OUT

= 4 V

), 100 Hz to 100 kHz,

Rev. A | Page 11 of 24

ADM7151

10

1

0.1

1k 10k 100k

FREQUENCY (Hz)

1M 10M

Figure 35. Output Noise Spectral Density, 1 kHz to 10 MHz, I

LOAD

= 10 mA

100k

10k

1k

100

10

1

0.1

1 10 100

FREQUENCY (Hz)

1k 10k 100k

Figure 36. Output Noise Spectral Density, 0.1 Hz to 10 kHz, I

LOAD

= 10 mA

1k

100

LOAD = 800mA

LOAD = 400mA

LOAD = 200mA

LOAD = 100mA

LOAD = 10mA

10

1

0.1

10 100 1k 10k

FREQUENCY (Hz)

100k 1M 10M

Figure 37. Output Noise Spectral Density at Different Load Currents,

10 Hz to 10 MHz

1

2

Data Sheet

100k

10k

1k

LOAD = 10mA

LOAD = 100mA

LOAD = 200mA

LOAD = 400mA

LOAD = 800mA

100

10

1

0.1

1 10 100 1k

FREQUENCY (Hz)

10k 100k 1M

Figure 38. Output Noise Spectral Density at Different Load Currents,

0.1 Hz to 1 MHz

100k

10k

C

C

C

BYP

BYP

BYP

= 1µF

= 4.7µF

C

BYP

= 10µF

= 22µF

C

BYP

C

BYP

C

BYP

= 47µF

= 100µF

= 470µF

1k

100

10

1

0.1

1 10 100 1k

FREQUENCY (Hz)

10k 100k 1M

Figure 39. Output Noise Spectral Density vs. at Different C

BYP

,

Load Current = 10 mA

T

CH1 500mA Ω

B

W

CH2 20mV

B

W

M20µs A CH1 200mA

T 10.40%

Figure 40. Load Transient Response, I

LOAD

= 1 mA to 800 mA,

V

OUT

= 5 V, V

IN

= 6.2 V, CH1 = I

OUT

, CH2 = V

OUT

Rev. A | Page 12 of 24

Data Sheet

T

1

2

CH1 500mA Ω

B

W

CH2 10mV

B

W

M4µs

T 11.0%

A CH1 200mA

Figure 41. Load Transient Response, I

LOAD

= 10 mA to 800 mA,

V

OUT

= 5 V, V

IN

= 6.2 V, CH1 = I

OUT

, CH2 = V

OUT

T

1

2

1

2

CH1 200mA Ω

B

W

CH2 10mV

B

W

M2µs

T 11.0%

A CH1 460mA

Figure 42. Load Transient Response, I

LOAD

= 100 mA to 600 mA,

V

OUT

= 5 V, V

IN

= 6.2 V, CH1 = I

OUT

, CH2 = V

OUT

T

CH1 50.0mA Ω B

W

CH2 2.0mV

B

W

M4µs

T 10.0%

A CH1 50.0mA

Figure 43. Load Transient Response, I

LOAD

= 1 mA to 100 mA,

V

OUT

= 5 V, V

IN

= 6.2 V, CH1 = I

OUT

, CH2 = V

OUT

ADM7151

T

1

2

CH1 1.0V

B

W

CH2 2.0mV Ω

B

W

M10µs

T 10.0%

A CH1 1.14V

Figure 44. Line Transient Response, 2 V Input Step, I

LOAD

= 800 mA,

V

OUT

= 1.8 V, V

IN

= 4.5 V, CH1 = V

IN

, CH2 = V

OUT

T

1

2

CH1 1.0V

B

W

CH2 2.0mV Ω

B

W

M10µs

T 10.0%

A CH3 1.14V

Figure 45. Line Transient Response, 2 V Input Step, I

LOAD

= 800 mA,

V

OUT

= 3.3 V, V

IN

= 4.5 V, CH1 = V

IN

, CH2 = V

OUT

T

1

2

CH1 1.0V

B

W

CH2 2.0mV Ω

B

W

M10µs

T 10.0%

A CH3 1.14V

Figure 46. Line Transient Response, 2 V Input Step, I

LOAD

= 800 mA,

V

OUT

= 5 V, V

IN

= 6.2 V, CH1 = V

IN

, CH2 = V

OUT

Rev. A | Page 13 of 24

ADM7151

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

V

EN

V

REG

V

REF

V

OUT

–0.5

0 1 2 3 4 5

TIME (ms)

6 7 8 9

Figure 47. V

OUT

, V

REF

, V

V

OUT

REG

Start-Up Times After V

= 3.3 V, V

IN

= 5 V

EN

Rising,

10

Data Sheet

Rev. A | Page 14 of 24

Data Sheet

THEORY OF OPERATION

The ADM7151 is an adjustable, ultralow noise, high power supply rejection ratio (PSRR) linear regulator targeting radio frequency (RF) applications. The input voltage range is 4.5 V to

16 V, and it can deliver up to 800 mA of output current. Typical shutdown current consumption is 0.1 μA at room temperature.

Optimized for use with 10 μF ceramic capacitors, the ADM7151 provides excellent transient performance.

VIN

VREG

BYP

ACTIVE

RIPPLE

FILTER

SHORT CIRCUIT,

THERMAL

PROTECT

VOUT

GND

OTA

REFERENCE

E/A

REF_SENSE

REF

SHUTDOWN

EN

Figure 48. Adjustable Output Voltage Internal Block Diagram

Internally, the ADM7151 consists of a reference, an error amplifier, a feedback voltage divider, and a P-channel MOSFET pass transistor. Output current is delivered via the PMOS pass device, which is controlled by the error amplifier. The error amplifier compares the reference voltage with the feedback voltage from the output and amplifies the difference. If the feedback voltage is lower than the reference voltage, the gate of the PMOS device is pulled lower, allowing more current to pass and increasing the output voltage. If the feedback voltage is higher than the reference voltage, the gate of the PMOS device is pulled higher, allowing less current to pass and decreasing the output voltage.

By heavily filtering the reference voltage, the ADM7151 is able to achieve 1.7 nV/√Hz output typical from 10 kHz to 1 MHz.

Because the error amplifier is always in unity gain, the output noise is independent of the output voltage.

To maintain very high PSRR over a wide frequency range, the

ADM7151 architecture uses an internal active ripple filter. This stage isolates the low output noise LDO from noise on VIN.

The result is that the ADM7151 PSRR is significantly higher over a wider frequency range than any single stage LDO.

The ADM7151 output voltage can be adjusted between 1.5 V and 5.1 V and is available in two models that optimize the input voltage and output voltage ranges to keep power dissipation as low as possible without compromising PSRR performance. The output voltage is determined by an external voltage divider according to the following equation:

V

OUT

= 1.5 V × (1 + R1/R2)

ADM7151

ADM7151-04

V

IN

= 6.2V

C

IN

10µF

VIN VOUT

V

OUT

= 5.0V

C

OUT

10µF

ON

OFF

V

BYP

C

BYP

1µF

EN

BYP

REF

C

REF

1µF

REF_SENSE

R1

V

OUT

= 1.5V × (R1 + R2)/R2

V

REG

C

REG

10µF

VREG

GND

R2

1kΩ < R2 < 200kΩ

Figure 49. Typical Adjustable Output Voltage Application Schematic

The R2 value must be greater than 1 kΩ to prevent excessive loading of the reference voltage appearing on the REF pin. To minimize errors in the output voltage caused by the REF_SENSE pin input current, the R2 value must be less than 200 kΩ. For example, when R1 and R2 each equal 200 kΩ, the output voltage is 3.0 V. The output voltage error introduced by the

REF_SENSE pin input current is 10 mV or 0.33%, assuming a maximum REF_SENSE pin input current of 100 nA at 125°C.

The ADM7151 uses the EN pin to enable and disable the VOUT pin under normal operating conditions. When EN is high, VOUT turns on, and when EN is low, VOUT turns off. For automatic startup, EN can be tied to VIN.

VIN

18V

VREG

6V

REF

REF_SENSE

6V

BYP

6V

OUT

EN

18V 6V 6V 6V 6V 6V 18V

GND

Figure 50. Simplified ESD Protection Block Diagram

The ESD protection devices are shown in the block diagram as

Zener diodes (see Figure 50).

Rev. A | Page 15 of 24

ADM7151

APPLICATIONS INFORMATION

MODEL SELECTION

The ADM7151 is available in two models to allow the user to select the best combination of power dissipation and PSRR performance for a given application.

CAPACITOR SELECTION

Output Capacitor

The ADM7151 is designed for operation with ceramic capacitors but functions with most commonly used capacitors as long as care is taken with regard to the effective series resistance (ESR) value. The ESR of the output capacitor affects the stability of the

LDO control loop. A minimum of 10 μF capacitance with an

ESR of 0.2 Ω or less is recommended to ensure the stability of the ADM7151 . Output capacitance also affects transient response to changes in load current. Using a larger value of output capacitance improves the transient response of the

ADM7151

to large changes in load current. Figure 51 shows the

transient responses for an output capacitance value of 10 μF.

T

1

Data Sheet

Input and VREG Capacitor

Connecting a 10 μF capacitor from VIN to GND reduces the circuit sensitivity to PCB layout, especially when long input traces or high source impedance are encountered.

To maintain the best possible stability and PSRR performance, connect a 10 μF capacitor from VREG to GND. When more than 10 μF of output capacitance is required, increase the input and VREG capacitors to match it.

REF Capacitor

The REF capacitor is necessary to stabilize the reference amplifier.

Connect a capacitor of at least 1 μF between REF and GND.

2

CH1 500mA Ω

B

W

CH2 10mV

B

W

M4µs

T 11.0%

A CH1 200mA

Figure 51. Output Transient Response, V

OUT

= 5 V, C

OUT

= 10 μF

Table 6. Model Selection Guide for PSRR

Model V

OUT

Range (V)

ADM7151-02 1.5 to 4.0

ADM7151-04 1.5 to 5.1

PSRR (dB) at 800 mA, 1.2 V Headroom

10 kHz 100 kHz 1 MHz

91

84

91

84

50

53

PSRR (dB) at 400 mA, 1 V Headroom

10 kHz 100 kHz 1 MHz

94

94

94

94

58

67

Table 7. Model Selection Guide for Input Voltage

Model V

OUT

Range (V)

ADM7151-02 1.5 to 4.0

ADM7151-04 1.5 to 5.1

Minimum V

IN

at 800 mA Load Minimum V

IN

at 400 mA Load

V

OUT

< 3.3 V V

OUT

< 5 V V

OUT

≥ 3.3 V V

OUT

≥ 5 V V

OUT

< 3.3 V V

OUT

< 5 V V

OUT

≥ 3.3 V V

OUT

≥ 5 V

4.5 V N/A

1

V

OUT

+ 1.2 V N/A

1

V N/A

1

V

OUT

+ 1.0 V N/A

1

N/A 1 6.2 N/A 1 V

OUT

+ 1.2 V N/A 1 6 1 V

OUT

+ 1.0 V

1

N/A = not applicable.

Rev. A | Page 16 of 24

Data Sheet

BYP Capacitor

The BYP capacitor is necessary to filter the reference buffer. A

1 µF capacitor is typically connected between BYP and GND.

Capacitors as small as 0.1 µF can be used; however, the output noise voltage of the LDO increases as a result.

In addition, the BYP capacitor can be increased to reduce the noise below 1 kHz at the expense of increasing the start-up time of the LDO. Very large values of C

BYP

significantly reduce the noise below 10 Hz. Tantalum capacitors are recommended for capacitors larger than about 33 µF. A 1 µF ceramic capacitor in parallel with the larger tantalum capacitor is required to retain good noise performance at higher frequencies.

100k

10k

1k

C

BYP

= 1µF

C

BYP

= 4.7µF

C

BYP

= 10µF

C

BYP

= 22µF

C

BYP

= 47µF

C

BYP

= 100µF

C

BYP

= 470µF

C

BYP

= 1mF

ADM7151

X5R or X7R dielectrics with a voltage rating of 6.3 V to 50 V are recommended. However, Y5V and Z5U dielectrics are not recommended due to their poor temperature and dc bias characteristics.

Figure 54 depicts the capacitance vs. dc bias voltage of a 1206,

10 µF, 10 V, X5R capacitor. The voltage stability of a capacitor is strongly influenced by the capacitor size and voltage rating. In general, a capacitor in a larger package or higher voltage rating exhibits better stability. The temperature variation of the X5R dielectric is ~±15% over the −40°C to +85°C temperature range and is not a function of package or voltage rating.

12

10

8

6

4

100

2

10

1

0.1

1 10 100 1k 10k 100k 1M

FREQUENCY (Hz)

Figure 52. Noise Spectral Density vs. Frequency, C

BYP

= 1 µF to 1 mF

10k

1k

100

10

1Hz

10Hz

100Hz

400Hz

3Hz

30Hz

300Hz

1kHz

1

1 10 100 1000

C

BYP

(µF)

Figure 53. Noise Spectral Density vs. C

BYP

for Different Frequencies

Capacitor Properties

Any good quality ceramic capacitors can be used with the

ADM7151 as long as they meet the minimum capacitance and maximum ESR requirements. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior over temperature and applied voltage. Capacitors must have a dielectric adequate to ensure the minimum capacitance over the necessary temperature range and dc bias conditions.

0

0 2 4 6

DC BIAS VOLTAGE (V)

8

Figure 54. Capacitance vs. DC Bias Voltage

10

Use Equation 1 to determine the worst-case capacitance accounting for capacitor variation over temperature, component tolerance, and voltage.

C

EFF

= C

BIAS

× (1 − TEMPCO) × (1 − TOL) (1) where:

C

BIAS

is the effective capacitance at the operating voltage.

TEMPCO is the worst-case capacitor temperature coefficient.

TOL is the worst-case component tolerance.

In this example, the worst-case temperature coefficient (TEMPCO) over −40°C to +85°C is assumed to be 15% for an X5R dielectric.

The tolerance of the capacitor (TOL) is assumed to be 10%, and

C

BIAS

is 9.72 µF at 5 V, as shown in Figure 54.

Substituting these values in Equation 1 yields

C

EFF

= 9.72 µF × (1 − 0.15) × (1 − 0.1) = 7.44 µF

Therefore, the capacitor chosen in this example meets the minimum capacitance requirement of the LDO over temperature and tolerance at the chosen output voltage.

To guarantee the performance of the ADM7151 , it is imperative that the effects of dc bias, temperature, and tolerances on the behavior of the capacitors be evaluated for each application.

Rev. A | Page 17 of 24

ADM7151

ENABLE (EN) AND UNDERVOLTAGE LOCKOUT

(UVLO)

The ADM7151 uses the EN pin to enable and disable the VOUT pin under normal operating conditions. As shown in Figure 55, when a rising voltage on EN crosses the upper threshold,

VOUT turns on. When a falling voltage on EN crosses the lower threshold, VOUT turns off. The hysteresis varies as a function of the input voltage. For example, the EN hysteresis is approximately 200 mV with an input voltage of 4.5 V.

3.5

1.5

1.0

0.5

3.0

2.5

2.0

VOUT_EN_FALL

VOUT_EN_RISE

0

1.0

1.1

1.2

1.3

1.4

1.5

1.6

V

EN

(V)

Figure 55. Typical V

OUT

Response to EN Pin Operation, V

OUT

= 3.3 V, V

IN

= 5 V

3.2

2.2

2.0

1.8

1.6

3.0

2.8

2.6

2.4

–40°C

+125°C

+25°C

1.4

6 8 10 12 14 16

V

IN

(V)

Figure 56. Typical EN Rise Threshold vs. Input Voltage (V

Temperatures

IN

) for Various

Data Sheet

2.4

2.2

2.0

1.8

1.6

1.4

1.2

–40°C

+25°C

+125°C

1.0

6 8 10 12 14 16

V

IN

(V)

Figure 57. Typical EN Fall Threshold vs. Input Voltage (V

IN

Temperatures

) for Various

The ADM7151 also incorporates an internal undervoltage lockout circuit to disable the output voltage when the input voltage is less than the minimum input voltage rating of the regulator. The upper and lower thresholds are internally fixed with approximately 300 mV of hysteresis.

3.5

3.0

2.5

2.0

1.5

1.0

VOUT_VIN_FALL

VOUT_VIN_RISE

0.5

0

4.0

4.1

4.2

4.3

4.4

V

IN

(V)

Figure 58. Typical UVLO Hysteresis, V

OUT

= 3.3 V

4.5

Figure 58 shows the typical hysteresis of the UVLO function.

This hysteresis prevents on/off oscillations that can occur due to noise on the input voltage as it passes through the threshold points.

Rev. A | Page 18 of 24

Data Sheet

START-UP TIME

The ADM7151 uses an internal soft start to limit the inrush current when the output is enabled. The start-up time for a 5 V output is approximately 3 ms from the time the EN active threshold is crossed to when the output reaches 90% of its final value.

The rise time of the output voltage (10% to 90%) is approximately

0.0012 × C

BYP

seconds where C

BYP

is in microfarads.

6

5

ENABLE

C

BYP

C

BYP

C

BYP

= 1µF

= 4.7µF

= 10µF

4

3

2

1

0

0 0.002

0.004

0.006

0.008

0.010

0.012

0.014

0.016

0.018

0.020

TIME (Seconds)

Figure 59. Typical Start-Up Behavior with C

BYP

= 1 µF to 10 µF

6

5

4

3

2

1

ENABLE

C

BYP

C

BYP

C

BYP

= 10µF

= 47µF

= 330µF

0

0 0.02

0.04

0.06

0.08

0.10

0.12

TIME (Seconds)

0.14

0.16

0.18

0.20

Figure 60. Typical Start-Up Behavior with C

BYP

= 10 µF to 330 µF

REF, BYP, AND VREG PINS

REF, BYP, and VREG are internally generated voltages that require external bypass capacitors for proper operation. Do not, under any circumstances, connect any loads to these pins because doing so compromises the noise and PSRR performance of the ADM7151 . Using larger values of C

BYP

, C

REF

, and C

REG

is acceptable but can increase the start-up time, as described in

the Start-Up Time section.

CURRENT-LIMIT AND THERMAL OVERLOAD

PROTECTION

The ADM7151 is protected against damage due to excessive power dissipation by current and thermal overload protection circuits. The ADM7151 is designed to current limit when the

Rev. A | Page 19 of 24

ADM7151

output load reaches 1.3 A (typical). When the output load exceeds 1.3 A, the output voltage is reduced to maintain a constant current limit.

Thermal overload protection is included, which limits the junction temperature to a maximum of 155°C (typical). Under extreme conditions (that is, high ambient temperature and/or high power dissipation) when the junction temperature starts to rise above 155°C, the output is turned off, reducing the output current to zero. When the junction temperature drops below

140°C, the output is turned on again, and output current is restored to its operating value.

Consider the case where a hard short from VOUT to GND occurs.

At first, the ADM7151 current limits, so that only 1.3 A is conducted into the short. If self heating of the junction is great enough to cause its temperature to rise above 155°C, thermal shutdown activates, turning off the output and reducing the output current to zero. As the junction temperature cools and drops below 140°C, the output turns on and conducts 1.3 A into the short, again causing the junction temperature to rise above

155°C. This thermal oscillation between 140°C and 155°C causes a current oscillation between 1.3 A and 0 mA that continues as long as the short remains at the output.

Current-limit and thermal limit protections are intended to protect the device against accidental overload conditions. For reliable operation, device power dissipation must be externally limited so that the junction temperature does not exceed 150°C.

THERMAL CONSIDERATIONS

In applications with low input to output voltage differential, the

ADM7151 does not dissipate much heat. However, in applications with high ambient temperature and/or high input voltage, the heat dissipated in the package can become large enough that it causes the junction temperature of the die to exceed the maximum junction temperature of 150°C.

When the junction temperature exceeds 155°C, the converter enters thermal shutdown. It recovers only after the junction temperature decreases below 140°C to prevent any permanent damage. Therefore, thermal analysis for the chosen application is important to guarantee reliable performance over all conditions.

The junction temperature of the die is the sum of the ambient temperature of the environment and the temperature rise of the package due to the power dissipation, as shown in Equation 2.

To guarantee reliable operation, the junction temperature of the

ADM7151 must not exceed 150°C. To ensure that the junction temperature stays below this maximum value, the user must be aware of the parameters that contribute to junction temperature changes. These parameters include ambient temperature, power dissipation in the power device, and thermal resistances between the junction and ambient air (θ

JA

). The θ

JA

number is dependent on the package assembly compounds that are used and the amount of copper used to solder the package GND pin and exposed pad to the PCB.

ADM7151

Table 8 shows typical θ

JA

values of the 8-lead SOIC and 8-lead

LFCSP packages for various PCB copper sizes.

Table 9 shows the typical Ψ

JB

values of the 8-lead SOIC and

8-lead LFCSP.

Table 8. Typical θ

JA

Values

Copper Size (mm

2

)

θ

JA

(°C/W)

8-Lead LFCSP 8-Lead SOIC

25 1

100

500

1000

6400

165.1

125.8

68.1

56.4

42.1

1 Device soldered to minimum size pin traces.

Table 9. Typical Ψ

JB

Values

Package Ψ

JB

(°C/W)

8-Lead LFCSP

8-Lead SOIC

15.1

17.9

165

126.4

69.8

57.8

43.6

The junction temperature of the ADM7151 is calculated from the following equation:

T

J

= T

A

+ (P

D

× θ

JA

) (2) where:

T

A

is the ambient temperature.

P

D

is the power dissipation in the die, given by

P

D

= [(V

IN

V

OUT

) × I

LOAD

] + (V

IN

× I

GND

) where:

V

IN

and V

I

LOAD

I

GND

OUT

are thinput and output voltages, respectively.

is the load current.

is the groune d current.

(3)

Power dissipation due to ground current is quite small and can be ignored. Therefore, the junction temperature equation simplifies to the following:

T

J

= T

A

+ {[(V

IN

V

OUT

) × I

LOAD

] × θ

JA

} (4)

As shown in Equation 4, for a given ambient temperature, input to output voltage differential, and continuous load current, there exists a minimum copper size requirement for the PCB to ensure that the junction temperature does not rise above 150°C.

The heat dissipation from the package can be improved by increasing the amount of copper attached to the pins and exposed pad of the ADM7151 . Adding thermal planes under the package

also improves thermal performance. However, as listed in Table 8, a

point of diminishing returns is eventually reached, beyond which an increase in the copper area does not yield significant reduction in the junction to ambient thermal resistance.

Rev. A | Page 20 of 24

Data Sheet

Figure 61 to Figure 66 show junction temperature calculations for

different ambient temperatures, power dissipation, and areas of

PCB copper.

155

145

135

125

115

105

95

85

75

65

55

6400mm

2

45 500mm

2

25mm

2

35

T

J

MAX

25

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0

TOTAL POWER DISSIPATION (W)

Figure 61. Junction Temperature vs. Total Power Dissipation for the 8-Lead LFCSP, T

A

= 25°C

160

150

140

130

120

110

100

90

80

70

60

6400mm

2

500mm

2

25mm

2

T

J

MAX

50

0 0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

TOTAL POWER DISSIPATION (W)

Figure 62. Junction Temperature vs. Total Power Dissipation for the 8-Lead LFCSP, T

A

= 50°C

155

145

135

125

115

105

95

85

75

6400mm

2

500mm

2

25mm

2

T

J

MAX

65

0 0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8 0.9 1.0 1.1 1.2 1.3 1.4

1.5

TOTAL POWER DISSIPATION (W)

Figure 63. Junction Temperature vs. Total Power Dissipation for the 8-Lead LFCSP, T

A

= 85°C

Data Sheet

115

102

95

85

75

155

145

135

125

65

55

45

35

25

0

6400mm

2

500mm

2

25mm

2

T

J

MAX

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

TOTAL POWER DISSIPATION (W)

Figure 64. Junction Temperature vs. Total Power Dissipation for the 8-Lead SOIC, T

A

= 25°C

160

150

140

130

120

110

100

90

80

70

60

6400mm

2

500mm

2

25mm

2

T

J

MAX

50

0 0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

TOTAL POWER DISSIPATION (W)

Figure 65. Junction Temperature vs. Total Power Dissipation for the 8-Lead SOIC, T

A

= 50°C

155

145

135

125

115

105

95

85

75

6400mm

2

500mm

2

25mm

2

T

J

MAX

65

0 0.2

0.4

0.6

0.8

1.0

1.2

1.4

TOTAL POWER DISSIPATION (W)

1.6

1.8

2.0

Figure 66. Junction Temperature vs. Total Power Dissipation for the 8-Lead SOIC, T

A

= 85°C

Rev. A | Page 21 of 24

Thermal Characterization Parameter (Ψ

JB

)

When the board temperature is known, use the thermal characterization parameter, Ψ

JB

, to estimate the junction

temperature rise (see Figure 67 and Figure 68). Maximum

junction temperature (T

J

) is calculated from the board temperature (T

B

) and power dissipation (P

D

) using the following formula:

T

J

= T

B

+ (P

D

× Ψ

JB

) (5)

The typical value of Ψ

JB

is 15.1°C/W for the 8-lead LFCSP package and 17.9°C/W for the 8-lead SOIC package.

160

140

120

100

80

60

40

20

T

B

= 25°C

T

B

= 50°C

T

B

= 65°C

T

B

= 85°C

T

J

MAX

0

0 0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

7.0

7.5

8.0

8.5

9.0

TOTAL POWER DISSIPATION (W)

Figure 67. Junction Temperature vs. Total Power Dissipation for the 8-Lead LFCSP

160

140

120

100

80

ADM7151

60

40

20

T

B

= 25°C

T

B

= 50°C

T

B

= 65°C

T

B

= 85°C

T

J

MAX

0

0 0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

6.5

7.0

7.5

TOTAL POWER DISSIPATION (W)

Figure 68. Junction Temperature vs. Total Power Dissipation for the 8-Lead SOIC

ADM7151

PRINTED CIRCUIT BOARD LAYOUT

CONSIDERATIONS

Place the input capacitor as close as possible to the VIN and

GND pins. Place the output capacitor as close as possible to the

VOUT and GND pins. Place the bypass capacitors for V

REG

,

V

REF

, and V

BYP

close to the respective pins and GND. Use of an

0805, 0603, or 0402 size capacitor achieves the smallest possible footprint solution on boards where area is limited.

Data Sheet

Figure 69. Example 8-Lead LFCSP PCB Layout

Figure 70. Example 8-Lead SOIC PCB Layout

Rev. A | Page 22 of 24

Data Sheet

OUTLINE DIMENSIONS

3.10

3.00 SQ

2.90

2.44

2.34

2.24

5 8

0.50 BSC

PIN 1 INDEX

AREA

0.80

0.75

0.70

SEATING

PLANE

TOP VIEW

EXPOSED

PAD

1.70

1.60

1.50

0.50

0.40

0.30

4

0.05 MAX

0.02 NOM

COPLANARITY

0.08

0.203 REF

BOTTOM VIEW

1

0.20 MIN

PIN 1

INDICATOR

(R 0.15)

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

0.30

0.25

0.20

COMPLIANT TO JEDEC STANDARDS MO-229-WEED

Figure 71. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]

3 mm × 3 mm Body, Very Very Thin, Dual Lead

(CP-8-11)

Dimensions shown in millimeters

5.00

4.90

4.80

3.098

0.356

8

5

4.00

3.90

3.80

6.20

6.00

5.80

0.457

1 4

1.27 BSC

1.75

1.35

TOP VIEW

3.81 REF

1.65

1.25

SEATING

PLANE

0.51

0.31

BOTTOM VIEW

0.10 MAX

0.05 NOM

COPLANARITY

0.10

0.50

0.25

45°

1.04 REF

2.41

0.25

0.17

1.27

0.40

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

COMPLIANT TO JEDEC STANDARDS MS-012-A A

Figure 72. 8-Lead Standard Small Outline Package, with Exposed Pad [SOIC_N_EP]

Narrow Body

(RD-8-2)

Dimensions shown in millimeters

ADM7151

Rev. A | Page 23 of 24

ADM7151

ORDERING GUIDE

Model 1

ADM7151ACPZ-02-R2

ADM7151ACPZ-02-R7

ADM7151ARDZ-02

ADM7151ARDZ-02-R7

ADM7151ACPZ-04-R2

ADM7151ACPZ-04-R7

ADM7151ARDZ-04

ADM7151ARDZ-04-R7

ADM7151CP-02-EVALZ

1 Z = RoHS Compliant Part.

Temperature Range Output Voltage Range(V)

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

1.5 to 4.0

1.5 to 4.0

1.5 to 4.0

1.5 to 4.0

1.5 to 5.1

−40°C to +125°C

−40°C to +125°C

−40°C to +125°C

1.5 to 5.1

1.5 to 5.1

1.5 to 5.1

1.5 to 4.0

Data Sheet

Package Description Package Option Branding

8-Lead LFCSP_WD

8-Lead LFCSP_WD

8-Lead SOIC_N_EP

8-Lead SOIC_N_EP

8-Lead LFCSP_WD

CP-8-11

CP-8-11

RD-8-2

RD-8-2

CP-8-11

LNN

LNN

LNP

8-Lead LFCSP_WD

8-Lead SOIC_N_EP

8-Lead SOIC_N_EP

Evaluation Board

CP-8-11

RD-8-2

RD-8-2

LNP

©2013–2015 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.

D11480-0-4/15(A)

Rev. A | Page 24 of 24

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