PS9850 Datasheet(Ver0.93)
 PS9850 Datasheet(Ver0.93) 8-channel,192kHz,24-bits
Audio Processor for Full Digital Amplifier
Digital
2009-08-17
Copyright © 2009 Pulsus Technologies, Inc.
1
PS9850
Multi-channel Digital Audio Processor
Eight-channels, 192kHz, 24-bits
Digital Audio Processor for Full Digital Amplifier
Introduction_______________________
Features___________________________
The PS9850 is a highly integrated system-on-chip audio
solution for multi-channel AV systems such as upper 5.1
channels, 6.1 channels or 7.1 channels. This device is a
high performance PWM modulator and a high resolution
digital audio processor.
Audio Interface
ü 8-Channel serial audio interface.
ü Supports 16/18/20/24-bit input
ü Supports 13kHz ~ 192kHz input Fs.
ü Supports up to 192kHz Fs for 8 Channels.
ü Data formats
2
ü (I S, left-justified or right-justified)
ü Microphone serial audio interface.
ü Sony Philips Digital Interface (SPDIF)
This device uses AD modulation operating at a 384kHz
switching rate, supports AM interference rejection function,
and has PWM sequences for pop-less.
This device has an asynchronous sample rate converter
for a variety of input sample rates with an embedded jitter
correction function. For high performances and high resolutions, audio processors operate 30bit data paths and a
192kHz sample rate.
This processor consists of equalizers, volume controls, a
bass management and automatic gain limiting functions.
Equalizers are fully programmable that have 69 band biquad filters with either a static or graphic mode and have
usable preset graphic equalizer.
This device is operated with a single power source, as it
has regulators for its core. This device has a built-in PLL
without external loop filter. Therefore the external components are minimized.
Applications______________________
ü
ü
ü
ü
ü
DVD receiver
Hi-Fi AV Receiver
Set-top box
Car AV Systems
Digital audio workstations
Features__________________________
General
ü 3.3V single power supply
ü Embedded regulator for 1.2V Power
ü 64pin TQFP package
ü Built-in PLL without external loop filter
ü Internal clock generation with X-tal
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ü I C or SPI serial control slave interface
Audio Processor
ü 192kHz sampling rate of audio processing
ü 30x24 multipliers and 54-bit accumulator architecture
ü 8-Channel sample rate converter
ü Fully programmable 69-band equalizers
ü Preset Graphic Equalizers
ü (+12 to -12, 0.5dB/step)
ü Pop Noise Reduction when equalizer coefficient
Downloads
ü Bass management
ü Four subsonic filter and LPF for subwoofer channel
ü Digital de-emphasis filter
ü Pre/post full matrix channel mixing.
ü Pre/post mapping.
ü Main volume control
ü (+18dB to -70dB, 0.5dB/step)
ü Soft/trim volume control
ü (+12dB to -12dB, 0.5dB/step)
ü Four independent automatic gain limiter
ü Supports night mode
ü Clipping Free Processing
ü (30-bit data processing)
PCM to PWM modulator
ü Pop noise reduction
ü AM interference rejection
ü 2-Channel PWM headphone output
ü 8-Channel PWM speaker output
ü PWM on/off control per channel
ü AD modulation operation
ü 384kHz carrier frequency
Copyright ©1999-2009 Pulsus Technologies, Inc.
Version: 0.93
Reserves the right to make changes to the information contained in this document without notice
August 17, 2009
Contact PULSUS Technologies for recent information. CONFIDENTIAL
Page: 2 / 3
PS9850
Block Diagram___________________________________________________________
HP_RIGHT_P/M
Post-mapper
Volume control
Bass mixer
Post-mixer
Sync. generator
Input interface
Transmitter
Equalizer
Pre-mixer
Pre-mapper
Input
interface
Receiver
(I2S /
SPDIF)
MIC
interpolator
MIC_SDIN
MIC_LRCK
MIC_BCK
MIC_MCLK
HP_LEFT P/M
Sample Rate
Convertor
SBCK
SLRCK
SSDIN0
SSDIN1
SSDIN2
SSDIN3
Sync. generator
Level
cut
MBCK
MLRCK
MSDIN0
MSDIN1
MSDIN2
MSDIN3
Bass
managem
ent
PWM_CH2_P/M
PWM
Convert
or
PWM_CH3_P/M
PWM_CH4_P/M
PWM_CH5_P/M
PWM_CH6_P/M
MIC interface
PWM_CH7_P/M
POP
NR
SPDIF
EXT_MUTE
SPI_I2C
SO_SDA
SCK_SCL
SI_AD0
nCS_AD2
PWM_CH1_P/M
Internal
Clock
Host
Interface
(I2C, SPI)
Internal
Controls
PWM_CH8_P/M
Internal
Reset
Clock control
Crystal
Oscillator
Power Supply
PLL
Regulator
VDD_VOUT1/2
VDD_VIN1/2
VDD_A
VDD_IO
VDD_CORE
nRESET
XOUT
XIN
Copyright ©1999-2009 Pulsus Technologies, Inc.
Version: 0.93
Reserves the right to make changes to the information contained in this document without notice
August 17, 2009
Contact PULSUS Technologies for recent information. CONFIDENTIAL
Page: 3 / 3
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