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240pin DDR3 SDRAM Registered DIMM
DDR3 SDRAM Registered DIMM
Based on 4Gb M-die
HMT451R7MFR8C
HMT41GR7MFR8C
HMT41GR7MFR4C
HMT42GR7MFR4C
HMT84GR7MMR4C
*SK hynix reserves the right to change products or specifications without notice.
Rev. 1.0 /Aug. 2012 1
Revision History
Revision No.
0.1
1.0
History
Initial Release
Latest JEDEC Spec and Product Line-up Updated
Draft Date
Aug.2011
Aug.2012
Remark
Rev. 1.0 / Aug. 2012 2
Description
SK hynix Registered DDR3 SDRAM DIMMs (Registered Double Data Rate Synchronous DRAM Dual In-Line
Memory Modules) are low power, high-speed operation memory modules that use DDR3 SDRAM devices.
These Registered SDRAM DIMMs are intended for use as main memory when installed in systems such as servers and workstations.
Features
• Power Supply: VDD=1.5V (1.425V to 1.575V)
• VDDQ = 1.5V (1.425V to 1.575V)
• VDDSPD=3.0V to 3.6V
• Functionality and operations comply with the DDR3 SDRAM datasheet
• 8 internal banks
• Data transfer rates: PC3-14900, PC3-12800, PC3-10600, PC3-8500
• Bi-Directional Differential Data Strobe
• 8 bit pre-fetch
• Burst Length (BL) switch on-the-fly BL8 or BC4(Burst Chop)
• Supports ECC error correction and detection
• On-Die Termination (ODT)
• Temperature sensor with integrated SPD
• This product is in compliance with the RoHS directive.
Ordering Information
Part Number
HMT451R7MFR8C-G7/H9/PB
HMT41GR7MFR8C-G7/H9/PB
HMT41GR7MFR4C-G7/H9/PB
HMT42GR7MFR4C-G7/H9/PB
HMT84GR7MMR4C-G7/H9
Density Organization
4GB
8GB
8GB
16GB
32GB
512Mx72
1Gx72
1Gx72
2Gx72
4Gx72
Component Composition
512Mx8(H5TQ4G83MFR)*9
512Mx8(H5TQ4G83MFR)*18
1Gx4(H5TQ4G43MFR)*18
1Gx4(H5TQ4G43MFR)*36
DDP 2Gx4(H5TQ8G43MMR)*36
# of ranks
1
2
1
2
4
FDHS
X
X
X
O
O
* In order to uninstall FDHS, please contact sales administrator
Rev. 1.0 / Aug. 2012 3
Key Parameters
MT/s
DDR3-1066
DDR3-1333
DDR3-1600
Grade
-G7
-H9
-PB tCK
(ns)
1.875
1.5
1.25
CAS
Latency
(tCK)
7
9
11 tRCD
(ns) tRP
(ns)
13.125
13.125
13.5
(13.125)*
13.5
(13.125)*
13.75
(13.125)*
13.75
(13.125)* tRAS
(ns)
37.5
36
35 tRC
(ns)
50.625
49.5
(49.125)*
48.75
(48.125)*
CL-tRCD-tRP
7-7-7
9-9-9
11-11-11
* SK hynix DRAM devices support optional downbinning to CL9 and CL7. SPD setting is programmed to match.
Speed Grade
Grade
-G7
-H9
-PB
CL6
800
800
800
Address Table
CL7
1066
1066
1066
Frequency [MHz]
CL8
1066
1066
1066
CL9
1333
1333
CL10
1333
1333
CL11
1600
Remark
Refresh Method
Row Address
Column Address
Bank Address
Page Size
4GB(1Rx8)
8K/64ms
A0-A15
A0-A9
BA0-BA2
1KB
8GB(1Rx4)
8K/64ms
A0-A15
A0-A9,A11
BA0-BA2
1KB
8GB(2Rx8)
8K/64ms
A0-A15
A0-A9
BA0-BA2
1KB
16GB(2Rx4)
8K/64ms
A0-A15
A0-A9,A11
BA0-BA2
1KB
32GB(4Rx4)
8K/64ms
A0-A15
A0-A9,A11
BA0-BA2
1KB
Rev. 1.0 / Aug. 2012 4
Pin Descriptions
Pin Name
CK0
CK0
CK1
CK1
CKE[1:0]
RAS
CAS
WE
Description
Clock Input, positive line
Clock Input, negative line
Clock Input, positive line
Clock Input, negative line
Clock Enables
Row Address Strobe
Column Address Strobe
Write Enable
S[3:0]
A[9:0],A11,
A[15:13]
A10/AP
A12/BC
BA[2:0]
SCL
SDA
SA[2:0]
Par_In
Err_Out
Chip Selects
Address Inputs
Address Input/Autoprecharge
Address Input/Burst chop
SDRAM Bank Addresses
Serial Presence Detect (SPD)
Clock Input
SPD Data Input/Output
SPD Address Inputs
Parity bit for the Address and
Control bus
Parity error found on the
Address and Control bus
14
1
1
3
1
1
3
1
Num ber
1
1
1
1
2
1
1
1
4
Pin Name Description
ODT[1:0] On Die Termination Inputs
DQ[63:0] Data Input/Output
CB[7:0]
DQS[8:0]
Data check bits Input/Output
Data strobes
Data strobes, negative line DQS[8:0]
DM[8:0]/
DQS[17:9],
TDQS[17:9]
DQS[17:9],
TDQS[17:9]
Data Masks / Data strobes,
Termination data strobes
EVENT
TEST
Data strobes, negative line,
Termination data strobes
Reserved for optional hardware temperature sensing
Memory bus test tool (Not Connected and Not Usable on DIMMs)
RESET Register and SDRAM control pin
V
DD
V
SS
V
REFDQ
V
REFCA
V
TT
V
DDSPD
Power Supply
Ground
Reference Voltage for DQ
Reference Voltage for CA
Termination Voltage
SPD Power
1
Num ber
8
9
2
64
9
9
9
1
1
1
22
59
1
1
4
1
Rev. 1.0 / Aug. 2012 5
Input/Output Functional Descriptions
Symbol
CK0
CK0
CK1
CK1
CKE[1:0]
Type Polarity
IN
IN
IN
IN
Positive
Line
Negative
Line
Positive
Line
Negative
Line
Function
Positive line of the differential pair of system clock inputs that drives input to the on-
DIMM Clock Driver.
Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM Clock Driver.
Terminated but not used on RDIMMs.
Terminated but not used on RDIMMs.
IN
Active
High
CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers of the SDRAMs. Taking CKE LOW provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN
(row ACTIVE in any bank)
S[3:0]
ODT[1:0]
RAS, CAS, WE
V
REFDQ
V
REFCA
IN
Supply
Supply
BA[2:0]
A[15:13,
12/BC,11,
10/AP,[9:0]
DQ[63:0],
CB[7:0]
DM[8:0]
V
DD
, V
SS
V
TT
IN
IN
IN
IN
I/O
IN
Supply
Supply
Active
Low
Active
High
Active
Low
—
—
Enables the command decoders for the associated rank of SDRAM when low and disables decoders when high. When decoders are disabled, new commands are ignored and previous operations continue. Other combinations of these input signals perform unique functions, including disabling all outputs (except CKE and ODT) of the register(s) on the DIMM or accessing internal control words in the register device(s). For modules with two registers, S[3:2] operate similarly to S[1:0] for the second set of register outputs or register control words.
On-Die Termination control signals
When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM.
Reference voltage for DQ0-DQ63 and CB0-CB7.
Reference voltage for A0-A15, BA0-BA2, RAS, CAS, WE, S0, S1, CKE0, CKE1, Par_In,
ODT0 and ODT1.
Selects which SDRAM bank of eight is activated.
BA0 - BA2 define to which bank an Active, Read, Write or Precharge command is being applied. Bank address also determines mode register is to be accessed during an MRS cycle.
Provided the row address for Active commands and the column address and Auto Precharge bit for Read/Write commands to select one location out of the memory array in the respective bank. A10 is sampled during a Precharge command to determine whether the Precharge applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA. A12 is also utilized for BL
4/8 identification for ‘’BL on the fly’’ during CAS command. The address inputs also provide the op-code during Mode Register Set commands.
Data and Check Bit Input/Output pins —
Active
High
Masks write data when high, issued concurrently with input data.
Power and ground for the DDR SDRAM input buffers and core logic.
Termination Voltage for Address/Command/Control/Clock nets.
Rev. 1.0 / Aug. 2012 6
Symbol
DQS[17:0]
DQS[17:0]
TDQS[17:9]
TDQS[17:9]
SA[2:0]
SDA
SCL
EVENT
V
DDSPD
RESET
Par_In
Err_Out
TEST
Type Polarity
I/O
I/O
OUT
IN
I/O
IN
OUT
(open drain)
Supply
IN
Function
Positive
Edge
Negative
Edge
Positive line of the differential data strobe for input and output data.
Negative line of the differential data strobe for input and output data.
—
—
—
Active Low
TDQS/TDQS is applicable for X8 DRAMs only. When enabled via Mode Register A11=1 in
MR1,DRAM will enable the same termination resistance function on TDQS/TDQS that is applied to DQS/DQS. When disabled via mode register A11=0 in MR1, DM/TDQS will provide the data mask function and TDQS is not used. X4 DRAMs must disable the TDQS function via mode register A11=0 in MR1
These signals are tied at the system planar to either V
SS serial SPD EEPROM address range.
or V
DDSPD
to configure the
This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V
DDSPD
on the system planar to act as a pullup.
This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V
DDSPD
on the system planar to act as a pullup.
This signal indicates that a thermal event has been detected in the thermal sensing device.The system should guarantee the electrical level requirement is met for the
EVENT pin on TS/SPD part.
No pull-up resister is provided on DIMM.
Serial EEPROM positive power supply wired to a separate power pin at the connector which supports from 3.0 Volt to 3.6 Volt (nominal 3.3V) operation.
The RESET pin is connected to the RESET pin on the register and to the RESET pin on the DRAM.
Parity bit for the Address and Control bus. (“1 “: Odd, “0 “: Even) IN
OUT
(open drain)
Parity error detected on the Address and Control bus. A resistor may be connected from
Err_Out bus line to V
DD
on the system planar to act as a pull up.
Used by memory bus analysis tools (unused (NC) on memory DIMMs)
Rev. 1.0 / Aug. 2012 7
Pin Assignments
Pin #
3
4
1
2
5
15
19
20
21
22
16
17
18
23
24
29
30
31
25
26
27
28
6
11
12
13
9
10
7
8
14
Front Side
(left 1–60)
V REF DQ
V
SS
DQ0
DQ1
V SS
DQS1
DQS1
V SS
DQ10
DQ11
V
SS
DQ16
DQ17
V SS
DQS2
DQS2
V
SS
DQ18
DQ19
V SS
DQ24
DQ25
DQS0
DQS0
V
SS
DQ2
DQ3
V SS
DQ8
DQ9
V
SS
Pin #
121
122
123
124
125
126
134
135
136
137
138
139
140
141
142
127
128
129
130
131
132
133
143
144
145
146
147
148
149
150
151
Back Side
(right 121–180)
V SS
DQ4
V SS
DQ20
DQ21
V
SS
DM2,DQS11,
TDQS11
NC,DQS11,
TDQS11
V SS
DQ22
DQ23
V
SS
DQ28
DQ29
V SS
DQ5
V
SS
DM0,DQS9,
TDQS9
NC,DQS9,
TDQS9
V SS
DQ6
DQ7
V
SS
DQ12
DQ13
V SS
DM1,DQS10,
TDQS10
NC,DQS10,
TDQS10
V
SS
DQ14
DQ15
Pin #
65
66
74
75
79
80
81
82
76
77
78
71
72
73
67
68
69
70
61
62
63
64
83
84
89
90
91
85
86
87
88
Front Side
(left 61–120) Pin #
A2
V
DD
NC, CK1
NC, CK1
V DD
V DD
V REF CA
Par_In, NC
V DD
A10 / AP
BA0
V
DD
WE
CAS
V
DD
S1, NC
ODT1, NC
V
DD
S2, NC
V
SS
DQ32
DQ33
V SS
DQS4
DQS4
V
SS
DQ34
DQ35
V SS
DQ40
DQ41
NC = No Connect; RFU = Reserved Future Use
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
203
204
196
197
198
199
200
201
202
205
206
207
208
209
210
211
Back Side
(right 181–240)
A1
V
DD
V DD
CK0
CK0
V DD
EVENT, NC
A0
V DD
BA1
V DD
RAS
S0
V
DD
ODT0
A13
V DD
S3, NC
V SS
DQ36
DQ37
V
SS
DM4,DQS13,
TDQS13
NC,DQS13,
TDQS13
V SS
DQ38
DQ39
V
SS
DQ44
DQ45
V SS
Rev. 1.0 / Aug. 2012 8
49
50
55
56
57
58
51
52
53
54
59
60
Pin #
32
33
38
39
40
34
35
36
37
41
42
46
47
48
43
44
45
Front Side
(left 1–60)
V SS
DQS8
DQS8
V SS
CB2, NC
CB3, NC
V
SS
VTT, NC
KEY
VTT, NC
DQS3
DQS3
V
SS
DQ26
DQ27
V SS
CB0, NC
CB1, NC
V
SS
CKE0
V DD
BA2
Err_Out, NC
V
DD
A11
A7
V DD
A5
A4
V
DD
Pin #
152
162
163
164
165
166
167
168
153
154
155
156
157
158
159
160
161
169
170
Back Side
(right 121–180)
DM3,DQS12,
TDQS12
NC,DQS12,
TDQS12
V SS
DQ30
DQ31
V
SS
CB4, NC
CB5, NC
V SS
NC,DM8,DQS17,
TDQS17
NC,DQS17,
TDQS17
V
SS
CB6, NC
CB7, NC
V SS
NC(TEST)
RESET
KEY
CKE1, NC
V DD
Pin #
92
102
103
104
105
106
107
108
109
110
93
98
99
100
94
95
96
97
101
111
Front Side
(left 61–120) Pin #
V SS 212
175
176
177
178
171
172
173
174
179
180
A15
A14
V DD
A12 / BC
A9
V
DD
A8
A6
V DD
A3
116
117
118
119
120
112
113
114
115
DQS7
V
SS
DQ58
DQ59
V SS
SA0
SCL
SA2
V TT
NC = No Connect; RFU = Reserved Future Use
DQS6
DQS6
V SS
DQ50
DQ51
V
SS
DQ56
DQ57
V SS
DQS5
DQS5
V
SS
DQ42
DQ43
V SS
DQ48
DQ49
V
SS
DQS7
222
223
224
225
226
227
228
229
230
231
236
237
238
239
240
232
233
234
235
213
214
215
216
217
218
219
220
221
Back Side
(right 181–240)
DM5,DQS14,
TDQS14
NC,DQS14,
TDQS14
V SS
DQ46
DQ47
V
SS
DQ52
DQ53
V SS
DM6,DQS15,
TDQS15
NC,DQS15,
TDQS15
V
SS
DQ54
DQ55
V SS
DQ60
DQ61
V
SS
DM7,DQS16,
TDQS16
NC,DQS16,
TDQS16
V SS
DQ62
DQ63
V
SS
V DDSPD
SA1
SDA
V
SS
V TT
Rev. 1.0 / Aug. 2012 9
Registering Clock Driver Specifications
Capacitance Values
Symbol
C
C
I
IR
Parameter
Input capacitance, Data inputs
Input capacitance, CK, CK, FBIN, FBIN
(up to DDR3-1600)
Input capacitance, RESET, MIRROR,
QCSEN
Conditions Min Typ Max Unit
1.5
2.5
pF
1.5
2.5
pF
V
I
= V
DD
or GND; V
DD
= 1.5v
3 pF
Input & Output Timing Requirements
Symbol Parameter f t t clock f
TEST t t t
SU
H
PDM
DIS
EN
Conditions
DDR3-800
1066/1333
Min
Input clock frequency
Input clock frequency
Application frequency
Test frequency
300
70
Setup time
Hold time
Input valid before
CK/CK
Input to remain valid after CK/CK
100
175
Propagation delay, single-bit switching
CK/CK to output 0.65
Output disable time (1/2-Clock prelaunch)
Yn/Yn to output float
0.5 + tQSK1(min)
Output enable time (1/2-Clock prelaunch)
Output driving to
Yn/Yn
0.5 - tQSK1(max)
Max
670
300
-
-
1.0
-
-
0.65
0.5 + tQSK1(min)
0.5 - tQSK1(max)
DDR3-1600
Min
300
Max
810
70
50
125
300
-
-
1.0
-
-
Unit ps ps ps ps
Mhz
Mhz ns
Rev. 1.0 / Aug. 2012 10
On DIMM Thermal Sensor
The DDR3 SDRAM DIMM temperature is monitored by integrated thermal sensor. The integrated thermal sensor comply with JEDEC “TSE2002av, Serial Presence Detect with Temperature Sensor”.
Connection of Thermal Sensor
EVENT
SCL
SDA
SA0
SA1
SA2
EVENT
SCL
SPD with
Integrated
SDA TS
SA0
SA1
SA2
Temperature-to-Digital Conversion Performance
Parameter
Temperature Sensor Accuracy (Grade B)
Condition
Active Range,
75°C < T
A
< 95°C
Monitor Range,
40°C < T
A
< 125°C
-20°C < T
A
< 125°C
Resolution
-
-
Min
-
Typ Max
± 0.5
± 1.0
Unit
°C
± 1.0
0.25
± 2.0
± 2.0
± 3.0
°C
°C
°C
Rev. 1.0 / Aug. 2012 11
Functional Block Diagram
4GB, 512Mx72 Module(1Rank of x8)
DQS8
DQS8
DM8/DQS17
DQS17
CB[7:0]
DQS
DQS
TDQS
TDQS
DQ [7:0]
D8
DQS3
DQS3
DM3/DQS12
DQS12
DQ[31:24]
DQS
DQS
TDQS
TDQS
DQ [7:0]
D3
ZQ DQS4
DQS4
DM4/DQS13
DQS13
DQ[39:32]
DQS
DQS
TDQS
TDQS
DQ [7:0]
D4
ZQ DQS5
DQS5
DM5/DQS14
DQS14
DQ[47:40]
DQS
DQS
TDQS
TDQS
DQ [7:0]
D5
ZQ
ZQ
DQS2
DQS2
DM2/DQS11
DQS11
DQ[23:16]
DQS
DQS
TDQS
TDQS
DQ [7:0]
D2
ZQ DQS6
DQS6
DM6/DQS15
DQS15
DQ[55:48]
DQS
DQS
TDQS
TDQS
DQ [7:0]
D6
ZQ
DQS1
DQS1
DM1/DQS10
DQS10
DQ[15:8]
DQS
DQS
TDQS
TDQS
DQ [7:0]
D1
D0
ZQ DQS7
DQS7
DM7/DQS16
DQS16
DQ[63:56]
DQS
DQS
TDQS
TDQS
DQ [7:0]
D7
ZQ
V
DDSPD
V DD
V
TT
VREFCA
VREFDQ
V SS
DQS0
DQS0
DM0/DQS9
DQS9
DQ[7:0]
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ Vtt
Note:
1.DQ-to-I/O wiring may be changed within byte.
2.ZQ resistors are 240 Ω ± 1%.For all other resistor values refer to the appropriate wiring diagram.
Vtt
S0
S1
BA[N:0]
A[N:0]
1:
2
R
E
G
I
S
T
E
R
/
P
L
L
RS0A → CS0: SDRAMs D[3:0], D8
RS0B → CS0: SDRAMs D[7:4]
RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D8
RBA[N:0]A → BA[N:0]: SDRAMs D[7:4]
RA[N:0]A → A[N:0]: SDRAMs D[3:0], D8
RA[N:0]A → A[N:0]: SDRAMs D[7:4]
RAS
RRASA → RAS: SDRAMs D[3:0], D8
RRASA → RAS: SDRAMs D[7:4]
CAS
WE
CKE0
RCASA → CAS: SDRAMs D[3:0], D8
RCASA → CAS: SDRAMs D[7:4]
RWEA → WE: SDRAMs D[3:0], D8
RWEA → WE: SDRAMs D[7:4]
RCKE0A → CKE0: SDRAMs D[3:0], D8
RCKE0B → CKE0: SDRAMs D[7:4]
ODT0
CK0
120 Ω
±1%
RODT0A → ODT0: SDRAMs D[3:0], D8
RODT0B → ODT0: SDRAMs D[7:4]
PCK0A → CK: SDRAMs D[3:0], D8
PCK0B → CK: SDRAMs D[7:4]
CK0
CK0
PCK0A → CK: SDRAMs D[3:0], D8
PCK0B → CK: SDRAMs D[7:4]
CK0
120 Ω
±1%
PAR_IN OERR
RST
Err_Out
RESET
RST: SDRAMs D[8:0]
S[3:2], CKE1, ODT1, are NC (Unused register inputs ODT1 and CKE1 have a 330 Ω resistor to ground
VDDSPD
EVENT
SCL
SDA
VDDSPD
EVENT
SCL
SDA
SPD with
Integrated
TS
SA0
SA1
SA2
VSS
SA0
SA1
SA2
VSS
Plan to use SPD with Integrated TS of Class B and might be changed on customer’s requests. For more details of SPD and Thermal sensor, please contact local SK hynix sales representative
SPD
D0–D8
D0–D8
D0–D8
D0–D8
Rev. 1.0 / Aug. 2012 12
8GB, 1Gx72 Module(1Rank of x4) - page1
DQS8
DQS8
VSS
CB[3:0]
DQS
DQS
DM
DQ [3:0]
D8
ZQ
DQS17
DQS17
VSS
CB[7:4]
DQS
DQS
DM
DQ [3:0]
D17
ZQ
DQS4
DQS4
VSS
DQ[35:32]
DQS
DQS
DM
DQ [3:0]
D4
ZQ
DQS13
DQS13
VSS
DQ[39:36]
DQS
DQS
DM
DQ [3:0]
D13
ZQ
DQS3
DQS3
VSS
DQ[27:24]
DQS
DQS
DM
DQ [3:0]
D3
ZQ
DQS12
DQS12
VSS
DQ[31:28]
DQS
DQS
DM
DQ [3:0]
D12
ZQ
DQS5
DQS5
VSS
DQ[43:40]
DQS
DQS
DM
DQ [3:0]
D5
ZQ
DQS14
DQS14
VSS
DQ[47:44]
DQS
DQS
DM
DQ [3:0]
D14
ZQ
DQS2
DQS2
VSS
DQ[19:16]
DQS
DQS
DM
DQ [3:0]
D2
ZQ
DQS11
DQS11
VSS
DQ23:20]
DQS
DQS
DM
DQ [3:0]
D11
ZQ
DQS6
DQS6
VSS
DQ[51:48]
DQS
DQS
DM
DQ [3:0]
D6
ZQ
DQS15
DQS15
VSS
DQ[55;52]
DQS
DQS
DM
DQ [3:0]
D15
ZQ
DQS1
DQS1
VSS
DQ[11;8]
DQS
DQS
DM
DQ [3:0]
D1
ZQ
DQS10
DQS10
VSS
DQ[15:12]
DQS
DQS
DM
DQ [3:0]
D10
ZQ
DQS7
DQS7
VSS
DQ[59:56]
DQS
DQS
DM
DQ [3:0]
D7
ZQ
DQS16
DQS16
VSS
DQ[63:60]
DQS
DQS
DM
DQ [3:0]
D16
ZQ
DQS0
DQS0
VSS
DQ[3:0]
DQS
DQS
DM
DQ [3:0]
D0
ZQ
DQS9
DQS9
VSS
DQ[7:4]
DQS
DQS
DM
DQ [3:0]
D9
ZQ Vtt
Vtt
VDDSPD
EVENT
SCL
SDA
VDDSPD
EVENT
SCL
SDA
SPD with
Integrated
TS
SA0
SA1
SA2
VSS
SA0
SA1
SA2
VSS
Plan to use SPD with Integrated TS of Class B and might be changed on customer’s requests. For more details of SPD and Thermal sensor, please contact local SK hynix sales representative
Note:
1. DQ-to-I/O wiring may be changed within a nibble.
2. Unless otherwise noted, resistor values are 15%.
1
5
3. See the wiring diagrams for all resistors associated with the command, address and control bus.
4. ZQ resistors are 240%. For all other resistor values refer to the appropriate wiring diagram.
V
DDSPD
V DD
V
TT
VREFCA
VREFDQ
V SS
SPD
D0–D17
D0–D17
D0–D17
D0–D17
D0–D17
Rev. 1.0 / Aug. 2012 13
8GB, 1Gx72 Module(1Rank of x4) - page2
CAS
WE
CKE0
ODT0
S0
S1
BA[N:0]
A[N:0]
RAS
1:2
R
E
G
I
S
R
/
T
E
RS0A → CS0: SDRAMs D[3:0], D[12:8], D17
RS0B → CS0: SDRAMs D[7:4], D[16:13]
RS1A → CS1: SDRAMs D[12:9], D17
RS1B → CS1: SDRAMs D[16:13]
CK0
RRASA → RAS: SDRAMs D[3:0], D[12:8], D17
RRASB → RAS: SDRAMs D[7:4], D[16:13]
RCASA → CAS: SDRAMs D[3:0], D[12:8], D17
RCASB → CAS: SDRAMs D[7:4], D[16:13]
RWEA → WE: SDRAMs D[3:0], D[12:8], D17
RWEB → WE: SDRAMs D[7:4], D[16:13]
RCKE0A → CKE0: SDRAMs D[3:0], D[12:8], D17
RCKE0B → CKE0: SDRAMs D[7:4], D[16:13]
RODT0A → ODT0: SDRAMs D[3:0], D[12:8]. D17
RODT0B → ODT0: SDRAMs D[7:4], D[16:13]
PCK0A → CK: SDRAMs D[3:0], D8
PCK0B → CK: SDRAMs D[7:4]
CK0 PCK0A → CK: SDRAMs D[3:0], D8
PCK0B → CK: SDRAMs D[7:4]
PAR_IN
OERR Err_Out
RESET RST
RST: SDRAMs D[17:0]
Rev. 1.0 / Aug. 2012 14
8GB, 1Gx72 Module(2Rank of x8) - page1
DQS8
DQS8
DM8/DQS17
DQS17
CB[7:0]
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
D8
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
D17
DQS4
DQS4
DM4/DQS13
DQS13
DQ[39:32]
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
D4
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
D13
DQS3
DQS3
DM3/DQS12
DQS12
DQ[31:24]
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
D3
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
D12
DQS5
DQS5
DM5/DQS14
DQS14
DQ[47:40]
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
D5
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
D14
DQS2
DQS2
DM2/DQS11
DQS11
DQ[23:16]
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
D2
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
D11
DQS6
DQS6
DM6/DQS15
DQS15
DQ55:48]
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
D6
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
D15
DQS1
DQS1
DM1/DQS10
DQS10
DQ[15:8]
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
D1
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
D10
DQS7
DQS7
DM7/DQS16
DQS16
DQ[63:56]
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
D7
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
D16
DQS0
DQS0
DM0/DQS9
DQS9
DQ[7:0]
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
D0
DQS
DQS
TDQS
TDQS
DQ [7:0]
ZQ
D9
Vtt
Vtt
Note:
1. DQ-to-I/O wiring may be changed within a byte.
2. Unless otherwise noted, resistor values are 15 Ω ±5%.
3. ZQ resistors are 240 Ω ±1%. For all other resistor values refer to the appropriate wiring diagram.
4. See the wiring diagrams for all resistors associated with the command, address and control bus.
V
DDSPD
V DD
V
TT
VREFCA
VREFDQ
V SS
VDDSPD
EVENT
SCL
SDA
VDDSPD
EVENT
SCL
SDA
SPD with
Integrated
TS
SA0
SA1
SA2
VSS
SA0
SA1
SA2
VSS
Plan to use SPD with Integrated TS of Class B and might be changed on customer’s requests. For more details of SPD and Thermal sensor, please contact local SK hynix sales representative
Serial PD
D0–D17
D0–D17
D0–D17
D0–D17
D0–D17
Rev. 1.0 / Aug. 2012 15
8GB, 1Gx72(2Rank of x8) - page2
CAS
WE
CKE0
CKE1
S0
S1
S[3:2] NC
BA[N:0]
A[N:0]
RAS
ODT0
ODT1
CK0
CK0
120Ω
±5%
120 Ω
±5%
1:2
T
E
I
S
R
R
E
G
L
L
/
P
RS0A → CS0: SDRAMs D[3:0], D8
RS0B → CS0: SDRAMs D[7:4]
RS1A → CS1: SDRAMs D[12:9], D17
RS1B → CS1: SDRAMs D[16:13]
RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D[12:8], D17
RBA[N:0]B → BA[N:0]: SDRAMs D[7:4], D[16:13]
RRASA → RAS: SDRAMs D[3:0], D[12:8], D17
RRASB → RAS: SDRAMs D[7:4], D[16:13]
RCASA → CAS: SDRAMs D[3:0], D[12:8], D17
RCASB → CAS: SDRAMs D[7:4], D[16:13]
RWEA → WE: SDRAMs D[3:0], D[12:8], D17
RWEB → WE: SDRAMs D[7:4], D[16:13]
RCKE0A → CKE0: SDRAMs D[3:0], D8
RCKE0B → CKE0: SDRAMs D[7:4]
RCKE1A → CKE1: SDRAMs D[12:9], D17
RCKE1B → CKE1: SDRAMs D[16:13]
RODT0A → ODT0: SDRAMs D[3:0], D8
RODT0B → ODT0: SDRAMs D[7:4]
RODT1A → ODT1: SDRAMs D[12:9], D17
RODT1A → ODT1: SDRAMs D[16:13]
PCK0A → CK: SDRAMs D[3:0], D8
PCK0B → CK: SDRAMs D[7:4]
PCK1A → CK: SDRAMs D[12:9], D17
PCK1B → CK: SDRAMs D[16:13]
PCK0A → CK: SDRAMs D[3:0], D8
PCK0B → CK: SDRAMs D[7:4]
PCK1A → CK: SDRAMs D[12:9], D17
PCK1B → CK: SDRAMs D[16:13] CK1
CK1
PAR_IN
OERR Err_Out
RESET RST
RST: SDRAMs D[17:0]
* S[3:2], CK1 and CK1 are NC
Rev. 1.0 / Aug. 2012 16
16GB, 2Gx72 Module(2Rank of x4) - page1
DQS17
DQS17
VSS
CB[7:4]
DQS
DQS
DM
DQ [3:0]
D17
DQS
DQS
DM
DQ [3:0]
D35
DQS8
DQS8
VSS
CB[3:0]
DQS
DQS
DM
DQ [3:0]
D8
DQS12
DQS12
VSS
DQ[31:28]
DQS
DQS
DM
DQ [3:0]
D12
DQS11
DQS11
VSS
DQ[23:20]
DQS
DQS
DM
DQ [3:0]
D11
DQS
DQS
DM
DQ [3:0]
D30
DQS3
DQS3
VSS
DQ[27:24]
DQS
DQS
DM
DQ [3:0]
D3
DQS
DQS
DM
DQ [3:0]
D29
DQS2
DQS2
VSS
DQ[19:16]
DQS
DQS
DM
DQ [3:0]
D2
DQS10
DQS10
VSS
DQ[15:12]
DQS
DQS
DM
DQ [3:0]
D10
DQS0
DQS0
VSS
DQ[3:0]
DQS
DQS
DM
DQ [3:0]
D0
DQS
DQS
DM
DQ [3:0]
D28
DQS1
DQS1
VSS
DQ[11:8]
DQS
DQS
DM
DQ [3:0]
D1
DQS
DQS
DM
DQ [3:0]
D18
DQS9
DQS9
VSS
DQ[7:4]
DQS
DQS
DM
DQ [3:0]
D9
Vtt Vtt
DQS
DQS
DM
DQ [3:0]
D26
DQS
DQS
DM
DQ [3:0]
D21
DQS
DQS
DM
DQ [3:0]
D20
DQS
DQS
DM
DQ [3:0]
D19
DQS
DQS
DM
DQ [3:0]
D27
Rev. 1.0 / Aug. 2012 17
16GB, 2Gx72 Module(2Rank of x4) - page2
DQS14
DQS14
VSS
DQ[47:44]
DQS
DQS
DM
DQ [3:0]
D14
DQS4
DQS4
VSS
DQ[35:32]
DQS
DQS
DM
DQ [3:0]
D4
DQS16
DQS16
VSS
DQ[63:60]
DQS
DQS
DM
DQ [3:0]
D16
DQS7
DQS7
VSS
DQ[59:56]
DQS
DQS
DM
DQ [3:0]
D7
DQS
DQS
DM
DQ [3:0]
D32
DQS13
DQS13
VSS
DQ[39:36]
DQS
DQS
DM
DQ [3:0]
D13
DQS
DQS
DM
DQ [3:0]
D22
DQS5
DQS5
VSS
DQ[43:40]
DQS
DQS
DM
DQ [3:0]
D5
DQS
DQS
DM
DQ [3:0]
D34
DQS15
DQS15
VSS
DQ[55:52]
DQS
DQS
DM
DQ [3:0]
D15
DQS
DQS
DM
DQ [3:0]
D25
DQS6
DQS6
VSS
DQ[51:48]
DQS
DQS
DM
DQ [3:0]
D6
DQS
DQS
DM
DQ [3:0]
D31
DQS
DQS
DM
DQ [3:0]
D23
DQS
DQS
DM
DQ [3:0]
D33
DQS
DQS
DM
DQ [3:0]
D24
Vtt Vtt
V
DDSPD
V
DD
V
TT
VREFCA
VREFDQ
V SS
SPD
D0–D35
D0–D35
D0–D35
D0–D35
D0–D35
VDDSPD
EVENT
SCL
SDA
VDDSPD
EVENT
SCL
SDA
SPD with
Integrated
TS
SA0
SA1
SA2
VSS
SA0
SA1
SA2
VSS
Plan to use SPD with Integrated TS of Class B and might be changed on customer’s requests. For more details of SPD and Thermal sensor, please contact local SK hynix sales representative
Note:
1. DQ-to-I/O wiring may be changed within a nibble.
2. See wiring diagrams for all resistors values.
3. ZQ pins of each SDRAM are connected to individual RZQ resistors (240+/-1%) ohms.
Rev. 1.0 / Aug. 2012 18
16GB, 2Gx72 Module(2Rank of x4) - page3
CAS
WE
CKE0
CKE1
ODT0
ODT1
CK0
S0
S1
BA[N:0]
A[N:0]
RAS
1:2
T
E
I
S
R
R
E
G
L
L
/
P
RS0A → CS0: SDRAMs D[3:0], D[12:8], D17
RS0B → CS0: SDRAMs D[7:4], D[16:13]
RS1A → CS1: SDRAMs D[21:18], D[30:26], D35
RS1B → CS1: SDRAMs D[25:22], D[34:31]
RBA[N:0]A → BA[N:0]: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RBA[N:0]B → BA[N:0]: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
CK0
RRASA → RAS: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RRASB → RAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RCASA → CAS: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RCASB → CAS: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RWEA → WE: SDRAMs D[3:0], D[12:8], D[21:17], D[30:26], D35
RWEB → WE: SDRAMs D[7:4], D[16:13], D[25:22], D[34:31]
RCKE0A → CKE0: SDRAMs D[3:0], D[12:8], D17
RCKE0B → CKE0: SDRAMs D[7:4], D[16:13]
RCKE1A → CKE1: SDRAMs D[21:18], D[30:26], D35
RCKE1B → CKE1: SDRAMs D[25:22], D[34:31]
RODT0A → ODT0: SDRAMs D[3:0], D[12:8], D17
RODT0B → ODT0: SDRAMs D[7:4], D[16:13]
RODT1A → ODT1: SDRAMs D[21:18], D[30:26], D35
RODT1A → ODT1: SDRAMs D[25:22], D[34:31]
PCK0A → CK: SDRAMs D[3:0], D[12:8], D17
PCK0B → CK: SDRAMs D[7:4], D[16:13]
PCK1A → CK: SDRAMs D[21:18], D[30:26], D35
PCK1B → CK: SDRAMs D[25:22], D[34:31]
PCK0A → CK: SDRAMs D[3:0], D[12:8], D17
PCK0B → CK: SDRAMs D[7:4], D[16:13]
PCK1A → CK: SDRAMs D[21:18], D[30:26], D35
PCK1B → CK: SDRAMs D[25:22], D[34:31] CK1
CK1
PAR_IN
120 Ω
±5%
RESET RST
Err_Out
RST: SDRAMs D[35:0]
* S[3:2], CK1 and CK1 are NC
Rev. 1.0 / Aug. 2012 19
32GB, 4Gx72 Module(4Rank of x4) - page1
VSS
DQS8
DQS8
VSS
CB[3:0]
ZQ
DQS
DQS
DM
DQ [3:0]
D9
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D8
VSS
DQS3
DQS3
VSS
DQ[27:24]
ZQ
DQS
DQS
DM
DQ [3:0]
D7
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D6
VSS
DQS2
DQS2
VSS
DQ[19:16]
ZQ
DQS
DQS
DM
DQ [3:0]
D5
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D4
VSS
DQS1
DQS1
VSS
DQ[11:8]
ZQ
DQS
DQS
DM
DQ [3:0]
D3
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D2
VSS
DQS0
DQS0
VSS
DQ[3:0]
ZQ
DQS
DQS
DM
DQ [3:0]
D1
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D0
Vtt
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D45
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D44
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D47
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D46
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D49
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D48
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D51
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D50
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D53
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D52
Rev. 1.0 / Aug. 2012 20
32GB, 4Gx72 Module(4Rank of x4) - page2
VSS
DQS17
DQS17
VSS
CB[7:4]
ZQ
DQS
DQS
DM
DQ [3:0]
D27
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D26
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D63
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D62
VSS
DQS12
DQS12
VSS
DQ[31:28]
ZQ
DQS
DQS
DM
DQ [3:0]
D25
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D24
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D65
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D64
VSS
DQS11
DQS11
VSS
DQ[23:20]
ZQ
DQS
DQS
DM
DQ [3:0]
D23
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D22
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D67
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D66
VSS
DQS10
DQS10
VSS
DQ[11:8]
ZQ
DQS
DQS
DM
DQ [3:0]
D21
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D20
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D69
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D68
VSS
DQS9
DQS9
VSS
DQ[7:4]
ZQ
DQS
DQS
DM
DQ [3:0]
D19
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D18
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D71
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D70
Vtt
Rev. 1.0 / Aug. 2012 21
32GB, 4Gx72 Module(4Rank of x4) - page3
VSS
DQS4
DQS4
VSS
DQ[35:32]
ZQ
DQS
DQS
DM
DQ [3:0]
D11
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D10
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D13
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D42
VSS
DQS5
DQS5
VSS
DQ[43:40]
ZQ
DQS
DQS
DM
DQ [3:0]
D13
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D12
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D41
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D40
VSS
DQS6
DQS6
VSS
DQ[51:48]
ZQ
DQS
DQS
DM
DQ [3:0]
D15
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D14
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D39
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D38
VSS
DQS7
DQS7
VSS
DQ[59:56
ZQ
DQS
DQS
DM
DQ [3:0]
D17
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D16
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D37
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D36
Vtt
Rev. 1.0 / Aug. 2012 22
32GB, 4Gx72 Module(4Rank of x4) - page4
VSS
DQS13
DQS13
VSS
DQ[39:36]
ZQ
DQS
DQS
DM
DQ [3:0]
D29
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D28
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D61
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D60
VSS
DQS14
DQS14
VSS
DQ[47:44]
ZQ
DQS
DQS
DM
DQ [3:0]
D31
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D30
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D59
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D58
VSS
DQS15
DQS15
VSS
DQ[55:52]
ZQ
DQS
DQS
DM
DQ [3:0]
D33
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D32
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D57
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D56
VSS
DQS16
DQS16
VSS
DQ[63:60]
ZQ
DQS
DQS
DM
DQ [3:0]
D35
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D34
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D55
VSS ZQ
DQS
DQS
DM
DQ [3:0]
D54
Vtt
V
DDSPD
V DD
V
TT
VREFCA
VREFDQ
V SS
SPD
D0–D71
D0–D71
D0–D71
D0–D71
VDDSPD
EVENT
SCL
SDA
VDDSPD
EVENT
SCL
SDA
SPD with
Integrated
TS
SA0
SA1
SA2
VSS
SA0
SA1
SA2
VSS
Plan to use SPD with Integrated TS of Class B and might be changed on customer’s requests. For more details of SPD and Thermal sensor, please contact local Hynix sales representative
Note:
1. DQ-to-I/O wiring may be changed within a nibble.
2. Unless otherwise noted, resistor values are 15 Ohms ±5%.
3. See the wiring diagrams for all resistors associated with the command, address and control bus.
4. ZQ resistors are 240 Ohms ±1%. For all other resistor values refer to the appropriate wiring diagram.
Rev. 1.0 / Aug. 2012 23
32GB, 4Gx72 Module(4Rank of x4) - page5
S0
S1
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
CKE1
ODT0
CK0
CK0
120 Ω
±5%
1:2
T
E
I
S
R
R
E
G
L
L
/
P
A
ARS0A → CS1: SDRAMs D1,D3,D5,D7 D9,
D19, D21, D23, D25, D27
ARS0B → CS1: SDRAMs D11, D13, D15, D17,
D29, D31, D33, D35
ARS1A → CS0: SDRAMs D0, D2, D4, D6, D8,
D18, D20, D22, D24, D26
ARS1B → CS0: SDRAMs D10, D12, D14, D16,
D28, D30, D32, D34
ARRASA → RAS: SDRAMs D[9:0],D[27:18]
ARRASB → RAS: SDRAMs D[17:10],D[35:28]
ARCASA → CAS: SDRAMs D[9:0],D[27:18]
ARCASB → CAS: SDRAMs D[17:10],D[35:28]
ARWEA → WE: SDRAMs D[9:0],D[27:18]
ARWEB → WE: SDRAMs D[17:10],D[35:28]
ARCKE0A → CKE1: SDRAMs D1,D3,D5,D7,D9,
D19, D21, D23, D25, D27
ARCKE0B → CKE1: SDRAMs D11,D13,D15,D17,
D29, D31, D33, D35
ARCKE1A → CKE0: SDRAMs D0,D2,D4,D6,D8,
D18, D20, D22, D24, D26
ARCKE1B → CKE0: SDRAMs D10,D12,D14,D16,
D28, D30, D32, D34
ARODT0A → ODT1: SDRAMs D1,D3,D5,D7,D9,
D19, D21, D23, D25, D27
ARODT0B → ODT0: SDRAMs D11,D13,D15,D17,
D29, D31, D33, D35
APCK0A → CK: SDRAMs D[9:0]
APCK0B → CK: SDRAMs D[17:10]
APCK1A → CK: SDRAMs D[27:18]
APCK1B → CK: SDRAMs D[35:28]
APCK0A → CK: SDRAMs D[9:0]
APCK0B → CK: SDRAMs D[17:10]
APCK1A → CK: SDRAMs D[27:18]
APCK1B → CK: SDRAMs D[35:28]
S2
S3
BA[N:0]
A[N:0]
RAS
CAS
WE
CKE0
CKE1
ODT1
CK0
CK0
120 Ω
±5%
1:2
T
E
I
S
R
R
E
G
L
L
/
P
B
BRS2A → CS1: SDRAMs D45,D47,D49,D51,D53
D63,D65,D67,D69,D71
BRS2B → CS1: SDRAMs D37,D39,D41,D43,
D55,D57,D59,D61
BRS3A → CS0: SDRAMs D44.D46,D48,D50,D52,
D62,D64,D66,D68,D70
BRS3B → CS0: SDRAMs D36,D38,D40,D42,
D54,D56,D58,D60
BRRASA → RAS: SDRAMs D[53:44],D[71:62]
BRRASB → RAS: SDRAMs D[43:36],D[61:54]
BRCASA → CAS: SDRAMs D[53:44],D[71:62]
BRCASB → CAS: SDRAMs D[43:36],D[61:54]
BRWEA → WE: SDRAMs D[53:44],D[71:62]
BRWEB → WE: SDRAMs D[43:36],D[61:54]
BRCKE0A → CKE1: SDRAMs D45,D47,D49,D51,D53,
D63,D65,D67,D69,D71
BRCKE0B → CKE1: SDRAMs D37,D39,D41,D43,
D55,D57,D59,D61
BRCKE1A → CKE0: SDRAMs D44.D46,D48,D50,D52,
D62,D64,D66,D68,D70
BRCKE1B → CKE0: SDRAMs D36,D38,D40,D42,
D54,D56,D58,D60
BRODT1A → ODT1: SDRAMs D45,D47,D49,D51,D53
D63,D65,D67,D69,D71
BRODT1B → ODT0: SDRAMs D37,D39,D41,D43
D55,D57,D59,D61
BPCK0A → CK: SDRAMs D[53:44]
BPCK0B → CK: SDRAMs D[43:36]
BPCK1A → CK: SDRAMs D[71:62]
BPCK1B → CK: SDRAMs D[61:54]
BPCK0A → CK: SDRAMs D[53:44]
BPCK0B → CK: SDRAMs D[43:36]
BPCK1A → CK: SDRAMs D[71:62]
BPCK1B → CK: SDRAMs D[61:54]
PAR_IN
RESET RST
Err_Out
RST: SDRAMs D[35:0]
PAR_IN
RESET RST
Err_Out
CK1
CK1
120 Ω
±5%
1. CK0 and CK0 are differentially terminated with a single 120 Ohms ±5% resistor.
2. CK1 and CK1 are differentially terminated with a single 120 Ohms ±5% resistor, but is not used.
3. Unused register inputs ODT1 for Register A and ODT0 for Register B are tied to ground.
4. The module drawing on this page is not drawn to scale.
Rev. 1.0 / Aug. 2012 24
Absolute Maximum Ratings
Absolute Maximum DC Ratings
Absolute Maximum DC Ratings
Symbol
VDD
Parameter
Voltage on VDD pin relative to Vss
VDDQ Voltage on VDDQ pin relative to Vss
V
IN
, V
OUT
Voltage on any pin relative to Vss
T
STG
Notes:
Storage Temperature
Rating
- 0.4 V ~ 1.80 V
- 0.4 V ~ 1.80 V
- 0.4 V ~ 1.80 V
-55 to +100
Units
V
V
V o C
Notes
1
1, 2
1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
3. VDD and VDDQ must be within 300mV of each other at all times; and VREF must not be greater than
0.6XVDDQ,When VDD and VDDQ are less than 500mV; VREF may be equal to or less than 300mV.
DRAM Component Operating Temperature Range
Temperature Range
Symbol
T
OPER
Parameter
Normal Operating Temperature Range
Extended Temperature Range
Notes:
Rating
0 to 85
85 to 95
Units o o
C 1,2
C
Notes
1,3
1. Operating Temperature TOPER is the case surface temperature on the center / top side of the DRAM. For measurement conditions, please refer to the JEDEC document JESD51-2.
2. The Normal Temperature Range specifies the temperatures where all DRAM specifications will be supported. During operation, the DRAM case temperature must be maintained between 0 - 85 o C under all operating conditions.
3. Some applications require operation of the DRAM in the Extended Temperature Range between 85 o
C and 95 o
C case temperature. Full specifications are guaranteed in this range, but the following additional conditions apply: a. Refresh commands must be doubled in frequency, therefore reducing the Refresh interval tREFI to 3.9 µs. It is also possible to specify a component with 1X refresh (tREFI to 7.8µs) in the Extended Temperature Range.
Please refer to the DIMM SPD for option availability b. If Self-Refresh operation is required in the Extended Temperature Range, then it is mandatory to either use the Manual Self-Refresh mode with Extended Temperature Range capability (MR2 A6 = 0b and MR2 A7 = 1b) or enable the optional Auto Self-Refresh mode (MR2 A6 = 1b and MR2 A7 = 0b). DDR3 SDRAMs support Auto
Self-Refresh and in Extended Temperature Range and please refer to component datasheet and/or the DIMM
SPD for tREFI requirements in the Extended Temperature Range
Rev. 1.0 / Aug. 2012 25
AC & DC Operating Conditions
Recommended DC Operating Conditions
Recommended DC Operating Conditions
Symbol
VDD Supply Voltage
Parameter
Min.
1.425
Rating
Typ.
1.500
Max.
1.575
VDDQ
Supply Voltage for Output
1.425
1.500
1.575
Notes:
1. Under all conditions, VDDQ must be less than or equal to VDD.
2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
Units Notes
V
V
1,2
1,2
Rev. 1.0 / Aug. 2012 26
AC & DC Input Measurement Levels
AC and DC Logic Input Levels for Single-Ended Signals
AC and DC Input Levels for Single-Ended Command and Address Signals
Single Ended AC and DC Input Levels for Command and ADDress
DDR3-800/1066/1333/1600
Symbol Parameter Unit Notes
Min Max
VIH.CA(DC100) DC input logic high
VIL.CA(DC100) DC input logic low
VIH.CA(AC175) AC input logic high
VIL.CA(AC175) AC input logic low
VIH.CA(AC150) AC Input logic high
VIL.CA(AC150) AC input logic low
VIH.CA(AC135) AC input logic high
VIL.CA(AC135) AC input logic low
VIH.CA(AC125) AC Input logic high
Vref + 0.100
VSS
Vref + 0.175
Note2
Vref + 0.150
Note2
-
-
-
VDD
Vref - 0.100
Note2
Vref - 0.175
Note2
Vref - 0.150
-
-
-
V
V
V
V
V
V
V
V
V
VIL.CA(AC125)
V
RefCA(DC
)
AC input logic low
Reference Voltage for
ADD, CMD inputs
-
0.49 * VDD
-
0.51 * VDD
V
V
1, 2, 8
3, 4
Notes:
1. For input only pins except RESET, Vref = VrefCA (DC).
2. Refer to "Overshoot and Undershoot Specifications" on page 40.
3. The ac peak noise on V
Ref
may not allow V
Ref
to deviate from V reference: approx. +/- 15 mV).
RefCA(DC)
by more than +/-1% VDD (for
4. For reference: approx. VDD/2 +/- 15 mV.
5. VIH(dc) is used as a simplified symbol for VIH.CA(DC100)
6. VIL(dc) is used as a simplified symbol for VIL.CA(DC100)
7. VIH(ac) is used as simplified symbol for VIH.CA(AC175), VIH.CA(AC150), VIH.CA(AC135), and
VIH.CA(AC125); VIH.CA(AC175) value is used when Vref + 0.175V is referenced, VIH.CA(AC150) value is used when Vref + 0.150V is referenced, VIH.CA(AC135) value is used when Vref + 0.135V is referenced, and VIH.CA(AC125) value is used when Vref + 0.125V is referenced.
8. VIL(ac) is used as simplified symbol for VIL.CA(AC175), VIL.CA(AC150), VIL.CA(AC135), and
VIL.CA(AC125); VIL.CA(AC175) value is used when Vref - 0.175V is referenced, VIL.CA(AC150) value is used when Vref - 0.150V is referenced, VIL.CA(AC135) value is used when Vref - 0.135V is referenced, and
VIL.CA(AC125) value is used when Vref - 0.125V is referenced.
1, 5
1, 6
1, 2, 7
1, 2, 8
1, 2, 7
1, 2, 8
1, 2, 7
1, 2, 8
1, 2, 7
Rev. 1.0 / Aug. 2012 27
AC and DC Input Levels for Single-Ended Signals
DDR3 SDRAM will support two Vih/Vil AC levels for DDR3-800 and DDR3-1066 as specified in the table below. DDR3 SDRAM will also support corresponding tDS values (Table 43 and Table 51 in “ DDR3 Device
Operation”) as well as derating tables in Table 46 of “DDR3 Device Operation” depending on Vih/Vil AC levels.
Single Ended AC and DC Input Levels for DQ and DM
DDR3-800/1066 DDR3-1333/1600
Symbol Parameter Unit Notes
Min Max Min Max
VIH.DQ(DC100) DC input logic high Vref + 0.100
VIL.DQ(DC100) DC input logic low VSS
VIH.DQ(AC175) AC input logic high Vref + 0.175
VIL.DQ(AC175) AC input logic low Note2
VIH.DQ(AC150) AC Input logic high Vref + 0.150
VIL.DQ(AC150) AC input logic low
VIH.CA(AC135) AC input logic high
VIL.CA(AC135) AC input logic low
Note2
-
-
VDD
Vref - 0.100
Note2
Vref - 0.175
Note2
Vref - 0.150
-
-
Vref + 0.100
VSS
-
-
Vref + 0.150
Note2
-
-
VDD
Vref - 0.100
-
-
Note2
Vref - 0.150
-
-
V 1, 5
V 1, 6
V 1, 2, 7
V 1, 2, 8
V 1, 2, 7
V 1, 2, 8 mV 1, 2, 7 mV 1, 2, 8
V
RefDQ(DC
)
Reference Voltage for DQ, DM inputs
0.49 * VDD 0.51 * VDD 0.49 * VDD 0.51 * VDD V 3, 4
Notes:
1. Vref = VrefDQ (DC).
2. Refer to "Overshoot and Undershoot Specifications" on page 40.
3. The ac peak noise on V
Ref
may not allow V
Ref reference: approx. +/- 15 mV).
to deviate from V
RefDQ(DC)
by more than +/-1% VDD (for
4. For reference: approx. VDD/2 +/- 15 mV.
5. VIH(dc) is used as a simplified symbol for VIH.DQ(DC100)
6. VIL(dc) is used as a simplified symbol for VIL.DQ(DC100)
7. VIH(ac) is used as simplified symbol for VIH.DQ(AC175), VIH.DQ(AC150), and VIH.DQ(AC135);
VIH.DQ(AC175) value is used when Vref + 0.175V is referenced, VIH.DQ(AC150) value is used when Vref
+ 0.150V is referenced, and VIH.DQ(AC135) value is used when Vref + 0.135V is referenced.
8. VIL(ac) is used as simplified symbol for VIL.DQ(AC175), VIL.DQ(AC150), and VIL.DQ(AC135);
VIL.DQ(AC175) value is used when Vref - 0.175V is referenced, VIL.DQ(AC150) value is used when Vref -
0.150V is referenced, and VIL.DQ(AC135) value is used when Vref - 0.135V is referenced.
Rev. 1.0 / Aug. 2012 28
Vref Tolerances
The dc-tolerance limits and ac-noise limits for the reference voltages
VRefCA
and V
RefDQ
are illustrated in figure below. It shows a valid reference voltage V
V
RefDQ
likewise).
Ref
(t) as a function of time. (V
Ref
stands for V
RefCA
and
V
Ref
(DC) is the linear average of V
Ref
(t) over a very long period of time (e.g. 1 sec). This average has to meet the min/max requirements in the table "Differential Input Slew Rate Definition" on page 35. Furthermore V
Ref
(t) may temporarily deviate from V
Ref (DC)
by no more than +/- 1% VDD.
voltage
VDD
V
Ref(DC)
V
Ref
ac-noise
V
Ref
(t)
V
Ref(DC)max
VDD/2
V
Ref(DC)min
VSS time
Illustration of V
Ref(DC)
tolerance and V
Ref
ac-noise limits
The voltage levels for setup and hold time measurements V
IH(AC) dent on V
Ref
.
, V
IH(DC)
, V
IL(AC)
, and V
IL(DC) are depen-
“V
Ref
” shall be understood as V
Ref(DC)
, as defined in figure above.
This clarifies that dc-variations of V
Ref
affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. System timing and voltage budgets need to account for V
Ref(DC)
deviations from the optimum position within the data-eye of the input signals.
This also clarifies that the DRAM setup/hold specification and derating values need to include time and voltage associated with V
Ref ac-noise. Timing and voltage effects due to ac-noise on V
Ref fied limit (+/- 1% of VDD) are included in DRAM timings and their associated deratings.
up to the speci-
Rev. 1.0 / Aug. 2012 29
AC and DC Logic Input Levels for Differential Signals
Differential signal definition t
DVAC
V
IL.DIFF.AC.MIN
V
IL.DIFF.MIN
0 half cycle
V
IL.DIFF.MAX
V
IL.DIFF.AC.MAX
t
DVAC time
Definition of differential ac-swing and “time above ac-level” t
DVAC
Rev. 1.0 / Aug. 2012 30
Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)
Differential AC and DC Input Levels
Symbol
VIHdiff
VILdiff
VIHdiff (ac)
VILdiff (ac)
Notes:
Parameter
Differential input high
Differential input logic low
Differential input high ac
Differential input low ac
DDR3-800, 1066, 1333, 1600
Min
+ 0.180
Note 3
2 x (VIH (ac) - Vref)
Note 3
Max
Note 3
- 0.180
Note 3
2 x (VIL (ac) - Vref)
Unit Notes
V
V
V
V
1. Used to define a differential signal slew-rate.
2. For CK - CK use VIH/VIL (ac) of AADD/CMD and VREFCA; for DQS - DQS, DQSL, DQSL, DQSU, DQSU use VIH/VIL
(ac) of DQs and VREFDQ; if a reduced ac-high or ac-low levels is used for a signal group, then the reduced level applies also here.
3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita-
tions for overshoot and undershoot. Refer to "Overshoot and Undershoot Specifications" on page 40.
1
1
2
2
Allowed time before ringback (tDVAC) for CK - CK and DQS - DQS
DDR3-800/1066/1333/1600
Slew Rate
[V/ns] tDVAC [ps]
@ VIH/Ldiff (ac)
= 350mV tDVAC [ps]
@ VIH/Ldiff (ac)
= 300mV tDVAC [ps]
@ VIH/Ldiff (ac)
= 270mV
(DQS-DQS)only
(Optional)
> 4.0
4.0
3.0
2.0
1.8
1.6
1.4
1.2
1.0
min
75
57
50
38
34
29
22 note note max
-
-
-
-
-
-
-
-
min
175
170
167
119
102
81
54
19 note max
-
-
-
-
-
-
-
min
214
214
191
146
131
113
88
56
11 max
-
-
-
-
-
-
-
-
< 1.0
note note note note : Rising input differential signal shall become equal to or greater than VIHdiff(ac) level and Falling input differential signal shall become equal to or less than VIL(ac) level.
Rev. 1.0 / Aug. 2012 31
Single-ended requirements for differential signals
Each individual component of a differential signal (CK, DQS, DQSL, DQSU, CK, DQS, DQSL, of DQSU) has also to comply with certain requirements for single-ended signals.
CK and CK have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH
(ac) / VIL (ac)) for ADD/CMD signals) in every half-cycle.
DQS, DQSL, DQSU, DQS, DQSL have to reach VSEHmin / VSELmax (approximately the ac-levels (VIH (ac)
/ VIL (ac)) for DQ signals) in every half-cycle preceding and following a valid transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g., if
VIH.CA(AC150)/VIL.CA(AC150) is used for ADD/CMD signals, then these ac-levels apply also for the singleended signals CK and CK.
VDD or VDDQ
VSEHmin
VSEH
VDD/2 or VDDQ/2
CK or DQS
VSELmax
VSEL
VSS or VSSQ time
Single-ended requirements for differential signals.
Note that, while ADD/CMD and DQ signal requirements are with respect to Vref, the single-ended components of differential signals have a requirement with respect to VDD / 2; this is nominally the same. the transition of single-ended signals through the ac-levels is used to measure setup time. For single-ended components of differential signals the requirement to reach VSELmax, VSEHmin has no bearing on timing, but adds a restriction on the common mode characteristics of these signals.
Rev. 1.0 / Aug. 2012 32
Single-ended levels for CK, DQS, DQSL, DQSU, CK, DQS, DQSL or DQSU
Symbol
VSEH
VSEL
Parameter
Single-ended high level for strobes
Single-ended high level for Ck, CK
Single-ended low level for strobes
Single-ended low level for CK, CK
DDR3-800, 1066, 1333, 1600
Min
(VDD / 2) + 0.175
(VDD /2) + 0.175
Note 3
Note 3
Max
Note 3
Note 3
(VDD / 2) = 0.175
(VDD / 2) = 0.175
Unit Notes
V
V
V
V
Notes:
1. For CK, CK use VIH/VIL (ac) of ADD/CMD; for strobes (DQS, DQS, DQSL, DQSL, DQSU, DQSU) use VIH/VIL (ac) of DQs.
2. VIH (ac)/VIL (ac) for DQs is based on VREFDQ; VIH (ac)/VIL (ac) for ADD/CMD is based on VREFCA; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here.
3. These values are not defined; however, the single-ended signals Ck, CK, DQS, DQS, DQSL, DQSL, DQSU, DQSU need to be within the respective limits (VIH (dc) max, VIL (dc) min) for single-ended signals as well as the limita-
tions for overshoot and undershoot. Refer to "Overshoot and Undershoot Specifications" on page 40.
1,2
1,2
1,2
1,2
Rev. 1.0 / Aug. 2012 33
Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each cross point voltage of differential input signals (CK, CK and DQS, DQS) must meet the requirements in table below. The differential input cross point voltage VIX is measured from the actual cross point of true and complement signals to the midlevel between of VDD and VSS
Vix Definition
Cross point voltage for differential input signals (CK, DQS)
DDR3-800, 1066, 1333, 1600
Symbol Parameter Unit Notes
Min Max
Differential Input Cross Point Voltage relative to VDD/2 for CK, CK
-150 150 mV 2
V
IX
(CK)
-175 175 mV 1
V
IX
(DQS)
Differential Input Cross Point Voltage relative to VDD/2 for DQS, DQS
-150 150 mV 2
Notes:
1. Extended range for V
IX
is only allowed for clock and if single-ended clock input signals CK and CK are monotonic with a single-ended swing VSEL / VSEH of at least VDD/2 +/-250 mV, and when the differential slew rate of CK - CK is larger than 3 V/ns.
2. The relation between Vix Min/Max and VSEL/VSEH should satisfy following.
(VDD/2) + Vix (Min) - VSEL 25mV
VSEH - ((VDD/2) + Vix (Max)) 25mV
Rev. 1.0 / Aug. 2012 34
Slew Rate Definitions for Single-Ended Input Signals
See 7.5 “Address / Command Setup, Hold and Derating” on “DDR3 Device Operation” for single-ended slew rate definitions for address and command signals.
See 7.6 “Data Setup, Hold and Slew Rate Derating” on “DDR3 Device Operation” for single-ended slew rate definition for data signals.
Slew Rate Definitions for Differential Input Signals
Input slew rate for differential signals (CK, CK and DQS, DQS) are defined and measured as shown in table and figure below.
Differential Input Slew Rate Definition
Measured
Description Defined by
Min Max
Differential input slew rate for rising edge
(CK-CK and DQS-DQS)
V
ILdiffmax
V
IHdiffmin
[V
IHdiffmin
-V
ILdiffmax
] / DeltaTRdiff
Differential input slew rate for falling edge
(CK-CK and DQS-DQS)
V
IHdiffmin
V
ILdiffmax
[V
IHdiffmin
-V
ILdiffmax
Notes:
The differential signal (i.e. CK-CK and DQS-DQS) must be linear between these thresholds.
] / DeltaTFdiff
Delta
TRdiff
V
IHdiffmin
0
V
ILdiffmax
Delta
TFdiff
Differential Input Slew Rate Definition for DQS, DQS and CK, CK
Rev. 1.0 / Aug. 2012 35
AC & DC Output Measurement Levels
Single Ended AC and DC Output Levels
Table below shows the output levels used for measurements of single ended signals.
Single-ended AC and DC Output Levels
Symbol
V
OH(DC)
V
OM(DC)
V
OL(DC)
V
OH(AC)
V
OL(AC)
Notes:
Parameter
DC output high measurement level (for IV curve linearity)
DC output mid measurement level (for IV curve linearity)
DC output low measurement level (for IV curve linearity)
AC output high measurement level (for output SR)
AC output low measurement level (for output SR)
DDR3-800, 1066,
1333, 1600
0.8 x V
DDQ
0.5 x V
DDQ
0.2 x V
DDQ
V
TT
+ 0.1 x V
DDQ
V
TT
- 0.1 x V
DDQ
Unit
V
V
V
V
V
Notes
1
1
1. The swing of ±0.1 x V
DDQ
is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 Ω and an effective test load of 25 Ω to V
TT
= V
DDQ
/ 2.
Differential AC and DC Output Levels
Table below shows the output levels used for measurements of single ended signals.
Differential AC and DC Output Levels
DDR3-800, 1066,
Symbol Parameter
AC differential output high measurement level (for output SR)
AC differential output low measurement level (for output SR)
Unit
V
V
Notes
V
OHdiff (AC)
V
OLdiff (AC)
Notes:
1333, 1600
+ 0.2 x V
DDQ
- 0.2 x V
DDQ
1. The swing of ±0.2 x V
DDQ
is based on approximately 50% of the static differential output high or low swing with a driver impedance of 40 Ω and an effective test load of 25 Ω to V
TT differential outputs.
= V
DDQ
/2 at each of the
1
1
Rev. 1.0 / Aug. 2012 36
Single Ended Output Slew Rate
When the Reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between V
OL(AC)
and V
OH(AC)
for single ended signals are shown in table and figure below.
Single-ended Output slew Rate Definition
Measured
Description Defined by
From To
Single-ended output slew rate for rising edge V
OL(AC)
V
OH(AC)
[V
OH(AC)
-V
OL(AC)
] / DeltaTRse
Single-ended output slew rate for falling edge V
OH(AC)
V
OL(AC)
[V
OH(AC)
-V
OL(AC)
] / DeltaTFse
Notes:
1. Output slew rate is verified by design and characterisation, and may not be subject to production test.
Delta TRse
V
OH(AC)
V
∏
V
OL(AC)
Delta TFse
Single Ended Output Slew Rate Definition
Single Ended Output slew Rate Definition
Output Slew Rate (single-ended)
DDR3-800 DDR3-1066 DDR3-1333 DDR3-1600
Units
Parameter Symbol Min Max Min Max Min Max Min Max
Single-ended Output Slew Rate SRQse 2.5
5 2.5
5 2.5
5 2.5
5 V/ns
Description: SR; Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output) se: Single-ended Signals
For Ron = RZQ/7 setting
Note 1): In two cases, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.
Case 1 is a defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the same byte lane are static (i.e. they stay at either high or low).
Case 2 is a defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining DQ signals in the same byte lane switching into the opposite direction (i.e. from low to high of high to low respectively). For the remaining DQ signal switching in to the opposite direction, the regular maximum limite of 5 V/ns applies.
Rev. 1.0 / Aug. 2012 37
Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between VOLdiff (AC) and VOHdiff (AC) for differential signals as shown in table and figure below.
Differential Output Slew Rate Definition
Measured
Description Defined by
From To
Differential output slew rate for rising edge V
OLdiff (AC)
V
OHdiff (AC)
[V
OHdiff (AC)
-V
OLdiff (AC)
] / DeltaTRdiff
Differential output slew rate for falling edge
Notes:
V
OHdiff (AC)
V
OLdiff (AC)
[V
OHdiff (AC)
-V
OLdiff (AC)
] / DeltaTFdiff
1. Output slew rate is verified by design and characterization, and may not be subject to production test.
Delta
TRdiff vOHdiff(AC)
O vOLdiff(AC)
Delta
TFdiff
Differential Output Slew Rate Definition
Differential Output slew Rate Definition
Differential Output Slew Rate
Parameter
DDR3-800
Symbol Min Max
DDR3-1066
Min Max
Differential Output Slew Rate SRQdiff
Description: SR; Slew Rate
5 10 5 10
Q: Query Output (like in DQ, which stands for Data-in, Query-Output) se: Single-ended Signals
For Ron = RZQ/7 setting
DDR3-1333
Min
5
Max
10
DDR3-1600
Min
5
Max
10
Units
V/ns
Rev. 1.0 / Aug. 2012 38
Reference Load for AC Timing and Output Slew Rate
Figure below represents the effective reference load of 25 ohms used in defining the relevant AC timing parameters of the device as well as output slew rate measurements.
It is not intended as a precise representation of any particular system environment or a depiction of the actual load presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or more coaxial transmission lines terminated at the tester electronics.
VDDQ
CK, CK
DUT
DQ
DQS
DQS
25 Ohm
VTT = VDDQ/2
Reference Load for AC Timing and Output Slew Rate
Rev. 1.0 / Aug. 2012 39
Overshoot and Undershoot Specifications
Address and Control Overshoot and Undershoot Specifications
AC Overshoot/Undershoot Specification for Address and Control Pins
DDR3DDR3-
Parameter
800 1066
Maximum peak amplitude allowed for overshoot area. (See Figure below) 0.4
Maximum peak amplitude allowed for undershoot area. (See Figure below) 0.4
Maximum overshoot area above VDD (See Figure below) 0.67
0.4
0.4
0.5
Maximum undershoot area below VSS (See Figure below) 0.67
(A0-A15, BA0-BA3, CS, RAS, CAS, WE, CKE, ODT)
See figure below for each parameter definition
0.5
DDR3-
1333
0.4
0.4
0.4
0.4
DDR3-
Units
1600
0.4
V
0.4
V
0.33
V-ns
0.33
V-ns
Maximum Amplitude
Overshoot Area
Volts
(V)
VDD
VSS
Undershoot Area
Maximum Amplitude
Time (ns)
Address and Control Overshoot and Undershoot Definition
Rev. 1.0 / Aug. 2012 40
Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications
AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask
DDR3-
Parameter
800
Maximum peak amplitude allowed for overshoot area. (See Figure below)
Maximum peak amplitude allowed for undershoot area. (See Figure below)
Maximum overshoot area above VDD (See Figure below)
0.4
0.4
0.25
Maximum undershoot area below VSS (See Figure below)
(CK,
CK
, DQ, DQS,
DQS
, DM)
0.25
See figure below for each parameter definition
DDR3-
1066
0.4
0.4
0.19
0.19
DDR3-
1333
0.4
0.4
0.15
0.15
DDR3-
Units
1600
0.4
V
0.4
V
0.13
V-ns
0.13
V-ns
Maximum Amplitude
Overshoot Area
Volts
(V)
VDDQ
VSSQ
Undershoot Area
Maximum Amplitude
Time (ns)
Clock, Data, Strobe and Mask Overshoot and Undershoot Definition
Rev. 1.0 / Aug. 2012 41
Refresh parameters by device density
Refresh parameters by device density
Parameter
REF command ACT or
REF command time
Average periodic refresh interval
RTT_Nom Setting tREFI tRFC
512Mb
90
0
C
T
CASE
85
C 7.8
85
C
T
CASE
95
C 3.9
1Gb
110
7.8
3.9
2Gb
160
7.8
3.9
4Gb
260
7.8
3.9
8Gb Units Notes
350 ns
7.8
3.9
us us 1
Rev. 1.0 / Aug. 2012 42
Standard Speed Bins
DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for each corresponding bin.
DDR3-800 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 47.
Speed Bin
CL - nRCD - nRP
Parameter
Internal read command to first data
Symbol t
AA min
DDR3-800E
6-6-6 max
15 20
ACT to internal read or write delay time t
RCD
15 —
PRE command period t
RP
15 —
ACT to ACT or REF command period t
RC
52.5
—
ACT to PRE command period
CL = 6 CWL = 5
Supported CL Settings
Supported CWL Settings t
RAS t
CK(AVG)
37.5
2.5
6
5
9 * tREFI
3.3
Unit ns ns ns ns ns ns n
CK n
CK
Notes
1,2,3
Rev. 1.0 / Aug. 2012 43
DDR3-1066 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 47.
Speed Bin
CL - nRCD - nRP
Parameter Symbol
Internal read command to first data t
AA
ACT to internal read or write delay time t
RCD min
13.125
13.125
DDR3-1066F
7-7-7 max
20
—
PRE command period t
RP
ACT to ACT or REF command period t
RC
ACT to PRE command period t
RAS
CL = 6
CL = 7
CL = 8
CWL = 5
CWL = 6
CWL = 5
CWL = 6
CWL = 5
CWL = 6 t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG)
Supported CL Settings
Supported CWL Settings
13.125
50.625
37.5
2.5
1.875
1.875
Reserved
Reserved
Reserved
6, 7, 8
5, 6
—
—
9 * tREFI
3.3
< 2.5
< 2.5
Unit ns ns ns ns ns ns ns ns ns ns ns n
CK n
CK
Note
1,2,3,6
1,2,3,4
4
1,2,3,4
4
1,2,3
Rev. 1.0 / Aug. 2012 44
DDR3-1333 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 47.
Speed Bin
CL - nRCD - nRP
Parameter Symbol
Internal read command to first data t
AA
ACT to internal read or write delay time t
RCD
PRE command period t
RP min
13.5
(13.125)
5,9
13.5
(13.125)
5,9
13.5
(13.125)
5,9
49.5
(49.125)
5,9
DDR3-1333H
9-9-9 max
20
—
—
—
ACT to ACT or REF command period t
RC
ACT to PRE command period
CL = 6
CWL = 5
CWL = 6
CWL = 7
CWL = 5 t
RAS t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG)
36
2.5
9 * tREFI
CL = 7 CWL = 6 t
CK(AVG)
CL = 8
CL = 9
CL = 10
CWL = 7
CWL = 5
CWL = 6
CWL = 7
CWL = 5, 6
CWL = 7
CWL = 5, 6
CWL = 7 t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG)
Supported CL Settings
Supported CWL Settings
1.875
1.875
1.5
1.5
3.3
Reserved
Reserved
Reserved
< 2.5
(Optional)
5,9
Reserved
Reserved
< 2.5
Reserved
Reserved
<1.875
Reserved
(Optional)
6, 7, 8, 9, 10
<1.875
5, 6, 7
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns n
CK n
CK
Note
1,2,3,7
1,2,3,4,7
4
4
1,2,3,4,7
1,2,3,4
4
1,2,3,7
1,2,3,4
4
1,2,3,4
4
1,2,3
5
Rev. 1.0 / Aug. 2012 45
DDR3-1600 Speed Bins
For specific Notes See "Speed Bin Table Notes" on page 47.
Speed Bin
CL - nRCD - nRP
Parameter Symbol
Internal read command to first data t
AA
ACT to internal read or write delay time t
RCD
PRE command period t
RP
ACT to ACT or REF command period t
RC
ACT to PRE command period
CL = 6
CWL = 5
CWL = 6
CWL = 7
CWL = 5 t
RAS t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG)
CL = 7
CL = 8
CL = 9
CWL = 6
CWL = 7
CWL = 8
CWL = 5
CWL = 6
CWL = 7
CWL = 8
CWL = 5, 6
CWL = 7
CL = 10
CL = 11
CWL = 8
CWL = 5, 6
CWL = 7
CWL = 8
CWL = 5, 6,7
CWL = 8 t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG)
Supported CL Settings
Supported CWL Settings t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) t
CK(AVG) min
13.75
(13.125) 5,9
13.75
(13.125)
5,9
13.75
(13.125) 5,9
48.75
(48.125)
5,9
35
2.5
1.875
1.875
1.5
1.5
1.25
DDR3-1600K
11-11-11 max
20
—
—
—
9 * tREFI
3.3
Reserved
Reserved
Reserved
< 2.5
(Optional) 5,9
Reserved
Reserved
Reserved
< 2.5
Reserved
Reserved
Reserved
<1.875
(Optional)
5,9
Reserved
Reserved
<1.875
Reserved
Reserved
<1.5
5, 6, 7, 8, 9, 10, 11
5, 6, 7, 8
Rev. 1.0 / Aug. 2012
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns n
CK n
CK ns ns ns
Note
1,2,3,8
1,2,3,4,8
4
4
1,2,3,4,8
1,2,3,4,8
4
4
1,2,3,8
1,2,3,4,8
1,2,3,4
4
1,2,3,4,8
1,2,3,4
4
1,2,3,8
1,2,3,4
4
1,2,3
46
Speed Bin Table Notes
Absolute Specification (T
OPER
; V
DDQ
= V
DD
= 1.5V +/- 0.075 V);
1. The CL setting and CWL setting result in tCK(AVG).MIN and tCK(AVG).MAX requirements. When making a selection of tCK(AVG), both need to be fulfilled: Requirements from CL setting as well as requirements from CWL setting.
2. tCK(AVG).MIN limits: Since CAS Latency is not purely analog - data and strobe output are synchronized by the DLL - all possible intermediate frequencies may not be guaranteed. An application should use the next smaller JEDEC standard tCK(AVG) value (3.0, 2.5, 1.875, 1.5, or 1.25 ns) when calculating CL [nCK] = tAA [ns] / tCK(AVG) [ns], rounding up to the next ‘Supported CL’, where tCK(AVG) =
3.0 ns should only be used for CL = 5 calculation.
3. tCK(AVG).MAX limits: Calculate tCK(AVG) = tAA.MAX / CL SELECTED and round the resulting tCK(AVG) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). This result is tCK(AVG).MAX corresponding to CL SELECTED.
4. ‘Reserved’ settings are not allowed. User must program a different value.
5. ‘Optional’ settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. Refer to DIMM data sheet and/or the DIMM SPD information if and how this setting is supported.
6. Any DDR3-1066 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization.
7. Any DDR3-1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization.
8. Any DDR3-1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design/Characterization.
9. DDR3 SDRAM devices supporting optional down binning to CL=7 and CL=9, and tAA/tRCD/tRP must be 13.125 ns or lower. SPD settings must be programmed to match. For example, DDR3-1333H devices supporting down binning to DDR3-1066F should program 13.125 ns in SPD bytes for tAAmin
(Byte 16), tRCDmin (Byte 18), and tRPmin (Byte 20). DDR3-1600K devices supporting down binning to
DDR3-1333H or DDR3-1600F should program 13.125 ns in SPD bytes for tAAmin (Byte 16), tRCDmin
(Byte 18), and tRPmin (Byte 20). Once tRP (Byte 20) is programmed to 13.125ns, tRCmin (Byte 21,23) also should be programmed accordingly. For example, 49.125ns (tRASmin + tRPmin = 36 ns + 13.125 ns) for DDR3-1333H and 48.125ns (tRASmin + tRPmin = 35 ns + 13.125 ns) for DDR3-1600K.
Rev. 1.0 / Aug. 2012 47
Environmental Parameters
Symbol
T
OPR
H
OPR
T
STG
H
STG
P
BAR
Parameter
Operating temperature
Operating humidity (relative)
Storage temperature
Storage humidity (without condensation)
Barometric Pressure (operating & storage)
Rating
See Note
10 to 90
-50 to +100
5 to 95
105 to 69
Units Notes
3
1 % o
C
%
1
1
K Pascal 1, 2
Note :
1. Stress greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation at or above the conditions indicated is not implied. Expousure to absolute maximum rating conditions for extended periods may affect reliablility.
2. Up to 9850 ft.
3. The designer must meet the case temperature specifications for individual module components.
Rev. 1.0 / Aug. 2012 48
IDD and IDDQ Specification Parameters and Test Conditions
IDD and IDDQ Measurement Conditions
In this chapter, IDD and IDDQ measurement conditions such as test load and patterns are defined. Figure
1. shows the setup and test load for IDD and IDDQ measurements.
• IDD currents (such as IDD0, IDD1, IDD2N, IDD2NT, IDD2P0, IDD2P1, IDD2Q, IDD3N, IDD3P, IDD4R,
IDD4W, IDD5B, IDD6, IDD6ET and IDD7) are measured as time-averaged currents with all VDD balls of the DDR3 SDRAM under test tied together. Any IDDQ current is not included in IDD currents.
• IDDQ currents (such as IDDQ2NT and IDDQ4R) are measured as time-averaged currents with all
VDDQ balls of the DDR3 SDRAM under test tied together. Any IDD current is not included in IDDQ currents.
Attention: IDDQ values cannot be directly used to calculate IO power of the DDR3 SDRAM. They can be used to support correlation of simulated IO power to actual IO power as outlined in Figure 2. In
DRAM module application, IDDQ cannot be measured separately since VDD and VDDQ are using one merged-power layer in Module PCB.
For IDD and IDDQ measurements, the following definitions apply:
• ”0” and “LOW” is defined as VIN <= V
ILAC(max).
• ”1” and “HIGH” is defined as VIN >= V
IHAC(max).
• “MID_LEVEL” is defined as inputs are VREF = VDD/2.
• Timing used for IDD and IDDQ Measurement-Loop Patterns are provided in Table 1.
• Basic IDD and IDDQ Measurement Conditions are described in Table 2.
• Detailed IDD and IDDQ Measurement-Loop Patterns are described in Table 3 through Table 10.
• IDD Measurements are done after properly initializing the DDR3 SDRAM. This includes but is not limited to setting
RON = RZQ/7 (34 Ohm in MR1);
Qoff = 0
B
(Output Buffer enabled in MR1);
RTT_Nom = RZQ/6 (40 Ohm in MR1);
RTT_Wr = RZQ/2 (120 Ohm in MR2);
TDQS Feature disabled in MR1
• Attention: The IDD and IDDQ Measurement-Loop Patterns need to be executed at least one time before actual IDD or IDDQ measurement is started.
• Define D = {CS, RAS, CAS, WE}:= {HIGH, LOW, LOW, LOW}
• Define D = {CS, RAS, CAS, WE}:= {HIGH, HIGH, HIGH, HIGH}
Rev. 1.0 / Aug. 2012 49
I
DD
I
DDQ (optional)
V
DD
RESET
CK/CK
CKE
CS
RAS, CAS, WE
A, BA
ODT
ZQ
V
SS
DDR3
SDRAM
V
DDQ
DQS, DQS
DQ, DM,
TDQS, TDQS
R
TT = 25 Ohm
V
DDQ
/2
V
SSQ
Figure 1 - Measurement Setup and Test Load for IDD and IDDQ (optional) Measurements
[Note: DIMM level Output test load condition may be different from above
Application specific memory channel environment
IDDQ
Test Load
Channel
IO Power
Simulation
IDDQ
Simulation
IDDQ
Simulation
Correction
Channel IO Power
Number
Figure 2 - Correlation from simulated Channel IO Power to actual Channel IO Power supported by IDDQ Measurement
Rev. 1.0 / Aug. 2012 50
Table 1 -Timings used for IDD and IDDQ Measurement-Loop Patterns
Symbol t
CK
CL n
RCD n
RC n
RAS n
RP n
FAW
1KB page size
2KB page size n
RRD
1KB page size
2KB page size n
RFC
-512Mb n
RFC
-1 Gb n
RFC
- 2 Gb n
RFC
- 4 Gb n
RFC
- 8 Gb
48
59
86
139
187
4
6
20
27
DDR3-1066
7-7-7
1.875
7
7
27
20
7
60
74
107
174
234
4
5
20
30
DDR3-1333
9-9-9
1.5
9
9
33
24
9
DDR3-1600
11-11-11
1.25
11
11
39
28
11
72
88
128
208
280
24
32
5
6
Unit nCK nCK nCK nCK ns nCK nCK nCK nCK nCK nCK nCK nCK nCK nCK
Table 2 -Basic IDD and IDDQ Measurement Conditions
Symbol
I
DD0
Description
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; tCK, nRC, nRAS, CL: see Table 1; BL: 8 a) ; AL: 0; CS: High between ACT and
PRE; Command, Address, Bank Address Inputs: partially toggling according to Table 3; Data IO: MID-LEVEL;
DM: stable at 0; Bank Activity: Cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 3); Output Buffer and RTT: Enabled in Mode Registers b) ; ODT Signal: stable at 0; Pattern Details: see Table 3.
Operating One Bank Active-Precharge Current
I
DD1
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 1; BL: 8 a)
; AL: 0; CS: High between ACT,
RD and PRE; Command, Address; Bank Address Inputs, Data IO: partially toggling according to Table 4; DM: stable at 0; Bank Activity: Cycling with on bank active at a time: 0,0,1,1,2,2,... (see Table 4); Output Buffer and
RTT: Enabled in Mode Registers b) ; ODT Signal: stable at 0; Pattern Details: see Table 4.
Rev. 1.0 / Aug. 2012 51
Symbol
I
DD2N
Description
Precharge Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8 a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers b) ; ODT Signal: stable at 0; Pattern Details: see Table 5.
Precharge Standby ODT Current
I
DD2NT
I
I
I
I
I
DD2P0
DD2P1
DD2Q
DD3N
DD3P
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8 a) ; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 6; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers b) ; ODT Signal: toggling according to Table 6;
Pattern Details: see Table 6.
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8 a) ; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers b)
; ODT Signal: stable at 0; Precharge Power Down Mode: Slow Exit c)
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8 a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers b)
; ODT Signal: stable at 0; Precharge Power Down Mode: Fast Exit c)
Precharge Quiet Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8 a) ; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in Mode Registers b) ; ODT Signal: stable at 0
Active Standby Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8 a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: partially toggling according to Table 5; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers b)
; ODT Signal: stable at 0; Pattern Details: see
Table 5.
Active Power-Down Current
CKE: Low; External clock: On; tCK, CL: see Table 1; BL: 8 a)
; AL: 0; CS: stable at 1; Command, Address, Bank
Address Inputs: stable at 0; Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in Mode Registers b) ; ODT Signal: stable at 0
Rev. 1.0 / Aug. 2012 52
Symbol
I
DD4R
Description
Operating Burst Read Current
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8 a)
; AL: 0; CS: High between RD; Command, Address,
Bank Address Inputs: partially toggling according to Table 7; Data IO: seamless read data burst with different data between one burst and the next one according to Table 7; DM: stable at 0; Bank Activity: all banks open,
RD commands cycling through banks: 0,0,1,1,2,2,...(see Table 7); Output Buffer and RTT: Enabled in Mode
Registers b)
; ODT Signal: stable at 0; Pattern Details: see Table 7.
Operating Burst Write Current
I
I
DD4W
DD5B
CKE: High; External clock: On; tCK, CL: see Table 1; BL: 8 a)
; AL: 0; CS: High between WR; Command, Address,
Bank Address Inputs: partially toggling according to Table 8; Data IO: seamless read data burst with different data between one burst and the next one according to Table 8; DM: stable at 0; Bank Activity: all banks open,
WR commands cycling through banks: 0,0,1,1,2,2,...(see Table 8); Output Buffer and RTT: Enabled in Mode
Registers b)
; ODT Signal: stable at HIGH; Pattern Details: see Table 8.
Burst Refresh Current
CKE: High; External clock: On; tCK, CL, nRFC: see Table 1; BL: 8 a)
; AL: 0; CS: High between REF; Command,
Address, Bank Address Inputs: partially toggling according to Table 9; Data IO: MID_LEVEL; DM: stable at 0;
Bank Activity: REF command every nREF (see Table 9); Output Buffer and RTT: Enabled in Mode Registers b)
;
ODT Signal: stable at 0; Pattern Details: see Table 9.
Self-Refresh Current: Normal Temperature Range
I
I
DD6
DD6ET
T
CASE
: 0 - 85 o C; Auto Self-Refresh (ASR): Disabled d) ;Self-Refresh Temperature Range (SRT): Normal e) ; CKE:
Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8 a)
; AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers b)
; ODT Signal: MID_LEVEL
Self-Refresh Current: Extended Temperature Range (optional)
T
CASE
: 0 - 95 o C; Auto Self-Refresh (ASR): Disabled d) ;Self-Refresh Temperature Range (SRT): Extended e) ;
CKE: Low; External clock: Off; CK and CK: LOW; CL: see Table 1; BL: 8 a) ; AL: 0; CS, Command, Address, Bank
Address Inputs, Data IO: MID_LEVEL; DM: stable at 0; Bank Activity: Extended Temperature Self-Refresh operation; Output Buffer and RTT: Enabled in Mode Registers b) ; ODT Signal: MID_LEVEL
Rev. 1.0 / Aug. 2012 53
Symbol
I
DD7
Description
Operating Bank Interleave Read Current
CKE: High; External clock: On; tCK, nRC, nRAS, nRCD, NRRD, nFAW, CL: see Table 1; BL: 8 a),f)
; AL: CL-1; CS:
High between ACT and RDA; Command, Address, Bank Address Inputs: partially toggling according to Table
10; Data IO: read data burst with different data between one burst and the next one according to Table 10;
DM: stable at 0; Bank Activity: two times interleaved cycling through banks (0, 1,...7) with different addressing, wee Table 10; Output Buffer and RTT: Enabled in Mode Registers b)
; ODT Signal: stable at 0; Pattern
Details: see Table 10.
a) Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B b) Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2]
= 011B; RTT_Wr enable: set MR2 A[10,9] = 10B c) Precharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12 = 1B for Fast Exit d) Auto Self-Refresh (ASR): set MR2 A6 = 0B to disable or 1B to enable feature e) Self-Refresh Temperature Range (SRT): set MR2 A7 = 0B for normal or 1B for extended temperature range f) Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B
Rev. 1.0 / Aug. 2012 54
Table 3 - IDD0 Measurement-Loop Pattern a)
0 0
1,2
3,4
...
nRAS
...
1*nRC+0
1*nRC+1, 2
1*nRC+3, 4
...
1*nRC+nRAS
...
1 2*nRC
2 4*nRC
3 6*nRC
4 8*nRC
5 10*nRC
6 12*nRC
7 14*nRC
ACT 0 0 1 1 0 0 00 0 0 0
D, D 1 0 0 0 0 0 00 0 0
D, D 1 1 1 1 0 0 00 0 0 repeat pattern 1...4 until nRAS - 1, truncate if necessary
PRE 0 0 1 0 0 0 00 0 0
0
0
PRE 0 0 1 0 0 0 00 0 0 repeat pattern 1...4 until 2*nRC - 1, truncate if necessary
0 repeat pattern 1...4 until nRC - 1, truncate if necessary
ACT
D, D
0
D, D 1
1
0
0
1
1
0
1
1
0
1
0
0
0
0
0
0
00
00
00
0
0
0
0
0
0
F
F
F repeat pattern 1...4 until 1*nRC + nRAS - 1, truncate if necessary
F repeat Sub-Loop 0, use BA[2:0] = 1 instead repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead
0
0
0
0
0
0
0
0 a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
Data b)
-
-
-
-
-
-
-
-
Rev. 1.0 / Aug. 2012 55
Table 4 - IDD1 Measurement-Loop Pattern a)
Data b)
0 0
1,2
3,4
...
nRCD
...
nRAS
...
1*nRC+0
1*nRC+1,2
1*nRC+3,4
...
1*nRC+nRCD
...
1*nRC+nRAS
...
1 2*nRC
2 4*nRC
3 6*nRC
4 8*nRC
5 10*nRC
6 12*nRC
7 14*nRC
ACT 0 0 1 1 0 0 00 0 0 0 0 -
D, D 1 0 0 0 0 0 00 0 0
D, D 1 1 1 1 0 0 00 0 repeat pattern 1...4 until nRCD - 1, truncate if necessary
0
RD 0 1 0 1 0 0 00 0 0 repeat pattern 1...4 until nRAS - 1, truncate if necessary
PRE 0 0 1 0 0 0 00 0 0
0
0
0
0
0
0
0 0 repeat pattern 1...4 until nRC - 1, truncate if necessary
ACT 0
D, D 1
0
0
1
0
1
0
0
0
0
0
00 0
00 0
0
0
F
F
0
0
D, D 1 1 1 1 0 0 00 0 0 F 0 repeat pattern nRC + 1,...4 until nRC + nRCE - 1, truncate if necessary
-
-
00000000
-
-
-
-
RD 0 1 0 1 0 0 00 0 0 F 0 00110011 repeat pattern nRC + 1,...4 until nRC + nRAS - 1, truncate if necessary
0 PRE 0 0 1 0 0 0 00 0 0 F repeat pattern nRC + 1,...4 until *2 nRC - 1, truncate if necessary repeat Sub-Loop 0, use BA[2:0] = 1 instead repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-
LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are
MID_LEVEL.
Rev. 1.0 / Aug. 2012 56
Table 5 - IDD2N and IDD3N Measurement-Loop Pattern a)
0 0
1
2
3
1 4-7
2 8-11
3 12-15
4 16-19
5 20-23
6 24-17
7 28-31
D 1 0 0 0 0 0 0
D
D
D
1
1
1
0
1
1
0
1
1
0
1
1
0
0
0
0
0
0 repeat Sub-Loop 0, use BA[2:0] = 1 instead
0
0
0 repeat Sub-Loop 0, use BA[2:0] = 2 instead repeat Sub-Loop 0, use BA[2:0] = 3 instead repeat Sub-Loop 0, use BA[2:0] = 4 instead repeat Sub-Loop 0, use BA[2:0] = 5 instead repeat Sub-Loop 0, use BA[2:0] = 6 instead repeat Sub-Loop 0, use BA[2:0] = 7 instead a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
0
0
0
0
Table 6 - IDD2NT and IDDQ2NT Measurement-Loop Pattern a)
0
0
0
0
0
0
F
F
0
0
0
0
Data b)
-
-
-
-
0 0
1
2
3
1 4-7
2 8-11
3 12-15
4 16-19
5 20-23
6 24-17
7 28-31
D
D
D
D
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 1 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 2
0
0
0
0 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 3 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 4 repeat Sub-Loop 0, but ODT = 0 and BA[2:0] = 5 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 6 repeat Sub-Loop 0, but ODT = 1 and BA[2:0] = 7 a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
0
0
0
0
F
F
0
0
0
0
0
0
Data b)
-
-
-
-
Rev. 1.0 / Aug. 2012 57
Table 7 - IDD4R and IDDQ4R Measurement-Loop Pattern a)
Data b)
0 0
1
2,3
4
5
6,7
1 8-15
2 16-23
3 24-31
4 32-39
5 40-47
6 48-55
7 56-63
RD 0 1 0 1 0
D
D,D
RD
D
1
1
0
1
0
1
1
0
0
1
0
0
0
1
1
0
D,D 1 1 1 1 0 repeat Sub-Loop 0, but BA[2:0] = 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 0, but BA[2:0] = 3 repeat Sub-Loop 0, but BA[2:0] = 4 repeat Sub-Loop 0, but BA[2:0] = 5 repeat Sub-Loop 0, but BA[2:0] = 6 repeat Sub-Loop 0, but BA[2:0] = 7
0
0
0
0
0
0
0
0
0
0
00
00
00
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
F
0 00000000
0
0
0 -
0 -
0 00110011
-
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
Table 8 - IDD4W Measurement-Loop Pattern a)
Data b)
0 0
1
2,3
4
5
6,7
1 8-15
2 16-23
3 24-31
4 32-39
5 40-47
6 48-55
7 56-63
WR 0 1 0 0 1
D
D,D
WR
1
1
0
0
1
1
0
1
0
0
1
0
1
1
1
D
D,D
1
1
0
1
0
1
0
1
1
1 repeat Sub-Loop 0, but BA[2:0] = 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 0, but BA[2:0] = 3 repeat Sub-Loop 0, but BA[2:0] = 4 repeat Sub-Loop 0, but BA[2:0] = 5 repeat Sub-Loop 0, but BA[2:0] = 6 repeat Sub-Loop 0, but BA[2:0] = 7
0
0
0
0
0
0
00
00
00
00
00
00
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
F
F
F
0
0
0
00000000
0 -
0 -
0 00110011
-
a) DM must be driven LOW all the time. DQS, DQS are used according to WR Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Write Command. Outside burst operation, DQ signals are MID-LEVEL.
Rev. 1.0 / Aug. 2012 58
Table 9 - IDD5B Measurement-Loop Pattern a)
0 0
1 1.2
3,4
5...8
9...12
13...16
17...20
21...24
25...28
29...32
2 33...nRFC-1
REF 0 0 0 1 0 0 0 0 0
D, D 1 0 0 0 0
D, D 1 1 1 1 0 repeat cycles 1...4, but BA[2:0] = 1 repeat cycles 1...4, but BA[2:0] = 2 repeat cycles 1...4, but BA[2:0] = 3 repeat cycles 1...4, but BA[2:0] = 4 repeat cycles 1...4, but BA[2:0] = 5 repeat cycles 1...4, but BA[2:0] = 6
0
0
00
00
0
0 repeat cycles 1...4, but BA[2:0] = 7 repeat Sub-Loop 1, until nRFC - 1. Truncate, if necessary.
0
0 a) DM must be driven LOW all the time. DQS, DQS are MID-LEVEL.
b) DQ signals are MID-LEVEL.
0
0
F
0
0
0
Data b)
-
-
-
Rev. 1.0 / Aug. 2012 59
Table 10 - IDD7 Measurement-Loop Pattern a)
ATTENTION! Sub-Loops 10-19 have inverse A[6:3] Pattern and Data Pattern than Sub-Loops 0-9
Data b)
0 0
1
2
...
nRRD nRRD+1
1 nRRD+2
...
2 2*nRRD
3 3*nRRD
4
4*nRRD
5 nFAW
6 nFAW+nRRD
7 nFAW+2*nRRD
8 nFAW+3*nRRD
9 nFAW+4*nRRD
10
11
2*nFAW+0
2*nFAW+1
2&nFAW+2
2*nFAW+nRRD
2*nFAW+nRRD+1
2&nFAW+nRRD+2
12 2*nFAW+2*nRRD
13 2*nFAW+3*nRRD
14 2*nFAW+4*nRRD
15 3*nFAW
16 3*nFAW+nRRD
17 3*nFAW+2*nRRD
18 3*nFAW+3*nRRD
19 3*nFAW+4*nRRD
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0 repeat above D Command until nRRD - 1
ACT 0 0 1 1 0
RDA 0 1 0 1 0
0
0
0
1
1
00
00
00
00
00
00
0
1
0
0
1
0
0
0
0
0
0
0 D 1 0 0 0 0 1 repeat above D Command until 2* nRRD - 1 repeat Sub-Loop 0, but BA[2:0] = 2 repeat Sub-Loop 1, but BA[2:0] = 3
D 1 0 0 0 0 3 00 0 0
Assert and repeat above D Command until nFAW - 1, if necessary repeat Sub-Loop 0, but BA[2:0] = 4 repeat Sub-Loop 1, but BA[2:0] = 5 repeat Sub-Loop 0, but BA[2:0] = 6
F repeat Sub-Loop 1, but BA[2:0] = 7
D 1 0 0 0 0 7 00 0 0 F
Assert and repeat above D Command until 2* nFAW - 1, if necessary
F
F
F
0
0
0
ACT
RDA
D
0
0
1
0
1
0
1
0
0
1
1
0
0
0
0
0
0
0
00
00
00
Repeat above D Command until 2* nFAW + nRRD - 1
0
1
0
ACT
RDA
0
0
0
1
1
0
1
1
0
0
1
1
00
00
0
1
D 1 0 0 0 0 1 00 0
Repeat above D Command until 2* nFAW + 2* nRRD - 1
0
0
0
0
0
0
F
F
F
0
0
0 repeat Sub-Loop 10, but BA[2:0] = 2 repeat Sub-Loop 11, but BA[2:0] = 3
D 1 0 0 0 0 3 00 0 0 0
Assert and repeat above D Command until 3* nFAW - 1, if necessary repeat Sub-Loop 10, but BA[2:0] = 4 repeat Sub-Loop 11, but BA[2:0] = 5 repeat Sub-Loop 10, but BA[2:0] = 6 repeat Sub-Loop 11, but BA[2:0] = 7
D 1 0 0 0 0 7 00 0 0 0
Assert and repeat above D Command until 4* nFAW - 1, if necessary
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
00000000
-
-
00110011
-
-
00110011
-
-
00000000
-
-
-
-
a) DM must be driven LOW all the time. DQS, DQS are used according to RD Commands, otherwise MID-LEVEL.
b) Burst Sequence driven on each DQ signal by Read Command. Outside burst operation, DQ signals are MID-LEVEL.
Rev. 1.0 / Aug. 2012 60
IDD Specifications (Tcase: 0 to 95
o
C)
* Module IDD values in the datasheet are only a calculation based on the component IDD spec and register power.
The actual measurements may vary according to DQ loading cap.
4GB, 512M x 72 R-DIMM: HMT451R7MFR8C
Symbol
IDD0
IDD1
IDD2N
IDD2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDD4W
IDD5B
IDD6
IDD6ET
IDD7
DDR3 1066
1169
1259
989
1034
408
426
989
1079
453
1619
1664
2024
408
426
2204
DDR3 1333
1214
1304
1034
1079
408
426
1034
1079
453
1754
1799
2069
408
426
2339
DDR3 1600
1214
1304
1034
1079
408
426
1034
1079
453
1889
1934
2069
408
426
2384 mA mA mA mA mA mA mA
Unit mA mA mA mA mA mA mA mA note
8GB, 1G x 72 R-DIMM: HMT41GR7MFR4C
Symbol
IDD0
IDD1
IDD2N
IDD2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDD4W
IDD5B
IDD6
IDD6ET
IDD7
DDR3 1066
1574
1754
1214
1304
588
624
1214
1394
678
2294
2294
3284
588
624
3464
DDR3 1333
1664
1844
1304
1394
588
624
1304
1394
678
2564
2564
3374
588
624
3734
DDR3 1600
1664
1844
1304
1394
588
624
1304
1394
678
2834
2744
3374
588
624
3824 mA mA mA mA mA mA mA mA mA
Unit mA mA mA mA mA mA note
Rev. 1.0 / Aug. 2012 61
8GB, 1GM x 72 R-DIMM: HMT41GR7MFR8C
Symbol
IDD0
IDD1
IDD2N
IDD2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDD4W
IDD5B
IDD6
IDD6ET
IDD7
DDR3 1066
1394
1484
1214
1304
588
624
1214
1394
678
1844
1889
2249
588
624
2429
DDR3 1333
1484
1574
1304
1394
588
624
1304
1394
678
2024
2069
2339
588
624
2609
16GB, 2G x 72 R-DIMM: HMT42GR7MFR4C
Symbol
IDD0
IDD1
IDD2N
IDD2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDD4W
IDD5B
IDD6 a)
IDD6ET
IDD7
DDR3 1066
2024
2204
1664
1844
948
1020
1664
2024
1128
2744
2744
3734
948
1020
3914
DDR3 1333
2204
2384
1844
2024
948
1020
1844
2024
1128
3104
3104
3914
948
1020
4274
DDR3 1600
1529
1619
1304
1394
588
624
1304
1394
678
2204
2249
2384
588
624
2699 mA mA mA mA mA mA mA mA mA
Unit mA mA mA mA mA mA note
DDR3 1600
2294
2474
1844
2024
948
1020
1844
2024
1128
3464
3374
4004
948
1020
4454 mA mA mA mA mA mA mA mA
Unit mA mA mA mA mA mA mA note
Rev. 1.0 / Aug. 2012 62
32GB, 4G x 72 R-DIMM: HMT84GR7MMR4C
Symbol
IDD0
IDD1
IDD2N
IDD2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
IDD4W
IDD5B
IDD6
IDD6ET
IDD7
DDR3 1066
2924
3104
2564
2924
1668
1812
2564
3284
2028
3644
3644
4634
1668
1812
4814
DDR3 1333
3284
3464
2924
3284
1668
1812
2924
3284
2028
4184
4184
4944
1668
1812
5354 mA mA mA mA mA mA mA mA mA
Unit mA mA mA mA mA mA note
Rev. 1.0 / Aug. 2012 63
Module Dimensions
512Mx72 - HMT451R7MFR8C
Front
133.35
128.95
SPD/TS 2.10±0.15
4X3.00±0.10
Detail A
2X3.00±0.10
1
1
5.175
47.00
Detail B Detail C
5.0
Back
71.00
120
240
2x R0.75 Max
Detail of Contacts A
1.20
±
0.15
3
±
0.1
Detail of Contacts B
0.80
± 0.05
1.00
Detail of Contacts C
2.50
1.50
±
0.10
5.00
0.3~0.1
Note :
Rev. 1.0 / Aug. 2012
121
1
Side
3.43mm max
1.27±010mm max
Units: millimeters
64
1Gx72 - HMT41GR7MFR4C
Front
133.35
128.95
SPD/TS
Detail A
4X3.00±0.10
2.10±0.15
2X3.00±0.10
1
1
5.175
Detail B
47.00
Detail C
5.0
Back
71.00
120
240
2x R0.75 Max
Detail of Contacts A
1.20
± 0.15
3
±
0.1
Detail of Contacts B
0.80
±
0.05
1.00
Detail of Contacts C
2.50
1.50
±
0.10
5.00
0.3+0.1
Note :
Rev. 1.0 / Aug. 2012
121
1
Side
3.43mm max
1.27±010mm max
Units: millimeters
65
1Gx72 - HMT41GR7MFR8C
Front
133.35
128.95
SPD/TS
Detail A
4X3.00±0.10
2.10±0.15
2X3.00±0.10
1
1
5.175
Detail B
47.00
Detail C
5.0
Back
71.00
120
240
2x R0.75 Max
Detail of Contacts A
1.20
± 0.15
3
±
0.1
Detail of Contacts B
0.80
±
0.05
1.00
Detail of Contacts C
2.50
1.50
±
0.10
5.00
0.3+0.1
Note :
Rev. 1.0 / Aug. 2012
121
1
Side
3.43mm max
1.27±010mm max
Units: millimeters
66
2Gx72 - HMT42GR7MFR4C
Detail B
2.10±0.15
Detail A
4X3.00±0.10
2X3.00±0.10
1
1
5.175
Front
133.35
128.95
SPD/TS
47.00
Detail C 5.0
Detail D
Back
71.00
120
240
2x R0.75 Max
Detail of Contacts A
1.20
± 0.15
Detail of Contacts B
14.90
13.60
0.4
3 ± 0.1
Detail of Contacts C
0.80
±
0.05
1.00
Note :
Rev. 1.0 / Aug. 2012
Detail of Contacts D
2.50
121
1
Side
3.43mm max
1.50 ± 0.10
5.00
0.3~0.1
1.27±010mm max
Units: millimeters
67
2Gx72 - HMT42GR7MFR4C - Heat Spreader
42.7
20.9
6.35
36.7
2.15
Front
133.75
133.35
127
8
6.3
1
7.36
46.46
80.54
33.4
57.2
119.64
Back
33.4
2.7
7.74
120
2.786
2x R0.75 Max
121 240
Side
7.19mm max
Note :
2.In order to uninstall FDHS, please contact sales administrator.
Rev. 1.0 / Aug. 2012
1.27±010mm max
Units: millimeters
68
4Gx72 - HMT84GR7MMR4C
2.10±0.15
Detail A
4X3.00±0.10
DDP
2X3.00±0.10
1
1
5.175
DDP
DDP
DDP
DDP
Detail B
DDP
DDP
DDP
DDP
Front
133.35
128.95
SPD/TS
DDP
DDP
DDP
47.00
Detail C
DDP
5.0
Detail D
DDP
SPD/TS
Back
DDP
DDP
DDP
DDP
DDP
DDP
71.00
DDP
DDP
DDP
DDP
DDP
DDP
120
DDP
2x R0.75 Max
Detail of Contacts A
1.20
±
0.15
240
DDP DDP DDP DDP
Detail of Contacts B
14.90
13.60
0.4
Detail of Contacts C
0.80
±
0.05
DDP DDP DDP DDP DDP
121
1
Side
3.43mm max
Detail of Contacts D
2.50
3 ± 0.1
1.00
1.50 ± 0.10
5.00
0.3~0.1
1.27±010mm max
Note :
Rev. 1.0 / Aug. 2012
Units: millimeters
69
4Gx72 - HMT84GR7MMR4C - Heat Spreader
41.9
20.9
6.35
36.7
2.155
4.49
5.39
Front
133.75
133.35
127
8
6.3
1
7.36
46.46
80.54
33.4
57.2
119.64
Back
33.4
2.7
8.04
120
3.59
121 240
Side
7.19mm max
Note :
2.In order to uninstall FDHS, please contact sales administrator.
Rev. 1.0 / Aug. 2012
1.27±010mm max
Units: millimeters
70
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Table of contents
- 3 Description
- 3 Features
- 3 Ordering Information
- 4 Key Parameters
- 4 Speed Grade
- 4 Address Table
- 5 Pin Descriptions
- 6 Input/Output Functional Descriptions
- 8 Pin Assignments
- 10 Registering Clock Driver Specifications
- 10 Capacitance Values
- 10 Input & Output Timing Requirements
- 11 On DIMM Thermal Sensor
- 11 Connection of Thermal Sensor
- 11 Temperature-to-Digital Conversion Performance
- 12 Functional Block Diagram
- 12 4GB, 512Mx72 Module(1Rank of x8)
- 13 8GB, 1Gx72 Module(1Rank of x4) - page1
- 14 8GB, 1Gx72 Module(1Rank of x4) - page2
- 15 8GB, 1Gx72 Module(2Rank of x8) - page1
- 16 8GB, 1Gx72(2Rank of x8) - page2
- 17 16GB, 2Gx72 Module(2Rank of x4) - page1
- 18 16GB, 2Gx72 Module(2Rank of x4) - page2
- 19 16GB, 2Gx72 Module(2Rank of x4) - page3
- 20 32GB, 4Gx72 Module(4Rank of x4) - page1
- 21 32GB, 4Gx72 Module(4Rank of x4) - page2
- 22 32GB, 4Gx72 Module(4Rank of x4) - page3
- 23 32GB, 4Gx72 Module(4Rank of x4) - page4
- 24 32GB, 4Gx72 Module(4Rank of x4) - page5
- 25 Absolute Maximum Ratings
- 25 Absolute Maximum DC Ratings
- 25 DRAM Component Operating Temperature Range
- 26 AC & DC Operating Conditions
- 26 Recommended DC Operating Conditions
- 27 AC & DC Input Measurement Levels
- 27 AC and DC Input Levels for Single-Ended Command and Address Signals
- 28 AC and DC Input Levels for Single-Ended Signals
- 29 Vref Tolerances
- 30 AC and DC Logic Input Levels for Differential Signals
- 30 Differential signal definition
- 31 Differential swing requirements for clock (CK - CK) and strobe (DQS-DQS)
- 32 Single-ended requirements for differential signals
- 34 Differential Input Cross Point Voltage
- 35 Slew Rate Definitions for Single-Ended Input Signals
- 35 Slew Rate Definitions for Differential Input Signals
- 36 AC & DC Output Measurement Levels
- 36 Single Ended AC and DC Output Levels
- 36 Differential AC and DC Output Levels
- 37 Single Ended Output Slew Rate
- 38 Differential Output Slew Rate
- 39 Reference Load for AC Timing and Output Slew Rate
- 40 Overshoot and Undershoot Specifications
- 40 Address and Control Overshoot and Undershoot Specifications
- 41 Clock, Data, Strobe and Mask Overshoot and Undershoot Specifications
- 42 Refresh parameters by device density
- 43 Standard Speed Bins
- 43 DDR3-800 Speed Bins
- 44 DDR3-1066 Speed Bins
- 45 DDR3-1333 Speed Bins
- 46 DDR3-1600 Speed Bins
- 47 Speed Bin Table Notes
- 48 Environmental Parameters
- 49 IDD and IDDQ Specification Parameters and Test Conditions
- 61 IDD Specifications (Tcase: 0 to 95oC)
- 61 4GB, 512M x 72 R-DIMM: HMT451R7MFR8C
- 61 8GB, 1G x 72 R-DIMM: HMT41GR7MFR4C
- 62 8GB, 1GM x 72 R-DIMM: HMT41GR7MFR8C
- 62 16GB, 2G x 72 R-DIMM: HMT42GR7MFR4C
- 63 32GB, 4G x 72 R-DIMM: HMT84GR7MMR4C
- 64 Module Dimensions
- 64 512Mx72 - HMT451R7MFR8C
- 65 1Gx72 - HMT41GR7MFR4C
- 66 1Gx72 - HMT41GR7MFR8C
- 67 2Gx72 - HMT42GR7MFR4C
- 68 2Gx72 - HMT42GR7MFR4C - Heat Spreader
- 69 4Gx72 - HMT84GR7MMR4C
- 70 4Gx72 - HMT84GR7MMR4C - Heat Spreader