Si4730/31-A10
Si4730/31-A10
B R O A D C A S T AM/FM R A D I O R E C E I V E R
Features
Worldwide FM band support
(76–108 MHz)
Worldwide AM band support
(520–1710 kHz)
Excellent real-world performance
Freq synthesizer with integrated VCO
Advanced AM/FM seek tuning
Automatic frequency control (AFC)
Automatic gain control (AGC)
Integrated LDO regulator
Digital FM stereo decoder
Programmable de-emphasis
Adaptive noise suppression
AM/FM digital tuning
No manual alignment necessary
Programmable reference clock
Volume control
Programmable soft mute control
RDS/RBDS processor (Si4731 only)
2-wire and 3-wire control interface
2.7 to 5.5 V supply voltage
Firmware upgradeable
Wide range of ferrite loop sticks and
air loop antennas supported
3 x 3 x 0.55 mm 20-pin QFN package
Pb-free/RoHS compliant
Ordering Information:
See page 25.
Pin Assignments
Si4730/31-GM
Applications
GPO3
NC
1
GPO2/INT
NC
GPO1
(Top View)
Cellular handsets
Modules
Clock radios
Mini HiFi
Entertainment systems
Car radios
NC
20
19
18
17
16
FMI 2
Description
15 NC
RFGND 3
13 ROUT
6
7
8
9
RCLK
12 GND
SDIO
RST 5
SCLK
Functional Block Diagram
AMI 4
SEN
The Si4730/31 is the first digital CMOS AM/FM radio receiver IC that integrates
the complete tuner function from antenna input to audio output.
14 LOUT
GND
PAD
10
11 VDD
VIO
Table and portable radios
Stereos
Mini/micro systems
CD/DVD players
Portable media players
Boom boxes
Si473x
AMI
LNA
RDS
(Si4731)
AGC
LOW-IF
ADC
LNA
AGC
2.7 - 5.5 V
ADC
VDD
LDO
AFC
RCLK
GND
Rev. 1.0 10/07
DAC
ROUT
DAC
LOUT
DSP
CONTROL
INTERFACE
SEN
FMI
SCLK
FM
ANT
Patents pending
VIO
1.5-3.6V
Notes:
1. To ensure proper operation and
receiver performance, follow the
guidelines in “AN384: Si4730/31
AM/FM Receiver Layout Guide.”
Silicon Laboratories will evaluate
schematics and layouts for qualified
customers.
2. Place Si4730/31 as close as
possible to antenna jack and keep
the FMI and AMI traces as short as
possible.
RST
RFGND
SDIO
AM
ANT
Copyright © 2007 by Silicon Laboratories
Si4730/31-A10
Silicon Laboratories Confidential. Information contained herein is covered under non-disclosure agreement (NDA).
Si4730/31-A10
2
Rev. 1.0
Si4730/31-A10
TA B L E O F C O N T E N TS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.3. FM Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.4. AM receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.5. Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.6. De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.7. Stereo DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.8. Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.9. RDS/RBDS Processor (Si4731 Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.10. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.11. Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.12. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.13. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
4.14. GPO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.15. Firmware Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.16. Reset, Powerup, and Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.17. Programming with Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5. Commands and Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6. Pin Descriptions: Si4730/31-GM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
8. Package Markings (Top Marks) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.1. Si4730/31 Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8.2. Top Mark Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
9. Package Outline: Si4730/31 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
10. PCB Land Pattern: Si4730/31 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
11. Additional Reference Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Rev. 1.0
3
Si4730/31-A10
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Supply Voltage
VDD
2.7
—
5.5
V
Interface Supply Voltage
VIO
1.5
—
3.6
V
Power Supply Power-Up Rise Time
VDDRISE
10
—
—
µs
Interface Power Supply Power-Up Rise Time
VIORISE
10
—
—
µs
TA
–20
25
85
°C
Ambient Temperature
Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at VDD = 3.3 V and 25 °C unless otherwise stated. Parameters are tested in production unless
otherwise stated.
Table 2. Absolute Maximum Ratings1,2
Parameter
Symbol
Value
Unit
Supply Voltage
VDD
–0.5 to 5.8
V
Interface Supply Voltage
VIO
–0.5 to 3.9
V
3
Input Current
IIN
10
mA
Input Voltage3
VIN
–0.3 to (VIO + 0.3)
V
Operating Temperature
TOP
–40 to 95
°C
Storage Temperature
TSTG
–55 to 150
°C
0.4
VpK
RF Input Level
4
Notes:
1. Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functional operation
should be restricted to the conditions as specified in the operational sections of this data sheet. Exposure beyond
recommended operating conditions for extended periods may affect device reliability.
2. The Si4730/31 devices are high-performance RF integrated circuits with certain pins having an ESD rating of < 2 kV
HBM. Handling and assembly of these devices should only be done at ESD-protected workstations.
3. For input pins SCLK, SEN, SDIO, RST, RCLK, GPO1, GPO2, and GPO3.
4. At RF input pins, FMI and AMI.
4
Rev. 1.0
Si4730/31-A10
Table 3. DC Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
—
19.2
22
mA
—
19.8
23
mA
—
19.9
23
mA
—
16.8
20.5
mA
IIO
—
400
820
µA
IDD
—
10
20
µA
—
1
10
µA
FM Mode
Supply Current
Supply Current
IFM
1
IFM
RDS Supply Current
Low SNR level
IFM
AM Mode
Supply Current
IAM
Analog Output Mode
Supplies and Interface
Interface Supply Current
Powerdown Current
2
2
Interface Powerdown Current
IIO
SCLK, RCLK inactive
3
VIH
0.7 x VIO
—
—
V
3
VIL
—
—
0.3 x VIO
V
3
IIH
VIN = VIO = 3.6 V
–10
—
10
µA
3
IIL
VIN = 0 V,
VIO = 3.6 V
–10
—
10
µA
High Level Output Voltage4
VOH
IOUT = 500 µA
0.8 x VIO
—
—
V
4
VOL
IOUT = –500 µA
—
—
0.2 x VIO
V
High Level Input Voltage
Low Level Input Voltage
High Level Input Current
Low Level Input Current
Low Level Output Voltage
Notes:
1. LNA is automatically switched to higher current mode for optimum sensitivity in weak signal conditions.
2. Specifications are guaranteed by characterization.
3. For input pins SCLK, SEN, SDIO, RST, and RCLK.
4. For output pins SDIO, GPO1, GPO2, and GPO3.
Rev. 1.0
5
Si4730/31-A10
Table 4. Reset Timing Characteristics1,2,3
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Min
Typ
Max
Unit
RST Pulse Width and GPO1, GPO2/INT Setup to RST↑4
tSRST
100
—
—
µs
GPO1, GPO2/INT Hold from RST↑
tHRST
30
—
—
ns
Important Notes:
1. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
2. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high until
after the 1st start condition.
3. When selecting 3-wire or SPI modes, the user must ensure that a rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
4. If GPO1 and GPO2 are actively driven by the user, then minimum tSRST is only 30 ns. If GPO1 or GPO2 is hi-Z, then
minimum tSRST is 100 µs, to provide time for on-chip 1 MΩ devices (active while RST is low) to pull GPO1 high and
GPO2 low.
tSRST
RST
tHRST
70%
30%
GPO1
70%
GPO2/
INT
70%
30%
30%
Figure 1. Reset Timing Parameters for Busmode Select
6
Rev. 1.0
Si4730/31-A10
Table 5. 2-Wire Control Interface Characteristics1,2,3
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK Frequency
fSCL
0
—
400
kHz
SCLK Low Time
tLOW
1.3
—
—
µs
SCLK High Time
tHIGH
0.6
—
—
µs
SCLK Input to SDIO ↓ Setup
(START)
tSU:STA
0.6
—
—
µs
SCLK Input to SDIO ↓ Hold
(START)
tHD:STA
0.6
—
—
µs
SDIO Input to SCLK ↑ Setup
tSU:DAT
100
—
—
ns
SDIO Input to SCLK ↓ Hold4,5
tHD:DAT
0
—
900
ns
SCLK input to SDIO ↑ Setup
(STOP)
tSU:STO
0.6
—
—
µs
STOP to START Time
tBUF
1.3
—
—
µs
SDIO Output Fall Time
tf:OUT
20 + 0.1 x Cb
—
250
ns
SDIO Input, SCLK Rise/Fall Time
tf:IN
tr:IN
20 + 0.1 x Cb
—
300
ns
SCLK, SDIO Capacitive Loading
Cb
—
—
50
pF
Input Filter Pulse Suppression
tSP
—
—
50
ns
Notes:
1. When VIO = 0 V, SCLK and SDIO are low impedance.
2. When selecting 2-wire mode, the user must ensure that a 2-wire start condition (falling edge of SDIO while SCLK is
high) does not occur within 300 ns before the rising edge of RST.
3. When selecting 2-wire mode, the user must ensure that SCLK is high during the rising edge of RST, and stays high
until after the 1st start condition.
4. The Si4730/31 delays SDIO by a minimum of 300 ns from the VIH threshold of SCLK to comply with the 0 ns tHD:DAT
specification.
5. The maximum tHD:DAT has only to be met when fSCL = 400 kHz. At frequencies below 400 KHz, tHD:DAT may be
violated so long as all other timing parameters are met.
Rev. 1.0
7
Si4730/31-A10
SCLK
SDIO
tSU:STA tHD:STA
tLOW
START
tr:IN
tHIGH
tr:IN
tf:IN
tSP
tSU:STO
tBUF
70%
30%
70%
30%
tf:IN,
tf:OUT
tHD:DAT tSU:DAT
STOP
START
Figure 2. 2-Wire Control Interface Read and Write Timing Parameters
SCLK
A6-A0,
R/W
SDIO
START
ADDRESS + R/W
D7-D0
ACK
DATA
D7-D0
ACK
DATA
ACK
Figure 3. 2-Wire Control Interface Read and Write Timing Diagram
8
Rev. 1.0
STOP
Si4730/31-A10
Table 6. 3-Wire Control Interface Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK Frequency
fCLK
—
—
2.5
MHz
SCLK High Time
tHIGH
25
—
—
ns
SCLK Low Time
tLOW
25
—
—
ns
tS
20
—
—
ns
SDIO Input to SCLK↑ Hold
tHSDIO
10
—
—
ns
SEN Input to SCLK↓ Hold
tHSEN
10
—
—
ns
SCLK↑ to SDIO Output Valid
tCDV
Read
2
—
25
ns
SCLK↑ to SDIO Output High Z
tCDZ
Read
2
—
25
ns
SCLK, SEN, SDIO, Rise/Fall time
tR, tF
—
—
10
ns
SDIO Input, SEN to SCLK↑ Setup
Note: When selecting 3-wire mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
SCLK
70%
30%
tS
SEN
SDIO
tR
tF
70%
tHSDIO
tHIGH
tLOW
tHSEN
tS
30%
70%
30%
A7
A6-A5,
R/W,
A4-A1
A0
D15
D14-D1
Address In
D0
Data In
Figure 4. 3-Wire Control Interface Write Timing Parameters
SCLK
70%
30%
tHSDIO
tS
SEN
70%
tCDV
tHSEN
tCDZ
tS
30%
70%
SDIO
A7
30%
A6-A5,
R/W,
A4-A1
Address In
A0
D15
½ Cycle Bus
Turnaround
D14-D1
D0
Data Out
Figure 5. 3-Wire Control Interface Read Timing Parameters
Rev. 1.0
9
Si4730/31-A10
Table 7. SPI Control Interface Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
SCLK Frequency
fCLK
0
—
2.5
MHz
SCLK High Time
tHIGH
25
—
—
ns
SCLK Low Time
tLOW
25
—
—
ns
tS
15
—
—
ns
SDIO Input to SCLK↑ Hold
tHSDIO
10
—
—
ns
SEN Input to SCLK↓ Hold
tHSEN
5
—
—
ns
SCLK↓ to SDIO Output Valid
tCDV
Read
2
—
25
ns
SCLK↓ to SDIO Output High Z
tCDZ
Read
2
—
25
ns
SCLK, SEN, SDIO, Rise/Fall time
tR, tF
—
—
10
ns
SDIO Input, SEN to SCLK↑ Setup
Note: When selecting SPI mode, the user must ensure that a rising edge of SCLK does not occur within 300 ns before the
rising edge of RST.
SCLK
70%
30%
tHIGH
SEN
SDIO
tLOW
tHSDIO
tR
tF
tHSEN
70%
30%
70%
30%
tS
tS
C7
C6–C1
C0
D7
Control Byte In
D6–D1
D0
8 Data Bytes In
Figure 6. SPI Control Interface Write Timing Parameters
SCLK
70%
30%
tCDV
tS
SEN
70%
tHSEN
tHSDIO
tS
30%
tCDZ
SDIO
70%
C7
C6–C1
C0
D7
D6–D1
D0
30%
Control Byte In
Bus
Turnaround
16 Data Bytes Out
(SDIO or GPO1)
Figure 7. SPI Control Interface Read Timing Parameters
10
Rev. 1.0
Si4730/31-A10
Table 8. FM Receiver Characteristics1,2
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Symbol
Parameter
Input Frequency
Test Condition
fRF
Min
Typ
Max
Unit
76
—
108
MHz
Sensitivity with Headphone
Network3,4,5
(S+N)/N = 26 dB
—
2.2
3.5
µV EMF
Sensitivity with 50 Ω Network3,4,5,7
(S+N)/N = 26 dB
—
1.1
—
µV EMF
Δf = 2 kHz,
RDS BLER < 5%
—
15
—
µV EMF
LNA Input Resistance6,7
3
4
5
kΩ
LNA Input Capacitance6,7
4
5
6
pF
100
105
—
dBµV
EMF
m = 0.3
40
50
—
dB
±200 kHz
35
50
—
dB
±400 kHz
60
70
—
dB
In-band
35
—
—
dB
72
80
90
mVRMS
—
—
1
dB
30
—
15k
Hz
25
—
—
dB
56
63
—
dB
Audio Stereo S/N5
—
58
—
dB
Audio THD3,6,9
—
0.1
0.5
%
FM_DEEMPHASIS = 2
70
75
80
µs
FM_DEEMPHASIS = 1
45
50
54
µs
0.7
0.8
0.9
V
RDS Sensitivity
7
Input IP37,8
AM Suppression3,4,6,7
Adjacent Channel Selectivity
Alternate Channel Selectivity
Spurious Response Rejection
Audio Output
7
Voltage3,4,6
Audio Output L/R Imbalance3,6,9
Audio Band Limits3,6,7
Audio Stereo
±1.5 dB
Separation6,9
Audio Mono S/N
3,4,5,6
De-emphasis Time Constant7
Audio Common Mode Voltage10
Audio Output Load Resistance7,10
Audio Output Load Capacitance
7,10
RL
Single-ended
10
—
—
kΩ
CL
Single-ended
—
—
50
pF
Notes:
1. Additional testing information is available in Application Note AN234. Volume = maximum for all tests. Tested at
Rf = 100 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN384: Si4730/31 AM/FM Receiver
Layout Guide.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
4. Δf = 22.5 kHz.
5. BAF = 300 Hz to 15 kHz, A-weighted.
6. VEMF = 1 mV.
7. Guaranteed by characterization.
8. |f2 – f1| > 2 MHz, f0 = 2 x f1 – f2. AGC is disabled. Refer to "6. Pin Descriptions: Si4730/31-GM" on page 24.
9. Δf = 75 kHz.
10. At LOUT and ROUT pins.
Rev. 1.0
11
Si4730/31-A10
Table 8. FM Receiver Characteristics1,2 (Continued)
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
—
—
80
ms/channel
From powerdown
—
—
110
ms
Input levels of 8 and
60 dBµV EMF
–3
—
3
dB
Seek/Tune Time7
Powerup Time7
RSSI Offset
Notes:
1. Additional testing information is available in Application Note AN234. Volume = maximum for all tests. Tested at
Rf = 100 MHz.
2. To ensure proper operation and receiver performance, follow the guidelines in “AN384: Si4730/31 AM/FM Receiver
Layout Guide.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
3. FMOD = 1 kHz, 75 µs de-emphasis, MONO = enabled, and L = R unless noted otherwise.
4. Δf = 22.5 kHz.
5. BAF = 300 Hz to 15 kHz, A-weighted.
6. VEMF = 1 mV.
7. Guaranteed by characterization.
8. |f2 – f1| > 2 MHz, f0 = 2 x f1 – f2. AGC is disabled. Refer to "6. Pin Descriptions: Si4730/31-GM" on page 24.
9. Δf = 75 kHz.
10. At LOUT and ROUT pins.
Table 9. AM Receiver Characteristics1
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Input Frequency
Sensitivity2,3
Large Signal Voltage Handling4
Power Supply Rejection Ratio
Symbol
Test Condition
Min
Typ
Max
Unit
520
—
1710
kHz
(S+N)/N = 26 dB
—
38
—
µV EMF
THD < 8%
—
300
—
mVRMS
ΔVDD = 100 mVRMS, 100 Hz
—
40
—
dB
54
60
67
mVRMS
48
56
—
dB
—
0.1
0.5
%
180
—
600
µH
—
—
110
ms
fRF
Audio Output Voltage2,5
Audio
S/N2,3,5
Audio THD2,3,5
Antenna
Inductance4
Powerup Time
From powerdown
Notes:
1. To ensure proper operation and receiver performance, follow the guidelines in “AN384: Si4730/31 AM/FM Receiver
Layout Guide.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
2. FMOD = 1 kHz, 30% modulation, A-weighted, 2 kHz channel filter.
3. fRF = 1000 kHz, Δf = 10 kHz.
4. Guaranteed by characterization.
5. VIN = 5 mVrms.
12
Rev. 1.0
Si4730/31-A10
Table 10. Reference Clock and Crystal Characteristics
(VDD = 2.7 to 5.5 V, VIO = 1.5 to 3.6 V, TA = –20 to 85 °C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
31.130
32.768
40,000
kHz
–100
—
100
ppm
1
—
4095
31.130
32.768
34.406
kHz
—
32.768
—
kHz
–100
—
100
ppm
—
—
3.5
pF
Reference Clock
RCLK Supported Frequencie1
RCLK Frequency Tolerance
2
REFCLK_PRESCALE
REFCLK
Crystal Oscillator
Crystal Oscillator Frequency
Crystal Frequency Tolerance2
Board Capacitance
Notes:
1. The Si4730/31 divides the RCLK input by REFCLK_PRESCALE to obtain REFCLK. There are some RCLK
frequencies between 31.130 kHz and 40 MHz that are not supported. See AN385, Table 6 for more details.
2. A frequency tolerance of ±50 ppm is required for FM seek/tune using 50 kHz channel spacing.
Rev. 1.0
13
Si4730/31-A10
2. Typical Application Schematic
GPO1
NC
GPO1
GPO2
GPO3
NC
20
19
18
17
16
GPO2/INT
GPO3
1
NC
2
FMI
3
RFGND
FMIP
L1
AM antenna
C5
4
AMI
5
RST
U1
Si4730/31-GM
NC
LOUT
ROUT
GND
VDD
15
14
13
12
11
LOUT
ROUT
VBATTERY
2.7 to 5.5 V
RST
6
7
8
9
10
SEN
SCLK
SDIO
RCLK
VIO
C1
X1
GPO3
SEN
SCLK
C2
SDIO
RCLK
VIO
1.5 to 3.6 V
RCLK
C3
Optional: for crystal oscillator option
L2
RFGND
AMI
T1
C5
Optional: AM air loop antenna
Notes:
1. Place C1 close to VDD pin.
2. All grounds connect directly to GND plane on PCB.
3. Pins 1 and 20 are no connects, leave floating.
4. To ensure proper operation and receiver performance, follow the guidelines in “AN384: Si4730/31 AM/FM Receiver
Layout Guide.” Silicon Laboratories will evaluate schematics and layouts for qualified customers.
5. Pin 2 connects to the FM antenna interface, and pin 4 connects to the AM antenna interface.
6. RFGND should be locally isolated from GND.
7. Place Si4730/31 as close as possible to antenna jack and keep the FMI and AMI traces as short as possible.
14
Rev. 1.0
Si4730/31-A10
3. Bill of Materials
Component(s)
Value/Description
Supplier
C1
Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R
Murata
C5
Coupling capacitor, 0.47 µF, ±20%, Z5U/X7R
Murata
L1
Ferrite loop stick, 180–600 µH
Various
U1
Si4730/31 AM/FM Radio Tuner
Silicon Laboratories
Optional Components
T1
Transformer, 1–5 turns ratio
Various
L2
Air loop antenna, 10–20 µH
Various
Crystal load capacitors, 22 pF, ±5%, COG
(Optional: for crystal oscillator option)
Venkel
32.768 kHz crystal (Optional: for crystal oscillator option)
Epson
C2, C3
X1
Rev. 1.0
15
Si4730/31-A10
4. Functional Description
4.1. Overview
Si473x
AMI
LNA
RDS
(Si4731)
AGC
LOW-IF
ADC
LNA
ADC
VDD
LDO
AFC
RCLK
GND
ROUT
DAC
LOUT
DSP
AGC
2.7 - 5.5 V
DAC
CONTROL
INTERFACE
VIO
1.5-3.6V
RST
FMI
SCLK
FM
ANT
SDIO
RFGND
SEN
AM
ANT
Figure 8. Functional Block Diagram
The Si4730/31 is the industry's first fully integrated,
100% CMOS AM/FM radio receiver IC. Offering
unmatched integration and PCB space savings, the
Si4730/31 requires only two external components and
less than 15 mm2 of board area, excluding the antenna
inputs. The Si4730/31 AM/FM radio provides the space
savings and low power consumption necessary for
portable devices while delivering the high performance
and design simplicity desired for all AM/FM solutions.
Leveraging Silicon Laboratories' proven and patented
Si4700/01 FM tuner's digital low intermediate frequency
(low-IF) receiver architecture, the Si4730/31 delivers
superior RF performance and interference rejection in
both AM and FM bands. The high integration and
complete system production test simplifies design-in,
increases
system
quality,
and
improves
manufacturability.
The Si4730/31 is a feature-rich solution including
advanced seek algorithms, soft mute, auto-calibrated
digital tuning, and FM stereo processing. In addition, the
Si4730/31 provides a programmable reference clock.
The device supports I2C-compatible 2-wire control
interface, SPI, and a Si4700/01 backwards-compatible
3-wire control interface.
16
The Si4730/31 utilizes digital processing to achieve high
fidelity, optimal performance, and design flexibility. The
chip provides excellent pilot rejection, selectivity, and
unmatched audio performance, and offers both the
manufacturer
and
the
end-user
extensive
programmability and flexibility in listening experience.
The Si4731 incorporates a digital processor for the
European Radio Data System (RDS) and the North
American Radio Broadcast Data System (RBDS)
including all required symbol decoding, block
synchronization, error detection, and error correction
functions. Using this feature, the Si4731 enables
broadcast data such as station identification and song
name to be displayed to the user.
4.2. Operating Modes
The Si4730/31 operates in either an FM receive or an
AM receive mode. In FM mode, radio signals are
received on FMI (pin 2) and processed by the FM frontend circuitry. In AM mode, radio signals are received on
AMI (pin 4) and processed by the AM front-end circuitry.
In addition to the receiver mode, there is a clocking
mode to choose to clock the Si4730/31 from a reference
clock or crystal. The receiver mode and the clocking
mode are set by the POWER_UP command listed in
Table 12. Si473x Command Summary.
Rev. 1.0
Si4730/31-A10
The Si4730/31 FM receiver is based on the proven
Si4700/01 FM tuner. The receiver uses a digital low-IF
architecture allowing the elimination of external
components and factory adjustments. The Si4730/31
integrates a low noise amplifier (LNA) supporting the
worldwide FM broadcast band (76 to 108 MHz). An
automatic gain control (AGC) circuit controls the gain of
the LNA to optimize sensitivity and rejection of strong
interferers. For testing purposes, the AGC can be
disabled. Refer to Section "5. Commands and
Properties" on page 21 for additional programming and
configuration information. An image-reject mixer
downconverts the RF signal to low-IF. The quadrature
mixer output is amplified, filtered, and digitized with high
resolution analog-to-digital converters (ADCs). This
advanced architecture allows the Si4730/31 to perform
channel selection, FM demodulation, and stereo audio
processing to achieve superior performance compared
to traditional analog architectures.
4.4. AM receiver
The highly integrated Si4730/31 supports worldwide AM
band reception from 520 to 1710 kHz using a digital lowIF architecture with a minimum number of external
components and no manual alignment required. This
digital low-IF architecture allows for high-precision
filtering offering excellent selectivity and noise
suppression. The DSP also provides 9 or 10 kHz
channel selection, AM demodulation, soft mute, and
additional features such as adjustable channel
bandwidth settings. Similar to the FM receiver, the
integrated LNA and AGC optimize sensitivity and
rejection of strong interferers allowing better reception
of weak stations.
The Si4730/31 provides highly accurate digital AM
tuning without factory adjustments. To offer maximum
flexibility, the receiver supports a wide range of ferrite
loop sticks from 180–600 µH. An air loop antenna is
supported by using a transformer to increase the
effective inductance from the air loop. Using a 1:5 turn
ratio inductor the inductance is increased by 25x easily
supporting all typical AM air loop antennas which
generally vary between 10 and 20 µH.
4.5. Stereo Audio Processing
The output of the FM demodulator is a stereo
multiplexed (MPX) signal. The MPX standard was
developed in 1961, and is used worldwide. Today's
MPX signal format consists of left + right (L+R) audio,
left – right (L–R) audio, a 19 kHz pilot tone, and
RDS/RBDS data as shown in Figure 9 below.
Modulation Level
4.3. FM Receiver
Mono Audio
Left + Right
0
Stereo
Pilot
15 19 23
Stereo Audio
Left - Right
38
RDS/
RBDS
53
57
Frequency (kHz)
Figure 9. MPX Signal Spectrum
4.5.1. Stereo Decoder
The
Si4730/31's
integrated
stereo
decoder
automatically decodes the MPX signal using DSP
techniques. The 0 to 15 kHz (L+R) signal is the mono
output of the FM tuner. Stereo is generated from the
(L+R), (L–R), and a 19 kHz pilot tone. The pilot tone is
used as a reference to recover the (L–R) signal. Output
left and right channels are obtained by adding and
subtracting the (L+R) and (L–R) signals respectively.
The Si4731 uses frequency information from the 19 kHz
stereo pilot to recover the 57 kHz RDS/RBDS signal.
4.5.2. Stereo-Mono Blending
Adaptive noise suppression is employed to gradually
combine the stereo left and right audio channels to a
mono (L+R) audio signal as the signal quality degrades
to maintain optimum sound fidelity under varying
reception conditions. Stereo/mono status can be
monitored with the FM_RSQ_STATUS command. Mono
operation
can
be
forced
with
the
FM_BLEND_MONO_THRESHOLD property.
4.6. De-emphasis
Pre-emphasis and de-emphasis is a technique used by
FM broadcasters to improve the signal-to-noise ratio of
FM receivers by reducing the effects of high-frequency
interference and noise. When the FM signal is
transmitted, a pre-emphasis filter is applied to
accentuate the high audio frequencies. The Si4730/31
incorporates a de-emphasis filter which attenuates high
frequencies to restore a flat frequency response. Two
time constants are used in various regions. The deemphasis time constant is programmable to 50 or 75 µs
and is set by the FM_DEEMPHASIS property.
4.7. Stereo DAC
High-fidelity stereo digital-to-analog converters (DACs)
drive analog audio signals onto the LOUT and ROUT
pins. The audio output may be muted. Volume is
adjusted digitally with the RX_VOLUME property.
Rev. 1.0
17
Si4730/31-A10
4.8. Soft Mute
The soft mute feature is available to attenuate the audio
outputs and minimize audible noise in very weak signal
conditions. The softmute attenuation level is adjustable
using the FM_SOFT_MUTE_MAX_ATTENUATION and
AM_SOFT_MUTE_MAX_ATTENUATION properties.
4.9. RDS/RBDS Processor (Si4731 Only)
The Si4731 implements an RDS/RBDS* processor for
symbol decoding, block synchronization, error
detection, and error correction.
The Si4731 device is user configurable and provides an
optional interrupt when RDS is synchronized, loses
synchronization, and/or the user configurable RDS
FIFO threshold has been met.
The Si4731 reports RDS decoder synchronization
status, and detailed bit errors in the information word for
each RDS block with the FM_RDS_STATUS command.
The range of reportable block errors is 0, 1–2, 3–5, or
6+. More than six errors indicates that the
corresponding block information word contains six or
more non-correctable errors, or that the block
checkword contains errors.
*Note: RDS/RBDS is referred to only as RDS throughout the
remainder of this document.
4.10. Tuning
The frequency synthesizer uses Silicon Laboratories’
proven technology, including a completely integrated
VCO. The frequency synthesizer generates the
quadrature local oscillator signal used to downconvert
the RF input to a low intermediate frequency. The VCO
frequency is locked to the reference clock and adjusted
with an automatic frequency control (AFC) servo loop
during reception. The tuning frequency can be directly
programmed using the FM_TUNE_FREQ and
AM_TUNE_FREQ commands. The Si4730/31 supports
channel spacing of 50, 100, or 200 kHz in FM mode and
9 or 10 kHz in AM mode.
4.11. Seek
Seek tuning will search up or down for a valid channel.
Valid channels are found when the receive signal
strength indicator (RSSI) and the signal-to-noise ratio
(SNR) values exceed the set threshold. Using the SNR
qualifier rather than solely relying on the more
traditional RSSI qualifier can reduce false stops and
increase the number of valid stations detected. Seek is
initiated
using
the
FM_SEEK_START
and
AM_SEEK_START commands. The RSSI and SNR
threshold settings are adjustable using properties (see
Table 13).
18
Two seek options are available. The device will either
wrap or stop at the band limits. If the seek operation is
unable to find a channel, the device will indicate failure
and return to the channel selected before the seek
operation began.
4.12. Reference Clock
The Si4730/31 reference clock is programmable,
supporting RCLK frequencies in Table 10. Refer to
Table 3, “DC Characteristics,” on page 5 for switching
voltage
levels
and
Table 8,
“FM
Receiver
Characteristics” on page 11 for frequency tolerance
information.
An onboard crystal oscillator is available to generate the
32.768 kHz reference when an external crystal and load
capacitors are provided. Refer to "2. Typical Application
Schematic" on page 14. This mode is enabled using the
POWER_UP command, see Table 12, “Si473x
Command Summary,” on page 21.
The Si4730/31 performance may be affected by data
activity on the SDIO bus when using the integrated
internal oscillator. SDIO activity results from polling the
tuner for status or communicating with other devices
that share the SDIO bus. If there is SDIO bus activity
while the Si4730/31 is performing the seek/tune
function, the crystal oscillator may experience jitter,
which may result in mistunes, false stops, and/or lower
SNR.
For best seek/tune results, Silicon Laboratories
recommends that all SDIO data traffic be suspended
during Si4730/31 seek and tune operations. This is
achieved by keeping the bus quiet for all other devices
on the bus, and delaying tuner polling until the tune or
seek operation is complete. The STC (seek/tune
complete) interrupt should be used instead of polling to
determine when a seek/tune operation is complete.
4.13. Control Interface
A serial port slave interface is provided, which allows an
external controller to send commands to the Si4730/31,
and receive responses from the device. The serial port
can operate in three bus modes: 2-wire mode, 3-wire
mode, or SPI mode. The Si4730/31 selects the bus
mode by sampling the state of the GPO1 and GPO2
pins on the rising edge of RST. The GPO1 pin includes
an internal pull-up resistor which is connected while
RST is low, and the GPO2 pin includes an internal pulldown resistor which is connected while RST is low.
Therefore, it is only necessary for the user to actively
drive pins which differ from these states. See Table 11.
Rev. 1.0
Si4730/31-A10
Table 11. Bus Mode Select on Rising Edge of
RST
Bus Mode
GPO1
GPO2
2-Wire
1
0
SPI
1
1 (must drive)
3-Wire
0 (must drive)
0
After the rising edge of RST, the pins GPO1 and GPO2
are used as general purpose output (O) pins as
described in Section “4.14. GPO Outputs”. In any bus
mode, commands may only be sent after VIO and VDD
supplies are applied.
In any bus mode, before sending a command or reading
a response, the user must first read the status byte to
ensure that the device is ready (CTS bit is high).
4.13.1. 2-Wire Control Interface Mode
When selecting 2-wire mode, the user must ensure that
SCLK is high during the rising edge of RST, and stays
high until after the first start condition. Also, a start
condition must not occur within 300 ns before the rising
edge of RST.
2-wire bus mode uses only the SCLK and SDIO pins for
signaling. A transaction begins with the START
condition, which occurs when SDIO falls while SCLK is
high. Next, the user drives an 8-bit control word serially
on SDIO, which is captured by the device on rising
edges of SCLK. The control word consists of a seven bit
device address, followed by a read/write bit (read = 1,
write = 0). The Si4730/31 acknowledges the control
word by driving SDIO low on the next falling edge of
SCLK.
Although the Si4730/31 will respond to only a single
device address, this address can be changed with the
SEN pin (note that the SEN pin is not used for signaling
in 2-wire mode). When SEN = 0, the seven-bit device
address is 0010001b. When SEN = 1, the address is
1100011b.
For write operations, the user then sends an eight bit
data byte on SDIO, which is captured by the device on
rising edges of SCLK. The Si4730/31 acknowledges
each data byte by driving SDIO low for one cycle, on the
next falling edge of SCLK. The user may write up to 8
data bytes in a single 2-wire transaction. The first byte is
a command, and the next seven bytes are arguments.
For read operations, after the Si4730/31 has
acknowledged the control byte, it will drive an eight bit
data byte on SDIO, changing the state of SDIO on the
falling edge of SCLK. The user acknowledges each data
byte by driving SDIO low for one cycle, on the next
falling edge of SCLK. If a data byte is not
acknowledged, the transaction will end. The user may
read up to 16 data bytes in a single 2-wire transaction.
These bytes contain the response data from the
Si4730/31.
A 2-wire transaction ends with the STOP condition,
which occurs when SDIO rises while SCLK is high.
For details on timing specifications and diagrams, refer
to Table 5, “2-Wire Control Interface Characteristics” on
page 7, Figure 2, “2-Wire Control Interface Read and
Write Timing Parameters,” on page 8 and Figure 3, “2Wire Control Interface Read and Write Timing Diagram,”
on page 8.
4.13.2. 3-Wire Control Interface Mode
When selecting 3-wire mode, the user must ensure that
a rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
3-wire bus mode uses the SCLK, SDIO and SEN_ pins.
A transaction begins when the user drives SEN low.
Next, the user drives a 9-bit control word on SDIO,
which is captured by the device on rising edges of
SCLK. The control word consists of a three-bit device
address (A7:A5 = 101b), a read/write bit (read = 1, write
= 0), and a five-bit register address (A4:A0).
For write operations, the control word is followed by a
16-bit data word, which is captured by the device on
rising edges of SCLK.
For read operations, the control word is followed by a
delay of one-half SCLK cycle for bus turn-around. Next,
the Si4730/31 will drive the 16-bit read data word
serially on SDIO, changing the state of SDIO on each
rising edge of SCLK.
A transaction ends when the user sets SEN high, then
pulses SCLK high and low one final time. SCLK may
either stop or continue to toggle while SEN is high.
In 3-wire mode, commands are sent by first writing each
argument to register(s) 0xA1–0xA3, then writing the
command word to register 0xA0. A response is
retrieved by reading registers 0xA8–0xAF.
For details on timing specifications and diagrams, refer
to Table 6, “3-Wire Control Interface Characteristics,” on
page 9, Figure 4, “3-Wire Control Interface Write Timing
Parameters,” on page 9, and Figure 5, “3-Wire Control
Interface Read Timing Parameters,” on page 9.
4.13.3. SPI Control Interface Mode
When selecting SPI mode, the user must ensure that a
rising edge of SCLK does not occur within 300 ns
before the rising edge of RST.
SPI bus mode uses the SCLK, SDIO and SEN pins for
read/write operations. The system controller can
choose to receive read data from the device on either
Rev. 1.0
19
Si4730/31-A10
SDIO or GPO1. A transaction begins when the system
controller drives SEN = 0. The system controller then
pulses SCLK eight times, while driving an 8-bit control
byte serially on SDIO. The device captures the data on
rising edges of SCLK. The control byte must have one
of five values:
0x48 = write a command (controller drives 8
additional bytes on SDIO).
0x80 = read a response (device drives one
additional byte on SDIO).
0xC0 = read a response (device drives 16 additional
bytes on SDIO).
0xA0 = read a response (device drives one
additional byte on GPO1).
0xE0 = read a response device drives 16 additional
bytes on GPO1).
For write operations, the system controller must drive
exactly 8 data bytes (a command and seven arguments)
on SDIO after the control byte. The data is captured by
the device on the rising edge of SCLK.
For read operations, the controller must read exactly
one byte (STATUS) after the control byte or exactly 16
data bytes (STATUS and RESP1–RESP15) after the
control byte. The device changes the state of SDIO (or
GPO1, if specified) on the falling edge of SCLK. Data
must be captured by the system controller on the rising
edge of SCLK.
Keep SEN low until all bytes have transferred. A
transaction may be aborted at any time by setting SEN
high and toggling SCLK high and then low. Commands
will be ignored by the device if the transaction is
aborted.
For details on timing specifications and diagrams, refer
to Figure 6 and Figure 7 on page 10.
4.14. GPO Outputs
GPO2 can be configured to provide interrupts for seek
and tune complete, receive signal quality, and RDS.
GPO1 and GPO3 are not available on Si4730-A10 and
Si4731-A10.
20
4.15. Firmware Upgrades
The Si4730/31 contains on-chip program RAM to
accommodate minor changes to the firmware. This
allows Silicon Labs to provide future firmware updates
to optimize the characteristics of new radio designs and
those already deployed in the field.
4.16. Reset, Powerup, and Powerdown
Setting the RST pin low will disable analog and digital
circuitry, reset the registers to their default settings, and
disable the bus. Setting the RST pin high will bring the
device out of reset.
A powerdown mode is available to reduce power
consumption when the part is idle. Putting the device in
powerdown mode will disable analog and digital circuitry
while keeping the bus active.
4.17. Programming with Commands
To ease development time and offer maximum
customization, the Si4730/31 provides a simple yet
powerful software interface to program the receiver. The
device is programmed using commands, arguments,
properties and responses.
To perform an action, the user writes a command byte
and associated arguments causing the chip to execute
the given command. Commands control an action such
as power up the device, shut down the device, or tune
to a station. Arguments are specific to a given command
and are used to modify the command. A complete list of
commands is available in Table 12, “Si473x Command
Summary,” on page 21.
Properties are a special command argument used to
modify the default chip operation and are generally
configured immediately after power-up. Examples of
properties are de-emphasis level, RSSI seek threshold,
and soft mute attenuation threshold. A complete list of
properties is available in Table 13, “Si473x Property
Summary,” on page 21.
Responses provide the user information and are
echoed after a command and associated arguments are
issued. All commands provide a one-byte status update
indicating interrupt and clear-to-send status information.
For a detailed description of the commands and
properties for the Si4730/31, see “AN385: Si4730/31
AM/FM Receiver Programming Guide.”
Rev. 1.0
Si4730/31-A10
5. Commands and Properties
Table 12. Si473x Command Summary
Cmd
Name
0x01
POWER_UP
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x20
0x21
GET_REV
POWER_DOWN
SET_PROPERTY
GET_PROPERTY
GET_INT_STATUS
PATCH_ARGS
PATCH_DATA
FM_TUNE_FREQ
FM_SEEK_START
0x22
FM_TUNE_STATUS
0x23
FM_RSQ_STATUS
0x24
FM_RDS_STATUS
0x40
0x41
AM_TUNE_FREQ
AM_SEEK_START
0x42
AM_TUNE_STATUS
0x43
AM_RSQ_STATUS
Description
Power up device and mode selection. Modes include AM or FM receive and
reference clock or crystal support.
Returns revision information on the device.
Power down device.
Sets the value of a property.
Retrieves a property’s value.
Read interrupt status bits.
Reserved command used for firmware file downloads.
Reserved command used for firmware file downloads.
Selects the FM tuning frequency.
Begins searching for a valid frequency
Queries the status of previous FM_TUNE_FREQ or FM_SEEK_START
command.
Queries the status of the Received Signal Quality (RSQ) of the current
channel.
Returns RDS information for current channel and reads an entry from the
RDS FIFO (Si4731 only).
Tunes to a given AM frequency.
Begins searching for a valid frequency.
Queries the status of the already issued AM_TUNE_FREQ or
AM_SEEK_START command.
Queries the status of the Received Signal Quality (RSQ) for the current
channel.
Table 13. Si473x Property Summary
Prop
Name
0x0001
GPO_IEN
0x0201
REFCLK_FREQ
0x0202
0x1100
REFCLK_PRESCALE
FM_DEEMPHASIS
0x1105
FM_BLEND_STEREO_
THRESHOLD
0x1106
FM_BLEND_MONO_
THRESHOLD
0x1108
0x1200
FM_MAX_TUNE_
ERROR
FM_RSQ_INT_
SOURCE
Description
Default
Enables interrupt sources.
0x0000
Sets frequency of reference clock in Hz. The range is 31130 to
0x8000
34406 Hz, or 0 to disable the AFC. Default is 32768 Hz.
Sets the prescaler value for RCLK input.
0x0001
Sets deemphasis time constant. Default is 75 us.
0x0002
Sets RSSI threshold for stereo blend (Full stereo above threshold, blend below threshold). To force stereo set this to 0. To
0x0031
force mono set this to 127. Default value is 49 dBuV.
Sets RSSI threshold for mono blend (Full mono below threshold, blend above threshold). To force stereo set this to 0. To
0x001E
force mono set this to 127. Default value is 30 dBuV.
Sets the maximum freq error allowed before setting the AFC rail
0x001E
(AFCRL) indicator. Default value is 30 kHz.
Configures interrupt related to Received Signal Quality metrics.
Rev. 1.0
0x0000
21
Si4730/31-A10
Table 13. Si473x Property Summary (Continued)
Prop
0x1201
0x1202
0x1203
0x1204
0x1207
0x1300
Name
FM_RSQ_SNR_HI_
THRESHOLD
FM_RSQ_SNR_LO_
THRESHOLD
FM_RSQ_RSSI_HI_
THRESHOLD
FM_RSQ_RSSI_LO_
THRESHOLD
FM_RSQ_BLEND_
THRESHOLD
FM_SOFT_MUTE_RATE
0x1500
FM_SOFT_MUTE_
MAX_ATTENUATION
FM_SOFT_MUTE_
SNR_THRESHOLD
FM_SEEK_BAND_
BOTTOM
FM_SEEK_BAND_TOP
FM_SEEK_FREQ_
SPACING
FM_SEEK_TUNE_
SNR_THRESHOLD
FM_SEEK_TUNE_
RSSI_TRESHOLD
RDS_INT_SOURCE
0x1501
RDS_INT_FIFO_COUNT
0x1502
RDS_CONFIG
0x3100
AM_DEEMPHASIS
0x3102
AM_CHANNEL_FILTER
0x3200
AM_RSQ_INTERRUPTS
0x1302
0x1303
0x1400
0x1401
0x1402
0x1403
0x1404
0x3201
0x3202
0x3203
0x3204
AM_RSQ_SNR_HIGH_
THRESHOLD
AM_RSQ_SNR_LOW_
THRESHOLD
AM_RSQ_RSSI_HIGH_
THRESHOLD
AM_RSQ_RSSI_LOW_
THRESHOLD
0x3300
AM_SOFT_MUTE_RATE
0x3301
AM_SOFT_MUTE_SLOPE
22
Description
Default
Sets high threshold for SNR interrupt.
0x007F
Sets low threshold for SNR interrupt.
0x0000
Sets high threshold for RSSI interrupt.
0x007F
Sets low threshold for RSSI interrupt.
0x0000
Sets the blend threshold for blend interrupt when boundary is
0x0081
crossed.
Sets the attack and decay rates when entering and leaving soft
0x0040
mute.
Sets maximum attenuation during soft mute (dB). Set to 0 to dis0x0010
able soft mute. Default is 16 dB.
Sets SNR threshold to engage soft mute. Default is 4 dB.
0x0004
Sets the bottom of the FM band for seek. Default is 8750.
0x222E
Sets the top of the FM band for seek. Default is 10790.
0x2A26
Selects frequency spacing for FM seek.
0x000A
Sets the SNR threshold for a valid FM Seek/Tune. Default value
is 3 dB.
Sets the RSSI threshold for a valid FM Seek/Tune. Default
value is 20 dBuV.
Configures RDS interrupt behavior.
Sets the minimum number of RDS groups stored in the receive
RDS FIFO required before RDS RECV is set.
Configures RDS setting.
Sets deemphasis time constant. Can be set to 50 us. Deemphasis is disabled by default.
Selects the bandwidth of the channel filter for AM reception. The
choices are 6, 4, 3, or 2 (kHz). The default bandwidth is 2 kHz.
Configures interrupt related to Received Signal Quality metrics.
All interrupts are disabled by default.
0x0003
0x0014
0x0000
0x0000
0x0000
0x0000
0x0003
0x0000
Sets high threshold for SNR interrupt. The default is 0 dB.
0x0000
Sets low threshold for SNR interrupt. The default is 0 dB.
0x0000
Sets high threshold for RSSI interrupt. The default is 0 dB.
0x0000
Sets low threshold for RSSI interrupt. The default is 0 dB.
0x0000
Sets the rate of attack when entering or leaving soft mute. The
default is 278 dB/s.
Sets the AM soft mute slope. The bigger the number, the higher
the max attenuation level. Default value is a slope of 2.
Rev. 1.0
0x0040
0x0002
Si4730/31-A10
Table 13. Si473x Property Summary (Continued)
Prop
0x3302
0x3303
0x3400
Name
AM_SOFT_MUTE_MAX_
ATTENUATION
AM_SOFT_MUTE_SNR_
THRESHOLD
AM_SEEK_BAND_
BOTTOM
0x3401
AM_SEEK_BAND_TOP
0x3402
AM_SEEK_FREQ_
SPACING
0x3403
AM_SEEK_SNR_
THRESHOLD
0x3404
AM_SEEK_RSSI_
THRESHOLD
0x4000
RX_VOLUME
0x4001
RX_HARD_MUTE
Description
Default
Sets maximum attenuation during soft mute (dB). Set to 0 to dis0x0010
able soft mute. Default is 16 dB.
Sets SNR threshold to engage soft mute. Default is 10 dB.
0x000A
Sets the bottom of the AM band for seek. Default is 520.
0x0208
Sets the top of the AM band for seek. Firmware 1.0 incorrectly
defaults to 1721 kHz instead of 1710.
Selects frequency spacing for AM seek. Default is 10 kHz spacing.
Sets the SNR threshold for a valid AM Seek/Tune. If the value is
zero then SNR threshold is not considered when doing a seek.
Default value is 5 dB.
Sets the RSSI threshold for a valid AM Seek/Tune. If the value
is zero then RSSI threshold is not considered when doing a
seek. Default value is 25 dBuV.
Sets the output volume.
Mutes the audio output. L and R audio outputs may be muted
independently in FM mode.
Rev. 1.0
0x06AE
0x000A
0x0005
0x0019
0x003F
0x0000
23
Si4730/31-A10
GPO1
GPO2/INT
GPO3
NC
NC
NC
6. Pin Descriptions: Si4730/31-GM
20
19
18
17
16
1
FMI 2
15 NC
RFGND 3
14 LOUT
GND
PAD
AMI 4
13 ROUT
6
7
8
9
10
SCLK
SDIO
RCLK
VIO
12 GND
SEN
RST 5
11 VDD
Pin Number(s)
Name
1, 20
NC
No connect. Leave floating.
2
FMI
FM RF inputs. FMI should be connected to the antenna trace.
3
RFGND
4
AMI
AM RF input. AMI should be connected to the AM antenna.
5
RST
Device reset (active low) input.
6
SEN
Serial enable input (active low).
7
SCLK
Serial clock input.
8
SDIO
Serial data input/output.
9
RCLK
External reference oscillator input.
10
VIO
I/O supply voltage.
11
VDD
Supply voltage. May be connected directly to battery.
12, GND PAD
GND
Ground. Connect to ground plane on PCB.
13
ROUT
Right audio line output.
14
LOUT
Left audio line output.
15, 16
NC
17
GPO3
18
19
24
Description
RF ground. Connect to ground plane on PCB.
No connect. Leave floating.
General purpose output.
GPO2/INT General purpose output or interrupt pin.
GPO1
General purpose output.
Rev. 1.0
Si4730/31-A10
7. Ordering Guide
Part Number*
Description
Package
Type
Operating
Temperature
Si4730-A10-GM
AM/FM Broadcast Radio Receiver
QFN
Pb-free
–20 to 85 C
Si4731-A10-GM
AM/FM Broadcast Radio Receiver with RDS/RBDS
QFN
Pb-free
–20 to 85 C
*Note: Add an “(R)” at the end of the device part number to denote tape and reel option; 2500 quantity per reel.
Rev. 1.0
25
Si4730/31-A10
8. Package Markings (Top Marks)
8.1. Si4730/31 Top Mark
3010
ATTT
YWW
3110
ATTT
YWW
8.2. Top Mark Explanation
Mark Method:
YAG Laser
Line 1 Marking:
Part Number
30 = Si4730, 31 = Si4731
Firmware Revision
10 = Firmware Revision 1.0
Die Revision
A = Revision A Die
TTT = Internal Code
Internal tracking code.
Line 2 Marking:
Line 3 Marking:
Circle = 0.5 mm Diameter Pin 1 Identifier
(Bottom-Left Justified)
Y = Year
WW = Workweek
26
Assigned by the Assembly House. Corresponds to the last significant digit of the year and workweek of the mold date.
Rev. 1.0
Si4730/31-A10
9. Package Outline: Si4730/31 QFN
Figure 10 illustrates the package details for the Si4730/31. Table 14 lists the values for the dimensions shown in
the illustration.
Figure 10. 20-Pin Quad Flat No-Lead (QFN)
Table 14. Package Dimensions
Symbol
Millimeters
Symbol
Millimeters
Min
Nom
Max
A
0.50
0.55
0.60
f
A1
0.00
0.02
0.05
L
0.35
0.40
0.45
b
0.20
0.25
0.30
L1
0.00
—
0.10
c
0.27
0.32
0.37
aaa
—
—
0.05
bbb
—
—
0.05
ccc
—
—
0.08
ddd
—
—
0.10
eee
—
—
0.10
D
D2
3.00 BSC
1.65
e
1.70
1.75
0.50 BSC
E
E2
Min
3.00 BSC
1.65
1.70
Nom
Max
2.53 BSC
1.75
Notes:
1. All dimensions are shown in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
Rev. 1.0
27
Si4730/31-A10
10. PCB Land Pattern: Si4730/31 QFN
Figure 11 illustrates the PCB land pattern details for the Si4730/31-GM. Table 15 lists the values for the dimensions
shown in the illustration.
Figure 11. PCB Land Pattern
28
Rev. 1.0
Si4730/31-A10
Table 15. PCB Land Pattern Dimensions
Symbol
Millimeters
Min
D
D2
Symbol
Max
2.71 REF
1.60
1.80
Min
Max
GE
2.10
—
W
—
0.34
—
e
0.50 BSC
X
E
2.71 REF
Y
E2
f
GD
1.60
1.80
2.53 BSC
2.10
Millimeters
0.28
0.61 REF
ZE
—
3.31
ZD
—
3.31
—
Notes: General
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification.
3. This Land Pattern Design is based on IPC-SM-782 guidelines.
4. All dimensions shown are at Maximum Material Condition (MMC). Least Material
Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm.
Notes: Solder Mask Design
1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the
solder mask and the metal pad is to be 60 µm minimum, all the way around the pad.
Notes: Stencil Design
1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should
be used to assure good solder paste release.
2. The stencil thickness should be 0.125mm (5 mils).
3. The ratio of stencil aperture to land pad size should be 1:1 for the perimeter pads.
4. A 1.45 x 1.45 mm square aperture should be used for the center pad. This provides
approximately 70% solder paste coverage on the pad, which is optimum to assure
correct component stand-off.
Notes: Card Assembly
1. A No-Clean, Type-3 solder paste is recommended.
2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C
specification for Small Body Components.
Rev. 1.0
29
Si4730/31-A10
11. Additional Reference Resources
Si4730/31 Revision A Errata
AN231: Si4700/01 Headphone and Antenna Interface
AN383: Si47xx 3 mm x 3 mm QFN Universal Layout Guide
AN384: Si473x AM/FM Receiver Layout Guide
AN385: Si473x AM/FM Receiver Programming Guide
AN386: Si473x Ferrite Loop Stick Antenna Interface
AN388: Si473x AM/FM Tuner Evaluation Board Test Procedure
AN389: Si473x EVB Quick-Start Guide
Si47xx Customer Support Site: http://www.mysilabs.com
This site contains all application notes, evaluation board schematics and layouts, and evaluation software. NDA
is required for access. To request access, register at http://www.mysilabs.com and send user’s first and last
name, company, NDA reference number, and mysilabs user name to [email protected] Silicon Labs
recommends an all lower case user name.
30
Rev. 1.0
Si4730/31-A10
DOCUMENT CHANGE LIST
Revision 0.7 to Revision 1.0
Revision 0.3 to Revision 0.5
Updated block diagram on page 1 and Figure 8 on
page 16.
Removed optional digital audio output and GPO
functionality. These features will be supported in
future firmware revisions.
Updated Table 3, “DC Characteristics,” on page 5.
Added SPI control interface timing diagrams,
Figure 6 and Figure 7.
Updated data sheet to be specific to Si4730/31-A10.
Removed digital output information.
Updated Table 3, “DC Characteristics,” on page 5.
Updated Table 8, “FM Receiver Characteristics1,2,”
on page 11.
Updated Table 9, “AM Receiver Characteristics1,” on
page 12.
Updated Table 8, “FM Receiver Characteristics1,2,”
on page 11.
Updated Table 9, “AM Receiver Characteristics1,” on
page 12.
Adjusted crystal frequency tolerance from +/– 200 ppm
to +/– 100 ppm.
Updated values for C5 and L2 in "3. Bill of Materials"
on page 15.
Updated “4. Functional Description” to include
appropriate commands and properties.
Updated Table 12, “Si473x Command Summary,” on
page 21.
Updated Table 13, “Si473x Property Summary,” on
page 21.
Updated "7. Ordering Guide" on page 25.
Updated "11. Additional Reference Resources" on
page 30.
Added instructions on gaining access to the secure
customer website on p.29.
Revision 0.5 to Revision 0.7
Updated AM seek tune time.
Updated RCLK and REFCLK details.
Updated SPI description.
Updated default values in Table 13, “Si473x Property
Summary,” on page 21.
Added "8. Package Markings (Top Marks)" on page
26.
Added digital audio output information.
Updated Table 4, “Reset Timing Characteristics1,2,3,”
on page 6.
Updated "4.9. RDS/RBDS Processor (Si4731 Only)"
on page 18.
Updated "6. Pin Descriptions: Si4730/31-GM" on
page 24.
Rev. 1.0
31
Si4730/31-A10
CONTACT INFORMATION
Silicon Laboratories Inc.
400 West Cesar Chavez
Austin, TX 78701
Tel: 1+(512) 416-8500
Fax: 1+(512) 416-9669
Toll Free: 1+(877) 444-3032
Email: [email protected]
Internet: www.silabs.com
The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.
Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from
the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features
or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to
support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.
Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.
Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders.
32
Rev. 1.0
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