BlueCore5JMultimedia External (BC57E687C

BlueCore5JMultimedia External (BC57E687C

Features

Fully qualified Bluetooth v2.1 + EDR specification system

Best-in-class Bluetooth radio with 8dBm transmit

power and -90dBm receive sensitivity

64MIPS Kalimba DSP coprocessor

16-bit internal stereo codec: 95dB SNR for DAC

Low-power 1.5V operation, 1.8V to 3.6V I/O

Integrated 1.5V and 1.8V linear regulators

Integrated switch-mode regulator

Integrated battery charger

USB, I²C and UART with dual-port bypass mode

to 4Mbits/s

Supports up to 32Mb of external flash memory

(8Mb typical requirement)

Multi-configurable I²S, PCM or SPDIF interface

Enhanced audibility and noise cancellation

8 x 8 x 1.2mm, 0.5mm pitch 169-ball TFBGA

Support for IEEE 802.11 coexistence

Green (RoHS compliant and no antimony or halogenated flame retardants)

General Description

The _äìÉ`çêÉ

RJjìäíáãÉÇá~=bñíÉêå~ä

is a product from

CSR's Connectivity Centre. It is a single-chip radio and

baseband IC for Bluetooth 2.4GHz systems.

BlueCore5‑Multimedia External interfaces up to 32Mb

of external flash memory. When used with the CSR

Bluetooth stack, it provides a fully compliant Bluetooth

v2.1 + EDR specification system for data and voice.

BlueCore5‑Multimedia External contains the Kalimba

DSP coprocessor with double the MIPS of

BlueCore3‑Multimedia External, supporting enhanced audio applications.

BlueCore5‑Multimedia External is designed to reduce the number of external components required which ensures production costs are minimised. The device

incorporates auto-calibration and BIST routines to

simplify development, type approval and production test.

_äìÉ`çêÉ

RJjìäíáãÉÇá~=bñíÉêå~ä

Fully Qualified Single-chip

Bluetooth

®

v2.1 + EDR System

Production Information

BC57E687C

Issue 4

Applications

High-quality stereo wireless headsets

High-quality mono headsets

Hands-free car kits

Wireless speakers

VoIP handsets

Analogue and USB multimedia dongles

Bluetooth automotive wireless gateways

To improve the performance of both Bluetooth and

802.11 b/g co-located systems, dedicated hardware

has been implemented to support coexistence

features including support for CSR's Unity coexistence

scheme.

For radio performance over temperature and additional performance information refer to the

BlueCore

®

5‑Multimedia External Performance

Specification

.

XTAL

RF IN

RF OUT

2.4

GHz

Radio

RAM

Baseband

DSP

MCU

Kalimba

DSP

I/O

External Memory

Flash

UART/USB

PIO

Audio In/Out

PCM/I 2 S/SPDIF

SPI

CS-121064-DSP4

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Document History

Document History

Revision Date

Issue 1 10 JUL 08

Issue 2

Issue 3

Issue 4

15 JUL 08

08 MAY 09

09 FEB 10

Change Reason

Original publication of document as BlueCore5-Multimedia External changed to revision C silicon.

Data sheet replaces revision B silicon, document number CS-101568-DSP.

USB interface updated

Internal release only.

SPI interface updated.

High-voltage linear regulator description updated.

Electrical Characteristics updates:

Correction of the units for the stereo codec ADC mic mode impedance

Reworded output current parameter in all linear regulator electrical characterisation tables to remove ambiguity

ESD precautions section moved to Electrical Characteristics

Tape dimensions added.

Status Information updated.

Power Consumption conditions updated.

Various editorial updates.

If you have any comments about this document, email [email protected]

giving number, title and section with your feedback.

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Status Information

Status Information

The status of this Data Sheet is Production Information.

CSR Product Data Sheets progress according to the following format:

Advance Information

Information for designers concerning CSR product in development. All values specified are the target values of the

design. Minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values.

All detailed specifications including pinouts and electrical specifications may be changed by CSR without notice.

Pre-production Information

Pinout and mechanical dimension specifications finalised. All values specified are the target values of the design.

Minimum and maximum values specified are only given as guidance to the final specification limits and must not be considered as the final values.

All electrical specifications may be changed by CSR without notice.

Production Information

Final Data Sheet including the guaranteed minimum and maximum limits for the electrical specifications.

Production Data Sheets supersede all previous document versions.

Life Support Policy and Use in Safety-critical Applications

CSR's products are not authorised for use in life-support or safety-critical applications. Use in such applications is done at the sole discretion of the customer. CSR will not warrant the use of its devices in such applications.

CSR Green Semiconductor Products and RoHS Compliance

BlueCore5‑Multimedia External devices meet the requirements of Directive 2002/95/EC of the European Parliament

and of the Council on the Restriction of Hazardous Substance (RoHS).

BlueCore5‑Multimedia External devices are also free from halogenated or antimony trioxide-based flame retardants

and other hazardous chemicals. For more information, see CSR's

Environmental Compliance Statement for CSR

Green Semiconductor Products

.

Trademarks, Patents and Licences

Unless otherwise stated, words and logos marked with

affiliates. Bluetooth

® owners.

and the Bluetooth

®

or

®

are trademarks registered or owned by CSR plc or its

logos are trademarks owned by Bluetooth

®

SIG, Inc. and licensed to

CSR. Other products, services and names used in this document may have been trademarked by their respective

The publication of this information does not imply that any license is granted under any patent or other rights owned

by CSR plc and/or its affiliates.

CSR reserves the right to make technical changes to its products as part of its development programme.

While every care has been taken to ensure the accuracy of the contents of this document, CSR cannot accept

responsibility for any errors.

Refer to www.csrsupport.com

for compliance and conformance to standards information.

No statements or representations in this document are to be construed as advertising, marketing, or offering for sale in the United States imported covered products subject to the Cease and Desist Order issued by the U.S.

International Trade Commission in its Investigation No. 337-TA-602. Such products include SiRFstarIII chips that operate with SiRF software that supports SiRFInstantFix, and/or SiRFLoc servers, or contains SyncFreeNav functionality.

CS-121064-DSP4

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Contents

4

5

6

7

8

1

2

3

Contents

Device Details ............................................................................................................................................... 10

Functional Block Diagram ............................................................................................................................ 11

Package Information ..................................................................................................................................... 12

3.1 Pinout Diagram .................................................................................................................................... 12

3.2 Device Terminal Functions .................................................................................................................. 13

3.3 Package Dimensions ........................................................................................................................... 21

3.4 PCB Design and Assembly Considerations ......................................................................................... 22

3.5 Typical Solder Reflow Profile ............................................................................................................... 22

Bluetooth Modem .......................................................................................................................................... 23

4.1 RF Ports ............................................................................................................................................... 23

4.1.1

RF_N and RF_P ..................................................................................................................... 23

4.2 RF Receiver ......................................................................................................................................... 23

4.2.1

Low Noise Amplifier ............................................................................................................... 23

4.2.2

RSSI Analogue to Digital Converter ....................................................................................... 23

4.3 RF Transmitter ..................................................................................................................................... 23

4.3.1

IQ Modulator .......................................................................................................................... 23

4.3.2

Power Amplifier ...................................................................................................................... 24

4.3.3

Transmit RF Power Control for Class 1 Applications (TX_PWR) ........................................... 24

4.4 Bluetooth Radio Synthesiser ............................................................................................................... 25

4.5 Baseband ............................................................................................................................................. 25

4.5.1

Burst Mode Controller ............................................................................................................ 25

4.5.2

Physical Layer Hardware Engine ........................................................................................... 25

4.6 Basic Rate Modem .............................................................................................................................. 25

4.7 Enhanced Data Rate Modem .............................................................................................................. 25

Clock Generation .......................................................................................................................................... 27

5.1 Clock Architecture ................................................................................................................................ 27

5.2 Input Frequencies and PS Key Settings .............................................................................................. 27

5.3 External Reference Clock .................................................................................................................... 28

5.3.1

Input (XTAL_IN) ..................................................................................................................... 28

5.3.2

XTAL_IN Impedance in External Mode .................................................................................. 28

5.3.3

Clock Start-up Delay .............................................................................................................. 28

5.3.4

Clock Timing Accuracy ........................................................................................................... 28

5.4 Crystal Oscillator (XTAL_IN, XTAL_OUT) ........................................................................................... 29

5.4.1

Load Capacitance .................................................................................................................. 30

5.4.2

Frequency Trim ...................................................................................................................... 30

5.4.3

Transconductance Driver Model ............................................................................................ 31

5.4.4

Negative Resistance Model ................................................................................................... 31

5.4.5

Crystal PS Key Settings ......................................................................................................... 31

Bluetooth Stack Microcontroller .................................................................................................................... 32

6.1 Programmable I/O Ports, PIO and AIO ................................................................................................ 32

6.2 TCXO Enable OR Function ................................................................................................................. 32

6.3 WLAN Coexistence Interface ............................................................................................................... 33

Kalimba DSP ................................................................................................................................................ 34

Memory Interface and Management ............................................................................................................. 35

8.1 Memory Management Unit .................................................................................................................. 35

8.2 System RAM ........................................................................................................................................ 35

8.3 Kalimba DSP RAM .............................................................................................................................. 35

8.4 External Memory Driver ....................................................................................................................... 35

8.5 External Flash Memory (32Mb) ........................................................................................................... 35

8.6 Off-chip Program Memory ................................................................................................................... 35

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Contents

9

8.6.1

Minimum Flash Specification ................................................................................................. 36

8.6.2

Common Flash Interface ........................................................................................................ 36

8.6.3

Virtual Machine Requirements ............................................................................................... 37

8.6.4

Memory Timing ...................................................................................................................... 38

Serial Interfaces ............................................................................................................................................ 40

9.1 UART Interface .................................................................................................................................... 40

9.1.1

UART Configuration While Reset is Active ............................................................................ 41

9.1.2

UART Bypass Mode ............................................................................................................... 42

9.1.3

Current Consumption in UART Bypass Mode ........................................................................ 42

9.2 USB Interface ...................................................................................................................................... 42

9.3 Programming and Debug Interface ...................................................................................................... 43

9.3.1

Instruction Cycle ..................................................................................................................... 43

9.3.2

Multi-slave Operation ............................................................................................................. 43

9.4 I²C Interface ......................................................................................................................................... 43

9.4.1

Software I²C Interface ............................................................................................................ 43

9.4.2

Bit-serialiser Interface ............................................................................................................ 44

10

Audio Interface .............................................................................................................................................. 45

10.1 Audio Input and Output ........................................................................................................................ 45

10.2 Stereo Audio Codec Interface .............................................................................................................. 45

10.2.1 Stereo Audio Codec Block Diagram ....................................................................................... 46

10.2.2 Stereo Codec Set-up .............................................................................................................. 46

10.2.3 ADC ........................................................................................................................................ 47

10.2.4 ADC Sample Rate Selection .................................................................................................. 47

10.2.5 ADC Digital Gain .................................................................................................................... 47

10.2.6 ADC Analogue Gain ............................................................................................................... 47

10.2.7 DAC ........................................................................................................................................ 48

10.2.8 DAC Sample Rate Selection .................................................................................................. 48

10.2.9 DAC Digital Gain .................................................................................................................... 48

10.2.10 DAC Analogue Gain ............................................................................................................... 49

10.2.11 IEC 60958 Interface ............................................................................................................... 49

10.2.12 Microphone Input ................................................................................................................... 50

10.2.13 Line Input ............................................................................................................................... 53

10.2.14 Output Stage .......................................................................................................................... 54

10.2.15 Mono Operation ..................................................................................................................... 55

10.2.16 Side Tone ............................................................................................................................... 55

10.2.17 Integrated Digital Filter ........................................................................................................... 55

10.3 PCM Interface ...................................................................................................................................... 56

10.3.1 PCM Interface Master/Slave .................................................................................................. 56

10.3.2 Long Frame Sync ................................................................................................................... 57

10.3.3 Short Frame Sync .................................................................................................................. 57

10.3.4 Multi-slot Operation ................................................................................................................ 58

10.3.5 GCI Interface .......................................................................................................................... 58

10.3.6 Slots and Sample Formats ..................................................................................................... 59

10.3.7 Additional Features ................................................................................................................ 59

10.3.8 PCM Timing Information ........................................................................................................ 60

10.3.9 PCM_CLK and PCM_SYNC Generation ................................................................................ 63

10.3.10 PCM Configuration ................................................................................................................. 63

10.4 Digital Audio Interface (I²S) .................................................................................................................. 65

11

Power Control and Regulation ...................................................................................................................... 70

11.1 Power Sequencing ............................................................................................................................... 70

11.2 External Voltage Source ...................................................................................................................... 71

11.3 Switch-mode Regulator ....................................................................................................................... 71

11.4 High-voltage Linear Regulator ............................................................................................................. 71

11.5 Low-voltage Linear Regulator .............................................................................................................. 71

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Contents

11.6 Low-voltage Audio Linear Regulator .................................................................................................... 72

11.7 Voltage Regulator Enable Pins ............................................................................................................ 72

11.8 Battery Charger ................................................................................................................................... 72

11.9 LED Drivers ......................................................................................................................................... 73

11.10Reset, RST# ........................................................................................................................................ 74

11.10.1 Digital Pin States on Reset .................................................................................................... 74

11.10.2 Status after Reset .................................................................................................................. 75

12

Example Application Schematic ................................................................................................................... 76

13

Electrical Characteristics .............................................................................................................................. 77

13.1 Absolute Maximum Ratings ................................................................................................................. 77

13.2 Recommended Operating Conditions .................................................................................................. 77

13.3 Input/Output Terminal Characteristics ................................................................................................. 78

13.3.1 High-voltage Linear Regulator ............................................................................................... 78

13.3.2 Low-voltage Linear Regulator ................................................................................................ 79

13.3.3 Low-voltage Linear Audio Regulator ...................................................................................... 80

13.3.4 Reset ...................................................................................................................................... 81

13.3.5 Regulator Enable ................................................................................................................... 81

13.3.6 Switch-mode Regulator .......................................................................................................... 82

13.3.7 Battery Charger ...................................................................................................................... 83

13.3.8 Digital Terminals .................................................................................................................... 84

13.3.9 LED Driver Pads .................................................................................................................... 85

13.3.10 USB ........................................................................................................................................ 85

13.3.11 Auxiliary ADC ......................................................................................................................... 86

13.3.12 Auxiliary DAC ......................................................................................................................... 86

13.3.13 Clocks .................................................................................................................................... 87

13.3.14 Stereo Codec: Analogue to Digital Converter ........................................................................ 88

13.3.15 Stereo Codec: Digital to Analogue Converter ........................................................................ 89

13.4 ESD Precautions ................................................................................................................................. 89

14

Power Consumption ..................................................................................................................................... 90

14.1 Kalimba DSP Typical Average Current Consumption ......................................................................... 91

14.2 Typical Peak Current at 20°C .............................................................................................................. 91

14.3 Conditions ............................................................................................................................................ 91

15

CSR Green Semiconductor Products and RoHS Compliance ..................................................................... 92

15.1 RoHS Statement .................................................................................................................................. 92

15.1.1 List of Restricted Materials ..................................................................................................... 92

16

CSR Synergy and Bluetooth Software Stack ................................................................................................ 93

16.1 BlueCore HCI Stack ............................................................................................................................ 93

16.1.1 Key Features of the HCI Stack: Standard Bluetooth Functionality ......................................... 93

16.1.2 Key Features of the HCI Stack: Extra Functionality ............................................................... 95

16.2 Host-Side Software .............................................................................................................................. 95

16.3 CSR Development Systems ................................................................................................................ 95

16.4 eXtension ............................................................................................................................................. 95

17

Ordering Information ..................................................................................................................................... 96

18

Tape and Reel Information ........................................................................................................................... 97

18.1 Tape Orientation .................................................................................................................................. 97

18.2 Tape Dimensions ................................................................................................................................. 98

18.3 Reel Information .................................................................................................................................. 99

18.4 Moisture Sensitivity Level .................................................................................................................... 99

19

Document References ................................................................................................................................ 100

Terms and Definitions .......................................................................................................................................... 101

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Contents

List of Figures

Figure 2.1

Functional Block Diagram ............................................................................................................... 11

Figure 3.1

Device Pinout .................................................................................................................................. 12

Figure 3.2

169-ball TFBGA Package Dimensions ............................................................................................ 21

Figure 4.1

Simplified Circuit RF_N and RF_P .................................................................................................. 23

Figure 4.2

Internal Power Ramping .................................................................................................................. 24

Figure 4.3

BDR and EDR Packet Structure ..................................................................................................... 26

Figure 5.1

Clock Architecture ........................................................................................................................... 27

Figure 5.2

TCXO Clock Accuracy .................................................................................................................... 29

Figure 5.3

Crystal Driver Circuit ....................................................................................................................... 29

Figure 5.4

Crystal Equivalent Circuit ................................................................................................................ 29

Figure 6.1

Example TCXO Enable OR Function .............................................................................................. 32

Figure 7.1

Kalimba DSP Interface to Internal Functions .................................................................................. 34

Figure 8.1

Memory Write Cycle ........................................................................................................................ 38

Figure 8.2

Memory Read Cycle ........................................................................................................................ 39

Figure 9.1

Universal Asynchronous Receiver .................................................................................................. 40

Figure 9.2

Break Signal .................................................................................................................................... 41

Figure 9.3

UART Bypass Architecture ............................................................................................................. 42

Figure 9.4

Example EEPROM Connection ...................................................................................................... 44

Figure 10.1 Audio Interface ................................................................................................................................ 45

Figure 10.2 Stereo Codec Audio Input and Output Stages ................................................................................ 46

Figure 10.3 ADC Analogue Amplifier Block Diagram ......................................................................................... 48

Figure 10.4 Example Circuit for SPDIF Interface (Co-Axial) .............................................................................. 50

Figure 10.5 Example Circuit for SPDIF Interface (Optical) ................................................................................. 50

Figure 10.6 Microphone Biasing ......................................................................................................................... 50

Figure 10.7 Differential Input .............................................................................................................................. 54

Figure 10.8 Single-ended Input .......................................................................................................................... 54

Figure 10.9 Speaker Output ............................................................................................................................... 54

Figure 10.10 PCM Interface Master ..................................................................................................................... 57

Figure 10.11 PCM Interface Slave ....................................................................................................................... 57

Figure 10.12 Long Frame Sync (Shown with 8-bit Companded Sample) ............................................................ 57

Figure 10.13 Short Frame Sync (Shown with 16-bit Sample) .............................................................................. 58

Figure 10.14 Multi-slot Operation with Two Slots and 8-bit Companded Samples .............................................. 58

Figure 10.15 GCI Interface ................................................................................................................................... 58

Figure 10.16 16-Bit Slot Length and Sample Formats ......................................................................................... 59

Figure 10.17 PCM Master Timing Long Frame Sync ........................................................................................... 61

Figure 10.18 PCM Master Timing Short Frame Sync .......................................................................................... 61

Figure 10.19 PCM Slave Timing Long Frame Sync ............................................................................................. 62

Figure 10.20 PCM Slave Timing Short Frame Sync ............................................................................................ 63

Figure 10.21 Digital Audio Interface Modes ......................................................................................................... 67

Figure 10.22 Digital Audio Interface Slave Timing ............................................................................................... 68

Figure 10.23 Digital Audio Interface Master Timing ............................................................................................. 69

Figure 11.1 Voltage Regulator Configuration ..................................................................................................... 70

Figure 11.2 LED Equivalent Circuit .................................................................................................................... 73

Figure 12.1 Example Application Schematic ...................................................................................................... 76

Figure 16.1 BlueCore HCI Stack ........................................................................................................................ 93

Figure 18.1 Tape and Reel Orientation .............................................................................................................. 97

Figure 18.2 Tape Dimensions ............................................................................................................................ 98

Figure 18.3 Reel Dimensions ............................................................................................................................. 99

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Contents

List of Tables

Table 4.1

Table 4.2

Table 5.1

Table 5.2

Table 5.3

Table 8.1

Table 8.2

Table 8.3

Table 8.4

TXRX_PIO_CONTROL Values ........................................................................................................ 24

Data Rate Schemes ......................................................................................................................... 26

PS Key Values for CDMA/3G Phone TCXO .................................................................................... 27

External Clock Specifications ........................................................................................................... 28

Crystal Specification ......................................................................................................................... 29

Flash Device Hardware Requirements ............................................................................................. 36

Flash Sector Boundaries .................................................................................................................. 36

Common Flash Interface Algorithm Command Set Codes .............................................................. 37

Erase Block Region Information for Uniform 2KW Sectors .............................................................. 37

Table 8.5

Table 8.6

Table 8.7

Table 8.8

Table 8.9

Erase Block Region Information for Uniform 1KW Sectors .............................................................. 37

Erase Block Region Information for 8 x 4KW, n x 32KW Sectors .................................................... 37

Erase Block Region Information for 1 x 8KW, 2 x 4KW, 1 x 16KW, n x 32KW Sectors ................... 37

Memory Write Cycle ......................................................................................................................... 38

Memory Read Cycle ......................................................................................................................... 39

Table 9.1

Table 9.2

Possible UART Settings ................................................................................................................... 40

Standard Baud Rates ....................................................................................................................... 41

Table 9.3

Instruction Cycle for a SPI Transaction ............................................................................................ 43

Table 10.1 Alternative Functions of the Digital Audio Bus Interface on the PCM Interface ............................... 45

Table 10.2 ADC Digital Gain Rate Selection ...................................................................................................... 47

Table 10.3 DAC Digital Gain Rate Selection ...................................................................................................... 49

Table 10.4 DAC Analogue Gain Rate Selection ................................................................................................. 49

Table 10.5 Voltage Output Steps ....................................................................................................................... 52

Table 10.6 Current Output Steps ....................................................................................................................... 53

Table 10.7 PCM Master Timing .......................................................................................................................... 60

Table 10.8 PCM Slave Timing ............................................................................................................................ 62

Table 10.9 PSKEY_PCM_LOW_JITTER_CONFIG Description ......................................................................... 64

Table 10.10 PSKEY_PCM_CONFIG32 Description ............................................................................................. 64

Table 10.11 Alternative Functions of the Digital Audio Bus Interface on the PCM Interface ............................... 65

Table 10.12 PSKEY_DIGITAL_AUDIO_CONFIG ................................................................................................. 66

Table 10.13 Digital Audio Interface Slave Timing ................................................................................................ 68

Table 10.14 Digital Audio Interface Master Timing .............................................................................................. 69

Table 11.1 BlueCore5‑Multimedia External Voltage Regulator Enable Pins ...................................................... 72

Table 11.2 Pin States on Reset .......................................................................................................................... 74

List of Equations

Equation 4.1 Output Voltage with Load Current I ................................................................................................. 24

Equation 4.2 Output Voltage with No Load Current ............................................................................................. 24

Equation 5.1 Load Capacitance ........................................................................................................................... 30

Equation 5.2 Trim Capacitance ............................................................................................................................ 30

Equation 5.3 Frequency Trim ............................................................................................................................... 30

Equation 5.4 Pullability ......................................................................................................................................... 30

Equation 5.5 Transconductance Required for Oscillation .................................................................................... 31

Equation 5.6 Equivalent Negative Resistance ..................................................................................................... 31

Equation 9.1 Baud Rate ....................................................................................................................................... 41

Equation 10.1IIR Filter Transfer Function, H(z) ..................................................................................................... 56

Equation 10.2IIR Filter plus DC Blocking Transfer Function, H

DC

(z) .................................................................... 56

Equation 10.3PCM_CLK Frequency When Being Generated Using the Internal 48MHz Clock ........................... 63

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Contents

Equation 10.4PCM_SYNC Frequency Relative to PCM_CLK ............................................................................... 63

Equation 11.1LED Current .................................................................................................................................... 74

Equation 11.2LED PAD Voltage ............................................................................................................................ 74

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Device Details

1 Device Details

Radio

Common TX/RX terminal simplifies external

matching; eliminates external antenna switch

BIST minimises production test time

Bluetooth v2.1 + EDR specification compliant

Transmitter

8dBm RF transmit power with level control from on-

chip 6-bit DAC over a dynamic range >30dB

Class 2 and Class 3 support without the need for an

external power amplifier or TX/RX switch

Receiver

Receiver sensitivity of -90dBm

Integrated channel filters

Digital demodulator for improved sensitivity and cochannel rejection

Real-time digitised RSSI available on HCI interface

Fast AGC for enhanced dynamic range

Synthesiser

Fully integrated synthesiser requires no external

VCO, varactor diode, resonator or loop filter

Compatible with crystals 16MHz to 26MHz or an external clock 12MHz to 52MHz

Accepts 14.40, 15.36, 16.2, 16.8, 19.2, 19.44,

19.68, 19.8 and 38.4MHz TCXO frequencies for

GSM and CDMA devices with sinusoidal or logic

level signals

Baseband and Software

32Mb external flash

48KB internal RAM, allows full-speed data transfer,

mixed voice/data and full piconet support

Logic for forward error correction, header error

control, access code correlation, CRC,

demodulation, encryption bit stream generation, whitening and transmit pulse shaping

Transcoders for A-law, µ-law and linear voice from host and A-law, µ-law and CVSD voice over air

Physical Interfaces

SPI with clock speeds up to 64MHz in master mode,

requires firmware support, and 32MHz in slave mode

I²C master compatible interface

UART interface with programmable data rate up to

3Mbits/s with an optional bypass mode

USB v2.0 interface

Bidirectional serial programmable audio interface

supporting PCM, I²S and SPDIF formats

2 LED drivers with faders

Kalimba DSP

Very low power Kalimba DSP coprocessor,

64MIPS, 24-bit fixed point core

SBC decode takes approximately 4mW power

consumption while streaming music

Single-cycle MAC; 24 x 24-bit multiply and 56-bit

accumulator

32-bit instruction word, dual 24-bit data memory

6K x 32-bit program RAM, 16K x 24-bit + 12K x 24bit data RAM

64-word x 32-bit program memory cache when executing from external flash

Stereo Audio Codec

16-bit internal stereo codec

Dual ADC and DAC for stereo audio

Integrated amplifiers for driving 16Ω speakers; no need for external components

Support for single-ended speaker termination and line output

Integrated low-noise microphone bias

ADC sample rates are 8, 11.025, 16, 22.05, 32 and

44.1kHz

DAC sample rates are 8, 11.025, 12, 16, 22.05, 24,

32, 44.1 and 48kHz

Auxiliary Features

User space on processor for customer applications

Crystal oscillator with built-in digital trimming

Power management includes digital shutdown and wake-up commands with an integrated low-power oscillator for ultra-low power Park/Sniff/Hold mode

Clock request output to control external clock

On-chip regulators: 1.5V output from 1.8V to 2.7V

input and 1.8V output from 2.7V to 4.5V input

On-chip high-efficiency switch-mode regulator;

1.8V output from 2.7V to 4.4V input

Power-on-reset cell detects low supply voltage

10-bit ADC and 8-bit DAC available to applications

On-chip charger for lithium ion/polymer batteries

Bluetooth Stack

CSR's Bluetooth Protocol Stack runs on the on-chip

MCU in a variety of configurations:

Standard HCI, UART or USB

Audio codec and echo-noise suppression or customer-specific algorithms running on the DSP

Package Option

■ TFBGA 169-ball, 8 x 8 x 1.2mm, 0.5mm pitch

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2 Functional Block Diagram

RF_N

RF_P

VDD_CORE

VSS_RADIO

VSS_ANA

VDD_LO

VSS_LO

LO_REF

XTAL_OUT

XTAL_IN

AUX_DAC

VDD_CHG

BAT_P

VDD_SMP_CORE

LX

BAT_N

VREGENABLE_H

VREGIN_H

VREGOUT_H

VREGENABLE_L

VREGIN_L

VDD_ANA

VDD_RADIO

VREGIN_AUDIO

VDD_AUDIO

VSS_AUDIO

Bluetooth Modem

Bluetooth v2.1

Radio

Baseband

Basic Rate

Modem

Enhanced

Rate Modem

Radio Control

Clock

Generation

AUX

DAC

Power Control and Regulation

IN

Battery Charger

OUT

SENSE

Switch-mode

Regulator

EN

IN

High-voltage

Linear Regulator

OUT

EN

SENSE

IN EN

Low-voltage

Linear Regulator

OUT SENSE

IN

Audio Lowvoltage Regulator

OUT

EN

SENSE

I

2

C Bus available on any PIO pins, default configuration shown

I 2 C Interface USB v1.1

UART

Serial Interfaces

SPI

Interface

Memory Management Unit

Bluetooth Stack Microcontroller

Interrupt

Controller

Timers MCU

System RAM

Kalimba DSP Coprocessor

Interrupt

Controller

Timers Kalimba DSP

Data Memory

DM1

Data Memory

DM2

Program

Memory PM

LED Driver

Programmable I/O

AIO GPIO

Flash / ROM Memory Interface

Flash

Interface

ROM Interface

CS-121064-DSP4

Figure 2.1: Functional Block Diagram

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PCM_CLK

PCM_SYNC

PCM_OUT

PCM_IN

SPKR_A_N

SPKR_A_P

SPKR_B_N

SPKR_B_P

MIC_BIAS

MIC_A_N

MIC_A_P

MIC_B_N

MIC_B_P

AU_REF_DCPL

VDD_PADS

VSS_DIG

VSS

SUBS

RST#

TEST_EN

Functional Block Diagram

Page 11 of 104

Package Information

3 Package Information

3.1

Pinout Diagram

Orientation from Top

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

H

J

F

G

K

L

M

N

P

R

C

D

E

A

B

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15

B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15

C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13

C14 C15

D1 D2 D3 D13 D14 D15

E1

F1

G1

H1

E2

F2

G2

H2

E3

F3

G3

H3

F6

G6

H6

F7

G7

H7

F8

G8

H8

F9

G9

H9

F10

G10

H10

E13 E14 E15

F13 F14 F15

G13 G14 G15

H13 H14 H15

J1 J2 J3

K1 K2 K3

J6 J7 J8 J9 J10

K6 K7 K8 K9 K10

J13 J14 J15

K13 K14 K15

L1 L2 L3 L13 L14 L15

M1 M2 M3 M13 M14 M15

N1 N2

N3

N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15

P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15

R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15

Figure 3.1: Device Pinout

CS-121064-DSP4

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Package Information

3.2

Device Terminal Functions

Radio Ball Pad Type

RF_P K1

RF

RF_N

AUX_DAC

L1

RF

H2 Analogue

Synthesiser and

Oscillator

XTAL_IN

XTAL_OUT

LO_REF

Ball Pad Type

R1 Analogue

R2 Analogue

P3 Analogue

Supply Domain

VDD_RADIO

VDD_RADIO

VDD_PIO

Supply Domain

VDD_ANA

VDD_ANA

VDD_ANA

UART

UART_TX

UART_RX

UART_RTS

UART_CTS

USB

USB_DP

USB_DN

Ball Pad Type

N15

Supply Domain

Bidirectional CMOS

output, tristate, with weak internal pull-up

VDD_USB

N14

R15

P15

CMOS input with

weak internal pulldown

CMOS input with

weak internal pulldown

VDD_USB

Bidirectional CMOS

output, tristate, with weak internal pull-up

VDD_USB

VDD_USB

Ball Pad Type

P14 Bidirectional

P13 Bidirectional

Supply Domain

VDD_USB

VDD_USB

Description

Transmitter output/switched receiver input

Complement of RF_P

8-bit voltage-output DAC

Description

For crystal or external clock input

Drive for crystal

Reference voltage to decouple the synthesiser

Description

UART data output

UART data input

UART request to send active low

UART clear to send active low

Description

USB data plus with selectable

internal 1.5kΩ pull-up resistor

USB data minus

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Package Information

PCM Interface

PCM_OUT

PCM_IN

PCM_SYNC

PCM_CLK

SPI Interface

SPI_MISO

SPI_MOSI

SPI_CS#

SPI_CLK

Ball Pad Type

F15

CMOS output,

tristate, with weak internal pull-down

G15

F14

F13

CMOS input, with

weak internal pulldown

Bidirectional with weak internal pulldown

Bidirectional with weak internal pulldown

Supply Domain

VDD_PADS

VDD_PADS

VDD_PADS

VDD_PADS

Ball Pad Type

D15

CMOS output,

tristate, with weak internal pull-down

E13

CMOS input, with

weak internal pulldown

Supply Domain

VDD_PADS

VDD_PADS

VDD_PADS

VDD_PADS

Description

Synchronous data output

Synchronous data input

Synchronous data sync

Synchronous data clock

Description

SPI data output

SPI data input

Chip select for SPI, active low

SPI clock

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Package Information

PIO[9]

PIO[8]

PIO[7]

PIO[6]

PIO[5]

PIO[4]

PIO[3]

PIO[2]

PIO Port

PIO[15]

PIO[14]

PIO[13]

PIO[12]

PIO[11]

PIO[10]

PIO[1]

PIO[0]

AIO[1]

AIO[0]

Test and Debug

RST#

TEST_EN

H14

H13

F3

G3

M14

J14

J13

H15

Ball Pad Type

M15

J15

K14

K13

L14

M13

Bidirectional with programmable strength internal pullup/down

Supply Domain

VDD_PADS

F2

Bidirectional with programmable strength internal pullup/down

VDD_PIO

F1

N3

R4

Bidirectional VDD_ANA

Ball Pad Type Supply Domain

G14

CMOS input with

strong internal pulldown

VDD_PADS

Description

Programmable input/output line

Programmable input/output line

Programmable input/output line

Programmable input/output line

(external TXEN)

Programmable input/output line

(external RXEN)

Analogue programmable input/ output line

Description

Reset if low. Input debounced so must be low for >5ms to cause a reset

For test purposes only (leave unconnected)

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A[6]

A[5]

A[4]

A[10]

A[9]

A[8]

A[7]

A[14]

A[13]

A[12]

A[11]

A[3]

A[2]

A[1]

A[0]

External Memory

Address Interface

A[20]

A[19]

A[18]

A[17]

A[16]

A[15]

Ball Pad Type

N6

R7

P7

P10

N10

R11

P11

N11

R12

P12

C9

P5

N5

R6

P6

N12

P8

N9

R10

P9

R5

CMOS output,

tristate, weak pulldown

Supply Domain

VDD_MEM

Description

Address line

Package Information

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Package Information

D[5]

D[4]

D[3]

D[2]

D[9]

D[8]

D[7]

D[6]

D[1]

D[0]

External Memory

Data Interface

D[15]

D[14]

D[13]

D[12]

D[11]

D[10]

External Memory

Interface

FLASH_RP#

OE#

WE#

CS#

Ball Pad Type

C6

B7

B8

A9

C10

B11

B10

A11

B5

A6

A5

C5

B6

A7

C7

C8

Bidirectional with weak internal pulldown

Supply Domain

VDD_MEM

Ball Pad Type

R9

C11

N7

A10

CMOS output,

tristate with internal weak pull-up

CMOS output,

tristate with internal weak pull-up

CMOS output,

tristate with internal weak pull-up

CMOS output,

tristate with internal weak pull-up

Supply Domain

VDD_MEM

VDD_MEM

VDD_MEM

VDD_MEM

Description

Data line

Description

Flash reset

Output enable for external memory, active low

Flash write enable for external memory, active low

Chip select for external memory, active low

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Package Information

Codec

MIC_A_P

MIC_A_N

MIC_B_P

MIC_B_N

SPKR_A_P

SPKR_A_N

SPKR_B_P

SPKR_B_N

MIC_BIAS

AU_REF_DCPL

Ball Pad Type

C2 Analogue

C1 Analogue

B2 Analogue

B1 Analogue

E1 Analogue

E2 Analogue

D1 Analogue

D2 Analogue

B3

E3

Analogue

Analogue

Supply Domain

VDD_AUDIO

VDD_AUDIO

VDD_AUDIO

VDD_AUDIO

VDD_AUDIO

VDD_AUDIO

VDD_AUDIO

VDD_AUDIO

VDD_AUDIO,

BAT_P

VDD_AUDIO

Description

Microphone input positive, left

Microphone input negative, left

Microphone input positive, right

Microphone input negative, right

Speaker output positive, left

Speaker output negative, left

Speaker output positive, right

Speaker output negative, right

Microphone bias

Decoupling of audio reference (for high-quality audio)

Description

LED driver

LED driver

LED Drivers

LED[1]

LED[0]

Power Supplies and

Control

VREGENABLE_H

Ball Pad Type

D14 Open drain output

D13 Open drain output

Ball

B14

VREGIN_H

VREGOUT_H

VREGENABLE_L

VREGIN_L

VDD_ANA

VREGIN_AUDIO

A15

B15

M2

N2

P1

A3

Supply Domain

See Section 11.9

See Section 11.9

Pad Type

Analogue

Regulator input

Supply

Analogue

Regulator input

VDD/Low-voltage regulator output

Regulator input

Description

Take high to enable high-voltage linear regulator and switch-mode regulator

Input to internal high-voltage linear regulator

High-voltage linear regulator output

Take high to enable both lowvoltage regulator and audio lowvoltage regulator

Input to internal low-voltage linear regulator for non-audio core circuitry

Positive supply output for analogue circuitry and 1.5V regulated output

(from internal low-voltage regulator)

Input to internal audio low-voltage linear regulator

CS-121064-DSP4

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Package Information

Power Supplies and

Control

VDD_AUDIO

VDD_CHG

BAT_P

VDD_SMP_CORE

LX

VDD_CORE

VDD_RADIO

VDD_LO

VDD_USB

VDD_PIO

VDD_PADS

VDD_MEM

VSS_DIG

VSS_RADIO

Ball Pad Type Description

A2

A12

B13

A14

A13

C15, K15

M1

N1

R14

G1

L15

A4, A8, B9, R8, R13 VDD

B4, C4, C12, C13, C14, H3,

L13, N4, N8, N13,

VSS

J2, K2, L2 VSS

VDD/Low-voltage regulator output

Charger input

Positive supply output for audio circuitry and 1.5V regulated output

(from internal low-voltage regulator)

Lithium ion/polymer battery charger input

Battery terminal +ve

Lithium ion/polymer battery positive terminal. Battery charger output and input to switch-mode regulator

VDD

Switch-mode power regulator output

VDD

Positive supply for switch mode control circuitry

Switch-mode power regulator output

Positive supply for internal digital circuitry, 1.5V

VDD/Low-voltage regulator sense

Positive supply for RF circuitry, 1.5V

VDD

VDD

VDD

VDD

Positive supply for local oscillator circuitry, 1.5V

Positive supply for UART/USB ports

Positive supply for PIO[3:0] and

auxiliary DAC

Positive supply for all other digital

Input/Output ports, SPI/PCM ports

and PIO[15:4]

Positive supply for flash pads

Ground connection for internal digital circuitry

Ground connections for RF circuitry

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Package Information

Power Supplies and

Control

VSS_LO

VSS_ANA

VSS_AUDIO

VSS

BAT_N

SUBS

Ball Pad Type Description

K3, L3

P2

VSS

VSS

Ground connections for local oscillator

Ground connections for analogue circuitry

Ground connection for audio A1, D3 VSS

C3, F6-F10, G6-G10, H6-

H10, J3,J6-J10, K6-10, M3 VSS

B12

R3

Ground connection

Battery terminal -ve

VSS

Lithium ion/polymer battery negative terminal. Ground connection for switch-mode regulator

Connection to internal die substrate

Connect to lowest possible potential

Unconnected

Terminals

NC

Ball

G2, H1, J1, P4

Description

Leave unconnected

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Package Information

3.3

Package Dimensions

1

X

2 3 4

5

Top View

6 7 8 10 11 12 13 14 15

Y

F

15 14 13 12 11

Bottom View

10 8 7 6 5 4 3 2 1

PX 5

PY

E

E1

SE

G

D

SD

J

D1

H

0.2 Z

3

A1

A2

A3

A

Scale = 1mm

0.08 Z

Z

2

SEATING PLANE

Description

Size

169-Ball Thin Fine-Pitch Ball Grid Array (TFBGA)

8 x 8 x 1.2mm

0.5mm

Pitch

Package Ball Land

Solder mask defined. Solder mask aperture 275 μm Ø

Minimum Typical Dimension

G

H

E1

F

E e

D1

A3 b

D

A

A1

A2

J

PX

PY

X

Y

SD

SE

JEDEC

0.16

0.27

7.90

7.90

MO-195

0.21

0.21

0.7

0.32

8.00

8.00

0.5

7.00

7.00

0.50

0.50

0.50

0.50

0.35

0.35

0.5

0.5

1.35

0.85

Maximum

1.2

0.26

0.37

8.10

8.10

1

2

3

4

5

Notes

Dimension b is measured at the maximum solder ball diameter parallel to datum plane Z

Datum Z is defined by the spherical crowns of the solder balls

Parallelism measurement shall exclude any effect of mark on top surface of package

Top-side polarity mark. The dimensions of the square polarity mark are 0.75 x

0.75mm.

Bottom-side polarity mark. The dimensions of the triangular polarity mark are 0.3 x 0.3 x 0.42mm.

Unit

mm e

Figure 3.2: 169-ball TFBGA Package Dimensions

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Package Information

3.4

PCB Design and Assembly Considerations

This section lists recommendations to achieve maximum board-level reliability of the 8 x 8 x 1.2mm TFBGA 169ball package:

NSMD lands, i.e. lands smaller than the solder mask aperture, are preferred because of the greater

accuracy of the metal definition process compared to the solder mask process. With solder mask defined pads, the overlap of the solder mask on the land creates a step in the solder at the land interface, which can cause stress concentration and act as a point for crack initiation.

Ideally, via-in-pad technology should be used to achieve truly NSMD lands. Where this is not possible, a

maximum of one trace connected to each land is preferred and this trace should be as thin as possible –

taking into consideration its current carrying and the RF requirements.

35µm thick (1oz) copper lands are recommended rather than 17µm thick (0.5oz). This results in a greater standoff which has been proven to provide greater reliability during thermal cycling.

Land diameter should be the same as that on the package to achieve optimum reliability.

Solder paste is preferred to flux during the assembly process because this adds to the final volume of solder in the joint, increasing its reliability.

Where a nickel gold plating finish is used, the gold thickness should be kept below 0.5µm to prevent brittle gold/tin intermetallics forming in the solder.

3.5

Typical Solder Reflow Profile

See

Typical Solder Reflow Profile for Lead-free Devices

for information.

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Bluetooth Modem

4 Bluetooth Modem

4.1

RF Ports

4.1.1

RF_N and RF_P

RF_N and RF_P form a complementary balanced pair and are available for both transmit and receive. On transmit their outputs are combined using an external balun into the single-ended output required for the antenna. Similarly, on receive their input signals are combined internally.

Both terminals present similar complex impedances that may require matching networks between them and the balun. Viewed from the chip, the outputs can each be modelled as an ideal current source in parallel with a lossy capacitor. An equivalent series inductance can represent the package parasitics.

PA

_

+

RF Switch

RF_N

RF_P

RF Switch

LNA

+

_

Figure 4.1: Simplified Circuit RF_N and RF_P

RF_N and RF_P require an external DC bias. The DC level must be set at VDD_RADIO.

4.2

RF Receiver

The receiver features a near-zero IF architecture that allows the channel filters to be integrated onto the die. Sufficient out-of-band blocking specification at the LNA input allows the receiver to be used in close proximity to GSM and

W‑CDMA cellular phone transmitters without being desensitised. The use of a digital FSK discriminator means that

no discriminator tank is needed and its excellent performance in the presence of noise allows

BlueCore5‑Multimedia External to exceed the Bluetooth requirements for co-channel and adjacent channel rejection.

For EDR, the demodulator contains an ADC which digitises the IF received signal. This information is then passed

to the EDR modem.

4.2.1

Low Noise Amplifier

The LNA operates in differential mode and takes its input from the shared RF port.

4.2.2

RSSI Analogue to Digital Converter

The ADC implements fast AGC. The ADC samples the RSSI voltage on a slot-by-slot basis. The front-end LNA gain

is changed according to the measured RSSI value, keeping the first mixer input signal within a limited range. This

improves the dynamic range of the receiver, improving performance in interference limited environments.

4.3

RF Transmitter

4.3.1

IQ Modulator

The transmitter features a direct IQ modulator to minimise frequency drift during a transmit timeslot, which results

in a controlled modulation index. Digital baseband transmit circuitry provides the required spectral shaping.

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Bluetooth Modem

4.3.2

Power Amplifier

The internal PA has a maximum output power that allows BlueCore5‑Multimedia External to be used in Class 2 and

Class 3 radios without an external RF PA.

4.3.3

Transmit RF Power Control for Class 1 Applications (TX_PWR)

An 8-bit voltage DAC, AUX_DAC, controls the amplification level of the external PA for Class 1 operation. The

DAC output is derived from the on-chip band gap and is virtually independent of temperature and supply voltage.

Equation 4.1 and Equation 4.2 show the the output voltage:

V

DAC

= MIN

((

3.7V ×

EXT_PA_GAIN

255

− 0.008 × I

)

, PIOSupply − 0.008 × I

)

Equation 4.1: Output Voltage with Load Current I or

V

DAC

= MIN

((

3.7V × EXT_PA_GAIN

)

, PIO Supply

)

Equation 4.2: Output Voltage with No Load Current

Note:

PIOSupply = VDD_PIO

BlueCore5‑Multimedia External enables the external PA only when transmitting. Before transmitting, the chip normally ramps up the power to the internal PA, then it ramps it down again afterwards. However, if a suitable external

PA is used, it may be possible to ramp the power externally by driving the TX_PWR pin on the PA from AUX_DAC.

TX Power t carrier

Modulation

Figure 4.2: Internal Power Ramping

The PS Key PSKEY_TX_GAINRAMP, is used to control the delay, in units of μs, between the end of the transmit

power ramp and the start of modulation.

PS Key TXRX_PIO_CONTROL controls external RF components such as a switch, an external PA or an external

LNA. PIO[0], PIO[1] and the AUX_DAC can be used for this purpose, as Table 4.1 shows.

TXRX_PIO_CONTROL Value

0

1

2

3

4

PIO and AUX_DAC Use

PIO[0], PIO[1], and AUX_DAC not used to control RF. Power ramping is

internal.

PIO[0] is high during RX, PIO[1] is high during TX. AUX_DAC not used.

Power ramping is internal.

PIO[0] is high during RX, PIO[1] is high during TX. AUX_DAC used to set gain of external PA. Power ramping is external.

PIO[0] is low during RX, PIO[1] is low during TX. AUX_DAC used to set gain of external PA. Power ramping is external.

PIO[0] is high during RX, PIO[1] is high during TX. AUX_DAC used to set gain of external PA. Power ramping is internal.

Table 4.1: TXRX_PIO_CONTROL Values

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Bluetooth Modem

4.4

Bluetooth Radio Synthesiser

The Bluetooth radio synthesiser is fully integrated onto the die with no requirement for an external VCO screening

can, varactor tuning diodes, LC resonators or loop filter. The synthesiser is guaranteed to lock in sufficient time

across the guaranteed temperature range to meet the Bluetooth v2.1 + EDR specification.

4.5

Baseband

4.5.1

Burst Mode Controller

During transmission the BMC constructs a packet from header information previously loaded into memory-mapped

registers by the software and payload data/voice taken from the appropriate ring buffer in the RAM. During reception,

the BMC stores the packet header in memory-mapped registers and the payload data in the appropriate ring buffer

in RAM. This architecture minimises the intervention required by the processor during transmission and reception.

4.5.2

Physical Layer Hardware Engine

Dedicated logic performs the following:

Forward error correction

Header error control

Cyclic redundancy check

Encryption

Data whitening

Access code correlation

Audio transcoding

Firmware performs the following voice data translations and operations:

A-law/µ-law/linear voice data (from host)

A-law/µ-law/CVSD (over the air)

Voice interpolation for lost packets

Rate mismatch correction

The hardware supports all optional and mandatory features of Bluetooth v2.1 + EDR specification including AFH

and eSCO.

4.6

Basic Rate Modem

The basic rate modem satisfies the basic data rate requirements of the Bluetooth v2.1 + EDR specification. The basic rate was the standard data rate available on the Bluetooth v1.2 specification and below, it is based on

GFSK modulation scheme.

Including the basic rate modem allows BlueCore5‑Multimedia External compatibility with earlier Bluetooth products.

The basic rate modem uses the RF ports, receiver, transmitter and synthesiser, alongside the baseband components

described in Section 4.5.

4.7

Enhanced Data Rate Modem

The EDR modem satisfies the requirements of the Bluetooth v2.1 + EDR specification. EDR has been introduced to provide 2x and 3x data rates with minimal disruption to higher layers of the Bluetooth stack.

BlueCore5‑Multimedia External supports both the basic and enhanced data rates and is compliant with the Bluetooth v2.1 + EDR specification.

At the baseband level, EDR utilises both the same 1.6kHz slot rate and the 1MHz symbol rate as defined for the basic data rate. EDR differs in that each symbol in the payload portion of a packet represents 2 or 3 bits. This is

achieved using 2 new distinct modulation schemes. Table 4.2 and Figure 4.3 summarise these. Link Establishment

and management are unchanged and still use GFSK for both the header and payload portions of these packets.

The enhanced data rate modem uses the RF ports, receiver, transmitter and synthesiser, with the baseband

components described in Section 4.5.

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Bluetooth Modem

Data Rate Scheme

Basic Rate

EDR

EDR

Bits Per Symbol

1

2

3

Table 4.2: Data Rate Schemes

Modulation

GFSK

π/4 DQPSK

8DPSK (optional)

Basic Rate

Access Code Header Payload

Enhanced Data Rate

Access Code Header Guard Sync Payload

/4 DQPSK or 8DPSK

Figure 4.3: BDR and EDR Packet Structure

Trailer

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Clock Generation

5 Clock Generation

BlueCore5‑Multimedia External requires a Bluetooth reference clock frequency of 12MHz to 52MHz from either an

externally connected crystal or from an external TCXO source.

All BlueCore5‑Multimedia External internal digital clocks are generated using a phase locked loop, which is locked to the frequency of either the external 12MHz to 52MHz reference clock source or an internally generated watchdog clock frequency of 1kHz.

The Bluetooth operation determines the use of the watchdog clock in low-power modes.

5.1

Clock Architecture

Reference Clock

Bluetooth

Radio

Auxiliary

PLL

Digital

Circuitry

Figure 5.1: Clock Architecture

5.2

Input Frequencies and PS Key Settings

BlueCore5‑Multimedia External should be configured to operate with the chosen reference frequency. Do this by

setting the PS Key PSKEY_ANA_FREQ for all frequencies with an integer multiple of 250kHz. The input frequency

default setting in BlueCore5‑Multimedia External is 26MHz depending on the software build. Full details are in the software release note for the specific build from www.csrsupport.com

.

The following CDMA/3G phone TCXO frequencies are also catered for: 14.40, 15.36, 16.2, 16.8, 19.2, 19.44, 19.68,

19.8 and 38.4MHz. The value of the PS Key is a multiple of 1kHz, so 38.4MHz is selected by using a PS Key value

of 38400.

Reference Crystal Frequency (MHz)

14.40

15.36

16.20

16.80

19.20

19.44

19.68

19.80

38.40

n x 0.25

26.00 (default)

PSKEY_ANA_FREQ (kHz)

14400

15360

16200

16800

19200

19440

19680

19800

38400 n x 250

26000

Table 5.1: PS Key Values for CDMA/3G Phone TCXO

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Clock Generation

5.3

External Reference Clock

5.3.1

Input (XTAL_IN)

The external reference clock is applied to the BlueCore5‑Multimedia External XTAL_IN input.

BlueCore5‑Multimedia External is configured to accept the external reference clock at XTAL_IN by connecting

XTAL_OUT to ground. The external clock can be either a digital level square wave or sinusoidal, and this may be directly coupled to XTAL_IN without the need for additional components. A digital level reference clock gives superior noise immunity, as the high slew rate clock edges have lower voltage to phase conversion. If peaks of the reference

clock are either below VSS_ANA or above VDD_ANA, it must be driven through a DC blocking capacitor

(approximately 33pF) connected to XTAL_IN.

The external reference clock signal should meet the specifications in Table 5.2.

Frequency

(a)

Duty cycle

Edge jitter (at zero crossing)

AC coupled sinusoid

Signal level

V

IL

DC coupled

digital

V

IH

Min

12

20:80

-

0.4

-

-

Typ

26

50:50

-

-

VSS_ANA

(c)

VDD_ANA

(b)

(c)

Max

52

80:20

15

VDD_ANA

(b)

-

-

Unit

MHz ps rms

V pk-pk

V

V

Table 5.2: External Clock Specifications

(a) The frequency should be an integer multiple of 250kHz except for the CDMA/3G frequencies

(b)

VDD_ANA is 1.50V nominal

(c)

If driven via a DC blocking capacitor max amplitude is reduced to 750mV pk-pk for non 50:50 duty cycle

5.3.2

XTAL_IN Impedance in External Mode

The impedance of XTAL_IN does not change significantly between operating modes, typically 10fF. When

transitioning from deep sleep to an active state a spike of up to 1pC may be measured. For this reason CSR

recommends that a buffered clock input is used.

5.3.3

Clock Start-up Delay

BlueCore5‑Multimedia External hardware incorporates an automatic 5ms delay after the assertion of the system

clock request signal before running firmware, see Figure 5.2. This is suitable for most applications using an external

clock source. However, there may be scenarios where the clock cannot be guaranteed to either exist or be stable after this period. Under these conditions, BlueCore5‑Multimedia External firmware provides a software function that extends the system clock request signal by a period stored in PSKEY_CLOCK_STARTUP_DELAY. This value is set in milliseconds from 1ms to 31ms. Zero is the default entry for 5ms delay.

This PS Key allows the designer to optimise a system where clock latencies may be longer than 5ms while still

keeping the current consumption of BlueCore5‑Multimedia External as low as possible.

BlueCore5‑Multimedia External consumes about 2mA of current for the duration of

PSKEY_CLOCK_STARTUP_DELAY before activating the firmware.

5.3.4

Clock Timing Accuracy

As Figure 5.2 shows, the 250ppm timing accuracy on the external clock is required 2ms after the firmware begins

to run. This is to guarantee that the firmware can maintain timing accuracy in accordance with the Bluetooth v2.1 +

EDR specification. Radio activity may occur after 6ms after the firmware starts. Therefore, at this point the timing

accuracy of the external clock source must be within ±20ppm.

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Clock Generation

CLK_REQ

Firmware Activity

PSKEY_CLOCK_STARTUP_DELAY

Firmware Activity

Clock Accuracy ms After Firmware

Radio Activity

1000 ppm

0

250 ppm

2

20 ppm

6

Figure 5.2: TCXO Clock Accuracy

5.4

Crystal Oscillator (XTAL_IN, XTAL_OUT)

BlueCore5‑Multimedia External contains a crystal driver circuit. This operates with an external crystal and capacitors to form a Pierce oscillator. The external crystal is connected to pins XTAL_IN, XTAL_OUT.

g m

-

C trim

C int

C t2

C t1

Figure 5.3: Crystal Driver Circuit

Figure 5.4 shows an electrical equivalent circuit for a crystal. The crystal appears inductive near its resonant

frequency. It forms a resonant circuit with its load capacitors.

C m

L m

R m

C o

Figure 5.4: Crystal Equivalent Circuit

The resonant frequency may be trimmed with the crystal load capacitance. BlueCore5‑Multimedia External contains variable internal capacitors to provide a fine trim.

Parameter

Frequency

Initial Tolerance

Pullability

Min

16

-

-

Typ

26

±25

±20

Max

26

-

-

Unit

MHz ppm ppm/pF

Table 5.3: Crystal Specification

The BlueCore5‑Multimedia External driver circuit is a transconductance amplifier. A voltage at XTAL_IN generates a current at XTAL_OUT. The value of transconductance is variable and may be set for optimum performance.

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Clock Generation

5.4.1

Load Capacitance

For resonance at the correct frequency the crystal should be loaded with its specified load capacitance, which is defined for the crystal. This is the total capacitance across the crystal viewed from its terminals.

BlueCore5‑Multimedia External provides some of this load with the capacitors C trim

and C int be from the external capacitors labelled C t1

and C t2

. C t1

. The remainder should

should be three times the value of C t2

for best noise performance. This maximises the signal swing and slew rate at XTAL_IN (to which all on-chip clocks are referred).

Crystal load capacitance, C l

is calculated with Equation 5.1:

C l

= C int

+

(C t2

C t2

+ C trim

+ C trim

) C

+ C t1 t1

Equation 5.1: Load Capacitance

Note:

C trim

= 3.4pF nominal (mid-range setting)

C int

= 1.5pF

C int

does not include the crystal internal self capacitance; it is the driver self capacitance.

5.4.2

Frequency Trim

BlueCore5‑Multimedia External enables frequency adjustments to be made. This feature is typically used to remove initial tolerance frequency errors associated with the crystal. Frequency trim is achieved by adjusting the crystal load capacitance with an on-chip trim capacitor, C

Its value is calculated as follows: trim

. The value of C trim

is set by a 6-bit word in the PSKEY_ANA_FTRIM.

C trim

= 125fF × PSKEY_ANA_FTRIM

Equation 5.2: Trim Capacitance

The C trim

capacitor is connected between XTAL_IN and ground. When viewed from the crystal terminals, the combination of the tank capacitors and the trim capacitor presents a load across the terminals of the crystal which varies in steps of typically 125fF for each least significant bit increment of PSKEY_ANA_FTRIM.

Equation 5.3 describes the frequency trim.

Δ(F

F x x

)

= pullability × 0.110 ×

(

C t1

+ C

C t1 t2

+ C trim

)

(ppm/LSB)

Equation 5.3: Frequency Trim

Note:

F x

= crystal frequency

Pullability is a crystal parameter with units of ppm/pF

Total trim range is 0 to 63

If not specified, the pullability of a crystal may be calculated from its motional capacitance with Equation 5.4.

( )

( )

=

F

X

2

(

C

I

C m

+ C

0

)

2

Equation 5.4: Pullability

Note:

C

0

= Crystal self capacitance (shunt capacitance)

C m

= Crystal motional capacitance (series branch capacitance in crystal model), see Figure 5.4

It is a Bluetooth requirement that the frequency is always within ±20ppm. The trim range should be sufficient to pull the crystal within ±5ppm of the exact frequency. This leaves a margin of ±15ppm for frequency drift with ageing and temperature. A crystal with an ageing and temperature drift specification of better than ±15ppm is

required.

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Clock Generation

5.4.3

Transconductance Driver Model

The crystal and its load capacitors should be viewed as a transimpedance element, whereby a current applied to one terminal generates a voltage at the other. The transconductance amplifier in BlueCore5‑Multimedia External uses the voltage at its input, XTAL_IN, to generate a current at its output, XTAL_OUT. Therefore, the circuit will oscillate if the transconductance, transimpedance product is greater than unity. For sufficient oscillation amplitude, the product should be greater than three. The transconductance required for oscillation is defined by the relationship

shown in Equation 5.5.

g m

> 3

(2πF x

)

2

R m

((C

0

+ C int

)(C

C t1 t1

+ C

(C t2 t2

+ C

+ C trim

) trim

) + C t1

(C t2

+ C trim

))

Equation 5.5: Transconductance Required for Oscillation

BlueCore5‑Multimedia External guarantees a transconductance value of at least 2mA/V at maximum drive level.

Note:

More drive strength is required for higher frequency crystals, higher loss crystals (larger R m capacitance loading

) or higher

Optimum drive level is attained when the level at XTAL_IN is approximately 1V pk-pk. The drive level is determined by the crystal driver transconductance.

5.4.4

Negative Resistance Model

An alternative representation of the crystal and its load capacitors is a frequency dependent resistive element. The driver amplifier may be considered as a circuit that provides negative resistance. For oscillation, the value of the negative resistance must be greater than that of the crystal circuit equivalent resistance. Although the

BlueCore5‑Multimedia External crystal driver circuit is based on a transimpedance amplifier, an equivalent negative

resistance can be calculated for it using Equation 5.6.

R neg

> g m

(2πF x

)

2

(C

0

+ C int

)((C

C t1

(C t2 t1

+ C

+ C t2 trim

)

+ C trim

) + C t1

(C t2

+ C trim

))

2

Equation 5.6: Equivalent Negative Resistance

This formula shows the negative resistance of the BlueCore5‑Multimedia External driver as a function of its drive strength.

The value of the driver negative resistance may be easily measured by placing an additional resistance in series with the crystal. The maximum value of this resistor (oscillation occurs) is the equivalent negative resistance of the oscillator.

5.4.5

Crystal PS Key Settings

The BlueCore5‑Multimedia External firmware automatically controls the drive level on the crystal circuit to achieve optimum input swing. The PSKEY_XTAL_TARGET_AMPLITUDE is used by the firmware to servo the required amplitude of crystal oscillation. Refer to the software build release note for a detailed description.

BlueCore5‑Multimedia External should be configured to operate with the chosen reference frequency.

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Bluetooth Stack Microcontroller

6 Bluetooth Stack Microcontroller

A 16-bit RISC MCU is used for low power consumption and efficient use of memory.

The MCU, interrupt controller and event timer run the Bluetooth software stack and control the Bluetooth radio and

host interfaces.

6.1

Programmable I/O Ports, PIO and AIO

18 lines of programmable bidirectional I/O are provided.

Note:

PIO[15:4] are powered from VDD_PADS and PIO[3:0] are powered from VDD_PIO. AIO[1:0] are powered from

VDD_ANA.

Any of the PIO lines can be configured as interrupt request lines or as wake-up lines from sleep modes. PIO[6] or

PIO[2] can be configured as a request line for an external clock source. Using

PSKEY_CLOCK_REQUEST_ENABLE, this terminal can be configured to be low when

BlueCore5‑Multimedia External is in deep sleep and high when a clock is required.

Note:

CSR cannot guarantee that the PIO assignments remain as described. Refer to the relevant software release note for the implementation of these PIO lines, as they are firmware build-specific.

BlueCore5‑Multimedia External has 2 general-purpose analogue interface pins, AIO[1:0], used to access internal

circuitry and control signals. Auxiliary functions available on the analogue interface include a 10-bit ADC and a 8-bit

DAC. Signals selectable on this interface include the band gap reference voltage and a variety of clock signals: 64,

48, 32, 24, 16, 12, 8, 6 and 2MHz (outputted from AIO[0] only) and the XTAL and XTAL/2 clock frequency (outputted from AIO[0] and AIO[1]). When used with analogue signals the voltage range is constrained by the analogue supply voltage. When configured to drive out digital level signals (clocks) generated from within the analogue part of the device, the output voltage level is determined by VDD_ANA.

6.2

TCXO Enable OR Function

An OR function exists for clock enable signals from a host controller and BlueCore5‑Multimedia External where

either device can turn on the clock without having to wake up the other device, see Figure 6.1. PIO[3] can be used

as the host clock enable input and PIO[2] can be used as the OR output with the TCXO enable signal from

BlueCore5‑Multimedia External.

Note:

To turn on the clock, the clock enable signal on PIO[3] must be high.

VDD

GSM System

TCXO

CLK IN

CLK REQ OUT

Enable

CS-121064-DSP4

BlueCore System

CLK REQ IN / PIO[3]

CLK REQ OUT / PIO[2]

CLK IN

Figure 6.1: Example TCXO Enable OR Function

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Bluetooth Stack Microcontroller

On reset and up to the time the PIO has been configured, PIO[2] is tristate. Therefore, the developer must ensure

that the circuitry connected to this pin is pulled via a 470kΩ resistor to the appropriate power rail. This ensures that

the TCXO is oscillating at start up.

6.3

WLAN Coexistence Interface

Dedicated hardware is provided to implement a variety of WLAN coexistence schemes. Channel skipping AFH,

priority signalling, channel signalling and host passing of channel instructions are all supported. The features are configured in firmware.

For more information see

Bluetooth and IEEE 802.11 b/g Co-existence Solutions Overview

.

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Kalimba DSP

7 Kalimba DSP

The Kalimba DSP is an open platform Kalimba DSP allowing signal processing functions to be performed on overair data or codec data in order to enhance audio applications. Figure 7.1 shows the Kalimba DSP interfaces to other

functional blocks within BlueCore5‑Multimedia External.

Kalimba DSP Core

Memory

Management Unit

MCU Register Interface (including Debug)

DSP MMU Port

DSP, MCU and Flash Window Control

Programmable Clock = 64MHz

Data Memory

Interface

Address

Generators

Instruction Decode

Program Flow

Clock Select

DEBUG

PIO

Internal Control Registers

MMU Interface

Interrupt Controller

Timer

MCU Window

Flash Window

ALU

PIO In/Out

IRQ to Subsystem

IRQ from Subsystem

1µs Timer Clock

DSP RAMs

DM2

DM1

PM

DSP Data Memory 2 Interface (DM2)

DSP Data Memory 1 Interface (DM1)

DSP Program Memory Interface (PM)

Figure 7.1: Kalimba DSP Interface to Internal Functions

The key features of the DSP include:

64MIPS performance, 24-bit fixed point DSP core

Single cycle MAC of 24 x 24-bit multiply and 56-bit accumulate

32-bit instruction word

Separate program memory and dual data memory, allowing an ALU operation and up to two memory

accesses in a single cycle

Zero overhead looping

Zero overhead circular buffer indexing

Single cycle barrel shifter with up to 56-bit input and 24-bit output

Multiple cycle divide (performed in the background)

Bit reversed addressing

Orthogonal instruction set

Low overhead interrupt

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Memory Interface and Management

8 Memory Interface and Management

8.1

Memory Management Unit

The MMU provides a number of dynamically allocated ring buffers that hold the data that is in transit between the

host, the air or the Kalimba DSP. The dynamic allocation of memory ensures efficient use of the available RAM and

is performed by a hardware MMU to minimise the overheads on the processor during data/voice transfers.

8.2

System RAM

48KB of on-chip RAM supports the RISC MCU and is shared between the ring buffers used to hold voice/data for

each active connection and the general-purpose memory required by the Bluetooth stack.

8.3

Kalimba DSP RAM

Additional on-chip RAM is provided to support the Kalimba DSP:

16K x 24-bit for data memory 1 (DM1)

12K x 24-bit for data memory 2 (DM2)

6K x 32-bit for program memory (PM)

Note:

The Kalimba DSP can also execute directly from external flash, using a 64-instruction on-chip cache.

8.4

External Memory Driver

The External Memory Driver interface can be used to connect to the external flash memory and also to the optional

external RAM for memory intensive applications.

8.5

External Flash Memory (32Mb)

Up to 32Mb of external flash is available on the BlueCore5‑Multimedia External, though typically 8Mb is used. The

external flash memory is provided for system firmware and the Kalimba DSP coprocessor code implementation.

FLASH_RP# is the flash reset signal. This behaves in the same way as the hard reset but is delayed by a couple of clock cycles. It only moves during boot.

8.6

Off-chip Program Memory

The external memory port provides a facility to interface up to 32Mb of 16-bit external memory. This off-chip storage stores BlueCore5‑Multimedia External settings and program code. Flash is the storage mechanism typically used

by BlueCore5‑Multimedia External modules. However external masked ROM may also be used if the host takes

over responsibility for storing configuration data.

The external memory port is:

16 bidirectional data lines, D[15:0]

21 output address lines, A[20:0]

3 active low output control signals, WE#, CE# and OE#

WE# is asserted when data is written to external memory

OE# is asserted when data is read from external memory

The chip select line CS# is asserted when any data transfer (read or write) is required

All of the external memory port connections are implemented using CMOS technology and use standard 0V to

VDD_MEM signal levels.

Note:

In addition to these hardware requirements, take care to ensure that the sector organisation of the extended memory has the correct format. A sector is defined as an individually erasable area of external flash.

Ensure that external memory devices meet certain minimum specifications, see Table 8.1.

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Memory Interface and Management

Parameter

Data width

Minimum capacity

Maximum access time

Value

16-bit

4Mb (256KW)

90ns @125°C 50pF load

110ns @85°C 10pF load

Table 8.1: Flash Device Hardware Requirements

8.6.1

Minimum Flash Specification

The flash device used with BlueCore5‑Multimedia External must meet the following criteria:

Either standard or extended form of the JEDEC (AMD/Fujitsu/SST) or Intel command set

Access time must be ≤90ns @125°C 50pF load or ≤110ns @85°C 10pF load (typically ≤ 70ns)

Write strobe of 100ns

Accessible in word mode, i.e. via a 16-bit data bus

Support changing different bits within each word from 1 to 0 in at least two separate programming operations

Programming and erase times must have fixed upper limits

Must be bottom boot or uniform sector

Must have independently erasable sectors with at least the following boundaries (see Memory Map for more information)

Word Address

0x00000 - 0x01FFF

0x02000 - 0x02FFF

0x03000 - 0x03FFF

0x04000 - 0x07FFF

0x08000 - 0x0FFFF

0x10000 - 0x17FFF

0x18000 - .......

Size (KW)

8

4

4

16

32

32

Don't care

Table 8.2: Flash Sector Boundaries

Important Note:

As well as satisfying the criteria in Section 8.6.1 a device must also support the Common Flash Interface described in Section 8.6.2 or be supported in the BlueCore5‑Multimedia External firmware and host-side tools.

8.6.2

Common Flash Interface

The firmware can adapt automatically to work with some flash devices, when the flash device satisfies the minimum

flash specification described in Section 8.6.1 and it meets the following criteria:

The device must support the Common Flash Interface, as defined by JEDEC standard JESD68.

The device must return one of the following codes for either the Primary or Alternative Algorithm Command

Set (offset

0x13b

or

0x17

of the Query Structure Output):

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Memory Interface and Management

Code

0x0001

0x0002

0x0003

0x0701

Description

Intel/Sharp Extended Command Set

AMD/Fujitsu Standard Command Set

Intel Standard Command Set

AMD/Fujitsu Extended Command Set

Table 8.3: Common Flash Interface Algorithm Command Set Codes

The device must return one of the following patterns of Erase Block Region Information (beginning at offset

0x2d

of the Query Structure Output).

Erase Block Region

1

Erase Block Region

1

Number of Erase Blocks

128, 256, 512 or 1024

Table 8.4: Erase Block Region Information for Uniform 2KW Sectors

Number of Erase Blocks

256, 512, 1024 or 2048

Block Size

4KB

Block Size

2KB

Erase Block Region

1

2

Table 8.5: Erase Block Region Information for Uniform 1KW Sectors

Number of Erase Blocks

8

7, 15, 31 or 63

Block Size

8KB

64KB

Table 8.6: Erase Block Region Information for 8 x 4KW, n x 32KW Sectors

Erase Block Region

1

2

3

4

Number of Erase Blocks

1

2

1

7, 15, 31 or 63

Block Size

16KB

8KB

32KB

64KB

Table 8.7: Erase Block Region Information for 1 x 8KW, 2 x 4KW, 1 x 16KW, n x 32KW Sectors

Important Note:

If any of these criteria is not met, then the device will not work unless it is supported by the

BlueCore5‑Multimedia External firmware.

8.6.3

Virtual Machine Requirements

Note:

The minimum requirements for external Flash are shown in Table 8.1 and Section 8.6.1, these figures are based

on running Bluetooth HCI stack.

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Memory Interface and Management

BlueCore5‑Multimedia External can run VM applications and as part of the VM configuration the internal processing clock speed and number of memory wait states can be set. To maximise VM application performance it may be

necessary to:

Use 70ns flash devices

Set 2 wait states

Set the clock to 32MHz

8.6.4

Memory Timing

Table 8.8 and Figure 8.1 show memory write cycle timing for BlueCore5‑Multimedia External.

Symbol t wc t dat:su t dat:hd t addr:su t we:low

Parameter

Write cycle time

Data set-up time

Data hold time

Address set-up time

WE# low

Minimum

(a)

300

150

150

150

100

Typical

-

-

-

-

-

Maximum

(a)

-

-

-

-

-

Unit ns ns ns ns ns

(a)

Valid for temperatures between -40 and 85°C

Table 8.8: Memory Write Cycle

A[18:0] t wc

Address Valid

CS# t we:low t dat:hd t addr:su

WE#

OE# t dat:su

D[15:0] Data Valid

Figure 8.1: Memory Write Cycle

Table 8.9 and Figure 8.2 show memory read cycle timing for BlueCore5‑Multimedia External.

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Memory Interface and Management

Minimum

(a)

114

-

-

Typical

125

-

-

-

Maximum

(a)

-

110

110

-

Unit ns ns ns ns

CS#

OE#

WE#

D[15:0] t re t dat:hd

Data Valid Data Valid

Figure 8.2: Memory Read Cycle

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Serial Interfaces

9 Serial Interfaces

9.1

UART Interface

BlueCore5‑Multimedia External has a standard UART serial interface that provides a simple mechanism for

communicating with other serial devices using the RS232 protocol.

UART_TX

UART_RX

UART_RTS

UART_CTS

Figure 9.1: Universal Asynchronous Receiver

Figure 9.1 shows the 4 signals that implement the UART function. When BlueCore5‑Multimedia External is

connected to another digital device, UART_RX and UART_TX transfer data between the 2 devices. The remaining

2 signals, UART_CTS and UART_RTS, can implement RS232 hardware flow control where both are active low indicators.

UART configuration parameters, such as baud rate and packet format, are set using BlueCore5‑Multimedia External

firmware.

Note:

To communicate with the UART at its maximum data rate using a standard PC, an accelerated serial port adapter card is required for the PC.

Parameter

Baud rate

Flow control

Parity

Number of stop bits

Bits per byte

Minimum

Maximum

Possible Values

1200 baud (≤2%Error)

9600 baud (≤1%Error)

4Mbaud (≤1%Error)

RTS/CTS or None

None, Odd or Even

1 or 2

8

Table 9.1: Possible UART Settings

The UART interface can reset BlueCore5‑Multimedia External on reception of a break signal. A break is identified

by a continuous logic low (0V) on the UART_RX terminal, as Figure 9.2 shows. If t

BRK

is longer than the value, defined by PSKEY_HOSTIO_UART_RESET_TIMEOUT, a reset occurs. This feature allows a host to initialise the system to a known state. Also, BlueCore5‑Multimedia External can emit a break character that may be used to wake the host.

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Serial Interfaces t

BRK

UART RX

Figure 9.2: Break Signal

Note:

The DFU boot loader must be loaded into the flash device before the UART or USB interfaces can be used.

This initial flash programming can be done via the SPI.

Table 9.2 shows a list of commonly used baud rates and their associated values for the PSKEY_UART_BAUDRATE.

There is no requirement to use these standard values. Any baud rate within the supported range can be set in the

PS Key according to the formula in Equation 9.1.

Baud Rate

76800

115200

230400

460800

921600

1382400

1843200

2764800

3686400

1200

2400

4800

9600

19200

38400

57600

Equation 9.1: Baud Rate

0x013b

0x01d8

0x03b0

0x075f

0x0ebf

0x161e

0x1d7e

0x2c3d

0x3afb

Hex

0x0005

Persistent Store Value

Dec

5

0x000a

0x0014

10

20

0x0027

0x004f

0x009d

0x00ec

39

79

157

236

3775

5662

7550

11325

15099

315

472

944

1887

Error

0.14%

0.03%

0.03%

-0.02%

0.00%

-0.01%

0.00%

0.00%

0.00%

1.73%

1.73%

1.73%

-0.82%

0.45%

-0.18%

0.03%

Table 9.2: Standard Baud Rates

9.1.1

UART Configuration While Reset is Active

The UART interface for BlueCore5‑Multimedia External is tristate while the chip is being held in reset. This allows the user to daisy chain devices onto the physical UART bus. The constraint on this method is that any devices

connected to this bus must tristate when BlueCore5‑Multimedia External reset is de-asserted and the firmware begins to run.

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Serial Interfaces

9.1.2

UART Bypass Mode

Host Processor

RXD

CTS

RTS

TXD

UART Bypass

RST#

UART_TX

UART_RTS

UART_CTS

UART_RX

PIO4

PIO5

PIO6

PIO7

UART

Another Device

TX

RTS

CTS

RX

Test Interface

Figure 9.3: UART Bypass Architecture

Alternatively, for devices that do not tristate the UART bus, the UART bypass mode on

BlueCore5‑Multimedia External can be used. The default state of BlueCore5‑Multimedia External after reset is de-

asserted; this is for the host UART bus to be connected to the BlueCore5‑Multimedia External UART, thereby allowing communication to BlueCore5‑Multimedia External via the UART. All UART bypass mode connections are

implemented using CMOS technology and have signalling levels of 0V and VDD_PADS.

To apply the UART bypass mode, a BCCMD command is issued to BlueCore5‑Multimedia External. Upon this issue,

it switches the bypass to PIO[7:4] as Figure 9.3 shows. When the bypass mode has been invoked,

BlueCore5‑Multimedia External enters the deep sleep state indefinitely.

To re-establish communication with BlueCore5‑Multimedia External, the chip must be reset so that the default configuration takes effect.

It is important for the host to ensure a clean Bluetooth disconnection of any active links before the bypass mode is invoked. Therefore, it is not possible to have active Bluetooth links while operating the bypass mode.

Note:

When in bypass mode, the UART signal levels on the PIO are at VDD_PADS level and when not bypassed, i.e.

when using the normal UART pins, the levels are at VDD_USB levels.

9.1.3

Current Consumption in UART Bypass Mode

The current consumption for a device in UART bypass mode is equal to the values quoted for a device in standby

mode.

9.2

USB Interface

BlueCore5‑Multimedia External has a full-speed (12Mbps) USB interface for communicating with other compatible digital devices. The USB interface on the BlueCore5‑Multimedia External acts as a USB peripheral, responding to

requests from a master host controller.

BlueCore5‑Multimedia External supports the

Universal Serial Bus Specification, Revision v2.0 (USB v2.0

Specification)

, available from http://www.usb.org

. For more information on how to integrate the USB interface on

BlueCore5‑Multimedia External see the

Bluetooth and USB Design Considerations Application Note

.

As well as describing USB basics and architecture, the application note describes:

Power distribution for high and low bus-powered configurations

Power distribution for self-powered configuration, which includes USB VBUS monitoring

USB enumeration

Electrical design guidelines for the power supply and data lines, as well as PCB tracks and the effects of

ferrite beads

USB suspend modes and Bluetooth low-power modes:

Global suspend

Selective suspend, includes remote wake

Wake on Bluetooth, includes permitted devices and set-up prior to selective suspend

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Serial Interfaces

3

4

1

2

5

Suspend mode current draw

PIO status in suspend mode

Resume, detach and wake PIOs

Battery charging from USB, which describes dead battery provision, charge currents, charging in suspend modes and USB VBUS voltage consideration

USB termination when interface is not in use

Internal modules, certification and non-specification compliant operation

9.3

Programming and Debug Interface

Important Note:

The SPI is used to program and configure (PS Keys), and debug the BlueCore5‑Multimedia External. It is

required in production. Ensure the 4 SPI signals are brought out to either test points or a header.

CSR provides development and production tools to communicate over the SPI from a PC, although a level translator circuit is often required. All are available from CSR.

BlueCore5‑Multimedia External uses a 16-bit data and 16-bit address programming and debug interface.

Transactions can occur when the internal processor is running or is stopped.

Data may be written or read one word at a time, or the auto-increment feature is available for block access.

9.3.1

Instruction Cycle

The BlueCore5‑Multimedia External is the slave and receives commands on SPI_MOSI and outputs data on

SPI_MISO. Table 9.3 shows the instruction cycle for a SPI transaction.

Reset the SPI interface

Write the command word

Write the address

Write or read data words

Termination

Hold SPI_CS# high for two SPI_CLK cycles

Take SPI_CS# low and clock in the 8-bit command

Clock in the 16-bit address word

Clock in or out 16-bit data word(s)

Take SPI_CS# high

Table 9.3: Instruction Cycle for a SPI Transaction

With the exception of reset, SPI_CS# must be held low during the transaction. Data on SPI_MOSI is clocked into the BlueCore5‑Multimedia External on the rising edge of the clock line SPI_CLK. When reading,

BlueCore5‑Multimedia External replies to the master on SPI_MISO with the data changing on the falling edge of the

SPI_CLK. The master provides the clock on SPI_CLK. The transaction is terminated by taking SPI_CS# high.

Sending a command word and the address of a register for every time it is to be read or written is a significant overhead, especially when large amounts of data are to be transferred. To overcome this

BlueCore5‑Multimedia External offers increased data transfer efficiency via an auto increment operation. To invoke auto increment, SPI_CS# is kept low, which auto increments the address, while providing an extra 16 clock cycles for each extra word to be written or read.

9.3.2

Multi-slave Operation

BlueCore5‑Multimedia External should not be connected in a multi-slave arrangement by simple parallel connection

of slave MISO lines. When BlueCore5‑Multimedia External is deselected (SPI_CS# = 1), the SPI_MISO line does

not float. Instead, BlueCore5‑Multimedia External outputs

0

if the processor is running or

1

if it is stopped.

9.4

I²C Interface

9.4.1

Software I²C Interface

PIO[8:6] can be used to form a master I²C interface. The interface is formed using software to drive these lines.

Therefore it is suited only to relatively slow functions such as driving a dot matrix LCD, keyboard scanner or

EEPROM.

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Serial Interfaces

PIO

PIO

[

[

8

6

]

]

PIO [ 7 ]

+1.8V

Decoupling

Capacitor

8

VCC

A0

1

7

WP A1

2

6

SCL A2

3

5

SDA GND

Serial EEPROM

(24AA32)

4

Figure 9.4: Example EEPROM Connection

9.4.2

Bit-serialiser Interface

In addition to the software I²C interface outlined in Section 9.4.1, the BlueCore5‑Multimedia External includes a

configurable hardware bit-serialiser interface. Any 3 PIOs can be used as a serial master interface by configuring

the hardware bit-serialiser. In the I²C master mode, the hardware bit-serialiser supports address, direction and

ACK handling, but does not support multi-master I²C bus systems. I²C slave mode is also not supported.

Note:

The I²C interface can be directly controlled by the MCU or the Kalimba DSP.

Suitable firmware is required to support the hardware bit-serialiser interface.

I²C and SPI are supported.

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Audio Interface

10 Audio Interface

The audio interface circuit consists of:

Stereo audio codec

Dual audio inputs and outputs

A configurable PCM, I²S or SPDIF interface

Figure 10.1 shows the functional blocks of the interface. The codec supports stereo playback and recording of audio signals at multiple sample rates with a resolution of 16-bit. The ADC and the DAC of the codec each contain 2 independent channels. Any ADC or DAC channel can be run at its own independent sample rate.

Stereo Codec

PCM PCM Interface

Memory

Management

Unit

MMU Voice Port

Voice Port

MCU Register Interface

Registers

Digital

Audio

Stereo

Audio

Codec

Driver

Left DAC

Right DAC

Left ADC

Right ADC

Figure 10.1: Audio Interface

The interface for the digital audio bus shares the same pins as the PCM codec interface described in Section 10.3

which means each of the audio buses are mutually exclusive in their usage. Table 10.1 lists these alternative

functions.

PCM Interface

PCM_OUT

PCM_IN

PCM_SYNC

PCM_CLK

-

-

SPDIF Interface

SPDIF_OUT

SPDIF_IN

I²S Interface

SD_OUT

SD_IN

WS

SCK

Table 10.1: Alternative Functions of the Digital Audio Bus Interface on the PCM Interface

10.1

Audio Input and Output

The audio input circuitry consists:

2 independent channels programmed for either microphone or line input

Each channel is independently configurable to be either single-ended or fully differential

Each channel has an analogue and digital programmable gain stage for optimisation of different microphones

The audio output circuitry consists of a dual differential class A-B output stage.

10.2

Stereo Audio Codec Interface

The main features of the interface are:

Stereo and mono analogue input for voice band and audio band

Stereo and mono analogue output for voice band and audio band

Support for stereo digital audio bus standards such as I²S

Support for IEC-60958 standard stereo digital audio bus standards, e.g. SPDIF and AES3/EBU

Support for PCM interfaces including PCM master codecs that require an external system clock

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Audio Interface

Important Note:

To avoid any confusion regarding stereo operation this data sheet explicitly states which is the left and right channel for audio input and output. With respect to software and any registers, channel 0 or channel A represents the left channel and channel 1 or channel B represents the right channel for both input and output.

10.2.1 Stereo Audio Codec Block Diagram

MIC_A_P

Input

Amplifier

ΣΔ -ADC

MIC_A_N

LP Filter

SPKR_A_P

SPKR_A_N

Output

Amplifier

ΣΔ - DAC

Digital

Circuitry

MIC_B_P

MIC_B_N

Input

Amplifier

ΣΔ -ADC

LP Filter

SPKR_B_P

SPKR_B_N

Output

Amplifier

ΣΔ - DAC

Figure 10.2: Stereo Codec Audio Input and Output Stages

The stereo audio codec uses a fully differential architecture in the analogue signal path, which results in low noise

sensitivity and good power supply rejection while effectively doubling the signal amplitude. It operates from a single power-supply of 1.5V and uses a minimum of external components.

10.2.2 Stereo Codec Set-up

The configuration and control of the ADC is through VM functions described in appropriate BlueLab Multimedia

documentation. This section is an overview of the parameters that can be set up using the VM functions.

The Kalimba DSP can communicate its codec requirements to the MCU, and therefore also to the VM, by exchange

of messages. The messages used between the Kalimba DSP and the embedded MCU are based on interrupts:

1 interrupt between the MCU and Kalimba DSP

1 interrupt between the Kalimba DSP and the MCU

Message content is transmitted using shared memory. There are VM and DSP library functions to send and receive messages; refer to BlueLab Multimedia documentation for further details.

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Audio Interface

10.2.3 ADC

The ADC consists of:

2 second-order Sigma-Delta converters allowing 2 separate channels that are identical in functionality, as

Figure 10.2 shows.

2 gain stages for each channel, 1 of which is an analogue gain stage and the other is a digital gain stage.

10.2.4 ADC Sample Rate Selection

Each ADC supports the following sample rates:

8kHz

11.025kHz

16kHz

22.05kHz

24kHz

32kHz

44.1kHz

10.2.5 ADC Digital Gain

The digital gain stage has a programmable selection value in the range of 0 to 15 with the associated ADC gain

settings summarised in Table 10.2. There is also a high resolution digital gain mode that allows the gain to be

changed in 1/32dB steps. Contact CSR for more information.

Gain Selection Value

6

7

4

5

0

1

2

3

ADC Digital Gain Setting

(dB)

0

3.5

6

9.5

12

15.5

18

21.5

Gain Selection Value

14

15

12

13

8

9

10

11

ADC Digital Gain Setting

(dB)

-24

-20.5

-18

-14.5

-12

-8.5

-6

-2.5

10.2.6 ADC Analogue Gain

Table 10.2: ADC Digital Gain Rate Selection

Figure 10.3 shows the equivalent block diagram for the ADC analogue amplifier. It is a two-stage amplifier:

The first stage amplifier has a selectable gain of either bypass for line input mode or gain of 24dB gain for the microphone mode.

The second stage has a programmable gain with seven individual 3dB steps. By combining the 24dB gain selection of the microphone input with the seven individual 3dB gain steps, the overall range of the analogue amplifier is approximately -3dB to 42dB in 3dB steps. The a VM function controls all the gain control of the

ADC.

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Audio Interface

Bypass or 24dB gain

P

N

-3dB to 18dB gain

P

N

Line Mode / Mic Mode

Switches shown for line mode

Microphone mode input impedance = 6kΩ

Line mode input impedance = 6kΩ to 30kΩ

Gain 0:7

Figure 10.3: ADC Analogue Amplifier Block Diagram

10.2.7 DAC

The DAC consists of:

2 second-order Sigma-Delta converters allowing 2 separate channels that are identical in functionality, as

Figure 10.2 shows.

2 gain stages for each channel, 1 of which is an analogue gain stage and the other is a digital gain stage.

10.2.8 DAC Sample Rate Selection

Each DAC supports the following samples rates:

8kHz

11.025kHz

12kHz

16kHz

22.050kHz

24kHz

32kHz

44.1kHz

48kHz

10.2.9 DAC Digital Gain

The digital gain stage has a programmable selection value in the range of 0 to 15 with associated DAC gain settings,

summarised in Table 10.3. There is also a high resolution digital gain mode that allows the gain to be changed in

1/32dB steps. Contact CSR for more information.

The overall gain control of the DAC is controlled by a VM function. Its setting is a combined function of the digital

and analogue amplifier settings.

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Audio Interface

Digital Gain Selection

Value

0

1

2

3

4

5

6

7

DAC Digital Gain Setting

(dB)

0

3.5

6

9.5

12

15.5

18

21.5

Digital Gain Selection

Value

8

9

10

11

12

13

14

15

DAC Digital Gain Setting

(dB)

-24

-20.5

-18

-14.5

-12

-8.5

-6

-2.5

10.2.10 DAC Analogue Gain

Table 10.3: DAC Digital Gain Rate Selection

As Table 10.4 shows the DAC analogue gain stage consists of 8 gain selection values that represent seven 3dB

steps.

The a VM function controls the overall gain control of the DAC. Its setting is a combined function of the digital and

analogue amplifier settings.

Analogue Gain Selection

Value

7

6

5

4

DAC Analogue Gain

Setting (dB)

3

0

-3

-6

Analogue Gain Selection

Value

3

2

1

0

DAC Analogue Gain

Setting (dB)

-9

-12

-15

-18

Table 10.4: DAC Analogue Gain Rate Selection

10.2.11 IEC 60958 Interface

The IEC 60958 interface is a digital audio interface that uses bi-phase coding to minimise the DC content of the

transmitted signal and allows the receiver to decode the clock information from the transmitted signal. The IEC 60958 specification is based on the 2 industry standards:

AES/EBU

Sony and Philips interface specification SPDIF

The interface is compatible with IEC 60958-1, IEC 60958-3 and IEC 60958-4.

The SPDIF interface signals are SPDIF_IN and SPDIF_OUT and are shared on the PCM interface pins. The input and output stages of the SPDIF pins can interface to:

A 75Ω coaxial cable with an RCA connector, see Figure 10.4

An optical link that uses Toslink optical components, see Figure 10.5.

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Audio Interface

SPDIF COAXIAL PC

CONN2

4

3

1

2

C26

150n

R15

120R

TN33

R16

560R

6

U4C

5

R17

560R

8

U4D

9

R18

560R

10

U4E

11

12

U4F

13

R19

100K

TN34

Figure 10.4: Example Circuit for SPDIF Interface (Co-Axial)

SPDIF TOSLINK TRANSMITTER

C24

3V3

100n

U5

INPUT 3

SPDIF_OUT (PCM_OUT)

SPDIF_OUT (PCM_OUT)

SPDIF TOSLINK RECEIVER

3V3

C25

100n

L3

47u

U6

OUT 1

SPDIF_IN (PCM_IN)

Figure 10.5: Example Circuit for SPDIF Interface (Optical)

10.2.12 Microphone Input

Figure 10.6 shows recommended biasing for each microphone. The microphone bias, MIC_BIAS, derives its power

from the BAT_P and requires a 1µF capacitor on its output.

Microphone Bias

R2

C1

C3

MIC_A_P

R1

C2

MIC_A_N

Input

Amplifier

C4

+

MIC1

Figure 10.6: Microphone Biasing

Note:

Figure 10.6 shows a single channel only.

The MIC_BIAS is like any voltage regulator and requires a minimum load to maintain regulation. The MIC_BIAS maintains regulation within the limits 0.200mA to 1.230mA. If the microphone sits below these limits, then the microphone output must be pre-loaded with a large value resistor to ground.

CS-121064-DSP4

R8

150R

C20

R9

150R

10n

8

D5

5

ESD PROTECTION

3

3V3 3V3

R10

1K

2

R11

1K

R12

10K

R13

10K

R14

470K

C21

1u

4

3

3V3 C22

100n

U3

1

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SPDIF_IN (PCM_IN)

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Audio Interface

The audio input is intended for use in the range from 1μA @ 94dB SPL to about 10μA @ 94dB SPL. With biasing

resistors R1 and R2 equal to 1kΩ, this requires microphones with sensitivity between about –40dBV and –60dBV.

The input impedance at MIC_A_N, MIC_A_P, MIC_B_N and MIC_B_P is typically 6.0kΩ.

C1 and C2 should be 150nF if bass roll-off is required to limit wind noise on the microphone.

R1 sets the microphone load impedance and is normally in the range of 1kΩ to 2kΩ.

R2, C3 and C4 improve the supply rejection by decoupling supply noise from the microphone. Values should be selected as required. R2 may be connected to a convenient supply, in which case the bias network is permanently enabled, or to the MIC_BIAS output (which is ground referenced and provides good rejection of the supply), which may be configured to provide bias only when the microphone is required.

Table 10.5 shows the 4-bit programmable output voltage that the microphone bias provides, and Table 10.6 shows

the 4-bit programmable output current.

The characteristics of the microphone bias include:

Power supply:

BlueCore5‑Multimedia External microphone supply is BAT_P

Minimum input voltage = Output voltage + drop-out voltage

Maximum input voltage is 4.4V

Typically the microphone bias is at the same level as VDD_AUDIO (1.5V)

Drop-out voltage:

300mV minimum

Guaranteed for configuration of voltage or current output shown in Table 10.5 and Table 10.6

Output voltage:

4-bit programmable between 1.7V to 3.6V

Tolerance 90 to 110%

Output current:

4-bit programmable from 200µA to 1.230mA

Maximum current guaranteed to be >1mA

Load capacitance:

■ Unconditionally stable for 1µF ± 20% and 2.2µF ± 20% pure C

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13

14

11

12

15

9

10

7

8

Output Step

0

1

2

5

6

3

4

VOL_SET[3:0]

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Min

-

Table 10.5: Voltage Output Steps

2.69

2.90

3.08

3.33

3.57

2.18

2.32

2.43

2.56

1.87

1.95

2.02

2.10

Typ

1.71

1.76

1.82

Audio Interface

V

V

V

V

V

V

V

V

V

V

V

V

V

Units

V

V

V

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

Max

-

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Audio Interface

13

14

11

12

15

9

10

7

8

Output Step

0

1

2

5

6

3

4

CUR_SET[3:0]

0000

1001

1010

1011

1100

1101

1110

1111

0101

0110

0111

1000

0001

0010

0011

0100 mA mA mA mA mA mA mA mA mA mA mA mA mA

Units mA mA mA

0.950

1.000

1.090

1.140

1.230

0.670

0.750

0.810

0.860

0.420

0.480

0.530

0.610

Typ

0.200

0.280

0.340

Table 10.6: Current Output Steps

Note:

For BAT_P, the PSRR at 100Hz to 22kHz, with >300mV supply headroom, decoupling capacitor of 1.1μF, is

typically 58.9dB and worst case 53.4dB.

For VDD_AUDIO, the PSRR at 100Hz to 22kHz, decoupling capacitor of 1.1μF, is typically 88dB and worst case

60dB.

10.2.13 Line Input

If the input analogue gain is set to less than 24dB, BlueCore5‑Multimedia External automatically selects line input mode. In line input mode the first stage of the amplifier is automatically disabled, providing additional power saving.

In line input mode the input impedance varies from 6kΩ to 30kΩ, depending on the volume setting. Figure 10.7 and

Figure 10.8 show 2 circuits for line input operation and show connections for either differential or single-ended inputs.

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Audio Interface

C1

MIC_A_P

C2

MIC_A_N

Figure 10.7: Differential Input

C1

MIC_A_P

C2

MIC_A_N

Figure 10.8: Single-ended Input

Note:

In Figure 10.7 and Figure 10.8 show only single channels.

10.2.14 Output Stage

The output stage digital circuitry converts the signal from 16-bit per sample, linear PCM of variable sampling

frequency to bit stream, which is fed into the analogue output circuitry.

The output stage circuit comprises a DAC with gain setting and class AB output stage amplifier. The output is

available as a differential signal between SPKR_A_N and SPKR_A_P for the left channel, as Figure 10.9 shows,

and between SPKR_B_N and SPKR_B_P for the right channel.

The output stage is capable of driving a speaker directly when its impedance is at least 8Ω and an external regulator is used, but this will be at a reduced output swing.

SPKR_A_P

SPKR_A_N

Figure 10.9: Speaker Output

Note:

Figure 10.9 shows a single channel only.

A 3-bit programmable resistive divider controls the analogue gain of the output stage, which sets the gain in steps of approximately 3dB.

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Audio Interface

10.2.15 Mono Operation

Mono operation is a single-channel operation of the stereo codec. The left channel represents the single mono

channel for audio in and audio out. In mono operation the right channel is the auxiliary mono channel that may be used in dual mono channel operation.

In single channel mono operation, disable the other channel to reduce power consumption.

Important Note:

For mono operation this data sheet uses the left channel for standard mono operation for audio input and output and with respect to software and any registers, channel 0 or channel A represents the standard mono channel for audio input and output. In mono operation the second channel which is the right channel, channel 1 or channel

B can be used as a second mono channel if required and this channel is referred to as the auxiliary mono channel for audio input and output.

10.2.16 Side Tone

In some applications it is necessary to implement side tone. This involves feeding an attenuated version of the

microphone signal to the earpiece. The BlueCore5‑Multimedia External codec contains side tone circuitry to do this.

The side tone hardware is configured through the following PS Keys:

PSKEY_SIDE_TONE_ENABLE

PSKEY_SIDE_TONE_GAIN

PSKEY_SIDE_TONE_AFTER_ADC

PSKEY_SIDE_TONE_AFTER_DAC

10.2.17 Integrated Digital Filter

BlueCore5‑Multimedia External has a programmable digital filter integrated into the ADC channel of the codec. The

filter is a 2 stage, second order IIR and is used for functions such as custom wind noise rejection. The filter also has

optional DC blocking.

The filter has 10 configuration words used as follows:

1 for gain value

8 for coefficient values

1 for enabling and disabling the DC blocking

The gain and coefficients are all 12-bit 2's complement signed integer with the format

XX.XXXXXXXXXX

Note:

The position of the binary point is between bit[10] and bit[9], where bit[11] is the most significant bit.

For example:

01.1111111111

= most positive number, close to

2

01.0000000000

=

1

00.0000000000

=

0

11.0000000000

=

-1

10.0000000000

=

-2

, most negative number

Equation 10.1 shows the equation for the IIR filter. Equation 10.2 shows the equation for when the DC blocking is

enabled.

The filter can be configured, enabled and disabled from the VM via the

CodecSetIIRFilterA

and

CodecSetIIRFilterB

traps. This requires firmware support. The configuration function takes 10 variables in the order shown below:

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Audio Interface

0

: Gain

1

: b

01

2

: b

02

3

: a

01

4

: a

02

5

: b

11

6

: b

12

7

: a

11

8

: a

12

9

: DC Block (1 = enable, 0 = disable)

Filter, H(z) = Gain ×

( 1 + b01 z

−1 + b

02 z

−2 )

( 1 + a01 z

−1 + a

02 z

−2 )

×

( 1 + b11 z

−1 + b

( 1 + a11 z

−1 + a

12 z

−2 )

12 z

−2 )

Equation 10.1: IIR Filter Transfer Function, H(z)

Filter with DC Blocking, H

DC

(z) = H(z) × ( 1 − z

−1

)

Equation 10.2: IIR Filter plus DC Blocking Transfer Function, H

DC

(z)

10.3

PCM Interface

The audio PCM interface supports continuous transmission and reception of PCM encoded audio data over

Bluetooth.

PCM is a standard method used to digitise audio, particularly voice, for transmission over digital communication channels. Through its PCM interface, BlueCore5‑Multimedia External has hardware support for continual transmission and reception of PCM data, so reducing processor overhead. BlueCore5‑Multimedia External offers a

bidirectional digital audio interface that routes directly into the baseband layer of the on-chip firmware. It does not

pass through the HCI protocol layer.

Hardware on BlueCore5‑Multimedia External allows the data to be sent to and received from a SCO connection.

Up to 3 SCO connections can be supported by the PCM interface at any one time.

BlueCore5‑Multimedia External can operate as the PCM interface master generating PCM_SYNC and PCM_CLK or as a PCM interface slave accepting externally generated PCM_SYNC and PCM_CLK.

BlueCore5‑Multimedia External is compatible with various clock formats, including Long Frame Sync, Short Frame

Sync and GCI timing environments.

It supports 13-bit or 16-bit linear, 8-bit µ-law or A-law companded sample formats, and can receive and transmit on

any selection of 3 of the first four slots following PCM_SYNC. The PCM configuration options are enabled by setting the PS Key PSKEY_PCM_CONFIG32.

10.3.1 PCM Interface Master/Slave

When configured as the master of the PCM interface, BlueCore5‑Multimedia External generates PCM_CLK and

PCM_SYNC.

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Audio Interface

PCM_OUT

PCM_IN

PCM_CLK

PCM_SYNC

128/256/512/1536/2400kHz

8/48kHz

Figure 10.10: PCM Interface Master

PCM_OUT

PCM_IN

PCM_CLK

PCM_ SYNC

Upto 2400kHz

8/48kHz

Figure 10.11: PCM Interface Slave

10.3.2 Long Frame Sync

Long Frame Sync is the name given to a clocking format that controls the transfer of PCM data words or samples.

In Long Frame Sync, the rising edge of PCM_SYNC indicates the start of the PCM word. When

BlueCore5‑Multimedia External is configured as PCM master, generating PCM_SYNC and PCM_CLK, then

PCM_SYNC is 8-bits long. When BlueCore5‑Multimedia External is configured as PCM Slave, PCM_SYNC may be

from one cycle PCM_CLK to half the PCM_SYNC rate.

PCM_SYNC

PCM_CLK

PCM_OUT 1 2 3 4 5 6 7 8

PCM_IN

Undefined

1 2 3 4 5 6 7 8

Undefined

Figure 10.12: Long Frame Sync (Shown with 8-bit Companded Sample)

BlueCore5‑Multimedia External samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the

rising edge. PCM_OUT may be configured to be high impedance on the falling edge of PCM_CLK in the LSB position

or on the rising edge.

10.3.3 Short Frame Sync

In Short Frame Sync, the falling edge of PCM_SYNC indicates the start of the PCM word. PCM_SYNC is always

one clock cycle long.

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Audio Interface

PCM_SYNC

PCM_CLK

PCM_OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

PCM_IN Undefined 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Undefined

Figure 10.13: Short Frame Sync (Shown with 16-bit Sample)

As with Long Frame Sync, BlueCore5‑Multimedia External samples PCM_IN on the falling edge of PCM_CLK and transmits PCM_OUT on the rising edge. PCM_OUT may be configured to be high impedance on the falling edge of

PCM_CLK in the LSB position or on the rising edge.

10.3.4 Multi-slot Operation

More than one SCO connection over the PCM interface is supported using multiple slots. Up to three SCO connections can be carried over any of the first four slots.

LONG_PCM_SYNC

Or

SHORT_PCM_SYNC

PCM_CLK

PCM_OUT 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

PCM_IN Do Not Care 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 Do Not Care

Figure 10.14: Multi-slot Operation with Two Slots and 8-bit Companded Samples

10.3.5 GCI Interface

BlueCore5‑Multimedia External is compatible with the GCI, a standard synchronous 2B+D ISDN timing interface.

The 2 64kbps B channels can be accessed when this mode is configured.

PCM_SYNC

PCM_CLK

PCM_OUT 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

PCM_IN

Do Not

Care

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

B1 Channel B2 Channel

Do Not

Care

Figure 10.15: GCI Interface

The start of frame is indicated by the rising edge of PCM_SYNC and runs at 8kHz.

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Audio Interface

10.3.6 Slots and Sample Formats

BlueCore5‑Multimedia External can receive and transmit on any selection of the first 4 slots following each sync pulse. Slot durations can be either 8 or 16 clock cycles. Durations of 8 clock cycles may only be used with 8-bit sample formats. Durations of 16 clocks may be used with 8-bit, 13-bit or 16-bit sample formats.

BlueCore5‑Multimedia External supports 13-bit linear, 16-bit linear and 8-bit µ-law or A-law sample formats. The

sample rate is 8ksamples/s. The bit order may be little or big endian. When 16-bit slots are used, the 3 or 8 unused bits in each slot may be filled with sign extension, padded with zeros or a programmable 3-bit audio attenuation

compatible with some Motorola codecs.

PCM_OUT 1 2

Sign

Extension

3 4 5 6 7 8 9 10 11 12 13 14 15 16

8-Bit

Sample

A 16-bit slot with 8-bit companded sample and sign extension selected.

PCM_OUT 1 2

8-Bit

Sample

3 4 5 6 7 8 9 10 11 12 13 14 15 16

Zeros

Padding

A 16-bit slot with 8-bit companded sample and zeros padding selected.

PCM_OUT 1

Sign

Extension

2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

13-Bit

Sample

A 16-bit slot with 13-bit linear sample and sign extension selected.

PCM_OUT 1 2

13-Bit

Sample

3 4 5 6 7 8 9 10 11 12 13 14 15 16

Audio

Gain

A 16-bit slot with 13-bit linear sample and audio gain selected.

Figure 10.16: 16-Bit Slot Length and Sample Formats

10.3.7 Additional Features

BlueCore5‑Multimedia External has a mute facility that forces PCM_OUT to be 0. In master mode, PCM_SYNC may also be forced to 0 while keeping PCM_CLK running which some codecs use to control power down.

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Audio Interface

10.3.8 PCM Timing Information

Symbol Parameter f mclk

4MHz DDS generation.

Selection of frequency is programmable. See

Table 10.10.

PCM_CLK frequency

48MHz DDS

generation. Selection of frequency is programmable. See

Table 10.9 and Section

10.3.9.

PCM_SYNC frequency for SCO connection

t mclkh

(a)

PCM_CLK high

4MHz DDS generation

t mclkl

(a) t hpinclkl

PCM_CLK low

4MHz DDS generation

t t

t dmclksynch dmclkpout dmclklsyncl

PCM_CLK jitter

48MHz DDS

generation

Delay time from PCM_CLK high to PCM_SYNC high

Delay time from PCM_CLK high to valid

PCM_OUT

Delay time from PCM_CLK low to PCM_SYNC low (Long Frame Sync only) t dmclkhsyncl

Delay time from PCM_CLK high to PCM_SYNC low t dmclklpoutz t supinclkl

Delay time from PCM_CLK low to PCM_OUT high impedance t dmclkhpoutz

Delay time from PCM_CLK high to PCM_OUT high impedance

Set-up time for PCM_IN valid to PCM_CLK low

Hold time for PCM_CLK low to PCM_IN invalid

Min

-

2.9

-

980

730

-

-

-

-

-

-

-

30

10

8

-

-

Typ

128

256

512

-

-

-

-

-

-

-

-

-

-

Max

-

-

-

-

-

21

20

20

20

20

20

20

-

-

Table 10.7: PCM Master Timing

(a)

Assumes normal system clock operation. Figures will vary during low-power modes, when system clock speeds are reduced.

Unit kHz kHz kHz ns ns ns pk-pk ns ns ns ns ns ns ns ns

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Audio Interface t dmclksynch t dmclklsyncl t dmclkhsyncl

PCM_SYNC t mclkh f mlk t mclkl

PCM_CLK

PCM_OUT t dmclkpout

MSB (LSB) t r

,t f

PCM_IN t supinclkl t hpinclkl

MSB (LSB) LSB (MSB)

Figure 10.17: PCM Master Timing Long Frame Sync t dmclksynch t dmclkhsyncl

PCM_SYNC t mclkh f mlk t mclkl

LSB (MSB) t dmclklpoutz t dmclkhpoutz

PCM_CLK

PCM_OUT

PCM_IN t dmclkpout

MSB (LSB) t r

,t f

LSB (MSB) t dmclklpoutz t dmclkhpoutz t supinclkl t hpinclkl

MSB (LSB) LSB (MSB)

Figure 10.18: PCM Master Timing Short Frame Sync

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Audio Interface

Symbol f sclk f sclk t sclkl t sclkh t hsclksynch t susclksynch t t t dpout dsclkhpout dpoutz

Parameter

PCM clock frequency (Slave mode: input)

PCM clock frequency (GCI mode)

PCM_CLK low time

PCM_CLK high time

Hold time from PCM_CLK low to PCM_SYNC high

Set-up time for PCM_SYNC high to PCM_CLK low

Delay time from PCM_SYNC or PCM_CLK whichever is later, to valid PCM_OUT data (Long

Frame Sync only)

Delay time from CLK high to PCM_OUT valid data

Delay time from PCM_SYNC or PCM_CLK low, whichever is later, to PCM_OUT data line high impedance

Set-up time for PCM_IN valid to CLK low

Hold time for PCM_CLK low to PCM_IN invalid t supinsclkl t hpinsclkl

Table 10.8: PCM Slave Timing

(a)

Max frequency is the frequency defined by PSKEY_PCM_MIN_CPU_CLOCK

(b)

Max frequency is twice the frequency defined by PSKEY_PCM_MIN_CPU_CLOCK f sclk t sclkh t tsclkl

PCM_CLK

80

20

20

Min

64

128

80

-

-

-

20

20 t hsclksynch t susclksynch

PCM_SYNC

PCM_OUT

PCM_IN t dpout

MSB (LSB) t dsclkhpout t r

,t f

LSB (MSB) t dpoutz t dpoutz t supinsclkl t hpinsclkl

MSB (LSB) LSB (MSB)

Figure 10.19: PCM Slave Timing Long Frame Sync

-

-

-

-

-

-

-

-

-

-

Typ

-

20

-

-

20

20

Max

(a)

(b)

-

-

-

ns ns ns ns ns ns ns ns

Unit kHz kHz ns

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Audio Interface t sclkh f sclk t tsclkl

PCM_CLK

PCM_SYNC t susclksynch t hsclksynch

PCM_OUT t dsclkhpout

MSB (LSB) t r

,t f

LSB (MSB) t dpoutz t dpoutz

PCM_IN t supinsclkl t hpinsclkl

MSB (LSB) LSB (MSB)

Figure 10.20: PCM Slave Timing Short Frame Sync

10.3.9 PCM_CLK and PCM_SYNC Generation

BlueCore5‑Multimedia External has 2 methods of generating PCM_CLK and PCM_SYNC in master mode:

Generating these signals by DDS from BlueCore5‑Multimedia External internal 4MHz clock. Using this

mode limits PCM_CLK to 128, 256 or 512kHz and PCM_SYNC to 8kHz.

Generating these signals by DDS from an internal 48MHz clock (which allows a greater range of frequencies

to be generated with low jitter but consumes more power). This second method is selected by setting bit

48M_PCM_CLK_GEN_EN in PSKEY_PCM_CONFIG32. When in this mode and with long frame sync, the length of PCM_SYNC can be either 8 or 16 cycles of PCM_CLK, determined by

LONG_LENGTH_SYNC_EN in PSKEY_PCM_CONFIG32.

Equation 10.3 describes PCM_CLK frequency when being generated using the internal 48MHz clock:

f

=

CNT _

CNT _

RATE

LIMIT

×

24 MHz

Equation 10.3: PCM_CLK Frequency When Being Generated Using the Internal 48MHz Clock

Set the frequency of PCM_SYNC relative to PCM_CLK using Equation 10.4:

f =

PCM _ CLK

SYNC _ LIMIT x 8

Equation 10.4: PCM_SYNC Frequency Relative to PCM_CLK

CNT_RATE, CNT_LIMIT and SYNC_LIMIT are set using PSKEY_PCM_LOW_JITTER_CONFIG. As an example, to generate PCM_CLK at 512kHz with PCM_SYNC at 8kHz, set PSKEY_PCM_LOW_JITTER_CONFIG to

0x08080177.

10.3.10 PCM Configuration

The PCM configuration is set using the PS Keys, PSKEY_PCM_CONFIG32 described in Table 10.10 and

PSKEY_PCM_LOW_JITTER_CONFIG in Table 10.9. The default for PSKEY_PCM_CONFIG32 is 0x00800000,

i.e. first slot following sync is active, 13-bit linear voice format, long frame sync and interface master generating

256kHz PCM_CLK from 4MHz internal clock with no tristate of PCM_OUT.

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Audio Interface

Name

CNT_LIMIT

CNT_RATE

SYNC_LIMIT

Bit Position Description

[12:0] Sets PCM_CLK counter limit

[23:16]

[31:24]

Sets PCM_CLK count rate

Sets PCM_SYNC division relative to PCM_CLK

-

-

Name

SLAVE_MODE_EN

SHORT_SYNC_EN

SIGN_EXTEND_EN

LSB_FIRST_EN

TX_TRISTATE_EN

SYNC_SUPPRESS_EN

GCI_MODE_EN

MUTE_EN

Table 10.9: PSKEY_PCM_LOW_JITTER_CONFIG Description

TX_TRISTATE_RISING_EDGE_EN

Bit Position Description

0 Set to 0.

1

0 = master mode with internal generation of PCM_CLK and

PCM_SYNC.

1 = slave mode requiring externally generated PCM_CLK and PCM_SYNC.

2

3

4

5

0 = long frame sync (rising edge indicates start of frame).

1 = short frame sync (falling edge indicates start of frame).

Set to 0.

0 = padding of 8 or 13-bit voice sample into a 16-bit slot by

inserting extra LSBs. When padding is selected with 13-bit

voice sample, the 3 padding bits are the audio gain setting; with 8-bit sample the 8 padding bits are zeroes.

1 = sign-extension.

0 = MSB first of transmit and receive voice samples.

1 = LSB first of transmit and receive voice samples.

6

7

8

9

10

0 = drive PCM_OUT continuously.

1 = tristate PCM_OUT immediately after falling edge of

PCM_CLK in the last bit of an active slot, assuming the next slot is not active.

0 = tristate PCM_OUT immediately after falling edge of

PCM_CLK in last bit of an active slot, assuming the next slot is also not active.

1 = tristate PCM_OUT after rising edge of PCM_CLK.

0 = enable PCM_SYNC output when master.

1 = suppress PCM_SYNC while keeping PCM_CLK running. Some codecs use this to enter a low power state.

1 = enable GCI mode.

1 = force PCM_OUT to 0.

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Audio Interface

-

Name

48M_PCM_CLK_GEN_EN

LONG_LENGTH_SYNC_EN

MASTER_CLK_RATE

ACTIVE_SLOT

SAMPLE_FORMAT

Bit Position Description

11

0 = set PCM_CLK and PCM_SYNC generation via DDS from internal 4MHz clock.

1 = set PCM_CLK and PCM_SYNC generation via DDS from internal 48MHz clock.

12

0 = set PCM_SYNC length to 8 PCM_CLK cycles.

1 = set length to 16 PCM_CLK cycles.

Only applies for long frame sync and with

48M_PCM_CLK_GEN_EN set to 1.

[20:16]

Set to

0b00000

.

[22:21]

[26:23]

[28:27]

Selects 128 (

0b01

), 256 (

0b00

), 512 (

PCM_CLK frequency when master and

0b10

48M_PCM_CLK_GEN_EN (bit 11) is low.

) kHz

Default is 0001. Ignored by firmware.

Selects between 13 (

0b00

), 16 (

0b01 sample with 16-cycle slot duration or 8 (

), 8 (

0b10

) bit

0b11

) bit sample with 8-cycle slot duration.

Table 10.10: PSKEY_PCM_CONFIG32 Description

10.4

Digital Audio Interface (I²S)

The digital audio interface supports the industry standard formats for I²S, left-justified or right-justified. The interface

shares the same pins as the PCM interface, which means each audio bus is mutually exclusive in its usage. Table

10.11 lists these alternative functions. Figure 10.21 shows the timing diagram.

PCM Interface

PCM_OUT

PCM_IN

PCM_SYNC

PCM_CLK

I

2

S Interface

SD_OUT

SD_IN

WS

SCK

Table 10.11: Alternative Functions of the Digital Audio Bus Interface on the PCM Interface

Table 10.12 describes the values for the PS Key PSKEY_DIGITAL_AUDIO_CONFIG that is used to set-up the digital

audio interface. For example, to configure an I

PSKEY_DIGITAL_AUDIO_CONFIG to 0x0406.

2

S interface with 16-bit SD data set

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Audio Interface

Bit

D[0]

D[1]

D[2]

D[3]

D[7:4]

D[9:8]

D[10]

Mask Name

0x0001 CONFIG_JUSTIFY_FORMAT

0x0002 CONFIG_LEFT_JUSTIFY_DELAY

0x0004 CONFIG_CHANNEL_POLARITY

0x0008 CONFIG_AUDIO_ATTEN_EN

0x00F0 CONFIG_AUDIO_ATTEN

0x0300 CONFIG_JUSTIFY_RESOLUTION

0x0400 CONFIG_16_BIT_CROP_EN

Description

0 for left justified, 1 for right justified.

For left justified formats: 0 is MSB of SD data

occurs in the first SCLK period following WS

transition. 1 is MSB of SD data occurs in the

second SCLK period.

For 0, SD data is left channel when WS is high. For 1 SD data is right channel.

For 0, 17-bit SD data is rounded down to

16bits. For 1, the audio attenuation defined in CONFIG_AUDIO_ATTEN is applied over

24bits with saturated rounding. Requires

CONFIG_16_BIT_CROP_EN to be 0.

Attenuation in 6dB steps.

Resolution of data on SD_IN, 00=16bit,

01=20bit, 10=24bit, 11=Reserved. This is required for right justified format and with left justified LSB first.

For 0, 17-bit SD_IN data is rounded down to

16bits. For 1 only the most significant 16bits of data are received.

Table 10.12: PSKEY_DIGITAL_AUDIO_CONFIG

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Audio Interface

WS

Left Channel Right Channel

SCK

SD_IN/OUT

MSB LSB MSB

Left-Justified Mode

Left Channel

LSB

Right Channel

WS

SCK

SD_IN/OUT

WS

MSB

Left Channel

LSB MSB

Right-Justified Mode

Right Channel

LSB

SCK

SD_IN/OUT

MSB LSB MSB LSB

I

2

S Mode

Figure 10.21: Digital Audio Interface Modes

The internal representation of audio samples within BlueCore5‑Multimedia External is 16-bit and data on SD_OUT is limited to 16-bit per channel.

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t ssu t sh t isu t ih

Symbol

-

t ch t cl t opd

WS(Input)

Parameter

SCK Frequency

WS Frequency

SCK high time

SCK low time

SCK to SD_OUT delay

WS to SCK set-up time

WS to SCK hold time

SD_IN to SCK set-up time

SD_IN to SCK hold time

Min

-

-

80

80

-

20

20

20

20

Table 10.13: Digital Audio Interface Slave Timing

-

-

-

-

-

Typ

-

-

-

t ch t ssu t cl t sh

SCK(Input)

-

-

-

Max

6.2

96

-

-

20

t opd

SD_OUT t isu t ih

SD_IN

Figure 10.22: Digital Audio Interface Slave Timing

Audio Interface ns ns ns

Unit

MHz kHz ns ns ns ns

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Symbol

-

t opd t spd t isu t ih

WS(Output)

Parameter

SCK Frequency

WS Frequency

SCK to SD_OUT delay

SCK to WS delay

SD_IN to SCK set-up time

SD_IN to SCK hold time

Min

-

-

-

-

20

10

Table 10.14: Digital Audio Interface Master Timing

-

-

Typ

-

-

-

t spd

SCK(Output)

Max

6.2

96

20

20

-

t opd

SD_OUT

SD_IN t isu

Figure 10.23: Digital Audio Interface Master Timing t ih

Audio Interface

Unit

MHz kHz ns ns ns ns

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Power Control and Regulation

11 Power Control and Regulation

BlueCore5‑Multimedia External contains 4 regulators:

A switch-mode regulator for generating the 1.8V supply rail.

2 low-voltage regulators, running in parallel to supply the 1.5V core supplies from a 1.8V supply rail.

Various configurations for power control and regulation with the BlueCore5‑Multimedia External are available:

A high-voltage rail running the switch-mode regulator and the low-voltage regulators in series, as Figure

11.1 shows

BlueCore5‑Multimedia External powered directly from an external 1.8V supply rail, by-passing the switchmode regulator

An external 1.5V rail omitting all regulators

A 1.8V linear voltage regulator

1.8V Supply Rail

VREGENABLE_L

VDD_CHG

BAT_P

BAT_N

IN

EN

OUT

Low-voltage

Linear Regulator

SENSE

EN OUT

Audio Low-voltage

Regulator

IN

SENSE

VREGIN_L

VDD_ANA

VDD_RADIO

VDD_AUDIO

VREGIN_AUDIO

IN

Battery Charger

OUT

EN

LX

Switch-mode

Regulator

SENSE

LX

VDD_SMP_CORE

L1

C1

VREGENABLE_H

VREGIN_H

EN OUT

High-voltage

Linear Regulator

IN SENSE

VREGOUT_H

Figure 11.1: Voltage Regulator Configuration

11.1

Power Sequencing

The 1.50V supply rails are VDD_ANA, VDD_LO, VDD_RADIO, VDD_AUDIO and VDD_CORE. CSR recommends

that these supply rails are all powered at the same time.

The digital I/O supply rails are VDD_PIO, VDD_PADS, VDD_USB and VDD_MEM.

The sequence of powering the 1.50V supply rails relative to the digital I/O supply rails is not important. If the digital

I/O supply rails are powered before the 1.50V supply rails, all digital I/Os will have a weak pull-down irrespective of

the reset state.

VDD_ANA, VDD_LO, VDD_RADIO and VDD_AUDIO can connect directly to a 1.50V supply.

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Power Control and Regulation

A simple RC filter is recommended for VDD_CORE to reduce transients fed back onto the power supply rails.

The digital I/O supply rails are connected either together or independently to an appropriate voltage rail. Decoupling of the digital I/O supply rails is recommended.

11.2

External Voltage Source

If any of the supply rails for BlueCore5‑Multimedia External are supplied from an external voltage source, rather than

one of the internal voltage regulators, CSR recommends that VDD_LO, VDD_RADIO and VDD_AUDIO should have

less than 10mV rms noise levels between 0 and 10MHz. Also avoid single tone frequencies.

The transient response of any external regulator used should match or be better than the internal regulator available

on BlueCore5‑Multimedia External. For more information, refer to regulator characteristics in Section 13. It is

essential that the power rail recovers quickly at the start of a packet, where the power consumption jumps to high levels.

11.3

Switch-mode Regulator

CSR recommends the on-chip switch-mode regulator to power the 1.8V supply rail.

An external LC filter circuit of a low-resistance series inductor, L1 (22µH), followed by a low ESR shunt capacitor,

C1 (4.7µF), is required between the LX terminal and the 1.8V supply rail. A connection between the 1.8V supply rail and the VDD_SMP_CORE pin is required.

A 2.2µF decoupling capacitor is required between BAT_P and BAT_N.

To maintain high-efficiency power conversion and low supply ripple, it is essential that the series resistance of tracks between the BAT_P and BAT_N terminals, the filter and decoupling components, and the external voltage source are minimised.

The switch-mode regulator is enabled by either:

VREGENABLE_H pin

BlueCore5‑Multimedia External device firmware

BlueCore5‑Multimedia External battery charger

The switch-mode regulator switches into a low-power pulse skipping mode when the device is sent into deep sleep mode, or in reset.

When the switch-mode regulator is not required the terminals BAT_P and LX must be grounded or left unconnected.

11.4

High-voltage Linear Regulator

A high-voltage linear regulator with a 1.8V output is available. This regulator should not be used to power external

circuitry, prior to using this regulator contact CSR.

A smoothing circuit using a low ESR 2.2µF capacitor and a 2.2Ω resistor to ground, should be connected to the

output of the high-voltage linear regulator, VREGOUT_H. Alternatively use a 2.2µF capacitor with an ESR of at least

2Ω.

The high-voltage linear regulator is enabled by either:

VREGENABLE_H pin

BlueCore5‑Multimedia External device firmware

BlueCore5‑Multimedia External battery charger

The regulator is switched into a low-power mode when the device is in deep sleep mode, or in reset.

When the high-voltage linear regulator is not used the terminals VREGIN_H and VREGOUT_H must be left unconnected, or tied to ground.

11.5

Low-voltage Linear Regulator

The low-voltage linear regulator is available to power a 1.5V supply rail. Its output is connected internally to

VDD_ANA, and can be connected externally to the other 1.5V power inputs.

If the low-voltage linear regulator is used, connect a smoothing circuit using a low ESR 2.2µF capacitor and a

2.2Ω resistor to ground to the output of the low-voltage linear regulator, VDD_ANA. Alternatively use a 2.2µF capacitor with an ESR of at least 2Ω.

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Power Control and Regulation

The low-voltage linear regulator is enabled by either:

VREGENABLE_L pin

BlueCore5‑Multimedia External device firmware

BlueCore5‑Multimedia External battery charger

The low-voltage linear regulator switches into a low power mode when the device is in deep sleep mode, or in reset.

When the low-voltage linear regulator is not used, either leave the terminal VREGIN_L unconnected, or tie it to

VDD_ANA.

11.6

Low-voltage Audio Linear Regulator

The low-voltage audio linear regulator is available to power a 1.5V audio supply rail. Its output is connected internally to VDD_AUDIO, and can be connected externally to the other 1.5V audio power inputs.

If the low-voltage audio linear regulator is used, connect a smoothing circuit using a low ESR 2.2µF capacitor and

a 2.2Ω resistor to ground to the output of the low-voltage audio linear regulator, VDD_AUDIO. Alternatively use a

2.2µF capacitor with an ESR of at least 2Ω.

The low-voltage audio linear regulator is enabled by either:

VREGENABLE_L pin

BlueCore5‑Multimedia External device firmware

The low-voltage audio linear regulator switches into a low-power mode when no audio cells are enabled, or when the chip is in reset.

When this regulator is not used, either leave the terminal VREGIN_AUDIO unconnected or tie it to VDD_AUDIO.

11.7

Voltage Regulator Enable Pins

The voltage regulator enable pins, VREGENABLE_H and VREGENABLE_L, are used to enable the

BlueCore5‑Multimedia External device if the on-chip regulators are being used. Table 11.1 shows the enable pin

responsible for each voltage regulator.

Enable Pin

VREGENABLE_H

VREGENABLE_L

Regulator

High-voltage Linear Regulator and Switch-mode Regulator

Low-voltage Linear Regulator and Low-voltage Audio Linear Regulator

Table 11.1: BlueCore5‑Multimedia External Voltage Regulator Enable Pins

The voltage regulator enable pins are active high, with weak pull-downs.

BlueCore5‑Multimedia External boots-up when the voltage regulator enable pins are pulled high, enabling the appropriate regulators. The firmware then latches the regulators on and the voltage regulator enable pins may then be released.

The status of the VREGENABLE_H pin is available to firmware through an internal connection. VREGENABLE_H also works as an input line.

11.8

Battery Charger

The battery charger is a constant current / constant voltage charger circuit, and is suitable for lithium ion/polymer batteries only. It shares a connection to the battery terminal, BAT_P, with the switch-mode regulator. However it may be used in conjunction with either of the high-voltage regulators on the device.

The constant current level can be varied to allow charging of different capacity batteries.

The charger enters various states of operation as it charges a battery, as listed below. A full operational description is in

BlueCore5 Charger Description and Calibration Procedure Application Note

:

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Power Control and Regulation

Off : entered when charger disconnected.

Trickle charge: entered when battery is below 2.9V. The battery is charged at a nominal 4.5mA. This mode is for the safe charge of deeply discharged cells.

Fast charge constant current: entered when battery is above 2.9V. The charger enters the main fast charge mode. This mode charges the battery at the selected constant current, I chgset

.

Fast charge constant voltage: entered when battery has reached a selected voltage, V float switches mode to maintain the cell voltage at the V float

. The charger

voltage by adjusting the charge current.

Standby: this is the state when the battery is fully charged and no charging takes place. The battery voltage is continuously monitored and if it drops by more than 150mV below the V float enter the fast charge constant current mode to keep the battery fully charged.

voltage the charger will re-

When a voltage is applied to the charger input terminal VDD_CHG, and the battery is not fully charged, the charger

operates and an ESD connected to the terminal LED[0] illuminates. By default, until the firmware is running, the

ESD pulses at a low-duty cycle to minimise current consumption.

The battery charger circuitry auto-detects the presence of a power source, allowing the firmware to detect, using an internal status bit, when the charger is powered. Therefore when the charger supply is not connected to VDD_CHG, the terminal must be left open-circuit. The VDD_CHG pin when not connected must be allowed to float and not pulled

to a power rail. When the battery charger is not enabled this pin may float to a low undefined voltage. Any DC

connection increases current consumption of the device. Capacitive components may be connected such as diodes,

FETs and ESD protection.

The battery charger is designed to operate with a permanently connected battery. If the application enables the charger input to be connected while the battery is disconnected, then the BAT_P pin voltage may become unstable.

This in turn may cause damage to the internal switch-mode regulator. Connecting a 470µF capacitor to BAT_P limits these oscillations so preventing damage.

11.9

LED Drivers

BlueCore5‑Multimedia External includes 2 pads dedicated to driving LED indicators. Both terminals can be controlled

by firmware, while LED[0] can also be set by the battery charger.

The terminals are open-drain outputs, so the LED must be connected from a positive supply rail to the pad in series with a current limiting resistor.

CSR recommends that the LED pad, LED[0] or LED[1] pins, operate with a pad voltage below 0.5V. In this case,

the pad is like a resistor, R

ON

. The resistance together with the external series resistor sets the current, I

LED. The current is also dependent on the external voltage, VDD, as Figure 11.2 shows.

LED

, in the

Figure 11.2: LED Equivalent Circuit

From Figure 11.2 it is possible to derive Equation 11.1 to calculate I

LED

the LED to give a specific luminous intensity, then the value of R

LED

. If a known value of current is required through

can be calculated.

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Power Control and Regulation

Pin Name / Group

USB_DP

USB_DN

UART_RX

UART_CTS

UART_TX

UART_RTS

SPI_MOSI

SPI_CLK

SPI_CS#

SPI_MISO

I

LED

=

VDD − VF

RLED + RON

Equation 11.1: LED Current

For the LED[0] or LED[1] pad to act as resistance, the external series resistor, R

LED voltage drop across it, V

R

, keeps V

PAD

below 0.5V. Equation 11.2 also applies.

, needs to be such that the

VDD = V

F

+ V

R

+ V

PAD

Equation 11.2: LED PAD Voltage

Note:

The LED current will add to the overall application current, so conservative selection of the LEDs will preserve power consumption.

11.10 Reset, RST#

BlueCore5‑Multimedia External can be reset from several sources:

RST# pin

Power-on reset

UART break character

Software configured watchdog timer

The RST# pin is an active low reset and is internally filtered using the internal low frequency clock oscillator. A reset

is performed between 1.5 and 4.0ms following RST# being active. CSR recommends that RST# be applied for a

period greater than 5ms.

The power-on reset typically occurs when the VDD_CORE supply falls below 1.25V and is released when

VDD_CORE rises above typically 1.30V. At reset the digital I/O pins are set to inputs for bidirectional pins and outputs

are tristate. Following a reset, BlueCore5‑Multimedia External assumes the maximum XTAL_IN frequency, which ensures that the internal clocks run at a safe (low) frequency until BlueCore5‑Multimedia External is configured for the actual XTAL_IN frequency. If no clock is present at XTAL_IN, the oscillator in BlueCore5‑Multimedia External free runs, again at a safe frequency.

11.10.1 Digital Pin States on Reset

Table 11.2 shows the pin states of BlueCore5‑Multimedia External on reset. PU and PD default to weak values

unless specified otherwise.

I/O Type

Digital bidirectional

Digital bidirectional

Digital input with PD

Digital input with PD

Digital bidirectional with PU

Digital bidirectional with PU

Digital input with PD

Digital input with PD

Digital input with PU

Digital tristate output with PD

No Core Voltage

Reset

N/A

N/A

PD

PD

PU

PU

PD

PD

PU

PD

Full Chip Reset

PU

PU

PD

PD

N/A

N/A

PD

PD

PU

PD

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Power Control and Regulation

Pin Name / Group

PCM_IN

PCM_CLK

PCM_SYNC

PCM_OUT

RST#

TEST_EN

PIO[15:0]

I/O Type

Digital input with PD

Digital bidirectional with PD

Digital bidirectional with PD

Digital tristate output with PD

Digital input with PU

Digital input with PD

Digital bidirectional with PU/

PD

Table 11.2: Pin States on Reset

11.10.2 Status after Reset

The status of BlueCore5‑Multimedia External after a reset is:

Warm reset: data rate and RAM data remain available

Cold reset: data rate and RAM data not available

No Core Voltage

Reset

PD

PD

PD

PD

PU

PD

PD

Full Chip Reset

PD

PD

PD

PD

PU

PD

PD

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Example Application Schematic

12 Example Application Schematic

0402

C2

15p

+1V5

0402

C3

2u2

R1

2R2

0402

C4

10n

+1V5

L2

15n

0402

C13

15p

U2

DBF81F104-CSR

2

DC

1

UNBAL

3

NC

BAL 6

BAL 4

L1

RF_N

K1

RF_P

H2

AUX_DAC

A1

D3

VSS_AUDIO

VSS_AUDIO

F10

G6

G7

G8

G9

G10

H6

H7

H8

H9

H10

F6

F7

F8

F9

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

K3

L3

P2

B12

R3

C3

J3

M3

C13

C14

H3

L13

N4

N8

N13

J2

K2

L2

B4

C4 VSS_DIG

C12

VSS_DIG

VSS_DIG

VSS_DIG

VSS_DIG

VSS_DIG

VSS_DIG

VSS_DIG

VSS_DIG

VSS_DIG

VSS_RADIO

VSS_RADIO

VSS_RADIO

VSS_LO

VSS_LO

VSS_ANA

BAT_N

SUBS

VSS

VSS

VSS

REG

Low-voltage Linear for Core

+1V8

0603

C5

4u7

L1

22u

0402

C6

2u2

VBUS

0402

VDD_BAT

C7

2u2

+1V5

SW1

0402

C1

NF

PIO_14

R3

NF

+1V8 +1V5_AUDIO

R2

2R2

0402

C8

2u2

0402

C9

10n

+1V8 +1V8

0402

C10

10n

SP1

STAR POINT

+1V8 +3V3

REG

High-voltage

Switch-mode

REG

High-voltage

Linear

REG

Low-voltage Linear for Audio

BlueCore5-Multimedia External (BC57E687C)

SUPPLY USING A REGULATOR

FROM VBUS IF USB IS NECESSARY

U1

0402

C11

6p8

XTAL_IN R1

XTAL_OUT R2

LED[1] D14

LED[0] D13

PIO[15] M15

PIO[14] J15

PIO[13] K14

PIO[12] K13

PIO[11] L14

PIO[10] M13

PIO[9] M14

PIO[8] J14

PIO[7] J13

PIO[6] H15

PIO[5] H14

PIO[4] H13

PIO[3] F3

PIO[2] G3

PIO[1] F2

PIO[0] F1

PCM_SYNC F14

PCM_IN G15

PCM_OUT F15

PCM_CLK F13

SPI_CLK E14

SPI_MISO D15

SPI_MOSIE13

SPI_CS#E15

USB_DN P13

USB_DP P14

UART_RX N14

UART_TX N15

UART_CTS P15

UART_RTS R15

AIO[0] R4

AIO[1] N3

LO_REF P3

TEST_EN G14

RST# G13

PIO_15

PIO_14

PIO_13

PIO_12

PIO_11

PIO_10

PIO_9

PIO_8

PIO_7

PIO_6

PIO_5

PIO_4

PIO_3

PIO_2

PIO_1

PIO_0

PCM_SYNC

PCM_IN

PCM_OUT

PCM_CLK

SPI_CLK

SPI_MISO

SPI_MOSI

SPI_CSB

UART_RX

UART_TX

UART_CTS

UART_RTS

AIO_0

AIO_1

+1V8

0402

C14

10n

X1 26MHz

0402

C12

18p

C4

C3

FLT1

15K

5.25V

A1

A3

C1

B2

1.5K

15K

C2

A4

ECLAMP2343C

A2

B1

B3

VDD_BAT VDD_BAT

D1

R4

470R

R5

47R

D2

VBUS

R6

2R2

CON1

1

USB MINI-B

2 VBUS

3 D-

4 D+

5 ID

LITHIUM POLYMER BATTERY WITH

PROTECTION CIRCUIT BUILT IN

VDD_BAT

BT1

3V7

FLASH_RP# IS NOT

SUPPORTED WITH

THIS FLASH

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D1

+1V8

0402

C21

10n

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A4

F1

G1

B4

F6

E1

D1

U3

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

NC

NC

C1

A1

B1

D2

C2

A2

B5

A5

C5

D5

B6

A6

C6

D6

E6

B2

C3

D4

D3

VCC G4

DQ0 E2

DQ1 H2

DQ2 E3

DQ3 H3

DQ4 H4

DQ5 E4

DQ6 H5

DQ7 E5

DQ8 F2

DQ9 G2

DQ10 F3

DQ11 G3

DQ12 F4

DQ13 G5

DQ14 F5

DQ15A-1 G6

NC A3

WE#

CE#

OE#

NC

NC

NC B3

NC C4

VSS H1

VSS H6

FLASH SST39WF800B

8Mbit, 70ns

D8

D9

D10

D11

D12

D13

D14

D15

D4

D5

D6

D7

D0

D1

D2

D3

0402

C15

47n

SP2

16/32 Ohms

SP3

16/32 Ohms

Figure 12.1: Example Application Schematic

0402

C16

100n

0402

C17

100n

R8

0402

2k2

L3

15n

0402

C22

15p

MIC1

0402

C18

100n

R7

0402

2k2

0402

C19

100n

0402

C20

1u

L4

15n

0402

C23

15p

OPTIONAL GSM FILTER

MIC2

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Electrical Characteristics

13 Electrical Characteristics

13.1

Absolute Maximum Ratings

Rating

Storage Temperature

Core supply voltage

I/O voltage

VDD_ANA, VDD_LO, VDD_RADIO,

VDD_AUDIO and VDD_CORE

VDD_PIO, VDD_PADS, VDD_USB and

VDD_MEM

VREGIN_L

VREGIN_AUDIO

Supply voltage

VREGIN_H, VREGENABLE_H and

VREGENABLE_L

BAT_P

LED[1:0]

VDD_CHG

Other terminal voltages

Min

-40

-0.4

-0.4

-0.4

-0.4

-0.4

-0.4

-0.4

-0.4

VSS - 0.4

13.2

Recommended Operating Conditions

Operating Condition

Operating temperature range

(a)

Core supply voltage

I/O supply voltage

VDD_ANA, VDD_LO,

VDD_RADIO,

VDD_AUDIO and

VDD_CORE

VDD_PIO, VDD_PADS,

VDD_USB and

VDD_MEM

Min

-40

1.42

1.7

Typ

20

1.50

3.3

Max

105

1.65

3.6

2.7

2.7

4.9

4.4

4.4

6.5

VDD + 0.4

Max

85

1.57

3.6

(a) For radio performance over temperature refer to BlueCore5‑Multimedia External Performance Specification

V

V

V

V

V

V

V

V

Unit

°C

V

Unit

°C

V

V

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Electrical Characteristics

13.3

Input/Output Terminal Characteristics

Note:

For all I/O Terminal Characteristics:

VDD_ANA, VDD_LO, VDD_RADIO, VDD_AUDIO and VDD_CORE at 1.50V unless shown otherwise.

VDD_PIO, VDD_PADS, VDD_USB and VDD_MEM at 3.3V unless shown otherwise.

Current drawn into a pin is defined as positive; current supplied out of a pin is defined as negative.

13.3.1 High-voltage Linear Regulator

Normal Operation

Input voltage

Output voltage (I load

= 100mA / VREGIN_H = 3.0V)

Temperature coefficient

Output noise

(b) (c)

Load regulation (100µA < I load

< 200mA ), ΔV out

Settling time

(b) (d)

Output current

Minimum load current

Drop-out voltage ( I load

= 200mA)

Quiescent current (excluding load, I load

< 1mA)

Low-power Mode (e)

Quiescent current (excluding load, I load

< 100μA)

-

-

-

5

30

Min

2.7

1.70

-300

-

-

11

-

-

-

-

50

Typ

-

1.80

0

-

-

15

5

50

200

-

900

60

Max

5.5

(a)

1.95

300

1

21

μs mA

µA mV

μA

Unit

V

V ppm/°C mV rms mV

μA

(a)

Short-term operation up to 5.5V is permissible without damage and without the output voltage rising sufficiently to damage the rest of the device, but output regulation and other specifications are no longer guaranteed at input voltages in excess of 4.9V. 5.5V can only be tolerated for short periods.

(b) Regulator output connected to 47nF pure and 4.7μF 2.2Ω ESR capacitors.

(c)

Frequency range 100Hz to 100kHz.

(d)

10mA to 200mA pulsed load.

(e)

The regulator is in low power mode when the chip is in deep sleep mode, or in reset.

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Electrical Characteristics

13.3.2 Low-voltage Linear Regulator

Normal Operation

Input voltage

Output voltage (I load

= 70mA / VREGIN_L = 1.7V)

Temperature coefficient

Output noise

(a) (b)

Load regulation (100µA < I load

< 90mA ), ΔV out

Load regulation (100µA < I load

< 115mA ), ΔV out

Settling time

(a) (c)

Output current

Minimum load current

Drop-out voltage ( I load

= 115mA)

Quiescent current (excluding load, I load

< 1mA)

Low-power Mode

(d)

Quiescent current (excluding load, I load

< 100μA)

5

(a) Regulator output connected to 47nF pure and 4.7μF 2.2Ω ESR capacitors

(b)

Frequency range 100Hz to 100kHz

(c)

1mA to 115mA pulsed load

(d)

The regulator is in low power mode when the chip is in deep sleep mode, or in reset

-

-

Min

1.70

1.42

-300

-

-

-

-

5

50

-

-

Typ

1.80

1.50

0

-

-

-

-

-

90

8

Unit

V

V ppm/°C mV rms mV mV

μs mA

µA mV

μA

Max

1.95

1.57

300

1

5

25

50

115

100

300

150

15 μA

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Electrical Characteristics

13.3.3 Low-voltage Linear Audio Regulator

Normal Operation

Input voltage

Output voltage (I load

= 70mA / VREGIN_AUDIO = 1.7V)

Temperature coefficient

Output noise

(a) (b)

Load regulation (100µA < I load

< 70mA ), ΔV out

Settling time

(a) (c)

Output current

Minimum load current

Dropout voltage ( I load

= 70mA)

Quiescent current (excluding load, I load

< 1mA)

Low-power Mode

(d)

Quiescent current (excluding load, I load

< 100μA)

5

(a)

Regulator output connected to 47nF pure and 4.7μF 2.2Ω ESR capacitors

(b) Frequency range 100Hz to 100kHz

(c) 1mA to 70mA pulsed load

(d)

The regulator is in low power mode when the chip is in deep sleep mode, or in reset

-

-

-

-

5

Min

1.70

1.42

-300

-

25

-

-

-

-

-

Typ

1.80

1.50

0

-

30

8

5

50

70

100

300

Max

1.95

1.57

300

1

50 mV

μs mA

µA mV

Unit

V

V ppm/°C mV rms

μA

15 μA

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13.3.4 Reset

Power-on Reset

VDD_CORE falling threshold

VDD_CORE rising threshold

Hysteresis

13.3.5 Regulator Enable

Switching Threshold

VREGENABLE_H

Rising threshold

Falling threshold

Hysteresis

VREGENABLE_L

Rising threshold

Falling threshold

Hysteresis

Electrical Characteristics

Min

1.13

1.20

0.05

Typ

1.25

1.30

0.10

Max

1.30

1.35

0.15

Unit

V

V

V

Min

0.50

0.35

0.14

0.50

0.35

0.14

Typ

-

-

-

-

-

-

Max

0.95

0.80

0.28

0.95

0.80

0.28

Unit

V

V

V

V

V

V

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Electrical Characteristics

13.3.6 Switch-mode Regulator

Switch-mode Regulator

Input voltage

Output voltage (I load

= 70mA)

Temperature coefficient

Normal Operation

Output ripple

Transient settling time

(a)

Maximum load current

Conversion efficiency (I load

= 70mA)

Switching frequency

(b)

Start-up current limit

(c)

Low-power Mode

(d)

Output ripple

Transient settling time

(e)

Maximum load current

Minimum load current

Conversion efficiency (I load

= 1mA )

Switching frequency

(f)

200

-

-

-

-

30

-

-

-

5

1

50

Min

2.5

1.70

-250

-

90

-

-

1.333

50

-

-

-

-

80

-

Typ

-

1.80

-

-

-

10

50

-

80

1

700

-

-

-

150

Max

4.4

1.90

250

(a)

For step changes in load of 30 to 80mA and 80 to 30mA

(b) Locked to crystal frequency

(c)

Current is limited on start-up to prevent excessive stored energy in the filter inductor

(d)

The regulator is in low power mode when the chip is in deep sleep mode, or in reset

(e)

100μA to 1mA pulsed load

(f) Defines minimum period between pulses. Pulses are skipped at low current loads

Note:

The external inductor used with the switch-mode regulator must have an ESR in the range 0.3Ω to 0.7Ω:

Low ESR < 0.3Ω causes instability.

High ESR > 0.7Ω derates the maximum current.

Unit

V

V ppm/°C mV rms

μs mA

µA

% kHz mV rms

μs mA

%

MHz mA

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Electrical Characteristics

13.3.7 Battery Charger

Battery Charger

Input voltage

Min

4.5

Typ

-

Max

6.5

Unit

V

Charging Mode (BAT_P rising to 4.2V)

Supply current

(a)

Battery trickle charge current

(b)

Maximum battery fast charge current (I-CTRL = 15)

(c) (d)

Minimum battery fast charge current (I-CTRL = 0)

(c) (d)

Headroom

(e)

> 0.7V

Headroom = 0.3V

Headroom > 0.7V

Headroom = 0.3V

Fast charge step size

(I-CTRL = 0 to 15)

Trickle charge voltage threshold

Spread ±17%

Float voltage (with correct trim value set), V

FLOAT

(f)

Float voltage trim step size

(f)

Battery charge termination current, % of fast charge current

Min

-

-

-

-

-

-

-

-

4.17

5

-

Typ

4.5

4

140

120

40

35

6.3

2.9

4.2

50

10

Max

-

4.23

-

-

-

-

-

-

-

6

20

Unit mA mA mA mA mA mA mA

%

(a)

Current into VDD_CHG does not include current delivered to battery (I

VDD_CHG

- I

BAT_P

)

(b)

BAT_P < trickle charge voltage threshold

(c)

Charge current can be set in 16 equally spaced steps

(d) Trickle charge threshold < BAT_P < Float voltage

(e)

Where headroom = VDD_CHG - BAT_P

(f)

Float voltage can be adjusted in 15 steps. Trim setting is determined in production test and must be loaded into the battery charger by firmware during boot-up sequence

Standby Mode (BAT_P falling from 4.2V)

Supply current

(a)

Battery current

Battery recharge hysteresis

(b)

Min

-

-

100

Typ

1.5

-5

-

Max

-

2

200

Unit mA

µA mV

(a)

Current into VDD_CHG; does not include current delivered to battery (I

VDD_CHG

- I

BAT_P

)

(b)

Hysteresis of (V

FLOAT

- BAT_P) for charging to restart

V

V mV

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Electrical Characteristics

Shutdown Mode (VDD_CHG too low or disabled by firmware)

Supply current

Battery current

VDD_CHG under-voltage threshold

VDD_CHG - BAT_P lockout threshold

VDD_CHG rising

VDD_CHG falling

VDD_CHG rising

VDD_CHG falling

13.3.8 Digital Terminals

Supply Voltage Levels

VDD

PRE

Pre-driver supply voltage

VDD I/O supply voltage (post-driver)

Full spec.

Reduced spec.

Input Voltage Levels

V

IL

input logic level low

V

IH

input logic level high

V

SCHMITT

Schmitt voltage

Output Voltage Levels

V

OL

output logic level low, l

OL

= 4.0mA

V

OH

output logic level high, l

OH

= -4.0mA

Input and Tristate Currents

I i

input leakage current at V in

= VDD or 0V

I oz

tristate output leakage current at V o

= VDD or 0V

With strong pull-up

With strong pull-down

With weak pull-up

With weak pull-down

C

I

input capacitance

Min

0

0.75 x VDD

Min

-100

-100

-100

10

-5

-0.2

1.0

Min

1.4

3.0

1.7

Min

-0.3

0.625 x VDD

0.25 x VDD

Min

-

-

-

-

-

-1

Typ

1.5

-

3.90

3.70

0.22

0.17

Max

-

-

-

-

2

0

Max

0.125

VDD

Max

100

100

-10

100

-0.2

5.0

5.0

Max

1.6

3.6

3.0

Max

0.25 x VDD

VDD + 0.3

0.625 x VDD

Unit

V

V

V

Unit

V

V

V

Unit nA nA

μA

μA

μA

μA pF

Unit

V

V

Typ

0

0

-40

40

-1.0

1.0

-

Typ

-

-

Typ

-

-

-

Typ

1.5

3.3

-

Unit

V

V

V

V mA

µA

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Electrical Characteristics

Resistive Strength

R puw

weak pull-up strength at VDD - 0.2V

R pdw

weak pull-down strength at 0.2V

R pus

strong pull-up strength at VDD - 0.2V

R pds

strong pull-down strength at 0.2V

13.3.9 LED Driver Pads

LED Driver Pads

Off current

On resistance

V

PAD

< 0.5V

On resistance, pad enabled by battery charger

V

PAD

< 0.5V

13.3.10 USB

Min

-

-

-

VDD_USB for correct USB operation

Input Threshold

V

IL

input logic level low

Min

3.1

-

V

IH

input logic level high

Input Leakage Current

VSS_DIG < V

IN

< VDD_USB

(a)

C

I

input capacitance

Output Voltage Levels to Correctly Terminated USB Cable

V

OL

output logic level low

V

OH

output logic level high

0.7 x

VDD_USB

-1

2.5

0.0

2.8

(a) Internal USB pull-up disabled

Min

0.5

0.5

10

10

-

-

Typ

-

-

Typ

-

1

-

-

-

Typ

1

20

20

-

-

Max

2

33

50

Max

2

2

50

50

Max

3.6

0.3 x

VDD_USB

-

V

V

5

10.0

Unit

MΩ kΩ kΩ

Unit

V

0.2

VDD_USB

V

V

µA pF

Unit

µA

Ω

Ω

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Electrical Characteristics

13.3.11 Auxiliary ADC

Auxiliary ADC

Resolution

Input voltage range

(a)

Accuracy

(Guaranteed monotonic)

Offset

Gain error

Input bandwidth

Conversion time

Sample rate

(b)

INL

DNL

-1

0

-1

-0.8

-

-

Min

-

0

-

-

-

100

2.5

-

-

Typ

-

-

-

(a)

LSB size = VDD_ANA/1023

(b)

The auxiliary ADC is accessed through a VM function. The sample rate given is achieved as part of this function.

13.3.12 Auxiliary DAC

Auxiliary DAC

Resolution

Average output step size

(a)

Output Voltage

Voltage range (I

O

= 0mA)

Current range

Minimum output voltage (I

O

=100μA)

Maximum output voltage (I

O

=10mA)

High impedance leakage current

Offset

Integral non-linearity

(a)

Settling time (50pF load)

Min

-

12.5

VSS_DIG

-10.0

0.0

VDD_PIO -

0.3

-1

-220

-2

-

Typ

-

14.5

monotonic

(a)

-

-

-

-

-

-

-

-

Max

8

17.0

VDD_PIO

0.1

0.2

VDD_PIO

1

120

2

10

Max

10

VDD_ANA

1

0.8

-

-

1

1

700

Unit

Bits

V

LSB

LSB

LSB

% kHz

µs

Samples/ s

(a)

Specified for an output voltage between 0.2V and VDD_PIO - 0.2V. Output is high impedance when chip is in deep sleep mode.

V mA

V

Unit

Bits mV

V

µA mV

LSB

µs

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Electrical Characteristics

13.3.13 Clocks

Clock Source

Crystal Oscillator

Crystal frequency

(a)

Digital trim range

(b)

Trim step size

(b)

Transconductance

Negative resistance

(c)

External Clock

Input frequency

(d)

Clock input level (e)

Edge jitter (allowable jitter), at zero crossing

XTAL_IN input impedance

XTAL_IN input capacitance

Min

16

5.0

-

2.0

870

12

-

-

0.4

-

Typ

26

6.2

0.1

-

1500

26

≥10

≤4

-

-

Max

26

8.0

-

-

2400

52

Unit

MHz

VDD_ANA V pk-pk

15 ps rms

-

kΩ pF

(a)

Integer multiple of 250kHz

(b)

The difference between the internal capacitance at minimum and maximum settings of the internal digital trim

(c)

XTAL frequency = 16MHz; XTAL C

0

= 0.75pF; XTAL load capacitance = 8.5pF

(d)

Clock input can be any frequency between 12MHz to 52MHz in steps of 250kHz plus CDMA/3G TCXO frequencies of 14.40, 15.36, 16.2,

16.8, 19.2, 19.44, 19.68, 19.8 and 38.4MHz

(e)

Clock input can be either sinusoidal or square wave. If the peaks of the signal are below VSS_ANA or above VDD_ANA a DC blocking capacitor is required between the signal and XTAL_IN

MHz pF pF mS

Ω

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Electrical Characteristics

13.3.14 Stereo Codec: Analogue to Digital Converter

Analogue to Digital Converter

Parameter

Resolution -

Input Sample

Rate, F sample

-

Conditions

F sample

Signal to Noise

Ratio, SNR (a) f in

= 1kHz

B/W = 20Hz→20kHz

A-Weighted

THD+N < 1%

150mV pk-pk

input

Digital Gain

Analogue Gain

44.1kHz

Digital Gain Resolution = 1/32dB

Analogue Gain Resolution = 3dB

Input full scale at maximum gain (differential)

Input full scale at minimum gain (differential)

3dB Bandwidth

Microphone mode input impedance

THD+N (microphone input) @ 30mV rms input

8kHz

11.025kHz

16kHz

22.050kHz

32kHz

Min

-

8

-

-

-

-

-

-

-

-

-

-

-

-

-24

Typ

-

-

79

77

76

76

75

75

-

-

4

800

20

6.0

0.04

Max

16

44.1

-

-

42

-

-

-

-

-

-

-

-

-

21.5

Unit

Bits kHz dB mV rms mV rms kHz kΩ

% dB dB dB dB dB dB dB

(a) Improved SNR performance can be achieved at the expense of current consumption. See Optimising BlueCore5-Multimedia ADC

Performance Application Note for details.

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Electrical Characteristics

13.3.15 Stereo Codec: Digital to Analogue Converter

Digital to Analogue Converter

Parameter

Resolution -

Output Sample

Rate, F sample

-

Conditions

Signal to Noise

Ratio, SNR

F sample f in

= 1kHz

B/W = 20Hz→20kHz

A-Weighted

THD+N < 0.01%

0dBFS signal

Load = 100kΩ

8kHz

11.025kHz

16kHz

22.050kHz

32kHz

44.1kHz

48kHz

Digital Gain Resolution = 1/32dB

Analogue Gain Resolution = 3dB

Digital Gain

Analogue Gain

Output voltage full-scale swing (differential)

(a)

Allowed Load

Resistive

Capacitive

THD+N 100kΩ load

THD+N 16Ω load

SNR (Load = 16Ω, 0dBFS input relative to digital silence)

Min

-

8

-

16(8)

-

-

-

-

-

-

-

-24

0

-

-

-

-

Typ

-

-

750

-

-

-

-

95

95

95

95

-

-

95

95

95

95

Max

16

48

-

O.C.

500

0.01

0.1

-

-

-

-

21.5

-21

-

-

-

-

Unit

Bits kHz mV rms

%

%

Ω pF dB dB dB dB dB dB dB dB dB dB

(a) Any combination of gain (digital and / or analogue) and input signal which results in the output signal level exceeding the minimum or maximum signal level (analogue or digital) could result in distortion.

13.4

ESD Precautions

BlueCore5‑Multimedia External is classified as a JESD22-A114 class 2 product. Apply ESD static handling

precautions during manufacturing.

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Power Consumption

Master

Master

Master

Master

Slave

Slave

Slave

Slave

Slave

Slave

Master

Master

Master

Master

Master

Master

Master

Master

eSCO

SCO

SCO

SCO

ACL

ACL

ACL

ACL

eSCO eSCO

ACL

ACL

ACL

ACL

eSCO eSCO eSCO eSCO

14 Power Consumption

-

-

-

Role Connection

Stand-by

Page Scan

Inquiry and Page

Scan

-

-

EV5

HV1

HV3

-

HV3

-

-

-

EV3

EV3

-

-

-

-

EV3

EV3

2 EV3

2 EV3

-

Audio Packet Type Description

Setting S1

Setting S2

-

Setting S3

-

-

Sniff = 30ms

No Traffic

Host connection

Interval = 1280ms

Inquiry scan =

1280ms

Page scan = 1280ms

No traffic

File transfer TX

Sniff = 40ms

-

Sniff = 1280ms

File transfer RX

Sniff = 40ms

-

Sniff = 1280ms

Setting S1

Current

16MHz 32MHz

0.06

0.07

0.45

0.50

0.84

0.88

22

21

15

16

40

21

1.6

0.26

25

27

22

17

22

24

4.4

9.1

1.8

0.19

23

22

15

17

42

21

1.7

0.26

26

27

22

17

23

24

4.4

9.2

1.9

0.20

mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA

Unit mA mA

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Power Consumption

Role

Slave

Slave

Slave

Slave

Slave

Slave

Connection

eSCO eSCO eSCO

SCO

SCO

SCO

Audio Packet Type Description

2 EV3

2 EV3

EV5

HV1

HV3

HV3

Setting S2

-

Setting S3

-

-

Sniff = 30ms

14.1

Kalimba DSP Typical Average Current Consumption

DSP

Minimum (NOP)

DSP core (including PM memory access)

Maximum (MAC)

Current

16MHz 32MHz

27 28

24

22

25

22

39

26

22

42

28

22

Average

0.11

0.32

DSP memory access (DM1 or DM2)

0.08

Unit mA/

MIPS mA/

MIPS mA/

MIPS

Unit mA mA mA mA mA mA

14.2

Typical Peak Current at 20°C

Device Activity / State

Peak current during cold boot

Master TX peak current

Master RX peak current

Slave TX peak current

Slave RX peak current

14.3

Conditions

Results include the power consumed by the external flash memory.

Host interface = UART.

Baud rate = 115200.

Supply = 1.8V in to VREGIN_L and VREGIN_AUDIO.

AFH switched OFF .

No audio load.

RF output power = 0dBm.

VM OFF.

eSCO settings:

EV3 and EV5 = no retry.

Setting S1 = optimised for power consumption.

Firmware build ID = 4508.

Typ

45

45

45

45

45

Unit mA mA mA mA mA

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CSR Green Semiconductor Products and RoHS Compliance

15 CSR Green Semiconductor Products and RoHS Compliance

15.1

RoHS Statement

BlueCore5‑Multimedia External where explicitly stated in this Data Sheet meets the requirements of Directive

2002/95/EC of the European Parliament and of the Council on the

Restriction of Hazardous Substance

(RoHS).

15.1.1 List of Restricted Materials

BlueCore5‑Multimedia External is compliant with RoHS in relation to the following substances:

Cadmium

Lead

Mercury

Hexavalent chromium

Polybrominated Biphenyl

Polybrominated Diphenyl Ether

In addition, the following substances are not intentionally added to BlueCore5‑Multimedia External devices:

Halogenated flame retardant

Antimony (Sb) and Compounds, including Antimony Trioxide flame retardant

Polybrominated Diphenyl and Biphenyl Oxides

Tetrabromobisphenol-A bis (2,3-dibromopropylether)

Asbestos or Asbestos compounds

Azo compounds

Organic tin compounds

Mirex

Polychlorinated napthelenes

Polychlorinated terphenyls

Polychlorinated biphenyls

Polychlorinated/Short chain chlorinated paraffins

Polyvinyl Chloride (PVC) and PVC blends

Formaldehyde

Arsenic and compounds (except as a semiconductor dopant)

Beryllium and its compounds

Ethylene Glycol Monomethyl Ether or its acetate

Ethylene Glycol Monoethyl Ether or its acetate

Halogenated dioxins and furans

Persistent Organic Pollutants (POP), including Perfluorooctane sulphonates

Red phosphorous

Ozone Depleting Chemicals (Class I and II): Chlorofluorocarbons (CFC) and Halons

Radioactive substances

For further information, see CSR's

Environmental Compliance Statement for CSR Green Semiconductor Products.

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CSR Synergy and Bluetooth Software Stack

16 CSR Synergy and Bluetooth Software Stack

BlueCore5‑Multimedia External is supplied with Bluetooth v2.1 + EDR specification compliant stack firmware, which

runs on the internal RISC MCU. The stack firmware is compatible with CSR's póåÉêÖó» wireless Host Software

Platform, for more information see http://www.csr.com/synergy .

The BlueCore5‑Multimedia External software architecture allows Bluetooth processing and the application program

to be shared in different ways between the internal RISC MCU and an external host processor. The upper layers of the Bluetooth stack, above the HCI, can be run either on-chip or on the host processor.

16.1

BlueCore HCI Stack

HCI

LM

LC

48KB RAM

Bluetooth Stack

MCU

USB

Host Host I/O

UART Radio

Microphone or Speaker

PCM / SPDIF / I

2

S

2

Digital Audio

Analogue Audio

Figure 16.1: BlueCore HCI Stack

Note:

Program Memory in Figure 16.1 is external flash.

In the implementation shown in Figure 16.1 the internal MCU runs the Bluetooth stack up to the HCI. The Host

processor must provide all upper layers including the application.

16.1.1 Key Features of the HCI Stack: Standard Bluetooth Functionality

CSR supports the following Bluetooth v2.1 + EDR specification functionality:

Secure simple pairing

Sniff subrating

Encryption pause resume

Packet boundary flags

Encryption

Extended inquiry response

As well as the following mandatory functions of Bluetooth v2.0 + EDR specification:

AFH, including classifier

Faster connection: enhanced inquiry scan (immediate FHS response)

LMP improvements

Parameter ranges

And optional Bluetooth v2.0 + EDR specification functionality:

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CSR Synergy and Bluetooth Software Stack

AFH as master and automatic channel classification

Fast connect: interlaced inquiry and page scan plus RSSI during inquiry

eSCO, eV3 + CRC, eV4, eV5

SCO handle

Synchronisation

The firmware was written against the Bluetooth v2.1 + EDR specification:

Bluetooth components:

Baseband including LC

LM

HCI

Standard UART HCI Transport Layers

All standard Bluetooth radio packet types

Full Bluetooth data rate, enhanced data rates of 2 and 3Mbps

Operation with up to 7 active slaves (this is the maximum Bluetooth v2.1 + EDR specification allows)

Scatternet v2.5 operation

Maximum number of simultaneous active ACL connections: 7

Maximum number of simultaneous active SCO connections: 3 (BlueCore5‑Multimedia External supports all combinations of active ACL and SCO channels for both master and slave operation, as specified by the

Bluetooth v2.1 + EDR specification)

Operation with up to 3 SCO links, routed to one or more slaves

All standard SCO voice coding, plus transparent SCO

Standard operating modes: Page, Inquiry, Page-Scan and Inquiry-Scan

All standard pairing, authentication, link key and encryption operations

Standard Bluetooth power saving mechanisms: Hold, Sniff and Park modes, including Forced Hold

Dynamic control of peers' transmit power via LMP

Master/slave switch

Broadcast

Channel quality driven data rate

All standard Bluetooth test modes

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CSR Synergy and Bluetooth Software Stack

16.1.2 Key Features of the HCI Stack: Extra Functionality

The firmware extends the standard Bluetooth functionality with the following features:

Supports BCSP, a proprietary, reliable alternative to the standard Bluetooth UART Host Transport

Supports H4DS, a proprietary alternative to the standard Bluetooth UART Host Transport, supporting deep

sleep for low-power applications

Provides a set of approximately 50 manufacturer-specific HCI extension commands. This command set,

called BCCMD, provides:

Access to BlueCore5‑Multimedia External general-purpose PIO port

The negotiated effective encryption key length on established Bluetooth links

Access to the firmware random number generator

Controls to set the default and maximum transmit powers; these can help minimise interference between overlapping, fixed-location piconets

Dynamic UART configuration

Bluetooth radio transmitter enable/disable. A simple command connects to a dedicated hardware

switch that determines whether the radio can transmit.

The firmware can read the voltage on a pair of BlueCore5‑Multimedia External external pins. This is normally used to build a battery monitor

A block of BCCMD commands provides access to the BlueCore5‑Multimedia External persistent store configuration database . The database sets the BlueCore5‑Multimedia External Bluetooth address, Class

of Device, Bluetooth radio (transmit class) configuration, SCO routing, LM, etc.

A UART break condition can be used in three ways:

Presenting a UART break condition to the chip can force the chip to perform a hardware reboot

Presenting a break condition at boot time can hold the IC in a low power state, preventing normal

initialisation while the condition exists

With BCSP, the firmware can be configured to send a break to the host before sending data. (This is

normally used to wake the host from a deep sleep state.)

A block of Bluetooth radio test or BIST commands allows direct control of the

BlueCore5‑Multimedia External radio. This aids the development of modules' radio designs, and can be

used to support Bluetooth qualification.

Hardware low power modes: shallow sleep and deep sleep. The chip drops into modes that significantly reduce power consumption when the software goes idle.

SCO channels are normally routed via HCI (over BCSP). However, up to three SCO channels can be routed

over the PCM interface (at the same time as routing any remaining SCO channels over HCI).

Note:

Always refer to the Firmware Release Note for the specific functionality of a particular build.

16.2

Host-Side Software

BlueCore5‑Multimedia External can be ordered with companion host-side software:

BlueCore5-PC includes software for a full Windows 98/ME, Windows 2000 or Windows XP Bluetooth host-

side stack together with IC hardware described in this document.

BlueCore5-Mobile includes software for a full host-side stack designed for modern ARM chip-based mobile

handsets together with IC hardware described in this document.

16.3

CSR Development Systems

CSR's BlueLab Multimedia and BlueTunes (BTN-002-2A) development kits are available to allow the evaluation of

the BlueCore5‑Multimedia External hardware and software, and as toolkits for developing on-chip and host software.

16.4

eXtension

A wide range of software options is available from 3rd parties through the CSR eXtension partner program, see http://www.csr.com/eXtension .

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Ordering Information

17 Ordering Information

Interface Version

Type

Package

Size

UART and USB

TFBGA 169-ball

(Pb free)

8 x 8 x 1.2mm,

0.5mm pitch

Shipment

Method

Tape and reel

Order Number

BC57E687C-GITB-E4

Note:

Minimum order quantity is 2kpcs taped and reeled.

Supply chain: CSR's manufacturing policy is to multisource volume products. For further details, contact your local sales account manager or representative.

To contact a CSR representative, email

[email protected]

or go to www.csr.com/contacts

CS-121064-DSP4

Production Information

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Page 96 of 104

Tape and Reel Information

18 Tape and Reel Information

For tape and reel packing and labelling see

IC Packing and Labelling Specification

.

18.1

Tape Orientation

The general orientation of the TFBGA in the tape is as Figure 18.1 shows.

Circular Holes

Pin A1 Marker

Direction of Feed

Figure 18.1: Tape and Reel Orientation

CS-121064-DSP4

Production Information

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© Cambridge Silicon Radio Limited 2006 - 2010

Page 97 of 104

Tape and Reel Information

18.2

Tape Dimensions

2.0

See Note 6

Ø1.5 MIN

4.0

See Note 1

Ø1.5 +0.1/-0.0

0.30 ± 0.05

R0.3 MAX

1.75

7.5

See Note 6

D1

A1 5.8

Section A-A

1.0

E1

5.8

B1

C1

Direction of feed

A1

8.3

B1

8.3

C1

12.0

D1

16.0 ±

0.3

Figure 18.2: Tape Dimensions

E1

2.0

Unit mm

Notes

1. 10 sprocket hole pitch cumulative tolerance ± 2.0 mm

2. Carrier camber not to exceed 1mm in

250mm.

3. Material: PS + C.

4. A1 and B1 measured on a plane 0.3mm

above the bottom of the pocket.

5. E1 measured from a plane on the inside bottom of the pocket to the top surface of the carrier.

6. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole.

CS-121064-DSP4

Production Information

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Page 98 of 104

18.3

Reel Information

Tape and Reel Information

Figure 18.3: Reel Dimensions

Package

Type

8 x 8 x

1.2mm

TFBGA

Tape

Width

A

Max

16 332

B

1.5

C

13.0

(0.5/-0.2)

D Min N Min

20.2

50

W1

16.4

(2.0/-0.0)

W2

Max

W3

Min Max

Units

22.4

16.4

19.1

mm

18.4

Moisture Sensitivity Level

BlueCore5‑Multimedia External is qualified to moisture sensitivity level MSL3 in accordance with JEDEC J-STD-020.

CS-121064-DSP4

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19 Document References

Document

BlueCore5 Charger Description and Calibration

Procedure Application Note

Reference, Date

CS-113282-ANP

BlueCore

®

5‑Multimedia External Performance

Specification

CS-121698-SPP

BlueCore5-Multimedia External Recommendations for

ESD Protection

CS-114058-ANP

Bluetooth and IEEE 802.11 b/g Co-existence Solutions

Overview

bcore-an-066P

CS-101412-AN

Bluetooth and USB Design Considerations

Core Specification of the Bluetooth System

Electrostatic Discharge (ESD) Sensitivity Testing

Human Body Model (HBM)

IC Packing and Labelling Specification

v2.1 + EDR, 26 July 2007

JESD22-A114

CS-112584-SPP

Moisture / Reflow Sensitivity Classification for

Nonhermitic Solid State Surface Mount Devices

Optimising BlueCore5-Multimedia ADC Performance

Application Note

Selection of I

2

C EEPROMS for Use with BlueCore

bcore-an-008P

Test Suite Structure (TSS) and Test Purposes (TP)

System Specification 1.2/2.0/2.0 + EDR/ 2.1/2.1 + EDR

RF.TS/2.1.E.0, 27 December 2006

Typical Solder Reflow Profile for Lead-free Device

Universal Serial Bus Specification

IPC / JEDEC J-STD-020

CS-120059-AN

CS-116434-ANP v2.0, 27 April 2000

Document References

CS-121064-DSP4

Production Information

This material is subject to CSR's non-disclosure agreement

© Cambridge Silicon Radio Limited 2006 - 2010

Page 100 of 104

Terms and Definitions

Terms and Definitions

Term

3G

BlueCore

®

BlueLab

®

Bluetooth

®

BMC

CDMA

CFC

CMOS

DC

DDS

DFU

DNL

DSP codec

CRC

CSR

CTS

CVSD

DAC dBm e.g.

EBU

EDR

EEPROM

AES

AFC

AFH

AGC

ALU

BCCMD

BCSP

BIST

802.11

8DPSK

π/4 DQPSK

µ-law

A-law

AC

ACK

ACL

ADC

Definition

3 rd

Generation of mobile communications technology

WLAN specification defined by a working group within the IEEE

8-phase Differential Phase Shift Keying

π/4 rotated Differential Quaternary Phase Shift Keying

Audio companding standard (G.711)

Audio companding standard (G.711)

Alternating Current

ACKnowledge

Asynchronous Connection-oriented

Analogue to Digital Converter

Audio Engineering Society

Automatic Frequency Control

Adaptive Frequency Hopping

Automatic Gain Control

Arithmetic logic unit

BlueCore Command

BlueCore Serial Protocol

Built-In Self-Test

Group term for CSR’s range of Bluetooth wireless technology ICs

CSR’s development toolset for building applications to run in the firmware’s VM

Set of technologies providing audio and data transfer over short-range radio connections

Burst Mode Controller

Code Division Multiple Access

Chlorofluorocarbon

Complementary Metal Oxide Semiconductor

Coder decoder

Cyclic Redundancy Check

Cambridge Silicon Radio

Clear to Send

Continuous Variable Slope Delta Modulation

Digital to Analogue Converter

Decibels relative to 1mW

Direct Current

Direct Digital Synthesis

Device Firmware Upgrade

Differential Non Linearity (ADC accuracy parameter)

Digital Signal Processor

exempli gratia

, for example

European Broadcasting Union

Enhanced Data Rate

Electrically Erasable Programmable Read Only Memory

CS-121064-DSP4

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Kalimba

LNA

LSB

MAC

Mbps

MCU

MIPS

MISO

LC

LC

LCD

LED

LM

LMP

MMU

MSB

N/A

I²S i.e.

I/O

IC

ID

IF

HBM

HCI

I²C

IIR

INL

IQ

ISDN

JEDEC

Term eSCO

ESD

ESR etc

FET

FHS

FSK

GCI

GFSK

GSM

H4DS

CS-121064-DSP4

Terms and Definitions

Definition

Extended SCO

Electrostatic Discharge

Equivalent Series Resistance

et cetera

, and the rest, and so forth

Field Effect Transistor

Frequency Hop Synchronisation

Frequency Shift Keying

General Circuit Interface

Gaussian Frequency Shift Keying

Global System for Mobile communications

H4 Deep Sleep

Human Body Model

Host Controller Interface

Inter-Integrated Circuit Interface

Inter-Integrated Circuit Sound

Id est

, that is

Input/Output

Integrated Circuit

Identifier

Intermediate Frequency

Infinite Impulse Response (filter)

Integral Non Linearity (ADC accuracy parameter)

In-Phase and Quadrature

Integrated Services Digital Network

Joint Electron Device Engineering Council (now the JEDEC Solid State Technology

Association)

An open platform DSP co-processor, enabling support of enhanced audio applications, such as echo and noise suppression, and file compression / decompression

An inductor (L) and capacitor (C) network

Link Controller

Liquid-Crystal Display

Light-Emitting Diode

Link Manager

Link Manager Protocol

Low Noise Amplifier

Least-Significant Bit (or Byte)

Multiplier and ACcumulator

Megabits per second

MicroController Unit

Million Instructions Per Second

Master In Slave Out

Memory Management Unit

Most Significant Bit (or Byte)

Not Applicable

Production Information

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© Cambridge Silicon Radio Limited 2006 - 2010

Page 102 of 104

Terms and Definitions

RF

RISC

RoHS

ROM

RSSI

RTS

RX

SBC

SCO

SIG

SNR

S/PDIF

PCB

PCM

PD

PIO plc

Term

NC

NOP

NSMD

O.C.

PA

PC

POP ppm

PS Key

PSRR

PU

PVC

RAM

RC

RCA

SPI

SPL

TCXO

TFBGA

THD+N

TP

TSS

TX

UART

CS-121064-DSP4

Definition

Not Connect

No Operation

Non Solder Mask Defined

Open Circuit

Power Amplifier

Personal Computer

Printed Circuit Board

Pulse Code Modulation

Pull-down

Programmable Input/Output

Public Limited Company

Persistent Organic Pollutants parts per million

Persistent Store Key

Power Supply Rejection Ratio

Pull-up

Poly Vinyl Chloride

Random Access Memory

Resistor Capacitor

Radio Corporation of America, normally used to refer to a RCA connector (also know as phono connector or Cinch connector)

Radio Frequency

Reduced Instruction Set Computer

Restriction of Hazardous Substances in Electrical and Electronic Equipment Directive

(2002/95/EC)

Read Only Memory

Received Signal Strength Indication

Request To Send

Receive or Receiver

Sub-band Coding

Synchronous Connection-Oriented

(Bluetooth) Special Interest Group

Signal-to-Noise Ratio

Sony/Philips Digital InterFace (also IEC 958 type II, part of IEC-60958). An interface designed to transfer stereo digital audio signals between various devices and stereo components with minimal loss.

Serial Peripheral Interface

Sound Pressure Level

Temperature Compensated crystal Oscillator

Thin Fine-Pitch Ball Grid Array

Total Harmonic Distortion and Noise

Test Purposes

Test Suite Structure

Transmit or Transmitter

Universal Asynchronous Receiver Transmitter

Production Information

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Page 103 of 104

Term

Unity

USB

VCO

VM

VoIP

W-CDMA

WLAN

Definition

CSR’s coexistence scheme

Universal Serial Bus

Voltage Controlled Oscillator

Virtual Machine

Voice over Internet Protocol

Wideband Code Division Multiple Access

Wireless Local Area Network

Terms and Definitions

CS-121064-DSP4

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