USB-Blaster II Cable User Guide

USB-Blaster II Cable User Guide
USB-Blaster II Download Cable User
Guide
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TOC-2
Contents
Setting Up the USB-Blaster II Download Cable................................................. 1-1
Supported Devices and Systems.................................................................................................................1-1
Power Source Requirements.......................................................................................................................1-1
Software Requirements and Support.........................................................................................................1-2
Installing the Download Cable for Configuration or Programming....................................................1-2
Installing the USB-Blaster II Driver on Windows 7/8 Systems.............................................................1-3
Installing the USB-Blaster II Driver on Linux Systems.......................................................................... 1-4
Installing the USB-Blaster II Driver on Windows XP Systems............................................................. 1-5
Setting Up the USB-Blaster II Hardware with the Quartus Prime Software....................................... 1-5
USB-Blaster II Download Cable Specifications..................................................2-1
Voltage Requirements................................................................................................................................. 2-1
Cable-to-Board Connection....................................................................................................................... 2-2
USB-Blaster II Plug Connection................................................................................................................ 2-2
10-Pin Female Plug Signal Names and Programming Modes...............................................................2-3
Circuit Board Header Connection.............................................................................................................2-4
Operating Conditions..................................................................................................................................2-5
JTAG Timing Constraints and Waveforms............................................................................................. 2-7
Changing the TCK Frequency................................................................................................................... 2-8
Additional Information......................................................................................A-1
Document Revision History...................................................................................................................... A-1
Certification Statements.............................................................................................................................A-2
RoHS Compliance...........................................................................................................................A-2
USB 2.0 Certification...................................................................................................................... A-2
CE EMI Conformity Caution........................................................................................................ A-2
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The USB-Blaster™ II download cable interfaces a USB port on a host computer to an Altera® FPGA
mounted on a printed circuit board. The download cable sends data from the PC to a standard 10-pin
header connected to the FPGA. You can use the download cable for the following:
• Iteratively download configuration data to a system during prototyping
• Program data into the system during production
• Advanced Encryption Standard (AES) key and fuse programming
Supported Devices and Systems
You can use the USB-Blaster II download cable to download configuration data to the following Altera
devices:
•
•
•
•
Stratix® series FPGAs
Cyclone® series FPGAs
MAX® series CPLDs
Arria® series FPGAs
You can perform in-system programming of the following devices:
• EPC4, EPC8, and EPC16 enhanced configuration devices
• EPCS1, EPCS4, EPCS16, EPCS64, and EPCS/Q128, EPCQ256, EPCQ-L and EPCQ512 serial configu‐
ration devices
The download cable supports target systems using the following:
• 5.0-V TTL, 3.3-V LVTTL/LVCMOS
• Single-ended I/O standards from 1.5 V to 3.3 V
Power Source Requirements
• 5.0 V from the USB cable
• Between 1.5 V and 5.0 V from the target circuit board
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
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Software Requirements and Support
Software Requirements and Support
•
•
•
•
Windows 7/8 (32-bit and 64-bit)
Windows XP (32-bit and 64-bit)
Windows Server 2008 R2 (64-bit)
Linux platforms such as Red Hat Enterprise 5
Use the Quartus® Prime software version 14.0 or later to configure your device.
Note: Quartus Prime software version 13.1 supports most of the download cable’s capabilities. If you use
this version, install the latest patch for full compatibility.
The download cable also supports the following tools:
• Quartus Prime Programmer (and stand-alone version)
• Quartus Prime SignalTap® II Logic Analyzer (and stand-alone version)
• JTAG and debug tools supported by the JTAG Server. For example:
• System Console
• Nios II debugger
• ARM DS-5 debugger
Installing the Download Cable for Configuration or Programming
1.
2.
3.
4.
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Disconnect the power cable from the circuit board.
Connect the download cable to the USB port on your computer and to the USB-Blaster II port.
Connect the download cable to the 10-pin header on the device board.
Reconnect the power cable to reapply power to the circuit board.
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Installing the USB-Blaster II Driver on Windows 7/8 Systems
1-3
Figure 1-1: The USB-Blaster II Download Cable
Note: For plug and header dimensions, pin names, and operating conditions, see Chapter 2, USB-Blaster
II Download Cable Specifications.
Related Information
USB-Blaster II Download Cable Specifications on page 2-1
Installing the USB-Blaster II Driver on Windows 7/8 Systems
You must have system administration (administrator) privileges to install the USB-Blaster II download
cable drivers.
The download cable drivers are included in the Quartus Prime software installation. Before you begin the
installation, verify that the USB-Blaster II driver is located in your directory: \<Quartus Prime system
directory>\drivers\usb-blaster-ii.
1. Connect the download cable to your computer’s USB port.
When plugged in for the first time, a message appears stating Device driver software was not success‐
fully installed.
2. From the Windows Device Manager, locate Other devices and right-click the top USB-BlasterII.
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Installing the USB-Blaster II Driver on Linux Systems
3.
4.
5.
6.
7.
You need to install drivers for each interface: one for the JTAG interface and one for the System
Console interface.
On the right-click menu, click Update Driver Software. The Update Driver Software - USB BlasterII
dialog appears.
Click Browse my computer for driver software to continue.
Click Browse… and browse to the location of the driver on your system: \<Quartus Prime system
directory>\drivers\usb-blaster-ii. Click OK.
Click Next to install the driver.
Click Install when asked if you want to install.
You should now have a JTAG cable showing in the Device Manager.
8. Now, install the driver for the other interface. Go back to step 2 and repeat the process for the other
USB-BlasterII device.
When you are finished, you will have added Altera USB-Blast II (JTAG interface) under JTAG cables.
Installing the USB-Blaster II Driver on Linux Systems
For Linux, the USB-Blaster II download cable supports Red Hat Enterprise 5 and above.
To access the download cable, the Quartus Prime software uses the built-in Red Hat USB drivers, the USB
file system (usbfs). By default, root is the only user allowed to use usbfs. You must have system adminis‐
tration (root) privileges to configure the USB-Blaster II download cable drivers.
1. Create a file named /etc/udev/rules.d/51-usbblaster.rules and add the following lines to it. (The .rules file
may already exist if you have installed an earlier USB-Blaster version.)
# USB-Blaster II
BUS=="usb", SYSFS{idVendor}=="09fb", SYSFS{idProduct}=="6010", MODE="0666"
BUS=="usb", SYSFS{idVendor}=="09fb", SYSFS{idProduct}=="6810", MODE="0666"
Caution: There should be only three lines in this file, one starting with a comment and two starting
with BUS. Do not add extra line breaks to the .rules file.
2. Complete your installation by setting up the programming hardware in the Quartus Prime software.
Go to the “Setting Up the USB-Blaster II Hardware with the Quartus Prime Software” section on the
following page.
For more information about USB-Blaster II driver installation, refer to the Cable and Adapter Drivers
Information page.
Related Information
• Setting Up the USB-Blaster II Hardware with the Quartus Prime Software on page 1-5
• Cable and Adapter Drivers Information
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1-5
Installing the USB-Blaster II Driver on Windows XP Systems
You must have system administration (administrator) privileges to install the USB-Blaster II download
cable driver.
The download cable drivers are included in the Quartus Prime software installation. Before you begin the
installation, verify that the USB-Blaster II driver is located in your directory: \<Quartus Prime system
directory>\drivers\usb-blaster-ii.
Setting Up the USB-Blaster II Hardware with the Quartus Prime Software
1.
2.
3.
4.
5.
6.
7.
Start the Quartus Prime software.
From the Tools menu, click Programmer.
Click Hardware Setup.
Click the Hardware Settings tab.
From the Currently selected hardware list, select USB-Blaster II.
Click Close.
In the Mode list, choose an appropriate programming mode. The table below describes each mode.
Table 1-1: Programming Modes
Mode
Mode Description
Joint Test Action Group (JTAG)
Programs or configures all Altera devices supported by Quartus
Prime software via JTAG programming.
In-Socket Programming
Not supported by the USB-Blaster II.
Passive Serial Programming
Configures all Altera devices supported by Quartus Prime
software excluding enhanced configuration devices (EPC) and
serial configuration devices (EPCS/Q).
Active Serial Programming
Programs a single EPCS1, EPCS4, EPCS16, EPCS64, EPCS/
Q128, EPCQ256, EPCQ-L and EPCQ512 device.
For detailed help on using the Quartus Prime Programmer, refer to the Quartus Prime Handbook.
Related Information
Quartus Prime Handbook
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Voltage Requirements
The USB-Blaster II VCC(TRGT) pin must be connected to a specific voltage for the device being programmed.
Connect pull-up resistors to the same power supply as the USB-Blaster II: VCC(TRGT).
Table 2-1: USB-Blaster II VCC(TRGT) Pin Voltage Requirements
Device Family
USB-Blaster II VCC Voltage Required
Arria GX
As specified by VCCSEL
Arria II GX
As specified by VCCPD or VCCIO of Bank 8C
Arria V
As specified by VCCPD Bank 3A
Arria 10
As specified by VCCPGM or VCCIO
Cyclone III
As specified by VCCA or VCCIO
Cyclone IV
As specified by VCCIO. Bank 9 for Cyclone IV GX and Bank 1
for Cyclone IV E devices.
Cyclone V
As specified by VCCPD Bank 3A
EPC4, EPC8, EPC16
3.3 V
EPCS1, EPCS4, EPCS16, EPCS64,
EPCS128
3.3 V
EPCS/Q16, EPCS/Q64, EPCS/Q128,
EPCQ256, EPCQ512
3.3 V
EPCQ-L
1.8 V
MAX II, MAX V
As specified by VCCIO of Bank 1
MAX 10
As specified by VCCIO
Stratix II, Stratix II GX
As specified by VCCSEL
Stratix III, Stratix IV
As specified by VCCPGM or VCCPD
Stratix V
As specified by VCCPD Bank 3A
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
101 Innovation Drive, San Jose, CA 95134
ISO
9001:2008
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Cable-to-Board Connection
Cable-to-Board Connection
A standard USB cable connects to the USB port on the device.
Figure 2-1: USB-Blaster II Download Cable Block Diagram
VCC
USB
Receptacle
LVDS
Drivers/Receivers
EPM570M100C5
USB Interface
Chip
LVDS
Cabling
I/O
Voltage
Translator Circuitry
Pin 1
10-Pin
Female Plug
VCC (TRGT)
I/O
I/Os
I/O
I/O
I/O
I/Os
I/O
I/O
USB-Blaster II Plug Connection
The 10-pin female plug connects to a 10-pin male header on the circuit board containing the target
device.
Figure 2-2: USB-Blaster II 10-Pin Female Plug Dimensions - Inches & Millimeters
0.37 (9.4) Typ.
10
8
6
4
2
9
7
5
3
1
0.24 (6.1) Typ.
0.04 (1.0) Typ.
.10 (2.5)Sq.
.025
0.15 (3.8) Typ. (.63)Sq.
0.70 (17.8) Typ.
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10-Pin Female Plug Signal Names and Programming Modes
2-3
Figure 2-3: USB-Blaster II Dimension - Inches and Millimeters
10-Pin Female Plug Signal Names and Programming Modes
Table 2-2: 10-Pin II Female Plug Signal Names and Programming Modes
Pin
Active Serial (AS) Mode
Signal Name
Description
1
DCLK
Clock signal
2
GND
3
CONF_DONE
4
VCC(TRGT)
5
nCONFIG
Signal Name
Description
JTAG Mode
Signal Name
Description
Clock signal TCK
Clock signal
Signal ground GND
Signal
ground
GND
Signal ground
Configuration CONF_DONE
done
Configuratio TDO
n done
Configuration
done
Target power
supply
Target
power
supply
Target power
supply
DCLK
VCC(TRGT)
Configuration nCONFIG
control
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Passive Serial (PS) Mode
VCC(TRGT)
Configuratio TMS
n control
Configuration
control
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Circuit Board Header Connection
Active Serial (AS) Mode
Pin
Signal Name
6
nCE
7
DATAOUT
8
nCS
9
ASDI
10
GND
Passive Serial (PS) Mode
Description
Cyclone chip
enable
Active serial
data out
Signal Name
JTAG Mode
Description
Cyclone
chip enable
-
Signal Name
PROC_RST(1)
Description
Cyclone chip
enable
Active serial data out
Active serial data
out
Serial
configuration
device chip
select
Serial
configuratio
n device
chip select
Serial configura‐
tion device chip
select
Active serial
data in
Active serial TDI
data in
Active serial data
in
Signal
ground
Signal ground
nSTATUS
DATA0
Signal ground GND
GND
Note: In JTAG mode, the PROC_RST pin can be used to trigger warm reset of the HPS block when
prompted via the ARM DS-5 debugger. PROC_RST is an active low signal and not an open collector
pin. As such, it is not recommended to connect PROC_RST to HPS_nRST directly. You should instead
connect this pin to a secondary device such as the MAX V CPLD, and use the device to manage the
reset network for HPS.
Circuit Board Header Connection
The 10-pin male header, which connects to the download cable's 10-pin female plug, has two rows of five
pins. The pins are connected to the device’s programming or configuration pins.
Caution: If the header connection on the circuit board is a male receptacle, it must have a key notch.
Without a key notch, the 10-pin female plug will not connect. The following figure shows a
typical 10-pin male header with a key notch.
Figure 2-4: 10-Pin Male Header Dimensions - Inches and Millimeters
Top View
Side View
0.100 (2.540)
0.100
0.025 (0.635) Sq.
0.235 (5.969)
A key notch is required.
(1)
Use pin 6 for a hard processor reset under JTAG mode.
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Operating Conditions
Although a 10-pin surface mount header can be used for the download cable, Altera recommends using a
through-hole connector. Through-hole connectors hold up better under the repeated insertion and
removal.
Operating Conditions
The following tables summarize the maximum ratings, recommended operating conditions, and DC
operating conditions for the USB-Blaster II cable.
Table 2-3: USB-Blaster II Cable Absolute Maximum Ratings
Symbol
Parameter
Conditions
Min
Max
Unit
VCC(TRGT) Target supply voltage
With respect to ground
–0.5
6.5
V
VCC(USB)
USB supply voltage
With respect to ground
–0.5
6.0
V
II
Target side input current
Pin 7
–100.0
100.0
mA
II(USB)
USB supply current
VBUS
–
200.0
mA
Io
Target side output current
Pins: 1, 5, 6, 8, 9
–50.0
50.0
mA
Min
Max
Unit
Table 2-4: USB-Blaster II Cable Recommended Operating Conditions
Symbol
Parameter
VCC(TRGT)
Conditions
Target supply voltage, 5.0-V
operation
—
4.75
5.25
V
Target supply voltage, 3.3-V
operation
—
3.0
3.6
V
Target supply voltage, 2.5-V
operation
—
2.375
2.625
V
Target supply voltage, 1.8-V
operation
—
1.71
1.89
V
Target supply voltage, 1.5-V
operation
—
1.43
1.57
V
Min
Max
Unit
0.7 x
VCC(TRGT
—
V
—
V
Table 2-5: USB-Blaster II Cable DC Operating Conditions
Symbol
Parameter
High-level input voltage
VIH
Conditions
VCC(TRGT) >= 2.0 V
)
High-level input voltage
VCC(TRGT) < 2.0 V
0.65 x
VCC(TRGT
)
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Operating Conditions
Symbol
Parameter
Low-level input voltage
VIL
Conditions
Min
VCC(TRGT) >= 2.0 V
—
Max
Unit
0.3 x
VCC(TR
V
GT)
Low-level input voltage
VCC(TRGT) >= 2.0 V
—
0.2 x
VCC(TR
V
GT)
VOH
VOL
ICC(TRGT)
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5.0-V high-level output voltage
VCC(TRGT) = 4.5 V, IOH = -32
mA
3.8
—
V
3.3-V high-level output voltage
VCC(TRGT) = 3.0 V, IOH = -24
mA
2.4
—
V
2.5-V high-level output voltage
VCC(TRGT) = 2.3 V, IOH = -12
mA
1.9
—
V
1.8-V high-level output voltage
VCC(TRGT) = 1.65 V, IOH = -8
mA
1.2
—
V
1.5-V high-level output voltage
VCC(TRGT) = 1.4 V, IOH = -6
mA
1.0
—
V
5.0-V low-level output voltage
VCC(TRGT) = 4.5 V, IOL = 32
mA
—
0.55
V
3.3-V low-level output voltage
VCC(TRGT) = 3.0 V, IOL = 24
mA
—
0.55
V
2.5-V low-level output voltage
VCC(TRGT) = 2.3 V, IOL =
12mA
—
0.3
V
1.8-V low-level output voltage
VCC(TRGT) = 1.65 V, IOL =
8mA
—
0.45
V
1.5-V low-level output voltage
VCC(TRGT) = 1.4 V, IOL = 6mA
—
0.3
V
Operating current (No Load)
VCC(TRGT)=5.5 V
—
316
uA
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JTAG Timing Constraints and Waveforms
2-7
JTAG Timing Constraints and Waveforms
Figure 2-5: Timing Waveform for JTAG Signals (From Target Device Perspective)
tJCP
tJCH
tJCL
TCK
JTAG Output
tJPCO
TDO
TCK
JTAG Inputs
tJPSU_TMS
tJPH
TMS
tJPSU_TDI
TDI
To use the USB-Blaster II at the maximum capability (24 MHz), meet the timing constraints like in the
tabe below for the target device.
The timing constraints require that you consider device specifications as well as trace propagation delays.
If you do not follow the recommended constraints, you might encounter timing issues at 24 MHz. If the
target design cannot meet these constraints, reduce the possibility of timing issues by slowing the TCK
frequency. See “Changing the TCK Frequency” section for instructions on running the USB-Blaster II at a
slower speed.
Table 2-6: JTAG Timing Constraints for the Target Device
Symbol
Parameter
Min
Max
Unit
tJCP
TCK clock period
41.67
—
ns
tJCH
TCK clock high
20.83
—
ns
tJCL
TCK clock low time
20.83
—
ns
5.46 (2.5 V)
ns
tJPCO
time
JTAG port clock to —
JTAG Header
output
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2.66 (1.5 V)
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Changing the TCK Frequency
Symbol
tJPSU_TDI
tJPSU_TMS
tJPH
Parameter
Min
Max
Unit
JTAG port setup
time (TDI)
—
24.42
ns
JTAG port setup
time (TMS)
—
26.43
ns
JTAG port hold
time
—
17.25
ns
The simulated timing is based on a slow timing model, which is a worst-case scenario environment.
For device-specific JTAG timing information, refer to the related device data sheet.
Figure 2-6: USB-Blaster II Download Cable Timing Constraints
Launch/Latch
Registers
JTAG
Header
USB Blaster II
MAX
Device
Launch/Latch
Registers
Target Board
JTAG Cable
11.575 ns 11.627 ns
FPGA
Board Traces
Your Own Set Input
Measurement Delay
If you cannot meet 24 MHz, you must decrease the frequencies to 16-6 MHz. Below is some example code
to set the TCK maximum frequency to 6 MHz:
jtagconfig --setparam 1 JtagClock 6M
Related Information
• Changing the TCK Frequency on page 2-8
• Documentation: Data Sheets
Changing the TCK Frequency
The USB-Blaster II download cable has a default TCK frequency of 24 MHz. Where signal integrity and
timing prevents operating at 24 MHz, change the TCK frequency of the USB-Blaster II:
1. Open the command line interface with the Quartus Prime bin directory in your path (for example, C:\
altera\14.0\quartus\bin64).
2. Type the following command to change the TCK frequency:
jtagconfig --setparam <cable number> JtagClock <frequency><unit prefix>
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Changing the TCK Frequency
2-9
Where:
• <cable number> is the USB-Blaster II cable to be modified.
• <frequency> is the desired TCK frequency. Use one the following supported rates:
•
•
•
•
24 MHz
16 MHz
6 MHz
24/n MHz (between 10 kHz and 6 MHz, where n represents an integer value number)
• <unit prefix> is the unit prefix for the frequency (e.g., M for MHz).
Example for setting TCK maximum frequency to 6 MHz:
jtagconfig --setparam 1 JtagClock 6M
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Document Revision History
Table A-1: USB-Blaster II Download Cable User Guide Revision History
Date
Version
December 2015
2015.12.11
Changes
Updated Sections:
• Supported Devices and Systems
• Setting Up the USB-Blaster II Hardware with the Quartus II
Software
• Voltage Requirements
• 10-Pin Female Plug Signal Names and Programming Modes
September 2014
1.2
• Added that the USB-II download cable supports Advanced
Encryption Standard (AES) key and fuse programming.
• Added magenta LED color to Figure 1-1 supporting multiple cable
use.
• Clarified a cross reference pointing to device-specific JTAG timing
information.
June 2014
1.1
• Added LED color table to Figure 1-1.
• Added “JTAG Timing Constraints and Waveforms” section.
• Added “Changing the TCK Frequency” section.
January 2014
1.0
Initial release.
© 2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are
trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as
trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html. Altera warrants performance
of its semiconductor products to current specifications in accordance with Altera's standard warranty, but reserves the right to make changes to any
products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information,
product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device
specifications before relying on any published information and before placing orders for products or services.
www.altera.com
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Certification Statements
Certification Statements
RoHS Compliance
The table below lists hazardous substances included with the USB-Blaster download cable.
A value of 0 indicates that the concentration of the hazardous substance in all homogeneous materials in
the parts is below the relevant threshold as specified by the SJ/T11363-2006 standard.
Table A-2: Hazardous Substances and Concentration
Part Name
Lead (Pb)
Cadmiu
m (Cd)
Hexavelent
Chromium
(Cr6+)
Mercury
(Hg)
Polybromi‐
nated
biphenyls
(PBB)
Polybrominated
diphenyl Ethers
(PBDE)
Electronic
Components
0
0
0
0
0
0
Populated
Circuit Board
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Manufacturing
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USB 2.0 Certification
This product is USB 2.0 certified.
CE EMI Conformity Caution
This board is delivered conforming to relevant standards mandated by Directive 2004/108/EC. Because of
the nature of programmable logic devices, it is possible for the user to modify the kit in such a way as to
generate electromagnetic interference (EMI) that exceeds the limits established for this equipment. Any
EMI caused as the result of modifications to the delivered material is the responsibility of the user.
Altera Corporation
Additional Information
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