THDB-HDMI

THDB-HDMI

Terasic HDMI Video Daughter Board

User Manual

1

CONTENTS

Chapter 1 Introduction ...................................................................................... 2

1.1 About the KIT .......................................................................................................................................... 2

1.2 Assemble the HDMI Board ...................................................................................................................... 3

1.3 Getting Help ............................................................................................................................................. 3

Chapter 2 HDMI Board ....................................................................................... 4

2.1 Features .................................................................................................................................................... 4

2.2 Layout and Componets ............................................................................................................................ 7

2.3 Block Diagram of HDMI Signal Transmission ........................................................................................ 8

2.4 Block Diagram of HDMI Signal Receiving ........................................................................................... 10

2.5 Generate Pin Assignments ..................................................................................................................... 11

2.6 Pin Definition of HSTC Connector ........................................................................................................ 13

Chapter 3 Demonstration ................................................................................ 21

3.1 Introduction ............................................................................................................................................ 21

3.2 System Requirements ............................................................................................................................. 21

3.3 Setup the Demonstration ........................................................................................................................ 22

3.4 Operation................................................................................................................................................ 23

Chapter 4 Case Study ....................................................................................... 27

4.1 Overview ................................................................................................................................................ 27

4.2 System Function Block .......................................................................................................................... 27

4.3 NIOS Program ....................................................................................................................................... 31

Chapter 5 Appendix ......................................................................................... 35

5.1 Revision History .................................................................................................................................... 35

5.2 Always Visit THDB-HDMI Webpage for Update.................................................................................. 35

1

Chapter 1

Introduction

THDB-HDMI is a HDMI transmitter/receiver daughter board with HSTC (High Speed Terasic

Connector) interface. Host boards, supporting HSTC-compliant connectors, can control the HDMI daughter board through the HSTC interface.

This THDB-HDMI kit contains complete reference designs with source code written in Verilog and

C, for HDMI signal transmitting and receiving. Based on reference designs, users can easily and quickly develop their applications.

1 .

.

1 A b o u t t h e K

I

I T

This section describes the package content.

The THDB-HDMI package, as shown in

Figure 1-1

, contains:

THDB-HDMI board x 1

System CD-ROM x 1

The CD contains technical documents of the HDMI receiver and transmitter, and one reference design for HDMI transmitting and receiving with source code.

Figure 1-1 THDB-HDMI Package

2

1 .

.

2 A s s e m b l l e t h e H D M

I

I B o a r d

This section describes how to connect the HDMI daughter board to a main board, and use DE3 as an example.

The HDMI board connects to main boards through the HSTC interface. For DE3, the HDMI daughter board can be connected to any one of four HSTC connectors on DE3.

Figure 1-2

shows a HDMI daughter board connected to the HSTC connector of DE3. Due to high

speed data rate in between, users are strongly recommended to screw the two boards together.

Note. Do not attempt to connect/remove the HDMI daughter board to/from the main board when the power is on, or the hardware could be damaged.

Figure 1-2 Connect HDMI daughter board to DE3 board

1 .

.

3 G e t t i i n g

H e l l p

Here are some places to get help if you encounter any problem:

Email to [email protected]

Taiwan & China: +886-3-550-8800

Korea : +82-2-512-7661

English Support Line: +1-408-512-12336

3

Chapter 2

HDMI Board

This chapter will illustrate technical details of HDMI board. Users may modify the reference designs for various purposes accordingly.

2 .

.

1 F e a t u r e s

This section describes the major features of the HDMI board.

Board Features:

One HSTC interface for connection purpose

One HDMI transmitter with single transmitting port

One HDMI receiver with dual receiving ports

Two 2K EEPROM for storing EDID of two receiver ports separately

Powered from 3.3V pins of HSTC connector

HDMI Transmitter Features:

1. HDMI 1.4 transmitter

2. Compliant with HDMI 1.3, HDMI1.4a 3D,HDCP 1.4 and DVI 1.1 specifications

3. Supporting link speeds of up to 2.25 Gbps (link clock rate of 225MHZ)

4. Supporting diverse 3D formats which are compliant with HDMI 1.4a 3D specification. o Supporting 3D video up to [email protected]/24/30Hz,[email protected]/59.94/60/Hz o Supporting formats: framing packing, side-by-side(half),top-and-bottom

5. Various video input interface supporting digital video standards such as: o 24/30/36-bit RGB/YCbCr 4:4:4 o 16/20/24-bit YCbCr 4:2:2 o 8/10/12-bit YCbCr 4:2:2 (CCIR-656)

6. Bi-direction Color Space Conversion (CSC) between RGB and YCbCr color space with programmable coefficients

7. Up/down sampling between YCbCr 4:4:4 and YCbCr 4:2:2

4

8. Either for conversion from 12-bit/10-bit to component to 8-bit

9. Support Gammat Metadata packet

10. Digital audio input interface supporting: o Up to four I2S interface supporting 8-channel audio, with sample rates of 32~192 kHz and sample sizes of 16~24 bits o S/PDIF interface supporting PCM, Dolby Digital, DTS digital audio at up to 192kHz frame rate o Support for high-bit-rate (HBR) audio such as DTS-HD and Dolby TrueHD through the four I2S interface or the S/PDIF interface, with frame rates as high as 768kHz o Support for 8-channel DSD audio through dedicated inputs o Compatible with IEC 60958 and IEC 61937 o Audio down-sampling of 2X and 4X

11. Software programmable, auto-calibrated TMDS source terminations provide for optimal source signal quality

12. Software programmable HDMI output current level

13. MCLK input is optional for audio operation. Users could opt to implement audio input interface with or without MCLK

14. Integrated pre-programmed HDCP keys

15. Purely hardware HDCP engine increasing the robustness and security of HDCP operation

16. Monitor detection through Hot Plug Detection and Receiver Termination Detection

17. Embedded full-function pattern generator

18. Intelligent, programmable power management

Table 2-1

lists supported input video format:

Table 2-1 Input video formats supported by the HDMI board

Input Pixel Clock Frequency(MHz)

Color space

RGB

YCbCr

Video

Format

4:4:4

4:4:4

4:2:2

Bus Hsync/

480i 480p XGA 720p 1080i SXGA 1080p UXGA

Width

24

30/36

Vsync

Separate

13.5 27

13.5 27

12/15/18 Separate 13.5 27

24

Separate

13.5 27

30/36 13.5 27

12/15/18 Separate 13.5 27

16/20/24

Separate 13.5 27

Embedded 13.5 27

12/15/18 Separate 27 54

65

65

65

65

65

65

74.25 74.25 108

74.25 74.25 108

74.25 74.25

74.25 74.25 108

74.25 74.25 108

74.25 74.25

74.25 74.25

74.25 74.25

148.5 148.5

148.5

148.5

162

148.5 162

148.5

148.5

148.5

5

Embedded 27 54

148.5 148.5

HDMI Receiver Features:

1. Dual-Port HDMI 1.4 receiver

2. Compliant with HDMI 1.3, HDMI1.4a 3D,HDCP 1.4 and DVI 1.1 specifications

3. Supporting link speeds of up to 2.25 Gbps (link clock rate of 225MHZ)

4. Supporting diverse 3D formats which are compliant with HDMI 1.4a 3D specification. o Supporting 3D video up to [email protected]/24/30Hz,[email protected]/59.94/60/Hz o Supporting formats: framing packing, side-by-side(half),top-and-bottom

5. Various video input interface supporting digital video standards such as: o 24/30/36-bit RGB/YCbCr 4:4:4 o 16/20/24-bit YCbCr 4:2:2 o 8/10/12-bit YCbCr 4:2:2 (ITU BT-656) o 12/15/18-bit double data rate interface (data bus width halved, clocked with both rising and falling edges) for RGB/YCbCr 4:4:4 o 24/30/36-bit double data rate interface (full bus width, pixel clock rate halved, clocked with both rising and falling edges) o Input channel swap o MSB/LSB swap

6. Bi-direction Color Space Conversion (CSC) between RGB and YCbCr color space with programmable coefficients

7. Up/down sampling between YCbCr 4:4:4 and YCbCr 4:2:2

8. Dither for conversion from 12-bit/10-bit to component to 10-bit/8-bit

9. Support Gammat Metadata packet

10. Digital audio output interface supporting: o Up to four I2S interface supporting 8-channel audio, with sample rates of 32~192 kHz and sample sizes of 16~24 bits o S/PDIF interface supporting PCM, Dolby Digital, DTS digital audio at up to 192kHz frame rate o Optional support for 8-channel DSD audio up to 8 channels at 88.2kHz sample rate o Support for high-bit-rate (HBR) audio such as DTS-HD and Dolby TrueHD through the four I2S interface or the S/PDIF interface, with frame rates as high as 768kHz o Automatic audio error detection for programmable soft mute, preventing annoying harsh output sound due to audio error or hot-unplug

11. Auto-calibrated input termination impedance provides process-, voltage- and temperature-invariant matching to the input transmission lines.

6

12. Integrated pre-programmed HDCP keys

13. Intelligent, programmable power management

Table 2-2

lists the supported output video formats:

Table 2-2 Output video formats supported by the HDMI board

Output Pixel Clock Frequency(MHz)

Color space

RGB

YCbCr

Video

Format

4:4:4

4:4:4

4:2:2

Bus

16/20/24

12/15/18

Hsync/

Width

24

30/36

Vsync

Separate

13.5 27

13.5 27

12/15/18 Separate 13.5 27

24

Separate

13.5 27

30/36 13.5 27

12/15/18 Separate 13.5 27

Separate

Embedded 13.5 27

Separate

480i 480p XGA 720p 1080i SXGA 1080p UXGA

13.5 27

27

Embedded 27

54

54

65

65

65

65

65

65

74.25 74.25 108

74.25 74.25 108

74.25 74.25

74.25 74.25 108

74.25 74.25 108

74.25 74.25

74.25 74.25

74.25 74.25

148.5 148.5

148.5 148.5

148.5

148.5

148.5 162

148.5

148.5

148.5

162

2 .

.

2 L a y o u t a n d C o m p o n e n t s

The photo of the HDMI board is shown in

Figure 2-1

and

Figure 2-2

. It indicates the location of

the connectors and key components.

Figure 2-1 HDMI transmitter and receiver on the front of the HDMI board

7

Figure 2-2 On the back of the HDMI board with HSTC connector and HDMI ports

The THDB-HDMI board includes the following key components:

Receiver (U3)

Receiver port 1/2 (J2/J3)

Transmitter (U6)

Transmitter port (J4)

27MHZ OSC (Y1)

HSTC expansion connector (J1)

Receiver I2C EEPORM (U4/U5)

RX Regulator (REG1)

TX Regulator (REG2)

Level shifter (U2)

2 .

.

3

B l l o c k D i i a g r a m o f f H D M I S i i g n a l l

T r a n s m i i s s i i o n

This section describes the block diagram of HDMI signal transmission.

Figure 2-3

shows the block diagram of HDMI signal transmission. Please refer to the schematic

included in the CD for more details. The HDMI transmitter is controlled through I2C interface, where the host works as master and the transmitter works as a slave. Because the pin PCADR is pulled low, the transmitter I2C device address is set to 0x98. Through the I2C interface, the host board can access the internal registers of transmitter to control its behavior.

8

Figure 2-3 The block diagram of the HDMI signal transmission

The host can use reset pin TX_RST_N to reset the transmitter, and listen to the interrupt pin

TX_INT_N to detect change of the transmitter status. When interrupt happens, the host needs to read the internal register to find out which event is triggered and perform proper actions for the interrupt.

Here are the steps 1-2-3 to control the transmitter:

1. Reset the transmitter from the TX_RST_N pin

2. Initialize the transmitter through the I2C interface

3. Polling the interrupt pin INT_N continuously.

If a HDMI sink device is detected (HDP flag is on): o Read and parse EDID to determine the capacity of the attached HDMI sink device. o Configure desired output video/audio, including color space and color depth. o Perform HDCP authentication o Output video/audio signals to the Video/Audio bus.

Stop video output if a video sink device is removed (HPD flag is off).

Perform proper actions according to various interrupt events.

9

2 .

.

4 B l l o c k D i i a g r a m o f f H D M I S i i g n a l l

R e c e i i v i i n g

This section describes the block diagram of HDMI signal receiving.

Figure 2-4

shows the block diagram of HDMI signal receiving. Please refer to the schematic

included in the CD for more details. The HDMI receiver is controlled through the I2C interface, where the host works as master and the transmitter works as a slave. Because the pin PCADR is pulled low, the transmitter I2C device address is set to 0x90. Through the I2C interface, the host board can access the internal registers of receiver to control its behavior. The receiver can support two receiving ports, but only one port can be activated at the same time.

Figure 2-4 The block diagram of HDMI signal receiving

The host can use the reset pin RX_RST_N to reset the receiver, and listen to the interrupt pin

RX_INT_N to detect change of the receiver status. When interrupt happens, the host needs to read the internal register to find out which event is triggered and perform proper actions for the interrupt.

10

Here are the steps to control the receiver:

1. Reset the receiver from the RX_RST_N pin

2. Read the EEPROM (EDID) to check whether the EEPROM contents need to be updated.

When writing data to EEPROM, remember to pull-low the EEPROM write protection pin

EDID_WP. Finally, make sure EDID_WP is pulled high and configure the both I2C pins as input pins, so the attached HSTC source device can read the EDID successfully.

3. Initialize the receiver through the I2C interface

4. Pull-Low the RX1_HPD_N and RX2_PHD_N pins to enable HPD pins of receiving ports.

5. Set receiver port 1 as active port.

6. Polling the interrupt pin RX_INT_N. Switch to another receiver port every three seconds and activate it if no HDMI source device found on the current active port.

If a HDMI source device is detected: o Perform HDCP authentication. o Read the input video format, including color space and color depth. o Configure input and output color space.

Perform proper actions according to various interrupt events.

2 .

.

5

G e n e r a t e

P i i n A s s i i g n m e n t s

This section describes how to automatically generate a top-level project, including HDMI pin assignments.

Users can easily create the HDMI board pin assignments by utilizing the DE3_System Builder V

1.3.1 or later. Here are the procedures to generate a top-level project for THDB-HDMI.

1. Launch DE3-System Builder

2. Add a DE3 board. Enable the HSTC-C connector and type desired pin pre-fix name in the dialog of DE3 Configuration.

11

3. Add HDMI Board.

4. Connect DE3 and HDMI Board by drag-and-drop the mouse.

12

5.

Click “Generate” to generate the desired top-level and pin assignments for a HDMI project.

2 .

.

6

P i i n D e f f i i n i i t i i o n o f f H S T C C o n n e c t o r

This section describes pin definition of the HSTC interface onboard.

All the control and data signals of HDMI transmitter and receiver are connected to the HSTC connector, so users can fully control the HDMI daughter board through the HSTC interface. Power is derived from 3.3V and 5V pins of the HSTC connector.

Figure 2-4

shows the physical pin

location and signal name on the HSTC connector.

13

14

15

Figure 2-5 HSTC Connector of HDMI board

16

The table below lists the HSMC signal direction and description.

Note. The power pins are not shown in the table.

Table 2-3 The HSTC pin definition of the THDB-HDMI board

Signal Name

RX_I2S[3]

RX_SCK

RX_WS

RX_MCLK

RX_RD[0]

RX_GD[10]

RX_GD[11]

RX_GD[9]

RX_RD[2]

RX_GD[8]

RX_RD[1]

RX_GD[7]

RX_RD[4]

RX_HPD[1]

RX_RD[3]

RX_CEC[1]

RX_I2S[1]

RX_RST_N

RX_I2S[2]

RX_SCDT

RX_SPDIF

RX_INT_N

RX_I2S[0]

RX_RD[11]

Pin

Number

3

4

5

16

17

18

21

22

6

9

10

11

12

15

23

24

27

28

29

30

33

34

35

36

Direction

(FPGA View)

input input input input input input input input input input input input input output input inout input input input input input input input input

Description

I2S serial data output, doubles as DSD

Serial Right CH2 data output

I2S serial clock output, doubles as DSD clock

I2S word select output, doubles as DSD

Serial Right CH0 data output

Audio master clock

Digital Video Output Pins.

Digital Video Output Pins.

Digital Video Output Pins.

Digital Video Output Pins.

Digital Video Output Pins.

Digital Video Output Pins.

Digital Video Output Pins.

Digital Video Output Pins.

Digital Video Output Pins.

Enable Hardware Plug Detection for

HDMP Port 1, Low Active

Digital Video Output Pins.

CEC (Consumer Electronics Control) for

HDMI Port 1

I2S serial data output, doubles as DSD

Serial Right CH1 data output

Hardware reset pin. Active LOW

I2S serial data output, doubles as DSD

Serial Left CH2 data output

Indication for active HDMI signal at input port

S/PDIF audio output, doubles as DSD

Serial Left CH2 data output

Interrupt output. Default active-low

I2S serial data output, doubles as DSD

Serial Left CH0 data output

Digital Video Output Pins.

17

RX_MUTE

RX_RD[10]

RX_DSD

RX_RD[9]

RX_RD[8]

RX_RD[7]

RX_RD[6]

RX_RD[5]

EDID_WP

RX_GD[3]

RX_GD[1]

RX_GD[5]

RX_GD[2]

RX_GD[6]

RX_GD[0]

RX_GD[4]

RX_BD[10]

RX_PCLK

RX_BD[8]

RX_BD[11]

RX_BD[9]

RX_BD[3]

RX_BD[2]

RX_BD[1]

RX_DE

RX_BD[0]

RX_PCSDA

RX_HS

RX_BD[4]

RX_PCSCL

RX_DDC_SDA[1] 87

RX_EVENODD 88

RX_DDC_SCL[1]

RX_VS

89

90

RX_DDC_SDA[0] 93

RX_BD[5]

RX_DDC_SCL[0]

94

95

RX_BD[6]

RX_HPD[0]

96

99

RX_BD[7]

TX_GD[8]

RX_CEC[0]

100

101

102

39

60

63

64

65

54

57

58

59

46

48

52

53

40

41

42

45

72

75

76

77

66

69

70

71

78

81

82

83

84 inout input inout output

Inout

Input

Inout input output

Input output inout input input input input input input input input input input input input input input input input output input input input input input input input input input inout output input inout

18

Mute output, doubles as DSD Serial

Right CH3 data output

Digital Video Output Pins.

DSD Serial Left CH3 data output

Digital Video Output Pins.

Digital Video Output Pins.

Digital Video Output Pins.

Digital Video Output Pins.

Digital Video Output Pins.

EEPROM Write Protection

Digital Video Output Pins.

Digital Video Output Pins.

Digital Video Output Pins.

Digital Video Output Pins.

Digital Video Output Pins.

Digital Video Output Pins.

Digital Video Output Pins.

Digital Video Output Pins.

Output data clock.

Digital Video Output Pins.

Digital Video Output Pins.

Digital Video Output Pins.

Digital Video Output Pins.

Digital Video Output Pins.

Digital Video Output Pins.

Data enable

Digital Video Output Pins.

Serial Programming Data for chip programming

Horizontal sync. signal

Digital Video Output Pins.

Serial Programming Clock for chip programming

DDC I2C Data for HDMI Port 1

Indicates whether the current field is

Even or Odd for interlaced format

DDC I2C Clock for HDMI Port 1

Vertical sync. signal

DDC I2C Data for HDMI Port 0

Digital Video Output Pins.

DDC I2C Clock for HDMI Port 0

Digital Video Output Pins.

Enable Hardware Plug Detection for

HDMP Port 0, Low Active

Digital Video Output Pins.

Digital video input pins.

CEC (Consumer Electronics Control) for

TX_GD[9]

TX_GD[10]

TX_RD[0]

TX_GD[11]

TX_RD[3]

TX_RD[1]

TX_RD[6]

TX_RD[2]

TX_RD[8]

TX_RD[4]

TX_RD[9]

TX_RD[5]

TX_RD[7]

SDA

SCL

TX_RD[11]

TX_GD[6]

TX_RD[10]

TX_GD[5]

TX_GD[7]

TX_GD[4]

TX_PCSCL

TX_PCSDA

TX_RST_N

TX_GD[3]

TX_INT_N

TX_GD[2]

TX_DSD_L[3]

TX_GD[1]

TX_DSD_R[3]

TX_GD[0]

TX_DSD_L[2]

TX_BD[11]

TX_DSD_R[2]

TX_BD[10]

TX_DSD_L[1]

TX_BD[9]

TX_DSD_R[1]

TX_PCLK

TX_DSD_L[0]

TX_BD[8]

TX_DSD_R[0]

TX_BD[7]

TX_DCLK

TX_BD[6]

TX_SCK

138

139

140

141

142

143

144

145

123

131

132

133

134

135

136

137

112

113

114

117

118

119

120

105

106

107

108

111

154

155

156

157

158

159

160

161

162

163

146

147

148

149

150

151

152

153 output inout output output output output output output output output inout output output input output output output output output output output output output output output output output output output output output output output output output output output output output output output output output output output output

19

HDMI Port 0

Digital video input pins.

Digital video input pins.

Digital video input pins.

Digital video input pins.

Digital video input pins.

Digital video input pins.

Digital video input pins.

Digital video input pins.

Digital video input pins.

Digital video input pins.

Digital video input pins.

Digital video input pins.

Digital video input pins.

I2S serial data for on-board EEPROM

I2S serial clock for on-board EEPROM

Digital video input pins.

Digital video input pins.

Digital video input pins.

Digital video input pins.

Digital video input pins.

Digital video input pins.

I

2

C Clock for DDC

I

2

C Data for DDC

Hardware reset pin. Active LOW

Digital video input pins.

Interrupt output. Default active-low

Digital video input pins.

DSD Serial Left CH3 data input

Digital video input pins.

DSD Serial Right CH3 data input

Digital video input pins.

DSD Serial Left CH2 data input

Digital video input pins.

DSD Serial Right CH2 data input

Digital video input pins.

DSD Serial Left CH1 data input

Digital video input pins.

DSD Serial Right CH1 data input

Input data clock

DSD Serial Left CH0 data input

Digital video input pins.

Digital video input pins.

Digital video input pins.

DSD Serial audio clock input

Digital video input pins.

I2S serial clock input

TX_BD[5]

TX_WS

TX_BD[4]

TX_MCLK

TX_BD[3]

TX_I2S[0]

TX_BD[2]

TX_I2S[1]

TX_BD[1]

TX_I2S[2]

TX_BD[0]

TX_I2S[3]

TX_DE

TX_VS

TX_HS

TX_SPDIF

TX_CEC

170

171

172

173

174

175

176

164

165

166

167

168

169

177

178

179

180 output output output output output output output output output output output output output output output output inout

Digital video input pins.

I2S word select input

Digital video input pins.

Audio master clock input

Digital video input pins.

I2S serial data input

Digital video input pins.

I2S serial data input

Digital video input pins.

I2S serial data input

Digital video input pins.

I2S serial data input

Data enable

Vertical sync. signal

Horizontal sync. signal

S/PDIF audio input

CEC (Consumer Electronics Control)

20

Chapter 3

Demonstration

This chapter illustrates the video/audio demonstration for the HDMI board.

3 .

.

1

I

I n t r o d u c t i i o n

This section describes the functionality of the demonstration briefly.

This demonstration shows how to use DE3 to control the HDMI board. The demonstration includes two parts:

Transmission-Only:

Generate HDMI Video/Audio signal for transmission, including various video formats and color space. There are 11 video formats available. The color space includes RGB444, YUV422, and

YUV444.

Loopback:

Loopback (Internal bypass) the HDMI Video/Audio Signals. The audio and video output pins of the receiver are directly connected to the input audio and video pins of the transmitter.

3 .

.

2

S y s t e m R e q u i i r e m e n t s

The following items are required for transmission-only and loopback demonstrations.

Transmission-Only

THDB-HDMI x 1

DE3 Board x 1

LCD monitor with at least one HDMI input x 1

21

HDMI Cable x 1

Loopback

THDB-HDMI x 1

DE3 Board x 1

LCD monitor with at least one HDMI input x 1

HDMI Source Device x 1

HDMI Cable x 2

3 .

.

3 S e t u p t h e D e m o n s t r a t i i o n

Figure 3-1

and

Figure 3-2

show how to setup hardware for transmission and loop-back

demonstrations, respectively.

Transmission Only

HDMI Cable

Loopback

Figure 3-1 HDMI Transmission-Only Demonstration Setup

22

Video in

HDMI Cable

Figure 3-2 HDMI Loopback Demonstration Setup

3 .

.

4 O p e r a t i i o n

This section describes the procedures of running the demonstration.

FPGA Configuration

Please follow the steps below to configure the FPGA.

Make sure hardware setup is completed.

Connect PC and DE3 with a USB cable.

Power on DE3.

Make sure Quartus II is installed on your PC.

Execute the batch file hdmi_demo.bat under the folder “examples\DE3_xxx_TX_RX\demo batch”.

HDMI Transmission-Only

After FPGA is configured, please follow the steps below to run the HDMI transmission-only demonstration.

Connect the HDMI LCD monitor and the HDMI transmitting port with a HDMI cable.

Power on the LCD monitor and make sure the LCD monitor is set to the mode where HDMI input is the source. Please refer to the user manual of your HDMI Display for more details.

23

When LCD monitor is detected, the LED2 of DE3 will be turned on.

After approximately 10 seconds, a test pattern will be displayed on the LCD monitor. The first displayed pattern is 480p (720x480p60) pattern.

Press “BUTTON0” to change test patterns. Please refer to

Table 4-2

for built-in test patterns.

There are eleven built-in test patterns available in this demonstration. You will not be able to see all the test patterns if your LCD monitor doesn’t support such resolution.

Press “BUTTON1” to change the color space of pattern source. The color space includes

RGB444, YUV422, and YUV444.

Figure 3-3

and

Figure 3-4

show the test pattern of FULL HD (1920x1080p60) in RGB and YUV

color space, respectively.

It will take approximately 10 seconds to display a new pattern on the LCD when users change test pattern or color space.

Figure 3-3 FULL HD in RGB444 Color Space

Figure 3-4 FULL HD in YUV Color Space

Figure 3-5

shows the NIOS program trace log when a HDMI LCD monitor is detected. It indicates

the LCD monitor in use supports color space YUV444 and YUV422, but not RGB444. Various video formats supported are listed according to Video Identify Code (VIC). The format of input and

24

output color of the transmitter is RGB444 and RGB444, respectively. It implies there is no change of color format in between.

Figure 3-5 NIOS program trace log of transmitting-only demonstration

HDMI Internal Loopback

After FPGA is configured, please follow the steps below to run the HDMI loopback demonstration.

Connect the HDMI LCD and the HDMI TX port with a HDMI Cable.

Power on the LCD monitor and make sure the LCD monitor is set to the mode where HDMI input is the source.

Connect the HDMI source device and HDMI RX port with a HDMI Cable.

Power on the HDMI source device and make sure its HDMI port is selected as the output.

Users will be able to see the video displayed on the LCD monitor and hear the sound, if there is a speaker built-in.

Users can change the RX port connected to the HDMI source device. The demonstration can automatically detect the RX port and activate it.

25

Figure 3-6

shows the NIOS program trace log when a HDMI LCD source device is detected. It

indicates the input video resolution is 1280 x 720 (VIC=4) with color space RGB444 and 36-bits color depth.

Both input color and output color of the receiver and transmitter are configured as RGB444. In another words, the color format doesn’t change from the source to the LCD monitor during the loopback process. The output color depth of the transmitter is configured as 24-bits.

Figure 3-6 NIOS program trace log of loopback demonstration

26

Chapter 4

Case Study

This chapter describes the design concepts for the HDMI demonstration in the previous chapter.

4 .

.

1 O v e r v i i e w

This section describes the overview of the reference design.

This reference design shows how to use DE3 to control HDMI board. Please refer to the pervious chapter for the demonstration of this reference design.

The source code of the reference design can be found in the THDB-HDMI CD under the directory of Examples folder. The demonstration includes the following two major functions:

Transmission only:

Generate HDMI Video/Audio signals for transmission, including various video formats and color space. There are 11 video formats available. The color space includes RGB444, YUV422, and

YUV444.

Loopback:

Loopback (internal bypass) the HDMI Video/Audio Signals. The audio and video output pins of the receiver are directly connected to the input audio and video pins of the transmitter.

4 .

.

2 S y s t e m F u n c t i i o n

B l l o c k

This section will describe the system behavior in function blocks.

Figure 4-1

shows the system function block diagram of this demonstration. In the design, SOPC is

included because NIOS II processor is used to control both transmitter and receiver through I2C interface.

27

The NIOS program is designed to run on the on-chip memory. A customized I2S controller is designed to generate I2S 48K stereo audio for the HDMI transmitting-only mode. The audio data is stored in the on-chip memory and sent to the HDMI transmitter by NIOS II processor.

The video pattern generator is designed to generate test patterns for HDMI transmitter-only mode. It provides eleven video formats in three color spaces. The source selector circuit is designed to select the desired video source between the video pattern generator and the video from the receiver. Four

LEDs and two BUTTONs on DE3 are used for human interface. BUTTONs are designed to change the test pattern and associated color space for transmission. LEDs are designed to indicate the

HDMI status, which is illustrated in

Table 4-1

. BUTTONs are designed to change the video format and color space of the build-in video pattern generator, which is illustrated in

Table 4-2

.

Figure 4-1 System Function Block Diagram

28

LED

Table 4-1 LED Indications

Description

System is running.

HDMI sink device is detected and synchronized.

BUTTON

HDMI source device is detected and synchronized.

Table 4-2 Button Operation Definition

Description

Press to change active video format of the built-in video pattern generator.

Press to change active video color space of the built-in video pattern generator.

Transmitter Controlled by NIOS II Processor

The transmitter is controlled by NIOS program through I2C interface. Based on I2C protocol, the

NIOS program can read/write the internal registers of the transmitter, and control the behavior of the transmitter. The NIOS program controls the transmitter to perform the following procedures step by step: o Initialize the HDMI chip. o Detect if a HDMI sink device is attached or detached, e.g. LCD Display. o Read and parse the EDID content to find the capability of the HDMI sink device.

The capability includes supported color space, video format (VIC code), and color depth etc. o Perform HDCP authentication. o Configure the color space of input and output. The transmitter offers color space transformation and outputs RGB444, YUV422, or YUV444 o Configure the color depth of output video. o Send VIC to the video sink device. o Configure the audio interface and format of output video.

29

Receiver Controlled by NIOS II Processor

The receiver is controlled by NIOS program through I2C interface. Based on I2C protocol, the

NIOS program can read/ write the internal registers of the receiver, and control the behavior of the receiver. The revision number of receiver is either A1 or A2, which can be determined by querying the register 4 of receiver.

The major differences between both revisions are:

1. Receiver initialization process

2. Video synchronization process.

Please search the global variable “Is_A2” in it6605.c for detail information.

The NIOS program controls the receiver to perform the following procedures step by step: o Initialize the HDMI receiver chip. o Detect if a HDMI source device is attached or detached. o Select one of the receiving ports and activate it. o Read and parse the EDID content to find the capability of the HDMI source device.

The capability includes supported color space, video format (VIC code), and color depth etc. o Perform HDCP authentication. o Report the input video (VIC) and audio format of the attached HDMI source device. o Configure the color space of input and output. The receiver can provide color space transformation.

Video Pattern Generator

The video pattern generator is designed to generate test pattern for HDMI transmitting-only mode.

The supported video formats are listed in

Table 4-2

.

Video Format

720x480p60

1024x76pP60

1280x720p50

1280x720p60

1280x1024

1920x1080i60

1920x1080i50

1920x1080p60

1920x1080p50

5

20

16

31

VIC

3

-

19

4

-

PCLK (MHZ)

27

65

74.25

74.25

108

74.25

74.25

148.5

148.5

30

1600x1200p5

1920x1080i120

-

46

162

148.5

It also supports three color spaces, which are RGB444, YUV422, and YUV444.

The required PCLK is generated from Megafunction ALTPLL and ALTPLL_RECONFIG IP. The required PLL-reconfigure data is stored in on-chip ROMs.

Video Source Selector

The source selector is implemented using Megafunction LPM_MUX.

4 .

.

3

N

I

I O S P r o g r a m

This section describes the design flow and how Nios II processor controls transmitter and receiver.

Figure 4-2

shows the software stack of the NIOS program. The I2C block implements the I2C

read/write functions based on GPIO system call. The HDMI transmitter block and receiver block are referred as the HDMI driver. The HDMI transmitter chip and receiver chip are managed and controlled through the I2C protocol. The I2S driver block is in charge of sending audio data to the transmitter.

Figure 4-2 Software Stack

Figure 4-3

shows the file list of the NIOS program. The control center is located in main.c. The

31

beep.c includes audio raw data for generating a tone sound. The folder named terasic_lib includes the I2C driver. The folder named HDMI_Lib includes transmitter and receiver drivers. The platform-dependent functions are located in mcu.c under HDMI_Lib.

Figure 4-3 NIOS Program File List

32

System Configuration

To use the HDMI library in NIOS II, the const _MCU_ should be defined in the configuration

settings, as shown in

Figure 4-4

. Two on-chip memories are created to store the NIOS program and

data separately. The size of each on-chip memory is 128 K bytes. One on-chip memory is used to store program and the other one is used to store data. The option “Small C Library” must be enabled

to reduce the size of the program. The associated configuration is shown in

Figure 4-5

Figure 4-4 Define _MCU_ constant

33

Figure 4-5 Configuration of System Library

Audio Test

If users would like to test audio during HDMI transmitting-only mode, please remove the constant definition TX_VPG_COLOR_CTRL_DISABLED from main.c. Users will hear a tone sound from the built-in speaker of HDMI LCD monitor when pressing BUTTON1 of DE3 board.

34

Chapter 5

Appendix

5 .

.

1

R e v i i s i i o n H i i s t o r y

Revision Date

1.0 DEC 02 2008

1.1

1.2

1.3

APR 06 2009

JAN 04 2010

MAR 09 2011

Change Log

Initial Version

Support Receiver Revision A2

Figure 2-1 Corrected

Support HDMI 1.4

5 .

.

2 A l l w a y s V i i s i i t T H D B -

-

H

D

M

I

I W e b p a g e f f o r U p d a t e

We will be continuing providing interesting examples and labs on our THDB-HDMI web page.

Please visit www.altera.com or hdmi.terasic.com for more information.

35

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