Micron 4GB DDR3
1GB, 2GB, 4GB (x64, SR) 240-Pin DDR3 UDIMM
Features
DDR3 SDRAM UDIMM
MT8JTF12864AZ – 1GB
MT8JTF25664AZ – 2GB
MT8JTF51264AZ – 4GB
Features
Figure 1: 240-Pin UDIMM (MO-269 R/C A)
• DDR3 functionality and operations supported as
defined in the component data sheet
• 240-pin, unbuffered dual in-line memory module
(UDIMM)
• Fast data transfer rates: PC3-14900, PC3-12800,
PC3-10600, PC3-8500, or PC3-6400
• 1GB (128 Meg x 64), 2GB (256 Meg x 64), or 4GB (512
Meg x 64)
• VDD = V DDQ = 1.5V ±0.075V
• VDDSPD = 3.0V to 3.6V
• Reset pin for improved system stability
• Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
• Single-rank
• Fixed burst chop (BC) of 4 and burst length (BL) of 8
via the mode register set (MRS)
• Adjustable data-output drive strength
• Serial presence-detect (SPD) EEPROM
• Gold edge contacts
• Halogen-free
• Fly-by topology
• Terminated control, command, and address bus
Module height: 30mm (1.181in)
Options
Marking
• Operating temperature 1
– Commercial (0°C ≤ T A ≤ +70°C)
– Industrial (–40°C ≤ T A ≤ +85°C)
• Package
– 240-pin DIMM (halogen-free)
• Frequency/CAS latency
– 1.07ns @ CL = 13 (DDR3-1866)
– 1.25ns @ CL = 11 (DDR3-1600)
– 1.5ns @ CL = 9 (DDR3-1333)
– 1.87ns @ CL = 7 (DDR3-1066)
None
I
Z
-1G9
-1G6
-1G4
-1G1
1. Contact Micron for industrial temperature
module offerings.
Note:
Table 1: Key Timing Parameters
Data Rate (MT/s)
Speed
Industry
Grade Nomenclature
CL =
13
CL =
11
CL =
10
CL = 9
CL = 8
CL = 7
CL = 6
tRCD
tRP
tRC
CL = 5
(ns)
(ns)
(ns)
-1G9
PC3-14900
1866
1600
1333
1333
1066
1066
800
667
13.125
13.125
47.125
-1G6
PC3-12800
–
1600
1333
1333
1066
1066
800
667
13.125
13.125
48.125
-1G4
PC3-10600
–
–
1333
1333
1066
1066
800
667
13.125
13.125
49.125
-1G1
PC3-8500
–
–
–
–
1066
1066
800
667
13.125
13.125
50.625
-1G0
PC3-8500
–
–
–
–
1066
–
800
667
15
15
52.5
-80B
PC3-6400
–
–
–
–
–
–
800
667
15
15
52.5
PDF: 09005aef837d3ecf
jtf8c128_256_512x64az.pdf - Rev. H 04/13 EN
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
1GB, 2GB, 4GB (x64, SR) 240-Pin DDR3 UDIMM
Features
Table 2: Addressing
Parameter
Refresh count
Row address
1GB
2GB
4GB
8K
8K
8K
16K A[13:0]
32K A[14:0]
64K A[15:0]
Device bank address
8 BA[2:0]
8 BA[2:0]
8 BA[2:0]
Device configuration
1Gb (128 Meg x 8)
2Gb (256 Meg x 8)
4Gb (512 Meg x 8)
1K A[9:0]
1K A[9:0]
1K A[9:0]
1 (S0#)
1 (S0#)
1 (S0#)
Column address
Module rank address
Table 3: Part Numbers and Timing Parameters – 1GB Modules
Base device: MT41J128M8,1 1Gb DDR3 SDRAM
Module
Part Number2
Density
Configuration
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL - tRCD - tRP)
MT8JTF12864A(I)Z-1G9__
1GB
128 Meg x 64
14.9 GB/s
1.07ns/1866 MT/s
13-13-13
MT8JTF12864A(I)Z-1G6__
1GB
128 Meg x 64
12.8 GB/s
1.25ns/1600 MT/s
11-11-11
MT8JTF12864A(I)Z-1G4__
1GB
128 Meg x 64
10.6 GB/s
1.5ns/1333 MT/s
9-9-9
MT8JTF12864A(I)Z-1G1__
1GB
128 Meg x 64
8.5 GB/s
1.87ns/1066 MT/s
7-7-7
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL - tRCD - tRP)
Table 4: Part Numbers and Timing Parameters – 2GB Modules
Base device: MT41J256M8,1 2Gb DDR3 SDRAM
Module
Part Number2
Density
Configuration
MT8JTF25664A(I)Z-1G9__
2GB
256 Meg x 64
14.9 GB/s
1.07ns/1866 MT/s
13-13-13
MT8JTF25664A(I)Z-1G6__
2GB
256 Meg x 64
12.8 GB/s
1.25ns/1600 MT/s
11-11-11
MT8JTF25664A(I)Z-1G4__
2GB
256 Meg x 64
10.6 GB/s
1.5ns/1333 MT/s
9-9-9
MT8JTF25664A(I)Z-1G1__
2GB
256 Meg x 64
8.5 GB/s
1.87ns/1066 MT/s
7-7-7
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL - tRCD - tRP)
Table 5: Part Numbers and Timing Parameters – 4GB Modules
Base device: MT41J512M8,14Gb DDR3 SDRAM
Module
Part Number2
Density
Configuration
MT8JTF51264A(I)Z-1G9__
4GB
512 Meg x 64
14.9 GB/s
1.07ns/1866 MT/s
13-13-13
MT8JTF51264A(I)Z-1G6__
4GB
512 Meg x 64
12.8 GB/s
1.25ns/1600 MT/s
11-11-11
MT8JTF51264A(I)Z-1G4__
4GB
512 Meg x 64
10.6 GB/s
1.5ns/1333 MT/s
9-9-9
MT8JTF51264A(I)Z-1G1__
4GB
512 Meg x 64
8.5 GB/s
1.87ns/1066 MT/s
7-7-7
Notes:
1. Data sheets for the base device parts can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT8JTF51264AZ-1G4E1.
PDF: 09005aef837d3ecf
jtf8c128_256_512x64az.pdf - Rev. H 04/13 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB (x64, SR) 240-Pin DDR3 UDIMM
Pin Assignments
Pin Assignments
Table 6: Pin Assignments
240-Pin DDR3 UDIMM Front
240-Pin DDR3 UDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
VREFDQ
31
DQ25
61
A2
91
DQ41
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
121
VSS
151
VSS
181
A1
211
VSS
2
VSS
32
VSS
62
VDD
92
VSS
122
DQ4
152
DM3
182
VDD
212
DM5
3
DQ0
33
DQS3#
63
CK1
93
DQS5#
123
DQ5
153
NC
183
VDD
213
NC
4
DQ1
34
DQS3
64
CK1#
94
DQS5
124
VSS
154
VSS
184
CK0
214
VSS
5
VSS
35
VSS
65
VDD
95
VSS
125
DM0
155
DQ30
185
CK0#
215
DQ46
6
DQS0#
36
DQ26
66
VDD
96
DQ42
126
NC
156
DQ31
186
VDD
216
DQ47
7
DQS0
37
DQ27
67
VREFCA
97
DQ43
127
VSS
157
VSS
187
NC
217
VSS
8
VSS
38
VSS
68
NC
98
VSS
128
DQ6
158
NC
188
A0
218
DQ52
9
DQ2
39
NC
69
VDD
99
DQ48
129
DQ7
159
NC
189
VDD
219
DQ53
10
DQ3
40
NC
70
A10
100
DQ49
130
VSS
160
VSS
190
BA1
220
VSS
11
VSS
41
VSS
71
BA0
101
VSS
131
DQ12
161
NC
191
VDD
221
DM6
12
DQ8
42
NC
72
VDD
102
DQS6#
132
DQ13
162
NC
192
RAS#
222
NC
13
DQ9
43
NC
73
WE#
103
DQS6
133
VSS
163
VSS
193
S0#
223
VSS
14
VSS
44
VSS
74
CAS#
104
VSS
134
DM1
164
NC
194
VDD
224
DQ54
15
DQS1#
45
NC
75
VDD
105
DQ50
135
NC
165
NC
195
ODT0
225
DQ55
16
DQS1
46
NC
76
NC
106
DQ51
136
VSS
166
VSS
196
A13
226
VSS
17
VSS
47
VSS
77
NC
107
VSS
137
DQ14
167
NC
197
VDD
227
DQ60
18
DQ10
48
NC
78
VDD
108
DQ56
138
DQ15
168
RESET#
198
NC
228
DQ61
19
DQ11
49
NC
79
NC
109
DQ57
139
VSS
169
NC
199
VSS
229
VSS
20
VSS
50
CKE0
80
VSS
110
VSS
140
DQ20
170
VDD
200
DQ36
230
DM7
21
DQ16
51
VDD
81
DQ32
111
DQS7#
141
DQ21
171 NC/A151 201
DQ37
231
NC
22
DQ17
52
BA2
82
DQ33
112
DQS7
142
VSS
172 NC/A142 202
VSS
232
VSS
23
VSS
53
NC
83
VSS
113
VSS
143
DM2
173
VDD
203
DM4
233
DQ62
24
DQS2#
54
VDD
84
DQS4#
114
DQ58
144
NC
174
A12
204
NC
234
DQ63
25
DQS2
55
A11
85
DQS4
115
DQ59
145
VSS
175
A9
205
VSS
235
VSS
26
VSS
56
A7
86
VSS
116
VSS
146
DQ22
176
VDD
206
DQ38
236
VDDSPD
27
DQ18
57
VDD
87
DQ34
117
SA0
147
DQ23
177
A8
207
DQ39
237
SA1
28
DQ19
58
A5
88
DQ35
118
SCL
148
VSS
178
A6
208
VSS
238
SDA
29
VSS
59
A4
89
VSS
119
SA2
149
DQ28
179
VDD
209
DQ44
239
VSS
30
DQ24
60
VDD
90
DQ40
120
VTT
150
DQ29
180
A3
210
DQ45
240
VTT
Notes:
PDF: 09005aef837d3ecf
jtf8c128_256_512x64az.pdf - Rev. H 04/13 EN
1. Pin 171 is NC for 1GB and 2GB; A15 for 4GB.
2. Pin 172 is NC for 1GB; A14 for 2GB and 4GB.
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB (x64, SR) 240-Pin DDR3 UDIMM
Pin Descriptions
Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for all DDR3
modules. All pins listed may not be supported on this module. See Pin Assignments for
information specific to this module.
Table 7: Pin Descriptions
Symbol
Type
Description
Ax
Input
Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command. See the Pin Assignments Table for density-specific
addressing information.
BAx
Input
Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA define which mode register (MR0, MR1,
MR2, or MR3) is loaded during the LOAD MODE command.
CKx,
CKx#
Input
Clock: Differential clock inputs. All control, command, and address input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#.
CKEx
Input
Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM.
DMx
Input
Data mask (x8 devices only): DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH, along with that input data, during a write access. Although DM pins are input-only, DM loading is designed to match that of the
DQ and DQS pins.
ODTx
Input
On-die termination: Enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
will be ignored if disabled via the LOAD MODE command.
Par_In
Input
Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.
RAS#, CAS#, WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
RESET#
Input
(LVCMOS)
Reset: RESET# is an active LOW asychronous input that is connected to each DRAM
and the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitialized as though a normal power-up was executed.
Sx#
Input
Chip select: Enables (registered LOW) and disables (registered HIGH) the command
decoder.
SAx
Input
Serial address inputs: Used to configure the temperature sensor/SPD EEPROM address range on the I2C bus.
SCL
Input
Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communication to and from the temperature sensor/SPD EEPROM on the I2C bus.
CBx
I/O
Check bits: Used for system error detection and correction.
DQx
I/O
Data input/output: Bidirectional data bus.
DQSx,
DQSx#
I/O
Data strobe: Differential data strobes. Output with read data; edge-aligned with
read data; input with write data; center-aligned with write data.
PDF: 09005aef837d3ecf
jtf8c128_256_512x64az.pdf - Rev. H 04/13 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB (x64, SR) 240-Pin DDR3 UDIMM
Pin Descriptions
Table 7: Pin Descriptions (Continued)
Symbol
Type
SDA
I/O
Description
Serial data: Used to transfer addresses and data into and out of the temperature sensor/SPD EEPROM on the I2C bus.
TDQSx,
TDQSx#
Output
Redundant data strobe (x8 devices only): TDQS is enabled/disabled via the LOAD
MODE command to the extended mode register (EMR). When TDQS is enabled, DM is
disabled and TDQS and TDQS# provide termination resistance; otherwise, TDQS# are
no function.
Err_Out#
Output
Parity error output: Parity error found on the command and address bus.
(open drain)
EVENT#
Output
Temperature event:The EVENT# pin is asserted by the temperature sensor when criti(open drain) cal temperature thresholds have been exceeded.
VDD
Supply
Power supply: 1.5V ±0.075V. The component VDD and VDDQ are connected to the
module VDD.
VDDSPD
Supply
Temperature sensor/SPD EEPROM power supply: 3.0–3.6V.
VREFCA
Supply
Reference voltage: Control, command, and address VDD/2.
VREFDQ
Supply
Reference voltage: DQ, DM VDD/2.
VSS
Supply
Ground.
VTT
Supply
Termination voltage: Used for control, command, and address VDD/2.
NC
–
No connect: These pins are not connected on the module.
NF
–
No function: These pins are connected within the module, but provide no functionality.
PDF: 09005aef837d3ecf
jtf8c128_256_512x64az.pdf - Rev. H 04/13 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB (x64, SR) 240-Pin DDR3 UDIMM
DQ Map
DQ Map
Table 8: Component-to-Module DQ Map
Component
Reference
Number
Component
DQ
U1
U3
U5
U7
Module DQ
Module Pin
Number
Component
Reference
Number
Component
DQ
Module DQ
Module Pin
Number
0
7
129
U2
0
15
138
1
5
123
1
13
132
2
6
128
2
14
137
3
0
3
3
8
12
4
3
10
4
11
19
5
4
122
5
12
131
6
2
9
6
10
18
7
1
4
7
9
13
0
23
147
0
31
156
1
21
141
1
29
150
2
22
146
2
30
155
3
16
21
3
24
30
4
19
28
4
27
37
5
20
140
5
28
149
6
18
27
6
26
36
7
17
22
7
25
31
0
39
207
0
47
216
1
37
201
1
45
210
2
38
206
2
46
215
3
32
81
3
40
90
4
35
88
4
43
97
5
36
200
5
44
209
6
34
87
6
42
96
7
33
82
7
41
91
0
55
225
0
63
234
1
53
219
1
61
228
2
54
224
2
62
233
3
48
99
3
56
108
4
51
106
4
59
115
5
52
218
5
60
227
6
50
105
6
58
114
7
49
100
7
57
109
PDF: 09005aef837d3ecf
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U4
U6
U8
6
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB (x64, SR) 240-Pin DDR3 UDIMM
Functional Block Diagram
Functional Block Diagram
Figure 2: Functional Block Diagram
S0#
DQS0#
DQS0
DM0
DQS4#
DQS4
DM4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1#
DQS1
DM1
VSS
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2#
DQS2
DM2
VSS
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3#
DQS3
DM3
VSS
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VSS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
U1
DQS5#
DQS5
DM5
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
U2
DM CS# DQS DQS#
DQS7#
DQS7
DM7
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
U4
VSS
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DM
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
CS# DQS DQS#
U5
BA[2:0]: DDR3 SDRAM
A[15/14/13:0]: DDR3 SDRAM
RAS#: DDR3 SDRAM
CAS#: DDR3 SDRAM
WE#: DDR3 SDRAM
CKE0: DDR3 SDRAM
ODT0: DDR3 SDRAM
RESET#: DDR3 SDRAM
Address, command, control, and clock line terminations:
CS# DQS DQS#
CKE0, A[15/14/13:0],
RAS#, CAS#, WE#,
S0#, ODT0, BA[2:0]
VSS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
VSS
DDR3
SDRAM
VTT
DDR3
SDRAM
U6
CK0
CK0#
VDD
SCL
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
U3
DM CS# DQS DQS#
VSS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS6#
DQS6
DM6
Note:
PDF: 09005aef837d3ecf
jtf8c128_256_512x64az.pdf - Rev. H 04/13 EN
DM CS# DQS DQS#
BA[2:0]
A[15/14/13:0]
RAS#
CAS#
WE#
CKE0
ODT0
RESET#
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
U7
DQ
DQ
DQ
DQ
ZQ
WP A0
A1
SDA
A2
VSS SA0 SA1 SA2
CK0
CK0#
CK1
CK1#
VDDSPD
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
U8
DQ
DQ
DQ
DQ
ZQ
U9
SPD EEPROM
VDD
VTT
VREFCA
DDR3 SDRAM x8
Unused clock termination
SPD EEPROM
DDR3 SDRAM
Address, command,
and control termination
DDR3 SDRAM
VREFDQ
DDR3 SDRAM
VSS
DDR3 SDRAM
1. The ZQ ball on each DDR3 component is connected to an external 240Ω ±1% resistor
that is tied to ground. It is used for the calibration of the component’s ODT and output
driver.
7
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© 2009 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB (x64, SR) 240-Pin DDR3 UDIMM
General Description
General Description
DDR3 SDRAM modules are high-speed, CMOS dynamic random access memory modules that use internally configured 8-bank DDR3 SDRAM devices. DDR3 SDRAM modules use DDR architecture to achieve high-speed operation. DDR3 architecture is essentially an 8n-prefetch architecture with an interface designed to transfer two data words
per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM module effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers
at the I/O pins.
DDR3 modules use two sets of differential signals: DQS, DQS# to capture data and CK
and CK# to capture commands, addresses, and control signals. Differential clocks and
data strobes ensure exceptional noise immunity for these signals and provide precise
crossing points to capture input signals.
Fly-By Topology
DDR3 modules use faster clock speeds than earlier DDR technologies, making signal
quality more important than ever. For improved signal quality, the clock, control, command, and address buses have been routed in a fly-by topology, where each clock, control, command, and address pin on each DRAM is connected to a single trace and terminated (rather than a tree structure, where the termination is off the module near the
connector). Inherent to fly-by topology, the timing skew between the clock and DQS signals can be easily accounted for by using the write-leveling feature of DDR3.
Serial Presence-Detect EEPROM Operation
DDR3 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to comply with
JEDEC standard JC-45, "Appendix X: Serial Presence Detect (SPD) for DDR3 SDRAM
Modules." These bytes identify module-specific timing parameters, configuration information, and physical attributes. The remaining 128 bytes of storage are available for use
by the customer. System READ/WRITE operations between the master (system logic)
and the slave EEPROM device occur via a standard I2C bus using the DIMM’s SCL
(clock) SDA (data), and SA (address) pins. Write protect (WP) is connected to V SS, permanently disabling hardware write protection. For further information refer to Micron
technical note TN-04-42, "Memory Module Serial Presence-Detect."
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1GB, 2GB, 4GB (x64, SR) 240-Pin DDR3 UDIMM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the module. This is a
stress rating only, and functional operation of the module at these or any other conditions outside those indicated in each device's data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability.
Table 9: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
VDD
VDD supply voltage relative to VSS
–0.4
1.975
V
VIN, VOUT
Voltage on any pin relative to VSS
–0.4
1.975
V
Table 10: Operating Conditions
Symbol Parameter
Min
Nom
Max
Units Notes
VDD
VDD supply voltage
1.425
1.5
1.575
V
IVTT
Termination reference current from VTT
–600
–
600
mA
VTT
Termination reference voltage (DC) – command/address bus
II
IOZ
IVREF
TA
TC
Input leakage current;
Any input 0V ≤ VIN ≤ VDD; VREF
input 0V ≤ VIN ≤ 0.95V (All
other pins not under test =
0V)
0.49 × VDD - 20mV 0.5 × VDD 0.51 × VDD + 20mV
V
Address
inputs, RAS#,
CAS#, WE#,
BA, S#, CKE,
ODT, CK,
CK#
–16
0
16
DM
–2
0
2
Output leakage current; 0V ≤ DQ, DQS,
VOUT ≤ VDDQ; DQ and ODT are DQS#
disabled; ODT is HIGH
–5
0
5
µA
VREF supply leakage current; VREFDQ = VDD/2
or VREFCA = VDD/2 (All other pins not under
test = 0V)
–8
0
8
µA
Module ambient operating
temperature
0
–
70
°C
–40
–
85
°C
0
–
85
°C
–40
–
95
°C
Commercial
Industrial
DDR3 SDRAM component case Commercial
operating temperature
Industrial
Notes:
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1
µA
2, 3
2, 3, 4
1. VTT termination voltage in excess of the stated limit will adversely affect the command
and address signals’ voltage margin and will reduce timing margins.
2. TA and TC are simultaneous requirements.
3. For further information, refer to technical note TN-00-08: ”Thermal Applications,” available on Micron’s Web site.
4. The refresh rate is required to double when 85°C < TC ≤ 95°C.
9
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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1GB, 2GB, 4GB (x64, SR) 240-Pin DDR3 UDIMM
DRAM Operating Conditions
DRAM Operating Conditions
Recommended AC operating conditions are given in the DDR3 component data sheets.
Component specifications are available on Micron’s web site. Module speed grades correlate with component speed grades, as shown below.
Table 11: Module and Component Speed Grades
DDR3 components may exceed the listed module speed grades; module may not be available in all listed speed grades
Module Speed Grade
Component Speed Grade
-2G1
-093
-1G9
-107
-1G6
-125
-1G4
-15E
-1G1
-187E
-1G0
-187
-80C
-25E
-80B
-25
Design Considerations
Simulations
Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length
matching, and decoupling. However, good signal integrity starts at the system level.
Micron encourages designers to simulate the signal characteristics of the system's
memory bus to ensure adequate signal integrity of the entire memory system.
Power
Operating voltages are specified at the DRAM, not at the edge connector of the module.
Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained.
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
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1GB, 2GB, 4GB (x64, SR) 240-Pin DDR3 UDIMM
IDD Specifications
IDD Specifications
Table 12: DDR3 IDD Specifications and Conditions – 1GB (Die Revision G)
Values are for the MT41J128M8 DDR3 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) component data sheet
Parameter
Symbol 1866 1600 1333 1066 Units
Operating current 0: One bank ACTIVATE-to-PRECHARGE
IDD0
560
560
520
480
mA
Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE
IDD1
720
720
680
640
mA
Precharge power-down current: Slow exit
IDD2P0
96
96
96
96
mA
Precharge power-down current: Fast exit
IDD2P1
280
240
240
200
mA
Precharge quiet standby current
IDD2Q
360
320
280
280
mA
Precharge standby current
IDD2N
400
360
320
280
mA
Precharge standby ODT current
IDD2NT
480
440
400
360
mA
Active power-down current
IDD3P
280
280
240
240
mA
Active standby current
IDD3N
400
360
320
320
mA
Burst read operating current
IDD4R
1240
1120
1000
840
mA
Burst write operating current
IDD4W
1280
1160
1000
880
mA
Refresh current
IDD5B
1400
1360
1320
1280
mA
Self refresh temperature current: MAX TC = 85°C
IDD6
64
64
64
64
mA
IDD6ET
80
80
80
80
mA
All banks interleaved read current
IDD7
2080
1960
1880
1560
mA
Reset current
IDD8
112
112
112
112
mA
Self refresh temperature current (SRT-enabled): MAX TC = 95°C
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
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1GB, 2GB, 4GB (x64, SR) 240-Pin DDR3 UDIMM
IDD Specifications
Table 13: DDR3 IDD Specifications and Conditions – 2GB (Die Revision D)
Values are for the MT41J256M8 DDR3 SDRAM only and are computed from values specified in the 2Gb (256 Meg x 8) component data sheet.
Parameter
Symbol 1866 1600 1333 1066 Units
Operating current 0: One bank ACTIVATE-to-PRECHARGE
IDD0
840
760
680
600
mA
Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE
IDD1
880
840
800
760
mA
Precharge power-down current: Slow exit
IDD2P0
96
96
96
96
mA
Precharge power-down current: Fast exit
IDD2P1
320
280
240
200
mA
Precharge quiet standby current
IDD2Q
360
320
280
240
mA
Precharge standby current
IDD2N
376
336
296
256
mA
Precharge standby ODT current
IDD2NT
440
400
360
320
mA
Active power-down current
IDD3P
360
320
280
240
mA
Active standby current
IDD3N
400
360
320
280
mA
Burst read operating current
IDD4R
1600
1440
1280
1120
mA
Burst write operating current
IDD4W
1640
1480
1320
1160
mA
Refresh current
IDD5B
1760
1720
1600
1520
mA
Self refresh temperature current: MAX TC = 85°C
IDD6
96
96
96
96
mA
IDD6ET
120
120
120
120
mA
All banks interleaved read current
IDD7
3880
3480
3080
2680
mA
Reset current
IDD8
112
112
112
112
mA
Self refresh temperature current (SRT-enabled): MAX TC = 95°C
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
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1GB, 2GB, 4GB (x64, SR) 240-Pin DDR3 UDIMM
IDD Specifications
Table 14: DDR3 IDD Specifications and Conditions – 2GB (Die Revision M)
Values are for the MT41J256M8 DDR3 SDRAM only and are computed from values specified in the 2Gb (256 Meg x 8) component data sheet.
Parameter
Symbol 1866 1600 1333 1066 Units
Operating current 0: One bank ACTIVATE-to-PRECHARGE
IDD0
600
560
520
480
mA
Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE
IDD1
680
640
600
560
mA
Precharge power-down current: Slow exit
IDD2P0
96
96
96
96
mA
Precharge power-down current: Fast exit
IDD2P1
336
296
256
216
mA
Precharge quiet standby current
IDD2Q
360
320
280
240
mA
Precharge standby current
IDD2N
284
344
304
264
mA
Precharge standby ODT current
IDD2NT
400
360
320
280
mA
Active power-down current
IDD3P
440
400
360
320
mA
Active standby current
IDD3N
480
440
400
360
mA
Burst read operating current
IDD4R
1368
1248
1128
1040
mA
Burst write operating current
IDD4W
1280
1160
1040
920
mA
Refresh current
IDD5B
1600
1560
1520
1480
mA
Self refresh temperature current: MAX TC = 85°C
IDD6
96
96
96
96
mA
IDD6ET
120
120
120
120
mA
All banks interleaved read current
IDD7
2040
1920
1800
1680
mA
Reset current
IDD8
112
112
112
112
mA
Self refresh temperature current (SRT-enabled): MAX TC = 95°C
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB (x64, SR) 240-Pin DDR3 UDIMM
IDD Specifications
Table 15: DDR3 IDD Specifications and Conditions – 2GB (Die Revision K)
Values are for the MT41J256M8 DDR3 SDRAM only and are computed from values specified in the 2Gb (256 Meg x 8) component data sheet.
Parameter
Symbol 1866 1600 1333 1066 Units
Operating current 0: One bank ACTIVATE-to-PRECHARGE
IDD0
344
336
328
312
mA
Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE
IDD1
464
448
432
400
mA
Precharge power-down current: Slow exit
IDD2P0
96
96
96
96
mA
Precharge power-down current: Fast exit
IDD2P1
120
120
120
120
mA
Precharge quiet standby current
IDD2Q
176
176
176
176
mA
Precharge standby current
IDD2N
184
184
184
184
mA
Precharge standby ODT current
IDD2NT
288
272
256
232
mA
Active power-down current
IDD3P
176
176
176
176
mA
Active standby current
IDD3N
296
280
264
248
mA
Burst read operating current
IDD4R
880
800
704
600
mA
Burst write operating current
IDD4W
912
824
728
632
mA
Refresh current
IDD5B
1472
1456
1448
1432
mA
Self refresh temperature current: MAX TC = 85°C
IDD6
96
96
96
96
mA
IDD6ET
120
120
120
120
mA
All banks interleaved read current
IDD7
1368
1304
1256
1024
mA
Reset current
IDD8
112
112
112
112
mA
Self refresh temperature current (SRT-enabled): MAX TC = 95°C
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jtf8c128_256_512x64az.pdf - Rev. H 04/13 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB (x64, SR) 240-Pin DDR3 UDIMM
IDD Specifications
Table 16: DDR3 IDD Specifications and Conditions – 4GB (Die Revision E)
Values are for the MT41J512M8 DDR3 SDRAM only and are computed from values specified in the 4Gb (512 Meg x 8) component data sheet.
Parameter
Symbol 1866 1600 1333 1066 Units
Operating current 0: One bank ACTIVATE-to-PRECHARGE
IDD0
496
440
376
352
mA
Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE
IDD1
560
528
496
472
mA
Precharge power-down current: Slow exit
IDD2P0
144
144
144
144
mA
Precharge power-down current: Fast exit
IDD2P1
296
256
224
208
mA
Precharge quiet standby current
IDD2Q
280
256
224
216
mA
Precharge standby current
IDD2N
280
256
232
224
mA
Precharge standby ODT current
IDD2NT
336
312
280
256
mA
Active power-down current
IDD3P
328
304
280
256
mA
Active standby current
IDD3N
328
304
280
256
mA
Burst read operating current
IDD4R
1392
1256
1120
984
mA
Burst write operating current
IDD4W
1128
1000
880
760
mA
Refresh current
IDD5B
1936
1880
1824
1792
mA
Self refresh temperature current: MAX TC = 85°C
IDD6
160
160
160
160
mA
IDD6ET
200
200
200
200
mA
All banks interleaved read current
IDD7
2008
1760
1520
1280
mA
Reset current
IDD8
160
160
160
160
mA
Self refresh temperature current (SRT-enabled): MAX TC = 95°C
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
1GB, 2GB, 4GB (x64, SR) 240-Pin DDR3 UDIMM
Serial Presence-Detect EEPROM
Serial Presence-Detect EEPROM
For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD.
Table 17: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to VDDSPD
Parameter/Condition
Symbol
Min
Max
Units
VDDSPD
3.0
3.6
V
VIL
–0.6
VDDSPD + 0.3
V
Input high voltage: Logic 1; All inputs
VIH
VDDSPD + 0.7
VDDSPD + 1.0
V
Output low voltage: IOUT = 3mA
VOL
–
0.4
V
Input leakage current: VIN = GND to VDD
ILI
0.1
2.0
µA
Output leakage current: VOUT = GND to VDD
ILO
0.05
2.0
µA
Supply voltage
Input low voltage: Logic 0; All inputs
Table 18: Serial Presence-Detect EEPROM AC Operating Conditions
Parameter/Condition
Symbol
Min
Max
Units
tSCL
10
400
kHz
Clock frequency
Notes
Clock pulse width HIGH time
tHIGH
0.6
–
µs
Clock pulse width LOW time
tLOW
1.3
–
µs
SDA rise time
tR
–
300
µs
1
SDA fall time
tF
20
300
ns
1
Data-in setup time
tSU:DAT
100
–
ns
Data-in hold time
tHD:DI
0
–
µs
Data-out hold time
tHD:DAT
200
900
ns
Data out access time from SCL LOW
tAA:DAT
0.2
0.9
µs
2
Start condition setup time
tSU:STA
0.6
–
µs
3
Start condition hold time
tHD:STA
0.6
–
µs
Stop condition setup time
tSU:STO
0.6
–
µs
tBUF
1.3
–
µs
tW
–
10
ms
Time the bus must be free before a new transition can
start
WRITE time
Notes:
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1. Guaranteed by design and characterization, not necessarily tested.
2. To avoid spurious start and stop conditions, a minimum delay is placed between the falling edge of SCL and the falling or rising edge of SDA.
3. For a restart condition, or following a WRITE cycle.
16
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1GB, 2GB, 4GB (x64, SR) 240-Pin DDR3 UDIMM
Module Dimensions
Module Dimensions
Figure 3: 240-Pin DDR3 UDIMM
Front view
2.7 (0.106)
MAX
133.50 (5.256)
133.20 (5.244)
0.9 (0.035) TYP
0.50 (0.02) R
(4X)
0.75 (0.03) R
(8X)
U1
U2
U3
2.50 (0.098) D
(2X)
U4
U5
U6
U7
U8
30.50 (1.20)
23.3 (0.92) 29.85 (1.175)
TYP
17.3 (0.68)
TYP
U9
2.30 (0.091) TYP
0.76 (0.030) R
Pin 1
2.20 (0.087) TYP
1.0 (0.039)
TYP
1.45 (0.057) TYP
0.80 (0.031)
TYP
9.5 (0.374)
TYP
1.37 (0.054)
1.17 (0.046)
Pin 120
54.68 (2.15)
TYP
123.0 (4.84)
TYP
15.0 (0.59)
4X TYP
1.0 (0.039) R (8X)
Back view
45°, 4X
5.1 (0.2) TYP
3.1 (0.122) 2X TYP
No components this side of module
3.0 (0.118) 4X TYP
3.05 (0.12) TYP
Pin 240
Notes:
Pin 121
5.0 (0.197) TYP
47.0 (1.85)
TYP
71.0 (2.79)
TYP
1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
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