CY25404 Quad PLL Programmable Clock Generator with Spread

CY25404 Quad PLL Programmable Clock Generator with Spread
CY25404
Quad PLL Programmable Clock Generator
with Spread Spectrum
Features
■
Four fully integrated phase-locked loops (PLLs)
■
■
Input frequency range
❐ External crystal: 8 to 48 MHz
❐ External reference: 8 to 166 MHz clock
Benefits
■
Wide operating output frequency range
❐ 3 to 166 MHz
Commercial and Industrial temperature ranges
■
Multiple high performance PLLs allow synthesis of unrelated
frequencies
■
Nonvolatile programming for personalization of PLL
frequencies, spread spectrum characteristics, drive strength,
crystal load capacitance, and output frequencies
■
Application specific programmable electromagnetic
interference (EMI) reduction using spread spectrum for
clocks
■
Programmable PLLs for system frequency margin tests
■
Meets critical timing requirements in complex system
designs
■
Suitability for PC, consumer, portable, and networking
applications
■
Programmable spread spectrum with center and down
spread option and lexmark and linear modulation profiles
■
Selectable VDD supply voltage options:
❐ 2.5 V, 3.0 V, and 3.3 V
■
Selectable output clock voltages, independent of VDD supply:
❐ 1.8 V, 2.5 V, 3.0 V, and 3.3 V
■
Frequency select feature with option to select eight different
frequencies over nine clock outputs
■
Output enable, and SS ON/OFF controls
■
Low jitter, high accuracy outputs
■
■
Ability to synthesize nonstandard frequencies with
Fractional-N capability
Capable of zero parts per million (PPM) frequency synthesis
error
■
■
Up to nine clock outputs with programmable drive strength
Uninterrupted system operation during clock frequency
switch
■
Glitch-free outputs while frequency switching
■
Application compatibility in standard and low power systems
■
20-pin TSSOP package
For a complete list of related documentation, click here.
Block Diagram
XOUT
CLK1
Crossbar
XIN/
EXCLKIN
Bank
1
Switch
OSC
Output
PLL1
CLK3
Dividers
and
FS 0
MUX
FS 1
and
FS 2
CLK4
Bank
2
Drive
PLL2
CLK2
CLK5
CLK6
Strength
CLK7
Control Bank
Control
3
PLL3
(SS)
Logic
CLK8
CLK9
PLL4
(SS)
OE
SSON
Cypress Semiconductor Corporation
Document #: 001-43258 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 3, 2014
CY25404
Contents
General Description ......................................................... 4
Four Configurable PLLs .............................................. 4
Input Reference Clocks ............................................... 4
VDD Power Supply Options ......................................... 4
Output Bank Settings .................................................. 4
Output Source Selection ............................................. 4
Spread Spectrum Control ............................................ 4
Frequency Select ........................................................ 4
Glitch-Free Frequency Switch ..................................... 4
Output Enable Mode ................................................... 4
Output Drive Strength .................................................. 4
Generic Configuration and Custom Frequency ........... 4
Absolute Maximum Conditions....................................... 5
Recommended Operating Conditions ............................ 5
DC Electrical Specifications ............................................ 6
Recommended Crystal Specification
for SMD Package .............................................................. 7
Document #: 001-43258 Rev. *E
Recommended Crystal Specification
for Thru-Hole Package ..................................................... 7
AC Electrical Specifications ............................................ 7
Test and Measurement Setup .......................................... 8
Voltage and Timing Definitions ....................................... 8
Ordering Information ........................................................ 9
Possible Configurations ............................................... 9
Ordering Code Definitions ........................................... 9
Package Drawing and Dimensions ............................... 10
Acronyms ........................................................................ 11
Document Conventions ................................................. 11
Units of Measure ....................................................... 11
Document History Page ................................................. 12
Sales, Solutions, and Legal Information ...................... 13
Worldwide Sales and Design Support ....................... 13
Products .................................................................... 13
PSoC Solutions ......................................................... 13
Page 2 of 13
CY25404
Figure 1. Pin Diagram - CY25404 20 LD TSSOP
VDD
1
20 CLK9
XOUT
2
19 VSS
XIN/EXCLKIN
3
18 CLK8
VSS
4
17 VDD_CLK_B3
16 CLK7/SSON
CLK1 5
CY25404
VDD_CLK_B1 6
15 VDD_CLK_B2
CLK2
7
14 CLK6
VSS
8
13 VSS
CLK3/FS0
9
12 CLK5
OE/FS1 10
11 CLK4/FS2
Table 1. Pin Definition - CY25404 (VDD = 2.5 V, 3.0 V or 3.3 V Supply)
Pin Number
Name
IO
Description
1
VDD
Power
Power supply: 2.5 V/3.0 V/3.3 V
2
XOUT
Output
Crystal output
3
XIN/EXCLKIN
Input
Crystal Input or 1.8 V external clock input
4
VSS
Power
Power supply ground
5
CLK1
Output
Programmable clock output. Output voltage depends on VDD_CLK_B1 voltage
6
VDD_CLK_B1
Power
Power supply for Bank1, (CLK1, CLK2, CLK3) outputs: 1.8 V/2.5 V/3.0 V/3.3 V
7
CLK2
Output
Programmable clock output. Output voltage depends on VDD_CLK_B1 voltage
8
VSS
Power
Power supply ground
9
CLK3/FS0
Output/Input
Multifunction programmable pin: Programmable clock output or frequency select
input pin. Output voltage of CLK3 depends on VDD_CLK_B1 voltage
10
OE/FS1
Input
Multifunction programmable pin: High-true output enable or frequency select pin
11
CLK4/FS2
Output/Input
Multifunction programmable pin: Programmable clock output or frequency select
input pin. Output voltage of CLK4 depends on VDD_CLK_B2 Voltage
12
CLK5
Output
Programmable clock output. Output voltage depends on VDD_CLK_B2 voltage
13
VSS
Power
Power supply ground
14
CLK6
Output
Programmable clock output. Output voltage depends on VDD_CLK_B2 voltage
15
VDD_CLK_B2
Power
Power supply for Bank2, (CLK4, CLK5, CLK6) outputs: 1.8 V/2.5 V/3.0 V/3.3 V
16
CLK7/SSON
Output/Input
Multifunction programmable pin. Programmable clock output or spread spectrum
On/OFF control input pin. Output voltage of CLK7 depends on VDD_CLK_B3
voltage
17
VDD_CLK_B3
Power
Power supply for Bank3, (CLK7, CLK8, CLK9) outputs: 1.8 V/2.5 V/3.0 V/3.3 V
18
CLK8
Output
Programmable clock output. Output voltage depends on VDD_CLK_B3 voltage
19
VSS
Power
Power supply ground
20
CLK9
Output
Programmable clock output. Output voltage depends on VDD_CLK_B3 voltage
Document #: 001-43258 Rev. *E
Page 3 of 13
CY25404
General Description
Four Configurable PLLs
Frequency Select
The CY25404 has four programmable PLLs that can be used to
generate output frequencies ranging from 3 to 166 MHz. The
advantage of having four PLLs is that a single device generates
up to four independent frequencies from a single crystal.
There are three multifunction frequency select pins (FS0, FS1
and FS2) that provide an option to select eight different sets of
frequencies among each of the four PLLs. Each output has
programmable output divider options.
Input Reference Clocks
Glitch-Free Frequency Switch
The input to the CY25404 can be either a crystal or a clock
signal. The input frequency range for crystals is 8 MHz to 48
MHz, while that for clock signals is 8 MHz to 166 MHz. The
required voltage level for the input reference clock (EXCLKIN) is
shown in the DC and AC Electrical Specification tables.
When the frequency select pin (FS) is used to switch frequency,
the outputs are glitch-free provided frequency is switched using
output dividers. This feature enables uninterrupted system
operation while clock frequency is being switched.
VDD Power Supply Options
This device has programmable power supply option and it can
be programmed to operate at any voltage 2.5 V, 3.0 V, or 3.3 V.
Output Bank Settings
There are nine clock outputs grouped in three output driver
banks. The Bank 1, Bank 2, and Bank 3 correspond to (CLK1,
CLK2, CLK3), (CLK4, CLK5, CLK6), and (CLK7, CLK8, CLK9)
respectively. Separate power supplies are used for each of these
banks and they can be any of 1.8 V, 2.5 V, 3.0 V, or 3.3 V. These
voltages are independent of VDD power supply used, giving user
multiple choice of output clock voltage levels.
Output Enable Mode
There is a multifunction programmable pin 10, OE/FS1 that can
be programmed to operate as output enable (OE) mode. OE is
a high-true input and individual clock outputs can be
programmed to be sensitive to this OE pin. If activated it shuts
off the output drivers, resulting in minimum power consumption
for the device.
Output Drive Strength
The DC drive strength of the individual clock output can be
programmed for different values. Table 2 shows the typical rise
and fall times for different drive strength settings.
Table 2. Output Drive Strength
Output Source Selection
These devices have programmable input sources for each of its
nine clock outputs (CLK1–9). There are five available clock
sources for these outputs. These clock sources are:
XIN/EXCLKIN, PLL1, PLL2, PLL3, or PLL4. Output clock source
selection is done using four out of five crossbar switch. Thus, any
one of these five available clock sources can be arbitrarily
selected for the clock outputs. This gives user a flexibility to have
up to four independent clock outputs.
Spread Spectrum Control
Two of the four PLLs (PLL3 and PLL4) have spread spectrum
capability for EMI reduction in the system. The device uses a
Cypress proprietary PLL and spread spectrum clock (SSC)
technology to synthesize and modulate the frequency of the PLL.
The spread spectrum feature can be turned on or off using a
multifunction control pin (CLK7/SSON). It can be programmed to
either center spread range from ±0.125% to ±2.50% or down
spread range from –0.25% to –5.0% with Lexmark or Linear
profile.
Document #: 001-43258 Rev. *E
Output Drive Strength
Rise/Fall Time (ns)
(Typical Value)
Low
6.8
Mid Low
3.4
Mid High
2.0
High
1.0
Generic Configuration and Custom Frequency
There is a generic set of output frequencies available from the
factory that can be used for the device evaluation purposes. The
device, CY25404 can be custom programmed to any desired
frequencies and listed features. For customer specific
programming, please contact local cypress field application
engineer (FAE) or sales representative.
Page 4 of 13
CY25404
Absolute Maximum Conditions
Parameter
Description
Condition
Min
Max
Unit
–
–0.5
4.5
V
VDD
Supply voltage
VDD_CLK_BX
Output bank supply voltage
VIN
Input voltage
Relative to VSS
–
–0.5
4.5
V
–0.5
VDD+0.5
V
+150
TS
Temperature, storage
Non functional
–65
ESDHBM
ESD protection (human body model)
JEDEC EIA/JESD22-A114-E
2000
UL-94
Flammability rating
V-0 at 1/8 in.
MSL
Moisture sensitivity level
–
–
°C
volts
10
ppm
3
Recommended Operating Conditions
Min
Typ
Max
Unit
VDD
Parameter
VDD operating voltage
Description
2.25
–
3.60
V
VDD_CLK_BX
Output driver voltage for Bank 1, 2 and 3
1.71
–
3.60
V
TAC
Commercial ambient temperature
0
–
+70
°C
TAI
Industrial ambient temperature
–40
--
+85
°C
CLOAD
Maximum load capacitance
–
–
15
pF
tPU
Power-up time for all VDD to reach minimum specified voltage (power ramps must
be monotonic)
0.05
–
500
ms
Notes
1. Guaranteed by design but not 100% tested.
2. Configuration dependent.
Document #: 001-43258 Rev. *E
Page 5 of 13
CY25404
DC Electrical Specifications
Parameter
VOL
Description
Output low voltage
Conditions
IOL = 2 mA, drive strength = [00]
Min
Typ
Max
Unit
–
–
0.4
V
VDD_CLK_BX
– 0.4
–
–
V
IOL = 3 mA, drive strength = [01]
IOL = 7 mA, drive strength = [10]
IOL = 12 mA, drive strength = [11]
VOH
Output high voltage
IOH = –2 mA, drive strength = [00]
IOH = –3 mA, drive strength = [01]
IOH = –7 mA, drive strength = [10]
IOH = –12 mA, drive strength = [11]
VIL1
Input low voltage of FS0, OE/FS1, FS2,
and SSON
–
–
–
0.2*VDD
V
VIL2
Input low voltage of EXCLKIN
–
–
–
0.18
V
VIH1
Input high voltage of FS0, OE/FS1,
FS2, and SSON
–
0.8*VDD
–
–
V
VIH2
Input high voltage of EXCLKIN
–
1.62
–
2.2
V
IIL1
Input low current of OE/FS1 pin
VIL = 0V
–
–
10
µA
IIH1
Input high current of OE/FS1 pin
VIH = VDD
–
–
10
µA
IIL2
Input low current of SSON, FS0 and
FS2 pins
VIL = 0V (Internal pull dn = 160k typ)
–
–
10
µA
IIH2
Input high current of SSON, FS0, and VIH = VDD (Internal pull dn = 160k typ)
FS2 pins
14
–
36
µA
RDN
Pull down resistor of SSON, FS0, and Clock outputs in off-state by setting OE
FS2 and off state (CLK1-CLK9) pins
= Low
100
160
250
k
IDD[1,2]
Supply current for CY25404
OE = High, No load
–
22
–
mA
Input capacitance
SSON, CLKIN, FS0, OE/FS1, and FS2
pins
–
7
pF
CIN
[1]
Document #: 001-43258 Rev. *E
Page 6 of 13
CY25404
AC Electrical Specifications
Parameter
Description
Conditions
Min
Typ
Max
Unit
FIN (crystal)
Crystal frequency, XIN
–
8
–
48
MHz
FIN (clock)
Input clock frequency, EXCLKIN
–
8
–
166
MHz
FCLK
Output clock frequency
–
3
–
166
MHz
DC1
Output duty cycle, All clocks
except Ref Out
Duty cycle is defined in Figure 3 on page 8; t1/t2,
measured at 50% of VDD_CLK_BX
45
50
55
%
DC2
Ref out duty cycle
Ref In Min 45%, Max 55%
40
–
60
%
[1]
Output rise/fall time
Measured from 20% to 80% of VDD_CLK_BX, as
shown in Figure 4 on page 8, CLOAD = 15 pF, Drive
strength [00]
–
6.8
–
ns
TRF2[1]
Output rise/fall time
Measured from 20% to 80% of VDD_CLK_BX, as
shown in Figure 4 on page 8, CLOAD = 15 pF, Drive
strength [01]
–
3.4
–
ns
TRF3[1]
Output rise/fall time
Measured from 20% to 80% of VDD_CLK_BX, as
shown in Figure 4 on page 8, CLOAD = 15 pF, Drive
strength [10]
–
2.0
–
ns
TRF4[1]
Output rise/fall time
Measured from 20% to 80% of VDD_CLK_BX, as
shown in Figure 4 on page 8, CLOAD = 15 pF, Drive
strength [11]
–
1.0
–
ns
TCCJ[1,2]
Cycle-to-cycle jitter (peak)
Configuration dependent. See Table 3
–
100
–
ps
TLOCK[1]
PLL lock time
Measured from 90% of the applied power supply
level
–
1
3
ms
TRF1
Table 3. Configuration Example for C-C Jitter
Ref. Freq.
(MHz)
CLK1 Output
Freq.
(MHz)
C-C Jitter
Typ (ps)
14.3181
8.0
19.2
74.25
CLK2 Output
CLK3 Output
Freq.
(MHz)
C-C Jitter
Typ (ps)
Freq.
(MHz)
134
166
103
99
166
94
CLK4 Output
CLK5 Output
C-C Jitter
Typ (ps)
Freq.
(MHz)
C-C Jitter
Typ (ps)
48
92
74.25
81
8
91
27
110
Freq.
(MHz)
C-C Jitter
Typ (ps)
Not Used
27
48
67
27
109
166
103
74.25
97
48
48
93
27
123
166
137
166
138
48
75
Not Used
8
103
Recommended Crystal Specification for SMD Package
Parameter
FIN
Description
Crystal frequency
Range 1
8 – 14
R1
Maximum motional resistance (ESR)
CL
Parallel load capacitance (device has internal load capacitance adjustment
feature)
DL(max)
Maximum crystal drive level
Range 2 Range 3
Unit
14 – 28
MHz
28 – 48
135
50
30

8 – 18
8 – 14
8 – 12
pF
300
300
300
µW
Recommended Crystal Specification for Thru-Hole Package
Parameter
FIN
Description
Crystal frequency
Range 1
8 – 14
Range 2 Range 3
Unit
14 – 24
MHz
24 – 32
R1
Maximum motional resistance (ESR)
90
50
30

CL
Parallel load capacitance (device has internal load capacitance
adjustment feature)
8 – 18
8 – 12
8 – 12
pF
DL(max)
Maximum crystal drive level
1000
1000
1000
µW
Document #: 001-43258 Rev. *E
Page 7 of 13
CY25404
Test and Measurement Setup
Figure 2. Test and Measurement Setup
V DD
0.1 F
Outputs
C LOAD
DUT
GND
Voltage and Timing Definitions
Figure 3. Duty Cycle Definition
t1
t2
VDD_CLK_BX
50% of V
Clock
Output
DD_CLK_BX
0V
Figure 4. Rise Time = TRF, Fall Time = TRF
TRF
TRF
V DD_CLK_BX
80% of V
Clock
Output
Document #: 001-43258 Rev. *E
20% of V
DD_CLK_BX
DD_CLK_BX
0V
Page 8 of 13
CY25404
Ordering Information
Some product offerings are factory programmed customer specific devices with customized part numbers. The Possible
Configurations table shows the available device types, but not complete part numbers. Contact your local Cypress FAE or Sales
representative for more information.
Possible Configurations
Part Number[3]
Type
Production Flow
Pb-free
CY25404ZXC-xxx
20-pin TSSOP
Commercial, 0 °C to 70 °C
CY25404ZXC-xxxT
20-pin TSSOP -Tape and Reel
Commercial, 0 °C to 70 °C
CY25404ZXI-xxx
20-pin TSSOP
Industrial, –40 °C to +85 °C
CY25404ZXI-xxxT
20-pin TSSOP -Tape and Reel
Industrial, –40 °C to +85 °C
Ordering Code Definitions
CY25404
ZX
C/I
- xxx T
Package Type: (T = Tape and Reel)
Customer specific identification code
Temperature code (C= Commercial or I= Industrial)
20-Pin TSSOP package
Marketing Code: CY25404 = Device Number
Note
3. xxx indicates Factory Programmable and are factory programmed configurations. For more details, contact your local Cypress FAE or Cypress Sales Representative.
Document #: 001-43258 Rev. *E
Page 9 of 13
CY25404
Package Drawing and Dimensions
Figure 5. 20-LD TSSOP, Thin Shrunk Small Outline Package (4.40 mm Body) ZZ2
51-85118 *E
Document #: 001-43258 Rev. *E
Page 10 of 13
CY25404
Acronyms
Acronym
Description
DL
drive level
EMI
electromagnetic interference
ESD
electrostatic discharge
FAE
field application engineer
FS
frequency select
JEDEC EIA
joint electron devices
engineering council electronic
industries alliance
OE
output enable
OSC
oscillator
PD
power-down
PLL
phase-locked loop
PPM
parts per million
SS
spread spectrum
SSC
spread spectrum clock
SSON
spread spectrum on
TSSOP
thin shrunk small outline
package
Document Conventions
Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
fF
femtofarads
mA
milliampere
MHz
megahertz
s
microseconds
ms
millisecond
W
microwatts
ns
nanoseconds
pF
picofarads
ppm
parts per million
ps
picoseconds
V
volts

ohms
W
watts
Document #: 001-43258 Rev. *E
Page 11 of 13
CY25404
Document History Page
Document Title: CY25404 Quad PLL Programmable Clock Generator with Spread Spectrum
Document Number: 001-43258
REV.
ECN NO.
Issue
Date
**
1793805
See ECN
Orig. of
Change
Description of Change
DPF/AESA New data sheet
*A
2748211
08/10/09
TSAI
Posting to external web.
*B
2899300
03/26/2010
CXQ
Updated Ordering Information. Added note regarding Possible Configurations in Ordering Information section.
Added Possible Configurations table for “xxx’ parts.
Updated Package Drawing and Dimensions
*C
3308261
07/11/2011
BASH
Added Ordering Code Definitions
Updated Package Drawing and Dimensions
Added Acronyms
Added Units of Measure
Added Contents
*D
4416418
06/30/2014
XHT
Added 1.8V for output clock voltage in page 1: Features
Added 1.8V for Table 1: Pin Definition, VDD_CLK_B1, VDD_CLK_B2 and
VDD_CLK_B3
Added 1.8V for General Description: Output Bank Settings
Changed VDD_CLK_BX Min parameter from 2.25 to 1.71
*E
4586478
03/12/2014
XHT
Added related documentation hyperlink in page 1.
Updated package diagram 51-85118 to current revision.
Updated package drawing revision *D
Document #: 001-43258 Rev. *E
Page 12 of 13
CY25404
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
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Interface
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PSoC Solutions
cypress.com/go/automotive
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PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
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© Cypress Semiconductor Corporation, 2007-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document #: 001-43258 Rev. *E
Revised December 3, 2014
Page 13 of 13
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