LM4844 Stereo 1.2W Audio Sub-System with 3D Enhancement

LM4844 Stereo 1.2W Audio Sub-System with 3D Enhancement
LM4844
www.ti.com
SNAS320D – JUNE 2005 – REVISED APRIL 2013
LM4844 Boomer™ Audio Power Amplifier Series Stereo 1.2W Audio Sub-System with 3D
Enhancement
Check for Samples: LM4844
FEATURES
DESCRIPTION
•
•
•
The LM4844 is an integrated audio sub-system
designed for stereo cell phone applications.
Operating on a 3.3V supply, it combines a stereo
speaker amplifier delivering 495mW per channel into
an 8Ω load and a stereo OCL headphone amplifier
delivering 33mW per channel into a 32Ω load.
1
23
•
•
•
•
•
Stereo Speaker Amplifier
Stereo OCL Headphone Amplifier
Independent Left, Right, and Mono Volume
Controls
Texas Instruments 3D Enhancement
I2C Compatible Interface
Ultra Low Shutdown Current
Click and Pop Suppression Circuit
10 Distinct Output Modes
APPLICATIONS
•
•
•
•
•
Cell Phones
PDAs
Portable Gaming Devices
Internet Appliances
Portable DVD, CD, AAC, and MP3 Players
It integrates the audio amplifiers, volume control,
mixer, power management control, and Texas
Instruments 3D enhancement all into a single
package. In addition, the LM4844 routes and mixes
the stereo and mono inputs into 10 distinct output
modes. The LM4844 is controlled through an I2C
compatible interface.
Boomer audio power amplifiers are designed
specifically to provide high quality output power with a
minimal amount of external components.
The LM4844 is available in a very small 2.5mm x
2.9mm 30-bump DSBGA (YZR) package.
KEY SPECIFICATIONS
•
•
•
POUT, Stereo BTL, 8Ω, 3.3V,
1% THD+N, 495mW (Typ)
POUT HP, 32Ω, 3.3V,
1% THD+N, 33mW (Typ)
Shutdown Current, 3.3V , 0.1µA (Typ)
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Boomer is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005–2013, Texas Instruments Incorporated
LM4844
SNAS320D – JUNE 2005 – REVISED APRIL 2013
www.ti.com
Block Diagram
C3DHP
VDD
P1
C3DLS
Ci1
MIN
+
LHP3D
4.7 k:
RHP3D
LLS3D
VDD
0.22 PF
4.7 k:
R3DLS
0.22 PF
1 PF
Audio Input
100 k:
RLS3D
CS +
P2
100 k:
R3DHP
LLS+
Mono Input
-34.5 dB to +12 dB
8:
0.22 PF
Ci2
Audio Input
LLSLIN
+
Left Stereo Input
-40.5 dB to +6 dB
RLS+
0.22 PF
Ci3
Audio Input
8:
RIN
+
Right Stereo Input
-40.5 dB to +6 dB
0.22 PF
BYPASS
CB
I2CVDD
National
3D
RLS-
Mixer
&
Mode Select
OCL
Bias
Click / Pop Supression
+
RHP
2.2 PF
LHP
I2CVDD
I2C
Interface
SCL
I2C
Bus
SDA
GND
ADR
VIH
VIL
Figure 1. Audio Sub-System Block Diagram
Connection Diagram
Figure 2. 30 Bump DSBGA (YZR) Package
Top View
(Bump-side down)
See Package Number YZR0030
2
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM4844
LM4844
www.ti.com
SNAS320D – JUNE 2005 – REVISED APRIL 2013
PIN CONNECTION (YZR)
Pin
Name
Pin Description
A1
RLS+
Right Loudspeaker Positive Output
A2
VDD
Power Supply
A3
SDA
Data
A4
RHP3D
Right Headphone 3D
A5
RHP
Right Headphone Output
B1
GND
Ground
B2
I2CVDD
I2C Interface Power Supply
B3
ADR
I2C Address Select
B4
LHP3D
Left Headphone 3D
B5
VDD
Power Supply
C1
RLS-
Right Loudspeaker Negative Output
C2
NC
No Connect
C3
SCL
Clock
C4
NC
No Connect
C5
GND
Ground
D1
LLS-
Left Loudspeaker Negative Output
D2
VDD
Power Supply
D3
MIN
Mono Input
D4
NC
No Connect
D5
OCL
VDD/2 Supply for headphone jack's sleeve
E1
GND
Ground
E2
BYPASS
Half-supply bypass
E3
LLS3D
Left Loudspeaker 3D
E4
RIN
Right Stereo Input
E5
NC
No Connect
F1
LLS+
Left Loudspeaker Positive Output
F2
VDD
Power Supply
F3
RLS3D
Right Loudspeaker 3D
F4
LIN
Left Stereo Input
F5
LHP
Left Headphone Output
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM4844
3
LM4844
SNAS320D – JUNE 2005 – REVISED APRIL 2013
www.ti.com
Absolute Maximum Ratings (1) (2) (3)
Supply Voltage
6.0V
−65°C to +150°C
Storage Temperature
−0.3V to VDD +0.3V
Input Voltage
Power Dissipation (4)
Internally Limited
(5)
2000V
ESD Susceptibility
ESD Susceptibility (6)
200V
Junction Temperature (TJ)
Thermal Resistance
(1)
(2)
(3)
(4)
(5)
(6)
150°C
θJA (YZR0030)
62°C/W
All voltages are measured with respect to the GND pin unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings,
whichever is lower. For the LM4844 typical application with VDD = 3.3V and RL = 8Ω stereo operation, the total power dissipation is
TBDW. θJA = TBD°C/W.
Human body model, 100pF discharged through a 1.5kΩ resistor.
Machine Model, 220pF-240pF discharged through all pins.
Operating Ratings
Temperature Range
TMIN ≤ TA ≤ TMAX
I2CVDD ≤ VDD
Supply Voltage (I2CVDD) (1)
(1)
4
−40°C ≤ TA ≤ +85°C
2.7V ≤ VDD ≤ 5.5V
Supply Voltage (VDD)
2
1.7V ≤ I CVDD ≤ 5.5V
Refer to Control Interface Electrical Characteristics tables.
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM4844
LM4844
www.ti.com
SNAS320D – JUNE 2005 – REVISED APRIL 2013
Audio Amplifier Electrical Characteristics VDD = 5.0V (1) (2)
The following specifications apply for VDD = 5.0V, unless otherwise specified. Limits apply for TA = 25°C.
Symbol
Parameter
Conditions
LM4844
Typical
(3)
Limits
(4) (5)
Units
(Limits)
VIN = 0V, No load;
LD5 = RD5 = 0
Supply Current (6)
IDD
ISD
Shutdown Current (6)
PO
Output Power
Mode 4, 9, 14
5
8
mA (max)
Mode 2, 7, 12
12
18
mA (max)
Mode 3, 8, 13
13
20
mA (max)
Mode 0
0.2
2.5
µA (max)
Speaker; THD+N = 1%;
f = 1kHz; 8Ω BTL
1.2
0.9
W (min)
Headphone; THD+N = 1%;
f = 1kHz; 32Ω SE
80
60
mW (min)
LD5 = RD5 = 0
THD+N
Total Harmonic Distortion Plus
Noise
VOS
Offset Voltage
NOUT
Output Noise
Speaker; PO = 400mW;
f = 1kHz; 8Ω BTL
0.05
%
Headphone; PO = 15mW;
f = 1kHz; 32Ω SE
0.06
%
Speaker; LD5 = RD5 = 0
5
40
mV (max)
Headphone; LD5 = RD5 = 0
2
30
mV (max)
A-weighted, 0dB gain;
LD5 = RD5 = 0
Speaker; Mode 2, 3, 7, 8
31
µV
Speaker; Mode 12, 13
35
µV
Headphone; Mode 3, 4, 8, 9
12
µV
Headphone; Mode 13, 14
14
µV
f = 217Hz; Vrip = 200mVpp; CB = 2.2µF;
0dB Gain Setting; LD5 = RD5 = 0
PSRR
Power Supply Rejection Ratio
Speaker; Mode 2, 3, 7, 8
71
Speaker; Mode 12, 13,
65
Headphone; Mode 3, 4, 8, 9
76
Headphone; Mode 13, 14
72
dB
55
dB (min)
62
dB (min)
dB
LD5 = RD5 = 0
Xtalk
TWU
(1)
(2)
(3)
(4)
(5)
(6)
Crosstalk
Wake-up Time
Loudspeaker; PO = 400mW;
f = 1kHz
84
dB
Headphone; PO = 15mW;
f = 1kHz
60
dB
CD4 = 0; CB = 2.2µF
103
ms
CD4 = 1; CB = 2.2µF
42
ms
All voltages are measured with respect to the GND pin unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
Typicals are measured at +25°C and represent the parametric norm.
Limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level).
Datasheet min/max specification limits are specified by design, test, or statistical analysis.
Shutdown current and supply current are measured in a normal room environment.
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM4844
5
LM4844
SNAS320D – JUNE 2005 – REVISED APRIL 2013
www.ti.com
Audio Amplifier Electrical Characteristics VDD = 3.0V (1) (2)
The following specifications apply for VDD = 3.0V, unless otherwise specified. Limits apply for TA = 25°C.
Symbol
Parameter
Conditions
LM4844
Typical
(3)
Limits
(4) (5)
Units
(Limits)
VIN = 0V, No load;
LD5 = RD5 = 0
Supply Current (6)
I DD
ISD
Shutdown Current (6)
PO
Output Power
Mode 4, 9, 14
4.5
7.5
mA (max)
Mode 2, 7, 12
10
16
mA (max)
Mode 3, 8, 13
11
18
mA (max)
Mode 0
0.1
2
µA (max)
Speaker; THD+N = 1%;
f = 1kHz; 4Ω BTL
390
320
mW (min)
Headphone; THD+N = 1%;
f = 1kHz; 32Ω SE
28
21
mW (min)
LD5 = RD5 = 0
THD+N
VOS
Total Harmonic Distortion Plus
Noise
Offset Voltage
Speaker; PO = 200mW;
f = 1kHz; 8Ω BTL
0.05
%
Headphone; PO = 10mW;
f = 1kHz; 32Ω SE
0.05
%
Speaker; LD5 = RD5 = 0
5
40
mV (max)
Headphone; LD5 = RD5 = 0
2
30
mV (max)
A-weighted; 0dB gain;
LD5 = RD5 = 0
NOUT
Output Noise
Speaker; Mode 2, 3, 7, 8
32
µV
Speaker; Mode 12, 13
41
µV
Headphone; Mode 3, 4, 8, 9
13
µV
Headphone; Mode 13, 14
15
µV
f = 217Hz, Vrip = 200mVpp; CB = 2.2µF;
0dB Gain Setting; LD5 = RD5 = 0
PSRR
Power Supply Rejection Ratio
Speaker; Mode 2, 3, 7, 8
73
Speaker; Mode 12, 13,
66
Headphone; Mode 3, 4, 8, 9
78
Headphone; Mode 13, 14
72
dB
55
dB (min)
62
dB (min)
dB
LD5 = RD5 = 0
Xtalk
TWU
(1)
(2)
(3)
(4)
(5)
(6)
6
Crosstalk
Wake-up Time
Loudspeaker; PO = 200mW;
f = 1kHz
85
dB
Headphone; PO = 10mW;
f = 1kHz
60
dB
CD4 = 0; CB = 2.2µF
70
ms
CD4 = 1; CB = 2.2µF
30
ms
All voltages are measured with respect to the GND pin unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
Typicals are measured at +25°C and represent the parametric norm.
Limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level).
Datasheet min/max specification limits are specified by design, test, or statistical analysis.
Shutdown current and supply current are measured in a normal room environment.
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM4844
LM4844
www.ti.com
SNAS320D – JUNE 2005 – REVISED APRIL 2013
Volume Control Electrical Characteristics (1) (2)
The following specifications apply for 3V ≤ VDD ≤ 5V and 3V ≤ I2CVDD ≤ 5V, unless otherwise specified. Limits apply for TA =
25°C.
Symbol
Parameter
Stereo Volume Control Range
Mono Volume Control Range
Conditions
maximum gain setting
6
5.5
6.5
dB (min)
dB (max)
minimum gain setting
-40.5
-41
-40
dB (min)
dB (max)
maximum gain setting
12
11.5
12.5
dB (min)
dB (max)
minimum gain setting
-34.5
-35
-34
dB (min)
dB (max)
+/-0.5
dB (max)
1.5
dB
Volume Control Step Size Error
+/-0.2
Stereo Channel to Channel Gain
Mismatch
0.3
dB
Headphone
100
dB
maximum gain setting
33
25
42
kΩ (min)
kΩ (max)
minimum gain setting
100
75
125
kΩ (min)
kΩ (max)
maximum gain setting
20
15
25
kΩ (min)
kΩ (max)
minimum gain setting
96
73
123
kΩ (min)
kΩ (max)
Mute Attenuation
LIN and RIN Input Impedance
MIN Input Impedance
(3)
(4)
(5)
Units
(Limits)
Limits (4) (5)
Volume Control Step Size
(1)
(2)
LM4844
Typical (3)
Mode 12, Vin = 1VRMS
All voltages are measured with respect to the GND pin unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
Typicals are measured at +25°C and represent the parametric norm.
Limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level).
Datasheet min/max specification limits are specified by design, test, or statistical analysis.
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM4844
7
LM4844
SNAS320D – JUNE 2005 – REVISED APRIL 2013
www.ti.com
Control Interface Electrical Characteristics (1) (2)
The following specifications apply for VDD = 5.0V and 3.0V, TA = 25°C, 2.2V ≤ I2CVDD ≤ 5.5V, unless otherwise specified.
Symbol
Parameter
Conditions
LM4844
Typical
(3)
Limits
(1) (4) (5)
Units
(Limits)
t1
I2C Clock Period
2.5
µs (min)
t2
I2C Data Setup Time
100
ns (min)
t3
I2C Data Stable Time
0
ns (min)
t4
Start Condition Time
100
ns (min)
t5
Stop Condition time
100
ns (min)
t6
I2C Data Hold Time
100
ns (min)
2
2
VIH
I C Input Voltage High
0.7 x I CVDD
V (min)
VIL
I2C Input Voltage Low
0.3 x I2CVDD
V (max)
(1)
(2)
(3)
(4)
(5)
All voltages are measured with respect to the GND pin unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
Typicals are measured at +25°C and represent the parametric norm.
Limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level).
Datasheet min/max specification limits are specified by design, test, or statistical analysis.
Control Interface Electrical Characteristics (1) (2)
The following specifications apply for VDD = 5.0V and 3.0V, TA = 25°C, 1.7V ≤ I2CVDD ≤ 2.2V, unless otherwise specified.
Symbol
Parameter
Conditions
LM4844
Typical (3)
t1
I2C Clock Period
2
Limits (1) (4) (5)
Units
(Limits)
2.5
µs (min)
t2
I C Data Setup Time
250
ns (min)
t3
I2C Data Stable Time
0
ns (min)
t4
Start Condition Time
250
ns (min)
t5
Stop Condition time
250
ns (min)
t6
I2C Data Hold Time
250
ns (min)
VIH
I2C Input Voltage High
0.7 x I2CVDD
V (min)
VIL
I2C Input Voltage Low
0.25 x I2CVDD
V (max)
(1)
(2)
(3)
(4)
(5)
8
All voltages are measured with respect to the GND pin unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional but do not ensure specific performance limits. Electrical Characteristics state DC and AC electrical
specifications under particular test conditions which ensure specific performance limits. This assumes that the device is within the
Operating Ratings. Specifications are not ensured for parameters where no limit is given, however, the typical value is a good indication
of device performance.
Typicals are measured at +25°C and represent the parametric norm.
Limits are specified to Texas Instruments' AOQL (Average Outgoing Quality Level).
Datasheet min/max specification limits are specified by design, test, or statistical analysis.
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM4844
LM4844
www.ti.com
SNAS320D – JUNE 2005 – REVISED APRIL 2013
Typical Performance Characteristics
10
5
5
2
2
1
1
THD + N (%)
THD + N (%)
10
LM4844TL THD+N vs Frequency
VDD = 5V, RL = 8Ω, Mode 7
LS, PO = 400mW
0.5
0.2
0.1
0.5
0.2
0.1
0.05
0.05
0.02
0.02
0.01
20
50 100 200 500 1k 2k
LM4844TL THD+N vs Frequency
VDD = 3V, RL = 8Ω, Mode 7
LS, PO = 200mW
0.01
20
5k 10k 20k
50 100 200
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 4.
LM4844TL THD+N vs Frequency
VDD = 5V, RL = 32Ω, Mode 9
HP, PO = 15mW, 0dB Gain
LM4844TL THD+N vs Frequency
VDD = 3V, RL = 32Ω, Mode 9
HP, PO = 10mW, 0dB Gain
10
5
5
2
2
1
1
0.5
0.2
0.1
0.5
0.2
0.1
0.05
0.05
0.02
0.02
0.01
20
50 100 200
500 1k 2k
0.01
20
5k 10k 20k
50 100 200 500 1k 2k
FREQUENCY (Hz)
5k 10k 20k
FREQUENCY (Hz)
Figure 5.
Figure 6.
LM4844TL THD+N vs Output Power
VDD = 5V, RL = 8Ω, Mode 7
LS, f = 1kHz, 0dB Gain
LM4844TL THD+N vs Output Power
VDD = 3V, RL = 8Ω, Mode 7
LS, f = 1kHz, 0dB Gain
10
10
5
5
2
2
1
1
THD + N (%)
THD + N (%)
5k 10k 20k
Figure 3.
THD + N (%)
THD + N (%)
10
500 1k 2k
0.5
0.2
0.1
0.5
0.2
0.1
0.05
0.05
0.02
0.02
0.01
10m 20m
50m 100m 200m 500m
1
2
OUTPUT POWER (W)
0.01
10m 20m
50m 100m 200m 500m
1
2
OUTPUT POWER (W)
Figure 7.
Figure 8.
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM4844
9
LM4844
SNAS320D – JUNE 2005 – REVISED APRIL 2013
www.ti.com
Typical Performance Characteristics (continued)
LM4844TL THD+N vs Output Power
VDD = 5V, RL = 32Ω, Mode 9
HP, f = 1kHz, 0dB Gain
LM4844TL THD+N vs Output Power
VDD = 3V, RL = 32Ω, Mode 9
HP, f = 1kHz, 0dB Gain
10
10
5
5
2
2
1
THD + N (%)
THD + N (%)
1
0.5
0.2
0.1
0.5
0.2
0.1
0.05
0.05
0.02
0.02
0.01
1m
2m
5m 10m 20m
0.01
1m
50m 100m 200m
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
20
Figure 10.
LM4844TL PSRR vs Frequency
VDD = 5V, RL = 8Ω, LS
Top-Modes 12, 13
Bottom-Modes 2, 3, 7, 8
LM4844TL PSRR vs Frequency
VDD = 3V, RL = 8Ω, LS
Top-Modes 12, 13
Bottom-Modes 2, 3, 7, 8
50 100 200
500 1k 2k
5k 10k 20k
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
20
5k 10k 20k
FREQUENCY (Hz)
Figure 12.
LM4844TL PSRR vs Frequency
VDD = 5V, RL = 32Ω, HP
Top-Modes 13, 14
Bottom-Modes 3, 4, 8, 9
LM4844TL PSRR vs Frequency
VDD = 3V, RL = 32Ω, HP
Top-Modes 13, 14
Bottom-Modes 3, 4, 8, 9
POWER SUPPLY REJECTION RATIO (dB)
POWER SUPPLY REJECTION RATIO (dB)
50 100 200 500 1k 2k
Figure 11.
50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
20
50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
Figure 13.
10
50m 100m 200m
OUTPUT POWER (W)
FREQUENCY (Hz)
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
20
5m 10m 20m
Figure 9.
POWER SUPPLY REJECTION RATIO (dB)
POWER SUPPLY REJECTION RATIO (dB)
OUTPUT POWER (W)
2m
Figure 14.
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM4844
LM4844
www.ti.com
SNAS320D – JUNE 2005 – REVISED APRIL 2013
Typical Performance Characteristics (continued)
LM4844TL Crosstalk vs Frequency
VDD = 3V, RL = 8Ω, Mode 7
LS, PO = 200mW
0
0
-10
-10
-20
-20
-30
-30
CROSSTALK (dB)
CROSSTALK (dB)
LM4844TL Crosstalk vs Frequency
VDD = 5V, RL = 8Ω, Mode 7
LS, PO = 400mW
-40
-50
-60
L to R
-70
-80
-90
-40
-50
-60
-70
L to R
-80
-90
-100
-100
R to L
-110
R to L
-110
-120
-120
20
50 100 200
500 1k 2k
5k 10k 20k
20
FREQUENCY (Hz)
Figure 16.
LM4844TL Crosstalk vs Frequency
VDD = 5V, RL = 32Ω, Mode 9
HP, PO = 15mW, 0dB Gain
LM4844TL Crosstalk vs Frequency
VDD = 3V, RL = 32Ω, Mode 9
HP, PO = 10mW, 0dB Gain
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
20
R to L
L to R
50 100 200
500 1k 2k
5k 10k 20k
0
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
20
FREQUENCY (Hz)
R to L
L to R
50 100 200
500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
Figure 17.
Figure 18.
LM4844TL Frequency Response
VDD = 5V, RL = 8Ω, Mode 2
LS, Full Gain = 18dB
LM4844TL Frequency Response
VDD = 5V, RL = 8Ω, Mode 7
LS, Full Gain = 12dB
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
20
GAIN (dB)
GAIN (dB)
5k 10k 20k
Figure 15.
CROSSTALK (dB)
CROSSTALK (dB)
FREQUENCY (Hz)
50 100 200 500 1k 2k
50 100 200
500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
14
13.5
13
12.5
12
11.5
11
10.5
10
9.5
9
8.5
8
7.5
7
6.5
6
20
50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
Figure 19.
Figure 20.
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM4844
11
LM4844
SNAS320D – JUNE 2005 – REVISED APRIL 2013
www.ti.com
Typical Performance Characteristics (continued)
14
13.5
13
12.5
12
11.5
11
10.5
10
9.5
9
8.5
8
7.5
7
6.5
6
5.5
5
4.5
4
20
LM4844TL Frequency Response
VDD = 5V, RL = 32Ω, Mode 9
HP, Full Gain = 6dB
GAIN (dB)
GAIN (dB)
LM4844TL Frequency Response
VDD = 5V, RL = 32Ω, Mode 4
HP, Full Gain = 12dB
50 100 200 500 1k 2k
5k 10k 20k
10
9.5
9
8.5
8
7.5
7
6.5
6
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
20
50 100 200
FREQUENCY (Hz)
500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
Figure 21.
Figure 22.
LM4844TL Power Dissipation vs Output Power
VDD = 5V, RL = 8Ω
LS, per channel
LM4844TL Power Dissipation vs Output Power
VDD = 3V, RL = 8Ω
LS, per channel
700
250
225
600
200
175
PDISS (mW)
PDISS (mW)
500
400
300
150
125
100
75
200
50
100
25
0
0
0
200
400
600
800 1000 1200 1400
0
50 100 150 200 250 300 350 400
POUT (mW)
POUT (mW)
Figure 23.
Figure 24.
LM4844TL Power Dissipation vs Output Power
VDD = 5V, RL = 8Ω
OCL HP, per channel
LM4844TL Power Dissipation vs Output Power
VDD = 3V, RL = 32Ω
OCL HP, per channel
60
180
160
50
140
40
PDISS (mW)
PDISS (mW)
120
100
80
30
20
60
40
10
20
0
0
0
10
20
30
40
50
60
70
80
90
5
10
15
20
25
30
POUT (mW)
POUT (mW)
Figure 25.
12
0
Figure 26.
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM4844
LM4844
www.ti.com
SNAS320D – JUNE 2005 – REVISED APRIL 2013
Typical Performance Characteristics (continued)
LM4844TL Output Power vs Load Resistance, LS
Top-VDD = 5V, 10% THD+N; Topmid-VDD = 5V, 1%THD+N
Botmid-VDD = 3V, 10% THD+N;
Botmid-VDD = 3V, 1% THD+N
1600
LM4844TL Output Power vs Load Resistance, HP
Top-VDD = 5V, 10% THD+N; Topmid-VDD = 5V, 1%THD+N
Botmid-VDD = 3V, 10% THD+N;
Botmid-VDD = 3V, 1% THD+N
180
160
OUTPUT POWER (mW)
OUTPUT POWER (mW)
1400
1200
1000
800
600
400
200
140
120
100
80
60
40
20
0
0
0
10
20
30
40
50
60
70
0
LOAD RESISTANCE (Ω)
10
20
30
40
50
60
70
LOAD RESISTANCE (: )
Figure 27.
Figure 28.
LM4844TL Output Power vs Supply Voltage, LS
RL = 8Ω; Top- 10%THD+N , Bot- 1%THD+N
LM4844TL Output Power vs Supply Voltage, HP
RL = 32Ω; Top- 10%THD+N, Bot- 1%THD+N
2000
140
120
1600
100
1400
POUT (mW)
OUTPUT POWER (mW)
1800
1200
1000
800
600
80
60
40
400
20
200
0
0
2
2.5
3
3.5
4
4.5
5
5.5
6
SUPPLY VOLTAGE (V)
2
3
4
5
6
SUPPLY VOLTAGE (V)
Figure 29.
Figure 30.
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM4844
13
LM4844
SNAS320D – JUNE 2005 – REVISED APRIL 2013
www.ti.com
APPLICATION INFORMATION
Figure 31. I2C Timing Diagram
Figure 32. I2C Bus Format
Table 1. Chip Address
A7
A6
A5
A4
A3
A2
A1
A0
Chip Address
1
1
1
1
1
0
EC
0
ADR = 0
1
1
1
1
1
0
0
0
ADR = 1
1
1
1
1
1
0
1
0
Table 2. Control Registers
D7
D6
D5
D4
D3
D2
D1
D0
Mono Volume control
0
0
0
MD4
MD3
MD2
MD1
MD0
Left Volume control
0
1
LD5
LD4
LD3
LD2
LD1
LD0
Right Volume control
1
0
RD5
RD4
RD3
RD2
RD1
RD0
Mode control
1
1
CD5
0
CD3
CD2
CD1
CD0
Table 3. Mono Volume Control
14
MD4
MD3
MD2
MD1
MD0
Gain (dB)
0
0
0
0
0
-34.5
0
0
0
0
1
-33.0
0
0
0
1
0
-31.5
0
0
0
1
1
-30.0
0
0
1
0
0
-28.5
0
0
1
0
1
-27.0
0
0
1
1
0
-25.5
0
0
1
1
1
-24.0
0
1
0
0
0
-22.5
0
1
0
0
1
-21.0
0
1
0
1
0
-19.5
0
1
0
1
1
-18.0
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM4844
LM4844
www.ti.com
SNAS320D – JUNE 2005 – REVISED APRIL 2013
Table 3. Mono Volume Control (continued)
MD4
MD3
MD2
MD1
MD0
Gain (dB)
0
1
1
0
0
-16.5
0
1
1
0
1
-15.0
0
1
1
1
0
-13.5
0
1
1
1
1
-12.0
1
0
0
0
0
-10.5
1
0
0
0
1
-9.0
1
0
0
1
0
-7.5
1
0
0
1
1
-6.0
1
0
1
0
0
-4.5
1
0
1
0
1
-3.0
1
0
1
1
0
-1.5
1
0
1
1
1
0.0
1
1
0
0
0
1.5
1
1
0
0
1
3.0
1
1
0
1
0
4.5
1
1
0
1
1
6.0
1
1
1
0
0
7.5
1
1
1
0
1
9.0
1
1
1
1
0
10.5
1
1
1
1
1
12.0
LD4//RD4
LD3//RD3
LD2//RD2
LD1//RD1
LD0//RD0
Gain (dB)
0
0
0
0
0
-40.5
0
0
0
0
1
-39.0
0
0
0
1
0
-37.5
0
0
0
1
1
-36.0
0
0
1
0
0
-34.5
0
0
1
0
1
-33.0
0
0
1
1
0
-31.5
0
0
1
1
1
-30.0
0
1
0
0
0
-28.5
0
1
0
0
1
-27.0
0
1
0
1
0
-25.5
0
1
0
1
1
-24.0
0
1
1
0
0
-22.5
0
1
1
0
1
-21.0
0
1
1
1
0
-19.5
0
1
1
1
1
-18.0
1
0
0
0
0
-16.5
1
0
0
0
1
-15.0
1
0
0
1
0
-13.5
1
0
0
1
1
-12.0
1
0
1
0
0
-10.5
1
0
1
0
1
-9.0
1
0
1
1
0
-7.5
1
0
1
1
1
-6.0
Table 4. Stereo Volume Control
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM4844
15
LM4844
SNAS320D – JUNE 2005 – REVISED APRIL 2013
www.ti.com
Table 4. Stereo Volume Control (continued)
LD4//RD4
LD3//RD3
LD2//RD2
LD1//RD1
LD0//RD0
Gain (dB)
1
1
0
0
0
-4.5
1
1
0
0
1
-3.0
1
1
0
1
0
-1.5
1
1
0
1
1
0.0
1
1
1
0
0
1.5
1
1
1
0
1
3.0
1
1
1
1
0
4.5
1
1
1
1
1
6.0
Table 5. Mixer and Output Mode
Mode
CD3
CD2
CD1
CD0
Loudspeaker L
Loudspeaker R
Headphone L
Headphone R
0
0
0
0
0
SD
SD
SD
SD
1
0
0
0
1
2
0
0
1
0
2(GM x M)
2(GM x M)
MUTE
MUTE
3
0
0
1
1
2(GM x M)
2(GM x M)
(GM x M)
(GM x M)
4
0
1
0
0
SD
SD
(GM x M)
(GM x M)
5
0
1
0
1
6
0
1
1
0
7
0
1
1
1
2(GL x L)
2(GR x R)
MUTE
MUTE
8
1
0
0
0
2(GL x L)
2(GR x R)
(GL x L)
(GR x R)
9
1
0
0
1
SD
SD
(GL x L)
(GR x R)
10
1
0
1
0
RESERVED
11
1
0
1
1
RESERVED
12
1
1
0
0
2(GL x L) + 2(GM
x M)
2(GRx R) + 2(GM
x M)
MUTE
MUTE
13
1
1
0
1
2(GL x L) + 2(GM
x M)
2(GR x R) + 2(GM
x M)
(GL x L) +
(GM x M)
(GR x R) +
(GM x M)
14
1
1
1
0
SD
SD
(GL x L) +
(GM x M)
(GR x R) +
(GM x M)
15
1
1
1
1
RESERVED
RESERVED
RESERVED
RESERVED
M - MIN Input Level
L - LIN Input Level
R - RIN Input Level
GM - Mono Volume Control Gain
GL - Left Stereo Volume Control Gain
GR - Right Stereo Volume Control Gain
SD - Shutdown
MUTE - Mute
Table 6. Texas Instruments 3D Enhancement
LD5
RD5
16
0
Loudspeaker Texas Instruments 3D Off
1
Loudspeaker Texas Instruments 3D On
0
Headphone Texas Instruments 3D Off
1
Headphone Texas Instruments 3D On
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM4844
LM4844
www.ti.com
SNAS320D – JUNE 2005 – REVISED APRIL 2013
Table 7. Wake-up Time Select
CD5
0
Fast Wake-up Setting
1
Slow Wake-up Setting
I2C COMPATIBLE INTERFACE
The LM4844 uses a serial bus, which conforms to the I2C protocol, to control the chip's functions with two wires:
clock (SCL) and data (SDA). The clock line is uni-directional. The data line is bi-directional (open-collector). The
maximum clock frequency specified by the I2C standard is 400kHz. In this discussion, the master is the
controlling microcontroller and the slave is the LM4844.
The I2C address for the LM4844 is determined using the ADR pin. The LM4844's two possible I2C chip
addresses are of the form 111110X10 (binary), where X1 = 0, if ADR is logic low; and X1 = 1, if ADR is logic high.
If the I2C interface is used to address a number of chips in a system, the LM4844's chip address can be changed
to avoid any possible address conflicts.
The bus format for the I2C interface is shown in Figure 31. The bus format diagram is broken up into six major
sections:
The "start" signal is generated by lowering the data signal while the clock signal is high. The start signal will alert
all devices attached to the I2C bus to check the incoming address against their own address.
The 8-bit chip address is sent next, most significant bit first. The data is latched in on the rising edge of the clock.
Each address bit must be stable while the clock level is high.
After the last bit of the address bit is sent, the master releases the data line high (through a pull-up resistor).
Then the master sends an acknowledge clock pulse. If the LM4844 has received the address correctly, then it
holds the data line low during the clock pulse. If the data line is not held low during the acknowledge clock pulse,
then the master should abort the rest of the data transfer to the LM4844.
The 8 bits of data are sent next, most significant bit first. Each data bit should be valid while the clock level is
stable high.
After the data byte is sent, the master must check for another acknowledge to see if the LM4844 received the
data.
If the master has more data bytes to send to the LM4844, then the master can repeat the previous two steps
until all data bytes have been sent.
The "stop" signal ends the transfer. To signal "stop", the data signal goes high while the clock signal is high. The
data line should be held high when not in use.
I2C INTERFACE POWER SUPPLY PIN (I2CVDD)
The LM4844's I2C interface is powered up through the I2CVDD pin. The LM4844's I2C interface operates at a
voltage level set by the I2CVDD pin which can be set independent to that of the main power supply pin VDD. This
is ideal whenever logic levels for the I2C interface are dictated by a microcontroller or microprocessor that is
operating at a lower supply voltage than the main battery of a portable system.
TEXAS INSTRUMENTS 3D ENHANCEMENT
The LM4844 features a 3D audio enhancement effect that widens the perceived soundstage from a stereo audio
signal. The 3D audio enhancement improves the apparent stereo channel separation whenever the left and right
speakers are too close to one another, due to system size constraints or equipment limitations.
An external RC network, shown in Figure 1, is required to enable the 3D effect. There are separate RC networks
for both the stereo loudspeaker outputs as well as the stereo headphone outputs, so the 3D effect can be set
independently for each set of stereo outputs.
The amount of the 3D effect is set by the R3D resistor. Decreasing the value of R3D will increase the 3D effect.
The C3D capacitor sets the low cutoff frequency of the 3D effect. Increasing the value of C3D will decrease the
low cutoff frequency at which the 3D effect starts to occur, as shown by Equation 1.
f3D(-3dB) = 1 / 2π(R3D)(C3D)
(1)
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM4844
17
LM4844
SNAS320D – JUNE 2005 – REVISED APRIL 2013
www.ti.com
Activating the 3D effect will cause an increase in gain by a multiplication factor of (1 + 20kΩ/R3D). Setting R3D to
20kΩ will result in a gain increase by a multiplication factor of (1+20kΩ/20kΩ) = 2 or 6dB whenever the 3D effect
is activated. The volume control can be programmed through the I2C compatible interface to compensate for the
extra 6dB increase in gain. For example, if the stereo volume control is set at 0dB (11011 from Table 4) before
the 3D effect is activated, the volume control should be programmed to –6dB (10111 from Table 4) immediately
after the 3D effect has been activated. Setting R3D = 20kΩ and C3D = 0.22μF allows the LM4844 to produce a
pronounced 3D effect with a minimal increase in output noise.
OUTPUT CAPACITOR-LESS (OCL) OPERATION AND LAYOUT TECHNIQUES FOR OPTIMUM CROSSTALK
The LM4844’s OCL headphone architecture eliminates output coupling capacitors. Unless the headphone is in
shutdown, the OCL output will be at a bias voltage of ½VDD, which is applied to the stereo headphone jack’s
sleeve. This voltage matches the bias voltage present on LHP and RHP outputs that drive the headphones. The
headphones operate in a manner similar to a bridge-tied load (BTL). Because the same DC voltage is applied to
both headphone speaker terminals there is no net DC current flow through the speaker. AC current flows through
a headphone speaker as an audio signal’s output amplitude increases on the speaker’s terminal.
The headphone jack’s sleeve is not connected to circuit ground when used in OCL mode. Using the headphone
output jack as a line-level output will place the LM4844’s ½VDD bias voltage on a plug’s sleeve connection.
Since the LHP and RHP outputs of the LM4844 share the OCL output as a reference, certain layout techniques
should be used in order to achieve optimum crosstalk performance. The crosstalk will depend on the parasitic
resistance of the trace connecting the LM4844 OCL output to the headphone jack sleeve and on the load
resistance value. Since the load resistance is often predetermined, it is advisable to use a trace that is as short
and as wide as possible. Reasonable application of this layout technique will result in crosstalk values of 60dB,
as specified in the electrical characteristics table.
BRIDGE CONFIGURATION EXPLANATION
The LM4844 consists of two sets of bridged-tied amplifier pairs that drive the left loudspeaker (LLS) and the right
loudspeaker (RLS). For this discussion, only the LLS bridge-tied amplifier pair will be referred to. The LM4844
drives a load, such as a speaker, connected between outputs, LLS+ and LLS-. In the LLS amplifier block, the
output of the amplifier that drives LLS- serves as the input to the unity gain inverting amplifier that drives LLS+.
This results in both amplifiers producing signals identical in magnitude, but 180° out of phase. Taking advantage
of this phase difference, a load is placed between LLS- and LLS+ and driven differentially (commonly referred to
as 'bridge mode'). This results in a differential or BTL gain of:
AVD = 2(Rf / Ri) = 2
(2)
Both the feedback resistor, Rf, and the input resistor, Ri, are internally set.
Bridge mode amplifiers are different from single-ended amplifiers that drive loads connected between a single
amplifier's output and ground. For a given supply voltage, bridge mode has a distinct advantage over the singleended configuration: its differential output doubles the voltage swing across the load. Theoretically, this produces
four times the output power when compared to a single-ended amplifier under the same conditions. This increase
in attainable output power assumes that the amplifier is not current limited and that the output signal is not
clipped.
Another advantage of the differential bridge output is no net DC voltage across the load. This is accomplished by
biasing LLS- and LLS+ outputs at half-supply. This eliminates the coupling capacitor that single supply, singleended amplifiers require. Eliminating an output coupling capacitor in a typical single-ended configuration forces a
single-supply amplifier's half-supply bias voltage across the load. This increases internal IC power dissipation
and may permanently damage loads such as speakers.
POWER DISSIPATION
Power dissipation is a major concern when designing a successful single-ended or bridged amplifier.
A direct consequence of the increased power delivered to the load by a bridge amplifier is higher internal power
dissipation. The LM4844 has 2 sets of bridged-tied amplifier pairs driving LLS and RLS. The maximum internal
power dissipation operating in the bridge mode is twice that of a single-ended amplifier. From Equation 3 and
Equation 4, assuming a 5V power supply and an 8Ω load, the maximum power dissipation for LLS and RLS is
634mW per channel.
PDMAX-LLS = 4(VDD)2/ (2π2 RL): Bridged
18
(3)
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM4844
LM4844
www.ti.com
SNAS320D – JUNE 2005 – REVISED APRIL 2013
PDMAX-RLS = 4(VDD)2/ (2π2 RL): Bridged
(4)
The LM4844 also has a pair of single-ended amplifiers driving LHP and RHP. The maximum internal power
dissipation for ROUT and LOUT is given by Equation 5 and Equation 6. FromEquation 5 and Equation 6,
assuming a 5V power supply and a 32Ω load, the maximum power dissipation for LOUT and ROUT is 40mW per
channel.
PDMAX-LHP = (VDD)2 / (2π2 RL): Single-ended
(5)
PDMAX-RHP = (VDD)2 / (2π2 RL): Single-ended
(6)
The maximum internal power dissipation of the LM4844 occurs during output modes 3, 8, and 13 when both
loudspeaker and headphone amplifiers are simultaneously on; and is given by Equation 7.
PDMAX-TOTAL = PDMAX-LLS + PDMAX-RLS + PDMAX-LHP + PDMAX-RHP
(7)
The maximum power dissipation point given by Equation 7 must not exceed the power dissipation given by
Equation 8:
PDMAX' = (TJMAX - TA) / θJA
(8)
The LM4844's TJMAX = 150°C. In the TL package, the LM4844's θJA is 62°C/W. At any given ambient
temperature TA, use Equation 8 to find the maximum internal power dissipation supported by the IC packaging.
Rearranging Equation 8 and substituting PDMAX-TOTAL for PDMAX' results in Equation 9. This equation gives the
maximum ambient temperature that still allows maximum stereo power dissipation without violating the LM4844's
maximum junction temperature.
TA = TJMAX - PDMAX-TOTAL θJA
(9)
For a typical application with a 5V power supply, stereo 8Ω loudspeaker load, and the stereo 32Ω headphone
load, the maximum ambient temperature that allows maximum stereo power dissipation without exceeding the
maximum junction temperature is approximately 100°C for the TL package.
TJMAX = PDMAX-TOTAL θJA + TA
(10)
Equation 10 gives the maximum junction temperature TJMAX. If the result violates the LM4844's 150°C, reduce
the maximum junction temperature by reducing the power supply voltage or increasing the load resistance.
Further allowance should be made for increased ambient temperatures.
The above examples assume that a device is a surface mount part operating around the maximum power
dissipation point. Since internal power dissipation is a function of output power, higher ambient temperatures are
allowed as output power or duty cycle decreases. If the result of Equation 7 is greater than that of Equation 8,
then decrease the supply voltage, increase the load impedance, or reduce the ambient temperature. If these
measures are insufficient, a heat sink can be added to reduce θJA. The heat sink can be created using additional
copper area around the package, with connections to the ground pin(s), supply pin and amplifier output pins.
External, solder attached SMT heatsinks such as the Thermalloy 7106D can also improve power dissipation.
When adding a heat sink, the θJA is the sum of θJC, θCS, and θSA. (θJC is the junction-to-case thermal impedance,
θCS is the case-to-sink thermal impedance, and θSA is the sink-to-ambient thermal impedance.) Refer to the
Typical Performance Characteristics curves for power dissipation information at lower output power levels.
POWER SUPPLY BYPASSING
As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply
rejection. Applications that employ a 5V regulator typically use a 10µF in parallel with a 0.1µF filter capacitors to
stabilize the regulator's output, reduce noise on the supply line, and improve the supply's transient response.
However, their presence does not eliminate the need for a local 1.0µF tantalum bypass capacitance connected
between the LM4844's supply pins and ground. Keep the length of leads and traces that connect capacitors
between the LM4844's power supply pin and ground as short as possible.
SELECTING EXTERNAL COMPONENTS
Input Capacitor Value Selection
Amplifying the lowest audio frequencies requires a high value input coupling capacitor (Ci in Figure 1). In many
cases, however, the speakers used in portable systems, whether internal or external, have little ability to
reproduce signals below 50Hz. Applications using speakers with this limited frequency response reap little
improvement; by using a large input capacitor.
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM4844
19
LM4844
SNAS320D – JUNE 2005 – REVISED APRIL 2013
www.ti.com
The internal input resistor (Ri) and the input capacitor (Ci) produce a high pass filter cutoff frequency that is found
using Equation 11.
fc = 1 / (2πRiCi)
(11)
As an example when using a speaker with a low frequency limit of 50Hz and Ri = 20kΩ, Ci, using Equation 11 is
0.19µF. The 0.22µF Ci shown in Figure 33 allows the LM4844 to drive high efficiency, full range speaker whose
response extends below 40Hz.
Bypass Capacitor Value Selection
Besides minimizing the input capacitor size, careful consideration should be paid to value of CB, the capacitor
connected to the BYPASS pin. Since CB determines how fast the LM4844 settles to quiescent operation, its
value is critical when minimizing turn-on pops. The slower the LM4844's outputs ramp to their quiescent DC
voltage (nominally VDD/2), the smaller the turn-on pop. Choosing CB equal to 2.2µF along with a small value of Ci
(in the range of 0.1µF to 0.39µF), produces a click-less and pop-less shutdown function. As discussed above,
choosing Ci no larger than necessary for the desired bandwidth helps minimize clicks and pops. CB's value
should be in the range of 5 times to 10 times the value of Ci. This ensures that output transients are eliminated
when the LM4844 transitions in and out of shutdown mode. Connecting a 2.2µF capacitor, CB, between the
BYPASS pin and ground improves the internal bias voltage's stability and improves the amplifier's PSRR. The
PSRR improvements increase as the bypass pin capacitor value increases. However, increasing the value of CB
will increase wake-up time. The selection of bypass capacitor value, CB, depends on desired PSRR
requirements, click and pop performance, wake-up time, system cost, and size constraints.
C3DHP
VDD
P1
C3DLS
Ci1
MIN
+
0.22 PF
Ci2
Audio Input
4.7 k:
0.22 PF
4.7 k:
RHP3D
VDD
LLS3D
1 PF
Audio Input
100
k:
R3DLS
0.22 PF
LHP3D
+
RLS3D
CS
P2
100 k:
R3DHP
LLS+
Mono Input
-34.5 dB to +12 dB
8:
LLS-
LIN
+
0.22 PF
Left Stereo Input
-40.5 dB to +6 dB
RLS+
8:
Ci3
Audio Input
RIN
+
0.22 PF
BYPASS
+
National
3D
Right Stereo Input
-40.5 dB to +6 dB
RLS-
Mixer
&
Mode Select
OCL
Bias
Click / Pop Supression
RHP
CB
VDD
I2CVDD
2.2 PF
LHP
I2CVDD
J2
I2C
Interface
SCL
SDA
extVDD
I2C Interface
6 Pin Header
ADR
J1
RPU
VDD
GND
100 k:
Figure 33. Reference Design Board Schematic
20
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM4844
LM4844
www.ti.com
SNAS320D – JUNE 2005 – REVISED APRIL 2013
Demonstration Board Layout
Figure 34. Recommended YZR PCB Layout:
Silkscreen Layer
Figure 35. Recommended YZR PCB Layout:
Top Layer
Figure 36. Recommended YZR PCB Layout:
Mid Layer 1
Figure 37. Recommended YZR PCB Layout:
Mid Layer 2
Figure 38. Recommended YZR PCB Layout:
Bottom Layer
Submit Documentation Feedback
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM4844
21
LM4844
SNAS320D – JUNE 2005 – REVISED APRIL 2013
www.ti.com
Revision History
22
Rev
Date
1.1
06/01/06
Initial WEB.
1.2
07/20/07
Edited the Control Interface Electrical
Characteristics tables.
1.3
08/07/07
Changed the I2CVdd from 1.8V into 1.7V
(under the Operating Ratings).
1.4
08/23/07
Fixed one place of typo.
D
04/05/13
Changed layout of National Data Sheet to TI
format
Submit Documentation Feedback
Description
Copyright © 2005–2013, Texas Instruments Incorporated
Product Folder Links: LM4844
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LM4844TL/NOPB
ACTIVE
DSBGA
YZR
30
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
GF3
LM4844TLX/NOPB
ACTIVE
DSBGA
YZR
30
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
GF3
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
LM4844TL/NOPB
DSBGA
YZR
30
250
178.0
8.4
LM4844TLX/NOPB
DSBGA
YZR
30
3000
178.0
8.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2.74
3.15
0.76
4.0
8.0
Q1
2.74
3.15
0.76
4.0
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM4844TL/NOPB
DSBGA
YZR
LM4844TLX/NOPB
DSBGA
YZR
30
250
210.0
185.0
35.0
30
3000
210.0
185.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
YZR0030xxx
0.600±0.075
D
E
TLA30XXX (Rev C)
D: Max = 2.99 mm, Min = 2.929 mm
E: Max = 2.581 mm, Min = 2.52 mm
4215057/A
NOTES:
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
www.ti.com
12/12
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertisement