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US 2007012776 1A1
(19) United States
(12) Patent Application Publication (10) Pub. No.: US 2007/0127761 A1
(43) Pub. Date:
Poulsen
(54)
(76)
MICROPHONE COMPRISING INTEGRAL
MULTI-LEVEL QUANTIZER AND
SINGLE-BIT CONVERSION MEANS
Inventor:
Related US. Application Data
(60)
Provisional application No. 60/525,039, ?led on Nov.
24, 2003.
Jens Kristian Poulsen, Hedehusene
(DK)
Correspondence Address:
Jun. 7, 2007
Publication Classi?cation
(51) Int. Cl.
JENKENS & GILCHRIST, P.C.
H04R
225 WEST WASHINGTON
(52)
9/08
(2006.01)
US. Cl. ............................................................ .. 381/355
SUITE 2600
(21)
CHICAGO, IL 60606 (US)
(57)
Appl NO .
The invention relates to a digital microphone comprising an
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ABSTRACT
integral analog-to-digital converter based on a multi-level
(22)
PCT Filed;
Oct 8’ 2004
quantiZer in cascade With a digital signal converter Which is
(86)
PCT NO_;
PCT/DK04/00680
phones in accordance With the invention are particularly
Well adapted for use in mobile terminals and compact
portable communication equipment such as mobile or cel
May 23, 2006
lular phones, headsets, hearing prostheses etc.
adapted to provide a single-bit output signal. Digital micro
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Jun. 7, 2007
US 2007/0127761 A1
MICROPHONE COMPRISING INTEGRAL
MULTI-LEVEL QUANTIZER AND SINGLE-BIT
CONVERSION MEANS
[0008] a digital signal converter adapted to convert the
multi-bit samples into a single-bit output signal, and an
externally accessible terminal adapted to provide the
single-bit output signal.
FIELD OF THE INVENTION
[0001] The invention relates to a digital microphone com
prising an integral analog-to-digital converter based on a
multi-level quantizer in cascade With a digital signal con
verter Which is adapted to provide a single-bit output signal.
Digital microphones in accordance With the invention are
particularly Well adapted for use in mobile terminals and
compact portable communication equipment such as mobile
or cellular phones, headsets, hearing prostheses etc.
BACKGROUND OF THE INVENTION
[0002] Microphones With integral analog-to-digital con
verters, or digital microphones, are knoWn in the art. EP 1
052880, WO 02/062101, US. Pat. No. 5,769,848 and GB
2319922 discloses several digital microphones for utiliza
tion in diverse applications such as professional audio,
hearing instruments and mobile phones. WO 02/062101
discloses a microphone assembly comprising an electro
acoustical transducer coupled to a preampli?er. An ampli?ed
signal is coupled to an analog-to-digital converter Which in
one embodiment comprises a single-bit delta-sigma modu
lator. A disclosed embodiment of the microphone assembly
comprises a formatting circuit that converts signal samples
[0009] In the present description and claims, the term
“multi-level quantizer” designates a signal quantizer that
comprises more than 2 quantization levels such as 3 or 5 or
7 discrete quantization levels.
[0010] A signi?cant advantage of the invention is provided
by the multi-level quantizer operatively coupled to the
digital signal converter Which converts the multi-bit samples
into a single-bit output signal. The present invention there
fore provides a digital microphone Which bene?ts from the
multi-level quantizer to provide a digitized version of the
transducer signal of improved quality, but still maintains a
simple and versatile unformatted data output Which previ
ously have been a unique feature of analog-to-digital con
verters based on single bit quantizers. By virtue of the
unformatted single-bit output signal, microprocessors or
signal processors are readily interfaced to digital micro
phones in accordance With the present invention Without any
need to contain dedicated audio data interface circuitry
compatible With several digital audio data protocols.
[0011] Finally, designers of products that incorporate digi
tal microphones in accordance With the invention enjoy a
considerable ?exibility in choosing an optimum perfor
generated by the delta-sigma modulator into digital signals
mance versus complexity trade-off in for example decima
in accordance With a standardized digital audio transmission
tion ?lter design.
protocol such as S/PDIF, I2S or AES/EBU.
[0003] US. Pat. No. 6,326,912 discloses an analog-to
digital converter comprising a front-end multi-bit delta
sigma modulator coupled directly, or indirectly, to a back
end single-bit delta-sigma modulator for professional audio
applications such as Super Audio Compact Discs that are
based on a bit stream format or DVD Audio Discs that are
based on a 24-bit PCM format.
[0004] While single-bit sigma-delta modulators have been
successfully incorporated in a commercially available min
iature microphone for hearing aid applications, there is a
need for digital microphones employing integral analog-to
digital converters of improved performance. The improved
digital microphones could advantageously be backWard
compatible With existing single-bit output devices.
[0012] The multi-level quantizer preferably comprises
betWeen 3 and 64 quantization levels such as betWeen 5 and
16 quantization levels to provide multi-bit samples repre
sentative thereof. The quantization levels may be selected so
as to provide linear or equidistant amplitude spacing, or
logarithmic amplitude spacing, or any other desired ampli
tude spacing. The multi-level quantizer provides several
bene?ts in comparison With a single-bit quantizer. These
improvements include, but are not limited to, loWer poWer
consumption for a given signal/noise ratio, improved signal/
noise ratio for a given sampling frequency and improved
suppression of annoying tonal noise components in the
multi-bit samples or quantized signal.
[0013]
For a desired or target signal-to-noise ratio or
dynamic range of the quantized signal, it is possible to
Improved performance analog-to-digital converters can be
obtained by replacing conventional single-bit, or dual-level,
reduce a clock frequency driving the analog-to-digital con
verter. This latter advantage is particularly bene?cial When
quantizers With a multi-level quantizer in sigma-delta con
the digital microphone comprises an external input clock
terminal for receipt of an externally generated clock signal
verter architectures.
DESCRIPTION OF THE INVENTION
such as a clock signal generated by an associated micropro
cessor or digital signal processor. In this latter embodiment
In a ?rst aspect, the invention relates to a digital
of the invention, poWer losses associated With driving exter
microphone comprising a microphone housing having a
sound inlet and comprising
nal parasitic capacitances on a clock line are reduced pro
[0005]
[0006] a transducer element comprising a displaceable
diaphragm and adapted to generate a transducer signal
representative of sound received through the sound
inlet,
portionally With the frequency of the externally generated
clock signal.
[0014] Preferably, the digital microphone comprises a
preampli?er inserted betWeen the transducer element and the
analog-to-digital converter. The input capacitance of the
multi-level quantizer operatively coupled to the trans
preampli?er may advantageously be selected or designed to
be suitable for coupling the preampli?er input to a miniature
[0007]
an analog-to-digital converter comprising a
ducer means to convert the transducer signal into
transducer element, said input capacitance being smaller
multi-bit samples representative of the transducer sig
than 10 pF or smaller than 5 pF or 2 pF or 1 pF, or even more
nal,
preferably less than 0.5 pF. This latter range of input
Jun. 7, 2007
US 2007/0127761 A1
capacitance values Will optimize coupling of the preampli
?er to miniature electret or condenser based transducer
therefore operative Without a separate poWer supply terminal
or pad on the microphone housing. The lack of the separate
elements as commonly used in miniature microphones for
hearing aid or mobile terminal applications.
poWer supply terminal is particularly advantageous for min
iature loW-poWer digital microphones such as digital hearing
[0015] A DC blocking ?lter, such as a band pass or high
pass ?lter may advantageously be operatively coupled to a
preampli?er output providing an ampli?ed transducer signal
so as to prevent DC bias point ?uctuations and/or loW
frequency signals at the preampli?er output are conveyed to
the analog-to-digital converter.
aid microphones that may have a nominal current consump
tion of less than 250 [LA or less than 150 [LA at 1.0 Volt
supply voltage. In a preferred embodiment of the invention,
the digital microphone is adapted to operate on a supply
voltage loWer than 2.9 V or loWer than 1.8 Volt such as loWer
than 1.5 Volt or loWer than 1.2 Volt.
[0021] According to a preferred embodiment of the inven
[0016] The digital microphone may comprise a dynamic
tion, interpolation means or an interpolator is inserted
transducer element or condenser transducer element. The
betWeen the analog-to-digital converter and the digital signal
dynamic transducer element may comprise a diaphragm
converter to interface betWeen different sample rates of the
With an attached voice coil suspended in a permanent
magnetic ?eld. The condenser transducer element may com
multi-bit samples and the single-bit output signal. The
prise a pair of closely spaced and suitably biased plates, such
and be adapted to raise the sample rate With a factor of 2-32.
as a polymer diaphragm having an electrically conductive
layer disposed thereon and an adjacently positioned perfo
rated backplate.
[0017]
Alternatively, the transducer means may be formed
in a semiconductor substrate such as silicon or any other
suitable material using Micro Electro Mechanical Systems
(MEMS) technologies. In the above-mentioned embodi
ments of the invention, the preampli?er, the analog-to
digital converter, the digital signal converter and, optionally,
clock generating means may advantageously be formed on
a common integrated circuit substrate. The preampli?er may
be electrically coupled to the transducer means or element
by utiliZation of ?ip-chip or Wire-bonding techniques.
[0018] The analog-to-digital converter preferably com
prises an oversampled delta-sigma modulator adapted to
sample the transducer signal or preampli?er signal With a
clock signal frequency betWeen 64 kHZ and 512 kHZ. For a
desired or target audio bandWidth of 8 kHZ, this clock signal
frequency span corresponds to oversampling ratios of 4 and
32, respectively.
[0019]
According to one embodiment of the invention, the
digital microphone comprises an integral clock generator
interpolator may advantageously comprise a loW pass ?lter
[0022] The multi-bit samples provided by the analog-to
digital converter may be represented by a tWo’s complement
data format and conveyed to an interpolator or decimator in
that format. In contrast, in accordance With a particularly
advantageous embodiment of the invention, the multi-bit
samples provided by the analog-to-digital converter are
represented by a set of corresponding symbols Wherein each
symbol comprises a number of one signs proportional With
a magnitude of the corresponding multi-bit sample. This
symbol representation is particularly advantageous in con
nection With three and ?ve level modulators since an effi
cient and direct mapping betWeen multi-bit samples and the
single bit output is possible, but generally a multi-level
quantiZer comprising N discrete quantiZation levels may
utiliZe corresponding symbols that comprises N-l bits to
represent each of the N levels With a unique symbol.
[0023] According to a second aspect of the invention, a
portable communication device comprises a digital micro
phone according to the present invention. The portable
communication device may be poWered by disposable or
rechargeable batteries and optimiZed for loW-poWer opera
tion. The portable communication device may comprise a
mobile terminal, a cellular phone, a headset, a hearing
adapted to generate a clock signal Which is operatively
coupled to the analog-to-digital converter to provide a
prosthesis or instrument etc.
sampling clock for the multi-level quantiZer. An advanta
monolithic integrated circuit comprises a preampli?er
adapted to provide an ampli?ed transducer signal and com
geous feature of this embodiment is a possibility to provide
a digital microphone With no requirement for an externally
accessible clock input terminal. The sampling clock signal
of the analog-to-digital converter and, optionally, internal
logic circuitry may be operated in by the internally gener
ated clock signal or clock signal derived there from.
[0020] Alternatively, the housing of the digital micro
phone may comprise a second externally accessible terminal
for receipt of an external clock signal. The external clock
signal is operatively coupled to the analog-to-digital con
verter to directly or indirectly control the sampling of the
transducer signal. In an advantageous version of this latter
embodiment of the digital microphone, the external clock
signal is operatively coupled to DC voltage generating
means disposed Within the microphone housing and used to
derive poWer for an internal DC supply voltage. The internal
DC supply voltage may poWer at least the analog-to-digital
[0024]
According to a third aspect of the invention, a
prising an input section couplable to a miniature electret or
condenser transducer element and an analog-to-digital con
verter comprising a multilevel-quantiZer operatively
coupled to the ampli?ed transducer signal and adapted to
convert the ampli?ed transducer signal into multi-bit
samples representative of the ampli?ed transducer signal
and a digital signal converter adapted to convert the multi
bit samples into a single-bit output signal. An integrated
circuit pad is ?nally adapted to provide the single-bit output
signal.
[0025]
The monolithic integrated circuit may be fabricated
in a standard CMOS process such as 0.5 um or 0.35 pm
CMOS. The input impedance of the preampli?er of the
monolithic circuit is preferably substantially capacitive and
converter and, optionally, all circuitry Within the digital
corresponding to a capacitance less than 2 pF, or less than 1
pF, or even more preferably less than 0.5 pF to support
interfacing or coupling to a miniature electret element
microphone such as a preampli?er, interpolation and deci
mation ?lters. This latter embodiment of the invention is
Without introducing unacceptable signal losses by source
loading effects.
Jun. 7, 2007
US 2007/0127761 A1
BRIEF DESCRIPTION OF THE DRAWINGS
[0026] FIG. 1 is a block diagram of a digital microphone
assembly according to a preferred embodiment of the
present invention;
[0027] FIG. 2 is a block diagram of a ?rst digital signal
converter for use in the digital microphone assembly illus
trated in FIG. 1,
[0028]
FIG. 3 is a block diagram of a second alternative
digital signal converter for use in the digital microphone
assembly illustrated in FIG. 1,
Wherein the embedded clock signal is derived from an
integral clock generator means disposed on the integrated
circuit.
[0035] The electret transducer element 1 comprises a
displaceable diaphragm adapted to receive an acoustical
signal through the sound inlet 3 and generate a transducer
signal representative of the acoustical signal. The transducer
signal is conveyed to a loW-poWer and loW-noise CMOS
based preampli?er 20 adapted to amplify and buffer the
transducer signal and provide an ampli?ed transducer signal
to the analog multilevel converter 40 or sigma-delta (SD)
modulator, Which comprises a multilevel-quantiZer so as to
[0029] FIG. 4 is a block diagram of a three-level sigma
delta based AD converter;
convert the ampli?ed transducer signal into a multi-bit
[0030]
to the present embodiment of the invention, the multi-level
FIG. 5 is a block diagram of a ?rst interface
processing circuitry betWeen the three-level sigma-delta
based AD converter and the digital signal converter,
[0031]
samples representative of the transducer signal. According
quantiZer comprises three discrete levels represented as +1,
0 and —l. Other embodiments may comprise a larger number
of discrete quantization levels such as 5 levels or 8 levels or
FIG. 6 is a block diagram of a second interface
16-64 levels depending on factors such as performance,
processing circuitry betWeen the three-level sigma-delta
tolerable complexity and siZe of the integrated circuit itself.
based AD converter and the digital signal converter.
DETAILED DESCRIPTION OF A PREFERRED
EMBODIMENT
[0032]
FIG. 1 shoWs a preferred embodiment of a digital
microphone according to the invention. The digital micro
[0036] The multi-bit samples provided by SD modulator
40 are operatively coupled to the digital signal converter 50
adapted to convert the multi-level digital signal into a
single-bit output signal. Finally, the single-bit output signal
is made accessible to an external programmable processor
such as a signal processor or microprocessor through an
phone comprises a housing or casing 2 With a sound inlet
externally accessible terminal 60 placed on the ceramic
port 3. An electret transducer element 1 is electrically
coupled to an integrated circuit and both arranged inside the
hybrid substrate and electrically connected to a correspond
ing terminal of the integrated circuit. The integrated circuit
of the present embodiment of the invention is preferably
manufactured by 0.35 um CMOS that provides loW-noise
housing 2. The integrated circuit comprises preampli?er 20,
high pass ?lter 30, analog multilevel converter 40 and a
digital signal converter 50. The integrated circuit is mounted
on, and supported by, a ceramic substrate carrier (not shoWn)
While electrical connectivity betWeen devices is established
by Wire-bonding techniques that are Well-knoWn in the art.
[0033] The present embodiment of the invention is imple
mented as a sub-miniature electret microphone capable of
operating on supply voltages doWn to 1.0 Volt and With a
and high performance analog PMOS transistors for appli
cation in the preampli?er 20 combined With high-density
and loW poWer digital logic circuitry for application in the
digital logic circuitry of digital signal converter 50. HoW
ever, other CMOS processes having larger or smaller feature
siZes as Well as BiCMOS process could alternatively be
utiliZed.
typical poWer consumption of about 100-200 uW. The
present embodiment is therefore particularly Well adapted
for hearing instrument applications Where loW-voltage and
embodiment of the digital signal converter 50 illustrating
loW-poWer requirements are essential to conserve battery
detail. The digital signal converter 50 is compatible With an
analog multilevel converter or delta-sigma multi-level quan
poWer. The digital microphone additionally comprises a set
of externally accessible terminals in form of an output signal
terminal 60, a clock input terminal 61, a poWer supply
terminal 62 and a ground terminal 59. The clock input
[0037]
FIG. 2 is a detailed block diagram of a ?rst
individual parts or components of the converter 50 in more
tiZer in Which multi-bit samples are represented in a con
ventional tWo’s complement format.
[0038] A forWard signal path comprises three cascaded
discrete tWo’s complement integrators 51a, 51b, 510 located
terminal 61 is adapted for receipt of an externally generated
clock signal Which controls timing and clock rate of the
single-bit output signal on output signal terminal 60 to
provide a simple and synchronous interface betWeen the
digital microphone and the external processor.
tiZes incoming 16 bit digital signal samples into a bi-level,
or single-bit, output signal. The input signal to the converter
[0034] Alternatively, in respect of applications Wherein a
feedback loop extends around the forWard signal path and
key concern is to minimiZe the number of external terminals,
comprises a single-bit decision circuit or comparator 56 that
feeds a MSB value, or sign, of the single-bit output signal
the single-bit output signal may be transmitted asynchro
in front of single-bit quantiZer or comparator 55 that quan
50 is a 2 bit signal provided in tWo’s complement format. A
nously or synchronously to the external processor through a
single data line. The processor must include appropriate data
receipt and clock retrieval means. In an embodiment of the
back to three separate feedback loops With respective feed
back coef?cients, a0, a1, a2. These three separate feedback
invention Wherein the single-bit output signal is transmitted
synchronously to the external processor through a single
data line, the single-bit output signal or output data may
ming junctions or 16 bit adders 52-54 to provide error or
advantageously comprise an embedded or coded clock sig
nal such as a Manchester coded composite clock/data line
loops feed respective feedback signals into respective sum
noise shaping in the digital signal converter 50. The noise
shaping operates to move or transpose loW-frequency noise
components, introduced as a result of signal quantiZation of
the multi-bit input signal, to a high-frequency range above
Jun. 7, 2007
US 2007/0127761 A1
audibility. A feed-forWard loop With a predetermined feed
ous-time signal at the output of integrator 41b into a dual-bit
forWard coef?cient, b0, around the ?rst adder 51 may as
digital signal samples in tWo’s complement format. A feed
illustrated optionally be added to the digital signal converter
50 to improve its dynamic range and stability. Internal state
back loop around the SD modulator comprises a multilevel
variables or signals eg at summing nodes 52-54 are pref
multi-bit samples output signal back to three separate feed
back loops With respective feedback coef?cients, a0, a1 and
a2. These three separate feedback loops feed respective
feedback signals into respective summing junctions 42-44 to
provide error shaping in the SD modulator 40 and transpose
or push a substantial portion of quantiZation noise generated
by the three-level quantiZer 45 to a frequency range above
erably represented by respective 16 bit tWo’s complement
numbers.
[0039] FIG. 3 illustrates another embodiment of the digital
signal converter 50 based on direct symbol mapping. This
implementation of the digital signal converter 50 requires a
minimum of logic circuitry and therefore represents a very
attractive option for loW-poWer and/or loW cost applications
like hearing instruments and mobile phones. The operation
is based on a novel coding of the tWo bit samples {D0, D1}
provided in standard tWo’s complement format by the tri
level sigma-delta (SD) modulator 40 (FIG. 1).
[0040] In the present embodiment, quantization level +1 is
coded as symbol {11}, While level 0 is represented by
symbol {01}, and level —1 is ?nally represented by symbol
{00}. Accordingly, a symbol associated With a particular
quantization level directly represents the average signal
value of that quantiZation level by the coding mechanism of
the digital signal converter 50. This coding form makes it
possible to generate the single-bit output signal in a very
ef?cient manner by a collection of four D-type Flip Flops 21,
22, 25 and 26, a dual-input multiplexer 26 and XOR gate 27.
D-FF 25 is operative to halve a clock frequency provided on
the clock input 2511 wherein the clock frequency signal may
digital-to-analog converter 46 that feeds a value of the
audibility, i.e. above about 16 or 20 kHZ. An optional
feed-forWard loop With a predetermined feed-forWard coef
?cient, b0, around the ?rst integrator 41a has been added to
the SD modulator 40 as illustrated to improve its dynamic
range and stability.
[0048]
The present SD modulator 40 is preferably oper
ated With a sampling clock frequency of 1.024 MHZ While
the digital signal converter 50 is operated With a 2.048 MHZ
output data rate of the single-bit output signal. In the present
embodiment of the invention, an interpolator is inserted
betWeen the SD modulator 40 and the digital signal con
verter 50, in accordance With FIG. 2, to raise the sampling
rate of the multi-bit samples provided by the SD modulator
to a target rate of 2.048 MHZ required by the digital signal
converter 50.
[0049] As illustrated in FIG. 5 and FIG. 6 various types of
sample rate conversion may be provided in-betWeen the SD
have been derived from the external clock signal terminal 61
(FIG. 1). D-type FFs 21 and 22 operates on half the clock
modulator 40 and the digital signal converter 50. According
frequency of D-type PF 26 that generates the single bit
output signal or bit-stream and the Nyquist criterion is
exactly complied With by direct coding and conversion of
cascaded to provide ?exible sample rate conversion betWeen
the sample rate of signals provided by the SD modulator 40
and the sample rate of the output signal of digital signal
incoming multi-bit samples.
converter 50 Wherein a ratio betWeen the sample rates may
be an integer or fractional number such as 4, 8, 16, 32 or 1.5
or 32/44.1 or 16/44.1 etc. According to FIG. 6, the sample
[0041]
Clearly, a different coding of the symbols or multi
bit samples is possible Within the general inventive concept
such as representing level +1 by symbol {1111} or {111111}
and the other quantiZation levels in a corresponding manner.
Likewise, the symbols that represent +1 and —1 can both be
inverted and/or the 0 level coded “01} or “10}. LikeWise,
several ef?cient coding formats of quantiZation levels pro
vided by a ?ve-level SD modulator also exist, eg by using
to FIG. 5, an interpolator 55 and decimator 56 may be
rate conversion means may comprise a cascade of a deci
mator 65 and an interpolator 66. Inclusion of appropriate
sample rate conversion means may be advantageous in some
embodiments of the invention to interface a certain sample
rate of signals from the SD modulator 40 to a standardiZed
data output rate required by the digital signal converter 50.
a collection symbols that each comprises four bits to repre
sent the corresponding quantiZation level, such as beloW
mentioned exemplary format:
1. A digital microphone comprising:
[0042]
[0043]
[0044]
[0045]
[0046]
Level
Level
Level
Level
Level
+2 is represented by symbol {1111},
+1 is represented by symbol {1110},
0 is represented by symbol {1010},
—1 is represented by symbol {0001},
—2 is represented by symbol {0000}.
a microphone housing having a sound inlet and compris
[0047]
FIG. 4 is a detailed block diagram of the analog
an analog-to-digital converter comprising a multi-level
multi-level SD modulator 40 or SD modulator illustrating
individual components of the modulator 40. The ampli?ed
transducer signal is provided as an analog input signal to the
SD modulator, Which converts received input signals into a
multi-bit samples output representative of the transducer
signal. A cascade of three integrators, 41a-41c is located in
a forWard signal path of the SD modulator 40. An output of
a last integrator 410 is operatively coupled to a three-level
quantiZer 45 that quantiZes amplitude values of a continu
ing:
a transducer element comprising a displaceable dia
phragm and adapted to generate a transducer signal
representative of sound received through the sound
inlet,
quantiZer operatively coupled to the transducer element
to convert the transducer signal into multi-bit samples
representative of the transducer signal,
a digital signal converter adapted to convert the multi
bit samples into an unformatted single-bit output
signal, and
an externally accessible terminal adapted to provide the
unformatted single-bit output signal.
Jun. 7, 2007
US 2007/0127761 A1
2. A digital microphone according to claim 1, wherein the
analog-to digital converter comprises an oversampled delta
sigma modulator.
3. A digital microphone according to claim 1, comprising
an integral clock generator operatively coupled to the ana
log-to-digital converter and the digital signal converter.
4. A digital microphone according to claim 1, Wherein the
microphone housing comprises a second externally acces
sible terminal for receipt of an external clock signal.
5. A digital microphone according to claim 4, comprising
DC voltage generating means disposed Within the micro
phone housing and operatively coupled to the external clock
signal so as to derive a DC voltage supply for operating at
least the analog-to-digital converter.
6. A digital microphone according to claim 1, Wherein the
multi-level quantizer of the analog-to-digital converter com
prises betWeen 3 and 64 discrete quantization levels.
7. A digital microphone according to claim 1, Wherein the
multi-bit samples provided by the analog-to-digital con
verter are represented in tWo’s complement format.
13. Adigital microphone according to claim 1, comprising
an interpolator operatively coupled betWeen the multi-bit
samples provided by the analog-to-digital converter and the
digital signal converter.
14. Aportable communication device comprising a digital
microphone according to claim 1.
15. A monolithic integrated circuit for a miniature micro
phone, comprising
a preampli?er adapted to provide an ampli?ed transducer
signal and comprising an input section couplable to a
miniature electret or condenser transducer element,
an analog-to-digital converter comprising a multilevel
quantizer operatively coupled to the ampli?ed trans
ducer signal and adapted to convert the ampli?ed
transducer signal into multi-bit samples representative
of the ampli?ed transducer signal,
a digital signal converter adapted to convert the multi-bit
samples into an unformatted single-bit output signal,
and
8. A digital microphone according to claim 1, Wherein
multi-bit samples generated by the multi-level quantizer are
represented by a set of corresponding symbols, and Wherein
an integrated circuit pad adapted to provide the single-bit
each symbol comprises a number of one signs Which is
proportional With a magnitude of the corresponding multi
16. A monolithic integrated circuit according to claim 15,
bit sample.
9. A digital microphone according to claim 8, Wherein the
multi-level quantizer comprises 3 or 5 discrete quantization
levels.
10. A digital microphone according to claim 8, Wherein
the multi-level quantizer comprises N discrete quantization
levels and each corresponding symbol comprises N-1 bits;
N being an integer betWeen 3 and 17.
11. A digital microphone according to claim 9, Wherein
the digital signal converter comprises a delay circuit in
cascade With an integer ratio upsampler.
12. Adigital microphone according to claim 1, comprising
a preampli?er interposed betWeen the transducer element
and the analog-to-digital converter.
output signal.
Wherein multi-bit samples generated by the multi-level
quantizer are represented by a set of corresponding symbols,
and Wherein each symbol comprises a number of one signs
Which is proportional With a magnitude of the corresponding
multi-bit sample.
17. A digital microphone according to claim 15, Wherein
the analog-to-digital converter comprises an oversampled
delta-sigma modulator.
18. A monolithic integrated circuit according to claim 15,
Wherein the multi-level quantizer of the analog-to-digital
converter comprises 3 or 5 discrete quantization levels.
19. A digital microphone according to claim 1, Wherein
the digital signal converter is a sigma-delta signal converter.
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