MAX17244

EVALUATION KIT AVAILABLE

3.5V–36V, 2.5A, Synchronous Buck Converter

With 28µA Quiescent Current and Reduced EMI

General Description

The MAX17244 high-efficiency, synchronous step-down

DC-DC converter with integrated MOSFETs operates over a 3.5V to 36V input voltage range with 42V input transient protection. The device can operate in dropout condition by running at 98% duty cycle. This converter delivers up to 2.5A and generates fixed output voltages of

3.3V/5V, along with the ability to program the output voltage between 1V to 10V.

The MAX17244 uses a current-mode control architecture.

The device can operate in the pulse-width modulation

(PWM) or pulse-frequency modulation (PFM) control schemes. PWM operation provides constant frequency operation at all loads, and is useful in applications sensitive to switching frequency. PFM operation disables negative inductor current and additionally skips pulses at light loads for high efficiency. Under light-load applications, the external sync pin FSYNC logic input allows the device to operate either in PFM mode for reduced current consumption or fixed-frequency FPWM (forced-PWM) mode to eliminate frequency variation to minimize EMI.

Fixed-frequency FPWM mode is extremely useful for power supplies designed for RF transceivers where tight emission control is necessary.

This device is available in a compact 16-pin (5mm x 5mm)

TQFN package with exposed pad and 16-pin TSSOP.

-40°C to +85°C operation.

Applications

● Distributed Supply Regulation

● Wall Transformer Regulation

● General-Purpose Point-of-Load

Benefits and Features

● Eliminates External Components and Reduces

Total Cost

• Integrated High-Side and Low-Side Switch Enables

Synchronous Operation for High Efficiency and

Reduced Cost

• All-Ceramic Capacitor Solution Allows Ultra-

Compact Solution Size

• 220kHz to 2.2MHz Adjustable Frequency with

External Synchronization

• Power Good Output and High-Voltage EN Input

Simplify Power Sequencing

● Increases Design Flexibility

• 180° Out-of-Phase Clock Output at SYNCOUT

Enables Cascaded Power Supplies for Increased

Power Output

• Fixed Output Voltage with ±2% Accuracy (5V/3.3V) or Externally Resistor Adjustable (1V to 10V)

● Reduces Power Dissipation

• >90% Peak Efficiency

• PWM and PFM Operation Optimizes Conversion

Efficiency From Heavy to Light Loads

• Automatic LX Slew-Rate Adjustment for Optimum

Efficiency Across Operating Frequency Range

• Low 5μA (typ.) Shutdown Current

• Low 28μA (typ.) Quiescent Current

● Operates Reliably

• 42V Input Voltage Transient Protection

• Fixed 8ms Internal Software Start Reduces Input

Inrush Current

• Cycle-by-Cycle Current Limit, Thermal Shutdown with Automatic Recovery

• Reduced EMI Emission with Spread-Spectrum

Control

Ordering Information and

Typical Application Circuit

appears at end of data sheet.

19-8526; Rev 1; 3/17

MAX17244 3.5V–36V, 2.5A, Synchronous Buck Converter

With 28µA Quiescent Current and Reduced EMI

Typical Application Circuit

V

BAT

C

IN1

C

COMP1

1000pF

R

COMP

20kΩ

R

IN3

0Ω

C

IN3

4.7µF

C

IN2

4.7µF

C

COMP2

12pF

OSC SYNC PULSE

R

FOSC

12kΩ

SUP SUPSW

BST

EN

LX

FSYNC

COMP

MAX17244

OUT

FB

FOSC

C

BIAS

1µF

BIAS

PGND AGND

PGOOD

SYNCOUT

C

BST

0.1µF

V

OUT

V

BIAS

V

OUT

R

SYNCOUT

100Ω

D1

R

SNUB*

C

SNUB*

L1

2.2µH

V

OUT

5V AT 2.5A

C

OUT

22µF

V

BIAS

R

PGOOD

10kΩ

POWER-GOOD OUTPUT

180° OUT-OF-PHASE OUTPUT

*R

SNUB

V

BAT

= 1Ω and C

≥ 25V, V

OUT

SNUB

≤ 5V, f

= 220pF REQUIRED FOR THE FOLLOWING OPERATING CONDITIONS:

SW

≥ 1.8MHz, PWM MODE ENABLED www.maximintegrated.com

Maxim Integrated │

2

MAX17244 3.5V–36V, 2.5A, Synchronous Buck Converter

With 28µA Quiescent Current and Reduced EMI

Absolute Maximum Ratings

SUP, SUPSW, EN to PGND ..................................-0.3V to +42V

LX (Note 1) ............................................................-0.3V to +42V

SUP to SUPSW ....................................................-0.3V to +0.3V

BIAS to AGND .........................................................-0.3V to +6V

SYNCOUT, FOSC, COMP, FSYNC,

PGOOD, FB to AGND ........................-0.3V to (V

BIAS

+ 0.3V)

OUT to PGND .......................................................-0.3V to +12V

BST to LX (Note 1) ..................................................-0.3V to +6V

AGND to PGND ...................................................-0.3V to + 0.3V

LX Continuous RMS Current ...................................................3A

Output Short-Circuit Duration ....................................Continuous

Continuous Power Dissipation (T

A

= +70°C)*

TSSOP (derate 26.1mw/NC above +70°C) ............2088.8mW

TQFN (derate 28.6mw/°C above +70°C) ...............2285.7mW

Operating Temperature Range ........................... -40°C to +85°C

Junction Temperature ......................................................+150°C

Storage Temperature Range ............................ -65°C to +150°C

Lead Temperature (soldering, 10s) .................................+300°C

Soldering Temperature (reflow) .......................................+260°C

*As per JEDEC51 standard (multilayer board).

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Package Thermal Characteristics (Note 2)

TSSOP

Junction-to-Ambient Thermal Resistance (θ

Junction-to-Ambient Thermal Resistance (θ

JA

) .......38.3°C/W

JC

) ............3°C/W

TQFN

Junction-to-Ambient Thermal Resistance (θ

Junction-to-Ambient Thermal Resistance (θ

JA

) ..........35°C/W

JC

) .........2.7°C/W

Note 1: Self-protected against transient voltages exceeding these limits for ≤ 50ns under normal operation and loads up to the maximum rated output current.

Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board. For detailed information on package thermal considerations, refer to

www.maximintegrated.com/thermal-tutorial

.

Electrical Characteristics

(V

SUP

= V

SUPSW

T

A

= T

J

= 14V, V

EN

= 14V, L1 = 2.2µH, C

IN

= 4.7µF, C

OUT

= -40°C to +85°C, unless otherwise noted. Typical values are at T

A

= 22µF, C

BIAS

= 1µF, C

BST

= 0.1µF, R

FOSC

= 12kΩ,

= +25°C.) (Note 3)

PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS

Supply Voltage V

SUP

, V

SUPSW

3.5

36 V

Line Transient Event Supply

Voltage

42 V

Supply Current

Shutdown Supply Current

BIAS Regulator Voltage

V

SUP_t_LT

I

SUP_STANDBY

I

SHDN

V

BIAS

V

UVBIAS t t_LT

< 1s

Standby mode, no load, V

OUT

V

FSYNC

= 0V

= 5V,

V

EN

= 0V

V

SUP

I

BIAS

= V

SUPSW

= 0 to 10mA

= 6V to 42V,

V

BIAS

rising

4.7

2.95

28

5

5

3.15

40

8

5.4

3.40

µA

µA

V

V BIAS Undervoltage Lockout

BIAS Undervoltage-Lockout

Hysteresis

Thermal Shutdown Threshold

Thermal Shutdown Threshold

Hysteresis

450

+175

15

650 mV

°C

°C www.maximintegrated.com

Maxim Integrated │

3

MAX17244 3.5V–36V, 2.5A, Synchronous Buck Converter

With 28µA Quiescent Current and Reduced EMI

Electrical Characteristics (continued)

(V

SUP

= V

SUPSW

T

A

= T

J

= 14V, V

EN

= 14V, L1 = 2.2µH, C

IN

= 4.7µF, C

OUT

= -40°C to +85°C, unless otherwise noted. Typical values are at T

A

= 22µF, C

BIAS

= 1µF, C

BST

= 0.1µF, R

FOSC

= 12kΩ,

= +25°C.) (Note 3)

PARAMETER

OUTPUT VOLTAGE (OUT)

SYMBOL CONDITIONS MIN TYP MAX UNITS

FPWM Mode Output Voltage

(Note 3)

V

OUT_5V

V

OUT_3.3V

V

FB

= V

BIAS

, 6V < V

SUPSW

< 36V,

MAX17244____A, fixed-frequency mode

4.9

3.234

5

3.3

5.1

3.366

V

PFM-Mode Output Voltage

(Note 4)

Load Regulation

Line Regulation

BST Input Current

V

OUT_5V

V

OUT_3.3V

I

BST_ON

I

BST_OFF

LX Current Limit

LX Rise Time

PFM-Mode Current Threshold

Spread Spectrum

High-Side Switch

On-Resistance

High-Side Switch Leakage

Current

I

SKIP_TH

R

I

LX

ON_H

Low-Side Switch

On-Resistance

Low-Side Switch

Leakage Current

R

ON_L

TRANSCONDUCTANCE AMPLIFIER (COMP)

FB Input Current I

FB

V

FB

= V

BIAS

, 6V < V

SUPSW

< 36V,

MAX17244____B, fixed-frequency mode

No load, V

FB

= V

BIAS

,

MAX17244____A, PFM mode

V

FB

= V

BIAS

, 6V < V

SUPSW

< 36V,

MAX17244____B, PFM mode

V

FB

= V

BIAS

, 300mA < I

LOAD

< 2.5A

V

FB

= V

BIAS

, 6V < V

SUPSW

< 36V

High-side MOSFET on,

V

BST

- V

LX

= 5V

High-side MOSFET off,

V

BST

- V

LX

= 5V, T

A

= +25°C

Peak inductor current

R

FOSC

= 12kΩ

T

A

= +25°C

Spread spectrum enabled

I

LX

= 1A, V

BIAS

= 5V

High-side MOSFET off, V

SUP

V

LX

= 0V, T

A

= +25°C

= 36V,

I

LX

= 0.2A, V

BIAS

= 5V

V

LX

= 36V, T

A

= +25°C

4.9

3.234

1

3

200

5

3.3

0.5

0.02

1.5

3.75

4

400 f

OSC

±6%

100

1

1.5

20

1

5.15

3.34

2

5

4.5

500

220

3

3

100

V

%

%/V mA

µA

A ns mA mΩ

µA

Ω

µA nA

FB Regulation Voltage V

FB

∆V

LINE

FB connected to an external resistordivider, 6V < V

SUPSW

< 36V (Note 5)

6V < V

SUPSW

< 36V

0.99

1.0

0.02

1.015

V

%/V FB Line Regulation

Transconductance

(from FB to COMP)

Minimum On-Time

Maximum Duty Cycle g m t

ON_MIN

DC

MAX

V

FB

= 1V, V

BIAS

= 5V

(Note 4)

700

80

98

µS ns

% www.maximintegrated.com

Maxim Integrated │

4

MAX17244 3.5V–36V, 2.5A, Synchronous Buck Converter

With 28µA Quiescent Current and Reduced EMI

Electrical Characteristics (continued)

(V

SUP

= V

SUPSW

T

A

= T

J

= 14V, V

EN

= 14V, L1 = 2.2µH, C

IN

= 4.7µF, C

OUT

= -40°C to +85°C, unless otherwise noted. Typical values are at T

A

= 22µF, C

BIAS

= 1µF, C

BST

= 0.1µF, R

FOSC

= 12kΩ,

= +25°C.) (Note 3)

PARAMETER

OSCILLATOR FREQUENCY

SYMBOL CONDITIONS MIN TYP MAX UNITS

Oscillator Frequency

R

FOSC

= 73.2kΩ

R

FOSC

= 12kΩ

340

2.0

400

2.2

460

2.4

kHz

MHz

EXTERNAL CLOCK INPUT (FSYNC)

External Input Clock

Acquisition Time

External Input Clock Frequency t

FSYNC

External Input Clock High

Threshold

External Input Clock Low

Threshold

Soft-Start Time

ENABLE INPUT (EN)

Enable Input High Threshold

Enable Input Low Threshold

Enable Threshold-Voltage

Hysteresis

V

V

FSYNC_HI

FSYNC_LO

V

V t

SS

EN_HI

V

EN_LO

EN_HYS

Enable Input Current

POWER GOOD (PGOOD)

I

EN

PGOOD Switching Level

V

TH_RISING

V

TH_FALLING

PGOOD Debounce Time

PGOOD Output Low Voltage

PGOOD Leakage Current

SYNCOUT Low Voltage

SYNCOUT Leakage Current

FSYNC Leakage Current

OVERVOLTAGE PROTECTION

Overvoltage Protection

Threshold

R

FOSC

= 12kΩ (Note 6)

V

FSYNC

rising

V

FSYNC

falling

T

A

= +25°C

V

FB

rising, V

PGOOD

= high

V

FB

falling, V

PGOOD

= low

I

SINK

= 5mA

V

OUT

in regulation, T

A

= +25°C

I

SINK

= 5mA

T

A

= +25°C

T

A

= +25°C

V

OUT

rising (monitored at FB pin)

V

OUT

falling (monitored at FB pin)

1.8

1.4

5.6

2.4

93

90

10

1

8

0.2

0.1

95

92

25

105

102

2.6

0.4

12

0.6

1

1

1

1

0.4

97

94

50

0.4

Cycles

MHz

V

V ms

V

V

µA

%V

FB

µs

V

µA

V

µA

µA

%

Note 3: Limits are 100% production tested at T

A

= +25°C. Limits over the operating temperature range are guaranteed by design.

Note 4: Device not in dropout condition.

Note 5: Guaranteed by design; not production tested.

Note 6: FB regulation voltage is 1%, 1.01V (max), for -40°C < T

A

< +105°C.

Note 7: Contact the factory for SYNC frequency outside the specified range.

www.maximintegrated.com

Maxim Integrated │

5

MAX17244 3.5V–36V, 2.5A, Synchronous Buck Converter

With 28µA Quiescent Current and Reduced EMI

Typical Operating Characteristics

(V

SUP

= V

SUPSW

= 14V, V

EN

= 14V, V

OUT

= 5V, V

FYSNC

= 0V, R

FOSC

= 12kΩ, T

A

= +25°C, unless otherwise noted.)

EFFICIENCY vs. LOAD CURRENT

100

90

80

70

60

50

40

30

20

10

0

0 f

SW

= 2.2MHz, V

IN

= 14V

5V PFM MODE

0.001

3.3V

5V

3.3V

PWM MODE

0.1

LOAD CURRENT (A)

10

V

OUT

LOAD REGULATION

5.10

5.08

5.06

5.04

5.02

5.00

4.98

4.96

4.94

4.92

4.90

0

V

OUT

= 5V, V

IN

= 14V

PWM MODE

0.5

1.0

400kHz

2.2MHz

1.5

I

LOAD

(A)

2.0

2.5

2.28

2.24

f

SW

vs. TEMPERATURE

V

IN

= 14V,

PWM MODE

V

OUT

= 5V

2.20

2.16

2.12

2.08

2.04

V

OUT

= 3.3V

2.00

-40 -25 -10 5 20 35 50 65

TEMPERATURE (°C)

80 95 110 125

EFFICIENCY vs. LOAD CURRENT

100

90

80

70

60

50

40

30

20

10

0

0 f

SW

= 400kHz, V

IN

= 14V

PFM MODE

5V

5V

3.3V

0.001

0.1

LOAD CURRENT (A)

3.3V

PWM MODE

10

f

SW

vs. LOAD CURRENT

2.30

2.28

2.26

2.24

2.22

2.20

2.18

2.16

2.14

2.12

2.10

0

V

IN

= 14V,

PWM MODE

0.5

V

OUT

= 5V

V

OUT

= 3.3V

1.0

1.5

I

LOAD

(A)

2.0

2.5

2.50

2.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0

12

SWITCHING FREQUENCY vs. R

FOSC

42 72

R

FOSC

(kΩ)

102 132

V

OUT

LOAD REGULATION

5.02

5.00

4.98

4.96

4.94

4.92

4.90

5.10

5.08

5.06

5.04

0

V

OUT

= 5V, V

IN

= 14V

PFM MODE

0.5

1.0

400kHz

2.2MHz

1.5

I

LOAD

(A)

2.0

f

SW

vs. LOAD CURRENT

435

434

433

432

431

430

429

428

427

426

425

0

V

IN

= 14V,

PWM MODE

0.5

V

OUT

= 5V

V

OUT

= 3.3V

1.0

1.5

I

LOAD

(A)

2.0

2.5

2.5

45

40

35

50

SUPPLY CURRENT vs. SUPPLY VOLTAGE

30

25

20

15

10

6

5V/2.2MHz

PFM MODE

16 26

SUPPLY VOLTAGE (V)

36 www.maximintegrated.com

Maxim Integrated │

6

MAX17244 3.5V–36V, 2.5A, Synchronous Buck Converter

With 28µA Quiescent Current and Reduced EMI

Typical Operating Characteristics (continued)

(V

SUP

= V

SUPSW

= 14V, V

EN

= 14V, V

OUT

= 5V, V

FYSNC

= 0V, R

FOSC

= 12kΩ, T

A

= +25°C, unless otherwise noted.)

V

IN

V

OUT

V

PGOOD

I

LOAD

10

9

8

7

6

5

4

3

2

1

0

6

SHDN CURRENT vs. SUPPLY VOLTAGE

5V/2.2MHz

PFM MODE

12 18 24

SUPPLY VOLTAGE (V)

30 36

5.05

5.03

I

5V/400kHz

PWM MODE

LOAD

= 0A

V

OUT

vs. V

IN

5.01

4.99

4.97

4.95

6 12 18

V

IN

(V)

24 30 36

V

BIAS

vs. TEMPERATURE

5.02

5.01

5.00

4.99

4.98

4.97

4.96

4.95

4.94

4.93

4.92

4.91

4.90

-40

V

IN

= 14V,

PWM MODE

-25 -10 5 20 35 50 65 80

TEMPERATURE (°C)

I

LOAD

= 0A

95 110 125

V

IN

V

OUT

I

LOAD

V

PGOOD

FULL-LOAD STARTUP BEHAVIOR

MAX17244 toc14

10V/div

0V

5V/div

0V

V

IN

V

OUT

1A/div

0A

5V/div

0V

V

PGOOD

I

LOAD

2ms

5.08

5.06

5.04

5.02

5.00

4.98

4.96

4.94

4.92

4.90

6

I

5V/2.2MHz

PWM MODE

LOAD

= 0A

12 18

V

OUT

vs. V

IN

V

IN

24

(V)

30 36 42

SLOW V

IN

RAMP BEHAVIOR

MAX17244 toc15

4s

10V/div

0V

5V/div

0V

5V/div

0V

2A/div

0A

SLOW V

IN

RAMP BEHAVIOR

MAX17244 toc16

4s

10V/div

0V

V

LX

5V/div

0V

5V/div

0V

V

FSYNC

2A/div

0A

SYNC FUNCTION

MAX17244 toc17

200ns

V

IN

5V/div

V

OUT

2V/div

V

LX

V

PGOOD

DIPS AND DROPS TEST

MAX17244 toc18

10V/div

5V/2.2MHz

0V

5V/div

0V

10V/div

0V

5V/div

0V

10ms www.maximintegrated.com

Maxim Integrated │

7

MAX17244 3.5V–36V, 2.5A, Synchronous Buck Converter

With 28µA Quiescent Current and Reduced EMI

Typical Operating Characteristics (continued)

(V

SUP

= V

SUPSW

= 14V, V

EN

= 14V, V

OUT

= 5V, V

FYSNC

= 0V, R

FOSC

= 12kΩ, T

A

= +25°C, unless otherwise noted.)

V

IN

LINE TRANSIENT

MAX17244 toc19

2V/div

V

OUT

V

PGOOD

2V/div

2V/div

0V

400ms

V

OUT

(AC-COUPLED)

LOAD

CURRENT

LOAD TRANSIENT (PWM MODE)

MAX17244 toc21 f

SW

V

= 2.2MHz

OUT

= 5V

200mV/div

2A/div

0A

100µs

LINE TRANSIENT

MAX17244 toc20

10V/div

V

IN

V

OUT

0V

5V/div

0V

100ms

V

OUT

INDUCTOR

CURRENT

SHORT CIRCUIT IN PWM MODE

MAX17244 toc22

2V/div

0V

2A/div

0A

PGOOD

5V/div

0V

10ms www.maximintegrated.com

Maxim Integrated │

8

MAX17244 3.5V–36V, 2.5A, Synchronous Buck Converter

With 28µA Quiescent Current and Reduced EMI

Pin Configuration

TOP VIEW

16 15 14 13 12 11 10 9

MAX17244

EP

+

1 2 3 4 5 6 7 8

12 11 10 9

LX 13

PGND 14

PGOOD 15

SYNCOUT 16

MAX17244

+

EP

1 2 3 4

TQFN

8

BST

7 AGND

6 BIAS

5 COMP

TSSOP

Pin Descriptions

PIN

TSSOP TQFN

1

2

3

4

5

6

7

8

9

16

1

2

3

4

5

6

7

8

NAME

SYNCOUT

FSYNC

FOSC

OUT

FB

COMP

BIAS

AGND

BST

FUNCTION

Open-Drain Clock Output. SYNCOUT outputs 180N out-of-phase signal relative to the internal oscillator. Connect to OUT with a resistor between 100Ω and 1kΩ for 2MHz operation. For low frequency operation, use a resistor between 1kΩ and 10kΩ.

Synchronization Input. The device synchronizes to an external signal applied to FSYNC.

Connect FSYNC to AGND to enable PFM mode operation. Connect to BIAS or to an external clock to enable fixed-frequency forced PWM mode operation.

Resistor-Programmable Switching Frequency Setting Control Input. Connect a resistor from FOSC to AGND to set the switching frequency.

Switching Regulator Output. OUT also provides power to the internal circuitry when the output voltage of the converter is set between 3V to 5V during standby mode.

Feedback Input. Connect an external resistive divider from OUT to FB and AGND to set the output voltage. Connect to BIAS to set the output voltage to 5V.

Error Amplifier Output. Connect an RC network from COMP to AGND for stable operation.

See the Compensation Network section for more information.

Linear Regulator Output. BIAS powers up the internal circuitry. Bypass with a 1µF capacitor to AGND.

Analog Ground

High-Side Driver Supply. Connect a 0.1µF capacitor between LX and BST for proper operation.

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Maxim Integrated │

9

MAX17244 3.5V–36V, 2.5A, Synchronous Buck Converter

With 28µA Quiescent Current and Reduced EMI

Pin Descriptions (continued)

PIN

NAME

TSSOP TQFN

10

11

9

10

EN

SUP

FUNCTION

SUP Voltage Compatible Enable Input. Drive EN low to PGND to disable the device. Drive

EN high to enable the device.

Voltage Supply Input. SUP powers up the internal linear regulator. Bypass SUP to PGND with a 4.7µF ceramic capacitor. It is recommended to add a placeholder for an RC filter to reduce noise on the internal logic supply (see the Typical Application Circuit)

12

13, 14

15

16

—

11

12, 13

14

15

—

SUPSW

LX

PGND

PGOOD

EP

Internal High-Side Switch Supply Input. SUPSW provides power to the internal switch.

Bypass SUPSW to PGND with 0.1µF and 4.7µF ceramic capacitors.

Inductor Switching Node. Connect a Schottky diode between LX and PGND.

Power Ground

Open-Drain, Active-Low Power-Good Output. PGOOD asserts when VOUT is above 95% regulation point. PGOOD goes low when V

OUT

is below 92% regulation point.

Exposed Pad. Connect EP to a large-area contiguous copper ground plane for effective power dissipation. Do not use as the only IC ground connection. EP must be connected to

PGND.

Detailed Description

The MAX17244 is a 2.5A current-mode, step-down converter with integrated high-side and low-side

MOSFETs designed to operate with an external Schottky diode for better efficiency. The low-side MOSFET enables fixed-frequency forced-PWM (FPWM) operation under light-load applications. The device operates with input voltages from 3.5V to 36V, while using only 28FA quiescent current at no load. The switching frequency is resistor programmable from 220kHz to 2.2MHz and can be synchronized to an external clock. The output voltage is available as 5V/3.3V fixed or adjustable from 1V to 10V.

The wide input voltage range, along with the ability to operate at 98% duty cycle during undervoltage transients, makes this device ideal for many applications.

Under light-load applications, the FSYNC logic input allows the device to either operate in PFM mode for reduced current consumption or fixed-frequency PWM mode to eliminate frequency variation to minimize EMI.

Fixed-frequency PWM mode is extremely useful for power supplies designed for RF transceivers where tight emission control is necessary. Protection features include cycle-by-cycle current limit, overvoltage protection, and thermal shutdown with automatic recovery. Additional features include a power-good monitor to ease powersupply sequencing and a 180° out-of-phase clock output relative to the internal oscillator at SYNCOUT to create cascaded power supplies with multiple devices.

Wide Input Voltage Range

This device includes two separate supply inputs (SUP and

SUPSW) specified for a wide 3.5V to 36V input voltage range. V

SUP

provides power to the device and V

SUPSW provides power to the internal switch. When the device is operating with a 3.5V input supply, conditions such as cold crank can cause the voltage at SUP and SUPSW to drop below the programmed output voltage. Under such conditions, the device operates in a high duty-cycle mode to facilitate minimum dropout from input to output.

In applications where the input voltage exceeds 25V, output is ≤ 5V, operating frequency is ≥ 1.8MHz, and the

IC is selected to be in PWM mode by either forcing the

FSYNC pin high, or by using an external clock, pulse skipping is observed on the LX pin. This happens due to insufficient minimum on time.

Add optional R

SNUB

= 1Ω and C

SNUB

= 220pF to reduce

ringing on the LX pin. (see the

Typical Application Circuit

).

Maximum Duty-Cycle Operation)

The devices have a maximum duty cycle of 98% (typ).

The IC monitors the off-time (time for which the lowside FET is on) in both PWM and PFM modes every switching cycle. Once the off-time of 25ns (typ) is detected continuously for 12μs, the low-side FET is forced on for

150ns (typ) every 12μs. The input voltage at which the device enters dropout changes depending on the input voltage, output voltage, switching frequency, load current, and the efficiency of the design.

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MAX17244 3.5V–36V, 2.5A, Synchronous Buck Converter

With 28µA Quiescent Current and Reduced EMI

OUT COMP PGOOD EN SUP BIAS

FB

FBSW FBOK AON HVLDO

SWITCH

OVER

BST

SUPSW

EAMP

REF

PWM LOGIC HSD

LX

CS

SOFT

START

BIAS

LSD

MAX17244

SLOPE

COMP

FSYNC

Figure 1. Internal Block Diagram

The input voltage at which the device enters dropout can be approximated as:

V

SUP

=

V

OUT

+ (I

OUT

0.98

× R

ON_H

)

Note: The equation above does not take into account the

efficiency and switching frequency, but is a good first-order

approximation. Use the RON_H number from the max column

Linear Regulator Output (BIAS)

The devices include a 5V linear regulator (BIAS) that provides power to the internal circuit blocks. Connect a

1µF ceramic capacitor from BIAS to AGND. When the output voltage is set between 3V and 5.5V, the internal linear regulator only provides power until the output is in regulation. The internal linear regulator turns off once the output is in regulation and allows OUT to provide power to the device. The internal regulator turns back on once the external load on the output of the device is higher than

OSC

FOSC AGND

PGND

SYNCOUT

100mA. In addition, the linear regulator turns on anytime the output voltage is outside the 3V to 5.5V range.

Power-Good Output (PGOOD)

The devices feature an open-drain power-good output,

PGOOD. PGOOD asserts when V

OUT

rises above 95% of its regulation voltage. PGOOD deasserts when V

OUT drops below 92% of its regulation voltage. Connect

PGOOD to BIAS with a 10kΩ resistor.

Overvoltage Protection (OVP)

If the output voltage reaches the OVP threshold, the highside switch is forced off and the low-side switch is forced on until negative-current limit is reached. After negativecurrent limit is reached, both the high-side and low-side switches are turned off. The MAX17244 offers a lower voltage threshold for applications requiring tighter limits of protection. www.maximintegrated.com

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11

MAX17244 3.5V–36V, 2.5A, Synchronous Buck Converter

With 28µA Quiescent Current and Reduced EMI

Synchronization Input (FSYNC)

FSYNC is a logic-level input useful for operating mode selection and frequency control. Connecting FSYNC to

BIAS or to an external clock enables fixed-frequency

PWM operation. Connecting FSYNC to AGND enables

PFM mode operation.

The external clock frequency at FSYNC can be higher or lower than the internal clock by 20%. Ensure the duty cycle of the external clock used has a minimum pulse width of 100ns. The MAX17244 synchronizes to the external clock within one cycle. When the external clock signal at FSYNC is absent for more than two clock cycles, the device reverts back to the internal clock.

System Enable (EN)

An enable control input (EN) activates the device from its low-power shutdown mode. EN is compatible with inputs from automotive battery level down to 3.5V. The high voltage compatibility allows EN to be connected to SUP,

KEY/KL30, or the inhibit pin (INH) of a CAN transceiver.

EN turns on the internal regulator. Once V the internal lockout threshold, V

UVL

BIAS

is above

= 3.15V (typ), the controller activates and the output voltage ramps up within 8ms.

A logic-low at EN shuts down the device. During shutdown, the internal linear regulator and gate drivers turn off.

Shutdown is the lowest power state and reduces the quiescent current to 5µA (typ). Drive EN high to bring the device out of shutdown.

Spread-Spectrum Option

The devices have an internal spread-spectrum option to optimize EMI performance. This is factory set and the S-version of the device should be ordered. For spread-spectrum-enabled ICs, the operating frequency is varied ±6% centered on FOSC. The modulation signal is a triangular wave with a period of 110µs at 2.2MHz.

Therefore, FOSC will ramp down 6% and back to 2.2MHz in 110µs and also ramp up 6% and back to 2.2MHz in

110µs. The cycle repeats.

For operations at FOSC values other than 2.2MHz, the modulation signal scales proportionally (e.g., at 400kHz, the 110µs modulation period increases to 110µs x

2.2MHz/400kHz = 605µs).

The internal spread spectrum is disabled if the device is synced to an external clock. However, the device does not filter the input clock and passes any modulation (including spread-spectrum) present on the driving external clock to the SYNCOUT pin.

Automatic Slew-Rate Control on LX

The MAX17244 has automatic slew-rate adjustment that optimizes the rise times on the internal HSFET gate drive to minimize EMI. The IC detects the internal clock frequency and adjusts the slew rate accordingly. When the user selects the external frequency setting resistor

R

FOSC

such that the frequency is > 1.1MHz, the HSFET is turned on in 4ns (typ). When the frequency is < 1.1MHz the HSFET is turned on in 8ns (typ). This slew-rate control optimizes the rise time on LX node externally to minimize

EMI while maintaining good efficiency.

Internal Oscillator (FOSC)

The switching frequency (f

(R

FOSC

) connected from FOSC to AGND. See Figure 3

to select the correct R ing frequency. The R equation below:

R

FOSC

=

FOSC

FOSC

SW

) is set by a resistor

value for the desired switch-

value is approximated by the

19.05E15

−

For example, a 400kHz switching frequency is set with

R

FOSC

= 73.2kΩ. Higher frequencies allow designs with lower inductor values and less output capacitance.

Consequently, peak currents and I

2

R losses are lower at higher switching frequencies, but core losses, gate charge currents, and switching losses increase.

Synchronizing Output (SYNCOUT)

SYNCOUT is an open-drain output that outputs a 180° out-of-phase signal relative to the internal oscillator.

Overtemperature Protection

Thermal-overload protection limits the total power dissipation in the devices. When the junction temperature exceeds 175°C (typ), an internal thermal sensor shuts down the internal bias regulator and the step-down controller, allowing the device to cool. The thermal sensor turns on the device again after the junction temperature cools by 15°C.

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MAX17244 3.5V–36V, 2.5A, Synchronous Buck Converter

With 28µA Quiescent Current and Reduced EMI

Applications Information

Setting the Output Voltage

Connect FB to BIAS for a fixed +5V/+3.3 output voltage.

To set the output to other voltages between 1V and 10V, connect a resistive divider from output (OUT) to FB to

AGND ( Figure 2

). Use the following formula to determine the R

FB2

of the resistive divider network:

R

FB2

= R

TOTAL x V

FB

/V

OUT where V

R

FB1

, R

FB

FB2

= 1V, R

TOTAL

in Ω, and V

= selected total resistance of

OUT

is the desired output in volts.

Calculate R

FB1 equation:

(OUT to FB resistor) with the following

R

FB1

= R

FB2

OUT

FB







− 1







 where V

FB

= 1V (see the

Electrical Characteristics

table).

PWM/PFM Modes

The MAX17244 offers a pin-selectable PFM mode or fixed-frequency PWM mode option. The IC has an internal LS

MOSFET that turns on when the FSYNC pin is connected to V

BIAS

or if there is a clock present on the FSYNC pin. This enables the fixed-frequency-forced PWM mode operation over the entire load range. This option allows the user to maintain fixed frequency over the entire load range in applications that require tight control on EMI.

Even though the devices have an internal LS MOSFET for fixed-frequency operation, an external Schottky diode is still required to support the entire load range. If the

FSYNC pin is connected to AGND, the PFM mode is enabled on the device.

In PFM mode of operation, the converter’s switching frequency is load dependent. At higher load current, the switching frequency does not change and the operating mode is similar to the PWM mode. PFM mode helps improve efficiency in light-load applications by allowing the converters to turn on the high-side switch only when the output voltage falls below a set threshold. As such, the converters do not switch MOSFETs on and off as often as is the case in the PWM mode. Consequently, the gate charge and switching losses are much lower in

PFM mode. Refer to the

Rectifier Selection

section for

PFM mode.

Inductor Selection

Three key inductor parameters must be specified for operation with the devices: inductance value (L), inductor saturation current (I

(R

DCR

SAT

), and DC resistance

). To select inductance value, the ratio of inductor peak-to-peak AC current to DC average current (LIR) must be selected first. A good compromise between size and loss is a 30% peak-to-peak ripple current to average current ratio (LIR = 0.3). The switching frequency, input voltage, output voltage, and selected LIR then determine the inductor value as follows:

L =

V

OUT

( V

SUP

V f I

− V

OUT

LIR

) where V

SUP

, V

OUT

, and I

OUT

are typical values (so that efficiency is optimum for typical conditions). The switching frequency is set by R

FOSC

(see

Figure 3

).

MAX17244

FB

Figure 2. Adjustable Output-Voltage Setting

V

OUT

R

FB1

R

FB2

2.50

2.25

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

0

12

SWITCHING FREQUENCY vs. R

FOSC

42 72

R

FOSC

(kΩ)

102 132

Figure 3. Switching Frequency vs. R

FOSC

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MAX17244 3.5V–36V, 2.5A, Synchronous Buck Converter

With 28µA Quiescent Current and Reduced EMI

Input Capacitor

The input filter capacitor reduces peak currents drawn from the power source and reduces noise and voltage ripple on the input caused by the circuit’s switching.

The input capacitor RMS current requirement (I

RMS defined by the following equation:

) is

I

RMS

= I

LOAD(MAX )

V

OUT

( V

SUP

V

SUP

− V

OUT

)

I

RMS

has a maximum value when the input voltage equals twice the output voltage (V

SUP

= 2V

OUT

), so I

RMS(MAX)

= I

LOAD(MAX)

/2.

Choose an input capacitor that exhibits less than +10°C self-heating temperature rise at the RMS input current for optimal long-term reliability.

The input voltage ripple is composed of ΔV by the capacitor discharge) and ΔV

ESR

Q

(caused

(caused by the

ESR of the capacitor). Use low-ESR ceramic capacitors with high ripple current capability at the input. Assume the contribution from the ESR and capacitor discharge equal to 50%. Calculate the input capacitance and ESR required for a specified input voltage ripple using the following equations:

ESR

IN

=

I

∆ V

ESR

OUT

+

∆ I

L

2 where:

∆ I

L

=

( V

SUP

V

−

SUP

V

OUT

× f

SW

×

× L

OUT and:

C

IN

=

I

OUT

∆ V

×

Q

× f

SW and D =

V

OUT

V

SUPSW where I

OUT duty cycle.

is the maximum output current and D is the

Output Capacitor

The output filter capacitor must have low enough ESR to meet output ripple and load transient requirements.

The output capacitance must be high enough to absorb the inductor energy while transitioning from full-load to no-load conditions without tripping the overvoltage fault protection. When using high-capacitance, low-ESR capacitors, the filter capacitor’s ESR dominates the output voltage ripple. So the size of the output capacitor depends on the maximum ESR required to meet the output voltage ripple (V

RIPPLE(P-P

)) specifications:

V =

LOAD(MAX)

× LIR

The actual capacitance value required relates to the physical size needed to achieve low ESR, as well as to the chemistry of the capacitor technology. Thus, the capacitor is usually selected by ESR and voltage rating rather than by capacitance value.

When using low-capacity filter capacitors, such as ceramic capacitors, size is usually determined by the capacity needed to prevent voltage droop and voltage rise from causing problems during load transients. Generally, once enough capacitance is added to meet the overshoot requirement, undershoot at the rising load edge is no longer a problem. However, low capacity filter capacitors typically have high ESR zeros that can affect the overall stability.

Rectifier Selection

The devices require an external Schottky diode rectifier as a freewheeling diode when they are is configured for

PFM-mode operation. Connect this rectifier close to the device using short leads and short PCB traces. In PWM mode, the Schottky diode helps minimize efficiency losses by diverting the inductor current that would otherwise flow through the low-side MOSFET. Choose a rectifier with a voltage rating greater than the maximum expected input voltage, V

SUPSW

. Use a low forward-voltage-drop

Schottky rectifier to limit the negative voltage at LX. Avoid higher than necessary reverse-voltage Schottky rectifiers that have higher forward-voltage drops.

Compensation Network

The devices use an internal transconductance error amplifier with its inverting input and its output available to the user for external frequency compensation. The output capacitor and compensation network determine the loop stability. The inductor and the output capacitor are chosen based on performance, size, and cost. Additionally, the compensation network optimizes the control-loop stability.

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MAX17244 3.5V–36V, 2.5A, Synchronous Buck Converter

With 28µA Quiescent Current and Reduced EMI

The controller uses a current-mode control scheme that regulates the output voltage by forcing the required current through the external inductor. The devices use the voltage drop across the high-side MOSFET to sense inductor current. Current-mode control eliminates the double pole in the feedback loop caused by the inductor and output capacitor, resulting in a smaller phase shift and requiring less elaborate error-amplifier compensation than voltage-mode control. Only a simple single-series resistor (R

C

) and capacitor (C

C

) are required to have a stable, high-bandwidth loop in applications where ceramic

capacitors are used for output filtering ( Figure 4

). For other types of capacitors, due to the higher capacitance and ESR, the frequency of the zero created by the capacitance and ESR is lower than the desired closed-loop crossover frequency. To stabilize a nonceramic output capacitor loop, add another compensation capacitor (C

COMP to AGND to cancel this ESR zero.

F

) from

The basic regulator loop is modeled as a power modulator, output feedback divider, and an error amplifier. The power modulator has a DC gain set by g m

x R

LOAD

, with a pole and zero pair set by R the output capacitor (C

OUT of the power modulator (GAIN

LOAD

,

), and its ESR. The following equations allow to approximate the value for the gain effect of the ramp stabilization. Ramp stabilization is necessary when the duty cycle is above 50% and is internally done for the device.

MOD(dc)

), neglecting the

GAIN

MOD(dc)

= g m

× R

LOAD where R

LOAD

= V

OUT

/I

LOUT(MAX)

in Ω and g m

= 3S.

In a current-mode step-down converter, the output capacitor, its ESR, and the load resistance introduce a pole at the following frequency: f pMOD

= 1 (2 π × C

OUT

× R

LOAD

)

The output capacitor and its ESR also introduce a zero at: f zMOD

=

1

2 π × ×

OUT

When C

OUT

is composed of “n” identical capacitors in parallel, the resulting C

OUT

= n x C

OUT(EACH)

, and

ESR = ESR

(EACH)

/n. Note that the capacitor zero for a parallel combination of alike capacitors is the same as for an individual capacitor.

The feedback voltage-divider has a gain of GAIN

FB

= V

FB

V

OUT

, where V

FB

is 1V (typ). The transconductance error amplifier has a DC gain of GAIN

EA(dc)

= g m

,EA x R

OUT,EA

/

,

R1

V

OUT

R2

V

REF g m

R

C

C

C

COMP

C

F

Figure 4. Compensation Network

where g m

,EA is the error amplifier transconductance, which is 700µS (typ), and R of the error amplifier 50MΩ.

OUT,EA

is the output resistance

A dominant pole (f capacitor (C

(R

OUT,EA

C dpEA

). A zero (f zEA

) is set by the compensation

) and the amplifier output resistance resistor (R

C

) is set by the compensation

) and the compensation capacitor (C

There is an optional pole (f pEA

) set by C

F

and R

C

C

).

to cancel the output capacitor ESR zero if it occurs near the cross over frequency (f

C

, where the loop gain equals

1 (0dB)). Thus: f dpEA

= f f

1

2 π × C

C

× (R

OUT,EA zEA pEA

=

=

1

2 π × C

C

1

× R

C

2 π × C

F

× R

C

+

The loop-gain crossover frequency (f than the power-modulator pole (f pMOD

C

):

) should be set below 1/5th of the switching frequency and much higher f pMOD

<< f

C

≤ f

SW

5

The total loop gain as the product of the modulator gain, the feedback voltage-divider gain, and the error amplifier gain at f

C

should be equal to 1. So:

GAIN

MOD( fC )

GAIN

×

V

FB

V

OUT

EA ( fC )

=

× GAIN g m, EA

×

EA ( fC )

R

C

GAIN

MOD( fC )

= GAIN

MOD( dc )

×

= f pMOD f

C

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MAX17244 3.5V–36V, 2.5A, Synchronous Buck Converter

With 28µA Quiescent Current and Reduced EMI

Therefore:

GAIN

MOD(fC)

×

V

FB

V

OUT

× g m,EA

× R

C

= 1

Solving for R

C

:

R

C

= g m,EA

× V

V

OUT

FB

× GAIN

MOD( fC )

Set the error-amplifier compensation zero formed by R

C and C

C follows:

(f zEA

) at the fp

MOD

. Calculate the value of C

C

a

C

C

=

1

2 π × f pMOD

× R

C

If f

C

F zMOD

is less than 5 x f formed by R

C value of C

F

and C

F

as follows:

(f pEA

C

, add a second capacitor,

, from COMP to GND and set the compensation pole

) at the f zMOD

. Calculate the

C

F

=

1

2 π × f zMOD

× R

C

As the load current decreases, the modulator pole also decreases; however, the modulator gain increases accordingly and the crossover frequency remains the same.

PCB Layout Guidelines

Careful PCB layout is critical to achieve low switching losses and clean, stable operation. Use a multilayer board whenever possible for better noise immunity and power dissipation. Follow these guidelines for good PCB layout:

1) Use a large contiguous copper plane under the IC package. Ensure that all heat-dissipating components have adequate cooling. The bottom pad of the IC must be soldered down to this copper plane for effective heat dissipation and for getting the full power out of the IC.

Use multiple throughputs, or a single large throughput, in this plane for heat dissipation.

2) Isolate the power components and high current path from the sensitive analog circuitry. Doing so is essential to prevent any noise coupling into the analog signals. Implementing an RC filter on the SUP pin decreases switching noise from entering the logic supply. Refer to the MAX17244 EV kit data sheet for details on filter configuration and PCB layout for the

SUP and SUPSW input capacitors. Do not route the

OUT or feedback signal next to the inductor. Make sure components used on FOSC, COMP, and BIAS are connected to analog AGND.

3) Keep the high-current paths short, especially at the ground terminals. This practice is essential for stable, jitter-free operation. The high-current path composed of the input capacitor, high-side FET, inductor, and the output capacitor should be as short as possible.

4) Keep the power traces and load connections short.

This practice is essential for high efficiency. Use thick copper PCBs (2oz vs. 1oz) to enhance full-load efficiency.

5) The analog signal lines should be routed away from the high-frequency planes. Doing so ensures integrity of sensitive signals feeding back into the IC.

6) The ground connection for the analog and power section should be close to the IC. This keeps the ground current loops to a minimum. In cases where only one ground is used, enough isolation between analog return signals and high power signals must be maintained.

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MAX17244 3.5V–36V, 2.5A, Synchronous Buck Converter

With 28µA Quiescent Current and Reduced EMI

Ordering Information

PART

V

OUT

ADJUSTABLE

(FB CONNECTED TO

RESISTIVE DIVIDER) (V)

MAX17244ETERA+

MAX17244ETERB+

MAX17244ETESA+

1 to 10

1 to 10

1 to 10

MAX17244ETESB+ 1 to 10

+Denotes a lead(Pb)-free/RoHS-compliant package.

*EP = Exposed pad.

Chip Information

PROCESS: BiCMOS

FIXED

(FB CONNECTED

TO BIAS) (V)

5

3.3

5

3.3

SPREAD

SPECTRUM

Off

Off

On

On

TEMP RANGE

-40°C to +85°C

-40°C to +85°C

-40°C to +85°C

-40°C to +85°C

PIN-PACKAGE

16 TQFN-EP*

16 TQFN-EP*

16 TQFN-EP*

16 TQFN-EP*

Package Information

For the latest package outline information and land patterns

(footprints), go to

www.maximintegrated.com/packages

. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.

PACKAGE

TYPE

16 TSSOP-EP

16 TQFN-EP

PACKAGE

CODE

U16E+3

T1655+4

OUTLINE

NO.

21-0108

21-0140

LAND

PATTERN

NO.

90-0120

90-0121

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MAX17244 3.5V–36V, 2.5A, Synchronous Buck Converter

With 28µA Quiescent Current and Reduced EMI

Revision History

REVISION

NUMBER

0

1

REVISION

DATE

4/16

3/17

DESCRIPTION

Initial release

Added equation to Induction Selection section

PAGES

CHANGED

—

12

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.

Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.

Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.

© 2017 Maxim Integrated Products, Inc. │ 18