Silicon Imaging SI-1920HD MegaCamera™ 1080P/24/30/60 12

Silicon Imaging SI-1920HD MegaCamera™ 1080P/24/30/60 12
Silicon Imaging
SI-1920HD MegaCamera
1080P/24/30/60 12-Bit
High-Definition Digital Camera
Revision .93
August, 2009
2.1 Million Pixels (16:9 Format)
1920 x 1080HD Sensor
5.0 um Square Pixel
12-Bit Digitizing
150MS/sec (2-tap x 12bit @ 75MHz)
Mono or Bayer Color
CameraLink Base (2 taps, 12bit each)
**** Company Confidential ****
 Silicon Imaging , Inc. 2004
Page 1 of 41
Company Confidential
Silicon Imaging MegaCameraHD
SI-1920HD
1920 x 1080, 2.1 Megapixel, 1080P/24/30/60,1080I & 720p
12-bit, 150 Mpixel/sec VariScan High-Definition Digital Camera
Silicon Imaging is proud to continue its innovation in ultra-high speed vision
technology. The Silicon Imaging MegaCameraHD (SI-1920HD) unleashes a
new generation of high-performance HDTV CMOS camera power that not only
replaces traditional CCD cameras, but surpasses their capability in single chip
high-quality HD video applications including broadcast sports, animation, matte
work, miniatures, Stereoscopic 3D and slow-motion special effects.
HDTV 1920 x 1080 at 60FPS (SMPTE 274M 1080P Timing)
By integrated a 2/3” optical format 2.1 Megapixel HDTV CMOS imaging sensor
with multi-tap 12-bit A/D conversion, digital signal processing, programmable
timing generation and high-speed cameralink digital outputs, Silicon Imaging has
developed the worlds smallest 1920 x 1080 60Hz progressive scan
(SMPTE274M timing) HD camera.
68dB Wide Dynamic Range ( > 11bits)
Perhaps one of the most important characteristics of this CMOS camera is its
ability to produce high-quality images even under adverse illumination. Unlike
CCD cameras which can bloom and reduce their dynamic range with increased
data rates (generally 50~55db), the SI-1920HD delivers excellent performance at
low light levels with >11 bits of dynamic range. The total noise for this camera is
limited to a S/N to 52dB at 0dB gain. Increasing sensor gain to 6dB boosts the
S/N to 57.5dB. At Pixel-limited read noise of only three electrons, at a gain of
18dB yields an S/N of 68dB and an ISO speed approaching 1600.
VariScanHD - 16:9 and 4:3 Aspect Switching and Multi-Format Timing
The VariscanHD feature enables the camera to produce HD video in multiple
formats with applicable timing and resolution standards including SMPTE 274M,
296M, 293M and ITU-R 601. It takes advantage of the windowing capability of
CMOS arrays to directly capture "native" 1080i, 1080p/30, and 720p, or switch
between 4:3 and 16:9, while maintaining correct timing for the desired format.
720P Slow-Motion, Stereoscopic 3-D & Special Effects at 120fps
In 720P mode the camera is capable of achieving selected frame rates from: 4fps up to 120-fps. When acquiring for 24-fps projects, higher than 24-fps
operation can be processed for slow motion effects while slower operation can
be processed to speed up motion. Combining the variable frame rate and a
variable shutter speed can create interesting ghost like motion blur effects, warp
speed zoom effects, and long exposure still shots typical of what one might see
in music videos, sci-fi dramas and dream sequences. For high speed motion
capture, the 720p mode at 120fps produces images without blur. Using the SI1920HD-3D stereo pair configuration, left/right eye images can be captured in
synch to create high-definition 3-D stereoscopic sequences.
12-Bits Uncompressed Bayer Color at 150Mpixel/sec
Unlike traditional broadcast and video cameras, which colorize and encode the
image data for transmission on analog or digital (HD-SDI) output, the
MegaCameraHD outputs raw 12-bits/pixel at 150MHz (1.8Gb/sec). The image
data is transmitted to a recording system using a dual-tap (2x12-bit 75MHz) base
cameralink interface and frame grabber. The image data can then be expanded
into an RGB per pixel (4:4:4) format with interpolation and color matrix for display
on PC graphic orHD-SDI playback hardware. As the 12-bit original data is
always maintained, no detail is lost in encoding, transcoding or recording.
CameraLink Digital Interfaces
An industry standard forum has adopted Camera Link, for low cost connectivity
and cabling of cameras and frame grabbers at very high speeds (over 2 GB/sec).
The SI-1290HD-CL utilizes the high speed CameraLink interface to output
1920x1080, 12 bit data at 75MHz continuously to a frame grabber and directly
into PC memory for further processing. The single cable includes image data,
vertical and horizontal synch, LVDS Triggering and Serial communication.
 Silicon Imaging , Inc. 2004
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FEATURES
•
1920 x 1080 Resolution (2.1 Million Pixels)
•
2/3” Imaging 16:9 Format , 5 um Square Pixel
•
1080P @ 24/25/30/60 FPS
•
720P Slow-Motion & Special Effects at 120fps
•
12 Bits per Pixel, 75MHz Sampling (150 MP/sec)
•
Region-of-Interest (ROI) windowing
•
Long Integration using external Triggering
•
Programmable Gain, Offset, Clock, Shutter & ROI
•
External Frame Synchronization (FrameLock)
•
Stereoscopic 3-D Capture with 2 cameras
•
Monochrome & Color Bayer RGB Models
•
5VDC Low Power, Small Package
•
C-Mount Housing or PCB versions
•
Cameralink (CL) & GigE Remote (GR) Models
Company Confidential
Sensor:
Active Pixels
Optical Imaging Format
Pixel Size (pitch)
Pixel Type
Aspect Ratio
Spectral Response
Peak QE
FPN (on chip corrected)
Maximum Noise (rms)
Read Noise
Saturation Charge
Dynamic range
Windowing (ROI)
Mono Sub-sampling
Readout Method
Hot Pixel
Shutter
Shutter Speed / Integration
Minimum Blanking
CameraLink Frame Grabber Control:
1920 (H) x 1080 (V)
2/3” Wide (9.68 x 5.45 mm2)
5 µm x 5 µm
CMOS (UMC 0.25 µm Process)
1:1
350 ~ 1000 nm
>55% Monochrome (>40% RGB) @ 600nm
<0.02%
3 counts
<15e- (@ 24dB gain)
60,000 e- max
>68dB
steps of 32 columns and 9 rows
- No readout of every third line/column
- Readout of every 2nd, 3rd, 4th line/column
- Independent horizontal and vertical ratios
Progressive Scan
Real-time Detection & Elimination
Rolling Shutter
Variable, 1 to 1086 Line times
280 Clocks/line
Serial Communication
Signaling
Region-of–Interest
Triggers & Genlock
RS-232 Protocol 9600bps
TX & RX (LVDS)
Programmable Horiz & Vertical
LVDS – CC1 (Frame grabber)
TTL Trigger-In
Exposure, Clock, Black Level,
Analog Gain, Digital Gain, Window
ROI, Subsampling, FPN, Presets.
Programmable Modes
Power
Input Voltage
Power
Power/Trigger Connection
+5 VDC +/- 10%
2.5 Watts
Tajimi RO3-PB3M 3Pin
Mechanical
Lens Mount
Enclosure Size
Weight
Camera Mount
Cable Connector
C-Mount, 7mm Back focus Adj.
45mm W x 52mm H x 50mm L
12 oz.
¼” x 20 standard tripod mount
Cameralink MDR-26 (-CL)
A/D Conversion & Sampling Clock Synthesizer
A/D Conversion
Vertical Resolution
Pixel Clock Frequency
Adjustment Method
Mean Black Level
150MHz (nominal) optional 74.25 MHz
(SMPTE 274M)
12 Bit (Dual-Outputs) – 4096 counts
20 ~ 85Mhz Programmable
Serial command Protocol
64 Counts (default)
Spectral Response Curve (Monochrome)
Quantum Efficiency
80%
70%
60%
Digital Video Output
QE [%]
50%
Frame Rate @ 75mhz clock
1920 x 1080
1280 x 1017
640 x 477
320 x 234
128 x 126
60
89
231
452
788
Minimum Blanking
40%
30%
20%
10%
280 Clocks/line
0%
300
400
500
600
700
800
900
Wavelength (nm)
ORDERING INFORMATION
SI-1920HD-[RGB or M]-CL
2.1 MP Digital Camera (RGB for Color, M for Monochrome)
FG-XXX
Consult Factory for frame grabber p/n
PS-5
5V power supply (power supply cable sold separately)
CL-2, 5, 10
2 / 5 / 10 Meter Digital Camera Cable
PC-2
Power supply Cable (2M)
PCT-2
Power supply cable (2M) WITH trigger-in/Genlock connections
 Silicon Imaging , Inc. 2004
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Company Confidential
1,000
1,100
SI-1920HD Camera Architecture Overview
The MegaCamera
SI-1920HD consists of 6 major component sections built on two PC boards (33 x 40mm):
2.1 Megapixel CMOS Image Sensor
Digital Clock Synthesizer
Digital Control Logic
Microprocessor
Dual 12-Bit CameraLink Interface (Base Configuration)
Camera Control Signals & +5VDC Power
Register
Programming
5VDC Power Supply
& Trigger Controller
DATA (12)
DATA (12)
CLOCK
LVAL
PLL & Timing
Generator
ChannelLink
MUX 28 : 4
LVDS
FVAL
DVAL
uP
Control
LVDS
1920 x1080
5.0 x 5.0 um
Digital
Logic
MDR-26
SI-1920HD Camera Block Diagram
The image sensor PCB contains the CMOS sensor array with ADC, digital clock synthesizers, Register programming
interface and digital data bus. The Processor PCB board contains the power regulation, microprocessor, digital control
logic, and CameraLink transmission interface. The Cameralink interface allows programming via the serial interface
and image data transfer over high-speed multiplexed LVDS interface, both combined onto a single 26-pin MDR cable.
The +5VDC power is connected via a 3-pin screw-on locking connector.
2.1 Megapixel CMOS Image Sensor (1920 x 1080)
The MegaCamera SI-1920HD utilizes a proprietary 2.1 Million pixel high-speed CMOS image sensor. Each pixel is
5um Square, ideal for image processing, and the entire array fits the 2/3” format for flexible optic choices. This
reduction in process geometry allows for both an increase in transistors and fill factor without compromising
performance, plus offers more advanced readout controls, greater speeds and lower power dissipation.
This new sensor technology offers a more responsive pixel design with added circuitry for increased dynamic range,
greater sensitivity, decreased fixed pattern noise and low dark current for long exposure applications. Unlike CCD,
which leak charge to adjacent pixels when the registers overflows (blooms), the SI-1920HD provides inherent antiblooming protection in each pixel, so that there is no blooming.
 Silicon Imaging , Inc. 2004
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Company Confidential
The array has 1920 pixels on a line and 1080 rows, which result in a 16:9 aspect ratio. The sensor array design is
based on a field integration read-out system with line-by-line transfer and an electronic shutter with a synchronous
pixel read-out scheme (aka. Rolling Shutter Method). Other features include subsampling for reduced resolution with
a full field of view, ROI (region of interest) for reduced field of view and full resolution and individual gain controls for
each Bayer pixel to maximize dynamic range.
Analog Gain Amplifier
The analog gain amplifier consists of two stages – one stage that controls the gain of each pixel in a four-quadrant
Bayer color filter group individually and one stage for overall analog gain. This configuration provides easy gain
adjustment and white balance control for the maximum dynamic range from the camera.
Dual 12-Bit Digital Sampling System
Dual12-Bit Analog-to-digital (A/D) converters sample each pixel value and quantize it into 4096 levels inside the
sensor. Pixel clock sampling ensures precise measurement of the photonic charge without the jitter and sampling
uncertainty associated with traditional analog video systems, such as RS-170 and CCIR. This produces images
which can deliver improved photometry accuracy and sub-pixel metrology. The use of 12-bit converters versus
traditional 8-bit systems further enhances the image dynamic range. The combination of 12-bit vertical resolution and
pixel clock sampling provide precise sub-pixel measurement accuracy (ex. 1/10 pixel).
 Silicon Imaging , Inc. 2004
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Company Confidential
Digital Clock Synthesizer
A wide range a master clock frequencies (eg. 20 to 90MHz) can by precisely generated using the Digital Clock
Synthesizer. The Frame Grabber, which is used with the camera, must be capable of receiving dual tap12bit data at
75Mhz+ to achieve the highest data rates. Without any byte packing of the 12-bit word the data rate would be
150MHz or 300MB/sec (2pixel x 2bytes/pixel x 75MHz). In standard 32Bit/33MHz PCI computers the maximum data
rate directly to host memory is usually below 120MB/sec (from 132MB/sec bus) without system interrupts. However,
100MB/sec is more reasonable rate to achieve with other system devices operating (eg. display, clock, mouse etc.).
Under these condition the 12-bit data can be mapped to 8-bits/pixel to reduce the bus traffic or the clock rate can be
reduced to and still maintain 12bits per pixel. The frequency of the clock synthesizer can be set by serial command.
A table with associated clock frequency is found in the serial programming section of the manual. Due to minimum
frequency restriction on the CL digital transmission link, the pixel clock frequency cannot be lower than 20Mhz.
Embedded Microprocessor
A microprocessor in the camera provides the control interface between the PC and the functional block in the camera
(Sensor, Clock Synthesizer, Register Memory, Channel Link Interface & Serial port (CameraLink). The
Microprocessor receives commands thru the LVDS level serial port and issues commands to the other devices. It
also can store preset values for camera setting, which can be recalled with single ASCII character commands.
Several digital I/O or analog sampling signals are available on the processor from PCB header points for custom OEM
applications.
Dual 12-Bit CameraLink Interface (Base Configuration)
Camera Link is a new digital transmission method designed by imaging component manufacturers as an easy and
standard way to connect digital cameras to frame grabbers. The Camera Link specification includes greater than
1.2Gb/sec data transmission as well as camera control and asynchronous serial communications all on a single cable
with high-density 26pin connector. Only two connections are required to quickly interface your digital camera to a
multitude of frame grabbers. This standardization will ultimately reduce cost of high performance digital cameras
through open market competition and a simple migration path to faster and higher resolution systems.
As a standard that has been defined by industry members, Camera Link provides the following benefits:
•
Standard Interface: Every Camera Link product will use the same cable and signaling. Cameras and
frame grabbers can easily be interchanged using the same cable.
•
Simple Connection: Only two connections will be required to interface a camera and frame grabber:
Power and Camera Link.
•
Lower Cost: Because Camera Link is an industry-wide standard, consumers will be able to take
advantage of lower cable prices.
•
Smaller connectors & cables: The technology used in Camera Link reduces the number of wires
required to transmit data over traditional LVDS or RS-422 parallel interfaces, allowing for smaller cables.
Smaller cables are more robust and less prone to breakage.
•
Higher data rates: The technology used in Camera Link has a maximum data rate of 2.3GB/s, for use in
the most demanding high definition, high frame rate and line scan.
CameraLink Camera Signal (MDR-26 Cable)
This section provides definitions for the signals used in the Camera Link interface. The standard Camera Link cable
uses a MDR 26-pin connector (3M Part# 10226-6212VC) provides the following signaling:
 Silicon Imaging , Inc. 2004
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Company Confidential
• Video Data (4 Pairs using 28:4 Mux, 24 Video, 4 Control)
• Camera control signals (1 Pair)
• Serial communication (2 Pairs)
Video Data
The 24 bit image data (2 words x 12 bit) and 4 control bits are transmitted over only 4 differential pairs using a 28:4
multiplexer (National Semiconductor DS90CR285 Channel Link device). The Four enable signals are defined as:
• FVAL—Frame Valid (FVAL) is defined HIGH for valid lines.
• LVAL—Line Valid (LVAL) is defined HIGH for valid pixels.
• DVAL—Data Valid (DVAL) is defined HIGH when data is valid.
• Spare— A spare has been defined for future use.
All four enables are provided on the camera, via the Channel Link chip. The unused data bits are tied to a known
value by the camera. For more information on image data bit allocations, see page 11, CameraLink Base
Configuration Bit Assignment Configuration.
Serial Communication & CC-1 Triggering
Two LVDS pairs have been allocated for asynchronous serial communication to and from the camera and frame
grabber. Cameras and frame grabbers should support at least 9600 baud. These signals are
• SerTFG—Differential pair with serial communications to the frame grabber.
• SerTC—Differential pair with serial communications to the camera.
The serial interface operates at 9600 baud, one start bit, one stop bit, no parity, and no handshaking. For applications
requiring high serial throughput, such as real time windowing update at over 200FPS, the camera can support a serial
link mode at 57kbs (not specified in CameraLink spec). The frame grabber serial communication must be set to
match this speed.
Four LVDS pairs are reserved for general-purpose camera control. They are defined as camera inputs and frame
grabber outputs. Camera manufacturers can define these signals to meet their needs for a particular product. The
signals are:
• Camera Control 1 (CC1) - Used to do triggered image capture or Genlock operation
• Camera Control 2 (CC2) for external master clock (optional)
 Silicon Imaging , Inc. 2004
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Company Confidential
5VDC Power & Camera Control Signals
The SI1920HD camera is powered via +5VDC (~320mA) Regulated supply. Power is applied thru a 3-pin Tajimi (Part
#RO3-PB3M) connector and cable. The power cable (PC-2, 2 meter long) has a 3-pin connector on one end and
2.1mm female plug for use with standard transformers or the factory recommended (PS-5) 5VDC, 1AMP supply.
Tajimi RO3-PB3M – POWER CABLE
+5VDC Power Supplies
 Silicon Imaging , Inc. 2004
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Company Confidential
3-PIN POWER & TRIGGER INPUT WIRING
PhotoEye Trigger and Power Connection
 Silicon Imaging , Inc. 2004
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Company Confidential
Power-On Communication & Presets
Initial State
When the power is first applied to the camera the camera will load its default (Preset #1) settings and will be
generating live video and a serial status message. Preset #1 can be overwritten thru programming commands. Once
Preset#1 is overwritten it will be the new power-on default setting.
If the Frame Grabber supports a serial terminal mode the following menu will appear
100: Booted
108: CameraLink SI-1920 4.05.17
120:B6460514 Sensor tag
's' - status
Returns the firmware version, clock configuration word and Sensor Tag (camera s/n). Camera output example:
108: CameraLink SI1920 4.05.17
110:306882 Clock
120: B6460514 Sensor tag
Default Settings
When first turned on, the SI-1920HD will be in the default mode, which will be 30fps Full Frame Readout at 40MHz
master clock (Note this is default for the camera itself, which may be different than the default settings for the frame
grabber being used). See serial programming section for details on changing formats.
Full Resolution, 40MHz
Resolution =
Clock =
Frame Rate =
 Silicon Imaging , Inc. 2004
1920 x 1080
40MHz
32 FPS
Page 10 of 41
Company Confidential
Serial Communication & Protocol
The SI-3300 is capable of mode programming through its serial interface. Commands are sent from the CameraLink
frame grabber to the camera. The commands are processed by the micro controller and communicated to various
devices in the camera including the sensor, digital clock synthesizer and the Flash memory inside the microprocessor
itself.
The communication uses an asynchronous serial format, similar to RS232, but is transferred to the camera using
LVDS as part of the CameraLink interface specification.
Format:
Rate:
Data Bits:
Parity:
Interface:
Asynchronous, ASCII
9600
8 + 2 Stop bits
No Parity
Serial LVDS (thru CameraLink)
The baud rate is set to 9600 and 8 data bits with no parity. This is the format set by the CameraLink standard.
However, faster rates can be set by the factory and coordination with the Frame Grabber supplier.
Serial Commands
There are two types of commands Single character and Register String (multiple characters followed by Carriage
Return). Once the camera receives the string ending with a <CR> it will respond. For each command, there is a
corresponding action and response from the camera.
Single Character commands
“s”
Camera status including firmware version, clock configuration word, sensor tag and
CPLD configuration codes.
“f”
Arm single frame capture. Trigger frame capture & readout if already armed.
“h”
Change to high-speed serial mode for operation at 57.6kbaud
“d”
Register dump command. Outputs all common used register values.
*** Note: All commands must terminate with a <cr> (carriage return).
 Silicon Imaging , Inc. 2004
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Company Confidential
Register String commands
Each command may be entered through the Terminal communication mode from the frame grabber software. All
ASCII characters sent should be lower case and no spaces between characters. The string is terminated with a
carriage return <cr>. Hex numbers are sent as ASCII characters: 0Fh is sent as “0F” character. There are no spaces
between characters being sent in strings. These are multiple character string commands with a common format.
Register String Commands
Command
Description
Parameters
Response
lc xxxxxx <cr>
Load Clock Register
(See clock table)
xxxxxx = 6 hex values from table
114: Clock updated
ly rr xxxx <cr>
Load Sensor Registers
Loads registers 00 to ff with 16bit
values, which are sent as 4 ascii
characters representing hex
values.
Load 4 Gain & Black Offset
rr = register number 00~ff
xxxx = x0000~xFFFF
Registers vary from 8~12 valid bits
104: Sensor updated
The first two bytes of data, 4 bits
wide become the four color gains
and the third byte is set to all four
black references.
x=1
le1 = stores preset #1
x = 0 or 1
ld1 = boots camera with preset #1
106: Preset updated
lg xxxxbb <cr>
le x <cr>
ld x <cr>
Load EEPROM preset value
***overwrites factory values
Load Bootup Default
106: Preset updated
*** Note: All commands must terminate with a <cr> (carriage return). Hex characters are lower case, no spaces.
Load Sensor Command Format
The following registers for SI-1920HD control the sensor readout, timing and signal output levels. These are
programmed thorough ‘ly’ register commands. The register number is represented by 2 characters. All sensor
registers are 16 bits in length and are represented by 4 characters. The ASCII command format is:
ly rr xxxx <cr> rr = register number
xxxx = values 0000 to ffff
The ly stands for load sensor array and must be sent as lower case. The “rr” is the register to be changed. The
“xxxx”, “represents four HEX values that are to be loaded into each register. The sequence must end with a carriage
return <cr>.
The following is an example of a 10-character command string (there are
l y 8 0 0 0 6 4 <cr>
This command will load the Exposure register “80” with hex “0064”. The resulting value loaded into the Exposure
register is “0064” or 101 in decimal.
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Company Confidential
SI-1920HD Registers
IMAGE WINDOW
REGISTER DEFAULT DESCRIPTION
START COLUMN
xD8
0
Hstart = START COLUMN * 16 (Mod 2). Must be even number for 32 pixel steps.
Width = 16*(H - HStart + 2) for <126.
Width = 16*(HEnd - Start) + 24 for =126.
HStop = END COLUMN * 16 (Mod2)
Note: Must be even number for 32 pixel steps
Max Width at x7c only 24 pixels increment = 2008 (1936 Active + 72 Black)
Example: x7A = 16*(122+2) = 1984 (1936 Active + 48 Black)
END COLUMN
xD9
x7a
START ROW
xDA
0
END ROW
xDB
x79
Vstop = END ROW * 9. Range 1~121. Max = x79h (121 * 9 = 1089 row)
Vwindow = 9 (Vstop - Vstart) + DEADROWS + 9 (+3, if Black Rows Disabled)
DEADROWS (VB)
xCB
x0C
Extra rows in Vertical Blanking. Rows+1 added to Image Height. Range = 1~255
VBlanking = DEADROWS + 9 (+3 with black rows disabled).
DEADPIXELS (HB)
xA0
x0E
Extra Clocks in Row time
Horizontal Blanking = 4 * (DEADPIXELS) + 8*(SAMPLETIME+1) + 16.
SAMPLETIME
xD1
x20
Sampling time for pixels into column Buffers. Adds to Row blanking time
Sampling Time = (SAMPLETIME+1) * 8 pixel clocks
xCD
xCC
xAC
xA8
xA4
0
x01
0
x01
xE3
x80
0
Vstart = START ROW * 9.
Range: 0~120.
SYNC PULSES
FVAL STOP
FVAL START
LVAL STOP
LVAL START
INTERLACE TIMING
FVAL Pulse Low position within vertical blanking period set by DEADROWS (xCB)
FVAL Pulse High position within vertical blanking period set by DEADROWS (xCB)
LVAL Pulse Low position within vertical blanking period set by DEADPIXELS (xA0)
FVAL Pulse High position within vertical blanking period set by DEADPIXELS (xA0)
FVAL of 2nd Field to new line for Interlaced Mode Only.
EXPOSURE
EXPOSURE
Exposure holdoff in row times). Smaller values yield higher exposure.
Exposure = (Height - INTEGRATIONTIME) * Row_Time. Max = Height - 1.
GAIN & OFFSET CONTROL
ANALOG GAIN MODE
xF4
30
Gain Mode: Set by individual RGGB or Mono (all gains set by Green1 value)
x0032 = individual RGGB Gain.
x0030 = Mono Gain
GAIN (BLUE/GREEN1)
xEC
11
0db (0) to 24dB (8) in 3dB Steps. RegF4 (Mono vs RGGB)
Blue = (Bits 7~4). Green1 =(Bits 3~0); Mono = (Bits 3~0).
GAIN (GREEN2/RED)
x6C
11
0db (0) to 24dB (8) in 3dB Steps. RegF4 (Mono vs RGGB)
GREEN2 = Bits 7~4. RED =Bits 3~0.
PGA_GAIN
xEB
xF0
Column Gain Amplifier. (xF0~F6)
Note: Changes to this register requires readjusting Black level and FPN recalculation
BLACK - BLUE
xBE
x4B
Black Level Target Value - BLUE pixels. 9-bits. Range: x0000~01FF
BLACK - GREEN1
x3E
x4B
Black Level Target Value - GREEN1 pixels
BLACK - RED
xBC
x4B
Black Level Target Value - RED pixels
BLACK - GREEN2
x3C
x4B
Black Level Target Value - GREEN2 pixels
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Company Confidential
DIGITAL GAINS
DIGITAL GAIN (Course)
xB8
44
Digital Gain: '
-24db (0) to 66dB (15) in 6dB Steps.
Range: 0~15. 0db = x0004.
DIGITAL GAIN (FINE)
xB0
00
Digital fine gain: '
0db to 6dB in .0006dB Steps (1024)
Range: 0~1023
00
bits 7-4: vertical subsampling mode
bits 3-0: horizontal subsampling mode
0 = reading of all rows/columns
(full resolution)
1 = not reading every third row/column (2/3 resol.)
2 = reading every second row/column (1/2 resol.)
3 = reading every third row/column
(1/3 resol.)
SUBSAMPLING
SUBSAMPLING
xF3
ANALOG READOUT TIMING
time of Pixel Value to input caps of column buffers.
x20 (32) Transfer
Typ = 32. Min: 16 (Lower will limit full scale output)
Min (16) = READTIME * 8 = (2cycles * 4 pixles)
READTIME
xCF
NONOVERLAPTIME
xF2
00
FASTRESETTIME
xD2
00
HARDRESETTIME
xD4
5a
min x46
RESETTIME (SOFT)
xD3
x0a
min x01
READRESETTIME
xD0
00
SAMPLETIME
xD1
0f
Sampling Time of Column Buffer Outputs
Min = 10~16, Optimum = 16~20, Value > 16 with will have bandwidth reduced.
= SAMPLETIME * 8 ; (2cycle * 4pixel/cycle)
WAITTIME
xCE
00
End of Row delay Added to minimum row time. Set to 0
= WAITIME * 32 ; (8cycles * 4 pixles)
READOUT CONTROL3
 Silicon Imaging , Inc. 2004
xFB
x78
Only if the sampling of analog row takes longer than digital readout..
Latency for DNR in upper nible. Non-Overlap = 0
Time for reset of rows not being used in the subsampling Used for Subsampling in Vertical.
Resets all rows not being readout. Adds time prior to readout
If not 0, hardreset is performed before soft or tappered reset.
Min 70 (more image lag). Typical 90
= HARDRESETTIME * 4 (1cycles * 4 pixles)
Time for main SOFT reset (limit for reduced KTC noise). Typ: 32. Min 1 = higher ktc noise.
Could turn off BY set reg to 0AND also use control Reg F9.
= READTIME * 32 = (8cycles * 4 pixels)
Settling Time before the sampleTransfer time of Reset Value to column buffers.
At full window = 14~18. Give more settling time. At 0 not much effect.
= READRESETTIME * 8 ; (2cycle * 4pixel/cycle)
Controls interlaced and synchronization settings (x7X)
bit 0: enable interlaced readout mode
bit 1: enables sync. of first field by FRAMESYNC signal
bit 2: Overlap sampling of column buffers outputs
bit 3: enable FRAMESTART and LINESTART signals
Page 14 of 41
Company Confidential
Digital Clock Synthesizer Programming
The SI-1920HD has a Digital Clock Synthesizer capable of generating a range of frequencies from 20MHz to 85MHz.
Note: The pixel data output rate is 2x as the master clock rate, as 2 pixels (odd & even)are readout on each clock.
The clock frequency is set by the “lc” Register String command. A range of preset frequencies are listed below:
Note: Refer to factory for a lc command to achieve a custom targeted clock rate. Note: As of Jan, 2009, the SI1920 outputs in B,A tap order NOT A,B! Therefore, odd columns are readout on tap B and even on tap A. Frame
grabbers such as the Epix frame grabbers allow for tap order of B,A.
Command
lcxxxx <cr>
lc306886
lc30b689
lc37cb8f
lc35d40b
lc34d20f
lc306882
lc35e709
lc356e03
lc34b689
lc34b688
lc36cb8f
lc367307
lc36ee0f
lc36f88f
lc34ae05
lc346882
lc34C105
lc339B85
lc31c00f
lc31cb8f
Clock
Rate
MHz
20
25
30
35
37.12
40
45
48
50
55
60
65
70
73
75
80
83
84
85
90
Pixel Rate
MHz
40
50
60
70
75
80
90
96
100
110
120
130
140
146
150
160
166
168
170
180
Approximate SI-1920HD Frame Rate
1920 x 1080
1280 x 1017
640x477
320x234
128 x 126
89
231
452
422
24
30
60
66
72
946
Sample Command:
The clock frequency is programmed by the “lc” command with by 6 HEX characters. An example is:
“lc36cb8f <cr>” Sets clock to 120MHz. The response to command is: 114: Clock updated
There are multiple settings to achieve each frequency. Some might be better than others for a particular application.
May experience increase in noise (saturated pixels) in 62-82mhz range, therefore, for maximum frame rates it may be
best to set pixel clock rate to 83-85, 90mhz.
 Silicon Imaging , Inc. 2004
Page 15 of 41
Company Confidential
Frame Rate Calculation
To calculate the frame rate for any clock rate the equation is estimated by:
)
(
clock rate(Hz) x2
( # of columns + 216) * ( # of rows +9)
=
# Frames Per Second (fps)
Example: What is the frame rate, at 37.5MHz clock rate for an image size of 1920 x 1080 with extra horizontal and
vertical blanking to get a total of 2200 x 1125?
37.12 x 106 x 2
= 30 Frames Per Second (fps)
((1920 + 64) + 216) * (1080 + 36+9)
Noise Correction (FPN and PRNU correction)
CMOS image sensors such as the one used in the SI-1920 MAY suffer from something called FPN (fixed pattern
Noise). Because of the processing and the pixel design of the sensor, all pixels have small offset differences
when compared to each other. This can corrected by subtracting a dark frame (which also contains these fixed offset
differences) on a pixel by pixel basis.
The noise can be corrected as follows (calibration):
Vn = Gn - Bn
Vn is Data of a pixel after a calibration/correction
Gn is Data of a pixel before carrying out a calibration
Bn is;Black calibration data of the pixel
Typical the black calibration image is acquired with no ambient light reaching sensor by covering the lens
Another type of noise is called PRNU (pixel response non uniformity) and it is caused by the difference in gain from
pixel to pixel. It basically means that pixels will respond in a different way to the same amount
of light. This can also be easily corrected. FPN and PRNU correction:
Vn = ( 256 / [ Wn - Bn + 1 ] ) x ( Gn - Bn )
Vn is Data of a pixel after a calibration
Gn is Data of a pixel before carrying out a calibration
Bn is Black calibration data of the pixel
Wn is White(Gray) calibration data of the pixel
This correction should be performed on a pixel by pixel. To have the white and black calibration data you should take
a black image first (cover the sensor, but make sure no value is absolute zero) and second take a grey image
(between 70% and 100% of illumination).
Software from frame grabber manufacturers such as Epix provide this correction with their camera software
(NORM tab in Xcap Capt & Adjust).
 Silicon Imaging , Inc. 2004
Page 16 of 41
Company Confidential
Pixel Arrangement
All active pixels are spaced horizontally and vertically on 5 micron pitch. This results in a 16:9 format comprising
1936 by 1086 active pixels, as illustrated in the drawing. Each line of video is bordered by the appropriate blanking
consistent with SMPTE 274M.
+ !'
,- . . / 0
/ 0
1
→
%
2 3
# $ %
Row_Time
Width
=
=
Horiz Blanking =
Frame_Time =
Height
=
Vert Blanking =
! "
& ' ( )*
Width + Horizontal Blanking * Clock_Rate
16*(Hstop - HStart + 2) for Hstop-Hstart < 126 + Horiz Blanking
16*(Hstop - HStart) + 24 ;for Hstop-Hstart =126 + Horiz Blanking
4 * (DEADPIXELS) + 8*(SAMPLETIME+1) + 60
Front Porch = 4 * (DEADPIXELS) + 60
Back Porch = 8 * (SAMPLETIME+1)
Height (rows) * Row_Time
9 (Vstop - Vstart) + VBlanking
DEADROWS + 8 (+3 with black rows disabled)
Note: Min Row_Time is set by Analog Readout time (min default = ~1100)
FRAME & ROW READOUT
TIMING
 Silicon Imaging , Inc. 2004
Page 17 of 41
Company Confidential
Dead
Rows
Dead
Rows
VWindow
BackPorch
Back Porch
VWindow
FrameStart
LineStart
VIDEO
Video
Video
Video
Dead Rows
Dead Rows = Dead Rows Register + 1
Vwindow (line periods) = 9(Vstop – Vstart)
Back Porch = 7 if Black rows enabled
= 1 if Black rows disabled
FrameSyncStart
FrameSyncStop
Note: Dead Rows register counts down.
FrameSyncStart <= Dead Rows
FrameSyncStop < Dead Rows
FrameSyncStart > FrameSyncStop
Analog Readout Time (pixel periods) = 8(SampleTime) + 32(ResetTime) + 4(HardResetTime) + RowWaitTime + 4(NonOverlapTime) + 8(ReadResetTime) + 96
Where RowWaitTime = 32(WaitTime) – 4 when WaitTime > 0
Else WaitTime = 0
Front
Porch
Dead
Pixels 60 Pixels
HWindow
Front
Porch
Dead
Pixels 60 Pixels
HWindow
LineStart
VIDEO
Video
Video
Video
Front Porch (pixel periods) = 8*SampleTime + 8
Dead Pixels
Dead Pixels = Dead Pixels Register
Hwindow (pixel periods) = 16(Hstop – Hstart + 2)
for Hstop and Hstart even and < 126
Hwindow (pixel periods) = 16(Hstop – Hstart) + 24
for Hstop and Hstart even
and Hstop = 126
Note: If Analog Readout Time > Digital Readout,
then Front Porch Increases to complete Analog
Readout
LineSyncStart
LineSyncStop
Note: Dead Pixels register counts down.
LineSyncStart <= Dead Pixels
LineSyncStop < Dead Pixels
LineSyncStart > LineSyncStop
Vwindow (row times) = 9(Vstop-Vstart) + Deadrows Register + 8 (for black rows enabled)
Vwindow (row times) = 9(Vstop-Vstart) + Deadrows Register + 2 (for black rows disabled)
 Silicon Imaging , Inc. 2004
Page 18 of 41
Company Confidential
Window Programming – Image Size & Position
Windowing is directly supported with programming resolution of 32 columns in the horizontal
direction and 9 rows in the vertical direction. The maximum frame rate of the subwindow is
given by 148.5 MHz divided by the number of pixels in the window or the minimum analog
row sampling time, whichever is larger. The smaller window reflects a smaller effective
format. For example, a 1280 x 720 window corresponding to the 720p standard is supported
at 120 frames per second.
Hstart = START COLUMN * 16 (Mod 2). Must be even number for 32 pixel steps.
Width = 16*(Hstop - HStart + 2) ; for Hstop-Hstart < 126
Width = 16*(Hstop - HStart) + 24 ; for Hstop-Hstart =126
START COLUMN
xD8
0
END COLUMN
xD9
x7a
START ROW
xDA
0
END ROW
xDB
x79
Vstop = END ROW * 9. Range 1~121. Max = x79h (121 * 9 = 1089 row)
Height = 9 (Vstop - Vstart) + DEADROWS + 8 (+3, if Black Rows Disabled)
DEADROWS (VB)
xCB
x1C
Extra rows in Vertical Blanking. Rows+1 added to Image Height. Range = 1~255
VBlanking = DEADROWS + 8 (+3 with black rows disabled).
DEADPIXELS (HB)
xA0
x05
Extra Clocks in Row time
Horizontal Blanking = 4 * (DEADPIXELS) + 8*(SAMPLETIME+1) + 60.
SAMPLETIME
xD1
x20
Sampling time for pixels into column Buffers. Adds to Row blanking time
Sampling Time = (SAMPLETIME+1) * 8 pixel clocks
Hstop = END COLUMN * 16 (Mod2). Must be even number for 32 pixel steps.
Max Width at x7c only 24 pixels increment = 2008 (1936 Active + 72 Black)
Example: x7A = 16*(122+2) = 1984 (1936 Active + 48 Black)
Vstart = START ROW * 9.
Range: 0~120.
Column Stop
Column Start
column
Row Start
Row Stop
Row
Display Window
ROI
+
To set a window size of 640 x 486 in upper corner.
ly d8 00xx
ly d9 00xx
ly da 00xx
ly db 00xx
Set START COLUMN to 0
Set END COLUMN to 640/16=40 Mod2
Set START ROW to 0
Set END ROW to 486/9 =54
(0x0000)
(0x0028)
(0x0000)
(0x0036)
Note: Other custom commands can be used to move the window at high speeds – please consult the factory.
 Silicon Imaging , Inc. 2004
Page 19 of 41
Company Confidential
Camera & Sync Timing
Camera timing (e.g. delays between sync pulses and first visible pixel/row) is programmable and can be adapted to
different standards. (e.g. to comply with the HDTV video standard). The vertical and horizontal blanking can be
extended using DEADROWS (xCB) and DEADPIXELS (xA0). In addition, the starting position of the FVAL and LVAL
sync signals can be moved within this extended blanking period.
FVAL STOP
FVAL START
LVAL STOP
LVAL START
INTERLACE TIMING
xCD
xCC
xAC
xA8
xA4
0
x01
0
x01
xE3
FVAL Pulse Low position within vertical blanking period set by DEADROWS (xCB)
FVAL Pulse High position within vertical blanking period set by DEADROWS (xCB)
LVAL Pulse Low position within vertical blanking period set by DEADPIXELS (xA0)
FVAL Pulse High position within vertical blanking period set by DEADPIXELS (xA0)
FVAL of 2nd Field to new line for Interlaced Mode Only.
Progressive Timing
Interlaced Timing
In the Interlaced mode, the entire image array is read in two sequential fields. The image sensor generates a valid
output on each edge of CLK, the image sensor clock. Yet again the pixels are sequentially read, column per column
and line per line. However, contrary to progressive mode operation, the odd rows are read in the first field and the
even rows are read in the second field.
 Silicon Imaging , Inc. 2004
Page 20 of 41
Company Confidential
Electronic Shutter
EXPOSURE
x80
00
Exposure holdoff in row times). Smaller values yield higher exposure.
Exposure = (Height - INTEGRATIONTIME) * Row_Time. Max = Height - 1.
The integration time can be adjusted electronically. This is commonly referred to as "electronic shutter". By default,
the SI-1920HD camera uses the maximum possible integration time, i.e., the frame time. In order to reduce the
integration time, the internal register Exposure Time must be appropriately programmed, i.e., no longer automatically
set to the default value.
Exposure_Time =
Row_Time
=
(Height – Exposure (x80)) * Row_Time
HWindow + Horizontal Blanking (~216) * Clock_Rate
Note: Min Row_Time is set by Analog Readout time (min default = ~1100)
NOTE: Exposure Time value must be set less than the total number of rows per frame or video output will stop
For interlaced readout operation, the effective integration time tint can be calculated as follows:
if bit 10 of Exposure Time is 0:
tint = 2 * field time – (Exposure Time * row time)
if bit 10 of Exposure Time is 1:
tint = field time – (Exposure Time * row time)
For 1080/60i operation, the frame time is 33 ms, the field time is 16.67 ms, and the corresponding row time is about
30µs. Please note that the sensor stops operating properly once tint becomes “negative”. Per SMPTE 274M, there are
1125 rows per frame, so setting Exposure Time to 0, i.e., zero row times of dead time, produces approximately 1125
row times of integration. While the programmed integration time will approximate the full frame time of 30 ms, pixel
reset consumes a fraction of a row time so the actual integration is slightly less than the full frame time of 1125 LS
periods.
Setting bit 10 to logic “0” limits the range in integration from as long as 1 frame time to as short as 1 field time. Setting
bit 10 to logic “1” hence reduces the maximum integration time to one field time and the minimum to zero. Please note
that the sensor stops operating properly once tint becomes smaller than one field time (if bit 10 = 0) or negative (if bit
10 = 1). Therefore, the user has to ensure that the lower 9 bits of Exposure Time stay below a certain limit
corresponding to the total number of rows per field.
In interlaced mode, the integration time can be adjusted to half the frame time by increasing the Exposure Time
register to about 562 (1/2 of 1125). For further increase in shutter speed, the 10th bit of the Exposure Time register
has to be set. At the same time, the lower bits (9 - 0) have to be reset to 0. Further increase of the lower bits 9 - 0 will
not result in the desired increase of shutter speed.
For example, to program the Exposure Time register in interlaced 1080i mode:
x8000: 1 frame (2 fields) integration time
1/30 s shutter
x8001: 1 frame (2 fields) - 1 row integration time
(1/30 - 1/33750) = 1124/33750 s shutter
…
x8232: 1 frame (2 fields) - 562 rows integration time
(1/30 - 562/33750) = 563/33750 shutter
x8400: 1/2 frame (= 1 field) integration time
562/33750 = approx. 1/60 shutter
x8401: 1/2 frame (= 1 field) - 1 row integration time
(562/33750 - 1/33750) = 561/33750 shutter
...
x8631: 1/2 frame (= 1 field) - 561 rows integration time
562/33750 - 561/33750 = 1/33750 shutter (1 row time)
 Silicon Imaging , Inc. 2004
Page 21 of 41
Company Confidential
Integration and Readout with External Mechanical Shutter or Strobe
SI-1920HD can be used with and external mechanical shutter or strobe by setting the Exposure reg to 0 for full frame
intagration. At the beginning of FVAL, all rows will be integrating, at which time a mechanical shutter and/or strobe
can be used to expose the entire imager. Several row times later, after the vertical blanking period, the valid exposed
image will begin readout. The "DEADROWS" vertical blanking register (xCB) can be setup to 255 to extended the
valid range. At the nominal pixel rate of 148.5 MHz the period for all rows integrating would be 3.79ms (256 × 14.8 µs
= 3.79ms).
Single-Frame Capture (‘f’ Mode)
The ‘f’ command stops the video output and waits for a CC-1 or Aux-TTL to capture and output a single frame of
video. In this mode, the camera internally continues to expose and readout frames. At the next top-of-frame, after
trigger, the exposed image is transferred with FVAL/LVAL signals. A strobe signal can be applied at the start of FVAL
to expose the entire frame being readout, with Exposure set to full frame time (Reg 80 set to x0000). When using
“camera direct” trigger input (trigger provided via trigger-in pin on 3 pin power Tajimi connector), the trigger is “edge”
triggered (as opposed to voltage level triggered). Every time trigger-in signal is pulled to ground a single image will be
acquired.
Genlock Operation (‘g’ Mode)
The normal mode of camera operation is free running where the start of Frame is not synchronized. A Slave or
Genlock mode is provided, where the frame timing is controlled by externally generated synchronization pulses using
CC-1 Triggers. When Register 80 is set to x0000 for full frame time exposure, the exposure time is determined by the
time between triggers. When using “camera direct” trigger input (trigger provided via trigger-in pin on 3 pin power
Tajimi connector), the trigger is “level” triggered (as opposed to edge triggered). Sinking trigger input to ground will
result in continuous image acquisition.
 Silicon Imaging , Inc. 2004
Page 22 of 41
Company Confidential
ANALOG & DIGITAL GAIN
There are three methods of gain control within the SI-1920HD; Analog Pixel Gain, Global PGA gain, and Digital Gain.
A block diagram is as follows:
Col amp 1
Analog
PGA
Control
1920 x 1080
Sensor Array
Col amp 2
12 bit
A/D
Converter
Col amp 3
Digital
Gain
Adjust
24 Bits
(2ch @ 12 bit)
12 bit
A/D
Converter
Col amp 4
The first method, Analog Gain (Reg xEC, x6C), can be used to set the individual bayer pixel gains (R, G1, B, G2) as a
first step of color image white balance. By doing the initial coarse white balance gains on the analog pixel signals in
the column, the maximum dynamic range is maintained. For Monochrome operation, the Green1 value can be used
to set all 4 amplifiers simultaneously ( Reg xF4 to 30).
GAIN & OFFSET
REGISTER DEFAULT DESCRIPTION
ANALOG GAIN MODE
xF4
30
Analog Gain Mode: Set by individual RGGB or Mono (all gains set by Green1)
x0032 = individual RGGB Gain.
x0030 = Mono Gain effects all 4 gain channels
BLUE /GREEN1 GAIN
xEC
11
Analog Gain: '
0db (0) to 24dB (8) in 3dB Steps. RegF4 (Mono vs RGGB)
Blue = (Bits 7~4). Green1 =(Bits 3~0); Mono = (Bits 3~0).
GREEN2 / RED GAIN
x6C
11
Analog Gain: '
0db (0) to 24dB (8) in 3dB Steps. RegF4 (Mono vs RGGB)
GREEN2 = Bits 7~4. RED =Bits 3~0.
The PGA amplifier (xEB) can also be used to adjust overall signal amplitude. However, a change to the PGA will shift
the signal range into the ADC. Therefore, the Black Level settings (xBE, x3E, xBC, x3C) will need to be readjusted
and FPN black column offset memory will require automatic recalibration time.
PGA GAIN
xEB
xF0
Column Analog Gain Amplifier. (xF0~F6)
Note: Changes to register requires readjusting Black level and FPN recalculation
BLACK - BLUE
xBE
x48
Black Level Target Value - BLUE pixels
BLACK - GREEN1
x3E
x48
Black Level Target Value - GREEN1 pixels
BLACK - RED
xBC
x48
Black Level Target Value - RED pixels
BLACK - GREEN2
x3C
x48
Black Level Target Value - GREEN2 pixels
Once the analog values are digitized by the 12-bit ADCs the resulting Digital data can be amplified in the digital
domain using Registers xB8 and xB0. The Digital gain can improve the visual quality of the captured images, but have
no direct change of the images dynamic range or noise.
DIGITAL GAIN (Course)
xB8
x44
DIGITAL GAIN (FINE)
xB0
0
Digital Gain: '
-24db (0) to 66dB (15) in 6dB Steps.
Range: 0~15. 0db = x0004.
Digital fine gain: '
0db to 6dB in .0006dB Steps (1024)
Range: 0~1023
It is also possible to set all four analog gains and black offset with a single command ‘lgxxxxbb <cr>’:
lg xxxxbb <cr>
Load Gain & Black Offset
 Silicon Imaging , Inc. 2004
The first two bytes of data, 4 bits wide become the four color gains
and the third byte is set to all four black references.
Page 23 of 41
Company Confidential
Sub-Sampling Readout
Subsampling can be used to readout fewer pixels in the imager at increased frame rates. Four subsampling modes to
provide 1.5X, 2X, 3X and 4X lower resolution in each the vertical and horizontal directions:
Due to the use of bayer patterns, only the 3x subsampling cab be used to produce a color image
SUBSAMPLING
 Silicon Imaging , Inc. 2004
xF3
00
bits 7-4: vertical subsampling mode
bits 3-0: horizontal subsampling mode
0 = reading of all rows/columns
(full resolution)
1 = not reading every third row/column (2/3 resol.)
2 = reading every second row/column (1/2 resol.)
3 = reading every third row/column
(1/3 resol.)
Page 24 of 41
Company Confidential
Secondary Registers (For Factory Use)
2 " '
4
) ..
* '
* 5 & '
6 0!
'
HOTLEVEL
x88
10001
11 bits
256
sets the difference level which has to be exceeded for detecting a "hot
pixel"
DNR_OFFSET_BOT
x9
1001
12 bits
512
Sets the offset between high gain and low gain transfer curve of the
bottom readout chain
DNR_OFFSET_TOP
x1
0001
12 bits
512
Sets the offset between high gain and low gain transfer curve of the top
readout chain
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1
0
0
1
1
1
1
1 bit
1
CONTROL3
- INTERLACED
- INTERSYNC
- PARALLELREAD
- SYNCOUT_EN
- SYNCTIMINGF_EN
- SYNCTIMINGL_EN
- LINESYNC_ALW.
xFB
11111011
- ROWNUMBEREVEN
CONTROL6
- HOTPIX_EN
- LOWJITTER
- AUTOADJUST
- ANAMUX_EN_BOT
- ANAMUX_EN_TOP
- ANAPERMAN_BOT
- ANAPERMAN_TOP
- PD_OUTPUTBUF
.
controls interlaced and synchronization settings
bit 0: enable interlaced readout mode
bit 1: enables sync. of first field by FRAMESYNC signal
bit 2:
bit 3: enable FRAMESTART and LINESTART signals
bit 4: enable timing settings for FRAMESTART
bit 5: enable timing settings for LINESTART
bit 6: always generate LINESYNC pulse, even if the current line
contains no pixels
bit 7: used for interlaced only, ensures correct timing in case of even
and odd number of lines, respectively
.
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1
0
1
0
0
0
0
1
controls defect pixel elimination
bit 0: enable "hot pixel" elimination
bit 1:
bit 2: automatically adapt hot/dead level to sel. gain
bit 3:
bit 4:
bit 5:
bit 6:
bit 7:
CONTROL8
SINGLE_OUTPUT
- RGB_GAIN
- ADDROW
xF4
- UNUSED
11110100
- PGA_RST_ALWAYS
- CLKDIVIDE1
- CLKINVERT
- CLKDIVIDE2
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
1
0
0
0
1
1
0
1
controls miscellaneous sensor settings
bit 0:
bit 1: enable separate gains for each RGB color
bit 2: For binning mode-not supported
bit 3:
bit 4: resets analog PGA every row (vs. once per frame)
bit 5:
bit 6:
bit 7:
FPN_CTRL
- STEPSIZE
- LARGESTEP_REF
- FPN_MEMRST
x72
4 bits
3 bits
1 bit
2
4
0
Controls FPN offset evaluation settings
bit 3-0: adjustment step size per cycle in 1/8 LSB
bit 6-4: threshold for large adjustment step (exponential)
bit 7: if active, FPN offset memory is reset to 0
x73
8 bits
128
FPN_REFOFFSET
 Silicon Imaging , Inc. 2004
xFE
11111110
Sets the offset reference for the automatic FPN correction
Page 25 of 41
Company Confidential
SI-1920 Gamma Curve
Video Before Gamma
0-255
256-639
640-1791
1792-4095
Gamma Equation
4x
2x + 512
x + 1152
x/2 + 2048
Output video
0-1020
1024-1791
1792-2943
2944-4095
4500
4000
3500
3000
2500
2000
1500
1000
500
0
0
500
1000
1500
2000
2500
3000
3500
4000
4500
To enable/disable gamma send the following command:
ly7000c0 <cr>
ly700040 <cr>
 Silicon Imaging , Inc. 2004
Enables gamma Curve (on)
Disables gamma Curve (off)
Page 26 of 41
Company Confidential
Response Codes
000:XXXX
Sensor Chip ID. This is sent at boot time, and also when the status
command is issued.
0XX:XXXXXX...
Sensor registers. This message gives the address and contents of a chip
register. 16 bytes of register data will be sent on each line.
100: Booted
This is the first string sent when the Camera boots. It will later be
augmented with a firmware version number.
102: Default loaded
A message sent a boot time after the sensor and clock have been
programmed.
104: Sensor updated
A response that follows the "ly..." command.
106: Preset updated
A response that follows the "le..." command.
108: CameraLink SI-3300
2.12.30
Output by the ‘s’ status command.
Identifies the camera model, interface and firmware version
110: XXXXXX
Output by the ‘s’ status command. It gives the current clock setting.
Clock
114: Clock updated
A response that follows the "lc..." command.
120: XXXX
Output by the ‘s’ status command. It provides the factory serial number.
Sensor Tag
152: serial to 57.6kbaud
Response to an ‘h’ command
159: serial rate fault
A serial framing error occurred in high-speed serial mode. Camera will
return to default 9600 baud.
190: XXXX Configuration
Code
Output by the ‘s’ status command. It gives the current configuration.
501: Unrecognized
Command
The first character of the command line input is unrecognized.
503: Invalid Input
There are multiple forms of the 503 message code. They represent invalid
input other then the command specifier, such as "ly..." commands which
include to many characters of input, or not enough to fill the specified data
byte count.
Further input was given while the camera was still processing the previous
input
505: busy
601: Loaded preset #1
A response to “1” command. Preset #1 was loaded.
605: help menu
All of the lines of the help menu begin with code 605.
 Silicon Imaging , Inc. 2004
Page 27 of 41
Company Confidential
702: Single frame
This message is sent after the camera enters single frame mode, and again
after each frame is sent.
703: Leave single frame
This message is sent after the camera exits single frame mode and enters
continuous frame mode.
802: Dual Slope
This message is sent after the camera enters dual slope synchronous
shutter mode
803: Leaving Dual Slope
This message is sent after the camera exits dual slope synchronous shutter
mode and enters continuous frames normal rolling shutter mode.
Binary to Hex (ASCII) Table
Binary
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
 Silicon Imaging , Inc. 2004
Hex in ASCII
0
1
2
3
4
5
6
7
8
9
a
b
c
d
e
f
Page 28 of 41
Company Confidential
SI-1920HD
CameraLink Frame Grabber
Hardware Interface Notes
1.
Data Configuration – 12bits x Dual-Tap
A & B outputs each transmit 12 bits of data.
2.
LVDS Serial Interface
The standard data rate is 9600 baud. (Faster rates, up to 57kbps can be programmed).
3.
CC-1 Trigger Interface
The camera is armed for capture modes via serial command. The CC-1 trigger is used to start the snap exposure for
single frame or live genlocked video output in.
4.
PCI Bandwidth
The camera can operate at 150 Million Pixels per second. In 8-bit mode, this equates to 150MB/sec a sustained data
rate, exceeding the PCI-32 bus bandwidth. In 12-bit mode, where 2 bytes per pixel are typically used, the maximum
rate is 300MB. The data rate can be adjusted thru the on-board clock synthesizer.
 Silicon Imaging , Inc. 2004
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Company Confidential
CameraLink Connection
MegaCamera to Frame Grabber Interface
26-PIN
26-PIN
CONNECTOR CONNECTOR
FROM
FRAME
CAMERA
GRABBER
SIGNAL NAME
PAIR
X0-
1-
2
25
X0+
1+
15
12
X1-
2-
3
24
X1+
2+
16
11
X2-
3-
4
23
X2+
3+
17
10
X3-
5-
6
21
X3+
5+
19
8
Xclk-
4-
5
22
Xclk+
4+
18
9
SerTC-
6-
20
7
SertTC+
6+
7
20
SerTFG-
7-
8
19
SerTFG+
7+
21
6
CC1-
8-
9
18
CC1+
8+
22
5
CC2- (NC)
9-
23
4
CC2+ (NC)
9+
10
17
CC3- (NC)
10-
11
16
CC3+ (NC)
10+
24
3
CC4- (NC)
11-
25
2
CC4+ (NC)
11+
12
15
Gnd
Gnd
1
1
Gnd
Gnd
13
13
Gnd
Gnd
14
14
Gnd
Gnd
26
26
MDR-26 Connector
The camera uses the standard 3M MDR-26 connector specified in CameraLink specifications.
 Silicon Imaging , Inc. 2004
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Company Confidential
12-Bit CameraLink
Base Configuration Bit Assignment
CameraLink
Port Assignments
PORT/BIT
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
C0
C1
C2
C3
C4
C5
C6
C7
12-bit x 2Ch
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
B8
B9
B10
B11
B0
B1
B2
B3
B4
B5
B6
B7
National
DS90CR285MTD
Signal
Name
RX-00
RX-01
RX-02
RX-03
RX-04
RX-05
RX-06
RX-07
RX-08
RX-09
RX-10
RX-11
RX-12
RX-13
RX-14
RX-15
RX-16
RX-17
RX-18
RX-19
RX-20
RX-21
RX-22
RX-23
RX-24
RX-25
RX-26
RX-27
RX-CLK
Bit
Name
DO-0
DO-1
DO-2
DO-3
DO-4
DO-5
DO-6
DO-7
DO-8
DO-9
DO-10
DO-11
DE-8
DE-9
DE-10
DE-11
DE-0
DE-1
DE-2
DE-3
DE-4
DE-5
DE-6
DE-7
DE = Even Pixels DO = Odd Pixels
The ODD and EVEN Outputs
are identical on the SI-3300.
Camera
Data Bit
DO-00
DO-01
DO-02
DO-03
DO-04
DO-07
DO-05
DO-08
DO-09
DO-10
DE-10
DE-11
D-11
DE-08
DE-09
DE-00
DE-06
DE-07
DE-01
DE-02
DE-03
DE-04
DE-05
SPARE
LVAL
FVAL
DVAL
DO-06
RX-CLK
Channel Link
Pin
27
29
30
32
33
34
35
37
38
39
41
42
43
45
46
47
49
50
51
53
54
55
1
2
3
5
6
7
26
The following are the pin numbers for the 28 signals
output from the National Semiconductor Channel
Link chip on the Frame Grabber:
 Silicon Imaging , Inc. 2004
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Company Confidential
Channel Link Interface
CameraLink Cable
CameraLink Cable Ordering
 Silicon Imaging , Inc. 2004
Page 32 of 41
Company Confidential
FRONT VIEW
REAR VIEW
SENSOR PACKAGING
RGB Color Filter Pattern
The SI-1920HD is available as monochrome or color using a Bayer filter array. To properly perform color mosaic
processing of bayer pattern, please note that pixel (1,1) is green, pixel (1,2) is blue, pixel (2,1) is red and pixel (2,2) is
green. The starting phase relationship can change in an image when performing electronic windowing.
RGB Bayer Pattern
 Silicon Imaging , Inc. 2004
Page 33 of 41
Company Confidential
SI-1920HD-CL ENCLOSURE DIMENSIONS
 Silicon Imaging , Inc. 2004
Page 34 of 41
Company Confidential
Conversion Gain and Dynamic Range Setup
The camera can be specifically tuned to minimize read noise, maximize dynamic range, set the conversion factor,
maximize linearity or to generally optimize overall performance. The nominal programming settings, result in
conversion factor of ~11 e-/LSB, as shown in the next figure for 1080/60p operation. Adjusting the gain and the ADC
input range for alternative optimizations enables tuning the sensor to decrease conversion factor or widen the imaging
dynamic range.
Quantum Efficiency with standard microlens and cover glass.
Square Wave MTF
1.0
Nyquist
0.8
0.6
0.4
650nm
550nm
450nm
0.2
0.0
0
500
1000
Horizontal Lines
1500
2000
Horizontal MTF with standard microlens and cover glass
 Silicon Imaging , Inc. 2004
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Company Confidential
Image Sensor electro-optical characteristics
Quantum efficiency and horizontal MTF for the base sensor configuration with standard microlens and cover glass are
shown in the next figures. Bare sensors without microlens and color filter have peak quantum efficiency >40% at 620
nm.
RGB Color Filter Pattern
The SI-1920HD color camera uses a standard Bayer color filter array. The minimum spectral characteristics of the
red, green, and blue bands are shown in the accompanying figure.
 Silicon Imaging , Inc. 2004
Page 36 of 41
Company Confidential
Cropped Still Capture of High Definition Test Pattern for 2/3-inch Format (JPEG)
 Silicon Imaging , Inc. 2004
Page 37 of 41
Company Confidential
16-bit Digital Still Capture from Monochrome Sensor (JPEG)
 Silicon Imaging , Inc. 2004
Page 38 of 41
Company Confidential
Cropped 1280 by 720 Digital Still Capture of Color Test Pattern from RGB Sensor
 Silicon Imaging , Inc. 2004
Page 39 of 41
Company Confidential
www.siliconimaging.com
[email protected]
SI-1920HD-M-CL
SI-1920HD-RGB-CL
SI-1920HD-M-S
SI-1920HD-RGB-S
PS-5
PC-2
CBL-3PT
2.1 Megapixel MegaCamera, Monochrome, Cameralink Camera
2.1 Megapixel MegaCamera, Color, Cameralink Camera
2.1 Megapixel, Monochrome, Cameralink Frame Grabber, Power Supply & Cables
3.2 Megapixel, Color Cameralink Frame Grabber, Power Supply & Cables
5VDC Power Supply
Power Cable, 2-Meter
Cable, 3Pin Tajimi to TTL Trigger-In & Power Input Plug
Silicon Imaging reserves the right to make changes to its products or to discontinue any product or service without notice, and advises customers to
obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. No license,
express or implied to any intellectual property rights is granted by this document.
Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR
SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SILICON IMAGING PRODUCTS ARE NOT DESIGNED,
AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL
APPLICATIONS. INCLUSION OF SILICON IMAGING PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE
CUSTOMER'
S RISK.
The Product described in this datasheet may contain design defects or errors known as errata which may cause the product to deviate from
published specifications. Current characterized errata are available upon request.
Copyright: Silicon Imaging, Inc., 2004
050804-Rev 0.7
 Silicon Imaging , Inc. 2004
Page 40 of 41
Company Confidential
 Silicon Imaging , Inc. 2004
Page 41 of 41
Company Confidential
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