LP3997 Micropower 250mA CMOS LDO Regulator with Error Flag

LP3997 Micropower 250mA CMOS LDO Regulator with Error Flag
LP3997
Micropower 250mA CMOS LDO Regulator with Error
Flag / Power-On-Reset
General Description
The LP3997 regulator is designed to meet the requirements
of portable, battery-powered systems, providing accurate
output voltage, low noise, and low quiescent current. The
LP3997 provides 3.3V output at up to 250mA load current.
The chip architecture is capable of providing output voltages
as low as 0.8V. When switched in shutdown mode, the
power consumption is virtually zero.
The LP3997 is designed to be stable with space saving
ceramic output capacitor as small as 1µF.
The LP3997 also includes an out-of-regulation error flag.
When the output is more than 5% below its nominal voltage,
the error flag sets to low. If a capacitor is connected to
device’s delay pin, a delayed power-on reset signal will be
generated.
Features
n Low, 140mV, Dropout at 250mA Load.
n Stable with Ceramic Capacitor.
n
n
n
n
n
Low Noise, with Bypass Capacitor.
Less than 80µA Typical IQ at 250mA.
Virtually Zero IQ (Disabled).
Thermal and Short Circuit Protection.
3.3V Output.
For other voltage options contact your NSC sales office
Package
8 Lead MSOP
For other package options contact your NSC sales office.
Applications
n
n
n
n
n
Portable Consumer Electronics
Cellular Handsets
Laptop and Palm Computers
PDA’s
Digital Cameras
Typical Application Circuit
20092901
© 2005 National Semiconductor Corporation
DS200929
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LP3997 Micropower 250mA CMOS LDO Regulator with Error Flag / Power-On-Reset
May 2005
LP3997
Functional Block Diagram
20092908
Pin Descriptions
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Pin #
Name
Description
1
CBYP
Noise bypass pin. For low noise applications a 0.1µF or larger ceramic
capacitor should be connected from this pin to ground. This will also improve
PSSR.
2
DELAY
3
GND
4
VIN
A capacitor connected from this pin to ground will allow a delayed
power-on-reset signal at the ERROR (pin 7) output. See Applications
Information.
Ground pin. Local ground for CBYP ,CIN, COUT and CDELAY.
Input supply pin. Connect CIN between this pin and GND.
5
VOUT
6
SENSE
Connect this pin to VOUT (pin 5). For best performance the connection should
be made as close to the load as possible.
7
ERROR
This open drain output is an error flag output which goes low when VOUT
drops 5% below its nominal voltage. This pin also provides a power-on-reset
signal if a capacitor is connected to the DELAY pin.
8
SD
Output voltage, Connect COUT between this pin and ground.
Shutdown. Disables the regulator when less than 0.4V is applied. Enables the
regulator when greater than 0.9V. The Shutdown pin is pulled down internally
by a 6MΩ resistor.
2
LP3997
Connection Diagram
8 Lead MSOP
NS Package Number MUA08A
20092904
Ordering Information
For MSOP Package
Output
Voltage (V)
Grade
LP3997 Supplied as 1000
Units, Tape and Reel
LP3997 Supplied as 3500
Units, Tape and Reel
Package Marking
3.3
STD
LP3997MM-3.3
LP3997MMX-3.3
SAKB
3
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LP3997
Absolute Maximum Ratings
Machine Model
200V
(Notes 2, 1)
CBYP Pin
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Human Body Model
Input Voltage
Operating Ratings
-0.3 to 6.5V
Output Voltage
-0.3 to (VIN + 0.3V) with
6.5V (max)
SD Input Voltage
-0.3 to (VIN + 0.3V) with
6.5V (max)
Junction Temperature
100V
(Note 1)
Input Voltage
2V to 6V
Junction Temperature
-40˚C to 125˚C
Ambient Temperature TA Range
(Note 5)
150˚C
Lead/Pad Temp.
MSOP
1KV
Machine Model
-40˚C to 85˚C
260˚C
Storage Temperature
Thermal Properties
-65 to 150˚C
Continuous Power Dissipation
Internally Limited (Note 3)
(Note 1)
Junction To Ambient Thermal
Resistance (Note 6)
ESD (Note 4)
All Pins Except CBYP
Human Body Model
θJA (MSOP)
2KV
210˚C/W
Electrical Characteristics
Unless otherwise noted, SD = 950mV, VIN = VOUT + 1.0V, CIN = 2.2 µF, IOUT = 1 mA, COUT = 2.2 µF and CBYP = 0.1 µF. Typical values and limits appearing in normal type apply for TJ = 27˚C. Limits appearing in boldface type apply over the full temperature range for operation, −40 to +125˚C. (Note 12)
Symbol
Parameter
Conditions
VIN
Input Voltage
∆VOUT
Output Voltage Tolerance
Over full line and load regulation.
Line Regulation Error
VIN = (VOUT(NOM) + 1.0V) to 6.0V,
IOUT = 1mA
Typ
Limit
Min
Max
2
6
V
-1.5
+1.5
%
-3
+3
0.02
0.3
%/V
µV/mA
Load Regulation Error
IOUT = 1mA to 250mA
20
80
VDO
Dropout Voltage
IOUT = 250mA
(Note 7)
140
400
ILOAD
Load Current
(Notes 8, 9)
IQ
Quiescent Current
SD = 950mV, IOUT = 0mA
55
100
SD = 950mV, IOUT = 250mA
80
150
SD = 0.4V
0.01
0.5
(Note 10)
600
1000
ISC
Short Circuit Current Limit
IOUT
Maximum Output Current
PSRR
Power Supply Rejection Ratio
0
250
CBYP = 0.1µF
Without CBYP
en
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Output noise Voltage (Note 9)
BW = 10Hz to
100kHz,
VIN = VOUT(nom)
+1V
f = 1kHz, IOUT =
1mA to 150mA
61
f = 10kHz, IOUT =
150mA
55
f = 1kHz, IOUT =
1mA to 150mA
61
f = 10kHz, IOUT =
150mA
39
w/o CBYP
CBYP = 0.1µF
4
Units
mV
µA
µA
mA
mA
dB
180
µVRMS
100
(Continued)
Unless otherwise noted, SD = 950mV, VIN = VOUT + 1.0V, CIN = 2.2 µF, IOUT = 1 mA, COUT = 2.2 µF and CBYP = 0.1 µF. Typical values and limits appearing in normal type apply for TJ = 27˚C. Limits appearing in boldface type apply over the full temperature range for operation, −40 to +125˚C. (Note 12)
Symbol
Parameter
TSHUTDOWN Thermal Shutdown
Conditions
Typ
Temperature
150
Hysteresis
10
SD = 0.0V
0.01
Limit
Min
Units
Max
˚C
Shutdown Control Characteristics
ISD
Maximum Input Current at
SD Input
SD = 6V (Note 11)
VIL
Low Input Threshold
VIN = 2V to 6V
VIH
High Input Threshold
VIN = 2V to 6V
µA
1
0.4
V
0.95
V
Error Flag Characteristics
VTH
Power Good Trip Threshold
VIN Rising
95
VHYST
Hysteresis
VIN Rising or Falling
2.5
VOL
ErrorError OutputOutput low
Voltage
ISINK = 2mA
0.1
0.4
IOFF
Error Output High Leakage
ERROR = VOUT(NOM)
10
2000
nA
IDELAY
Delay Pin Current Source
VOUT > 95% VOUT(NOM)
2.2
3
µA
To 95% Level
150
250
µs
91
99
%VOUT
%VOUT
1.2
V
Timing Characteristics
tON
Turn On Time (Note 9)
CBYP = 0.1µF
2
ms
Transient
Response
Line Transient Response |δVOUT| Trise = Tfall = 30µs w/o CBYP
(Note 9)
CBYP = 0.1µF
δVIN = 600mV
40
mV
(pk - pk)
Load Transient Response
|δVOUT|
w/o CBYP
4
Trise = Tfall = 1µs (Note 9)
IOUT = 1mA to 150mA
70
80
mV
Note 1: Absolute Maximum Ratings are limits beyond which damage can occur. Operating Ratings are conditions under which operation of the device is
guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical
Characteristics tables.
Note 2: All Voltages are with respect to the potential at the GND pin.
Note 3: Internal thermal shutdown circuitry protects the device from permanent damage.
Note 4: The human body model is 100pF discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF capacitor discharged directly into each
pin.
Note 5: The maximum ambient temperature (TA(max)) is dependant on the maximum operating junction temperature (TJ(max-op) = 125˚C), the maximum power
dissipation of the device in the application (PD(max)), and the junction to ambient thermal resistance of the part/package in the application (θJA), as given by the
following equation: TA(max) = TJ(max-op) - (θJA x PD(max)).
Note 6: Junction to ambient thermal resistance is dependant on the application and board layout. In applications where high maximum power dissipation is possible,
special care must be paid to thermal dissipation issues in board design.
Note 7: Dropout voltage is defined as the voltage difference between input and output when the output voltage drops 100mV below its nominal value.
Note 8: The device maintains the regulated output voltage without the load.
Note 9: This electrical specification is guaranteed by design.
Note 10: Short circuit current is measured on the input supply line at the point when the short circuit condition reduces the output voltage to 5% of its nominal value.
Note 11: SD Pin has 6MΩ typical, resistor connected to GND.
Note 12: All limits are guaranteed. All electrical characteristics having room-temperature limits are tested during production at TJ = 25˚C or correlated using
Statistical Quality Control methods. Operation over the temperature specification is guaranteed by correlating the electrical characteristics to process and
temperature variations and applying statistical process control.
Output Capacitor, Recommended Specifications
Symbol
Co
Parameter
Output Capacitor
Conditions
Capacitance(Note 13)
ESR
Typ
2.2
Limit
Min
Max
0.7
5
Units
µF
500
mΩ
Note 13: The capacitor tolerance should be 30% or better over temperature. The full operating conditions for the application should be considered when selecting
a suitable capacitor to ensure that the minimum value of capacitance is always met. Recommended capacitor type is X7R. However, dependent on application, X5R,
Y5V, and Z5U can also be used. (See capacitor characteristics section in Application Hints)
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LP3997
Electrical Characteristics
LP3997
Typical Performance Characteristics.
Unless otherwise noted, SD = 950mV, VIN = VOUT + 1.0V,
CIN = 2.2 µF, IOUT = 1 mA, COUT = 2.2 µF and CBYP = 0.1 µF.
Typical values and limits appearing in normal type apply for TJ = 27˚C. Limits appearing in boldface type apply over the full
temperature range for operation, −40 to +125˚C.
Output Voltage Change vs Temperature
Ground Current vs Load Current
20092910
20092911
Ground Current vs VIN. ILOAD = 0mA
Ground Current vs VIN. ILOAD = 1mA
20092930
20092931
Ground Current vs VIN. ILOAD = 250mA
Dropout Voltage vs Load Current
20092932
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20092916
6
= 2.2 µF, IOUT = 1 mA, COUT = 2.2 µF and CBYP = 0.1 µF.
Typical values and limits appearing in normal type apply for TJ = 27˚C. Limits appearing in boldface type apply over the full
temperature range for operation, −40 to +125˚C. (Continued)
Line Transient
Line Transient
20092918
20092919
Load Transient (No CBYP)
Enable Start-up Time
20092921
20092923
Enable Start-up Time
Short Circuit Current
20092929
20092926
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LP3997
Typical Performance Characteristics. Unless otherwise noted, SD = 950mV, VIN = VOUT + 1.0V, CIN
LP3997
Typical Performance Characteristics. Unless otherwise noted, SD = 950mV, VIN = VOUT + 1.0V, CIN
= 2.2 µF, IOUT = 1 mA, COUT = 2.2 µF and CBYP = 0.1 µF.
Typical values and limits appearing in normal type apply for TJ = 27˚C. Limits appearing in boldface type apply over the full
temperature range for operation, −40 to +125˚C. (Continued)
Power Supply Rejection Ratio
Noise Spectrum
20092925
20092924
Turn-On Sequence
Turn-Off Sequence
20092927
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20092928
8
DELAY
External Capacitors
A capacitor from DELAY to GROUND sets the time delay for
ERROR changing from low to high state. The delay time is
set by the following formula.
In common with most regulators, the LP3997 requires the
inclusion of external capacitors.
VIN
An input capacitor is required for stability. It is recommended
that a minimum of 1.0µF capacitor is connected between the
LP3997 input pin and ground (this capacitance value may be
increased without limit).
This capacitor must be located a distance of not more than
1cm from the input pin and returned to a clean analog
ground. Any good quality ceramic, tantalum, or film capacitor
may be used at the input.
Important: To ensure stable operation it is essential that
good PCB design practices are employed to minimize
ground impedance and keep input inductance low. If these
conditions cannot be met, or if long wire leads are used to
connect the battery or other power source to the LP3997,
then it is recommended to increase the input capacitor to at
least 2.2µF. Also, tantalum capacitors can suffer catastrophic
failures due to surge current when connected to a lowimpedance source of power (like a battery or a very large
capacitor). If a tantalum capacitor is used at the input, it must
be guaranteed by the manufacturer to have a surge current
rating sufficient for the application.
There are no requirements for the ESR (Equivalent Series
Resistance) on the input capacitor, but tolerance and temperature coefficient must be considered when selecting the
capacitor to ensure the capacitance will remain ) 1.0µF over
the entire operating temperature range.
20092905
VTH(DELAY) is nominally 1.2V.
The DELAY pin should be open circuit if not used.
CBYP
For low noise application, connect a high frequency ceramic
capacitor from CBYP to ground, A 0.01µF to 0.1µF X5R or
X7R is recommended. This capacitor is connected directly to
high impedance node in the band gap reference circuit. Any
significant loading on this node will cause a change in the
regulated output voltage. For this reason, DC leakage current from this pin must be kept as low as possible for best
output voltage accuracy.
CAPACITOR CHARACTERISTICS
In common with most regulators, the LP3997 requires external capacitors for regulator stability. The LP3997 is specifically designed for portable applications requiring minimum
board space and can use capacitors in the range 1µF to
4.7µF.These capacitors must be correctly selected for good
performance. Ceramic capacitors are the smallest, least expensive and have the lowest ESR values (which makes
them best for eliminating high frequency noise). The ESR of
a typical 1µF ceramic capacitor is in the range of 20 mΩ to
40 mΩ, which easily meets the ESR requirement for stability
by the LP3997.These capacitors must be correctly selected
to ensure good performance of the LP3997.
For both input and output capacitors careful interpretation of
the capacitor specification is required to ensure correct device operation. The capacitor value can change greatly dependant on the conditions of operation and capacitor type.
VOUT
VOUT is the output voltage of the regulator. Connect capacitance (minimum 1.0µF) to ground from this pin. To ensure
stability the capacitor must meet the minimum value for
capacitance and have an ESR in the range 5mΩ to 500mΩ.
Ceramic X7R types are recommended. If an output capacitor
larger than 4.7µF is fitted then checks on in-rush current,
transient performance and stability, should be made.
In particular the output capacitor selection should take account of all the capacitor parameters to ensure that the
specification is met within the application. Capacitance value
can vary with DC bias conditions as well as temperature and
frequency of operation. Capacitor values will also show
some decrease over time due to aging. The capacitor parameters are also dependant on the particular case size with
smaller sizes giving poorer performance figures in general.
As an example Figure 1 shows a typical graph showing a
comparison of capacitor case sizes in a Capacitance versus
DC Bias plot. As shown in the graph, as a result of the DC
Bias condition, the capacitance value may drop below the
minimum capacitance value given in the recommended capacitor table (0.7µF in this case). Note that the graph shows
the capacitance out of spec for the 0402 case size capacitor
at higher bias voltages. It is therefore recommended that the
capacitor manufacturers’ specifications for the nominal value
capacitor are consulted for all conditions as some capacitor
sizes (e.g. 0402) may not be suitable in the actual application.
SENSE
SENSE is used to sense the output voltage. Connect sense
to VOUT
SHUTDOWN
SD controls the turning on and off of the LP3997. VOUT is
guaranteed to be on when the voltage on the SD pin is
greater than 0.95V. VOUT is guaranteed to be off when the
voltage on the SD pin is less than 0.4V.
ERROR
ERROR is an open drain output which is set low when VOUT
is more than 5% below its nominal value. An external pull up
resistor is required on this pin. When a capacitor is connected from DELAY to GROUND, the error signal is delayed
(see DELAY section). This delayed error signal can be used
as the power-on reset signal for the application system. The
ERROR pin is disconnected when not used.
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LP3997
Applications Information
LP3997
Applications Information
The value of ceramic capacitors can vary with temperature.
The capacitor type X7R, which operates over a temperature
range of -55˚C to +125˚C, will only vary the capacitance to
within ± 15%. The capacitor type X5R has a similar tolerance
over a reduced temperature range of -55˚C to +85˚C. Most
large value ceramic capacitors, larger than 1µF are manufactured with Z5U or Y5V temperature characteristics. Their
capacitance can drop by more than 50% as the temperature
goes from 25˚C to 85˚C. Therefore X7R is recommended
over Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25˚C.
Tantalum capacitors are less desirable than ceramic for use
as output capacitors because they are more expensive when
comparing equivalent capacitance and voltage ratings in the
1µF to 4.7µF range.
Another important consideration is that tantalum capacitors
have higher ESR values than equivalent size ceramics. This
means that while it may be possible to find a tantalum
capacitor with an ESR value within the stable range, it would
have to be larger in capacitance (which means bigger and
more costly ) than a ceramic capacitor with the same ESR
value. It should also be noted that the ESR of a typical
tantalum will increase about 2:1 as the temperature goes
from 25˚C down to -40˚C, so some guard band must be
allowed.
(Continued)
20092940
FIGURE 1. Graph Showing a Typical Variation in
Capacitance vs DC Bias
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10
inches (millimeters) unless otherwise noted
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the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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LP3997 Micropower 250mA CMOS LDO Regulator with Error Flag / Power-On-Reset
Physical Dimensions
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