Chapter 5 Internal Memory Computer Organization and Architecture

Chapter 5 Internal Memory Computer Organization and Architecture
Computer Organization and Architecture
Chapter 5
Internal Memory
Semiconductor main memory
• Early computers used doughnut shaped
ferromagnetic loops called cores for each bit
• Main memory was often referred to as “core”
memory or just “core”
• Term persists: e.g. a core dump
• Semiconductors are almost universal today
Memory Cells
Memory Cell Operation
• Properties:
• Select line selects cell for operation specified
by control line
• Control line has read or write signal
• Data/Sense line
• Most details below this level are beyond the
scope of this course
— Exhibit two stable or semi-stable states representing
1 and 0
— Capable of being written to at least once to set
state
— Capable of being read to sense the state
Semiconductor Memory Types
Semiconductor Memory
• RAM (Random Access Memory)
— Misnamed as all semiconductor memory is “random
access”
– Time required to access any address is constant and does
not depend on previous address accessed
— Read/Write
— Volatile
— Temporary storage
• Two technologies:
— Dynamic RAM: analog device, uses capacitor to store
charge
— Static RAM: digital device, uses flip-flop logic gates
to store state
1
Dynamic RAM (DRAM)
Dynamic RAM Structure
• Bits stored as charge in capacitors
• But charges leak, need refreshing even when
powered
• Simpler construction than static RAM (SRAM)
• Slower, but smaller per bit and less expensive
than SRAM
• Used for main memory
• Essentially analog rather than digital
— Level of charge determines value
DRAM Operation
Static RAM
• Address line active when bit read or written
•
•
•
•
•
— Transistor switch closed (current flows)
• Write
— Voltage is applied to bit line
– High for 1 low for 0
— Then address line is activated
– Transistor allows current to flow; transfers charge to capacitor
• Read
— Address line is activated
– Transistor allows current to flow; transfers charge from capacitor
to bit line
— Bit line fed to sense amplifier
Bits stored as on/off switches (flip-flops)
No charges to leak
No refresh needed when powered
More complex construction – 6 transistors
Larger and more expensive per bit, but faster
than DRAM
• Used for cache
• True digital device
— Uses flip-flops
– Compares with reference value to determine 0 or 1
— Capacitor charge must be restored to complete the read
operation
Static RAM Structure
Static RAM Operation
• Transistor arrangement gives stable logic state
• State 1
— C1 high, C2 low
— T1 T4 off, T2 T3 on
• State 0
— C2 high, C1 low
— T2 T3 off, T1 T4 on
• Address line transistors T5 T6 form a switch
• Write – apply value to B & complement to B
• Read – value is on line B
2
SRAM v DRAM
Acronym Soup
• Both are volatile
• So what is SDRAM?
— Power needed to preserve data
• Dynamic cell
— Simpler to build and smaller then SRAM
– Therefore more dense and less expensive
— Needs refresh circuitry
— Favored for larger memory units
• Static cells
— Faster then DRAM
— More expensive to build
— Favored for cache memory
— Synchronous DRAM
• SDR SDRAM “Single Data Rate”
• DDR SDRAM “Double Data Rate”
— DDR2, DDR3 double and quadruple r/w unit, DDR4 in
development
• RDRAM Rambus DRAM (more later)
• Many more acronyms abound
• See A Fast Guide to RAM
http://whatis.techtarget.com/definition/0,,sid9_gci523855,00.html
• More on SDRAM later
Read Only Memory (ROM)
Types of ROM
• Permanent, nonvolatile storage
• Data written during manufacture
• Typical usage:
— Microprogramming (see later)
— Library subroutines
— Systems programs (BIOS)
— Function tables
— Actually wired into the chip
— Large fixed cost, expensive for small runs
• Programmable (once)
— PROM is electrically programmed after manufacture
— Needs special equipment to program
Read-mostly memories
Flash memory
• Read “mostly” memories can be rewritten
• Erasable Programmable (EPROM)
• Provides block electrical erasure but not byte
level
• High-density, only one transistor per bit
• Fast read speeds, but not as good as DRAM
• Erase (very slow) sets blocks to all 1’s
• After a block is erased, 0’s can be written to
individual bits
— Optical erasure of entire chip by UV
— Can take 20 minutes to erase
— Only one transistor per bit
• Electrically Erasable (EEPROM)
— Takes much longer to write than read (several
hundred microseconds)
— Can rewrite single bytes
— Less dense than EPROM
— But large block size for erasure makes them
considerably faster then other EEPROMs
— Typical block (page) sizes are 512, 2048 and 4096
3
Flash memory
Chip Logic
• Flash memory is not durable
• Mostly limited to ~50K to ~100K erase cycles
• Trade-offs in chip design among speed,
capacity and cost
• Key issue is number of bits that can be written
simultaneously
— Recently extended upwards to ~1M cycles
• Flash drivers have to manage bad blocks in a
fashion similar to disk drivers
Organization in detail
— One extreme: physical arrangement of memory cells
same as logical arrangement of words in memory.
16Mbit chip is 1M 16-bit words
— Other extreme: one bit per chip, 16M memory uses
16 1-bit chips; with bit 1 of each word in chip 1 etc.
Typical 16 Mbit DRAM (4M x 4)
• A 16Mbit (2 MByte) chip can be also organized
as a 2048 x 2048 x 4bit array
— Reduces number of address pins
– Multiplex row address and column address
– 11 pins to address (211=2048)
– Adding one more pin doubles range of values so x4 capacity
Refreshing
Packaging
• Refresh circuit included on chip
— Disable chip
— Count through rows
— Read & Write back
• Refresh takes time
• Slows down apparent performance
4
1 MB EPROM Packaging
16MBit DRAM
•
•
•
•
•
• Programming voltage pin Vpp used in write
operations
• Organized as 4Mx4 bits
• Data pins D1-D4 are input/output
• WE (Write enable) and OE (output enable)
determine if R or W
• Because DRAM is accessed by row, then by
column, 11 address pins A0-A10 are
multiplexed
• RAS (row address select) and CAS (column
address select) pins
• 2 supply Vcc and ground pins Vss
• One No-Connect NC to make even number of
pins
256kByte Module
Organisation
1MByte Module Organisation
Organized as 1M 8 bit words; 32 pins
A0 – A19 address pins (20 bit address)
D0 – D7 are data out
Power supply Vcc and ground Vss
Chip enable pin CE
— indicates whether address is valid for this chip;
there may be several chips
— CE pins are connected to H.O. bits of address lines
on bus (> A19)
Each
Error Detection and Correction
Error Correcting Code Function
• Hard Failure
— Permanent defect
• Soft Error
— Random, non-destructive
— No permanent damage to memory
• A single parity bit can be used to detect (most)
errors in a word
• Parity bit test can fail to detect errors when
there is more than bit error
• Hamming codes can be used to detect AND
correct errors
5
Hamming Codes
History of Hamming Codes
• Developed at Bell Labs by Richard Hamming –
late 1940’s
• Richard Hamming worked on a Bell Model V
electro-mechanical computer
• Input was on punch cards, and the reader was
not reliable
• On weekdays it would flash lights to alert the
operator of an error. On weekends it would just
abort the job
• Richard Hamming unfortunately worked on
weekends and became rather annoyed at having
to re-run all of his jobs, so he invented errorcorrecting codes!
• Key to Hamming codes is to add extra parity
bits in such a way that each bit in a word is
checked by a unique combination of parity bits
• Parity bits themselves are included in parity
computations – we can tell if there was simply
an error in a parity bit
Computing a Hamming Code for a 4-bit word
Error Correction
• Compute even parity bit as XOR of 3 bits in
each circle
• Data read from memory does not match parity
computation for A and C
• Only one bit is in A and C but not B
• We will correct that bit to a 1
How many bits?
Pattern for Check Bits
• For memory of M bits we need K check bits,
where
2k – 1 >= M + K
• Cn : skip n-1 bits, check n bits, skip n bits,
check n bits, skip n bits, …
• Bits are numbered from 1 (not zero)
• Check bits are placed in every bit position that
is a power of 2
— c1=1, c2=2, c3=4, c4=8, c5=16,…
– 7=1+2+4, so pos 7 checked byc1,c2,c3
— 9=1+8, so pos 9 checked by c1,c4
Bit Position
Enc ode d Bits
Che ck Bit
Cov era ge
c1
c2
c3
c4
c5
1
c1
X
2
c2
X
3
d1
X
X
4
c3
X
5
d2
X
X
6
d3
X
X
7
d4
X
X
X
8
c4
X
9
d5
X
X
10
d6
X
11
d7
X
X
X
X
12
d8
X
X
13 14 15 16 17 18 19 20 21 …
d9 d10 d11 c 5 d12 d13 d14 d15 d16 …
X
X
X
X
X
…
X
X
X
X
…
X
X
X
X
X
…
X
X
X
…
X
X
X
X
X
X
…
6
Computing a Hamming Code
Finding the error
• Note that each check bit also checks itself!
• We had
• Example: A byte of data: 10110010
Create the data word, leaving spaces for the parity bits:
_ _ 1 _ 01 1 _ 0 0 1 0
Calculate the parity for each check bit (? represents the bit position being set;
treat as 0):
• Position 1 checks bits 1,3,5,7,9,11:
?_1_011_0010. Odd parity so c1 <- 1:
1_1_011_0010
• Position 2 checks bits 2,3,6,7,10,11:
1?1_011_0010. Even parity so c2<-0:
101_011_0010
• Position 4 checks bits 4,5,6,7,12:
101?011_0010. Even parity so c3 <-0:
1010011_0010
• Position 8 checks bits 8,9,10,11,12:
1010011?0010. Odd parity so c4 <- 1
101001110010
• Coded word: 101001110010
101001110010
• Suppose mem read =
101001110110
• Compute check bits:
• _ _ 1 _ 0 1 1 _ 0 1 1 0
1 2 3 4 5 6 7 8 9 10 11 12
c1 [3,5,7,9,11]
<- 1 (OK)
c2 [3,6,7,10,11]
<- 1 (but c2 = 0)
c3 [5,6,7,12]
<- 0 (OK)
c4 [9,10,11,12]
<- 0 (but c4 = 1)
Error: c2 in pos 2, c4 in pos 8. 8+2=10
Correct bit 10:
101001110010
Error in check bit
SEC-DED Coding
• We had
• Hamming codes as described above are capable
only of correcting single-bit errors
101001110010
• Suppose mem read =
101001100010
• Compute check bits:
• _ _ 1 _ 0 1 1 _ 0 0 1 0
1 2 3 4 5 6 7 8 9 10 11 12
c1 [3,5,7,9,11]
<- 1 (OK)
c2 [3,6,7,10,11]
<- 0 (OK)
c3 [5,6,7,12]
<- 0 (OK)
c4 [9,10,11,12]
<- 1 (but c4 = 0)
Error: only c4 in pos 8.
No data bits were affected; check bit itself is the error
— A double-bit error cannot be distinguished from a
single-bit error in a different code
— Correction will add a third error!
• Adding a single parity bit over the entire M+K
bits allows double-bit errors to be detected
(but not corrected)
— Hence “Single Error Correction, Double Error
Detection”
• A common implementation uses 8 check bits
per 64 bits of memory
— Same overhead as older 9-bit parity check DRAM
Advanced DRAM Organization
DRAM Enhancements
• Memory access is a bottleneck (the “von
Neumann bottleneck”) in a high-performance
system
• Basic DRAM same since first RAM chips
• SRAM cache is one line of attack
• DDR-DRAM:
— Expensive
— Diminishing returns as more cache is added
Double-data-rate DRAM
— DDR-SDRAM now available
•
•
•
•
SDRAM: Synchronous DRAM
RDRAM: Rambus DRAM
CDRAM: Cache DRAM
DDR = Double Data Rate
— Data sent on both rising and falling edges of clock
signal
7
Synchronous DRAM (SDRAM)
Synchronous DRAM (SDRAM)
• Access is synchronized with an external clock
• SDRAM latency is about the same asynchronous
DRAM
• Speed comes from ability to interleave
operations between banks of chips
• Note that SDRAM has a “mode register”
— Very fast (18 ns access time, 1.3 Gbs at 166 MHz bus speed)
• Request on address bus latched in the SDRAM
• Some time later RAM responds with data
— (CPU waits for conventional DRAM)
— Since SDRAM moves data in time with system clock, CPU knows
when data will be ready
— CPU and bus do not have to wait; can do something else
— Specifies things like burst length and read timing
• Burst mode allows SDRAM to set up stream of data and
fire it out in block
• DDR-SDRAM sends data twice per clock cycle (leading &
trailing edge)
SDRAM
SDRAM Read Timing
Typical SDRAM Organization
RAMBUS
• A 512 MB SDRAM DIMM might be made of 8 or 9 SDRAM chips, each
containing 512 Mbit of storage, and each one contributing 8 bits to the
DIMM's 64- or 72-bit width.
• A typical 512 Mbit SDRAM chip internally contains 4 independent 16 Mbyte
banks. Each bank is an array of 8192 rows of 16384 bits each. A bank is
either idle, active, or changing from one to the other.
• An active command activates an idle bank. It takes a 2-bit bank address
(BA0–BA1) and a 13-bit row address (A0–A12), and reads that row into the
bank's array of 16384 sense amplifiers. This is also known as "opening" the
row. This operation has the side effect of refreshing that row.
• Once the row has been activated or "opened", read and write commands
are possible. Each command requires a column address, but because each
chip works on 8 bits at a time, there are 2048 possible column addresses,
needing only 11 address lines (A0–A9,A11).
• (Source http://en.wikipedia.org/wiki/SDRAM)
• Intel attempted to adopt RDRAM for Pentium &
Itanium; provided commitments and funding 1997-2000
— Market share never exceeded 5%
— RAMBUS still is involved in several nasty legal battles; primary
income is from patent licensing
— Also alleges DDR mfrs fixed prices to suppress RDRAM
•
•
•
•
Vertical package – all pins on one side
Data exchange over 28 wires < cm long
Bus addresses up to 320 RDRAM chips at 1.6Gbps
Asynchronous block protocol
— 480ns access time
— Then 1.6 Gbps
• Can require heat-sinks
8
RAMBUS Diagram
DDR SDRAM
• SDRAM can only send data once per clock
• Double-data-rate SDRAM can send data twice
per clock cycle
— Rising edge and falling edge
• Fast, 12.5ns access time, 3.2Gbs at 200MHz bus
speed
DDR SDRAM Read Timing
DDR2 and DDR3
• Operate at twice or more the bus speed of DDR
SDRAM
• Higher latency than DDR SDRAM means worse
performance at same bus speed
• Both have larger prefetch buffers
SDR/DDR/DDR2 Comparison
Cache DRAM
• Mitsubishi
• Integrates small SRAM cache (16 kb) onto
generic DRAM chip
• Used as true cache
— 64-bit lines
— Effective for ordinary random access
• To support serial access of block of data
— E.g. refresh bit-mapped screen
– CDRAM can prefetch data from DRAM into SRAM buffer
– Subsequent accesses solely to SRAM
9
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