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Cyclone V Device Handbook

Volume 1: Device Interfaces and Integration

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Cyclone V Device Handbook Volume 1: Device Interfaces and Integration

Contents

Logic Array Blocks and Adaptive Logic Modules in Cyclone V Devices...........1-1

LAB ...............................................................................................................................................................1-1

MLAB ................................................................................................................................................1-2

Local and Direct Link Interconnects ............................................................................................1-3

LAB Control Signals........................................................................................................................1-4

ALM Resources ...............................................................................................................................1-5

ALM Output ....................................................................................................................................1-6

ALM Operating Modes ..............................................................................................................................1-7

Normal Mode ..................................................................................................................................1-8

Extended LUT Mode ......................................................................................................................1-8

Arithmetic Mode .............................................................................................................................1-8

Shared Arithmetic Mode ................................................................................................................1-9

Document Revision History.....................................................................................................................1-11

Embedded Memory Blocks in Cyclone V Devices..............................................2-1

Types of Embedded Memory.....................................................................................................................2-1

Embedded Memory Capacity in Cyclone V Devices..................................................................2-1

Embedded Memory Design Guidelines for Cyclone V Devices............................................................2-2

Guideline: Consider the Memory Block Selection......................................................................2-2

Guideline: Implement External Conflict Resolution..................................................................2-3

Guideline: Customize Read-During-Write Behavior.................................................................2-3

Guideline: Consider Power-Up State and Memory Initialization............................................2-6

Guideline: Control Clocking to Reduce Power Consumption..................................................2-7

Embedded Memory Features.....................................................................................................................2-7

Embedded Memory Configurations.............................................................................................2-8

Mixed-Width Port Configurations................................................................................................2-9

Embedded Memory Modes......................................................................................................................2-10

Embedded Memory Clocking Modes.....................................................................................................2-11

Clocking Modes for Each Memory Mode..................................................................................2-11

Asynchronous Clears in Clocking Modes..................................................................................2-12

Output Read Data in Simultaneous Read/Write.......................................................................2-12

Independent Clock Enables in Clocking Modes.......................................................................2-13

Parity Bit in Memory Blocks....................................................................................................................2-13

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Cyclone V Device Handbook Volume 1: Device Interfaces and Integration

TOC-3

Byte Enable in Embedded Memory Blocks............................................................................................2-13

Byte Enable Controls in Memory Blocks....................................................................................2-13

Data Byte Output...........................................................................................................................2-14

RAM Blocks Operations...............................................................................................................2-15

Memory Blocks Packed Mode Support..................................................................................................2-15

Memory Blocks Address Clock Enable Support....................................................................................2-15

Document Revision History.....................................................................................................................2-17

Variable Precision DSP Blocks in Cyclone V Devices........................................3-1

Features.........................................................................................................................................................3-1

Supported Operational Modes in Cyclone V Devices............................................................................3-2

Resources.......................................................................................................................................................3-3

Design Considerations................................................................................................................................3-4

Operational Modes..........................................................................................................................3-4

Internal Coefficient and Pre-Adder...............................................................................................3-4

Accumulator.....................................................................................................................................3-4

Chainout Adder................................................................................................................................3-4

Block Architecture.......................................................................................................................................3-5

Input Register Bank.........................................................................................................................3-6

Pre-Adder..........................................................................................................................................3-8

Internal Coefficient..........................................................................................................................3-8

Multipliers.........................................................................................................................................3-8

Adder.................................................................................................................................................3-9

Accumulator and Chainout Adder................................................................................................3-9

Systolic Registers............................................................................................................................3-10

Double Accumulation Register....................................................................................................3-10

Output Register Bank....................................................................................................................3-10

Operational Mode Descriptions..............................................................................................................3-10

Independent Multiplier Mode.....................................................................................................3-11

Independent Complex Multiplier Mode....................................................................................3-13

Multiplier Adder Sum Mode........................................................................................................3-15

18 x 18 Multiplication Summed with 36-Bit Input Mode........................................................3-15

Systolic FIR Mode..........................................................................................................................3-15

Document Revision History.....................................................................................................................3-18

Clock Networks and PLLs in Cyclone V Devices................................................4-1

Clock Networks............................................................................................................................................4-1

Clock Resources in Cyclone V Devices.........................................................................................4-2

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TOC-4

Cyclone V Device Handbook Volume 1: Device Interfaces and Integration

Types of Clock Networks................................................................................................................4-3

Clock Sources Per Quadrant..........................................................................................................4-7

Types of Clock Regions...................................................................................................................4-8

Clock Network Sources...................................................................................................................4-9

Clock Output Connections...........................................................................................................4-11

Clock Control Block......................................................................................................................4-11

Clock Power Down........................................................................................................................4-14

Clock Enable Signals......................................................................................................................4-14

Cyclone V PLLs..........................................................................................................................................4-16

PLL Physical Counters in Cyclone V Devices............................................................................4-16

PLL Locations in Cyclone V Devices..........................................................................................4-17

PLL Migration Guidelines ...........................................................................................................4-22

Fractional PLL Architecture.........................................................................................................4-22

PLL Cascading................................................................................................................................4-23

PLL External Clock I/O Pins........................................................................................................4-23

PLL Control Signals.......................................................................................................................4-24

Clock Feedback Modes..................................................................................................................4-25

Clock Multiplication and Division..............................................................................................4-31

Programmable Phase Shift............................................................................................................4-32

Programmable Duty Cycle...........................................................................................................4-32

Clock Switchover...........................................................................................................................4-32

PLL Reconfiguration and Dynamic Phase Shift........................................................................4-37

Document Revision History.....................................................................................................................4-38

I/O Features in Cyclone V Devices......................................................................5-1

I/O Resources Per Package for Cyclone V Devices.................................................................................5-1

I/O Vertical Migration for Cyclone V Devices........................................................................................5-4

Verifying Pin Migration Compatibility........................................................................................5-5

I/O Standards Support in Cyclone V Devices..........................................................................................5-5

I/O Standards Support for FPGA I/O in Cyclone V Devices....................................................5-5

I/O Standards Support for HPS I/O in Cyclone V Devices........................................................5-7

I/O Standards Voltage Levels in Cyclone V Devices...................................................................5-8

MultiVolt I/O Interface in Cyclone V Devices..........................................................................5-10

I/O Design Guidelines for Cyclone V Devices.......................................................................................5-11

Mixing Voltage-Referenced and Non-Voltage-Referenced I/O Standards...........................5-11

PLLs and Clocking.........................................................................................................................5-12

LVDS Interface with External PLL Mode...................................................................................5-15

Guideline: Use the Same V

CCPD for All I/O Banks in a Group...............................................5-17

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Cyclone V Device Handbook Volume 1: Device Interfaces and Integration

TOC-5

Guideline: Ensure Compatible V

CCIO and V

CCPD

Voltage in the Same Bank......................5-18

Guideline:

VREF

Pin Restrictions.................................................................................................5-18

Guideline: Observe Device Absolute Maximum Rating for 3.3 V Interfacing......................5-18

Guideline: Adhere to the LVDS I/O Restrictions and Differential Pad Placement

Rules...........................................................................................................................................5-19

I/O Banks Locations in Cyclone V Devices............................................................................................5-19

I/O Banks Groups in Cyclone V Devices...............................................................................................5-21

Modular I/O Banks for Cyclone V E Devices............................................................................5-22

Modular I/O Banks for Cyclone V GX Devices.........................................................................5-23

Modular I/O Banks for Cyclone V GT Devices.........................................................................5-24

Modular I/O Banks for Cyclone V SE Devices..........................................................................5-25

Modular I/O Banks for Cyclone V SX Devices..........................................................................5-26

Modular I/O Banks for Cyclone V ST Devices..........................................................................5-27

I/O Element Structure in Cyclone V Devices........................................................................................5-27

I/O Buffer and Registers in Cyclone V Devices.........................................................................5-27

Programmable IOE Features in Cyclone V Devices.............................................................................5-29

Programmable Current Strength.................................................................................................5-30

Programmable Output Slew-Rate Control.................................................................................5-31

Programmable IOE Delay.............................................................................................................5-31

Programmable Output Buffer Delay...........................................................................................5-31

Programmable Pre-Emphasis......................................................................................................5-32

Programmable Differential Output Voltage..............................................................................5-32

I/O Pins Features for Cyclone V Devices...............................................................................................5-33

Open-Drain Output.......................................................................................................................5-33

Bus-Hold Circuitry........................................................................................................................5-33

Pull-up Resistor..............................................................................................................................5-34

On-Chip I/O Termination in Cyclone V Devices.................................................................................5-34

R

S

OCT without Calibration in Cyclone V Devices..................................................................5-35

R

S

OCT with Calibration in Cyclone V Devices........................................................................5-36

R

T

OCT with Calibration in Cyclone V Devices.......................................................................5-38

Dynamic OCT in Cyclone V Devices..........................................................................................5-40

LVDS Input R

D

OCT in Cyclone V Devices..............................................................................5-41

OCT Calibration Block in Cyclone V Devices...........................................................................5-42

External I/O Termination for Cyclone V Devices.................................................................................5-44

Single-ended I/O Termination.....................................................................................................5-45

Differential I/O Termination.......................................................................................................5-47

Dedicated High-Speed Circuitries...........................................................................................................5-52

High-Speed Differential I/O Locations.......................................................................................5-52

LVDS SERDES Circuitry..............................................................................................................5-54

Altera Corporation

TOC-6

Cyclone V Device Handbook Volume 1: Device Interfaces and Integration

True LVDS Buffers in Cyclone V Devices..................................................................................5-55

Emulated LVDS Buffers in Cyclone V Devices.........................................................................5-63

Differential Transmitter in Cyclone V Devices.....................................................................................5-63

Transmitter Blocks.........................................................................................................................5-63

Serializer Bypass for DDR and SDR Operations.......................................................................5-64

Differential Receiver in Cyclone V Devices...........................................................................................5-65

Receiver Blocks in Cyclone V Devices........................................................................................5-65

Receiver Mode in Cyclone V Devices.........................................................................................5-67

Receiver Clocking for Cyclone V Devices..................................................................................5-68

Differential I/O Termination for Cyclone V Devices...............................................................5-68

Source-Synchronous Timing Budget......................................................................................................5-69

Differential Data Orientation.......................................................................................................5-69

Differential I/O Bit Position.........................................................................................................5-70

Transmitter Channel-to-Channel Skew.....................................................................................5-71

Receiver Skew Margin for LVDS Mode......................................................................................5-71

Document Revision History.....................................................................................................................5-73

External Memory Interfaces in Cyclone V Devices............................................6-1

External Memory Performance..................................................................................................................6-2

HPS External Memory Performance.........................................................................................................6-2

Memory Interface Pin Support in Cyclone V Devices............................................................................6-2

Guideline: Using DQ/DQS Pins....................................................................................................6-3

DQ/DQS Bus Mode Pins for Cyclone V Devices........................................................................6-3

DQ/DQS Groups in Cyclone V E..................................................................................................6-5

DQ/DQS Groups in Cyclone V GX...............................................................................................6-7

DQ/DQS Groups in Cyclone V GT...............................................................................................6-9

DQ/DQS Groups in Cyclone V SE..............................................................................................6-11

DQ/DQS Groups in Cyclone V SX..............................................................................................6-11

DQ/DQS Groups in Cyclone V ST..............................................................................................6-12

External Memory Interface Features in Cyclone V Devices................................................................6-12

UniPHY IP......................................................................................................................................6-12

External Memory Interface Datapath.........................................................................................6-13

DQS Phase-Shift Circuitry............................................................................................................6-13

PHY Clock (PHYCLK) Networks...............................................................................................6-21

DQS Logic Block............................................................................................................................6-24

Dynamic OCT Control.................................................................................................................6-26

IOE Registers..................................................................................................................................6-26

Delay Chains...................................................................................................................................6-28

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Cyclone V Device Handbook Volume 1: Device Interfaces and Integration

TOC-7

I/O and DQS Configuration Blocks............................................................................................6-29

Hard Memory Controller.........................................................................................................................6-30

Features of the Hard Memory Controller..................................................................................6-30

Multi-Port Front End....................................................................................................................6-32

Bonding Support............................................................................................................................6-33

Hard Memory Controller Width for Cyclone V E....................................................................6-35

Hard Memory Controller Width for Cyclone V GX................................................................6-36

Hard Memory Controller Width for Cyclone V GT................................................................6-37

Hard Memory Controller Width for Cyclone V SE..................................................................6-37

Hard Memory Controller Width for Cyclone V SX.................................................................6-38

Hard Memory Controller Width for Cyclone V ST..................................................................6-38

Document Revision History.....................................................................................................................6-39

Configuration, Design Security, and Remote System Upgrades in Cyclone V

Devices.............................................................................................................7-1

Enhanced Configuration and Configuration via Protocol.....................................................................7-1

MSEL Pin Settings........................................................................................................................................7-2

Configuration Sequence..............................................................................................................................7-3

Power Up...........................................................................................................................................7-4

Reset...................................................................................................................................................7-5

Configuration...................................................................................................................................7-5

Configuration Error Handling.......................................................................................................7-5

Initialization......................................................................................................................................7-6

User Mode.........................................................................................................................................7-6

Device Configuration Pins..........................................................................................................................7-6

Configuration Pin Options in the Quartus II Software..............................................................7-8

Fast Passive Parallel Configuration...........................................................................................................7-9

Fast Passive Parallel Single-Device Configuration......................................................................7-9

Fast Passive Parallel Multi-Device Configuration.....................................................................7-10

Active Serial Configuration......................................................................................................................7-12

DATA Clock (DCLK)....................................................................................................................7-12

Active Serial Single-Device Configuration.................................................................................7-13

Active Serial Multi-Device Configuration..................................................................................7-14

Estimating the Active Serial Configuration Time.....................................................................7-15

Using EPCS and EPCQ Devices..............................................................................................................7-15

Controlling EPCS and EPCQ Devices........................................................................................7-16

Trace Length and Loading............................................................................................................7-16

Programming EPCS and EPCQ Devices....................................................................................7-16

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TOC-8

Cyclone V Device Handbook Volume 1: Device Interfaces and Integration

Passive Serial Configuration.....................................................................................................................7-20

Passive Serial Single-Device Configuration Using an External Host.....................................7-21

Passive Serial Single-Device Configuration Using an Altera Download Cable....................7-21

Passive Serial Multi-Device Configuration................................................................................7-22

JTAG Configuration..................................................................................................................................7-24

JTAG Single-Device Configuration.............................................................................................7-25

JTAG Multi-Device Configuration.............................................................................................7-27

CONFIG_IO JTAG Instruction...................................................................................................7-27

Configuration Data Compression...........................................................................................................7-28

Enabling Compression Before Design Compilation.................................................................7-28

Enabling Compression After Design Compilation...................................................................7-28

Using Compression in Multi-Device Configuration................................................................7-28

Remote System Upgrades.........................................................................................................................7-29

Configuration Images....................................................................................................................7-30

Configuration Sequence in the Remote Update Mode.............................................................7-30

Remote System Upgrade Circuitry..............................................................................................7-31

Enabling Remote System Upgrade Circuitry.............................................................................7-31

Remote System Upgrade Registers..............................................................................................7-32

Remote System Upgrade State Machine.....................................................................................7-34

User Watchdog Timer...................................................................................................................7-34

Design Security...........................................................................................................................................7-34

ALTCHIP_ID Megafunction.......................................................................................................7-35

JTAG Secure Mode........................................................................................................................7-35

Security Key Types.........................................................................................................................7-36

Security Modes...............................................................................................................................7-37

Design Security Implementation Steps.......................................................................................7-37

Document Revision History.....................................................................................................................7-38

SEU Mitigation for Cyclone V Devices...............................................................8-1

Error Detection Features.............................................................................................................................8-1

Configuration Error Detection..................................................................................................................8-1

User Mode Error Detection........................................................................................................................8-1

Specifications................................................................................................................................................8-2

Minimum EMR Update Interval...................................................................................................8-2

Error Detection Frequency.............................................................................................................8-3

CRC Calculation Time....................................................................................................................8-3

Using Error Detection Features in User Mode........................................................................................8-4

Enabling Error Detection................................................................................................................8-4

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Cyclone V Device Handbook Volume 1: Device Interfaces and Integration

TOC-9

CRC_ERROR Pin.............................................................................................................................8-5

Error Detection Registers................................................................................................................8-5

Error Detection Process..................................................................................................................8-7

Testing the Error Detection Block.................................................................................................8-8

Document Revision History.......................................................................................................................8-9

JTAG Boundary-Scan Testing in Cyclone V Devices.........................................9-1

BST Operation Control ..............................................................................................................................9-1

IDCODE ...........................................................................................................................................9-1

Supported JTAG Instruction .........................................................................................................9-3

JTAG Secure Mode .........................................................................................................................9-6

JTAG Private Instruction ...............................................................................................................9-6

I/O Voltage for JTAG Operation ..............................................................................................................9-7

Performing BST ...........................................................................................................................................9-7

Enabling and Disabling IEEE Std. 1149.1 BST Circuitry ......................................................................9-8

Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing.......................................................................9-9

IEEE Std. 1149.1 Boundary-Scan Register ...............................................................................................9-9

Boundary-Scan Cells of a Cyclone V Device I/O Pin...............................................................9-10

Document Revision History.....................................................................................................................9-12

Power Management in Cyclone V Devices.......................................................10-1

Power Consumption..................................................................................................................................10-1

Dynamic Power Equation.............................................................................................................10-1

Hot-Socketing Feature..............................................................................................................................10-2

Hot-Socketing Implementation...............................................................................................................10-2

Power-Up Sequence..................................................................................................................................10-4

Power-On Reset Circuitry........................................................................................................................10-5

Power Supplies Monitored and Not Monitored by the POR Circuitry.................................10-7

Document Revision History.....................................................................................................................10-7

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Logic Array Blocks and Adaptive Logic Modules in Cyclone V Devices

2014.01.10

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This chapter describes the features of the logic array block (LAB) in the Cyclone

®

V core fabric.

The LAB is composed of basic building blocks known as adaptive logic modules (ALMs) that you can configure to implement logic functions, arithmetic functions, and register functions.

You can use a quarter of the available LABs in the Cyclone V devices as a memory LAB (MLAB).

The Quartus

®

II software and other supported third-party synthesis tools, in conjunction with parameterized functions such as the library of parameterized modules (LPM), automatically choose the appropriate mode for common functions such as counters, adders, subtractors, and arithmetic functions.

This chapter contains the following sections:

• LAB

• ALM Operating Modes

Related Information

Cyclone V Device Handbook: Known Issues

Lists the planned updates to the

Cyclone V Device Handbook

chapters.

1

LAB

The LABs are configurable logic blocks that consist of a group of logic resources. Each LAB contains dedicated logic for driving control signals to its ALMs.

MLAB is a superset of the LAB and includes all the LAB features.

©

2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with

Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO

9001:2008

Registered www.altera.com

101 Innovation Drive, San Jose, CA 95134

1-2

MLAB

Figure 1-1: LAB Structure and Interconnects Overview in Cyclone V Devices

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2014.01.10

This figure shows an overview of the Cyclone V LAB and MLAB structure with the LAB interconnects.

C2/C4 C12

Row Interconnects of

Variable Speed and Length

R14

R3/R6

ALMs

Connects to adjacent

LABs, memory blocks, digital signal processing

(DSP) blocks, or I/O element (IOE) outputs.

Direct-Link

Interconnect from

Adjacent Block

Direct-Link

Interconnect from

Adjacent Block

Direct-Link

Interconnect to

Adjacent Block

Local Interconnect LAB

Direct-Link

Interconnect to

Adjacent Block

MLAB

Fast Local Interconnect Is Driven from Either Sides by Column Interconnect and LABs, and from Above by Row Interconnect

Column Interconnects of

Variable Speed and Length

MLAB

Each MLAB supports a maximum of 640 bits of simple dual-port SRAM.

You can configure each ALM in an MLAB as a 32 x 2 memory block, resulting in a configuration of 32 x 20 simple dual-port SRAM block.

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Logic Array Blocks and Adaptive Logic Modules in Cyclone V Devices

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Figure 1-2: LAB and MLAB Structure for Cyclone V Devices

You can use an MLAB

ALM as a regular LAB

ALM or configure it as a dual-port SRAM.

You can use an MLAB

ALM as a regular LAB

ALM or configure it as a dual-port SRAM.

LUT-Based-32 x 2

Simple Dual-Port SRAM

LUT-Based-32 x 2

Simple Dual-Port SRAM

LUT-Based-32 x 2

Simple Dual-Port SRAM

LUT-Based-32 x 2

Simple Dual-Port SRAM

LUT-Based-32 x 2

Simple Dual-Port SRAM

LAB Control Block

LUT-Based-32 x 2

Simple Dual-Port SRAM

LUT-Based-32 x 2

Simple Dual-Port SRAM

LUT-Based-32 x 2

Simple Dual-Port SRAM

LUT-Based-32 x 2

Simple Dual-Port SRAM

LUT-Based-32 x 2

Simple Dual-Port SRAM

MLAB

Local and Direct Link Interconnects

ALM

ALM

ALM

ALM

ALM

LAB Control Block

ALM

ALM

ALM

ALM

ALM

LAB

1-3

Local and Direct Link Interconnects

Each LAB can drive 30 ALMs through fast-local and direct-link interconnects. Ten ALMs are in any given

LAB and ten ALMs are in each of the adjacent LABs.

The local interconnect can drive ALMs in the same LAB using column and row interconnects and ALM outputs in the same LAB.

Neighboring LABs, MLABs, M10K blocks, or digital signal processing (DSP) blocks from the left or right can also drive the LAB’s local interconnect using the direct link connection.

The direct link connection feature minimizes the use of row and column interconnects, providing higher performance and flexibility.

Logic Array Blocks and Adaptive Logic Modules in Cyclone V Devices

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LAB Control Signals

Figure 1-3: LAB Fast Local and Direct Link Interconnects for Cyclone V Devices

Direct Link Interconnect from

Left LAB, Memory Block,

DSP Block, or IOE Output

Direct Link Interconnect from

Right LAB, Memory Block,

DSP Block, or IOE Output

ALMs ALMs

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Direct Link

Interconnect to Left

Direct Link

Interconnect to Right

Fast Local

Interconnect

MLAB LAB

LAB Control Signals

Each LAB contains dedicated logic for driving the control signals to its ALMs, and has two unique clock sources and three clock enable signals.

The LAB control block generates up to three clocks using the two clock sources and three clock enable signals. Each clock and the clock enable signals are linked.

De-asserting the clock enable signal turns off the corresponding LAB-wide clock.

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Figure 1-4: LAB-Wide Control Signals for Cyclone V Devices

This figure shows the clock sources and clock enable signals in a LAB.

There are two unique clock signals per LAB.

6

Dedicated Row

LAB Clocks

6

6

Local Interconnect

Local Interconnect

Local Interconnect

Local Interconnect

ALM Resources

1-5

labclk0 labclkena0 or asyncload or labpreset labclk1 labclkena1 labclk2 labclkena2 syncload labclr0 labclr1 synclr

ALM Resources

One ALM contains four programmable registers. Each register has the following ports:

• Data

• Clock

• Synchronous and asynchronous clear

• Synchronous load

Global signals, general-purpose I/O (GPIO) pins, or any internal logic can drive the clock and clear control signals of an ALM register.

GPIO pins or internal logic drives the clock enable signal.

For combinational functions, the registers are bypassed and the output of the look-up table (LUT) drives directly to the outputs of an ALM.

Note:

The Quartus II software automatically configures the ALMs for optimized performance.

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ALM Output

Figure 1-5: ALM High-Level Block Diagram for Cyclone V Devices

shared_arith_in dataf0 datae0 dataa datab

6-Input

LUT carry_in

Combinational/

Memory ALUT0

adder0 labclk

D reg0

Q

D reg1

Q datac datad datae1 dataf1

6-Input

LUT

Combinational/

Memory ALUT1

adder1

D reg2

Q shared_arith_out carry_out

D reg3

Q

To General or

Local Routing

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ALM Output

The general routing outputs in each ALM drive the local, row, and column routing resources. Two ALM outputs can drive column, row, or direct link routing connections, and one of these ALM outputs can also drive local interconnect resources.

The LUT, adder, or register output can drive the ALM outputs. The LUT or adder can drive one output while the register drives another output.

Register packing improves device utilization by allowing unrelated register and combinational logic to be packed into a single ALM. Another mechanism to improve fitting is to allow the register output to feed back into the look-up table (LUT) of the same ALM so that the register is packed with its own fan-out LUT. The

ALM can also drive out registered and unregistered versions of the LUT or adder output.

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Figure 1-6: ALM Connection Details for Cyclone V Devices

shared_arith_in carry_in syncload aclr[1:0] clk[2:0] sclr dataf0 datae0 dataa datab datac0

4-Input

LUT

GND

+

3-Input

LUT

3-Input

LUT datac1

4-Input

LUT

+

3-Input

LUT

3-Input

LUT

VCC datae1 dataf1 shared_arith_out carry_out

ALM Operating Modes

The Cyclone V ALM operates in any of the following modes:

• Normal mode

• Extended LUT mode

• Arithmetic mode

• Shared arithmetic mode

ALM Operating Modes

1-7

D

CLR

Q

Row, Column

Direct Link Routing

D

CLR

Q

D

CLR

Q

Row, Column

Direct Link Routing

Local

Interconnect

Row, Column

Direct Link Routing

D

CLR

Q

Row, Column

Direct Link Routing

Local

Interconnect

Logic Array Blocks and Adaptive Logic Modules in Cyclone V Devices

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1-8

Normal Mode

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Normal Mode

Normal mode allows two functions to be implemented in one Cyclone V ALM, or a single function of up to six inputs.

Up to eight data inputs from the LAB local interconnect are inputs to the combinational logic.

The ALM can support certain combinations of completely independent functions and various combinations of functions that have common inputs.

Extended LUT Mode

In this mode, if the 7-input function is unregistered, the unused eighth input is available for register packing.

Functions that fit into the template, as shown in the following figure, often appear in designs as “if-else” statements in Verilog HDL or VHDL code.

Figure 1-7: Template for Supported 7-Input Functions in Extended LUT Mode for Cyclone V Devices

datae0 datac dataa datab datad dataf0

5-Input

LUT

5-Input

LUT combout0

D reg0

Q

To General or

Local Routing datae1 dataf1

This input is available for register packing.

Arithmetic Mode

The ALM in arithmetic mode uses two sets of two 4-input LUTs along with two dedicated full adders.

The dedicated adders allow the LUTs to perform pre-adder logic; therefore, each adder can add the output of two 4-input functions.

The ALM supports simultaneous use of the adder’s carry output along with combinational logic outputs.

The adder output is ignored in this operation.

Using the adder with the combinational logic output provides resource savings of up to 50% for functions that can use this mode.

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Logic Array Blocks and Adaptive Logic Modules in Cyclone V Devices

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Figure 1-8: ALM in Arithmetic Mode for Cyclone V Devices

datae0 carry_in

adder0

4-Input

LUT dataf0 datac datab dataa

4-Input

LUT reg0

adder1

reg1 datad datae1 dataf1

4-Input

LUT

4-Input

LUT reg2 carry_out reg3

Shared Arithmetic Mode

1-9

To General or

Local Routing

Carry Chain

The carry chain provides a fast carry function between the dedicated adders in arithmetic or shared arithmetic mode.

The two-bit carry select feature in Cyclone V devices halves the propagation delay of carry chains within the ALM. Carry chains can begin in either the first ALM or the fifth ALM in a LAB. The final carry-out signal is routed to an ALM, where it is fed to local, row, or column interconnects.

To avoid routing congestion in one small area of the device when a high fan-in arithmetic function is implemented, the LAB can support carry chains that only use either the top half or bottom half of the LAB before connecting to the next LAB. This leaves the other half of the ALMs in the LAB available for implementing narrower fan-in functions in normal mode. Carry chains that use the top five ALMs in the first LAB carry into the top half of the ALMs in the next LAB in the column. Carry chains that use the bottom five ALMs in the first LAB carry into the bottom half of the ALMs in the next LAB within the column. You can bypass the top-half of the LAB columns and bottom-half of the MLAB columns.

The Quartus II Compiler creates carry chains longer than 20 ALMs (10 ALMs in arithmetic or shared arithmetic mode) by linking LABs together automatically. For enhanced fitting, a long carry chain runs vertically, allowing fast horizontal connections to the TriMatrix memory and DSP blocks. A carry chain can continue as far as a full column.

Shared Arithmetic Mode

The ALM in shared arithmetic mode can implement a 3-input add in the ALM.

This mode configures the ALM with four 4-input LUTs. Each LUT either computes the sum of three inputs or the carry of three inputs. The output of the carry computation is fed to the next adder using a dedicated connection called the shared arithmetic chain.

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Shared Arithmetic Mode

Figure 1-9: ALM in Shared Arithmetic Mode for Cyclone V Devices

shared_arith_in carry_in labclk

4-Input

LUT datae0 datac datab dataa

4-Input

LUT reg0 reg1 datad datae1

4-Input

LUT

4-Input

LUT reg2

To General or

Local Routing

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shared_arith_out carry_out reg3

Shared Arithmetic Chain

The shared arithmetic chain available in enhanced arithmetic mode allows the ALM to implement a 3-input adder. This significantly reduces the resources necessary to implement large adder trees or correlator functions.

The shared arithmetic chain can begin in either the first or sixth ALM in a LAB.

Similar to carry chains, the top and bottom half of the shared arithmetic chains in alternate LAB columns can be bypassed. This capability allows the shared arithmetic chain to cascade through half of the ALMs in an LAB while leaving the other half available for narrower fan-in functionality. In every LAB, the column is top-half bypassable; while in MLAB, columns are bottom-half bypassable.

The Quartus II Compiler creates shared arithmetic chains longer than 20 ALMs (10 ALMs in arithmetic or shared arithmetic mode) by linking LABs together automatically. To enhance fitting, a long shared arithmetic chain runs vertically, allowing fast horizontal connections to the TriMatrix memory and DSP blocks. A shared arithmetic chain can continue as far as a full column.

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Document Revision History

1-11

Document Revision History

Date

January 2014

Version

2014.01.10

May 2013

December 2012

June 2012

November 2011

October 2011

2013.05.06

2012.12.28

2.0

1.1

1.0

Changes

Added multiplexers for the bypass paths and register outputs in the following diagrams:

• ALM High-Level Block Diagram for Cyclone V Devices

• Template for Supported 7-Input Functions in Extended LUT Mode for

Cyclone V Devices

• ALM in Arithmetic Mode for Cyclone V Devices

• ALM in Shared Arithmetic Mode for Cyclone V Devices

• Added link to the known document issues in the Knowledge Base.

• Removed register chain outputs information in ALM output section.

• Removed reg_chain_in and reg_chain_out ports in ALM high-level block diagram and ALM connection details diagram.

Reorganized content and updated template.

Updated for the Quartus II software v12.0 release:

• Restructured chapter.

• Updated Figure 1–6.

Minor text edits.

Initial release.

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The embedded memory blocks in the devices are flexible and designed to provide an optimal amount of small- and large-sized memory arrays to fit your design requirements.

Related Information

Cyclone V Device Handbook: Known Issues

Lists the planned updates to the

Cyclone V Device Handbook

chapters.

Types of Embedded Memory

The Cyclone V devices contain two types of memory blocks:

• 10 Kb M10K blocks—blocks of dedicated memory resources. The M10K blocks are ideal for larger memory arrays while still providing a large number of independent ports.

• 640 bit memory logic array blocks (MLABs)—enhanced memory blocks that are configured from dualpurpose logic array blocks (LABs). The MLABs are ideal for wide and shallow memory arrays. The MLABs are optimized for implementation of shift registers for digital signal processing (DSP) applications, wide shallow FIFO buffers, and filter delay lines. Each MLAB is made up of ten adaptive logic modules (ALMs).

In the Cyclone V devices, you can configure these ALMs as ten 32 x 2 blocks, giving you one 32 x 20 simple dual-port SRAM block per MLAB.

Embedded Memory Capacity in Cyclone V Devices

Table 2-1: Embedded Memory Capacity and Distribution in Cyclone V Devices

Variant

Cyclone V E

Member

Code

A2

A4

A5

A7

A9

Block

M10K

RAM Bit (Kb)

176

308

446

686

1,220

1,760

3,080

4,460

6,860

12,200

Block

MLAB

RAM Bit (Kb)

314

485

679

1338

2748

196

303

424

836

1,717

Total RAM Bit (Kb)

1,956

3,383

4,884

7,696

13,917

2

©

2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with

Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO

9001:2008

Registered www.altera.com

101 Innovation Drive, San Jose, CA 95134

2-2

Embedded Memory Design Guidelines for Cyclone V Devices

Variant

Cyclone V GX

Cyclone V GT

Cyclone V SE

Cyclone V SX

Cyclone V ST

Member

Code

A4

A5

A6

C2

D5

D7

D9

A2

C3

C4

C5

C7

C9

C4

C5

C6

D5

D6

M10K

RAM Bit (Kb)

1,190

2,500

4,460

6,860

12,200

4,460

6,860

12,200

1,400

2,700

3,970

5,570

1,400

2,700

3,970

5,570

3,970

5,570

Block

270

397

557

140

446

686

1,220

140

119

250

446

686

1,220

270

397

557

397

557

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MLAB

RAM Bit (Kb)

231

480

621

138

424

836

1,717

138

159

295

424

836

1,717

231

480

621

480

621

Block

370

768

994

221

679

1338

2748

221

255

472

679

1338

2748

370

768

994

768

994

Total RAM Bit (Kb)

1,349

2,795

4,884

7,696

13,917

4,884

7,696

13,917

1,538

2,460

4,450

5,761

1,538

2,460

4,450

5,761

4,450

5,761

Embedded Memory Design Guidelines for Cyclone V Devices

There are several considerations that require your attention to ensure the success of your designs. Unless noted otherwise, these design guidelines apply to all variants of this device family.

Guideline: Consider the Memory Block Selection

The Quartus II software automatically partitions the user-defined memory into the memory blocks based on your design's speed and size constraints. For example, the Quartus II software may spread out the memory across multiple available memory blocks to increase the performance of the design.

To assign the memory to a specific block size manually, use the RAM megafunction in the MegaWizard

Plug-In Manager.

For the memory logic array blocks (MLAB), you can implement single-port SRAM through emulation using the Quartus II software. Emulation results in minimal additional use of logic resources.

Because of the dual-purpose architecture of the MLAB, only data input and output registers are available in the block. The MLABs gain read address registers from the ALMs. However, the write address and read data registers are internal to the MLABs.

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Guideline: Implement External Conflict Resolution

Guideline: Implement External Conflict Resolution

2-3

In the true dual-port RAM mode, you can perform two write operations to the same memory location.

However, the memory blocks do not have internal conflict resolution circuitry. To avoid unknown data being written to the address, implement external conflict resolution logic to the memory block.

Guideline: Customize Read-During-Write Behavior

Customize the read-during-write behavior of the memory blocks to suit your design requirements.

Figure 2-1: Read-During-Write Data Flow

This figure shows the difference between the two types of read-during-write operations available—same port and mixed port.

FPGA Device

Port A data in

Port B data in

Mixed-port data flow

Same-port data flow

Port A data out

Port B data out

Same-Port Read-During-Write Mode

The same-port read-during-write mode applies to a single-port RAM or the same port of a true dual-port

RAM.

Table 2-2: Output Modes for Embedded Memory Blocks in Same-Port Read-During-Write Mode

This table lists the available output modes if you select the embedded memory blocks in the same-port read-during-write mode.

Output Mode Memory Type Description

"new data"

(flow-through)

"don't care"

M10K

M10K, MLAB

The new data is available on the rising edge of the same clock cycle on which the new data is written.

The RAM outputs "don't care" values for a read-during-write operation.

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Mixed-Port Read-During-Write Mode

Figure 2-2: Same-Port Read-During-Write: New Data Mode

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This figure shows sample functional waveforms of same-port read-during-write behavior in the “new data” mode.

clk_a

0A 0B address rden wren byteena data_a q_a (asynch)

A123

A123

B456

B456

C789

C789

11

DDDD

DDDD

EEEE

EEEE

FFFF

FFFF

Mixed-Port Read-During-Write Mode

The mixed-port read-during-write mode applies to simple and true dual-port RAM modes where two ports perform read and write operations on the same memory address using the same clock—one port reading from the address, and the other port writing to it.

Table 2-3: Output Modes for RAM in Mixed-Port Read-During-Write Mode

Output Mode

"new data"

Memory Type

MLAB

"old data"

"don't care"

M10K, MLAB

M10K, MLAB

Description

A read-during-write operation to different ports causes the

MLAB registered output to reflect the “new data” on the next rising edge after the data is written to the MLAB memory.

This mode is available only if the output is registered.

A read-during-write operation to different ports causes the

RAM output to reflect the “old data” value at the particular address.

For MLAB, this mode is available only if the output is registered.

The RAM outputs “don’t care” or “unknown” value.

• For M10K memory, the Quartus II software does not analyze the timing between write and read operations.

• For MLAB, the Quartus II software analyzes the timing between write and read operations by default. To disable this behavior, turn on the Do not analyze the timing

between write and read operation. Metastability issues are prevented by never writing and reading at the

same address at the same time option.

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Output Mode

"constrained don't care"

Memory Type

MLAB

Mixed-Port Read-During-Write Mode

2-5

Description

The RAM outputs “don’t care” or “unknown” value. The

Quartus II software analyzes the timing between write and read operations in the MLAB.

Figure 2-3: Mixed-Port Read-During-Write: New Data Mode

This figure shows a sample functional waveform of mixed-port read-during-write behavior for the “new data” mode.

clk_a&b wren_a address_a data_a byteena_a rden_b address_b q_b (registered)

AAAA

XXXX

A0

BBBB

A0

AAAA

CCCC

11

BBBB

DDDD

CCCC

A1

EEEE

A1

DDDD

FFFF

EEEE FFFF

Figure 2-4: Mixed-Port Read-During-Write: Old Data Mode

This figure shows a sample functional waveform of mixed-port read-during-write behavior for the “old data” mode.

clk_a&b wren_a address_a data_a byteena_a rden_b address_b q_b (asynch)

AAAA

A0

BBBB

A0

A0 (old data) AAAA

CCCC

11

DDDD

A1

EEEE

A1

BBBB A1 (old data) DDDD

FFFF

EEEE

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Guideline: Consider Power-Up State and Memory Initialization

Figure 2-5: Mixed-Port Read-During-Write: Don’t Care or Constrained Don’t Care Mode

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This figure shows a sample functional waveform of mixed-port read-during-write behavior for the “don’t care” or “constrained don’t care” mode.

clk_a&b wren_a address_a data_a byteena_a rden_b address_b q_b (asynch)

AAAA

11

BBBB

A0

CCCC

01 10

A0

DDDD

XXXX (unknown data)

A1

EEEE

11

A1

FFFF

In the dual-port RAM mode, the mixed-port read-during-write operation is supported if the input registers have the same clock. The output value during the operation is “unknown.”

Related Information

Internal Memory (RAM and ROM) User Guide

Provides more information about the RAM megafunction that controls the read-during-write behavior.

Guideline: Consider Power-Up State and Memory Initialization

Consider the power up state of the different types of memory blocks if you are designing logic that evaluates the initial power-up values, as listed in the following table.

Table 2-4: Initial Power-Up Values of Embedded Memory Blocks

Memory Type

MLAB

M10K

Output Registers

Used

Bypassed

Used

Bypassed

Power Up Value

Zero (cleared)

Read memory contents

Zero (cleared)

Zero (cleared)

By default, the Quartus II software initializes the RAM cells in Cyclone V devices to zero unless you specify a .mif.

All memory blocks support initialization with a .mif. You can create .mif files in the Quartus II software and specify their use with the RAM megafunction when you instantiate a memory in your design. Even if a memory is pre-initialized (for example, using a .mif), it still powers up with its output cleared.

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Guideline: Control Clocking to Reduce Power Consumption

Related Information

Internal Memory (RAM and ROM) User Guide

Provides more information about .mif files.

Quartus II Handbook

Provides more information about .mif files.

2-7

Guideline: Control Clocking to Reduce Power Consumption

Reduce AC power consumption in your design by controlling the clocking of each memory block:

• Use the read-enable signal to ensure that read operations occur only when necessary. If your design does not require read-during-write, you can reduce your power consumption by deasserting the read-enable signal during write operations, or during the period when no memory operations occur.

• Use the Quartus II software to automatically place any unused memory blocks in low-power mode to reduce static power.

Embedded Memory Features

Table 2-5: Memory Features in Cyclone V Devices

This table summarizes the features supported by the embedded memory blocks.

Features M10K

Maximum operating frequency 315 MHz

Total RAM bits (including parity bits) 10,240

Parity bits

Byte enable

Packed mode

Address clock enable

Simple dual-port mixed width

True dual-port mixed width

FIFO buffer mixed width

Memory Initialization File (.mif)

Mixed-clock mode

Fully synchronous memory

Asynchronous memory

Supported

Supported

Supported

Supported

Supported

Supported

Supported

Supported

Supported

Supported

MLAB

420 MHz

640

Supported

Supported

Supported

Supported

Supported

Supported

Only for flow-through read memory operations.

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Embedded Memory Configurations

Features

Power-up state

Asynchronous clears

Write/read operation triggering

Same-port read-during-write

Mixed-port read-during-write

ECC support

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M10K

Output ports are cleared.

MLAB

• Registered output ports—Cleared.

• Unregistered output ports—Read memory contents.

Output registers and output latches

Rising clock edges

Output ports set to

"new data" or "don't care".

(The "don't care" mode applies only for the single-port RAM mode).

Output registers and output latches

Rising clock edges

Output ports set to "don't care".

Output ports set to "old data" or "don't care".

Output ports set to "old data", "new data", "don't care", or "constrained don't care".

Soft IP support using the Quartus II software.

Soft IP support using the Quartus II software.

Related Information

Internal Memory (RAM and ROM) User Guide

Provides more information about the embedded memory features.

Embedded Memory Configurations

Table 2-6: Supported Embedded Memory Block Configurations for Cyclone V Devices

This table lists the maximum configurations supported for the embedded memory blocks. The information is applicable only to the single-port RAM and ROM modes.

Memory Block Depth (bits) Programmable Width

MLAB

M10K

1K

2K

4K

8K

32

256

512 x16, x18, or x20 x40 or x32 x20 or x16 x10 or x8 x5 or x4 x2 x1

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Mixed-Width Port Configurations

Mixed-Width Port Configurations

2-9

The mixed-width port configuration is supported in the simple dual-port RAM and true dual-port RAM memory modes.

Note:

MLABs do not support mixed-width port configurations.

Related Information

Internal Memory (RAM and ROM) User Guide

Provides more information about dual-port mixed width support.

M10K Blocks Mixed-Width Configurations

Table 2-7: M10K Block Mixed-Width Configurations in Simple Dual-Port RAM Mode

Read Port

8K x 1

4K x 2

2K x 4

2K x 5

1K x 8

1K x 10

512 x 16

512 x 20

256 x 32

256 x 40

8K x 1

Yes

Yes

Yes

Yes

Yes

Yes

4K x 2

Yes

Yes

Yes

Yes

Yes

Yes

2K x 4

Yes

Yes

Yes

Yes

Yes

Yes

2K x 5

Yes

Yes

Yes

Yes

1K x 8

Write Port

1k x 10 512 x 16 512 x 20 256 x 32

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Table 2-8: M10K Block Mixed-Width Configurations in True Dual-Port Mode

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Port B

8K x 1

4K x 2

2K x 4

2K x 5

1K x 8

1K x 10

512 x 16

8K x 1

Yes

Yes

Yes

Yes

Yes

4K x 2

Yes

Yes

Yes

Yes

Yes

2K x 4

Yes

Yes

Yes

Yes

Yes

2K x 5

Yes

Yes

Port A

1K x 8

Yes

Yes

Yes

Yes

Yes

1K x 10

Yes

Yes

512 x 16

Yes

Yes

Yes

Yes

Yes

512 x 20

Yes

Yes

256 x 40

Yes

Yes

Yes

Yes

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Embedded Memory Modes

Port B

512 x 20

8K x 1

4K x 2

2K x 4

2K x 5

Yes

Port A

1K x 8

1K x 10

Yes

512 x 16

512 x 20

Yes

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Embedded Memory Modes

Caution:

To avoid corrupting the memory contents, do not violate the setup or hold time on any of the memory block input registers during read or write operations. This is applicable if you use the memory blocks in single-port RAM, simple dual-port RAM, true dual-port RAM, or ROM mode.

Table 2-9: Memory Modes Supported in the Embedded Memory Blocks

This table lists and describes the memory modes that are supported in the Cyclone V embedded memory blocks.

Memory Mode

M10K

Support

MLAB

Support Description

Single-port RAM Yes Yes You can perform only one read or one write operation at a time.

Use the read enable port to control the RAM output ports behavior during a write operation:

• To retain the previous values that are held during the most recent active read enable—create a read-enable port and perform the write operation with the read enable port deasserted.

• To show the new data being written, the old data at that address, or a "Don't Care" value when read-during-write occurs at the same address location—do not create a read-enable signal, or activate the read enable during a write operation.

Simple dual-port

RAM

Yes Yes

True dual-port

RAM

Shift-register

Yes

Yes

Yes

You can simultaneously perform one read and one write operations to different locations where the write operation happens on port A and the read operation happens on port B.

You can perform any combination of two port operations: two reads, two writes, or one read and one write at two different clock frequencies.

You can use the memory blocks as a shift-register block to save logic cells and routing resources.

This is useful in DSP applications that require local data storage such as finite impulse response (FIR) filters, pseudo-random number generators, multi-channel filtering, and auto- and crosscorrelation functions. Traditionally, the local data storage is implemented with standard flip-flops that exhaust many logic cells for large shift registers.

The input data width (w), the length of the taps (m), and the number of taps (n) determine the size of a shift register

(w × m × n). You can cascade memory blocks to implement larger shift registers.

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Memory Mode

ROM

FIFO

M10K

Support

Yes

Yes

Embedded Memory Clocking Modes

2-11

MLAB

Support

Yes

Yes

Description

You can use the memory blocks as ROM.

• Initialize the ROM contents of the memory blocks using a .mif or .hex.

• The address lines of the ROM are registered on M10K blocks but can be unregistered on MLABs.

• The outputs can be registered or unregistered.

• The output registers can be asynchronously cleared.

• The ROM read operation is identical to the read operation in the single-port RAM configuration.

You can use the memory blocks as FIFO buffers. Use the SCFIFO and DCFIFO megafunctions to implement single- and dual-clock asynchronous FIFO buffers in your design.

For designs with many small and shallow FIFO buffers, the

MLABs are ideal for the FIFO mode. However, the MLABs do not support mixed-width FIFO mode.

Related Information

Internal Memory (RAM and ROM) User Guide

Provides more information memory modes.

RAM-Based Shift Register (ALTSHIFT_TAPS) Megafunction User Guide

Provides more information about implementing the shift register mode.

SCFIFO and DCFIFO Megafunctions User Guide

Provides more information about implementing FIFO buffers.

Embedded Memory Clocking Modes

This section describes the clocking modes for the Cyclone V memory blocks.

Caution:

To avoid corrupting the memory contents, do not violate the setup or hold time on any of the memory block input registers during read or write operations.

Clocking Modes for Each Memory Mode

Table 2-10: Memory Blocks Clocking Modes Supported for Each Memory Mode

Clocking Mode

Single clock mode

Read/write clock mode

Single-Port

Yes

Simple Dual-

Port

Yes

Yes

Memory Mode

True Dual-

Port

Yes

ROM

Yes

FIFO

Yes

Yes

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Single Clock Mode

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Clocking Mode

Input/output clock mode

Independent clock mode

Single-Port

Yes

Simple Dual-

Port

Yes

Memory Mode

True Dual-

Port

ROM

Yes

Yes

Yes

Yes

FIFO

Note:

The clock enable signals are not supported for write address, byte enable, and data input registers on MLAB blocks.

Single Clock Mode

In the single clock mode, a single clock, together with a clock enable, controls all registers of the memory block.

Read/Write Clock Mode

In the read/write clock mode, a separate clock is available for each read and write port. A read clock controls the data-output, read-address, and read-enable registers. A write clock controls the data-input, write-address, write-enable, and byte enable registers.

Input/Output Clock Mode

In input/output clock mode, a separate clock is available for each input and output port. An input clock controls all registers related to the data input to the memory block including data, address, byte enables, read enables, and write enables. An output clock controls the data output registers.

Independent Clock Mode

In the independent clock mode, a separate clock is available for each port (A and B). Clock A controls all registers on the port A side; clock B controls all registers on the port B side.

Note:

You can create independent clock enable for different input and output registers to control the shut down of a particular register for power saving purposes. From the parameter editor, click More

Options (beside the clock enable option) to set the available independent clock enable that you prefer.

Asynchronous Clears in Clocking Modes

In all clocking modes, asynchronous clears are available only for output latches and output registers. For the independent clock mode, this is applicable on both ports.

Output Read Data in Simultaneous Read/Write

If you perform a simultaneous read/write to the same address location using the read/write clock mode, the output read data is unknown. If you require the output read data to be a known value, use single-clock or input/output clock mode and select the appropriate read-during-write behavior in the MegaWizard

Plug-

In Manager.

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Independent Clock Enables in Clocking Modes

Independent Clock Enables in Clocking Modes

Independent clock enables are supported in the following clocking modes:

• Read/write clock mode—supported for both the read and write clocks.

• Independent clock mode—supported for the registers of both ports.

To save power, you can control the shut down of a particular register using the clock enables.

Related Information

Guideline: Control Clocking to Reduce Power Consumption

on page 2-7

2-13

Parity Bit in Memory Blocks

Table 2-11: Parity Bit Support for the Embedded Memory Blocks

This table describes the parity bit support for the memory blocks.

M10K MLAB

• The parity bit is the fifth bit associated with each

4 data bits in data widths of 5, 10, 20, and 40 (bits

4, 9, 14, 19, 24, 29, 34, and 39).

• In non-parity data widths, the parity bits are skipped during read or write operations.

• Parity function is not performed on the parity bit.

• The parity bit is the ninth bit associated with each byte.

• The ninth bit can store a parity bit or serve as an additional bit.

• Parity function is not performed on the parity bit.

Byte Enable in Embedded Memory Blocks

The embedded memory blocks support byte enable controls:

• The byte enable controls mask the input data so that only specific bytes of data are written. The unwritten bytes retain the values written previously.

• The write enable ( wren

) signal, together with the byte enable ( byteena

) signal, control the write operations on the RAM blocks. By default, the byteena signal is high (enabled) and only the wren signal controls the writing.

• The byte enable registers do not have a clear port.

• If you are using parity bits, on the M10K blocks, the byte enable function controls 8 data bits and 2 parity bits; on the MLABs, the byte enable function controls all 10 bits in the widest mode.

• The MSB and LSB of the byteena signal correspond to the MSB and LSB of the data bus, respectively.

• The byte enables are active high.

Byte Enable Controls in Memory Blocks

Table 2-12: byteena

Controls in x20 Data Width byteena[1:0]

11 (default)

[19:10]

Data Bits Written

[9:0]

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Data Byte Output byteena[1:0]

10

01

Table 2-13: byteena

Controls in x40 Data Width

[19:10]

byteena[3:0]

1111 (default)

1000

0100

0010

0001

[39:30]

[39:30]

Data Bits Written

[29:20]

[29:20]

Data Bits Written

[19:10]

[19:10]

[9:0]

[9:0]

[9:0]

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Data Byte Output

In M10K blocks, the corresponding masked data byte output appears as a “don’t care” value.

In MLABs, when you de-assert a byte-enable bit during a write cycle, the corresponding data byte output appears as either a “don't care” value or the current data at that location. You can control the output value for the masked byte in the MLABs by using the Quartus II software.

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RAM Blocks Operations

Figure 2-6: Byte Enable Functional Waveform

RAM Blocks Operations

2-15

This figure shows how the wren and byteena signals control the operations of the RAM blocks. For the

M10K blocks, the write-masked data byte output appears as a “don’t care” value because the “current data” value is not supported.

inclock wren address data byteena contents at a0 contents at a1 contents at a2 contents at a3 contents at a4 an

XXXXXXXX

XXXX a0

1000

FFFFFFFF

FFFFFFFF

FFFFFFFF a1

0100

FFFFFFFF

FFFFFFFF a2

ABCDEF12

0010 a3 a4 a0

XXXXXXXX

XXXX 0001 1111

ABFFFFFF

FFCDFFFF

FFFFEFFF

FFFFFF12

ABCDEF12 don’t care: q (asynch) current data: q (asynch) doutn doutn

ABXXXXXX

ABFFFFFF

XXCDXXXX XXXXEFXX

FFCDFFFF FFFFEFFF

XXXXXX12

FFFFFF12

ABCDEF12

ABCDEF12

ABFFFFFF

ABFFFFFF

Memory Blocks Packed Mode Support

The M10K memory blocks support packed mode.

The packed mode feature packs two independent single-port RAM blocks into one memory block. The

Quartus II software automatically implements packed mode where appropriate by placing the physical RAM block in true dual-port mode and using the MSB of the address to distinguish between the two logical RAM blocks. The size of each independent single-port RAM must not exceed half of the target block size.

Memory Blocks Address Clock Enable Support

The embedded memory blocks support address clock enable, which holds the previous address value for as long as the signal is enabled ( addressstall = 1

). When the memory blocks are configured in dual-port mode, each port has its own independent address clock enable. The default value for the address clock enable signal is low (disabled).

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Memory Blocks Address Clock Enable Support

Figure 2-7: Address Clock Enable

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This figure shows an address clock enable block diagram. The address clock enable is referred to by the port name addressstall

.

address[0]

1

0 address[0] register address[0]

1

0 address[N] register address[N] address[N] addressstall clock

Figure 2-8: Address Clock Enable During Read Cycle Waveform

This figure shows the address clock enable waveform during the read cycle.

inclock rdaddress rden a0 addressstall latched address

(inside memory) an q (synch) doutn-1 q (asynch) doutn a0 a1 doutn dout0 dout0 a2 a1 a3 dout1 dout1 a4 a4 dout4 a5 a5 dout4 dout5 a6

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Document Revision History

Figure 2-9: Address Clock Enable During the Write Cycle Waveform

This figure shows the address clock enable waveform during the write cycle.

inclock wraddress data wren addressstall latched address

(inside memory) contents at a0 contents at a1 contents at a2 contents at a3 contents at a4 contents at a5 an

XX a0

00

XX a0 a1

01

01

XX a2

02

XX a1

02

XX

XX a3

03

00 a4

04 a4

03 a5

05

04 a5

05 a6

06

2-17

Document Revision History

Date

May 2013

Version

2013.05.06

Changes

• Moved all links to the Related Information section of respective topics for easy reference.

• Added link to the known document issues in the Knowledge Base.

• Updated the maximum operating frequency of the MLAB.

• Corrected the description about the "don't care" output mode for RAM in mixed-port read-during-write.

• Reorganized the structure of the supported memory configurations topics (single-port and mixed-width dual-port) to improve clarity about maximum data widths supported for each configuration.

• Added a description to the table listing the maximum embedded memory configurations to clarify that the information applies only to the single port or ROM mode.

• Removed the topic about mixed-width configurations for MLABs and added a note to clarify that MLABs do not support mixed-width configuration.

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Document Revision History

Date

December 2012

Version

2012.12.28

June 2012

October 2011

2.0

1.0

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Changes

• Reorganized content and updated template.

• Added memory capacity information from the

Cyclone V Device

Overview

for easy reference.

• Moved information about supported memory block configurations into its own table.

• Added short descriptions of each clocking mode.

• Added topic about the packed mode support.

• Added topic about the address clock enable support.

• Restructured the chapter.

• Updated the “Memory Modes”, “Clocking Modes”, and “Design

Considerations” sections.

• Updated Table 2–1.

• Added the “Parity Bit” and “Byte Enable” sections.

• Moved the memory capacity information to the

Cyclone V Device

Overview

.

Initial release.

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Variable Precision DSP Blocks in Cyclone V Devices

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This chapter describes how the variable-precision digital signal processing (DSP) blocks in Cyclone V devices are optimized to support higher bit precision in high-performance DSP applications.

Related Information

Cyclone V Device Handbook: Known Issues

Lists the planned updates to the

Cyclone V Device Handbook

chapters.

Features

The Cyclone V variable precision DSP blocks offer the following features:

• High-performance, power-optimized, and fully registered multiplication operations

• 9-bit, 18-bit, and 27-bit word lengths

• Two 18 x 19 complex multiplications

• Built-in addition, subtraction, and dual 64-bit accumulation unit to combine multiplication results

• Cascading 19-bit or 27-bit to form the tap-delay line for filtering applications

• Cascading 64-bit output bus to propagate output results from one block to the next block without external logic support

• Hard pre-adder supported in 19-bit, and 27-bit mode for symmetric filters

• Internal coefficient register bank for filter implementation

• 18-bit and 27-bit systolic finite impulse response (FIR) filters with distributed output adder

Related Information

Cyclone V Device Overview

Provides more information about the number of multipliers in each Cyclone V device.

3

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2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with

Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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3-2

Supported Operational Modes in Cyclone V Devices

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Supported Operational Modes in Cyclone V Devices

Table 3-1: Variable Precision DSP Blocks Operational Modes for Cyclone V Devices

Variable-Precision

DSP Block Resource

Operation Mode

Supported

Instance

1 variable precision DSP block

2 variable precision DSP blocks

Independent

9 x 9 multiplication

Independent

18 x 18 multiplication

Independent

18 x 19 multiplication

Independent

18 x 25 multiplication

Independent

20 x 24 multiplication

Independent

27 x 27 multiplication

Two 18 x 19 multiplier adder mode

18 x 18 multiplier adder summed with

36-bit input

Complex 18 x 19 multiplication

3

2

2

1

1

1

1

1

1

Pre-Adder

Support

No

Yes

Yes

Yes

Yes

Yes

Yes

Yes

No

Coefficient

Support

Input

Cascade

Support

(1)

No

Yes

Yes

Yes

Yes

Yes

Yes

No

No

No

Yes

Yes

Yes

Yes

Yes

Yes

No

Yes

Chainout Support

No

No

No

Yes

Yes

Yes

Yes

Yes

No

(1)

When you enable the pre-adder feature, the input cascade support is not available.

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Resources

3-3

Resources

Table 3-2: Number of Multipliers in Cyclone V Devices

The table lists the variable-precision DSP resources by bit precision for each Cyclone V device.

Independent Input and Output

18 x 18

Variant

Member

Code

Variableprecision

DSP Block

Multiplications Operator

9 x 9 18 x 18 27 x 27

Multiplier

Adder

Mode

Multiplier Multiplier Multiplier

Cyclone V E

Cyclone V GX

Cyclone V GT

Cyclone V SE

Cyclone V SX

Cyclone V ST

342

36

84

87

156

342

150

156

342

51

70

150

25

66

150

156

112

36

84

87

112

87

112

342

36

84

87

156

342

150

156

342

51

70

150

25

66

150

156

112

36

84

87

112

87

112

684

72

168

174

312

684

300

312

684

102

140

300

50

132

300

312

224

72

168

174

224

174

224

468

1,026

450

468

1,026

108

252

261

1,026

153

210

450

75

198

450

468

336

108

252

261

336

261

336

342

36

84

87

156

342

150

156

342

51

70

150

25

66

150

156

112

36

84

87

112

87

112

D9

A2

A4

A5

C7

C9

D5

D7

A9

C3

C4

C5

A2

A4

A5

A7

C6

D5

D6

A6

C2

C4

C5

18 x 18

Multiplier Adder

Summed with

36 bit Input

342

36

84

87

156

342

150

156

342

51

70

150

25

66

150

156

112

36

84

87

112

87

112

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Design Considerations

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Design Considerations

You should consider the following elements in your design:

• Operational modes

• Internal coefficient and pre-adder

• Accumulator

• Chainout adder

Operational Modes

The Quartus II software includes megafunctions that you can use to control the operation mode of the multipliers. After entering the parameter settings with the MegaWizard Plug-In Manager, the Quartus II software automatically configures the variable precision DSP block.

Altera provides two methods for implementing various modes of the Cyclone V variable precision DSP block in a design—using the Quartus II DSP megafunction and HDL inferring.

The following Quartus II megafunctions are supported for the Cyclone V variable precision DSP blocks implementation:

• LPM_MULT

• ALTMULT_ADD

• ALTMULT_ACCUM

• ALTMULT_COMPLEX

Related Information

Introduction to Megafunction User Guide

Integer Arithmetic Megafunctions User Guide

Floating-Point Megafunctions User Guide

Quartus II Software Help

Internal Coefficient and Pre-Adder

To use the pre-adder feature, all input data and multipliers must have the same clock setting.

The input cascade support is not available when you enable the pre-adder feature.

In both 18-bit and 27-bit modes, you can use the coefficient feature and pre-adder feature independently.

Accumulator

The accumulator in the Cyclone V devices supports double accumulation by enabling the 64-bit double accumulation registers located between the output register bank and the accumulator.

The double accumulation registers are set statically in the programming file.

Chainout Adder

You can use the output chaining path to add results from other DSP blocks.

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Block Architecture

3-5

Block Architecture

The Cyclone V variable precision DSP block consists of the following elements:

• Input register bank

• Pre-adder

• Internal coefficient

• Multipliers

• Adder

• Accumulator and chainout adder

• Systolic registers

• Double accumulation register

• Output register bank

If the variable precision DSP block is not configured in systolic FIR mode, both systolic registers are bypassed.

Figure 3-1: Variable Precision DSP Block Architecture for Cyclone V Devices

scanin

CLK[2..0]

ENA[2..0]

ACLR[1..0] chainin[63..0]

LOADCONST

ACCUMULATE

NEGATE

SUB_COMPLEX dataa_y0[18..0] dataa_z0[17..0] dataa_x0[17..0]

COEFSELA[2..0] datab_y1[18..0] datab_z1[17..0] datab_x1[17..0]

COEFSELB[2..0]

Pre-Adder

+/-

Systolic

Registers

(1)

Internal

Coefficient

Pre-Adder

+/-

Multiplier

Systolic

Register (1) x

Multiplier

Adder

+/-

+

Chainout adder/ accumulator x

Internal

Coefficient

Constant

Double

Accumulation

Register

Result[73..0] scanout

Note:

1. When enabled, systolic registers are clocked with the same clock source as the output register bank.

chainout[63..0]

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Input Register Bank

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Input Register Bank

The input register bank consists of data, dynamic control signals, and two sets of delay registers.

All the registers in the DSP blocks are positive-edge triggered and cleared on power up. Each multiplier operand can feed an input register or a multiplier directly, bypassing the input registers.

The following variable precision DSP block signals control the input registers within the variable precision

DSP block:

CLK[2..0]

ENA[2..0]

ACLR[0]

In 18 x 19 mode, you can use the delay registers to balance the latency requirements when you use both the input cascade and chainout features.

The tap-delay line feature allows you to drive the top leg of the multiplier input, dataa_y0 and datab_y1 in

18 x 19 mode and dataa_y0 only in 27 x 27 mode, from the general routing or cascade chain.

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Input Register Bank

Figure 3-2: Input Register of a Variable Precision DSP Block in 18 x 19 Mode for Cyclone V Devices

3-7

The figures show the data registers only. Registers for the control signals are not shown.

CLK[2..0] scanin[18..0]

ENA[2..0]

ACLR[0] dataa_y0[18..0] dataa_z0[17..0] dataa_x0[17..0] datab_y1[18..0]

Delay registers datab_z1[17..0] datab_x1[17..0]

Delay registers scanout[18..0]

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Pre-Adder

Figure 3-3: Input Register of a Variable Precision DSP Block in 27 x 27 Mode for Cyclone V Devices

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The figures show the data registers only. Registers for the control signals are not shown.

CLK[2..0] scanin[26..0]

ENA[2..0]

ACLR[0] dataa_y0[26..0] dataa_z0[25..0] dataa_x0[26..0] scanout[26..0]

Pre-Adder

Cyclone V Devices

Each variable precision DSP block has two 19-bit pre-adders. You can configure these pre-adders in the following configurations:

• Two independent 19-bit pre-adders

• One 27-bit pre-adder

The pre-adder supports both addition and subtraction in the following input configurations:

• 18-bit (signed) addition or subtraction for 18 x 19 mode

• 17-bit (unsigned) addition or subtraction for 18 x 19 mode

• 26-bit addition or subtraction for 27 x 27 mode

Internal Coefficient

The Cyclone V variable precision DSP block has the flexibility of selecting the multiplicand from either the dynamic input or the internal coefficient.

The internal coefficient can support up to eight constant coefficients for the multiplicands in 18-bit and

27-bit modes. When you enable the internal coefficient feature,

COEFSELA

/

COEFSELB are used to control the selection of the coefficient multiplexer.

Multipliers

A single variable precision DSP block can perform many multiplications in parallel, depending on the data width of the multiplier.

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Adder

3-9

There are two multipliers per variable precision DSP block. You can configure these two multipliers in several operational modes:

• One 27 x 27 multiplier

• Two 18 (signed)/(unsigned) x 19 (signed) multipliers

• Three 9 x 9 multipliers

Related Information

Operational Mode Descriptions

on page 3-10

Provides more information about the operational modes of the multipliers.

Adder

You can use the adder in various sizes, depending on the operational mode:

• One 64-bit adder with the 64-bit accumulator

• Two 18 x 19 modes—the adder is divided into two 37-bit adders to produce the full 37-bit result of each independent 18 x 19 multiplication

• Three 9 x 9 modes—you can use the adder as three 18-bit adders to produce three 9 x 9 multiplication results independently

Accumulator and Chainout Adder

The Cyclone V variable precision DSP block supports a 64-bit accumulator and a 64-bit adder.

The following signals can dynamically control the function of the accumulator:

NEGATE

LOADCONST

ACCUMULATE

The accumulator supports double accumulation by enabling the 64-bit double accumulation registers located between the output register bank and the accumulator.

The double accumulation registers are set statically in the programming file.

The accumulator and chainout adder features are not supported in two independent 18 x 19 modes and three independent 9 x 9 modes.

Table 3-3: Accumulator Functions and Dynamic Control Signals

This table lists the dynamic signals settings and description for each function. In this table, X denotes a "don't care" value.

Function Description NEGATE LOADCONST ACCUMULATE

Zeroing

Preload

Disables the accumulator.

Loads an initial value to the accumulator.

Only one bit of the

64-bit preload value can be “1”. It can be used as rounding the

DSP result to any position of the 64-bit result.

0

0

0

1

0

0

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Systolic Registers

Function

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Accumulation

Decimation

Description

Adds the current result to the previous accumulate result.

This function takes the current result, converts it into two’s complement, and adds it to the previous result.

NEGATE

0

1

LOADCONST

X

X

ACCUMULATE

1

1

Systolic Registers

There are two systolic registers per variable precision DSP block. If the variable precision DSP block is not configured in systolic FIR mode, both systolic registers are bypassed.

The first set of systolic registers consists of 18-bit and 19-bit registers that are used to register the 18-bit and

19-bit inputs of the upper multiplier, respectively.

The second set of systolic registers are used to delay the chainout output to the next variable precision DSP block.

You must clock all the systolic registers with the same clock source as the output register bank.

Double Accumulation Register

The double accumulation register is an extra register in the feedback path of the accumulator. Enabling the double accumulation register will cause an extra clock cycle delay in the feedback path of the accumulator.

This register has the same

CLK

,

ENA

, and

ACLR settings as the output register bank.

By enabling this register, you can have two accumulator channels using the same number of variable precision

DSP block.

Output Register Bank

The positive edge of the clock signal triggers the 64-bit bypassable output register bank and is cleared after power up.

The following variable precision DSP block signals control the output register per variable precision DSP block:

CLK[2..0]

ENA[2..0]

ACLR[1]

Operational Mode Descriptions

This section describes how you can configure an Cyclone V variable precision DSP block to efficiently support the following operational modes:

• Independent Multiplier Mode

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Independent Multiplier Mode

3-11

• Independent Complex Multiplier Mode

• Multiplier Adder Sum Mode

• 18 x 18 Multiplication Summed with 36-Bit Input Mode

• Systolic FIR Mode

Independent Multiplier Mode

In independent input and output multiplier mode, the variable precision DSP blocks perform individual multiplication operations for general purpose multipliers.

Table 3-4: Variable Precision DSP Block Independent Multiplier Mode Configurations

Configuration

9 x 9

18 (signed) x 18 (unsigned)

18 (unsigned) x 18 (unsigned)

18 (signed) x 19 (signed)

18 (unsigned) x 19 (signed)

18 x 25

20 x 24

27 x 27

Multipliers per block

3

2

1

1

1

9 x 9 Independent Multiplier

Figure 3-4: Three 9 x 9 Independent Multiplier Mode per Variable Precision DSP Block for Cyclone V Devices

Three pairs of data are packed into the ax and ay ports; result contains three 18-bit products.

Variable-Precision DSP Block

Multiplier

27 ay[y2, y1, y0]

54 x Result[53..0]

(p2, p1, p0)

27 ax[x2, x1, x0]

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18 x 18 or 18 x 19 Independent Multiplier

18 x 18 or 18 x 19 Independent Multiplier

Figure 3-5: Two 18 x 18 or 18 x 19 Independent Multiplier Mode per Variable Precision DSP Block for

Cyclone V Devices

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In this figure, the variables are defined as follows:

• n = 19 and m = 37 for 18 x 19 mode

• n = 18 and m = 36 for 18 x 18 mode

Variable-Precision DSP Block n

Multiplier data_b1[(n-1)..0] m x

[(m-1)..0]

18 data_a1[17..0] data_b0[(n-1)..0] n

Multiplier x m

[(m-1)..0]

18 data_a0[17..0]

18 x 25 Independent Multiplier

Figure 3-6: One 18 x 25 Independent Multiplier Mode per Variable Precision DSP Block for Cyclone V Devices

In this mode, the result can be up to 52 bits when combined with a chainout adder or accumulator.

Variable-Precision DSP Block

Multiplier

18 dataa_b0[17..0]

43 x

Result[42..0]

25 dataa_a0[24..0]

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20 x 24 Independent Multiplier

3-13

20 x 24 Independent Multiplier

Figure 3-7: One 20 x 24 Independent Multiplier Mode per Variable Precision DSP Block for Cyclone V Devices

In this mode, the result can be up to 52 bits when combined with a chainout adder or accumulator.

Variable-Precision DSP Block

Multiplier

20 dataa_b0[19..0]

44 x

Result[43..0]

24 dataa_a0[23..0]

27 x 27 Independent Multiplier

Figure 3-8: One 27 x 27 Independent Multiplier Mode per Variable Precision DSP Block for Cyclone V Devices

In this mode, the result can be up to 64 bits when combined with a chainout adder or accumulator.

Variable-Precision DSP Block

Multiplier

27 dataa_b0[26..0]

54 x

Result[53..0]

27 dataa_a0[26..0]

Independent Complex Multiplier Mode

The Cyclone V devices support the 18 x 19 complex multiplier mode using two Cyclone V variable-precision

DSP blocks.

Figure 3-9: Sample of Complex Multiplication Equation

The imaginary part [(a × d) + (b × c)] is implemented in the first variable-precision DSP block, while the real part [(a × c) - (b × d)] is implemented in the second variable-precision DSP block.

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18 x 19 Complex Multiplier

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18 x 19 Complex Multiplier

Figure 3-10: One 18 x 19 Complex Multiplier with Two Variable Precision DSP Blocks for Cyclone V Devices

c[18..0] b[17..0]

Variable-Precision DSP Block 1

Multiplier

19 x

18

Adder

38

Multiplier

+ Imaginary Part

(ad+bc) d[18..0] a[17..0]

19

18 x d[18..0] b[17..0] c[18..0] a[17..0]

Variable-Precision DSP Block 2

Multiplier

19 x

18

Multiplier

19

18 x

Adder

-

38

Real Part

(ac-bd)

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Multiplier Adder Sum Mode

3-15

Multiplier Adder Sum Mode

Figure 3-11: One Sum of Two 18 x 19 Multipliers with One Variable Precision DSP Block for Cyclone V

Devices

SUB_COMPLEX dataa_y0[18..0]

Variable-Precision DSP Block

19

Multiplier x

18

Chainout adder or accumulator dataa_x0[17..0]

38

Result[37..0]

+/+

Multiplier

19 datab_y1[18..0]

Adder x

18 datab_x1[17..0]

18 x 18 Multiplication Summed with 36-Bit Input Mode

Cyclone V variable precision DSP blocks support one 18 x 18 multiplication summed to a 36-bit input.

Use the upper multiplier to provide the input for an 18 x 18 multiplication, while the bottom multiplier is bypassed. The datab_y1[17..0] and datab_y1[35..18] signals are concatenated to produce a 36-bit input.

Figure 3-12: One 18 x 18 Multiplication Summed with 36-Bit Input Mode for Cyclone V Devices

Variable-Precision DSP Block

SUB_COMPLEX

Multiplier

18 dataa_y0[17..0] x

18 dataa_x0[17..0]

Chainout adder or accumulator

18

37 datab_y1[35..18]

+/-

+

Result[36..0]

18 datab_y1[17..0]

Adder

Systolic FIR Mode

The basic structure of a FIR filter consists of a series of multiplications followed by an addition.

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18-Bit Systolic FIR Mode

Figure 3-13: Basic FIR Filter Equation

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Depending on the number of taps and the input sizes, the delay through chaining a high number of adders can become quite large. To overcome the delay performance issue, the systolic form is used with additional delay elements placed per tap to increase the performance at the cost of increased latency.

Figure 3-14: Systolic FIR Filter Equivalent Circuit

y [ n ] x [ n ] c

1 w ] c

2 w ] c k − 1 w k−

1 n

] c k w k [ n ]

Cyclone V variable precision DSP blocks support the following systolic FIR structures:

• 18-bit

• 27-bit

In systolic FIR mode, the input of the multiplier can come from four different sets of sources:

• Two dynamic inputs

• One dynamic input and one coefficient input

• One coefficient input and one pre-adder output

• One dynamic input and one pre-adder output

18-Bit Systolic FIR Mode

In 18-bit systolic FIR mode, the adders are configured as dual 44-bit adders, thereby giving 8 bits of overhead when using an 18-bit operation (36-bit products). This allows a total of 256 multiplier products.

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Figure 3-15: 18-Bit Systolic FIR Mode for Cyclone V Devices

chainin[43..0]

44

Multiplier

Systolic

Register (1) dataa_y0[17..0] dataa_z0[17..0] dataa_x0[17..0]

COEFSELA[2..0]

18

18

18

3

Pre-Adder

+/-

Systolic

Registers (1) x datab_y1[17..0] datab_z1[17..0] datab_x1[17..0]

COEFSELB[2..0]

18

3

18

18

Internal

Coefficient

Pre-Adder

+/-

Multiplier x

Adder

27-Bit Systolic FIR Mode

+

Chainout adder or accumulator

44

Internal

Coefficient

18-bit Systolic FIR

44

3-17

Result[43..0] chainout[43..0]

Note:

1. The systolic registers have the same clock source as the output register bank.

27-Bit Systolic FIR Mode

In 27-bit systolic FIR mode, the chainout adder or accumulator is configured for a 64-bit operation, providing

10 bits of overhead when using a 27-bit data (54-bit products). This allows a total of 1,024 multiplier products.

The 27-bit systolic FIR mode allows the implementation of one stage systolic filter per DSP block.

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Document Revision History

Figure 3-16: 27-Bit Systolic FIR Mode for Cyclone V Devices

dataa_y0[25..0] dataa_z0[25..0] dataa_x0[26..0]

COEFSELA[2..0]

26

26

27

3

Pre-Adder

+/-

27

Internal

Coefficient chainin[63..0]

64

Multiplier x

+/-

27-bit Systolic FIR

Adder

+

Chainout adder or accumulator

64 chainout[63..0]

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Document Revision History

Date

January 2014

Version

2014.01.10

May 2013

December 2012

2013.05.06

2012.12.28

Changes

• Corrected variable-precision DSP block, 27 x 27 multiplier, 18 x 18 multiplier adder mode and 18 x 18 multiplier adder summed with 36 bit input for Cyclone V SE A4 from 58 to 84.

• Corrected 18 x 18 multiplier for Cyclone V SE A4 from 116 to 168.

• Corrected 9 x 9 multiplier for Cyclone V SE A4 from 174 to 252.

• Added link to the known document issues in the Knowledge Base.

• Moved all links to the Related Information section of respective topics for easy reference.

• Updated the variable DSP blocks and multipliers counts for the

Cyclone V SX device variants.

• Added resources for Cyclone V devices.

• Updated design considerations for Cyclone V devices in operational modes.

• Updated Figure 3-10, changed 37 to 38.

• Updated Figure 3-11, changed 37 to 38 and changed Result[36..0] to

Result [37..0].

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Date

June 2012

May 2011

Version

2.0

1.0

Document Revision History

3-19

Changes

Updated for the Quartus II software v12.0 release:

• Restructured chapter.

• Added “Design Considerations”, “Adder”, and “Double Accumulation

Register” sections.

• Updated Figure 3–1 and Figure 3–13.

• Added Table 3–3.

• Updated “Systolic Registers” and “Systolic FIR Mode” sections.

• Added Equation 3–2.

• Added Figure 3–12.

Initial release.

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Clock Networks and PLLs in Cyclone V Devices

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This chapter describes the advanced features of hierarchical clock networks and phase-locked loops (PLLs) in Cyclone V devices. The Quartus II software enables the PLLs and their features without external devices.

Related Information

Cyclone V Device Handbook: Known Issues

Lists the planned updates to the

Cyclone V Device Handbook

chapters.

Clock Networks

The Cyclone V devices contain the following clock networks that are organized into a hierarchical structure:

• Global clock (GCLK) networks

• Regional clock (RCLK) networks

• Periphery clock (PCLK) networks

4

©

2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with

Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO

9001:2008

Registered www.altera.com

101 Innovation Drive, San Jose, CA 95134

4-2

Clock Resources in Cyclone V Devices

Clock Resources in Cyclone V Devices

Table 4-1: Clock Resources in Cyclone V Devices

Clock Resource

Clock input pins

GCLK and RCLK networks

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Device

Number of Resources

Available

• Cyclone V E A5, A7, and A9

• Cyclone V GX C4,

C5, C7, and C9

• Cyclone V GT D5,

D7, and D9

24 single-ended or 12 differential

• Cyclone V E A2 and

A4

• Cyclone V GX C3

18 single-ended or 9 differential

• Cyclone V SE A5 and

A6

• Cyclone V SX C5 and

C6

• Cyclone V ST D5 and

D6

16 single-ended or 8 differential

• Cyclone V SE A2 and

A4

• Cyclone V SX C2 and

C4

12 single-ended or 6 differential

CLK[0..11][p,n]

CLK[0..3][p,n] and

Source of Clock Resource

CLK[8..11][p,n]

CLK[0..7][p,n]

CLK[0..3][p,n]

CLK[6,7][p,n] pins

,

CLK[6][p,n]

, pins and pins pins

• Cyclone V E A5, A7, and A9

• Cyclone V GX C4,

C5, C7, and C9

• Cyclone V GT D5,

D7, and D9

• GCLK networks: 16

• RCLK networks: 88

CLK[0..11][p,n] pins, PLL clock outputs, and logic array

• Cyclone V E A2 and

A4

• Cyclone V GX C3

CLK[0..3][p,n]

,

CLK[6][p,n]

,

CLK[8..11][p,n] pins, PLL clock outputs, and logic array

• Cyclone V SE A2 and

A4

• Cyclone V SX C2 and

C4

• GCLK networks: 16

• RCLK networks: 72

CLK[0..3][p,n]

CLK[6,7][p,n] and pins

• Cyclone V SE A5 and

A6

• Cyclone V SX C5 and

C6

• Cyclone V ST D5 and

D6

• GCLK networks: 16

• RCLK networks: 66

CLK[0..7][p,n] pins, PLL clock outputs, and logic array

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Clock Resource

PCLK networks

Types of Clock Networks

4-3

Device

Cyclone V E A2 and A4

Cyclone V GX C3

• Cyclone V E A5

• Cyclone V GX C4and

C5

• Cyclone V GT D5

• Cyclone V SE A2 and

A4

• Cyclone V SX C2 and

C4

• Cyclone V E A7

• Cyclone V GX C7

• Cyclone V GT D7

• Cyclone V SE A5 and

A6

• Cyclone V SX C5 and

C6

• Cyclone V ST D5 and

D6

• Cyclone V E A9

• Cyclone V GX C9

• Cyclone V GT D9

Number of Resources

Available

6

12

18

24

Source of Clock Resource

PLD-transceiver interface clocks,

I/O pins, and logic array

For more information about the clock input pins connections, refer to the pin connection guidelines.

Related Information

Cyclone V Device Family Pin Connection Guidelines

Types of Clock Networks

Global Clock Networks

Cyclone V devices provide GCLKs that can drive throughout the device. The GCLKs serve as low-skew clock sources for functional blocks, such as adaptive logic modules (ALMs), digital signal processing (DSP), embedded memory, and PLLs. Cyclone V I/O elements (IOEs) and internal logic can also drive GCLKs to create internally-generated global clocks and other high fan-out control signals, such as synchronous or asynchronous clear and clock enable signals.

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Regional Clock Networks

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Figure 4-1: GCLK Networks in Cyclone V E, GX, and GT Devices

This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.

CLK[8..11][p,n]

GCLK[12..15]

GCLK[0..3]

Q1

Q4

Q2

Q3

GCLK[8..11]

For Cyclone V E A2 and A4 devices, and Cyclone V GX C3 device, only CLK[6][p,n] pins are available.

GCLK[4..7]

CLK[0..3][p,n]

Figure 4-2: GCLK Networks in Cyclone V SE, SX, and ST Devices

This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.

CLK[6,7][p,n]

GCLK[12..15]

GCLK[0..3] GCLK[8..11]

Q1

Q4

Q2

Q3

GCLK network is not available in quadrant 2 for Cyclone V SE A5 and

A6 devices, Cyclone V ST D5 and

D6 devices, and Cyclone V SX C5 and C6 devices.

GCLK[4..7]

CLK[0..3][p,n]

Regional Clock Networks

RCLK networks are only applicable to the quadrant they drive into. RCLK networks provide the lowest clock insertion delay and skew for logic contained within a single device quadrant. The Cyclone V IOEs and

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Periphery Clock Networks

4-5

internal logic within a given quadrant can also drive RCLKs to create internally generated regional clocks and other high fan-out control signals.

Figure 4-3: RCLK Networks in Cyclone V E, GX, and GT Devices

This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.

RCLK[0..9]

CLK[8..11][p,n]

RCLK[10..19]

RCLK[40..45]

RCLK[46..51]

RCLK[64..69]

RCLK[70..75]

Q1 Q2

Q4 Q3

RCLK[82..87]

RCLK[58..63]

RCLK[30..39]

CLK[0..3][p,n]

RCLK[20..29]

RCLK[76..81]

RCLK[52..57]

For Cyclone V E A2 and A4 devices, and

Cyclone V GX C3 device, only CLK[6][p,n] pins are available.

Figure 4-4: RCLK Networks in Cyclone V SE, SX, and ST Devices

This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.

RCLK[0..9]

CLK[6,7][p,n]

RCLK[40..45]

RCLK[64..69]

RCLK[70..75]

Q1 Q2

Q4 Q3

RCLK network is not available in quadrant 2 for

Cyclone V SE A5 and A6 devices, and Cyclone V ST

D5 and D6 devices.

RCLK[82..87]

RCLK[58..63]

RCLK[30..39]

CLK[0..3][p,n]

RCLK[20..29]

RCLK[76..81]

RCLK[52..57]

Periphery Clock Networks

Cyclone V devices provide only horizontal PCLKs from the left periphery.

Clock outputs from the programmable logic device (PLD)-transceiver interface clocks, horizontal I/O pins, and internal logic can drive the PCLK networks.

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Periphery Clock Networks

PCLKs have higher skew when compared with GCLK and RCLK networks. You can use PCLKs for general purpose routing to drive signals into and out of the Cyclone V device.

Figure 4-5: PCLK Networks in Cyclone V E, GX, and GT Devices

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This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.

CLK[8..11][p,n]

Horizontal

PCLK

Horizontal

PCLK

Horizontal

PCLK

Horizontal

PCLK

Q1 Q2

Q4 Q3

For Cyclone V E A2 and A4 devices and Cyclone V GX C3 device, only CLK[6][p,n] pins are available.

CLK[0..3][p,n]

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Clock Sources Per Quadrant

4-7

Figure 4-6: PCLK Networks in Cyclone V SE, SX, and ST Devices

This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.

CLK[6,7][p,n]

Horizontal

PCLK

Horizontal

PCLK

Horizontal

PCLK

Horizontal

PCLK

Q1 Q2

Q4 Q3

CLK[0..3][p,n]

Clock Sources Per Quadrant

The Cyclone V devices provide 30 section clock (SCLK) networks in each spine clock per quadrant. The

SCLK networks can drive six row clocks in each logic array block (LAB) row, nine column I/O clocks, and two core reference clocks. The SCLKs are the clock resources to the core functional blocks, PLLs, and I/O interfaces of the device.

A spine clock is another layer of routing between the GCLK, RCLK, and PCLK networks before each clock is connected to the clock routing for each LAB row. The settings for spine clocks are transparent. The

Quartus II software automatically routes the spine clock based on the GCLK, RCLK, and PCLK networks.

The following figure shows SCLKs driven by the GCLK, RCLK, PCLK, or the PLL feedback clock networks in each spine clock per quadrant. The GCLK, RCLK, PCLK, and PLL feedback clocks share the same routing to the SCLKs. To ensure successful design fitting in the Quartus II software, the total number of clock resources must not exceed the SCLK limits in each region.

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Types of Clock Regions

Figure 4-7: Hierarchical Clock Networks in Each Spine Clock Per Quadrant

Clock output from the PLL that drives into the SCLKs.

GCLK

PLL Feedback Clock

PCLK

RCLK

There are up to 12 PCLKs that can drive the SCLKs in each spine clock per quadrant in the largest device.

There are up to 22 RCLKs that can drive the SCLKs in each spine clock per quadrant in the largest device.

16

5

12

22

SCLK

30

9

Column I/O clock: clock that drives the I/O column core registers and I/O interfaces.

2

Core reference clock: clock that feeds into the PLL as the PLL reference clock.

6

Row clock: clock source to the LAB, memory blocks, and row I/O interfaces in the core row.

For Cyclone V E A5 device, Cyclone V GX C3, C4, and C5 devices, and

Cyclone V GT D5 device, only 18 SCLKs are available in quadrant 3 and quadrant

4, which are SCLK[0,1], SCLK[5..10], SCLK[12..15], and SCLK[20..25].

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Types of Clock Regions

This section describes the types of clock regions in Cyclone V devices.

Entire Device Clock Region

To form the entire device clock region, a source drives a signal in a GCLK network that can be routed through the entire device. The source is not necessarily a clock signal. This clock region has the maximum insertion delay when compared with other clock regions, but allows the signal to reach every destination in the device.

It is a good option for routing global reset and clear signals or routing clocks throughout the device.

Regional Clock Region

To form a regional clock region, a source drives a signal in a RCLK network that you can route throughout one quadrant of the device. This clock region provides the lowest skew in a quadrant. It is a good option if all the destinations are in a single quadrant.

Dual-Regional Clock Region

To form a dual-regional clock region, a single source (a clock pin or PLL output) generates a dual-regional clock by driving two RCLK networks (one from each quadrant). This technique allows destinations across two adjacent device quadrants to use the same low-skew clock. The routing of this signal on an entire side has approximately the same delay as a RCLK region. Internal logic can also drive a dual-regional clock network.

Dual-regional clock region is only supported for quadrant 3 and quadrant 4 in Cyclone V SE, SX, and ST devices.

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Clock Network Sources

4-9

Figure 4-8: Dual-Regional Clock Region for Cyclone V Devices

This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.

Clock pins or PLL outputs can drive half of the device to create dual-regional clocking regions for improved interface timing.

Clock Network Sources

In Cyclone V devices, clock input pins, PLL outputs, high-speed serial interface (HSSI) outputs, and internal logic can drive the GCLK, RCLK, and PCLK networks.

Dedicated Clock Input Pins

You can use the dedicated clock input pins

(CLK[0..11][p,n]) for high fan-out control signals, such as asynchronous clears, presets, and clock enables, for protocol signals through the GCLK or RCLK networks.

CLK pins can be either differential clocks or single-ended clocks. When you use the

CLK pins as single-ended clock inputs, only the

CLK<#>p pins have dedicated connections to the PLL. The

CLK<#>n pins drive the PLLs over global or regional clock networks and do not have dedicated routing paths to the PLLs.

Driving a PLL over a global or regional clock can lead to higher jitter at the PLL input, and the PLL will not be able to fully compensate for the global or regional clock. Altera recommends using the

CLK<#>p pins for optimal performance when you use single-ended clock inputs to drive the PLLs.

Internal Logic

You can drive each GCLK, RCLK, and horizontal PCLK network using LAB-routing and row clock to enable internal logic to drive a high fan-out, low-skew signal.

Note:

Internally-generated GCLKs, RCLKs, or PCLKs cannot drive the Cyclone V PLLs. The input clock to the PLL has to come from dedicated clock input pins, PLL-fed GCLKs, or PLL-fed RCLKs.

HSSI Outputs

Every three HSSI outputs generate a group of four PCLKs to the core.

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PLL Clock Outputs

Related Information

PLLs and Clocking

on page 5-12

Provides more information about HSSI outputs.

LVDS Interface with External PLL Mode

on page 5-15

Provides more information about HSSI outputs.

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PLL Clock Outputs

The Cyclone V PLL clock outputs can drive both GCLK and RCLK networks.

Clock Input Pin Connections to GCLK and RCLK Networks

Table 4-2: Dedicated Clock Input Pin Connectivity to the GCLK Networks for Cyclone V E, GX, and GT Devices

Clock Resources

GCLK[0,1,2,3,4,5,6,7]

GCLK[8,9,10,11]

GCLK[0,1,2,3,12,13,14,15]

CLK[0,1,2,3]

CLK[4,5,6,7]

(2)

CLK[8,9,10,11]

CLK (p/n Pins)

Table 4-3: Dedicated Clock Input Pin Connectivity to the GCLK Networks for Cyclone V SE, SX, and ST Devices

CLK (p/n Pins) Clock Resources

GCLK[0,1,2,3,4,5,6,7]

GCLK[8,9,10,11]

GCLK[0,1,2,3,12,13,14,15]

CLK[0,1,2,3]

CLK[4,5]

(3)

CLK[6,7]

Table 4-4: Dedicated Clock Input Pin Connectivity to the RCLK Networks for Cyclone V E, GX, and GT Devices

A given clock input pin can drive two adjacent RCLK networks to create a dual-regional clock network.

Clock Resources CLK (p/n Pins)

RCLK[20,24,28,30,34,38,58,59,60,61,62,63,64,68,82,86] CLK[0]

RCLK[21,25,29,31,35,39,58,59,60,61,62,63,65,69,83,87]

RCLK[22,26,32,36,52,53,54,55,56,57,58,59,60,61,62,63,66,84]

RCLK[23,27,33,37,52,53,54,55,56,57,58,59,60,61,62,63,67,85]

RCLK[46,47,48,49,50,51,70,74,76,80]

RCLK[46,47,48,49,50,51,71,75,77,81]

CLK[1]

CLK[2]

CLK[3]

CLK[4]

(4)

CLK[5]

(4)

(2)

(3)

(4)

For Cyclone V E A2 and A4 devices, and Cyclone V GX C3 device, only

CLK[6] is available.

This applies to all Cyclone V SE, SX, and ST devices except for Cyclone V SE A2 and A4 devices, and

Cyclone V SX C2 and C4 devices.

This applies to all Cyclone V E, GX, and GT devices except for Cyclone V E A2 and A4 devices, and

Cyclone V GX C3 device.

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Clock Resources

RCLK[52,53,54,55,56,57,72,78]

RCLK[52,53,54,55,56,57,73,79]

RCLK[0,4,8,10,14,18,40,41,42,43,44,45,64,68,82,86]

RCLK[1,5,9,11,15,19,40,41,42,43,44,45,65,69,83,87]

RCLK[2,6,12,16,40,41,42,43,44,45,46,47,48,49,50,51,66,84]

RCLK[3,7,13,17,40,41,42,43,44,45,46,47,48,49,50,51,67,85]

Clock Output Connections

CLK (p/n Pins)

CLK[6]

CLK[7]

(4)

CLK[8]

CLK[9]

CLK[10]

CLK[11]

4-11

Table 4-5: Dedicated Clock Input Pin Connectivity to the RCLK Networks for Cyclone V SE, SX, and ST Devices

A given clock input pin can drive two adjacent RCLK networks to create a dual-regional clock network.

Clock Resources CLK (p/n pins)

RCLK[20,24,28,30,34,38,58,59,60,61,62,63,64,68,82,86] CLK[0]

RCLK[21,25,29,31,35,39,58,59,60,61,62,63,65,69,83,87]

RCLK[22,26,32,36,52,53,54,55,56,57,58,59,60,61,62,63,66,84]

RCLK[23,27,33,37,52,53,54,55,56,57,58,59,60,61,62,63,67,85]

RCLK[52,53,54,55,56,57,78]

RCLK[52,53,54,55,56,57,79]

RCLK[0,4,8,40,41,42,43,44,45,64,68,82,86]

RCLK[1,5,9,40,41,42,43,44,45,65,69,83,87]

CLK[1]

CLK[2]

CLK[3]

CLK[4]

(3)

CLK[5]

(3)

CLK[6]

CLK[7]

Clock Output Connections

For Cyclone V PLL connectivity to GCLK and RCLK networks, refer to the PLL connectivity to GCLK and

RCLK networks spreadsheet.

Related Information

PLL Connectivity to GCLK and RCLK Networks for Cyclone V Devices

Clock Control Block

Every GCLK, RCLK, and PCLK network has its own clock control block. The control block provides the following features:

• Clock source selection (dynamic selection available only for GCLKs)

• Global clock multiplexing

• Clock power down (static or dynamic clock enable or disable available only for GCLKs and RCLKs)

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Pin Mapping in Cyclone V Devices

Pin Mapping in Cyclone V Devices

Table 4-6: Mapping Between the Input Clock Pins, PLL Counter Outputs, and Clock Control Block Inputs

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Clock

inclk[0] and inclk[1] inclk[2] inclk[3]

Fed by

Any of the four dedicated clock pins on the same side of the Cyclone V device.

• PLL counters

C0 and

C2 from PLLs on the same side of the clock control block (for top, bottom, and right side of the Cyclone V device).

• PLL counter

C4 from PLLs on the same side of the clock control block

(for left side of the Cyclone V device).

PLL counters

C1 and

C3 from PLLs on the same side of the clock control block (for top, bottom, and right side of the Cyclone V device). This input clock port is not connected for the clock control block on left side of the

Cyclone V device.

GCLK Control Block

You can select the clock source for the GCLK select block either statically or dynamically using internal logic to drive the multiplexer-select inputs.

When selecting the clock source dynamically, you can select up to two PLL counter outputs and up to two clock pins.

Figure 4-9: GCLK Control Block for Cyclone V Devices

When the device is in user mode, you can dynamically control the clock select signals through internal logic.

PLL Counter

Outputs

CLKSELECT[1..0]

2

2

CLKp

Pins

2 CLKn

Pin

PLL Counter

Outputs

Internal

Logic

Static Clock

Select

This multiplexer supports user-controllable dynamic switching

Enable/

Disable

Internal

Logic

GCLK

The CLKn pin is not a dedicated clock input when used as a single-ended PLL clock input. The

CLKn pin can drive the PLL using the GCLK.

When the device is in user mode, you can only set the clock select signals through a configuration file (SRAM object file [.sof] or programmer object file [.pof]) because the signals cannot be controlled dynamically.

RCLK Control Block

You can only control the clock source selection for the RCLK select block statically using configuration bit settings in the configuration file (.sof or .pof) generated by the Quartus II software.

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Figure 4-10: RCLK Control Block for Cyclone V Devices

PCLK Control Block

PLL Counter

Outputs

2

CLKp

Pin

CLKn

Pin

Internal Logic

Static Clock Select

Enable/

Disable

Internal

Logic

RCLK

The CLKn pin is not a dedicated clock input when used as a single-ended PLL clock input. The

CLKn pin can drive the PLL using the RCLK.

When the device is in user mode, you can only set the clock select signals through a configuration file

(.sof or .pof); they cannot be controlled dynamically.

4-13

You can set the input clock sources and the clkena signals for the GCLK and RCLK network multiplexers through the Quartus II software using the ALTCLKCTRL megafunction.

Note:

When selecting the clock source dynamically using the ALTCLKCTRL megafunction, choose the inputs using the

CLKSELECT[0..1] signal. The inputs from the clock pins feed the inclk[0..1] ports of the multiplexer, and the PLL outputs feed the inclk[2..3] ports.

Related Information

Clock Control Block (ALTCLKCTRL) Megafunction User Guide

Provides more information about ALTCLKCTRL megafunction.

PCLK Control Block

To drive the HSSI horizontal PCLK control block, select the HSSI output or internal logic .

Figure 4-11: Horizontal PCLK Control Block for Cyclone V Devices

HSSI Output

Internal Logic

Static Clock Select

Horizontal PCLK

External PLL Clock Output Control Block

You can enable or disable the dedicated external clock output pins using the ALTCLKCTRL megafunction.

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Clock Power Down

Figure 4-12: External PLL Output Clock Control Block for Cyclone V Devices

The clock control block feeds to a multiplexer within the

FPLL_<#>_CLKOUT pin’s IOE. The

FPLL_<#>_CLKOUT pin is a dual-purpose pin. Therefore, this multiplexer selects either an internal signal or the output of the clock control block.

PLL Counter

Outputs

9

Static Clock Select

Enable/

Disable

Internal

Logic

IOE

Internal

Logic

Static Clock

Select

FPLL_<#>_CLKOUT pin

When the device is in user mode, you can only set the clock select signals through a configuration file

(.sof or .pof); they cannot be controlled dynamically.

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Related Information

Clock Control Block (ALTCLKCTRL) Megafunction User Guide

Provides more information about ALTCLKCTRL megafunction.

Clock Power Down

You can power down the GCLK and RCLK clock networks using both static and dynamic approaches.

When a clock network is powered down, all the logic fed by the clock network is in off-state, reducing the overall power consumption of the device. The unused GCLK, RCLK, and PCLK networks are automatically powered down through configuration bit settings in the configuration file (.sof or .pof) generated by the

Quartus II software.

The dynamic clock enable or disable feature allows the internal logic to control power-up or power-down synchronously on the GCLK and RCLK networks, including dual-regional clock regions. This feature is independent of the PLL and is applied directly on the clock network.

Note:

You cannot dynamically enable or disable GCLK or RCLK networks that drive PLLs.

Clock Enable Signals

You cannot use the clock enable and disable circuit of the clock control block if the GCLK or RCLK output drives the input of a PLL.

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Clock Enable Signals

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Figure 4-13: clkena

Implementation with Clock Enable and Disable Circuit

This figure shows the implementation of the clock enable and disable circuit of the clock control block.

The R1 and R2 bypass paths are not available for the PLL external clock outputs.

clkena

Clock Select

Multiplexer Output

D Q D Q

R1 R2

GCLK/

RCLK/

FPLL_<#>_CLKOUT

The select line is statically controlled by a bit setting in the .sof or .pof.

The clkena signals are supported at the clock network level instead of at the PLL output counter level. This allows you to gate off the clock even when you are not using a PLL. You can also use the clkena signals to control the dedicated external clocks from the PLLs.

Figure 4-14: Example of clkena

Signals

This figure shows a waveform example for a clock output enable. The clkena signal is synchronous to the falling edge of the clock output.

Clock Select

Multiplexer Output

Use the clkena signals to enable or disable the GCLK and RCLK networks or the

FPLL_<#>_CLKOUT pins.

clkena

AND Gate Output with R2 Bypassed

(ena Port Registered as

Falling Edge of Input Clock)

AND Gate Output with R2 Not Bypassed

(ena Port Registered as Double

Register with Input Clock)

Cyclone V devices have an additional metastability register that aids in asynchronous enable and disable of the GCLK and RCLK networks. You can optionally bypass this register in the Quartus II software.

The PLL can remain locked, independent of the clkena signals, because the loop-related counters are not affected. This feature is useful for applications that require a low-power or sleep mode. The clkena signal can also disable clock outputs if the system is not tolerant of frequency overshoot during resynchronization.

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Cyclone V PLLs

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Cyclone V PLLs

PLLs provide robust clock management and synthesis for device clock management, external system clock management, and high-speed I/O interfaces.

The Cyclone V device family contains fractional PLLs that can function as fractional PLLs or integer PLLs.

The output counters in Cyclone V devices are dedicated to each fractional PLL that support integer or fractional frequency synthesis.

The Cyclone V devices offer up to 8 fractional PLLs in the larger densities.

Table 4-7: PLL Features in Cyclone V Devices

Feature

Integer PLL

Fractional PLL

C output counters

M

,

N

,

C counter sizes

Dedicated external clock outputs

Dedicated clock input pins

External feedback input pin

Spread-spectrum input clock tracking

Source synchronous compensation

Direct compensation

Normal compensation

Zero-delay buffer compensation

External feedback compensation

LVDS compensation

Phase shift resolution

Programmable duty cycle

Power down mode

Support

Yes

Yes

9

1 to 512

2 single-ended and 1 differential

4 single-ended or 4 differential

Single-ended or differential

Yes

(5)

Yes

Yes

Yes

Yes

Yes

Yes

78.125 ps

(6)

Yes

Yes

PLL Physical Counters in Cyclone V Devices

The physical counters for the fractional PLLs are arranged in the following sequences:

• Up-to-down

(5)

(6)

Provided input clock jitter is within input jitter tolerance specifications. The modulation frequency of the input clock is below the PLL bandwidth which is specified in the Fitter report.

The smallest phase shift is determined by the voltage-controlled oscillator (VCO) period divided by eight. For degree increments, the Cyclone V device can shift all output frequencies in increments of at least 45°. Smaller degree increments are possible depending on the frequency and divide parameters.

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PLL Locations in Cyclone V Devices

• Down-to-up

Figure 4-15: PLL Physical Counters Orientation for Cyclone V Devices

4-17

This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.

PLL

Physical Counter C0

Physical Counter C1

Physical Counter

C0 to C8

(Up-to-Down

Sequence)

PLL

Physical Counter C8

Physical Counter C7

Physical Counter

C8 to C0

(Down-to-Up

Sequence)

Physical Counter C8 Physical Counter C0

PLL Locations in Cyclone V Devices

Cyclone V devices provide a PLL for each group of three transceiver channels. These PLLs are located in a strip, where the strip refers to an area in the FPGA.

For the PLL in the strip, only PLL counter

C[4..8] of the strip fractional PLLs are used in a clock network.

PLL counter

C[0..3] are used for supporting high-speed requirement of HSSI applications.

The total number of PLLs in the Cyclone V devices includes the PLLs in the PLL strip. However, the transceivers can only use the PLLs located in the strip.

The following figures show the physical locations of the fractional PLLs. Every index represents one fractional

PLL in the device. The physical locations of the fractional PLLs correspond to the coordinates in the Quartus II

Chip Planner.

Figure 4-16: PLL Locations for Cyclone V E A2 and A4 Devices

This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.

CLK[8..11][p,n]

Pins

CLK[10,11]

4 Logical Clocks 2 Logical Clocks

4

FRACTIONALPLL_X0_Y38 FRACTIONALPLL_X54_Y38

FRACTIONALPLL_X0_Y1

4

FRACTIONALPLL_X54_Y1

3

Logical

Clocks

1

Pins

CLK[6][p,n]

2 Logical Clocks

4 Logical Clocks

CLK[2,3]

Pins

CLK[0..3][p,n]

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PLL Locations in Cyclone V Devices

Figure 4-17: PLL Locations for Cyclone V GX C3 Device

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This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.

CLK[8..11][p,n]

Pins

CLK[10,11]

FRACTIONALPLL_X0_Y28

4

4 Logical Clocks

FRACTIONALPLL_X48_Y28

2 Logical Clocks

PLL Strip

4

FRACTIONALPLL_X0_Y13

FRACTIONALPLL_X48_Y1

3

Logical

Clock

1

Pins

CLK[6][p,n]

2 Logical Clocks

CLK[2,3]

Pins

CLK[0..3][p,n]

Figure 4-18: PLL Locations for Cyclone V E A5 Device, Cyclone V GX C4 and C5 Devices, and Cyclone V GT D5

Device

This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.

CLK[8..11][p,n]

Pins

CLK[10,11]

2 Logical Clocks

4 Logical Clocks

4

FRACTIONALPLL_X0_Y54 FRACTIONALPLL_X68_Y54

4

2

Logical

Clocks

Pins

CLK[4..5][p,n]

PLL Strip

4

FRACTIONALPLL_X0_Y30

FRACTIONALPLL_X0_Y14

4

FRACTIONALPLL_X0_Y1

4

4

Logical Clocks

FRACTIONALPLL_X68_Y1

4

CLK[2,3]

2

Logical

Clocks

2

Logical

Clocks

Pins

CLK[0..3][p,n]

Pins

CLK[6..7][p,n]

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PLL Locations in Cyclone V Devices

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Figure 4-19: PLL Locations for Cyclone V E A7 Device, Cyclone V GX C7 Device, and Cyclone V GT D7 Device

This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.

CLK[8..11][p,n]

Pins

CLK[10,11]

FRACTIONALPLL_X0_Y74

4

4 Logical Clocks

FRACTIONALPLL_X89_Y74

4

2 Logical Clocks

2

Logical

Clocks

Pins

CLK[4..5][p,n]

PLL Strip

4

FRACTIONALPLL_X0_Y56

FRACTIONALPLL_X0_Y32

2

2

4

FRACTIONALPLL_X0_Y15

FRACTIONALPLL_X0_Y1

4

4 Logical Clocks

FRACTIONALPLL_X89_Y1

4

CLK[2,3]

2

Logical

Clocks

2 Logical

Clocks

Pins

CLK[0..3][p,n]

Pins

CLK[6..7][p,n]

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PLL Locations in Cyclone V Devices

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Figure 4-20: PLL Locations for Cyclone V E A9 Device, Cyclone V GX C9 Device, and Cyclone V GT D9 Device

This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.

CLK[8..11][p,n]

Pins

CLK[10,11]

FRACTIONALPLL_X0_Y108

PLL Strip

FRACTIONALPLL_X0_Y81

4

4

4 Logical Clocks

FRACTIONALPLL_X121_Y108

4

2 Logical Clocks

2

Logical

Clocks

Pins

CLK[4..5][p,n]

FRACTIONALPLL_X0_Y64

4

FRACTIONALPLL_X0_Y39

4

FRACTIONALPLL_X0_Y22

4

FRACTIONALPLL_X0_Y1

4

4 Logical Clocks

FRACTIONALPLL_X121_Y1

4

CLK[2,3]

2

Logical

Clocks

2 Logical

Clocks

Pins

CLK[0..3][p,n]

Pins

CLK[6..7][p,n]

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PLL Locations in Cyclone V Devices

Figure 4-21: PLL Locations for Cyclone V SE A2 and A4 Devices, and Cyclone V SX C2 and C4 Devices

4-21

This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.

CLK[6,7][p,n]

Pins

2 Logical Clocks

FRACTIONALPLL_X0_Y54

2

PLL Strip

FRACTIONALPLL_X0_Y30

2

FRACTIONALPLL_X0_Y14

2

FRACTIONALPLL_X0_Y1

4

FRACTIONALPLL_X68_Y1

4 Logical Clocks

Pins

CLK[0..3][p,n]

CLK[2,3]

2

Logical Clocks

Figure 4-22: PLL Locations for Cyclone V SE A5 and A6 Devices, Cyclone V SX C5 and C6 Devices, and

Cyclone V ST D5 and D6 Devices

This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.

CLK[6,7][p,n]

Pins

2 Logical Clocks

2

FRACTIONALPLL_X0_Y74

PLL Strip

FRACTIONALPLL_X0_Y56

2

FRACTIONALPLL_X0_Y32

FRACTIONALPLL_X0_Y15

2

2

4

FRACTIONALPLL_X0_Y1

4

4 Logical Clocks

FRACTIONALPLL_X89_Y1

4

CLK[2,3]

2

Logical

Clocks

2 Logical

Clocks

Pins

CLK[0..3][p,n]

Pins

CLK[4,5][p,n]

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PLL Migration Guidelines

Related Information

PLL Migration Guidelines

on page 4-22

Provides more information about PLL migration between Cyclone V SX C2, C4, C5, and C6 devices.

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PLL Migration Guidelines

If you plan to migrate your design between Cyclone V SX C2, C4, C5, and C6 devices, and your design requires a PLL to drive the HSSI and clock network (GCLK or RCLK), use the PLLs on the left side of the device.

Table 4-8: Location of PLLs for PLL Migration

Variant

Cyclone V SX

Member Code

C2

C4

C5

C6

PLL Location (Left Side)

FRACTIONALPLL_X0_Y14

FRACTIONALPLL_X0_Y32

Related Information

PLL Locations in Cyclone V Devices

on page 4-17

Provides more information about

CLKIN pin connectivity to the PLLs.

Fractional PLL Architecture

Figure 4-23: Fractional PLL High-Level Block Diagram for Cyclone V Devices

For single-ended clock inputs, only the CLK<#>p pin has a dedicated connection to the PLL. If you use the

CLK<#>n pin, a global or regional clock is used.

pfdena

4

Dedicated

Clock Inputs

GCLK/RCLK inclk0 inclk1

Clock

Switchover

Block

Cascade Input from Adjacent PLL

Dedicated refclk

÷N clkswitch clkbad0 clkbad1 activeclock

PFD

Lock

Circuit locked

CP LF

VCO

8

÷2

VCO Post Divider

8

÷C0

÷C1

÷C2

÷C3

Delta Sigma

Modulator

÷C8

÷M

Direct Compensation Mode

ZDB, External Feedback Modes

LVDS Compensation Mode

Source Synchronous, Normal Modes

Casade Output to Adjacent PLL

GCLKs

RCLKs

External Clock Outputs

TX Serial Clock

TX Load Enable

FBOUT

Only C0 and C2 drive the TX serial clock and C1 and C3 can drive the TX load enable.

This FBOUT port is fed by the M counter in the PLLs.

External Memory

Interface DLL

PMA Clocks

FBIN

DIFFIOCLK Network

GCLK/RCLK Network

Fractional PLL Usage

You can configure the fractional PLL to function either in the integer or in the enhanced fractional mode.

One fractional PLL can use up to 9 output counters and all external clock outputs.

Fractional PLLs can be used as follows:

• Reduce the number of required oscillators on the board

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• Reduce the clock pins used in the FPGA by synthesizing multiple clock frequencies from a single reference clock source

• Compensate clock network delay

• Zero delay buffering

• Transmit clocking for transceivers

PLL Cascading

Cyclone V devices support two types of PLL cascading.

PLL-to-PLL Cascading

This cascading mode synthesizes a more precise output frequency than a single PLL in integer mode.

Cascading two PLLs in integer mode expands the effective range of the pre-scale counter,

N and the multiply counter,

M

.

Cyclone V devices only use adjpllin input clock source for inter-cascading between fracturable fractional

PLLs.

Altera recommends using a low bandwidth setting for the source (upstream) PLL and a high bandwidth setting for destination (downstream) PLL.

Counter-Output-to-Counter-Output Cascading

This cascading mode synthesizes a lower frequency output than a single post-scale counter,

C

. Cascading two

C counters expands the effective range of

C counters.

PLL External Clock I/O Pins

All Cyclone V external clock outputs for corner fractional PLLs (that are not from the PLL strips) are dualpurpose clock I/O pins. Two external clock output pins associated with each corner fractional PLL are organized as one of the following combinations:

• Two single-ended clock outputs

• One differential clock output

• Two single-ended clock outputs and one single-ended clock input in the I/O driver feedback for zero delay buffer (ZDB) mode support

• One single-ended clock output and one single-ended feedback input for single-ended external feedback

(EFB) mode support

• One differential clock output and one differential feedback input for differential EFB support

Note:

The external clock outputs support is dependent on the device density and package.

The following figure shows that any of the output counters (

C[0..8]

) or the

M counter on the PLLs can feed the dedicated external clock outputs. Therefore, one counter or frequency can drive all output pins available from a given PLL.

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PLL Control Signals

Figure 4-24: Dual-Purpose Clock I/O Pins Associated with PLL for Cyclone V Devices

I/O / FPLL_<#>_CLKOUT0/ FPLL_<#>_CLKOUTp /

FPLL_<#>_FB

Fractional PLL

VCO

C4

C5

C6

C2

C3

C0

C1

C7

C8

M

10 2

EXTCLKOUT[1..0]

EXTCLKOUT[0]

EXTCLKOUT[1] fbin

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I/O / FPLL_<#>_CLKOUT1 /FPLL_<#>_ CLKOUTn

I/O /FPLL_<#>_FBp

You can feed these clock output pins using any one of the C[8..0] or M counters. When not used as external clock outputs, you can use these clock output pins as regular user

I/Os.

The FPLL_<#>_CLKOUT0 and

FPLL_<#>_CLKOUT1 pins are single-ended clock output pins.

The FPLL_<#>_CLKOUTp and

FPLL_<#>_CLKOUTn pins are differential output pins while the FPLL_<#>_FBp and

FPLL_<#>_FBn pins are differential feedback input pins to support differential

EFB.

I/O / FPLL_<#>_FBn

The FPLL_<#>_FB pin is a single-ended feedback input pin for single-ended EFB mode.

Each pin of a single-ended output pair can be either in-phase or 180° out-of-phase. To implement the 180° out-of-phase pin in a pin pair, the Quartus II software places a NOT gate in the design into the IOE.

The clock output pin pairs support the following I/O standards:

• Same I/O standard for the pin pairs

• LVDS

• Differential high-speed transceiver logic (HSTL)

• Differential SSTL

Cyclone V PLLs can drive out to any regular I/O pin through the GCLK or RCLK network. You can also use the external clock output pins as user I/O pins if you do not require external PLL clocking.

Related Information

I/O Features in Cyclone V Devices

Provides more information about I/O standards supported by the PLL clock input and output pins.

Cyclone V Device Pin-Out Files

Provides more information about the external clock output availability.

Zero-Delay Buffer Mode

on page 4-28

External Feedback Mode

on page 4-29

PLL Control Signals

You can use the areset signal to control PLL operation and resynchronization, and use the locked signal to observe the status of the PLL.

areset

The areset signal is the reset or resynchronization input for each PLL. The device input pins or internal logic can drive these input signals.

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locked

4-25

When areset is driven high, the PLL counters reset, clearing the PLL output and placing the PLL out-oflock. The VCO is then set back to its nominal setting. When areset is driven low again, the PLL resynchronizes to its input as it re-locks.

You must assert the areset signal every time the PLL loses lock to guarantee the correct phase relationship between the PLL input and output clocks. You can set up the PLL to automatically reset (self-reset) after a loss-of-lock condition using the Quartus II MegaWizard Plug-In Manager.

You must include the areset signal if either of the following conditions is true:

• PLL reconfiguration or clock switchover is enabled in the design

• Phase relationships between the PLL input and output clocks must be maintained after a loss-of-lock condition

Note:

If the input clock to the PLL is not toggling or is unstable after power up, assert the areset signal after the input clock is stable and within specifications.

locked

The locked signal output of the PLL indicates the following conditions:

• The PLL has locked onto the reference clock.

• The PLL clock outputs are operating at the desired phase and frequency set in the MegaWizard Plug-In

Manager.

The lock detection circuit provides a signal to the core logic. The signal indicates when the feedback clock has locked onto the reference clock both in phase and frequency.

Clock Feedback Modes

This section describes the following clock feedback modes:

• Source synchronous

• LVDS compensation

• Direct

• Normal compensation

• ZDB

• EFB

Each mode allows clock multiplication and division, phase shifting, and programmable duty cycle.

The input and output delays are fully compensated by a PLL only when using the dedicated clock input pins associated with a given PLL as the clock source.

The input and output delays may not be fully compensated in the Quartus II software for the following conditions:

• When a GCLK or RCLK network drives the PLL

• When the PLL is driven by a dedicated clock pin that is not associated with the PLL

For example, when you configure a PLL in ZDB mode, the PLL input is driven by an associated dedicated clock input pin. In this configuration, a fully compensated clock path results in zero delay between the clock input and one of the clock outputs from the PLL. However, if the PLL input is fed by a non-dedicated input

(using the GCLK network), the output clock may not be perfectly aligned with the input clock.

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Source Synchronous Mode

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Source Synchronous Mode

If the data and clock arrive at the same time on the input pins, the same phase relationship is maintained at the clock and data ports of any IOE input register. Data and clock signals at the IOE experience similar buffer delays as long as you use the same I/O standard.

Altera recommends source synchronous mode for source synchronous data transfers.

Figure 4-25: Example of Phase Relationship Between Clock and Data in Source Synchronous Mode

Data Pin

PLL Reference Clock at the Input Pin

Data at the Register

Clock at the Register

The source synchronous mode compensates for the delay of the clock network used and any difference in the delay between the following two paths:

• Data pin to the IOE register input

• Clock input pin to the PLL phase frequency detector (PFD) input

The Cyclone V PLL can compensate multiple pad-to-input-register paths, such as a data bus when it is set to use source synchronous compensation mode.

LVDS Compensation Mode

The purpose of LVDS compensation mode is to maintain the same data and clock timing relationship seen at the pins of the internal serializer/deserializer (SERDES) capture register, except that the clock is inverted

(180° phase shift). Thus, LVDS compensation mode ideally compensates for the delay of the LVDS clock network, including the difference in delay between the following two paths:

• Data pin-to-SERDES capture register

• Clock input pin-to-SERDES capture register

The output counter must provide the 180° phase shift.

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Direct Mode

4-27

Figure 4-26: Example of Phase Relationship Between the Clock and Data in LVDS Compensation Mode

Data Pin

PLL Reference Clock at the Input Pin

Data at the Register

Clock at the Register

Direct Mode

In direct mode, the PLL does not compensate for any clock networks. This mode provides better jitter performance because the clock feedback into the PFD passes through less circuitry. Both the PLL internaland external-clock outputs are phase-shifted with respect to the PLL clock input.

Figure 4-27: Example of Phase Relationship Between the PLL Clocks in Direct Mode

Phase Aligned

PLL Reference

Clock at the

Input Pin

The PLL clock outputs lag the PLL input clocks depending on routing delays.

PLL Clock at the

Register Clock Port

External PLL

Clock Outputs

Normal Compensation Mode

An internal clock in normal compensation mode is phase-aligned to the input clock pin. The external clock output pin has a phase delay relative to the clock input pin if connected in this mode. The Quartus II

TimeQuest Timing Analyzer reports any phase difference between the two. In normal compensation mode, the delay introduced by the GCLK or RCLK network is fully compensated.

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Zero-Delay Buffer Mode

Figure 4-28: Example of Phase Relationship Between the PLL Clocks in Normal Compensation Mode

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Phase Aligned

PLL Reference

Clock at the Input Pin

PLL Clock at the

Register Clock Port

Dedicated PLL

Clock Outputs

The external clock output can lead or lag the PLL internal clock signals.

Zero-Delay Buffer Mode

In ZDB mode, the external clock output pin is phase-aligned with the clock input pin for zero delay through the device. This mode is supported on all Cyclone V PLLs.

When using this mode, you must use the same I/O standard on the input clocks and clock outputs to guarantee clock alignment at the input and output pins. You cannot use differential I/O standards on the PLL clock input or output pins.

To ensure phase alignment between the clk pin and the external clock output (

CLKOUT

) pin in ZDB mode, instantiate a bidirectional I/O pin in the design. The bidirectional I/O pin serves as the feedback path connecting the fbout and fbin ports of the PLL. The bidirectional I/O pin must always be assigned a singleended I/O standard. The PLL uses this bidirectional I/O pin to mimic and compensate for the output delay from the clock output port of the PLL to the external clock output pin.

Note:

To avoid signal reflection when using ZDB mode, do not place board traces on the bidirectional I/O pin.

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Figure 4-29: ZDB Mode in Cyclone V PLLs

External Feedback Mode

4-29

inclk

÷N PFD CP/LF

VCO

C8

M

C6

C7

C0

C1

EXTCLKOUT[0]

C2

C3

C4

10

Multiplexer

2

C5

EXTCLKOUT[1] fbout fbin

FPLL_<#>_FB

Figure 4-30: Example of Phase Relationship Between the PLL Clocks in ZDB Mode

Phase Aligned

PLL Reference

Clock at the Input Pin

The internal PLL clock output can lead or lag the external PLL clock outputs.

PLL Clock at the

Register Clock Port

Dedicated PLL

Clock Outputs

Related Information

PLL External Clock I/O Pins

on page 4-23

Provides more information about PLL clock outputs.

External Feedback Mode

In EFB mode, the output of the

M counter ( fbout) feeds back to the PLL fbin input (using a trace on the board) and becomes part of the feedback loop.

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External Feedback Mode

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One of the dual-purpose external clock outputs becomes the fbin input pin in this mode. The external feedback input pin, fbin is phase-aligned with the clock input pin. Aligning these clocks allows you to remove clock delay and skew between devices.

When using EFB mode, you must use the same I/O standard on the input clock, feedback input, and clock outputs.

This mode is supported only on the corner fractional PLLs. For Cyclone V E A2 and A4 devices, and

Cyclone V GX C3 device, EFB mode is supported only on the left corner fractional PLLs.

Figure 4-31: EFB Mode in Cyclone V Devices

EXTCLKOUT[0] fbout[p]

I/O / FPLL_<#>_CLKOUT0

/ FPLL_<#>_CLKOUTp /

FPLL_<#>_FB fbin inclk

÷

N PFD CP/LF VCO 0

C7

C8

M

C0

C1

C2

C3

C4

10

Multiplexer

2

C5

C6

EXTCLKOUT[1] fbout[n] fbout

I/O / FPLL_<#>_CLKOUT1 /

FPLL_<#>_ CLKOUTn fbin[p]

I/O /FPLL_<#>_FBp fbin[n]

I/O / FPLL_<#>_FBn

External board connection for one differential clock output and one differential feedback input for differential EFB support.

External

Board Trace

For differential EFB mode,

FPLL_<#>_CLKOUT[p,n] are the fbout[p,n] output pin; while

FPLL_<#>_FB[p,n] are the fbin[p,n] input pins.

External board connection for one single-ended clock output and one single-ended feedback input for single-ended EFB support.

For single-ended EFB mode,

FPLL_<#>_CLKOUT1 is the fbout output pin; while the FPLL_<#>_FB is the fbin input pin.

Figure 4-32: Example of Phase Relationship Between the PLL Clocks in EFB Mode

Phase Aligned

PLL Reference

Clock at the

Input Pin

PLL Clock at the Register

Clock Port

The PLL clock outputs can lead or lag the fbin clock input.

Dedicated PLL

Clock Outputs fbin Clock Input Pin

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Clock Multiplication and Division

4-31

Related Information

PLL External Clock I/O Pins

on page 4-23

Provides more information about PLL clock outputs.

Clock Multiplication and Division

Each Cyclone V PLL provides clock synthesis for PLL output ports using the M/(N × C) scaling factors. The input clock is divided by a pre-scale factor,

N

, and is then multiplied by the

M feedback factor. The control loop drives the VCO to match f in

× (M/N).

The Quartus II software automatically chooses the appropriate scaling factors according to the input frequency, multiplication, and division values entered into the ALTERA_PLL megafunction.

VCO Post Divider

A VCO post divider is inserted after the VCO. When you enable the VCO post divider, the VCO post divider divides the VCO frequency by two. When the VCO post divider is bypassed, the VCO frequency goes to the output port without being divided by two.

Post-Scale Counter,

C

Each output port has a unique post-scale counter,

C

, that divides down the output from the VCO post divider.

For multiple PLL outputs with different frequencies, the VCO is set to the least common multiple of the output frequencies that meets its frequency specifications. For example, if the output frequencies required from one PLL are 33 and 66 MHz, the Quartus II software sets the VCO to 660 MHz (the least common multiple of 33 and 66 MHz within the VCO range). Then the post-scale counters,

C

, scale down the VCO frequency for each output port.

Pre-Scale Counter,

N and Multiply Counter,

M

Each PLL has one pre-scale counter,

N

, and one multiply counter,

M

, with a range of 1 to 512 for both

M and

N

. The

N counter does not use duty-cycle control because the only purpose of this counter is to calculate frequency division. The post-scale counters have a 50% duty cycle setting. The high- and low-count values for each counter range from 1 to 256. The sum of the high- and low-count values chosen for a design selects the divide value for a given counter.

Delta-Sigma Modulator

The delta-sigma modulator (DSM) is used together with the

M multiply counter to enable the PLL to operate in fractional mode. The DSM dynamically changes the

M counter divide value on a cycle to cycle basis. The different

M counter values allow the "average"

M counter value to be a non-integer.

Fractional Mode

In fractional mode, the

M counter divide value equals to the sum of the "clock high" count, "clock low" count, and the fractional value. The fractional value is equal to

K

/2^

X

, where

K is an integer between 0 and (2^

X

– 1), and

X

= 8, 16, 24, or 32.

Integer Mode

For PLL operating in integer mode,

M is an integer value and DSM is disabled.

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Programmable Phase Shift

Related Information

Altera Phase-Locked Loop (ALTERA_PLL) Megafunction User Guide

Provides more information about PLL software support in the Quartus II software.

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Programmable Phase Shift

The programmable phase shift feature allows the PLLs to generate output clocks with a fixed phase offset.

The VCO frequency of the PLL determines the precision of the phase shift. The minimum phase shift increment is 1/8 of the VCO period. For example, if a PLL operates with a VCO frequency of 1000 MHz, phase shift steps of 125 ps are possible.

The Quartus II software automatically adjusts the VCO frequency according to the user-specified phase shift values entered into the megafunction.

Programmable Duty Cycle

The programmable duty cycle allows PLLs to generate clock outputs with a variable duty cycle. This feature is supported on the PLL post-scale counters.

The duty-cycle setting is achieved by a low and high time-count setting for the post-scale counters. To determine the duty cycle choices, the Quartus II software uses the frequency input and the required multiply or divide rate.

The post-scale counter value determines the precision of the duty cycle. The precision is defined as 50% divided by the post-scale counter value. For example, if the

C0 counter is 10, steps of 5% are possible for duty-cycle choices from 5% to 90%. If the PLL is in external feedback mode, set the duty cycle for the counter driving the fbin pin to 50%.

Combining the programmable duty cycle with programmable phase shift allows the generation of precise non-overlapping clocks.

Clock Switchover

The clock switchover feature allows the PLL to switch between two reference input clocks. Use this feature for clock redundancy or for a dual-clock domain application where a system turns on the redundant clock if the previous clock stops running. The design can perform clock switchover automatically when the clock is no longer toggling or based on a user control signal, clkswitch

.

The following clock switchover modes are supported in Cyclone V PLLs:

• Automatic switchover—The clock sense circuit monitors the current reference clock. If the current reference clock stops toggling, the reference clock automatically switches to inclk0 or inclk1 clock.

• Manual clock switchover—Clock switchover is controlled using the clkswitch signal. When the clkswitch signal goes from logic low to logic high, and stays high for at least three clock cycles, the reference clock to the PLL is switched from inclk0 to inclk1

, or vice-versa.

• Automatic switchover with manual override—This mode combines automatic switchover and manual clock switchover. When the clkswitch signal goes high, it overrides the automatic clock switchover function. As long as the clkswitch signal is high, further switchover action is blocked.

Automatic Switchover

Cyclone V PLLs support a fully configurable clock switchover capability.

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Automatic Switchover

Figure 4-33: Automatic Clock Switchover Circuit Block Diagram

This figure shows a block diagram of the automatic switchover circuit built into the PLL.

clkbad[0] clkbad[1] activeclock

Clock

Sense

clksw

Switchover

State Machine inclk0 inclk1

N Counter

Clock Switch

Control Logic

PFD clkswitch

Multiplexer

Out refclk

fbclk

4-33

When the current reference clock is not present, the clock sense block automatically switches to the backup clock for PLL reference. You can select a clock source as the backup clock by connecting it to the inclk1 port of the PLL in your design.

The clock switchover circuit sends out three status signals— clkbad[0]

, clkbad[1]

, and activeclock

—from the PLL to implement a custom switchover circuit in the logic array.

In automatic switchover mode, the clkbad[0] and clkbad[1] signals indicate the status of the two clock inputs. When they are asserted, the clock sense block detects that the corresponding clock input has stopped toggling. These two signals are not valid if the frequency difference between inclk0 and inclk1 is greater than 20%.

The activeclock signal indicates which of the two clock inputs ( inclk0 or inclk1

) is being selected as the reference clock to the PLL. When the frequency difference between the two clock inputs is more than 20%, the activeclock signal is the only valid status signal.

Note:

Glitches in the input clock may cause the frequency difference between the input clocks to be more than 20%.

Use the switchover circuitry to automatically switch between inclk0 and inclk1 when the current reference clock to the PLL stops toggling. You can switch back and forth between inclk0 and inclk1 any number of times when one of the two clocks fails and the other clock is available.

For example, in applications that require a redundant clock with the same frequency as the reference clock, the switchover state machine generates a signal ( clksw

) that controls the multiplexer select input. In this case, inclk1 becomes the reference clock for the PLL.

When using automatic clock switchover mode, the following requirements must be satisfied:

• Both clock inputs must be running when the FPGA is configured.

• The period of the two clock inputs can differ by no more than 20%.

If the current clock input stops toggling while the other clock is also not toggling, switchover is not initiated and the clkbad[0..1] signals are not valid. If both clock inputs are not the same frequency, but their period

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Automatic Switchover with Manual Override

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difference is within 20%, the clock sense block detects when a clock stops toggling. However, the PLL may lose lock after the switchover is completed and needs time to relock.

Note:

Altera recommends resetting the PLL using the areset signal to maintain the phase relationships between the PLL input and output clocks when using clock switchover.

Figure 4-34: Automatic Switchover After Loss of Clock Detection

This figure shows an example waveform of the switchover feature in automatic switchover mode. In this example, the inclk0 signal is stuck low. After the inclk0 signal is stuck at low for approximately two clock cycles, the clock sense circuitry drives the clkbad[0] signal high. Since the reference clock signal is not toggling, the switchover state machine controls the multiplexer through the clkswitch signal to switch to the backup clock, inclk1

.

inclk0 inclk1 muxout clkbad0 clkbad1 activeclock

Switchover is enabled on the falling edge of inclk0 or inclk1, depending on which clock is available. In this figure, switchover is enabled on the falling edge of inclk1.

Automatic Switchover with Manual Override

In automatic switchover with manual override mode, you can use the clkswitch signal for user- or systemcontrolled switch conditions. You can use this mode for same-frequency switchover, or to switch between inputs of different frequencies.

For example, if inclk0 is 66 MHz and inclk1 is 200 MHz, you must control switchover using the clkswitch signal. The automatic clock-sense circuitry cannot monitor clock input ( inclk0 and inclk1

) frequencies with a frequency difference of more than 100% (2×).

This feature is useful when the clock sources originate from multiple cards on the backplane, requiring a system-controlled switchover between the frequencies of operation.

You must choose the backup clock frequency and set the

M

,

N

,

C

, and

K counters so that the VCO operates within the recommended operating frequency range. The ALTERA_PLL MegaWizard Plug-in Manager notifies you if a given combination of inclk0 and inclk1 frequencies cannot meet this requirement.

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Manual Clock Switchover

4-35

Figure 4-35: Clock Switchover Using the clkswitch

(Manual) Control

This figure shows a clock switchover waveform controlled by the clkswitch signal. In this case, both clock sources are functional and inclk0 is selected as the reference clock; the clkswitch signal goes high, which starts the switchover sequence. On the falling edge of inclk0

, the counter’s reference clock, muxout

, is gated off to prevent clock glitching. On the falling edge of inclk1

, the reference clock multiplexer switches from inclk0 to inclk1 as the PLL reference. The activeclock signal changes to indicate the clock which is currently feeding the PLL.

inclk0 inclk1 muxout clkswitch activeclock clkbad0 clkbad1

To initiate a manual clock switchover event, both inclk0 and inclk1 must be running when the clkswitch signal goes high.

In automatic override with manual switchover mode, the activeclock signal mirrors the clkswitch signal.

Since both clocks are still functional during the manual switch, neither clkbad signal goes high. Because the switchover circuit is positive-edge sensitive, the falling edge of the clkswitch signal does not cause the circuit to switch back from inclk1 to inclk0

. When the clkswitch signal goes high again, the process repeats.

The clkswitch signal and automatic switch work only if the clock being switched to is available. If the clock is not available, the state machine waits until the clock is available.

Related Information

Altera Phase-Locked Loop (ALTERA_PLL) Megafunction User Guide

Provides more information about PLL software support in the Quartus II software.

Manual Clock Switchover

In manual clock switchover mode, the clkswitch signal controls whether inclk0 or inclk1 is selected as the input clock to the PLL. By default, inclk0 is selected.

A clock switchover event is initiated when the clkswitch signal transitions from logic low to logic high, and being held high for at least three inclk cycles.

You must bring the clkswitch signal back low again to perform another switchover event. If you do not require another switchover event, you can leave the clkswitch signal in a logic high state after the initial switch.

Pulsing the clkswitch signal high for at least three inclk cycles performs another switchover event.

If inclk0 and inclk1 are different frequencies and are always running, the clkswitch signal minimum high time must be greater than or equal to three of the slower frequency inclk0 and inclk1 cycles.

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Guidelines

Figure 4-36: Manual Clock Switchover Circuitry in Cyclone V PLLs

clkswitch

Clock Switch

Control Logic inclk0 inclk1

N Counter muxout refclk

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PFD fbclk

You can delay the clock switchover action by specifying the switchover delay in the ALTERA_PLL megafunction. When you specify the switchover delay, the clkswitch signal must be held high for at least three inclk cycles plus the number of the delay cycles that has been specified to initiate a clock switchover.

Related Information

Altera Phase-Locked Loop (ALTERA_PLL) Megafunction User Guide

Provides more information about PLL software support in the Quartus II software.

Guidelines

When implementing clock switchover in Cyclone V PLLs, use the following guidelines:

• Automatic clock switchover requires that the inclk0 and inclk1 frequencies be within 20% of each other. Failing to meet this requirement causes the clkbad[0] and clkbad[1] signals to not function properly.

• When using manual clock switchover, the difference between inclk0 and inclk1 can be more than 100%

(2×). However, differences in frequency, phase, or both, of the two clock sources will likely cause the PLL to lose lock. Resetting the PLL ensures that you maintain the correct phase relationships between the input and output clocks.

• Both inclk0 and inclk1 must be running when the clkswitch signal goes high to initiate the manual clock switchover event. Failing to meet this requirement causes the clock switchover to not function properly.

• Applications that require a clock switchover feature and a small frequency drift must use a low-bandwidth

PLL. When referencing input clock changes, the low-bandwidth PLL reacts more slowly than a highbandwidth PLL. When switchover happens, a low-bandwidth PLL propagates the stopping of the clock to the output more slowly than a high-bandwidth PLL. However, be aware that the low-bandwidth PLL also increases lock time.

• After a switchover occurs, there may be a finite resynchronization period for the PLL to lock onto a new clock. The time it takes for the PLL to relock depends on the PLL configuration.

• The phase relationship between the input clock to the PLL and the output clock from the PLL is important in your design. Assert areset for at least 10 ns after performing a clock switchover. Wait for the locked signal to go high and be stable before re-enabling the output clocks from the PLL.

• The VCO frequency gradually decreases when the current clock is lost and then increases as the VCO locks on to the backup clock, as shown in the following figure.

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Figure 4-37: VCO Switchover Operating Frequency

Primary Clock Stops Running

PLL Reconfiguration and Dynamic Phase Shift

4-37

Switchover Occurs

VCO Tracks Secondary Clock

Fvco

PLL Reconfiguration and Dynamic Phase Shift

For more information about PLL reconfiguration and dynamic phase shifting, refer to AN661.

Related Information

AN661: Implementing Fractional PLL Reconfiguration with ALTERA_PLL and

ALTERA_PLL_RECONFIG Megafunctions

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Document Revision History

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Document Revision History

Date

January 2014

Version

2014.01.10

Changes

• Removed Preliminary tags for clock resources, clock input pin connections to GCLK and RCLK networks, and PLL features tables.

• Updated clock resources table.

• Updated GCLK, RCLK, and PCLK networks diagrams for Cyclone V E,

GX, and GT devices.

• Added GCLK, RCLK, and PCLK networks diagrams for Cyclone V SE,

SX, and ST devices.

• Added notes to dedicated clock input pin connectivity to GCLK and

RCLK tables for Cyclone V SE, ST, and SX devices.

• Updated the following PLL locations diagrams:

• Cyclone V GX C3 device

• Cyclone V E A7 device, Cyclone V GX C7 device, and

Cyclone V GT D7 device

• Added the following PLL locations diagrams:

• Cyclone V SE A2 and A4 devices, and Cyclone V SX C2 and C4 devices

• Cyclone V SE A5 and A6 devices, Cyclone V SX C5 and C6 devices, and Cyclone V ST D5 and D6 devices

• Added information on PLL migration guidelines.

• Updated VCO post-scale counter,

K

, to VCO post divider.

• Added information on PLL cascading.

• Updated information on external clock output support.

• Added information on programmable phase shift.

• Updated automatic clock switchover mode requirement.

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Document Revision History

4-39

Date

May 2013

December 2012

Version

2013.05.06

2012.12.28

Changes

• Added link to the known document issues in the Knowledge Base.

• Updated PCLK clock sources in hierarchical clock networks in each spine clock per quadrant diagram.

• Added PCLK networks in clock network sources section.

• Updated dedicated clock input pins in clock network sources section.

• Added descriptions for PLLs located in a strip.

• Added information on PLL physical counters.

• Updated the fractional PLL architecture diagram to add dedicated refclk input port and connections.

• Updated PLL support for EFB mode.

• Updated the scaling factors for PLL output ports.

• Updated the fractional value for PLL in fractional mode.

• Moved all links to the Related Information section of respective topics for easy reference.

• Reorganized content.

• Added note to indicate that the figures shown are the top view of the silicon die.

• Removed DPA support.

• Updated clock resources table.

• Updated diagrams for GCLK, RCLK, and PCLK networks.

• Updated diagram for clock sources per quadrant.

• Updated dual-regional clock region for Cyclone V SoC devices support.

• Restructured and updated tables for clock input pin connectivity to the

GCLK and RCLK networks.

• Added tables for clock input pin connectivity to the GCLK and RCLK networks for Cyclone V SoC devices.

• Updated PCLK control block diagram.

• Updated information on clock power down.

• Added diagram for PLL physical counter orientation.

• Updated PLL locations diagrams.

• Updated fractional PLL high-level block diagram.

• Removed information on pfdena

PLL control signal.

• Removed information on PLL Compensation assignment in the

Quartus II software.

• Updated the fractional value for PLL in fractional mode.

• Reorganized content and updated template.

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Document Revision History

Date

June 2012

Version

2.0

February 2012

October 2011

1.1

1.0

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Changes

• Restructured chapter.

• Updated Figure 4–4, Figure 4–6, Figure 4–7, Figure 4–11, Figure 4–13,

Figure 4–15, Figure 4–16, Figure 4–17, Figure 4–19, and Figure 4–20.

• Updated Table 4–2, Table 4–3, and Table 4–5.

• Added “Clock Regions”, “Clock Network Sources”, “Clock Output

Connections”, “Clock Enable Signals”, “PLL Control Signals”, “Clock

Multiplication and Division”, “Programmable Duty Cycle”, “Clock

Switchover”, and “PLL Reconfiguration and Dynamic Phase Shift” sections.

Updated Table 4–2.

Initial release.

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I/O Features in Cyclone V Devices

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This chapter provides details about the features of the Cyclone V I/O elements (IOEs) and how the IOEs work in compliance with current and emerging I/O standards and requirements.

The Cyclone V I/Os support the following features:

• Single-ended, non-voltage-referenced, and voltage-referenced I/O standards

• Low-voltage differential signaling (LVDS), RSDS, mini-LVDS, HSTL, HSUL, and SSTL I/O standards

• Serializer/deserializer (SERDES)

• Programmable output current strength

• Programmable slew-rate

• Programmable bus-hold

• Programmable pull-up resistor

• Programmable pre-emphasis

• Programmable I/O delay

• Programmable voltage output differential (V

OD

)

• Open-drain output

• On-chip series termination (R

S

OCT) with and without calibration

• On-chip parallel termination (R

T

OCT)

• On-chip differential termination (R

• High-speed differential I/O support

D

OCT)

Note:

The information in this chapter is applicable to all Cyclone V variants, unless noted otherwise.

Related Information

Cyclone V Device Handbook: Known Issues

Lists the planned updates to the

Cyclone V Device Handbook

chapters.

5

I/O Resources Per Package for Cyclone V Devices

The following package plan tables for the different Cyclone V variants list the maximum I/O resources available for each package.

©

2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with

Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO

9001:2008

Registered www.altera.com

101 Innovation Drive, San Jose, CA 95134

5-2

I/O Resources Per Package for Cyclone V Devices

Table 5-1: Package Plan for Cyclone V E Devices

Member Code

A2

A4

A5

A7

A9

M383

GPIO

223

223

175

M484

GPIO

240

U324

GPIO

176

176

Table 5-2: Package Plan for Cyclone V GX Devices

F256

GPIO

128

128

U484

GPIO

224

224

224

240

240

F484

GPIO

224

224

240

240

224

F672

GPIO

336

336

F896

GPIO

480

480

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C3

C4

C5

C7

C9

Member

Code

M301

GPIO XCVR

M383 M484

GPIO XCVR GPIO XCVR

U324

GPIO

U484

XCVR GPIO XCVR

F484 F672 F896

GPIO XCVR GPIO XCVR GPIO XCVR GPIO

F1152

XCVR

129

129

4

4

175

175

6

6

240

3

144

3

208

224

224

240

240

3

6

6

6

5

208

240

240

240

224

3

6

6

6

6

336

336

336

336

6

6

9

9

480

480

9

12

560

12

Table 5-3: Package Plan for Cyclone V GT Devices

Member

Code

M301

GPIO XCVR

M383

GPIO XCVR

M484

GPIO XCVR

U484

GPIO XCVR

F484

GPIO XCVR

F672

GPIO XCVR

F896

GPIO XCVR GPIO

F1152

XCVR

D5

D7

D9

129

4

175

6

240

3

224

240

240

6

6

5

240

240

224

6

6

6

336

336

336

6

9

9

480

480

9

12

560

12

Table 5-4: Package Plan for Cyclone V SE Devices

The HPS I/O counts are the number of I/Os in the HPS and does not correlate with the number of HPS-specific I/O pins in the FPGA. Each HPS-specific pin in the FPGA may be mapped to several HPS I/Os.

U484 U672 F896

Member Code

FPGA GPIO HPS I/O FPGA GPIO HPS I/O FPGA GPIO HPS I/O

A2

A4

A5

A6

66

66

66

66

151

151

151

151

145

145

145

145

181

181

181

181

288

288

181

181

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Table 5-5: Package Plan for Cyclone V SX Devices

I/O Resources Per Package for Cyclone V Devices

5-3

The HPS I/O counts are the number of I/Os in the HPS and does not correlate with the number of HPS-specific I/O pins in the FPGA. Each HPS-specific pin in the FPGA may be mapped to several HPS I/Os.

U672 F896

Member Code

FPGA GPIO HPS I/O XCVR FPGA GPIO HPS I/O XCVR

C2

C4

C5

C6

145

145

145

145

181

181

181

181

6

6

6

6

288

288

181

181

9

9

Table 5-6: Package Plan for Cyclone V ST Devices

The HPS I/O counts are the number of I/Os in the HPS and does not correlate with the number of HPS-specific I/O pins in the FPGA. Each HPS-specific pin in the FPGA may be mapped to several HPS I/Os.

F896

Member Code

FPGA GPIO HPS I/O XCVR

D5

D6

288

288

181

181

9

9

For more information about each device variant, refer to the device overview.

Related Information

Cyclone V Device Overview

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I/O Vertical Migration for Cyclone V Devices

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I/O Vertical Migration for Cyclone V Devices

Figure 5-1: Vertical Migration Capability Across Cyclone V Device Packages and Densities

The arrows indicate the vertical migration paths. The devices included in each vertical migration path are shaded. You can also migrate your design across device densities in the same package option if the devices have the same dedicated pins, configuration pins, and power pins.

Variant

Cyclone V E

Cyclone V GX

Cyclone V GT

Cyclone V SE

Cyclone V SX

Cyclone V ST

Member

Code

A7

A9

C3

A2

A4

A5

A4

A5

A6

D7

D9

A2

C4

C5

C7

C9

D5

C6

D5

D6

C2

C4

C5

Package

M301 M383 M484 F256 U324 U484 F484 U672 F672 F896 F1152

You can achieve the vertical migration shaded in red if you use only up to 175 GPIOs. This migration path is not shown in the Quartus II software Pin Migration View.

Note:

To verify the pin migration compatibility, use the Pin Migration View window in the Quartus II software Pin Planner.

Related Information

Verifying Pin Migration Compatibility

on page 5-5

I/O Management chapter, Quartus II Handbook

Provides more information about vertical I/O migrations.

What is the difference between pin-to-pin compatibility and drop-in compatibility?

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Verifying Pin Migration Compatibility

Verifying Pin Migration Compatibility

5-5

You can use the Pin Migration View window in the Quartus II software Pin Planner to assist you in verifying whether your pin assignments migrate to a different device successfully. You can vertically migrate to a device with a different density while using the same device package, or migrate between packages with different densities and ball counts.

1. Open Assignments > Pin Planner and create pin assignments.

2. If necessary, perform one of the following options to populate the Pin Planner with the node names in the design:

• Analysis & Elaboration

• Analysis & Synthesis

• Fully compile the design

3. Then, on the menu, click View > Pin Migration View.

4. To select or change migration devices:

a. Click Device to open the Device dialog box.

b. Under Migration compatibility click Migration Devices.

5. To show more information about the pins:

a. Right-click anywhere in the Pin Migration View window and select Show Columns.

b. Then, click the pin feature you want to display.

6. If you want to view only the pins, in at least one migration device, that have a different feature than the corresponding pin in the migration result, turn on Show migration differences.

7. Click Pin Finder to open the Pin Finder dialog box and find and highlight pins with specific functionality.

If you want to view only the pins found and highlighted by the most recent query in the Pin Finder dialog box, turn on Show only highlighted pins.

8. To export the pin migration information to a Comma-Separated Value File (.csv), click Export.

Related Information

I/O Vertical Migration for Cyclone V Devices

on page 5-4

I/O Management chapter, Quartus II Handbook

Provides more information about vertical I/O migrations.

I/O Standards Support in Cyclone V Devices

This section lists the I/O standards supported in the FPGA I/Os and HPS I/Os of Cyclone V devices, the typical power supply values for each I/O standard, and the MultiVolt I/O interface feature.

I/O Standards Support for FPGA I/O in Cyclone V Devices

Table 5-7: Supported I/O Standards in FPGA I/O for Cyclone V Devices

I/O Standard

3.3 V LVTTL/3.3 V LVCMOS

Standard Support

JESD8-B

I/O Features in Cyclone V Devices

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I/O Standards Support for FPGA I/O in Cyclone V Devices

I/O Standard

3.0 V LVTTL/3.0 V LVCMOS

3.0 V PCI

(7)

3.0 V PCI-X

(8)

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

1.2 V LVCMOS

SSTL-2 Class I

SSTL-2 Class II

SSTL-18 Class I

SSTL-18 Class II

SSTL-15 Class I

SSTL-15 Class II

1.8 V HSTL Class I

1.8 V HSTL Class II

1.5 V HSTL Class I

1.5 V HSTL Class II

1.2 V HSTL Class I

1.2 V HSTL Class II

Differential SSTL-2 Class I

Differential SSTL-2 Class II

Differential SSTL-18 Class I

Differential SSTL-18 Class II

Differential SSTL-15 Class I

Differential SSTL-15 Class II

Differential 1.8 V HSTL Class I

Differential 1.8 V HSTL Class II

Differential 1.5 V HSTL Class I

Differential 1.5 V HSTL Class II

Differential 1.2 V HSTL Class I

Differential 1.2 V HSTL Class II

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Standard Support

JESD8-B

PCI Rev. 2.2

PCI-X Rev. 1.0

JESD8-16A

JESD8-9B

JESD8-9B

JESD8-15

JESD8-15

JESD8-6

JESD8-6

JESD8-6

JESD8-6

JESD8-16A

JESD8-16A

JESD8-5

JESD8-7

JESD8-11

JESD8-12

JESD8-9B

JESD8-9B

JESD8-15

JESD8-15

JESD8-6

JESD8-6

JESD8-6

JESD8-6

JESD8-16A

(7)

(8)

3.3 V PCI I/O standard is not supported.

3.3 V PCI-X I/O standard is not supported. PCI-X does not meet the PCI-X I–V curve requirement at the linear region.

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LVDS

RSDS

(9)

Mini-LVDS

(10)

LVPECL

SLVS

Sub-LVDS

HiSpi

SSTL-15

SSTL-135

SSTL-125

HSUL-12

Differential SSTL-15

Differential SSTL-135

Differential SSTL-125

Differential HSUL-12

I/O Standard

I/O Standards Support for HPS I/O in Cyclone V Devices

Standard Support

ANSI/TIA/EIA-644

JESD8-13

JESD79-3D

JESD79-3D

5-7

I/O Standards Support for HPS I/O in Cyclone V Devices

Table 5-8: Supported I/O Standards in HPS I/O for Cyclone V SE, SX, and ST Devices

I/O Standard

3.3 V LVTTL/3.3 V LVCMOS

3.0 V LVTTL/3.0 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

SSTL-18 Class I

SSTL-18 Class II

SSTL-15 Class I

SSTL-15 Class II

1.5 V HSTL Class I

1.5 V HSTL Class II

Standard Support

JESD8-B

JESD8-B

JESD8-5

JESD8-7

JESD8-11

JESD8-15

JESD8-15

JESD8-6

JESD8-6

HPS Column I/O

Yes

Yes

Yes

Yes

Yes

Yes

Yes

HPS Row I/O

Yes

Yes

Yes

Yes

Yes

(9)

(10)

The Cyclone V devices support true RSDS output standard with data rates of up to 230 Mbps using true LVDS output buffer types on all I/O banks.

The Cyclone V devices support true mini-LVDS output standard with data rates of up to 340 Mbps using true

LVDS output buffer types on all I/O banks.

I/O Features in Cyclone V Devices

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I/O Standards Voltage Levels in Cyclone V Devices

SSTL-135

HSUL-12

I/O Standard Standard Support

HPS Column I/O

HPS Row I/O

Yes

Yes

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I/O Standards Voltage Levels in Cyclone V Devices

Table 5-9: Cyclone V I/O Standards Voltage Levels

This table lists the typical power supplies for each supported I/O standards in Cyclone V devices.

V

CCIO

(V) V

CCPD

(V) V

REF

(V)

I/O Standard

Input

(11)

Output

(Pre-Driver

Voltage)

(Input Ref

Voltage)

V

TT

(V)

(Board Termination

Voltage)

3.3 V LVTTL/3.3 V

LVCMOS

3.0 V LVTTL/3.0 V

LVCMOS

3.0 V PCI

3.0 V PCI-X

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

1.2 V LVCMOS

SSTL-2 Class I

SSTL-2 Class II

SSTL-18 Class I

SSTL-18 Class II

SSTL-15 Class I

SSTL-15 Class II

1.8 V HSTL Class I

1.8 V HSTL Class II

1.5 V HSTL Class I

1.5 V HSTL Class II

1.2 V HSTL Class I

1.2 V HSTL Class II

3.3/3.0/2.5

3.3/3.0/2.5

3.0

3.0

3.3/3.0/2.5

1.8/1.5

1.8/1.5

1.2

V

CCPD

V

CCPD

V

CCPD

V

CCPD

V

CCPD

V

CCPD

V

CCPD

V

CCPD

V

CCPD

V

CCPD

V

CCPD

V

CCPD

3.3

3.0

3.0

3.0

2.5

1.8

1.5

1.2

2.5

2.5

1.8

1.8

1.5

1.5

1.8

1.8

1.5

1.5

1.2

1.2

3.3

3.0

3.0

3.0

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

1.25

1.25

0.9

0.9

0.75

0.75

0.9

0.9

0.75

0.75

0.6

0.6

0.75

0.75

0.9

0.9

0.75

0.75

0.6

0.6

1.25

1.25

0.9

0.9

(11)

Input buffers for the SSTL, HSTL, Differential SSTL, Differential HSTL, LVDS, RSDS, Mini-LVDS, LVPECL,

HSUL, and Differential HSUL are powered by V

CCPD

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I/O Standard

Differential SSTL-2 Class

I

Differential SSTL-2 Class

II

Differential SSTL-18 Class

I

Differential SSTL-18 Class

II

Differential SSTL-15 Class

I

Differential SSTL-15 Class

II

Differential 1.8 V HSTL

Class I

Differential 1.8 V HSTL

Class II

Differential 1.5 V HSTL

Class I

Differential 1.5 V HSTL

Class II

Differential 1.2 V HSTL

Class I

Differential 1.2 V HSTL

Class II

LVDS

RSDS

Mini-LVDS

LVPECL (Differential clock input only)

SLVS (Input only)

Sub-LVDS (input only)

HiSpi (input only)

V

CCPD

V

CCPD

V

CCPD

V

CCPD

V

CCPD

V

CCPD

V

CCPD

V

CCPD

V

CCPD

V

CCPD

V

CCPD

V

CCPD

V

CCPD

V

CCPD

Input

(11)

V

CCIO

(V)

Output

I/O Standards Voltage Levels in Cyclone V Devices

V

CCPD

(V)

(Pre-Driver

Voltage)

V

REF

(V)

(Input Ref

Voltage)

5-9

V

TT

(V)

(Board Termination

Voltage)

V

CCPD

2.5

2.5

— 1.25

2.5

2.5

— 1.25

V

CCPD

V

CCPD

V

CCPD

V

CCPD

1.8

1.8

1.5

2.5

2.5

2.5

0.9

0.9

0.75

1.5

2.5

— 0.75

1.8

1.8

1.5

1.5

1.2

1.2

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

0.9

0.9

0.75

0.75

0.6

0.6

(11)

Input buffers for the SSTL, HSTL, Differential SSTL, Differential HSTL, LVDS, RSDS, Mini-LVDS, LVPECL,

HSUL, and Differential HSUL are powered by V

CCPD

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MultiVolt I/O Interface in Cyclone V Devices

I/O Standard

Input

(11)

V

CCIO

(V)

Output

SSTL-15

SSTL-135

SSTL-125

HSUL-12

Differential SSTL-15

Differential SSTL-135

Differential SSTL-125

Differential HSUL-12

V

CCPD

V

CCPD

V

CCPD

V

CCPD

V

CCPD

V

CCPD

V

CCPD

V

CCPD

1.5

1.35

1.25

1.2

1.5

1.35

1.25

1.2

Related Information

MultiVolt I/O Interface in Cyclone V Devices

on page 5-10

Non-Voltage-Referenced I/O Standards

on page 5-11

V

CCPD

(V)

(Pre-Driver

Voltage)

2.5

2.5

2.5

2.5

2.5

2.5

2.5

2.5

V

REF

(V)

(Input Ref

Voltage)

0.75

0.675

0.625

0.6

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V

TT

(V)

(Board Termination

Voltage)

Typically does not require board termination

Typically does not require board termination

MultiVolt I/O Interface in Cyclone V Devices

The MultiVolt I/O interface feature allows Cyclone V devices in all packages to interface with systems of different supply voltages.

Table 5-10: MultiVolt I/O Support in Cyclone V Devices

V

CCIO

(V)

1.2

1.25

1.35

1.5

1.8

2.5

3.0

3.3

V

CCPD

(V)

2.5

2.5

2.5

2.5

2.5

2.5

3.0

3.3

Input Signal (V)

1.2

1.25

1.35

1.5, 1.8

1.5, 1.8

2.5, 3.0, 3.3

2.5, 3.0, 3.3

2.5, 3.0, 3.3

Output Signal (V)

1.2

1.25

1.35

1.5

1.8

2.5

3.0

3.3

The pin current may be slightly higher than the default value. Verify that the V minimum voltages of the driving device do not violate the applicable V

IL

OL maximum and V

OH maximum and V

IH minimum voltage specifications of the Cyclone V device.

(11)

Input buffers for the SSTL, HSTL, Differential SSTL, Differential HSTL, LVDS, RSDS, Mini-LVDS, LVPECL,

HSUL, and Differential HSUL are powered by V

CCPD

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I/O Design Guidelines for Cyclone V Devices

5-11

The V

CCPD power pins must be connected to a 2.5 V, 3.0 V, or 3.3 V power supply. Using these power pins to supply the pre-driver power to the output buffers increases the performance of the output pins.

Note:

If the input signal is 3.0 V or 3.3 V, Altera recommends that you use a clamping diode on the I/O pins.

Related Information

I/O Standards Voltage Levels in Cyclone V Devices

on page 5-8

I/O Design Guidelines for Cyclone V Devices

There are several considerations that require your attention to ensure the success of your designs. Unless noted otherwise, these design guidelines apply to all variants of this device family.

Mixing Voltage-Referenced and Non-Voltage-Referenced I/O Standards

Each I/O bank can simultaneously support multiple I/O standards. The following sections provide guidelines for mixing non-voltage-referenced and voltage-referenced I/O standards in the devices.

Non-Voltage-Referenced I/O Standards

Each Cyclone V I/O bank has its own V

CCIO pins and supports only one V

CCIO of 1.2, 1.25, 1.35, 1.5, 1.8,

2.5, 3.0, or 3.3 V. An I/O bank can simultaneously support any number of input signals with different I/O standard assignments if the I/O standards support the V

CCIO level of the I/O bank.

For output signals, a single I/O bank supports non-voltage-referenced output signals that drive at the same voltage as V

CCIO

. Because an I/O bank can only have one V non-voltage-referenced signals.

CCIO value, it can only drive out the value for

For example, an I/O bank with a 2.5 V V

CCIO

3.0 V LVCMOS inputs only.

setting can support 2.5 V standard inputs and outputs, and

Related Information

I/O Standards Voltage Levels in Cyclone V Devices

on page 5-8

Voltage-Referenced I/O Standards

To accommodate voltage-referenced I/O standards:

• Each Cyclone V I/O bank contains a dedicated

VREF pin.

• Each bank can have only a single V

CCIO voltage level and a single voltage reference (V

REF

) level.

An I/O bank featuring single-ended or differential standards can support different voltage-referenced standards if the V

CCIO and V

REF are the same levels.

For performance reasons, voltage-referenced input standards use their own V

CCPD level as the power source.

This feature allows you to place voltage-referenced input signals in an I/O bank with a V

CCIO of 2.5 V or below. For example, you can place HSTL-15 input pins in an I/O bank with 2.5 V V

CCIO

. However, the voltage-referenced input with R

T the input standard. R

T

OCT enabled requires the V

CCIO of the I/O bank to match the voltage of

OCT cannot be supported for the HSTL-15 I/O standard when V

CCIO is 2.5 V.

Voltage-referenced bidirectional and output signals must be the same as the V

CCIO voltage of the I/O bank.

For example, you can place only SSTL-2 output pins in an I/O bank with a 2.5 V V

CCIO

.

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Mixing Voltage-Referenced and Non-Voltage Referenced I/O Standards

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Mixing Voltage-Referenced and Non-Voltage Referenced I/O Standards

An I/O bank can support voltage-referenced and non-voltage-referenced pins by applying each of the rule sets individually.

Examples:

• An I/O bank can support SSTL-18 inputs and outputs, and 1.8 V inputs and outputs with a 1.8 V V

CCIO and a 0.9 V V

REF

.

• An I/O bank can support 1.5 V standards, 1.8 V inputs (but not outputs), and 1.5 V HSTL I/O standards with a 1.5 V V

CCIO and 0.75 V V

REF

.

PLLs and Clocking

The Cyclone V device family supports fractional PLLs on each side of the device. You can use fractional

PLLs to reduce the number of oscillators and the clock pins used in the FPGA by synthesizing multiple clock frequencies from a single reference clock source.

The corner fractional PLLs can drive the LVDS receiver and driver channels. However, the clock tree network cannot cross over to different I/O regions. For example, the top left corner fractional PLL cannot cross over to drive the LVDS receiver and driver channels on the top right I/O bank. The Quartus II compiler automatically checks the design and issues an error message if the guidelines are not followed.

Related Information

High-Speed Differential I/O Locations

on page 5-52

PLL locations that are available for each device.

Guideline: Use PLLs in Integer PLL Mode for LVDS

on page 5-12

Guideline: Use PLLs in Integer PLL Mode for LVDS

To drive the LVDS channels, you must use the PLLs in integer PLL mode. The corner PLLs can drive the

LVDS receiver and transmitter channels.

Guideline: Reference Clock Restriction for LVDS Application

You must use the dedicated reference clock pin of the same I/O bank used by the data channel. For I/O banks without a dedicated reference clock pin, use the reference clock pin in the I/O bank listed in the following table.

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Guideline: Using LVDS Differential Channels

Table 5-11: Reference Clock Pin for I/O Bank Without Dedicated Reference Clock Pin

Device Variant

Cyclone V E

Cyclone V GX

Cyclone V GT

Cyclone V SE

Cyclone V SX

Cyclone V ST

Member Code

A2, A4

A5, A9

A7

C4, C5, C9

C3, C7

D5, D9

D7

A2, A4

A5, A6

C2, C4

C5, C6

D5, D6

Data Channel I/O Bank

Banks using bottom right PLL

Banks using bottom left PLL

Banks using top right

PLL

Banks using top left

PLL

3A

5A

5A

3A

3A

3A

5A

3A

5A

5A

3A

5A

5A

5A

3B

7A

8A

5-13

Reference Clock Pin I/O Bank

4A

3B

3B

5B

3B

5B

5B

5B

5B

3B

5B

3B

5B

5B

3B

Guideline: Using LVDS Differential Channels

If you use LVDS channels, adhere to the following guidelines.

LVDS Channel Driving Distance

Each PLL can drive all the LVDS channels in the entire quadrant.

Using Both Corner PLLs

You can use both corner PLLs to drive LVDS channels simultaneously. You can use a corner PLL to drive all the transmitter channels and the other corner PLL to drive all the receiver channels in the same I/O bank.

Both corner PLLs can drive duplex channels in the same I/O bank if the channels that are driven by each

PLL are not interleaved. You do not require separation between the groups of channels that are driven by both corner PLLs.

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Guideline: Using LVDS Differential Channels

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Note:

The figures in this section show guidelines for using corner PLLs but do not necessarily represent the exact locations of the high-speed LVDS I/O banks.

Figure 5-2: Corner PLLs Driving LVDS Differential I/Os in the Same Bank

Corner PLL

Reference CLK

Diff RX Diff TX

Corner PLL

Reference CLK

Diff I/O

Channels Driven by Corner PLL

Diff RX

Diff RX

Diff RX

Diff RX

Diff RX

Diff RX

Diff RX

Diff RX

Diff TX

Diff TX

Diff TX

Diff TX

Diff TX

Diff TX

Diff TX

Diff TX

Diff I/O

Diff I/O

Diff I/O

Diff I/O

Diff I/O

Diff I/O

Diff I/O

Diff I/O

No Separation

Buffer Needed

Channels Driven by Corner PLL

Diff RX Diff TX

Reference CLK

Corner PLL

Diff I/O

Reference CLK

Corner PLL

Figure 5-3: Invalid Placement of Differential I/Os Due to Interleaving of Channels Driven by the Corner PLLs

Corner PLL

Reference CLK

Diff I/O

Diff I/O

Diff I/O

Diff I/O

Diff I/O

Diff I/O

Diff I/O

Diff I/O

Diff I/O

Diff I/O

Reference CLK

Corner PLL

Related Information

Clock Networks and PLLs in Cyclone V Devices

on page 4-1

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LVDS Interface with External PLL Mode

LVDS Interface with External PLL Mode

5-15

The MegaWizard Plug-In Manager provides an option for implementing the LVDS interface with the Use

External PLL option. With this option enabled you can control the PLL settings, such as dynamically reconfiguring the PLL to support different data rates, dynamic phase shift, and other settings. You must also instantiate the an Altera_PLL megafunction to generate the various clock and load enable signals.

If you enable the Use External PLL option with the ALTLVDS transmitter and receiver, the following signals are required from the Altera_PLL megafunction:

• Serial clock input to the SERDES of the ALTLVDS transmitter and receiver

• Load enable to the SERDES of the ALTLVDS transmitter and receiver

• Parallel clock used to clock the transmitter FPGA fabric logic and parallel clock used for the receiver rx_syncclock port and receiver FPGA fabric logic

• Asynchronous PLL reset port of the ALTLVDS receiver

Altera_PLL Signal Interface with ALTLVDS Megafunction

Table 5-12: Signal Interface Between Altera_PLL and ALTLVDS Megafunctions

This table lists the signal interface between the output ports of the Altera_PLL megafunction and the input ports of the ALTLVDS transmitter and receiver. As an example, the table lists the serial clock output, load enable output, and parallel clock output generated on ports outclk0, outclk1, and outclk2, along with the locked signal of the

Altera_PLL instance. You can choose any of the PLL output clock ports to generate the interface clocks.

From the Altera_PLL Megafunction To the ALTLVDS Transmitter To the ALTLVDS Receiver

rx_inclock

(serial clock input) Serial clock output (outclk0)

The serial clock output (outclk0) can only drive tx_inclock on the

ALTLVDS transmitter, and rx_ inclock on the ALTLVDS receiver.

This clock cannot drive the core logic.

tx_inclock

(serial clock input to the transmitter)

Load enable output (outclk1) tx_enable

(load enable to the transmitter) rx_enable deserializer)

(load enable for the

Parallel clock output (outclk2)

~(locked)

Parallel clock used inside the transmitter core logic in the FPGA fabric parallel clock used inside the receiver core logic in the FPGA fabric

— pll_areset

(asynchronous PLL reset port)

The pll_areset signal is automatically enabled for the LVDS receiver in external PLL mode. This signal does not exist for LVDS transmitter instantiation when the external PLL option is enabled.

Note:

With soft SERDES, a different clocking requirement is needed.

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Altera_PLL Parameter Values for External PLL Mode

Related Information

LVDS SERDES Transmitter/Receiver (ALTLVDS_RX/TX) Megafunction User Guide

More information about the different clocking requirement for soft SERDES.

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Altera_PLL Parameter Values for External PLL Mode

The following example shows the clocking requirements to generate output clocks for ALTLVDS_TX and

ALTLVDS_RX using the Altera_PLL megafunction. The example sets the phase shift with the assumption that the clock and data are edge aligned at the pins of the device.

Note:

For other clock and data phase relationships, Altera recommends that you first instantiate your

ALTLVDS_RX and ALTLVDS_TX interface without using the external PLL mode option. Compile the megafunctions in the Quartus II software and take note of the frequency, phase shift, and duty cycle settings for each clock output. Enter these settings in the Altera_PLL megafunction parameter editor and then connect the appropriate output to the ALTLVDS_RX and ALTLVDS_TX megafunctions.

Table 5-13: Example: Generating Output Clocks Using an Altera_PLL Megafunction

This table lists the parameter values that you can set in the Altera_PLL parameter editor to generate three output clocks using an Altera_PLL megafunction if you are not using DPA and soft-CDR mode.

Parameter outclk0 outclk1 outclk2

(Connects to the tx_inclock port of ALTLVDS_TX and the rx_inclock port of ALTLVDS_

RX)

(Connects to the tx_enable port of ALTLVDS_TX and the rx_enable port of ALTLVDS_

RX)

(Used as the core clock for the parallel data registers for both transmitter and receiver)

Frequency data rate

Phase shift

Duty cycle

–180°

50% data rate/serialization factor data rate/serialization factor

[(deserialization factor – 2)/ deserialization factor] x 360°

–180/serialization factor

(outclk0 phase shift divided by the serialization factor)

100/serialization factor 50%

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Connection between Altera_PLL and ALTLVDS

Figure 5-4: Phase Relationship for External PLL Interface Signals

5-17

inclk0

VCO clk

(internal PLL clk) outclk0

(-180° phase shift) outclk1

(288° phase shift) outclk2

(-18° phase shift)

RX serial data tx_outclk

TX serial data

D1 D2 D3 D4 D5 D6 D7 D8 D9 D10

D1 D2 D3 D4 D5 D6 D7 D8 D9 D10

Connection between Altera_PLL and ALTLVDS

Figure 5-5: LVDS Interface with the Altera_PLL Megafunction

This figure shows the connections between the Altera_PLL and ALTLVDS megafunction.

FPGA Fabric

Transmitter

Core Logic

D Q

LVDS Transmitter

(ALTLVDS)

tx_in tx_inclock tx_enable

Altera_PLL

tx_coreclk outclk0 outclk1 outclk2 inclk0 pll_areset rx_coreclk

Receiver

Core Logic

Q D

LVDS Receiver

(ALTLVDS)

rx_out rx_inclock rx_enable pll_areset locked

When generating the Altera_PLL megafunction, the Left/Right PLL option is configured to set up the PLL in LVDS mode. Instantiation of pll_areset is optional.

Guideline: Use the Same V

CCPD for All I/O Banks in a Group

In the Cyclone V devices, all I/O banks have individual V

CCPD share V

CCPD in each group: except the following I/O bank groups, which

• Banks 1A (if available) and 2A

• Banks 3B and 4A

• Banks 7A and 8A

I/O Features in Cyclone V Devices

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Guideline: Ensure Compatible V

CCIO and V

CCPD

Voltage in the Same Bank

Examples:

• If bank 3B uses a 3.0 V V

CCPD

, bank 4A must also use 3.0 V V

CCPD

.

• If bank 8A uses a 2.5 V V

CCPD

, bank 7A must also use 2.5 V V

CCPD

.

For more information about the I/O banks available in each device package, refer to the related links.

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Related Information

Modular I/O Banks for Cyclone V E Devices

on page 5-22

Modular I/O Banks for Cyclone V GX Devices

on page 5-23

Modular I/O Banks for Cyclone V GT Devices

on page 5-24

Modular I/O Banks for Cyclone V SE Devices

on page 5-25

Modular I/O Banks for Cyclone V SX Devices

on page 5-26

Modular I/O Banks for Cyclone V ST Devices

on page 5-27

Guideline: Ensure Compatible V

CCIO and V

CCPD

Voltage in the Same Bank

When planning I/O bank usage for Cyclone V devices, you must ensure the V

CCIO with the V

CCPD voltage of the same bank. Some banks may share the same V

CCPD voltage is compatible power pin. This limits the possible V

CCIO voltages that can be used on banks that share

VCCPD power pins.

Examples:

VCCPD3B is connected to 2.5 V—

VCCIO pins for banks 3B and 4A can be connected 1.2 V, 1.25 V, 1.35 V,

1.5 V, 1.8 V, or 2.5 V.

VCCPD3B is connected to 3.0 V—

VCCIO pins for banks 3B and 4A must be connected to 3.0 V.

Guideline:

VREF

Pin Restrictions

For the Cyclone V devices, consider the following

VREF pins guidelines:

• You cannot assign shared

VREF pins as LVDS or external memory interface pins.

• SSTL, HSTL, and HSUL I/O standards do not support shared

VREF pins. For example, if a particular

B1p or

B1n pin is a shared

VREF pin, the corresponding

B1p/B1n pin pair do not have LVDS transmitter support.

• You must perform signal integrity analysis using your board design when using a shared

VREF pin to determine the F

MAX for your system.

For more information about pin capacitance of the

VREF pins, refer to the device datasheet.

Related Information

Cyclone V Device Datasheet

Guideline: Observe Device Absolute Maximum Rating for 3.3 V Interfacing

To ensure device reliability and proper operation when you use the device for 3.3 V I/O interfacing, do not violate the absolute maximum ratings of the device. For more information about absolute maximum rating and maximum allowed overshoot during transitions, refer to the device datasheet.

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Guideline: Adhere to the LVDS I/O Restrictions and Differential Pad Placement Rules

5-19

Tip:

Perform IBIS or SPICE simulations to make sure the overshoot and undershoot voltages are within the specifications.

Transmitter Application

If you use the Cyclone V device as a transmitter, use slow slew-rate and series termination to limit the overshoot and undershoot at the I/O pins. Transmission line effects that cause large voltage deviations at the receiver are associated with an impedance mismatch between the driver and the transmission lines. By matching the impedance of the driver to the characteristic impedance of the transmission line, you can significantly reduce overshoot voltage. You can use a series termination resistor placed physically close to the driver to match the total driver impedance to the transmission line impedance.

Receiver Application

If you use the Cyclone V device as a receiver, use the on-chip clamping diode to limit the overshoot and undershoot voltage at the I/O pins.

Related Information

Cyclone V Device Datasheet

Guideline: Adhere to the LVDS I/O Restrictions and Differential Pad Placement Rules

For Cyclone V LVDS applications, adhere to these guidelines to avoid adverse impact on LVDS performance:

• I/O restrictions guideline—to avoid excessive jitter on the LVDS transmitter output pins.

• Differential pad placement rule for each device—to avoid crosstalk effects.

Related Information

Cyclone V Device Family Pin Connection Guidelines

Describes the I/O restriction guidelines for the Cyclone V LVDS transmitters.

Cyclone V Differential Pad Placement Rule and Pad Mapping Files

Provides the pad mapping spreadsheets for Cyclone V devices.

I/O Banks Locations in Cyclone V Devices

The number of Cyclone V I/O banks in a particular device depends on the device density.

Note:

The availability of I/O banks in device packages varies. For more details, refer to the related links.

I/O Features in Cyclone V Devices

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I/O Banks Locations in Cyclone V Devices

Figure 5-6: I/0 Banks for Cyclone V E Devices

Bank 8A Bank 7A

Bank 3A Bank 3B Bank 4A

Figure 5-7: I/0 Banks for Cyclone V GX and GT Devices

Bank 8A Bank 7A

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Bank 3A Bank 3B Bank 4A

Figure 5-8: I/0 Banks for Cyclone V SE Devices

Bank 8A HPS Column I/O

HPS Core

Bank 3A Bank 3B Bank 4A

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Figure 5-9: I/0 Banks for Cyclone V SX and ST Devices

Bank 8A

I/O Banks Groups in Cyclone V Devices

HPS Column I/O

5-21

HPS Core

Bank 3A Bank 3B Bank 4A

Related Information

Modular I/O Banks for Cyclone V E Devices

on page 5-22

Modular I/O Banks for Cyclone V GX Devices

on page 5-23

Modular I/O Banks for Cyclone V GT Devices

on page 5-24

Modular I/O Banks for Cyclone V SE Devices

on page 5-25

Modular I/O Banks for Cyclone V SX Devices

on page 5-26

Modular I/O Banks for Cyclone V ST Devices

on page 5-27

I/O Banks Groups in Cyclone V Devices

The I/O pins in Cyclone V devices are arranged in groups called modular I/O banks:

• Modular I/O banks have independent power supplies that allow each bank to support different I/O standards.

• Each modular I/O bank can support multiple I/O standards that use the same V

CCIO and V

CCPD voltages.

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Modular I/O Banks for Cyclone V E Devices

Modular I/O Banks for Cyclone V E Devices

Table 5-14: Modular I/O Banks for Cyclone V E A2 and A4 Devices

Member Code

Package

I/O

Bank

Total

3B

4A

5A

5B

1A

2A

3A

7A

8A

M383

21

38

16

16

16

32

16

38

30

223

U324

16

32

16

16

32

16

32

16

176

A2

F256

16

16

16

16

16

16

16

16

128

U484

32

48

16

16

16

16

48

32

224

F484

32

48

16

16

16

16

48

32

224

M383

21

38

16

16

16

32

16

38

30

223

Table 5-15: Modular I/O Banks for Cyclone V E A5, A7, and A9 Devices

U324

16

32

16

16

32

16

32

16

176

A4

F256

Related Information

I/O Banks Locations in Cyclone V Devices

on page 5-19

Guideline: Use the Same V

CCPD

Provides guidelines about V

CCPD

for All I/O Banks in a Group

on page 5-17 and I/O banks groups.

16

16

16

16

16

16

16

16

128

Member Code

Package

I/O

Bank

Total

3A

3B

4A

5A

5B

6A

7A

8A

M383

16

21

38

16

14

39

31

175

A5

U484

16

32

48

16

32

48

32

224

F484

16

32

48

16

16

80

32

240

M484

16

32

48

16

16

32

48

32

240

U484

16

32

48

16

48

48

32

240

A7

F484

16

32

48

16

16

80

32

240

F672

16

32

80

16

64

16

80

32

336

F896

32

48

80

32

48

80

80

80

480

U484

16

32

48

16

48

48

32

240

F484

16

32

48

16

16

64

32

224

A9

F672

16

32

80

16

32

48

80

32

336

U484

32

48

16

16

16

16

48

32

224

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2014.01.10

F484

32

48

16

16

16

16

48

32

224

F896

32

48

80

32

48

80

80

80

480

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Modular I/O Banks for Cyclone V GX Devices

Modular I/O Banks for Cyclone V GX Devices

Table 5-16: Modular I/O Banks for Cyclone V GX C3, C4, and C5 Devices

5-23

Member Code

Package U324

I/O

Bank

5A

5B

6A

7A

3A

3B

4A

Total

8A

16

16

32

16

16

32

16

144

C3

U484

16

16

48

16

32

48

32

208

F484

16

16

48

16

32

48

32

208

M301 M383

16

14

23

16

18

22

20

129

16

14

39

16

21

38

31

175

C4

U484

16

32

48

16

32

48

32

224

F484

16

16

80

16

32

48

32

240

F672

16

64

16

80

16

32

80

32

336

M301 M383

16

14

23

16

18

22

20

129

16

14

39

16

21

38

31

175

C5

U484 F484

16

32

48

16

32

48

32

224

16

16

80

16

32

48

32

240

Table 5-17: Modular I/O Banks for Cyclone V GX C7 and C9 Devices

Member Code

I/O

Package

Bank

3A

3B

4A

5A

5B

6A

7A

8A

Total

M484

48

32

240

16

32

48

16

16

32

U484

48

32

240

16

32

48

16

48

C7

F484

80

32

240

16

32

48

16

16

F672

80

32

336

16

32

80

16

64

16

F896

80

80

480

32

48

80

32

48

80

U484

48

32

240

16

32

48

16

48

F484

64

32

224

16

32

48

16

16

Related Information

I/O Banks Locations in Cyclone V Devices

on page 5-19

Guideline: Use the Same V

CCPD

Provides guidelines about V

CCPD

for All I/O Banks in a Group

on page 5-17 and I/O banks groups.

C9

F672

80

32

336

16

32

80

16

32

48

F896

80

80

480

32

48

80

32

48

80

F1152

96

96

560

48

48

96

48

48

80

F672

16

64

16

80

16

32

80

32

336

I/O Features in Cyclone V Devices

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Modular I/O Banks for Cyclone V GT Devices

Modular I/O Banks for Cyclone V GT Devices

Table 5-18: Modular I/O Banks for Cyclone V GT D5 and D7 Devices

CV-52005

2014.01.10

Member Code

Package

I/O Bank

Total

3A

3B

4A

5A

5B

6A

7A

8A

M301

16

14

23

16

18

22

20

129

M383

16

14

39

16

21

38

31

175

D5

U484

16

32

48

16

32

48

32

224

F484

16

16

80

16

32

48

32

240

F672

16

64

16

80

16

32

80

32

336

Table 5-19: Modular I/O Banks for Cyclone V GT D9 Devices

M484

16

16

32

48

16

32

48

32

240

Member Code

Package

I/O Bank

Total

3A

3B

4A

5A

5B

6A

7A

8A

U484

48

32

240

16

32

48

16

48

F484

64

32

224

16

32

48

16

16

F672

80

32

336

16

32

80

16

32

48

D9

Related Information

I/O Banks Locations in Cyclone V Devices

on page 5-19

Guideline: Use the Same V

CCPD

Provides guidelines about V

CCPD

for All I/O Banks in a Group

on page 5-17 and I/O banks groups.

F896

80

80

480

32

48

80

32

48

80

U484

16

48

48

16

32

48

32

240

D7

F484

16

16

80

16

32

48

32

240

F672

16

64

16

80

16

32

80

32

336

F1152

96

96

560

48

48

96

48

48

80

F896

32

48

80

80

32

48

80

80

480

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Modular I/O Banks for Cyclone V SE Devices

Modular I/O Banks for Cyclone V SE Devices

5-25

Table 5-20: Modular I/O Banks for Cyclone V SE Devices

Note:

The HPS row and column I/O counts are the number of HPS-specific I/O pins on the device. Each HPSspecific pin may be mapped to several HPS I/Os.

Member Code

Package

FPGA I/

O Bank

5A

5B

HPS

Row I/O

Bank

6A

6B

HPS

Column

I/O

Bank

7A

7B

7C

FPGA I/

O Bank

Total

7D

8A

3A

3B

4A

U484

16

52

23

16

6

22

19

21

8

14

6

203

A2

U672

16

56

44

16

32

68

19

22

12

14

13

312

U484

16

52

23

16

6

22

19

21

8

14

6

203

A4

U672

16

56

44

16

32

68

19

22

12

14

13

312

U484

16

52

23

16

6

22

19

21

8

14

6

203

A5

U672

16

56

44

16

32

68

19

22

12

14

13

312

U484

16

52

23

16

6

22

19

21

8

14

6

F896

32

16

56

44

32

48

80

19

22

12

14

80

455 203

Related Information

I/O Banks Locations in Cyclone V Devices

on page 5-19

Guideline: Use the Same V

CCPD

Provides guidelines about V

CCPD

for All I/O Banks in a Group

on page 5-17 and I/O banks groups.

A6

U672

16

56

44

16

32

68

19

22

12

14

13

312 455

F896

32

16

56

44

32

48

80

19

22

12

14

80

I/O Features in Cyclone V Devices

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Modular I/O Banks for Cyclone V SX Devices

Modular I/O Banks for Cyclone V SX Devices

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Table 5-21: Modular I/O Banks for Cyclone V SX Devices

Note:

The HPS row and column I/O counts are the number of HPS-specific I/O pins on the device. Each HPSspecific pin may be mapped to several HPS I/Os.

C6 Member Code

Package

FPGA I/O

Bank

HPS Row I/

O Bank

HPS

Column I/O

Bank

5A

5B

6A

6B

3A

3B

4A

7A

7B

7C

7D

8A FPGA I/O

Bank

Total

C2

U672

16

56

44

16

32

68

19

22

12

14

13

312

C4

U672

16

56

44

16

32

68

19

22

12

14

13

312

U672

16

56

44

16

32

68

19

22

12

14

13

312

C5

F896

32

16

56

44

32

48

80

19

22

12

14

80

455

U672

16

56

44

16

32

68

19

22

12

14

13

312

Related Information

I/O Banks Locations in Cyclone V Devices

on page 5-19

Guideline: Use the Same V

CCPD

Provides guidelines about V

CCPD

for All I/O Banks in a Group

on page 5-17 and I/O banks groups.

455

F896

32

16

56

44

32

48

80

19

22

12

14

80

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Modular I/O Banks for Cyclone V ST Devices

Modular I/O Banks for Cyclone V ST Devices

5-27

Table 5-22: Modular I/O Banks for Cyclone V ST Devices

Note:

The HPS row and column I/O counts are the number of HPS-specific I/O pins on the device. Each HPSspecific pin may be mapped to several HPS I/Os.

Member Code

Package

FPGA I/O Bank

HPS Row I/O Bank

HPS Column I/O Bank

FPGA I/O Bank

Total

3A

3B

4A

5A

5B

6A

6B

7A

7B

7C

7D

8A

D5

F896

19

22

12

14

80

455

32

16

56

44

32

48

80

Related Information

I/O Banks Locations in Cyclone V Devices

on page 5-19

Guideline: Use the Same V

CCPD

Provides guidelines about V

CCPD

for All I/O Banks in a Group

on page 5-17 and I/O banks groups.

D6

F896

19

22

12

14

80

455

32

16

56

44

32

48

80

I/O Element Structure in Cyclone V Devices

The I/O elements (IOEs) in Cyclone V devices contain a bidirectional I/O buffer and I/O registers to support a complete embedded bidirectional single data rate (SDR) or double data rate (DDR) transfer.

The IOEs are located in I/O blocks around the periphery of the Cyclone V device.

The Cyclone V SE, SX, and ST devices also have I/O elements for the HPS.

I/O Buffer and Registers in Cyclone V Devices

I/O registers are composed of the input path for handling data from the pin to the core, the output path for handling data from the core to the pin, and the output enable (

OE

) path for handling the

OE signal to the output buffer. These registers allow faster source-synchronous register-to-register transfers and resynchronization.

I/O Features in Cyclone V Devices

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I/O Buffer and Registers in Cyclone V Devices

Table 5-23: Input and Output Paths in Cyclone V Devices

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This table summarizes the input and output path in the Cyclone V devices.

Input Path

Consists of:

• DDR input registers

• Alignment and synchronization registers

• Half data rate blocks

Output Path

Consists of:

• Output or

OE registers

• Alignment registers

• Half data rate blocks

You can bypass each block in the input path. The input path uses the deskew delay to adjust the input register clock delay across process, voltage, and temperature (PVT) variations.

You can bypass each block of the output and

OE paths.

Figure 5-10: IOE Structure for Cyclone V Devices

This figure shows the Cyclone V FPGA IOE structure. In the figure, one dynamic on-chip termination (OCT) control is available for each DQ/DQS group.

From Core

DQS Logic Block

OE from

Core

2

Half Data

Rate Block

OE Register

D

PRN

Q

D5_OCT

Dynamic OCT Control

Write

Data from

Core clkout

To

Core

To

Core

Read

Data to

Core

4

DQS

CQn clkin

4 Half Data

Rate Block

D3_1

Delay

OE Register

D

PRN

Q

Output Register

D

PRN

Q

Output Register

D

PRN

Q

D3_0

Delay

D1

Delay

Same avalaible settings in the Quartus II software

Input Register

D

PRN

Q

D5 Delay

Programmable

Current

Strength and

Slew Rate

Control

D5 Delay

Output

Buffer

VCCIO

Optional

PCI Clamp

VCCIO

Programmable

Pull-Up Resistor

From OCT

Calibration

Block

On-Chip

Termination

Open Drain

Input Buffer

Bus-Hold

Circuit

Read

FIFO

Input Register

D

PRN

Q

Input Register

D

PRN

Q

D4 Delay

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Programmable IOE Features in Cyclone V Devices

5-29

Programmable IOE Features in Cyclone V Devices

Table 5-24: Summary of Supported Cyclone V Programmable IOE Features and Settings

Feature Setting (Default setting in bold)

Condition Supported in HPS I/O

(SoC Devices Only)

Yes Slew Rate Control

I/O Delay

Open-Drain Output

Bus-Hold

Weak Pull-up Resistor

Pre-Emphasis

Differential Output Voltage

On-Chip Clamp Diode

0 (Slow), 1 (Fast) Disabled if you use the R

S

OCT feature.

— Refer to the device datasheet

On, Off

On, Off

On, Off

0 (disabled) and 1

(enabled)

Disabled if you use the weak pull-up resistor feature.

Disabled if you use the bus-hold feature.

For LVDS I/O standard only. Not supported for differential HSTL and

SSTL I/O standards.

00 (low), 01

(medium), 10 (high)

On, Off

Recommended to turn on for 3.3 V I/O standards

Yes

Yes

Yes

Yes

Note:

The on-chip clamp diode is available on all general purpose I/O (GPIO) pins in all Cyclone V device variants.

Related Information

Cyclone V Device Datasheet

Programmable Current Strength

on page 5-30

Programmable Output Slew-Rate Control

on page 5-31

Programmable IOE Delay

on page 5-31

Programmable Output Buffer Delay

on page 5-31

Programmable Pre-Emphasis

on page 5-32

Programmable Differential Output Voltage

on page 5-32

I/O Features in Cyclone V Devices

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Programmable Current Strength

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Programmable Current Strength

You can use the programmable current strength to mitigate the effects of high signal attenuation that is caused by a long transmission line or a legacy backplane.

Table 5-25: Programmable Current Strength Settings for Cyclone V Devices

The output buffer for each Cyclone V device I/O pin has a programmable current strength control for the I/O standards listed in this table.

I/O Standard I

OH

/ I

OL

Current Strength Setting (mA) Supported in HPS

(Default setting in bold)

(SoC Devices Only)

3.3 V LVTTL

3.3 V LVCMOS

3.0 V LVTTL

3.0 V LVCMOS

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

1.2 V LVCMOS

SSTL-2 Class I

SSTL-2 Class II

SSTL-18 Class I

SSTL-18 Class II

SSTL-15 Class I

SSTL-15 Class II

1.8 V HSTL Class I

1.8 V HSTL Class II

1.5 V HSTL Class I

1.5 V HSTL Class II

1.2 V HSTL Class I

1.2 V HSTL Class II

16, 8, 4

2

16, 12, 8, 4

16, 12, 8, 4

16, 12, 8, 4

12, 10, 8, 6, 4, 2

12, 10, 8, 6, 4, 2

8, 6, 4, 2

12, 10, 8

16

12, 10, 8, 6, 4

16

12, 10, 8, 6, 4

16

12, 10, 8, 6, 4

16

12, 10, 8, 6, 4

16

12, 10, 8, 6, 4

16

Yes (except 16 mA)

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Note:

Altera recommends that you perform IBIS or SPICE simulations to determine the best current strength setting for your specific application.

Related Information

Programmable IOE Features in Cyclone V Devices

on page 5-29

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Programmable Output Slew-Rate Control

Programmable Output Slew-Rate Control

5-31

The programmable output slew-rate control in the output buffer of each regular- and dual-function I/O pin allows you to configure the following:

• Fast slew-rate—provides high-speed transitions for high-performance systems.

• Slow slew-rate—reduces system noise and crosstalk but adds a nominal delay to the rising and falling edges.

You can specify the slew-rate on a pin-by-pin basis because each I/O pin contains a slew-rate control.

Note:

Altera recommends that you perform IBIS or SPICE simulations to determine the best slew rate setting for your specific application.

Related Information

Programmable IOE Features in Cyclone V Devices

on page 5-29

Programmable IOE Delay

You can activate the programmable IOE delays to ensure zero hold times, minimize setup times, or increase clock-to-output times. This feature helps read and write timing margins because it minimizes the uncertainties between signals in the bus.

Each pin can have a different input delay from pin-to-input register or a delay from output register-to-output pin values to ensure that the signals within a bus have the same delay going into or out of the device.

For more information about the programmable IOE delay specifications, refer to the device datasheet.

Related Information

Cyclone V Device Datasheet

Programmable IOE Features in Cyclone V Devices

on page 5-29

Programmable Output Buffer Delay

The delay chains are built inside the single-ended output buffer. There are four levels of output buffer delay settings. By default, there is no delay.

The delay chains can independently control the rising and falling edge delays of the output buffer, allowing you to:

• Adjust the output-buffer duty cycle

• Compensate channel-to-channel skew

• Reduce simultaneous switching output (SSO) noise by deliberately introducing channel-to-channel skew

• Improve high-speed memory-interface timing margins

For more information about the programmable output buffer delay specifications, refer to the device datasheet.

Related Information

Cyclone V Device Datasheet

Programmable IOE Features in Cyclone V Devices

on page 5-29

I/O Features in Cyclone V Devices

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Programmable Pre-Emphasis

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Programmable Pre-Emphasis

The V

OD setting and the output impedance of the driver set the output current limit of a high-speed transmission signal. At a high frequency, the slew rate may not be fast enough to reach the full V

OD level before the next edge, producing pattern-dependent jitter. With pre-emphasis, the output current is boosted momentarily during switching to increase the output slew rate.

Pre-emphasis increases the amplitude of the high-frequency component of the output signal, and thus helps to compensate for the frequency-dependent attenuation along the transmission line. The overshoot introduced by the extra current happens only during a change of state switching to increase the output slew rate and does not ring, unlike the overshoot caused by signal reflection. The amount of pre-emphasis required depends on the attenuation of the high-frequency component along the transmission line.

Figure 5-11: Programmable Pre-Emphasis

This figure shows the LVDS output with pre-emphasis.

Voltage boost from pre-emphasis

V

P

OUT

V

OD

OUT

V

P

Differential output voltage (peak–peak)

Table 5-26: Quartus II Software Assignment Editor—Programmable Pre-Emphasis

This table lists the assignment name for programmable pre-emphasis and its possible values in the Quartus II software

Assignment Editor.

Field Assignment (Default setting in bold)

To

Assignment name

Allowed values tx_out

Programmable Pre-emphasis

0 (disabled) and 1 (enabled)

Related Information

Programmable IOE Features in Cyclone V Devices

on page 5-29

Programmable Differential Output Voltage

The programmable V

OD settings allow you to adjust the output eye opening to optimize the trace length and power consumption. A higher V

OD swing improves voltage margins at the receiver end, and a smaller

V

OD swing reduces power consumption. You can statically adjust the V changing the V

OD

OD settings in the Quartus II software Assignment Editor.

of the differential signal by

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Figure 5-12: Differential V

OD

This figure shows the V

OD of the differential LVDS output.

Single-Ended Waveform

I/O Pins Features for Cyclone V Devices

Positive Channel (p)

V

OD

V

CM

Negative Channel (n)

Ground

5-33

Differential Waveform

V

OD

V

OD

(diff peak - peak) = 2 x V

OD

(single-ended)

V

OD p - n = 0 V

Table 5-27: Quartus II Software Assignment Editor—Programmable V

OD

This table lists the assignment name for programmable V

OD

Assignment Editor.

and its possible values in the Quartus II software

Field Assignment (Default setting in bold)

To tx_out

Assignment name

Allowed values

Programmable Differential Output Voltage (V

OD

)

00 (low), 01 (medium), 10 (high)

Related Information

Programmable IOE Features in Cyclone V Devices

on page 5-29

I/O Pins Features for Cyclone V Devices

Open-Drain Output

on page 5-33

Bus-Hold Circuitry

on page 5-33

Pull-up Resistor

on page 5-34

Open-Drain Output

The optional open-drain output for each I/O pin is equivalent to an open collector output. If it is configured as an open drain, the logic value of the output is either high-Z or logic low.

Use an external resistor to pull the signal to a logic high.

Bus-Hold Circuitry

Each I/O pin provides an optional bus-hold feature that is active only after configuration. When the device enters user mode, the bus-hold circuit captures the value that is present on the pin by the end of the configuration.

I/O Features in Cyclone V Devices

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Pull-up Resistor

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The bus-hold circuitry uses a resistor with a nominal resistance (R

BH

), approximately 7 kΩ, to weakly pull the signal level to the last-driven state of the pin. The bus-hold circuitry holds this pin state until the next input signal is present. Because of this, you do not require an external pull-up or pull-down resistor to hold a signal level when the bus is tri-stated.

For each I/O pin, you can individually specify that the bus-hold circuitry pulls non-driven pins away from the input threshold voltage—where noise can cause unintended high-frequency switching. To prevent overdriving signals, the bus-hold circuitry drives the voltage level of the I/O pin lower than the V

CCIO level.

If you enable the bus-hold feature, you cannot use the programmable pull-up option. To configure the I/O pin for differential signals, disable the bus-hold feature.

Pull-up Resistor

Each I/O pin provides an optional programmable pull-up resistor during user mode. The pull-up resistor weakly holds the I/O to the V

CCIO level.

The Cyclone V device supports programmable weak pull-up resistors only on user I/O pins but not on dedicated configuration pins, dedicated clock pins, or JTAG pins .

If you enable this option, you cannot use the bus-hold feature.

On-Chip I/O Termination in Cyclone V Devices

Dynamic R

S and R

T

OCT provides I/O impedance matching and termination capabilities. OCT maintains signal quality, saves board space, and reduces external component costs.

The Cyclone V devices support OCT in all FPGA I/O banks. For the HPS I/Os, the column I/Os do not support OCT.

Table 5-28: OCT Schemes Supported in Cyclone V Devices

Output

Input

Bidirectional

Direction OCT Schemes

R

S

OCT with calibration

R

S

OCT without calibration

R

T

OCT with calibration

R

D

OCT (LVDS and SLVS

I/O standards only)

Dynamic R

S

OCT and R

OCT

T

Related Information

R

S

OCT without Calibration in Cyclone V Devices

on page 5-35

R

S

OCT with Calibration in Cyclone V Devices

on page 5-36

R

T

OCT with Calibration in Cyclone V Devices

on page 5-38

LVDS Input R

D

OCT in Cyclone V Devices

on page 5-41

Supported in HPS Row I/Os

Yes

Yes

Yes

Yes

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R

S

OCT without Calibration in Cyclone V Devices

Dynamic OCT in Cyclone V Devices

on page 5-40

5-35

R

S

OCT without Calibration in Cyclone V Devices

The Cyclone V devices support R

S

OCT for single-ended and voltage-referenced I/O standards. R without calibration is supported on output only.

S

OCT

Table 5-29: Selectable I/O Standards for R

S

OCT Without Calibration

This table lists the output termination settings for uncalibrated OCT on different I/O standards.

Uncalibrated OCT (Output)

I/O Standard

R

S

(Ω)

3.0 V LVTTL/3.0 V LVCMOS

2.5 V LVCMOS

25/50

25/50

1.8 V LVCMOS

1.5 V LVCMOS

1.2 V LVCMOS

SSTL-2 Class I

25/50

25/50

25/50

50

SSTL-2 Class II

SSTL-18 Class I

SSTL-18 Class II

SSTL-15 Class I

SSTL-15 Class II

1.8 V HSTL Class I

1.8 V HSTL Class II

1.5 V HSTL Class I

25

50

25

50

25

50

25

50

1.5 V HSTL Class II

1.2 V HSTL Class I

1.2 V HSTL Class II

Differential SSTL-2 Class I

Differential SSTL-2 Class II

Differential SSTL-18 Class I

Differential SSTL-18 Class II

Differential SSTL-15 Class I

Differential SSTL-15 Class II

Differential 1.8 V HSTL Class I

Differential 1.8 V HSTL Class II

Differential 1.5 V HSTL Class I

25

50

25

50

25

50

25

50

25

50

25

50

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R

S

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I/O Standard

Differential 1.5 V HSTL Class II

Differential 1.2 V HSTL Class I

Differential 1.2 V HSTL Class II

SSTL-15

SSTL-135

SSTL-125

HSUL-12

Differential SSTL-15

Differential SSTL-135

Differential SSTL-125

Differential HSUL-12

Uncalibrated OCT (Output)

R

S

(Ω)

25

50

25

25, 50, 34, 40

34, 40

34, 40

34, 40, 48, 60, 80

25, 50, 34, 40

34, 40

34, 40

34, 40, 48, 60, 80

Driver-impedance matching provides the I/O driver with controlled output impedance that closely matches the impedance of the transmission line. As a result, you can significantly reduce signal reflections on PCB traces.

If you select matching impedance, current strength is no longer selectable.

Figure 5-13: R

S

OCT Without Calibration

This figure shows the R

S as the intrinsic impedance of the output transistors.

Driver

Series Termination

V

CCIO

Receiving

Device

R

S

Z

0

= 50 Ω

GND

R

S

Related Information

On-Chip I/O Termination in Cyclone V Devices

on page 5-34

R

S

OCT with Calibration in Cyclone V Devices

The Cyclone V devices support R

S

OCT with calibration in all banks.

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R

S

OCT with Calibration in Cyclone V Devices

Table 5-30: Selectable I/O Standards for R

S

OCT With Calibration

This table lists the output termination settings for calibrated OCT on different I/O standards.

Calibrated OCT (Output)

I/O Standard

R

S

(Ω)

(12)

RZQ

(Ω)

3.0 V LVTTL/3.0 V LVCMOS 25/50 100

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

1.2 V LVCMOS

SSTL-2 Class I

SSTL-2 Class II

25/50

25/50

25/50

25/50

50

25

100

100

100

100

100

100

SSTL-18 Class I

SSTL-18 Class II

SSTL-15 Class I

SSTL-15 Class II

1.8 V HSTL Class I

1.8 V HSTL Class II

1.5 V HSTL Class I

1.5 V HSTL Class II

50

25

50

25

50

25

50

25

100

100

100

100

100

100

100

100

1.2 V HSTL Class I

1.2 V HSTL Class II

Differential SSTL-2 Class I

Differential SSTL-2 Class II

Differential SSTL-18 Class I

Differential SSTL-18 Class II

Differential SSTL-15 Class I

Differential SSTL-15 Class II

Differential 1.8 V HSTL Class I

Differential 1.8 V HSTL Class II

Differential 1.5 V HSTL Class I

Differential 1.5 V HSTL Class II

Differential 1.2 V HSTL Class I

Differential 1.2 V HSTL Class II

50

25

50

25

50

25

50

25

50

25

50

25

50

25

100

100

100

100

100

100

100

100

100

100

100

100

100

100

5-37

(12)

Final values are pending silicon characterization.

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R

T

OCT with Calibration in Cyclone V Devices

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SSTL-15

SSTL-135

SSTL-125

HSUL-12

I/O Standard

Differential SSTL-15

Differential SSTL-135

Differential SSTL-125

Differential HSUL-12

R

S

(Ω)

(12)

25, 50

34, 40

34, 40

34, 40

34, 40, 48, 60, 80

25, 50

Calibrated OCT (Output)

RZQ

(Ω)

100

240

240

240

240

100

34, 40

34, 40

34, 40

34, 40, 48, 60, 80

240

240

240

240

The R

S

OCT calibration circuit compares the total impedance of the I/O buffer to the external reference resistor connected to the

RZQ pin and dynamically enables or disables the transistors until they match.

Calibration occurs at the end of device configuration. When the calibration circuit finds the correct impedance, the circuit powers down and stops changing the characteristics of the drivers.

Figure 5-14: R

S

OCT with Calibration

This figure shows the R

S as the intrinsic impedance of the output transistors.

Driver

Series Termination

V

CCIO

Receiving

Device

R

S

Z

0

= 50 Ω

GND

R

S

Related Information

On-Chip I/O Termination in Cyclone V Devices

on page 5-34

R

T

OCT with Calibration in Cyclone V Devices

The Cyclone V devices support R

T with calibration. If you use R you enable the R

T

OCT.

T

OCT with calibration in all banks. R

T

OCT, the V

CCIO

OCT with calibration is available only for configuration of input and bidirectional pins. Output pin configurations do not support R

T

OCT of the bank must match the I/O standard of the pin where

(12)

Final values are pending silicon characterization.

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R

T

OCT with Calibration in Cyclone V Devices

Table 5-31: Selectable I/O Standards for R

T

OCT With Calibration

This table lists the input termination settings for calibrated OCT on different I/O standards.

Calibrated OCT (Input)

I/O Standard

R

T

(Ω)

(13)

RZQ (Ω)

SSTL-2 Class I 50 100

SSTL-2 Class II

SSTL-18 Class I

SSTL-18 Class II

SSTL-15 Class I

SSTL-15 Class II

1.8 V HSTL Class I

50

50

50

50

50

50

100

100

100

100

100

100

1.8 V HSTL Class II

1.5 V HSTL Class I

1.5 V HSTL Class II

1.2 V HSTL Class I

1.2 V HSTL Class II

Differential SSTL-2 Class I

Differential SSTL-2 Class II

Differential SSTL-18 Class I

50

50

50

50

50

50

50

50

100

100

100

100

100

100

100

100

Differential SSTL-18 Class II

Differential SSTL-15 Class I

Differential SSTL-15 Class II

Differential 1.8 V HSTL Class I

Differential 1.8 V HSTL Class II

Differential 1.5 V HSTL Class I

Differential 1.5 V HSTL Class II

Differential 1.2 V HSTL Class I

Differential 1.2 V HSTL Class II

SSTL-15

SSTL-135

SSTL-125

Differential SSTL-15

Differential SSTL-135

50

50

50

50

50

50

50

50

50

20, 30, 40, 60,120

20, 30, 40, 60, 120

20, 30, 40, 60, 120

20, 30, 40, 60,120

20, 30, 40, 60, 120

100

240

240

240

240

240

100

100

100

100

100

100

100

100

5-39

(13)

Final values are pending silicon characterization.

I/O Features in Cyclone V Devices

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I/O Standard

R

T

(Ω)

(13)

20, 30, 40, 60, 120

Calibrated OCT (Input)

RZQ (Ω)

240 Differential SSTL-125

The R

T

OCT calibration circuit compares the total impedance of the I/O buffer to the external resistor connected to the

RZQ pin. The circuit dynamically enables or disables the transistors until the total impedance of the I/O buffer matches the external resistor.

Calibration occurs at the end of the device configuration. When the calibration circuit finds the correct impedance, the circuit powers down and stops changing the characteristics of the drivers.

Figure 5-15: R

T

OCT with Calibration

V

CCIO

FPGA OCT

100 Ω

Z

0

= 50 Ω

V

REF

100 Ω

Transmitter

GND

Receiver

Related Information

On-Chip I/O Termination in Cyclone V Devices

on page 5-34

Dynamic OCT in Cyclone V Devices

Dynamic OCT is useful for terminating a high-performance bidirectional path by optimizing the signal integrity depending on the direction of the data. Dynamic OCT also helps save power because device termination is internal—termination switches on only during input operation and thus draw less static power.

Note:

If you use the SSTL-15, SSTL-135, and SSTL-125 I/O standards with the DDR3 memory interface,

Altera recommends that you use dynamic OCT with these I/O standards to save board space and cost. Dynamic OCT reduces the number of external termination resistors used.

Table 5-32: Dynamic OCT Based on Bidirectional I/O

Dynamic R

T driver.

OCT or R

S

OCT is enabled or disabled based on whether the bidirectional I/O acts as a receiver or

Dynamic OCT Bidirectional I/O State

Dynamic R

Dynamic R

T

S

OCT

OCT

Acts as a receiver

Acts as a driver

Acts as a receiver

Acts as a driver

Enabled

Disabled

Disabled

Enabled

(13)

Final values are pending silicon characterization.

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Figure 5-16: Dynamic R

T

OCT in Cyclone V Devices

V

CCIO

Transmitter

50 Ω

100 Ω

Z

0

= 50 Ω

100 Ω

Receiver

50 Ω

FPGA OCT

GND

V

CCIO

100 Ω

Z

0

= 50 Ω

FPGA OCT

GND

100 Ω

LVDS Input R

D

OCT in Cyclone V Devices

V

CCIO

100 Ω

Receiver

GND

100 Ω

FPGA OCT

V

CCIO

100 Ω

50 Ω

Transmitter

GND

100 Ω

FPGA OCT

50 Ω

5-41

Related Information

On-Chip I/O Termination in Cyclone V Devices

on page 5-34

LVDS Input R

D

OCT in Cyclone V Devices

The Cyclone V devices support R

D

OCT in all I/O banks.

You can only use R

D

OCT if you set the V

CCPD to 2.5 V.

Figure 5-17: Differential Input OCT

The Cyclone V devices support OCT for differential LVDS and SLVS input buffers with a nominal resistance value of 100 Ω, as shown in this figure.

Transmitter Receiver

Z

0

= 50 Ω

100 Ω

Z

0

= 50 Ω

Related Information

On-Chip I/O Termination in Cyclone V Devices

on page 5-34

I/O Features in Cyclone V Devices

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OCT Calibration Block in Cyclone V Devices

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OCT Calibration Block in Cyclone V Devices

You can calibrate the OCT using any of the available four OCT calibration blocks for each device. Each calibration block contains one

RZQ pin.

You can use R

S same V

CCIO and R the same I/O buffer.

T

OCT in the same I/O bank for different I/O standards if the I/O standards use the supply voltage. You cannot configure the R

S

OCT and the programmable current strength for

The OCT calibration process uses the

RZQ pin that is available in every calibration block in a given I/O bank for series- and parallel-calibrated termination:

• Connect the

RZQ pin to GND through an external 100 Ω or 240 Ω resistor (depending on the R

S

OCT value).

or R

T

• The

RZQ pin shares the same V

CCIO supply voltage with the I/O bank where the pin is located.

Cyclone V devices support calibrated R

S configuration pins.

and calibrated R

T

OCT on all I/O pins except for dedicated

Calibration Block Locations in Cyclone V Devices

Figure 5-18: OCT Calibration Block and RZQ Pin Location

This figure shows the location of I/O banks with OCT calibration blocks and

RZQ pins in the Cyclone V device.

RZQ pin

Bank 8A Bank 7A

Bank 3A Bank 3B

RZQ pin

Calibration block

Bank 4A

Sharing an OCT Calibration Block on Multiple I/O Banks

An OCT calibration block has the same V

CCIO the same V

CCIO as the I/O bank that contains the block. All I/O banks with can share one OCT calibration block, even if that particular I/O bank has an OCT calibration block.

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OCT Calibration Block Sharing Example

5-43

I/O banks that do not have calibration blocks share the calibration blocks in the I/O banks that have calibration blocks.

All I/O banks support OCT calibration with different V

CCIO

OCT calibration blocks.

voltage standards, up to the number of available

You can configure the I/O banks to receive calibration codes from any OCT calibration block with the same

V

CCIO

. If a group of I/O banks has the same V

CCIO voltage, you can use one OCT calibration block to calibrate the group of I/O banks placed around the periphery.

Related Information

OCT Calibration Block Sharing Example

on page 5-43

Dynamic Calibrated On-Chip Termination (ALTOCT) Megafunction User Guide

Provides more information about the OCT calibration block.

OCT Calibration Block Sharing Example

Figure 5-19: Example of Calibrating Multiple I/O Banks with One Shared OCT Calibration Block

As an example, this figure shows a group of I/O banks that has the same V

CCIO show transceiver calibration blocks.

voltage. The figure does not

Bank 8A Bank 7A

CB3

Bank 3A Bank 3B

I/O bank with different V

CCIO

I/O bank with the same V

CCIO

Bank 4A

Because banks 5A and 7A have the same V

CCIO as bank 3A, you can calibrate all three I/O banks (3A, 5A, and 7A) with the OCT calibration block (CB3) located in bank 3A.

To enable this calibration, serially shift out the R

S in bank 3A to the I/O banks around the periphery.

OCT calibration codes from the OCT calibration block

Related Information

Sharing an OCT Calibration Block on Multiple I/O Banks

on page 5-42

I/O Features in Cyclone V Devices

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External I/O Termination for Cyclone V Devices

Dynamic Calibrated On-Chip Termination (ALTOCT) Megafunction User Guide

Provides more information about the OCT calibration block.

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External I/O Termination for Cyclone V Devices

Table 5-33: External Termination Schemes for Different I/O Standards

I/O Standard

3.3 V LVTTL/3.3 V LVCMOS

3.0 V LVVTL/3.0 V LVCMOS

3.0 V PCI

3.0 V PCI-X

2.5 V LVCMOS

1.8 V LVCMOS

1.5 V LVCMOS

1.2 V LVCMOS

SSTL-2 Class I

SSTL-2 Class II

SSTL-18 Class I

SSTL-18 Class II

SSTL-15 Class I

SSTL-15 Class II

1.8 V HSTL Class I

1.8 V HSTL Class II

1.5 V HSTL Class I

1.5 V HSTL Class II

1.2 V HSTL Class I

1.2 V HSTL Class II

Differential SSTL-2 Class I

Differential SSTL-2 Class II

Differential SSTL-18 Class I

Differential SSTL-18 Class II

Differential SSTL-15 Class I

Differential SSTL-15 Class II

External Termination Scheme

No external termination required

Single-Ended SSTL I/O Standard Termination

Single-Ended HSTL I/O Standard Termination

Differential SSTL I/O Standard Termination

Altera Corporation

I/O Features in Cyclone V Devices

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I/O Standard

Differential 1.8 V HSTL Class I

Differential 1.8 V HSTL Class II

Differential 1.5 V HSTL Class I

Differential 1.5 V HSTL Class II

Differential 1.2 V HSTL Class I

Differential 1.2 V HSTL Class II

LVDS

RSDS

Mini-LVDS

LVPECL

SLVS

SSTL-15

(14)

SSTL-135

(14)

SSTL-125

(14)

HSUL-12

Differential SSTL-15

(14)

Differential SSTL-135

(14)

Differential SSTL-125

(14)

Differential HSUL-12

Single-ended I/O Termination

External Termination Scheme

5-45

Differential HSTL I/O Standard Termination

LVDS I/O Standard Termination

RSDS/mini-LVDS I/O Standard Termination

Differential LVPECL I/O Standard Termination

SLVS I/O Standard Termination

No external termination required

Single-ended I/O Termination

Voltage-referenced I/O standards require an input V

REF and a termination voltage (V

TT

). The reference voltage of the receiving device tracks the termination voltage of the transmitting device.

The supported I/O standards such as SSTL-125, SSTL-135, and SSTL-15 typically do not require external board termination.

Altera recommends that you use dynamic OCT with these I/O standards to save board space and cost.

Dynamic OCT reduces the number of external termination resistors used.

Note:

You cannot use R

S information.

and R

T

OCT simultaneously. For more information, refer to the related

(14)

Altera recommends that you use dynamic OCT with these I/O standards to save board space and cost. Dynamic

OCT reduces the number of external termination resistors used.

I/O Features in Cyclone V Devices

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Single-ended I/O Termination

Figure 5-20: SSTL I/O Standard Termination

This figure shows the details of SSTL I/O termination on Cyclone V devices.

Termination SSTL Class I

V

TT

V

TT

SSTL Class II

V

TT

External

On-Board

Termination

25 Ω

50 Ω

50 Ω

VREF

25 Ω

50 Ω

50 Ω

50 Ω

VREF

Transmitter Receiver Transmitter

OCT Transmit

Series OCT 50 Ω

50 Ω

50 Ω

VREF

V

TT

Series OCT 25 Ω

V

TT

50 Ω

50 Ω

50 Ω

VREF

V

TT

Transmitter

OCT Receive

OCT in

Bidirectional

Pins

Transmitter

Transmitter

V

CCIO

Series

OCT 50 Ω

100 Ω

100 Ω

FPGA

GND

25 Ω

50 Ω

VREF

V

CCIO

100 Ω

Receiver

FPGA

Parallel OCT

VREF

50 Ω

VREF

100 Ω

GND

V

CCIO

Receiver

100 Ω

100 Ω

GND

Series

OCT 50 Ω

FPGA

V

TT

50 Ω

25 Ω

50 Ω

VREF

Transmitter

V

CCIO

Series

OCT 25 Ω

100 Ω

100 Ω

FPGA

GND

VREF

VREF

50 Ω

Receiver

V

CCIO

100 Ω

Receiver

FPGA

Parallel OCT

100 Ω

GND

Receiver

V

CCIO

100 Ω

100 Ω

GND

Series

OCT 25 Ω

FPGA

CV-52005

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I/O Features in Cyclone V Devices

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Figure 5-21: HSTL I/O Standard Termination

This figure shows the details of HSTL I/O termination on the Cyclone V devices.

Termination

External

On-Board

Termination

HSTL Class I

50 Ω

50 Ω

VREF

V

TT

Differential I/O Termination

HSTL Class II

V

TT

50 Ω

50 Ω

50 Ω

VREF

V

TT

Transmitter Receiver Transmitter Receiver

OCT Transmit

Series OCT 50 Ω

50 Ω

50 Ω

VREF

V

TT

Series OCT 25 Ω

V

TT

50 Ω

50 Ω

50 Ω

VREF

V

TT

Transmitter

V

CCIO

100 Ω

Receiver

FPGA

Parallel OCT

OCT Receive

OCT in

Bidirectional

Pins

50 Ω

VREF

Transmitter

V

CCIO

Series

OCT 50 Ω

100 Ω

FPGA

100 Ω

GND

VREF

VREF

50 Ω

100 Ω

GND

Receiver

V

CCIO

100 Ω

100 Ω

GND

Series

OCT 50 Ω

FPGA

Transmitter

V

TT

50 Ω

50 Ω

VREF

Transmitter

V

CCIO

Series

OCT 25 Ω

100 Ω

FPGA

100 Ω

GND

VREF

VREF

50 Ω

V

CCIO

100 Ω

Receiver

FPGA

Parallel OCT

100 Ω

GND

Receiver

V

CCIO

100 Ω

100 Ω

GND

Series

OCT 25 Ω

FPGA

5-47

Related Information

Dynamic OCT in Cyclone V Devices

on page 5-40

Differential I/O Termination

The I/O pins are organized in pairs to support differential I/O standards. Each I/O pin pair can support differential input and output buffers.

The supported I/O standards such as Differential SSTL-15, Differential SSTL-125, and Differential SSTL-

135 typically do not require external board termination.

Altera recommends that you use dynamic OCT with these I/O standards to save board space and cost.

Dynamic OCT reduces the number of external termination resistors used.

Differential HSTL, SSTL, and HSUL Termination

Differential HSTL, SSTL, and HSUL inputs use LVDS differential input buffers. However, R

D only available if the I/O standard is LVDS.

support is

Differential HSTL, SSTL, and HSUL outputs are not true differential outputs. These I/O standards use two single-ended outputs with the second output programmed as inverted.

I/O Features in Cyclone V Devices

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LVDS, RSDS, SLVS, and Mini-LVDS Termination

Figure 5-22: Differential SSTL I/O Standard Termination

This figure shows the details of Differential SSTL I/O termination on Cyclone V devices.

Termination Differential SSTL Class I

V

TT

V

TT

50 Ω

25 Ω

50 Ω

50 Ω 50 Ω

V

TT

V

TT

Differential SSTL Class II

V

TT

V

TT

50 Ω

50 Ω

50 Ω 50 Ω

25 Ω

External

On-Board

Termination

25 Ω 25 Ω

50 Ω 50 Ω

Transmitter

OCT

Series OCT 50 Ω

Transmitter

Z

0

= 50 Ω

Z

0

= 50 Ω

V

CCIO

100 Ω

V

CCIO

100 Ω

GND

100 Ω

100 Ω

GND

Receiver

Receiver Transmitter

Series OCT 25 Ω

Transmitter

V

TT

V

TT

50 Ω

Z

0

= 50 Ω

V

CCIO

100 Ω

50 Ω

Z

0

= 50 Ω

V

CCIO

100 Ω

GND

100 Ω

GND

100 Ω

Receiver

Receiver

Figure 5-23: Differential HSTL I/O Standard Termination

This figure shows the details of Differential HSTL I/O standard termination on Cyclone V devices.

Termination Differential HSTL Class I

V

TT

V

TT

50 Ω

50 Ω

50 Ω 50 Ω

V

TT

V

TT

Differential HSTL Class II

V

TT

V

TT

50 Ω

50 Ω

50 Ω 50 Ω

External

On-Board

Termination

50 Ω 50 Ω

Transmitter

OCT

Series OCT 50 Ω

Transmitter

Z

0

= 50 Ω

Z

0

= 50 Ω

V

CCIO

100 Ω

V

CCIO

100 Ω

100 Ω

GND

100 Ω

GND

Receiver

Receiver Transmitter

Series OCT 25 Ω

Transmitter

V

TT

V

CCIO

V

TT

50 Ω

Z

0

= 50 Ω

V

CCIO

50 Ω

Z

0

= 50 Ω

100 Ω

100 Ω

100 Ω

GND

100 Ω

GND

Receiver

Receiver

CV-52005

2014.01.10

LVDS, RSDS, SLVS, and Mini-LVDS Termination

All I/O banks have dedicated circuitry to support the true LVDS, RSDS, SLVS, and mini-LVDS I/O standards by using true LVDS output buffers without resistor networks.

Altera Corporation

I/O Features in Cyclone V Devices

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Figure 5-24: LVDS and SLVS I/O Standard Termination

Emulated LVDS, RSDS, and Mini-LVDS Termination

5-49

This figure shows the LVDS and SLVS I/O standards termination. The on-chip differential resistor is available in all I/O banks.

Termination LVDS or SLVS

Differential Outputs Differential Inputs

External

On-Board

Termination

50 Ω

100 Ω

50 Ω

OCT Receiver

(True LVDS or SLVS

Output)

Differential Outputs

50 Ω

50 Ω

Differential Inputs

OCT

100 Ω

Receiver

Emulated LVDS, RSDS, and Mini-LVDS Termination

The I/O banks also support emulated LVDS, RSDS, and mini-LVDS I/O standards.

Emulated LVDS, RSDS and mini-LVDS output buffers use two single-ended output buffers with an external single-resistor or three-resistor network, and can be tri-stated.

I/O Features in Cyclone V Devices

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Emulated LVDS, RSDS, and Mini-LVDS Termination

Figure 5-25: Emulated LVDS, RSDS, or Mini-LVDS I/O Standard Termination

CV-52005

2014.01.10

The output buffers, as shown in this figure, are available in all I/O banks. R

S characterization.

and R

P values are pending

Termination Emulated LVDS, RSDS, and mini-LVDS

External

On-Board

Termination

(RSDS_E_3R)

1 inch

R

S

R

S

External Resistor

R

P

50 Ω

50 Ω

100 Ω

Transmitter Receiver

OCT

OCT

(RSDS_E_3R)

Transmitter

Single-Ended Outputs

1 inch

R

S

R

S

External Resistor

R

P

50 Ω

50 Ω

OCT Receive

(Single-Ended

Output with

Single Resistor

LVDS_E_1R)

External

Resistor

R

P

50 Ω

50 Ω

100 Ω

Receiver

Differential Inputs

OCT

100 Ω

Receiver

Differential Inputs

OCT

OCT Receive

(Single-Ended

Output with

Three-Resistor

Network,

LVDS_E_3R)

Transmitter

Single-Ended Outputs

1 inch

R

S

R

S

External Resistor

R

P

50 Ω

50 Ω

Transmitter

100 Ω

Receiver

To meet the RSDS or mini-LVDS specifications, you require a resistor network to attenuate the outputvoltage swing.

Altera Corporation

I/O Features in Cyclone V Devices

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LVPECL Termination

5-51

You can modify the three-resistor network values to reduce power or improve the noise margin. Choose resistor values that satisfy the following equation.

Figure 5-26: Resistor Network Calculation

Note:

Altera recommends that you perform additional simulations with IBIS or SPICE models to validate that the custom resistor values meet the RSDS or mini-LVDS I/O standard requirements.

For information about the data rates supported for external single resistor or three-resistor network, refer to the device datasheet.

Related Information

Cyclone V Device Datasheet

National Semiconductor (www.national.com)

For more information about the RSDS I/O standard, refer to the

RSDS Specification

on the National

Semiconductor web site.

LVPECL Termination

The Cyclone V devices support the LVPECL I/O standard on input clock pins only:

• LVPECL input operation is supported using LVDS input buffers.

• LVPECL output operation is not supported.

Use AC coupling if the LVPECL common-mode voltage of the output buffer does not match the LVPECL input common-mode voltage.

Note:

Altera recommends that you use IBIS models to verify your LVPECL AC/DC-coupled termination.

Figure 5-27: LVPECL AC-Coupled Termination

LVPECL

Output Buffer

LVPECL

Input Buffer

0.1 µF

0.1 µF

Z

0

= 50 Ω

Z

0

= 50 Ω

V

ICM

50 Ω

50 Ω

Support for DC-coupled LVPECL is available if the LVPECL output common mode voltage is within the

Cyclone V LVPECL input buffer specification.

I/O Features in Cyclone V Devices

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Dedicated High-Speed Circuitries

Figure 5-28: LVPECL DC-Coupled Termination

LVPECL

Output Buffer

LVPECL

Input Buffer

CV-52005

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Z

0

= 50 Ω

Z

0

= 50 Ω

100 Ω

For information about the V

ICM specification, refer to the device datasheet.

Related Information

Cyclone V Device Datasheet

Dedicated High-Speed Circuitries

The Cyclone V device has dedicated circuitries for differential transmitter and receiver to transmit or receive high-speed differential signals.

Table 5-34: Features and Dedicated Circuitries of the Differential Transmitter and Receiver

Feature

True differential buffer

SERDES

Fractional PLL

Differential Transmitter

LVDS, mini-LVDS, and RSDS

Up to 10 bit serializer

Clocks the load and shift registers

Programmable V

OD

Statically assignable

Programmable pre-emphasis Boosts output current

— Data realignment block (Bitslip)

Skew adjustment

On-chip termination (OCT)

Differential Receiver

LVDS, SLVS, mini-LVDS, and RSDS

Up to 10 bit deserializer

Generates different phases of a clock for data synchronizer

Inserts bit latencies into serial data

Manual

100 Ω in LVDS and SLVS standards

Related Information

Guideline: Use PLLs in Integer PLL Mode for LVDS

on page 5-12

High-Speed Differential I/O Locations

The following figures show the locations of the dedicated serializer/deserializer (SERDES) circuitry and the high-speed I/Os in the Cyclone V devices.

Altera Corporation

I/O Features in Cyclone V Devices

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High-Speed Differential I/O Locations

Figure 5-29: High-Speed Differential I/O Locations in Cyclone V E A2 and A4 Devices

5-53

General Purpose I/O and High-Speed

LVDS I/O with SERDES

Fractional PLL

FPGA Fabric

(Logic Elements, DSP,

Embedded Memory,

Clock Networks)

Figure 5-30: High-Speed Differential I/O Locations in Cyclone V GX C3 Devices

General Purpose I/O and High-Speed

LVDS I/O with SERDES

Fractional PLL

Transceiver Block

FPGA Fabric

(Logic Elements, DSP,

Embedded Memory,

Clock Networks)

Figure 5-31: High-Speed Differential I/O Locations in Cyclone V GX C4, C5, C7, and C9 Devices, and Cyclone V

GT D5, D7, and D9 Devices

General Purpose I/O and High-Speed

LVDS I/O with SERDES

Fractional PLL

Transceiver Block

FPGA Fabric

(Logic Elements, DSP,

Embedded Memory,

Clock Networks)

I/O Features in Cyclone V Devices

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LVDS SERDES Circuitry

Figure 5-32: High-Speed Differential I/O Locations in Cyclone V SE A2, A4, A5, and A6 Devices

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General Purpose I/O and High-Speed

LVDS I/O with SERDES

Fractional PLL

HPS I/O

FPGA Fabric

(Logic Elements, DSP,

Embedded Memory,

Clock Networks)

HPS Core

Figure 5-33: High-Speed Differential I/O Locations in Cyclone V SX C2, C4, C5, and C6 Devices, and Cyclone V

ST D5 and D6 Devices

General Purpose I/O and High-Speed

LVDS I/O with SERDES

Fractional PLL

HPS I/O

Transceiver Block

FPGA Fabric

(Logic Elements, DSP,

Embedded Memory,

Clock Networks)

HPS Core

Related Information

PLLs and Clocking

on page 5-12

I/O design guidelines related to PLLs and clocking.

Guideline: Use PLLs in Integer PLL Mode for LVDS

on page 5-12

LVDS SERDES Circuitry

The following figure shows a transmitter and receiver block diagram for the LVDS SERDES circuitry with the interface signals of the transmitter and receiver data paths.

Altera Corporation

I/O Features in Cyclone V Devices

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Figure 5-34: LVDS SERDES

True LVDS Buffers in Cyclone V Devices

10 bits maxiumum data width tx_in

10

Serializer

2

IOE

IOE supports SDR, DDR, or non-registered datapath

DIN DOUT

LVDS Transmitter

+

– tx_coreclock rx_out

10

10

3

(LVDS_LOAD_EN, diffioclk, tx_coreclock)

IOE supports SDR, DDR, or non-registered datapath

2

IOE

Deserializer Bit Slip

DOUT DIN DOUT DIN

FPGA

Fabric

diffioclk

2

(LOAD_EN, diffioclk) rx_outclock

LVDS Receiver

tx_out

+

– rx_in

LVDS Clock Domain

3 (LVDS_LOAD_EN,

LVDS_diffioclk, rx_outclock)

Fractional PLL rx_inclock / tx_inclock

5-55

The preceding figure shows a shared PLL between the transmitter and receiver. If the transmitter and receiver do not share the same PLL, you require two fractional PLLs. In single data rate (SDR) and double data rate

(DDR) modes, the data width is 1 and 2 bits, respectively.

Note:

For the maximum data rate supported by the Cyclone V devices, refer to the device overview.

Related Information

Cyclone V Device Overview

LVDS SERDES Transmitter/Receiver (ALTLVDS_TX and ALTLVDS_RX) Megafunction User Guide

Provides a list of the LVDS transmitter and receiver ports and settings using ALTLVDS.

Guideline: Use PLLs in Integer PLL Mode for LVDS

on page 5-12

True LVDS Buffers in Cyclone V Devices

The Cyclone V device family supports LVDS on all I/O banks:

• Both row and column I/Os support true LVDS input buffers with R

D

OCT and true LVDS output buffers.

• Cyclone V devices offer single-ended I/O reference clock support for the fractional PLL that drives the

SERDES.

Note:

True LVDS output buffers cannot be tri-stated.

The following tables list the number of true LVDS buffers supported in Cyclone V devices with these conditions:

• The LVDS channel count does not include dedicated clock pins.

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True LVDS Buffers in Cyclone V Devices

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• Each I/O sub-bank can support up to two independent ALTLVDS interfaces. For example, you can place two ALTLVDS interfaces in bank 8A driven by two different PLLs, provided that the LVDS channels are not interleaved.

Table 5-35: LVDS Channels Supported in Cyclone V E Devices

Member Code

A2 and A4

A5

Package

256-pin FineLine BGA

324-pin Ultra FineLine BGA

383-pin Micro FineLine BGA

484-pin Ultra FineLine BGA

484-pin FineLine BGA

383-pin Micro FineLine BGA

484-pin Ultra FineLine BGA

484-pin FineLine BGA

RX

24

28

8

24

8

21

20

12

4

8

24

19

4

8

24

20

12

8

20

20

8

8

16

19

8

12

12

8

4

TX

24

28

8

24

7

16

20

12

4

8

24

15

4

8

24

20

12

7

16

20

8

8

16

15

8

12

12

8

4

Side

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Left

Right

Bottom

Top

Left

Right

Bottom

Top

Top

Left

Right

Bottom

Top

Left

Right

Bottom

Top

Left

Right

Bottom

Top

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I/O Features in Cyclone V Devices

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Member Code Package

484-pin Micro FineLine BGA

A7

A9

484-pin Ultra FineLine BGA

484-pin FineLine BGA

672-pin FineLine BGA

896-pin FineLine BGA

484-pin Ultra FineLine BGA

484-pin FineLine BGA

672-pin FineLine BGA

896-pin FineLine BGA

Side

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

True LVDS Buffers in Cyclone V Devices

RX

8

24

28

24

20

16

24

24

32

40

40

40

32

40

40

40

8

24

28

24

20

16

24

28

20

16

24

TX

8

24

28

24

20

16

24

24

32

40

40

40

32

40

40

40

8

24

28

24

20

16

24

28

20

16

24

5-57

I/O Features in Cyclone V Devices

Send Feedback

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5-58

True LVDS Buffers in Cyclone V Devices

Table 5-36: LVDS Channels Supported in Cyclone V GX Devices

Member Code

C3

C4

Package

324-pin Ultra FineLine BGA

484-pin Ultra FineLine BGA

484-pin FineLine BGA

301-pin Micro FineLine BGA

383-pin Micro FineLine BGA

484-pin Ultra FineLine BGA

484-pin FineLine BGA

672-pin FineLine BGA

Side

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

TX

24

28

8

24

7

16

20

12

28

24

32

6

7

8

15

24

20

8

24

12

8

16

20

8

RX

24

28

8

24

8

21

20

12

28

24

32

15

8

20

19

24

20

8

24

12

8

16

20

8

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Member Code

C5

C7

Package

301-pin Micro FineLine BGA

383-pin Micro FineLine BGA

484-pin Ultra FineLine BGA

484-pin FineLine BGA

672-pin FineLine BGA

484-pin Micro FineLine BGA

484-pin Ultra FineLine BGA

484-pin FineLine BGA

672-pin FineLine BGA

896-pin FineLine BGA

True LVDS Buffers in Cyclone V Devices

RX

40

40

40

24

28

24

32

16

24

28

8

20

16

24

20

24

28

24

32

12

24

28

8

19

8

21

20

15

8

20

TX

40

40

40

24

28

24

32

16

24

28

8

20

16

24

20

24

28

24

32

12

24

28

8

15

7

16

20

6

7

8

Side

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

5-59

I/O Features in Cyclone V Devices

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5-60

Member Code

C9

Package

484-pin Ultra FineLine BGA

484-pin FineLine BGA

672-pin FineLine BGA

896-pin FineLine BGA

1152-pin FineLine BGA

Side

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Table 5-37: LVDS Channels Supported in Cyclone V GT Devices

Member Code

D5

True LVDS Buffers in Cyclone V Devices

Package

301-pin Micro FineLine BGA

383-pin Micro FineLine BGA

484-pin Ultra FineLine BGA

484-pin FineLine BGA

672-pin FineLine BGA

Side

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Altera Corporation

TX

20

12

24

28

8

15

6

7

7

16

8

24

28

24

32

TX

40

48

44

48

24

32

40

40

24

8

24

28

20

16

24

RX

20

12

24

28

15

8

20

19

8

21

8

24

28

24

32

I/O Features in Cyclone V Devices

Send Feedback

RX

40

48

44

48

24

32

40

40

24

8

24

28

20

16

24

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Member Code Package

484-pin Micro FineLine BGA

D7

D9

484-pin Ultra FineLine BGA

484-pin FineLine BGA

672-pin FineLine BGA

896-pin FineLine BGA

484-pin Ultra FineLine BGA

484-pin FineLine BGA

672-pin FineLine BGA

896-pin FineLine BGA

1152-pin FineLine BGA

True LVDS Buffers in Cyclone V Devices

RX

48

44

48

32

40

40

40

8

24

28

24

20

16

24

24

32

40

40

40

8

24

28

24

20

16

24

28

20

16

24

TX

48

44

48

32

40

40

40

8

24

28

24

20

16

24

24

32

40

40

40

8

24

28

24

20

16

24

28

20

16

24

Side

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

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I/O Features in Cyclone V Devices

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True LVDS Buffers in Cyclone V Devices

Table 5-38: LVDS Channels Supported in Cyclone V SE Devices

Member Code

A2 and A4

A5 and A6

Package

484-pin Ultra FineLine BGA

672-pin Ultra FineLine BGA

484-pin Ultra FineLine BGA

672-pin Ultra FineLine BGA

896-pin FineLine BGA

Side

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Table 5-39: LVDS Channels Supported in Cyclone V SX Devices

Member Code

C2 and C4

C5 and C6

Package

672-pin Ultra FineLine BGA

672-pin Ultra FineLine BGA

896-pin FineLine BGA

Side

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Table 5-40: LVDS Channels Supported in Cyclone V ST Devices

Member Code Package

D5 and D6 896-pin FineLine BGA

Side

Top

Right

Bottom

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TX

1

5

26

20

1

5

26

12

40

TX

1

5

26

20

26

1

4

10

12

40

10

1

5

1

4

RX

2

6

29

20

2

6

29

12

40

RX

2

6

29

20

29

2

4

12

12

40

12

2

6

2

4

TX

20

12

40

RX

20

12

40

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Emulated LVDS Buffers in Cyclone V Devices

Related Information

Guideline: Use PLLs in Integer PLL Mode for LVDS

on page 5-12

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Emulated LVDS Buffers in Cyclone V Devices

The Cyclone V device family supports emulated LVDS on all I/O banks:

• You can use unutilized true LVDS input channels as emulated LVDS output buffers (eTX), which use two single-ended output buffers with an external resistor network to support LVDS, mini-LVDS, and

RSDS I/O standards.

• The emulated differential output buffers support tri-state capability.

Differential Transmitter in Cyclone V Devices

The Cyclone V transmitter contains dedicated circuitry to support high-speed differential signaling. The differential transmitter buffers support the following features:

• LVDS signaling that can drive out LVDS, mini-LVDS, and RSDS signals

• Programmable V

OD and programmable pre-emphasis

Transmitter Blocks

The dedicated circuitry consists of a true differential buffer, a serializer, and fractional PLLs that you can share between the transmitter and receiver. The serializer takes up to 10 bits wide parallel data from the

FPGA fabric, clocks it into the load registers, and serializes it using shift registers that are clocked by the fractional PLL before sending the data to the differential buffer. The MSB of the parallel data is transmitted first.

Note:

To drive the LVDS channels, you must use the PLLs in integer PLL mode.

The following figure shows a block diagram of the transmitter. In SDR and DDR modes, the data width is

1 and 2 bits, respectively.

Figure 5-35: LVDS Transmitter

FPGA

Fabric

10 bits maximum data width tx_in tx_coreclock

10

Serializer

DIN DOUT

2

IOE

IOE supports SDR, DDR, or non-registered datapath

3

(LVDS_LOAD_EN, diffioclk, tx_coreclock)

Fractional PLL tx_inclock

LVDS Transmitter

+

– tx_out

LVDS Clock Domain

Related Information

Guideline: Use PLLs in Integer PLL Mode for LVDS

on page 5-12

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Transmitter Clocking

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Transmitter Clocking

The fractional PLL generates the parallel clocks (rx_outclock and tx_outclock), the load enable (

LVDS_LOAD_EN

) signal and the diffioclk signal (the clock running at serial data rate) that clocks the load and shift registers.

You can statically set the serialization factor to x4, x5, x6, x7, x8, x9, or x10 using the Quartus II software.

The load enable signal is derived from the serialization factor setting.

You can configure any Cyclone V transmitter data channel to generate a source-synchronous transmitter clock output. This flexibility allows the placement of the output clock near the data outputs to simplify board layout and reduce clock-to-data skew.

Different applications often require specific clock-to-data alignments or specific data-rate-to-clock-rate factors. You can specify these settings statically in the Quartus II MegaWizard Plug-In Manager:

• The transmitter can output a clock signal at the same rate as the data—with a maximum output clock frequency that each speed grade of the device supports.

• You can divide the output clock by a factor of 1, 2, 4, 6, 8, or 10, depending on the serialization factor.

• You can set the phase of the clock in relation to the data using internal PLL option of the ALTLVDS megafunction. The fractional PLLs provide additional support for other phase shifts in 45° increments.

The following figure shows the transmitter in clock output mode. In clock output mode, you can use an

LVDS channel as a clock output channel.

Figure 5-36: Transmitter in Clock Output Mode

Transmitter Circuit

Parallel Series

Txclkout+

Txclkout–

FPGA

Fabric

Fractional

PLL diffioclk

LVDS_LOAD_EN

Related Information

Guideline: Use PLLs in Integer PLL Mode for LVDS

on page 5-12

Serializer Bypass for DDR and SDR Operations

You can bypass the serializer to support DDR (x2) and SDR (x1) operations to achieve a serialization factor of 2 and 1, respectively. The I/O element (IOE) contains two data output registers that can each operate in either DDR or SDR mode.

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FPGA

Fabric

tx_in

2

Serializer

2

IOE

DIN DOUT

Differential Receiver in Cyclone V Devices

+

– tx_out

5-65

Figure 5-37: Serializer Bypass

This figure shows the serializer bypass path. In DDR mode, tx_inclock clocks the IOE register. In SDR mode, data is passed directly through the IOE. In SDR and DDR modes, the data width to the IOE is 1 and

2 bits, respectively.

IOE supports SDR, DDR, or non-registered datapath tx_coreclock

LVDS Transmitter

3 (LVDS_LOAD_EN, diffioclk, tx_coreclock)

Fractional PLL Note: Disabled blocks and signals are grayed out

Differential Receiver in Cyclone V Devices

The receiver has a differential buffer and fractional PLLs that you can share among the transmitter and receiver, a data realignment block, and a deserializer. The differential buffer can receive LVDS, mini-LVDS, and RSDS signal levels. You can statically set the I/O standard of the receiver pins to LVDS, SLVS, mini-

LVDS, or RSDS in the Quartus II software Assignment Editor.

Note:

To drive the LVDS channels, you must use the PLLs in integer PLL mode.

Related Information

Guideline: Use PLLs in Integer PLL Mode for LVDS

on page 5-12

Receiver Blocks in Cyclone V Devices

The Cyclone V differential receiver has the following hardware blocks:

• Data realignment block (bit slip)

• Deserializer

The following figure shows the hardware blocks of the receiver. In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively. The deserializer includes shift registers and parallel load registers, and sends a maximum of 10 bits to the internal logic.

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Data Realignment Block (Bit Slip)

Figure 5-38: Receiver Block Diagram

10 bits maxiumum data width rx_out

10

FPGA

Fabric

10

IOE supports SDR, DDR, or non-registered datapath

2

IOE

Deserializer Bit Slip

LVDS Receiver

+

– rx_in

DOUT DIN

2

(LOAD_EN, diffioclk)

DOUT DIN diffioclk rx_outclock

LVDS Clock Domain

3 (LVDS_LOAD_EN,

LVDS_diffioclk, rx_outclock)

Fractional PLL rx_inclock / tx_inclock

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Data Realignment Block (Bit Slip)

Skew in the transmitted data along with skew added by the link causes channel-to-channel skew on the received serial data streams. To compensate for this channel-to-channel skew and establish the correct received word boundary at each channel, each receiver channel has a dedicated data realignment circuit that realigns the data by inserting bit latencies into the serial stream.

An optional

RX_CHANNEL_DATA_ALIGN port controls the bit insertion of each receiver independently controlled from the internal logic. The data slips one bit on the rising edge of

RX_CHANNEL_DATA_ALIGN

. The requirements for the

RX_CHANNEL_DATA_ALIGN signal include the following items:

• The minimum pulse width is one period of the parallel clock in the logic array.

• The minimum low time between pulses is one period of the parallel clock.

• The signal is an edge-triggered signal.

• The valid data is available two parallel clock cycles after the rising edge of

RX_CHANNEL_DATA_ALIGN

.

Figure 5-39: Data Realignment Timing

This figure shows receiver output (

RX_OUT

) after one bit slip pulse with the deserialization factor set to 4.

rx_inclock rx_in rx_outclock rx_channel_data_align rx_out

3 2 1 0 3 2 1 0 3 2 1 0

3210 321x xx21 0321

The data realignment circuit can have up to 11 bit-times of insertion before a rollover occurs. The programmable bit rollover point can be from 1 to 11 bit-times, independent of the deserialization factor.

Set the programmable bit rollover point equal to, or greater than, the deserialization factor—allowing enough depth in the word alignment circuit to slip through a full word. You can set the value of the bit rollover point using the MegaWizard Plug-In Manager. An optional status port,

RX_CDA_MAX

, is available to the FPGA fabric from each channel to indicate the reaching of the preset rollover point.

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Deserializer

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Figure 5-40: Receiver Data Realignment Rollover

This figure shows a preset value of four bit-times before rollover occurs. The rx_cda_max signal pulses for one rx_outclock cycle to indicate that rollover has occurred.

rx_inclock rx_channel_data_align rx_outclock rx_cda_max

Deserializer

You can statically set the deserialization factor to x4, x5, x6, x7, x8, x9, or x10 by using the Quartus II software.

You can bypass the deserializer in the Quartus II MegaWizard Plug-In Manager to support DDR (x2) or

SDR (x1) operations, as shown in the following figure.

Figure 5-41: Deserializer Bypass

rx_out

10

10

IOE supports SDR, DDR, or non-registered datapath

2

IOE

Deserializer Bit Slip

DOUT DIN DOUT DIN

FPGA

Fabric

diffioclk

2

(LOAD_EN, diffioclk) rx_outclock

LVDS Receiver

+

– rx_in

3 (LVDS_LOAD_EN,

LVDS_diffioclk, rx_outclock)

Fractional PLL rx_inclock / tx_inclock

Note: Disabled blocks and signals are grayed out

The IOE contains two data input registers that can operate in DDR or SDR mode. In DDR mode, rx_inclock clocks the IOE register. In SDR mode, data is directly passed through the IOE. In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.

Receiver Mode in Cyclone V Devices

The Cyclone V devices support the LVDS receiver mode.

LVDS Receiver Mode

Input serial data is registered at the rising edge of the serial

LVDS_diffioclk clock that is produced by the left and right PLLs.

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Receiver Clocking for Cyclone V Devices

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You can select the rising edge option with the Quartus II MegaWizard Plug-In Manager. The

LVDS_diffioclk clock that is generated by the left and right PLLs clocks the data realignment and deserializer blocks.

The following figure shows the LVDS datapath block diagram. In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.

Figure 5-42: Receiver Data Path in LVDS Mode

10 bits maxiumum data width rx_out

10

FPGA

Fabric

10

IOE supports SDR, DDR, or non-registered datapath

2

IOE

Deserializer Bit Slip

LVDS Receiver

+

– rx_in

DOUT DIN

2

(LOAD_EN, diffioclk)

DOUT DIN diffioclk rx_outclock

LVDS Clock Domain

3 (LVDS_LOAD_EN,

LVDS_diffioclk, rx_outclock)

Fractional PLL rx_inclock / tx_inclock

Note: All disabled blocks and signals are grayed out

Receiver Clocking for Cyclone V Devices

The fractional PLL receives the external clock input and generates different phases of the same clock.

The physical medium connecting the transmitter and receiver LVDS channels may introduce skew between the serial data and the source-synchronous clock. The instantaneous skew between each LVDS channel and the clock also varies with the jitter on the data and clock signals as seen by the receiver.

LVDS mode allows you to statically select the optimal phase between the source synchronous clock and the received serial data to compensate skew.

Related Information

Guideline: Use PLLs in Integer PLL Mode for LVDS

on page 5-12

Differential I/O Termination for Cyclone V Devices

The Cyclone V devices provide a 100 Ω, on-chip differential termination option on each differential receiver channel for LVDS standards. On-chip termination saves board space by eliminating the need to add external resistors on the board. You can enable on-chip termination in the Quartus II software Assignment Editor.

All I/O pins and dedicated clock input pins support on-chip differential termination, R

D

OCT.

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Figure 5-43: On-Chip Differential I/O Termination

LVDS

Transmitter

Source-Synchronous Timing Budget

Z

0

= 50 Ω

Differential Receiver with On-Chip 100 Ω

Termination

R

D

Z

0

= 50 Ω

5-69

Table 5-41: Quartus II Software Assignment Editor—On-Chip Differential Termination

This table lists the assignment name for on-chip differential termination in the Quartus II software Assignment

Editor.

Field Assignment

To

Assignment name

Value rx_in

Input Termination

Differential

Source-Synchronous Timing Budget

The topics in this section describe the timing budget, waveforms, and specifications for source-synchronous signaling in the Cyclone V device family.

The LVDS I/O standard enables high-speed transmission of data, resulting in better overall system performance. To take advantage of fast system performance, you must analyze the timing for these highspeed signals. Timing analysis for the differential block is different from traditional synchronous timing analysis techniques.

The basis of the source synchronous timing analysis is the skew between the data and the clock signals instead of the clock-to-output setup times. High-speed differential data transmission requires the use of timing parameters provided by IC vendors and is strongly influenced by board skew, cable skew, and clock jitter.

This section defines the source-synchronous differential data orientation timing parameters, the timing budget definitions for the Cyclone V device family, and how to use these timing parameters to determine the maximum performance of a design.

Differential Data Orientation

There is a set relationship between an external clock and the incoming data. For operations at 840 Mbps and a serialization factor of 10, the external clock is multiplied by 10. You can set phase-alignment in the

PLL to coincide with the sampling window of each data bit. The data is sampled on the falling edge of the multiplied clock.

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Differential I/O Bit Position

Figure 5-44: Bit Orientation in the Quartus II Software

This figure shows the data bit orientation of the x10 mode.

incloc k/outcloc k data in

MSB

9 8 7 6

10 LVDS Bits

5 4 3 2 1

LSB

0

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Differential I/O Bit Position

Data synchronization is necessary for successful data transmission at high frequencies.

The following figure shows the data bit orientation for a channel operation and is based on the following conditions:

• The serialization factor is equal to the clock multiplication factor.

• The phase alignment uses edge alignment.

• The operation is implemented in hard SERDES.

Figure 5-45: Bit-Order and Word Boundary for One Differential Channel

Transmitter Channel Operation (x8 Mode)

tx_outclock tx_out

Previous Cycle

X X X X X X X X

Current Cycle

7 6 5 4 3 2 1 0

MSB LSB

Receiver Channel Operation (x8 Mode)

Next Cycle

X X X X X X X X rx_inclock rx_in rx_outclock rx_out [7..0]

7 6 5 4 3

X X X X X X X X

2 1 0

X X X X X

X X X X X X X X

X X X X X X X X

X X X X 7 6 5 4

X X X X X X X X X X X

3 2 1 0 X X X X

Note: These waveforms are only functional waveforms and do not convey timing information

For other serialization factors, use the Quartus II software tools to find the bit position within the word.

Differential Bit Naming Conventions

The following table lists the conventions for differential bit naming for 18 differential channels. The MSB and LSB positions increase with the number of channels used in a system.

Table 5-42: Differential Bit Naming

This table lists the conventions for differential bit naming for 18 differential channels, and the bit positions after deserialization.

Internal 8-Bit Parallel Data

Receiver Channel Data Number

MSB Position LSB Position

1

2

3

4

7

15

23

31

0

8

16

24

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Receiver Channel Data Number

7

8

9

5

6

10

11

12

13

14

15

16

17

18

Transmitter Channel-to-Channel Skew

MSB Position

39

47

55

63

71

79

87

95

103

111

119

127

135

143

Internal 8-Bit Parallel Data

LSB Position

32

40

48

56

64

72

80

88

96

104

112

120

128

136

5-71

Transmitter Channel-to-Channel Skew

The receiver skew margin calculation uses the transmitter channel-to-channel skew (TCCS)—an important parameter based on the Cyclone V transmitter in a source-synchronous differential interface:

• TCCS is the difference between the fastest and slowest data output transitions, including the T

CO and clock skew.

variation

• For LVDS transmitters, the TimeQuest Timing Analyzer provides the TCCS value in the TCCS report

( report_TCCS

) in the Quartus II compilation report, which shows TCCS values for serial output ports.

• You can also get the TCCS value from the device datasheet.

Related Information

Cyclone V Device Datasheet

LVDS SERDES Transmitter/Receiver (ALTLVDS_TX and ALTLVDS_RX) Megafunction User Guide

Provides more information about the LVDS Transmitter/Receiver Package Skew Compensation report panel.

Receiver Skew Margin for LVDS Mode

In LVDS mode, use RSKM, TCCS, and sampling window (SW) specifications for high-speed sourcesynchronous differential signals in the receiver data path.

The following equation expresses the relationship between RSKM, TCCS, and SW.

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Receiver Skew Margin for LVDS Mode

Figure 5-46: RSKM Equation

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Conventions used for the equation:

• RSKM—the timing margin between the receiver’s clock input and the data input sampling window.

• Time unit interval (TUI)—time period of the serial data.

• SW—the period of time that the input data must be stable to ensure that data is successfully sampled by the LVDS receiver. The SW is a device property and varies with device speed grade.

• TCCS—the timing difference between the fastest and the slowest output edges, including t

CO variation and clock skew, across channels driven by the same PLL. The clock is included in the TCCS measurement.

You must calculate the RSKM value to decide whether the LVDS receiver can sample the data properly or not, given the data rate and device. A positive RSKM value indicates that the LVDS receiver can sample the data properly, whereas a negative RSKM indicates that it cannot sample the data properly.

The following figure shows the relationship between the RSKM, TCCS, and the SW of the receiver.

Figure 5-47: Differential High-Speed Timing Diagram and Timing Budget for LVDS Mode

Timing Diagram

External

Input Clock

Internal

Clock

Receiver

Input Data

TCCS

RSKM

Time Unit Interval (TUI)

SW

TCCS

RSKM

Timing Budget

External

Clock

Internal

Clock

Synchronization

Transmitter

Output Data

Receiver

Input Data

TCCS

RSKM t

SW

(min)

Bit n

Internal

Clock

Falling Edge

TUI t

SW

(max)

Bit n

Clock Placement

RSKM

TCCS

2

SW

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For LVDS receivers, the Quartus II software provides an RSKM report showing the SW, TUI, and RSKM values for non-DPA LVDS mode:

• You can generate the RSKM report by executing the report_RSKM command in the TimeQuest Timing

Analyzer. You can find the RSKM report in the Quartus II compilation report in the TimeQuest Timing

Analyzer section.

• To obtain the RSKM value, assign the input delay to the LVDS receiver through the constraints menu of the TimeQuest Timing Analyzer. The input delay is determined according to the data arrival time at the

LVDS receiver port, with respect to the reference clock.

• If you set the input delay in the settings parameters for the Set Input Delay option, set the clock name to the clock that reference the source synchronous clock that feeds the LVDS receiver.

• If you do not set any input delay in the TimeQuest Timing Analyzer, the receiver channel-to-channel skew defaults to zero.

• You can also directly set the input delay in a Synopsys Design Constraint file (.sdc) using the set_input_delay command.

Related Information

LVDS SERDES Transmitter/Receiver (ALTLVDS_TX and ALTLVDS_RX) Megafunction User Guide

Provides more information about the RSKM equation and calculation.

Quartus II TimeQuest Timing Analyzer chapter, Quartus II Development Software Handbook

Provides more information about .sdc commands and the TimeQuest Timing Analyzer.

Document Revision History

Date

January 2014

Version

2014.01.10

Changes

• Added 3.3 V V

CCIO input for 3.0 V LVTTL/3.0 V LVCMOS and 2.5 V

LVCMOS I/O standards.

• Added 3.3 V input signal for 2.5 V V

CCIO

MultiVolt I/O support.

in the table listing the

• Updated the statement about setting the phase of the clock in relation to data in the topic about transmitter clocking.

• Updated statements in several topics to clarify that each modular I/O bank can support multiple I/O standards that use the same voltage.

• Updated the guideline topic about using the same V

CCPD in the same V

CCPD group to improve clarity.

for I/O banks

• Added the optional PCI clamp diode to the figure showing the IOE structure.

• Changed all "SoC FPGA" to "SoC".

• Removed SSTL-125 from the list of supported I/O standards for the

HPS I/O.

• Added SSTL-15, SSTL-135, SSTL-125, HSUL-12, Differential SSTL-15,

Differential SSTL-135, Differential SSTL-125, and Differential HSUL-12 to the list of output termination settings for uncalibrated R

S

OCT.

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Document Revision History

Date

June 2013

June 2013

May 2013

Version

2013.06.21

2013.06.17

2013.05.06

CV-52005

2014.01.10

Changes

• Removed I/O banks 5A and 5B from Cyclone V SE A2 and A4, and

Cyclone V SX C2 and C4 in the table that lists the reference clock pin for I/O banks without dedicated reference clock pin. These devices do not have I/O bank 5B.

• Added the M301 and M383 packages to the modular I/O banks tables for Cyclone V GX C4 device.

• Added the number of true LVDS buffers for the M301 and M383 packages of the Cyclone V GX C4 device.

• Added a figure that shows the phase relationship for the external PLL interface signals.

• Clarified that you can only use R

D

• Removed all "preliminary" marks.

OCT if V

CCPD is 2.5 V.

• Added link to Knowledge Base article that clarifies about vertical migration (drop-in compatibility).

• Clarified that "internal PLL option" refers to the option in the ALTLVDS megafunction.

• Updated the topic about emulated LVDS buffers to clarify that you can use unutilized true LVDS input channels (instead of "buffers") as emulated LVDS output buffers.

Updated the figure about data realignment timing to correct the data pattern after a bit slip.

• Removed 3.3 V input signal for 2.5 V V

CCIO

MultiVolt I/O support.

in the table listing the

• Added a topic about LVDS I/O restrictions and differential pad placement rule.

• Updated the preliminary I/O counts per bank for the following packages:

• M301 packages of Cyclone V GX C5 and GT D5 devices.

• U324 package of Cyclone V GX C3 device.

• M383 packages of Cyclone V E A5, GX C5, and GT D5 devices.

• M484 packages of Cyclone V E A7, GX C7, and GT D7 devices.

• U484 packages of Cyclone V E A9, GX C9, and GT D9 devices.

• F1152 packages of Cyclone V GX C9 and GT D9 devices.

• Updated the preliminary LVDS channels counts for the M301 and M383 packages of Cyclone V E, GX, and GT devices.

• Added the preliminary LVDS channels counts for Cyclone V SE, SX, and ST devices.

• Updated the topic about LVDS input R

D ment for setting the V

CCIO to 2.5 V. R

D

OCT to remove the require-

OCT now requires only that the

V

CCPD is 2.5 V.

• Updated the topic about LVPECL termination to improve clarity.

• Moved all links in all topics to the Related Information section for easy reference.

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Date Version

Document Revision History

5-75

Changes

• Added link to the known document issues in the Knowledge Base.

• Updated the M386 package to M383.

• Updated the M383 package plan of the Cyclone V E device.

• Updated the GPIO count for the M301 package of the Cyclone V GX devices.

• Updated the HPS I/O counts for Cyclone V SE, SX, and ST devices.

• Updated the I/O vertical migration table.

• Corrected the note in the MultiVolt I/O interface topic.

• Updated the 3.3 V LVTTL programmable current strength values to add 16 mA current strength.

• Removed statements indicating that the clock tree network cannot cross over to different I/O regions.

• Removed references to rx_syncclock port because the port does not apply to Cyclone V devices.

• Added Bank 1A to the I/O banks location figure for Cyclone V E devices because it is now available for the Cyclone V E A2 and A4 devices.

• Added the M383 and M484 packages to the modular I/O banks tables for Cyclone V E devices, and added the U484 package for the Cyclone V

E A9 device.

• Added the U324, M301, M383, and M484 to the modular I/O banks tables for the Cyclone V GX devices, and added the U484 package for the Cyclone V GX C9 device.

• Added the M301, M383, and M484 to the modular I/O banks tables for the Cyclone V GT devices, and added the U484 package for the

Cyclone V GT D9 device.

• Added notes to clarify the HPS row and column I/O counts in the modular I/O banks tables for the Cyclone V SE, SX, and ST devices.

• Changed the color of the transceiver blocks in the high-speed differential

I/O location diagrams for clarity.

• Repaired the diagram for the example of calibrating multiple I/O banks with a shared OCT calibration block for readability.

• Added a topic about emulated LVDS buffers.

• Edited the topic about true LVDS buffers.

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Document Revision History

Date Version

December 2012 2012.12.28

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Changes

• Updated the tables listing the number of LVDS channels for the

Cyclone V devices:

• Removed the F256 package from Cyclone V GX C3 device.

• Removed the F324 package from the Cyclone V GX C4 and C5, and

Cyclone V GT D5 devices.

• Changed the F324 package of the Cyclone V GX C3 device to U324.

• Separated the Cyclone V GX C4 and C5 devices to different rows.

• Removed the F672 package from Cyclone V E A5.

• Added the M301 package to the Cyclone V GX C5 and Cyclone V

GT D5 devices.

• Added the M383 package to the Cyclone V E A2, A4 and A4,

Cyclone V GX C5, and Cyclone V GT D5 devices.

• Added the M484 package to the Cyclone V E A7, Cyclone V GX C7, and Cyclone V GT D7 devices.

• Added the U484 package to the Cyclone V E A9, Cyclone V GX C9, and Cyclone V GT D9 devices.

• Added the F484 package to the Cyclone V GX C9 and Cyclone V

GT D9 devices.

• Updated the data realignment timing figure to improve clarity.

• Updated the receiver data realignment rollover figure to improve clarity.

• Reorganized content and updated template.

• Added the I/O resources per package and I/O vertical migration sections for easy reference.

• Added the steps to verify pin migration compatibility using the

Quartus II software.

• Updated the I/O standards support table with HPS I/O information.

• Added topic about the reference clock pin restriction for LVDS application.

• Updated the pin placement guideline for using LVDS differential channels.

• Added guideline about using the external PLL mode.

• Rearranged the I/O banks groups tables for easier reference.

• Removed statements that imply that V

REF

I/Os.

pins can be used as normal

• Updated the 3.3 V LVTTL programmable current strength values.

• Restructured the information in the topic about I/O buffers and registers to improve clarity and for faster reference.

• Added HPS information to the topic on programmable IOE features.

• Rearranged the tables about on-chip I/O termination for clarity and topic-based reference.

• Updated the high-speed differential I/O locations diagram for

Cyclone V GX, SX, and ST devices.

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Date

June 2012

February 2012

November 2011

October 2011

Version

2.0

1.2

1.1

1.0

Document Revision History

5-77

Changes

• Removed statements about LVDS SERDES being available on top and bottom banks only.

• Removed the topic about LVDS direct loopback mode.

• Updated the true LVDS buffers count for Cyclone V E, GX, and GT devices.

• Added the RSKM equation, description, and high-speed timing diagram.

Updated for the Quartus II software v12.0 release:

• Restructured chapter.

• Added “Design Considerations”, “VCCIO Restriction”, “LVDS

Channels”, “Modular I/O Banks”, and “OCT Calibration Block” sections.

• Added Figure 5–3, Figure 5–4, Figure 5–5, Figure 5–6, and Figure 5–27.

• Updated Table 5–1, Table 5–8, and Table 5–10.

• Updated Figure 5–22 with emulated LVDS with external single resistor.

• Updated Table 5–1, Table 5–2, Table 5–8, and Table 5–10.

• Updated “I/O Banks” on page 5–8.

• Minor text edits.

• Updated Table 5–2.

• Updated Figure 5–3, Figure 5–4.

• Updated “Sharing an OCT Calibration Block on Multiple I/O Banks”,

“High-Speed Differential I/O Interfaces”, and “Fractional PLLs and

Cyclone V Clocking” sections.

Initial release.

I/O Features in Cyclone V Devices

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The Cyclone V devices provide an efficient architecture that allows you to fit wide external memory interfaces to support a high level of system bandwidth within the small modular I/O bank structure. The I/Os are designed to provide high-performance support for existing and emerging external memory standards.

Table 6-1: Supported External Memory Standards in Cyclone V Devices

Memory Standard

DDR3 SDRAM

DDR2 SDRAM

LPDDR2 SDRAM

Hard Memory Controller

Full rate

Full rate

Full rate

Soft Memory Controller

Half rate

Half rate

Half rate

Related Information

External Memory Interface Spec Estimator

For the latest information and to estimate the external memory system performance specification, use

Altera's External Memory Interface Spec Estimator tool.

External Memory Interface Handbook

Provides more information about the memory types supported, board design guidelines, timing analysis, simulation, and debugging information.

Cyclone V Device Handbook: Known Issues

Lists the planned updates to the

Cyclone V Device Handbook

chapters.

6

©

2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with

Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO

9001:2008

Registered www.altera.com

101 Innovation Drive, San Jose, CA 95134

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External Memory Performance

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External Memory Performance

Table 6-2: External Memory Interface Performance in Cyclone V Devices

The maximum and minimum operating frequencies depend on the memory interface standards and the supported delay-locked loop (DLL) frequency listed in the device datasheet.

Interface

Voltage

(V)

Maximum Frequency (MHz)

Hard Controller Soft Controller

Minimum Frequency (MHz)

DDR3 SDRAM

DDR2 SDRAM

LPDDR2 SDRAM

1.5

1.35

1.8

1.2

400

400

400

333

303

303

300

300

303

303

167

167

Related Information

External Memory Interface Spec Estimator

For the latest information and to estimate the external memory system performance specification, use

Altera's External Memory Interface Spec Estimator tool.

Cyclone V Device Datasheet

HPS External Memory Performance

Table 6-3: HPS External Memory Interface Performance

The hard processor system (HPS) is available in Cyclone V SoC devices only.

Interface Voltage (V) HPS Hard Controller (MHz)

DDR3 SDRAM

DDR2 SDRAM

LPDDR2 SDRAM

1.5

1.35

1.8

1.2

400

400

400

333

Related Information

External Memory Interface Spec Estimator

For the latest information and to estimate the external memory system performance specification, use Altera's

External Memory Interface Spec Estimator tool.

Memory Interface Pin Support in Cyclone V Devices

In the Cyclone V devices, the memory interface circuitry is available in every I/O bank that does not support transceivers. The devices offer differential input buffers for differential read-data strobe and clock operations.

The memory clock pins are generated with double data rate input/output (DDRIO) registers.

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Guideline: Using DQ/DQS Pins

6-3

Related Information

Planning Pin and FPGA Resources chapter, External Memory Interface Handbook

Provides more information about which pins to use for memory clock pins and pin location requirements.

Guideline: Using DQ/DQS Pins

The following list provides guidelines on using the DQ/DQS pins:

• The devices support DQ and DQS signals with DQ bus modes of x8 or x16. Cyclone V devices do not support the x4 bus mode.

• You can use the DQSn pins that are not used for clocking as DQ pins.

• If you do not use the DQ/DQS pins for memory interfacing, you can use these pins as user I/Os. However, unused HPS DQ/DQS pins on the Cyclone V SX and ST devices cannot be used as user I/Os.

• Some specific DQ pins can also be used as RZQ pins. If you need extra RZQ pins, you can use these the

DQ pins as RZQ pins instead.

Note:

For the x8 or x16 DQ/DQS groups whose members are used as RZQ pins, Altera recommends that you assign the DQ and DQS pins manually. Otherwise, the Quartus II software might not be able to place the DQ and DQS pins, resulting in a “no-fit” error.

Reading the Pin Table

For the maximum number of DQ pins and the exact number per group for a particular Cyclone V device, refer to the relevant device pin table.

In the pin tables, the DQS and DQSn pins denote the differential data strobe/clock pin pairs. The DQS and

DQSn pins are listed respectively in the Cyclone V pin tables as

DQSXY and

DQSnXY

.

X

indicates the DQ/DQS grouping number and

Y

indicates whether the group is located on the top (T), bottom (B), left (L), or right

(R) side of the device.

Note:

The F484 package of the Cyclone V E A9, GX C9, and GT D9 devices can only support a 24 bit hard memory controller on the top side using the

T_DQ_0 to

T_DQ_23 pin assignments. Even though the

F484 package pin tables of these devices list

T_DQ_32 to

T_DQ_39 in the "HMC Pin Assignment" columns, you cannot use these pin assignments for the hard memory controller.

Related Information

Hard Memory Controller Width for Cyclone V E

on page 6-35

Hard Memory Controller Width for Cyclone V GX

on page 6-36

Hard Memory Controller Width for Cyclone V GT

on page 6-37

Cyclone V Device Pin-Out Files

Download the relevant pin tables from this web page.

DQ/DQS Bus Mode Pins for Cyclone V Devices

The following table lists the pin support per DQ/DQS bus mode, including the DQS and DQSn pin pairs.

The maximum number of data pins per group listed in the table may vary according to the following conditions:

• Single-ended DQS signaling—the maximum number of DQ pins includes data mask connected to the

DQS bus network.

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DQ/DQS Bus Mode Pins for Cyclone V Devices

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• Differential or complementary DQS signaling—the maximum number of data pins per group decreases by one.

• DDR3 and DDR2 interfaces—each x8 group of pins require one DQS pin. You may also require one

DQSn pin and one DM pin. This further reduces the total number of data pins available.

Table 6-4: DQ/DQS Bus Mode Pins for Cyclone V Devices

x8 x16

Mode DQSn Support

Yes

Yes

Data Mask

(Optional)

Yes

Yes

Maximum Data Pins per Group

11

23

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DQ/DQS Groups in Cyclone V E

6-5

Table 6-5: Number of DQ/DQS Groups Per Side in Cyclone V E Devices

This table lists the DQ/DQS groups for the soft memory controller. For the hard memory controller, you can get the

DQ/DQS groups from the pin table of the specific device. The numbers are preliminary before the devices are available.

Member Code

A2

A4

A5

Package

256-pin FineLine BGA

324-pin Ultra FineLine BGA

383-pin Micro FineLine BGA

484-pin Ultra FineLine BGA

484-pin FineLine BGA

383-pin Micro FineLine BGA

484-pin Ultra FineLine BGA

484-pin FineLine BGA

x16

1

2

0

1

0

0

1

0

0

0

1

0

0

0

1

1

0

0

0

1

0

0

0

0

0

0

0

0

0

x8

6

7

2

6

1

4

5

3

1

2

6

4

1

2

6

5

2

1

4

5

2

2

4

4

2

3

3

2

1

Side

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Left

Right

Bottom

Top

Left

Right

Bottom

Top

Top

Left

Right

Bottom

Top

Left

Right

Bottom

Top

Left

Right

Bottom

Top

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DQ/DQS Groups in Cyclone V E

Member Code Package

A7

A9

484-pin Micro FineLine BGA

484-pin Ultra FineLine BGA

484-pin FineLine BGA

672-pin FineLine BGA

896-pin FineLine BGA

484-pin Ultra FineLine BGA

484-pin FineLine BGA

672-pin FineLine BGA

896-pin FineLine BGA

Related Information

Cyclone V Device Pin-Out Files

Download the relevant pin tables from this web page.

Side

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

x16

0

1

2

0

1

0

1

1

2

3

3

3

2

3

3

3

0

1

2

0

1

1

1

2

1

0

1

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x8

2

6

7

6

5

4

6

5

8

10

10

10

8

10

10

10

2

6

7

6

5

4

6

7

5

4

6

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DQ/DQS Groups in Cyclone V GX

6-7

Table 6-6: Number of DQ/DQS Groups Per Side in Cyclone V GX Devices

This table lists the DQ/DQS groups for the soft memory controller. For the hard memory controller, you can get the

DQ/DQS groups from the pin table of the specific device. The numbers are preliminary before the devices are available.

Member Code

C3

C4

C5

Package

324-pin Ultra FineLine BGA

484-pin Ultra FineLine BGA

484-pin FineLine BGA

301-pin Micro FineLine BGA

383-pin Micro FineLine BGA

484-pin Ultra FineLine BGA

484-pin FineLine BGA

672-pin FineLine BGA

x16

0

1

2

0

0

0

0

1

1

2

2

2

TBD

TBD

TBD

TBD

1

1

0

1

0

1

0

0

0

x8

3

6

7

2

4

1

4

5

6

7

6

8

TBD

TBD

TBD

TBD

6

5

2

6

4

5

2

3

2

Side

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Left

Right

Bottom

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DQ/DQS Groups in Cyclone V GX

Member Code Package

C7

C9

484-pin Micro FineLine BGA

484-pin Ultra FineLine BGA

484-pin FineLine BGA

672-pin FineLine BGA

896-pin FineLine BGA

484-pin Ultra FineLine BGA

484-pin FineLine BGA

672-pin FineLine BGA

896-pin FineLine BGA

1152-pin FineLine BGA

Related Information

Cyclone V Device Pin-Out Files

Download the relevant pin tables from this web page.

Side

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

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12

11

12

8

10

10

10

2

6

7

6

5

4

6

5

8

10

10

10

2

6

7

6

5

4

6

7

5

4

6

x16

4

4

4

2

3

3

3

0

1

2

0

1

0

1

1

2

3

3

3

0

1

2

0

1

1

1

2

1

0

1

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DQ/DQS Groups in Cyclone V GT

DQ/DQS Groups in Cyclone V GT

6-9

Table 6-7: Number of DQ/DQS Groups Per Side in Cyclone V GT Devices

This table lists the DQ/DQS groups for the soft memory controller. For the hard memory controller, you can get the

DQ/DQS groups from the pin table of the specific device. The numbers are preliminary before the devices are available.

Member Code

D5

Package

301-pin Micro FineLine BGA

383-pin Micro FineLine BGA

484-pin Ultra FineLine BGA

484-pin FineLine BGA

672-pin FineLine BGA

Side

Top

Left

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

x16

1

2

0

1

0

0

1

0

2

2

2

TBD

TBD

TBD

TBD

0

x8

6

7

2

6

1

4

5

3

7

6

8

TBD

TBD

TBD

TBD

4

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DQ/DQS Groups in Cyclone V GT

Member Code Package

D7

D9

484-pin Micro FineLine BGA

484-pin Ultra FineLine BGA

484-pin FineLine BGA

672-pin FineLine BGA

896-pin FineLine BGA

484-pin Ultra FineLine BGA

484-pin FineLine BGA

672-pin FineLine BGA

896-pin FineLine BGA

1152-pin FineLine BGA

Related Information

Cyclone V Device Pin-Out Files

Download the relevant pin tables from this web page.

Side

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

Right

Bottom

Top

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12

11

12

8

10

10

10

2

6

7

6

5

4

6

5

8

10

10

10

2

6

7

6

5

4

6

7

5

4

6

x16

4

4

4

2

3

3

3

0

1

2

0

1

0

1

1

2

3

3

3

0

1

2

0

1

1

1

2

1

0

1

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DQ/DQS Groups in Cyclone V SE

DQ/DQS Groups in Cyclone V SE

6-11

Table 6-8: Number of DQ/DQS Groups Per Side in Cyclone V SE Devices

This table lists the DQ/DQS groups for the soft memory controller. For the hard memory controller, you can get the

DQ/DQS groups from the pin table of the specific device. The numbers are preliminary before the devices are available.

Member Code

A2

A4

A5

A6

Package

484-pin Ultra FineLine BGA

672-pin Ultra FineLine BGA

484-pin Ultra FineLine BGA

672-pin Ultra FineLine BGA

896-pin FineLine BGA

Side

Right

Bottom

Right

Bottom

Right

Bottom

Right

Bottom

Top

Right

Bottom

x8

2

1

8

5

3

10

1

8

1

1

2

x16

0

0

2

2

0

3

0

2

0

0

0

DQ/DQS Groups in Cyclone V SX

Table 6-9: Number of DQ/DQS Groups Per Side in Cyclone V SX Devices

This table lists the DQ/DQS groups for the soft memory controller. For the hard memory controller, you can get the

DQ/DQS groups from the pin table of the specific device. The numbers are preliminary before the devices are available.

Member Code

C2

C4

C5

C6

Package

672-pin Ultra FineLine BGA

672-pin Ultra FineLine BGA

896-pin FineLine BGA

Side

Right

Bottom

Right

Bottom

Top

Right

Bottom

x8

1

8

5

3

10

1

8

x16

0

2

2

0

3

0

2

Related Information

Cyclone V Device Pin-Out Files

Download the relevant pin tables from this web page.

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DQ/DQS Groups in Cyclone V ST

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Table 6-10: Number of DQ/DQS Groups Per Side in Cyclone V ST Devices

This table lists the DQ/DQS groups for the soft memory controller. For the hard memory controller, you can get the

DQ/DQS groups from the pin table of the specific device. The numbers are preliminary before the devices are available.

Member Code

D5

D6

Package

896-pin FineLine BGA

Side

Top

Right

Bottom

x8

5

3

10

x16

2

0

3

Related Information

Cyclone V Device Pin-Out Files

Download the relevant pin tables from this web page.

External Memory Interface Features in Cyclone V Devices

The Cyclone V I/O elements (IOE) provide built-in functionality required for a rapid and robust implementation of external memory interfacing.

The following device features are available for external memory interfaces:

• DQS phase-shift circuitry

• PHY Clock (PHYCLK) networks

• DQS logic block

• Dynamic on-chip termination (OCT) control

• IOE registers

• Delay chains

• Hard memory controllers

UniPHY IP

The high-performance memory interface solution includes the self-calibrating UniPHY IP that is optimized to take advantage of the Cyclone V I/O structure and the Quartus II software TimeQuest Timing Analyzer.

The UniPHY IP helps set up the physical interface (PHY) best suited for your system. This provides the total solution for the highest reliable frequency of operation across process, voltage, and temperature (PVT) variations.

The UniPHY IP instantiates a PLL to generate related clocks for the memory interface. The UniPHY IP can also dynamically choose the number of delay chains that are required for the system. The amount of delay is equal to the sum of the intrinsic delay of the delay element and the product of the number of delay steps and the value of the delay steps.

The UniPHY IP and the Altera memory controller MegaCore

® functions can run at half the I/O interface frequency of the memory devices, allowing better timing management in high-speed memory interfaces.

The Cyclone V devices contain built-in circuitry in the IOE to convert data from full rate (the I/O frequency) to half rate (the controller frequency) and vice versa.

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External Memory Interface Datapath

Related Information

Reference Material volume, External Memory Interface Handbook

Provides more information about the UniPHY IP.

6-13

External Memory Interface Datapath

The following figure shows an overview of the memory interface datapath that uses the Cyclone V I/O elements. In the figure, the DQ/DQS read and write signals may be bidirectional or unidirectional, depending on the memory standard. If the signal is bidirectional, it is active during read and write operations. You can bypass each register block.

Figure 6-1: External Memory Interface Datapath Overview for Cyclone V Devices

FPGA

Postamble Clock

DLL

Postamble Enable

DQS Delay

Chain

DQS Postamble

Circuitry

DQS Enable

Control

Circuit

DQS

Enable

Circuit

Memory

DQS (Read)

4n or 2n

2n

Clock

Management and Reset

Full-Rate Clock

DQ Write Clock

Half-Rate Clock

DQS Write Clock

4n

4

Read FIFO

Half Data

Rate

Output

Registers

Half Data

Rate

Output

Registers

2n

2

DDR Input

Registers

DDR Output and Output

Enable

Registers

DDR Output and Output

Enable

Registers n n

DQ (Read)

DQ (Write)

DQS (Write)

Note: There are slight block differences for different memory interface standards. The shaded blocks are part of the I/O elements.

DQS Phase-Shift Circuitry

The Cyclone V DLL provides phase shift to the DQS pins on read transactions if the DQS pins are acting as input clocks or strobes to the FPGA.

The following figures show how the DLLs are connected to the DQS pins in the various Cyclone V variants.

The reference clock for each DLL may come from adjacent PLLs.

Note:

The following figures show all possible connections for each device. For available pins and connections in each device package, refer to the device pin-out files.

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DQS Phase-Shift Circuitry

Figure 6-2: DQS Pins and DLLs in Cyclone V E (A2 and A4) Devices

DQS

Pin

DQS

Pin

DLL

Reference

Clock

Δt Δt

DQS Logic

Blocks

DQS

Pin

Δt

DQS

Pin

Δt

DLL

Reference

Clock

DLL

DQS

Pin

DQS Logic

Blocks

Δt to

IOE

DQS

Pin

Δt to

IOE to

IOE to

IOE to

IOE to

IOE

DLL to

IOE

DQS Logic

Blocks

Δt to

IOE

Δt

DQS

Pin

DQS

Pin

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DQS

Pin

DQS

Pin

Δt

Δt to

IOE to

IOE to

IOE to

IOE

Δt

Δt

DQS

Pin

DQS

Pin

DLL to

IOE to

IOE to

IOE to

IOE

DLL

DLL

Reference

Clock

Δt Δt

DQS

Pin

DQS

Pin

DQS Logic

Blocks

Δt

DQS

Pin

Δt

DLL

Reference

Clock

DQS

Pin

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Figure 6-3: DQS Pins and DLLs in Cyclone V GX (C3) Devices

DQS

Pin

DQS

Pin

DLL

Reference

Clock

Δt Δt

DQS Logic

Blocks

DQS

Pin

Δt

DQS

Pin

Δt

DLL

Reference

Clock

DQS Phase-Shift Circuitry

6-15

DLL to

IOE to

IOE to

IOE to

IOE

DLL to

IOE

DQS Logic

Blocks

Δt to

IOE

Δt

DQS

Pin

DQS

Pin to IOE to IOE

Δt Δt

DQS

Pin

DQS

Pin to

IOE to

IOE

Δt

Δt

DQS

Pin

DQS

Pin to IOE to IOE

Δt Δt

DQS

Pin

DQS

Pin

DLL

DLL

Reference

Clock

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DQS Phase-Shift Circuitry

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Figure 6-4: DQS Pins and DLLs in Cyclone V E (A5, A7, and A9), GX (C4, C5, C7, and C9), GT (D5, D7, and

D9) Devices

DQS

Pin

DQS

Pin

DQS

Pin

DLL

Reference

Clock

Δt Δt

DQS Logic

Blocks

DQS

Pin

Δt Δt

DLL

Reference

Clock

DLL to

IOE to

IOE to

IOE to

IOE

DLL to

IOE

DQS Logic

Blocks

Δt to

IOE

Δt

DQS

Pin

DQS

Pin to

IOE to

IOE

Δt

Δt

DQS

Pin

DQS

Pin

DLL to

IOE to

IOE to

IOE to

IOE

DLL

DLL

Reference

Clock

Δt Δt

DQS

Pin

DQS

Pin

DQS Logic

Blocks

Δt

DQS

Pin

Δt

DQS

Pin

DLL

Reference

Clock

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DQS Phase-Shift Circuitry

Figure 6-5: DQS Pins and DLLs in Cyclone V SE (A2, A4, A5, and A6) Devices

DQS

Pin

DQS

Pin

DLL

Reference

Clock

Δt Δt

6-17

DLL to IOE to IOE

HPS I/O DLL

HPS Block

HPS

PLL to IOE to IOE

Δt

DQS Logic

Blocks

DQS

Pin

Δt

DQS

Pin to

IOE to

IOE

Δt

DQS

Pin

Δt

DQS Logic

Blocks

DQS

Pin to

IOE to

IOE

DLL

DLL to

IOE to

IOE

DLL

Reference

Clock

Δt Δt

DQS

Pin

DQS

Pin

DQS Logic

Blocks

Δt

DQS

Pin

Δt

DQS

Pin

DLL

Reference

Clock

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Delay-Locked Loop

Figure 6-6: DQS Pins and DLLs in Cyclone V SX (C2, C4, C5, and C6) and ST (D5 and D6) Devices

DQS

Pin

DQS

Pin

DLL

Reference

Clock

Δt Δt

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DLL to IOE to IOE

HPS I/O DLL

HPS Block

HPS

PLL to IOE to IOE

Δt

DQS Logic

Blocks

DQS

Pin

Δt

DQS

Pin to

IOE to

IOE

Δt

DQS

Pin

Δt

DQS Logic

Blocks

DQS

Pin to

IOE to

IOE

DLL

DLL to

IOE to

IOE

DLL

Reference

Clock

Δt Δt

DQS

Pin

DQS

Pin

DQS Logic

Blocks

Δt

DQS

Pin

Δt

DQS

Pin

DLL

Reference

Clock

Related Information

Cyclone V Device Pin-Out Files

Download the relevant pin tables from this web page.

Delay-Locked Loop

The delay-locked loop (DLL) uses a frequency reference to dynamically generate control signals for the delay chains in each of the DQS pins, allowing the delay to compensate for process, voltage, and temperature

(PVT) variations. The DQS delay settings are gray-coded to reduce jitter if the DLL updates the settings.

There are a maximum of four DLLs, located in each corner of the Cyclone V devices. You can clock each

DLL using different frequencies.

The DLLs can access the two adjacent sides from its location in the device. You can have two different interfaces with the same frequency on the two sides adjacent to a DLL, where the DLL controls the DQS delay settings for both interfaces.

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DLL Reference Clock Input for Cyclone V Devices

6-19

I/O banks between two DLLs have the flexibility to create multiple frequencies and multiple-type interfaces.

These banks can use settings from either or both adjacent DLLs. For example,

DQS1R can get its phase-shift settings from

DLL_TR

, while DQS2R can get its phase-shift settings from

DLL_BR

.

The reference clock for each DLL may come from the PLL output clocks or clock input pins.

Note:

If you have a dedicated PLL that only generates the DLL input reference clock, set the PLL mode to

Direct Compensation to achieve better performance (or the Quartus II software automatically changes it). Because the PLL does not use any other outputs, it does not have to compensate for any clock paths.

DLL Reference Clock Input for Cyclone V Devices

Table 6-11: DLL Reference Clock Input from PLLs for Cyclone V E (A2, A4, A5, A7, and A9), GX (C4, C5, C7, and

C9), and GT (D5, D7, and D9) Devices—Preliminary

DLL_TL

DLL_TR

DLL_BL

DLL_BR

DLL

Top Left

pllout

Top Right

— pllout

PLL

Bottom Left

— pllout

Bottom Right

— pllout

Table 6-12: DLL Reference Clock Input from PLLs for Cyclone V GX (C3) Device—Preliminary

DLL_TL

DLL_TR

DLL_BL

DLL_BR

DLL

Top Left

pllout

Top Right

— pllout

PLL

Bottom Left

Bottom Right

— pllout

Table 6-13: DLL Reference Clock Input from PLLs for Cyclone V SE A2, A4, A5, and A6 Devices, Cyclone V SX

C2, C4, C5, and C6 Devices, and Cyclone V ST D5 and D6 Devices—Preliminary

DLL_TL

DLL_TR

DLL_BL

DLL

Top Left

pllout

Top Right

PLL

Bottom Left

— pllout

Bottom Right

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DLL Phase-Shift

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DLL_BR

DLL

Top Left

Top Right

PLL

Bottom Left

Bottom Right

pllout

DLL Phase-Shift

The DLL can shift the incoming DQS signals by 0° or 90°. The shifted DQS signal is then used as the clock for the DQ IOE input registers, depending on the number of DQS delay chains used.

All DQS pins referenced to the same DLL, can have their input signal phase shifted by a different degree amount but all must be referenced at one particular frequency. However, not all phase-shift combinations are supported. The phase shifts on the DQS pins referenced by the same DLL must all be a multiple of 90°.

The 7-bit DQS delay settings from the DLL vary with PVT to implement the phase-shift delay. For example, with a 0° shift, the DQS signal bypasses both the DLL and DQS logic blocks. The Quartus II software automatically sets the DQ input delay chains, so that the skew between the DQ and DQS pins at the DQ IOE registers is negligible if a 0° shift is implemented. You can feed the DQS delay settings to the DQS logic block and logic array.

The shifted DQS signal goes to the DQS bus to clock the IOE input registers of the DQ pins. The signal can also go into the logic array for resynchronization if you are not using IOE read FIFO for resynchronization.

For Cyclone V SoC devices, you can feed the hard processor system (HPS) DQS delay settings to the HPS

DQS logic block only.

Figure 6-7: Simplified Diagram of the DQS Phase-Shift Circuitry

This figure shows a simple block diagram of the DLL. All features of the DQS phase-shift circuitry are accessible from the UniPHY megafunction in the Quartus II software.

DLL

Input Reference

Clock clk aload upndnin

Phase

Comparator upndninclkena

Up/Down

Counter

DQS delay settings can go to the logic array and DQS logic block

This clock can come from a PLL output clock or an input clock pin

Delay Chains

7 delayctrlout [6:0]

7

DQS Delay

Settings

7 dqsupdate

The input reference clock goes into the DLL to a chain of up to eight delay elements. The phase comparator compares the signal coming out of the end of the delay chain block to the input reference clock. The phase comparator then issues the upndn signal to the Gray-code counter. This signal increments or decrements a

7-bit delay setting (DQS delay settings) that increases or decreases the delay through the delay element chain to bring the input reference clock and the signals coming out of the delay element chain in phase.

The DLL can be reset from either the logic array or a user I/O pin. Each time the DLL is reset, you must wait for 2,560 clock cycles for the DLL to lock before you can capture the data properly. The DLL phase comparator requires 2,560 clock cycles to lock and calculate the correct input clock period.

For the frequency range of each DLL frequency mode, refer to the device datasheet.

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PHY Clock (PHYCLK) Networks

6-21

Related Information

Cyclone V Device Datasheet

PHY Clock (PHYCLK) Networks

The PHYCLK network is a dedicated high-speed, low-skew balanced clock tree designed for a highperformance external memory interface.

The top and bottom sides of the Cyclone V devices have up to four PHYCLK networks each. There are up to two PHYCLK networks on the left and right side I/O banks. Each PHYCLK network spans across one

I/O bank and is driven by one of the PLLs located adjacent to the I/O bank.

The following figures show the PHYCLK networks available in the Cyclone V devices.

Figure 6-8: PHYCLK Networks in Cyclone V E A2 and A4 Devices

Left

PLL

I/O Bank 8

Sub-Bank Sub-Bank

I/O Bank 7

Sub-Bank Sub-Bank

PHYCLK Networks

Right

PLL

FPGA Device

Left

PLL

Sub-Bank Sub-Bank

I/O Bank 3

PHYCLK Networks

Sub-Bank Sub-Bank

I/O Bank 4

Right

PLL

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PHY Clock (PHYCLK) Networks

Figure 6-9: PHYCLK Networks in Cyclone V GX C3 Devices

Left

PLL

I/O Bank 8

Sub-Bank Sub-Bank

I/O Bank 7

Sub-Bank Sub-Bank

PHYCLK Networks

Right

PLL

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FPGA Device

Sub-Bank Sub-Bank

I/O Bank 3

PHYCLK Networks

Sub-Bank Sub-Bank

I/O Bank 4

Right

PLL

Figure 6-10: PHYCLK Networks in Cyclone V E A7, A5, and A9 Devices, Cyclone V GX C4, C5, C7, and C9

Devices, and Cyclone V GT D5, D7, and D9 Devices

Left

PLL

I/O Bank 8

Sub-Bank Sub-Bank

I/O Bank 7

Sub-Bank Sub-Bank

PHYCLK Networks

Right

PLL

Altera Corporation

FPGA Device

Left

PLL

Sub-Bank Sub-Bank

I/O Bank 3

PHYCLK Networks

Sub-Bank Sub-Bank

I/O Bank 4

Right

PLL

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PHY Clock (PHYCLK) Networks

Figure 6-11: PHYCLK Networks in Cyclone V SE A2, A4, A5, and A6 Devices

Left

PLL

I/O Bank 8

Sub-Bank Sub-Bank

PHYCLK Networks

I/O Bank 7

Sub-Bank Sub-Bank

HPS

PLL

HPS Block

6-23

FPGA Device

Left

PLL

Sub-Bank Sub-Bank

I/O Bank 3

PHYCLK Networks

Sub-Bank Sub-Bank

I/O Bank 4

Right

PLL

Figure 6-12: PHYCLK Networks in Cyclone V SX C2, C4, C5, and C6 Devices, and Cyclone V ST D5 and D6

Devices

Left

PLL

I/O Bank 8

Sub-Bank Sub-Bank

PHYCLK Networks

I/O Bank 7

Sub-Bank Sub-Bank

HPS

PLL

HPS Block

FPGA Device

Left

PLL

Sub-Bank Sub-Bank

I/O Bank 3

PHYCLK Networks

Sub-Bank Sub-Bank

I/O Bank 4

Right

PLL

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DQS Logic Block

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DQS Logic Block

Each DQS/CQ/CQn/QK# pin is connected to a separate DQS logic block, which consists of the update enable circuitry, DQS delay chains, and DQS postamble circuitry.

The following figure shows the DQS logic block.

Figure 6-13: DQS Logic Block in Cyclone V Devices

DQS Postamble Circuitry

DQS Pin dqsin

DQS Enable

D Q

The dqsenable signal can also come from the

FPGA fabric dqsdisablen

DQS Enable Control Circuit

Postamble

Enable dqsenablein

D Q D Q

0

1

D Q

PRE dqsenable dqsenableout

0

1

2

<delay dqs enable>

D Q zerophaseclk

(Postamble clock) enaphasetransferreg levelingclk

(Read-leveled postamble clock)

Applicable only if the DQS delay settings come from a side with two DLLs

Bypass

DQS Delay Chain

dqsin

This clock can come from a PLL output clock or an input clock pin

7

7

1

0 dqsbusout

<dqs delay chain bypass>

7 delayctrlin [6:0]

7

7 delayctrlin [6:0]

7

0

1

2

D Q

7

1

0

7 dqsupdateen

Input Reference

Clock

Update

Enable

Circuitry

Update Enable Circuitry

The update enable circuitry enables the registers to allow enough time for the DQS delay settings to travel from the DQS phase-shift circuitry or core logic to all the DQS logic blocks before the next change.

Both the DQS delay settings and the phase-offset settings pass through a register before going into the DQS delay chains. The registers are controlled by the update enable circuitry to allow enough time for any changes in the DQS delay setting bits to arrive at all the delay elements, which allows them to be adjusted at the same time.

The circuitry uses the input reference clock or a user clock from the core to generate the update enable output. The UniPHY intellectual property (IP) uses this circuit by default.

Figure 6-14: DQS Update Enable Waveform

This figure shows an example waveform of the update enable circuitry output.

DLL Counter Update

(Every 8 cycles)

DLL Counter Update

(Every 8 cycles)

System Clock

DQS Delay Settings

Updated every 8 cycles

Update Enable

Circuitry Output

7 bit

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DQS Delay Chain

DQS Delay Chain

6-25

DQS delay chains consist of a set of variable delay elements to allow the input DQS signals to be shifted by the amount specified by the DQS phase-shift circuitry or the logic array.

There are two delay elements in the DQS delay chain that have the same characteristics:

• Delay elements in the DQS logic block

• Delay elements in the DLL

The DQS pin is shifted by the DQS delay settings.

The number of delay chains required is transparent because the UniPHY IP automatically sets it when you choose the operating frequency.

In the Cyclone V SE, SX, and ST devices, the DQS delay chain is controlled by the DQS phase-shift circuitry only.

Related Information

ALTDQ_DQS2 Megafunction User Guide

Provides more information about programming the delay chains.

Delay Chains

on page 6-28

DQS Postamble Circuitry

There are preamble and postamble specifications for both read and write operations in DDR3 and DDR2

SDRAM. The DQS postamble circuitry ensures that data is not lost if there is noise on the DQS line during the end of a read operation that occurs while DQS is in a postamble state.

The Cyclone V devices contain dedicated postamble registers that you can control to ground the shifted

DQS signal that is used to clock the DQ input registers at the end of a read operation. This function ensures that any glitches on the DQS input signal during the end of a read operation and occurring while DQS is in a postamble state do not affect the DQ IOE registers.

• For preamble state, the DQS is low, just after a high-impedance state.

• For postamble state, the DQS is low, just before it returns to a high-impedance state.

For external memory interfaces that use a bidirectional read strobe (DDR3 and DDR2 SDRAM), the DQS signal is low before going to or coming from a high-impedance state.

Half Data Rate Block

The Cyclone V devices contain a half data rate (HDR) block in the postamble enable circuitry.

The HDR block is clocked by the half-rate resynchronization clock, which is the output of the I/O clock divider circuit. There is an AND gate after the postamble register outputs to avoid postamble glitches from a previous read burst on a non-consecutive read burst. This scheme allows half-a-clock cycle latency for dqsenable assertion and zero latency for dqsenable deassertion.

Using the HDR block as the first stage capture register in the postamble enable circuitry block is optional.

Altera recommends using these registers if the controller is running at half the frequency of the I/Os.

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Dynamic OCT Control

Figure 6-15: Avoiding Glitch on a Non-Consecutive Read Burst Waveform

This figure shows how to avoid postamble glitches using the HDR block.

Postamble

Postamble glitch

Preamble

DQS

Postamble Enable dqsenable

Delayed by

1/2T logic

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Dynamic OCT Control

The dynamic OCT control block includes all the registers that are required to dynamically turn the on-chip parallel termination (R

T

OCT) on during a read and turn R

T

OCT off during a write.

Figure 6-16: Dynamic OCT Control Block for Cyclone V Devices

OCT Control Path

OCT Control

D Q

DFF

D Q

DFF

OCT Control

0

1

1

0

OCT Enable

D Q

DFF

D

Q

DFF

OCT Half-Rate Clock

Write Clock

The full-rate write clock comes from the PLL. The DQ write clock and DQS write clock have a 90° offset between them

Related Information

Dynamic OCT in Cyclone V Devices

on page 5-40

Provides more information about dynamic OCT control.

IOE Registers

The IOE registers are expanded to allow source-synchronous systems to have faster register-to-FIFO transfers and resynchronization. All top, bottom, and right IOEs have the same capability.

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Input Registers

Input Registers

6-27

The input path consists of the DDR input registers and the read FIFO block. You can bypass each block of the input path.

There are three registers in the DDR input registers block. Registers A and B capture data on the positive and negative edges of the clock while register C aligns the captured data. Register C uses the same clock as

Register A.

The read FIFO block resynchronizes the data to the system clock domain and lowers the data rate to half rate.

The following figure shows the registers available in the Cyclone V input path. For DDR3 and DDR2 SDRAM interfaces, the DQS and DQSn signals must be inverted. If you use Altera’s memory interface IPs, the DQS and DQSn signals are automatically inverted.

Figure 6-17: IOE Input Registers for Cyclone V Devices

DQ

Double Data Rate Input Registers

D Q datain [0] dataout[3..0]

To core

The input clock can be from the DQS logic block or from a global clock line.

DQS/CQ

D

Input Reg A

D Q

DFF

Input Reg B

D Q datain [1]

Read FIFO

DFF

Input Reg C wrclk rdclk

This half-rate or full-rate read clock comes from a PLL through the clock network

Half-rate or full-rate clock

Output Registers

The Cyclone V output and output-enable path is divided into the HDR block, and output and output-enable registers. The device can bypass each block of the output and output-enable path.

The output path is designed to route combinatorial or registered single data rate (SDR) outputs and full-rate or half-rate DDR outputs from the FPGA core. Half-rate data is converted to full-rate with the HDR block, clocked by the half-rate clock from the PLL.

The output-enable path has a structure similar to the output path—ensuring that the output-enable path goes through the same delay and latency as the output path.

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Delay Chains

Figure 6-18: IOE Output and Output-Enable Path Registers for Cyclone V Devices

The following figure shows the registers available in the Cyclone V output and output-enable paths.

Data coming from the FPGA core are at half the frequency of the memory interface clock frequency in half-rate mode

Double Data Rate

Output-Enable Registers

From Core

D

Half Data Rate to Single

Data Rate Output-Enable

Registers

DFF

Q

0

1

D

DFF

Q

OR2

OE Reg A

OE 1

0

From Core

D

DFF

Q

D

DFF

Q

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From Core

(wdata2)

From Core

(wdata0)

Half Data Rate to Single

Data Rate Output Registers

D

DFF

Q

D

DFF

Q

0

1

OE Reg B

OE

D

DFF

Q

OE Reg A

O

Double Data Rate

Output Registers

TRI

DQ or DQS

0

1

From Core

(wdata3)

From Core

(wdata1)

D

DFF

Q

0

1

D

DFF

Q

OE Reg B

O

D

DFF

Q

Half-Rate Clock from PLL

Write Clock

The full-rate write clock can come from the PLL. The DQ write clock have a 90° offset to the DQS write clock.

Delay Chains

The Cyclone V devices contain run-time adjustable delay chains in the I/O blocks and the DQS logic blocks.

You can control the delay chain setting through the I/O or the DQS configuration block output.

Every I/O block contains a delay chain between the following elements:

• The output registers and output buffer

• The input buffer and input register

• The output enable and output buffer

• The R

T

OCT enable-control register and output buffer

You can bypass the DQS delay chain to achieve a 0° phase shift.

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Figure 6-19: Delay Chains in an I/O Block

DQ or DQS

OCT Enable Output Enable

D5 OCT delay chain

D5 output-enable delay chain

D5 Delay delay chain

D1 Delay delay chain

I/O and DQS Configuration Blocks

6-29

0

1

Each DQS logic block contains a delay chain after the dqsbusout output and another delay chain before the dqsenable input.

Figure 6-20: Delay Chains in the DQS Input Path

DQS

DQS

Enable dqsin dqsenable

DQS delay chain

D4 delay chain dqsbusout

T11 delay chain

DQS

Enable

Control

Related Information

ALTDQ_DQS2 Megafunction User Guide

Provides more information about programming the delay chains.

DQS Delay Chain

on page 6-25

I/O and DQS Configuration Blocks

The I/O and DQS configuration blocks are shift registers that you can use to dynamically change the settings of various device configuration bits.

• The shift registers power-up low.

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Hard Memory Controller

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• Every I/O pin contains one I/O configuration register.

• Every DQS pin contains one DQS configuration block in addition to the I/O configuration register.

Figure 6-21: Configuration Block (I/O and DQS)

This figure shows the I/O configuration block and the DQS configuration block circuitry.

MSB bit2 bit1 bit0 datain update ena rankselectread rankselectwrite clk dataout

Related Information

ALTDQ_DQS2 Megafunction User Guide

Provides details about the I/O and DQS configuration block bit sequence.

Hard Memory Controller

The Cyclone V devices feature dedicated hard memory controllers. You can use the hard memory controllers for LPDDR2, DDR2, and DDR3 SDRAM interfaces. Compared to the memory controllers implemented using core logic, the hard memory controllers allow support for higher memory interface frequencies with shorter latency cycles.

The hard memory controllers use dedicated I/O pins as data, address, command, control, clock, and ground pins for the SDRAM interface. If you do not use the hard memory controllers, you can use these dedicated pins as regular I/O pins.

Related Information

Functional Description—HPC II Controller chapter, External Memory Interface Handbook

The hard memory controller is functionally similar to the High-Performance Controller II (HPC II).

Functional Description—Hard Memory Interface chapter, External Memory Interface Handbook

Provides detailed information about application of the hard memory interface.

Features of the Hard Memory Controller

Table 6-14: Features of the Cyclone V Hard Memory Controller

Feature

Memory Interface

Data Width

• 8, 16, and 32 bit data

• 16 bit data + 8 bit ECC

• 32 bit data + 8bit ECC

Description

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Features of the Hard Memory Controller

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Feature

Memory Density

Description

The controller supports up to four gigabits density parts and two chip selects.

Memory Burst Length • DDR3—Burst length of 8 and burst chop of 4

• DDR2—Burst lengths of 4 and 8

• LPDDR2—Burst lengths of 2, 4, 8, and 16

Command and Data

Reordering

The controller increases efficiency through the support for out-of-order execution of DRAM commands—with address collision detection-and in-order return of results.

Starvation Control A starvation counter ensures that all requests are served after a predefined time-out period. This function ensures that data with low priority access are not left behind when reordering data for efficiency.

User-Configurable

Priority Support

When the controller detects a high priority request, it allows the request to bypass the current queuing request. This request is processed immediately and thus reduces latency.

Avalon

®

-MM Data

Slave Local Interface

By default, the controller supports the Avalon Memory-Mapped protocol.

Bank Management By default, the controller provides closed-page bank management on every access.

The controller intelligently keeps a row open based on incoming traffic. This feature improves the efficiency of the controller especially for random traffic.

Streaming Reads and

Writes

The controller can issue reads or writes continuously to sequential addresses every clock cycle if the bank is open. This function allows for very high efficiencies with large amounts of data.

Bank Interleaving

Predictive Bank

Management

Multiport Interface

The controller can issue reads or writes continuously to 'random' addresses.

The controller can issue bank management commands early so that the correct row is open when the read or write occurs. This increases efficiency.

Built-in Burst

Adaptor

The interface allows you to connect up to six data masters to access the memory controller through the local interface. You can update the multiport scheduling configuration without interrupting traffic on a port.

The controller can accept bursts of arbitrary sizes on its local interface and map these bursts to efficient memory commands.

Run-time Configuration of the Controller

This feature provides support for updates to the timing parameters without requiring reconfiguration of the FPGA, apart from the standard compile-time setting of the timing parameters.

On-Die Termination The controller controls the on-die termination (ODT) in the memory, which improves signal integrity and simplifies your board design.

User-Controlled

Refresh Timing

You can optionally control when refreshes occur—allowing the refreshes to avoid clashing of important reads or writes with the refresh lock-out time.

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Partial Array Self-

Refresh

ECC

Multi-Port Front End

Feature

Low Power Modes

Additive Latency

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Description

You can optionally request the controller to put the memory into the self-refresh or deep power-down modes.

You can select the region of memory to refresh during self-refresh through the mode register to save power.

Standard Hamming single error correction, double error detection (SECDED) error correction code (ECC) support:

• 32 bit data + 8 bit ECC

• 16 bit data + 8 bit ECC

With additive latency, the controller can issue a READ/WRITE command after the

ACTIVATE command to the bank prior to t

RCD to increase the command efficiency.

The controller supports write acknowledgment on the local interface.

Write Acknowledgment

User Control of

Memory Controller

Initialization

Controller Bonding

Support

The controller supports initialization of the memory controller under the control of user logic—for example, through the software control in the user system if a processor is present.

You can bond two controllers to achieve wider data width for higher bandwidth applications.

Multi-Port Front End

The multi-port front end (MPFE) and its associated fabric interface provide up to six command ports, four read-data ports and four write-data ports, through which user logic can access the hard memory controller.

Figure 6-22: Simplified Diagram of the Cyclone V Hard Memory Interface

This figure shows a simplified diagram of the Cyclone V hard memory interface with the MPFE.

FPGA

FPGA

Core Logic

MPFE

Avalon-MM Interface

Memory

Controller

AFI

PHY Memory

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Numbers of MPFE Ports Per Device

Numbers of MPFE Ports Per Device

Table 6-15: Numbers of MPFE Command, Write-Data, and Read-Data Ports for Each Cyclone V Device

6-33

Variant

Cyclone V E

Cyclone V GX

Cyclone V GT

Member Code

D5

D7

D9

C5

C7

C9

A7

A9

C3

C4

A2

A4

A5

Command

6

6

6

6

6

6

4

6

6

6

4

4

6

MPFE Ports

Write-data

4

4

4

4

4

4

2

4

4

4

2

2

4

Read-data

4

4

4

4

4

4

2

4

4

4

2

2

4

Bonding Support

Note:

Bonding is supported only for hard memory controllers configured with one port. Do not use the bonding configuration when there is more than one port in each hard memory controller.

You can bond two hard memory controllers to support wider data widths.

If you bond two hard memory controllers, the data going out of the controllers to the user logic is synchronized. However, the data going out of the controllers to the memory is not synchronized.

The bonding controllers are not synchronized and remain independent with two separate address buses and two independent command buses. These buses are calibrated separately.

If you require ECC support for a bonded interface, you must implement the ECC logic external to the hard memory controllers.

Note:

A memory interface that uses the bonding feature has higher average latency. Bonding through the core fabric will also cause a higher latency.

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Bonding Support

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Figure 6-23: Hard Memory Controllers Bonding Support in Cyclone V E A7, A5, and A9 Devices, Cyclone V

GX C4, C5, C7, and C9 Devices, and Cyclone V GT D5, D7, and D9 Devices

This figure shows the bonding of two opposite hard memory controllers through the core fabric.

Bank 8A

Bank 7A

Hard Memory Controller

Bank 3A Bank 3B

Hard Memory Controller

Bank 4A

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Hard Memory Controller Width for Cyclone V E

6-35

Figure 6-24: Hard Memory Controllers in Cyclone V SX C2, C4, C5, and C6 Devices, and Cyclone V ST D5 and

D6 Devices

This figure shows hard memory controllers in the SoC devices. There is no bonding support.

Bank 8A

HPS I/O

HPS Block

Bank 3A Bank 3B

Hard Memory Controller

Bank 4A

32-bit Interface

Related Information

Bonding Does Not Work for Multiple MPFE Ports in Hard Memory Controller

Cyclone V Device Family Pin Connection Guidelines

Provides more information about the dedicated pins.

Hard Memory Controller Width for Cyclone V E

Table 6-16: Hard Memory Controller Width Per Side in Cyclone V E Devices—Preliminary

Package

M383

M484

F256

U324

Top

≤ 24

0

0

A2

Bottom

0

0

0

Top

≤ 24

0

0

A4

Bottom

0

0

0

Top

≤ 24

Member Code

A5

Bottom

0

Top

24

A7

Bottom

24

Top

A9

Bottom

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Hard Memory Controller Width for Cyclone V GX

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Package

U484

F484

F672

F896

Top

24

24

A2

Bottom

0

0

Top

24

24

A4

Bottom

0

0

Top

24

40

Member Code

A5

Bottom

24

24

Top

24

40

40

40

A7

Bottom

24

24

40

40

Top

24

40

40

A9

Bottom

24

40

40

Related Information

Guideline: Using DQ/DQS Pins

on page 6-3

Important information about usable pin assignments for the hard memory controller in the F484 package of this device.

Hard Memory Controller Width for Cyclone V GX

Table 6-17: Hard Memory Controller Width Per Side in Cyclone V GX Devices—Preliminary

Package

M301

M383

M484

U324

U484

F484

F672

F896

F1152

Top

24

0

24

C3

Bottom

0

0

0

Top

C4

Bottom

40

40

0

≤ 24

24

24

40

0

0

24

40

40

Member Code

C5

Top Bottom

0

≤ 24

24

0

0

24

24

40

Top

C7

Bottom

40

40

40

24

24

24

40

40

24

24

Top

24

24

40

40

40

C9

Bottom

24

40

40

40

24

Related Information

Guideline: Using DQ/DQS Pins

on page 6-3

Important information about usable pin assignments for the hard memory controller in the F484 package of this device.

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Hard Memory Controller Width for Cyclone V GT

Hard Memory Controller Width for Cyclone V GT

Table 6-18: Hard Memory Controller Width Per Side in Cyclone V GT Devices—Preliminary

6-37

Package

M301

M383

M484

U484

F484

F672

F896

F1152

40

Top

0

≤ 24

24

40

D5

Bottom

0

0

24

24

40

Top

24

24

40

40

40

Member Code

D7

Bottom

24

24

24

40

40

Top

24

24

40

40

40

D9

Bottom

24

24

40

40

40

Related Information

Guideline: Using DQ/DQS Pins

on page 6-3

Important information about usable pin assignments for the hard memory controller in the F484 package of this device.

Hard Memory Controller Width for Cyclone V SE

Table 6-19: Hard Memory Controller Width Per Side in Cyclone V SE Devices—Preliminary

Package

U484

U672

F896

Top

0

0

A2

Bottom

0

40

Top

0

0

A4

Bottom

0

40

Member Code

A5

Top

0

0

0

Bottom

0

40

40

Table 6-20: HPS Hard Memory Controller Width in Cyclone V SE Devices—Preliminary

Top

0

0

0

Package

U484

U672

F896

A2

32

40

A4

32

40

Member Code

A5

32

40

40

A6

32

40

40

A6

Bottom

0

40

40

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Hard Memory Controller Width for Cyclone V SX

Hard Memory Controller Width for Cyclone V SX

Table 6-21: Hard Memory Controller Width Per Side in Cyclone V SX Devices—Preliminary

Package

U672

F896

Top

0

C2

Bottom

40

Top

0

C4

Bottom

40

Member Code

C5

Top

0

0

Bottom

40

40

Table 6-22: HPS Hard Memory Controller Width in Cyclone V SX Devices—Preliminary

Top

0

0

Package

U672

F896

C2

40

C4

40

Member Code

C5

40

40

C6

40

40

C6

Bottom

40

40

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Hard Memory Controller Width for Cyclone V ST

Table 6-23: Hard Memory Controller Width Per Side in Cyclone V ST Devices—Preliminary

Member Code

Package D5 D6

F896

Top

0

Bottom

40

Top

0

Table 6-24: HPS Hard Memory Controller Width in Cyclone V ST Devices—Preliminary

Member Code

Package

F896

D5

40

D6

40

Bottom

40

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Document Revision History

6-39

Document Revision History

Date

January 2014

Version

2014.01.10

Changes

• Added Cyclone V SE DLL reference clock input information.

• Added the DQ/DQS groups table for Cyclone V SE.

• Added the DQS pins and DLLs figure for Cyclone V SE.

• Added the PHYCLK networks figure for Cyclone V SE.

• Updated the DQ/DQS numbers for the M383 package of Cyclone V E,

GX, and GT variants.

• Removed the statement about the bottom hard memory controller restrictions in the figure that shows the Cyclone V GX C5 hard memory controller bonding.

• Added information about the hard memory controller interface widths for the Cyclone V SE.

• Added the HPS hard memory controller widths for Cyclone V SE, SX, and ST.

• Added related information link to

ALTDQ_DQS2 Megafunction User

Guide

for more information about using the delay chains.

• Changed all "SoC FPGA" to "SoC".

• Added links to Altera's

External Memory Spec Estimator

tool to the topics listing the external memory interface performance.

• Updated the topic about using DQ/DQS pins to specify that only some specific DQ pins can also be used as RZQ pins.

• Updated the topic about DQS delay chain to remove statements about using delayctrlin[6..0] signals in UniPHY IP to input your own gray-coded 7 bit settings. This mode is not recommended with the

UniPHY controllers.

• Updated topic about hard memory controller bonding support to specify that bonding is supported only for hard memory controllers configured with one port.

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Document Revision History

Date

May 2013

December 2012

Version

2013.05.06

2012.11.28

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Changes

• Moved all links to the Related Information section of respective topics for easy reference.

• Added link to the known document issues in the Knowledge Base.

• Added the supported minimum operating frequencies for the supported memory interface standards.

• Added packages and updated the DQ/DQS groups of Cyclone V E, GX,

GT, and SX devices.

• Added the number of MPFE command, write-data, and read-data ports for each Cyclone V E, GX, and GT device.

• Added a note about the usable hard memory controller pin assignments for the F484 package of the Cyclone V E A9, GX C9, and GT D9 devices.

• Updated the M386 package to M383.

• Removed the F672 package from the Cyclone V E A5 device in the table listing Cyclone V E hard memory controller widths.

• Added the U484 package for the Cyclone V GX C9 device in the table listing Cyclone V GX hard memory controller widths.

• Updated the hard memory controller widths of Cyclone V E, GX, SX, and ST.

• Removed the restrictions on using the bottom hard memory controller of the Cyclone V GX C5 device if the configuration is 3.3/3.0 V.

• Added note to clarify that the DQS phase-shift circuitry figures show all possible connections and the device pin-out files have per package information.

• Reorganized content and updated template.

• Added a list of supported external memory interface standards using the hard memory controller and soft memory controller.

• Added performance information for external memory interfaces and the HPS external memory interfaces.

• Separated the DQ/DQS groups tables into separate topics for each device variant for easy reference.

• Updated the DQ/DQS numbers and device packages for the Cyclone V

E, GX, GT, SX, and ST variants.

• Moved the PHYCLK networks pin placement guideline to the

Planning

Pin and FPGA Resources

chapter of the

External Memory Interface

Handbook

.

• Moved information from the "Design Considerations" section into relevant topics.

• Removed the "DDR2 SDRAM Interface" and "DDR3 SDRAM DIMM" sections. Refer to the relevant sections in the

External Memory Interface

Handbook

for the information.

• Added the I/O and DQS configuration blocks topic.

• Updated the term "Multiport logic" to "multi-port front end" (MPFE).

• Added information about the hard memory controller interface widths for the Cyclone V E, GX, GT, SX, and ST variants.

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Date

June 2012

February 2012

November 2011

October 2011

Version

2.0

1.2

1.1

1.0

Document Revision History

Changes

Updated for the Quartus II software v12.0 release:

• Restructured chapter.

• Updated “Design Considerations”, “DQS Postamble Circuitry”, and

“IOE Registers”sections.

• Added SoC devices information.

• Added Figure 6–5, Figure 6–10, and Figure 6–21.

• Updated Figure 6–20.

• Minor text edits.

• Updated Table 6–2.

• Added Figure 6–2.

Initial release.

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External Memory Interfaces in Cyclone V Devices

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Configuration, Design Security, and Remote

System Upgrades in Cyclone V Devices

2014.01.10

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This chapter describes the configuration schemes, design security, and remote system upgrade that are supported by the Cyclone V devices.

Related Information

Cyclone V Device Handbook: Known Issues

Lists the planned updates to the

Cyclone V Device Handbook

chapters.

Cyclone V Device Overview

Provides more information about configuration features supported for each configuration scheme.

Cyclone V Device Datasheet

Provides more information about the estimated uncompressed .rbf file sizes, FPP

DCLK

-to-

DATA[] ratio, and timing parameters.

Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide

Provides more information about the CvP configuration scheme.

Hard Processor System Technical Reference Manual

Provides more information about configuration via HPS configuration scheme.

Design Planning for Partial Reconfiguration

Provides more information about partial reconfiguration.

7

Enhanced Configuration and Configuration via Protocol

Cyclone V devices support 1.8 V, 2.5 V, 3.0 V, and 3.3 V programming voltages and several configuration modes.

©

2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with

Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO

9001:2008

Registered www.altera.com

101 Innovation Drive, San Jose, CA 95134

7-2

MSEL Pin Settings

Table 7-1: Configuration Modes and Features Supported by Cyclone V Devices

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Mode Data

Width

AS through the

EPCS and EPCQ serial configuration device

PS through CPLD or external microcontroller

1 bit, 4 bits

1 bit

FPP

CvP (PCIe)

JTAG

8 bits

16 bits x1, x2, and x4 lanes

1 bit

Max Clock

Rate

(MHz)

Max Data

Rate

(Mbps)

100 —

Decompression

Yes

Design

Security

Yes

Partial

Reconfiguration

(15)

125

125

125

33

125

33

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Remote System

Update

Yes

Parallel flash loader

Instead of using an external flash or ROM, you can configure the Cyclone V devices through PCIe using

CvP. The CvP mode offers the fastest configuration rate and flexibility with the easy-to-use PCIe hard IP block interface. The Cyclone V CvP implementation conforms to the PCIe 100 ms power-up-to-active time requirement.

Related Information

Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide

Provides more information about the CvP configuration scheme.

MSEL Pin Settings

To select a configuration scheme, hardwire the

MSEL pins to V

CCPGM resistors.

or GND without pull-up or pull-down

Note:

Do not drive the

MSEL pins with a microprocessor or another device.

(15)

Partial reconfiguration is an advanced feature of the device family. If you are interested in using partial reconfiguration, contact Altera for support.

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Configuration Sequence

Table 7-2: MSEL Pin Settings for Each Configuration Scheme of Cyclone V Devices

7-3

Configuration Scheme

FPP x8

FPP x16

PS

(16)

AS (x1 and x4)

JTAG-based configuration

Compression

Feature

Disabled

Disabled

Enabled

Disabled

Disabled

Enabled

Enabled/

Disabled

Enabled/

Disabled

Disabled

Design Security

Feature

Disabled

Enabled

Enabled/

Disabled

Disabled

Enabled

Enabled/

Disabled

Enabled/

Disabled

Enabled/

Disabled

Disabled

V

CCPGM

(V)

1.8/2.5/3.0/3.3

1.8/2.5/3.0/3.3

1.8/2.5/3.0/3.3

1.8/2.5/3.0/3.3

1.8/2.5/3.0/3.3

1.8/2.5/3.0/3.3

1.8/2.5/3.0/3.3

3.0/3.3

Power-On Reset

(POR) Delay

Fast

Standard

Fast

Standard

Fast

Standard

Fast

Standard

Fast

Standard

Fast

Standard

Fast

Standard

Fast

Standard

Valid MSEL[4..0]

10100

11000

10101

11001

10110

11010

00000

00100

00001

00101

00010

00110

10000

10001

10010

10011

Use any valid

MSEL pin settings above

Note:

You must also select the configuration scheme in the Configuration page of the Device and Pin

Options dialog box in the Quartus II software. Based on your selection, the option bit in the programming file is set accordingly.

Related Information

FPGA Manager

Provides more information about the MSEL pin settings for configuration with hard processor system

(HPS) in system on a chip (SoC) FPGA devices.

Cyclone V Device Family Pin Connection Guidelines

Provides more information about JTAG pins voltage-level connection.

Configuration Sequence

Describes the configuration sequence and each configuration stage.

(16)

For configuration with HPS in SoC FPGA devices, refer to the FPGA Manager for the related MSEL pin settings.

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Power Up

Figure 7-1: Configuration Sequence for Cyclone V Devices

Configuration Error Handling

• nSTATUS pulled low

CONF_DONE remains low

• Restarts configuration if option enabled

Power Up

• nSTATUS and

CONF_DONE driven low

• All I/Os pins are tied to an internal weak pull-up

• Clears configuration RAM bits

Power supplies including V

CCPD recommended operating voltage and V

CCPGM reach

Reset

• nSTATUS and

CONF_DONE remain low

• All I/Os pins are tied to an internal weak pull-up

• Samples

MSEL pins

nSTATUS and nCONFIG released high

CONF_DONE pulled low

Configuration

Writes configuration data to

FPGA

CONF_DONE released high

Initialization

• Initializes internal logic and registers

• Enables I/O buffers

INIT_DONE released high

(if option enabled)

User Mode

Executes your design

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You can initiate reconfiguration by pulling the nCONFIG pin low to at least the minimum t

CFG low-pulse width except for configuration using the partial reconfiguration operation. When this pin is pulled low, the nSTATUS and

CONF_DONE pins are pulled low and all I/O pins are tied to an internal weak pull-up.

Power Up

Power up all the power supplies that are monitored by the POR circuitry. All power supplies, including

V

CCPGM and V

CCPD

, must ramp up from 0 V to the recommended operating voltage level within the rampup time specification. Otherwise, hold the nCONFIG pin low until all the power supplies reach the recommended voltage level.

V

CCPGM

Pin

The configuration input buffers do not have to share power lines with the regular I/O buffers in Cyclone V devices.

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Reset

7-5

The operating voltage for the configuration input pin is independent of the I/O banks power supply, V

CCIO

, during configuration. Therefore, Cyclone V devices do not require configuration voltage constraints on

V

CCIO

.

V

CCPD

Pin

Use the V

CCPD pin, a dedicated programming power supply, to power the I/O pre-drivers and JTAG I/O pins (

TCK

,

TMS

,

TDI

, and

TDO

). The supported configuration voltages are 2.5, 3.0, and 3.3 V.

If V

CCIO of the bank is set to 2.5 V or lower, V

2.5 V, V

CCPD must be greater than V

CCIO

3.0 V or above. When V

CCIO is set to 3.3 V, V

CCPD

CCPD must be powered up at 2.5 V. If V

CCIO

. For example, when V

CCIO is set to 3.0 V, V must be set at 3.3 V.

is set greater than

CCPD must be set at

Related Information

Cyclone V Device Datasheet

Provides more information about the ramp-up time specifications.

Cyclone V Device Family Pin Connection Guidelines

Provides more information about configuration pin connections.

Device Configuration Pins

on page 7-6

Provides more information about configuration pins.

I/O Standards Voltage Levels in Cyclone V Devices

on page 5-8

Provides more information about typical power supplies for each supported I/O standards in Cyclone V devices.

Reset

POR delay is the time frame between the time when all the power supplies monitored by the POR circuitry reach the recommended operating voltage and when nSTATUS is released high and the Cyclone V device is ready to begin configuration.

Set the POR delay using the

MSEL pins.

The user I/O pins are tied to an internal weak pull-up until the device is configured.

Related Information

MSEL Pin Settings

on page 7-2

Cyclone V Device Datasheet

Provides more information about the POR delay specification.

Configuration

For more information about the

DATA[] pins for each configuration scheme, refer to the appropriate configuration scheme.

Configuration Error Handling

To restart configuration automatically, turn on the Auto-restart configuration after error option in the

General page of the Device and Pin Options dialog box in the Quartus II software.

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Initialization

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If you do not turn on this option, you can monitor the nSTATUS pin to detect errors. To restart configuration, pull the nCONFIG pin low for at least the duration of t

CFG

.

Related Information

Cyclone V Device Datasheet

Provides more information about t

STATUS and t

CFG timing parameters.

Initialization

The initialization clock source is from the internal oscillator,

CLKUSR pin, or

DCLK pin. By default, the internal oscillator is the clock source for initialization. If you use the internal oscillator, the Cyclone V device will be provided with enough clock cycles for proper initialization.

Note:

If you use the optional

CLKUSR pin as the initialization clock source and the nCONFIG pin is pulled low to restart configuration during device initialization, ensure that the

CLKUSR or

DCLK pin continues toggling until the nSTATUS pin goes low and then goes high again.

The

CLKUSR pin provides you with the flexibility to synchronize initialization of multiple devices or to delay initialization. Supplying a clock on the

CLKUSR pin during initialization does not affect configuration. After the

CONF_DONE pin goes high, the

CLKUSR or

DCLK pin is enabled after the time specified by t

CD2CU

. When this time period elapses, Cyclone V devices require a minimum number of clock cycles as specified by T init to initialize properly and enter user mode as specified by the t

CD2UMC parameter.

Related Information

Cyclone V Device Datasheet

Provides more information about t

CD2CU

, t init

, and t source.

CD2UMC timing parameters, and initialization clock

User Mode

You can enable the optional

INIT_DONE pin to monitor the initialization stage. After the

INIT_DONE pin is pulled high, initialization completes and your design starts executing. The user I/O pins will then function as specified by your design.

Device Configuration Pins

Configuration Pins Summary

The following table lists the Cyclone V configuration pins and their power supply.

Note:

The

TDI

,

TMS

,

TCK

, and

TDO pins are powered by V

CCPD of the bank in which the pin resides.

Note:

The

CLKUSR

,

DEV_OE

,

DEV_CLRn

, and

DATA[15..5] pins are powered by V

CCPGM and by V

CCIO during configuration of the bank in which the pin resides if you use it as a user I/O pin.

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Table 7-3: Configuration Pin Summary for Cyclone V Devices

Configuration Pin

TDI

TMS

TCK

TDO

CLKUSR

CRC_ERROR

CONF_DONE

DCLK

Configuration

Scheme

JTAG

JTAG

Input/Output

Input

Input

JTAG

JTAG

Input

Output

All schemes

Input

Optional, all schemes

Output

All schemes

Bidirectional

FPP and PS Input

AS Output

DEV_OE

DEV_CLRn

INIT_DONE

MSEL[4..0] nSTATUS nCE nCEO nCONFIG

DATA[15..5]

Optional, all schemes

Input

Optional, all schemes

Input

Optional, all schemes

Output

All schemes

Input

All schemes

All schemes

All schemes

All schemes

Bidirectional

Input

Output

Input

FPP x8 and x16

Input

AS Output nCSO

/

DATA4

FPP

AS_DATA[3..1]

/

DATA[3..1]

AS

FPP

Input

Bidirectional

Input

AS_DATA0

/

DATA0

/

ASDO

AS Bidirectional

FPP and PS Input

I/O

I/O

I/O

I/O

I/O

I/O

I/O

User Mode

Device Configuration Pins

V

V

V

V

CCPD

V

CCPGM

/V

CCIO

(17)

Pull-up

V

V

CCPGM

V

CCPGM

V

CCPGM

/V

CCIO

(17)

V

CCPGM

Pull-up

V

V

V

Pull-up

V

V

CCPGM

V

V

V

V

V

V

CCPD

CCPD

CCPD

CCPGM

CCPGM

CCPGM

CCPGM

CCPGM

CCPGM

CCPGM

CCPGM

CCPGM

CCPGM

CCPGM

Powered By

/Pull-up

/V

CCIO

/Pull-up

/V

CCIO

(17)

(17)

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Configuration Pin Options in the Quartus II Software

Configuration Pin

PR_REQUEST

PR_READY

PR_ERROR

PR_DONE

Configuration

Scheme

Input/Output

Partial

Reconfiguration

Input

Partial

Reconfiguration

Output

Partial

Reconfiguration

Output

Partial

Reconfiguration

Output

I/O

I/O

I/O

I/O

User Mode Powered By

V

CCPGM

/V

CCIO

(17)

V

CCPGM

/V

CCIO

(17)

V

CCPGM

/V

CCIO

(17)

V

CCPGM

/V

CCIO

(17)

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Related Information

Cyclone V Device Family Pin Connection Guidelines

Provides more information about each configuration pin.

Configuration Pin Options in the Quartus II Software

The following table lists the dual-purpose configuration pins available in the Device and Pin Options dialog box in the Quartus II software.

Table 7-4: Configuration Pin Options

CLKUSR

Configuration Pin

DEV_CLRn

DEV_OE

INIT_DONE nCEO

CRC_ERROR

Category Page

General

General

General

General

General

Error Detection CRC

Option

Enable user-supplied start-up clock

(CLKUSR)

Enable device-wide reset (DEV_CLRn)

Enable device-wide output enable

(DEV_OE)

Enable INIT_DONE output

Enable nCEO pin

Enable Error Detection CRC_ERROR pin

Enable open drain on CRC_ERROR pin

Enable internal scrubbing

PR_REQUEST

PR_READY

PR_ERROR

PR_DONE

General Enable PR pin

(17)

This pin is powered by V

CCPGM during configuration and powered by V resides when you use this pin as a user I/O pin.

CCIO of the bank in which the pin

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Fast Passive Parallel Configuration

Related Information

Reviewing Printed Circuit Board Schematics with the Quartus II Software

Provides more information about the device and pin options dialog box setting.

7-9

Fast Passive Parallel Configuration

The FPP configuration scheme uses an external host, such as a microprocessor, MAX

®

II device, or MAX V device. This scheme is the fastest method to configure Cyclone V devices. The FPP configuration scheme supports 8- and 16-bits data width.

You can use an external host to control the transfer of configuration data from an external storage such as flash memory to the FPGA. The design that controls the configuration process resides in the external host.

You can store the configuration data in Raw Binary File (.rbf), Hexadecimal (Intel-Format) File (.hex), or

Tabular Text File (.ttf) formats.

You can use the PFL megafunction with a MAX II or MAX V device to read configuration data from the flash memory device and configure the Cyclone V device.

Note:

Two

DCLK falling edges are required after the

CONF_DONE pin goes high to begin the initialization of the device for both uncompressed and compressed configuration data in an FPP configuration.

Related Information

Parallel Flash Loader Megafunction User Guide

Cyclone V Device Datasheet

Provides more information about the FPP configuration timing.

Fast Passive Parallel Single-Device Configuration

To configure a Cyclone V device, connect the device to an external host as shown in the following figure.

Figure 7-2: Single Device FPP Configuration Using an External Host

Memory

ADDR DATA[7..0]

External Host

(MAX II Device,

MAX V Device, or

Microprocessor)

Connect the resistor to a supply that provides an acceptable input signal for the FPGA device. V

CCPGM must be high enough to meet the V

IH specification of the I/O on the device and the external host. Altera recommends powering up all configuration system I/Os with V

CCPGM

.

V

CCPGM

V

CCPGM

10 kΩ 10 kΩ

FPGA Device

MSEL[4..0]

CONF_DONE nSTATUS nCE nCEO N.C.

GND

DATA[] nCONFIG

DCLK

For more information, refer to the MSEL pin settings.

You can leave the nCEO pin unconnected or use it as a user

I/O pin when it does not feed another device’s nCE pin.

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Fast Passive Parallel Multi-Device Configuration

Fast Passive Parallel Multi-Device Configuration

You can configure multiple Cyclone V devices that are connected in a chain.

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Pin Connections and Guidelines

Observe the following pin connections and guidelines for this configuration setup:

• Tie the following pins of all devices in the chain together:

• nCONFIG

• nSTATUS

DCLK

DATA[]

CONF_DONE

By tying the

CONF_DONE and nSTATUS pins together, the devices initialize and enter user mode at the same time. If any device in the chain detects an error, configuration stops for the entire chain and you must reconfigure all the devices. For example, if the first device in the chain flags an error on the nSTATUS pin, it resets the chain by pulling its nSTATUS pin low.

• Ensure that

DCLK and

DATA[] are buffered for every fourth device to prevent signal integrity and clock skew problems.

• All devices in the chain must use the same data width.

• If you are configuring the devices in the chain using the same configuration data, the devices must be of the same package and density.

Using Multiple Configuration Data

To configure multiple Cyclone V devices in a chain using multiple configuration data, connect the devices to an external host as shown in the following figure.

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Using One Configuration Data

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Figure 7-3: Multiple Device FPP Configuration Using an External Host When Both Devices Receive a Different

Set of Configuration Data

Memory

ADDR DATA[7..0]

Connect the resistor to a supply that provides an acceptable input signal for the FPGA device.

V

CCPGM must be high enough to meet the V

IH specification of the

I/O on the device and the external host. Altera recommends powering up all configuration system I/Os with V

CCPGM

.

V

CCPGM

V

CCPGM

10 kΩ 10 kΩ

External Host

(MAX II Device,

MAX V Device, or

Microprocessor)

GND

FPGA Device Master

CONF_DONE nSTATUS nCE

MSEL[4..0] nCEO

10 kΩ

V

CCPGM

DATA[] nCONFIG

DCLK

For more information, refer to the MSEL pin settings.

FPGA Device Slave

CONF_DONE nSTATUS nCE

MSEL[4..0] nCEO N.C.

DATA[] nCONFIG

DCLK

You can leave the nCEO pin unconnected or use it as a user

I/O pin when it does not feed another device’s nCE pin.

Buffers

Connect the repeater buffers between the

FPGA master and slave device for DATA[] and DCLK for every fourth device.

When a device completes configuration, its nCEO pin is released low to activate the nCE pin of the next device in the chain. Configuration automatically begins for the second device in one clock cycle.

Using One Configuration Data

To configure multiple Cyclone V devices in a chain using one configuration data, connect the devices to an external host as shown in the following figure.

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Active Serial Configuration

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Figure 7-4: Multiple Device FPP Configuration Using an External Host When Both Devices Receive the Same

Data

Memory

Connect the resistor to a supply that provides an acceptable input signal for the

FPGA device. V

CCPGM must be high enough to meet the VIH specification of the I/O on the device and the external host. Altera recommends powering up all configuration system I/Os with V

CCPGM

.

V

CCPGM

V

CCPGM

ADDR DATA[7..0]

10 kΩ 10 kΩ

External Host

(MAX II Device,

MAX V Device, or

Microprocessor)

FPGA Device Master

MSEL[4..0]

CONF_DONE nSTATUS nCE nCEO N.C.

GND

DATA[] nCONFIG

DCLK

For more information, refer to the MSEL pin settings.

FPGA Device Slave

MSEL[4..0]

CONF_DONE nSTATUS nCE nCEO N.C.

GND

DATA[] nCONFIG

DCLK

You can leave the nCEO pin unconnected or use it as a user

I/O pin when it does not feed another device’s nCE pin.

Buffers

Connect the repeater buffers between the

FPGA master and slave device for DATA[] and DCLK for every fourth device.

The nCE pins of the device in the chain are connected to GND, allowing configuration for these devices to begin and end at the same time.

Active Serial Configuration

The AS configuration scheme supports AS x1 (1-bit data width) and AS x4 (4-bit data width) modes. The

AS x4 mode provides four times faster configuration time than the AS x1 mode. In the AS configuration scheme, the Cyclone V device controls the configuration interface.

Related Information

Cyclone V Device Datasheet

Provides more information about the AS configuration timing.

DATA Clock (DCLK)

Cyclone V devices generate the serial clock,

DCLK

, that provides timing to the serial interface. In the AS configuration scheme, Cyclone V devices drive control signals on the falling edge of

DCLK and latch the configuration data on the following falling edge of this clock pin.

The maximum

DCLK frequency supported by the AS configuration scheme is 100 MHz except for the AS multi-device configuration scheme. You can source

DCLK using

CLKUSR or the internal oscillator. If you use the internal oscillator, you can choose a 12.5, 25, 50, or 100 MHz clock under the Device and Pin Options dialog box, in the Configuration page of the Quartus II software.

After power-up,

DCLK is driven by a 12.5 MHz internal oscillator by default. The Cyclone V device determines the clock source and frequency to use by reading the option bit in the programming file.

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Active Serial Single-Device Configuration

Related Information

Cyclone V Device Datasheet

Provides more information about the

DCLK frequency specification in the AS configuration scheme.

7-13

Active Serial Single-Device Configuration

To configure a Cyclone V device, connect the device to a serial configuration (EPCS) device or quad-serial configuration (EPCQ) device, as shown in the following figures.

Figure 7-5: Single Device AS x1 Mode Configuration

Connect the pull-up resistors to

V

CCPGM at 3.0- or 3.3-V power supply.

V

CCPGM

V

CCPGM

V

CCPGM

EPCS or EPCQ Device

DATA

DCLK nCS

ASDI

10 kΩ 10 kΩ

GND

10 kΩ

FPGA Device nSTATUS

CONF_DONE nCONFIG nCE nCEO

AS_DATA1

DCLK nCSO

ASDO

MSEL[4..0]

CLKUSR

N.C.

For more information, refer to the MSEL pin settings.

Use the CLKUSR pin to supply the external clock source to drive DCLK during configuration.

Figure 7-6: Single Device AS x4 Mode Configuration

Connect the pull-up resistors to

V

CCPGM at 3.0- or 3.3-V power supply.

V

CCPGM

V

CCPGM

V

CCPGM

EPCQ Device

DATA0

DATA1

DATA2

DATA3

DCLK nCS

10 kΩ 10 kΩ

GND

10 kΩ

FPGA Device nSTATUS

CONF_DONE nCONFIG nCE nCEO

AS_DATA0/

ASDO

AS_DATA1

MSEL[4..0]

CLKUSR

AS_DATA2

AS_DATA3

DCLK nCSO

N.C.

For more information, refer to the MSEL pin settings.

Use the CLKUSR pin to supply the external clock source to drive DCLK during configuration.

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Active Serial Multi-Device Configuration

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Active Serial Multi-Device Configuration

You can configure multiple Cyclone V devices that are connected to a chain. Only AS x1 mode supports multi-device configuration.

The first device in the chain is the configuration master. Subsequent devices in the chain are configuration slaves.

Pin Connections and Guidelines

Observe the following pin connections and guidelines for this configuration setup:

• Hardwire the

MSEL pins of the first device in the chain to select the AS configuration scheme. For subsequent devices in the chain, hardwire their

MSEL pins to select the PS configuration scheme. Any other Altera

® devices that support the PS configuration can also be part of the chain as a configuration slave.

• Tie the following pins of all devices in the chain together:

• nCONFIG

• nSTATUS

DCLK

DATA[]

CONF_DONE

By tying the

CONF_DONE

, nSTATUS

, and nCONFIG pins together, the devices initialize and enter user mode at the same time. If any device in the chain detects an error, configuration stops for the entire chain and you must reconfigure all the devices. For example, if the first device in the chain flags an error on the nSTATUS pin, it resets the chain by pulling its nSTATUS pin low.

• Ensure that

DCLK and

DATA[] are buffered every fourth device to prevent signal integrity and clock skew problems.

Using Multiple Configuration Data

To configure multiple Cyclone V devices in a chain using multiple configuration data, connect the devices to an EPCS or EPCQ device, as shown in the following figure.

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7-15

Figure 7-7: Multiple Device AS Configuration When Both Devices in the Chain Receive Different Sets of

Configuration Data

Connect the pull-up resistors to

V

CCPGM supply.

at a 3.0- or 3.3-V power

V

CCPGM

V

CCPGM

V

CCPGM

10 kΩ 10 kΩ 10 kΩ

V

CCPGM

10 kΩ

EPCS or EPCQ Device

DATA

DCLK nCS

ASDI

GND

FPGA Device Master nSTATUS

CONF_DONE nCONFIG nCE nCEO

AS_DATA1

DCLK nCSO

ASDO

MSEL[4..0]

CLKUSR

FPGA Device Slave nSTATUS

CONF_DONE nCONFIG nCE nCEO

DATA0

DCLK MSEL [4..0]

You can leave the nCEO pin unconnected or use it as a user I/O pin when it does not feed another device’s nCE pin.

For the appropriate MSEL settings based on POR delay settings, set the slave device MSEL setting to the PS scheme.

For more information, refer to the

MSEL pin settings.

Use the CLKUSR pin to supply the external clock source to drive DCLK during configuration.

Buffers

Connect the repeater buffers between the

FPGA master and slave device for AS_DATA1 or DATA0 and DCLK for every fourth device.

When a device completes configuration, its nCEO pin is released low to activate the nCE pin of the next device in the chain. Configuration automatically begins for the second device in one clock cycle.

Estimating the Active Serial Configuration Time

The AS configuration time is mostly the time it takes to transfer the configuration data from an EPCS or

EPCQ device to the Cyclone V device.

Use the following equations to estimate the configuration time:

• AS x1 mode

.rbf Size x (minimum

DCLK period / 1 bit per

DCLK cycle) = estimated minimum configuration time.

• AS x4 mode

.rbf Size x (minimum

DCLK period / 4 bits per

DCLK cycle) = estimated minimum configuration time.

Compressing the configuration data reduces the configuration time. The amount of reduction varies depending on your design.

Using EPCS and EPCQ Devices

EPCS devices support AS x1 mode and EPCQ devices support AS x1 and AS x4 modes.

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Controlling EPCS and EPCQ Devices

Related Information

Serial Configuration (EPCS) Devices Datasheet

Quad-Serial Configuration (EPCQ) Devices Datasheet

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Controlling EPCS and EPCQ Devices

During configuration, Cyclone V devices enable the EPCS or EPCQ device by driving its nCSO output pin low, which connects to the chip select ( nCS

) pin of the EPCS or EPCQ device. Cyclone V devices use the

DCLK and

ASDO pins to send operation commands and read address signals to the EPCS or EPCQ device.

The EPCS or EPCQ device provides data on its serial data output (

DATA[]

) pin, which connects to the

AS_DATA[] input of the Cyclone V devices.

Note:

If you wish to gain control of the EPCS pins, hold the nCONFIG pin low and pull the nCE pin high.

This causes the device to reset and tri-state the AS configuration pins.

Trace Length and Loading

The maximum trace length and loading apply to both single- and multi-device AS configuration setups as listed in the following table. The trace length is the length from the Cyclone V device to the EPCS or EPCQ device.

Table 7-5: Maximum Trace Length and Loading for AS x1 and x4 Configurations for Cyclone V Devices

Cyclone V Device AS Pins

DCLK

DATA[3..0] nCSO

10

10

10

Maximum Board Trace Length (Inches)

12.5/ 25/ 50 MHz 100 MHz

6

6

6

5

10

10

Maximum Board Load (pF)

Programming EPCS and EPCQ Devices

You can program EPCS and EPCQ devices in-system using a USB-Blaster

, EthernetBlaster, EthernetBlaster II, or ByteBlaster

II download cable. Alternatively, you can program the EPCS or EPCQ using a microprocessor with the SRunner software driver.

In-system programming (ISP) offers you the option to program the EPCS or EPCQ either using an AS programming interface or a JTAG interface. Using the AS programming interface, the configuration data is programmed into the EPCS by the Quartus II software or any supported third-party software. Using the

JTAG interface, an Altera IP called the serial flash loader (SFL) must be downloaded into the Cyclone V device to form a bridge between the JTAG interface and the EPCS or EPCQ. This allows the EPCS or EPCQ to be programmed directly using the JTAG interface.

Related Information

AN 370: Using the Serial FlashLoader with the Quartus II Software

AN 418: SRunner: An Embedded Solution for Serial Configuration Device Programming

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Programming EPCS Using the JTAG Interface

Programming EPCS Using the JTAG Interface

7-17

To program an EPCS device using the JTAG interface, connect the device as shown in the following figure.

Figure 7-8: Connection Setup for Programming the EPCS Using the JTAG Interface

V

CCPGM

V

CCPGM

V

CCPGM

10 kΩ 10 kΩ 10 kΩ

V

CCPD

V

CCPD

Connect the pull-up resistors to V

CCPGM at a

3.0- or 3.3-V power supply.

EPCS Device

DATA

DCLK nCS

ASDI

For more information, refer to the MSEL pin settings.

Use the CLKUSR pin to supply the external clock source to drive

DCLK during configuration.

GND

FPGA Device nSTATUS

CONF_DONE nCONFIG nCE

TCK

TDO

TMS

TDI

AS_DATA1

DCLK nCSO

ASDO

MSEL[4..0]

CLKUSR

Serial

Flash

Loader

Instantiate SFL in your design to form a bridge between the EPCS and the

10-pin header.

1 kΩ

Pin 1

V

CCPD

Download Cable

GND

10-Pin Male Header

GND

(JTAG Mode) (Top View)

The resistor value can vary from 1 k Ω to 10 kΩ. Perform signal integrity analysis to select the resistor value for your setup.

Programming EPCQ Using the JTAG Interface

To program an EPCQ device using the JTAG interface, connect the device as shown in the following figure.

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Programming EPCS Using the Active Serial Interface

Figure 7-9: Connection Setup for Programming the EPCQ Using the JTAG Interface

V

CCPGM

V

CCPGM

V

CCPGM

10 kΩ 10 kΩ 10 kΩ

V

CCPD

V

CCPD

Connect the pull-up resistors to

V

CCPGM at a 3.0- or 3.3-V power supply.

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EPCQ Device

DATA0

DATA1

DATA2

DATA3

DCLK nCS

GND

FPGA Device nSTATUS

CONF_DONE nCONFIG nCE

TCK

TDO

TMS

TDI

AS_DATA0/ASDO

AS_DATA1

AS_DATA2

AS_DATA3

DCLK nCSO

Serial

Flash

Loader

MSEL[4..0]

CLKUSR

Instantiate SFL in your design to form a bridge between the EPCQ and the 10-pin header.

Pin 1

V

CCPD

The resistor value can vary from 1 k Ω to 10 kΩ. Perform signal integrity analysis to select the resistor value for your setup.

1 kΩ

Download Cable

GND

10-Pin Male Header

GND

(JTAG Mode) (Top View)

For more information, refer to the MSEL pin settings.

Use the CLKUSR pin to supply the external clock source to drive DCLK during configuration.

Programming EPCS Using the Active Serial Interface

To program an EPCS device using the AS interface, connect the device as shown in the following figure.

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Programming EPCQ Using the Active Serial Interface

Figure 7-10: Connection Setup for Programming the EPCS Using the AS Interface

EPCS Device

Connect the pull-up resistors to V

CCPGM at a 3.0- or 3.3-V power supply.

V

CCPGM

V

CCPGM

V

CCPGM

10 kΩ 10 kΩ 10 kΩ

FPGA Device

CONF_DONE nSTATUS nCONFIG nCEO nCE

10 kΩ

DATA

DCLK nCS

ASDI

AS_DATA1

DCLK nCSO

ASDO

MSEL[4..0]

CLKUSR

Pin 1

V

CCPGM

N.C.

For more information, refer to the MSEL pin settings.

Use the CLKUSR pin to supply the external clock source to drive DCLK during configuration.

Power up the USB-Blaster,

ByteBlaster II, EthernetBlaster, or

EthernetBlaster II cable’s V

CC(TRGT) to V

CCPGM

.

USB-Blaster or ByteBlaster II

(AS Mode)

GND

10-Pin Male Header

7-19

Programming EPCQ Using the Active Serial Interface

To program an EPCQ device using the AS interface, connect the device as shown in the following figure.

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Passive Serial Configuration

Figure 7-11: Connection Setup for Programming the EPCQ Using the AS Interface

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Using the AS header, the programmer serially transmits the operation commands and configuration bits to the EPCQ on

DATA0

. This is equivalent to the programming operation for the EPCS.

Connect the pull-up resistors to V

CCPGM at a 3.0- or 3.3-V power supply.

V

CCPGM

V

CCPGM

V

CCPGM

10 kΩ 10 kΩ 10 kΩ

EPCQ Device

FPGA Device

CONF_DONE nSTATUS nCONFIG nCE nCEO

N.C.

10 kΩ

DATA0

DATA1

DATA2

DATA3

DCLK nCS

Pin 1

V

CCPGM

AS_DATA0/ASDO

AS_DATA1

AS_DATA2

AS_DATA3

DCLK nCSO

MSEL[4..0]

CLKUSR

For more information, refer to the MSEL pin settings.

Use the CLKUSR pin to supply the external clock source to drive DCLK during configuration.

Power up the USB-Blaster, ByteBlaster II,

EthernetBlaster, or EthernetBlaster II cable’s

V

CC(TRGT) to V

CCPGM

.

USB-Blaster or ByteBlaster II

(AS Mode)

GND

10-Pin Male Header

When programming the EPCS and EPCQ devices, the download cable disables access to the AS interface by driving the nCE pin high. The nCONFIG line is also pulled low to hold the Cyclone V device in the reset stage. After programming completes, the download cable releases nCE and nCONFIG

, allowing the pull-down and pull-up resistors to drive the pin to GND and V

CCPGM

, respectively.

During the EPCQ programming using the download cable,

DATA0 transfers the programming data, operation command, and address information from the download cable into the EPCQ. During the EPCQ verification using the download cable,

DATA1 transfers the programming data back to the download cable.

Passive Serial Configuration

The PS configuration scheme uses an external host. You can use a microprocessor, MAX II device, MAX V device, or a host PC as the external host.

You can use an external host to control the transfer of configuration data from an external storage such as flash memory to the FPGA. The design that controls the configuration process resides in the external host.

You can store the configuration data in Programmer Object File (.pof), .rbf, .hex, or .ttf. If you are using configuration data in .rbf, .hex, or .ttf, send the LSB of each data byte first. For example, if the .rbf contains

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Passive Serial Single-Device Configuration Using an External Host

7-21

the byte sequence 02 1B EE 01 FA, the serial data transmitted to the device must be 0100-0000 1101-1000

0111-0111 1000-0000 0101-1111.

You can use the PFL megafunction with a MAX II or MAX V device to read configuration data from the flash memory device and configure the Cyclone V device.

For a PC host, connect the PC to the device using a download cable such as the Altera USB-Blaster USB port, ByteBlaster II parallel port, EthernetBlaster, and EthernetBlaster II download cables.

The configuration data is shifted serially into the

DATA0 pin of the device.

If you are using the Quartus II programmer and the

CLKUSR pin is enabled, you do not need to provide a clock source for the pin to initialize your device.

Related Information

Parallel Flash Loader Megafunction User Guide

Cyclone V Device Datasheet

Provides more information about the PS configuration timing.

Passive Serial Single-Device Configuration Using an External Host

To configure a Cyclone V device, connect the device to an external host, as shown in the following figure.

Figure 7-12: Single Device PS Configuration Using an External Host

Memory

ADDR DATA0

V

CCPGM

V

CCPGM

10 kΩ 10 kΩ

External Host

(MAX II Device,

MAX V Device, or

Microprocessor

GND

Connect the resistor to a power supply that provides an acceptable input signal for the FPGA device. V

CCPGM meet the V

IH must be high enough to specification of the I/O on the device and the external host. Altera recommends powering up all the configuration system

I/Os with V

CCPGM

.

FPGA Device

CONF_DONE nSTATUS nCE nCEO N.C.

DATA0 nCONFIG

DCLK

MSEL[4..0]

You can leave the nCEO pin unconnected or use it as a user

I/O pin when it does not feed another device’s nCE pin.

For more information, refer to the MSEL pin settings.

Passive Serial Single-Device Configuration Using an Altera Download Cable

To configure a Cyclone V device, connect the device to a download cable, as shown in the following figure.

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Passive Serial Multi-Device Configuration

Figure 7-13: Single Device PS Configuration Using an Altera Download Cable

V

CCPGM

10 kΩ

V

CCPGM

10 kΩ

V

CCPGM

10 kΩ

FPGA Device

CONF_DONE nSTATUS

V

CCPGM

V

10 kΩ

CCPGM

10 kΩ

MSEL[4..0]

Connect the pull-up resistor to the same supply voltage (V

CCIO

) as the

USB-Blaster, ByteBlaster II,

EthernetBlaster, or EthernetBlaster II cable.

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GND nCE

DCLK

DATA0 nCONFIG nCEO N.C.

You only need the pull-up resistors on

DATA0 and DCLK if the download cable is the only configuration scheme used on your board. This ensures that

DATA0 and DCLK are not left floating after configuration. For example, if you are also using a MAX II device, MAX V device, or microprocessor, you do not need the pull-up resistors on DATA0 and DCLK.

For more information, refer to the MSEL pin settings.

Pin 1

Download Cable

10-Pin Male Header

(PS Mode)

V

CCIO

V

IO

GND

Shield

GND

In the USB-Blaster and

ByteBlaster II cables, this pin is connected to nCE when you use it for AS programming. Otherwise, this pin is a no connect.

Passive Serial Multi-Device Configuration

You can configure multiple Cyclone V devices that are connected in a chain.

Pin Connections and Guidelines

Observe the following pin connections and guidelines for this configuration setup:

• Tie the following pins of all devices in the chain together:

• nCONFIG

• nSTATUS

DCLK

DATA0

CONF_DONE

By tying the

CONF_DONE and nSTATUS pins together, the devices initialize and enter user mode at the same time. If any device in the chain detects an error, configuration stops for the entire chain and you must reconfigure all the devices. For example, if the first device in the chain flags an error on the nSTATUS pin, it resets the chain by pulling its nSTATUS pin low.

• If you are configuring the devices in the chain using the same configuration data, the devices must be of the same package and density.

Using Multiple Configuration Data

To configure multiple Cyclone V devices in a chain using multiple configuration data, connect the devices to the external host as shown in the following figure.

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Figure 7-14: Multiple Device PS Configuration when Both Devices Receive Different Sets of Configuration

Data

Memory

ADDR

DATA0

External Host

(MAX II Device,

MAX V Device, or

Microprocessor

V

CCPGM

V

CCPGM

Connect the resistor to a power supply that provides an acceptable input signal for the FPGA device. V

CCPGM must be high enough to meet the V

IH specification of the

I/O on the device and the external host. Altera recommends powering up all the configuration system I/Os with V

CCPGM

.

10 kΩ 10 kΩ

FPGA Device 1

V

CCPGM

FPGA Device 2

GND

CONF_DONE nSTATUS nCE

DATA0 nCONFIG

DCLK nCEO

MSEL[4..0]

10 kΩ

CONF_DONE nSTATUS nCE nCEO N.C.

DATA0 nCONFIG

DCLK MSEL[4..0]

You can leave the nCEO pin unconnected or use it as a user I/O pin when it does not feed another device’s nCE pin.

For more information, refer to the MSEL pin settings.

After a device completes configuration, its nCEO pin is released low to activate the nCE pin of the next device in the chain. Configuration automatically begins for the second device in one clock cycle.

Using One Configuration Data

To configure multiple Cyclone V devices in a chain using one configuration data, connect the devices to an external host, as shown in the following figure.

Figure 7-15: Multiple Device PS Configuration When Both Devices Receive the Same Set of Configuration

Data

Memory

ADDR DATA0

External Host

(MAX II Device,

MAX V Device, or

Microprocessor

V

CCPGM

V

CCPGM

10 kΩ 10 kΩ

Connect the resistor to a power supply that provides an acceptable input signal for the FPGA device. V

CCPGM must be high enough to meet the V

IH specification of the I/O on the device and the external host. Altera recommends powering up all the configuration system I/Os with V

CCPGM

.

FPGA Device 1 FPGA Device 2

GND

CONF_DONE nSTATUS nCE nCEO N.C.

GND

DATA0 nCONFIG

DCLK MSEL[4..0]

CONF_DONE nSTATUS nCE nCEO

DATA0 nCONFIG

DCLK MSEL[4..0]

N.C.

For more information, refer to the MSEL pin settings.

You can leave the nCEO pin unconnected or use it as a user I/O pin.

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Using PC Host and Download Cable

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The nCE pins of the devices in the chain are connected to GND, allowing configuration for these devices to begin and end at the same time.

Using PC Host and Download Cable

To configure multiple Cyclone V devices, connect the devices to a download cable, as shown in the following figure.

Figure 7-16: Multiple Device PS Configuration Using an Altera Download Cable

V

CCPGM

10 kΩ

You only need the pull-up resistors on

DATA0 and DCLK if the download cable is the only configuration scheme used on your board. This ensures that

DATA0 and DCLK are not left floating after configuration. For example, if you are also using a configuration device, you do not need the pull-up resistors on

DATA0 and DCLK.

V

CCPGM

10 kΩ

GND

For more information, refer to the MSEL pin settings.

FPGA Device 1

MSEL[4..0]

CONF_DONE nSTATUS

DCLK

V

CCPGM

V

CCPGM

10 kΩ

10 kΩ

V

10 kΩ (2)

CCPGM nCEO nCE

DATA0 nCONFIG

Download Cable

10-Pin Male Header

(PS Mode)

Pin 1

V

CCPGM

Connect the pull-up resistor to the same supply voltage (VCCIO) as the

USB-Blaster, ByteBlaster II,

EthernetBlaster, or EthernetBlaster II cable.

GND

V

IO

GND

In the USB-Blaster and

ByteBlaster II cables, this pin is connected to nCE when you use it for AS programming. Otherwise, this pin is a no connect.

FPGA Device 2

CONF_DONE nSTATUS

DCLK

MSEL[4..0] nCEO nCE

DATA0 nCONFIG

N.C.

When a device completes configuration, its nCEO pin is released low to activate the nCE pin of the next device.

Configuration automatically begins for the second device.

JTAG Configuration

In Cyclone V devices, JTAG instructions take precedence over other configuration schemes.

The Quartus II software generates an SRAM Object File (.sof) that you can use for JTAG configuration using a download cable in the Quartus II software programmer. Alternatively, you can use the JRunner software with .rbf or a JAM

Standard Test and Programming Language (STAPL) Format File (.jam) or JAM Byte

Code File (.jbc) with other third-party programmer tools.

Related Information

JTAG Boundary-Scan Testing in Cyclone V Devices

on page 9-1

Provides more information about JTAG boundary-scan testing.

Device Configuration Pins

on page 7-6

Provides more information about JTAG configuration pins.

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JTAG Single-Device Configuration

JTAG Secure Mode

on page 7-35

AN 425: Using the Command-Line Jam STAPL Solution for Device Programming

Cyclone V Device Datasheet

Provides more information about the JTAG configuration timing.

JTAG Boundary-Scan Testing in Cyclone V Devices

Programming Support for Jam STAPL Language

USB-Blaster Download Cable User Guide

ByteBlaster II Download Cable User Guide

EthernetBlaster Communications Cable User Guide

EthernetBlaster II Communications Cable User Guide

7-25

JTAG Single-Device Configuration

To configure a single device in a JTAG chain, the programming software sets the other devices to the bypass mode. A device in a bypass mode transfers the programming data from the

TDI pin to the

TDO pin through a single bypass register. The configuration data is available on the

TDO pin one clock cycle later.

The Quartus II software can use the

CONF_DONE pin to verify the completion of the configuration process through the JTAG port:

CONF_DONE pin is low—indicates that configuration has failed.

CONF_DONE pin is high—indicates that configuration was successful.

After the configuration data is transmitted serially using the JTAG

TDI port, the

TCK port is clocked an additional 1,222 cycles to perform device initialization.

To configure a Cyclone V device using a download cable, connect the device as shown in the following figure.

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JTAG Single-Device Configuration

Figure 7-17: JTAG Configuration of a Single Device Using a Download Cable

V

CCPGM

10 kΩ

V

CCPGM

10 kΩ

GND

N.C.

FPGA Device nCE nCEO

TCK

TDO nSTATUS

CONF_DONE nCONFIG

MSEL[4..0]

DCLK

TMS

TDI

If you only use the JTAG configuration, connect nCONFIG to V

CCPGM and MSEL[4..0] to GND.

Pull DCLK either high or low whichever is convenient on your board. If you are using JTAG in conjunction with another configuration scheme, connect MSEL[4..0], nCONFIG, and DCLK based on the selected configuration scheme.

V

CCPD

V

CCPD

1 kΩ

GND

The resistor value can vary from 1 kΩ to 10 kΩ. Perform signal integrity analysis to select the resistor value for your setup.

Connect the pull-up resistor V

CCPD

.

Download Cable

10-Pin Male Header

(JTAG Mode) (Top View)

Pin 1

V

CCPD

GND

GND

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To configure a Cyclone V device using a microprocessor, connect the device as shown in the following figure.

You can use JRunner as your software driver.

Figure 7-18: JTAG Configuration of a Single Device Using a Microprocessor

Memory

ADDR

DATA

Microprocessor

Connect the pull-up resistor to a supply that provides an acceptable input signal for all

FPGA devices in the chain. V

CCPGM high enough to meet the V

IH must be specification of the I/O on the device.

10 kΩ

FPGA Device nSTATUS

CONF_DONE

TDI

TCK

TMS

TDO

DCLK nCONFIG

MSEL[4..0] nCEO N.C.

nCE

GND

The microprocessor must use the same I/O standard as

V

CCPD to drive the JTAG pins.

V

CCPGM

V

CCPGM

10 kΩ

If you only use the JTAG configuration, connect nCONFIG to V

CCPGM and

MSEL[4..0] to GND. Pull DCLK high or low. If you are using JTAG in conjunction with another configuration scheme, set the MSEL[4..0] pins and tie nCONFIG and

DCLK based on the selected configuration scheme.

Related Information

AN 414: The JRunner Software Driver: An Embedded Solution for PLD JTAG Configuration

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JTAG Multi-Device Configuration

You can configure multiple devices in a JTAG chain.

JTAG Multi-Device Configuration

7-27

Pin Connections and Guidelines

Observe the following pin connections and guidelines for this configuration setup:

• Isolate the

CONF_DONE and nSTATUS pins to allow each device to enter user mode independently.

• One JTAG-compatible header is connected to several devices in a JTAG chain. The number of devices in the chain is limited only by the drive capability of the download cable.

• If you have four or more devices in a JTAG chain, buffer the

TCK

,

TDI

, and

TMS pins with an on-board buffer. You can also connect other Altera devices with JTAG support to the chain.

• JTAG-chain device programming is ideal when the system contains multiple devices or when testing your system using the JTAG boundary-scan testing (BST) circuitry.

Using a Download Cable

The following figure shows a multi-device JTAG configuration.

Figure 7-19: JTAG Configuration of Multiple Devices Using a Download Cable

Connect the pull-up resistor V

CCPD

.

If you only use the JTAG configuration, connect nCONFIG to VCCPGM and MSEL[4..0] to GND. Pull DCLK either high or low, whichever is convenient on your board. If you are using JTAG in conjunction with another configuration scheme, connect MSEL[4..0], nCONFIG, and DCLK based on the selected configuration scheme.

Download Cable

10-Pin Male Header

(JTAG Mode)

V

CCPD

Pin 1

V

CCPD

V

IO

V

CCPGM

FPGA Device

V

CCPGM

10 kΩ 10 kΩ nSTATUS nCONFIG

DCLK

CONF_DONE

MSEL[4..0] nCE

V

CCPD

GND

TDI

TMS TCK

TDO

V

CCPGM

FPGA Device

V

CCPGM

V

CCPGM

FPGA Device

GND

10 kΩ 10 kΩ nSTATUS nCONFIG

DCLK

CONF_DONE

MSEL[4..0] nCE

TDI

TMS TCK

TDO

GND

10 kΩ

V

CCPGM

10 kΩ nSTATUS nCONFIG

DCLK

CONF_DONE

MSEL[4..0] nCE

TDI

TMS TCK

TDO

1 kΩ

The resistor value can vary from 1 kΩ to 10 kΩ. Perform signal integrity analysis to select the resistor value for your setup.

Related Information

AN 656: Combining Multiple Configuration Schemes

Provides more information about combining JTAG configuration with other configuration schemes.

CONFIG_IO JTAG Instruction

The

CONFIO_IO

JTAG instruction allows you to configure the I/O buffers using the JTAG port before or during device configuration. When you issue this instruction, it interrupts configuration and allows you to issue all JTAG instructions. Otherwise, you can only issue the

BYPASS

,

IDCODE

, and

SAMPLE

JTAG instructions.

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Configuration Data Compression

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You can use the

CONFIO_IO

JTAG instruction to interrupt configuration and perform board-level testing.

After the board-level testing is completed, you must reconfigure your device. Use the following methods to reconfigure your device:

• JTAG interface—issue the

PULSE_NCONFIG

JTAG instruction.

• FPP, PS, or AS configuration scheme—pulse the nCONFIG pin low.

Configuration Data Compression

Cyclone V devices can receive compressed configuration bitstream and decompress the data in real-time during configuration. Preliminary data indicates that compression typically reduces the configuration file size by 30% to 55% depending on the design.

Decompression is supported in all configuration schemes except the JTAG configuration scheme.

You can enable compression before or after design compilation.

Enabling Compression Before Design Compilation

To enable compression before design compilation, follow these steps:

1. On the Assignment Menu, click Device.

2. Select your Cyclone V device and then click Device and Pin Options.

3. In the Device and Pin Options window, select Configuration under the Category list and turn on

Generate compressed bitstreams.

Enabling Compression After Design Compilation

To enable compression after design compilation, follow these steps:

1. On the File menu, click Convert Programming Files.

2. Select the programming file type (.pof, .sof, .hex, .hexout, .rbf, or .ttf). For POF output files, select a configuration device.

3. Under the Input files to convert list, select SOF Data.

4. Click Add File and select a Cyclone V device .sof.

5. Select the name of the file you added to the SOF Data area and click Properties.

6. Turn on the Compression check box.

Using Compression in Multi-Device Configuration

The following figure shows a chain of two Cyclone V devices. Compression is only enabled for the first device.

This setup is supported by the AS or PS multi-device configuration only.

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Remote System Upgrades

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Figure 7-20: Compressed and Uncompressed Serial Configuration Data in the Same Configuration File

Serial Configuration Data

Compressed

Configuration

Data

Decompression

Controller

FPGA

Device 1 nCE nCEO

Uncompressed

Configuration

Data nCE

FPGA

Device 2 nCEO

GND

N.C.

EPCS, EPCQ, or

External Host

For the FPP configuration scheme, a combination of compressed and uncompressed configuration in the same multi-device configuration chain is not allowed because of the difference on the

DCLK

-to-

DATA[] ratio.

Remote System Upgrades

Cyclone V devices contain dedicated remote system upgrade circuitry. You can use this feature to upgrade your system from a remote location.

Figure 7-21: Cyclone V Remote System Upgrade Block Diagram

1

Development

Location

2

Data

Data

Data

3

FPGA

Remote System

Upgrade Circuitry

Configuration

FPGA Configuration

4

Memory

You can design your system to manage remote upgrades of the application configuration images in the configuration device. The following list is the sequence of the remote system upgrade:

1. The logic (embedded processor or user logic) in the Cyclone V device receives a configuration image from a remote location. You can connect the device to the remote source using communication protocols such as TCP/IP, PCI, user datagram protocol (UDP), UART, or a proprietary interface.

2. The logic stores the configuration image in non-volatile configuration memory.

3. The logic starts reconfiguration cycle using the newly received configuration image.

4. When an error occurs, the circuitry detects the error, reverts to a safe configuration image, and provides error status to your design.

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Configuration Images

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Configuration Images

Each Cyclone V device in your system requires one factory image. The factory image is a user-defined configuration image that contains logic to perform the following:

• Processes errors based on the status provided by the dedicated remote system upgrade circuitry.

• Communicates with the remote host, receives new application images, and stores the images in the local non-volatile memory device.

• Determines the application image to load into the Cyclone V device.

• Enables or disables the user watchdog timer and loads its time-out value.

• Instructs the dedicated remote system upgrade circuitry to start a reconfiguration cycle.

You can also create one or more application images for the device. An application image contains selected functionalities to be implemented in the target device.

Store the images at the following locations in the EPCS or EPCQ devices:

• Factory configuration image—

PGM[23..0]

= 24'h000000 start address on the EPCS or EPCQ device.

• Application configuration image—any sector boundary. Altera recommends that you store only one image at one sector boundary.

Configuration Sequence in the Remote Update Mode

Figure 7-22: Transitions Between Factory and Application Configurations in Remote Update Mode

Configuration Error

Configuration

Error

Power Up

Factory

Configuration

(page 0)

Set Control Register and Reconfigure

Reload a

Different Application

Reload a

Different Application

Application 1

Configuration

Application

n

Configuration

Set Control Register and Reconfigure

Configuration Error

Related Information

Remote System Upgrade State Machine

on page 7-34

A detailed description of the configuration sequence in the remote update mode.

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Remote System Upgrade Circuitry

Remote System Upgrade Circuitry

7-31

The remote system upgrade circuitry contains the remote system upgrade registers, watchdog timer, and a state machine that controls these components.

Note:

If you are using the ALTREMOTE_UPDATE megafunction, the megafunction controls the

RU_DOUT

,

RU_SHIFTnLD

,

RU_CAPTnUPDT

,

RU_CLK

,

RU_DIN

,

RU_nCONFIG

, and

RU_nRSTIMER signals internally to perform all the related remote system upgrade operations.

Figure 7-23: Remote System Upgrade Circuitry

Internal Oscillator

Status Register (SR)

[4..0]

Control Register

[37..0]

Logic Array

Update Register

[37..0] update dout

Shift Register din dout

Bit [4..0] capture

Bit [37..0] din capture

Remote

System

Upgrade

State

Machine

Timeout

User

Watchdog

Timer

RU_DOUT clkout capture update

Logic Array

clkin

RU_SHIFTnLD RU_CAPTnUPDT

Logic Array

RU_CLK

RU_DIN RU_nCONFIG RU_nRSTIMER

Related Information

Cyclone V Device Datasheet

Provides more information about remote system upgrade circuitry timing specifications.

Enabling Remote System Upgrade Circuitry

To enable the remote system upgrade feature, follow these steps:

1. Select Active Serial x1/x4 or Configuration Device from the Configuration scheme list in the Configu-

ration page of the Device and Pin Options dialog box in the Quartus II software.

2. Select Remote from the Configuration mode list in the Configuration page of the Device and Pin Options dialog box in the Quartus II software.

Enabling this feature automatically turns on the Auto-restart configuration after error option.

Altera-provided ALTREMOTE_UPDATE megafunction provides a memory-like interface to the remote system upgrade circuitry and handles the shift register read and write protocol in the Cyclone V device logic.

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Remote System Upgrade Registers

Related Information

Remote System Upgrade (ALTREMOTE_UPDATE) Megafunction User Guide

Remote System Upgrade Registers

Table 7-6: Remote System Upgrade Registers

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Shift

Control

Update

Status

Register Description

Accessible by the logic array and clocked by

RU_CLK

.

Bits[4..0]

—Contents of the status register are shifted into these bits.

Bits[37..0]

—Contents of the update and control registers are shifted into these bits.

This register is clocked by the 10-MHz internal oscillator. The contents of this register are shifted to the shift register for the user logic in the application configuration to read. When reconfiguration is triggered, this register is updated with the contents of the update register.

This register is clocked by

RU_CLK

. The factory configuration updates this register by shifting data into the shift register and issuing an update. When reconfiguration is triggered, the contents of the update register are written to the control register.

After each reconfiguration, the remote system upgrade circuitry updates this register to indicate the event that triggered the reconfiguration. This register is clocked by the 10-MHz internal oscillator.

Related Information

Control Register

on page 7-33

Status Register

on page 7-33

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Control Register

Table 7-7: Control Register Bits

Bit Name

Control Register

7-33

0

1..24

25

3

4

AnF

PGM[0..23]

Wd_en nCONFIG

Wd

Reset

Value

(18)

1'b0

Description

Application not Factory bit. Indicates the configuration image type currently loaded in the device; 0 for factory image and 1 for application image. When this bit is 1, the access to the control register is limited to read only and the watchdog timer is enabled.

Factory configuration design must set this bit to 1 before triggering reconfiguration using an application configuration image.

24'h000000

1'b0

Upper 24 bits of AS configuration start address

(

StAdd[31..8]

), the 8 LSB are zero.

User watchdog timer enable bit. Set this bit to

1 to enable the watchdog timer.

12'b000000000000 User watchdog time-out value.

26..37

Wd_timer[11..0]

Status Register

Table 7-8: Status Register Bits

Bit Name

0

1

2

CRC nSTATUS

Core_nCONFIG

Reset

Value

(19)

1'b0

1'b0

1'b0

1'b0

1'b0

Description

When set to 1, indicates CRC error during application configuration.

When set to 1, indicates that nSTATUS is asserted by an external device due to error.

When set to 1, indicates that reconfiguration has been triggered by the logic array of the device.

When set to 1, indicates that nCONFIG is asserted.

When set to 1, indicates that the user watchdog time-out.

(18)

(19)

This is the default value after the device exits POR and during reconfiguration back to the factory configuration image.

After the device exits POR and power-up, the status register content is 5'b00000.

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Remote System Upgrade State Machine

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Remote System Upgrade State Machine

The operation of the remote system upgrade state machine is as follows:

1. After power-up, the remote system upgrade registers are reset to 0 and the factory configuration image is loaded.

2. The user logic sets the

AnF bit to 1 and the start address of the application image to be loaded. The user logic also writes the watchdog timer settings.

3. When the configuration reset (

RU_CONFIG

) goes low, the state machine updates the control register with the contents of the update register, and triggers reconfiguration using the application configuration image.

4. If error occurs, the state machine falls back to the factory image. The control and update registers are reset to 0, and the status register is updated with the error information.

5. After successful reconfiguration, the system stays in the application configuration.

User Watchdog Timer

The user watchdog timer prevents a faulty application configuration from stalling the device indefinitely.

You can use the timer to detect functional errors when an application configuration is successfully loaded into the device. The timer is automatically disabled in the factory configuration; enabled in the application configuration.

Note:

If you do not want this feature in the application configuration, you need to turn off this feature by setting the

Wd_en bit to 1'b0 in the update register during factory configuration user mode operation.

You cannot disable this feature in the application configuration.

The counter is 29 bits wide and has a maximum count value of 2

29

. When specifying the user watchdog timer value, specify only the most significant 12 bits. The granularity of the timer setting is 2

17 cycles. The cycle time is based on the frequency of the user watchdog timer internal oscillator.

The timer begins counting as soon as the application configuration enters user mode. When the timer expires, the remote system upgrade circuitry generates a time-out signal, updates the status register, and triggers the loading of the factory configuration image. To reset the time, assert

RU_nRSTIMER

.

Related Information

Cyclone V Device Datasheet

Provides more information about the operating range of the user watchdog internal oscillator's frequency.

Design Security

The Cyclone V design security feature supports the following capabilities:

• Enhanced built-in advanced encryption standard (AES) decryption block to support 256-bit key industry-standard design security algorithm (FIPS-197 Certified)

• Volatile and non-volatile key programming support

• Secure operation mode for both volatile and non-volatile key through tamper protection bit setting

• Limited accessible JTAG instruction during power-up in the JTAG secure mode

• Supports board-level testing

• Supports in-socket key programming for non-volatile key

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ALTCHIP_ID Megafunction

7-35

• Available in all configuration schemes except JTAG

• Supports both remote system upgrades and compression features

The Cyclone V design security feature provides the following security protection for your designs:

• Security against copying—the security key is securely stored in the Cyclone V device and cannot be read out through any interface. In addition, as configuration file read-back is not supported in Cyclone V devices, your design information cannot be copied.

• Security against reverse engineering—reverse engineering from an encrypted configuration file is very difficult and time consuming because the Cyclone V configuration file formats are proprietary and the file contains millions of bits that require specific decryption.

• Security against tampering—After you set the tamper protection bit, the Cyclone V device can only accept configuration files encrypted with the same key. Additionally, programming through the JTAG interface and configuration interface is blocked.

When you use compression with the design security feature, the configuration file is first compressed and then encrypted using the Quartus II software. During configuration, the device first decrypts and then decompresses the configuration file.

When you use design security with Cyclone V devices in an FPP configuration scheme, it requires a different

DCLK

-to-

DATA[] ratio.

ALTCHIP_ID Megafunction

The ALTCHIP_ID megafunction provides the following features:

• Acquiring the chip ID of an FPGA device.

• Allowing you to identify your device in your design as part of a security feature to protect your design from an unauthorized device.

Related Information

ALTCHIP_ID Megafunction User Guide

JTAG Secure Mode

When you enable the tamper-protection bit, Cyclone V devices are in the JTAG secure mode after power-up.

During this mode, many JTAG instructions are disabled. Cyclone V devices only allow mandatory JTAG

1149.1 instructions to be exercised. These JTAG instructions are

SAMPLE/PRELOAD

,

BYPASS

,

EXTEST

, and optional instructions such as

IDCODE and

SHIFT_EDERROR_REG

.

To enable the access of other JTAG instructions such as

USERCODE

,

HIGHZ

,

CLAMP

,

PULSE_nCONFIG

, and

CONFIG_IO

, you must issue the

UNLOCK instruction to deactivate the JTAG secure mode. You can issue the

LOCK instruction to put the device back into JTAG secure mode. You can only issue both the

LOCK and

UNLOCK

JTAG instructions during user mode.

Related Information

Supported JTAG Instruction

on page 9-3

Provides more information about JTAG binary instruction code related to the

LOCK and

UNLOCK instructions.

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Security Key Types

JTAG Boundary-Scan Testing in Cyclone V Devices

Provides more information about JTAG binary instruction code related to the

LOCK and

UNLOCK instructions.

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Security Key Types

Cyclone V devices offer two types of keys—volatile and non-volatile. The following table lists the differences between the volatile key and non-volatile keys.

Table 7-9: Security Key Types

Volatile

Key Types

Non-volatile

Key Programmability

• Reprogrammable

• Erasable

Power Supply for Key

Storage

Required external battery, V

CCBAT

(20)

Programming Method

On-board

One-time programming

Does not require an external battery

On-board and in-socket programming

(21)

Both non-volatile and volatile key programming offers protection from reverse engineering and copying. If you set the tamper-protection bit, the design is also protected from tampering.

You can perform key programming through the JTAG pins interface. Ensure that the nSTATUS pin is released high before any key-programming attempts.

Note:

To clear the volatile key, issue the

KEY_CLR_VREG

JTAG instruction. To verify the volatile key has been cleared, issue the

KEY_VERIFY

JTAG instruction.

Related Information

Supported JTAG Instruction

on page 9-3

Provides more information about the

KEY_CLR_VREG and

KEY_VERIFY instructions.

JTAG Boundary-Scan Testing in Cyclone V Devices

Provides more information about the

KEY_CLR_VREG and

KEY_VERIFY

JTAG instructions.

Cyclone V Device Family Pin Connection Guidelines

Provides more information about the V

CCBAT pin connection recommendations.

Cyclone V Device Datasheet

Provides more information about battery specifications.

(20)

(21)

V

CCBAT is a dedicated power supply for volatile key storage. V register regardless of the on-chip supply condition.

CCBAT

Third-party vendors offer in-socket programming.

continuously supplies power to the volatile

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Security Modes

Table 7-10: Supported Security Modes

Security Modes

7-37

Security Mode

No key

Volatile Key

Volatile Key with

Tamper Protection Bit

Set

Non-volatile Key

Non-volatile Key with

Tamper Protection Bit

Set

Set

Tamper Protection

Bit Setting

Device Accepts

Unencrypted File

Yes

Set

Yes

No

Device Accepts

Encrypted File

No

Yes

Yes

Yes

No

Yes

Yes

Security Level

Secure

Secure with tamper resistant

Secure

Secure with tamper resistant

The use of unencrypted configuration bitstream in the volatile key and non-volatile key security modes is supported for board-level testing only.

Note:

For the volatile key with tamper protection bit set security mode, Cyclone V devices do not accept the encrypted configuration file if the volatile key is erased. If the volatile key is erased and you want to reprogram the key, you must use the volatile key security mode.

Enabling the tamper protection bit disables the test mode in Cyclone V devices and disables programming through the JTAG interface. This process is irreversible and prevents Altera from carrying out failure analysis.

Design Security Implementation Steps

Figure 7-24: Design Security Implementation Steps

AES Key

Programming File

Step 3

FPGA Device

Key Storage

Step 1

256-bit User-Defined

Key

Quartus II Software

AES Encryptor

Step 1

Encrypted

Configuration

File

Step 2

AES Decryption

Step 4

Memory or

Configuration

Device

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To carry out secure configuration, follow these steps:

1. The Quartus II software generates the design security key programming file and encrypts the configuration data using the user-defined 256-bit security key.

2. Store the encrypted configuration file in the external memory.

3. Program the AES key programming file into the Cyclone V device through a JTAG interface.

4. Configure the Cyclone V device. At the system power-up, the external memory device sends the encrypted configuration file to the Cyclone V device.

Document Revision History

Date

January 2014

Version

2014.01.10

June 2013

May 2013

May 2013

December 2012

June 2012

November 2011

October 2011

2013.06.11

2013.05.10

2013.05.06

2012.12.28

2.0

1.1

1.0

Changes

• Added decompression support for the CvP configuration mode.

• Added a link to the FPGA Manager chapter for details about the MSEL pin settings for the HPS in SoC FPGA devices.

• Updated the Enabling Remote System Upgrade Circuitry section.

• Updated the Configuration Pin Summary section.

• Updated Figure 7-3, Figure 7-7, and Figure 7-14.

Updated the Configuration Error Handling section.

Removed support for active serial multi-device configuration using the same configuration data.

• Added link to the known document issues in the Knowledge Base.

• Added the ALTCHIP_ID megafunction section.

• Updated "Connection Setup for Programming the EPCS Using the JTAG

Interface" and "Connection Setup for Programming the EPCQ Using the JTAG Interface" figures.

• Added links for AS, PS, FPP, and JTAG configuration timing to device datasheet.

• Updated CvP support for partial reconfiguration in the Table 7-1:

Configuration Modes and Features Supported by Cyclone V Devices.

• Moved all links to the Related Information section of respective topics for easy reference.

• Added configuration modes and features for Cyclone V devices.

• Added

PR_REQUEST

,

PR_READY

,

PR_ERROR

, and

PR_DONE pins to

Configuration Pin Options table.

• Reorganized content and updated template.

Restructured the chapter.

Updated Table 7-4.

Initial release.

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This chapter describes the error detection features in Cyclone V devices. You can use these features to mitigate single event upset (SEU) or soft errors.

Related Information

Cyclone V Device Handbook: Known Issues

Lists the planned updates to the

Cyclone V Device Handbook

chapters.

Error Detection Features

The on-chip error detection CRC circuitry allows you to perform the following operations without any impact on the fitting or performance of the device:

• Auto-detection of CRC errors during configuration.

• Optional CRC error detection and identification in user mode.

• Testing of error detection functions by deliberately injecting errors through the JTAG interface.

8

Configuration Error Detection

When the Quartus II software generates the configuration bitstream, the software also computes a 16-bit

CRC value for each frame. A configuration bitstream can contain more than one CRC values depending on the number of data frames in the bitstream. The length of the data frame varies for each device.

When a data frame is loaded into the FPGA during configuration, the precomputed CRC value shifts into the CRC circuitry. At the same time, the CRC engine in the FPGA computes the CRC value for the data frame and compares it against the precomputed CRC value. If both CRC values do not match, the nSTATUS pin is set to low to indicate a configuration error.

You can test the capability of this feature by modifying the configuration bitstream or intentionally corrupting the bitstream during configuration.

User Mode Error Detection

In user mode, the contents of the configured CRAM bits may be affected by soft errors. These soft errors, which are caused by an ionizing particle, are not common in Altera devices. However, high-reliability

©

2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with

Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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Specifications

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applications that require the device to operate error-free may require that your designs account for these errors.

You can enable the error detection circuitry to detect soft errors. Each data frame stored in the CRAM contains a 32-bit precomputed CRC value. When this feature is enabled, the error detection circuitry continuously computes a 32-bit CRC value for each frame in the CRAM and compares the CRC value against the precomputed value.

• If the CRC values match, the 32-bit CRC signature in the syndrome register is set to zero to indicate that no error is detected.

• Otherwise, the resulting 32-bit CRC signature in the syndrome register is non-zero to indicate a CRC error. The

CRC_ERROR pin is pulled high, and the error type and location are identified.

Within a frame, the error detection circuitry can detect all single-, double-, triple-, quadruple-, and quintuplebit errors. When a single-bit or double-adjacent error is detected, the error detection circuitry reports the bit location and determines the error type for single-bit and double-adjacent errors. The probability of other error patterns is very low and the reporting of bit location is not guaranteed. The probability of more than five CRAM bits being flipped by soft errors is very low. In general, the probability of detection for all error patterns is 99.9999%. The process of error detection continues until the device is reset by setting the nCONFIG signal low.

Specifications

This section lists the EMR update interval, error detection frequencies, and CRC calculation time for error detection in user mode.

Minimum EMR Update Interval

The interval between each update of the error message register depends on the device and the frequency of the error detection clock. Using a lower clock frequency increases the interval time, hence increasing the time required to recover from a single event upset (SEU).

Table 8-1: Estimated Minimum EMR Update Interval in Cyclone V Devices

Variant

Cyclone E

Cyclone V GX

Member Code

C4

C5

C7

C9

A2

A4

A5

A7

A9

C3

Timing Interval (µs)

1.79

1.79

2.33

3.23

1.47

1.47

1.79

2.33

3.23

1.09

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Variant

Cyclone V GT

Cyclone V SE

Cyclone V SX

Cyclone V ST

Member Code

A2

A4

A5

A6

D5

D7

D9

C4

C5

C6

D5

D6

Error Detection Frequency

Timing Interval (µs)

1.79

2.33

3.23

1.77

1.77

2.31

2.31

1.77

2.31

2.31

2.31

2.31

8-3

Error Detection Frequency

You can control the speed of the error detection process by setting the division factor of the clock frequency in the Quartus II software. The divisor is 2 n

, where n can be any value listed in the following table.

The speed of the error detection process for each data frame is determined by the following equation:

Figure 8-1: Error Detection Frequency Equation

Error Detection Frequency =

Internal Oscillator Frequency

2 n

Table 8-2: Error Detection Frequency Range for Cyclone V Devices

The following table lists the frequencies and valid values of n.

Error Detection Frequency

Internal Oscillator Frequency

Maximum Minimum

100 MHz 100 MHz 390 kHz

n

0, 1, 2, 3, 4, 5, 6, 7, 8

Divisor Range

1 – 256

CRC Calculation Time

The time taken by the error detection circuitry to calculate the CRC for each frame is determined by the device in use and the frequency of the error detection clock.

You can calculate the minimum and maximum time for any number of divisor based on the following formula:

Maximum time (

n

) = 2^(

n

-8) * maximum time

Minimum time (

n

) = 2^

n

* minimum time where the range of

n

is from 0 to 8.

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Using Error Detection Features in User Mode

Table 8-3: CRC Calculation Time in Cyclone V Devices

The following table lists the minimum and maximum time taken to calculate the CRC value:

• The minimum time is derived using the maximum clock frequency with a divisor of 0.

• The maximum time is derived using the minimum clock frequency with a divisor of 8.

Variant

Cyclone E

Cyclone V GX

Cyclone V GT

Cyclone V SE

Cyclone V SX

Cyclone V ST

Member Code

C9

D5

D7

D9

C3

C4

C5

C7

A2

A4

A5

A7

A9

C4

C5

C6

D5

D6

A2

A4

A5

A6

Minimum Time (ms)

15

7

7

15

8

7

7

7

7

7

15

4

4

7

13

13

13

13

7

7

13

13

Maximum Time (s)

7.40

3.54

3.62

7.40

4.05

3.54

3.54

3.62

2.08

2.08

3.54

3.62

7.40

3.59

6.30

6.30

6.30

6.30

3.59

3.59

6.30

6.30

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Using Error Detection Features in User Mode

This section describes the pin, registers, process flow, and procedures for error detection in user mode.

Enabling Error Detection

To enable user mode error detection in the Quartus II software, follow these steps:

1. On the Assignments menu, click Device.

2. In the Device dialog box, click Device and Pin Options.

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CRC_ERROR Pin

8-5

3. In the Category list, click Error Detection CRC.

4. Turn on Enable Error Detection CRC_ERROR pin.

5. To set the

CRC_ERROR pin as output open drain, turn on Enable open drain on CRC_ERROR pin. Turning off this option sets the

CRC_ERROR pin as output.

6. In the Divide error check frequency by list, select a valid divisor.

7. Click OK.

CRC_ERROR Pin

Table 8-4: Pin Description

Pin Name

CRC_ERROR

Pin Type

I/O or output/ output open-drain

Description

An active-high signal, when driven high indicates that an error is detected in the CRAM bits. This pin is only used when you enable error detection in user mode. Otherwise, the pin is used as a user I/O pin.

When using the WYSIWYG function, you can route the crcerror port from the WYSIWYG atom to the dedicated

CRC_ERROR pin or any user I/O pin. To route the crcerror port to a user I/O pin, insert a D-type flipflop between them.

Error Detection Registers

This section describes the registers used in user mode.

Figure 8-2: Block Diagram for Error Detection in User Mode

The block diagram shows the registers and data flow in user mode.

Readback

Bitstream with

Expected CRC

Error

Detection

State

Machine

Control

Signals

32-bit Error Detection

CRC Calculation and

Error Search Engine

Syndrome

Register

Error

Message

Register

Error Injection

Block

Fault

Injection

Register

JTAG

Fault

Injection

Register

JTAG

Update

Register

JTAG

Shift

Register

User

Update

Register

User

Shift

Register

JTAG TDO General Routing

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Error Detection Registers

Table 8-5: Error Detection Registers

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Name

Syndrome register

Error message register (EMR)

JTAG update register

JTAG shift register

User update register

User shift register

JTAG fault injection register

Fault injection register

Width (Bits)

32

67

67

67

67

67

46

46

Description

Contains the 32-bit CRC signature calculated for the current frame. If the CRC value is 0, the

CRC_ERROR pin is driven low to indicate no error. Otherwise, the pin is pulled high.

Contains error details for single-bit and double-adjacent errors. The error detection circuitry updates this register each time the circuitry detects an error.

Figure 8-3

shows the fields in this register and

Table 8-6

lists the possible error types.

This register is automatically updated with the contents of the EMR one clock cycle after the content of this register is validated. The JTAG update register includes a clock enable, which must be asserted before its contents are written to the

JTAG shift register. This requirement ensures that the JTAG update register is not overwritten when its contents are being read by the JTAG shift register.

This register allows you to access the contents of the JTAG update register via the JTAG interface using the

SHIFT_

EDERROR_REG JTAG instruction.

This register is automatically updated with the contents of the EMR one clock cycle after the contents of this register are validated. The user update register includes a clock enable, which must be asserted before its contents are written to the user shift register. This requirement ensures that the user update register is not overwritten when its contents are being read by the user shift register.

This register allows user logic to access the contents of the user update register via the core interface.

You can use this register with the

EDERROR_INJECT JTAG instruction to inject errors in the bitstream.

Table 8-7

lists the fields in this register.

This register is updated with the contents of the JTAG fault injection register.

Figure 8-3: Error Message Register Map

MSB

Syndrome Frame Address

Double Word

Location

Byte Offset

32 bits 16 bits 10 bits 2 bits

Bit Offset

3 bits

LSB

Error Type

4 bits

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Table 8-6: Error Type in EMR

Error Detection Process

The following table lists the possible error types reported in the error type field in the EMR.

Error Type

Description

Bit 3 Bit 2 Bit 1 Bit 0

0

0

0

1

0

0

0

1

0

0

1

1

0

1

0

1

No CRC error.

Location of a single-bit error is identified.

Location of a double-adjacent error is identified.

Error types other than single-bit and double-adjacent errors.

Table 8-7: JTAG Fault Injection Register Map

Field Name

Error Byte

Value

Bit Range

31:0

Byte Location 41:32

Description

8-7

Contains the location of the bit error that corresponds to the error injection type to this field.

Contains the location of the injected error in the first data frame.

Error Type

Bit 45

0

0

0

Bit 44

45:42

Bit 43

0

0

0

0

0

1

Bit 42

0

1

0

Specifies the following error types.

No error

Single-bit error

Double adjacent error

Error Detection Process

When enabled, the user mode error detection process activates automatically when the FPGA enters user mode. The process continues to run until the device is reset even when an error is detected in the current frame.

Figure 8-4: Error Detection Process Flow in User Mode

Receive

Data Frame

Calculate and

Compare

CRC Values

Error

Detected?

Yes

Update Error

Message Register

(Overwrite)

No

Pull CRC_ERROR

Signal Low for

32 Clock Cycles

Search for

Error Location

Drive

CRC_ERROR

Signal High

Timing

The

CRC_ERROR pin is always driven low during CRC calculation for a minimum of 32 clock cycles. When an error occurs, the pin is driven high once the EMR is updated or 32 clock cycles have lapsed, whichever

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comes last. Therefore, you can start retrieving the contents of the EMR at the rising edge of the

CRC_ERROR pin. The pin stays high until the current frame is read and then driven low again for a minimum of 32 clock cycles. To ensure information integrity, complete the read operation within one frame of the CRC verification.

The following diagram shows the timing of these events.

Figure 8-5: Timing Requirements

Frame

Data Integrity

Read Data Frame

N

No CRC Error

N+1

CRC Error

N+2

CRC Error

N+3

No CRC Error

N+4

CRC Error

N+5

No CRC Error

CRC ERROR Pin

CRC Calculation

(minimum 32 clock cycles)

Read Error Message

Register (allowed time)

Read Error Message for frame N+1

Read Error Message for frame N+2

Read Error Message for frame N+4

Retrieving Error Information

You can retrieve the error information via the core interface or the JTAG interface using the

SHIFT_EDERROR_REG JTAG instruction.

Recovering from CRC Errors

The system that hosts the FPGA must control device reconfiguration. To recover from a CRC error, drive the nCONFIG signal low. The system waits for a safe time before reconfiguring the device. When reconfiguration completes successfully, the FPGA operates as intended.

Related Information

Error Detection Frequency

on page 8-3

Provides more information about the minimum and maximum error detection frequencies.

Minimum EMR Update Interval

on page 8-2

Provides more information about the duration of each Cyclone Vdevice.

Test Methodology of Error Detection and Recovery using CRC in Altera FPGA Devices

Provides more information about how to retrieve the error information.

Testing the Error Detection Block

You can inject errors into the configuration data to test the error detection block. This error injection methodology provides design verification and system fault tolerance characterization.

Testing via the JTAG Interface

You can intentionally inject single or double-adjacent errors into the configuration data using the

EDERROR_INJECT

JTAG instruction.

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Table 8-8: EDERROR_INJECT instruction

Document Revision History

8-9

JTAG Instruction

EDERROR_INJECT

Instruction Code

00 0001 0101

Description

Use this instruction to inject errors into the configuration data. This instruction controls the

JTAG fault injection register, which contains the error you want to inject into the bitstream.

You can only inject errors into the first frame of the configuration data. However, you can monitor the error information at any time. Altera recommends that you reconfigure the FPGA after the test completes.

Automating the Testing Process

You can automate the testing process by creating a Jam

™ file (.jam). Using this file, you can verify the CRC functionality in-system and on-the-fly without reconfiguring the device. You can then switch to the CRC circuitry to check for real errors caused by an SEU.

Related Information

Test Methodology of Error Detection and Recovery using CRC in Altera FPGA Devices

Provides more information about how to test the error detection block.

Document Revision History

Date

November 2013

Version

2013.11.12

May 2013

December 2012

June 2012

October 2011

2013.05.06

2012.12.28

2.0

1.0

Changes

• Updated the CRC Calculation Time section to include a formula to calculate the minimum and maximum time.

• Removed preliminary for the Minimum EMR Update Interval and CRC

Calculation Time.

• Removed related information for the Internal Scrubbing feature.

• Added link to the known document issues in the Knowledge Base.

• Updated the minimum EMR Update Interval and CRC Calculation

Time for Cyclone V E, Cyclone V GX, and Cyclone V GT devices.

• Moved all links to the Related Information section of respective topics for easy reference.

• Updated the width of the JTAG fault injection and fault injection registers.

• Added the “Basic Description”, “Error Detection Features”, “Types of

Error Detection”, “Error Detection Components”, “Using the Error

Detection Feature”, and “Testing the Error Detection Block” sections.

• Updated Table 8–4, Table 8–5, and Table 8–6.

• Restructured the chapter.

Initial release.

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This chapter describes the boundary-scan test (BST) features in Cyclone V devices.

Related Information

JTAG Configuration

on page 7-24

Provides more information about JTAG configuration.

Cyclone V Device Handbook: Known Issues

Lists the planned updates to the

Cyclone V Device Handbook

chapters.

BST Operation Control

Cyclone V devices support IEEE Std. 1149.1 BST. You can perform BST on Cyclone V devices before, after, and during configuration.

IDCODE

The

IDCODE is unique for each Cyclone V device. Use this code to identify the devices in a JTAG chain.

©

2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with

Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO

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Registered www.altera.com

101 Innovation Drive, San Jose, CA 95134

9-2

IDCODE

Table 9-1: IDCODE Information for Cyclone V Devices

Variant

Cyclone V E

Cyclone V GX

Cyclone V GT

Cyclone V SE

Member Code

A2

A4

A5

A7

A9

C3

C4

C5

C7

C9

D5

D7

D9

A2

A4

A5

A6

IDCODE (32 Bits)

Version (4 Bits)

0000

Part Number

(16 Bits)

Manufacture

Identity

(11 Bits)

0010 1011 0001

0101

000 0110 1110

0000

0000

0000

0010 1011 0000

0101

000 0110 1110

0010 1011 0010

0010

000 0110 1110

0010 1011 0001

0011

000 0110 1110

0000

0000

0000

0000

0000

0000

0010 1011 0001

0100

000 0110 1110

0010 1011 0000

0001

000 0110 1110

0010 1011 0001

0010

000 0110 1110

0010 1011 0000

0010

000 0110 1110

0010 1011 0000

0011

000 0110 1110

0010 1011 0000

0100

000 0110 1110

0000

0000

0000

0000

0000

0000

0000

0010 1011 0000

0010

000 0110 1110

0010 1011 0000

0011

000 0110 1110

0010 1011 0000

0100

000 0110 1110

0010 1101 0001

0001

000 0110 1110

0010 1101 0000

0001

000 0110 1110

0010 1101 0001

0010

000 0110 1110

0010 1101 0000

0010

000 0110 1110

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LSB (1 Bit)

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1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

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Variant

Cyclone V SX

Cyclone V ST

Supported JTAG Instruction

Member Code

C2

C4

C5

C6

D5

D6

Version (4 Bits)

0000

0000

0000

0000

IDCODE (32 Bits)

Part Number

(16 Bits)

Manufacture

Identity

(11 Bits)

0010 1101 0001

0001

000 0110 1110

0010 1101 0000

0001

000 0110 1110

0010 1101 0001

0010

000 0110 1110

0010 1101 0000

0010

000 0110 1110

0000

0000

0010 1101 0001

0010

000 0110 1110

0010 1101 0000

0010

000 0110 1110

LSB (1 Bit)

1

1

1

1

1

1

9-3

Supported JTAG Instruction

Table 9-2: JTAG Instructions Supported by Cyclone V Devices

JTAG Instruction

SAMPLE

/

PRELOAD

Instruction Code

00 0000 0101

Description

• Allows you to capture and examine a snapshot of signals at the device pins during normal device operation and permits an initial data pattern to be an output at the device pins.

• Use this instruction to preload the test data into the update registers before loading the

EXTEST instruction.

• Used by the SignalTap

II

Embedded Logic Analyzer.

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Supported JTAG Instruction

JTAG Instruction

EXTEST

BYPASS

USERCODE

IDCODE

Instruction Code

00 0000 1111

11 1111 1111

00 0000 0111

00 0000 0110

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Description

• Allows you to test the external circuit and board-level interconnects by forcing a test pattern at the output pins, and capturing the test results at the input pins. Forcing known logic high and low levels on output pins allows you to detect opens and shorts at the pins of any device in the scan chain.

• The high-impedance state of

EXTEST is overridden by bus hold and weak pull-up resistor features.

Places the 1-bit bypass register between the

TDI and

TDO pins. During normal device operation, the 1-bit bypass register allows the BST data to pass synchronously through the selected devices to adjacent devices.

• Examines the user electronic signature (UES) within the devices along a JTAG chain.

• Selects the 32-bit

USERCODE register and places it between the

TDI and

TDO pins to allow serial shifting of

USERCODE out of

TDO

.

• The UES value is set to default value before configuration and is only user-defined after the device is configured.

• Identifies the devices in a JTAG chain. If you select

IDCODE

, the device identification register is loaded with the 32-bit vendor-defined identification code.

• Selects the

IDCODE register and places it between the

TDI and

TDO pins to allow serial shifting of

IDCODE out of

TDO

.

IDCODE is the default instruction at power up and in the

TAP RESET state. Without loading any instructions, you can go to the

SHIFT_DR state and shift out the JTAG device

ID.

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HIGHZ

JTAG Instruction

CLAMP

PULSE_NCONFIG

CONFIG_IO

Instruction Code

00 0000 1011

00 0000 1010

00 0000 0001

00 0000 1101

Supported JTAG Instruction

9-5

Description

• Sets all user I/O pins to an inactive drive state.

• Places the 1-bit bypass register between the

TDI and

TDO pins.

During normal operation, the 1-bit bypass register allows the BST data to pass synchronously through the selected devices to adjacent devices while tri-stating all I/O pins until a new JTAG instruction is executed.

• If you are testing the device after configuration, the programmable weak pull-up resistor or the bus hold feature overrides the

HIGHZ value at the pin.

• Places the 1-bit bypass register between the

TDI and

TDO pins.

During normal operation, the 1-bit bypass register allows the BST data to pass synchronously through the selected devices to adjacent devices while holding the I/O pins to a state defined by the data in the boundary-scan register.

• If you are testing the device after configuration, the programmable weak pull-up resistor or the bus hold feature overrides the

CLAMP value at the pin. The

CLAMP value is the value stored in the update register of the boundary-scan cell

(BSC).

Emulates pulsing the nCONFIG pin low to trigger reconfiguration even though the physical pin is not affected.

Allows I/O reconfiguration (after or during reconfigurations) through the

JTAG ports using I/O configuration shift register (IOCSR) for JTAG testing.

You can issue the

CONFIG_IO instruction only after the nSTATUS pin goes high.

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LOCK

JTAG Secure Mode

UNLOCK

JTAG Instruction

KEY_CLR_VREG

KEY_VERIFY

Instruction Code

01 1111 0000

11 0011 0001

00 0010 1001

00 0001 0011

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Description

Put the device in JTAG secure mode.

In this mode, only

BYPASS

,

SAMPLE

/

PRELOAD

,

EXTEST

,

IDCODE

,

SHIFT_EDERROR_REG

, and

UNLOCK instructions are supported. This instruction can only be accessed through JTAG core access in user mode. It cannot be accessed through external JTAG pins in test or user mode.

Release the device from the JTAG secure mode to enable access to all other JTAG instructions. This instruction can only be accessed through

JTAG core access in user mode. It cannot be accessed through external

JTAG pins in test or user mode.

Clears the volatile key.

Verifies the non-volatile key has been cleared.

Note:

If the device is in a reset state and the nCONFIG or nSTATUS signal is low, the device

IDCODE might not be read correctly. To read the device

IDCODE correctly, you must issue the

IDCODE

JTAG instruction only when the nCONFIG and nSTATUS signals are high.

Related Information

JTAG Secure Mode

on page 7-35

Provides more information about

PULSE_NCONFIG

,

CONFIG_IO

,

LOCK

, and

UNLOCK

JTAG instructions.

Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices

Provides more information about

PULSE_NCONFIG

,

CONFIG_IO

,

LOCK

, and

UNLOCK

JTAG instructions.

JTAG Secure Mode

If you enable the tamper-protection bit, the Cyclone V device is in JTAG secure mode after power up. In the JTAG secure mode, the JTAG pins support only the

BYPASS

,

SAMPLE

/

PRELOAD

,

EXTEST

,

IDCODE

,

SHIFT_EDERROR_REG

, and

UNLOCK instructions. Issue the

UNLOCK

JTAG instruction to enable support for other JTAG instructions.

JTAG Private Instruction

Caution:

Never invoke the following instruction codes. These instructions can damage and render the device unusable:

• 1100010000

• 0011001001

• 1100010011

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I/O Voltage for JTAG Operation

9-7

• 1100010111

• 0111100000

• 1110110011

• 0011100101

• 0011100110

• 0000101010

• 0000101011

I/O Voltage for JTAG Operation

The Cyclone V device operating in IEEE Std. 1149.1 BST mode uses four dedicated JTAG pins—

TDI

,

TDO

,

TMS

, and

TCK

. Cyclone V devices do not support the optional

TRST pin.

The

TCK pin has an internal weak pull-down resistor, while the

TDI and

TMS pins have internal weak pull-up resistors. The 3.3-, 3.0-, or 2.5-V V

CCPD supply of I/O bank 3A powers the user I/O pins are tri-stated during JTAG configuration.

TDO

,

TDI

,

TMS

, and

TCK pins. All

The JTAG chain supports several different devices. Use the supported

TDO and

TDI voltage combinations listed in the following table if the JTAG chain contains devices that have different V voltage level of the

TDO pin must meet the specification of the

TDI pin it drives.

CCIO levels. The output

Table 9-3: Supported TDO and TDI Voltage Combinations

The TDO output buffer for V

CCPD of 2.5 V meets V

OH of 3.3 V or 3.0 V meets V

(MIN) of 2.0 V.

OH

(MIN) of 2.4 V, and the TDO output buffer for V

CCPD

Device

TDI Input Buffer

Power (V)

V

CCPD

= 3.3 V

Cyclone V TDO V

CCPD

V

CCPD

= 3.0 V V

CCPD

= 2.5 V

Cyclone V

V

CCPD

= 3.3

V

CCPD

= 3.0

Yes

Yes

Yes

Yes

Yes

Yes

Non-Cyclone V

(22)

V

CCPD

= 2.5

V

CC

= 3.3

V

CC

= 2.5

V

CC

= 1.8

V

CC

= 1.5

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Performing BST

You can issue

BYPASS

,

IDCODE

, and

SAMPLE

JTAG instructions before, after, or during configuration without having to interrupt configuration.

To issue other JTAG instructions, follow these guidelines:

• To perform testing before configuration, hold the nCONFIG pin low.

(22)

The input buffer must be tolerant to the TDO V

CCPD voltage.

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Enabling and Disabling IEEE Std. 1149.1 BST Circuitry

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• To perform BST during configuration, issue

CONFIG_IO

JTAG instruction to interrupt configuration.

While configuration is interrupted, you can issue other JTAG instructions to perform BST. After BST is completed, issue the

PULSE_CONFIG

JTAG instruction or pulse nCONFIG low to reconfigure the device.

The chip-wide reset

(DEV_CLRn) and chip-wide output enable

(DEV_OE) pins on Cyclone V devices do not affect JTAG boundary-scan or configuration operations. Toggling these pins does not disrupt BST operation

(other than the expected BST behavior).

If you design a board for JTAG configuration of Cyclone V devices, consider the connections for the dedicated configuration pins.

Note:

Do not cascade JTAG chains for FPGA and HPS together when you are performing BST. The JTAG for HPS does not support BST.

Related Information

Cyclone V Device Family Pin Connection Guidelines

Provides more information about pin connections.

Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices

Provides more information about JTAG configuration.

Cyclone V Device Datasheet

Provides more information about JTAG configuration timing.

Enabling and Disabling IEEE Std. 1149.1 BST Circuitry

The IEEE Std. 1149.1 BST circuitry is enabled after the Cyclone V device powers up. However for Cyclone V

SoC FPGAs, you must power up both HPS and FPGA to perform BST.

To ensure that you do not inadvertently enable the IEEE Std. 1149.1 circuitry when it is not required, disable the circuitry permanently with pin connections as listed in the following table.

Table 9-4: Pin Connections to Permanently Disable the IEEE Std. 1149.1 Circuitry for Cyclone V Devices

JTAG Pins

(23)

TMS

TCK

TDI

TDO

Connection for Disabling

V

CCPD supply of Bank 3A

GND

V

CCPD supply of Bank 3A

Leave open

(23)

The JTAG pins are dedicated. Software option is not available to disable JTAG in Cyclone V devices.

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Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing

9-9

Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing

Consider the following guidelines when you perform BST with IEEE Std. 1149.1 devices:

• If the “10...” pattern does not shift out of the instruction register through the

TDO pin during the first clock cycle of the

SHIFT_IR state, the TAP controller did not reach the proper state. To solve this problem, try one of the following procedures:

• Verify that the TAP controller has reached the

SHIFT_IR state correctly. To advance the TAP controller to the

SHIFT_IR state, return to the

RESET state and send the

01100 code to the

TMS pin.

• Check the connections to the

VCC

,

GND

,

JTAG

, and dedicated configuration pins on the device.

• Perform a

SAMPLE/PRELOAD test cycle before the first

EXTEST test cycle to ensure that known data is present at the device pins when you enter

EXTEST mode. If the

OEJ update register contains 0, the data in the

OUTJ update register is driven out. The state must be known and correct to avoid contention with other devices in the system.

• Do not perform

EXTEST testing during in-circuit reconfiguration because

EXTEST is not supported during in-circuit reconfiguration. To perform testing, wait for the configuration to complete or issue the

CONFIG_IO instruction to interrupt configuration.

• After configuration, you cannot test any pins in a differential pin pair. To perform BST after configuration, edit and redefine the BSC group that correspond to these differential pin pairs as an internal cell.

Related Information

IEEE 1149.1 BSDL Files

Provides more information about BSC group definitions.

IEEE Std. 1149.1 Boundary-Scan Register

The boundary-scan register is a large serial shift register that uses the

TDI pin as an input and the

TDO pin as an output. The boundary-scan register consists of 3-bit peripheral elements that are associated with

Cyclone V I/O pins. You can use the boundary-scan register to test external pin connections or to capture internal data.

JTAG Boundary-Scan Testing in Cyclone V Devices

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Boundary-Scan Cells of a Cyclone V Device I/O Pin

Figure 9-1: Boundary-Scan Register

This figure shows how test data is serially shifted around the periphery of the IEEE Std. 1149.1 device.

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Internal Logic

Each peripheral element is either an

I/O pin, dedicated input pin, or dedicated configuration pin.

TAP Controller

TDI TMS TCK TDO

Boundary-Scan Cells of a Cyclone V Device I/O Pin

The Cyclone V device 3-bit BSC consists of the following registers:

• Capture registers—Connect to internal device data through the

OUTJ

,

OEJ

, and

PIN_IN signals.

• Update registers—Connect to external data through the

PIN_OUT and

PIN_OE signals.

The TAP controller generates the global control signals for the IEEE Std. 1149.1 BST registers ( shift

, clock

, and update

) internally. A decode of the instruction register generates the

MODE signal.

The data signal path for the boundary-scan register runs from the serial data in (

SDI

) signal to the serial data out (

SDO

) signal. The scan register begins at the

TDI pin and ends at the

TDO pin of the device.

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Boundary-Scan Cells of a Cyclone V Device I/O Pin

Figure 9-2: User I/O BSC with IEEE Std. 1149.1 BST Circuitry for Cyclone V Devices

Capture

Registers

SDO

Update

Registers

INJ

PIN_IN

0

1

D Q

INPUT

D

INPUT

Q

0

1

9-11

From or

To Device

I/O Cell

Circuitry

And/Or

Logic

Array

OEJ

OUTJ

0

1

D

OE

Q D

OE

Q

VCC

0

1

0

1

PIN_OE

0

1

D Q

OUTPUT

D Q

OUTPUT

0

1

PIN_OUT

Output

Buffer

Pin

SDI

SHIFT CLOCK UPDATE HIGHZ MODE

Global

Signals

Note:

TDI

,

TDO

,

TMS

, and

TCK pins, all

VCC and

GND pin types, and

VREF pins do not have BSCs.

Table 9-5: Boundary-Scan Cell Descriptions for Cyclone V Devices

This table lists the capture and update register capabilities of all BSCs within Cyclone V devices.

Captures Drives

Pin Type

Output

Capture

Register

OE Capture

Register

Input

Capture

Register

Output

Update

Register

OE Update

Register

Input

Update

Register

User I/O pins

Dedicated clock input

OUTJ

0

OEJ

1

PIN_IN

PIN_IN

PIN_OUT

No

Connect

(N.C.)

PIN_OE

N.C.

INJ

N.C.

Dedicated input

(24)

0 1

PIN_IN

N.C.

N.C.

N.C.

Comments

PIN_IN drives to the clock network or logic array

PIN_IN drives to the control logic

(24)

This includes the

PLL_ENA

,

VCCSEL

,

PORSEL

, nIO_PULLUP

, nCONFIG

,

MSEL0

,

MSEL1

,

MSEL2

,

MSEL3

,

MSEL4

, and nCE pins.

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Document Revision History

Pin Type

Dedicated bidirectional

(open drain)

(25)

0

Output

Capture

Register

Dedicated bidirectional

(26)

OUTJ

Captures

OE Capture

Register

OEJ

Input

Capture

Register

PIN_IN

OEJ PIN_IN

Dedicated output

(27)

OUTJ

0 0

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Output

Update

Register

N.C.

Drives

OE Update

Register

N.C.

Input

Update

Register

N.C.

Comments

PIN_IN drives to the configuration control

N.C.

N.C.

N.C.

N.C.

N.C.

N.C.

PIN_IN drives to the configuration control and

OUTJ drives to the output buffer

OUTJ drives to the output buffer

Document Revision History

Date

January 2014

Version

2014.01.10

May 2013

December 2012

June 2012

October 2011

2013.05.06

2012.12.28

2.0

1.0

Changes

• Added a note to the Performing BST section.

• Updated the

KEY_CLR_VREG

JTAG instruction.

• Added link to the known document issues in the Knowledge Base.

• Moved all links to the Related Information section of respective topics for easy reference.

Reorganized content and updated template.

• Restructured the chapter.

• Updated Table 9-1 and Table 9-2.

Initial release.

(25)

(26)

(27)

This includes the

CONF_DONE and nSTATUS pins.

This includes the

DCLK pin.

This includes the nCEO pin.

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Power Management in Cyclone V Devices

10

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This chapter describes the hot-socketing feature, power-on reset (POR) requirements, and their implementation in Cyclone V devices.

Related Information

Cyclone V Device Handbook: Known Issues

Lists the planned updates to the

Cyclone V Device Handbook

chapters.

PowerPlay Power Analysis

Provides more information about the Quartus

®

II PowerPlay Power Analyzer tool.

Cyclone V Device Datasheet

Provides more information about the recommended operating conditions of each power supply.

Cyclone V Device Family Pin Connection Guidelines

Provides detailed information about power supply pin connection guidelines and power regulator sharing.

Board Design Resource Center

Provides detailed information about power supply design requirements.

Power Consumption

The total power consumption of a Cyclone V device consists of the following components:

• Static power—the power that the configured device consumes when powered up but no clocks are operating.

• Dynamic power— the additional power consumption of the device due to signal activity or toggling.

Dynamic Power Equation

Figure 10-1: Dynamic Power

The following equation shows how to calculate dynamic power where P is power, C is the load capacitance, and V is the supply voltage level.

©

2014 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with

Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO

9001:2008

Registered www.altera.com

101 Innovation Drive, San Jose, CA 95134

10-2

Hot-Socketing Feature

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The equation shows that power is design-dependent and is determined by the operating frequency of your design. Cyclone V devices minimize static and dynamic power using advanced process optimizations. This technology allows Cyclone V designs to meet specific performance requirements with the lowest possible power.

Hot-Socketing Feature

Cyclone V devices support hot socketing—also known as hot plug-in or hot swap.

The hot-socketing circuitry monitors the V

CCIO

, V

CCPD

, and V

CC banks.

power supplies and all V

CCIO and V

CCPD

You can power up or power down these power supplies in any sequence.

During the hot-socketing operation, the I/O pin capacitance is less than 15 pF and the clock pin capacitance is less than 20 pF.

The hot-socketing capability removes some of the difficulty that designers face when using the Cyclone V devices on PCBs that contain a mixture of devices with different voltage requirements.

The hot-socketing capability in Cyclone V devices provides the following advantages:

• You can drive signals into the I/O, dedicated input, and dedicated clock pins before or during power up or power down without damaging the device. External input signals to the I/O pins of the unpowered device will not power the power supplies through internal paths within the device.

• The output buffers are tri-stated during system power up or power down. Because the Cyclone V device does not drive signals out before or during power up, the device does not affect the other operating buses.

• You can insert or remove a Cyclone V device from a powered-up system board without damaging or interfering with the system board's operation. This capability allows you to avoid sinking current through the device signal pins to the device power supply, which can create a direct connection to GND that causes power supply failures.

• During hot socketing, Cyclone V devices are immune to latch up that can occur when a device is hotsocketed into an active system.

Altera uses GND as a reference for hot-socketing and I/O buffer circuitry designs. To ensure proper operation, connect GND between boards before connecting the power supplies. This prevents GND on your board from being pulled up inadvertently by a path to power through other components on your board. A pulled up GND could otherwise cause an out-of-specification I/O voltage or over current condition in the Altera device.

Related Information

Cyclone V Device Datasheet

Provides details about the Cyclone V hot-socketing specifications.

Hot-Socketing Implementation

The hot-socketing feature tri-state the output buffer during power up and power down of the power supplies.

When these power supplies are below the threshold voltage, the hot-socketing circuitry generates an internal

HOTSCKT signal.

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Hot-Socketing Implementation

10-3

Hot-socketing circuitry prevents excess I/O leakage during power up. When the voltage ramps up very slowly, I/O leakage is still relatively low, even after the release of the POR signal and configuration is complete.

Note:

The output buffer cannot flip from the state set by the hot-socketing circuitry at very low voltage.

To allow the

CONF_DONE and

nSTATUS pins to operate during configuration, the hot-socketing feature is not applied to these configuration pins. Therefore, these pins will drive out during power up and power down.

Figure 10-2: Hot-Socketing Circuitry for Cyclone V Devices

Power-On

Reset (POR)

Monitor

V

CCIO

Weak

Pull-Up

Resistor

PAD

R

Voltage

Tolerance

Control

Output Enable

Hot-Socket

Output

Pre-Driver

Input Buffer to Logic Array

The POR circuitry monitors the voltage level of the power supplies and keeps the I/O pins tri-stated until the device is in user mode. The weak pull-up resistor (R) in the Cyclone V input/output element (IOE) is enabled during configuration download to keep the I/O pins from floating.

The 3.3-V tolerance control circuit allows the I/O pins to be driven by 3.3 V before the power supplies are powered and prevents the I/O pins from driving out before the device enters user mode.

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Power-Up Sequence

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Power-Up Sequence

Figure 10-3: Power-Up Sequence Recommendation for Cyclone V Devices

To ensure the minimum current draw during device power up for Cyclone V devices, follow the power-up sequence recommendations as shown in the following figure.

Power up V

CCBAT at any time. Ramp up the power rails in Group 1 to a minimum of 80% of their full rail before Group 2 starts. Power up V

CCE_GXB and V

CCL_GXB together with V

CC

.

Group 1

1.1V

VCC

VCCE_GXB

VCCL_GXB

VCC_HPS

Group 2

2.5V

VCCPGM

VCCIO

VCCPD

VCCA_FPLL

VCCH_GXB

VCC_AUX

VCCPD_HPS

VCCIO_HPS

VCCRSTCLK_HPS

VCCPLL_HPS

VCC_AUX_SHARED

Power rails that are only available with

Cyclone V SX, SE, and ST devices.

This table lists the current transient that you may observe at the indicated power rails after powering up the

Cyclone V device, and before configuration starts. These transients have a finite duration bounded by the time at which the device enters configuration mode. For Cyclone V SX, SE and ST devices, you may observe the current transient in the following table after powering up the device, and before all the power supplies reach the recommended operating range.

For details about the minimum current requirements, refer to the PowerPlay Early Power Estimator (EPE), and compare to the information listed in the following table. If the current transient exceeds the minimum current requirements in the PowerPlay EPE, you need to take the information into consideration for your power regulator design.

Table 10-1: Maximum Power Supply Current Transient and Typical Duration

Power Rail Typical Duration (µs)

(28)

V

CCPD

(29)

,

(30)

V

CCIO

(31)

,

(30)

V

CC_AUX

(32)

V

CC

(32)

Maximum Power Supply

Current Transient (mA)

1000

250

400

350

50

200

10

100

(28)

(29)

(30)

(31)

(32)

Only typical duration is provided as it may vary on the board design.

You may observe the current transient at V

CCPD only when you do not follow the recommended power-up sequence. To avoid the current transient at V

CCPD

, follow the recommended power-up sequence.

The maximum current for V

CCIO and V

CCPD applies to all voltage levels supported by the Cyclone V device.

You may observe the current transient at V

CCIO if you power up V

CCIO before V

CCPD

. To avoid the current transient at V

CCIO

, follow the recommended power-up sequence by powering up V

You may observe the current transient at V

CC_AUX

, V

CC

, and V

CC_HPS

CCIO and V

CCPD with any power-up sequence.

together.

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Power-On Reset Circuitry

Typical Duration (µs)

(28)

Power Rail

V

CCPD_HPS

(33)

,

(34)

,

(35)

V

CCIO_HPS

(33)

,

(36)

,

(35)

V

CC_HPS

(32)

,

(33)

Maximum Power Supply

Current Transient (mA)

400

100

420

Related Information

PowerPlay Early Power Estimators (EPE) and Power Analyzer

Provides more information about the PowerPlay EPE support for Cyclone V devices.

50

200

100

10-5

Power-On Reset Circuitry

The POR circuitry keeps the Cyclone V device in the reset state until the power supply outputs are within the recommended operating range.

A POR event occurs when you power up the Cyclone V device until the power supplies reach the recommended operating range within the maximum power supply ramp time, t

RAMP

. If t

RAMP is not met, the Cyclone V device I/O pins and programming registers remain tri-stated, during which device configuration could fail.

(28)

(33)

(34)

(35)

(36)

Only typical duration is provided as it may vary on the board design.

These power rails are only available on Cyclone V SX, SE and ST devices.

You may observe the current transient at V

CCPD_HPS only when you do not follow the recommended powerup sequence. To avoid the current transient at V

CCPD_HPS

, follow the recommended power-up sequence.

The maximum current for V

CCIO_HPS device.

and V

CCPD_HPS applies to all voltage levels supported by the Cyclone V

You may observe the current transient at V

CCIO_HPS and V

CCPD_HPS if you power up V

CCIO_HPS before V

CCPD_HPS

. To avoid the current transient at V

CCIO_HPS

, follow the recommended power-up sequence by powering up V together.

CCIO_HPS

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Power-On Reset Circuitry

Figure 10-4: Relationship Between t

RAMP and POR Delay

Volts

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POR trip level first power supply last power supply t

RAMP

POR delay configuration time

Time

The Cyclone V POR circuitry uses an individual detecting circuitry to monitor each of the configuration-related power supplies independently. The main POR circuitry is gated by the outputs of all the individual detectors. The main POR signal is asserted when the power starts to ramp up. This signal is released after the last ramp-up power reaches the POR trip level during power up.

In user mode, the main POR signal is asserted when any of the monitored power goes below its POR trip level. Asserting the POR signal forces the device into the reset state.

The POR circuitry checks the functionality of the I/O level shifters powered by the V

CCPD and V

CCPGM power supplies during power-up mode. The main POR circuitry waits for all the individual POR circuitries to release the POR signal before allowing the control block to start programming the device.

Figure 10-5: Simplified POR Diagram for Cyclone V Devices

V

CC

V

CC

POR

V

CC_AUX

V

CC_AUX

POR

Modular

Main POR

Main POR

V

CCPD

V

CCPGM

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Power Supplies Monitored and Not Monitored by the POR Circuitry

Related Information

Cyclone V Device Datasheet

Provides more information about the POR delay specification and t

RAMP

.

Power Supplies Monitored and Not Monitored by the POR Circuitry

Table 10-2: Power Supplies Monitored and Not Monitored by the Cyclone V POR Circuitry

Power Supplies Monitored

• V

CC_AUX

• V

CCBAT

• V

CC

• V

CCPD

• V

CCPGM

• V

CC_HPS

• V

CCPD_HPS

• V

CCRSTCLK_HPS

Power Supplies Not Monitored

• V

CCE_GXBL

• V

CCH_GXBL

• V

CCL_GXBL

• V

CCA_FPLL

• V

CCIO

• V

CCIO_HPS

• V

CCPLL_HPS

10-7

Note:

For the device to exit POR, you must power the V

CCBAT volatile key.

power supply even if you do not use the

Related Information

Reset Manager

Provides information from the Hard Processor System Technical Reference Manual.

Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices

Provides more information about the

MSEL pin settings for each POR delay.

Document Revision History

Date

January 2014

Version

2014.01.10

June 2013

May 2013

2013.06.28

2013.05.06

Changes

• Updated the note to the V

CCPD_HPS

V

CCPD_HPS power rail that current transient at is observed only when the recommended power-up sequence is not followed. To avoid the current transient at V

CCPD_HPS

, follow the recommended power-up sequence.

• Added Group 1 and Group 2 to the Power-Up Sequence.

• Added power-up sequences for Cyclone V SX, SE and ST devices.

• Added the current transient that occurs on HPS power rails during power-up

• Added link to the known document issues in the Knowledge Base.

• Moved all links to the Related Information section of respective topics for easy reference.

• Updated dynamic power in Power Consumption for improve clarity.

Power Management in Cyclone V Devices

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Document Revision History

Date

December 2012

Version

2012.12.28

June 2012

October 2011

2.0

1.0

Changes

• Added the Power-Up Sequence section.

• Reorganized content and updated template.

Restructured the chapter.

Initial release.

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Power Management in Cyclone V Devices

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Cyclone V Device Handbook

Volume 2: Transceivers

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2013.10.17

101 Innovation Drive

San Jose, CA 95134 www.altera.com

TOC-2

Cyclone V Device Handbook Volume 2: Transceivers

Contents

Transceiver Architecture in Cyclone V Devices.................................................1-1

Architecture Overview................................................................................................................................1-2

Transceiver Banks............................................................................................................................1-3

6.144 Gbps CPRI Support Capability in GT Devices..................................................................1-8

Transceiver Channel Architecture.................................................................................................1-8

PMA Architecture........................................................................................................................................1-9

Transmitter PMA Datapath.........................................................................................................1-10

Receiver PMA Datapath................................................................................................................1-15

Transmitter PLL.............................................................................................................................1-20

Clock Divider..................................................................................................................................1-24

Calibration Block...........................................................................................................................1-25

PCS Architecture........................................................................................................................................1-27

Transmitter PCS Datapath...........................................................................................................1-28

Receiver PCS Datapath..................................................................................................................1-34

Channel Bonding.......................................................................................................................................1-49

PLL Sharing................................................................................................................................................1-49

Document Revision History.....................................................................................................................1-49

Transceiver Clocking in Cyclone V Devices.......................................................2-1

Input Reference Clocking...........................................................................................................................2-1

Dedicated Reference Clock Pins....................................................................................................2-2

Fractional PLL (fPLL)......................................................................................................................2-4

Internal Clocking.........................................................................................................................................2-5

Transmitter Clock Network...........................................................................................................2-5

Transmitter Clocking......................................................................................................................2-9

Receiver Clocking..........................................................................................................................2-14

FPGA Fabric–Transceiver Interface Clocking.......................................................................................2-18

Transceiver Datapath Interface Clocking...................................................................................2-21

Transmitter Datapath Interface Clocking..................................................................................2-21

Receiver Datapath Interface Clock..............................................................................................2-25

Document Revision History.....................................................................................................................2-28

Transceiver Reset Control in Cyclone V Devices...............................................3-1

Altera Corporation

Cyclone V Device Handbook Volume 2: Transceivers

TOC-3

PHY IP Embedded Reset Controller.........................................................................................................3-1

Embedded Reset Controller Signals..............................................................................................3-1

Resetting the Transceiver with the PHY IP Embedded Reset Controller during Device

Power-Up.....................................................................................................................................3-3

Resetting the Transceiver with the PHY IP Embedded Reset Controller during Device

Operation.....................................................................................................................................3-4

User-Coded Reset Controller.....................................................................................................................3-5

User-Coded Reset Controller Signals............................................................................................3-6

Resetting the Transmitter with the User-Coded Reset Controller during Device Power-Up

.......................................................................................................................................................3-7

Resetting the Transmitter with the User-Coded Reset Controller during Device

Operation.....................................................................................................................................3-8

Resetting the Receiver with the User-Coded Reset Controller during Device Power-Up

Configuration..............................................................................................................................3-9

Resetting the Receiver with the User-Coded Reset Controller during Device

Operation...................................................................................................................................3-10

Transceiver Reset Using Avalon Memory Map Registers....................................................................3-11

Transceiver Reset Control Signals Using Avalon Memory Map Registers............................3-11

Clock Data Recovery Manual Lock Mode Reset Sequence..................................................................3-12

Control Settings for CDR Manual Lock Mode..........................................................................3-12

Resetting the Transceiver in CDR Manual Lock Mode............................................................3-13

Resetting the Transceiver During Dynamic Reconfiguration.............................................................3-13

Guidelines for Dynamic Reconfiguration if Transmitter Duty Cycle Distortion Calibration is Required during Device Operation....................................................................................3-14

Transceiver Blocks Affected by the Reset and Powerdown Signals....................................................3-14

Transceiver Power-Down.........................................................................................................................3-15

Document Revision History.....................................................................................................................3-15

Transceiver Protocol Configurations in Cyclone V Devices..............................4-1

PCI Express...................................................................................................................................................4-2

PIPE Transceiver Datapath............................................................................................................4-3

PCIe Supported Features................................................................................................................4-4

PCIe Supported Configurations and Placement Guidelines......................................................4-7

Gigabit Ethernet.........................................................................................................................................4-11

Gigabit Ethernet Transceiver Datapath......................................................................................4-13

XAUI............................................................................................................................................................4-16

Transceiver Datapath in a XAUI Configuration.......................................................................4-17

XAUI Supported Features............................................................................................................4-19

Altera Corporation

TOC-4

Cyclone V Device Handbook Volume 2: Transceivers

Transceiver Clocking and Channel Placement Guidelines in XAUI Configuration...........4-22

Serial Digital Interface...............................................................................................................................4-24

Configurations Supported in SDI Mode.....................................................................................4-25

Serial Digital Interface Transceiver Datapath............................................................................4-26

Serial Data Converter (SDC) JESD204...................................................................................................4-26

SATA and SAS Protocols..........................................................................................................................4-27

Deterministic Latency Protocols—CPRI and OBSAI...........................................................................4-29

Latency Uncertainty Removal with the Phase Compensation FIFO in Register Mode.......4-29

Channel PLL Feedback for Deterministic Relationship...........................................................4-29

CPRI and OBSAI............................................................................................................................4-30

6.144-Gbps Support Capability in Cyclone V GT Devices......................................................4-31

CPRI Enhancements......................................................................................................................4-32

Document Revision History.....................................................................................................................4-34

Transceiver Custom Configurations in Cyclone V Devices...............................5-1

Standard PCS Configuration......................................................................................................................5-1

Custom Configuration Channel Options.....................................................................................5-2

Rate Match FIFO in Custom Configuration................................................................................5-5

Standard PCS in Low Latency Configuration..........................................................................................5-6

Low Latency Custom Configuration Channel Options..............................................................5-7

Document Revision History.....................................................................................................................5-10

Transceiver Loopback Support...........................................................................6-1

Serial Loopback............................................................................................................................................6-1

Forward Parallel Loopback.........................................................................................................................6-2

PIPE Reverse Parallel Loopback................................................................................................................6-3

Reverse Serial Loopback..............................................................................................................................6-3

Reverse Serial Pre-CDR Loopback............................................................................................................6-4

Document Revision History.......................................................................................................................6-5

Dynamic Reconfiguration in Cyclone V Devices...............................................7-1

Dynamic Reconfiguration Features...........................................................................................................7-1

Offset Cancellation......................................................................................................................................7-2

Transmitter Duty Cycle Distortion Calibration......................................................................................7-2

PMA Analog Controls Reconfiguration...................................................................................................7-3

Dynamic Reconfiguration of Loopback Modes.......................................................................................7-4

Transceiver PLL Reconfiguration .............................................................................................................7-4

Altera Corporation

Cyclone V Device Handbook Volume 2: Transceivers

TOC-5

Transceiver Channel Reconfiguration......................................................................................................7-5

Transceiver Interface Reconfiguration ....................................................................................................7-5

Reduced .mif Reconfiguration ..................................................................................................................7-6

Unsupported Reconfiguration Modes......................................................................................................7-6

Document Revision History.......................................................................................................................7-7

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Transceiver Architecture in Cyclone V Devices

2013.05.06

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Describes the Cyclone

®

V transceiver architecture, clocking, channels, channel bonding, and transmitter and receiver channel datapaths.

Altera

®

28-nm Cyclone V devices provide transceivers with the lowest power requirement at 3.125 and 6.144

Gigabits per second (Gbps). These transceivers comply with a wide range of protocols and data rate standards; however, 6.144 Gbps support is limited to the common public radio interface (CPRI) protocol only.

Cyclone V devices have up to 12 transceiver channels with serial data rates between 614 megabits per second

(Mbps) and 6.144 Gbps and have backplane-capable transceiver support for PCI Express

®

(PCIe

®

) Base

Specification 2.0 Gen1 and Gen2 up to x4 bonded channels.

Cyclone V transceiver channels are full-duplex and clock data recovery (CDR)–based with physical coding sublayer (PCS) and physical medium attachment (PMA) layers.

1

©

2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with

Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO

9001:2008

Registered www.altera.com

101 Innovation Drive, San Jose, CA 95134

1-2

Architecture Overview

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Architecture Overview

Figure 1-1: Basic Layout of Transceivers in a Cyclone V Device

This figure represents a Cyclone V device with transceivers. Other Cyclone V devices may have a different floor plan than the one shown here.

I/O, LVDS, and Memory Interface

Hard Memory Controller

Transceiver

PMA

Transceiver

PMA

Transceiver

PMA

Transceiver

PMA

Transceiver

Individual Channels

Hard

PCS

Hard

PCS

Hard

PCS

Hard

PCS

Distributed Memory

Core Logic Fabric and MLABs

M10K Internal Memory Blocks

Variable-Precision DSP Blocks

Hard Memory Controller

I/O, LVDS, and Memory Interface

The embedded high-speed clock networks in Cyclone V devices provide dedicated clocking connectivity for the transceivers. You can also use the fractional phase-locked loop (fPLL) between the PMA and PCS to clock the transceivers.

The embedded PCIe hard intellectual property (IP) of Cyclone V devices implements the following PCIe protocol stacks:

• Physical interface/media access control (PHY/MAC) layer

• Data link layer

• Transaction layer

The embedded hard IP saves significant FPGA resources, reduces design risks, and reduces the time required to achieve timing closure. The hard IP complies with the PCIe Base Specification 2.0 for Gen1 and Gen2 signaling data rates.

Related Information

Transceiver Clocking in Cyclone V Devices

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Transceiver Banks

1-3

IP Compiler for PCI Express User Guide

Cyclone V Device Handbook: Known Issues

Lists the planned updates to the

Cyclone V Device Handbook

chapters.

Transceiver Banks

Cyclone V transceivers are grouped in transceiver banks of three channels. Some Cyclone V devices support four or five transceiver channels.

Every transceiver bank is comprised of three channels (ch 0, ch 1, and ch 2, or ch 3, ch 4 , and ch 5). The

Cyclone V device family has a total of four transceiver banks (for the largest density family) namely, GXB_L0,

GXB_L1, GXB_L2 and GXB_L3.

The location of the transceiver bank boundaries are important for clocking resources, bonding channels, and fitting.

In some package variations, the total transceiver count is reduced.

Figure 1-2: GX/GT Devices with Three or Five Transceiver Channels and One PCIe HIP Block

The PCIe HIP block is located across Ch 1 and Ch 2 of banks GXB_L0.

GXB_L1

GXB_L0

5 Ch (2)

3 Ch (1)

Ch 5

Ch 4

Ch 3

Ch 2

Ch 1

Ch 0

PCIe Hard IP

Transceiver

Bank Names

Notes:

1. 3-channel device transceiver channels are located on bank L0.

2. 5-channel device transceiver channels are located on bank L0, and Ch 3 and Ch 4 of bank L1.

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Transceiver Banks

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Figure 1-3: GX/GT Devices with Four or Six Transceiver Channels and Two PCIe HIP Blocks

The PCIe HIP blocks are located across Ch 1 and Ch 2 of bank GXB_L0, and Ch 4 and Ch 5 of bank GXB_L1.

GXB_L1

GXB_L0

6 Ch

(2)

4 Ch

(1)

Ch 5

Ch 4

Ch 3

Ch 2

Ch 1

Ch 0

PCIe Hard IP

PCIe Hard IP

Transceiver

Bank Names

Notes:

1. 4-channel device transceiver channels are located on bank L0, and Ch 5 of bank L1.

2. 6-channel device transceiver channels are located on banks L0 and L1.

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Transceiver Banks

1-5

Figure 1-4: GX/GT/SX/ST Devices with Nine Transceiver Channels and Two PCIe HIP Blocks

The PCIe HIP blocks are located across Ch 1 and Ch 2 of bank GXB_L0, and Ch 1 and Ch 2 of bank GXB_L2.

9 Ch

(1)

GXB_L2

Ch 2

Ch 1

Ch 0

PCIe Hard IP

GXB_L1

GXB_L0

Ch 5

Ch 4

Ch 3

Ch 2

Ch 1

Ch 0

PCIe Hard IP

Transceiver

Bank Names

Note:

1. 9-channel device transceiver channels are located on banks L0, L1, and L2.

Transceiver Architecture in Cyclone V Devices

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Transceiver Banks

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Figure 1-5: GX/GT Devices with 12 Transceiver Channels and Two PCIe HIP Blocks

The PCIe HIP blocks are located across Ch 1 and Ch 2 of bank GXB_L0, and Ch 1 and Ch 2 of bank GXB_L2.

GXB_L3

GXB_L2

12 Ch (1)

Ch 5

Ch 4

Ch 3

Ch 2

Ch 1

Ch 0

PCIe Hard IP

GXB_L1

GXB_L0

Ch 5

Ch 4

Ch 3

Ch 2

Ch 1

Ch 0

PCIe Hard IP

Transceiver

Bank Names

Note:

1. 12-channel device transceiver channels are located on banks L0, L1, L2, and L3.

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Usage Restrictions on Specific Channels

1-7

Figure 1-6: SX Device with Six Transceiver Channels and One or Two PCIe HIP Blocks

The PCIe HIP blocks are located across Ch 1 and Ch 2 of bank GXB_L0, and Ch 4 and Ch 5 of bank GXB_L1.

GXB_L1

GXB_L0

6 Ch

(2)

6 Ch

(1)

Ch 5

Ch 4

Ch 3

Ch 2

Ch 1

Ch 0

PCIe Hard IP

PCIe Hard IP

Transceiver

Bank Names

Notes:

1. 6 transceiver channels with one PCIe HIP block.

2. 6 transceiver channels with two PCIe HIP blocks.

Usage Restrictions on Specific Channels

Channels next to PCIe Hard IP block are not timing-optimized for the 6.144 Gbps CPRI data rate. Avoid placing the 6.144 Gbps CPRI channels in affected channels. The affected channels can still be used as a CMU to clock the CPRI channels.

Table 1-1: Usage Restrictions on Specific Channels Across Device Variants

Channels

Ch 1, Ch 2

Ch 4, Ch 5

Ch 1, Ch 2

Channel Bank Location

GXB_L0

GXB_L1

(1)

GXB_L2

(1)

Usage Restriction

• No 6.144 Gbps CPRI support

• No support for PCS with phase compensation FIFO in registered mode

Cyclone V GX transceiver channels are comprised of a transmitter and receiver that can operate individually and simultaneously—providing a full-duplex physical layer implementation for high-speed serial interfacing.

(1)

Impacted only if the device has PCIe HIP block located next to this bank.

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6.144 Gbps CPRI Support Capability in GT Devices

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The transmitter and receiver in a channel are structured into PMA and PCS sections:

• PMA—converts serial data to parallel data and vice versa for connecting the FPGA to a serial transmission medium.

• PCS—prepares the parallel data for transmission across a physical medium or restores the data to its original form using hard digital logic implementation.

6.144 Gbps CPRI Support Capability in GT Devices

You can configure Cyclone V GT devices to support 6.144 Gbps for CPRI protocol only. The Cyclone V GT device supports up to three full duplex channels that are compliant to the 6.144 Gbps CPRI protocol for every two transceiver banks. The transceivers are grouped in transceiver banks of three channels.

Altera recommends that you increase the

VCCE_GXBL and

VCCL_GXBL to a nominal value of 1.2 V in order to be compliant to the 6.144Gbps CPRI protocol. The reference clock frequency for the 6.144 Gbps

CPRI channel must be ≥ 307.2 MHz.

Related Information

Transceiver Protocol Configurations in Cyclone V Devices

Transceiver Channel Architecture

Cyclone V transceiver channels support the following interface methods with the FPGA fabric:

• Directly—bypassing the PIPE interface for the PCIe interface and PCIe hard IP block

• Through the PIPE interface and PCIe hard IP block—for hard IP implementation of the PCIe protocol stacks (PHY/MAC, data link layer, and transaction layer)

Figure 1-7: Transceiver Channel Block Diagram in Cyclone V Devices

Transceiver Channel

Transmitter PMA Transmitter PCS

Receiver PMA Receiver PCS

Note:

1. Only certain transceiver channels support interfacing to the PCIe hard IP block.

You can bond multiple channels to implement a multilane link.

Related Information

Transceiver Banks

on page 1-3

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PMA Architecture

1-9

PMA Architecture

The PMA includes the transmitter and receiver datapaths, clock multiplier unit (CMU) PLL—configured from the channel PLL—and the clock divider. The analog circuitry and differential on-chip termination

(OCT) in the PMA requires the calibration block to compensate for process, voltage, and temperature variations (PVT).

Each transmitter channel has a clock divider. There are two types of clock dividers, depending on the channel location in a transceiver bank:

• Channels 0, 2, 3, and 5—local clock divider

• Channels 1 and 4—central clock divider

Using clocks from the clock lines and CMU PLL, the clock divider generates the parallel and serial clock sources for transmitter and optionally for the receiver PCS. The central clock divider can additionally feed the clock lines used to bond channels compared to the local clock divider.

Figure 1-8: PMA Block Diagram of a Transceiver Channel in Cyclone V Devices

Transmitter PMA

From the Transmitter PCS or FPGA Fabric (1)

Serializer

Transmitter

Buffer

High-speed

Clock

Networks

Clock

Divider

To the Receiver PCS or FPGA Fabric (1)

Deserializer

(2)

Channel PLL

(CMU PLL or

CDR)

Receiver

Buffer

Receiver PMA

Notes:

1. The channel PLL provides the serial clock when configured as a CMU PLL.

2. The channel PLL recovers the clock and serial data stream when configured as a CDR.

Physical

Transmission

Medium

Related Information

Altera Transceiver PHY IP Core User Guide

IP Compiler for PCI Express User Guide

Transceiver Architecture in Cyclone V Devices

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Transmitter PMA Datapath

Transmitter PMA Datapath

Table 1-2: Functional Blocks in the Transmitter PMA Datapath

Block

Serializer

Transmitter

Buffer

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Functionality

• Converts the incoming low-speed parallel data from the transmitter PCS to high-speed serial data and sends the data LSB first to the transmitter buffer.

• Supports 8-, 10-, 16-, and 20-bit serialization factors.

• Supports the optional polarity inversion and bit reversal features.

• The 1.5-V PCML output buffer conditions the high-speed serial data for transmission into the physical medium.

• Programmable differential output voltage (VOD )

• Programmable pre-emphasis

• Programmable V

CM current strength

• Programmable slew rate

• On-chip biasing for common-mode voltage (TX V

CM

• Differential OCT (85, 100, 120, and 150 Ω )

)

• Transmitter output tristate

• Receiver detect (for the PCIe receiver detection function)

Related Information

Transmitter Buffer Features and Capabilities

on page 1-13

Serializer

The serializer converts the incoming low-speed parallel data from the transceiver PCS to high-speed serial data and sends the data to the transmitter buffer.

The serializer supports 8, 10, 16, and 20 bits of serialization factors. The serializer block sends out the LSB of the input data first. The transmitter serializer also has polarity inversion and bit reversal capabilities.

Transmitter Polarity Inversion

The positive and negative signals of a serial differential link might accidentally be swapped during board layout. The transmitter polarity inversion feature is provided to correct this situation without requiring a board re-spin or major updates to the logic in the FPGA fabric.

A high value on the tx_invpolarity port inverts the polarity of every bit of the input data word to the serializer in the transmitter datapath. Because inverting the polarity of each bit has the same effect as swapping the positive and negative signals of the differential link, correct data is sent to the receiver. The dynamic tx_invpolarity signal might cause initial disparity errors at the receiver of an 8B/10B encoded link.

The downstream system must be able to tolerate these disparity errors.

Caution:

If the polarity inversion is asserted midway through a serializer word, the word will be corrupted.

Bit Reversal

You can reverse the transmission bit order to achieve MSB-to-LSB ordering using the bit reversal feature at the transmitter.

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Table 1-3: Bit Reversal Feature

Transmitter Buffer

1-11

Bit Reversal Option

Disabled (default)

Enabled

Transmission Bit Order

8- or 10-bit Serialization

Factor

LSB to MSB

MSB to LSB

16- or 20-bit Serialization Factor

LSB to MSB

MSB to LSB

For example: For example:

8-bit—

D[7:0] rewired to

D[0:7]

16-bit—

D[15:0] rewired to

D[0:15]

10-bit—

D[9:0] rewired to

D[0:9]

20-bit—

D[19:0] rewired to

D[0:19]

Transmitter Buffer

Transmitter buffers support the programmable analog settings (differential output voltage and pre-emphasis), common-mode voltage (TX V

CM

), and OCT.

The transmitter buffer includes additional circuitry to improve integrity, such as the programmable differential output voltage (VOD), programmable three-tap pre-emphasis circuitry, internal termination circuitry, and PCIe receiver detect capability to support a PCIe configuration.

Modifying programmable values withing transmitter output buffers can be performed by a single reconfiguration controller for the entire FPGA, or multiple reconfiguration controllers if desired. Within each transceiver bank (three-transceiver channels), a maximum of one reconfiguration controller is allowed.

There is only one slave interface to all PLLs and PMAs within each transceiver bank. Therefore, many transceiver banks can be connected to a single reconfiguration controller, but only one reconfiguration controller can be connected to the transceiver bank (three-transceiver channels).

Note:

A maximum of one reconfiguration controller is allowed per transceiver bank.

Figure 1-9: Transmitter Buffer Block Diagram in Cyclone V Devices

Transmitter

Output

Tri-State

High-speed

Differential

Transmitter

Channel

Output Pins

Tx

VCM

+

From Serializer

Programmable

Pre-Emphasis and V

OD

Receiver

Detect

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Transmitter Buffer

Table 1-4: Description of the Transmitter Buffer Features

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Features provided by the Pseudo Current Mode Logic (PCML) output buffer to the integrated circuitry.

Category Features Description

Improve Signal Integrity

Programmable

Differential

Output Voltage

(V

OD

)

Programmable

Pre-Emphasis

Controls the current mode drivers for signal amplitude to handle different trace lengths, various backplanes, and receiver requirements. The actual V

OD level is a function of the current setting and the transmitter termination value.

Boosts the high-frequency components of the transmitted signal, which may be attenuated when propagating through the transmission medium. The physical transmission medium can be represented as a low-pass filter in the frequency domain. Variation in the signal frequency response that is caused by attenuation significantly increases the datadependent jitter and other intersymbol interference (ISI) effects at the receiver end. Use the pre-emphasis feature to maximize the data opening at the far-end receiver.

Save Board Space and

Cost

Reduce Power

Programmable

Slew Rate

On-Chip Biasing

Controls the rate of change for the signal transition.

Differential OCT

Establishes the required transmitter common-mode voltage

(TX V

CM

) level at the transmitter output. The circuitry is available only if you enable OCT. When you disable OCT, you must implement off-chip biasing circuitry to establish the required TX V

CM level.

The termination resistance is adjusted by the calibration circuitry, which compensates for PVT.

You can disable OCT and use external termination. However, you must implement off-chip biasing circuitry to establish the required TX V

CM level. TX V use external termination.

CM is tri-stated when you

Programmable

V

CM

Current

Strength

Controls the impedance of V

CM

. A higher impedance setting reduces current consumption from the on-chip biasing circuitry.

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Category

Protocol-Specific

Function

Transmitter Buffer Features and Capabilities

1-13

Features

Transmitter

Output Tri-State

Receiver Detect

Description

Enables the transmitter differential pair voltages to be held constant at the same value determined by the TX V with the transmitter in the high impedance state.

CM level

This feature is compliant with differential and common-mode voltage levels and operation time requirements for transmitter electrical idle, as specified in the PCI Express Base Specification 2.0 for Gen1 and Gen2 signaling rates.

Provides link partner detection capability at the transmitter end using an analog mechanism for the receiver detection sequence during link initialization in the Detect state of the

PCIe Link Training and Status State Machine (LTSSM) states.

The circuit detects if there is a receiver downstream by changing the transmitter common-mode voltage to create a step voltage and measuring the resulting voltage rise time.

For proper functionality, the series capacitor (AC-coupled link) and receiver termination values must comply with the

PCI Express Base Specification 2.0 for Gen1 and Gen2 signaling rates. The circuit is clocked using fixedclk and requires an enabled transmitter OCT with the output tristated.

Transmitter Buffer Features and Capabilities

Table 1-5: Transmitter Buffer Features

Feature Capability

Programmable Differential Output

Voltage (V

OD

)

Programmable Pre-Emphasis

Up to 1200 mV of differential peak-to-peak output voltage

Support first Updated the Post Tap Pre-emphasis setting

On-Chip Biasing for Common-Mode

Voltage (TX V

CM

)

0.65 V

Differential OCT 85, 100, 120, and 150 Ω

Transmitter Output Tri-State

Receiver Detect

Supports the electrical idle function at the transmitter as required by the PCIe Base Specification 2.0 for Gen1 and Gen2 signaling rates

Supports the receiver detection function as required by the PCIe Base

Specification 2.0 for Gen1 and Gen2 signaling rates

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Programmable Transmitter Analog Settings

Figure 1-10: Example of the Pre-Emphasis Effect on Signal Transmission at the Transmitter Output

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Signal transmission at the transmitter output with and without applying pre-emphasis post-tap for a 3.125

Gbps signal with an alternating data pattern of five 1s and five 0s.

VOD Differential

Peak-to-Peak

With Pre-Emphasis

Without Pre-Emphasis

Output

Voltage

1-bit period

You can AC-couple the transmitter to a receiver. In an AC-coupled link, the AC-coupling capacitor blocks the transmitter common-mode voltage. At the receiver end, the termination and biasing circuitry restores the common-mode voltage level that is required by the receiver.

Figure 1-11: AC-Coupled Link with a Cyclone V Transmitter

The PCIe spec requires that you enable transmitter OCT for receiver detect operation.

AC-Coupling

Capacitor

Physical Medium

Transmitter Receiver

+

TX

V

CM

RX

V

CM

+

Physical Medium

(1)

AC-Coupling

Capacitor

Notes:

1. When you disable OCT, you must implement external termination and off-chip biasing circuitry to establish the required TX V

CM level.

Programmable Transmitter Analog Settings

Figure 1-12: V

OD

(Differential) Signal Level

Single-Ended Waveform

±V

OD

Differential Waveform

+V

OD

V

OD

(Differential)

=V

A

-V

B

V

OD

(Differential)

V

A

V

B

+700 mV

0 V Differential

-V

OD

-700 mV

Each transmit buffer has programmable pre-emphasis circuits that boost high frequencies in the transmit data signal, which might be attenuated in the transmission media. Using pre-emphasis can maximize the

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Programmable Transmitter V

CM

1-15

data eye opening at the far-end receiver. The pre-emphasis circuitry provides first post-tap settings with up to 6 dB of high-frequency boost.

Programmable Transmitter V

CM

The transmitter buffers have on-chip biasing circuitry to establish the required V

CM

The circuitry supports a V

CM setting of 0.65 V.

at the transmitter output.

Note:

On-chip biasing circuitry is available only if you select one of the Termination logic options in order to configure OCT. If you select external termination, you must implement off-chip biasing circuitry to establish the V

CM at the transmitter output buffer.

Programmable Transmitter Differential OCT

The transmitter buffers support optional differential OCT resistances of 85, 100, 120, and 150 Ω . The resistance is adjusted by the on-chip calibration circuit during calibration, which compensates for PVT changes. The transmitter buffers are current mode drivers. Therefore, the resultant V

OD transmitter termination value.

is a function of the

Transmitter Protocol Specific

There are two PCIe features in the transmitter PMA section—receiver detect and electrical idle.

• PCIe Receiver Detect—The transmitter buffers have a built-in receiver detection circuit for use in PCIe configurations for Gen1 and Gen2 data rates. This circuit detects whether there is a receiver downstream by sending out a pulse on the common mode of the transmitter and monitoring the reflection.

• PCIe Electrical Idle—The transmitter output buffers support transmission of PCIe electrical idle (or individual transmitter tri-state).

Related Information

Altera Transceiver PHY IP Core User Guide

Receiver PMA Datapath

There are three blocks in the receiver PMA datapath—the receiver buffer, channel PLL configured for clock data recovery (CDR) operation, and deserializer.

Table 1-6: Functional Blocks in the Receiver PMA Datapath

Block

Receiver Buffer

Functionality

• Receives the serial data stream and feeds the stream to the channel PLL if you configure the channel PLL as a CDR

• Supports the following features:

• Programmable CTLE (Continuous Time Linear Equalization)

• Programmable DC gain

• Programmable V

CM current strength

• On-chip biasing for common-mode voltage (RX V

CM

)

• I/O standard (1.5 V PCML, 2.5 V PCML, LVDS, LVPECL )

• Differential OCT (85, 100, 120 and 150 Ω )

• Signal detect

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Receiver Buffer

Block

Channel PLL

Deserializer

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Functionality

• Recovers the clock and serial data stream if you configure the channel

PLL as a CDR.

• Requires offset cancellation to correct the analog offset voltages.

• If you do not use the channel PLL as a CDR, you can configure the channel PLL as a CMU PLL for clocking the transceivers.

• Converts the incoming high-speed serial data from the receiver buffer to low-speed parallel data for the receiver PCS.

• Receives serial data in LSB-to-MSB order.

• Supports 8-, 10-, 16-, and 20-bit deserialization factors.

• Supports the optional clock-slip feature for applications with stringent latency uncertainty requirement.

Receiver Buffer

Table 1-7: Cyclone Receiver Buffer Features

Category Features Description

Improve Signal

Integrity

Programmable

Continuous Time

Linear

Equalization

(CTLE)

Boosts the high-frequency components of the received signal, which may be attenuated when propagating through the transmission medium. The physical transmission medium can be represented as a low-pass filter in the frequency domain. Variation in the signal frequency response that is caused by attenuation leads to data-dependent jitter and other ISI effects—causing incorrect sampling on the input data at the receiver. The amount of the high-frequency boost required at the receiver to overcome signal attenuation depends on the loss characteristics of the physical medium.

Programmable

DC Gain

Provides equal boost to the received signal across the frequency spectrum.

On-Chip Biasing

Save Board Space and

Cost

Differential OCT

Establishes the required receiver common-mode voltage (RX V

CM

) level at the receiver input. The circuitry is available only if you enable OCT. When you disable OCT, you must implement offchip biasing circuitry to establish the required RX V

CM level.

The termination resistance is adjusted by the calibration circuitry, which compensates for PVT. You can disable OCT and use external termination. However, you must implement off-chip biasing circuitry to establish the required RX V is tri-stated when you use external termination.

CM level. RX V

CM

Reduce Power Programmable

V

CM

Current

Strength

Controls the impedance of V

CM

. A higher impedance setting reduces current consumption from the on-chip biasing circuitry.

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Category

Protocol-Specific

Function

Features

Signal Detect

Receiver Buffer

1-17

Description

Senses if the signal level present at the receiver input is above or below the threshold voltage that you specified. The detection circuitry has a hysteresis response that asserts the status signal only when a number of data pulses exceeding the threshold voltage are detected and deasserts the status signal when the signal level below the threshold voltage is detected for a number of recovered parallel clock cycles. The circuitry requires the input data stream to be 8B/10B-coded.

Signal detect is compliant to the threshold voltage and detection time requirements for electrical idle detection conditions as specified in the PCI Express Base Specification 2.0 for Gen1 and

Gen2 signaling rates. Signal detect is also compliant to SATA/SAS protocol up to 3 Gbps support.

You can AC-couple the receiver to a transmitter. In an AC-coupled link, the AC-coupling capacitor blocks the transmitter common-mode voltage. At the receiver end, the termination and biasing circuitry restores the common-mode voltage level that is required by the receiver.

Figure 1-13: AC-Coupled Link with a Cyclone V Receiver

AC-Coupling

Capacitor

Physical Medium

Transmitter Receiver

+

TX

VCM

RX

VCM

+

Physical Medium

AC-Coupling

Capacitor

(1)

Note:

1. When you disable OCT, you must implement external termination and off-chip biasing circuitry to establish the required RX V

CM level.

The receiver buffers support the programmable analog settings (CTLE and DC gain), programmable common mode voltage (RX V

CM

), OCT, and signal detect function.

The receiver input buffer receives serial data from the high-speed differential receiver channel input pins and feeds the serial data to the channel PLL configured as a CDR unit.

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Programmable CTLE and DC Gain

Figure 1-14: Receiver Buffer Block Diagram in Cyclone V Devices

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High-speed

Differential

Receiver

Channel

Input Pins

Rx

VCM

+

CTLE and DC Gain

Circuitry

To CDR PLL

Signal

Detect

Circuitry

Modifying programmable values within receiver input buffers can be performed by a single reconfiguration controller for the entire FPGA, or multiple reconfiguration controllers if desired. Within each transceiver bank (three-transceiver channels) a maximum of one reconfiguration controller is allowed. There is only one slave interface to all PLLs and PMAs within each transceiver bank. Therefore, many transceiver banks can be connected to a single reconfiguration controller, but only one reconfiguration controller can be connected to the transceiver bank (three-transceiver channels).

Note:

A maximum of one reconfiguration controller is allowed per transceiver bank.

Programmable CTLE and DC Gain

Each receiver buffer has a single-tap programmable equalization circuit that boosts the high-frequency gain of the incoming signal, thereby compensating for the low-pass filter effects of the physical medium. The amount of high-frequency gain required depends on the loss characteristics of the physical medium. The equalization circuitry provides up to 4 dB of high-frequency boost.

Each receiver buffer also supports the programmable DC gain circuitry that provides an equal boost to the incoming signal across the frequency spectrum. The DC gain circuitry provides up to 3 dB of gain setting.

Programmable Receiver V

CM

The receiver buffers have on-chip biasing circuitry to establish the required V

CM circuitry supports a V

CM setting of 0.8 V.

at the receiver input. The

On-chip biasing circuitry is available only if you select one of the termination logic options in order to configure OCT. If you select external termination, you must implement off-chip biasing circuitry to establish

V

CM at the receiver input buffer.

Programmable Receiver Differential On-Chip Termination

The receiver buffers support optional differential OCT resistances of 85, 100, 120, and 150 Ω . The resistance is adjusted by the on-chip calibration circuit during calibration, which compensates for PVT changes.

Signal Threshold Detection Circuitry

In a PCIe and SATA/SAS configuration, the signal threshold detection circuitry will be enabled to detect the present of incoming signal.

The signal threshold detection circuitry senses whether the signal level present at the receiver input buffer is above the signal detect threshold voltage you specified.

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Deserializer

1-19

Deserializer

The deserializer block clocks in serial input data from the receiver buffer using the high-speed serial recovered clock and deserializes the data using the low-speed parallel recovered clock. The deserializer forwards the deserialized data to the receiver PCS.

The deserializer supports 8, 10, 16, and 20 bits of deserialization factors.

Figure 1-15: Deserializer Operation with a 10-bit Deserialization Factor

Received Data

D2

D1

D0

D5

D4

D3

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

D9

D8

D7

D6

10

To RX PCS

Serial Recovered

Clock from CDR

Parallel Recovered

Clock from CDR

Figure 1-16: Deserializer Bit Order with 10-bit Deserialization Factor

The serial stream (0101111100) is deserialized to a 10'h17C value. The serial data is received LSB to MSB.

Parallel Clock

Serial Clock datain 0 0 1 1 1 1 1 0 1 0 1 1 0 0 0 0 0 1 0 1 dataout 0101111100 1010000011

Clock-slip

Word alignment in the PCS may contribute up to one parallel clock cycle of latency uncertainty. The clockslip feature allows word alignment operation with a reduced latency uncertainty by performing the word alignment function in the deserializer. Use the clock slip feature for applications that require deterministic latency.

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The deterministic latency state machine in the word aligner from the PCS automatically controls the clockslip operation. After completing the clock-slip process, the deserialized data is word-aligned into the receiver

PCS.

Transmitter PLL

In Cyclone V GX/GT/SX/ST devices, there are two transmitter PLL sources: CMU PLL (channel PLL) and fPLL. The channel PLL can be used as CMU PLL to clock the transceivers or as clock data recovery (CDR)

PLL.

Note:

Cyclone V transceiver channels support full-duplex operation. The CMU PLL is sourced from the channel PLL of channels 1 or 4.

Table 1-8: Transmitter PLL Capability and Availability

Transmitter PLL

CMU PLL fPLL

Serial Data Range

0.611 Gbps to 6.144 Gbps

0.611 Gbps to 3.125 Gbps

Availability

Every channel when not used as receiver CDR

Two per transceiver bank

Related Information

Transceiver Clocking in Cyclone V Devices

Channel PLL Architecture

In LTR mode, the channel PLL tracks the input reference clock. The PFD compares the phase and frequency of the voltage controlled oscillator (VCO) output and the input reference clock. The resulting PFD output controls the VCO output frequency to half the data rate with the appropriate counter (M or L) value given an input reference clock frequency. The lock detect determines whether the PLL has achieved lock to the phase and frequency of the input reference clock.

In LTD mode, the channel PLL tracks the incoming serial data. The phase detector compares the phase of the VCO output and the incoming serial data. The resulting phase detector output controls the VCO output to continuously match the phase of the incoming serial data.

The channel PLL supports operation in either LTR or LTD mode.

Note:

Use the LTR/LTD controller only when the channel PLL is configured as a CDR PLL.

Table 1-9: Channel PLL Counters

The Quartus

®

II software automatically selects the appropriate counter values for each transceiver configuration.

Counter Description Values

N Pre-scale counter to divide the input reference clock frequency to the PFD by the N factor

1, 2, 4, 8

M

L (PFD)

Feedback loop counter to multiply the VCO frequency above the input reference frequency to the PFD by the M factor

1, 4, 5, 8, 10, 12, 16, 20, 25

VCO post-scale counter to divide the VCO output frequency by the L factor in the LTR loop

1, 2, 4, 8

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Counter

L (PD)

Channel PLL as CDR PLL

Description

VCO post-scale counter to divide the VCO output frequency by the L factor in the LTD loop

1, 2, 4, 8

Values

1-21

Channel PLL as CDR PLL

When configured as a receiver CDR, each channel PLL independently recovers the clock from the incoming serial data. The serial and parallel recovered clocks are used to clock the receiver PMA and PCS blocks.

The CDR supports the full range of data rates. The voltage-controlled oscillator (VCO) operates at half rate.

The L-counter dividers (PD) after the VCO extend the CDR data rate range. The Quartus II software automatically selects these settings.

The CDR operates in either lock-to-reference (LTR) or lock-to-data (LTD) mode. In LTR mode, the CDR tracks the input reference clock. In LTD mode, the CDR tracks the incoming serial data.

The time needed for the CDR PLL to lock to data depends on the transition density and jitter of the incoming serial data and the PPM difference between the receiver input reference clock and the upstream transmitter reference clock. You must hold the receiver PCS in reset until the CDR PLL locks to data and produces a stable recovered clock.

After the receiver power up and reset cycle, you must keep the CDR in LTR mode until the CDR locks to the input reference clock. When locked to the input reference clock, the CDR output clock is trained to the configured data rate. The CDR then switches to LTD mode to recover the clock from the incoming data.

The LTR/LTD controller controls the switch between the LTR and LTD modes.

Figure 1-17: Channel PLL Block Diagram

From Signal

Detect Circuit (1)

Manual Lock

Controls

Channel PLL

LTR/LTD

Controller rx_is_lockedtodata rx_serial_data refclk

/N

Phase

Detector

(PD)

Down

Up

LTD Mode

Phase

Frequency

Detector

(PFD)

Up

Down

LTR Mode

Charge Pump

&

Loop Filter

Voltage

Controlled

Oscilator

(VCO)

Lock

Detect

/M

Notes:

1. Applicable in a PCIe configuration and custom mode configuration, for example SATA/SAS.

2. Applicable when configured as a CDR PLL.

3. Applicable when configured as a CMU PLL.

/L(PD)

/L(PFD)

Recovered Clock to Deserializer (2)

Serial Clock (3) rx_is_lockedtoref

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Lock-to-Reference Mode

Lock-to-Reference Mode

In LTR mode, the phase frequency detector (PFD) in the CDR tracks the receiver input reference clock. The

PFD controls the charge pump that tunes the VCO in the CDR. Depending on the data rate and the selected input reference clock frequency, the Quartus II software automatically selects the appropriate /M and /L divider values so the CDR output clock frequency is half the data rate. The rx_is_lockedtoref status signal is asserted to indicate that the CDR has locked to the phase and frequency of the receiver input reference clock.

The phase detector is inactive in LTR mode and rx_is_lockedtodata is ignored.

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Lock-to-Data Mode

During normal operation, the CDR must be in LTD mode to recover the clock from the incoming serial data. In LTD mode, the phase detector in the CDR tracks the incoming serial data at the receiver buffer.

Depending on the phase difference between the incoming data and the CDR output clock, the phase detector controls the CDR charge pump that tunes the VCO.

Note:

The PFD output is invalid in LTD mode. The rx_is_lockedtoref signal may toggle randomly and has no significance in LTD mode.

After switching to LTD mode, the rx_is_lockedtodata status signal is asserted. It can take a maximum of 1 ms for the CDR to lock to the incoming data and produce a stable recovered clock. The actual lock time depends on the transition density of the incoming data and the parts per million (ppm) difference between the receiver input reference clock and the upstream transmitter reference clock. The receiver PCS logic must be held in reset until the CDR produces a stable recovered clock.

CDR PLL in Automatic Lock Mode

In automatic lock mode, the LTR/LTD controller directs the transition between the LTR and LTD modes when a set of conditions are met to ensure proper CDR PLL operation. The mode transitions are indicated by the rx_is_lockedtodata status signal.

After power-up or reset of the receiver PMA, the CDR PLL is directed into LTR mode. The controller transitions the CDR PLL from LTR to LTD mode when all the following conditions are met:

• The frequency of the CDR PLL output clock and input reference clock is within the configured ppm frequency threshold setting

• The phase of the CDR PLL output clock and input reference clock is within approximately 0.08 unit interval (UI) of difference

• In PCIe configurations only—the signal detect circuitry must also detect the presence of the signal level at the receiver input above the threshold voltage specified in the PCI Express Base Specification 2.0.

(Signal detect is an optional signal in Custom or Native PHY IP. Use the Assignment Editor to select the threshold voltage.)

The controller transitions the CDR PLL from LTD to LTR mode when either of the following conditions are met:

• The difference in between frequency of the CDR PLL output clock and input reference clock exceeds the configured ppm frequency threshold setting

• In PCIe configurations only—the signal detect circuitry detects the signal level at the receiver input below the threshold voltage specified in the PCI Express Base Specification 2.0

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CDR PLL in Manual Lock Mode

1-23

After switching to LTD mode, the rx_is_lockedtodata status signal is asserted. Lock to data takes a minimum of 4 μs, however the actual lock time depends on the transition density of the incoming data and the parts per million (PPM) difference between the receiver input reference clock and the upstream transmitter reference clock. The receiver PCS logic must be held in reset until the CDR produces a stable recovered clock.

If there is no transition on the incoming serial data for an extended duration, the CDR output clock may drift to a frequency exceeding the configured PPM threshold when compared with the input reference clock.

In such a case, the LTR/LTD controller transitions the CDR PLL from LTD to LTR mode.

CDR PLL in Manual Lock Mode

In manual lock mode, the LTR/LTD controller directs the transition between the LTR and LTD modes based on user-controlled settings in the pma_rx_set_locktodata and pma_rx_set_locktoref registers.

Alternatively you can control it using the

rx_set_locktodata and

rx_set_locktoref ports available in the transceiver PHY IPs.

In LTR mode, the phase detector is not active. When the CDR PLL locks to the input reference clock, you can switch the CDR PLL to LTD mode to recover the clock and data from the incoming serial data.

In LTD mode, the PFD output is not valid and may cause the lock detect status indicator to toggle randomly.

When there is no transition on the incoming serial data for an extended duration, you must switch the CDR

PLL to LTR mode to wait for the read serial data.

Manual lock mode provides the flexibility to manually control the CDR PLL mode transitions bypassing the

PPM detection as required by certain applications that include, but not limited to, the following:

• Link with frequency differences between the upstream transmitter and the local receiver clocks exceeding the CDR PLL ppm threshold detection capability. For example, a system with asynchronous spreadspectrum clocking (SSC) downspread of –0.5% where the SSC modulation results in a PPM difference of up to 5000.

• Link that requires a faster CDR PLL transition to LTD mode, avoiding the duration incurred by the PPM detection in automatic lock mode.

In manual lock mode, your design must include a mechanism—similar to a PPM detector—that ensures the

CDR PLL output clock is kept close to the optimum recovered clock rate before recovering the clock and data. Otherwise, the CDR PLL might not achieve locking to data. If the CDR PLL output clock frequency is detected as not close to the optimum recovered clock rate in LTD mode, direct the CDR PLL to LTR mode.

Related Information

Transceiver Reset Control and Power Down in Cyclone V Devices

Channel PLL as a CMU PLL

When you use the channel PLL as the CMU PLL, you can configure the transceiver channel only as a transmitter.

The CMU PLL operates in LTR mode only and supports the full range of data rates.

The VCO of the PLL operates at half rate and the L-counter dividers (PFD), after the VCO, extend the PLL data rate range.

Note:

CDR functionality for the receiver is not available when you configure the channel PLL as a CMU

PLL—you can use the transceiver channel only as a transmitter.

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Figure 1-18: CMU PLL in Cyclone V Devices

Channel PLL

From Signal

Detect Circuit

Manual Lock

Controls

LTR/LTD

Controller rx_serial_data

Phase

Detector

(PD)

Down

Up refclk

/N

Phase

Frequency

Detector

(PFD)

Up

Down rx_is_lockedtodata

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Charge Pump

+

Loop Filter

Voltage

Controlled

Oscilator

(VCO)

Lock

Detect

/M

/L(PD)

/L(PFD)

Recovered Clock to Deserializer

Serial Clock pll_locked

The CMU PLL output serial clock, with a frequency that is half of the data rate, feeds the clock divider that resides in the transmitter of the same transceiver channel. The CMU PLLs in channels 1 and 4 feed the x1 and x6 clock lines.

Related Information

Transceiver Clocking in Cyclone V Devices

fPLL as a Transmitter PLL

In addition to CMU PLL, the fPLL located adjacent to the transceiver banks are available for clocking the transmitters for serial data rates up to 3.125 Gbps.

Related Information

Clock Networks and PLLs in Cyclone V Devices

Clock Divider

Each Cyclone V transmitter channel has a clock divider.

There are two types of clock dividers, depending on the channel location in a transceiver bank:

• Local clock divider—channels 0, 2, 3, and 5 provide serial and parallel clocks to the PMA

• Central clock divider—channels 1 and 4 can drive the x6 and xN clock lines

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Figure 1-19: Clock Divider for a Transceiver Channel in Cyclone V Devices

Calibration Block

1-25

x6 Clock Lines (1) xN Clock Lines (1)

To Serializer x1 Clock Lines (1)

Fractional PLL

CMU PLL (2)

/N

(1, 2, 4, 8)

PCIe Rateswitch

Circuit

/S

(4, 5, 8, 10)

(5)

PCIe Rateswitch

Control (4)

Serial Clock

Serial and Parallel

Clocks

To x6 Clock Lines (3)

Notes:

1. For information about the x1, x6, and xN clock lines, refer to Transceiver Clocking in Cyclone V Devices.

2. Only from the channel PLL in the same transceiver channel configured as a CMU PLL.

3. Applicable for central clock dividers only (clock dividers in channels 1 and 4).

4. The PCIe rateswitch circuit allows dynamic switching between Gen2 and Gen1 line rates in a PCIe Gen2 design.

5. The divider settings are configured automatically depending on the serialization factor. The selected divider setting is half of the serialization factor.

Both types of clock dividers can divide the serial clock input to provide the parallel and serial clocks for the serializer in the channel if you use clocks from the clock lines or transmit PLLs. The central clock divider can additionally drive the x6 clock lines used to bond multiple channels.

In bonded channel configurations, both types of clock dividers can feed the serializer with the parallel and serial clocks directly, without dividing them from the x6 or xN clock lines.

Related Information

Transceiver Clocking in Cyclone V Devices

Calibration Block

The calibration block calibrates the differential OCT resistance and analog circuitry in the transceiver PMA to ensure the functionality is independent of PVT.

It is also used for duty cycle calibration of the clock line at serial data rates ≥ 4.9152 Gbps.

There is only one calibration block available for the Cyclone V transceiver PMA. It is located on the top left of the device (same side as the transceiver channels).

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Calibration Block

Figure 1-20: Calibration Block Location and Connections in Cyclone V Devices

Transceivers are on the left side of the device only.

2 k Ω ±1%

RREF

Calibration

Block

GXB_L3

(1)

GXB_L2 (1)

GXB_L1 (1)

GXB_L0

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Note:

1. GXB_L1, GXB_L2, and GXB_L3 banks are only available in some device variants.

The calibration block internally generates a constant internal reference voltage, independent of PVT variations.

The block uses the internal reference voltage and external reference resistor to generate constant reference currents.

Note:

You must connect the external reference resistor to the

RREF pin.

These reference currents are used by the analog block calibration circuit to calibrate the transceiver banks.

You must connect a separate 2 kΩ (tolerance max ± 1%) external resistor on each

RREF pin to ground. To ensure the calibration block operates properly, the

RREF resistor connection in the board must be free from external noise.

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PCS Architecture

Figure 1-21: PCS Block Diagram of a Transceiver Channel in a Cyclone V Device

The serial and parallel clocks are sourced from the clock divider.

Transmitter PMA Transmitter PCS

PCS Architecture

1-27

Cyclone V

FPGA Fabric

tx_parallel data tx_coreclkin

Serial

Clock

/2 tx_clkout

Receiver PMA

Receiver PCS

rx_parallel data rx_coreclkin

Recovered Clock from Master Channel

Parallel Clock

/2 rx_clkout

Serial Clock

Parallel Clock

The transceiver channel PCS datapath is categorized into two configurations—single-width and doublewidth, based on the transceiver channel PMA-PCS width (or serialization/deserialization factor).

Table 1-10: PCS Datapath Configurations

Parameters

PMA–PCS Interface Width

FPGA Fabric–Transceiver Interface

Width

Single-Width

8 or 10 bit

8 or 10 bit

16 or 20 bit

(2)

16 or 20 bit

16 or 20 bit

32 or 40 bit

(2)

Double-Width

(2)

The byte serializer and deserializer are enabled.

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Transmitter PCS Datapath

Transmitter PCS Datapath

Table 1-11: Blocks in the Transmitter PCS Datapath

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Block

Transmitter Phase Compensation

FIFO

Byte Serializer

8B/10B Encoder

Transmitter Bit-Slip

Functionality

• Compensates for the phase difference between the low-speed parallel clock and the FPGA fabric interface clock, when interfacing the transmitter PCS with the FPGA fabric directly or with the PCIe hard

IP block

• Supports operation in phase compensation and registered modes

• Halves the FPGA fabric–transceiver interface frequency at the transmitter channel by doubling the transmitter input datapath width

• Allows the transmitter channel to operate at higher data rates with the FPGA fabric–transceiver interface frequency that is within the maximum limit

• Supports operation in single- and double-width modes

• Generates 10-bit code groups from 8-bit data and the 1-bit control identifier in compliance with Clause 36 of the IEEE 802.3 specification

• Supports operation in single- and double-width modes and running disparity control

• Enables user-controlled, bit-level delay in the data prior to serialization for serial transmission

• Supports operation in single- and double-width modes

Transmitter Phase Compensation FIFO

The transmitter phase compensation FIFO is four words deep and interfaces with the transmitter channel

PCS and the FPGA fabric or PCIe hard IP block. The transmitter phase compensation FIFO compensates for the phase difference between the low-speed parallel clock and the FPGA fabric interface clock.

Figure 1-22: Transmitter Phase Compensation FIFO

Datapath from the FPGA

Fabric or PIPE Interface tx_coreclk

TX

Phase

Compensation

FIFO wr_clk rd_clk

Datapath to the Byte Serializer or the 8B/10B Encoder or Serializer tx_clkout coreclkout

The transmitter phase compensation FIFO supports two operations:

• Phase compensation mode with various clocking modes on the read clock and write clock

• Registered mode with only one clock cycle of datapath latency

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Registered Mode

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Registered Mode

To eliminate the FIFO latency uncertainty for applications with stringent datapath latency uncertainty requirements, bypass the FIFO functionality in registered mode to incur only one clock cycle of datapath latency when interfacing the transmitter channel to the FPGA fabric. Configure the FIFO to registered mode when interfacing the transmitter channel to the FPGA fabric or PCIe hard IP block to reduce datapath latency. In registered mode, the low-speed parallel clock that is used in the transmitter PCS clocks the FIFO.

Phase Compensation Mode

The transmitter phase compensation FIFO compensates for any phase difference between the read and write clocks for the transmitter control and data signals. The low-speed parallel clock feeds the read clock, while the FPGA fabric interface clock feeds the write clock. The clocks must have 0 ppm difference in frequency or a FIFO underrun or overflow condition may result.

The FIFO supports various clocking modes on the read and write clocks depending on the transceiver configuration.

Related Information

Transceiver Clocking in Cyclone V Devices

Byte Serializer

The byte serializer divides the input datapath by two to run the transceiver channel at higher data rates while keeping the FPGA fabric interface frequency within the maximum limit.

The byte serializer supports operation in single- and double-width modes. The datapath clock rate at the output of the byte serializer is twice the FPGA fabric–transmitter interface clock frequency. The byte serializer forwards the least significant word first followed by the most significant word.

Note:

You must use the byte serializer in configurations that exceed the maximum frequency limit of the

FPGA fabric–transceiver interface.

Byte Serializer in Single-Width Mode

The byte serializer forwards the LSByte first, followed by the MSByte. The input data width to the byte serializer depends on the channel width option. For example, in single-width mode with a channel width of

20 bits, the byte serializer sends out the least significant word tx_parallel_data[9:0] of the parallel data from the FPGA fabric, followed by tx_parallel_data

[19:10].

Table 1-12: Input and Output Data Width of the Byte Serializer in Single-Width Mode for Cyclone V Devices

Mode

Single-width

Input Data Width to the

Byte Serializer

16

20

Output Data Width from the

Byte Serializer

8

10

Byte Serializer Output Ordering

Least significant 8 bits of the 16bit output first

Least significant 10 bits of the

20-bit output first

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Byte Serializer in Double-Width Mode

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Byte Serializer in Double-Width Mode

The operation in double-width mode is similar to that of single-width mode. For example, in double-width mode with a channel width of 32 bits, the byte serializer forwards tx_parallel_data[15:0] first, followed by

tx_parallel_data[31:16]

.

Table 1-13: Input and Output Data Width of the Byte Serializer in Double-Width Mode for Cyclone V Devices

Mode

Double-width

Input Data Width to the Byte Serializer

32

40

Output Data Width from the

Byte Serializer

16

Byte Serializer Output Ordering

Least significant 16 bits of the 32bit output first

20 Least significant 20 bits of the 40bit output first

If you select the 8B/10B Encoder option, the 8B/10B encoder uses the output from the byte serializer.

Otherwise, the byte serializer output is forwarded to the serializer.

8B/10B Encoder

The 8B/10B encoder supports operation in single- and double-width modes with the running disparity control feature.

8B/10B Encoder in Single-Width Mode

In single-width mode, the 8B/10B encoder generates 10-bit code groups from 8-bit data and 1-bit control identifier with proper disparity according to the PCS reference diagram in the Clause 36 of the IEEE 802.3

specification. The 10-bit code groups are generated as valid data code-groups (/Dx.y/) or special control code-groups (/Kx.y/), depending on the 1-bit control identifier.

Figure 1-23: 8B/10B Encoder in Single-Width Mode

datain[7:0] control identifier disparity controls

8B/10B Encoder dataout[9:0]

The IEEE 802.3 specification identifies only 12 sets of 8-bit characters as

/Kx.y/

. If other sets of 8-bit characters are set to encode as special control code-groups, the 8B/10B encoder may encode the output 10bit code as an invalid code (it does not map to a valid /Dx.y/ or /Kx.y/ code), or unintended valid /Dx.y/ code, depending on the value entered.

In single-width mode, the 8B/10B encoder translates the 8-bit data to a 10-bit code group (control word or data word) with proper disparity. If the tx_datak input is high, the 8B/10B encoder translates the input

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8B/10B Encoder in Double-Width Mode

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data[7:0] to a 10-bit control word. If the tx_datak input is low, the 8B/10B encoder translates the input data[7:0] to a 10-bit data word.

Figure 1-24: 8B/10B Conversion Format

The LSB is transmitted first.

7

H

6

G

5

F

4

E

3

D

2

C

1

B

0

A control_code j

9 h

8 g

7 f

6 i

5 e

4 d

3 c

2 b

1 a

0

MSB LSB

8B/10B Encoder in Double-Width Mode

In double-width mode, two 8B/10B encoders are cascaded to generate two sets of 10-bit code groups from

16-bit data and two 1-bit control identifiers. When receiving the 16-bit data, the 8-bit LSByte is encoded first, followed by the 8-bit MSByte.

Figure 1-25: 8B/10B Encoder in Double-Width Mode

datain[15:8]

MSB control identifier

MSB disparity controls

8B/10B Encoder

(MSB Encoding) dataout[19:10] datain[7:0]

LSB control identifier

LSB disparity controls

8B/10B Encoder

(LSB Encoding) dataout[9:0]

Running Disparity Control

The 8B/10B encoder automatically performs calculations that meet the running disparity rules when generating the 10-bit code groups. The running disparity control feature provides user-controlled signals ( tx_dispval and tx_forcedisp

) to manually force encoding into a positive or negative current running disparity code group. When you enable running disparity control, the control overwrites the current running disparity value in the encoder based on the user-controlled signals, regardless of the internally-computed current running disparity in that cycle.

Note:

Using running disparity control may temporarily cause a running disparity error at the receiver.

Control Code Encoding

The 8B/10B block provides the tx_datak signal to indicate whether the 8-bit data at the tx_parallel_data signal should be encoded as a control word (Kx.y) or a data word (Dx.y). When

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Reset Condition

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tx_datak is low, the 8B/10B encoder block encodes the byte at the tx_parallel_data signal as data

(Dx.y). When tx_datak is high, the 8B/10B encoder encodes the input data as a Kx.y code group. The rest of the tx_parallel_data bytes are encoded as a data word (Dx.y).

Figure 1-26: Control Word and Data Word Transmission

The second 0xBC is encoded as a control word (K28.5).

clock tx_datain[7:0]

83 78 BC BC 0F 00 BF 3C tx_datak code group

D3.4

D24.3

D28.5

K28.5

D15.0

D0.0

D31.5

D28.1

Note:

The IEEE802.3 8B/10B encoder specification identifies only a set of 8-bit characters for which you must assert tx_datak

. If you assert tx_datak for any other set of bytes, the 8B/10B encoder might encode the output 10-bit code as an invalid code (it does not map to a valid Dx.y or Kx.y code), or unintended valid Dx.y code, depending on the value entered. It is possible for a downstream

8B/10B decoder to decode an invalid control word into a valid Dx.y code without asserting code error flags.

Reset Condition

The reset_tx_digital signal resets the 8B/10B encoder. During reset, the running disparity and data registers are cleared. Also, the 8B/10B encoder outputs a K28.5 pattern from the RD– column continuously until reset_tx_digital is deasserted. The input data and control code from the FPGA fabric is ignored during the reset state. After reset, the 8B/10B encoder starts with a negative disparity (RD–) and transmits three K28.5 code groups for synchronization before it starts encoding and transmitting the data on its output.

Note:

While reset_tx_digital is asserted, the downstream 8B/10B decoder that receives the data might observe synchronization or disparity errors.

Encoder Output During Reset Sequence

When in reset ( reset_tx_digital is high), a K28.5- (K28.5 10-bit code group from the RD– column) is sent continuously until reset_tx_digital is low. Because of some pipelining of the transmitter channel PCS, some “don’t cares” (10’hxxx) are sent before the three synchronizing K28.5 code groups. User data follows the third K28.5 code group.

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Transmitter Bit-Slip

Figure 1-27: 8B/10B Encoder Output During and After Reset Conditions

8B/10B encoder output during and after reset conditions in both single- and double-width modes.

(a) Single-Width Mode

clock

1-33

tx_digitalreset dataout[9:0] K28.5K28.5K28.5XXX XXX XXX K28.5K28.5+ K28.5-

Dx.y+

(b) Double-Width Mode

clock tx_digitalreset dataout[19:10] K28.5+ K28.5+ K28.5+ dataout[9:0] K28.5K28.5K28.5-

XXX

XXX

XXX

XXX

XXX

XXX

K28.5+ K28.5+ K28.5+

Dx.y+

K28.5K28.5K28.5-

Dx.y-

Table 1-14: 8B/10B Encoder Output During and After Reset Conditions

Operation Mode

Single Width

Double Width

During 8B/10B Reset

Continuously sends the /K28.5/ code from the RD– column

Continuously sends the /K28.5/ code from the RD– column on the LSByte and the /

K28.5/ code from the RD+ column on the

MSByte

After 8B/10B Reset Release

Some “don't cares” are seen due to pipelining in the transmitter channel, followed by three

/K28.5/ codes with proper disparity—starts with negative disparity—before sending encoded 8-bit data at its input.

Some “don't cares” are seen due to pipelining in the transmitter channel, followed by:

• Three /K28.5/ codes from the RD– column before sending encoded 8-bit data at its input on LSByte.

• Three /K28.5/ codes from the RD+ column before sending encoded 8-bit data at its input on MSByte.

Transmitter Bit-Slip

The transmitter bit-slip allows you to compensate for the channel-to-channel skew between multiple transmitter channels by slipping the data sent to the PMA. The maximum number of bits slipped is controlled from the FPGA fabric and is equal to the width of the PMA-PCS minus 1.

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Receiver PCS Datapath

Table 1-15: Bits Slip Allowed with the tx_bitslipboundaryselect signal

Operation Mode

Single width (8 or 10 bit)

Double width (16 or 20 bit)

9

19

Maximum Bit-Slip Setting

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Receiver PCS Datapath

The sub-blocks in the receiver PCS datapath are described in order from the word aligner to the receiver phase compensation FIFO block.

Table 1-16: Blocks in the Receiver PCS Datapath

Block

Word Aligner

Rate Match FIFO

8B/10B Decoder

Byte Deserializer

Byte Ordering

Functionality

• Searches for a predefined alignment pattern in the deserialized data to identify the correct boundary and restores the word boundary during link synchronization

• Supports an alignment pattern length of 7, 8, 10, 16, 20, or 32 bits

• Supports operation in four modes—manual alignment, bit-slip, automatic synchronization state machine, and deterministic latency state machine—in single- and double-width configurations

• Supports the optional programmable run-length violation detection, polarity inversion, bit reversal, and byte reversal features

• Compensates for small clock frequency differences of up to ±300 parts per million (ppm)—600 ppm total—between the upstream transmitter and the local receiver clocks by inserting or deleting skip symbols when necessary

• Supports operation that is compliant to the clock rate compensation function in supported protocols

• Receives 10-bit data and decodes the data into an 8-bit data and a 1bit control identifier—in compliance with Clause 36 of the IEEE 802.3

specification

• Supports operation in single- and double-width modes

• Halves the FPGA fabric–transceiver interface frequency at the receiver channel by doubling the receiver output datapath width

• Allows the receiver channel to operate at higher data rates with the

FPGA fabric–transceiver interface frequency that is within maximum limit

• Supports operation in single- and double-width modes

• Searches for a predefined pattern that must be ordered to the LSByte position in the parallel data going to the FPGA fabric when you enable the byte deserializer

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Block

Receiver Phase Compensation

FIFO

Word Aligner

1-35

Functionality

• Compensates for the phase difference between the low-speed parallel clock and the FPGA fabric interface clock when interfacing the receiver

PCS with the FPGA fabric directly or with the PCIe hard IP block

• Supports operation in phase compensation and registered modes

Word Aligner

Parallel data at the input of the receiver PCS loses the word boundary of the upstream transmitter from the serial-to-parallel conversion in the deserializer. The word aligner receives parallel data from the deserializer and restores the word boundary based on a pre-defined alignment pattern that must be received during link synchronization.

The word aligner searches for a pre-defined alignment pattern in the deserialized data to identify the correct boundary and restores the word boundary during link synchronization. The alignment pattern is pre-defined for standard serial protocols according to the respective protocol specifications for achieving synchronization.

For proprietary protocol implementations, you can specify a custom word alignment pattern specific to your application.

In addition to restoring the word boundary, the word aligner implements the following features:

• Synchronization state machine

• Programmable run length violation detection (for all transceiver configurations)

• Receiver polarity inversion (for all transceiver configurations except PCIe)

• Receiver bit reversal (for custom single- and double-width configurations only)

• Receiver byte reversal (for custom double-width configuration only)

The word aligner operates in one of the following three modes:

• Manual alignment

• Automatic synchronization state machine

• Bit-slip

• Deterministic latency state machine

Except for bit-slip mode, after completing word alignment, the deserialized data is synchronized to have the word alignment pattern at the LSB portion of the aligned data.

Word Aligner Options and Behaviors

The operation mode and alignment pattern length support varies depending on the word aligner configurations.

Table 1-17: Word Aligner Options and Behaviors

PMA-PCS Interface Width

(bits)

8

Word Alignment

Mode

Manual

Alignment

Bit-Slip

Word Alignment

Pattern Length (bits)

16

16

Word Alignment Behavior

User-controlled signal starts the alignment process. Alignment happens once unless the signal is reasserted.

User-controlled signal shifts data one bit at a time.

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Word Aligner in Manual Alignment Mode

PMA-PCS Interface Width

(bits)

10

16

20

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Word Alignment

Mode

Manual

Alignment

Bit-Slip

Automatic

Synchronized

State Machine

Deterministic

Latency State

Machine

Manual

Alignment

Bit-Slip

Manual

Alignment

Bit-Slip

Deterministic

Latency State

Machine

Word Alignment

Pattern Length (bits)

7 and 10

7 and 10

7 and 10

10

8, 16, and 32

8, 16, and 32

7, 10, and 20

7, 10, and 20

10 and 20

Word Alignment Behavior

User-controlled signal starts the alignment process. Alignment happens once unless the signal is reasserted.

User-controlled signal shifts data one bit at a time.

Data is required to be 8B/10B encoded.

Aligns to selected word aligner pattern when pre-defined conditions are satisfied.

User-controlled signal starts the alignment process. After the pattern is found and the word boundary is identified, the state machine controls the deserializer to clockslip the boundary-indicated number of serial bits.

Alignment happens automatically after RX

PCS reset. User-controlled signal starts the alignment process thereafter. Alignment happens once unless the signal is reasserted.

User-controlled signal shifts data one bit at a time.

Alignment happens automatically after RX

PCS reset. User-controlled signal starts the alignment process thereafter. Alignment happens once unless the signal is reasserted.

User-controlled signal shifts data one bit at a time.

User-controlled signal starts the alignment process. After the pattern is found and the word boundary is identified, the state machine controls the deserializer to clockslip the boundary-indicated number of serial bits.

Word Aligner in Manual Alignment Mode

In manual alignment mode, word alignment is manually controlled with the rx_enapatternalign register. Depending on the configuration, controlling the

rx_enapatternalign register enables the word aligner to look for the predefined word alignment pattern in the received data stream and automatically synchronizes to the new word boundary.

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Table 1-18: Word Aligner Operations in Manual Alignment Mode

Word Aligner in Manual Alignment Mode

PCS Mode

Single Width

1-37

PMA–PCS

Interface Width

(bits)

8

10

Word Alignment Operation

1. After the

rx_digitalreset signal deasserts, a 0-to-1 transition on the rx_enapatternalign register triggers the word aligner to look for the predefined word alignment pattern in the received data stream and automatically synchronize to the new word boundary.

2. Any alignment pattern found thereafter in a different word boundary does not cause the word aligner to resynchronize to this new word boundary because there is a lack of a preceding 0-to-1 transition on the

rx_enapatternalign register.

3. To resynchronize to the new word boundary, create a 0-to-1 transition in the rx_enapatternalign register.

4. If you set the

rx_enapatternalign register to 1 before the deassertion of the

rx_digitalreset signal, the word aligner updates the word boundary when the first alignment pattern is found, even though a 0-to-1 transition was not explicitly generated.

5. To resynchronize to the new word boundary, create a 0-to-1 transition to the

rx_enapatternalign register.

6. When the word aligner synchronized to the new word boundary, the rx_patterndetect and

rx_syncstatus signals will assert for one parallel clock cycle.

1. After the

rx_digitalreset signal deasserts, setting the rx_ enapatternalign register to 1 triggers the word aligner to look for the predefined word alignment pattern, or its complement in the received data stream, and automatically synchronize to the new word boundary.

2. Any alignment pattern found thereafter in a different word boundary causes the word aligner to resynchronize to this new word boundary if the rx_enapatternalign register remains set to 1.

3. If you set the rx_enapatteralign register to 0, the word aligner maintains the current word boundary even when it finds the alignment pattern in a new word boundary.

4. When the word aligner synchronized to the new word boundary, the rx_patterndetect and

rx_syncstatus signals will assert for one parallel clock cycle.

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Word Aligner in Bit-Slip Mode

PCS Mode

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PMA–PCS

Interface Width

(bits)

16

20

Word Alignment Operation

1. After the

rx_digitalreset signal deasserts, regardless of the setting in the rx_enapatternalign register, the word aligner synchronizes to the first predefined alignment pattern found.

2. Any alignment pattern found thereafter in a different word boundary does not cause the word aligner to resynchronize to this new word boundary.

3. To resynchronize to the new word boundary, create a 0-to-1 transition in the rx_enapatternalign register.

4. When the word aligner synchronized to the new word boundary, the rx_patterndetect and rx_syncstatus signals will assert for one parallel clock cycle. The

rx_syncstatus signal will deassert if the next rising edge of rx_enapatternalign is detected.

Word Aligner in Bit-Slip Mode

In bit-slip mode, the word aligner is controlled by the rx_bitslip bit of the pcs8g_rx_wa_control register. At every 0-1 transition of the rx_bitslip bit of the pcs8g_rx_wa_control register, the bit-slip circuitry slips one bit into the received data stream, effectively shifting the word boundary by one bit. Also in bit-slip mode, the word aligner pcs8g_rx_wa_status register bit for rx_patterndetect is driven high for one parallel clock cycle when the received data after bit-slipping matches the 16-bit word alignment pattern programmed.

To achieve word alignment, you can implement a bit-slip controller in the FPGA fabric that monitors the rx_parallel_data signal, the rx_patterndetect signal, or both, and controls them with the rx_bitslip signal.

Table 1-19: Word Aligner in Bit-Slip Mode

PCS Mode

Single Width

Double Width

PMA–PCS Interface Width

(bits)

8

10

16

20

Word Alignment Operation

1. At every rising edge to the rx_bitslip signal, the word aligner slips one bit into the received data.

2. When bit-slipping shifts a complete round of the data bus width, the word boundary is back to the original boundary.

3. Use the rx_patterndetect signal assertion or check the data output to indicate completion of alignment process—where the word aligner output matches the predefined alignment pattern.

Note:

For every bit slipped in the word aligner, the earliest bit received is lost.

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Word Aligner in Automatic Synchronization State Machine Mode

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Word Aligner in Automatic Synchronization State Machine Mode

In automatic synchronization state machine mode, a programmable state machine determines the moment that the word aligner has either achieved synchronization or lost synchronization.

You can configure the state machine to provide hysteresis control during link synchronization and throughout normal link operation. Depending on your protocol configurations, the state machine parameters are automatically configured so they are compliant with the synchronization state machine in the respective protocol specification.

Table 1-20: Programmable Parameters for the Word Aligner in Synchronization State Machine Mode

Parameter

Number of valid synchronization code groups or ordered sets received to achieve synchronization

1–256

Number of erroneous code groups received to lose synchronization 1–64

Number of continuous good code groups received to reduce the error count by one

1–256

Values

Table 1-21: Word Aligner Operation in Automatic Synchronization State Machine Mode

PCS Mode

Single Width

PMA–PCS Interface

Width

10 bits

Word Alignment Operation

1. After the rx_digitalreset signal deasserts, the word aligner starts looking for the predefined word alignment pattern, or its complement, in the received data stream and automatically aligns to the new word boundary.

2. Synchronization is achieved only after the word aligner receives the programmed number of valid synchronization code groups in the same word boundary and is indicated with the assertion of the rx_syncstatus signal.

3. After assertion and achieving synchronization, the rx_ syncstatus signal remains asserted until the word aligner loses synchronization.

4. Loss of synchronization occurs when the word aligner receives the programmed number of erroneous code groups without receiving the intermediate good code groups and is indicated with the deassertion of the

rx_syncstatus signal.

5. The word aligner may achieve synchronization again after receiving a new programmed number of valid synchronization code groups in the same word boundary.

Word Aligner in Automatic Synchronization State Machine Mode with a 10-Bit PMA-PCS Interface

Configuration

Protocols such as PCIe require the receiver PCS logic to implement a synchronization state machine to provide hysteresis during link synchronization. Each of these protocols defines a specific number of

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Word Aligner Operations in Deterministic Latency State Machine Mode

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synchronization code groups that the link must receive to acquire synchronization and a specific number of erroneous code groups that it must receive to fall out of synchronization.

In PCIe configurations, the word aligner in automatic synchronization state machine mode automatically selects the word alignment pattern length and pattern as specified by each protocol. The synchronization state machine parameters are fixed for PCIe configurations as specified by the respective protocol.

Table 1-22: Word Aligner in Synchronization State Machine Modes for a PCIe Configuration

Mode

Number of valid synchronization code groups or ordered sets received to achieve synchronization

Number of erroneous code groups received to lose synchronization

Number of continuous good code groups received to reduce the error count by one

PCIe

4

17

16

After deassertion of the reset_rx_digital signal in automatic synchronization state machine mode, the word aligner starts looking for the word alignment pattern or synchronization code groups in the received data stream. When the programmed number of valid synchronization code groups or ordered sets is received, the rx_syncstatus status bit is driven high to indicate that synchronization is acquired. The rx_syncstatus status bit is constantly driven high until the programmed number of erroneous code groups is received without receiving intermediate good groups; after which rx_syncstatus is driven low. The word aligner indicates loss of synchronization ( rx_syncstatus remains low) until the programmed number of valid synchronization code groups are received again.

Word Aligner Operations in Deterministic Latency State Machine Mode

In deterministic latency state machine mode, word alignment is achieved by performing a clock-slip in the deserializer until the deserialized data coming into the receiver PCS is word-aligned. The deterministic latency state machine controls the clock-slip process in the deserializer after the word aligner has found the alignment pattern and has identified the word boundary. Deterministic latency state machine mode offers a reduced latency uncertainty in the word alignment operation for applications that require deterministic latency.

Table 1-23: Word Aligner Operations in Deterministic Latency State Machine Mode

PCS Mode

Single Width

Double Width

PMA–PCS Interface

Width

10 bits

20 bits

Word Alignment Operation

1. After the rx_digitalreset signal deasserts, a 0-to-1 transition in the rx_enapatternalign register triggers the word aligner to look for the predefined word alignment pattern, or its complement, in the received data stream.

2. After the pattern is found and the word boundary is identified, the state machine controls the deserializer to clock-slip the boundary-indicated number of serial bits.

3. When clock-slip is complete, the deserialized data coming into the receiver PCS is word-aligned and indicated when the rx_syncstatus signal asserts.

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Programmable Run-Length Violation Detection

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Programmable Run-Length Violation Detection

The programmable run-length violation detection circuit resides in the word aligner block and detects if consecutive 1s or 0s in the received data exceed the user-specified threshold.

If the data stream exceeds the preset maximum number of consecutive 1s or 0s, the violation is signified by the assertion of the rx_rlv status bit.

Table 1-24: Detection Capabilities of the Run-Length Violation Circuit

PCS Mode

Single Width

Double Width

PMA–PCS Interface

Width (bits)

8

10

16

20

Minimum

4

5

8

10

Run-Length Violation Detector Range

Maximum

128

160

512

640

Receiver Polarity Inversion

The positive and negative signals of a serial differential link might erroneously be swapped during board layout. Solutions such as board re-spin or major updates to the PLD logic can be expensive. The polarity inversion feature at the receiver corrects the swapped signal error without requiring board re-spin or major updates to the logic in the FPGA fabric. The polarity inversion feature inverts the polarity of every bit at the input to the word aligner, which has the same effect as swapping the positive and negative signals of the serial differential link.

Inversion is controlled dynamically with the rx_invpolarity register. When you enable the polarity inversion feature, initial disparity errors may occur at the receiver with the 8B/10B-coded data. The receiver must be able to tolerate these disparity errors.

Caution:

If you enable polarity inversion midway through a word, the word will be corrupted.

Bit Reversal

By default, the receiver assumes a LSB-to-MSB transmission. If the transmission order is MSB-to-LSB, the receiver forwards the bit-flipped version of the parallel data to the FPGA fabric on

rx_parallel_data

.

To reverse the bit order at the output of the word aligner to receive a MSB-to-LSB transmission, use the bit reversal feature at the receiver.

Table 1-25: Bit Reversal Feature

Bit Reversal Option

Disabled (default)

Single-Width Mode (8 or 10 bit)

LSB to MSB

Received Bit Order

Double-Width Mode (16 or 20 bit)

LSB to MSB

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Receiver Byte Reversal

Bit Reversal Option

Enabled

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Single-Width Mode (8 or 10 bit)

MSB to LSB

For example:

8-bit—D[7:0] rewired to D[0:7]

10-bit—D[9:0] rewired to D[0:9]

Received Bit Order

Double-Width Mode (16 or 20 bit)

MSB to LSB

For example:

16-bit—D[15:0] rewired to D[0:15]

20-bit—D[19:0] rewired to D[0:19]

Note:

When receiving the MSB-to-LSB transmission, the word aligner receives the data in reverse order.

The word alignment pattern must be reversed accordingly to match the MSB first incoming data ordering.

You can dynamically control the bit reversal feature to use the rx_bitreversal_enable register with the word aligner in bit-slip mode. When you dynamically enable the bit reversal feature in bit-slip mode, ignore the pattern detection function in the word aligner because the word alignment pattern cannot be dynamically reversed to match the MSB first incoming data order.

Receiver Byte Reversal

In double-width mode, two symbols of incoming data at the receiver may be accidentally swapped during transmission. For a 16-bit input data width at the word aligner, the two symbols are bits

[15:8] and bits

[7:0]

. For a 20-bit input data width at the word aligner, the two symbols are bits

[19:10] and bits

[9:0]

. The byte reversal feature at the word aligner output corrects the swapped signal error by swapping the two symbols in double-width mode at the word aligner output, as listed in

Table 1-26

.

Table 1-26: Byte Reversal Feature

Byte Reversal Option

Disabled

Enabled

16-bit Data Width

D[15:0]

D[7:0], D[15:8]

Word Aligner Output

20-bit Data Width

D[19:0]

D[9:0], D[19:10]

The reversal is controlled dynamically using the rx_bytereversal_enable register, and when you enable the receiver byte reversal option, this may cause initial disparity errors at the receiver with 8B/10Bcoded data. The receiver must be able to tolerate these disparity errors.

Note:

When receiving swapped symbols, the word alignment pattern must be byte-reversed accordingly to match the incoming byte-reversed data.

Rate Match FIFO

The Rate Match FIFO compensates for the small clock frequency differences between the upstream transmitter and the local receiver clocks.

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In a link where the upstream transmitter and local receiver can be clocked with independent reference clock sources, the data can be corrupted by any frequency differences (in ppm count) when crossing the data from the recovered clock domain—the same clock domain as the upstream transmitter reference clock—to the local receiver reference clock domain.

The rate match FIFO is 20 words deep, which compensates for the small clock frequency differences of up to ±300 ppm (600 ppm total) between the upstream transmitter and the local receiver clocks by performing symbol insertion or deletion, depending on the ppm difference on the clocks.

The rate match FIFO requires that the transceiver channel is in duplex configuration (both transmit and receive functions) and has a predefined 20-bit pattern (that consists of a 10-bit control pattern and a 10-bit skip pattern). The 10-bit skip pattern must be chosen from a code group with neutral disparity.

The rate match FIFO operates by looking for the 10-bit control pattern, followed by the 10-bit skip pattern in the data, after the word aligner has restored the word boundary. After finding the pattern, the rate match

FIFO performs the following operations to ensure the FIFO does not underflow or overflow:

• Inserts the 10-bit skip pattern when the local receiver reference clock frequency is greater than the upstream transmitter reference clock frequency

• Deletes the 10-bit skip pattern when the local receiver reference clock frequency is less than the upstream transmitter reference clock frequency

The rate match FIFO supports operations in single-width mode. The 20-bit pattern can be user-defined for custom configurations. For protocol configurations, the rate match FIFO is automatically configured to support a clock rate compensation function as required by the following specifications:

• The PCIe protocol per clock tolerance compensation requirement, as specified in the PCI Express Base

Specification 2.0 for Gen1 and Gen2 signaling rates

• The Gbps Ethernet (GbE) protocol per clock rate compensation requirement using an idle ordered set, as specified in Clause 36 of the IEEE 802.3 specification

In asynchronous systems, use independent reference clocks to clock the upstream transmitter and local receiver. Frequency differences in the order of a few hundred ppm can corrupt the data when latching from the recovered clock domain (the same clock domain as the upstream transmitter reference clock) to the local receiver reference clock domain.

The rate match FIFO deletes SKP symbols or ordered sets when the upstream transmitter reference clock frequency is higher than the local receiver reference clock frequency and inserts SKP symbols or ordered sets when the local receiver reference clock frequency is higher than the upstream transmitter reference clock frequency.

Related Information

Transceiver Custom Configurations in Cyclone V Devices

Transceiver Protocol Configurations in Cyclone V Devices

8B/10B Decoder

The receiver channel PCS datapath implements the 8B/10B decoder after the rate match FIFO. In configurations with the rate match FIFO enabled, the 8B/10B decoder receives data from the rate match FIFO. In configurations with the rate match FIFO disabled, the 8B/10B decoder receives data from the word aligner.

The 8B/10B decoder supports operation in single- and double-width modes.

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8B/10B Decoder in Single-Width Mode

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8B/10B Decoder in Single-Width Mode

In single-width mode, the 8B/10B decoder decodes the received 10-bit code groups into an 8-bit data and a

1-bit control identifier, in compliance with Clause 36 in the IEEE 802.3 specification. The 1-bit control identifier indicates if the decoded 8-bit code is a valid data or special control code. The decoded data is fed to the byte deserializer or the receiver phase compensation FIFO (if the byte deserializer is disabled).

Figure 1-28: 8B/10B Decoder in Single-Width Mode

datain[9:0]

8B/10B Decoder dataout[7:0] control identifier error status

8B/10B Decoder in Double-Width Mode

In double-width mode, two 8B/10B decoders are cascaded to decode the 20-bit code groups into two sets of

8-bit data and two 1-bit control identifiers. When receiving the 20-bit code group, the 10-bit LSByte is decoded first and the ending running disparity is forwarded to the other 8B/10B decoder for decoding the

10-bit MSByte.

Figure 1-29: 8B/10B Decoder in Double-Width Mode

datain[19:10]

8B/10B Decoder

(MSByte Decoding) dataout[15:8] control identifier error status datain[9:0]

Current Running Disparity

8B/10B Decoder

(LSByte Decoding) dataout[7:0] control identifier error status

Control Code Group Detection

The 8B/10B decoder indicates whether the decoded 8-bit code group is a data or a control code group on the rx_datak signal. If the received 10-bit code group is one of the 12 control code groups (

/Kx.y/

) specified in the IEEE802.3 specification, the rx_datak signal is driven high. If the received 10-bit code group is a data code group (

/Dx.y/

), the rx_datak signal is driven low.

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Byte Deserializer

1-45

Byte Deserializer

The FPGA fabric-transceiver interface frequency has an upper limit. In configurations that have a receiver

PCS frequency greater than the upper limit stated, the parallel received data and status signals cannot be forwarded directly to the FPGA fabric because it violates this upper limit for the FPGA fabric-transceiver interface frequency. In such configurations, the byte deserializer is required to reduce the FPGA fabric-transceiver interface frequency to half while doubling the parallel data width.

Note:

The byte deserializer is required in configurations that exceed the FPGA fabric-transceiver interface clock upper frequency limit. It is optional in configurations that do not exceed the FPGA fabrictransceiver interface clock upper frequency limit.

The byte deserializer supports operation in single- and double-width modes. The datapath clock rate at the input of the byte deserializer is twice the FPGA fabric–receiver interface clock frequency. After byte deserialization, the word alignment pattern may be ordered in the MSByte or LSByte position.

The data is assumed to be received as LSByte first—the least significant 8 or 10 bits in single-width mode or the least significant 16 or 20 bits in double-width mode.

Table 1-27: Byte Deserializer Input Datapath Width Conversion

Single Width

Double Width

Mode

8

10

16

20

Byte Deserializer Input

Datapath Width

16

20

32

40

Receiver Output Datapath Width

Byte Deserializer in Single-Width Mode

In single-width mode, the byte deserializer receives 8-bit wide data from the 8B/10B decoder or 10-bit wide data from the word aligner (if the 8B/10B decoder is disabled) and deserializes it into 16- or 20-bit wide data at half the speed.

Figure 1-30: Byte Deserializer in Single-Width Mode

datain[7:0] or datain[9:0]

D1 D2 D3 D4

Byte

Deserializer

D2

D1

D4

D3 dataout[15:0} or dataout[19:0]

/2 Receiver PCS Clock

Byte Deserializer in Double-Width Mode

In double-width mode, the byte deserializer receives 16-bit wide data from the 8B/10B decoder or 20-bit wide data from the word aligner (if the 8B/10B decoder is disabled) and deserializes it into 32- or 40-bit wide data at half the speed.

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Byte Ordering

Figure 1-31: Byte Deserializer in Double-Width Mode

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datain[15:0] or datain[19:0]

D1D2 D3D4 D5D6 D7D8

Byte

Deserializer

D2D4

D1D2

D7D8

D5D6 dataout[31:0] or dataout[39:0]

/2

Receiver PCS Clock

Byte Ordering

When you enable the byte deserializer, the output byte order may not match the originally transmitted ordering. For applications that require a specific pattern to be ordered at the LSByte position of the data, byte ordering restores the proper byte order of the byte-deserialized data before forwarding it to the FPGA fabric.

Byte ordering operates by inserting a predefined pad pattern to the byte-deserialized data if the predefined byte ordering pattern found is not in the LSByte position.

Byte ordering requires the following:

• A receiver with the byte deserializer enabled

• A predefined byte ordering pattern that must be ordered at the LSByte position of the data

• A predefined pad pattern

Byte ordering supports operation in single- and double-width modes. Both modes support operation in word aligner-based and manual ordering modes.

Byte Ordering in Single-Width Mode

Byte ordering is supported only when you enable the byte deserializer.

Table 1-28: Byte Ordering Operation in Single-Width Mode

PMA–PCS Interface Width

8 bits

10 bits

FPGA

Fabric–Transceiver

Interface Width

16 bits

16 bits

20 bits

8B/10B Decoder

Disabled

Enabled

Disabled

Byte Ordering

Pattern Length

8 bits

9 bits

(3)

10 bits

Pad Pattern Length

8 bits

9 bits

(3)

10 bits

(3)

The MSB of the 9-bit pattern represents the 1-bit control identifier of the 8B/10B-decoded data. The lower 8 bits represent the 8-bit decoded code.

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Byte Ordering in Double-Width Mode

Figure 1-32: Byte Ordering Operation Example in Single-Width Mode

1-47

An example of a byte ordering operation in single-width mode (8-bit PMA-PCS interface width) where A is the predefined byte ordering pattern and P is the predefined pad pattern.

Transmitter Channel Receiver datain[15:8] D2 D3 D5 datain[7:0]

D1 A D4

Byte

Serializer

Byte

Deserializer

D1 A D4

XX D2 D3

Byte

Ordering

D1 P

XX D2

D3 D5 dataout[15:8]

A D4 dataout[7:0]

Byte Ordering in Double-Width Mode

Byte ordering is supported only when you enable the byte deserializer.

Table 1-29: Byte Ordering Operation in Double-Width Mode

PMA–PCS Interface Width

16 bits

20 bits

FPGA

Fabric–Transceiver

Interface Width

32 bits

32 bits

40 bits

8B/10B Decoder

Disabled

Enabled

Disabled

Byte Ordering

Pattern Length

8 or 16 bits

9

(4) or 18 bits

(5)

10 or 20 bits

Pad Pattern Length

8 bits

9 bits

(4)

10 bits

Figure 1-33: Byte Ordering Operation Example in Double-Width Mode

An example of a byte ordering operation in double-width mode (16-bit PMA-PCS interface width) where

A1A2 is the predefined byte ordering pattern and P is the predefined pad pattern.

Transmitter Channel Receiver datain[31:16]

(MSByte)

D2D3 datain[15:0]

(LSByte)

D0D1

D4D5 D8D9

B1B2 D6D7

Byte

Serializer

Byte

Deserializer

D0D1 A1A2 D6D7 xxxx D2D3 D4D5

Byte

Ordering

D0D1 xxxx

PP D4D5

D2D3 A1A2

D8D9

D6D7 dataout[31:16]

(MSByte) dataout[15:0]

(LSByte)

Word Aligner-Based Ordering Mode

In word aligner-based ordering mode, the byte ordering operation is controlled by the word aligner synchronization status signal, rx_syncstatus

.

After a rising edge on the rx_syncstatus signal, byte ordering looks for the byte ordering pattern in the byte-deserialized data.

(4)

(5)

The MSB of the 9-bit pattern represents the 1-bit control identifier of the 8B/10B-decoded data. The lower 8 bits represent the 8-bit decoded code.

The 18-bit pattern consists of two sets of 9-bit patterns, individually represented as in the previous note.

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Manual Ordering Mode

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When the first data byte that matches the byte ordering pattern is found, the byte ordering performs the following operations:

• If the pattern is not in the LSByte position—byte ordering inserts the appropriate number of pad patterns to push the byte ordering pattern to the LSByte position and indicates the byte alignment.

• If the pattern is in the LSByte position—byte ordering indicates the byte alignment.

Any byte misalignment found thereafter is ignored unless another rising edge on the rx_syncstatus signal, indicating resynchronization, is observed.

Manual Ordering Mode

In manual ordering mode, the byte ordering operation is controlled using the rx_enabyteord signal.

A rising edge on the rx_enabyteord signal triggers byte ordering to look for the byte ordering pattern in the byte-deserialized data.

When the first data byte that matches the byte ordering pattern is found, the byte ordering performs the following operations:

• If the pattern is not in the LSByte position—byte ordering inserts the appropriate number of pad patterns to push the byte ordering pattern to the LSByte position and indicates the byte alignment.

• If the pattern is in the LSByte position—byte ordering indicates the byte alignment.

Any byte misalignment found thereafter is ignored unless another rising edge on the rx_enabyteord signal is observed.

Receiver Phase Compensation FIFO

The receiver phase compensation FIFO is four words deep and interfaces the status and data signals between the receiver PCS and the FPGA fabric or the PCIe hard IP block.

The low-speed parallel clock feeds the write clock, while the FPGA fabric interface clock feeds the read clock.

The clocks must have 0 ppm difference in frequency or a receiver phase compensation FIFO underrun or overflow condition may result.

The FIFO supports the following operations:

• Phase compensation mode with various clocking modes on the read clock and write clock

• Registered mode with only one clock cycle of datapath latency

Figure 1-34: Receiver Phase Compensation FIFO

Datapath to the FPGA Fabric rx_clkout wr_clk

RX

Phase

Compensation

FIFO rd_clk

Datapath from the

Last PCS Block Used

Parallel Recovered Clock

(1)

tx_clkout

(1)

coreclkout

(1)

rx_coreclk

(1)

Note:

1. These clocks may have been divided by 2 if you used a byte deserializer.

Related Information

Transceiver Clocking in Cyclone V Devices.

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Registered Mode

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Registered Mode

To eliminate the FIFO latency uncertainty for applications with stringent datapath latency uncertainty requirements, bypass the FIFO functionality in registered mode to incur only one clock cycle of datapath latency when interfacing the transmitter channel to the FPGA fabric. Configure the FIFO to registered mode when interfacing the transmitter channel to the FPGA fabric or PCIe hard IP block to reduce datapath latency. In registered mode, the low-speed parallel clock that is used in the transmitter PCS clocks the FIFO.

Channel Bonding

The high-speed serial clock and low-speed parallel clock skew between channels and unequal latency in the transmitter phase compensation FIFO contribute to transmitter channel-to-channel skew. Bonded transmitter datapath clocking provides low channel-to-channel skew when compared with non-bonded channel configurations.

• Bonded channel configurations—the serial clock and parallel clock for all bonded channels are generated by the transmit PLL and central clock divider, resulting in lower channel-to-channel clock skew.

The transmitter phase compensation FIFO in all bonded channels share common pointers and control logic generated in the central clock divider, resulting in equal latency in the transmitter phase compensation FIFO of all bonded channels. The lower transceiver clock skew and equal latency in the transmitter phase compensation FIFOs in all channels provide lower channel-to-channel skew in bonded channel configurations.

• Non-bonded channel configurations—the parallel clock in each channel are generated independently by its local clock divider, resulting in higher channel-to-channel clock skew.

The transmitter phase compensation FIFO in each non-bonded channel has its own pointers and control logic that can result in unequal latency in the transmitter phase compensation FIFO of each channel. The higher transceiver clock skew and unequal latency in the transmitter phase compensation FIFO in each channel can result in higher channel-to-channel skew.

Related Information

Transceiver Clocking in Cyclone V Devices

PLL Sharing

In a Quartus II design, you can merge two different protocol configurations to share the same CMU PLL resources. These configurations must fit in the same transceiver bank and the input refclk and PLL output frequencies must be identical.

Document Revision History

The revision history for this chapter.

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Document Revision History

Table 1-30: Document Revision History

Date Version

May 2013

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Changes

• Updated the

6.144 Gbps CPRI Support Capability in GT

Devices

section.

• Added link to the known document issues in the

Knowledge Base

• Updated the

Transceiver Architecture in Cyclone V

Devices

section.

• Updated the

Architecture Overview

section.

• Updated the

Automatic Lock Mode

section.

• Updated the

Transmitter Buffer

section.

• Updated Table 1-2.

• Updated Table 1-5.

• Updated the

Rate Match FIFO

section.

• Updated the

Transceiver Banks

section.

• Added the

Channel Variants

section.

• Updated the

Transceiver Channel Architecture

section.

• Updated Figure 1-7.

• Updated the

Transmitter PLL

section.

• Updated the

Channel PLL Architecture

section.

• Updated the

Channel PLL as CDR PLL

section.

• Updated the

CDR PLL in Automatic Lock Mode

section.

• Added the

CDR PLL in Manual Lock Mode

section.

• Updated the

Channel PLL as a CMU PL

L section.

• Added the

fPLL as a Transmitter PLL

section.

• Updated the

Clock Divider

section.

• Updated the

Receiver PMA Datapath

section.

• Updated the

Receiver Buffer

section.

• Updated the

Programmable Receiver V

CM

section.

• Updated the

Transmitter PMA Datapath

section.

• Added the

Bit Reversal

section.

• Updated the

Transmitter Buffer

section.

• Updated the

Transmitter Buffer Features and Capabilities

section.

• Updated the

Transmitter Protocol Specific

section.

• Updated the

Calibration Block

section.

• Updated the

PCS Architecture

section.

• Updated the

Transmitter Phase Compensation FIFO

section.

• Added the

Registered Mode

section.

• Updated the

Byte Serializer

section.

• Updated the

8B/10B Encoder in Single-Width Mode

section.

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Date

December 2012

November 2012

June 2012

2012.11.19

1.1

Version

2012.12.03

Document Revision History

1-51

Changes

• Updated the

Word Aligner

section.

• Updated the

Word Aligner Options and Behaviors

section.

• Updated the

Word Aligner in Manual Alignment Mode

section.

• Updated the

Programmable Run-Length Violation

Detection

section.

• Updated the

Rate Match FIFO

section.

• Updated the

8B/10B Decoder

section.

• Updated the

Byte Deserializer

section.

• Updated the

Byte Ordering in Single-Width Mode

section.

• Updated the

Byte Ordering in Double-Width Mode

section.

• Added the

Word Aligner-Based Ordering Mode

section.

• Added the

Manual Ordering Mode

section.

• Updated the

Receiver Phase Compensation FIFO

section.

• Updated the

Channel Bonding

section.

• Updated the

PLL Sharing

section.

Clarified note to Figure 1-6 to indicate only certain transceiver channels support interfacing to PCIe.

Removed DC-Coupling information from Transmitter

Buffer Features and Capabilities and PMA Receiver Buffer.

Reorganized content and updated template

Added in contents of Transceiver Basics for Cyclone V

Devices.

Updated “Architecture Overview”, “PMA Architecture” and “PCS Architecture” sections.

Updated Table 1–11.

Updated Figure 1–36.

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This chapter provides information about the Cyclone

®

V transceiver clocking architecture. The chapter describes the clocks that are required for operation, internal clocking architecture, and clocking options when the transceiver interfaces with the FPGA fabric.

Figure 2-1: Transceiver Clocking Architecture Overview

2

Transceivers

Input Reference Clock

Transmit PLL or CDR

FPGA

Fabric

FPGA Fabric-Transceiver

Interface Clocks Internal Clocks Transceiver

Channels

Related Information

Cyclone V Device Handbook: Known Issues

Lists the planned updates to the

Cyclone V Device Handbook

chapters.

Input Reference Clocking

This section describes how the reference clock for the transmitter PLL and CDR is provided to generate the clocks required for transceiver operation.

Table 2-1: Input Reference Clock Sources

Sources

Dedicated refclk pin

REFCLK network

Dual-purpose RX / refclk pin

Fractional PLL

Transmitter PLL

CMU PLL

Yes

Yes

Yes

Yes

CDR

Yes

Yes

Yes

Yes

Jitter Performance

(6)

1

2

3

4

(6)

The lower number indicates better jitter performance.

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. Altera warrants performance of its semiconductor products to current specifications in accordance with

Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO

9001:2008

Registered www.altera.com

101 Innovation Drive, San Jose, CA 95134

2-2

Dedicated Reference Clock Pins

Sources

Generic

CLK pin

Core clock network (GCLK, RCLK,

PCLK)

Transmitter PLL

CMU PLL

No

No

CDR

No

No

Jitter Performance

(6)

5

6

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Dedicated Reference Clock Pins

Cyclone V devices have one dedicated reference clock ( refclk

) pin for each bank of three transceiver channels.

The dedicated reference clock pins drive the channel PLL in channel 1 or 4 directly. This option provides the best quality of input reference clock to the transmitter PLL and CDR.

Note:

For specifications about the input frequency supported by the refclk pins, refer to the

Cyclone V

Device Datasheet

.

As shown in the following figure the dedicated refclk pin direct connection to the channel PLL (which can be configured either as a CMU PLL or CDR) is only available in channel 1 of a transceiver bank and channel 4 of the neighboring transceiver bank.

(6)

The lower number indicates better jitter performance.

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Dedicated refclk Using the Reference Clock Network

Figure 2-2: Input Reference Clock Sources for Transceiver Channels

Reference Clock

Network

Dedicated refclk

Transmitter

Receiver

Transceiver

Channel 5

Channel PLL

N

GXB_L1

Transmitter

Receiver

Transceiver

Channel 4

Channel PLL

N

GXB_L0

Transmitter

Receiver

Dedicated refclk

Transmitter

Receiver

Transceiver

Channel 3

Channel PLL

Transceiver

Channel 2

Channel PLL

N

N

Transmitter

Receiver

Transceiver

Channel 1

Channel PLL

N

Transmitter

Receiver

Transceiver

Channel 0

Channel PLL

N

N (1)

Note (1):

N is the number of dedicated refclk pins, which equals the number of transceiver channels on a side divided by 3.

2-3

Related Information

Cyclone V Device Datasheet

Dedicated refclk Using the Reference Clock Network

Designs that use multiple channel PLLs with the same clock frequency can use the same dedicated refclk pin. Each dedicated refclk pin can drive any channel PLL (CMU PLL/CDR) and the fractional PLL through the reference clock network.

Figure 2-2

shows the input reference clock sources for six channel PLLs across two transceiver banks. For six transceiver channels, the total number of clock lines in the reference clock network is 2 (N = 6/3).

Dual-Purpose RX/refclk Pins

When not used as a receiver, an RX differential pair can be used as an additional input reference clock source.

The clock from the RX pins feed the RX clock network that spans all the channels on one side of the device.

Only one RX differential pair for every three channels can be used as input reference clock at a time. The following figure shows the use of dual-purpose RX/refclk differential pin as input reference clock source and the RX clock network.

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Fractional PLL (fPLL)

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Note:

• An RX differential pair from another bank can be used as an input reference clock pin on the same side of the device.

• refclk switching cannot be performed when dual-purpose RX differential pins are used refclk pins.

Figure 2-3: Dual-Purpose RX/refclk Pin as an Input Reference Clock

RX Clock

Network

N (1)

CH2 Channel PLL

Dual-Purpose RX/refclk Pin

CH1 Channel PLL

Dual-Purpose RX/refclk Pin

CH0 Channel PLL

Dual-Purpose RX/refclk Pin

Note (1): N is the number of transceiver channels on a side divided by 3.

fPLL

0

Fractional PLL (fPLL)

The fPLL clock output can be used as input reference clock source to transmitter PLL or CDR.

Cascading the fPLL to transmitter PLL or CDR enables you to use an input reference clock that is not supported by the transmitter PLL or CDR. The fPLL synthesizes a supported input reference clock for the transmitter PLL or CDR.

A fPLL is available for each bank of three transceiver channels. Each fPLL drives one of two fPLL cascade clock network lines that can provide an input reference clock to any transmitter PLL or CDR on the same side of a device. fPLLs support fractional and integer modes. The fractional mode allows you to synthesize a clock of any supported frequency, and the integer mode allows you to synthesize an output clock that is an integer multiple or factor of the input clock. For example, fPLLs allow you to take a 100 MHz clock and synthesize a clock of 50 or 200 MHz in integer mode, or 614.4 MHz in fractional mode.

Figure 2-4: fPLL Clock Output as Input Reference Clock

fPLL Cascade

Clock Network

2

CH2 Channel PLL

CH1 Channel PLL fPLL

0

CH0 Channel PLL

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Internal Clocking

2-5

Internal Clocking

This section describes the clocking architecture internal to Cyclone V transceivers.

Different physical coding sublayer (PCS) configurations and channel bonding options result in various transceiver clock paths.

Note:

The Quartus II software automatically performs the internal clock routing based on the transceiver configuration that you select.

The labels listed in the following table and figure mark the three sections of the transceiver internal clocking.

Table 2-2: Internal Clocking Subsections

Label

A

B

C

Scope

Transmitter Clock Network

Transmitter Clocking

Receiver Clocking

Description

Clock distribution from transmitter PLLs to channels

Clocking architecture within transmitter channel datapath

Clocking architecture within receiver channel datapath

Figure 2-5: Internal Clocking

Transmitter

Clock

Network

A

Transmit

PLL

Transceiver Channel

B

Transmitter

C

Receiver

CDR

Input

Reference Clock tx_serial_data rx_serial_data

Clock Lines

×1 ×6 ×N

Transceiver Channel

Transmitter

CDR

Receiver

Input

Reference Clock tx_serial_data rx_serial_data

Transmitter Clock Network

The transmitter PLL is comprised of the CMU PLL. All CMU PLLs are identical, but the usage varies depending on channel location due to the availability of access to the clock distribution network.

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Transmitter Clock Network

Table 2-3: Usage Capability of Each CMU PLL Within Two Transceiver Banks

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CMU PLL Location in Two Transceiver

Banks

CH 0

CH 1

Clock Network

Access

No

Yes

CH 2

CH 3

CH 4

CH 5

No

No

Yes

No

Usage Capability

Clock transmitter within same channel only

Clock transmitter within same channel only and other channels via clock network

Clock transmitter within same channel only

Clock transmitter within same channel only

Clock transmitter within same channel and other channels via clock network

Clock transmitter within same channel only

The transmitter clock network routes the clock from the transmitter PLL to the transmitter channel. As shown in the previous figure, the transmitter clock network routes the clock from the transmit PLL to the transmitter channel. A clock divider provides two clocks to the transmitter channel:

• Serial clock—high-speed clock for the serializer

• Parallel clock—low-speed clock for the serializer and the PCS

Cyclone V transceivers support non-bonded and bonded transceiver clocking configurations:

• Non-bonded configuration—Only the serial clock from the transmit PLL is routed to the transmitter channel. The clock divider of each channel generates the local parallel clock.

• Bonded configuration—Both the serial clock and parallel clock are routed from the central clock divider in channel 1 or 4 to the bonded transmitter channels.

The transmitter clock network is comprised of x1 (x1 and x1_fPLL), x6 and xN clock lines.

Table 2-4: Characteristics of x1, x6, and xN Clock Lines

Characteristics x1 x6 xN

Clock Source CMU PLL from CH 1 or CH 4 in two banks

(serial clock only)

Central clock divider from CH 1 or Ch 4 in two banks (serial and parallel clock ) x6 clock lines (serial and parallel clock)

Maximum Data Rate

(Gbps)

Clock Line Span

Non-bonded Configuration

Within two transceiver banks

Yes

Bonded Configuration

5.0 (GT and ST), 3.125

(GX and SX)

No

5.0 (GT and ST), 3.125

(GX and SX)

Within two transceiver banks

Yes

Yes

3.125

Across all channels on the same side of the device

Yes

Yes

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Figure 2-6: x1 Clock Line Architecture

Transmitter Clock Network

2-7

x1_top x1_bot

CMU PLL

CH5

Local Clock Divider

CMU PLL

CH4

Local Clock Divider

CMU PLL

CH3

Local Clock Divider

CMU PLL

CH2

Local Clock Divider

CMU PLL

CH1

Local Clock Divider

CMU PLL

CH0

Local Clock Divider

Note: All clock lines shown in this figure carry the serial clock only.

The x1 clock lines are driven by serial clocks of CMU PLLs from channels 1 and 4. The serial clock in the x1 clock line is then distributed to the local and central clock dividers of every channel within both the neighboring transceiver banks.

Note:

When you configure the channel PLL as a CMU PLL to drive the local clock divider, or the central clock divider of its own channel, you cannot use the channel PLL as a CDR. Without a CDR, you can use the channel only as a transmitter channel.

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Transmitter Clock Network

Figure 2-7: x6 and xN Clock Line Architecture

x6_top x6_bot xN_top xN_bot

CH5 Local Clock Divider

CH4 Central Clock

CH3 Local Clock Divider

CH2 Local Clock Divider

CH1 Central Clock

CH0 Local Clock Divider xN_top x6_top x6_bot xN_bot

CH5 Local Clock Divider

CH4 Central Clock

CH3 Local Clock Divider

CH2 Local Clock Divider

CH1 Central Clock

CH0 Local Clock Divider xN_top xN_bot

Note: All the clock lines shown in this figure carry both the serial and parallel clocks.

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The x6 clock lines are driven by serial and parallel clocks from the central clock divider in channels 1 and

4. For channels 0 to 5 within the 2 transceiver banks, the serial and parallel clocks in the x6 clock line are then distributed to every channel in both the transceiver banks.

The xN clock lines extend the clocking reach of the x6 clock line to all channels on the same side of the device. To reach a xN clock line, the clocks must be provided on the x6 clock line. The serial and parallel clocks in the x6 clock line are distributed to every channel within the two transceiver banks. The serial and parallel clocks are distributed to other channels beyond the two banks or the six channels using the xN clock line.

In bonded configurations, serial and parallel clocks from the x6 or xN clock lines are received by the clock divider of every bonded channel and fed directly to the serializer. In a non-bonded configuration, the clock divider of every non-bonded channel receives the serial clock from the x6 or xN clock lines and generates the individual parallel clock to the serializer.

Note:

In a bonded configuration, bonded channels must be placed contiguously without leaving a gap between the channels, except when the gap channel is a CMU PLL used for the bonded channels.

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Transmitter Clocking

2-9

The contiguous channels may span across many banks for bonded mode. For example, in x8 bonding, the bonded channels may span across 3 to 4 banks with the condition that there must be no gap between the channels except when the gap is due to the channel used for CMU PLL.

Transmitter Clocking

Transmitter (TX) clocking refers to the clocking architecture that is internal to the TX channel of a transceiver.

As shown in the following figure, the clock divider provides the serial clock to the serializer, and the parallel clock to the serializer and TX PCS. When the byte serializer is not used, the parallel clock clocks all the blocks up to the read side of the TX phase compensation FIFO. For configurations with the byte serializer, the parallel clock is divided by a factor of two for the byte serializer and the read side of the TX phase compensation FIFO. The read side clock of the TX phase compensation FIFO is also forwarded to the FPGA fabric to interface the FPGA fabric with the transceiver.

Figure 2-8: Clocking Architecture for Transmitter PCS and PMA Configuration

Transmitter PMA

Transmitter PCS FPGA Fabric

Local/Central clock divider

/2 tx_parallel_data tx_coreclkin / tx_std_coreclkin tx_clkout / tx_std_clkout

Both Parallel and Serial Clocks

Serial Clock

Parallel Clock

Data Path

Transmitter

Table 2-5: Clock Sources for All TX PCS Blocks

PCS Block Side

Write

TX Phase Compensation

FIFO

Byte Serializer

8B/10B Encoder

TX Bit Slip

Read

Write

Read

Clock Source

FPGA fabric write clock, driven either by tx_clkout or tx_ coreclkin

Parallel clock (divided). Clock forwarded to FPGA fabric as tx_ clkout

Parallel clock (divided) either by factor of 1 (not enabled), or factor of 2 (enabled)

Parallel clock

Parallel clock

Parallel clock

Non-Bonded Channel Configurations

This section describes the clock path for non-bonded configurations.

The following table describes the clock path for non-bonded configuration with the CMU PLL and fPLL as

TX PLL using various clock lines.

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Non-Bonded Channel Configurations

Table 2-6: Clock Path for Non-Bonded Configurations

Clock Line

x1 x6, xN

Transmitter PLL

CMU

CMU

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Clock Path

CMU PLL » x1 » individual clock divider » serializer

CMU PLL » central clock divider » x6 » xN » individual clock divider

» serializer

(7)

(7)

Non-bonded channels within the neighboring two banks or within the six channels of TX PLL are driven by clocks from x6 clock line. Channels in other banks outside the 6 channels are driven by the xN clock line.

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Non-Bonded Channel Configurations

2-11

Figure 2-9: Three Non-Bonded Transmitter Channels Driven by CMU PLL using x1 Clock Line Within a

Transceiver Bank

x1_top

TX PMA Ch5

TX PCS Ch5

Local Clock Divider

Clock Divider

TX PMA Ch4

TX PCS Ch4

Central Clock Divider

Clock Divider

TX PMA Ch3

TX PCS Ch3

CMU PLL

CMU PLL

Local Clock Divider

Clock Divider

Channels 0, 1, 2

Both Parallel and Serial Clocks

Serial Clock

Parallel Clock

Data Path

Unused Resources

CMU PLL

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Bonded Channel Configurations

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Figure 2-10: Three Non-Bonded Transmitter Channels Driven by CMU PLL using x6 and xN Clock Lines Across

Multiple Transceiver Banks

xN_top x6_bot x6_top

TX PMA Ch0

TX PCS Ch0

Local Clock Divider

Clock Divider x6_bot x6_top

TX PMA Ch5

TX PCS Ch5

Local Clock Divider

Clock Divider

TX PMA Ch4 TX PCS Ch4

CMU PLL

CMU PLL

Central Clock Divider

Clock Divider

TX PMA Ch3

TX PCS Ch3

CMU PLL

Local Clock Divider

Clock Divider

CMU PLL

xN_top Channels 0, 1, 2

Both Parallel and Serial Clocks

Serial Clock

Parallel Clock

Data Path

Unused Resources

Bonded Channel Configurations

This section describes the clock path for bonded configurations.

The following table describes the clock path for bonded configurations with the CMU PLL as TX PLL using various clock lines.

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Table 2-7: Clock Path for Bonded Configurations

Bonded Channel Configurations

2-13

Clock Line

x6, xN

Transmitter PLL

CMU

Clock Path

CMU PLL » central clock divider » x6 » xN » serializer

(8)

Figure 2-11: Four Bonded Transmitter Channels Driven by CMU PLL using x6 and xN Clock Line Across

Multiple Transceiver Banks

xN_top x6_bot x6_top

TX PMA Ch0

TX PCS Ch0

Local Clock Divider

Clock Divider x6_bot x6_top

TX PMA Ch5

TX PCS Ch5

Local Clock Divider

Clock Divider

TX PMA Ch4

TX PCS Ch4

Central Clock Divider

Clock Divider

TX PMA Ch3

TX PCS Ch3

CMU PLL

CMU PLL

CMU PLL

xN_top Channels 0, 1, 2

Local Clock Divider

Clock Divider

CMU PLL

Both Parallel and Serial Clocks

Serial Clock

Parallel Clock

Data Path

Unused Resources

(8)

Bonded channels within the neighboring two banks or within the six channels of TX PLL are driven by clocks from x6 clock line. Channels in other banks outside the 6 channels are driven by the xN clock line.

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Note:

When a channel PLL is configured as a CMU PLL to drive the local clock divider or the central clock divider of its own channel, the channel PLL cannot be used as a CDR. Without a CDR, the channel can be used only as a transmitter.

Receiver Clocking

This section describes receiver clocking, which is the clocking architecture internal to the receiver channel of a transceiver.

Figure 2-12: Clocking Architecture for Receiver PCS and PMA Configuration

Receiver PMA Receiver PCS FPGA Fabric

rx_parallel_data rx_coreclkin / rx_std_coreclkin

Parallel Clock

(Recovered)

Input

Reference

Clock

Parallel Clock (from the Clock Divider)

Data Path

Serial Clock

Parallel Clock

/2 rx_clkout / rx_std_clkout

The CDR in the PMA of each channel recovers the serial clock from the incoming data and generates the parallel clock (recovered) by dividing the serial clock (recovered). The deserializer uses both clocks. The receiver PCS can use the following clocks depending on the configuration of the receiver channel:

• Parallel clock (recovered) from the CDR in the PMA

• Parallel clock from the clock divider that is used by the channel’s transmitter PCS

Table 2-8: Clock Sources for All Receiver PCS Blocks

Block

Word aligner

Rate match FIFO

8B/10B decoder

Byte deserializer

Byte ordering

Side

-

Write

Read

-

Write

Read

-

Clock Source

Parallel clock (recovered)

Parallel clock (recovered)

Parallel clock from the clock divider

• Rate match FIFO is not used-Parallel clock (recovered)

• Rate match FIFO is used-Parallel clock from the clock divider

• Rate match FIFO is not used-Parallel clock (recovered)

• Rate match FIFO is used-Parallel clock from the clock divider

Divided down version of the write side clock depending on the deserialization factor of 1 or 2, also called the parallel clock (divided)

Parallel clock (divided)

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Block

Receiver (RX) phase compensation FIFO

Side

Write

Receiver Non-Bonded Channel Configurations

2-15

Clock Source

Parallel clock (divided). This clock is also forwarded to the

FPGA fabric.

Clock sourced from the FPGA fabric Read

Receiver Non-Bonded Channel Configurations

This section describes the receiver non-bonded channel configurations.

The receiver clocking in non-bonded mode varies depending on whether the rate match FIFO is enabled.

When the rate match FIFO is not enabled, the receiver PCS in every channel uses the parallel recovered clock. When the rate match FIFO is enabled, the receiver PCS in every channel uses both the parallel recovered clock and parallel clock from the clock divider.

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Receiver Non-Bonded Channel Configurations

Figure 2-13: Three Non-Bonded Receiver Channels without Rate Match FIFO Enabled

Receiver PMA Ch5

Receiver PCS Ch5

Parallel Clock

(Recovered)

Input

Reference

Clock

Parallel Clock

(from the

Clock Divider)

To Transmitter Channel

Local Clock Divider

Clock Divider

From the x6 or xN Clock Lines

Receiver PMA Ch4

Receiver PCS Ch4

CMU PLL

Parallel Clock

(Recovered)

Input

Reference

Clock

To Transmitter Channel

Parallel Clock

(from the

Clock Divider)

Central Clock Divider

Clock Divider

From the x6 or xN Clock Lines

Receiver PMA Ch3

Receiver PCS Ch3

CMU PLL

Parallel Clock

(Recovered)

Input

Reference

Clock

To Transmitter Channel

Parallel Clock

(from the

Clock Divider)

Local Clock Divider

Clock Divider

From the x6 or xN Clock Lines

Both Parallel and Serial Clocks

Serial Clock

Parallel Clock

Data Path

Unused Resources

CMU PLL

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Receiver Bonded Channel Configurations

Figure 2-14: Two Non-Bonded Receiver Channels with Rate Match FIFO Enabled

x1_top

Receiver PMA Ch5

Receiver PCS Ch5

2-17

Parallel Clock

(Recovered)

Input

Reference

Clock

Parallel Clock

(from the

Clock Divider)

Local Clock Divider

Clock Divider

To Transmitter Channel

Receiver PMA Ch4

Receiver PCS Ch4

Parallel Clock

(Recovered)

Input

Reference

Clock

Parallel Clock

(from the

Clock Divider)

Local Clock Divider

Clock Divider

To Transmitter Channel

Receiver PMA Ch3

Receiver PCS Ch3

CMU PLL

CMU PLL

Channels 0, 1, 2

Parallel Clock

(Recovered)

Input

Reference

Clock

Parallel Clock

(from the

Clock Divider)

Local Clock Divider

Clock Divider

To Transmitter Channel

Both Parallel and Serial Clocks

Serial Clock

Parallel Clock

Data Path

Unused Resources

CMU PLL

Receiver Bonded Channel Configurations

Receiver channels can only be bonded in configurations where rate match FIFOs are enabled. When bonded, the receiver PCS requires the parallel clock (recovered) and the parallel clock from the central clock divider in channel 1 or 4.

Note:

For more information about the clocking scheme used in different configurations, refer to the

Transceiver Protocol Configurations in Cyclone V Devices

and

Transceiver Custom Configurations in

Cyclone V Devices

chapters.

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FPGA Fabric–Transceiver Interface Clocking

Figure 2-15: Five Bonded Receiver Channels with Rate Match FIFO Enabled

Receiver PMA Ch5

CDR

Deserializer

Parallel Clock

(Recovered)

Input

Reference

Clock

To Transmitter Channel

Parallel Clock

(from the

Clock Divider)

Receiver PCS Ch5

Local Clock Divider

Clock Divider

Receiver PMA Ch4

CDR

Deserializer

Parallel Clock

(Recovered)

Input

Reference

Clock

To Transmitter Channel

Parallel Clock

(from the

Clock Divider)

Receiver PCS Ch4

Central Clock Divider

Clock Divider

From the x1

Clock Lines

CMU PLL

From the x1

Clock Lines

CMU PLL

x6 Clock Lines

Receiver PMA Ch3

CDR

Deserializer

Parallel Clock

(Recovered)

Input

Reference

Clock

To Transmitter Channel

Parallel Clock

(from the

Clock Divider)

Receiver PCS Ch3

Local Clock Divider

Clock Divider

Receiver PMA Ch2

CDR

Deserializer

Parallel Clock

(Recovered)

Input

Reference

Clock

To Transmitter Channel

Parallel Clock

(from the

Clock Divider)

Receiver PCS Ch2

Local Clock Divider

Clock Divider

Receiver PMA Ch1

CDR

Deserializer

Parallel Clock

(Recovered)

Input

Reference

Clock

To Transmitter Channel

Parallel Clock

(from the

Clock Divider)

Receiver PCS Ch1

Central Clock Divider

Clock Divider

Receiver PMA Ch0

CDR

Deserializer

Parallel Clock

(Recovered)

Input

Reference

Clock

To Transmitter Channel

Parallel Clock

(from the

Clock Divider)

Receiver PCS Ch0

Local Clock Divider

Clock Divider

Both Parallel and Serial Clocks

Serial Clock

Parallel Clock

Data Path

Unused Resources

Receiver

From the x1

Clock Lines

CMU PLL

From the x1

Clock Lines

CMU PLL

From the x1

Clock Lines

CMU PLL

From the x1

Clock Lines

CMU PLL

Related Information

Transceiver Protocol Configurations in Cyclone V Devices

Transceiver Custom Configurations in Cyclone V Devices

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FPGA Fabric–Transceiver Interface Clocking

This section describes the clocking options available when the transceiver interfaces with the FPGA fabric.

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FPGA Fabric–Transceiver Interface Clocking

2-19

The FPGA fabric-transceiver interface clocks consist of clock signals from the FPGA fabric to the transceiver blocks and clock signals from the transceiver blocks to the FPGA fabric. These clock resources use the clock networks in the FPGA core, including the global (GCLK), regional (RCLK), and periphery (PCLK) clock networks.

The FPGA fabric–transceiver interface clocks can be subdivided into the following three categories:

• Input reference clocks—Can be an FPGA fabric–transceiver interface clock. This may occur when the

FPGA fabric-transceiver interface clock is forwarded to the FPGA fabric, where it can then clock logic.

• Transceiver datapath interface clocks—Used to transfer data, control, and status signals between the

FPGA fabric and the transceiver channels. The transceiver channel forwards the tx_clkout signal to the FPGA fabric to clock the data and control signals into the transmitter. The transceiver channel also forwards the recovered rx_clkout clock (in configurations without the rate matcher) or the tx_clkout clock (in configurations with the rate matcher) to the FPGA fabric to clock the data and status signals from the receiver into the FPGA fabric.

• Other transceiver clocks—The following transceiver clocks form a part of the FPGA fabric–transceiver interface clocks:

• mgmt_clk

—Avalon

®

-MM interface clock used for controlling the transceivers, dynamic reconfiguration, and calibration

• fixed_clk

—the 125 MHz fixed-rate clock used in the PCIe (PIPE) receiver detect circuitry

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FPGA Fabric–Transceiver Interface Clocking

Table 2-9: FPGA Fabric–Transceiver Interface Clocks

Clock Name Clock Description Interface Direction

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FPGA Fabric Clock Resource

Utilization

tx_pll_refclk, rx_cdr_ refclk tx_clkout, tx_pma_clkout rx_clkout, rx_pma_clkout tx_coreclkin rx_coreclkin fixed_clk mgmt_clk

(9)

Input reference clock used for clocking logic in the FPGA fabric

Clock forwarded by the transceiver for clocking the transceiver datapath interface

Clock forwarded by the receiver for clocking the receiver datapath interface

User-selected clock for clocking the transmitter datapath interface

Transceiver-to-FPGA fabric

User-selected clock for clocking the receiver datapath interface

PCIe receiver detect clock

Avalon-MM interface management clock

FPGA fabric-totransceiver

GCLK, RCLK, PCLK

Note:

For more information about the GCLK, RCLK, and PCLK resources available in each device, refer to the

Clock Networks and PLLs in Cyclone V Devices

chapter.

(9)

The mgmt_clk is a free-running clock that is not derived from the transceiver blocks.

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Transceiver Datapath Interface Clocking

2-21

Related Information

Clock Networks and PLLs in Cyclone V Devices

Transceiver Datapath Interface Clocking

There are two types of design considerations for clock optimization when interfacing the transceiver datapath to the FPGA fabric:

• PCS with FIFO in phase compensation mode – share clock network for identical channels

• PCS with FIFO in registered mode or PMA direct mode – refer to

AN 580: Achieving Timing Closure in

Basic (PMA Direct) Functional Mode

, for additional timing closure techniques between transceiver and

FPGA fabric

The following sections describe design considerations for interfacing the PCS transmitter and PCS receiver datapath to the FPGA fabric with FIFO in phase compensation mode.

Related Information

AN 580: Achieving Timing Closure in Basic (PMA Direct) Functional Mode

Transmitter Datapath Interface Clocking

The write side of the TX phase compensation FIFO makes up the transmitter datapath interface. The transmitter datapath interface clock clocks this interface.

The following figure shows the transmitter datapath interface clocking. The transmitter PCS forwards the following clocks to the FPGA fabric:

• tx_clkout

—for each transmitter channel in a non-bonded configuration

• tx_clkout[0]

—for all transmitter channels in a bonded configuration

Figure 2-16: Transmitter Datapath Interface Clocking for Transceivers

Transmitter PCS

Transmitter Data

Parallel Clock

TX

Phase

Compensation

FIFO

Transmitter Data

FPGA Fabric

tx_coreclkin

(User Selected Clock) tx_clkout

(Quartus II Selected Clock) tx_clkout

All configurations that use the PCS channel must have a 0 parts per million (ppm) difference between write and read clocks of the transmitter phase compensation FIFO.

Note:

For more information about interface clocking for each configuration, refer to the T

Configuration in Cyclone V Devices

and

Transceiver Protocol Configurations in Cyclone V Devices

chapters.

ransceiver Custom

You can clock the transmitter datapath interface with one of the following options:

• The Quartus II-selected transmitter datapath interface clock

• The user-selected transmitter datapath interface clock

Note:

To reduce GCLK, RCLK, and PCLK resource utilization in your design, you can select the userselection option to share the transceiver datapath interface clocks.

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Quartus II-Software Selected Transmitter Datapath Interface Clock

Related Information

Transceiver Custom Configurations in Cyclone V Devices

Transceiver Protocol Configurations in Cyclone V Devices

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Quartus II-Software Selected Transmitter Datapath Interface Clock

The Quartus II software automatically selects the appropriate clock from the FPGA fabric to clock the transmitter datapath interface.

The following figure shows the transmitter datapath interface of two transceiver non-bonded channels clocked by their respective transmitter PCS clocks, which are forwarded to the FPGA fabric.

Figure 2-17: Transmitter Datapath Interface Clocking for Non-Bonded Channels

FPGA Fabric Channel 1

Transmitter Data

TX

Phase

Compensation

FIFO

Transmitter Data

Channel 1 Transmitter

Data and Control Logic tx_coreclkin[1] tx_clkout[1]

Parallel Clock

Channel 0

Transmitter Data

TX

Phase

Compensation

FIFO

Transmitter Data

Channel 0 Transmitter

Data and Control Logic tx_coreclkin[0] tx_clkout[0]

Parallel Clock

The following figure shows the transmitter datapath interface of three bonded channels clocked by the tx_clkout[0] clock. The tx_clkout[0] clock is derived from the central clock divider of channel 1 or 4 of the two transceiver banks.

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Selecting a Transmitter Datapath Interface Clock

Figure 2-18: Transmitter Datapath Interface Clocking for Three Bonded Channels

Channel 2

Transmitter Data

TX

Phase

Compensation

FIFO

Transmitter Data

FPGA Fabric

Channel 2 Transmitter

Data and Control Logic tx_coreclkin[2]

Channel 1

Parallel Clock

Transmitter Data

TX

Phase

Compensation

FIFO

Transmitter Data

Channel 1 Transmitter

Data and Control Logic tx_coreclkin[1] tx_clkout[0]

Channel 0

Parallel Clock

Transmitter Data

TX

Phase

Compensation

FIFO

Transmitter Data

Channel 0 Transmitter

Data and Control Logic tx_coreclkin[0]

Parallel Clock

2-23

Selecting a Transmitter Datapath Interface Clock

Multiple non-bonded transmitter channels use a large portion of GCLK, RCLK, and PCLK resources.

Selecting a common clock driver for the transmitter datapath interface of all identical transmitter channels saves clock resources.

Multiple transmitter channels that are non-bonded lead to high utilization of GCLK, RCLK, and PCLK resources (one clock resource per channel). You can significantly reduce GCLK, RCLK, and PCLK resource use for transmitter datapath clocks if the transmitter channels are identical.

Note:

Identical transmitter channels have the same input reference clock source, transmit PLL configuration, transmitter PMA, and PCS configuration, but may have different analog settings, such as transmitter voltage output differential (V

OD

), transmitter common-mode voltage (V

CM

), or pre-emphasis settings.

To achieve the clock resource savings, select a common clock driver for the transmitter datapath interface of all identical transmitter channels. The following figure shows six identical channels clocked by a single clock ( tx_clkout of channel 4).

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Selecting a Transmitter Datapath Interface Clock

Figure 2-19: Six Identical Channels with a Single User-Selected Transmitter Interface Clock

Transceivers

Channel 7 tx_coreclkin[7]

FPGA Fabric

tx_coreclkin[6]

Channel 6 tx_coreclkin[5]

Channel 5

Channel 4 tx_coreclkin[4] Channel [7:0] Transmitter

Data and Control Logic tx_clkout[4] tx_coreclkin[3]

Channel 3 tx_coreclkin[2]

Channel 2 tx_coreclkin[1]

Channel 1 tx_coreclkin[0]

Channel 0

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To clock six identical channels with a single clock, perform these steps:

1. Instantiate the tx_coreclkin port for all the identical transmitter channels ( tx_coreclkin[5:0]

).

2. Connect tx_clkout[4] to the tx_coreclkin[5:0] ports.

3. Connect tx_clkout[4] to the transmitter data and control logic for all six channels.

Note:

Resetting or powering down channel 4 causes a loss of the clock for all six channels.

The common clock must have a 0 ppm difference for the read side of the transmitter phase compensation

FIFO of all the identical channels. A frequency difference causes the FIFO to under run or overflow, depending on whether the common clock is slower or faster, respectively.

You can drive the 0 ppm common clock by one of the following sources:

• tx_clkout of any channel in non-bonded channel configurations

• tx_clkout[0] in bonded channel configurations

• Dedicated refclk pins

Note:

The Quartus II software does not allow gated clocks or clocks that are generated in the FPGA logic to drive the tx_coreclkin ports.

You must ensure a 0 ppm difference. The Quartus II software is unable to ensure a 0 ppm difference because it allows you to use external pins, such as dedicated refclk pins.

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Receiver Datapath Interface Clock

2-25

Receiver Datapath Interface Clock

The read side of the RX phase compensation FIFO makes up the 6-Gbps receiver datapath interface. The receiver datapath interface clock clocks this interface.

The receiver PCS forwards the following clocks to the FPGA fabric:

• rx_clkout

—for each receiver channel in a non-bonded configuration when you do not use a rate matcher

• tx_clkout

—for each receiver channel in a non-bonded configuration when you use a rate matcher

• single rx_clkout[0]

—for all receiver channels in a bonded configuration

Figure 2-20: Receiver Datapath Interface Clocking

Receiver PCS

Receiver Data

Parallel Clock (Recovered Clock)

RX

Phase

Compensation

FIFO

Receiver Data

FPGA Fabric

rx_coreclkin

(User Selected Clock) rx_clkout/tx_clkout

(Quartus II Selected Clock) rx_clkout

All configurations that use the PCS channel must have a 0 ppm difference between the receiver datapath interface clock and the read side clock of the RX phase compensation FIFO.

Note:

For more information about interface clocking for each configuration, refer to the

Configuration in Cyclone V Devices

and

Transceiver Protocol Configurations in Cyclone V Devices

chapters.

Transceiver Custom

You can clock the receiver datapath interface with one of the following options:

• The Quartus II-selected receiver datapath interface clock

• The user-selected receiver datapath interface clock

Note:

To reduce GCLK, RCLK, and PCLK resource utilization in your design, you can select the userselection option to share the transceiver datapath interface clocks.

Related Information

Transceiver Custom Configuration in Cyclone V Devices

Transceiver Protocol Configurations in Cyclone V Devices

Quartus II Software-Selected Receiver Datapath Interface Clock

Quartus II automatically selects the appropriate clock from the FPGA fabric to clock the receiver datapath interface.

The following figure shows the receiver datapath interface of two transceiver non-bonded channels clocked by their respective receiver PCS clocks, which are forwarded to the FPGA fabric.

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Quartus II Software-Selected Receiver Datapath Interface Clock

Figure 2-21: Receiver Datapath Interface Clocking for Non-Bonded Channels

Channel 1

Receiver Data

RX

Phase

Compensation

FIFO

Receiver Data

FPGA Fabric

Channel 1 Receiver

Data and Status Logic rx_coreclkin[1]

Parallel Clock (Recovered Clock)

Channel 0

Receiver Data rx_clkout[1]/tx_clkout[1]

RX

Phase

Compensation

FIFO

Receiver Data

Channel 0 Receiver

Data and Status Logic rx_coreclkin[0] rx_clkout[0]/tx_clkout[0]

Parallel Clock (Recovered Clock)

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The following figure shows the receiver datapath interface of three bonded channels clocked by the tx_clkout[0] clock. The tx_clkout[0] clock is derived from the central clock divider of channel 1 or 4 of the two transceiver banks.

Figure 2-22: Receiver Datapath Interface Clocking for Three Bonded Channels

Channel 2 FPGA Fabric

Receiver Data

RX

Phase

Compensation

FIFO

Receiver Data

Channel 2 Receiver

Data and Status Logic rx_coreclkin[2]

Channel 1

Parallel Clock (Recovered Clock)

Receiver Data

RX

Phase

Compensation

FIFO

Receiver Data

Channel 1 Receiver

Data and Status Logic rx_coreclkin[1]

Channel 0

Parallel Clock (Recovered Clock)

Receiver Data

RX

Phase

Compensation

FIFO rx_clkout[0]

Receiver Data

Channel 0 Receiver

Data and Status Logic rx_coreclkin[0]

Parallel Clock (Recovered Clock)

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Selecting a Receiver Datapath Interface Clock

2-27

Selecting a Receiver Datapath Interface Clock

Multiple non-bonded receiver channels use a large portion of GCLK, RCLK, and PCLK resources. Selecting a common clock driver for the receiver datapath interface of all identical receiver channels saves clock resources.

Non-bonded multiple receiver channels lead to high utilization of GCLK, RCLK, and PCLK resources (one clock resource per channel). You can significantly reduce GCLK, RCLK, and PCLK resource use for the receiver datapath clocks if the receiver channels are identical.

Note:

Identical receiver channels are defined as channels that have the same input reference clock source for the CDR and the same receiver PMA and PCS configuration. These channels may have different analog settings, such as receiver common mode voltage (V

ICM

), equalization, or DC gain setting.

To achieve clock resource savings, select a common clock driver for the receiver datapath interface of all identical receiver channels. To select a common clock driver, perform these steps:

1. Instantiate the rx_coreclkin port for all the identical receiver channels

2. Connect the common clock driver to their receiver datapath interface, and receiver data and control logic.

The following figure shows six identical channels that are clocked by a single clock ( rx_clkout[0]

).

Figure 2-23: Six Identical Channels with a Single User-Selected Receiver Interface Clock

Receiver Standard PCS

Channel 7

FPGA Fabric

rx_coreclkin[7] rx_coreclkin[6]

Channel 6 rx_coreclkin[5]

Channel 5

Channel 4 rx_coreclkin[4]

Channel [7:0] Receiver

Data and Control Logic rx_clkout[4] rx_coreclkin[3]

Channel 3 rx_coreclkin[2]

Channel 2 rx_coreclkin[1]

Channel 1 rx_coreclkin[0]

Channel 0

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Document Revision History

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To clock six identical channels with a single clock, perform these steps:

• Instantiate the rx_coreclkin port for all the identical receiver channels ( rx_coreclkin[5:0]

).

• Connect rx_clkout[4] to the rx_coreclkin[5:0] ports.

• Connect rx_clkout[4] to the receiver data and control logic for all six channels.

Note:

Resetting or powering down channel 4 leads to a loss of the clock for all six channels.

The common clock must have a 0 ppm difference for the write side of the RX phase compensation FIFO of all the identical channels. A frequency difference causes the FIFO to under run or overflow, depending on whether the common clock is faster or slower, respectively.

You can drive the 0 ppm common clock driver from one of the following sources:

• tx_clkout of any channel in non-bonded receiver channel configurations with the rate matcher

• rx_clkout of any channel in non-bonded receiver channel configurations without the rate matcher

• tx_clkout[0] in bonded receiver channel configurations

• Dedicated refclk pins

Note:

The Quartus II software does not allow gated clocks or clocks generated in the FPGA logic to drive the rx_coreclkin ports.

Note:

You must ensure a 0 ppm difference. The Quartus II software is unable to ensure a 0 ppm difference because it allows you to use external pins, such as dedicated refclk pins.

Document Revision History

The table below lists the revision history for this chapter.

Table 2-10: Document Revision History

Date

May 2013

November 2012

June 2012

October 2011

Version

2013.05.06

2012.11.19

1.1

1.0

Changes

• Updated Content for Quartus II software version 13.0

• Updated figure "Input Reference Clock Sources for Transceiver

Channels"

• Added a section on "Dual-Purpose RX/refclk Pins".

• Added link to the known document issues in the Knowledge Base.

• Reorganized content and updated template.

• Updated for the Quartus II software version 12.1.

Minor editorial changes.

Initial release.

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Altera’s recommended reset sequence ensures that both the physical coding sublayer (PCS) and physical medium attachment (PMA) in each transceiver channel are initialized and functioning correctly.

Related Information

Cyclone V Device Handbook: Known Issues

Lists the planned updates to the

Cyclone V Device Handbook

chapters.

3

PHY IP Embedded Reset Controller

The embedded reset controller in the PHY IP enables you to initialize the transceiver physical coding sublayer

(PCS) and physical medium attachment (PMA) blocks.

To simplify your transceiver-based design, the embedded reset controller provides an option that requires only one control input to implement an automatic reset sequence. Only one embedded reset controller is available for all the channels in a PHY IP instance.

The embedded reset controller automatically performs the entire transceiver reset sequence whenever the phy_mgmt_clk_reset signal is triggered. In case of loss-of-link or loss-of-data, the embedded reset controller asserts the appropriate reset signals. You must monitor tx_ready and rx_ready

. A high on these status signals indicates the transceiver is out of reset and ready for data transmission and reception.

Note:

Deassert the mgmt_rst_reset signal of the transceiver reconfiguration controller before or at the same time as phy_mgmt_clk_reset to start calibration.

Note:

The PHY IP embedded reset controller is enabled by default in all transceiver PHY IP cores except the Native PHY IP core.

Embedded Reset Controller Signals

The following figure shows the embedded reset controller and signals in the PHY IP instance. These signals reset your transceiver when you use the embedded reset controller.

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. Altera warrants performance of its semiconductor products to current specifications in accordance with

Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

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3-2

Embedded Reset Controller Signals

Figure 3-1: Embedded Reset Controller

Transceiver PHY

Receiver

PCS rx_digitalreset tx_digitalreset

Transmitter

PCS rx_is_lockedtodata

Receiver

PMA

CDR pll_is_locked rx_analogreset

Transmitter

PMA

Transmitter

PLL pll_powerdown tx_analogreset phy_mgmt_clk phy_mgmt_clk_reset

Embedded Reset Controller

Avalon-MM

Interface

Avalon-MM

PHY Management

S M

PCS and PMA Control and Status Register

Memory Map

S

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tx_ready rx_ready pll_locked rx_is_lockedtodata rx_is_lockedtoref reconfig_busy reconfig_to_xcvr reconfig_from_xcvr

Transceiver

Reconfiguration

Controller mgmt_clk_clk mgmt_rst_reset

Table 3-1: Embedded Reset Controller Reset Control and Status Signals

Signal Name

phy_mgmt_clk phy_mgmt_clk_reset tx_ready rx_ready

Signal

Control Input

Control Input

Status Output

Status Output

Description

Clock for the embedded reset controller.

A high-to-low transition of this asynchronous reset signal initiates the automatic reset sequence control.

Hold this signal high to keep the reset signals asserted.

A continuous high on this signal indicates that the transmitter (TX) channel is out of reset and is ready for data transmission. This signal is synchronous to phy_mgmt_clk

.

A continuous high on this signal indicates that the receiver (RX) channel is out of reset and is ready for data reception. This signal is synchronous to phy_ mgmt_clk

.

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pll_locked mgmt_clk_clk

Resetting the Transceiver with the PHY IP Embedded Reset Controller during Device Power-Up

Signal Name

reconfig_busy rx_is_lockedtodata rx_is_lockedtoref mgmt_rst_reset

Signal

Status Output

Status Output

Status Output

Status Output

Clock

Reset

Description

3-3

An output from the Transceiver Reconfiguration

Controller block indicates the status of the dynamic reconfiguration controller. At the first mgmt_clk_ clk clock cycle after power-up, reconfig_busy remains low.

This signal is asserted from the second mgmt_clk_ clk clock cycle to indicate that the calibration process is in progress . When the calibration process is completed, the reconfig_busy signal is deasserted.

This signal is also routed to the embedded reset controller by the Quartus

®

II software by embedding the signal in the reconfig_to_xcvr bus between the PHY IP and the Transceiver Reconfiguration

Controller.

This signal is asserted when the TX PLL achieves lock to the input reference clock. When this signal is asserted high, the embedded reset controller deasserts the tx_digitalreset signal.

This signal is an optional output status port. When asserted, this signal indicates that the CDR is locked to the RX data and the CDR has changed from lockto-reference (LTR) to lock-to-data (LTD) mode.

This is an optional output status port. When asserted, this signal indicates that the CDR is locked to the reference clock.

Clock for the Transceiver Reconfiguration Controller.

This clock must be stable before releasing mgmt_ rst_reset

.

Reset for the Transceiver Reconfiguration Controller

Resetting the Transceiver with the PHY IP Embedded Reset Controller during Device

Power-Up

Follow this reset sequence to ensure a reliable link initialization after the initial power-up.

The numbers in the following figure correspond to the following numbered list, which guides you through the transceiver reset sequence during device power-up.

1. During device power-up, mgmt_rst_reset and phy_mgmt_clk_reset must be asserted to initialize the reset sequence.

phy_mgmt_clk_reset holds the transceiver blocks in reset and mgmt_rst_reset is required to start the calibration IPs. Both these signals should be held asserted for a minimum of two phy_mgmt_clk clock cycles. Deassert phy_mgmt_clk_reset at the same time as mgmt_rst_reset

.

2. After the transmitter calibration and reset sequence are complete, the tx_ready status signal is asserted and remains asserted to indicate that the transmitter is ready to transmit data.

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3. After the receiver calibration and reset sequence are complete, the rx_ready status signal is asserted and remains asserted to indicate that the receiver is ready to receive data.

Note:

If the tx_ready and rx_ready signals do not stay asserted, the reset sequence did not complete successfully and the link will be down.

Figure 3-2: Reset Sequence Timing Diagram Using Embedded Reset Controller during Device

Power-Up

Control Signals

mgmt_rst_reset phy_mgmt_clk_reset tx_ready rx_ready

1

1

2

3

Status Signals

reconfig_busy pll_locked rx_is_lockedtodata

Resetting the Transceiver with the PHY IP Embedded Reset Controller during Device

Operation

Follow this reset sequence to reset the entire transceiver at any point during the device operation, to re-establishing a link, or after certain dynamic reconfigurations.

The numbers in the following figure correspond to the numbered list, which guides you through the transceiver reset sequence during device operation.

1. Assert phy_mgmt_clk_reset for two phy_mgmt_clk clock cycles to re-start the entire transceiver reset sequence.

2. After the transmitter reset sequence is complete, the tx_ready status signal is asserted and remains asserted to indicate that the transmitter is ready to transmit data.

3. After the receiver reset sequence is complete, the rx_ready status signal is asserted and remains asserted to indicate that the receiver is ready to receive data.

Note:

If the tx_ready and rx_ready signals do not stay asserted, the reset sequence did not complete successfully and the link will be down.

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User-Coded Reset Controller

Figure 3-3: Reset Sequence Timing Diagram Using Embedded Reset Controller during Device

Operation

Control Signals

phy_mgmt_clk_reset tx_ready

1

2

3 rx_ready

Status Signals

reconfig_busy pll_locked rx_is_lockedtodata

Note:

To reset the transmitter and receiver analog and digital blocks separately without repeating the entire reset sequence, use the Avalon Memory Map registers.

3-5

User-Coded Reset Controller

You must implement external reset controller logic (user-coded reset controller) if you disable the embedded reset controller to initialize the transceiver physical coding sublayer (PCS) and physical medium attachment

(PMA) blocks.

You can implement a user-coded reset controller with one of the following:

• Using your own Verilog/VHDL code to implement the reset sequence

• Using the Quartus II MegaWizard Plug-In Manager, which provides a ready-made reset controller IP to place your own verilog/vhdl code

Note:

You must disable the embedded reset controller before using the user-coded reset controller.

Note:

The embedded reset controller can only be disabled for non-protocol transceiver PHY IPs, such as custom PHY, low latency PHY and deterministic latency PHY. Native PHY IP does not have an embedded reset controller, so you must implement your own reset logic.

If you implement your own reset controller, consider the following:

• The user-coded reset controller must be level sensitive (active high)

• The user-coded reset controller does not depend on phy_mgmt_clk_reset

• You must provide a clock and reset to the reset controller logic

• The internal signals of the PHY IP embedded reset controller are configured as ports

• You can hold the transceiver channels in reset by asserting the appropriate reset control signals

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Related Information

"Transceiver PHY Reset Controller IP Core" chapter of the Altera Transceiver PHY IP Core User Guide.

For information about the transceiver PHY reset controller.

User-Coded Reset Controller Signals

Use the signals in the following figure and table with a user-coded reset controller.

Figure 3-4: Interaction Between the Transceiver PHY Instance, Transceiver Reconfiguration Controller, and the User-Coded Reset Controller

User-Coded

Reset Controller

clock reset

Transceiver PHY Instance

pll_powerdown tx_digitalreset tx_analogreset rx_digitalreset rx_analogreset pll_locked tx_cal_busy rx_cal_busy rx_is_lockedtoref rx_is_lockedtodata

Receiver

PCS

Transmitter

PCS

Receiver

PMA

CDR

Transmitter

PMA

Transmitter

PLL mgmt_rst_reset mgmt_clk_clk reconfig_from_xcvr reconfig_to_xcvr

Transceiver

Reconfiguration

Controller reconfig_busy

Table 3-2: Signals Used by the Transceiver PHY instance, Transceiver Reconfiguration Controller, and User-Coded

Reset Controller

Signal Name

mgmt_clk_clk mgmt_rst_reset pll_powerdown tx_analogreset tx_digitalreset rx_analogreset rx_digitalreset reconfig_busy tx_cal_busy

Signal Type

Clock

Reset

Control

Control

Control

Control

Control

Status

Status

Description

Clock for the Transceiver Reconfiguration Controller.

This clock must be stable before releasing mgmt_ rst_reset

.

Reset for the Transceiver Reconfiguration Controller

Resets the TX PLL when asserted high

Resets the TX PMA when asserted high

Resets the TX PCS when asserted high

Resets the RX PMA when asserted high

Resets the RX PCS when asserted high

A high on this signal indicates that reconfiguration is active

A high on this signal indicates that TX calibration is active

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Signal Name

rx_cal_busy pll_locked

Resetting the Transmitter with the User-Coded Reset Controller during Device Power-Up

rx_is_lockedtoref rx_is_lockedtodata

Signal Type

Status

Status

Status

Status

Description

3-7

A high on this signal indicates that RX calibration is active

A high on this signal indicates that the TX PLL is locked

A high on this signal indicates that the RX CDR is in the lock to reference (LTR) mode

A high on this signal indicates that the RX CDR is in the lock to data (LTD) mode

Resetting the Transmitter with the User-Coded Reset Controller during Device Power-Up

Follow this reset sequence when designing your User-Coder Reset Controller to ensure a reliable transmitter initialization after the initial power-up.

The numbers in the figure correspond to the following numbered list, which guides you through the transmitter reset sequence during device power-up.

1. To reset the transmitter, begin with:

• Assert mgmt_rst_reset at power-up to start the calibration IPs. Hold mgmt_rst_reset active for a minimum of two reset controller clock cycles.

• Assert and hold pll_powerdown

, tx_analogreset

, and tx_digitalreset at power-up to reset the transmitter. You can deassert tx_analogreset at the same time as pll_powerdown

.

2. After the transmitter PLL locks, the pll_locked status gets asserted after t pll_lock

.

3. After the transmitter calibration completes, the tx_cal_busy status is deasserted. Depending on the transmitter calibrations, this could happen before or after the pll_locked is asserted.

4. Deassert tx_digitalreset after the gating conditions occur for a minimum duration of t tx_digitalreset

.

The gating conditions are:

• pll_powerdown is deasserted

• pll_locked is asserted

• tx_cal_busy is deasserted

The transmitter is out of reset and ready for operation.

Note:

During calibration, pll_locked might assert and deassert as the calibration IP runs.

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Resetting the Transmitter with the User-Coded Reset Controller during Device Operation

Figure 3-5: Reset Sequence Timing Diagram for Transmitter using the User-Coded Reset Controller during Device Power-Up

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mgmt_rst_reset pll_powerdown tx_analogreset tx_digitalreset pll_locked tx_cal_busy

1

1

1

1

2 t pll_lock

max 10 μs

3

4 t tx_digitalreset

min 20 ns

Table 3-3: Guidelines for Resetting the PLL, TX PMA, and TX PCS

To Reset

PLL

TX PMA

TX PCS

You Must Reset

pll_powerdown tx_analogreset tx_digitalreset tx_analogreset tx_digitalreset tx_digitalreset

Resetting the Transmitter with the User-Coded Reset Controller during Device Operation

Follow this reset sequence if you want to reset the PLL, or analog or digital blocks of the transmitter at any point during device operation. This might be necessary for re-establishing a link or after certain dynamic reconfigurations.

The numbers in the following figure correspond to the following numbered list, which guides you through the transmitter reset sequence during device operation.

1. To reset the transmitter:

• Assert pll_powerdown

, tx_analogreset and tx_digitalreset

.

tx_digitalreset must be asserted every time pll_powerdown and tx_analogreset are asserted to reset the

PCS blocks.

• Hold

pll_powerdown asserted for a minimum duration of t pll_powerdown

.

• Deassert tx_analogreset at the same time or after pll_powerdown is deasserted.

2. After the transmitter PLL locks, the pll_locked status is asserted after t pll_lock

. While the TX PLL locks, the pll_locked status signal may toggle. It is asserted after t pll_lock

.

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Resetting the Receiver with the User-Coded Reset Controller during Device Power-Up Configuration

3-9

3. Deassert tx_digitalreset after a minimum duration of t tx_digitalreset

, and after all the gating conditions are removed:

• pll_powerdown is deasserted

• pll_locked is deasserted

Figure 3-6: Reset Sequence Timing Diagram for Transmitter using the User-Coded Reset Controller during Device Operation

mgmt_rst_reset pll_powerdown tx_analogreset tx_digitalreset pll_locked tx_cal_busy

1

1

1

1 t pll_powerdown

min 1 μs

2

3 t tx_digitalreset

min 20ns

t pll_lock

max 10 μs

Resetting the Receiver with the User-Coded Reset Controller during Device Power-Up

Configuration

Follow this reset sequence to ensure a reliable receiver initialization after the initial power-up.

The numbers in the following figure correspond to the following numbered list, which guides you through the receiver reset sequence during device power-up.

1. Assert mgmt_rst_reset at power-up to start the calibration IPs. Hold mgmt_rst_reset active for a minimum of two mgmt_clk_clock cycles. Hold rx_analogreset and rx_digitalreset active at power-up to hold the receiver in reset. You can deassert them after all the gating conditions are removed.

2. After the receiver calibration completes, the rx_cal_busy status is de-asserted.

3. Deassert rx_analogreset after a minimum duration of t rx_analogreset after rx_cal_busy is deasserted.

4.

rx_is_lockedtodata is a status signal from the receiver CDR indicating that the CDR is in the lock to data (LTD) mode. Ensure rx_is_lockedtodata is asserted and stays asserted for a minimum duration of t

LTD before deasserting rx_digitalreset toggles, you must wait another additional t

LTD

. If rx_is_lockedtodata duration before deasserting is asserted and rx_digitalreset

.

5. Deassert rx_digitalreset after a minimum duration of t

LTD after rx_is_lockedtodata asserted. Ensure rx_analogreset and rx_cal_busy are deasserted before deasserting rx_digitalreset

.

stays

The receiver is now out of reset and ready for operation.

Note:

rx_is_lockedtodata might toggle when there is no data at the receiver input.

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Resetting the Receiver with the User-Coded Reset Controller during Device Operation

Note:

rx_is_lockedtoref is a don't care when rx_is_lockedtodata is asserted.

Note:

rx_analogreset must always be followed by rx_digitalreset

.

Figure 3-7: Reset Sequence Timing Diagram for Receiver using the User-Coded Reset Controller during Device Power-Up

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mgmt_rst_reset rx_analogreset rx_digitalreset rx_is_lockedtodata rx_cal_busy

1

1

1

2

3 t rx_analogreset

two clock cycles of the user reset control

5 t

LTD

4

Related Information

Transceiver Architecture in Cyclone V Devices

For information about CDR lock modes.

Resetting the Receiver with the User-Coded Reset Controller during Device Operation

Follow this reset sequence to reset the analog or digital blocks of the receiver at any point during the device operation. This might be necessary for re-establishing a link or after certain dynamic reconfigurations.

The numbers in the following figure correspond to the following numbered list, which guides you through the receiver reset sequence during device operation.

1. Assert rx_analogreset and rx_digitalreset at any point independently. However, you must assert rx_digitalreset every time rx_analogreset is asserted to reset the PCS blocks.

2. Deassert rx_analogreset after a minimum duration of 40 ns (t rx_analogreset

).

3.

rx_is_lockedtodata is a status signal from the receiver CDR that indicates that the CDR is in the lock to data (LTD) mode. Ensure rx_is_lockedtodata is asserted and stays asserted before deasserting rx_digitalreset

.

4. Deassert rx_digitalreset after a minimum duration of t

LTD asserted. Ensure rx_analogreset is de-asserted.

after rx_is_lockedtodata stays

Note:

rx_is_lockedtodata might toggle when there is no data at the receiver input.

rx_is_lockedtoref is a don't care when rx_is_lockedtodata is asserted.

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Figure 3-8: Reset Sequence Timing Diagram for Receiver using the User-Coded Reset Controller during Device Operation

mgmt_rst_reset rx_analogreset rx_digitalreset rx_is_lockedtodata

1

1

2 t rx_analogreset

two clock cycles of user control reset

4 t

LTD

3 rx_cal_busy

3-11

Related Information

Transceiver Architecture in Cyclone V Devices

For information about CDR lock modes.

Transceiver Reset Using Avalon Memory Map Registers

You can use Memory Map registers within the PHY IP instance to control the reset signals through the

Avalon Memory Map interface.

This gives the flexibility of resetting the PLL, and transmitter and receiver analog and digital blocks separately without repeating the entire reset sequence.

Transceiver Reset Control Signals Using Avalon Memory Map Registers

The following table lists the memory map registers for CDR lock mode and channel reset. These signals help you reset your transceiver when you use Memory Map registers within the PHY IP.

Table 3-4: Transceiver Reset Control Using Memory Map Registers

Register Name

pma_rx_set_locktodata pma_rx_set_locktoref

Description

This register is for CDR manual lock mode only. When you set the register to high, the RX CDR PLL is in the lock to data (LTD) mode. The default is low when both registers have the CDR in auto lock mode.

This register is for CDR manual lock mode only. When you set the register to high, the RX CDR PLL is in the lock to reference

(LTR) mode if pma_rx_set_lockedtodata is not asserted.

The default is low when both registers have the CDR in auto lock mode.

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Register Name

reset_tx_digital

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Description

When you set this register to high, the tx_digitalreset signal is asserted in every channel that is enabled for reset control through the reset_ch_bitmask register. To deassert the tx_digitalreset signal, set the reset_tx_digital register to 0.

reset_rx_analog reset_rx_digital reset_ch_bitmask pll_powerdown

When you set this register to high, the rx_analogreset signal is asserted in every channel that is enabled for reset control through the reset_ch_bitmask register. To deassert the rx_analogreset signal, set the reset_rx_analog register to 0.

When you set this register to high, the rx_digitalreset signal is asserted in every channel that is enabled for reset control through the reset_ch_bitmask register. To deassert the rx_digitalreset signal, set the reset_rx_digital register to 0.

The registers provide an option to enable or disable certain channels in a PHY IP instance for reset control. By default, all channels in a PHY IP instance are enabled for reset control.

When asserted, the TX phase-locked loop (PLL) is turned off.

Related Information

Altera Transceiver PHY IP Core User Guide

For information about register addresses.

Clock Data Recovery Manual Lock Mode Reset Sequence

Use the clock data recovery (CDR) manual lock mode to override the default CDR automatic lock mode.

The two control signals to enable and control the CDR in manual lock mode are rx_set_locktoref and rx_set_locktodata

.

Control Settings for CDR Manual Lock Mode

Use the following control signals to reset the transceiver when the CDR is in manual lock mode.

Table 3-5: Control Settings for the CDR in Manual Lock Mode rx_set_locktoref

0

1

X

rx_set_locktodata

0

0

1

CDR Lock Mode

Automatic

Manual-RX CDR LTR

Manual-RX CDR LTD

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3-13

Resetting the Transceiver in CDR Manual Lock Mode

Follow this sequence to reset your transceiver when the CDR is in manual lock mode.

The numbers in the following figure correspond to the following numbered list, which guides you through the steps to put the CDR in manual lock mode.

1. Make sure that the calibration is complete ( rx_cal_busy is low) and the transceiver goes through the initial reset sequence. The rx_digitalreset and rx_analogreset signals should be low. The rx_is_lockedtoref is a don't care and can be either high or low. The rx_is_lockedtodata and rx_ready signals should be high, indicating that the transceiver is out of reset. Alternatively, you can start directly with the CDR in manual lock mode after the calibration is complete.

2. Assert the rx_set_locktoref signal high to switch the CDR to the lock-to-reference mode. The rx_is_lockedtodata status signal gets de-asserted. Assert the rx_digitalreset signal high at the same time or after rx_set_lockedtoref is asserted if you use the user-controlled reset. When the Transceiver PHY reset controller is used, the rx_digitalreset is automatically asserted.

3. After the rx_digitalreset signal gets asserted, the rx_ready status signal gets de-asserted.

4. Assert the rx_set_locktodata signal high after t

LTR_LTD_manual to switch the CDR to the lock-todata mode. The rx_is_lockedtodata status signal gets asserted when it acquires lock to the data.

The rx_is_lockedtoref status signal can be a high or low and can be ignored.

5. Deassert the rx_digitalreset signal after t

LTD_Manual

.

6. After the rx_digitalreset signal is de-asserted, the rx_ready status signal gets asserted if you are using the Transceiver PHY Reset Controller, indicating that the receiver is now ready to receive data with the CDR in manual mode.

Figure 3-9: Reset Sequence Timing Diagram for Transceiver when CDR is in Manual Lock Mode

Control Signals

rx_set_locktoref rx_set_locktodata rx_digitalreset

1 rx_analogreset

Status Signals

rx_is_lockedtoref

1

1 rx_is_lockedtodata

1 rx_ready

1

2

2

2 t

LTR_LTD_manual

min 15 μs

4

3

4 t

LTD_Manual

min 4 μs

5

6

Resetting the Transceiver During Dynamic Reconfiguration

Reset is required for transceiver during dynamic reconfiguration except in the PMA Analog Control

Reconfiguration mode.

In general, follow these guidelines when dynamically reconfiguring the transceiver:

1. Hold the targeted channel and PLL in the reset state before dynamic reconfiguration starts.

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Guidelines for Dynamic Reconfiguration if Transmitter Duty Cycle Distortion Calibration is Required during

Device Operation

2. Repeat the sequence as needed after dynamic reconfiguration is complete, which is indicated by deassertion of the reconfig_busy

, tx_cal_busy

, rx_cal_busy signals.

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Guidelines for Dynamic Reconfiguration if Transmitter Duty Cycle Distortion Calibration is Required during Device Operation

If transmitter duty cycle distortion calibration is required during device operation, ensure the general guidelines for transceiver dynamic reconfiguration are followed. Additionally, use the following recommendations:

1. Do not connect tx_cal_busy to the transceiver Reset Controller IP.

2. Disable the embedded reset controller and use an external reset controller.

Note:

If channel reconfiguration is required before TX DCD calibration, ensure the following:

• The TX PLL, TX channel, and Transceiver Reconfiguration Controller blocks must not be in the reset state during TX DCD calibration. Ensure the following signals are not asserted during

TX DCD calibration:

• pll_powerdown

• tx_digitalreset

• tx_analogreset

• mgmt_rst_reset

Repeat the reset sequence when TX DCD calibration is complete.

Transceiver Blocks Affected by the Reset and Powerdown Signals

The following table lists blocks that are affected by specific reset and powerdown signals

Table 3-6: Transceiver Blocks Affected

Transceiver Block

CMU PLL

Receiver Word Aligner

Receiver Deskew FIFO

Receiver Rate Match FIFO

Receiver 8B/10B Decoder

Receiver Byte Deserializer

Receiver Byte Ordering

pll_ powerdown

Yes

rx_digitalreset

PLL

rx_analogreset tx_digitalreset

Receiver Standard PCS

Yes —

Yes

Yes

Yes

Yes

Yes

tx_analogreset

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Transceiver Power-Down

Transceiver Block

Receiver Phase Compensation FIFO

pll_ powerdown

Receiver Buffer

Receiver CDR

Receiver Deserializer

rx_digitalreset

Yes

rx_analogreset tx_digitalreset

Receiver PMA

Yes

Yes

— Yes

Transmitter Standard PCS

— —

Yes Transmitter Phase

Compensation FIFO

Byte Serializer

8B/10B Encoder

Transmitter Bit-Slip

Transmitter CGB

Serializer

Transmitter Buffer

Transmitter PMA

— —

Yes

Yes

Yes

Yes

Yes

Yes

3-15 tx_analogreset

Transceiver Power-Down

To maximize power savings, enable PMA hard power-down across all channels on a side of the device where you do not use the transceivers.

The hard power-down granularity control of the transceiver PMA is per side. To enable PMA hard powerdown on the left or right side of the device, ground the transceiver power supply of the respective side.

Related Information

Cyclone V Device Datasheet

For information about the transceiver power supply operating conditions of the left and right side of Cyclone

V devices.

Document Revision History

Date Version Changes

• Changed term of User-Controlled

Reset Controller to User-Coded

Reset Controller.

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Document Revision History

Date

May 2013

November 2012

November 2011

August 2011

1.1

1.0

2013.05.06

Version

2012.11.19

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Changes

• Updated the guidelines for Dynamic

Reconfiguration if TX DCD

Calibration is required during device operation.

• Added link to the known document issues in the Knowledge Base.

• Rewritten and reorganized content, and updated template

• Updated reset sequence procedures

• Included sequences for resetting transceiver during device operation

• Added “User-Controlled Reset

Controller” section.

• Updated Figure 3–1 and Table 3–1.

Initial release.

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The dedicated transceiver physical coding sublayer (PCS) and physical medium attachment (PMA) circuitry supports the following communication protocols.

Table 4-1: Transceiver PCS Features for Cyclone V Devices

PCS Support

PCI Express

®

(PCIe

®

) Gen1

(x1, x2, and x4) and Gen2 (x1, x2, and x4)

2.5, 5

Gbps Ethernet (GbE)

Serial Digital Interface (SDI)

SATA, SAS

Common Public Radio

Interface (CPRI)

Data Rates (Gbps)

1.25, 3.125

0.27

(10)

, 1.485, and

2.97

Transmitter Datapath Receiver Datapath

PIPE (PHY Interface for the PCIe architecture) interface to the

PCIe Hard IP

PIPE interface to the PCIe

Hard IP

The same as custom single- and doublewidth modes

The same as custom singleand double-width modes, plus the rate match FIFO

Phase compensation

FIFO and byte serializer

Phase compensation FIFO and byte deserializer

1.5 and 3.0

Phase compensation

FIFO, byte serializer, and 8B/10B encoder

Phase compensation FIFO, byte deserializer, word aligner, and 8B/10B decoder

0.6144, 1.2288,

2.4576, 3.072, 4.9152,

6.144

(11)

The same as custom single- and doublewidth modes, plus the transmitter (TX) deterministic latency

The same as custom singleand double-width modes, plus the receiver (RX) deterministic latency

4

(10)

(11)

The 0.27 gigabits per second (Gbps) data rate is supported using oversampling user logic that must be implemented by the user in the FPGA core.

Cyclone V GT devices support data rates greater than 5.0 Gbps only in CPRI.

©

2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with

Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO

9001:2008

Registered www.altera.com

101 Innovation Drive, San Jose, CA 95134

4-2

PCI Express

OBSAI

PCS Support

XAUI

Data Rates (Gbps)

0.768, 1.536, 3.072

3.125

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Transmitter Datapath Receiver Datapath

The same as custom single- and doublewidth modes, plus the

TX deterministic latency

The same as custom singleand double-width modes, plus the RX deterministic latency

Implemented using soft PCS

Implemented using soft PCS

Related Information

Use this chapter along with the Altera Transceiver PHY IP Core User Guide.

Upcoming Cyclone V Device Features

Cyclone V Device Handbook: Known Issues

Lists the planned updates to the

Cyclone V Device Handbook

chapters.

PCI Express

The Cyclone Vdevices have PCIe Hard IP that is designed for performance, ease-of-use, and increased functionality. The Hard IP consists of the media access control (MAC) lane, data link, and transaction layers.

The PCIe Hard IP supports the PCIe Gen1 end point and root port up to x4 lane configurations. The PCIe endpoint support includes multifunction support for up to eight functions and Gen2 x4 lane configurations.

Figure 4-1: PCIe Multifunction for Cyclone V Devices

External System

Host CPU

FPGA Device

PCIe Link

Root

Complex

Local

Peripheral 1

Local

Peripheral 2

The Cyclone V PCIe Hard IP operates independently from the core logic, which allows the PCIe link to wake up and complete link training in less than 100 ms while the Cyclone V device completes loading the programming file for the rest of the device.

In addition, the Cyclone V device PCIe Hard IP has improved end-to-end datapath protection using error correction code (ECC).

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PIPE Transceiver Datapath

Figure 4-2: Transceivers in a PCIe Hard IP Configuration

Functional Mode

Data Rate (Gbps)

Number of Bonded Channels

PMA–PCS Interface Width

Word Aligner (Pattern)

8B/10B Encoder/Decoder

Rate Match FIFO

PCIe Hard IP

Byte SERDES

PCS–Hard IP Interface Width

(Per lane)

PCS–Hard IP Interface Frequency

PCIe HIP

2.5 for Gen1 5 for Gen2 x1, x2, x4

10-Bit

Automatic Synchronization

State Machine (/K28.5+/K28.5-/)

Enabled

Enabled

Enabled

Disabled

8-Bit

Gen1 - 250 MHz

Gen2 - 500 MHz

PIPE Transceiver Datapath

4-3

Note:

Refer to the

Cyclone V Device Datasheet

for the mgmt_clk_clk frequency specification when PCIe

HIP is used.

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PCIe Supported Features

Transceiver Channel Datapath

Figure 4-3: Transceiver Channel Datapath in a PIPE Configuration

Transmitter PMA

Transmitter PCS

/2

Receiver PMA

Receiver PCS

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PCIe hard IP

/2

Parallel Clock

Serial Clock

Parallel and Serial Clocks

Parallel and serial clocks

(only from the central clock divider)

Clock Divider

Central/ Local Clock Divider

Parallel and serial clocks (from the ×6 clock lines)

CMU PLL

Serial clock

(from the ×1 clock lines)

Related Information

Transceiver Architecture in Cyclone V Devices

Cyclone V Device Datasheet

PCIe Supported Features

The PIPE configuration for the 2.5 Gbps (Gen1) and 5 Gbps (Gen2) data rates supports these features:

• PCIe-compliant synchronization state machine

• x1 and x4 link configurations

• ±300 parts per million (ppm)—total 600 ppm—clock rate compensation

• 8-bit FPGA fabric–transceiver interface

• 16-bit FPGA fabric–transceiver interface

• Transmitter buffer electrical idle

• Receiver detection

• 8B/10B encoder disparity control when transmitting compliance pattern

• Power state management (Electrical Idle only)

• Receiver status encoding

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PIPE Interface

4-5

PIPE Interface

In a PIPE configuration, each channel has a PIPE interface block that transfers data, control, and status signals between the PHY-MAC layer and the transceiver channel PCS and PMA blocks.

Note:

The PIPE interface block is used in a PIPE configuration and cannot be bypassed.

In addition to transferring data, control, and status signals between the PHY-MAC layer and the transceiver, the PIPE interface block implements the following functions that are required in a PCIe-compliant physical layer device:

• Forces the transmitter buffer into an electrical idle state

• Initiates the receiver detect sequence

• Controls the 8B/10B encoder disparity when transmitting a compliance pattern

• Manages the PCIe power states (Electrical Idle only)

• Indicates the completion of various PHY functions, such as receiver detection and power state transitions on the pipe_phystatus signal

• Encodes the receiver status and error conditions on the pipe_rxstatus[2:0] signal, as specified in the PCIe specification

Transmitter Electrical Idle Generation

The PIPE interface block places the channel transmitter buffer in an electrical idle state when the electrical idle input signal is asserted.

During electrical idle, the transmitter buffer differential and common configuration output voltage levels are compliant to the PCIe Base Specification 2.1 for the PCIe Gen2 data rate.

The PCIe specification requires that the transmitter buffer be placed in electrical idle in certain power states.

Power State Management

The PCIe specification defines four power states: P0, P0s, P1, and P2.

The physical layer device must support these power states to minimize power consumption:

• P0 is the normal operating state during which packet data is transferred on the PCIe link.

• P0s, P1, and P2 are low-power states into which the physical layer must transition as directed by the

PHY-MAC layer to minimize power consumption.

The PIPE interface in the transceivers provides an input port for each transceiver channel configured in a

PIPE configuration.

Note:

When transitioning from the P0 power state to lower power states (P0s, P1, and P2), the PCIe specification requires that the physical layer device implements power saving measures. The transceivers do not implement these power saving measures except to place the transmitter buffer in electrical idle in the lower power states.

8B/10B Encoder Usage for Compliance Pattern Transmission Support

The PCIe transmitter transmits a compliance pattern when the Link Training and Status State Machine

(LTSSM) enters a polling compliance substate. The polling compliance substate assesses if the transmitter is electrically compliant with the PCIe voltage and timing specifications.

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Receiver Status

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Receiver Status

The PCIe specification requires that the PHY encode the receiver status on a 3-bit status signal

( pipe_rxstatus[2:0]

).

This status signal is used by the PHY-MAC layer for its operation. The PIPE interface block receives the status signals from the transceiver channel PCS and PMA blocks, and encodes the status on the pipe_rxstatus[2:0] signal to the FPGA fabric. The encoding of the status signals on the pipe_rxstatus[2:0] signal is compliant with the PCIe specification.

Receiver Detection

The PIPE interface block in Cyclone V transceivers provides an input signal

( pipe_txdetectrx_loopback

) for the receiver detect operation that is required by the PCIe protocol during the detect substate of the LTSSM.

When the pipe_txdetectrx_loopback signal is asserted in the P1 power state, the PCIe interface block sends a command signal to the transmitter buffer in that channel to initiate a receiver detect sequence.

In the P1 power state, the transmitter buffer must always be in the electrical idle state.

After receiving this command signal, the receiver detect circuitry creates a step voltage at the output of the transmitter buffer. If an active receiver that complies with the PCIe input impedance requirements is present at the far end, the time constant of the step voltage on the trace is higher than if the receiver is not present.

The receiver detect circuitry monitors the time constant of the step signal that is seen on the trace to determine if a receiver was detected. The receiver detect circuitry monitor requires a 125-MHz clock for operation that you must drive on the fixedclk port.

Note:

For the receiver detect circuitry to function reliably, the AC-coupling capacitor on the serial link and the receiver termination values used in your system must be compliant with the PCIe Base Specification

2.1.

The PCI Express PHY (PIPE) IP core provides a 1-bit PHY status ( pipe_phystatus

) and a 3-bit receiver status signal ( pipe_rxstatus[2:0]

) to indicate whether a receiver was detected or not, in accordance to the PIPE specifications.

Clock Rate Compensation Up to ±300 ppm

In compliance with the PCIe protocol, the receiver channels are equipped with a rate match FIFO to compensate for the small clock frequency differences of up to ± 300 ppm between the upstream transmitter and local receiver clocks.

Related Information

Transceiver Architecture in Cyclone V Devices

PCIe Reverse Parallel Loopback

The PCIe reverse parallel loopback is only available in the PCIe functional configuration for the Gen1 data rate. The received serial data passes through the receiver CDR, deserializer, word aligner, and rate matching

FIFO buffer. It is then looped back to the transmitter serializer and transmitted out through the transmitter buffer. The received data is also available to the FPGA fabric through the port.

PCIe reverse parallel loopback mode is compliant with PCIe specification 2.1.

Cyclone V devices provide the pipe_txdetectrx_loopback input signal to enable this loopback mode. If the pipe_txdetectrx_loopback signal is asserted in the P1 power state, receiver detection is performed. If the signal is asserted in the P0 power state, reverse parallel loopback is performed.

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PCIe Supported Configurations and Placement Guidelines

4-7

Note:

The PCIe reverse parallel loopback is the only loopback option that is supported in PIPE configurations.

Figure 4-4: PIPE Reverse Parallel Loopback Mode Datapath

Transmitter PMA

Transmitter PCS

PCIe hard IP

Receiver PMA

Receiver PCS

Reverse Parallel

Loopback Path

/2

/2

Parallel Clock

Serial Clock

Parallel and Serial Clocks

Parallel and serial clocks

(only from the central clock divider)

Clock Divider

Central/ Local Clock Divider

Parallel and serial clocks (from the ×6 clock lines)

CMU PLL

Serial clock

(from the ×1 clock lines)

PCIe Supported Configurations and Placement Guidelines

Placement by the Quartus II software may vary with design and device. The following figures show examples of transceiver channel and PCIe Hard IP block locations, supported x1, x2, and x4 bonding configurations, and channel placement guidelines. The Quartus II software automatically places the CMU PLL in a channel different from that of the data channels.

Note:

This section shows the supported PCIe channel placement if you use both the top and bottom PCIe Hard IP blocks in the device separately.

In the following figures, channels shaded in blue provide the high-speed serial clock. Channels shaded in gray are data channels.

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Figure 4-5: 12 Transceiver Channels and 2 PCIe HIP Blocks with PCIe x2 and x4 Channel Placement

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PCIe x4

PCIe x2

Transceiver Bank

Ch5

Ch4

Ch3

CMU PLL

Ch2

Ch1

Ch0

Master

PCIe x4

PCIe x2

Transceiver Bank

Ch5

Ch4

Ch3

Ch2

Ch1

Ch0

CMU PLL

Master

PCIe

Hard IP

PCIe

Hard IP

Figure 4-6: 12 Transceiver Channels and 2 PCIe HIP Blocks with PCIe x1 Channel Placement

PCIe x1

Transceiver Bank

Ch5

Ch4

Ch3

Ch2

Ch1

Ch0

CMU PLL

Master

PCIe x1

Transceiver Bank

Ch5

Ch4

Ch3

Ch2

Ch1

Ch0

CMU PLL

Master

PCIe

Hard IP

PCIe

Hard IP

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Figure 4-7: 9 Transceiver Channels and 2 PCIe HIP Blocks with PCIe x2 and x4 Channel Placement

The grayed out PCIe Hard IP block is not used in this example

Transceiver Bank

Ch2

Ch1

Ch0

PCIe

Hard IP

4-9

PCIe x4

PCIe x2

Transceiver Bank

Ch5

Ch4

Ch3

Ch2

Ch1

Ch0

CMU PLL

Master

PCIe

Hard IP

Figure 4-8: 9 Transceiver Channels and 2 PCIe HIP Blocks with PCIe x1 Channel Placement

PCIe x1

Transceiver Bank

Ch2

Ch1

Ch0

CMU PLL

Master

PCIe

Hard IP

PCIe x1

Transceiver Bank

Ch5

Ch4

Ch3

Ch2

Ch1

Ch0

CMU PLL

Master

PCIe

Hard IP

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PCIe Supported Configurations and Placement Guidelines

Figure 4-9: 6 Transceiver Channels and 1 PCIe HIP Blocks with PCIe x2 and x4 Channel Placement

The grayed out PCIe Hard IP block is not used in this example.

PCIe x4

PCIe x2

Transceiver Bank

Ch5

Ch4

Ch3

Ch2

Ch1

Ch0

CMU PLL

Master

PCIe

Hard IP

PCIe

Hard IP

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Figure 4-10: 6 Transceiver Channels and 2 PCIe HIP with PCIe x1 Channel Placement

The grayed out PCIe Hard IP block is not used in this example.

PCIe x1

Transceiver Bank

Ch5

Master

Ch4

CMU PLL

Ch3

Ch2

Ch1

Ch0

PCIe

Hard IP

PCIe

Hard IP

–OR–

PCIe x1

Transceiver Bank

Ch5

Ch4

Ch3

Ch2

Ch1

Ch0

CMU PLL

Master

PCIe

Hard IP

PCIe

Hard IP

Figure 4-11: 3 Transceiver Channels and 1 PCIe HIP Blocks with PCIe x1 Channel Placement

PCIe x1

Transceiver Bank

Ch2

Ch1

Ch0

CMU PLL

Master

PCIe

Hard IP

For PCIe Gen1 and Gen2, there are restrictions on the achievable x1 and x4 bonding configurations if you intend to use both top and bottom Hard IP blocks in the device.

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Gigabit Ethernet

Table 4-2: Hard IP Configurations for PCIe Gen1 and Gen2

The following table lists the configurations allowed for each Cyclone V device when you use both PCIe Hard

IP blocks on the top and bottom transceiver banks. Support will vary by the number of transceiver channels in a device.

Top PCIe Hard IP Bottom PCIe

Hard IP

5CGXC4,

5CGXC5,

5CGTD5, 5CSXC5,

5CSTD5

5CGXC7,

5CGTD7, 5CSXC6,

5CSTD6

5CGXC9, 5CGTD9

x1 x2 x4 x1 x2 x4 x1 x2 x4 x1 x2 x4

Yes

No

No

No

No

No

No

No

No

Yes

Yes

Yes

No

No

No

No

No

No

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

Yes

4-11

The following table lists the maximum number of data channels that can be enabled to ensure the channels meet the PCIe Gen2 Transmit Jitter Specification. Follow this recommendation when planning channel placement for PCIe Gen2 using Cyclone V GT or Cyclone V ST device variants.

Table 4-3: Recommended Channel Placement for PCIe Gen2

CMU channels are not counted as data channels.

Device

5CGTD7F672, 5CGTD7F896, 5CGTD9F672,

5CSTD5F896, 5CSTD6F896

5CGTD9F896, 5CGTD9F1152

Maximum Channels Utilization

6

8

Related Information

Transceiver Architecture in Cyclone V Devices

Gigabit Ethernet

The IEEE 802.3 specification defines the 1000BASE-X PHY as an intermediate, or transition layer that interfaces various physical media with the MAC in a gigabit ethernet (GbE) system, shielding the MAC layer from the specific nature of the underlying medium. The 1000BASE-X PHY is divided into the PCS, PMA, and PMD sublayers.

The PCS sublayer interfaces with the MAC through the gigabit media independent interface (GMII). The

1000BASE-X PHY defines a physical interface data rate of 1 Gbps and 2.5 Gbps.

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Gigabit Ethernet

Figure 4-12: 1000BASE-X PHY in a GbE OSI Reference Model

OSI Reference

Model Layers

Application

Presentation

Session

Transport

Network

Data Link

Physical

LAN

CSMA/CD Layers

Higher Layers

LLC

MAC (Optional)

MAC

Reconciliation

GMII

PCS

PMA

PMD

1000 Base-X PHY

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The transceivers, when configured in GbE functional mode, have built-in circuitry to support the following

PCS and PMA functions, as defined in the IEEE 802.3 specification:

• 8B/10B encoding and decoding

• Synchronization

• Upstream transmitter and local receiver clock frequency compensation (rate matching)

• Clock recovery from the encoded data forwarded by the receiver PMD

• Serialization and deserialization

Note:

The transceivers do not have built-in support for other PCS functions, such as the autonegotiation state machine, collision-detect, and carrier-sense functions. If you require these functions, implement them in the FPGA fabric or in external circuits.

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Figure 4-13: Transceiver Blocks in a GbE Configuration

Functional Mode

PMA-PCS Interface Width

Data Rate (Gbps)

Number of Bonded Channels

Low Latency PCS

Word Aligner (Pattern Length)

8B/10B Encoder/Decoder

Rate Match FIFO

Byte SERDES

Byte Ordering

FPGA Fabric-Transceiver

Interface Width

FPGA Fabric-Transceiver

Interface Frequency (MHz)

Gigabit Ethernet Transceiver Datapath

4-13

Gbe

10 bit

1.25

x1

Disabled

Automatic Synchronization

State Machine

(7-bit Comma, 10-bit /K28.5/)

Enabled

Enabled

Disabled

Disabled

8-bit

125

3.125

x1

Disabled

Automatic Synchronization

State Machine

(7-bit Comma, 10-bit /K28.5/)

Enabled

Enabled

Enabled

Disabled

16-bit

156.25

Gigabit Ethernet Transceiver Datapath

Figure 4-14: Transceiver Datapath in GbE-1.25 Gbps Configuration

FPGA Fabric Transmitter Channel PCS

TX Phase

Compensation

FIFO wrclk rdclk

8B/10B

Encoder tx_coreclk[0]

Low-Speed Parallel Clock tx_clkout[0]

FPGA Fabric–Transceiver Interface Clock rx_coreclk[0]

RX Phase

Compensation

FIFO

8B/10B

Decoder

Receiver Channel PCS

Rate

Match

FIFO

Word

Aligner

Parallel Recovered Clock

Low-Speed Parallel Clock

Serializer

Local Clock

Divider

Transmitter Channel PMA

High-Speed Serial Clock

Receiver Channel PMA

Deserializer CDR

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Gigabit Ethernet Transceiver Datapath

Figure 4-15: Transceiver Datapath in GbE-3.125 Gbps Configuration

FPGA Fabric Transmitter Channel PCS

TX Phase

Compensation

FIFO wrclk rdclk

Byte

SERDES

8B/10B

Encoder tx_coreclk[0]

Low-Speed Parallel Clock tx_clkout[0]

FPGA Fabric–Transceiver Interface Clock rx_coreclk[0]

RX Phase

Compensation

FIFO

Byte

SERDES

8B/10B

Decoder

Receiver Channel PCS

Rate

Match

FIFO

Word

Aligner

Low-Speed Parallel Clock

Parallel Recovered Clock

Serializer

Transmitter Channel PMA

High-Speed Serial Clock

Local Clock

Divider

Receiver Channel PMA

Deserializer CDR

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Table 4-4: Transceiver Datapath Clock Frequencies in GbE Configuration

Functional Mode Data Rate High-Speed Serial

Clock Frequency

625 MHz

Parallel Recovered

Clock and Low-Speed

Parallel Clock

Frequency

125 MHz

FPGA Fabric-Transceiver Interface

Clock Frequency

125 MHz GbE-1.25

Gbps

GbE-3.125

Gbps

1.25 Gbps

3.125 Gbps 1562.5 MHz 312.5 MHz 156.25 MHz

8B/10B Encoder

In GbE configuration, the 8B/10B encoder clocks in 8-bit data and 1-bit control identifiers from the transmitter phase compensation FIFO and generates 10-bit encoded data. The 10-bit encoded data is fed to the serializer.

For more information about the 8B/10B encoder functionality, refer to the

Transceiver Architecture for

Cyclone V Devices

chapter.

Rate Match FIFO

In GbE configuration, the rate match FIFO is capable of compensating for up to ±100 ppm (200 ppm total) difference between the upstream transmitter and the local receiver reference clock. The GbE protocol requires that the transmitter send idle ordered sets /I1/ (/K28.5/D5.6/) and /I2/ (/K28.5/D16.2/) during interpacket gaps, adhering to the rules listed in the IEEE 802.3 specification.

The rate match operation begins after the synchronization state machine in the word aligner indicates that the synchronization is acquired-by driving the rx_syncstatus signal high. The rate matcher always deletes or inserts both symbols (/K28.5/ and /D16.2/) of the /I2/ ordered sets, even if only one symbol needs to be deleted to prevent the rate match FIFO from overflowing or underrunning. The rate matcher can insert or delete as many /I2/ ordered sets as necessary to perform the rate match operation.

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Gigabit Ethernet Transceiver Datapath

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Two flags are forwarded to the FPGA fabric:

• rx_rmfifodatadeleted

- Asserted for two clock cycles for each deleted /I2/ ordered set to indicate the rate match FIFO deletion event

• rx_rmfifodatainserted

- Asserted for two clock cycles for each inserted /I2/ ordered set to indicate the rate match FIFO insertion event

For more information about the rate match FIFO, refer to the

Transceiver Architecture for Cyclone V

Devices

chapter.

GbE Protocol-Ordered Sets and Special Code Groups

Table 4-5: GIGE Ordered Sets

The following ordered sets and special code groups are specified in the IEEE 802.3-2008 specification.

Code Ordered Set Number of Code

Groups

Encoding

/C/

Configuration

— Alternating /C1/ and /C2/

/C1/ Configuration 1 4 /K28.5/D21.5/

Config_Reg

(12)

/I2/

-

/R/

/S/

/T/

/C2/

/I/

/I1/

/V/

Configuration 2

IDLE

IDLE 1

IDLE 2

Encapsulation

Carrier_Extend

Start_of_Packet

End_of_Packet

Error_Propagation

1

1

2

1

4

2

1

/K28.5/D2.2/

Config_Reg

Correcting /I1/, Preserving /I2/

/K28.5/D5.6/

/K28.5/D16.2/

/K23.7/

/K27.7/

/K29.7/

/K30.7/

Table 4-6: Synchronization State Machine Parameters in GbE Mode

Synchronization State Machine Parameters

Number of valid {/K28.5/, /Dx,y/} ordered sets received to achieve synchronization

Number of errors received to lose synchronization

Number of continuous good code groups received to reduce the error count by 1

Setting

3

4

4

(12)

Two data code groups represent the

Config_Reg value.

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XAUI

Figure 4-16: Synchronization State Machine in GbE Mode

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This figure is from “Figure 36–9” in the IEEE 802.3-2008 specification. For more details about the 1000BASE-X implementation, refer to Clause 36 of the IEEE 802.3-2008 specification.

2

3

(PUDI * signal_detect=FAIL * mr_loopback=FALSE +

PUDI(![/COMMA/])

PUDI(![/D/]) power_on=TRUE + mr_main_reset=TRUE +

(signal_detectChange=TRUE mr_loopback=FALSE PUDI)

LOSS_OF_SYNC sync_status

FAIL rx_even

! rx_even

SUDI

(signal_detect=OK + mr_loopback=TRUE)

PUDI([/COMMA/])

COMMA_DETECT_1 rx_even

TRUE

SUDI

PUDI([/D/])

ACQUIRE_SYNC_1 rx_even

! rx_even

SUDI

PUDI(![/COMMA/] cgbad rx_even=FALSE PUDI([/COMMA/])

PUDI(![/D/])

COMMA_DETECT_2 rx_even

TRUE

SUDI

PUDI([/D/])

[/INVALID/])

SYNC_ACQUIRED_2 rx_even

! rx_even

SUDI good_cgs

0 cgbad

SYNC_ACQUIRED_3 rx_even

! rx_even

SUDI good_cgs

0 cgbad

SYNC_ACQUIRED_4 rx_even

! rx_even

SUDI good_cgs

0 cgbad cgbad

ACQUIRE_SYNC_2 rx_even

! rx_even

SUDI

PUDI(![/D/])

PUDI(![/COMMA/]

[/INVALID/]) rx_even=FALSE PUDI([/COMMA/])

COMMA_DETECT_3 rx_even

TRUE

SUDI

PUDI([/D/])

SYNC_ACQUIRED_1 sync_status

OK rx_even

! rx_even

SUDI cgbad cggood cggood

SYNC_ACQUIRED_2A rx_even

! rx_even

SUDI good_cgs

⇐ good_cgs + 1 cggood good_cgs

3 cgbad good_cgs = 3 cggood cggood

SYNC_ACQUIRED_3A rx_even

! rx_even

SUDI good_cgs

⇐ good_cgs + 1 cgbad

2

cggood good_cgs cggood good_cgs

=

3

3 cggood

SYNC_ACQUIRED_4A rx_even

! rx_even

SUDI good_cgs

⇐ good_cgs + 1 cggood good_cgs

3 cgbad

3

cggood good_cgs

=

3

Related Information

Refer to the "Custom PHY IP Core" and "Native PHY IP Core" chapters in the Altera Transceiver PHY

IP Core User Guide

XAUI

In a XAUI configuration, the transceiver channel data path is configured using soft PCS. It provides the transceiver channel datapath description, clocking, and channel placement guidelines. With the MegaWizard

Plug-In Manager, you can implement a XAUI link. Under Ethernet in the Interfaces menu, select the XAUI

PHY IP core. The XAUI PHY IP core implements the XAUI PCS in soft logic.

XAUI is a specific physical layer implementation of the 10 Gigabit Ethernet link defined in the IEEE 802.3ae-

2002 specification. The XAUI PHY uses the XGMII interface to connect to the IEEE802.3 MAC and

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Transceiver Datapath in a XAUI Configuration

4-17

Reconciliation Sublayer (RS). The IEEE 802.3ae-2002 specification requires the XAUI PHY link to support a 10 Gbps data rate at the XGMII interface and four lanes each at 3.125 Gbps at the PMD interface.

Figure 4-17: XAUI and XGMII Layers

OSI

Reference

Model Layers

Application

Presentation

Session

Transport

Network

Data Link

Physical

LAN Carrier Sense Multiple

Access/Collision Detect (CSMA/CD)

Layers

Higher Layers

Logical Link Control (LLC)

MAC Control (Optional)

Media Access Control (MAC)

Reconciliation

Optional

XGMII

Extender

XGMII Extender Sublayer

XGMII Extender Sublayer

PCS

PMA

PMD

Medium

10 Gbps

10 Gigabit Media Independent Interface

10 Gigabit Attachment Unit Interface

10 Gigabit Media Independent Interface

Physical Layer Device

Medium Dependent Interface

Related Information

Refer to the "XAUI PHY IP Core" chapter in the Altera Transceiver PHY IP Core User Guide.

Transceiver Datapath in a XAUI Configuration

The XAUI PCS is implemented in soft logic inside the FPGA core when using the XAUI PHY IP core. You must ensure that your channel placement is compatible with the soft PCS implementation.

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Transceiver Datapath in a XAUI Configuration

Figure 4-18: XAUI Configuration Datapath

Transceiver PHY IP

Lane Data Rate

Number of Bonded Channels

PCS-PMA Interface Width

Word Aligner (Pattern Length)

(1)

8B/10B Encoder/Decoder

(1)

Deskew FIFO

(1)

Rate Match FIFO

(1)

Byte SERDES

(1)

Byte Ordering

(1)

FPGA Fabric-to-Transceiver

Interface Width

FPGA Fabric-to-Transceiver

Interface Frequency

Note:

1. Implemented in soft logic.

XAUI PHY IP

3.125 Gbps

×4

10-Bit

10-Bit/K28.5

Enabled

Enabled

Enabled

Enabled

Disabled

16-Bit

156.25 MHz

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XAUI Supported Features

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Figure 4-19: Transceiver Channel Datapath for XAUI Configuration

Standard PCS in a low latency configuration is used in this configuration. Additionally, a portion of the PCS is implemented in soft logic.

FPGA Fabric

Channel 3

Channel 2

Channel 1

Channel 0

Soft PCS

Soft PCS

Soft PCS

Soft PCS

Channel 3

Channel 2

Channel 1

Channel 0

Transmitter Standard PCS

Transmitter Standard PCS

Transmitter Standard PCS

Transmitter Standard PCS

Transmitter PMA Ch3

Transmitter PMA Ch2

Transmitter PMA Ch1

Transmitter PMA Ch0

16 20 20 10

16 20 20 20 20 20

Receiver Standard PCS

10

Receiver PMA

XAUI Supported Features

64-Bit SDR Interface to the MAC/RS

Clause 46 of the IEEE 802.3-2008 specification defines the XGMII interface between the XAUI PCS and the

Ethernet MAC/RS. The specification requires each of the four XAUI lanes to transfer 8-bit data and 1-bit wide control code at both the positive and negative edge (DDR) of the 156.25 MHz interface clock.

Cyclone V transceivers and soft PCS solution in a XAUI configuration do not support the XGMII interface to the MAC/RS as defined in IEEE 802.3-2008 specification. Instead, they allow the transferring of 16-bit data and 2-bit control code on each of the four XAUI lanes, only at the positive edge (SDR) of the 156.25

MHz interface clock

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XAUI Supported Features

Figure 4-20: Implementation of the XGMII Specification in Cyclone V Devices Configuration

XGMII Transfer (DDR)

Interface Clock (156.25 MHz)

Lane 0

8-bit

D0 D1 D2 D3

Lane 1

Lane 2

Lane 3

D0

D0

D0

Cyclone V Soft PCS Interface (SDR)

Interface Clock (156.25 MHz)

Lane 0

16-bit

{D1, D0}

Lane 1 {D1, D0}

D1

D1

D1

D2

D2

D2

{D3, D2}

{D3, D2}

D3

D3

D3

{D1, D0} {D3, D2}

Lane 2

Lane 3

{D1, D0} {D3, D2}

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8B/10B Encoding/Decoding

Each of the four lanes in a XAUI configuration support an independent 8B/10B encoder/decoder as specified in Clause 48 of the IEEE802.3-2008 specification. 8B/10B encoding limits the maximum number of consecutive 1s and 0s in the serial data stream to five, thereby ensuring DC balance as well as enough transitions for the receiver CDR to maintain a lock to the incoming data.

The XAUI PHY IP core provides status signals to indicate running disparity as well as the 8B/10B code group error.

Transmitter and Receiver State Machines

In a XAUI configuration, the Cyclone V soft PCS implements the transmitter and receiver state diagrams shown in Figure 48-6 and Figure 48-9 of the IEEE802.3-2008 specification.

In addition to encoding the XGMII data to PCS code groups, in conformance with the 10GBASE-X PCS, the transmitter state diagram performs functions such as converting Idle ||I|| ordered sets into Sync ||K||,

Align ||A||, and Skip ||R|| ordered sets.

In addition to decoding the PCS code groups to XGMII data, in conformance with the 10GBASE-X PCS, the receiver state diagram performs functions such as converting Sync ||K||, Align ||A||, and Skip ||R|| ordered sets to Idle ||I|| ordered sets.

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XAUI Supported Features

4-21

Synchronization

The word aligner block in the receiver PCS of each of the four XAUI lanes implements the receiver synchronization state diagram shown in Figure 48-7 of the IEEE802.3-2008 specification.

The XAUI PHY IP core provides a status signal per lane to indicate if the word aligner is synchronized to a valid word boundary.

Deskew

The lane aligner block in the receiver PCS implements the receiver deskew state diagram shown in Figure

48-8 of the IEEE 802.3-2008 specification.

The lane aligner starts the deskew process only after the word aligner block in each of the four XAUI lanes indicates successful synchronization to a valid word boundary.

The XAUI PHY IP core provides a status signal to indicate successful lane deskew in the receiver PCS.

Clock Compensation

The rate match FIFO in the receiver PCS datapath compensates up to ±100 ppm difference between the remote transmitter and the local receiver. It does so by inserting and deleting Skip ||R|| columns, depending on the ppm difference.

The clock compensation operation begins after:

• The word aligner in all four XAUI lanes indicates successful synchronization to a valid word boundary.

• The lane aligner indicates a successful lane deskew.

The rate match FIFO provides status signals to indicate the insertion and deletion of the Skip ||R|| column for clock rate compensation.

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Transceiver Clocking and Channel Placement Guidelines in XAUI Configuration

Transceiver Clocking and Channel Placement Guidelines in XAUI Configuration

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Transceiver Clocking

Figure 4-21: Transceiver Clocking for XAUI Configuration

One of the two channel PLLs configured as a CMU PLL in a transceiver bank generates the transmitter serial and parallel clocks for the four XAUI channels. The x6 clock line carries the transmitter clocks to the PMA and PCS of each of the four channels.

FPGA Fabric

Channel 3

Channel 2

Channel 1

Channel 0

Soft PCS

Soft PCS

Soft PCS

Soft PCS

Channel 3

Channel 2

Channel 1

Channel 0

Transmitter Standard PCS

Transmitter Standard PCS

Transmitter Standard PCS

Transmitter Standard PCS

Transmitter PMA Ch 3

Transmitter PMA Ch 2

Transmitter PMA Ch 1

Transmitter PMA Ch 0

16 20 20 10 xgmii_tx_clk

20

/2

Parallel Clock

Receiver Standard PCS

10

Receiver PMA

16 20 xgmii_rx_clk

Parallel Clock

Parallel Clock

(Recovered) from Channel 0

/2

Parallel Clock (Recovered)

CMU PLL

Serial Clock

(From the ×1 Clock Lines)

Central/ Local Clock Divider

Clock Divider

Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)

Parallel Clock

Serial Clock

Parallel and Serial Clocks

Table 4-7: Input Reference Clock Frequency and Interface Speed Specifications for XAUI Configurations

Input Reference Clock Frequency

(MHz)

156.25

FPGA Fabric-Transceiver Interface Width

16-bit data, 2-bit control

FPGA Fabric-Transceiver Interface

Frequency (MHz)

156.25

Transceiver Clocking Guidelines for Soft PCS Implementation

In the soft PCS implementation in the XAUI configuration, you must route xgmii_rx_clk to xgmii_tx_clk as shown in the following figure.

This method uses xgmii_rx_clk to compensate for the phase difference on the TX side.

Without this method, the tx_digitalreset signal may experience intermittent failure.

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Transceiver Clocking and Channel Placement Guidelines in XAUI Configuration

Figure 4-22: Transceiver Clocking for XAUI Soft PCS Implementation

FPGA Fabric

Channel 3

Channel 2

Channel 1

Channel 0

16

Soft PCS

Soft PCS

Soft PCS

Soft PCS

20

Channel 3

Channel 2

Channel 1

Channel 0

20

Transmitter Standard PCS

Transmitter Standard PCS

Transmitter Standard PCS

Transmitter Standard PCS

Transmitter PMA Ch 3

Transmitter PMA Ch 2

Transmitter PMA Ch 1

Transmitter PMA Ch 0

10

4-23

xgmii_tx_clk

16

20 20

/2

Parallel Clock

Receiver Standard PCS

10

Receiver PMA

xgmii_rx_clk

Parallel Clock

Parallel Clock

(Recovered) from Channel 0

/2

Parallel Clock (Recovered)

CMU PLL

Serial Clock

(From the ×1 Clock Lines)

Central/ Local Clock Divider

Clock Divider

Parallel and Serial Clocks (From the ×6 or ×N Clock Lines)

Parallel Clock

Serial Clock

Parallel and Serial Clocks

Transceiver Channel Placement Guidelines

In the soft PCS implementation of the XAUI configuration, all four channels must be placed continuously.

The channels may all be placed in one bank or they may span two banks. Only the placements shown in the following figure are allowed.

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Serial Digital Interface

Figure 4-23: Transceiver Channel Placement Guidelines in a XAUI Configuration

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Use one of the two allowed channel placements when using the CMU PLL to drive the XAUI link. The

Quartus II software implements the XAUI PCS in soft logic.

Placement 1

Placement 2

XCVR Channel 5

XCVR Channel 5

XCVR Channel 4

XCVR Channel 4

XCVR Channel 3

XCVR Channel 2

XCVR Channel 3

XCVR Channel 2

XCVR Channel 1

CMU PLL

XCVR Channel 0

Bank 1

XCVR Channel 0

Bank 0

XCVR Channel 5

XCVR Channel 4

XCVR Channel 3

XCVR Channel 2

CMU PLL

XCVR Channel 0

Bank 0

Related Information

To implement the QSF assignment workaround using the Assignment Editor, refer to the "XAUI PHY

IP Core" chapter in the Altera Transceiver PHY IP Core User Guide.

Serial Digital Interface

The Society of Motion Picture and Television Engineers (SMPTE) defines various Serial Digital Interface

(SDI) standards for transmission of uncompressed video.

The following SMPTE standards are popular in video broadcasting applications:

• SMPTE 259M standard - more popularly known as the standard-definition (SD) SDI; defined to carry video data at 270 Mbps

• SMPTE 292M standard - more popularly known as the high-definition (HD) SDI; defined to carry video data at either 1485 Mbps or 1483.5 Mbps

• SMPTE 424M standard - more popularly known as the third-generation (3G) SDI; defined to carry video data at either 2970 Mbps or 2967 Mbps

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Configurations Supported in SDI Mode

Table 4-8: Configurations Supported in SDI Mode

Configuration Data Rate (Mbps)

HD

3G

1,485

1,483.5

2,970

2,967

Configurations Supported in SDI Mode

4-25

REFCLK Frequencies

(MHz)

74.25, 148.5

74.175, 148.35

148.5, 297

148.35, 296.7

FPGA Fabric-Transceiver Interface

Width

10 bit and 20 bit

10 bit and 20 bit

Only 20-bit interfaces allowed in

3G

Only 20-bit interfaces allowed in

3G

Figure 4-24: SDI Mode

Functional Mode

PMA-PCS Interface Width

Data Rate (Gbps)

Number of Bonded Channels

Low Latency PCS

Word Aligner (Pattern Length)

8B/10B Encoder/Decoder

Rate Match FIFO

Byte SERDES

Byte Ordering

FPGA Fabric-Transceiver

Interface Width

FPGA Fabric-Transceiver

Interface Frequency (MHz)

HD-SDI (1.485/1.4835) x1

Disabled

Bit-Slip

Disabled

Disabled

Disabled Enabled

Disabled Disabled

10-bit 20-bit

148.5/148.35

74.25/74.175

SDI

10 bit

3G-SDI (2.97/2.967) x1

Disabled

Bit-Slip

Disabled

Disabled

Enabled

Disabled

20-bit

148.5/148.35

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Serial Digital Interface Transceiver Datapath

Serial Digital Interface Transceiver Datapath

Figure 4-25: SDI Mode Transceiver Datapath

FPGA Fabric tx_coreclk

FPGA

Fabric–Transceiver

Interface Clock

TX Phase

Compensation

FIFO wrclk rdclk tx_clkout rx_coreclk

RX Phase

Compensation

FIFO

Transmitter Channel PCS

Byte

Serializer wrclk rdclk

/2

Low-Speed Parallel Clock

Receiver Channel PCS

Serializer

Transmitter Channel PMA

High-Speed Serial Clock

Local Clock

Divider

Receiver Channel PMA

Byte

Deserializer

Word

Aligner

Deserializer CDR

/2

Parallel Recovered Clock rx_clkout

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Transmitter Datapath

The transmitter datapath in the HD-SDI configuration with a 10-bit wide FPGA fabric-transceiver interface consists of the transmitter phase compensation FIFO and the 10:1 serializer. In HD-SDI and 3G-SDI configurations with 20-bit wide FPGA fabric-transceiver interface, the transmitter datapath also includes the byte serializer.

Note:

In SDI mode, the transmitter is purely a parallel-to-serial converter. You must implement the SDI transmitter functions, such as the scrambling and cyclic redundancy check (CRC) code generation, in the FPGA logic array.

Receiver Datapath

In the 10-bit channel width SDI configuration, the receiver datapath consists of the clock recovery unit

(CRU), 1:10 deserializer, word aligner in bit-slip mode, and receiver phase compensation FIFO. In the 20bit channel width SDI configuration, the receiver datapath also includes the byte deserializer.

Note:

You must implement the SDI receiver functions, such as descrambling, framing, and CRC checker, in the FPGA logic array.

Receiver Word Alignment and Framing

In SDI systems, the word aligner in the receiver datapath is not useful because the word alignment and framing happen after descrambling. Altera recommends that you drive the rx_bitslip of the PHY

MegaWizard

™ signal low to avoid having the word aligner insert bits in the received data stream.

Serial Data Converter (SDC) JESD204

The SDC (JESD204) protocol conforms to JESD204, a JEDEC standard that enables a high-speed serial connection between analog-to-digital converters and logic devices using only a two-wire high-speed serial

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SATA and SAS Protocols

4-27

interface. SDC (JESD204) data rate ranges of 312.5 Mbps to 3.125 Gbps are supported. The minimum supported data rate is 611 Mbps, so a 5x oversampling factor is used for the SDC (JESD204) data rate of

312.5 Mbps, resulting in a data rate of 1.5625 Gbps.

Figure 4-26: Configurations for the SDC (JESD204) Protocol

Configuration option for data rate range of

312.5 Mbps - 1.5625 Gbps

Single Width

Configuration option for data rate range of

1.5625 Gbps - 3.125 Gpbs

Single Width

Functional Modes

PMA-PCS Interface Width

10-bit

Functional Modes

Data Rate (Gbps)

Channel Bonding

Word Aligner (Pattern Length)

8B/10B Encoder/Decoder

Rate Match FIFO

Byte SERDES

Byte Ordering

FPGA Fabric-Transceiver

Interface Width

FPGA Fabric-Transceiver

Interface Frequency (MHz)

Basic Single-Width

10-bit PMA-PCS

Interface Width

1.5625

x1

Enabled (Manual)

Enabled

Disabled

Disabled

Disabled

8-bit

156.25

Basic Single-Width

10-bit PMA-PCS

Interface Width

1.5625 - 3.125

x1

Enabled (Manual)

Enabled

Disabled

Enabled

Enabled

16-bit

78.125 -

156.25

SATA and SAS Protocols

Serial ATA (SATA) and Serial Attached SCSI (SAS) are data storage protocol standards that have the primary function of transferring data (directly or otherwise) between the host system and mass storage devices, such as hard disk drives, optical drives, and solid-state disks.

These serial storage protocols offer several advantages over older parallel storage protocol (ATA and SCSI) interfaces:

• Faster data transfer

• Hot swapping (when supported by the operating system)

• Thinner cables for more efficient air cooling

• Increased operation reliability

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SATA and SAS Protocols

Table 4-9: Serial Data Rates for SATA and SAS Protocols

Gen1

Gen2

Protocol SATA (Gbps)

1.5

3.0

Figure 4-27: Configurations for the SATA and SAS Protocols

SAS (Gbps)

3.0

Cyclone V Configurations

Basic

Functional Modes

PMA-PCS Interface

Width

Single

Width

10-Bit

Functional Modes

Data Rate (Gbps)

Basic Single-Width

10-Bit PMA-PCS

Interface Width

1.5

Reference Clock (MHz)

150

Channel Bonding

x1

Low Latency PCS

Word Aligner

(Pattern Length)

8B/10B Encoder/

Decoder

Rate Match FIFO

Disabled

Enabled

(Manual, 10-Bit)

Enabled

Disabled

Byte SERDES

Disabled Enabled

Byte Ordering

FPGA Fabric-Transceiver

Interface Width

FPGA Fabric-Transceiver

Interface Frequency (MHz)

Disabled Disabled

8-Bit

150

16-Bit

75

Configuration Option for SATA/SAS

1.5 Gbps Data Rate

Basic Single-Width

10-Bit PMA-PCS

Interface Width

3.0

150 x1

Disabled

Enabled

(Manual, 10-Bit)

Enabled

Disabled

Enabled

Disabled

16-Bit

Basic Double-Width

20-Bit PMA-PCS

Interface Width

1.5

150 x1

Disabled

Enabled

(Manual, 10-Bit)

Enabled

Disabled

Disabled Enabled

Disabled Disabled

16-Bit 16-Bit

150

Configuration Option for SATA/SAS

3.0 Gbps Data Rate

75 37.5

Configuration Option for SATA/SAS

1.5 Gbps Data Rate

Double

Width

20-Bit

Basic Double-Width

20-Bit PMA-PCS

Interface Width

3.0

150 x1

Disabled

Enabled

(Manual, 10-Bit)

Enabled

Disabled

Disabled Enabled

Disabled Disabled

16-Bit 16-Bit

150 75

Configuration Option for SATA/SAS

3.0 Gbps Data Rate

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Deterministic Latency Protocols—CPRI and OBSAI

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Deterministic Latency Protocols—CPRI and OBSAI

A deterministic latency option is available for use in high-speed serial interfaces such as the Common Public

Radio Interface (CPRI) and OBSAI Reference Point 3 (OBSAI RP3). Both CPRI and OBSAI RP3 protocols place stringent requirements on the amount of latency variation that is permissible through a link that implements these protocols.

Figure 4-28: Transceiver Datapath in Deterministic Latency Mode

Transmitter Channel PCS

Transmitter Channel

PMA

FPGA

Fabric

TX Phase

Compensation

FIFO wrclk rdclk

Byte Serializer wrclk rdclk

Receiver Channel PCS

8B/10B Encoder

Receiver Channel

PMA

Transmitter Channel Datapath

Receiver Channel Datapath

Latency Uncertainty Removal with the Phase Compensation FIFO in Register Mode

To remove the latency uncertainty through the receiver's phase compensation FIFO, the receiver and transmitter phase compensation FIFOs are always set to register mode. In register mode, the phase compensation FIFO acts as a register and thereby removes the uncertainty in latency. The latency through the transmitter and receiver phase compensation FIFO in register mode is one clock cycle.

The following options are available:

• Single-width mode with 8-bit channel width and 8B/10B encoder enabled or 10-bit channel width with

8B/10B disabled

• Double-width mode with 16-bit channel width and 8B/10B encoder enabled or 20-bit channel width with

8B/10B disabled

Channel PLL Feedback for Deterministic Relationship

To implement the deterministic latency functional mode, the phase relationship between the low-speed parallel clock and channel PLL input reference clock must be deterministic. A feedback path is enabled to ensure a deterministic relationship between the low-speed parallel clock and channel PLL input reference clock.

To achieve deterministic latency through the transceiver, the reference clock to the channel PLL must be the same as the low-speed parallel clock. For example, if you need to implement a data rate of 1.2288 Gbps for the CPRI protocol, which places stringent requirements on the amount of latency variation, you must choose a reference clock of 122.88 MHz to allow the usage of a feedback path from the channel PLL. This feedback path reduces the variations in latency.

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CPRI and OBSAI

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When you select this option, provide an input reference clock to the channel PLL that has the same frequency as the low-speed parallel clock.

CPRI and OBSAI

Use the deterministic latency functional mode to implement protocols such as CPRI and OBSAI.

The CPRI interface defines a digital point-to-point interface between the Radio Equipment Control (REC) and the Radio Equipment (RE), allowing flexibility in either co-locating the REC and the RE, or a remote location of the RE.

Figure 4-29: CPRI Topologies

In most cases, CPRI links are between REC and RE modules or between two RE modules in a chain configuration.

RE

RE

Ring

RE

RE

RE

Tree and Branch

RE

REC

Radio Equipment

Control

RE

RE

Chain

Point-to-Point

RE

RE

If the destination for the high-speed serial data that leaves the REC is the first RE, it is a single-hop connection.

If the serial data from the REC must traverse through multiple REs before reaching the destination RE, it is a multi-hop connection.

Remotely locating the RF transceiver from the main base station introduces a complexity with overall system delay. The CPRI specification requires that the accuracy of measurement of roundtrip delay on single-hop and multi-hop connections be within ±16.276 ns to properly estimate the cable delay.

For a single-hop system, this allows a variation in roundtrip delay of up to ±16.276 ns. However, for multihop systems, the allowed delay variation is divided among the number of hops in the connection—typically, equal to ±16.276 ns/(the number of hops) but not always equally divided among the hops.

Deterministic latency on a CPRI link also enables highly accurate triangulation of the location of the caller.

OBSAI was established by several OEMs to develop a set of specifications that can be used for configuring and connecting common modules into base transceiver stations (BTS).

The BTS has four main modules:

• Radio frequency (RF)

• Baseband

• Control

• Transport

In a typical BTS, the radio frequency module (RFM) receives signals using portable devices and converts the signals to digital data. The baseband module processes the encoded signal and brings it back to the baseband before transmitting it to the terrestrial network using the transport module. A control module maintains the coordination between these three functions.

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6.144-Gbps Support Capability in Cyclone V GT Devices

Figure 4-30: Example of the OBSAI BTS Architecture

System Software

Transport Module

RP2 (1)

Baseband

Module

Interface Switch

BB

RP3 (1)

RF Module

RFM

4-31

Proprietary

Module(s)

Control

& Clock

Clock and Sync

RP1 (1)

Power System

Control

Module

(1) RP = Reference Point

Using the deterministic latency option, you can implement the CPRI data rates in the following modes:

• Single-width mode—with 8/10-bit channel width

• Double-width mode—with 16/20-bit channel width

Table 4-10: Sample Channel Width Options for Supported Serial Data Rates

Serial Data Rate (Mbps)

614.4

1228.8

2457.6

3072

4915.2

6144

(13)

No

No

No

Yes

Yes

No

8-Bit

Single Width

Channel Width (FPGA-PCS Fabric)

Double-Width

16-Bit 16-Bit 32-Bit

Yes No No

Yes

Yes

Yes

Yes

Yes

Yes

Yes

No

No

Yes

No

No

Yes

Yes

Yes

6.144-Gbps Support Capability in Cyclone V GT Devices

Cyclone V GT devices support a 6.144 Gbps data rate for the CPRI protocol only. For CPRI 6.144-Gbps transmit jitter compliance, Altera recommends you use only up to three full-duplex channels for every two transceiver banks. The transceivers are grouped in banks of three channels. For transceiver bank information, refer to the

Transceiver Architecture in Cyclone V Devices

chapter.

The maximum number of CPRI channels allowed for 9-channel and 12-channel devices is as follows. The same limitation applies to devices with fewer transceiver channels.

(13)

6144 Mbps is supported only for the CPRI protocol in the C5 and I5 speed grades.

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CPRI Enhancements

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• For a 9-channel device, you can implement a maximum of 4 full duplex 6.144-Gbps CPRI-compliant channels.

• For a 12-channel device, you can implement a maximum of 6 full duplex 6.144-Gbps CPRI-compliant channels.

You must increase the voltage on VCCE_GXB and VCCL_GXB to 1.2 V to support the maximum number of channels.

The reference clock frequency for the 6.144 Gbps CPRI channel must be ≥ 307.2 MHz.

The maximum number of transceiver channels in a Cyclone V GT device that can achieve 6.144-Gbps CPRI compliance is based on:

• Transceiver performance in meeting the TX jitter specification for 6.144-Gbps CPRI.

• CPRI channels with an auto-rate negotiation capability from 1228.8 Mbps to 6.144 Gbps.

• 6.144-Gbps CPRI channel restriction based on the following figure.

Figure 4-31: 6.144-Gbps CPRI Channel Placement Restriction

The channels next to a PCIe Hard IP block are not timing optimized for the 6.144-Gbps CPRI data rate.

Affected channels are shaded in gray in the above figure. Avoid placing the 6.144-Gbps CPRI channels in the affected channels. The affected channels can still be used as a CMU for the CPRI channels.

Related Information

Transceiver Architecture in Cyclone V Devices

CPRI Enhancements

The deterministic latency state machine in the word aligner reduces the known delay variation from the word alignment process and automatically synchronizes and aligns the word boundary by slipping a clock cycle in the deserializer. Incoming data to the word aligner is aligned to the boundary of the word alignment

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pattern (K28.5). User logic is not required to manipulate the TX bit slipper for constant round-trip delay.

In manual mode, the TX bit slipper is able to compensate one unit interval (UI).

The word alignment pattern (K28.5) position varies in byte deserialized data. Delay variation is up to ½ parallel clock cycle. You must add in extra user logic to manually check the K28.5 position in byte deserialized data for the actual latency.

Figure 4-32: Deterministic Latency State Machine in the Word Aligner

Clock-slip Control

To 8B/10B Decoder Deterministic Latency

Synchronization State Machine

Word Aligner

Deserializer

From RX CDR

Table 4-11: Methods to Achieve Deterministic Latency Mode in Cyclone V Devices

Existing Feature

Description Requirement Description

Enhanced Feature

(14)

Requirement

Manual alignment with bit position indicator provides deterministic latency. Delay variation up to 1 parallel clock cycle

Extra user logic to manipulate the TX bit slipper with a bit position indicator from the word aligner for constant total round-trip delay

Deterministic latency state machine alignment reduces the known delay variation in word alignment operation

None

Related Information

Refer to the "Deterministic Latency PHY IP Core" chapter in the Altera Transceiver PHY IP Core User

Guide

(14)

Enhanced deterministic latency feature in Cyclone V devices.

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Document Revision History

Document Revision History

Table 4-12: Document Revision History

Date

October 2013 2013.10.17

Version

May 2013 2013.05.06

November 2012 2012.11.19

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Changes

• Added clock frequency information to "6.144-Gbps Support

Capability in Cyclone V GT

Devices" section.

• Removed fPLL information from the "Transceiver Clocking and

Channel Placement Guidelines in

XAUI Configuration" section.

• Added Gen2 information to the

"Hard IP Configurations for PCIe

Gen1 and Gen2" table.

• Added link to the known document issues in the Knowledge

Base.

• Removed the "Receiver Electrical

Idle Inference" section.

• Added the "Recommended

Channel Placement for PCIe

Gen2" table.

• Updated the figures in the "PCIe

Supported Configurations and

Placement Guidelines" section.

• Added the "Transceiver Clocking

Guidelines for Soft PCS

Implementation" section.

• Added the "6-Gbps Support

Capability in Cyclone V GT

Devices" section.

• Reorganized content and updated template.

• Added the "XAUI" section.

• Added the "PCI Express" section.

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June 2012

Date

1.1

Version

October 2011 1.0

Document Revision History

4-35

Changes

• Updated for the Quartus II software version 12.0 release.

• Updated Table 4–1.

• Updated Figure 4–2.

• Updated Figure 4–18.

• Added the “Gigabit Ethernet” section.

• Added the “Serial Digital

Interface” section.

• Added the “Serial Data Converter

(SDC) JESD204” section.

• Added the “SATA and SAS

Protocols” section.

Initial release.

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Transceiver Custom Configurations in Cyclone V

Devices

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For integration with the FPGA fabric, the full-duplex transceiver channel supports custom configuration with physical medium attachment (PMA) and physical coding sublayer (PCS).

You can customize the transceiver with one of the following configurations:

• Standard PCS— Physical coding sublayer (PCS) and physical medium attachment (PMA)

• Standard PCS in low latency mode— Low latency PCS and PMA

Figure 5-1: Custom Configuration Options

5

Up to 5 Gbps with PCS (Standard PCS and low latency mode)

- 5 Gbps channels are available in GT and ST device variants

FPGA Fabric

HIP PIPE PCS

Transceiver Resources

PMA tx_serial_data rx_serial_data

Serial Interface

Related Information

Cyclone V Device Handbook: Known Issues

Lists the planned updates to the

Cyclone V Device Handbook

chapters.

Standard PCS Configuration

In this configuration, you can customize the transceiver channel to include a PMA and PCS with functions that your application requires. The transceiver channel interfaces with the FPGA fabric through the PCS.

©

2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with

Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO

9001:2008

Registered www.altera.com

101 Innovation Drive, San Jose, CA 95134

5-2

Custom Configuration Channel Options

Figure 5-2: Complete Datapath in a Custom Configuration

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Based on your application requirements, you can enable, modify, or disable the blocks, except the deskew

FIFO block, as shown in the following figure.

Transmitter PMA Transmitter PCS FPGA Fabric

Serial

Clock

Receiver PMA Receiver PCS

/2

tx_parallel data tx_coreclkin tx_clkout

Parallel Clock

/2

rx_parallel data rx_coreclkin rx_clkout

Serial Clock

Parallel Clock

The serial and parallel clocks are sourced from the clock divider.

Custom Configuration Channel Options

There are multiple channel options when you use Custom Configuration.

The supported interface width varies depending on the usage of the byte serializer/deserializer (SERDES), and the 8B/10B encoder or decoder. The byte serializer or deserializer is assumed to be enabled. Otherwise, the maximum data rate supported is half of the specified value.

The maximum supported data rate varies depending on the customization.

Table 5-1: Maximum Supported Data Rate

The following table shows the maximum supported data rate for the fastest speed grade in Standard PCS (transceiver speed grade 6) for Cyclone V GX and SX devices, and (transceiver speed grade 5) for Cyclone V GT and ST devices.

PCS-FPGA Fabric Interface Width

Data Configuration

PMA-PCS

Interface

Width

8B/10B

Enabled

8B/10B

Disabled

Maximum Data

Rate for GX and SX (Mbps)

Maximum Data Rate for GT and ST (Mbps)

Single-width

8

10

8

16

8

16

10

20

1,500

3,000

1,875

3,125

1,500

3,000

1,875

3,750

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Data Configuration

Double-width

PMA-PCS

Interface

Width

16

20

Custom Configuration Channel Options

5-3

PCS-FPGA Fabric Interface Width

8B/10B

Enabled

8B/10B

Disabled

Maximum Data

Rate for GX and SX (Mbps)

16 2,621.44

16

32

32

20

40

3,125

3,125

3,125

Maximum Data Rate for GT and ST (Mbps)

2,621.44

5,000

3,276.8

5,000

In all the supported configuration options of the channel, the transmitter bit-slip function is optional, where:

• The blocks shown as “Disabled” are not used but incur latency.

• The blocks shown as “Bypassed” are not used and do not incur any latency.

• The transmitter bit-slip is disabled.

Figure 5-3: Configuration Options for Custom Single-Width Mode (8-bit PMA–PCS Interface Width)

Word Aligner (Pattern Length)

8B/10B Encoder/Decoder

Rate Match FIFO

Byte SERDES

FPGA Fabric–Transceiver

Interface Width

Data Rate (Gbps)

Disabled

8-Bit

1.5

Manual Alignment or Bit-Slip

Disabled

Disabled

Enabled

16-Bit

3.0

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Custom Configuration Channel Options

Figure 5-4: Configuration Options for Custom Single-Width Mode (10-bit PMA–PCS Interface Width)

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Word Aligner (Pattern Length)

Manual Alignment or Bit-Slip

Automatic Synchronization

State Machine

8B/10B Encoder/Decoder

Enabled Disabled

Rate Match FIFO

Disabled Disabled

Enabled/

Disabled

Enabled/

Disabled

Byte SERDES

Disabled Enabled Disabled Enabled Disabled Enabled Disabled Enabled

FPGA Fabric–Transceiver

Interface Width

10-Bit 20-Bit 8-Bit 16-Bit 10-Bit 20-Bit 8-Bit 16-Bit

Data Rate (Gbps)

Disabled

1.875

GX/SX= 3.125

GT/ST= 3.75

1.875

3.125

1.875

GX/SX= 3.125

GT/ST= 3.75

1.875

Enabled

3.125

Figure 5-5: Configuration Options for Custom Double-Width Mode (16-bit PMA–PCS Interface Width)

Word Aligner (Pattern Length)

8B/10B Encoder/Decoder

Rate Match FIFO

Byte SERDES

FPGA Fabric–Transceiver

Interface Width

Data Rate (Gbps)

Disabled

16-Bit

2.62144

Manual Alignment or Bit-Slip

Disabled

Disabled

Enabled

32-Bit

GX/SX= 3.125

GT/ST= 5

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Rate Match FIFO in Custom Configuration

Figure 5-6: Configuration Options for Custom Double-Width Mode (20-bit PMA–PCS Interface Width)

5-5

Word Aligner (Pattern Length)

Manual Alignment or Bit-Slip

8B/10B Encoder/Decoder

Disabled Enabled

Rate Match FIFO

Disabled Disabled

Byte SERDES

Disabled Enabled Disabled Enabled

FPGA Fabric–Transceiver

Interface Width

Data Rate (Gbps)

20-Bit 40-Bit 16-Bit 32-Bit

GX/SX= 3.125

GT/ST= 3.2768

GX/SX= 3.125

GT/ST= 5

GX/SX= 3.125

GT/ST= 3.2768

GX/SX= 3.125

GT/ST= 5

Rate Match FIFO in Custom Configuration

In a custom configuration, the 20-bit pattern for the rate match FIFO is user-defined. The FIFO operates by looking for the 10-bit control pattern followed by the 10-bit skip pattern in the data, after the word aligner restores the word boundary. After finding the pattern, the FIFO performs a skip pattern insertion or deletion to ensure that the FIFO does not underflow or overflow a given parts per million (ppm) difference between the clocks.

The rate match FIFO operation requires 8B/10B-coded data.

Rate Match FIFO Behaviors in Custom Single-Width Mode

The different operations available in custom single-width mode for the rate match FIFO are symbol insertion, symbol deletion, full condition, and empty condition.

Table 5-2: Rate Match FIFO Behaviors in Custom Single-Width Mode (10-bit PMA–PCS Interface Width)

Symbol Insertion

Symbol Deletion

Full Condition

Empty Condition

Operation Behavior

Inserts a maximum of four skip patterns in a cluster, only if there are no more than five skip patterns in the cluster after the symbol insertion.

Deletes a maximum of four skip patterns in a cluster, only if there is one skip pattern left in the cluster after the symbol deletion.

Deletes the data byte that causes the FIFO to go full.

Inserts a /K30.7/ (9'h1FE) after the data byte that caused the FIFO to go empty.

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Rate Match FIFO Behaviors in Custom Double-Width Mode

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Rate Match FIFO Behaviors in Custom Double-Width Mode

The different operations available in custom double-width mode for the rate match FIFO are symbol insertion, symbol deletion, full condition, and empty condition.

Table 5-3: Rate Match FIFO Behaviors in Custom Double-Width Mode (20-bit PMA–PCS Interface Width)

Symbol Insertion

Symbol Deletion

Full Condition

Empty Condition

Operation Behavior

Inserts as many pairs (10-bit skip patterns at the

LSByte and MSByte of the 20-bit word at the same clock cycle) of skip patterns as needed.

Deletes as many pairs (10-bit skip patterns at the

LSByte and MSByte of the 20-bit word at the same clock cycle) of skip patterns as needed.

Deletes the pair (20-bit word) of data bytes that causes the FIFO to go full.

Inserts a pair of /K30.7/ ({9'h1FE, 9'h1FE}) after the data byte that causes the FIFO to go empty.

Standard PCS in Low Latency Configuration

In this configuration, you can customize the transceiver channel to include a PMA and PCS that bypasses most of the PCS logical functionality for a low latency datapath.

To provide a low latency datapath, the PCS includes only the phase compensation FIFO in phase compensation mode, and optionally, the byte serializer and byte deserializer blocks, as shown in the following figure. The transceiver channel interfaces with the FPGA fabric through the PCS.

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Low Latency Custom Configuration Channel Options

Figure 5-7: Datapath in Low Latency Custom Configuration

Transmitter PMA Transmitter PCS FPGA Fabric

5-7

Serial

Clock

Receiver PMA Receiver PCS

/2

tx_parallel data tx_coreclkin tx_clkout rx_parallel data rx_coreclkin

Parallel Clock

/2

rx_clkout

Serial Clock

Parallel Clock

The serial and parallel clocks are sourced from the clock divider.

The maximum supported data rate varies depending on the customization and is identical to the custom configuration except that the 8B/10B block is disabled

Low Latency Custom Configuration Channel Options

There are multiple channel options when you use Low Latency Custom Configuration.

In the following figures:

• The blocks shown as “Disabled” are not used but incur latency.

• The blocks shown as “Bypassed” are not used and do not incur any latency.

• The transmitter bit-slip is disabled.

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Low Latency Custom Configuration Channel Options

Figure 5-8: Configuration Options for Low Latency Custom Single-Width Mode (8-bit PMA–PCS

Interface Width)

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Word Aligner (Pattern Length)

8B/10B Encoder/Decoder

Rate Match FIFO

Byte SERDES

Byte Ordering

FPGA Fabric–Transceiver

Interface Width

Data Rate (Gbps)

Bypassed

Bypassed

8-Bit

1.5

Disabled

Disabled

Bypassed

Enabled

Bypassed

16-Bit

3.0

Figure 5-9: Configuration Options for Low Latency Custom Single-Width Mode (10-bit PMA–PCS

Interface Width)

Word Aligner (Pattern Length)

8B/10B Encoder/Decoder

Rate Match FIFO

Byte SERDES

Byte Ordering

FPGA Fabric–Transceiver

Interface Width

Data Rate (Gbps)

Bypassed

Bypassed

10-Bit

1.875

Disabled

Disabled

Bypassed

Enabled

Bypassed

20-Bit

GX/SX= 3.125

GT/ST= 3.75

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Low Latency Custom Configuration Channel Options

Figure 5-10: Configuration Options for Low Latency Custom Double-Width Mode (16-bit PMA–PCS

Interface Width)

5-9

Word Aligner (Pattern Length)

8B/10B Encoder/Decoder

Rate Match FIFO

Byte SERDES

Byte Ordering

FPGA Fabric–Transceiver

Interface Width

Data Rate (Gbps)

Bypassed

Bypassed

16-Bit

2.62144

Disabled

Disabled

Bypassed

Enabled

Bypassed

32-Bit

GX/SX= 3.125

GT/ST= 5

Figure 5-11: Configuration Options for Low Latency Custom Double-Width Mode (20-bit PMA–PCS

Interface Width)

Word Aligner (Pattern Length)

8B/10B Encoder/Decoder

Rate Match FIFO

Byte SERDES

Byte Ordering

FPGA Fabric–Transceiver

Interface Width

Data Rate (Gbps)

Bypassed

Bypassed

20-Bit

GX/SX= 3.125

GT/ST= 3.2768

Disabled

Disabled

Bypassed

Enabled

Bypassed

40-Bit

GX/SX= 3.125

GT/ST= 5

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Document Revision History

Document Revision History

Table 5-4: Document Revision History

May 2013

Date

2013.05.06

November 2012

June 2012

October 2011

2012.11.19

1.1

1.0

Version Changes

Added link to the known document issues in the Knowledge Base.

Reorganized content and updated template.

Updated for the Quartus II software version 12.0 release.

Initial release.

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Transceiver Loopback Support

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The Cyclone V loopback options allow you to verify how different functional blocks work in the transceiver.

Related Information

Cyclone V Device Handbook: Known Issues

Lists the planned updates to the Cyclone V Device Handbook chapters.

6

Serial Loopback

This section describes the use of serial loopback as a debugging aid to ensure the enabled PCS and PMA blocks in the transmitter and receiver channels function correctly.

Serial loopback is available for all transceiver configurations except the PIPE mode. You can use serial loopback as a debugging aid to ensure that the enabled physical coding sublayer (PCS) and physical media attachment (PMA) blocks in the transmitter and receiver channels are functioning correctly. Furthermore, you can dynamically enable serial loopback on a channel-by-channel basis.

The data from the FPGA fabric passes through the transmitter channel and is looped back to the receiver channel, bypassing the receiver buffer. The received data is available to the FPGA logic for verification.

Figure 6-1: Serial Loopback Datapath

Transmitter PMA

Transmitter PCS FPGA

Fabric

Serial

Loopback can be

Dynamically

Enabled

Receiver PMA Receiver PCS

When you enable serial loopback, the transmitter channel sends data to both the tx_serial_data output port and to the receiver channel. The differential output voltage on the tx_serial_data port is based on the selected differential output voltage (V

OD

) settings.

©

2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html

. Altera warrants performance of its semiconductor products to current specifications in accordance with

Altera's standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.

ISO

9001:2008

Registered www.altera.com

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6-2

Forward Parallel Loopback

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The looped-back data is forwarded to the receiver clock data recovery (CDR). You must provide an alignment pattern for the word aligner to enable the receiver channel to retrieve the byte boundary.

If the device is not in the serial loopback configuration and is receiving data from a remote device, the recovered clock from the receiver CDR is locked to the data from the remote source.

Note:

For the phy_serial_loopback

Modes” section of the

Transceiver Reconfiguration Controller

chapter in the

Altera Transceiver PHY

IP Core User Guide

.

register access description and addressing, refer to the “Loopback

If the device is placed in the serial loopback configuration, the data source to the receiver changes from the remote device to the local transmitter channel—prompting the receiver CDR to start tracking the phase of the new data source. During this time, the recovered clock from the receiver CDR may be unstable. Because the receiver PCS is running off of this recovered clock, you must place the receiver PCS under reset by asserting the rx_digitalreset signal during this period.

Note:

When moving into or out of serial loopback, you must assert the rx_digitalreset signal for a minimum of two parallel clock cycles.

Related Information

Altera Transceiver PHY IP Core User Guide

Forward Parallel Loopback

Forward parallel loopback is a debugging aid to ensure the enabled PCS blocks in the transmitter and receiver channel function correctly.

Forward parallel loopback is only available in transceiver Native PHY. You enable forward parallel loopback by enabling the PRBS test mode, through the dynamic reconfiguration controller. You must perform a rx_digitalreset after the dynamic reconfiguration operation has completed.

Parallel data travels across the forward parallel loopback path, passing through the RX word aligner, and finally verified inside the RX PCS PRBS verifier block. Check the operations status from the FPGA fabric.

Figure 6-2: Parallel Loopback Datapath

The following figure shows the parallel PRBS data generated by the TX PCS PRBS generator block.

Transmitter PMA Transmitter PCS FPGA

Fabric

Receiver PMA

Forward Parallel

Loopback Path

Receiver PCS

PRBS Gen

PRBS

Checker

Note:

Usage details for the feature are described in the Altera Transceiver PHY IP Core User Guide.

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PIPE Reverse Parallel Loopback

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Altera Transceiver PHY IP Core User Guide

PIPE Reverse Parallel Loopback

This section describes PIPE Reverse Parallel Loopback debugging option using parallel data through the rate match FIFO, transmitter serializer, and tx_serial_data port path.

PIPE reverse parallel loopback is only available in the PCIe

® configuration for Gen1 and Gen2 data rates.

Figure 2 shows the received serial data passing through the receiver CDR, deserializer, word aligner, and rate match FIFO buffer. The parallel data from the rate match FIFO is then looped back to the transmitter serializer and transmitted out through the tx_serial_data port. The received data is also available to the FPGA fabric through the rx_parallel_data signal.

PIPE reverse parallel loopback is compliant with the PCIe 2.0 specification. To enable this loopback configuration, assert the tx_detectrx_loopback signal.

Note:

PIPE reverse parallel loopback is the only loopback option supported in the PCIe configuration.

Figure 6-3: PIPE Reverse Parallel Loopback Configuration Datapath

Transmitter PMA Transmitter PCS FPGA

Fabric

Receiver PMA

Receiver PCS

Reverse Parallel Loopback Path

Note: Grayed-out blocks are not active when the PIPE reverse parallel loopback is enabled.

Reverse Serial Loopback

You can use the reverse serial loopback option to debug with data through the rx_serial_data port

, receiver CDR, and tx_serial_data port path.

You can enable reverse serial loopback through the reconfiguration controller.

Note:

For further details, refer to the Altera Transceiver PHY IP Core User Guide.

In reverse serial loopback, the data is received through the rx_serial_data port, re-timed through the receiver CDR, and sent to the tx_serial_data port. The received data is also available to the FPGA logic. No dynamic pin control is available to select or deselect reverse serial loopback.

The transmitter buffer is the only active block in the transmitter channel. You can change the V

OD and the pre-emphasis first post tap values on the transmitter buffer through the dynamic reconfiguration controller.

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Reverse Serial Pre-CDR Loopback

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Reverse serial loopback is often implemented when using a bit error rate tester (BERT) on the upstream transmitter.

Figure 6-4: Reverse Serial Loopback Datapath

Transmitter PMA Transmitter PCS FPGA

Fabric

Reverse Serial

Loopback Datapath

Receiver PMA Receiver PCS

Note: Grayed-out blocks are not active when the reverse serial loopback is enabled.

Related Information

Altera Transceiver PHY IP Core User Guide

Reverse Serial Pre-CDR Loopback

This section describes reverse serial pre-CDR loopback debugging with a data path through the rx_serial_data port to the tx_serial_data port, and before the receiver CDR.

You can enable reverse serial pre-CDR loopback through the reconfiguration controller.

Note:

For further details, refer to the Altera Transceiver PHY IP Core User Guide.

In reverse serial pre-CDR loopback, the data received through the rx_serial_data port is looped back to the tx_serial_data port before the receiver CDR. The received data is also available to the FPGA logic. No dynamic pin control is available to select or deselect reverse serial pre-CDR loopback.

The transmitter buffer is the only active block in the transmitter channel. You can change the VOD on the transmitter buffer through the dynamic reconfiguration controller. The pre-emphasis settings for the transmitter buffer cannot be changed in this configuration.

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Figure 6-5: Reverse Serial Pre-CDR Loopback Datapath

Transmitter PMA

Transmitter PCS

Reverse Serial

Pre-CDR

Loopback

Datapath

Receiver PMA Receiver PCS

Document Revision History

6-5

FPGA

Fabric

Note: Grayed-out blocks are not active when the reverse serial pre-CDR loopback is enabled.

Related Information

Altera Transceiver PHY IP Core User Guide

Document Revision History

The table below lists the revision history for this chapter.

Table 6-1: Document Revision History

Date

May 2013

November 2012

June 2012

Version

2013.05.06

2012.11.19

1.0

Changes

• Added the Forward Parallel Loopback topic.

• Updated the Reverse Serial Loopback topic.

• Updated the Reverse Serial Pre-CDR Loopback topic.

• Added link to the known document issues in the Knowledge Base.

• Reorganized content and updated template.

• Minor updates for the Quartus II software version 12.1.

Initial release.

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The transceiver reconfiguration controller offers several different dynamic reconfiguration modes. You can choose the appropriate reconfiguration mode that best suits your application needs. All the dynamic reconfiguration modes are implemented through the transceiver Reconfiguration Controller PHY IP.

Related Information

Cyclone V Device Handbook: Known Issues

Lists the planned updates to the

Cyclone V Device Handbook

chapters.

7

Dynamic Reconfiguration Features

The following table lists the available dynamic reconfiguration features.

Table 7-1: Reconfiguration Features

Reconfiguration Feature

Offset Cancellation

DCD Calibration

Analog Controls Reconfiguration

Loopback Modes

Description Affected Blocks

Counter offset variations due to process operation for the analog circuit. This feature is mandatory if you use receivers.

CDR

Compensates for the duty cycle distortion caused by clock network skew.

TX buffer and clock network skew

Fine-tune signal integrity by adjusting the transmitter

(TX) and receiver (RX) analog settings while bringing up a link.

Analog circuit of TX and RX buffer

Enable or disable Pre- and

Post-CDR Reverse Serial

Loopback dynamically.

PMA

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7-2

Offset Cancellation

Reconfiguration Feature

Data Rate Change

Description

Increase or decrease the data rate (/1, /2, /4, /8) for autonegotiation purposes such as CPRI and SATA/

SAS applications

Affected Blocks

TX Local clock dividers

Reconfigure the TX PLL settings for protocols with multi-data rate support such as CPRI

TX PLL

Switch between multiple TX

PLLs for multi-data rate support

• TX PLL

• Fractional PLL (Reconfigure the fPLL data rate with the ALTERA_

PLL_RECONFIG megafunction.)

Channel reconfiguration—Reconfigure the RX CDR from one data rate to another data rate

CDR

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Related Information

Backplane Applications with 28 nm FPGAs

AN661: Implementing Fractional PLL Reconfiguration with ALTERA_PLL and

ALTERA_PLL_RECONFIG Megafunctions

For information about reconfiguration of the fPLL data rate.

Offset Cancellation

Offset cancellation adjusts the offsets within the CDR parameters for process variations.

Every transceiver channel has offset cancellation circuitry to compensate for the offset variations that are caused by process operations. The offset cancellation circuitry is controlled by the offset cancellation control logic IP within the Transceiver Reconfiguration Controller. Resetting the Transceiver Reconfiguration

Controller during user mode does not trigger the offset cancellation process.

When offset cancellation calibration is complete, the reconfig_busy status signal is deasserted to indicate the completion of the process.

The clock ( mgmt_clk_clk

) used by the Transceiver Reconfiguration Controller is also used for transceiver calibration and must be 75-125 MHz if the Hard IP for PCIe Express IP core is not enabled. When the Hard

IP for PCIe Express is enabled, the frequency range is 75-100 MHz. If the clock ( mgmt_clk_clk

) is not free-running, hold the reconfiguration controller reset ( mgmt_rst_reset

) until the clock is stable.

Transmitter Duty Cycle Distortion Calibration

The duty cycle calibration function tunes the transmitter to minimize duty cycle distortion.

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The transmitter clocks generated by the CMU that travel across the clock network may introduce duty cycle distortions (DCD). Reduce DCD with the DCD calibration IP that is integrated in the transceiver reconfiguration controller.

Enabled the DCD calibration IP in Cyclone GT devices for better TX jitter performance, if either of the following conditions are met:

• Data rate is ≥ 4915.2 Mbps

• Clock network switching (TX PLL switching) and the data rate is ≥ 4915.2 Mbps

The following DCD calibration modes are supported:

• DCD calibration at power-up mode

• Manual DCD calibration during user mode

DCD calibration is performed automatically after device configuration and before entering user mode if the transceiver channels connected have the Calibrate duty cycle during power up option enabled. You can optionally trigger DCD calibration manually during user mode if:

• You reconfigure the transceiver from lower data rates to higher data rates (≥ 4.9152 Gbps)

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