CS4237B
CS4237B
CrystalClear Advanced Audio System with 3D Sound
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Integrated SRS®
General Description
3D Sound Technology
TM
Compatible with Sound Blaster , Sound Blaster
ProTM, and Windows Sound SystemTM
The CS4237B is a single chip multimedia audio system
that provides compatibility with the Microsoft Windows
Sound System standard and will run software written to
the Sound Blaster and Sound Blaster Pro interfaces.
The CS4237B is fully compliant with Microsoft’s PC’ 97
and WHQL audio requirements. The product includes
an internal FM synthesizer and Plug-and-Play external
interfaces for Wavetable, CD-ROM, and modem devices. In addition, the CS4237B includes hardware
master volume control pins as well as extensive power
management and SRS 3D sound technology.
Advanced MPC3-Compliant Input and Output Mixer
Enhanced Stereo Full Duplex Operation
Dual Type-F DMA Support
Industry Leading Delta-Sigma Data Converters
Fully Plug-and-Play ISA Compatible
3.3 V or 5 V ISA Bus Operation
Programmable Power Management
Hardware Master Volume Control
Enhanced Digital Gameport
CS9236 Wavetable Digital Audio Interface
MPU-401 MIDI Interface
Consumer IEC-958 Digital Output (S/PDIF)
ORDERING INFORMATION:
CS4237B-JQ
100 pin TQFP, 14x14x1.4mm
CS4237B-KQ
100 pin TQFP, 14x14x1.4mm
CS4236/CS4232/CS4231 Register Compatible
XTALI
XTALO
VREF REFFLT
L/RFILT
VREF
OSCILLATOR
Stereo
A/D
ISA
BUS
INTERFACE
Sample Rate
Converters
SD<7:0>
16
SAMPLE
FIFO
INPUT MIXER
LINEAR
µ-LAW
A-LAW
ADPCM
GAIN
Σ
SA<11:0>
IRQ<A:F>
DRQ<A:C>
DACK<A:C>
CODEC
REG
I/F
Config
IO
IRQ
DMA
Decode
Logic
SA<12:15>
(CDROM)
(Modem)
Loopback
Monitor
Attenuation
GAIN
L/RAUX1
GAIN
L/RAUX2
CMAUX2
GAIN
L/RMIC
ATTN.
MIN
FM
Synthesizer
GAIN
CD-ROM, Modem, or
Upper Address Bits
LINEAR
µ-LAW
A-LAW
ADPCM
Σ
DIGITAL/
ANALOG
JOYSTICK
LOGIC
CS9236
SERIAL
PORT
JOYSTICK
WAVETABLE
SERIAL PORT
Advanced Product Information
Cirrus Logic, Inc.
P.O. Box 17847, Austin, TX 78760
(512) 445 7222 Fax: (512) 445 7581
http://www.cirrus.com
DSP
SERIAL
PORT
DSP SERIAL
PORT
Σ
OUTPUT MIXER
DIGITAL
MIXER
Σ
Stereo
D/A
IOCHRDY
L/RLINE
SERIAL
SHIFT
DSP
AEN
PLUG
AND
PLAY
16
SAMPLE
FIFO
IOW
Sample Rate
Converters
IOR
GAIN
S/PDIF
MOUT
L/ROUT
GAIN
MPU-401
UART
with
FIFOS
Synth. Interface
or Hardware
Volume Control
MIDI
SCS/ SINT/ MUTE
UP DOWN
WSS
SBPRO
Registers
Peripherals
&
EEPROM
Interface
XIOW
XIOR
XD<7:0>
XA<2:0>
BRESET
This document contains information for a new product. Cirrus
Logic, Inc. reserves the right to modify this product without notice.
Copyright  Cirrus Logic, Inc. 1997
(All Rights Reserved)
SEP ’97
DS213PP4
1
CS4237B
TABLE OF CONTENTS
CS4237B PERFORMANCE SPECIFICATIONS 3
GENERAL DESCRIPTION ................................. 12
ISA Bus Interface............................................. 13
PLUG AND PLAY ............................................... 15
PnP Data ......................................................... 16
Loading Resource Data................................... 17
Loading Firmware Patch Data......................... 17
The Crystal Key ............................................... 18
Bypassing Plug and Play................................. 19
Hardware Configuration Data .......................... 20
Hostload Procedure ......................................... 24
External E2PROM............................................ 24
WINDOWS SOUND SYSTEM CODEC .............. 26
Enhanced Functions (MODEs)........................ 26
FIFOs ............................................................... 27
WSS Codec PIO Register Interface ................ 27
DMA Interface.................................................. 28
Sound System Codec Register Interface ........ 29
Direct Mapped Registers (R0-R3) ............... 29
Indirect Mapped Registers (I0-I31) .............. 35
WSS Extended Registers (X0-X25) ............ 48
SOUND BLASTER INTERFACE........................ 57
Mode Switching ............................................... 57
Sound Blaster Register Interface .................... 57
GAME PORT INTERFACE ................................. 60
CONTROL INTERFACE ..................................... 61
Control Register Interface................................ 61
Control Indirect Registers (C0-C8) .................. 65
SRS 3D Sound Overview ................................ 68
Hearing Basics................................................. 69
The SRS 3D Stereo Process .......................... 69
SRS Space Control ......................................... 69
SRS Center Control......................................... 70
SRS Mono-to-Stereo Synthesis....................... 71
Consumer IEC-958 Digital Output................... 71
MPU-401 INTERFACE ........................................ 72
MPU-401 Register Interface ............................ 72
MIDI UART ...................................................... 73
MPU-401 "UART" Mode Operation ................. 73
FM SYNTHESIZER (Internal)............................. 73
EXTERNAL PERIPHERAL PORT...................... 74
Synthesizer Interface ....................................... 74
CDROM Interface ............................................ 75
Modem Interface.............................................. 76
DSP SERIAL AUDIO DATA PORT.................... 76
CS9236 WAVETABLE SERIAL DATA PORT ... 78
WSS CODEC SOFTWARE DESCRIPTION .......79
Calibration ........................................................79
Changing Sampling Rate .................................80
Changing Audio Data Formats.........................81
Audio Data Formats .........................................81
DMA Registers .................................................85
Digital Loopback...............................................86
Timer Registers ................................................86
WSS Codec Interrupt .......................................86
Error Conditions ...............................................87
DIGITAL HARDWARE DESCRIPTION...............87
Bus Interface ....................................................87
Volume Control Interface .................................87
Crystal/Clock ....................................................88
General Purpose Output Pins ..........................88
Reset and Power Down ...................................89
Multiplexed Pin Configuration...........................89
ANALOG HARDWARE DESCRIPTION .............90
Line-Level Inputs Plus MPC Mixer...................90
Microphone Level Inputs ..................................91
Mono Input .......................................................91
Line-Level Outputs ...........................................92
Mono Output with Mute Control .......................92
Miscellaneous Analog Signals..........................92
GROUNDING AND LAYOUT ..............................92
POWER SUPPLIES.............................................93
ADC/DAC FILTER RESPONSE..........................95
PIN DESCRIPTIONS ...........................................97
ISA Bus Interface Pins .....................................98
Analog Inputs ...................................................99
Analog Outputs.................................................100
MIDI Interface...................................................101
External FM Synthesizer Interface ...................101
External Peripheral Port ...................................101
Joystick/DSP Serial Port Interface ...................103
CS9236 Wavetable Serial Port Interface .........104
CDROM Interface.............................................105
Volume Control.................................................106
Miscellaneous ...................................................106
Power Supplies ................................................107
PARAMETER DEFINITIONS...............................108
PACKAGE PARAMETERS .................................109
APPENDIX A: E2PROM TYPICAL DATA ..........110
APPENDIX B: CS4237B DIFFERENCES...........112
Windows and Windows Sound System are registered trademarks of Microsoft Corporation.
Sound Blaster and Sound Blaster Pro are registered trademarks of Creative Labs.
Adlib is a registered trademark of Adlib Corporation.
The word SRS and the SRS Symbol
are registered trademarks of SRS Labs, Inc.
The CS4237B incorporates the SRS (Sound Retrieval System) under license from SRS Labs, Inc.
2
DS213PP4
CS4237B
ANALOG CHARACTERISTICS
TA = 25 °C; VA, VD1, VDF1-VDF4 = +5V
Input Levels: Logic 0 = 0V, Logic 1 = VD1; 1 kHz Input Sine wave; Sample Frequency, Fs = 44.1 kHz;
Measurement Bandwidth is 20 Hz to 20 kHz - unweighted, 16-bit linear coding.)
CS4237B-JQ
Parameter*
Symbol
Min
Typ
CS4237B-KQ
Max
Min
Typ
Max
Units
Analog Input Characteristics - Minimum Gain Setting (0dB); unless otherwise specified.
ADC Resolution
(Note 1)
16
-
-
16
-
-
Bits
ADC Differential Nonlinearity
(Note 1)
-
-
±0.5
-
-
±0.5
LSB
85
79
-
dB
dB
Instantaneous Dynamic Range
Line Inputs
(Note 2) Mic Inputs
IDR
-
80
75
-
80
72
Total Harmonic Distortion
THD
-
0.05
0.05
-
-
Line to Line Inputs
Line to Mic Inputs
Line-to-AUX1
Line-to-AUX2
-
80
80
90
90
-
-
80
80
90
90
-
dB
dB
dB
dB
Interchannel Gain Mismatch
Line Inputs
Mic Inputs
-
-
±0.5
±0.5
-
-
±0.5
±0.5
dB
dB
Programmable Input Gain Span
Line Inputs
21.5
22.5
-
21.5
22.5
-
dB
1.3
1.5
1.7
1.3
1.5
1.7
dB
-
-
-
-
±10
±100
LSB
0.26
2.6
2.6
0.28
2.8
2.8
-
0.26
2.6
2.6
0.28
2.8
2.8
-
Vpp
Vpp
Vpp
-
±100
-
-
±100
-
ppm/°C
8
20
11
23
-
8
20
11
23
-
kΩ
kΩ
-
15
pF
Line Inputs
Mic Inputs
Interchannel Isolation
Gain Step Size
ADC Offset Error
0 dB Gain
Full Scale Input Voltage: (MGE=1) MIC Inputs
(MGE=0) MIC Inputs
LINE, AUX1, AUX2, MIN Inputs
Gain Drift
Input Resistance
(Note 1) Mic Inputs
Other Inputs
Input Capacitance
(Note 1)
15
Notes: 1. This specification is guaranteed by characterization, no production testing.
2. MGE = 1 (see WSS Indirect Reg I0, I1).
0.006 0.02
0.01 0.025
%
%
*Parameter definitions are given at the end of this data sheet.
Specifications are subject to change without notice.
DS213PP4
3
CS4237B
ANALOG CHARACTERISTICS
(Continued)
CS4237B-JQ
Parameter*
Symbol
Min
Typ
CS4237B-KQ
Max
Min
Typ
Max
Units
Analog Output Characteristics - Minimum Attenuation (0dB); unless otherwise specified.
DAC Resolution
(Note 1)
16
-
-
16
-
-
Bits
DAC Differential Nonlinearity
(Note 1)
-
-
±0.5
-
-
±0.5
LSB
TDR
IDR
-
85
-
80
95
85
-
dB
THD
-
0.01
-
-
0.01
0.02
%
Dynamic Range
-Total
All Outputs
-Instantaneous
Total Harmonic Distortion
(Note 3)
Interchannel Isolation
(Note 3)
-
95
-
-
95
-
dB
Line Out
-
±0.1
±0.5
-
±0.1
±0.5
dB
2.0
2.2
2.5
2.0
2.2
2.5
V
-
100
400
-
100
400
µA
DAC Programmable Attenuation Span
100
106.5
-
100
106.5
-
dB
DAC Attenuation Step Size +12 dB to -81 dB
-82.5 dB to -94.5 dB
1.3
1.0
1.5
1.5
1.7
2
1.3
1.0
1.5
1.5
1.7
2
dB
dB
-
-
-
-
±1
±10
mV
2.6
2.8
3.2
2.6
2.8
3.2
Vpp
-
100
-
-
100
-
ppm/°C
-
-
1
-
-
1
Degree
10
-
-
10
-
-
kΩ
80
-
-
80
-
-
dB
0.6xFs to 100 kHz
(Note 1)
-
-
-
-
-
-45
dB
Audible Out-of-Band Energy 0.6xFs to 22 kHz
(Fs=8kHz)
(Note 1)
-
-
-
-
-
-70
dB
-
80
25
105
100
-
-
80
25
105
100
91
31
122
400
mA
mA
mA
µA
40
-
-
40
-
-
dB
Line Out
Interchannel Gain Mismatch
Voltage Reference Output - VREF
Voltage Reference Output Current - VREF
(Notes 1,4)
DAC Offset Voltage
Full Scale Output Voltage:
OUT, MOUT
(Note 3)
Gain Drift
Deviation from Linear Phase
(Passband)
(Note 1)
External Load Impedance
(Note 1)
Mute Attenuation
Total Out-of-Band Energy
Power Supply
Power Supply Current
Digital, Operating
Analog, Operating
Total Operating
Total Power Down
Power Supply Rejection 1 kHz
(Note 1)
Notes: 3. 10 kΩ, 100 pF load.
4. DC current only. If dynamic loading exists, then the voltage reference output must be buffered
or the performance of ADCs and DACs will be degraded.
4
DS213PP4
CS4237B
MIXERS (TA = 25 °C; VA, VD1, VDF1-VDF4 = +5V; Input Levels:
Logic 0 = 0V, Logic 1 = VD1;
1 kHz Input Sine wave, Measurement Bandwidth is 20 Hz to 20 kHz - unweighted.)
CS4237B-JQ
Parameter*
Min
Typ
Max
Min
Typ
Max
Units
LINE, AUX1, AUX2
MIC, MIN
Hardware Master
Wavetable, Monitor, PC Wave, DSP, FM
-
-
-
45
42
44
90
46.5
45
48
94.4
-
dB
dB
dB
dB
MIC, LINE, AUX1, AUX2
MIN
Hardware Master
Wavetable, Monitor, PC Wave, DSP, FM
-
-
-
1.3
2.3
1.6
0.9
1.5
3.0
2.0
1.5
1.7
3.7
2.4
2.0
dB
dB
dB
dB
-
88
-
-
94.5
91
-
dB
dB
-
0.005
-
-
0.002
-
dB
Mixer Gain Range Span
(Digital)
Step Size
(Digital)
CS4237B-KQ
Dynamic Range
(Analog Mixers)
-Total
-Instantaneous
Total Harmonic Distortion
(Analog Mixers)
(Note 3)
ABSOLUTE MAXIMUM RATINGS (AGND, DGND, SGND = 0V, all voltages with respect to 0V.)
Parameter
Symbol
Power Supplies:
Digital
VD1
VDF1-VDF4
Analog
VA
Total Power Dissipation
Min
Max
Units
-0.3
-0.3
-0.3
6.0
6.0
6.0
V
V
V
-
1
W
(Supplies, Inputs, Outputs)
Input Current per Pin
(Except Supply Pins)
-10.0
+10.0
mA
Output Current per Pin
(Except Supply Pins)
-50
+50
mA
-0.3
VA+0.3
V
SA<11:0>, IOR, IOW, AEN
SD<7:0>, DACK<A:C>
-0.3
VD1+0.3
V
All other digital inputs
-0.3
VDF+0.3
V
-55
+125
°C
+150
°C
Analog Input Voltage
Digital Input Voltage:
Ambient Temperature
(Power Applied)
Storage Temperature
-65
Warning: Operation beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
RECOMMENDED OPERATING CONDITIONS (AGND, DGND, SGND = 0V,
all voltages with respect to 0V.)
Parameter
Power Supplies:
Digital
Symbol
Min
Typ
Max
Units
VD1
4.75
3.0
4.75
4.75
5.0
3.3
5.0
5.0
5.25
3.6
5.25
5.25
V
V
V
V
(Note 5)
Digital Filtered
Analog
VDF1-VDF4
VA
0
25
70
°C
Operating Ambient Temperature
TA
Note
5. When VD1 is powered from 3.3 Volts, all ISA bus input pins, except DRQA, must also be 3.3 Volts.
DRQA is internally powered from the VDF supply and must have a 5 Volt interface. To use DRQA in
a 3.3 Volt application, a level translator is needed.
DS213PP4
5
CS4237B
DIGITAL FILTER CHARACTERISTICS (Note 1)
Parameter
Symbol
Min
Typ
Max
Units
0
-
0.40xFs
Hz
-1.0
-
+0.5
dB
-
-
±0.1
dB
Transition Band
0.40xFs
-
0.60xFs
Hz
Stop Band
0.60xFs
-
-
Hz
74
-
-
dB
8- and 16-bit formats
Stereo ADPCM format
Mono ADPCM format
-
-
10/Fs
14/Fs
18/Fs
s
s
s
ADCs
DACs
-
-
0.0
0.1/Fs
µs
µs
Passband
Frequency Response
Passband Ripple
(0-0.40xFs)
Stop Band Rejection
Group Delay
Group Delay Variation vs. Frequency
DIGITAL CHARACTERISTICS (TA = 25°C; VA, VDF1-VDF4 = 5V, VD1 = 5V/3V;
AGND, DGND1, SGND1-SGND4 = 0V.)
Parameter
High-level Input Voltage
Digital Inputs
XTALI
Low-level Input Voltage
High-level Output Voltage:
ISA Bus Pins (except DRQA)
I0 = -24.0 mA
DRQA
I0 = -24.0 mA
IOCHRDY, SDA/XD0 (Note 6)
All Others
I0 = -1.0 mA
Low-level Output Voltage:
ISA Bus Pins
IOCHRDY
All Others
Input Leakage Current
6
mA
mA
mA
mA
(Digital Inputs)
Min
Max
Units
VIH
2.0
VD-1.0
-
V
V
VIL
-
0.8
V
VOH
2.4
2.4
2.4
2.4
VD1
VDF
VDF
VDF
V
V
V
V
VOL
-
0.55
0.4
0.4
0.4
V
V
V
V
-10
10
µA
µA
6. Open Collector pins. High level output voltage dependent on external pull up (required) used and
number of peripherals (gates) attached.
Output Leakage Current
Note
I0 = 24.0
I0 = 18.0
I0 = 8.0
I0 = 4.0
Symbol
(High-Z Digital Outputs)
-10
10
DS213PP4
CS4237B
TIMING PARAMETERS (TA = 25 °C; VA, VD1, VDF1-VDF4 = +5V; outputs loaded with 30pF
Input Levels: Logic 0 = 0V, Logic 1 = VD1)
Parameter
Symbol
Min
Max
Units
tAA
0
3.5
µs
tHD:STA
4.0
-
µs
Clock Low Period
tLSCL
4.7
-
µs
Clock High Period
tHSCL
4.0
-
µs
Start Condition Setup Time
(for a Repeated Start Condition)
tSU:STA
4.7
-
µs
Data In Hold Time
tHD:DAT
0
-
µs
Data In Setup Time
tSU:DAT
250
-
ns
tR
-
1
µs
tF
-
300
ns
tSU:STO
4.7
-
µs
E2PROM Timing (Note 1)
SCL Low to SDA Data Out Valid
Start Condition Hold Time
SDA and SCL Rise Time
(Note 7)
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
tDH
0
ns
Notes 7. Rise time on SDA is determined by the capacitance of the SDA line with all connected gates and the
external pullup resistor required.
tF
t HSCL
t HD:STA
t HD:DAT
t LSCL
tR
XA0/SCL
t SU:STA
t SU:DAT
t SU:STO
XD0/SDA (IN)
t AA
t DH
XD0/SDA (OUT)
E2PROM 2-Wire Interface Timing
DS213PP4
7
CS4237B
TIMING PARAMETERS (Continued)
Parameter
Symbol
Min
Max
Units
tSTW
90
-
ns
tWDSU
22
-
ns
IOR falling edge to data valid (read cycle)
tRDDV
-
60
ns
SA <> and AEN setup to IOR or IOW falling edge
tADSU
22
-
ns
SA <> and AEN hold from IOW or IOR rising edge
tADHD
10
-
ns
DACK<> inactive to IOW or IOR falling edge (DMA cycle
immediately followed by a non-DMA cycle)
(Note 8)
tSUDK1
60
-
ns
DACK<> active from IOW or IOR rising edge (non-DMA
cycle completion followed by DMA cycle)
(Note 8)
tSUDK2
0
-
ns
DACK<> setup to IOR falling edge (DMA cycles)
DACK<> setup to IOW falling edge
tDKSUa
tDKSUb
25
25
-
ns
ns
tDHD2
15
-
ns
tDRHD
-25
45
-
ns
Time between rising edge of IOW or IOR to next falling
edge of IOW or IOR
tBWDN
80
-
ns
Data hold from IOR rising edge
tDHD1
0
25
ns
DACK<> hold from IOW rising edge
DACK<> hold from IOR rising edge
tDKHDa
tDKHDb
25
25
-
ns
ns
1
-
ms
130
1200
ms
1
420
ms
Parallel Bus Timing
IOW or IOR strobe width
Data valid to IOW rising edge
(write cycle)
(Note 8)
Data hold from IOW rising edge
DRQ<> hold from IOW or IOR falling edge
(assumes no more DMA cycles needed)
RESDRV pulse width high
Initialization Time
EEPROM Read Time
DTM(I10) = 0
DTM(I10) = 1
(Note 1) tRESDRV
(Note 1, 9)
tINIT
(Note 1, 10) tEEPROM
XTAL, 16.9344 MHz, frequency
(Notes 1, 11)
16.92
16.95
MHz
XTALI high time
(Notes 1, 11)
24
-
ns
XTALI low time
(Notes 1, 11)
24
-
ns
Sample Frequency
(Note 1)
Fs
3.918
50
kHz
SCLK rising to SDOUT valid
(Note 1)
tPD1
-
60
ns
SCLK rising to FSYNC transition
(Note 1)
tPD2
-20
20
ns
SDIN valid to SCLK falling
(Note 1)
tS1
30
-
ns
SDIN hold after SCLK falling
(Note 1)
tH1
30
-
ns
Serial Port Timing
Notes: 8. AEN must be high during DMA cycles.
9. Initialization time depends on the power supply circuitry, as well as the the type of clock used.
10. EEPROM read time is dependent on amount of data in EEPROM. Minimum time relates to no
EEPROM present. Maximum time relates to EEPROM data size of 2k bytes.
11. The Sample frequency specification must not be exceeded.
8
DS213PP4
CS4237B
t
FSYNC
SF1,0=01,10
FSYNC
SF1,0=00
t
pd2
t
pd2
pd2
SCLK
t
t
sckw
s1
t
h1
SDIN
MSB, Left
SDOUT
MSB, Left
t
pd1
DSP Serial Port Timing
DRQ<>
t DKSUa
t DRHD
DACK<>
t STW
t DKHDb
IOR
t DHD1
t RDDV
SD<7:0>
8-Bit Mono DMA Read/Capture Cycle
t RESDRV
RESDRV
t
XD0/XA0
INIT
t EEPROM
EEPROM read
SD<7:0>
Codec responds to ISA activity
Reset Timing
DS213PP4
9
CS4237B
DRQ<>
t DKSUb
t DRHD
DACK<>
t STW
t DKHDa
IOW
t WDSU
t DHD2
SD<7:0>
8-Bit Mono DMA Write/Playback Cycle
DRQ<>
DACK<>
IOR/IOW
tBWDN
LEFT/LOW
BYTE
SD<7:0>
RIGHT/HIGH
BYTE
8-Bit Stereo or 16-Bit Mono DMA Cycle
DRQ<>
DACK<>
IOR/IOW
t BWDN
SD<7:0>
LEFT/LOW
BYTE
LEFT/HIGH
BYTE
RIGHT/LOW
BYTE
RIGHT/HIGH
BYTE
16-Bit Stereo or ADPCM DMA Cycle
10
DS213PP4
CS4237B
DRQ<>
t SUDK1
t SUDK2
DACK<>
IOR
t RDDV
t DHD1
SD<7:0>
t ADSU
t ADHD
SA<>
AEN
I/O Read Cycle
DRQ<>
t SUDK1
t SUDK2
DACK<>
t STW
IOW
t WDSU
tDHD2
SD<7:0>
t ADSU
tADHD
SA<>
AEN
I/O Write Cycle
DS213PP4
11
CS4237B
GENERAL DESCRIPTION
This device is comprised of six physical devices
along with Plug-and-Play support for two additional external devices. The internal devices are:
Windows Sound System Codec
Sound Blaster Pro Compatible Interface
Game Port (Joystick)
Control
MPU-401
FM Synthesizer
The two external devices are:
IDE CDROM
Modem
A full ISA interface with Plug and Play compatibility and an External Peripheral Port for
interfacing to external devices (i.e. Wave-Table
Synthesizer, CDROM, and Modem) is included.
Since the Wave-Table Synthesizer and CDROM
analog inputs are external, mapping as shown in
Figure 5, on page 58, must be used to maintain
Sound Blaster compatibility, i.e. CDROM analog
must be connected to the AUX2 analog inputs of
the mixer.
On power up, this part requires a RESDRV signal to initialize the internal configuration. When
initially powered up, the part is isolated from the
bus, and each device supported by the part must
be activated via software. Once activated, each
device responds to the resources given (Address,
IRQ, and DMA channels). The eight devices
listed above are grouped into six logical devices,
as shown in Figure 1 (bracketed features are supported, but typically not used). The six logical
devices are:
LOGICAL DEVICE 0:
Windows Sound System Codec (WSS Codec)
Adlib/Sound Blaster-compatible Synthesizer
Sound Blaster Pro Compatible Interface
LOGICAL DEVICE 1: Game Port
LOGICAL DEVICE 2: Control
12
LOGICAL DEVICE 3: MPU401
LOGICAL DEVICE 4: CDROM
LOGICAL DEVICE 5: Modem
Logical Device 0 consists of three physical devices. The WSS Codec and the Synthesizer are
grouped together since the original Windows
Sound System board expected an FM synthesizer
if the codec was present. The Sound Blaster Pro
Compatible interface, SBPro, is also grouped to
allow the WSS Codec and the SBPro to share
Interrupts and DMA channels. The Synthesizer
device could be the internal FM synthesizer, or a
synthesizer externally located on the Peripheral
Port. The external synthesizer interface supports
both FM and wavetable synthesizers such as the
CS9233. The WSS Codec, FM synthesizer, and
the SBPro compatible devices are internal to the
part.
Logical Device 1 is the Game Port that supports
up to two joystick devices.
Logical Device 2 is the Control device that supports global features of the part. This device uses
I/O locations to control power management,
joystick rate, and PnP resource data loading.
Logical Device 3 is the MPU-401 interface. The
MPU-401 MIDI interface includes a 16-byte
FIFO for data transmitted out the MIDOUT pin
and a 16-byte FIFO for data received from the
MIDIN pin.
Logical Device 4 supports an IDE CDROM connected to the peripheral port. This interface, on
the external peripheral port, can support
CDROMs with up to 8 I/O locations and supports both the base address and the alternate base
address, an interrupt, and a DMA channel. Although this logical device is listed as a CDROM,
any external device that fits within the resources
listed above may be substituted.
DS213PP4
CS4237B
PnP ISA Bus
Interface
Logical Device 1
WSS Codec:
Game Port:
Control:
MPU-401:
CDROM:
Modem:
I/O: GAMEbase
I/O: CTRLbase
[1 Interrupt]
I/O: MPUbase
1 Interrupt
I/O:
CDbase
ACDbase
[1 Interrupt]
[1 DMA Chan.]
I/O: COMbase
[1 Interrupt]
I/O: WSSbase
2 DMA Chan.
1 Interrupt
Synthesis:
Logical Device 2
Logical Device 3
Logical Device 4
Logical Device 5
Logical Device 0
Figure 1. Logical Devices
I/O: SYNbase
[1 Interrupt]
SBPro:
I/O: SBbase
(DMA shared)
(Interrupt shared)
Logical Device 5 supports a modem connected
to the peripheral port. This interface, on the external peripheral port, supports modems with 2
to 256 I/O locations (only SA2-SA0 are buffered
through the part) and supports a base address
and an interrupt. Although this logical device is
listed as a modem, any external device that fits
within the resources listed above may be substituted.
ISA Bus Interface
The 8-bit parallel I/O and 8-bit parallel DMA
ports provide an interface which is compatible
with the Industry Standard Architecture (ISA)
bus. The ISA Interface enables the host to com-
DS213PP4
municate with the various functional blocks
within the part via two types of accesses: Programmed I/O (PIO) access, and DMA access.
A number of configuration registers must be programmed prior to any accesses by the host
computer. The configuration registers are programmed via a Plug-and-Play configuration
sequence or via configuration software provided
by Crystal Semiconductor.
I/O CYCLES
Every device that is enabled, requires I/O space.
An I/O cycle begins when the part decodes a
valid address on the bus while the DMA acknowledge signals are inactive and AEN is low.
The IOR and IOW signals determine the direction of the data transfer. For read cycles, the part
will drive data on the SD<7:0> lines while the
host asserts the IOR strobe. Write cycles require
the host to assert data on the SD<7:0> lines and
strobe the IOW signal. Data is latched on the rising edge of the IOW strobe.
13
CS4237B
I/O ADDRESS DECODING
The logical devices use 10-bit or 12-bit address
decoding. The Synthesizer, Sound Blaster, Game
Port, MPU-401, CDROM, and Modem devices
support 10-bit address decoding, while the Windows Sound System and Control devices support
12-bit address decoding. Devices that support
10-bit address decoding, require A10 and A11 be
zero for proper decode; therefore, no aliasing occurs through the 12-bit address space.
To prevent aliasing into the upper address space,
a "16-bit decode" option may be used, where the
upper address bits SA12 through SA15 are connected to the part. SA12-SA15 are then decoded
to be 0,0,0,0 for all logical device address decoding. When the upper address bits are used,
the CDROM and Modem interfaces are no
longer available since the upper address pins are
multiplexed with the CDROM and Modem interfaces (See Reset and Power Down section). If
the CDROM or Modem is needed, the circuit
shown in Figure 2 can replace the SA12 through
SA15 pins and provide the same functionality.
Four cascaded OR gates, using a 74ALS32, can
replace the ALS138 in Figure 2, but causes a
greater delay in address decoding.
74ALS138
ISA Bus
SA12
SA13
SA14
1
2
3
A
Y0
B
Y1
C
Y2
15
Y3
Y4
SA15
AEN
+5V
4
5
6
G2A
Y5
G2B
Y6
G1
Y7
Figure 2. 16-bit Decode Circuit
14
AEN
DMA CYCLES
The part supports up to three 8-bit ISA-compatible DMA channels. The default hardware
connections, which can be changed through the
hardware configuration data, are:
DMA A = ISA DMA channel 0
DMA B = ISA DMA channel 1
DMA C = ISA DMA channel 3
The typical configuration would require two
DMA channels. One for the WSS Codec and
Sound Blaster playback, and the other for WSS
Codec capture (to support full-duplex). The
CDROM, if used, can also support a DMA channel, although this is not typical.
DMA cycles are distinguished from control register cycles by the generation of a DRQ (DMA
Request). The host acknowledges the request by
generating a DACK (DMA Acknowledge) signal. The transfer of audio data occurs during the
DACK cycle. During the DACK cycle the address lines are ignored.
The digital audio data interface uses DMA request/grant pins to transfer the digital audio data
between the part and the ISA bus. Upon receipt
of a DMA request, the host processor responds
with an acknowledge signal and a command
strobe which transfers data to and from the part,
eight bits at a time. The request pin stays active
until the appropriate number of 8-bit cycles have
occurred. The number of 8-bit transfers will vary
depending on the digital audio data format, bit
resolution, and operation mode.
The DMA request signal can be asserted at any
time. Once asserted, the DMA request will remain asserted until a complete DMA cycle
occurs. A complete DMA cycle consists of one
or more bytes depending on which device internal to the part is generating the request.
DS213PP4
CS4237B
INTERRUPTS
For Plug-and-Play flexibility, six interrupt pins
are supported, although only one or two are typically used. The default hardware connections,
which can be modified through the hardware
configuration data, are:
IRQ A = ISA Interrupt 5
IRQ B = ISA Interrupt 7
IRQ C = ISA Interrupt 9
IRQ D = ISA Interrupt 11
IRQ E = ISA Interrupt 12
IRQ F = ISA Interrupt 15
The typical configuration would support two interrupt sources: one shared between the WSS
Codec and the Sound Blaster Pro compatible devices, and the other for the MPU401 device.
Interrupts are also supported for the Synthesizer,
Control, CDROM devices, but are typically not
used. If the modem logical device (LD5) is used,
it would typically support an interrupt.
PLUG AND PLAY
The Plug-and-Play (PnP) interface logic is compatible with the Intel/Microsoft Plug-and-Play
specification, version 1.0a, for an ISA-bus device. Since the part is an ISA-bus device, it only
supports ISA-compatible IRQs and DMA channels. Plug and Play compatibility allows the PC
to automatically configure the part into the system upon power up. Plug and Play capability
optimally resolves conflicts between Plug and
Play and non-Plug and Play devices within the
system. Alternatively, the PnP feature can be bypassed. See the Bypassing PnP section for more
information. For a detailed Plug-and-Play protocol description, please refer to the Plug and Play
ISA Specification.
To support Plug-and-Play in ISA systems that do
not have a PnP BIOS or a PnP-aware operating
system, the Configuration Manager (CM) TSR
and an ISA Configuration Utility (ICU) from Intel Corp. are used to provide these functions.
DS213PP4
The CM isolates the cards, assigns Card Select
Numbers, reads PnP card resource requirements,
and allocates resources to the cards based on
system resource availability. The ICU is used to
keep the BIOS and the CM informed of the current system configuration. It also aids users in
determining configurations for non-PnP ISA
cards. A more thorough discussion of the Configuration Manager and the ISA Configuration
Utility can be found in the Product Development
Information document of the Plug and Play Kit
by Intel Corp. In a PnP BIOS system, the BIOS
is responsible for configuring at least all system
board PnP devices. Some systems require additional software to aid the BIOS in configuring
PnP ISA cards. The PnP BIOS can execute all
PnP functions independently of the type of operating system. However, if a PnP aware operating
system is present, the PnP responsibilities are
shared between the BIOS and the operating system. For more information regarding PnP BIOS,
please refer to the latest revision of the Plug and
Play BIOS Specification published by Compaq
Computer, Phoenix Technologies, and Intel.
The Plug and Play configuration sequence maps
the various functional blocks of the part (logical
devices) into the host system address space and
configures both the DMA and interrupt channels.
The host has access to the part via three 8-bit
auto-configuration ports: Address port (0279h),
Write Data port (0A79h), and relocatable Read
Data port (020Bh - 03FFh). The read data port is
relocated automatically by PnP software when a
conflict occurs.
The configuration sequence is as follows:
1. Host sends a software key which places all
PnP cards in the sleep state (or Plug-andPlay mode).
2. The Crystal part is isolated from the system
using an isolation sequence.
15
CS4237B
3. A unique identifier (handle) is assigned to the
part and the resource data is read.
4. After all cards’ resource requirements are determined, the host uses the handle to assign
conflict-free resources
5. After the configuration registers have been
programmed, each configured logical device
is activated.
6. The part is then removed from Plug-and-Play
mode.
Upon power-up, the chip is inactive and must be
enabled via software. The Crystal part monitors
writes to the PnP Auto-Configuration Address
port (0279h). If the host sends a PnP initiation
key, consisting of a series of 32 predefined byte
writes, the hardware will detect the key and
place the part into the Plug-and-Play (PnP)
mode. Another method to program the part is to
use a special Crystal initiation key which functions like the PnP initiation key, but can be
invoked by the user at any time. However, the
Crystal Key only supports one Crystal part per
system. The Crystal key and special commands
are detailed in the Crystal Key and Bypassing
PnP sections.
The isolation sequence uses a unique 72-bit serial identifier. The host performs 72 pairs of I/O
read accesses to the Read Data port. The identifier determines what data is put on the data bus
in response to those read accesses. When the isolation sequence is complete, the CM assigns a
Card Select Number (CSN) to the part. This
number distinguishes the Crystal part from the
other PnP devices in the system. The Configuration Manager (CM) then reads the resource data
from the Crystal part. The 72-bit identifier and
the resource data is either stored in an external
user-programmable E2PROM, or loaded via a
"hostload" procedure from BIOS before PnP
software is initiated.
16
The CM determines the necessary resource requirements for the system and then programs the
part through the configuration registers. The configuration register data is written one logical
device at a time. After all logical devices have
been configured, CM activates each device individually. Each logical device is now available on
the ISA bus and responds to the programmed
address range, DMA channels, and interrupts that
have been allocated to that logical device.
PnP Data
Hardware Configuration and Plug-and-Play resource data must be loaded into the part’s RAM.
The data may be stored in an external E2PROM
or may be downloaded from the host.
To load the data, refer to the Loading Resource
Data section. The following is the Plug-and-Play
resource data:
The first nine bytes of the PnP resource data are
the Plug-and-Play ID, which uniquely identifies
the Crystal part from other PnP devices. The
Crystal default is broken down as follows:
0Eh, 63h - Crystal ID - ’CSC’ in compressed
ASCII. (See the PnP Spec for more
information)
42h - Oem ID. A unique Oem ID must be obtained from Crystal for each unique
Crystal product used.
37h - Crystal product ID for the CS4237B
FFh, FFh, FFh, FFh - Serial number. This can
be modified by each OEM to uniquely
identify their card.
??h - Checksum.
Of the 9-byte serial number listed above, Crystal
software uses the first two bytes to indicate the
presence of a Crystal part, and the fourth byte,
0x37, to indicate the CS4237B; therefore, these
three bytes must not be altered.
DS213PP4
CS4237B
The next 3 bytes are the PnP version number.
The default is version 1.0a: 0Ah, 10h, 01h.
External E2PROM section for more information
on the serial E2PROM interface and E2PROM
programming.
The next sequence of bytes are the ANSI identifier string. The default is: 82h, 0Eh, 00h,
’Crystal Codec’, 00h.
The format for the data stored in the E2PROM is
as follows:
The logical device data must be entered using
the PnP ISA Specification format. Typical logical
device values are found in Table 1. The
E2PROM version for this data is found in Appendix A.
Loading Resource Data
A serial E2PROM interface allows user-programmable serial number and resource data to be
stored in an external E2PROM. The interface is
compatible with devices from a number of vendors and the size may vary according to specific
customer requirements. The maximum size for
resource data supported by the part’s internal
RAM is 384 bytes of combined Hardware Configuration and PnP resource data. With the
addition of the 4-byte header, the maximum
amount of E2PROM space used would be 388
bytes. However, the part also supports firmware
upgrades via the E2PROM. The maximum size
E2PROM supported is 2k bytes. After power-up,
the existence of an E2PROM is checked by reading the first two bytes from the E2PROM
interface. If the data from the E2PROM port
reads 55h and BBh, then the rest of the
E2PROM data is loaded into the internal RAM.
If the first two bytes aren’t correct, the E2PROM
is assumed not to exist and a "hostload" procedure must be used to load the internal RAM. The
Hostload procedure can be found in the Hostload
section. For motherboard designs, an E2PROM
should still be included, to allow faster integrating of resource and firmware patch data. This
allows updates without respiring BIOS code. If
the part is installed on a plug-in card, then an
external E2PROM is required to ensure that the
proper PnP resource data is loaded into the internal RAM prior to a PnP sequence. See the
DS213PP4
(Hardware Configuration Data:)
2 bytes E2PROM validation: 55h, BBh
2 bytes length of resource data in E2PROM
19 bytes Hardware Configuration
(Plug and Play Resource Data:)
9 bytes Plug and Play ID
3 bytes Plug and Play version number
Variable number of bytes of user defined
ASCII ID string
Logical Device 0 (Windows Sound System,
FM Synthesizer, Sound Blaster Pro) data
Logical Device 1 ( Game Port) data
Logical Device 2 ( Control) data
Logical Device 3 ( MPU-401) data
Logical Device 4 ( CD-ROM) data
Logical Device 5 (Modem) data
End of Resource byte & checksum byte
Firmware patch code.
A typical E2PROM data load, in assembly format, can be found in Appendix A.
Loading Firmware Patch Data
An external E2PROM is read during the powerup sequence that stores Hardware Configuration
and PnP data, and firmware patch data. The part
contains RAM and ROM to run the core proces17
CS4237B
sor. The RAM allows updates to the core processor functionality. Placing the firmware patches
in E2PROM, gives the maximum functionality at
power-up without the need for a software driver.
The firmware patch data is typically included at
the end of the PnP resource data. Crystal provides a utility that will read in patch data from a
file, and append it to the PnP resource data. The
patch file must be obtained from Crystal.
Physical Device
Logical Device
WSS
16-bit address
decode
high true
edge sensitive
8-bit, count by
byte, type A
same
Synthesis
16-bit address
decode
0
WSSbase
Length/Alignment
IRQ
SB Pro
16-bit address
decode
Game Port
16-bit address
decode
Control
16-bit address
decode
MPU401
16-bit address
decode
DMA
DMA
0
SYNbase
Length/Alignment
IRQ
0
SBbase
Length/Alignment
1
GAMEbase
Length/Alignment
2
CTRLbase
Length/Alignment
IRQ
3
MPUbase
Length/Alignment
IRQ
The Crystal Key
NOTE: The Crystal Key cannot differentiate between multiple Crystal Codecs in a system;
therefore, ONLY ONE Crystal part is allowed in
systems using the Crystal Key. To allow multiple
parts in a system, the Plug-and-Play isolation sequence must be used since it supports multiple
parts via the serial identifier used in the isolation
sequence.
Best Choice
Acceptable
Choice 1
534h-534h
4/4
5
(SB share)
1
(SB share)
0, 3
534-608h
4/D4h
5,7,9,11,12,15
(SB share)
0, 3
(SB share)
0, 1, 3
388h
4/8
----
388h
4/8
----
220h
16/16
220-260h
16/32
200h
8/8
208h
8/8
Sub optimal
Sub optimal
Choice 1
Choice 2
ANSI ID = WSS/SB
534-FFCh
4/4
5, 7, 9, 11, 12, 15
(SB share)
0, 1, 3
(SB share)
---388-3F8h
4/8
---220-300h
16/32
ANSI ID = GAME
ANSI ID = CTRL
120-3F8h
8/8
---330h
2/8
9
330-360h
2/8
9,11,12,15
ANSI ID = MPU
330-3E0h
2/8
----
---- Feature not supported in the listed configuration, but is supported through customization.
Table 1. Typical Motherboard Plug-and-Play Resource Data
18
DS213PP4
CS4237B
The Crystal key places the part in the configuration mode. Once the Crystal key has been
initiated, new PnP resource data can be downloaded by a hostload sequence, or an alternate
method of programming the configuration registers may be used. This alternate method is
referred to as the "SLAM" method. The SLAM
method allows the user to directly access the
configuration registers, configure, and activate
the chip, and then, optionally, disable the PnP
and/or Crystal key feature. The SLAM method
uses commands that are similar to the PnP commands; however, they are different since the user
has direct access to the configuration registers.
To use the SLAM method, see the Bypassing
PnP section.
To use the SLAM method, the following sequence must be followed:
The following 32 bytes, in hex, are the Crystal
key:
96, 35, 9A, CD, E6, F3, 79, BC,
I/O Port Base Address 0 (47h, xxh, xxh)
high byte , low byte
5E, AF, 57, 2B, 15, 8A, C5, E2
F1, F8, 7C, 3E, 9F, 4F, 27, 13,
09, 84, 42, A1, D0, 68, 34, 1A
Bypassing Plug and Play
The SLAM method allows the user to bypass the
Plug and Play features and, as an option, allows
the part to act like a non-Plug and Play or legacy
device; however, the SLAM method only supports one Crystal IC per system. The user
directly programs the resources into the part, and
then optionally disables the PnP and/or the Crystal Key, which forces the part to disregard any
future PnP or Crystal initiation key sequences
(All activated logical devices appear as legacy
devices to PnP). The Crystal and PnP keys can
also be disabled through the E2PROM.
1. Host sends 32-byte Crystal key to I/O
0279h, chip enters configuration mode.
2. Host programs CSN (Card Select Number)
by writing a 06h and 00h to I/O 0279h.
3. Host programs the configuration registers of
each logical device by writing to I/O 0279h.
The following data is the maximum amount
of information per device. All current devices
only need a subset of this data:
Logical Device ID (15h, xxh)
xxh is logical device number: 0-5
I/O Port Base Address 1 (48h, xxh, xxh)
high byte , low byte
I/O Port Base Address 2 (42h, xxh, xxh)
high byte , low byte
Interrupt Select 0 (22h, xxh)
Interrupt Select 1 (27h, xxh)
DMA Select 0 (2Ah, xxh)
DMA Select 1 (25h, xxh)
Activate Device (33h, 01h)
(33h, 00h deactivates a device)
4. Repeat #3 for each logical device to be enabled. (Not all devices need be enabled.)
5. Host activates chip by writing a 79h to 279h.
6. (Optional) Host disables PnP Key by writing
a 55h to CTRLbase+5. The part will not participate in any future PnP cycles. The Crystal
Key can also be disabled by writing a 56h to
CTRLbase+5.
DS213PP4
19
CS4237B
NOTE: To enable the PnP/Crystal Keys after
they have been disabled by the SLAM
method, bring the RESDRV pin to a logic
high or remove power from the device.
The following illustrates typical data sent using
the SLAM method.
006h, 001h
; CSN=1
015h, 000h
047h, 005h, 034h
048h, 003h, 088h
042h, 002h, 020h
022h, 005h
02Ah, 001h
025h, 003h
033h, 001h
; LOGICAL DEVICE 0
; WSSbase = 0x534
; SYNbase = 0x388
; SBbase = 0x220
; WSS & SB IRQ = 5
; WSS & SB DMA0 = 1
; WSS capture DMA1 = 3
; activate logical device 0
015h, 001h
; LOGICAL DEVICE 1
047h, 002h, 000h ; GAMEbase = 0x200
033h, 001h
; activate logical device 1
015h, 002h
; LOGICAL DEVICE 2
047h, 001h, 020h ; CTRLbase = 0x120
033h, 001h
; activate logical device 2
015h, 003h
; LOGICAL DEVICE 3
047h, 003h, 030h ; MPUbase=0x330
022h, 009h
033h, 001h
; MPU IRQ = 9
; activate logical device 3
079h
; activate Crystal device
If all the above data is sent, after the Crystal key,
all devices except the CDROM and Modem will
respond to the appropriate resources given.
20
Hardware Configuration Data
The Hardware Configuration data contains mapping information that links interrupt and DMA
pins with actual interrupt numbers used by PnP
and SLAM procedures. This data also controls
the XCTL0/XA2 pin functionality. The Hardware Configuration data precedes the PnP
Resource data.
The Hardware Configuration data is either 19 or
23 bytes long and contains the data necessary to
configure the part. If an E2PROM is not used
(Hostload), the first four bytes are not needed,
which means the configuration data is only 19
bytes long. The configuration data maps the
many functions of the logical devices to the
physical pins of the chip. Table 2 lists the Hardware Configuration bytes. The detailed bit
descriptions for each byte follows below.
HW Config. Byte 5: ACDbase Address Length
Mask, Default = 00000000
D7
D6
D5
D4
D3
D2
D1
D0
res
res
res
res
res
CM2
CM1
CM0
CM2-CM0
Address bit masks for the Alternate
CDROM address decode, ACDbase.
See the CDROM Interface section
for more details on ACDbase
000 - ACDCS low for 1 byte
001 - ACDCS low for 2 bytes
011 - ACDCS low for 4 bytes
111 - ACDCS low for 8 bytes
xxx - all others, RESERVED
DS213PP4
CS4237B
BYTE
Default
Description
2
1
55h
E PROM validation byte 1.
The first two bytes tell the Crystal Codec that the E2PROM exists.
2
BBh
E2PROM validation byte 2
3
00h
High byte for length of resource data in E2PROM
4
DDh
Low byte for length of resource data in E2PROM
5
00h
Alternate CDROM (Logical Device 4), ACDbase, Address length mask
6
03h
Modem (Logical Device 5), COMbase, Address length mask
7
80h
Misc. Configuration Bits: Interrupt Pin Polarities, Key Disables, VCEN, & LD4 features
8
00h
Global Configuration Bits: IFM, VCF1 and VCF0, WTEN, SPS
9
0Bh
Code Base Byte - Must be 0x0B
10*
20h
RESERVED - Must be 0x20
11*
04h
RESERVED - Must be 0x04
12*
08h
RESERVED - Must be 0x08
13*
10h
RESERVED - Must be 0x10
14*
80h
RESERVED - Must be 0x80
15*
00h
RESERVED - Must be 0x00
16*
00h
RESERVED - Must be 0x00
17
00h
External Peripheral Port I/O Decode Address Length 00 = 4 bytes, 08 = 8 bytes
08h causes XCTL0/XA2 pin to change to peripheral port address bit XA2.
18*
48h
RESERVED - Must be 0x48
19
75h
IRQ A/B Selection: Lower nibble = A, Upper nibble = B.
Along with next two bytes - specify hardware interrupts tied to IRQA-IRQF pins
20
B9h
IRQ C/D Selection: Lower nibble = C, Upper nibble = D.
21
FCh
IRQ E/F Selection: Lower nibble = E, Upper nibble = F.
22
10h
DMA A/B Selection: Lower nibble = A, Upper nibble = B.
This byte and the next byte - specify hardware DRQ/DACKs tied to the DMAA-DMAC pins
23
03h
DMA C Selection: Lower nibble = C, Upper nibble = reserved (must be 0).
NOTE:The first four bytes are exclusive to the E2PROM and are not used in the Hostload mode.
* Currently not supported. Must be set to default values given in the table.
Table 2. Hardware Configuration Data
DS213PP4
21
CS4237B
HW Config. Byte 6: COMbase Address Length
Mask, Default = 00000011
HW Config. Byte 7: Misc. Configuration Bits,
Default = 10000000
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
MM7
MM6
MM5
MM4
MM3
MM2
MM1
MM0
IHCD
IHS
PKD
CKD
IHM
VCEN
SDD
ACDB7D
MM7-MM0
Address bit masks for Logical Device
5, typically a modem address,
COMbase. See the Modem Interface
Section for more details on
COMbase.
00000000 - MCS low for 1 byte
00000001 - MCS low for 2 bytes
00000011 - MCS low for 4 bytes
00000111 - MCS low for 8 bytes
00001111 - MCS low for 16 bytes
00011111 - MCS low for 32 bytes
00111111 - MCS low for 64 bytes
01111111 - MCS low for 128 bytes
11111111 - MCS low for 256 bytes
xxxxxxxx - all others, RESERVED
NOTE: The part only buffers the lower three address
bits onto the peripheral port. When setting the address decode greater than 8 bytes, the upper
address bits should be buffered externally.
22
ACDB7D
Alternate CDROM, data Bit 7 Disable.
When set, SD7 is held in a high
impedance state when reading from
ACDbase+1 (only this one address).
This bit provides support for IDE alternate base address sharing with
the floppy disk controller.
SDD
SD Disable. When set, SD<7:0> are
high impedance on reads from any
peripheral port address: External synthesis, CDROM or Modem devices.
Allows external buffers to bypass the
part while still allowing PnP address
support. This bit is also internally
forced on whenever WTEN or SPS
in HW Config. byte 8, or C8, is set.
VCEN
Volume Control Enable. When set,
the UP, DOWN, and MUTE pins become active and provide a hardware
master volume control.
IHM
Interrupt High - Modem (LD5). When
set, MINT is active high. When clear,
MINT is active low.
CKD
Crystal Key disable. When set, blocks
the part from receiving the Crystal
key. Note that if both CKD and PKD
are set, software will be unable to reconfigure the part.
PKD
PnP Key disable. When set, blocks
the part from receiving the Plug-andPlay key. Note that if both CKD and
PKD are set, software will be unable
to reconfigure the part.
IHS
Interrupt High - Synthesizer. When
set, SINT is active high. When clear,
SINT is active low.
IHCD
Interrupt High - CDROM. When set,
CDINT is active high. When clear,
CDINT is active low.
DS213PP4
CS4237B
10 - MUTE is not used. Two button
volume control. Pressing the up
and down buttons simultaneously
causes the volume to mute.
Pressing up or down un-mutes.
11 - UP pin is not used. The
MUTE pin functions as the Up
function. With this exception, this
mode functions similarly to the
pervious two-button mode. This
mode provides backwards
compatibility with the CS4236.
HW Config. Byte 8: Global Configuration Bits,
Default = 00000000
D7
D6
D5
IFM
VCF1
VCF0
D4
D3
SLAD WTEN
D2
D1
D0
SPS
res
res
res
Must be set to zero to allow compatibility with future upgrades.
SPS
DSP Serial Port Switch. When
set, switches the DSP serial port
pins from the second joystick to the
XD4-XD1 pins. Then, when SPE in
I16 is set, the XD4-XD1 pins convert
to the DSP serial port pins. Once
this bit is enabled, the SD bus will
not be driven when accesses occur
to peripheral port devices. This function is also available in C8.
WTEN
SLAD
VCF1,0
WaveTable Serial Port Enable. When
set, forces XD7-XD5 pins to convert
to the CS9236 Single-Chip Wavetable Music Synthesizer serial port
pins. Once this bit is enabled, the
SD bus will not be driven when accesses occur to peripheral port
devices. This function is also available in C8.
Soundblaster Alternate Line Disable.
When clear, Sound Blaster (SB)
Synthesizer Volume changes affect
the LINE Alternate (X0/X1) volume.
When set, SB Synthesizer Volume
changes do not affect X0/X1 registers.
Hardware Volume Control Format.
These bits control the format of the
hardware volume control pins UP,
DOWN, and MUTE. The volume control is enabled by setting VCEN in
the previous Hardware Configuration
byte.
00 - MUTE is a toggle switch. When
MUTE is low, the volume is muted.
01 - MUTE is a momentary switch.
MUTE toggles between mute and
un-mute. Pressing the up or down
switch always un-mutes.
DS213PP4
IFM
Internal FM. When set, the internal
FM synthesizer is enabled. When
clear, FM must be provided on the
external LINE analog inputs.
HW Config. Byte 9: Code Base Byte,
Default = 00001011
D7
D6
D5
D4
D3
D2
D1
D0
CB7
CB6
CB5
CB4
CB3
CB2
CB1
CB0
CB7-CB0
Code Base Byte. Determines the code
base located in the E2PROM. If not
correct, the Firmware code after the
PnP resource data is not loaded.
0x0B - CS4237B
0x43 - CS4236
The next 7 bytes are reserved for future expansion and must be set to their default values as
listed in Table 2
The next byte of hardware configuration data is
byte 17 in Table 2. This byte determines the
function of the XCTL0/XA2 pin. The default of
0, forces the pin to the control function XCTL0,
and the external peripheral port supports only 4
I/O locations through XA0-XA1. If this byte is
set to 08h, the pin switches to the XA2 function
and the peripheral port supports 8 I/O locations
through XA2-XA0.
The next byte, listed as byte 18, is reserved for
future expansion and must be set to 0x48.
23
CS4237B
Bytes 19 through 21 map the interrupt number to
the actual interrupt pins A - F. As shown in the
table, the byte 20 default is 0xB9; therefore,
IRQC, which is the lower nibble, maps to the
ISA interrupt 9. Likewise IRQD, which is the
upper nibble, maps to the ISA interrupt 11
(0Bh).
2. Write 57h (Jump to ROM) command to
CTRLbase+5.
Bytes 22 and 23 map the DMA channel number
to the actual DMA pins A-C. As shown in the
table, the byte 22 default is 0x10; therefore,
DRQA/DACKA is the lower nibble which maps
to the ISA DMA channel 0. Likewise
DRQB/DACKB is the upper nibble which maps
to the ISA DMA channel 1.
b. Send starting download address (4000h)
by writing low byte (00h) first, and then
high byte (40h) to CTRLbase+5.
Hostload Procedure
This procedure is provided for backwards compatibility with the CS4236. Since the E2PROM
allows all resource and firmware patch data to be
loaded at power-up, this procedure is typically
not used. To download PnP resource data from
the host to the part’s internal RAM, use the following sequence:
1. Configure Control I/O base address,
CTRLbase, by one of two methods: regular
PnP cycle or Crystal Key method.
a. The host can use the regular PnP cycle to
program the CTRLbase, and then place the
chip in the wait_for_key_state
b. If the Crystal Key method is used:
First, send the 32-byte Crystal key to I/O
address 0279h. (The Crystal Key only
supports one Crystal part per system.)
Second, configure logical device 2 base
address, CTRLbase, by writing to I/O
0279h (15h, 02h, 47h, xxh, xxh, 33h,
01h, 79h).
Note: The two xxh represent the base_address_high and base_address_low
respectively. The default is: 01h, 20h.
24
3. Download the PnP resource data.
a. Send download command by writing AAh
to CTRLbase+5.
c. Send the Hardware Configuration and resource data in successive bytes to
CTRLbase+5. This includes the Hardware
Configuration and the PnP resource data.
The PnP resource format is described in
the PnP Data section. The resource header
should not contain the first four bytes
which are only used for E2PROM loads.
4. End download by writing 00h to
CTRLbase+6.
5. If any of the Hardware Configuration Data
(first 19 bytes) has changed, 5Ah must be
written to CTRLbase+5 to force the part to
internally update this information.
The new PnP data is loaded and the part is ready
for the next PnP cycle.
External E2PROM
The Plug and Play specification defines 32 bits
of the 72-bit Serial Identifier as being a user defined serial number. The E2PROM is used to
change the user section of the identifier, store
default resource data for PnP, Hardware Configuration data specific to the Crystal part, and
firmware patches to upgrade the core processor
functionality.
DS213PP4
CS4237B
The E2PROM interface uses an industry standard
2-wire interface consisting of a bi-directional
data line and a clock line driven from the part.
After power-on the part looks for the existence
of an E2PROM device and loads the user defined data. The existence is determined by the
first two bytes read (0x55 followed by 0xBB). If
the first two bytes are correct, the part reads the
next two bytes to determine the length of data in
the E2PROM. The length bytes indicate the
number of bytes left to be read (not including
the two validation bytes or two length bytes). As
shown in Figure 3, the E2PROM is read using a
start bit followed by a dummy write, to initialize
the address to zero. Then another start bit and
device address, followed by all the data. Since
the part uses the sequential read properties of the
E2PROM, only one E2PROM, is supported
(ganged E2PROMs are not supported).
The maximum Hardware Configuration and PnP
resource RAM data supported is 384 bytes, and
a four byte header; therefore, the maximum
amount of data storage, without firmware
patches, in E2PROM would be 388 bytes. The
maximum size E2PROM supported is 2k bytes.
This allows the inclusion of firmware patches after the PnP resource data.
If an external E2PROM exists, it is accessed by
the serial interface and is connected to the XD0
and XA0 pins. The two-wire interface is controlled by three bits in the Control logical device,
Hardware Control Register (CTRLbase+1). The
serial data can be written to or read from the
E2PROM by sequentially writing or reading that
register. The three register bits, D0, D1, D2 are
labeled CLK, DOUT, and DIN/EEN respectively.
The DIN/EEN bit, when written to a one, enables the E2PROM serial interface. When the
DIN/EEN bit is written to a zero, the serial interface is disabled. The DIN/EEN bit is also the
Data In (DIN) signal to read back data from the
E2PROM. The XD0 pin is a bi-directional opendrain data line supporting DIN and DOUT;
therefore, to read the correct data, the DOUT bit
must be set to a one prior to performing a read
of the register. Otherwise, the data read back
from DIN/EEN will be all zeros. The E2PROM
data can then be read from the DIN/EEN bit.
The CLK bit timing is controlled by the host
software. This is the serial clock for the
E2PROM. The DOUT bit is used to write/program the data out to the E2PROM. An external
pull-up resistor is required on XD0 because it is
an open-drain output. Use the guidelines in the
Some E2PROMs that are compatible with this
interface are:
Atmel
AT24Cxx series
MicroChip
24LCxxB series
National
NM24CxxL series
Ramtron
FM24Cxx series
SGS Thompson ST24Cxx series
Xicor
X24Cxx series
where the xx is replaced by 02, 04, 08, or 16
based on the size of the E2PROM desired. The
size of 16 (2k bytes) is preferred since it allows
the maximum flexibility for upgrading firmware
patches. Other E2PROMs compatible with Figure 3 and the timing parameters listed in the
front of the data sheet may also be used.
Crystal IC
Bank
Part
Start Address Write Address
Start
Part Read
Address
S 1 0 1 0 0 0 0 0 A 0 0 0 0 0 0 0 0 AS 1 0 1 0 0 0 0 1 A
EEPROM
Acknowledge
Acknowledge
Data
A
No
Acknowledge
Stop
Data
1P
Data
Figure 3. EEPROM Format
DS213PP4
25
CS4237B
specific E2PROM data sheet to select the value
of the pull-up resistor (a typical value would be
3.3kΩ).
Programming the E2PROM:
1. Configure Control I/O base address by one
of two methods: regular PnP cycle or Crystal
Key method.
a. The host can use the regular PnP cycle to
program the logical device 2 I/O base address, and then place the chip in the
wait_for_key_state
b. If the Crystal Key method is used:
First, write to I/O 0279h, send the 32byte Crystal key. (The Crystal Key only
supports one Crystal part per system.)
Second, configure the Control I/O base
address by writing 15h, 02h, 47h, 01h,
20h, 33h, 01h, 79h to 0279h.
2. Refer to the specific data sheet for the
E2PROM you are using for timing requirements and data format. Also, refer to the
Loading Resource Data section of this data
sheet for the E2PROM resource data format.
3. Send the E2PROM data in successive bits to
CTRLbase+1 (Hardware Control Register)
while following the E2PROM data sheet format.
The E2PROM now contains the PnP resource
data. For this new data to take effect, the part
must be reset, causing the part to read the
E2PROM during initialization. Crystal can provide a utility, RESOURCE.EXE, to program
E2PROMs through the Control logical device interface.
WINDOWS SOUND SYSTEM CODEC
The WSS Codec software interface consists of 4
I/O locations starting at the Plug and Play address ’WSSbase’, and supports 12-bit address
decoding. If the upper address bits, SA12-SA15
are used, they must be 0 to decode a valid address. The WSS Codec also requires one
interrupt and one or preferably two DMA channels, one for playback and one for capture. Since
the WSS Codec and Sound Blaster device are
mutually exclusive, the two devices share the
same interrupt and DMA playback channel.
The WSS Codec/Mixer is register compatible
with the Microsoft Windows Sound System.
Functions include stereo Analog-to-Digital and
Digital-to-Analog converters (ADCs and DACs),
analog mixing, anti-aliasing and reconstruction
filters, line and microphone level inputs, optional
A-Law/µ-Law coding, simultaneous capture and
playback (at independent sample frequencies)
and a parallel bus interface. Five analog inputs
are provided and four can be mixed to the ADC
mixer. All five can be mixed with the output of
the DAC with full volume control. Several data
modes are supported including 8- and 16-bit linear as well as 8-bit companded, 4-bit ADPCM
compressed, and 16-bit big Endian.
Enhanced Functions (MODEs)
The initial state is labeled MODE 1 and forces
the part to appear as a CS4248. The more popular second mode, MODE 2, forces the part to
appear as a CS4231 super set and is compatible
with the CS4232. To switch from MODE 1 to
MODE 2, the CMS1,0 bits, in the MODE and
ID register (I12), should be set to 10 respectively. When MODE 2 is selected, the bit IA4 in
the Index Address register (R0) will be decoded
as a valid index pointer providing 16 additional
registers and increased functionality over the
CS4248.
To reverse the procedure, set the CMS1,0 bits to
00 and the part will resume operation in
26
DS213PP4
CS4237B
MODE 1. Except for the Capture Data Format
(I28), Capture Base Count (I30/31), and Alternate Feature Status (I24) registers, all other
Mode 2 functions retain their values when retur ning to Mode 1. The WS S Codec is
backwards compatible with the CS4236,
CS4232, CS4231 and CS4248.
The additional MODE 2 functions are: full-duplex support, a programmable timer, Mono In
and Mono Out support.
MODE 3 is selected by setting CMS1,0 to 11.
MODE 3 allows access to new bits in the indirect registers I0-I31, and allows access to a third
set of "extended registers" which are designated
X0-X17+X25. The extended registers are accessed through I23. The additional MODE 3
functions are:
1. A full symmetrical mixer. This changes the input multiplexer to a input mixer.
2. Independent sample frequency control on the
ADCs and DACs.
3. Programmable Gain and Attenuation on the
Microphone inputs.
4. Independent control over the volume of internal FM synthesis and external wavetable.
5. Volume control on the DSP serial port input
data.
6. Stereo volume on the monitor feedback path.
FIFOs
The WSS Codec contains 16-sample FIFOs in
both the playback and capture digital audio data
paths. The FIFOs are transparent and have no
programming associated with them.
When playback is enabled, the playback FIFO
continually requests data until the FIFO is full,
DS213PP4
and then makes requests as positions inside the
FIFO are emptied, thereby keeping the playback
FIFO as full as possible. Thus when the system
cannot respond within a sample period, the FIFO
starts to empty, avoiding a momentary loss of
audio data. If the FIFO runs out of data, the last
valid sample can be continuously output to the
DACs (if DACZ in I16 is set) which will eliminate pops from occurring.
When capture is enabled, the capture FIFO tries
to continually stay empty by making requests
every sample period. Thus when the system cannot respond within a sample period, the capture
FIFO starts filling, thereby avoiding a loss of
data in the audio data stream.
WSS Codec PIO Register Interface
Four I/O mapped locations are available for accessing the Codec functions and mixer. The
control registers allow access to status, audio
data, and all indirect registers via the index registers. The IOR and IOW signals are used to
define the read and write cycles respectively. A
PIO access to the Codec begins when the host
puts an address on to the ISA bus which matches
WSSbase and drives AEN low. WSSbase is programmed during a Plug and Play configuration
sequence. Once a valid base address has been
decoded then the assertion of IOR will cause the
WSS Codec to drive data on the ISA data bus
lines. Write cycles require the host to assert data
on the ISA data bus lines and strobe the IOW
signal. The WSS Codec will latch data into the
PIO register on the rising edge of the IOW
strobe.
The audio data interface typically uses DMA request/grant pins to transfer the digital audio data
between the WSS Codec and the bus. The WSS
Codec is responsible for asserting a request signal whenever the Codec’s internal buffers need
updating. The bus responds with an acknowledge
signal and strobes data to and from the Codec, 8
bits at a time. The WSS Codec keeps the request
27
CS4237B
pin active until the appropriate number of 8-bit
cycles have occurred to transfer one audio sample. Note that different audio data types will
require a different number of 8-bit transfers.
DMA Interface
The second type of parallel bus cycle from the
WSS Codec is a DMA transfer. DMA cycles are
distinguished from PIO register cycles by the assertion of a DRQ followed by an
acknowledgment by the host by the assertion of
DACK (with AEN high). While the acknowledgment is received from the host, the WSS
Codec assumes that any cycles occurring are
DMA cycles and ignores the addresses on the
address lines.
The WSS Codec may assert the DMA request
signal at any time. Once asserted, the DMA request will remain asserted until a complete DMA
cycle occurs to the part. DMA transfers may be
terminated by resetting the PEN and/or CEN bits
in the Interface Configuration register (I9), depending on the DMA that is in progress
(playback, capture, or both). Termination of
DMA transfers may only happen between sample
transfers on the bus. If DRQ goes active while
resetting PEN and/or CEN, the request must be
acknowledged with DACK and a final sample
transfer completed.
DMA CHANNEL MAPPING
Mapping of the WSS Codec’s DRQ and DACK
onto the ISA bus is accomplished by the Plug
and Play configuration registers. If the Plug and
Play resource data specifies only one DMA
channel for the Codec (or the codec is placed in
SDC mode) then both the playback and capture
DMA requests should be routed to the same
DRQ/DACK pair (DMA Channel Select 0). If
the Plug and Play resource data specifies two
DMA channels for the Codec, then the playback
DMA request will be routed to the DMA pair
specified by the DMA Channel Select 0 resource
28
data, and the capture DMA requests will be
routed to the DMA pair specified by the DMA
Channel Select 1 resource data.
DUAL DMA CHANNEL MODE
The WSS Codec supports a single and a dual
DMA channel mode. In dual DMA channel
mode, playback and capture DMA requests and
acknowledges occur on independent DMA channels. In dual DMA mode, SDC should be set to
0. The Playback- and Capture-Enables (PEN,
CEN, I9) can be changed without a Mode
Change Enable (MCE, R0). This allows for
proper full duplex control where applications are
independently using playback and capture.
SINGLE DMA CHANNEL (SDC) MODE
When two DMA channels are not available, the
SDC mode forces all DMA transfers (capture or
playback) to occur on a single DMA channel
(playback channel). The trade-off is that the
WSS Codec will no longer be able to perform
simultaneous DMA capture and playback.
To enable the SDC mode, set the SDC bit in the
Interface Configuration register (I9). With the
SDC bit asserted, the internal workings of the
WSS Codec remain exactly the same as dual
mode, except for the manner in which DMA request and acknowledges are handled.
The playback of audio data will occur on the
playback channel exactly as dual channel operation; however, the capture audio channel is now
diverted to the playback channel. Alternatively
stated, the capture DMA request occurs on DMA
channel select 0 for the WSS Codec. (In
MODEs 2 and 3, the capture data format is always set in register I28.) If both playback and
capture are enabled, the default will be playback.
SDC does not have any affect when using PIO
accesses.
DS213PP4
CS4237B
Sound System Codec Register Interface
The Windows Sound System codec is mapped
via four locations. The I/O base address,
WSSbase, is determined by the Plug and Play
configuration. The WSSbase supports four direct
registers, shown in Table 3. The first two direct
registers are used to access 32 indirect registers
shown in Table 4. The Index Address register
(WSSbase+0) points to the indirect register that
is accessed through the Indexed Data register
(WSSbase+1).
This section describes all the direct and indirect
registers for the WSS Codec. Table 5 details a
summary of each bit in each register with Tables 6 through 15 illustrating the majority of
decoding needed when programming the WSS
logical device, and are included for reference.
When enabled, the WSS Codec default state is
defined as MODE 1. MODE 1 is backwards
compatible with the CS4248 and only allows access to the first 16 indirect registers. Putting the
part in MODE 2 or MODE 3, using CMS1,0 bits
in the MODE and ID register (I12), allows access to indirect registers 16 through 31. Putting
the part in MODE 3 also allows access to the
extended registers through I23 and other extended features in the indirect registers.
DIRECT MAPPED REGISTERS
The first two WSS Codec registers provide indirect accessing to more codec registers via an
index register. The other two registers provide
status information and allow audio data to be
transferred to and from the WSS Codec without
using DMA cycles or indexing.
Note that register defaults are listed in binary
form with reserved bits marked with ’x’ to indicate unknown. To maintain compatibility with
future parts, these reserved bits must be written
as 0, and must be masked off when the register
is read. The current value read for reserved bits
is not guaranteed on future revisions.
DS213PP4
Direct Registers: (R0-R3)
Address
Reg.
Register Name
WSSbase+0
R0
Index Address register
WSSbase+1
R1
Indexed Data register
WSSbase+2
R2
Status register
WSSbase+3
R3
PIO Data register
Table 3. WSS Codec Direct Register
Index
I0
I1
I2
I3
I4
I5
I6
I7
I8
I9
I10
I11
I12
I13
I14
I15
I16
I17
I18
I19
I20
I21
I22
I23
I24
I25
I26
I27
I28
I29
I30
I31
Register Name
Left ADC Input Control
Right ADC Input Control
Left Aux #1 Volume
Right Aux #1Volume
Left Aux #2 Volume
Right Aux #2 Volume
Left DAC (PC Wave) Volume
Right DAC (PC Wave) Volume
Fs & Playback Data Format
Interface Configuration
Pin Control
Error Status and Initialization
MODE and ID
Monitor Loopback Volume
Playback Upper Base Count
Playback Lower Base Count
Alternate Feature Enable I
Alternate Feature Enable II
Left Line (Synthesizer) Volume
Right Line (Synthesizer) Volume
Timer Low Byte
Timer High Byte
Alternate Sample Frequency
Extended Register Access (X regs)
Alternate Feature Status
Compatibility ID
Mono Input & Output Control
Reserved
Capture Data Format
Reserved
Capture Upper Base Count
Capture Lower Base Count
Table 4. WSS Codec Indirect Registers
29
CS4237B
Direct Registers: WSSbase (R0-R3)
ADDRESS
WSSbase+0 R0
WSSbase+1 R1
WSSbase+2 R2
WSSbase+3 R3
D7
D6
D5
D4
D3
D2
D1
D0
INIT
MCE
TRD
IA4
IA3
IA2
IA1
IA0
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
CU/L
CL/R
CRDY
SER
PU/L
PL/R
PRDY
INT
CD7/PD7
CD6/PD6
CD5/PD5
CD4/PD4
CD3/PD3
CD2/PD2
CD1/PD1
CD0/PD0
Indirect Registers: (I0-I31)
IA4-IA0
0
1
2
3
4
5
6
7
8§
9§
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
D7
D6
D5
D4
D3
D2
D1
D0
LSS1
LSS0
LMGE
-
LAG3
LAG2
LAG1
LAG0
RSS1
RSS0
RMGE
-
RAG3
RAG2
RAG1
RAG0
LX1OM
LX1IM
LX1BM
LX1G4
LX1G3
LX1G2
LX1G1
LX1G0
RX1OM
RX1IM
RX1BM
RX1G4
RX1G3
RX1G2
RX1G1
RX1G0
LX2OM
LX2IM
-
LX2G4
LX2G3
LX2G2
LX2G1
LX2G0
RX2OM
RX2IM
-
RX2G4
RX2G3
RX2G2
RX2G1
RX2G0
LDOM
LPM
RDOM
RPM
FMT1
LDG6
res
RDG6
res
FMT0
LDG5
LPA5
RDG5
RPA5
C/L
LDG4
LPA4
RDG4
RPA4
S/M
LDG3
LPA3
RDG3
RPA3
CFS2
LDG2
LPA2
RDG2
RPA2
CFS1
LDG1
LPA1
RDG1
RPA1
CFS0
LDG0
LPA0
RDG0
RPA0
C2SL
CPIO
PPIO
-
CAL1
CAL0
SDC
CEN
PEN
XCTL1
XCTL0
OSM1
OSM0
DEN
DTM
IEN
-
COR
PUR
ACI
DRS
ORR1
ORR0
ORL1
ORL0
1
CMS1
CMS0
-
ID3
ID2
ID1
ID0
LBA5
LBA4
LBA3
LBA2
LBA1
LBA0
-
LBE
PUB7
PUB6
PUB5
PUB4
PUB3
PUB2
PUB1
PUB0
PLB7
PLB6
PLB5
PLB4
PLB3
PLB2
PLB1
PLB0
DACZ
OLB
TE
CMCE
PMCE
SF1
SF0
SPE
TEST
TEST
TEST
TEST
APAR
-
XTALE
HPF
LLOM
LR7
RLOM
RR7
TL7
LLIM
LR6
RLIM
RR6
TL6
LLBM
LR5
RLBM
RR5
TL5
LLG4
LR4
RLG4
RR4
TL4
LLG3
LR3
RLG3
RR3
TL3
LLG2
LR2
RLG2
RR2
TL2
LLG1
LR1
RLG1
RR1
TL1
LLG0
LR0
RLG0
RR0
TL0
TU7
TU6
TU5
TU4
TU3
TU2
TU1
TU0
SRE
DIV5
DIV4
DIV3
DIV2
DIV1
DIV0
CS2
XA3
XA2
XA1
XA0
XRAE
XA4
-
ACF
-
TI
CI
PI
CU
CO
PO
PU
0
0
0
0
0
0
1
1
MIM
MOM
MBY
-
MIA3
MIA2
MIA1
MIA0
-
-
-
-
-
-
-
-
FMT1
FMT0
C/L
S/M
-
-
-
-
-
-
-
-
-
-
-
-
CUB7
CUB6
CUB5
CUB4
CUB3
CUB2
CUB1
CUB0
CLB7
CLB6
CLB5
CLB4
CLB3
CLB2
CLB1
CLB0
Table 5. WSS Codec Direct & Indirect Register Bits
30
DS213PP4
CS4237B
bit5
bit4
bit3
bit2
bit1
bit0
WG5-0 (X16,17)
LBA5-0, PA5-0, SPA5-0, FMA5-0
0
0
0
0
.
0
.
.
1
1
1
1
0
0
0
0
.
0
.
.
1
1
1
1
0
0
0
0
.
1
.
.
1
1
1
1
0
0
0
0
.
0
.
.
1
1
1
1
0
0
1
1
.
0
.
.
0
0
1
1
0
1
0
1
.
0
.
.
0
1
0
1
12.0 dB
10.5 dB
9.0 dB
7.5 dB
0 dB
-78.0 dB
-79.5 dB
-81.0 dB
-82.5 dB
0.0 dB
-1.5 dB
-3.0 dB
-4.5 dB
.
-12.0 dB
.
.
-90.0 dB
-91.5 dB
-93.0 dB
-94.5 dB
0
1
2
3
.
8
.
.
60
61
62
63
Table 6. Wavetable, Loopback, PC Wave, DSP Serial, & FM
bit3
bit2
bit1
0
0
0
0
.
.
.
1
1
1
1
0
0
0
0
.
.
.
1
1
1
1
0
0
1
1
.
.
.
0
0
1
1
0
1
2
3
.
.
.
12
13
14
15
bit0 Input Gain Mono In
(I0,I1)
(I26)
0
1
0
1
.
.
.
0
1
0
1
0.0 dB
1.5 dB
3.0 dB
4.5 dB
18.0 dB
19.5 dB
21.0 dB
22.5 dB
0.0 dB
-3.0 dB
-6.0 dB
-9.0 dB
.
.
.
-36.0 dB
-39.0 dB
-42.0 dB
-45.0 dB
Table 7. Input ADC Gain and Mono In Levels
LIS1
RIS1
LIS0
RIS0
LEVEL
0
0
1
1
0
1
0
1
0 dB
-6 dB
-12 dB
-18 dB
G4
G3
G2
G1
G0
Level
0
0
0
0
0
0
0
0
0
0
0
0
0
.
.
.
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
.
.
.
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
.
.
.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
.
.
.
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
.
.
.
0
1
0
1
0
1
0
1
12.0 dB
10.5 dB
9.0 dB
7.5 dB
6.0 dB
4.5 dB
3.0 dB
1.5 dB
0.0 dB
-1.5 dB
-3.0 dB
-4.5 dB
-6.0 dB
.
.
.
-24.0 dB
-25.5 dB
-27.0 dB
-28.5 dB
-30.0 dB
-31.5 dB
-33.0 dB
-34.5 dB
0
1
2
3
4
5
6
7
8
9
10
11
12
.
.
.
24
25
26
27
28
29
30
31
Table 10. AUX1, AUX2, LINE
Table 8. Input Mixer Attenuation
2
0
0
0
0
1
1
1
1
CFS
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
C2SL = 0
8.0 kHz
16.0 kHz
27.42 kHz
32.0 kHz
N/A
N/A
48.0 kHz
9.6 kHz
C2SL=1
5.51 kHz
11.025 kHz
18.9 kHz
22.05 kHz
37.8 kHz
44.1 kHz
33.075 kHz
6.62 kHz
Table 9. Sample Frequencies
DS213PP4
FMT1
FMT0 C/L
0
0
0
0
0
1
0
1
0
0
1
1
1
0
1
1
1
0
Data Format
Linear, 8-bit unsigned
µ-Law, 8-bit companded
Linear, 16-bit two’s
complement, Little Endian
A-Law, 8-bit companded
ADPCM, 4-bit, IMA compatible
Linear, 16-bit two’s
complement, Big Endian
Table 11. WSS Codec Data Format
31
CS4237B
Decimal
Value
Hex
Value
64
65
66
67
68
69
70
71
72
127
0
1
2
3
4
5
6
23
24
25
26
27
28
29
30
31
32
62
63
40
41
42
43
44
45
46
47
48
7F
0
1
2
3
4
5
6
17
18
19
1A
1B
1C
1D
1E
1F
20
3E
3F
Digital Analog LEVEL
Atten. Atten.
0 dB
0 dB
0 dB
0 dB
0 dB
0 dB
0 dB
0 dB
res
res
0 dB
0 dB
0 dB
0 dB
0 dB
0 dB
0 dB
0 dB
-6 dB
-6 dB
-6 dB
-6 dB
-12 dB
-12 dB
-12 dB
-12 dB
-18dB
-60 dB
-60 dB
12.0 dB
10.5 dB
9.0 dB
7.5 dB
6.0 dB
4.5 dB
3.0 dB
1.5 dB
res
res
0.0 dB
-1.5 dB
-3.0 dB
-4.5 dB
-6.0 dB
-7.5 dB
-9.0 dB
-34.5 dB
-30.0 dB
-31.5 dB
-33.0 dB
-34.5 dB
-30.0 dB
-31.5 dB
-33.0 dB
-34.5 dB
-30.0 dB
-33.0 dB
-34.5 dB
12.0 dB
10.5 dB
9.0 dB
7.5 dB
6.0 dB
4.5 dB
3.0 dB
1.5 dB
res
res
0.0 dB
-1.5 dB
-3.0 dB
-4.5 dB
-6.0 dB
-7.5 dB
-9.0 dB
-34.5 dB
-36.0 dB
-37.5 dB
-39.0 dB
-40.5 dB
-42.0 dB
-43.5 dB
-45.0 dB
-46.5 dB
-48.0 dB
-93.0 dB
-94.5 dB
Table 12. Master Digital Gain
0
1
2
3
11
12
13
14
15
28
29
30
31
MG4
MG3
MG2
MG1
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
0
0
1
1
0
0
1
1
MG0 LEVEL
0
1
0
1
1
0
1
0
1
0
1
0
1
22.5 dB
21.0 dB
19.5 dB
18.0 dB
6.0 dB
4.5 dB
3.0 dB
1.5 dB
0 dB
-19.5 dB
-21.0 dB
-22.5 dB
-24.0 dB
Decimal
Value
Sample Rate
Divider
0
1
2
3
4
5
6
7
8
21
22
23
24
25
26
189
190
191
192
255
50.40 KHz
48.00 KHz
32.00 KHz
27.42 KHz
16.00 KHz
9.600 KHz
8.000 KHz
6.620 KHz
50.40 KHz
50.40 KHz
48.10 KHz
46.01 KHz
44.10 KHz
42.36 KHz
40.70KHz
5600 KHz
5570.5 KHz
5541.4 KHz
5512.5 KHz
5512.5 KHz
16 X 21
353
529
617
1058
1764
2117
2558
16 X 21
16 X 21
16 X 22
16 X 23
16 X 24
16 X 25
16 X 26
16 X 189
16 X 190
16 X 191
16 X 192
16 X 192
Table 14. A/D Sample Rate (SRAD7-SRAD0)
Decimal
Value
0
1
2
3
4
5
6
7
8
21
22
23
24
25
26
27
28
255
Sample Rate
50.40
48.00
32.00
27.42
16.00
9.600
8.000
6.620
50.40
50.40
48.10
46.01
44.10
42.36
40.70
39.20
37.80
4.150
KHz
KHz
KHz
KHz
KHz
KHz
KHz
KHz
KHz
KHz
KHz
KHz
KHz
KHz
KHz
KHz
KHz
KHz
Divider
16 X 21
353
529
617
1058
1764
2117
2558
16 X 21
16 X 21
16 X 22
16 X 23
16 X 24
16 X 25
16 X 26
16 X 27
16 X 28
16 X 255
Table 15. D/A Sample Rate (SRDA7-SRDA0)
Table 13. Microphone Gain
32
DS213PP4
CS4237B
During initialization and software power down
(PM1,0 = 01), this register CANNOT be written
and always reads 10000000 (80h)
Index Address Register
(WSSbase+0, R0)
D7
D6
D5
D4
D3
D2
D1
D0
INIT
MCE
TRD
IA4
IA3
IA2
IA1
IA0
IA3-IA0
IA4
TRD
Index Address: These bits define the
address of the indirect register accessed by the Indexed Data register
(R1). These bits are read/write.
Allows access to indirect registers 16
- 31. In MODE 1, this bit is reserved and must be written as zero.
Transfer Request Disable: This bit,
when set, causes DMA transfers to
cease when the INT bit of the Status
Register (R2) is set. Independent for
playback and capture interrupts.
0 - Transfers Enabled (playback and
capture DRQs occur uninhibited)
1 - Transfers Disabled (playback and
capture DRQ only occur if INT bit
is 0)
MCE
INIT
D7
D6
D5
D4
D3
D2
D1
D0
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
ID7-ID0
WSS Codec Initialization: This bit is
read as 1 when the Codec is in a
state in which it cannot respond to
parallel interface cycles. This bit is
read-only.
Indexed Data register: These bits are
the indirect register referenced by
the Indexed Address register (R0).
During initialization and software power down
of the WSS Codec, this register can NOT be
written and is always read 10000000 (80h)
Status Register
(WSSbase+2, R2, Read Only)
D7
D6
D5
D4
D3
D2
D1
D0
CU/L
CL/R
CRDY
SER
PU/L
PL/R
PRDY
INT
INT
Mode Change Enable: This bit must
be set whenever the current mode
of the WSS Codec is changed. The
Data Format (I8, I28) and Interface
Configuration (I9) registers CANNOT
be changed unless this bit is set.
The exceptions are CEN and PEN
which can be changed "on-the-fly".
The DAC output is muted when
MCE is set.
Immediately after RESET (and once the WSS
Codec has left the INIT state), the state of this
register is: 010x0000 (binary - where ’x’ indicates unknown).
DS213PP4
Indexed Data Register
(WSSbase+1, R1)
Interrupt Status: This indicates the
status of the internal interrupt logic
of the WSS Codec. This bit is
cleared by any write of any value to
this register. The IEN bit of the Pin
Control register (I10) determines
whether the state of this bit is reflected on the IRQ pin assigned to
the WSS Codec.
Read States
0 - Interrupt inactive
1 - Interrupt active
PRDY
Playback Data Ready. The Playback
Data register (R3) is ready for more
data. This bit would be used when direct programmed I/O data transfers
are desired.
0 - Data still valid. Do not overwrite.
1 - Data stale. Ready for next host
data write value.
33
CS4237B
PL/R
Playback Left/Right Sample: This bit
indicates whether data needed is for
the Left channel or Right channel in
all data formats except ADPCM. In
ADPCM it indicates whether the first
two or last two bytes of a 4-byte set
(8 ADPCM samples) are needed.
CL/R
0 - Right or 3/4 ADPCM byte needed
1 - Left, Mono, or 1/2 ADPCM byte
needed
PU/L
Playback Upper/Lower Byte: This bit
indicates whether the playback data
needed is for the upper or lower
byte of the channel. In ADPCM it indicates, along with PL/R, which one
of the four ADPCM bytes is needed.
0 - Lower or 1/3 ADPCM byte needed
1 - Upper, any 8-bit format, or 2/4
ADPCM byte needed.
SER
CRDY
Sample Error: This bit indicates that a
sample was not serviced in time and
an error has occurred. The bit indicates an overrun for capture and
underrun for playback. If both the
capture and playback are enabled,
the source which set this bit can not
be determined. However, the Alternate Feature Status register (I24)
can indicate the exact source of the
error.
Capture Data Ready. The Capture
Data register (R3) contains data
ready for reading by the host. This
bit would be used for direct programmed I/O data transfers.
0 - Data is stale. Do not reread the
information.
1 - Data is fresh. Ready for next
host data read.
34
Capture Left/Right Sample: This bit
indicates whether the capture data
waiting is for the Left channel or
Right channel in all audio data formats except ADPCM. In ADPCM it
indicates whether the first two or last
two bytes of a 4-byte set (8 ADPCM
samples) are waiting.
0 - Right or 3/4 ADPCM byte available
1 - Left, Mono, or 1/2 ADPCM byte
available
CU/L
Capture Upper/Lower Byte: This bit
indicates whether the capture data
ready is for the upper or lower byte
of the channel. In ADPCM it indicates, along with CL/R, which one of
four ADPCM bytes is available.
0 - Lower or 1/3 ADPCM byte
available
1 - Upper, any 8-bit format, or 2/4
ADPCM byte available
Note on PRDY/CRDY: These two bits are designed to be read as one when action is required
by the host. For example, when PRDY is set to
one, the device is ready for more data; or when
the CRDY is set to one, data is available to the
host. The definition of the CRDY and PRDY bits
are therefore consistent in this regard.
I/O DATA REGISTERS
The PIO Data register is two registers mapped to
the same address. Writes to this register sends
data to the Playback Data register. Reads from
this register will receive data from the Capture
Data register.
During initialization and software power down
of the WSS Codec, this register CANNOT be
written and is always read 10000000 (80h)
DS213PP4
CS4237B
Capture I/O Data Register
(WSSbase+3, R3, Read Only)
D7
D6
D5
D4
D3
D2
D1
D0
CD7
CD6
CD5
CD4
CD3
CD2
CD1
CD0
CD7-CD0
Capture Data Port. This is the control
register where capture data is read
during programmed I/O data transfers.
The reading of this register will increment the
state machine so that the following read will be
from the next appropriate byte in the sample.
The exact byte which is next to be read can be
determined by reading the Status register (R2).
Once all relevant bytes have been read, the state
machine will point to the last byte of the sample
until a new sample is received from the ADCs.
Once the Status register (R2) is read and a new
sample is received from the FIFO, the state machine and Status register (R2) will point to the
first byte of the new sample.
INDIRECT MAPPED REGISTERS
These registers are accessed by placing the appropriate index in the Index Address register
(R0) and then accessing the Indexed Data register (R1). A detailed description of each indirect
register is given below. All reserved bits should
be written zero and may be 0 or 1 when read.
Note that indirect registers 16-31 are not available when in MODE 1 (CMS1,0 in MODE and
ID register I12 are both zero).
Left ADC Input Control (I0)
Default = 000x0000
D7
LSS1
D6
D5
LSS0 LMGE
D4
D3
D2
D1
D0
res
LAG3
LAG2
LAG1
LAG0
LAG3-LAG0
Left ADC Gain. The least significant
bit represents +1.5 dB, with
0000 = 0 dB. See Table 7.
res
Reserved. Must write 0. Could read
as 0 or 1.
During initialization and software power down
of the WSS Codec, this register can NOT be
written and is always read 10000000 (80h)
LMGE
This bit has no function in MODE 3.
In MODEs 1 & 2 it controls the
20 dB gain boost for the left MIC input to the ADC.
Playback I/O Data Register
WSSbase+3, R3, Write Only)
LSS1-LSS0
Left output loopback. In MODE 3,
setting these bits to 11 enables the
left output loopback into the input
mixer. Bit combinations of 01, 10,
and 00 disable the loopback.
In MODEs 1 & 2, the input mixer is
used as a multiplexer where these
bits select the left ADC input source.
00 - LLINE
01 - LAUX1
10 - LMIC
11 - Left Output Mixer Loopback
D7
D6
D5
D4
D3
D2
D1
D0
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PD7-PD0
Playback Data Port. This is the control
register where playback data is
written during programmed IO data
transfers.
Writing data to this register will increment the
playback byte tracking state machine so that the
following write will be to the correct byte of the
sample. Once all bytes of a sample have been
written, subsequent byte writes to this port are
ignored. The state machine is reset after the
Status register (R2) is read, and the current sample is sent to the DACs via the FIFOs.
DS213PP4
35
CS4237B
the gain stage, is muted.
In MODEs 1 & 2, this bit is not available and internally forced on (muted).
Right ADC Input Control (I1)
Default = 000x0000
D7
D6
D5
D4
D3
D2
D1
D0
RSS1
RSS0
RMGE
res
RAG3
RAG2
RAG1
RAG0
RAG3-RAG0
res
Right ADC Gain. The least significant
bit represents +1.5 dB, with
0000 = 0 dB. See Table 7.
Reserved. Must write 0. Could read
as 0 or 1.
RMGE
This bit has no function in MODE 3.
In MODEs 1 & 2 it controls the
20 dB gain boost for the right MIC input to the ADCs.
RSS1-RSS0
Right output loopback. In MODE 3
setting these bits to 11 enables the
right output loopback into the input
mixer. Other bit combinations disable the loopback.
In MODEs 1 & 2, the input mixer is
used as a mux. where these bits select the right ADC input source.
00 - RLINE
01 - RAUX1
10 - RMIC
11 - Right Output Mixer Loopback
LX1OM
Left Auxiliary #1 Mute. When set to 1,
the left Auxiliary #1 input, LAUX1, to
the output mixer through the gain
stage, is muted.
LAUX1
(Line In)
+12 to -34.5 dB
D6
D5
D4
D3
D2
D1
D0
LX1IM
36
Left Auxiliary #1 Mute. In MODE 3,
when set, the left Auxiliary #1 input,
LAUX1, to the input mixer through
To Input
Mixer
D7
D6
D5
D4
D3
D2
D1
D0
RX1OM RX1IM RX1BM RX1G4 RX1G3 RX1G2 RX1G1 RX1G0
RX1G4-RX1G0 Right Auxiliary #1, RAUX1, Mix Gain.
The least significant bit represents
1.5 dB, with 01000 = 0 dB.
See Table 10.
RX1BM
Right Auxiliary #1 Bypass Mute. In
MODE 3, when set, the right Auxiliary #1 input, RAUX1, (bypassing
the gain) to the input mixer is muted.
In MODEs 1 & 2, this bit is not available and is internally controlled by
RSS1,0 in I1.
RX1IM
Right Auxiliary #1 Mute. When set to 1,
the right Auxiliary #1 input, RAUX1,
to the input mixer through the gain
stage, is muted.
In MODEs 1 & 2, this bit is not available and internally forced on (muted).
RX1OM
Right Auxiliary #1 Mute. When set to 1,
the right Auxiliary #1 input, RAUX1,
to the output mixer through the gain
stage, is muted.
LX1G4-LX1G0 Left Auxiliary #1, LAUX1, Mix Gain.
The least significant bit represents
1.5 dB, with 01000 = 0 dB.
See Table 10.
Left Auxiliary #1 Bypass Mute. In
MODE 3, when set, the left Auxiliary
#1 input, LAUX1, (bypassing the
gain) to the input mixer, is muted. In
MODEs 1 & 2, this bit is not available and is internally controlled by
LSS1,0 in I0.
LX1IM
Right Auxiliary #1 Volume (I3)
Default = 11101000
LX1OM LX1IM LX1BM LX1G4 LX1G3 LX1G2 LX1G1 LX1G0
LX1BM
To Output
Mixer
LX1BM
Left Auxiliary #1 Volume (I2)
Default = 11101000
D7
LX1G4-G0
LX1OM
RAUX1
(Line In)
RX1G4-G0
+12 to -34.5 dB
RX1OM
To Output
Mixer
RX1IM
To Input
Mixer
RX1BM
DS213PP4
CS4237B
RX2OM
Left Auxiliary #2 Volume (I4)
Default = 11x01000
D7
D6
D5
LX2OM LX2IM res
D4
D3
D2
D1
D0
LX2G4 LX2G3 LX2G2 LX2G1 LX2G0
LX2G4-LX2G0 Left Auxiliary #2, LAUX2, Mix Gain.
The least significant bit represents
1.5 dB, with 01000 = 0 dB.
See Table 10.
Left DAC (PC Wave) Volume (I6)
Default = 10000000
res
Reserved. Must write 0.
LX2IM
Left Auxiliary #2 Mute. In MODE 3,
when set to 1, the left Auxiliary #2 input, LAUX2, to the input mixer
through the gain stage, is muted.
In MODEs 1 & 2, this bit is not available and internally forced on (muted).
LX2OM
Left Auxiliary #2 Mute. When set to 1,
the left Auxiliary #2 input, LAUX2, to
the output mixer through the gain
stage, is muted.
LAUX2
(Line In)
LX2G4-G0
RAUX2
(Line In)
LX2OM
To Output
Mixer
LX2IM
To Input
Mixer
D7
D6
LDOM LDG6
LPM
res
Right Auxiliary #2 Volume (I5)
Default = 11x01000
D6
D5
D4
D3
D2
D1
D0
D5
D4
D3
D2
D1
D0
LDG5
LPA5
LDG4
LPA4
LDG3
LPA3
LDG2
LPA2
LDG1
LPA1
LDG0
LPA0
If both IFM (X4 or Global Config. byte) and WTEN
(C8 or Global Config. byte) are cleared, this register
is the master digital audio volume for the left channel
with the following bit definitions:
LDG6-LDG0
Left DAC Master Volume. The least
significant bit represents 1.5 dB, with
0000000 = 0 dB. The total range is
+12 to -94.5 dB. See Table 12.
LDOM
Left DAC Master Mute. When set, the
left DAC to the output mixer is
muted.
+12 to -34.5 dB
D7
Right Auxiliary #2 Mute. When set to
1, the right Auxiliary #2 input,
RAUX2, to the output mixer through
the gain stage, is muted.
To Output
Mixer
RX2OM
RX2G4-G0
To Input
Mixer
RX2IM
+12 to -34.5 dB
If IFM or WTEN is set, this register controls the left
channel volume for data coming from the ISA bus
only (and X14 is the left channel digital audio master
volume) with the following bit descriptions.
RX2OM RX2IM res RX2G4 RX2G3 RX2G2 RX2G1 RX2G0
RX2G4-RX2G0 Right Auxiliary #2, RAUX2, Mix Gain.
The least significant bit represents
1.5 dB, with 01000 = 0 dB.
See Table 10.
res
Reserved. Must write 0. Could read
as 0 or 1.
RX2IM
Right Auxiliary #2 Mute. In MODE 3,
when set, the right Auxiliary #2 input, RAUX2, to the input mixer
through the gain stage, is muted.
In MODEs 1 & 2, this bit is not available and internally forced on (muted).
DS213PP4
LPA5-LPA0
Left PC Wave Attenuation. The least
significant bit represents -1.5 dB,
with 000000 = 0 dB. The total range
is 0 to -94.5 dB. See Table 6.
res
Reserved. Must write 0. Could read
as 0 or 1.
LPM
Left PC Wave Mute. When set, the
left PCM input to the digital mixer
summer will be muted.
37
CS4237B
See Table below.
Right DAC (PC Wave) Volume (I7)
Default = 10000000
D7
D6
D5
RDOM RDG6 RDG5
RPM res
RPA5
CFS2-CFS0
D4
D3
D2
D1
D0
RDG4
RPA4
RDG3
RPA3
RDG2
RPA2
RDG1
RPA1
RDG0
RPA0
If both IFM (X4 or Global Config. byte) and WTEN
(C8 or Global Config. byte) are cleared, this register
is the master digital audio volume for the right channel with the following bit definitions:
RDG6-RDG0
Right DAC Master Volume. The least
significant bit represents 1.5 dB, with
0000000 = 0 dB. The total range is
+12 to -94.5 dB. See Table 12.
RDOM
Right DAC Master Mute. When set,
the right DAC to the output mixer is
muted.
If IFM or WTEN is set, this register controls the right
channel volume for data coming from the ISA bus
only (and X15 is the right channel digital audio master volume) with the following bit descriptions.
RPA5-RPA0
Right PC Wave Attenuation. The least
significant bit represents -1.5 dB,
with 000000 = 0 dB. The total range
is 0 to -94.5 dB. See Table 6.
res
Reserved. Must write 0. Could read
as 0 or 1.
RPM
Right PC Wave Mute. When set, the
right PCM input to the digital mixer
summer will be muted.
Fs and Playback Data Format (I8)
Default = 00000000
D7
D6
D5
D4
D3
D2
D1
D0
FMT1
FMT0
C/L
S/M
CFS2
CFS1
CFS0
C2SL
C2SL
38
DIVIDE
0 - 3072
1 - 1536
2 - 896
3 - 768
4 - 448
5 - 384
6 - 512
7 - 2560
S/M
Clock Frequency Divide Select: These
bits select the audio sample frequency for both capture and
playback. The actual audio sample
frequency depends on which clock
base (C2SL) is selected. Note that
these bits can be disabled by setting
SRE in I22 or IFSE in X11.
CAUTION: CFS2-CFS0 can only be
changed while MCE (R0) is set.
C2SL = 0
8.0 kHz
16.0 kHz
27.42 kHz
32.0 kHz
N/A
N/A
48.0 kHz
9.6 kHz
C2SL = 1
5.51 kHz
11.025 kHz
18.9 kHz
22.05 kHz
37.8 kHz
44.1 kHz
33.075 kHz
6.62 kHz
Stereo/Mono Select: This bit determines how the audio data streams
are formatted. Selecting stereo will
result in alternating samples representing left and right audio channels.
Mono playback plays the same
audio sample on both channels.
Mono capture only captures data
from the left channel. In MODE 1,
this bit is used for both playback and
capture. In MODEs 2 and 3, this bit
is only used for playback, and the
capture format is independently selected via I28. MCE (R0) or PMCE
(I16) must be set to modify S/M.
See Changing Audio Data Formats
section for more details.
Clock 2 Source Select: This bit selects
the clock base used for the audio
sample rates for both capture and
playback. Note that this bit can be
disabled by setting SRE in I22 or by
setting IFSE in X11.
CAUTION: C2SL can only be
changed while MCE (R0) is set.
DS213PP4
CS4237B
0 - Mono
1 - Stereo
CEN
C/L, FMT1, and FMT0 bits set the audio data format
as shown below. In MODE 1, FMT1,
which is forced low, FMT0, and C/L
are used for both playback and capture. In MODEs 2 and 3, these bits
are only used for playback, and the
capture format is independently selected via register I28. MCE (R0) or
PMCE (I16) must be set to modify
the upper four bits of this register.
See Changing Audio Data Formats
section for more details.
FMT1† FMT0 C/L
D7
D6
D5
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
0 - Capture Disabled (capture DRQ
and PIO inactive)
1 - Capture Enabled
SDC
Audio Data Format
Linear, 8-bit unsigned
µ-Law, 8-bit companded
Linear, 16-bit two’s
complement, Little Endian
A-Law, 8-bit companded
RESERVED
ADPCM, 4-bit, IMA compatible
Linear, 16-bit two’s
complement, Big Endian
RESERVED
CAL1,0
Interface Configuration (I9)
Default = 00x01000
D7
D6
D5
D4
D3
D2
D1
D0
PPIO
res
CAL1
CAL0
SDC
CEN
PEN
PEN
Playback Enable. This bit enables
playback. The WSS Codec will
generate a DRQ and respond to
DACK signal when this bit is enabled and PPIO=0. If PPIO=1, PEN
enables PIO playback mode. PEN
may be set and reset without setting
the MCE bit.
0 - Playback Disabled (playback DRQ
and PIO inactive)
1 - Playback Enabled
DS213PP4
Single DMA Channel: This bit will force
BOTH capture and playback DMA requests to occur on the Playback
DMA channel. This bit forces the
WSS Codec to use one DMA channel. Should both capture and
playback be enabled in this mode,
only the playback will occur. See the
DMA Interface section for further explanation.
0 - Dual DMA channel mode
1 - Single DMA channel mode
† FMT1 is not available in MODE 1 (forced to 0).
CPIO
Capture Enabled. This bit enables the
capture of data. The WSS Codec
will generate a DRQ and respond to
DACK signal when CEN is enabled
and CPIO=0. If CPIO=1, CEN enables PIO capture mode. CEN may
be set and reset without setting the
MCE bit.
Calibration: These bits determine
which type of calibration the WSS
Codec performs whenever the Mode
Change Enable (MCE) bit, R0,
changes from 1 to 0. The number of
sample periods required for calibration is listed in parenthesis.
0
1
2
3
PPIO
-
No calibration (0)
Converter calibration (321)
DAC calibration (120)
Full calibration (450)
Playback PIO Enable: This bit determines whether the playback data is
transferred via DMA or PIO.
0 - DMA transfers
1 - PIO transfers
CPIO
Capture PIO Enable: This bit determines whether the capture data is
transferred via DMA or PIO.
0 - DMA transfers
1 - PIO transfers
39
CS4237B
00 - 12kHz < Fs ≤ 24kHz
01 - Fs > 24kHz
10 - Fs ≤ 12kHz
11 - reserved
Caution: This register, except bits CEN and
PEN, can only be written while in Mode Change
Enable (either MCE or PMCE). See the Changing Sampling Rate section for more details.
Pin Control (I10)
Default = 0000000x
D7
D6
D5
D4
D3
D2
D1
D0
XCTL1
XCTL0
OSM1
OSM0
DEN
DTM
IEN
res
res
Reserved. Must write 0. Could read
as 0 or 1.
IEN
Interrupt Enable: This bit enables the
interrupt pin. The Interrupt pin will reflect the value of the INT bit of the
Status register (R2). The interrupt
pin is active high.
0 - Interrupt disabled
1 - Interrupt enabled
DTM
DEN
DMA Timing Mode. MODE 2 & 3 only.
When set, causes the current DMA
request signal to be deasserted on
the rising edge of the IOW or IOR
strobe during the next to last byte of
a DMA transfer. When DTM = 0 the
DMA request is released on the falling edge of the IOW or IOR during
the last byte of a DMA transfer.
XCTL1-XCTL0 XCTL Control: These bits are reflected
on the XCTL1,0 pins of the part.
NOTE: These pins are multiplexed
with other functions; therefore, they
may not be available on a particular
design.
0 - TTL logic low on XCTL1,0 pins
1 - TTL logic high on XCTL1,0 pins
Error Status and Initialization (I11, Read Only)
Default = 00000000
D7
D6
D5
D4
COR
PUR
ACI
DRS
ORL1-ORL0
ORR1-ORR0
Dither Enable: When set, triangular
pdf dither is added before truncating
the ADC 16-bit value to 8-bit, unsigned data. Dither is only active in
the 8-bit unsigned data mode.
40
These bits are enabled by setting
SRE = 1 in I22. These bits in combination with DIV5-DIV0 and CS2
(I22) determine the current sample
rate of the WSS Codec when
SRE = 1. Note that these bits can
be disabled by setting IFSE in X11.
D2
D1
D0
ORL1
ORL0
Overrange Left Detect: These bits
determine the overrange on the left
ADC channel. These bits are updated on a sample by sample basis.
0 - Less than -1.5 dB
1 - Between -1.5 dB and 0 dB
2 - Between 0 dB and 1.5 dB
overrange
3 - Greater than 1.5 dB overrange
Overrange Right Detect: These bits
determine the overrange on the
Right ADC channel.
0 - Less than -1.5 dB
1 - Between -1.5 dB and 0 dB
2 - Between 0 dB and 1.5 dB
overrange
3 - Greater than 1.5 dB overrange
0 - Dither enabled
1 - Dither disabled
OSM1-OSM0
D3
ORR1 ORR0
DRS
DRQ Status: This bit indicates the
current status of the DRQs assigned
to the WSS Codec.
0 - Capture AND Playback DRQs are
presently inactive
1 - Capture OR Playback DRQs are
presently active
DS213PP4
CS4237B
ACI
Auto-calibrate In-Progress: This bit
indicates the state of calibration.
00 - MODE 1
01 - Reserved
10 - MODE 2
11 - MODE 3
0 - Calibration not in progress
1 - Calibration is in progress
PUR
Playback underrun: This bit is set
when playback data has not arrived
from the host in time to be played.
As a result, if DACZ = 0, the last
valid sample will be sent to the
DACs. This bit is set when an error
occurs and will not clear until the
Status register (R2) is read.
COR
Capture overrun: This bit is set when
the capture data has not been read
by the host before the next sample
arrives. The old sample will not be
overwritten and the new sample will
be ignored. This bit is set when an
error condition occurs and will not
clear until the Status register (R2) is
read.
The SER bit in the Status register (R2) is simply
a logical OR of the COR and PUR bits. This
enables a polling host CPU to detect an error
condition while checking other status bits.
Monitor Loopback Volume (I13)
Default = 000000x0
D7
D6
D5
D4
D3
D2
D1
D0
LBA5
LBA4
LBA3
LBA2
LBA1
LBA0
res
LBE
LBE
Loopback Enable: When set to 1, the
ADC data is digitally mixed with data
sent to the DACs. This bit controls
the loopback enable for both channels regardless of how SLBE in X10
is set.
0 - Loopback disabled
1 - Loopback enabled
res
Reserved. Must write 0. Could read
as 0 or 1.
LBA5-LBA0
Loopback Attenuation: These bits
determine the attenuation of the loopback from ADC to DAC. The least
significant bit represents -1.5 dB,
with 000000 = 0 dB. See Table 6.
MODE and ID (I12)
Default = 100x1010
D7
D6
D5
D4
D3
D2
D1
D0
1
CMS1
CMS0
res
ID3
ID2
ID1
ID0
ID3-ID0
Codec ID: These four bits indicate the
ID and initial revisions of the codec.
Further revisions are expanded in indirect register I25 through the
CS4236 and C1 for newer chips.
These bits are read only.
0001 - Rev B CS4248/CS4231
1010 - All other revisions and parts.
See Registers X25 or C1.
res
Reserved. Must write 0. Could read
as 0 or 1.
CMS1,0
Codec Mode Select bits: Enables the
Extended registers and functions of
the part.
DS213PP4
LBA5-LBA0 control left and right
channels when SLBE in X10 is
clear. When SLBE = 1, these bits
only control the left channel and
RLBA5- RLBA0 in X10 control the
right.
Playback Upper Base (I14)
Default = 00000000
D7
D6
D5
D4
D3
D2
D1
D0
PUB7
PUB6
PUB5
PUB4
PUB3
PUB2
PUB1
PUB0
PUB7-PUB0
Playback Upper Base: This register is
the upper byte which represents the
8 most significant bits of the 16-bit
Playback Base register. Reads from
this register return the same value
41
CS4237B
which was written. The Current
Count registers cannot be read.
When set for MODE 1 or SDC, this
register is used for both the Playback and Capture Base registers.
1 - 64-bit. Figure 10.
2 - 32-bit. Figure 11.
3 - ADC/DAC. Figure 12.
PMCE
Playback Mode Change Enable.
When set, it allows modification of
the stereo/mono and audio data format bits (D7-D4) for the playback
channel, I8. MCE in R0 must be
used to change the sample frequency.
CMCE
Capture Mode Change Enable.
When set, it allows modification of
the stereo/mono and audio data format bits (D7-D4) for the capture
channel, I28. MCE in R0 must be
used to change the sample frequency in I8.
TE
Timer Enable: This bit, when set, will
enable the timer to run and interrupt
the host at the specified frequency
in the timer registers.
OLB
Output Level Bit: Provided for backwards compatibility with the CS4236.
This bit does nothing on this chip.
Playback Lower Base (I15)
Default = 00000000
D7
D6
D5
D4
D3
D2
D1
D0
PLB7
PLB6
PLB5
PLB4
PLB3
PLB2
PLB1
PLB0
PLB7-PLB0
Lower Base Bits: This register is the
lower byte which represents the 8
least significant bits of the 16-bit
Playback Base register. Reads from
this register return the same value
which was written. When set for
MODE 1 or SDC, this register is
used for both the Playback and Capture Base registers.
Alternate Feature Enable I (I16)
Default = 00000000
D7
D6
OLB
TE
DACZ
D5
D4
CMCE PMCE
D3
D2
D1
D0
SF1
SF0
SPE
DACZ
DAC Zero: This bit will force the output of the playback channel to AC
zero when an underrun error occurs
1 - Go to center scale
0 - Hold previous valid sample
SPE
DSP Serial Port Enable. When
set, audio data from the ADCs is
sent out SDOUT and audio data
from SDIN is sent to the DACs.
MCE in R0 must be set to change
this bit.
1 - Enable serial port
0 - Disable serial port. ISA Bus
used for audio data.
SF1,SF0
Serial Format. Selects the format of
the serial port when enabled by
SPE. MCE in R0 must be set to
change these bits.
Alternate Feature Enable II (I17)
Default = 0000x000
D7
D6
D5
D4
D3
D2
D1
D0
TEST
TEST
TEST
TEST
APAR
res
XTALE
HPF
HPF
High Pass Filter: This bit enables a
DC-blocking high-pass filter in the
digital filter of the ADC. This filter
forces the ADC offset to 0.
0 - disabled
1 - enabled
XTALE
Crystal Enable. Provided for backwards compatibility with the
CS4231A. This bit does nothing on
the this part.
res
Reserved. Must write 0. Could read
as 0 or 1.
0 - 64-bit enhanced. Figure 9.
42
DS213PP4
CS4237B
APAR
ADPCM Playback Accumulator Reset.
While set, the Playback ADPCM
accumulator is held at zero. Used
when pausing a playback stream.
TEST
Factory Test. These bits are used for
factory testing and must remain at 0
for normal operation.
the input mixer is muted.
In MODEs 1 & 2, this bit is not available and internally forced on (muted).
LLOM
Left Line (Synthesizer) Volume (I18)
Default = xxxxxxxx
D7
D6
D5
D4
D3
D2
D1
D0
LLOM
LR7
LLIM
LR6
LLBM
LR5
LLG4
LR4
LLG3
LR3
LLG2
LR2
LLG1
LR1
LLG0
LR0
This register controls either the left LINE input or is
remapped to control the internal FM (X6) or external
CS9236 Wavetable synthesizer (X16), or both. When
no remapping occurs, the bit definitions are:
LLG4-LLG0
LLBM
LLIM
Left LINE Output Mute.
When set to 1, the Left Line Input,
LLINE, from the volume control to
the output mixer is muted.
When IFM=1 (X4 or Global Config. byte) and
FMRM=1 (X4), FM remapping is enabled. When
WTEN=1 (C8 or Global Config. byte) and
WTRMD=0 (X4), Wavetable remapping is enabled. If
either synthesizer remap is enabled, left LINE analog volume is controlled through X0. With remapping
the bit definitions are:
LR7-LR0
When IFM=1 and FMRM=1, writes
to I18 will write the Internal FM register X6.
Left LINE Volume. This register is
used to control the LLINE analog input volume to the mixers. The least
significant bit represents 1.5 dB, with
01000 = 0 dB. See Table 10.
Left LINE Bypass Mute. In MODE 3,
when set to 1, the analog Left Line
Input, LLINE, (bypassing the gain
block) to the input mixer is muted.
In MODEs 1 & 2, this bit is not available and is internally controlled by
LSS1,0 in I0.
Left LINE Input Mute. In MODE 3,
when set to 1, the Left Line Input,
LLINE, from the volume control to
When WTEN=1 and WTRMD=0,
writes to I18 will write the Wavetable
synthesis register X16.
Right Line (Synthesizer) Volume (I19)
Default = xxxxxxxx
D7
D6
RLOM RLIM
RR7 RR6
LLINE
(Synthesis)
LLG4-G0
To Output
Mixer
LLIM
To Input
Mixer
D5
D4
D3
D2
D1
D0
RLBM
RR5
RLG4
RR4
RLG3
RR3
RLG2
RR2
RLG1
RR1
RLG0
RR0
This register controls either the right LINE input or is
remapped to control the internal FM (X7) or external
CS9236 Wavetable synthesizer (X17), or both. When
no remapping occurs, the bit definitions are:
RLG4-RLG0
LLOM
Left Remapped Register.
Right LINE Volume. This register is
used to control the RLINE analog input volume to the mixers. The least
significant bit represents 1.5 dB, with
01000 = 0 dB. See Table 10.
+12 to -34.5 dB
LLBM
DS213PP4
43
CS4237B
RLBM
Right LINE Bypass Mute. In MODE 3,
when set to 1, the analog Right Line
Input, RLINE, (bypassing the gain
block) to the input mixer is muted.
In MODEs 1 & 2, this bit is not available and is internally controlled by
RSS1,0 in I1.
RLIM
Right LINE Input Mute. In MODE 3,
when set to 1, the Right Line Input,
RLINE, from the volume control to
RLINE
(Synthesis)
To Output
Mixer
RLOM
RLG4-G0
To Input
Mixer
RLIM
into the internal timer; therefore, the
upper timer register should be
loaded before the lower. Once the
count reaches zero, an interrupt is
generated, if enabled, and the timer
is automatically reloaded with these
base registers.
Timer Upper Base (I21)
Default = 00000000
D7
D6
D5
D4
D3
D2
D1
D0
TU7
TU6
TU5
TU4
TU3
TU2
TU1
TU0
TU7-TU0
+12 to -34.5 dB
RLBM
the input mixer is muted.
In MODEs 1 & 2, this bit is not available and internally forced on (muted).
RLOM
Right LINE Output Mute.
When set to 1, the Right Line Input,
RLINE, from the volume control to
the output mixer is muted.
When IFM=1 and FMRM=1, FM remapping is enabled. When WTEN=1 and WTRMD=0, Wavetable
remapping is enabled. If either synthesizer remap is
enabled, right LINE analog volume is controlled
through X1. With remapping the bit definitions are:
RR7-RR0
C2SL = 0 - 24.576MHz / 245
(9.969 µs)
C2SL = 1 - 16.9344MHz / 168
(9.92 µs)
Alternate Sample Frequency Select (I22)
Default = 00000000
D7
D6
D5
D4
D3
D2
D1
D0
SRE
DIV5
DIV4
DIV3
DIV2
DIV1
DIV0
CS2
CS2
Right Remapped Register.
When IFM=1 and FMRM=1, writes
to I19 will write the Internal FM register X7.
When WTEN=1 and WTRMD=0,
writes to I19 will write the Wavetable
synthesis register X17.
D7
D6
D5
D4
D3
D2
D1
D0
TL7
TL6
TL5
TL4
TL3
TL2
TL1
TL0
TL7-TL0
44
Clock 2 Base Select. This bit selects
the base clock frequency used for
generating the audio sample rate.
Note that the part uses only one
crystal to generate both clock base
frequencies. This bit can be disabled
by setting IFSE in X11.
0 - 24.576 MHz base
1 - 16.9344 MHz base
DIV5 - DIV0
Timer Lower Base (I20)
Default = 00000000
Upper Timer Bits: This is the high
order byte of the 16-bit timer. The
time base is determined by the frequency base selected from either
C2SL in I8 or CS2 in I22.
Clock Divider. These bits select the
audio sample frequency for both capture and playback. These bits can
be overridden by IFSE in X11.
Fs = (2*XT)/(M*N)
Lower Timer Bits: This is the low order
byte of the 16-bit timer base register.
Writes to this register cause both
timer base registers to be loaded
DS213PP4
CS4237B
XT = 24.576 MHz
CS2 = 0
XT = 16.9344 MHz CS2 = 1
XA3-XA0
Extended Register Address. Along
with XA4, sets the register number
(X0-X17+X25) accessed when
XRAE is set. MODE 3 only. See the
WSS Extended Register section for
more details.
N = DIV5-DIV0
16 ≤ N ≤ 49 for XT = 24.576 MHz
12 ≤ N ≤ 33 for XT = 16.9344 MHz
(M set by OSM1,0 in I10)
M = 64 for Fs > 24 kHz
M = 128 for 12 kHz < Fs ≤ 24 kHz
M = 256 for Fs ≤ 12 kHz
SRE
Alternate Sample Rate Enable. When
this bit is set to a one, bits 0-3 of I8
will be ignored, and the sample frequency is then determined by CS2,
DIV5-DIV0, and the oversampling
mode bits OSM1, OSM0 in I10. Note
that this register can be overridden
(disabled) by IFSE in X11.
Extended Register Access (I23)
Default = 00000xx0
D7
D6
D5
D4
D3
D2
D1
D0
XA3
XA2
XA1
XA0
XRAE
XA4
res
ACF
ACF
ADPCM Capture Freeze. When set,
the capture ADPCM accumulator
and step size are frozen. This bit
must be set to zero for adaptation to
continue. This bit is used when
pausing a ADPCM capture stream.
res
Reserved. Must write 0. Could read
as 0 or 1.
XA4
Extended Register Address bit 4.
Along with XA3-XA0, enables access to extended registers X16,
X17, and X25. MODE 3 only.
XRAE
Extended Register Access Enable.
Setting this bit converts this register
from the extended address register
to the extended data register. To convert back to an address register, R0
must be written. MODE 3 only.
DS213PP4
Alternate Feature Status (I24)
Default = x0000000
D7
D6
D5
D4
D3
D2
D1
D0
res
TI
CI
PI
CU
CO
PO
PU
PU
Playback Underrun: When set,
indicates the DAC has run out of
data and a sample has been missed.
PO
Playback Overrun: When set,
indicates that the host attempted to
write data into a full FIFO and the
data was discarded.
CO
Capture Overrun: When set,
indicates that the ADC had a sample
to load into the FIFO but the FIFO
was full. In this case, this bit is set
and the new sample is discarded.
CU
Capture Underrun: Indicates the host
has read more data out of the FIFO
than it contained. In this condition,
the bit is set and the last valid byte
is read by the host.
PI
Playback Interrupt: Indicates an
interrupt is pending from the playback DMA count registers.
CI
Capture Interrupt: Indicates an
interrupt is pending from the capture
DMA count registers.
TI
Timer Interrupt: Indicates an interrupt
is pending from the timer registers
45
CS4237B
res
summed into the mixer. MIA0 is the
least significant bit and represents
3 dB attenuation, with 0000 = 0 dB.
See Table 7.
Reserved. Must write 0. Could read
as 0 or 1.
The PI, CI, and TI bits are reset by writing a "0"
to the particular interrupt bit or by writing any
value to the Status register (R2).
Compatibility ID (I25)
Default = 00000011
D7
D6
D5
D4
D3
D2
D1
D0
V2
V1
V0
CID4
CID3
CID2
CID1
CID0
CID4-CID0
All Chips:
V2-V0
Chip Identification. Distinguishes
between this chip and previous
codec chips that support this register
set. This register is fixed to indicate
code compatibility with the CS4236.
X25 or C1 should be used to further
differentiate between parts that are
compatible with the CS4236.
res
Reserved. Must write 0. Could read
as 0 or 1.
MBY
Mono Bypass. MBY connects MIN
directly to MOUT with an attenuation
of 9 dB. When MBY = 1, MIM
should be set to 1.
0 - MIN not connected directly to
MOUT.
1 - MIN connected directly to MOUT.
MOM
00011 - CS4236, CS4237B
00010 - CS4232/CS4232A
00000 - CS4231/CS4231A
Mono Output Mute. In MODE 3, MOM
will mute the left Line Out to the
mono mix output, MOUT. The right
Line Out mute, MOMR, is in X5. In
MODE 2, MOM mutes left and right
Line Out to MOUT. This mute is independent of the line output mute.
0 - no mute
1 - mute
Version number. As enhancements
are made to the part, the version
number is changed so software can
distinguish between the different versions.
000 - Compatible with the CS4236
MIM
Mono Input Mute. In MODE 3, MIM
mutes the MIN analog input to the
left output mixer channel. MIMR in
X4 mutes MIN analog input to the
right output mixer channel. In
MODE 2, MIM mutes both left and
These bits are fixed for compatibility
with the CS4236. Register X25 or
C1 may be used to differentiate between the CS4236 and newer chips.
Mono Input and Output Control (I26)
Default = 101x0000
D7
D6
D5
D4
D3
D2
D1
D0
MIM
MOM
MBY
res
MIA3
MIA2
MIA1
MIA0
MIA3-MIA0
46
Mono Input Attenuation. When MIM
is 0, these bits set the level of MIN
DS213PP4
CS4237B
right channels. The mono input provides mix for the "beeper" function in
most personal computers.
sample frequency must be the same
and is set in I8. MCE (R0) or CMCE
(I16) must be set to modify this register. See Changing Audio Data
Formats section for more details.
0 - no mute
1 - muted
Reserved (I29)
Default = xxxxxxxx
Reserved (I27)
Default = xxxxxxxx
D7
D6
D5
D4
D3
D2
D1
D0
res
res
res
res
res
res
res
res
D7
D6
D5
D4
D3
D2
D1
D0
res
res
res
res
res
res
res
res
res
res
Reserved. Must write 0. Could read
as 0 or 1.
Reserved. Must write 0. Could read
as 0 or 1.
Capture Upper Base (I30)
Default = 00000000
Capture Data Format (I28)
Default = 0000xxxx
D7
D6
D5
D4
D3
D2
D1
D0
FMT1
FMT0
C/L
S/M
res
res
res
res
D7
D6
D5
D4
D3
D2
D1
D0
CUB7
CUB6
CUB5
CUB4
CUB3
CUB2
CUB1
CUB0
CUB7-CUB0
res
Reserved. Must write 0. Could read
as 0 or 1.
S/M
Stereo/Mono Select: This bit determines how the capture audio data
stream is formatted. Selecting stereo
will result with alternating samples
representing left and right audio
channels. Selecting mono only captures data from the left audio
channel. MCE (R0) or CMCE (I16)
must be set to modify S/M. See
Changing Audio Data Formats section for more details.
0 - Mono
1 - Stereo
C/L, FMT1, FMT0 set the capture data format in
MODEs 2 and 3. See Table 11 or
register I8 for the bit settings and
data formats. The capture data format can be different than the
playback data format; however, the
DS213PP4
Capture Upper Base: This register is
the upper byte which represents the
8 most significant bits of the 16-bit
Capture Base register. Reads from
this this register returns the same
value that was written.
Capture Lower Base (I31)
Default = 00000000
D7
D6
D5
D4
D3
D2
D1
D0
CLB7
CLB6
CLB5
CLB4
CLB3
CLB2
CLB1
CLB0
CLB7-CLB0
Lower Base Bits: This register is the
lower byte which represents the 8
least significant bits of the 16-bit
Capture Base register. Reads from
this register returns the same value
which was written.
47
CS4237B
WSS EXTENDED REGISTERS
The Windows Sound System codec contains
three sets of registers: R0-R3, I0-I31, and X0X25. R0-R3 are directly mapped to the ISA bus
through WSSbase+0 through WSSbase+3 respectively. R0 and R1 provide access to the
indirect registers I0-I31. The third set of registers
are extended registers X0-X25 that are indirectly
mapped through the WSS register I23. I23 acts
as both the extended address and extended data
register. These extended registers are only available when in MODE 3.
Accessing the X registers requires writing the
register address to I23 with XRAE set. When
XRAE is set, I23 changes from an address register to a data register. Subsequent accesses to I23
access the extended data register. To convert I23
back to the extended address register, R0 must
be written which internally clears XRAE. Assuming the part is in MODE 3, the following
steps access the X registers:
1. Write 17h to R0 (to access I23).
R1 is now the extended address register.
2. Write the desired X register address to R1
with XRAE = 1.
R1 is now the extended data register.
3. Write/Read X register data from R1.
To read/write a different X register:
4. Write 17h to R0 again. (resets XRAE)
R1 is now the extended address register.
5. Write the new X register address to R1
with XRAE = 1.
R1 is now the new extended data register.
6. Read/Write new X register data from R1.
48
Address
WSSbase+0
WSSbase+1
Reg.
R0
R1
I23
Register Name
Reset Address
Address/Data access
Indexed Address/Data
Extended Register Access (I23)
D7
D6
D5
D4
D3
D2
D1
D0
XA3
XA2
XA1
XA0
XRAE
XA4
res
ACF
Table 16. WSS Extended Register Control
Index
X0
X1
X2
X3
X4
X5
X6
X7
X8
X9
X10
X11
X12
X13
X14
X15
X16
X17
X18-X24
X25
Register Name
Left LINE Alternate Volume
Right LINE Alternate Volume
Left MIC Volume
Right MIC Volume
Synthesis and Input Mixer Control
Right Input Mixer Control
Left FM Synthesis Volume
Right FM Synthesis Volume
Left DSP Serial Port Volume
Right DSP Serial Port Volume
Right Loopback Monitor Volume
DAC Mute and IFSE Enable
Independent ADC Sample Freq.
Independent DAC Sample Freq.
Left Master Digital Audio Volume
Right Master Digital Audio Volume
Left Wavetable Serial Port Volume
Right Wavetable Serial Port Volume
Reserved
Chip Version and ID
Table 17. WSS Extended Registers
DS213PP4
CS4237B
Control Registers for the Extended Registers
ADDRESS
WSSbase+0 R0
WSSbase+1 R1
D7
D6
D5
D4
D3
D2
D1
D0
INIT
MCE
TRD
IA4
IA3
IA2
IA1
IA0
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
I23
XA3
XA2
XA1
XA0
XRAE
XA4
-
ACF
Extended Registers: (X0-X17, X25)
XA4 - XA0
X0
X1
X2
X3
X4
X5
X6
X7
X8
X9
X10
X11
X12
X13
X14
X15
X16
X17
X25
D7
D6
D5
D4
D3
D2
D1
D0
LLAOM
LLAIM
LLABM
LLAG4
LLAG3
LLAG2
LLAG1
LLAG0
RLAOM
RLAIM
RLABM
RLAG4
RLAG3
RLAG2
RLAG1
RLAG0
LMIM
LMOM
LMBST
LMG4
LMG3
LMG2
LMG1
LMG0
RMIM
RMOM
RMBST
RMG4
RMG3
RMG2
RMG1
RMG0
MIMR
LIS1
LIS0
IFM
WTRMD
FMRM
-
-
MOMR
RIS1
RIS0
-
-
-
-
-
LFMM
-
LFMA5
LFMA4
LFMA3
LFMA2
LFMA1
LFMA0
RFMM
-
RFMA5
RFMA4
RFMA3
RFMA2
RFMA1
RFMA0
LSPM
-
LSPA5
LSPA4
LSPA3
LSPA2
LSPA1
LSPA0
RSPM
-
RSPA5
RSPA4
RSPA3
RSPA2
RSPA1
RSPA0
SLBE
-
RLBA5
RLBA4
RLBA3
RLBA2
RLBA1
RLBA0
LDMIM
RDMIM
IFSE
-
-
-
-
-
SRAD7
SRAD6
SRAD5
SRAD4
SRAD3
SRAD2
SRAD1
SRAD0
SRDA7
SRDA6
SRDA5
SRDA4
SRDA3
SRDA2
SRDA1
SRDA0
LDMOM
LDMG6
LDMG5
LDMG4
LDMG3
LDMG2
LDMG1
LDMG0
RDMOM
RDMG6
RDMG5
RDMG4
RDMG3
RDMG2
RDMG1
RDMG0
LWM
-
LWG5
LWG4
LWG3
LWG2
LWG1
LWG0
RWM
-
RWG5
RWG4
RWG3
RWG2
RWG1
RWG0
V2
V1
V0
CID4
CID3
CID2
CID1
CID0
Table 18. Extended Register Bit Summary
DS213PP4
49
50
DSP SERIAL PORT
Gain X2L
X3R
Mute X2L, X3R
DSP Audio Data Serial Port
s
s
NOTE: The symbol
shows the active bit(s) for the
register function specified
s
s
s
s
s
Mute I2L, I3R
s
Gain I2L
I3R
Mute I2L, I3R
s
Gain I18L
* I19R
s
LINE
(Syn.)
s
s
s
s
s
s
s
s
s
s
s
s
s
s
Mute X2L, X3R
Output
Loopback
I0L, I1R
Mute I2L, I3R
s
16 bit
D/A
DSP
20dB X2L
Gain X3R
s
Digital Mixer
Master Digital
Volume
Gain X14L
X15R
s
s
s
s
s
s
s
s
s
Mute I4L, I5R
s
s
PnP ISA Interface
s
s
s
s
s
s
s
Mute I18L, I19R
*
Mute I18L, I19R
*
s
X10R
Loopback enable I13
Mute I6L
I7R
AUX 2
(CDROM)
Mute
X11L
X11R
s
Mute X8L
X9R
Gain I4L
I5R
Mute I4L, I5R
s
s
s
s
s
s
s
s
s
s
s
Loopback Atten.
I13L & (R)
X10 Stereo Enable
s
s
s
s
s
s
Atten. X8L
X9R
AUX1
(LINE IN)
s
s
s
s
s
SRC
Atten.
X4L
X5R
s
16-bit
A/D
Analog Input
Mixer
Gain I0L
I1R
MIC
s
Mute X6L
* X7R
Mute X14L
X15R
s
s
s
s
s
s
s
Mute I18L, I19R
*
Master
Volume
LINE
OUT
Mute
Mixer
I26L
X5R
s
s
s
s
s
s
Mute I26L
X4R
Mono Bypass
Atten.
-9db
s
s
WAVETABLE SERIAL PORT
MIN
MONO
OUT
s
s
s
s
Atten. I26
s
Mute I26
s
UP/DOWN/MUTE
Figure 4. MODE 3 Mixer (assumes IFM or WTEN is set)
CS4237B
DS213PP4
Wavetable Serial Port
C8
s
Gain X16L
* X17R
FM Synthesizer enable
X4
* I18/I19 can be remapped to control
X6/X7 and X16/X17. If remapping is
enabled, X0/X1 control LINE inputs
Analog
Output
s
Atten. X6L
* X7R
s
s
s
s
s
s
SRC
Mute X16L
* X17R
s
s
Atten. I6L
I7R
CS4237B
Left LINE Alternate Volume (X0)
Default = 11101000
D7
D6
D5
D4
D3
D2
Right LINE Alternate Volume (X1)
Default = 11101000
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
LLAOM LLAIM LLBAM LLAG4 LLAG3 LLAG2 LLAG1 LLAG0
RLAOM RLAIM RLABM RLAG4 RLAG3 RLAG2 RLAG1 RLAG0
LLAG4-LLAG0 Left LINE Alternate Volume. This
register is used to control the LLINE
analog input volume to the mixers
when I18 is remapped to control FM
and/or Wavetable Serial Port volume. The remapping bits are FMRM
and WTRMD (X4). The least significant bit represents 1.5 dB, with
01000 = 0 dB. See Table 10.
RLAG4-RLAG0 Right LINE Alternate Volume.
This register is used to control the
RLINE analog input volume to the
mixers when I19 is remapped to control FM and/or Wavetable Serial Port
volume. The remapping bits are
FMRM and WTRMD in X4. The
least significant bit represents
1.5 dB, with 01000 = 0 dB.
See Table 10.
LLABM
LLAIM
LAOM
LLINE
(Synthesis)
Left LINE Alternate Bypass Mute.
When set to 1, the analog Left Line
Input, LLINE, (bypassing the gain
block) to the input mixer is muted.
Left LINE Alternate Input Mute.
When set to 1, the Left Line Input,
LLINE, from the volume control to
the input mixer is muted.
Left LINE Alternate Output Mute.
When set to 1, the Left Line Input,
LLINE, from the volume control to
the output mixer is muted.
LLAG4-G0
LLAOM
To Output
Mixer
LLAIM
To Input
Mixer
+12 to -34.5 dB
Right LINE Alternate Bypass Mute.
When set to 1, the analog Right Line
Input, RLINE, (bypassing the gain
block) to the input mixer is muted.
RLAIM
Right LINE Alternate Input Mute.
When set to 1, the Right Line Input,
RLINE, from the volume control to
the input mixer is muted.
RLAOM
Right LINE Alternate Output Mute.
When set to 1, the Right Line Input,
RLINE, from the volume control to
the output mixer is muted.
RLINE
(Synthesis)
RLAG4-G0
RLAOM
To Output
Mixer
RLAIM
To Input
Mixer
+12 to -34.5 dB
LLABM
DS213PP4
RLABM
RLABM
51
CS4237B
Left MIC Volume (X2)
Default = 11001111
D7
D6
D5
D4
LMIM LMOM LMBST LMG4
LMG4-LMG0
RMIC
Input
D3
D2
D1
D0
LMG3
LMG2
LMG1
LMG0
Left Microphone Gain.
The least significant bit represents
1.5 dB, with 01111 = 0 dB.
See Table 13.
LMBST
Left Microphone 20 dB boost.
When set to 1, the signal to the output mixer is given a 20 dB boost.
LMOM
Left Microphone Output Mixer Mute.
When set to 1, the signal to the output mixer is muted.
LMIM
Left Microphone Input Mixer Mute.
When set to 1, the signal to the input mixer is muted.
LMIC
Input
LMOM
LMG4-G0
LMBST
LMIM
Synthesis and Input Mixer Control (X4)
Default = 100001xx
D7
D6
D5
D4
D3
D2
D1
D0
MIMR
LIS1
LIS0
IFM
WTRMD
FMRM
res
res
res
Reserved. Must write 0. Could be
read as 0 or 1.
FMRM
FM Volume Control Remap. This bit
only functions when IFM = 1.
If FMRM = 1, internal FM Synthesis
volume is controlled by I18/I19
(writes to I18/I19 get remapped to
X6/X7). Analog LINE volume is controlled by X0/X1.
If FMRM = 0, internal FM synthesis
volume is controlled by X6/X7 only.
WTRMD
Right MIC Volume (X3)
Default = 11001111
D7
D6
D5
D4
RMIM RMOM RMBST RMG4
RMG4-RMG0
D3
D2
D1
D0
RMG3
RMG2
RMG1
RMG0
Right Microphone 20 dB boost.
When set to 1, the signal to the output mixer is given a 20 dB boost.
RMOM
Right Microphone Output Mixer Mute.
When set to 1, the signal to the output mixer is muted.
RMIM
52
Right Microphone Input Mixer Mute.
When set to 1, the signal to the input mixer is muted.
WaveTable Volume Remap Disable.
This bit only functions when
WTEN = 1 (C8/Global Config. byte).
If WTRMD = 0, the Wavetable Serial
Port volume is controlled by I18/I19
(writes to I18/I19 get remapped to
X16/X17). Analog LINE volume is
controlled by X0/X1.
Right Microphone gain.
The least significant bit represents
1.5 dB, with 01111 = 0 dB.
See Table 13.
RMBST
To Input
Mixer
RMIM
To Input
Mixer
+22.5 to -22.5 dB
RMBST
+22.5 to -22.5 dB
To Output
Mixer
+20 dB
RMOM
RMG4-G0
To Output
Mixer
+20 dB
If WTRMD = 1, the Wavetable Serial
Port volume is controlled by
X16/X17 only.
NOTE: If FMRM = 1, and
WTRMD = 0, I18/I19 control both internal FM and Wavetable Serial Port
volume.
IFM
Internal FM enable. When set to 1,
the internal FM synthesis engine is
enabled. Setting this bit also
changes I6/7 from the master digital
audio volume to the ISA bus wave
volume control. X14/15 becomes the
DS213PP4
CS4237B
master digital audio volume. This bit
can be set through the Hardware
Configuration data in the EEPROM.
LIS1-LIS0
MIMR
Left Input Mixer Summer Attenuator.
This attenuates the inputs to the left
input mixer to enable overload protection when multiple input sources
are utilized. The least significant bit
represents 6 dB of attenuation,
where 00 yields 0 dB of attenuation.
See Table 8.
Mono Input Mute to the Right Output
mixer. When set to 1, the MIN signal
to the right output mixer is muted.
Right Input Mixer Control (X5)
Default = 000xxxxx
D7
D6
D5
D4
D3
D2
D1
D0
MOMR
RIS1
RIS0
res
res
res
res
res
res
Reserved. Must write 0. Could be
read as 0 or 1.
RIS1-RIS0
Right Input Mixer Summer Attenuator.
This attenuates the inputs to the
right input mixer to enable overload
protection when multiple input
sources are utilized. The least significant bit represents 6 dB of
attenuation, where 00 yields 0 dB of
attenuation. See Table 8.
MOMR
Mono Output Mute from the Right
Line Out, ROUT, to the mono output
mixer. When set to 1, the signal to
the mono output mixer from the
Right Line Out is muted.
D6
LFMM
res
D5
D4
D3
LFMM
Left FM mute. When set to 1, the
left internal FM input to the digital
mixer is muted.
Internal FM
Synthesizer
LFMA5-A0
LFMM
To Digital Mixer
Summer
0 to -94.5 dB
Right FM Synthesis Volume (X7)
Default = 1x000000
D7
D6
RFMM
res
D5
D4
D3
D2
D1
D0
RFMA5 RFMA4 RFMA3 RFMA2 RFMA1 RFMA0
NOTE: This FM volume register can also be controlled through I19 when IFM = 1 and FMRM = 1.
RFMA5-RFMA0 Right Internal FM Synthesis Volume.
The least significant bit represents
1.5 dB, with 000000 = 0 dB.
See Table 6.
res
Reserved. Must write 0. Could read
as 0 or 1.
RFMM
Right FM mute. When set to 1, the
right internal FM input to the digital
mixer is muted.
Internal FM
Synthesizer
RFMA5-A0
RFMM
To Digital Mixer
Summer
0 to -94.5 dB
D7
D2
D1
D0
LSPM
D6
D5
D4
D3
D2
D1
D0
res LSPA5 LSPA4 LSPA3 LSPA2 LSPA1 LSPA0
LFMA5 LFMA4 LFMA3 LFMA2 LFMA1 LFMA0
NOTE: This FM volume register can also be controlled through I18 when IFM = 1 and FMRM = 1.
LFMA5-LFMA0 Left Internal FM Synthesis Volume.
The least significant bit represents
1.5 dB, with 000000 = 0 dB.
See Table 6.
DS213PP4
Reserved. Must write 0. Could read
as 0 or 1.
Left DSP Serial Port Volume (X8)
Default = 0x000000
Left FM Synthesis Volume (X6)
Default = 1x000000
D7
res
LSPA4-LSPA0 Left DSP Serial Port Attenuation.
The least significant bit represents
1.5 dB, with 000000 = 0 dB.
See Table 6.
res
Reserved. Must write 0. Could read
as 0 or 1.
53
CS4237B
LSPM
Left DSP Serial Port Mute. When set
to 1, the Left DSP Serial Port input
(SDIN) to the digital mixer is muted.
Serial
Port
LSPA5-A0
SLBE
Stereo LoopBack Enable. When set to
1, control over the Left and Right
loopback volume is separated.
RLBA5-RLBA0 (X10) control the
Right channel, and LBA5-LBA0 (I13)
control the Left channel.
When set to 0, LBA5-LBA0 (I13) control both channels.
To Digital Mixer
Summer
LSPM
0 to -94.5 dB
DAC Mute and IFSE Enable (X11)
Default = 110xxxxx
Right DSP Serial Port Volume (X9)
Default = 0x000000
D7
D6
RSPM
res
D5
D4
D3
D2
D1
D0
D6
D5
D4
D3
D2
D1
D0
RDMIM
IFSE
res
res
res
res
res
RSPA5 RSPA4 RSPA3 RSPA2 RSPA1 RSPA0
RSPA4-RSPA0 Right DSP Serial Port Attenuation.
The least significant bit represents
1.5 dB, with 000000 = 0 dB.
See Table 6.
res
Reserved. Must write 0. Could read
as 0 or 1.
RSPM
Right DSP Serial Port Mute. When
set to 1, the Right DSP Serial Port
input (SDIN) to the digital mixer is
muted.
Serial
Port
D7
LDMIM
RSPA5-A0
To Digital Mixer
Summer
RSPM
res
Reserved. Must write 0. Could read
as 0 or 1.
IFSE
Independent Sample Freq. Enable.
When set to 1, the extended
registers X12 and X13 are used to
set the sample rate, and registers I8,
I10 (OSM1,0), and I22 are ignored.
X12 and X13 cannot be modified unless this bit is set to 1.
RDMIM
Right Digital Master Input Mixer Mute.
When set to 1, the output from the
Right DAC is Muted to the Right input mixer. See Figure 4.
LDMIM
Left Digital Master Input Mixer Mute.
When set to 1, the output from the
Left DAC is Muted to the Left input
mixer. See Figure 4.
0 to -94.5 dB
Right Loopback Monitor Volume (X10)
Default = 0x111111
D7
D6
SLBE
res
D5
D4
D3
D2
D1
D0
RLBA5 RLBA4 RLBA3 RLBA2 RLBA1 RLBA0
Independent ADC Fs (X12)
Default = xxxxxxxx
D7
D6
D5
D4
D3
D2
D1
D0
SRAD7 SRAD6 SRAD5 SRAD4 SRAD3 SRAD2 SRAD1 SRAD0
RLBA5-RLBA0 Right Channel Loopback Attenuation.
These bits determine the attenuation
of the loopback from the right ADC
to the right digital mixer. LBE in I13
must be set to enable loopback. The
least significant bit represents -1.5
dB, with 000000 = 0 dB. See Table 6.
res
54
SRAD7-SRAD0 Sample Rate frequency select for
the A/D converter. This register is
only in effect (and can only be written) while IFSE=1 in X11.
See Table 14.
Reserved. Must write 0. Could read
as 0 or 1.
DS213PP4
CS4237B
Independent DAC Fs (X13)
Default = xxxxxxxx
D7
D6
D5
D4
D3
Right Master Digital Audio Volume (X15)
Default = 00000000
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
SRDA7 SRDA6 SRDA5 SRDA4 SRDA3 SRDA2 SRDA1 SRDA0
RDMOM RDMG6 RDMG5RDMG4RDMG3RDMG2RDMG1RDMG0
SRDA7-SRDA0 Sample Rate frequency select for
the D/A converter. This register is
only in effect (and can only be written) while IFSE=1 in X11. See Table
15.
This register becomes the master digital audio volume control for the left channel when either IFM or
WTEN is set to one.
Left Master Digital Audio Volume (X14)
Default = 00000000
D7
D6
D5
D4
D3
D2
D1
D0
RDMG6-RDMG0 Right Digital Master Mixer Attenuation. The least significant bit
represents 1.5 dB, with 000000 =
0 dB. See Table 12.
RDMOM
Right Digital Master Output Mixer Mute.
When set, the Right DAC output is
muted to the Right output mixer.
LDMOM LDMG6 LDMG5 LDMG4 LDMG3 LDMG2 LDMG1 LDMG0
Note: This bit is controlled
by register (X11)
This register becomes the master digital audio volume control for the left channel when either IFM or
WTEN is set to one.
LDMG6-LDMG0Left Digital Master Mixer Attenuation.
The least significant bit represents
1.5 dB, with 000000 = 0 dB.
See Table 12.
LDMOM
Digital
Analog
From Digital
Mixer
Summer
DAC
0 to -60dB
RDMIM
To Input
Mixer
RDMOM
To Output
Mixer
+12 to -34.5dB
RDMG6-G0
Left Digital Master Output Mixer Mute.
When set to 1, the output of the Left
DAC is muted to the Left output
mixer.
Note: This bit is controlled
by register (X11)
Digital
Analog
From Digital
Mixer
Summer
DAC
0 to -60dB
LDMIM
To Input
Mixer
LDMOM
To Output
Mixer
+12 to -34.5dB
LDMG6-G0
DS213PP4
55
CS4237B
Left Wavetable Serial Port Volume (X16)
Default = 00000000
Chip Version and ID (X25)
Default = 11001000
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
LWM
res
LWG5
LWG4
LWG3
LWG2
LWG1
LWG0
V2
V1
V0
CID4
CID3
CID2
CID1
CID0
This Wavetable volume register can also be controlled through I18 when WTEN=1 (C8 or Global Config.
byte) & WTRMD=0 (X4).
This register was added to Revision C silicon. In revision B, this register read 0x00.
LWG5-LWG0
Left Wavetable Serial Port Gain.
Least significant bit represents
1.5 dB, with 01000 = 0 dB.
See Table 6.
CID5-CID0
Chip Identification. Distinguishes
between this chip and other codec
chips that support this register set.
This register is identical to C1 and
replaces the ID register in I25.
res
Reserved. Must write 0. Could read
as 0 or 1.
00000 - CS4237B, Revision B
01000 - CS4237B
LWM
Left Wavetable Serial Port Mute.
When set, the Left Wavetable Serial
Input to the digital mixer is muted.
Right Wavetable Serial Port Volume (X17)
Default = 00000000
D7
D6
RWM
res
D5
D4
D3
D2
D1
D0
RWG5 RWG4 RWG3 RWG2 RWG1 RWG0
V2-V0
Version Number. As enhancements
are made, the version number is
changed so software can distinguish
between the different versions of the
same chip.
000 - Revision B
110 - Revision C/D
111 - Revision E
This Wavetable volume register can also be controlled through I19 when WTEN=1 (C8 or Global Config.
byte) & WTRMD=0 (X4).
RWG5-RWG0 Right Wavetable Serial Port Gain.
Least significant bit represents
1.5 dB, with 01000 = 0 dB.
See Table 6.
res
Reserved. Must write 0. Could read
as 0 or 1.
RWM
Right Wavetable Serial Port Mute.
When set, the Right Wavetable Serial Input to the digital mixer is
muted.
56
DS213PP4
CS4237B
SOUND BLASTER INTERFACE
The Sound Blaster Pro compatible interface is
the third physical device in logical device 0.
Since the WSS Codec and the Sound Blaster are
mutually exclusive, the WSS Codec interrupt
and playback DMA channel are shared with the
Sound Blaster interface. To map volume controls
properly, the external devices: synthesizer (when
used), CDROM, etc., must be connected to the
proper analog inputs as illustrated in Figure 5.
Mode Switching
To facilitate switching between different functional modes (i.e. Sound Blaster and Windows
Sound System), logic is included to handle the
switch transparently to the host. No special software is required on the host side to perform the
mode switch.
Address
SBbase+0
SBbase+0
SBbase+1
SBbase+2
SBbase+2
SBbase+3
SBbase+4
SBbase+5
SBbase+6
SBbase+8
SBbase+8
SBbase+9
SBbase+A
SBbase+C
SBbase+C
SBbase+E
Sound Blaster Direct Register Interface
The Sound Blaster software interface utilizes 10bit address decoding and is compatible with
Sound Blaster and Sound Blaster Pro interfaces.
10-bit addressing requires that the upper address
bits be 0 to decode a valid address, i.e. no aliasing occurs. This device requires 16 I/O locations
located at the PnP address ’SBbase’. The following registers, shown in Table 19, are provided
for Sound Blaster compatibility.
Left/Right FM Registers,
SBbase+0 - SBbase+3
These registers are mapped directly to the appropriate FM synthesizer registers.
Mixer Address Register,
SBbase+4, write only
This register is used to specify the index address
for the mixer. This register must be written before any data is accessed from the mixer
registers. The mixer indirect register map is
shown in Table 20.
Description
Left FM Status Port
Left FM Register Status Port
Left FM Data Port
Right FM Status Port
Right FM Register Status Port
Right FM Status Port
Mixer Register Address
Mixer Data Port
Reset
FM Status Port
FM Register port
FM Data Port
Read Data Port
Command/Write Data
Write Buffer Status (Bit 7)
Data Available Status (Bit 7)
Type
Read
Write
Write Only
Read
Write
Write Only
Write Only
Read/Write
Write Only
Read Only
Write
Write Only
Read Only
Write
Read
Read
Table 19. Sound Blaster Pro Compatible I/O Interface
DS213PP4
57
CS4237B
MIC
LINE
FM
MIC
A
D
C
V
O
L
AUX1
LINE
CD
VOL
DIG
ATTN
A
U
X
1
A
U
X
2
Σ
LINE OUT
L
I
N
E
DIG VOICE
Σ
PC SPEAKER
D
A
C
MONO IN
V
O
L
V
O
L
Figure 5. SBPro Mixer Mapping
Register
00H
02H
04H
06H
08H
0AH
0CH
0EH
20H
22H
24H
26H
28H
2AH
2CH
2EH
D7
D6
D5
D4
D3
DATA RESET
RESERVED
VOICE VOLUME LEFT
X
X
X
X
X
X
X
X
D2
D1
D0
VOICE VOLUME RIGHT
RESERVED
RESERVED
X
X
X
X
X
RESERVED
MASTER VOLUME LEFT
MIC MIXING
INPUT SELECT
X
VSTC
X
X
MASTER VOLUME RIGHT
RESERVED
FM VOLUME LEFT
CD VOLUME LEFT
FM VOLUME RIGHT
CD VOLUME RIGHT
RESERVED
RESERVED
LINE VOLUME LEFT
LINE VOLUME RIGHT
Table 20. SBPro Compatible Mixer Interface
58
DS213PP4
CS4237B
Mixer Data Register,
SBbase+5
This register provides read/write access to a particular mixer register depending on the index
address specified in the Mixer Address Register.
Reset
SBbase+6, write only
When bit D[0] of this register is set to a one and
then set to a zero, a reset of the Sound Blaster
interface will occur.
Read Data Port
SBbase+A, read only
When bit D[7] of the Data Available Register,
SBbase+E, is set =1 then valid data is available
in this register. The data may be the result of a
Command that was previously written to the
Command/Write Data Register or digital audio
data.
Command/Write Data
SBbase+C, write only
The Command/Write Data register is used to
send Sound Blaster Pro commands.
Write Buffer Status,
SBbase+C, read only
The Write Buffer Status register bit D[7] indicates when the SBPro interface is ready to
accept another command to the Command/Write
Data register. D[7]=1 indicates ready. D[7]=0 indicates not ready.
Sound Blaster Mixer Registers
The Sound Blaster mixer registers are shown in
Table 20. The Sound Blaster mixer to WSS
Codec mixer mapping is shown in Figure 5.
Reset Register,
Mixer Index 00H
Writing any value to this register will reset the
mixer to default values.
DS213PP4
Voice Volume Register,
Mixer Index 04H, Default = 99H
This register provides 8 steps of voice volume
control each for the right and left channels.
Microphone Mixing Register,
Mixer Index 0AH, Default = 01H
This register provides 4 steps of microphone volume control.
Input Control Register,
Mixer Index 0CH
This register selects the input source to the ADC.
D2,D1 - 00 - Microphone
01 - CD Audio
10 - Microphone
11 - Line In
Output Control Register,
Mixer Index 0EH
VSTC - 0 - Mono Mode
1 - Stereo Mode
Master Volume Register,
Mixer Index 22H, Default = 99H
This register provides 8 steps of master volume
control each for the right and left channels.
FM Volume Register,
Mixer Index 26H, Default = 99H
This register provides 8 steps of FM volume
control each for the right and left channels.
CD Volume Register,
Mixer Index 28H, Default = 01H
This register provides 8 steps of CD volume
control each for the right and left channels.
Line-In Volume Register,
Mixer Index 2EH, Default = 01H
This register provides 8 steps of line-in volume
control each for the right and left channels.
59
CS4237B
GAME PORT INTERFACE
The Game Port logical device software interface
utilizes 10-bit address decoding and is located at
PnP address ’GAMEbase’. 10-bit addressing requires that the upper address bits be 0 to decode
a valid address, i.e. no aliasing occurs. For backwards compatibility, the Game Port consists of 8
I/O locations where the lower 6 alias to the same
location, which consists of one read and one
write register.
Plug and Play configuration capability will allow
the joystick I/O base address, GAMEbase, to be
located anywhere within the host I/O address
space. Currently most games software assume
that the joystick I/O port is located at 200h.
A write to the GAMEbase register triggers four
timers. A read from the same register returns
four status bits corresponding to the joystick fire
buttons and four bits that correspond to the output from the four timers.
A button value of 0 indicates the button is
pressed or active. The button default state is 1.
When GAMEbase is written, the X/Y timer bits
go high. Once GAMEbase is written, each timer
output remains high for a period of time determined by the current joystick position. The
number in parenthesis below is the joystick connector pin number.
GAMEbase+0 - GAMEbase+5
D7
D6
D5
D4
D3
D2
D1
D0
JBB2
JBB1
JAB2
JAB1
JBCY
JBCX
JACY
JACX
JACX
Joystick A, Coordinate X (pin 3)
JACY
Joystick A, Coordinate Y (pin 6)
JBCX
Joystick B, Coordinate X (pin 11)
JBCY
Joystick B, Coordinate Y (pin 13)
60
JAB1
Joystick A, Button 1 (pin 2)
JAB2
Joystick A, Button 2 (pin 7)
JBB1
Joystick B, Button 1 (pin 10)
JBB2
Joystick B, Button 2 (pin 14)
Two bits, JR1 and JR0, are located in the Control register space (CTRLbase+0) for defining
the speed of the Game Port Interface. Four different rates are software selectable for use with
various joysticks and to support older software
timing loops with aliasing (roll-over) problems.
GAMEbase+6
D7
D6
D5
D4
D3
D2
D1
D0
res
res
res
res
res
res
res
res
res
Must not write any value to this
register. May read any value.
GAMEbase+7
D7
D6
D5
D4
D3
D2
D1
D0
res
res
res
res
res
res
res
res
res
Must not write any value to this
register. May read any value.
The Game Port hardware interface consists of
8 pins that connect directly to the standard game
port connector. Buttons must have a 4.7 kΩ pullup resistor and a 1000 pF capacitor to ground.
X/Y coordinates must have a 5.6 nF capacitor to
ground and a 2.2 kΩ series resistor to the appropriate joystick connector pin. For a detailed
hardware description, see the Reference Design
Data Sheet.
DS213PP4
CS4237B
CONTROL INTERFACE
The Control logical device includes registers for
controlling various functions of the part that are
not included in the other logical device blocks.
These functions include game port rate control
and programmable power management, as well
as extra mixing functions.
Control Register Interface
The Control logical device software interface occupies 8 I/O locations, utilizes 12-bit address
decoding, and is located at PnP address
’CTRLbase’. If the upper address bits, SA12SA15 are used, they must be 0 to decode a valid
address. This device can also support an interrupt. Table 21 lists the eight Control registers.
Address
CTRLbase+0
CTRLbase+1
CTRLbase+2
CTRLbase+3
CTRLbase+4
CTRLbase+5
CTRLbase+6
CTRLbase+7
Register
Joystick & Power Control
E2PROM Interface
Block Power Down
Control Indirect Address Reg.
Control Indirect Data Register
Control/RAM Access
RAM Access End
Global Status
Table 21. Control Logical Device Registers
Joystick and Power Control
CTRLbase + 0, Default = 00000000
D7
D6
D5
D4
D3
D2
PM1
PM0
CONSW
PDC
PDP
PDM
JR1,0
JR0
Joystick rate control. Selects operating
speed of the joystick (changes the
trigger threshold for the X/Y coordinates).
00 - slowest speed
01 - medium slow speed
10 - medium fast speed
11 - fastest speed
DS213PP4
D1 D0
JR1
PDM
Power Down Mixer. When set, the
analog mixer is powered down and
all mixer control registers (in
WSSbase space) are reset to default values.
PDP*
Power Down Processor. When set,
places the internal processor in an
idle state. This effects the PnP interface, MPU-401, and SBPro devices.
PDC*
Power Down Codec. When set,
ADCs and DACs are powered down.
CONSW
controls host interrupt generation
when a context switch occurs
0 - no interrupt on context switch
1 - Control interrupt generated on
context switch
PM1,0
Power Management. These bits are
provided for backwards compatibility.
For new designs, the bits in
CTRLbase+2 should be used.
00 - All functions active.
01 - A/D and D/A powered down.
Mixer still active, but volume registers are frozen. Disables PDC
and PDM bits.
10 - Full part power down. All
functions are disabled except
reads and writes to this register.
All internal logic, including PnP
config. registers are reset. To exit
this power-down mode, PM1/0
must be reset, through CTRLbase+
0, and then the entire chip must be
reinitialized.
11* - WSS Codec, SBPro, MPU-401,
and PnP interfaces, and the analog
mixer are powered down.
* NOTE: The SBPro, PnP, and MPU-401 interfaces
are linked together. Setting PM1,0 or PDP will power
all three interfaces down; however, if any one of the
interfaces is written to, they will all power back up
automatically. PM1,0 and PDP always reflects the
value written, not whether the three devices are powered up or not.
61
CS4237B
E2PROM Interface
CTRLbase+1, Default = 10000000
D7
D6
D5
D4
D3
D2
D1
D0
ICH
ISH
ADC1
ADC0
IMH
DIN/
EEN
DOUT
CLK
CLK
This bit is used to generate the clock
for the Plug and Play E2PROM.
EEN must be set to 1 to make this
bit operational.
DOUT
This bit is used to output serial data
to the Plug and Play E2PROM. EEN
must be set to 1 to make this bit operational.
DIN/EEN
When read (DIN), this bit reflects
the XD0 pin, which should be serial
data output from the Plug and Play
E2PROM. EEN and DOUT must be
1 for this bit to function.
10 - Codec Input mux is mixed into
output mixer. A/D input is from
line outputs. This facilitates the Mic
mixed to output, and the output
recorded by the ADCs.
11 - reserved.
When written (EEN), enables the
E2PROM interface: CLK and DOUT
onto the peripheral port pins. Writing:
0 - E2PROM interface disabled
1 - E2PROM interface enabled
IMH*
Interrupt polarity - Modem. When set,
the MINT pin is an active high signal. When low, MINT is an active
low signal.
ADC1,0
These two bits are used to control
an additional A/D mux and enable
for an analog loopback path. These
two mixing paths provide Karaoke
support. These bits are provided for
backwards compatibility. New software should use the MIC volume
control in MODE 3 registers X2/X3
to support MIC mix to the output
mixer. See Figure 6.
00 - Normal. A/D input from the input
mux.
01 - Codec Input mux is mixed into
output mixer. A/D input is from
the input mux. This facilitates the
Mic mixed to output, but only Mic
recorded.
62
Figure 6. MODE 2 Mixer Addition
ISH*
Interrupt polarity - External Synthesizer. When set, the SINT pin is an
active high signal. When low, SINT
is an active low signal.
ICH*
Interrupt polarity - CDROM. When set,
the CDINT pin is an active high signal. When low, CDINT is an active
low signal.
* Note: These bits can be initialized through the
Hardware Configuration data.
DS213PP4
CS4237B
PDWN
Global Power Down. When set, the
entire chip is powered down, except
reads and writes to this register.
When this bit is cleared, a full calibration is initiated. All registers retain
their values; therefore, normal operation can resume after calibration is
completed. When clearing this bit,
the internal processor stays in powerdown until accesses occur to
processor interface (Sound Blaster,
MPU, or PnP accesses). If hardware
volume control is enabled, this bit
should be written to 0 twice causing
the processor to go active (which
reenables the hardware volume).
Block Power Down
CTRLbase+2, Default = 00000000
D7
D6
D5
D4
D3
D2
D1
D0
PDWN
SRC
VREF
MIX
ADC
DAC
PROC
FM
FM
Internal FM synthesizer powered down
when set.
PROC
Processor set to idle mode. When set,
places the internal processor in an
idle state. This effects the PnP interface, MPU401, and SBPro devices.
Any command to any one of these
interfaces will cause the processor
to go active.
DAC
DAC power down. When set, powers
down the D/A converters, serial
ports, and internal FM synthesizer.
The DACs should be muted prior to
setting this bit to prevent audible
pops.
ADC
ADC power down. When set, powers
down the A/D Converters.
MIX
Mixer power down. All analog input
and output channels are powered
down, except MIN and MOUT (assuming VREF is not powered down).
If MIX is 1 and VREF is 0, the MBY
bit in the WSS I26 register is forced
on. The outputs should be muted
prior to setting this bit to prevent
audible pops.
VREF
SRC
DS213PP4
VREF power down. When set, powers
down the entire mixer. Since
powering down VREF, powers down
the entire analog section, some audible pops can occur.
Internal Sample-Rate Converters are
powered down. Only 44.1 kHz sample frequency is allowed when this
bit is set.
NOTE: Software should mute the DACs and Mixers
and FM volume when asserting any power down
modes to prevent clicks and pops.
Control Indirect Address Register
CTRLbase+3
D7
D6
D5
D4
D3
D2
D1
D0
res
res
res
res
CA3
CA2
CA1
CA0
CA3-CA0
Address bits to access the Control
Indirect registers C0-C8 through
CTRLbase+4
res
Reserved. Could read as 0 or 1.
Must write as 0.
Control Indirect Data Register
CTRLbase+4
D7
D6
D5
D4
D3
D2
D1
D0
CD7
CD6
CD5
CD4
CD3
CD2
CD1
CD0
CD7-CD0
Control Indirect Data register. This
register provides access to the indirect registers C0-C8, where
CTRLbase+3 selects the actual register. See the Control Indirect
Register section for more details.
63
CS4237B
Control/RAM Access
CTRLbase+5, Default = xxxxxxxx
Global Status
CTRLbase+7, Default = xxxxxxxx
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
CR7
CR6
CR5
CR4
CR3
CR2
CR1
CR0
CWSS
ICTRL
ISB
IWSS
IMPU
res
res
res
CR7-CR0
Commands:
This register controls the loading of
the part’s internal RAM. RAM support includes hardware configuration
and PnP default resource data, as
well as program memory. See the
Hostload Procedure section for more
information. Commands are followed
by address and data information.
res
Reserved. Could read as 0 or 1.
IMPU
MPU-401 Interrupt status.
0 - no interrupt pending
1 - an interrupt is pending
IWSS
0x55 - Disable PnP Key
0 - no interrupt pending
1 - an interrupt is pending
0x56 - Disable Crystal Key
0x57 - Jump to ROM
ISB
0x5A - Update Hardware Configuration Data.
0xAA - Download RAM. Address
followed by data. (Stopped by writing 0 to CTRLbase+6)
ICTRL
Control Logical Device 2 Interrupt
status. Interrupts are generated on
a context switch between WSS and
SBPro modes.
0 - no interrupt pending
1 - an interrupt is pending
D7
D6
D5
D4
D3
D2
D1
D0
RE7
RE6
RE5
RE4
RE3
RE2
RE1
RE0
64
Sound Blaster Interrupt status.
0 - no interrupt pending
1 - an interrupt is pending
RAM Access End
CTRLbase+6, Default = xxxxxxxx
RE7-RE0
Windows Sound System Interrupt
status.
A 0 written to this location resets the
previous location, CTRLbase+5,
from data download mode to command mode.
CWSS
Context - WSS. Indicates the current
context.
0 - Sound Blaster Emulation
1 - Windows Sound System
DS213PP4
CS4237B
Control Indirect Registers
The Control Indirect registers are accessed
thr ough CTRLbase+3 and CTRLbase+4.
CTRLbase+3 is the address register and
CTRLbase+4 is the data register used to access
C0 through C8 indirect registers.
WSS Master Control (C0)
Default = 0xxxxxxx
D7
D6
D5
D4
D3
D2
D1
D0
RWSS
res
res
res
res
res
res
res
res
Reserved. Must write 0. Could read
as 0 or 1.
RWSS
Reset WSS registers. Setting this bit
forces the WSS registers to zero,
then clearing this bit forces the WSS
registers to their default state.
Address
CTRLbase+3
CTRLbase+4
Register Name
Control Indirect Address
Control Indirect Data
Table 22. Control Indirect Access Registers
Index
C0
C1
C2
C3
C4
C5
C6
C7
C8
Register Name
WSS Master Control
Version / Chip ID
3D Space and Center
3D Enable
Consumer Serial Port Enable
Lower Channel Status
Upper Channel Status
Reserved
CS9236 Wavetable Control
Table 23. Control Indirect Registers
Version / Chip ID (C1)
Default = 11001000
D7
D6
D5
D4
D3
D2
D1
D0
V2
V1
V0
CID4
CID3
CID2
CID1
CID0
CID4-CID0
Chip Identification. Distinguishes
between this chip and other codec
chips that support this register set.
This register is identical to the WSS
X25 register.
01000 - CS4237B
V2-V0
Version number. As enhancements
are made, the version number is
changed so software can distinguish
between the different versions of the
same chip.
100 - Revision A
101 - Revision B
110 - Revision C/D
111 - Revision E
DS213PP4
65
CS4237B
3DM
3D Mono Enable. When set, the SRS
Mono-to-Stereo DSP is enabled.
(3DEN must also be enabled). This
allows a mono signal to be SRS
processed into a pseudo stereo image.
3DEN
3D Enable. Must be set to enable the
SRS 3D Sound DSP.
3D Space and Center (C2)
Default = 00000000
D7
D6
SPC3
SPC2
CTR3-CTR0
SPC3-SPC0
D5
D4
SPC1 SPC0
D3
D2
D1
D0
CTR3
CTR2
CTR1
CTR0
SRS processed "Center" gain term.
The least significant bit represents
1.5 dB attenuation, with 0000=0 dB.
See Table 24. When 3DM is on, this
value is forced to 0000.
SRS processed "Space" gain term.
The least significant bit represents
1.5 dB attenuation, with 0000=0 dB.
See Table 24. When 3DM is on, this
value is forced to 0010.
3D Enable (C3)
Default = 000xxxxx
D7
D6
D5
D4
D3
D2
D1
D0
3DEN
3DM
3DSO
res
res
res
res
res
res
Reserved. Must write 0. Could read
as 0 or 1.
3DSO
3D Serial Output. When set, SDOUT
data comes from the DAC inputs
which includes 3D effects. Typically
used when CSPE in C4 is set and
determines the data used on the
Consumer Serial Port output pin.
Consumer Serial Port Enable (C4)
Default = 0000xxxx
D7
D6
D5
D4
D3
D2
D1
D0
CSPE
CSBR
U
V
res
res
res
res
V
The Validity bit in a sub-frame of
digital audio data.
U
The User bit in a sub-frame of digital
audio data.
CSBR
Channel Status Block Reset. When
set, resets the channel status block
boundary.
CSPE
Consumer Serial Port Enable. When
set, the serial port output format, on
SDOUT, converts to the consumer
standard for digital audio transmission, compatible with the consumer
portion of IEC-958. An older version
of the standard is also called
S/PDIF. Note that the serial port is
still enabled using the SPE bit in
WSS I16. For more information on
the consumer digital audio transmission format see Crystal’s Application
Note 22 titled Overview of Digital
Audio Interface Data Structures.
0 - The output is from the ADCs.
1 - The output is from the SRS DSP.
0
1
2
3
.
8
.
12
13
14
15
bit3
bit2
bit1
bit0
0
0
0
0
.
1
.
1
1
1
1
0
0
0
0
.
0
.
1
1
1
1
0
0
1
1
.
0
.
0
0
1
1
0
1
0
1
.
0
.
0
1
0
1
Space (SPC3-SPC0)
0.0 dB
-1.5 dB
-3.0 dB
-4.5 dB
-12.0 dB
-18.0 dB
-19.5 dB
-21.0 dB
-22.5 dB
Center (CTR3-CTR0)
0.0 dB
-1.5 dB
-3.0 dB
-4.5 dB
-12.0 dB
-18.0 dB
-19.5 dB
-21.0 dB
-22.5 dB
Table 24. SRS 3D Sound Control
66
DS213PP4
CS4237B
Lower Channel Status (C5)
Upper Channel Status (C6)
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
CS9
CS8
CS5
CS4
CS3
CS2
CS1
res
CS25
CS24
CS15
CS14
CS13
CS12
CS11
CS10
res
Reserved. Must write 0. Could read
as 0 or 1.
CS1
Channel Status bit 1: Audio. When
clear, indicates that the transmitted
data is digital audio and suitable for
conversion to an analog signal.
CS8-CS14
0000000 - General
0000001 - Experimental
0001xxx - Solid State Memory
001xxxx - Broadcast
010xxxx - Digital/Digital Converters
01100xx - ADCs w/o copy protection
01101xx - ADCs with copy protection
0111xxx - Broadcast
100xxxx - Laser-Optical
101xxxx - Musical Instruments
110xxxx - Magnetic Tape or Disk
111xxxx - Reserved.
0 - Digital Audio
1 - Non-Audio Data
CS2
Channel Status bit 2: Copy/Copyright
This bit, along with the L bit and the
category codes, form the SCMS
copy protection scheme.
0 - copy inhibited/copyright asserted
1 - copy permitted/copyright not
asserted.
CS4, CS3
Channel Status bits 4,3: Pre-emphasis
CS15
L or Generation Status. This bit
changes polarity based on the category codes above. For most
categories:
00 - None
01 - 50/15µs - 2 channel audio
CS5
0 - No indication, 1st generation or
higher.
1 - Original/Commercially prerecorded data.
Channel Status bit 5: Lock
0 - Source Fs Locked
1 - Source Fs Unlocked.
CS8, CS9
The above definition is reversed for
category codes:
001xxxx - Broadcast
0111xxx - Broadcast
100xxxx - Laser-Optical
The first two bits of the Category
code. See the next register
description for more details.
NOTE: More information on copy protection can be
found in the Sanchez AES paper titled An Understanding and Implementation of the SCMS Serial
Copy Management System for Digital Audio Transmission.
Category Code channel status bits.
Note: CS8 and CS9 are in the previous register. These bits define the
type of product transmitting and are
used in the SCMS copy protection
scheme to interpret the L bit.
CS25, CS24
Channel Status bits 25, 24. Sample
frequency.
00 - 44.1 kHz Sample Frequency.
This is the only Fs supported.
Reserved (C7)
D7
D6
D5
D4
D3
D2
D1
D0
res
res
res
res
res
res
res
res
res
DS213PP4
Reserved. Must write 0. Could read
as 0 or 1.
67
CS4237B
CS9236 Wavetable Control (C8)
Default = xxxx0000
D7 D6
D5
D4
D3
D2
D1
D0
res
res
res
WTEN
SPS
DMCLK
BRES
res
BRES
Force BRESET low. When set, the
BRESET pin is forced low. Typically
used for power management of peripheral devices.
DMCLK
Disable MCLK. When set, the MCLK
pin of the CS9236 Wavetable Synthesizer serial interface is forced low
providing a power savings mode.
SPS
DSP Serial Port Switch. When set,
switches the DSP serial port pins
from the 2nd joystick to the XD4XD1 pins. When SPE in I16 is set,
XD4-XD1 convert to the DSP serial
port pins. Once SPS is enabled, the
SD<7:0> bus will not be driven when
accesses occur to peripheral port devices. SPS can also be set in the
E2PROM Hardware Configuration
data, Global Configuration byte.
WTEN
res
Wavetable Serial Port Enable. When,
set, forces XD7-XD5 pins to convert
to the CS9236 Single-Chip Wavetable Music Synthesizer serial port
pins. Once WTEN is enabled, the
SD<7:0> bus will not be driven when
accesses occur to peripheral port devices. WTEN can also be set in the
E2PROM Hardware Configuration
data, Global Configuration byte.
Setting this bit also changes I6/I7
from the master digital audio volume
to the ISA bus wave volume control.
X14/15 becomes the master digital
audio volume.
Reserved. Must write 0. Could read
as 0 or 1.
SRS 3D Sound Overview
The SRS 3D Stereo DSP engine is designed to
retrieve and restore spacial information, directional cues, and other sonic nuances which are
68
either missing or altered by the electronic reproduction of stereo and/or the microphone mixing
process. SRS 3D Mono processing, when used in
conjunction with the SRS 3D Stereo system,
synthesizes a 3D stereo signal from a monaural
source.
SRS stands for Sound Retrieval System. It differs from stereo and other sound expansion
techniques because it is based on the human
hearing system. The ears are complex instruments that allow us to hear in three dimensions.
Microphones and traditional stereo playback systems only produce flat, two dimensional sound
images which are somewhat limited compared to
"real live sound". SRS compensates for these
limitations by re-establishing the necessary information that allows us to hear in three
dimensions. The results are surprisingly close to
real live sound.
SRS is unique because it does not rely on special
recording techniques. It works with any audio
signal whether it is mono, stereo, surround
sound, or even signals encoded with a sound-enhancement process. Most importantly, SRS does
not alter the original program material by adding
any form of time delay, phase shift, or harmonic
distortion.
With SRS 3D sound there is no critical listening
position or sweet spot. The listener can move
around the room and continue to be immersed in
full three-dimensional sound. Speakers are no
longer the discernible point source of sound.
SRS is a patented process that differs from stereo and surround sound in that it works with any
existing recorded material: mono, stereo, surround-encoded, or other encoding technologies.
SRS is not required in the recording process.
This means a listener’s entire audio library can
be enhanced by SRS by simply playing it
through the CS4237B Crystal chip. Like stereo,
any two-speaker stereo system is adequate.
DS213PP4
CS4237B
Hearing Basics
It has long been known that the hearing system
uses several methods to determine from which
direction a particular sound is coming. Since human hearing is binaural (two ears), these
methods include relative phase shift for low frequency sounds, relative intensity for sounds in
the voice range, and relative time of arrival for
sounds having fast rise times and high frequency
components.
The outer ear plays a significant role in the determination of direction. Due to the complex
nature of the ear’s shape, sound is subject to reflection, reinforcement, and cancellation at
various frequencies. Effectively, the human hearing system functions as a multiple filter,
emphasizing some frequencies, attenuating others, and letting some get through with no
change. The response changes with both azimuth
and elevation, and together with the binaural capabilities helps determine whether a sound is
coming from up, down, left, right, ahead, or behind.
The frequency response of microphones is not
dependent on azimuth in the same way as the
ear. Omni-directional microphones exhibit flat
response in all directions. Cardioid microphones
exhibit flat response to sounds coming from the
front and sides and are dead at the rear. As no
microphone behaves like the human ear, the
sounds picked up by a microphone are accurate
as far as the microphone is concerned but are not
the same as the sounds impinging on the human
eardrum under similar circumstances.
When the sound is reproduced by speakers, the
situation is further altered by speaker location. If
sounds which originally came from one side or
the other are reproduced by speakers which are
frontally located, these side sounds are heard
with the incorrect spectral response. The same is
true for frontal sounds which are coming from
DS213PP4
side-mounted loudspeakers. The result is spacial
distortion of the sound field which prevents the
user from hearing what was originally performed
with the proper spatial cues.
The SRS 3D Stereo Process
The Crystal SRS DSP, illustrated in Figure 7,
processes the signal in such a manner that the
spacial cues lost in the record/playback process
are restored. Since the human hearing system is
involved and is actually part of the loop, its
transfer function is made part of the system
transfer function. At the same time, SRS 3D Stereo processing avoids an objectionable buildup
of frequencies of increased phase sensitivity and
is effective over a wide area so that the listener
is not restricted to a favorable listening position
(sweet spot) between two speakers.
In the stereophonic signal, frontal sounds produce equal amplitudes in the left and right
channels and are therefore present in the "sum"
or L+R signal. Ambient sounds, which include
reflected and side sounds, produce a complex
sound field and do not appear equally in the left
and right channels. They are therefore present in
the "difference" or L-R signal. Although these
two signals are normally heard as a composite
signal, it is possible to separate and process them
independently and then remix them into a new
composite signal which contains the required
spatial cues that the stereo recording and playback processes do not provide. The directional
cues are mostly contained in the difference signals, so these can be processed, (L-R)p, to bring
the missing directional cues back to their normal
levels. The processed difference signal can then
be increased in amplitude, using SPC3-0, in order to increase apparent image width.
SRS Space Control
The SRS Space adjustment, SPC3-0 in C2, controls the amount of processed difference signal,
(L-R)p, that is added to the final left and right
digital signals going to the DACs. The difference
69
CS4237B
Σ
L+R
Digital
Mixer
Stereo
16-bit
∆-Σ
DAC
CTR3-0
L-R
Perspective
Correction
3DEN
(L-R)p
SPC3-0
Σ
R
Master Digital Volume
L
To
Analog
Mixers
Figure 7. SRS Block Diagram
signal contains the spatial information that allows us to perceive sounds from coming all
around and the directional cues that we use to
determine the localization of those sounds.
Turning up the Space control increases the
amount of corrected directional information, restores the proper localization of the original
sounds, and expands the width of the overall
sound stage. Turning down the Space control results in having no processed difference signal
component and thus limits the intensity of these
effects.
When SRS 3D sound is first turned on (3DEN in
C3), the Space control (SPC3-SPC0) should be
adjusted before the Center control. Space should
be set to approximately 75% (SPC3-0 = 0011, or
-4.5 dB) with the Center control set to 50%. As
the level of Space is increased, the sound stage
expands both in width and depth. The proper listening level is subjective and program
dependent. If centered sound information (such
as vocals) seem too low as a result of the Space
control setting, they can be adjusted using the
Center control.
SRS Center Control
The SRS Center adjustment, CTR3-0 in C2, determines the amount of sum signal (L+R) that is
added to the final left and right digital signals
going to the DACs. The sum signal contains information common to both channels that is
intended to appear in front or at the center of the
sound stage. Vocals, dialog, solo instruments,
bass, and kick drums are examples of sounds
that are often placed at the center.
When SRS 3D sound is first turned on (3DEN in
C3), the Space control should be adjusted before
the Center control (CTR3-0). Space should be
set to approximately 75% with the Center control set to 50% (CTR3-0 = 1000, or -12.0 dB).
Turning up the Center control emphasizes the
centered sounds so that their perceived level is
increased and they are brought out and into the
center of the room. Once Space is set, the Center
control should be adjusted to provide a pleasant
balance between the ambient sounds and the
centered sounds.
If adjusting the Space control yields no change
in the sound image, the input signal is probably
mono and the Mono-to-Stereo switch, 3DM,
should be enabled.
70
DS213PP4
CS4237B
SRS Mono-to-Stereo Synthesis
In addition to creating 3D Stereo images from
stereo program material, the 3DM bit in C3 expands monaural signals to a wider image format.
The first step in the conversion of a monaural
audio signal to 3D sound is the creation of a
synthetic stereo signal. This is accomplished in
the SRS 3D Mono system (3DM=1) through a
technique that makes use of constant phase filters. The original mono signal is applied to two
banks of filters which create two outputs with
one shifted 90 degrees relative to the other. Due
to the precedence effect, the ear will perceive the
leading signal as the direct sound (analogous to
L+R) and the lagging signal as ambience information (analogous to L-R or difference signal).
The lead and lag signals are dematrixed using
conventional sum and difference techniques, into
synthetic left and right stereo signals. These signals are then applied to the SRS 3D Stereo
process. Because the synthetic L, R, L+R, and
processed L-R signals are generated synthetically
from a mono input, their relationships remain
constant, and user control of the L+R and L-R
signal levels ("Center" and "Space") are not required and are internally fixed.
Consumer IEC-958 Digital Output
The CS4237B supports the industry standard
IEC-958 consumer digital interface. Sometimes
this standard is referred to S/PDIF which refers
to an older version of this standard. This output
provides an interface, external to the PC, for
storing digital audio (as in a DAT or recordable
CD-ROM) or playing digital audio from digital
speakers.
The interface is enabled by turning on the CSPE
bit in C4 and SPE in I16. The data is sent out
the SDOUT DSP serial interface pin. The other
DSP serial interface pins still function properly
when SDOUT is used for the IEC-958 interface.
DS213PP4
The SDOUT pin can either be on joystick B’s
CX pin or it can be on the peripheral port data
bus pin XD3, controlled by the SPS bit in the
Hardware Configuration data or register C8.
The data going out SDOUT can come from the
ADC or from the DAC interface (which includes
QSound 3D Sound if enabled). This functionality
is controlled by the 3DSO bit in register C3.
For the receiving device to function properly, the
Channel Status bits in C5 and C6 must be set
properly. See the Sanchez AES paper An Understanding and Implementation of the SCMS Serial
Copy Management System for Digital Audio
Transmission for more details on setting the
Channel Status information.
Figure 8 illustrates the circuit necessary for implementation of the IEC-958 consumer interface.
An external buffer is required to drive the current needed to drive the 75 Ω interface (415 Ω
or 12 mA).
374 Ω
SDOUT
90.9 Ω
RCA
Phono
Figure 8. IEC-958 Consumer Interface
The transformers can be obtained from:
Pulse Engineering
Telecom Products Group
San Diego, CA
(619) 268-2400
or
Schott Corporation
Wayzata, MN
(612) 475-1173
71
CS4237B
MPU-401 INTERFACE
The MPU-401 is an intelligent MIDI interface
that was introduced by Roland in 1984. Voyetra
Technologies subsequently introduced an IBMPC plug in card that incorporated the MPU-401
functionality. The MPU-401 has become the defacto standard for controlling MIDI devices via
IBM-PC compatible personal computers.
Although the MPU-401 does have some intelligence, a non-intelligent mode is available in
which the MPU-401 operates as a basic UART.
By incorporating hardware to emulate the MPU401 in UART mode, MIDI capability is
supported.
MPU-401 Register Interface
The MPU401 logical device software interface
occupies 2 I/O locations, utilizes 10-bit address
decoding, and is located at PnP address
’MPUbase’. 10-bit addressing requires that the
upper address bits be 0 to decode a valid address, i.e. no aliasing occurs. The standard base
address is 330h. This device also uses an interrupt, typically 9. The PnP alignment for the
MPU-401 must be a multiple of 8.
MPUbase+0 is the MIDI Transmit/Receive port
and MPUbase+1 is the Command/Status port. In
addition to I/O decodes the only additional functionality required from an ISA bus viewpoint is
the generation of a hardware interrupt whenever
data has been received into the receive buffer.
MIDI Transmit/Receive Port,
MPUbase+0, default = xxxxxxxx
D7
D6
D5
D4
D3
D2
D1
D0
TR7
TR6
TR5
TR4
TR3
TR2
TR1
TR0
TR7-TR0
72
The MIDI Transmit/Receive Port is
used to send and receive MIDI data
as well as status information that
was returned from a previously sent
command.
All MIDI transmit data is transferred through a
16-byte FIFO and receive data through a 16-byte
FIFO. The FIFO gives the ISA interface time to
respond to the asynchronous MIDI transfer rate
of 31.25K baud.
The Command/Status Registers occupy the same
address and are used to send instructions to and
receive status information from the MPU-401.
Command Register, write only
MPUbase+1
D7
D6
D5
D4
D3
D2
D1
D0
CS7
CS6
CS5
CS4
CS3
CS2
CS1
CS0
CS7-CS0
Each write to the Command/Status
Register must be monitored and the
appropriate acknowledge generated.
Status Register, read only
MPUbase+1, Default = xxxxxxxx
D7
D6
D5
D4
D3
D2
D1
D0
RXS
TXS
CS5
CS4
CS3
CS2
CS1
CS0
CS5-CS1
D0-D5 are the 6 LSBs of the last
command written to this port.
TXS
Transmit Buffer Status Flag.
0 - Transmit buffer not full
1 - Transmit buffer full
RXS
Receive Buffer Status Flag
0 - Data in Receive buffer
1 - Receive buffer empty
When in "UART" mode, data is received into the
receive buffer FIFO and a hardware interrupt is
generated. Data can be received from two
sources: MIDI data via the UART serial input or
acknowledge data that is the result of a write to
the Command Register (MPUbase+1). The interrupt is cleared by a read of the MIDI Receive
Port (MPUbase+0).
DS213PP4
CS4237B
UART mode operation is defined as follows:
MIDI UART
The UART is used to convert parallel data to the
serial data required by MIDI. The serial data rate
is fixed at 31.25K baud (±1%). The serial data
format is RS-232 like: 1 start bit, 8 data bits, and
1 stop bit.
In multimedia systems, the MIDI pins are typically connected to the joystick connector. See the
Reference Design Data Sheet for detailed information.
MPU-401 "UART" Mode Operation
After power-up reset, the interface is in "nonUART" mode. Non-UART mode operation is
defined as follows:
1. All writes to the Transmit Port, MPUbase+0,
are ignored.
2. All reads of the Receive Port, MPUbase+0,
return the last received buffer data.
3. All writes to the Command Port, MPUbase+1,
are monitored and acknowledged as follows:
a. A write of 3Fh sets the interface into
UART operating mode. An acknowledge
is generated by putting an FEh into the
receive buffer FIFO which generates an
interrupt.
b. A write of A0-A7, ABh, ACh, ADh, AFh
places an FEh into the receive buffer
FIFO (which generates an interrupt) followed by a one byte write to the receive
buffer FIFO of 00h for A0-A7, and ABh
commands, 15h for ACh, 01h for ADh,
and 64h for AFh commands.
c. All other writes to the Command Port are
ignored and an acknowledge is generated by putting an FEh into the receive
buffer FIFO which generates an interrupt.
DS213PP4
1. All writes to the Transmit Port, MPUbase+0,
are placed in the transmit buffer FIFO.
Whenever the transmit buffer FIFO is not
empty, the next byte is read from the buffer
and sent out the MIDOUT pin. The Status
Register, MPUbase+1, bit 6, TXS is updated
to reflect the transmit buffer FIFO status.
2. All reads of the Receive Port, MPUbase+0,
return the next byte in the receive buffer
FIFO. When serial data is received from the
MIDIN pin, it is placed in the next receive
buffer FIFO location. If the buffer is full,
the last location is overwritten with the new
data. The Status Register, MPUbase+1,
bit 7, RXS is updated to reflect the new receive buffer FIFO state.
3. A write to the Command Register,
MPUbase+1, of FFh will return the interface
to non-UART mode.
4. All other writes to the Command Register,
MPUbase+1, are ignored.
FM SYNTHESIZER (Internal)
This part contains a games-compatible internal
FM synthesizer. When enabled, this internal FM
synthesis engine responds to both the SBPro FM
synthesis addresses as well as the SYNbase addresses.
To enable the internal FM synthesis engine, the
IFM bit in the Hardware Configuration data,
byte 8 (Global Configuration Byte) must be set.
This bit is also available in WSS register X4.
Volume control for the internal FM synthesizer is
supported through X6 and X7 in the WSS extended register space. The volume range is 0 dB
to -94.4 dB with 000000 equal to 0 dB. After
73
CS4237B
volume is applied to the PCM FM data, it is
summed into the digital mixer which is then
summed into the analog output mixer.
as the Yamaha OPL3LS, or the Crystal Semiconductor CS9233 wave-table synthesizer chip. This
interface consists of:
For backwards compatibility with analog-mixed
external FM devices, I18 and I19 in the WSS
logical device can be remapped to control the
volume of internal FM. Remapping is controlled
through the FMRM bit in X4 register. When
IFM = 1, and FMRM = 1, writes to I18 and I19
are remapped to X6 and X7 respectively. When
remapping is enabled, the LINE analog input
volume is controlled through X0/1. When
FMRM = 0, internal FM volume is only controlled through X6/7.
SCS - chip select
SINT - Synthesizer Interrupt
The synthesizer interface is compatible with the
Adlib and Sound Blaster standards. The typical
Adlib I/O address is SYNbase = 388h.
Standard Adlib Synthesizer I/O Map
Address
SYNbase+0
SYNbase+0
SYNbase+1
SYNbase+2
SYNbase+3
Name
FM Status
FM Address 0
FM Data 0
FM Address 1
FM Data 1
Type
Read Only
Write Only
Write Only
Write Only
Read Only
EXTERNAL PERIPHERAL PORT
An external peripheral port is provided for interfacing devices external to the part. These may
include the CS9233 Wavetable synthesizer,
CDROM interface, modem interface, and Plug
and Play E2PROM.
The External Peripheral Port consists of the following signals: 8-bit data bus, 2 or 3 address
lines, read strobe, write strobe, and reset signal.
External Synthesizer Interface
This part contains an internal FM synthesis engine. For backwards compatibility the default is
to use an external FM-type synthesizer chip such
74
The other signals such as address bits, data
strobes, data, and reset are provided by the External Peripheral Port. The interface allows the
host computer to access up to eight I/O mapped
locations. When using an external FM synthesizer, SCS will respond to the SYNbase decode
addresses as well as the SBPro mapped FM synthesizer addresses. The PnP synthesizer
alignment must be a multiple of 8.
The polarity of SINT is programmable via Hardware Configuration data, IHS in byte 7, or
through CTRLbase+1. The default is active low
(IHS = 0).
Since the typical FM interface only requires four
I/O address and does not use an interrupt, the
XA2 address and the SINT pins are multifunction pins that default to XCTL0 and XCTL1. To
use XCTL0/XA2 as an address pin, the hardware
resource data must be changed. See the Hardware Configuration Data section for more
information. To use XCTL1/SINT/ACDCS/
DOWN as an interrupt for the synthesizer,
VCEN (in the Hardware Configuration data)
must be zero, a pulldown resistor must be placed
on the XIOW pin. Since XCTL1 and SINT are
rarely used the pin has a third multiplexed function, ACDCS, which is described in the
CDROM section below. The fourth multiplexed
function is the hardware volume control pin
DOWN which is controlled through the VCEN
bit. See the Volume Control Interface section for
more details. Note that ACDCS takes precedence
over XCTL1/SINT. Also DOWN, when VCEN
is set, takes precedence over all other functions.
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CS4237B
CDROM Interface
An IDE CDROM controller interface is provided
that supports Enhanced as well as Legacy IDE
CDROM drives. This interface includes two programmable chip selects and on-chip hardware to
map DMA and interrupt signals to the ISA bus.
There are five pins that make up the CDROM
interface which consist of:
CDCS - chip select, COMbase address
CDINT - interrupt, COMint
CDRQ - DMA request, COMdma
CDACK - DMA acknowledge, COMdma
ACDCS - alternate chip select, ACDbase
The four basic CDROM interface pins are multifunction pins that default to the upper address
bits SA12 - SA15. To use the pins as a CDROM
interface, a pulldown resistor must be placed on
XIOR (XIOR must be buffered if driving TTL
logic). Once the CDROM interface is selected,
the CDROM DMA pins are further multiplexed
with the Modem pins. Therefore, a fifth logical
device, typically a modem, can be used if the
CDROM doesn’t support DMA. See the Modem
Interface section for more details.
The fifth CDROM pin ACDCS is multiplexed
with XCTL1/SINT/DOWN. This chip select supports the alternate CDROM chip select used for
status in legacy IDE drives. The volume control
pin DOWN has the highest precedence; therefore, the VCEN bit must be zero to use this pin
for the CDROM interface. Given that VCEN is
zero, if the base address for ACDCS, which is
ACDbase, is programmed to a non-zero value,
this pin converts to ACDCS. ACDbase, base address 1 in LD4, is programmed via PnP or via
the SLAM method. Once this pin is set to
ACDCS, the only way to revert to XCTL1 or
SINT is to reset the part. The range of addresses
that ACDCS will respond to is programmable
via the Hardware Configuration data, byte 5,
DS213PP4
from one to eight bytes. The default is 1 byte. In
legacy IDE CDROM drives, the alternate
CDROM address plus 1, ACDbase+1, is typically shared with the floppy controller, which
only drives data bit 7. Therefore, a bit in the
Hardware Configuration data keeps the SD7 pin
from driving data bit 7 when that address is decoded. This bit is labeled ACDB7D and is
located in the Hardware Configuration data, byte
7. When using ACDCS, the SINT function
should be selected and a pullup placed on this
line, which will allow this pin to powerup inactive. If XCTL1 is selected, it will powerup low;
therefore, ACDCS will be low until ACDbase is
programmed to a non-zero value.
The default address space for the peripheral port
is 4 I/O locations where XCTL0/XA2 defaults to
the control pin XCTL0. To use XCTL0/XA2 as
the XA2 address pin, thereby increasing the address range of the peripheral port to 8 locations,
the hardware resource data must be changed. See
the Hardware Configuration Data section. Even
though the default address space is only 4 locations, the alignment for CDbase must be a
division of 8.
To make the CDROM interface more flexible,
two global bits, located in the Hardware Configuration data section - byte 7, allow control
over the polarity of the CDROM interrupt pin
CDINT, and whether the SD<7-0> pins drive the
ISA bus or not. The first bit is IHC which defaults to 1 indicating that CDINT is an active
high interrupt. IHC is also controllable through
CTRLbase+1. The second bit is SDD - SD<7:0>
bus Disable. When this bit is set, the part will
not drive the ISA Data bus SD<7:0> pins, on
reads from either CDbase or ACDbase addresses.
This bit allows external data buffers to be used
for a CDROM that bypasses the XD<7:0> bus
and connects directly to the ISA bus. Note that
SDD affects any peripheral port device which includes the external FM and modem interfaces.
75
CS4237B
Modem Interface
The modem interface, Logical Device 5 (LD5)
consist of:
MCS - Modem Chip Select
MINT - Modem Interrupt
The other signals such as address bits, data
strobes, data, and reset are provided by the External Peripheral Port. The interface allows the
host computer to access up to eight I/O mapped
locations.
The Modem signals are multiplexed with both
the upper ISA address pins, and the CDROM
DMA pins. To enable the Modem, first a pulldown resistor must be placed on XIOR which
disables the upper ISA address pins. Second, the
Modem base address, COMbase, must be programmed to a non-zero value which will convert
the SA13/CDACK/MCS pin to the modem chip
select MCS, and the SA15/CDRQ/MINT pin to
the modem interrupt pin MINT. Once these two
pins switch to modem pins, they can only be
changed by resetting the part. COMbase, Logical
Device 5 base address 0, is programmed via PnP
or the SLAM method.
The polarity of MINT is programmable via
Hardware Configuration data, IHM in byte 7, or
through CTRLbase+1. The default is active low
(IHM = 0).
DSP SERIAL AUDIO DATA PORT
The WSS Codec includes a DSP serial audio interface for transferring digital audio data
between the part and an external serial device
such as a DSP processor. The DSP serial port
pins are multiplexed with either the #2 joystick
inputs of the Game Port interface or a portion of
the XD peripheral bus. The selection is made via
the SPS bit located in Control register C8, or the
Global Config. byte in the Hardware Configuration data. If SPS is 0, the joystick B pins convert
76
to the DSP serial port when SPE is set (MCE
must be 1 to change SPE). If SPS is 1, XD<4:1>
convert to the DSP serial port when SPE is set.
In this case, SD<7:0> is disabled on reads of peripheral port addresses (CDROM, modem, etc.)
since XD<7:0> is no longer available.
The DSP audio serial port is software enabled
via the SPE bit in the WSS Codec indirect register I16. The ISA interface is fully active in this
mode. While the serial port is enabled, audio
data may still be read from the ADCs over the
ISA bus, and the DACs will sum data from the
SDIN pin, the parallel ISA bus data, and the internal FM synthesizer engine. The serial port
sample frequency is always 44.1 kHz regardless
of the ISA bus sample frequency, and the data
format is always two’s complement 16-bit linear.
FSYNC and SCLK are always output from the
part when the serial port is enabled. The serial
port can be configured in one of four serial port
formats, shown in Figures 9-12. SF1 and SF0 in
I16 select the particular format. MCE in R0 must
be set to change SF1/0. Both left and right audio
words are always 16 bit two’s complement.
When the mono audio format is selected, the
right channel output is set to zero and the left
channel input is summed to both DAC channels.
The first format - SPF0, shown in Figure 9, is
called 64-bit enhanced. This format has 64
SCLKs per frame with a one bit period wide
FSYNC that precedes the frame. The first 16 bits
occupy the left word and the second 16 bits occupy the right word. The last 32 bits contain four
status bits and 28 zeros. This is the only mode
that contains status information.
The second serial format - SPF1, shown in Figure 10, is called 64-bit mode. This format has 64
SCLKs per frame, with FSYNC high transitions
at the start of the left data word and low transitions at the start of the right data word. Both the
left and right data words are followed by 16 zeros.
DS213PP4
CS4237B
FSYNC
SCLK
SDOUT
...
... 0
15 14 13 12
15 14
16 Bits
Left Data
SDIN
...
8 zeros
0
INT
7 zeros
16 Bits
Right Data
... 0
15 14 13 12
15 14
16 Bits
Left Data
...
CEN PEN OVR
13 zeros
32 Bits
0
16 Bits
Right Data
INT = Interrupt Bit
CEN = Capture Enable
PEN = Playback Enable
OVR = Left Overrange or
Right Overrange
Figure 9. 64-bit Enhanced Mode (SF1,0 = 00)
FSYNC
SCLK
SDOUT/
SDIN
...
...
15 14 13
...
0
15 14 13
16 Clocks
16 Clocks
...
16 Clocks
Left Data
0
15
16 Clocks
Right Data
Figure 10. 64-bit Mode (SF1,0 = 01)
FSYNC
SCLK
SDOUT/
SDIN
...
15 14 13
32 No-Clock bit periods
...
...
0
16 Clocks
15 14 13
...
0
...
15 14
16 Clocks
Left Data
Right Data
Left Data
Figure 11. 32-bit Mode (SF1,0 = 10)
DS213PP4
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CS4237B
ADC and DAC data on the SDOUT allows external modem DSPs to cancel the local audio
source from the local microphone signal.
The third serial format - SPF2, shown in Figure 11, is called 32-bit mode. This format has 32
SCLKs per frame and FSYNC is high for the
left channel and low for the right channel. The
absolute time is similar to the other two modes
but SCLK is stopped after the right channel is
finished. SCLK is held stopped until the start of
the next frame (stopped for 32 bit period times).
This mode is useful for DSPs that do not want
the interrupt overhead of the 32 unused bit periods. As an example, if a DSP serial word length
is 16 bits, then four interrupts will occur in SPF0
and SPF1 modes. In mode SPF2 the DSP will
only be interrupted twice.
CS9236 WAVETABLE SERIAL PORT
A digital interface to the Crystal CS9236 SingleChip Wavetable Music Synthesizer is provided
that allows the CS9236 PCM audio data to be
summed digitally into the output digital mixer.
The Wavetable Serial port pins are multiplexed
with the XD7-XD5 external bus pins; therefore,
when this serial interface is enabled, any external
peripheral (CDROM, modem, etc.) will need an
external buffer to the ISA bus. This serial port is
enabled via the WTEN bit located in Control
register C8 or in the Global Configuration byte
in the Hardware Configuration data. The hardware connections to the CS9236 are illustrated in
Figure 13.
The fourth serial format - SPF3, shown in Figure 12, is called ADC/DAC mode. This format
has 64 SCLKs per frame, with FSYNC high
transitions at the start of the left ADC data word
and low transitions at the start of the right ADC
data word. For serial data in, SDIN, both the left
and right 16-bit DAC data word should be followed by zeros. For serial data out, SDOUT,
both the left and right ADC data words are followed by 16 bits of the DAC data words. The
DAC data words are tapped off the data stream
right before the data enters the Codec DACs (after all digital summing is done). Having the
Volume control for the serial port is supported
through X16 and X17 in the WSS extended register space. The volume range is +12 dB to
-82.5 dB with 001000 equal to 0 dB. After volume is applied to the PCM data, it is summed
into the digital mixer which is then summed into
the analog output mixer.
FSYNC
...
SCLK
SDIN
15 14 13
...
...
0
15 14 13
DAC 16 Clocks
SDOUT
15 14 13
...
0
ADC 16 Clocks
...
15
0
DAC 16 Clocks
15 14 13
...
0
DAC 16 Clocks
15 14 13
...
0
ADC 16 Clocks
Left Data
15 14 13
...
0
15
DAC 16 Clocks
Right Data
Figure 12. ADC/DAC Mode (SF1,0 = 11)
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DS213PP4
CS4237B
For backwards compatibility with analog-mixed
wavetable devices, I18 and I19 in the WSS logical device can be remapped to control the
volume of the Wavetable serial port. Remapping
is controlled through the WTRMD bit in X4 register. When WTEN = 1, and WTRMD = 0,
writes to I18 and I19 are remapped to X16 and
X17 respectively. When remapping is enabled,
the LINE analog input volume is controlled
through X0/1. When WTRMD = 1, the
Wavetable Serial Port volume is only controlled
through X16/17.
CS9236
100 Ω
MCLK
MCLK5I
LRCLK
LRCLK
SDATA
SOUT
BRESET
RST
100k Ω
100k Ω
MIDOUT
XTAL3I
Midi In
The completion of calibration can be determined
by polling the Auto-Calibrate In-Progress bit in
the Error Status and Initialization register (ACI,
I11). This bit will be high while the calibration is
in progress and low once completed. Transfers
enabled during calibration will not begin until
the calibration cycle has completed. Since the
part always operates at 44.1 kHz internally, all
calibration times are based on 44.1 kHz sample
periods.
The Calibration procedure is as follows:
PDN
MIDI_IN
MIDIN
Calibration
The WSS Codec has four different calibration
modes. The selected calibration occurs whenever
the Mode Change Enable (MCE, R0) bit goes
form 1 to 0.
Midi Out
1) Place the WSS Codec in Mode Change
Enable using the MCE bit of the Index Address register (R0).
2) Set the CAL1,0 bits in the Interface Configuration register (I9).
Joystick Connector
Figure 13. CS9236 Wavetable Serial Port Interface
WSS CODEC SOFTWARE DESCRIPTION
The WSS Codec must be in Mode Change Enable Mode (MCE=1) before any changes to the
Interface Configuration register (I9) or the Sample Frequency (lower four bits) in the Fs &
Playback Data Format registers (I8) are allowed.
The actual audio data formats, which are the upper four bits of I8 for playback and I28 for
capture, can be changed by setting MCE (R0) or
PMCE/CMCE (I16) high. The exceptions are
CEN and PEN which can be changed "on-thefly" via programmed I/O writes. All outstanding
DMA transfers must be completed before new
values of CEN or PEN are recognized.
DS213PP4
3) Return from Mode Change Enable by resetting the MCE bit of the Index Address
register (R0).
4) Wait until 80h NOT returned
5) Wait until ACI (I11) cleared to proceed
NO CALIBRATION (CAL1,0 = 00)
This is the fastest mode since no calibration is
performed. This mode is useful for games which
require the sample frequency be changed
quickly. This mode is also useful when the codec
is operating full-duplex and an ADC data format
change is desired. This is the only calibration
mode that does not affect the DACs (i.e. mute
the DACs). The No Calibration mode takes zero
sample periods.
79
CS4237B
CONVERTER CALIBRATION (CAL1,0 = 01)
This calibration mode calibrates the ADCs and
the DACs, but does not calibrate any of the analog mixing channels. This is the second longest
calibration mode, taking 321 sample periods at
44.1 kHz. Because the analog mixer is not calibrated in this mode, any signals fed through the
mixer will be unaffected. The calibration sequence is as follows:
The DACs are muted
The ADCs are calibrated
The DACs are calibrated
The DACs are unmuted
DAC CALIBRATION (CAL1,0 = 10)
This calibration mode only clears the DACs
(playback) interpolation filters leaving the ADC
unaffected. This is the second fastest calibration
mode (no cal. is the fastest) taking 120 sample
periods at 44.1 kHz to complete. The calibration
sequence is as follows:
The DACs are muted
The DAC filters are cleared
The DACs are unmuted
FULL CALIBRATION (CAL1, 0 = 11)
This calibration mode calibrates all offsets,
ADCs, DACs, and analog mixers. Full calibration will automatically be initiated on power up
or anytime the WSS Codec exits from a full
power down state. This is the longest calibration
mode and takes 450 sample periods at 44.1 kHz
to complete. The calibration sequence is as follows:
All outputs are muted (DACs and mixer)
The mixer is calibrated
The ADCs are calibrated
The DACs are calibrated
All outputs are unmuted
Changing Sampling Rate
The internal states of the WSS Codec are synchronized by the selected sampling frequency.
The sample frequency can be set in one of three
fashions. The standard WSS Codec method uses
the Fs & Playback Data Format register (I8) to
set the sample frequency. The changing of either
the clock source or the clock frequency divide
requires a special sequence for proper WSS
Codec operation:
1) Place the WSS Codec in Mode Change Enable using the MCE bit of the Index Address
register (R0).
2) During a single write cycle, change the Clock
Frequency Divide Select (CFS) and/or
Clock 2 Base Select (C2SL) bits of the Fs &
Playback Data Format register (I8) to the desired value. (The data format may also be
changed.)
3) The WSS Codec resynchronizes its internal
states to the new frequency. During this time
the WSS Codec will be unable to respond.
Writes to the WSS Codec will not be recognized and reads will always return the value
80 hex.
4) The host now polls the WSS Codec’s Index
Address register (R0) until the value 80 hex
is no longer returned. On slow processor systems, 80h may occur to fast; therefore, it
may never be seen by software.
5) Once the WSS Codec is no longer responding
to reads with a value of 80 hex, normal operation can resume and the WSS Codec can
be removed from MCE.
A second method of changing the sample frequency is to disable the sample frequency bits in
I8 (lower four bits) by setting SRE in I22. When
this bit is set, OSM1 and OSM0 in I10, along
80
DS213PP4
CS4237B
with the rest of the bits in I22, are used to set the
sample frequency. Once enabled, these bits can
be changed without doing an MCE cycle.
The third method supports independent sample
frequencies (Fs) for capture and playback. The
independent sample frequency mode is enabled
by setting IFSE in X11. Once enabled, the other
two methods for setting Fs (I8, I10, and I22) are
disabled. The capture (ADC) Fs is set in X12
and the playback (DAC) Fs is set in X13.
Changing Audio Data Formats
In MODE 1, MCE must be used to select the
audio data format in I8. Since MCE causes a
calibration cycle, it is not ideal for full-duplex
operation. In MODE 2 and 3, individual Mode
Change Enable bits for capture and playback are
provided in register I16. MCE (R0) must still be
used to select the sample frequency, but PMCE
(playback) and CMCE (capture) allow changing
the respective data formats without causing a
calibration to occur. Setting PMCE (I16) clears
the playback FIFO and allows the upper four
bits of I8 to be changed. Setting CMCE (I16)
clears the capture FIFO and allows the upper
four bits of I28 to be changed.
Audio Data Formats
In MODE 1 operation, all data formats of the
WSS Codec are in "little endian" format. This
format defines the byte ordering of a multibyte
word as having the least significant byte occupying the lowest memory address. Likewise, the
most significant byte of a little endian word occupies the highest memory address.
The sample frequency is always selected in the
Fs & Playback Data Format register (I8). In
MODE 1 the same register, I8, determines the
audio data format for both playback and capture;
however, in MODE 2 and 3, I8 only selects the
playback data format and the capture data format
is independently selectable in the Capture Data
Format register (I28).
DS213PP4
The WSS Codec always orders the left channel
data before the right channel. Note that these
definitions apply regardless of the specific format of the data. For example, 8-bit linear data
streams look exactly like 8-bit companded data
streams. Also, the left sample always comes first
in the data stream regardless of whether the sample is 16-bit or 8-bit in size.
There are four data formats supported by the
WSS Codec during MODE 1 operation: 16-bit
signed (little endian), 8-bit unsigned, 8-bit companded µ-Law, and 8-bit companded A-Law.
See Figures 14-17.
Additional data formats are supported in MODE
2 and 3: 4-bit ADPCM, and 16-bit signed Big
Endian. See Figures 18 through 21. With the addition of the Big Endian and ADPCM audio data
formats, the WSS Codec is compliant with the
IMA recommendations for digital audio data formats (and sample frequencies).
16-BIT SIGNED
The 16-bit signed format (also called 16-bit 2’s
complement) is the standard method of representing 16-bit digital audio. This format gives
96 dB theoretical dynamic range and is the
standard for compact disk audio players. This
format uses the value -32768 (8000h) to represent maximum negative analog amplitude, 0 for
center scale, and 32767 (7FFFh) to represent
maximum positive analog amplitude.
8-BIT UNSIGNED
The 8-bit unsigned format is commonly used in
the personal computer industry. This format delivers a theoretical dynamic range of 48 dB. This
format uses the value 0 (00h) to represent maximum negative analog amplitude, 128 for center
scale, and 255 (FFh) to represent maximum
positive analog amplitude. The 16-bit signed and
8-bit unsigned transfer functions are shown in
Figure 22.
81
CS4237B
32-bit Word
sample 6
sample 5
MONO
sample 4
MONO
31
sample 3
Time
sample 2
MONO
24 23
sample 1
MONO
16 15
8 7
0
Figure 14. 8-bit Mono, Unsigned Audio Data
32-bit Word
sample 3
sample 3
RIGHT
sample 2
LEFT
31
sample 2
sample 1
RIGHT
24 23
Time
sample 1
LEFT
16 15
8 7
0
Figure 15. 8-bit Stereo, Unsigned Audio Data
32-bit Word Time
sample 6
sample 5
sample 4
sample 3
sample 2
MONO
31
24 23
sample 1
MONO
16 15
8 7
0
Figure 16. 16-bit Mono, Signed Little Endian Audio Data
32-bit Word Time
sample 3
sample 3
sample 2
sample 2
sample 1
RIGHT
31
24 23
sample 1
LEFT
16 15
8 7
0
Figure 17. 16-bit Stereo, Signed Little Endian Audio Data
82
DS213PP4
CS4237B
32-bit Word
sample 8
MONO
31
MONO
28 27
sample 7
MONO
24 23
sample 6
MONO
20 19
sample 5
MONO
16 15
Time
sample 4
sample 3
MONO
12 11
sample 2
MONO
8 7
sample 1
MONO
4 3
0
Figure 18. 4-bit Mono, ADPCM Audio Data
32-bit Word
sample 4
RIGHT
31
LEFT
28 27
sample 4
RIGHT
24 23
sample 3
LEFT
20 19
sample 3
RIGHT
16 15
Time
sample 2
sample 2
LEFT
12 11
sample 1
RIGHT
8 7
sample 1
LEFT
4 3
0
Figure 19. 4-bit Stereo, ADPCM Audio Data
32-bit Word
sample 4
sample 4
sample 3
MONO LO
23
sample 3
sample 2
MONO HI
16 31
sample 2
sample 1
MONO LO
24 7
Time
sample 1
MONO HI
0 15
8
Figure 20. 16-bit Mono, Signed Big Endian Audio Data
32-bit Word
sample 2
sample 2
sample 2
RIGHT LO
23
sample 2
sample 1
RIGHT HI
16 31
sample 1
sample 1
LEFT LO
24 7
Time
sample 1
LEFT HI
0 15
8
Figure 21. 16-bit Stereo, Signed Big Endian Audio Data
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CS4237B
8-BIT COMPANDED
The 8-bit companded formats (A-Law and µLaw) come from the telephone industry. µ-Law
is the standard for the United States/Japan while
A-Law is used in Europe. Companded audio allows either 64 dB or 72 dB of dynamic range
using only 8-bits per sample. This is accomplished using a non-linear companding transfer
function which assigns more digital codes to
lower amplitude analog signals with the sacrifice
of precision on higher amplitude signals. The µLaw and A-Law formats of the WSS Codec
conform to the CCITT G.711 specifications. Figure 23 illustrates the transfer function for both
A- and µ-Law. Please refer to the standards mentioned above for an exact definition.
ADPCM COMPRESSION/DECOMPRESSION
In MODE 2 and 3, the WSS Codec also contains Adaptive Differential Pulse Code
Modulation (ADPCM) for improved performance and compression ratios over µ-Law or
A-Law. The ADPCM format is compliant with
the IMA standard and provides a 4-to-1 compression ratio (i.e. 4 bits are saved for each
16-bit sample captured). For more information
on the specifics of the format, contact the IMA
at (410) 626-1380. Figures 18 and 19 illustrate
the ADPCM data flow.
The ADPCM format is unique with respect to
the FIFO depth and the DMA Base register
value. The ADPCM format fills the FIFOs completely (64 bytes); therefore, the FIFOs hold 64
stereo samples and 128 mono samples. When
samples are being transferred using DMA, the
DMA request stays active for four bytes, similar
to the 16-bit stereo data mode. In PIO mode, the
Status register (R2) indicates which of the four
bytes is being transferred.
When CEN is 0 (capture disabled), the ADPCM
block’s accumulator and step size are cleared.
When CEN is enabled, the ADPCM block will
start converting. Care should be taken to insure
that the "overrun" condition never occurs, otherwise the data may not be constructed properly
upon playback. If pausing the capture sequence
is desired, the ADPCM Capture Freeze bit (ACF,
I23) should be set. When this bit is set, the
ADPCM algorithm will continue to operate until
a complete word (4 bytes) is written to the FIFO.
Then the ADPCM’s block accumulator and step
size will be frozen. The software must continue
ANALOG VALUE
+FS
0
-FS
A-Law: 2Ah
u-Law: 00h
Figure 22. Linear Transfer Functions
84
15h
3Fh
55h/D5h
7Fh/FFh
DIGITAL CODE
95h
BFh
AAh
80h
Figure 23. Companded Transfer Functions
DS213PP4
CS4237B
reading until the FIFO is empty, at which time
the requests will stop. When ACF is cleared, the
ADPCM adaptation will continue.
When PEN is cleared (playback disabled), the
ADPCM block’s accumulator and step size are
cleared. When PEN is set, the ADPCM block
will start converting. When pausing the playback
stream is desired, audio data should not be sent
to the codec which will cause a data underrun.
This can be accomplished by disabling the DMA
controller or not sending data in PIO mode. The
underrun will be detected by the WSS Codec
and the adaptation will freeze. When data is sent
to the codec, adaptation will resume. It is critical
that all playback ADPCM samples are sent to the
codec, since dropped samples will cause errors
in adaptation. Whereas toggling PEN resets the
accumulator and step size, the APAR bit (I17)
only resets the accumulator without affecting the
step size.
DMA Registers
The DMA registers allow easy integration of this
part into ISA systems. Peculiarities of the ISA
DMA controller require an external count
mechanism to notify the host CPU of a full
DMA buffer via interrupt. The programmable
DMA Base registers provide this service.
The act of writing a value to the Upper Base
register causes both Base registers to load the
Current Count register. DMA transfers are enabled by setting the PEN/CEN bit while
PPIO/CPIO is clear. (PPIO/CPIO can only be
changed while the MCE bit is set.) Once transfers are enabled, each sample that is transferred
by a DMA cycle will decrement the Current
Count register (with the exception of the
ADPCM format) until zero is reached. The next
sample after zero generates an interrupt and reloads the Current Count registers with the values
in the Base registers.
DS213PP4
For all data formats except ADPCM, the DMA
Base registers must be loaded with the number
of samples, minus one, to be transferred between
"DMA Interrupts". Stereo data contains twice as
many samples as mono data; however, 8-bit data
and 16-bit data contain the same number of samples. Symbolically:
DMA Base register16 = NS - 1
Where NS is the number of samples transferred
between interrupts and the "DMA Base register16" consists of the concatenation of the upper
and lower DMA Base registers.
For the ADPCM data format, the contents of the
DMA Base registers is calculated differently
from any other data format. The Base registers
must be loaded with the number of BYTES to be
transferred between "DMA interrupts", divided
by four, minus one. The same equation is used
whether the data format is stereo or mono
ADPCM. Symbolically:
DMA Base register16 = Nb/4 - 1
Where Nb is the number of BYTES transferred
between interrupts and the "DMA Base register16" consists of the concatenation of the upper
and lower DMA Base registers.
PLAYBACK DMA REGISTERS
The playback DMA registers (I14/15) are used
for sending playback data to the DACs in
MODE 2 and 3. In MODE 1, these registers
(I14/15) are used for both playback and capture;
therefore, full-duplex DMA operation is not possible.
When the playback Current Count register rolls
under, the Playback Interrupt bit, PI, (I24) is set
causing the INT bit (R2) to be set. The interrupt
is cleared by a write of any value to the Status
register (R2), or writing a "0" to the Playback
Interrupt bit, PI (I24).
85
CS4237B
CAPTURE DMA REGISTERS
The Capture DMA Base registers (I30/31) provide a second pair of Base registers that allow
full-duplex DMA operation. With full-duplex operation capture and playback can occur
simultaneously. These registers are provided in
MODE 2 and 3 only.
When the capture Current Count register rolls
under, the Capture Interrupt bit, CI, (I24) is set
causing the INT bit (R2) to be set. The interrupt
is cleared by a write of any value to the Status
register (R2), or writing a "0" to the Capture Interrupt bit, CI (I24).
Digital Loopback
Digital Loopback is enabled via the LBE bit in
the Loopback Control register (I13). This loopback routes the digital data from the ADCs to
the DACs. There are two Methods of controlling this loopback. The first method does not
allow separate control over the attenuation level
of the left and right channels. Changes to the
attenuation bits of register I13 will simultaneously affect both the left and the right channels.
The other method of controlling loopback, is to
set the SLBE bit in register X10. This separates
the attenuation levels of the left and right channels. With SLBE enabled, the attenuation bits of
register I13 only control the left channel, and the
attenuation bits of register X10 control the right
channel. The LBE bit in register I13 still enables, or disables digital loopback for both
channels. Loopback is then summed into the
digital mixer. The digital loopback is illustrated
in Figure 4. Since the WSS Codec allows selection of different data formats between capture
and playback, if the capture channel is set to
mono and the playback channel set to stereo, the
mono input (mic) data will be mixed into both
channels of the output mixer.
86
If the sum of the digital mixer inputs is greater
than full scale, WSS Codec will send the appropriate full scale value to the DACs (clipping).
Timer Registers
The Timer registers are provided for synchronization, watch dog and other functions where a
high resolution time reference is required. This
counter is 16 bits and the exact time base, listed
in the register description, is determined by the
clock base frequency selected.
The Timer register is set by loading the high and
low registers to the appropriate values and setting the Timer Enable bit, TE, in the Alternate
Feature Enable register (I16). This value will be
loaded into an internal Current Count register
and will decrement at approximately a 10 µsec
rate. When the value of the Current Count register reaches zero, an interrupt will be posted to
the host and the Timer Interrupt bit, TI, is set in
the Alternate Feature Status register (I24). On
the next timer clock the value of the Timer registers will be loaded into the internal Current
Count register and the process will begin again.
The interrupt is cleared by any write to the
Status register (R2) or by writing a "0" to the
Timer Interrupt bit, TI, in the Alternate Feature
Status register (I24).
WSS Codec Interrupt
The INT bit of the Status register (R2) always
reflects the status of the WSS Codec’s internal
interrupt state. A roll-over from any Current
Count register (DMA playback, DMA capture, or
Timer) sets the INT bit. This bit remains set until
cleared by a write of ANY value to Status register (R2), or by clearing the appropriate bit or bits
(PI, CI, TI) in the Alternate Feature Status register (I24).
DS213PP4
CS4237B
The Interrupt Enable (IEN) bit in the Pin Control
register (I10) determines whether the interrupt
assigned to the WSS Codec responds to the interrupt event. When the IEN bit is low, the
interrupt is masked and the IRQ pin assigned to
the WSS Codec is held low. However, the INT
bit in the Status register (R2) always responds to
the counter.
Error Conditions
Data overrun or underrun could occur if data is
not supplied to or read from the WSS Codec in
an appropriate amount of time. The amount of
time for such data transfers depends on the frequency selected within the WSS Codec.
Should an overrun condition occur during data
capture, the last whole sample (before the overrun condition) will be read by the DMA
interface. A sample will not be overwritten while
the DMA interface is in the process of transferring the sample.
Should an underrun condition occur in a playback case the last valid sample will be output
(assuming DACZ = 0) to the digital mixer. This
will mask short duration error conditions. When
the next complete sample arrives from the host
computer the data stream will resume on the
next sample clock.
The overrun and underrun error bits in the Alternate Feature Status register, I24, are cleared by
first clearing the condition that caused the overrun or underrun error, followed by writing the
particular bit to a zero. As an example, to clear
the playback underrun bit PU, first a sample
must be sent to the WSS Codec, and then the PU
bit must be written to a zero.
DIGITAL HARDWARE DESCRIPTION
The best example of hardware connection for the
different sections of this part such as joystick
connector, ISA bus, and peripheral port connections is the Reference Design Data Sheet. The
DS213PP4
Reference Design Data Sheet contains all the
schematics, layout plots and a Bill of Materials;
thereby providing a complete example.
Bus Interface
The ISA bus interface is capable of driving a
24mA data bus load and therefore does not require any external data bus buffering. See the
Reference Design Data Sheet for a typical connection diagram.
Volume Control Interface
Three hardware master volume control pins are
supported: volume up, volume down, and mute.
Hardware volume control is enabled by setting
the VCEN bit in the Hardware Configuration
data, byte 7 (Misc. Config. Byte). Once VCEN
is set, the SCS/UP pin converts to the volume up
function and the XTAL1/SINT/ACDCS/DOWN
pin converts to the volume down function. The
volume control pins affect the master volume
control output after the analog output mixer. The
UP and DOWN pins, when low, increment and
decrement the master volume. These two pins
would use SPST momentary switches. The
MUTE pin supports three options: push-on/pushoff, momentary (similar to the up/down
functions), and non-existent where pressing up
and down simultaneously mutes the output volume. As shown in Figure 24, the three pins
require external pullups and are active low. The
circuit also contains an optional RC for EMI and
ESD protection.
The volume control range is +12 to -36 dB in
2 dB steps. Pressing the up button, increments
the volume. Pressing the down button, decrements the volume. Holding either of these
buttons in the low state causes the volume to to
continue changing.
The mute function is supported using three formats. These formats are selected using the VCF1
and VCF0 bits in the Hardware Configuration
data, Global Config. byte.
87
CS4237B
The three formats listed above as illustrated in
Figure 25.
VDF
10 k Ω
10 k Ω
10 k Ω
UP
100 Ω
Up
100 Ω
DOWN
Down
100 Ω
MUTE
A four th format for mute exists, where
VCF1,0 = 11, which is backwards compatible
with the CS4236. This mode is similar to the
two button mode, except the MUTE pin is used
as the up function and the UP pin is not used.
Mute
100 pF
100 pF
100 pF
GND
Figure 24. Volume Control Circuit
In the first format, where VCF1,0 = 00, the mute
function is a toggle or push-on/push-off style.
When the MUTE pin is low, the master out volume is muted. Pressing the up or down buttons
have no effect while the mute switch is on.
In the second format, where VCF1,0 = 01, the
mute function is a momentary switch (similar to
up and down). When MUTE goes low the master out volume mutes if it was un-muted and
vise-versa (the mute button alternates between
mute and un-mute). If the master volume is
muted and up or down is pressed, the volume
automatically un-mutes.
In the third format, where VCF1,0 = 10, the
MUTE pin is not used. This is a two-button format where pressing up and down simultaneously
mutes the master volume. If the master volume
is muted and up or down is individually pressed,
the volume automatically un-mutes.
Crystal / Clock
Two pins have been allocated to allow the interfacing of a crystal oscillator: XTALI and
XTALO. The crystal should be designed as fundamental mode, parallel resonant, with a load
capacitor of between 10 and 20 pF. The capacitors connected to each of the crystal pins should
be twice the load capacitance specified to the
crystal manufacturer.
An external CMOS clock may be connected to
the crystal input XTALI in lieu of the crystal.
When using an external CMOS clock, the
XTALO pin must be left floating with no trace
or external connection of any kind.
General Purpose Output Pins
Two general purpose outputs are provided to enable control of external circuitry (i.e. mute
function). XCTL1 and XCTL0 in the WSS
Codec register I10 are output directly to the appropriate pin when enabled.
Pin XCTL0/XA2 becomes an output for XCTL0
whenever the resource data for the CDROM or
Synthesizer specifies a logical device address
Up
Up
Up
Down
Down
Down
Mute
Mute
Mute
GND
GND
GND
VCF1,0 = 00
VCF1,0 = 01
VCF1,0 = 10
Figure 25. Volume Control Formats
88
DS213PP4
CS4237B
range that is four bytes. If the address range is
specified to be eight bytes, then XA2 becomes
an output for SA2 from the ISA bus.
Pin XCTL1/SINT/ACDCS/DOWN is initially
controlled by the VCEN bit in the Hardware
Configuration data. If VCEN is zero, this pin becomes an output for XCTL1 when the state of
the XIOW pin is sampled high during a high to
low transition of the RESDRV pin. This pin also
becomes an output for ACDCS if ACDbase is
programmed to a non-zero value. If XIOW is
sampled low and ACDbase is never programmed
to a non-zero value, SINT becomes an input for
the external Synthesizer interrupt. XIOW has an
internal pullup resistor. ACDCS takes precedence over the other two functions. The first
time ACDbase is programmed to a non-zero
value, the pin converts to ACDCS. The only way
to convert back to XTAL1 or SINT is to reset
the part. VCEN has the highest precedence and
will cause this pin to convert to the DOWN
function whenever VCEN is set.
Reset and Power Down
A RESDRV pin places the part into maximum
power conservation mode. When RESDRV goes
high, the PnP registers are reset - all logical devices are disabled, all analog outputs are muted,
and the voltage reference then slowly decays to
ground. When RESDRV is brought low, an initialization procedure begins which causes a full
calibration cycle to occur. When initialization is
completed, the registers will contain their reset
value and the part will be isolated from the bus.
RESDRV is required whenever the part is powered up. The initialization time varies based on
whether an E2PROM is present or not and the
size of the data in the E2PROM. After RESDRV
goes low, the CS4236 should not be written to
for approximately one and one half second to
guarantee that the part is ready to respond to
commands. The exact timing is specified in the
Timing Section in the front of this data sheet.
DS213PP4
Software low-power states are available through
bits in the Control logical device register space.
This part supports the same power down bits
contained in the CS4232; however, new power
down modes are provided in CTRLbase+2 that
allow for a more efficient power management
routine. This register allows individual blocks
within the part to be powered down. See the
CONTROL INTERFACE section for more information.
Multiplexed Pin Configuration
On the high to low transition of the RESDRV
pin, the part samples the state of the XIOR and
XIOW pins. Both of these pins have internal
100kΩ pullups to +5V. If either of these pins is
pulled low externally, they must be buffered before connecting to a TTL input (as in a CDROM
port) since TTL cannot be pulled low.
The state of XIOR at the time RESDRV is
brought low determines the function of the
CDROM interface pins. If XIOR is sampled
high, then CDCS, CDACK, CDINT, CDRQ are
used to input SA12, SA13, SA14, SA15 respectively. If XIOR is sampled low (external
pulldown) then CDCS, CDACK, CDINT, CDRQ
become the standard CDROM interface pins.
Since many CDROM drives do not use DMA,
the CDRQ and CDACK pins are further multiplexed with MCS and MINT respectively. MCS
is the Modem chip select that responds to COMbase addresses, and MINT is the modem
interrupt input. These two pins comprise logical
device 5. The first time COMbase is programmed to non-zero (assuming XIOR was
sampled low), CDACK/MCS and CDRQ/MINT
switch to MCS and MINT respectively. Once
this switch occurs, the only way to revert to the
CDROM DMA pins is to reset the part or remove power.
The XCTL1/SINT/ACDCS/DOWN pin state is
first determined by VCEN. If VCEN is set this
pin is forced to the DOWN volume control pin.
89
CS4237B
If VCEN is zero, then if ACDbase is ever programmed to a non-zero value, this pin converts
to the ACDCS pin and keeps this function until
the part is reset (or VCEN is set to one). If
ACDbase is never programmed non-zero, then
the state of XIOW at the time RESDRV is
brought low determines whether the pin is
XCTL1 or SINT. If XIOW is sampled low (external pulldown) then XCTL1/SINT/
ACDCS/DOWN functions as an input for the
synthesizer interrupt. If XIOW is sampled high
(pin left unconnected) then XCTL1/SINT/
ACDCS/DOWN becomes an output for XCTL1.
This part contains another multiplexed pin,
SCS/UP. This pin provides the FM synthesizer
chip select or the hardware volume control "volume up" feature. Since an internal FM
synthesizer exists, this pin would normally be
used for the volume control feature. Setting
VCEN forces this pin to the UP volume control
function. When VCEN is clear, this pin is the
SCS chip select function.
ANALOG HARDWARE DESCRIPTION
The analog hardware consist of an MPC
Level 2-compatible mixer (four stereo mix
sources), three line-level stereo inputs, a stereo
microphone input, a mono input, a mono output,
and a stereo line output. This section describes
the analog hardware needed to interface with
these pins.
Line-Level Inputs Plus MPC Mixer
The analog inputs consist of four stereo analog
inputs, and one mono input. As shown in Figure 4, the input to the ADCs comes from the
Input Mixer that selects any combination of the
following: LINE, AUX1, AUX2, MIC, the DAC
output, and the output from the analog output
mixer. Unused analog inputs should be connected together and then connected through a
capacitor to analog ground.
The analog input interface is designed to accommodate four stereo inputs and one mono input.
Four of these sources are mixed to the ADC.
These inputs are: a stereo line-level input
(LINE), a stereo microphone input (MIC), a stereo CD-ROM input (AUX2), and a stereo
auxiliary line-level input (AUX1). The LINE
and AUX1 inputs have two paths to the Input
Mixer. One path is direct with no volume control. The other path goes through an inverting
amplifier, which enables volume control. Care
should be taken to select only one of these dual
paths, because the inverting path will cancel the
signal of the non-inverting path at the Input
Mixer. The LINE, MIC, AUX1, and AUX2 inputs have paths after their volume controls, to
the output mixer. The output mixer has the additional input of a mono input channel. All audio
inputs should be capacitively coupled.
To obtain Sound Blaster mixer compatibility, the
mapping of external devices to analog inputs is
important. An external FM or Wavetable synthesizer analog output must be connected to the
LINE input. The internal FM’s volume control,
when enabled, maps to the LINE analog mixer
registers. The CDROM analog outputs must be
connected to the AUX2 inputs, and the external
Line Inputs must be connected to the AUX1 analog inputs.
Since some analog inputs can be as large as
2 VRMS, the circuit shown in Figure 26 can be
used to attenuate the analog input to 1 VRMS
which is the maximum voltage allowed for the
line-level inputs.
6.8 kΩ
1.0 µF
R
1.0 µF
6.8 kΩ
6.8 kΩ
L
6.8 kΩ
Figure 26. Line Inputs
90
DS213PP4
CS4237B
The AUX2 line-level inputs have an extra pin,
CMAUX2, which provides a pseudo-differential
input for both LAUX2 and RAUX2. This pin
takes the common-mode noise out of the AUX2
inputs when connected to the ground coming
from the AUX2 analog source. Connecting the
AUX2 pins as shown in Figure 27 provides extra
noise attenuation coming from the CDROM
drive, thereby producing a higher quality signal.
Since the better the resistors match, the better the
common-mode attenuation, one percent resistors
are recommended. If CMAUX2 is not used, it
should be connected through an AC cap to analog ground.
1.0 µF
3.4 kΩ
6.8 kΩ
6.8 kΩ
1.0 µF
3.4 kΩ
47 kΩ
VREF
+
47 kΩ
0.1 µF
MC33078 or
MC33178
1 µF
0.33 µF
LMIC
4.7 kΩ
X7R
RMIC
600 Ω
+
2.7 nF
NPO
0.33 µF
10 µF
Figure 28. Left or Mono Microphone Input
(All resistors 1%)
6.8 kΩ
2 kΩ
RAUX2
CMAUX2
LAUX2
1.0 µF
6.8 kΩ
Figure 27. Differential CDROM In
Microphone Level Inputs
The microphone level inputs, LMIC and RMIC,
include a selectable -22.5 dB to +22.5 dB gain
stage for interfacing to an external microphone.
An additional 20 dB gain block is available in
the path to the output mixer. The 20 dB gain
block can be switched off to provide another stereo line-level input. Figure 28 illustrates a
single-ended microphone input buffer circuit that
will support lower gain mics. If a mono microphone is all that is desired, the RMIC input
should be connected to the output of the mono
op amp, used for LMIC, through its own AC
coupling capacitor. The circuit in Figure 28 supports dynamic mics and phantom-powered mics
that use the right channel of the jack for power.
Mono Input
The mono input, MIN, is useful for mixing the
output of the "beeper" (timer chip), provided in
all PCs, with the rest of the audio signals. The
attenuation control allows 16 levels in -3dB
steps. In addition, a mute control is provided.
The attenuator is a single channel block with the
resulting signal sent to the output mixer where it
is mixed with the left and right outputs. Figure 29 illustrates a typical input circuit for the
Mono In. If MIN is driven from a CMOS gate,
the 4.7kΩ should be tied to AGND instead of
VA+. Although this input is described for a lowquality beeper, the input is of the same
high-quality as all other analog inputs and may
be used for other purposes. At power-up, the
MIN line is connected directly to the MOUT pin
(with 9 dB of attenuation) allowing the initial
beeps, heard when the computer is initializing, to
pass through.
+5VA (Low Noise) or
AGND - if CMOS Source
4.7 kΩ
1
47 kΩ
0.1 µF
MIN
2.7 nF
Figure 29. Mono Input
DS213PP4
91
CS4237B
Line Level Outputs
The analog output section provides a stereo linelevel output. The other output types (headphone
and speaker) can be implemented with external
circuitry. LOUT and ROUT outputs should be
capacitively coupled to external circuitry. Both
LOUT and ROUT need 1000 pF NPO capacitors
between the pin and AGND.
Mono Output with Mute Control
The mono output, MOUT, is a sum of the left
and right output channels, attenuated by 6dB to
prevent clipping at full scale. The mono out
channel can be used to drive the PC-internal
mono speaker using an appropriate drive circuit.
This approach allows the traditional PC-sounds
to be integrated with the rest of the audio system. Figure 30 illustrates a typical speaker driver
circuit. The mute control is independent of the
line outputs allowing the mono channel to mute
the speaker without muting the line outputs. The
power-up default has MIN connected to MOUT
providing a pass-through for the beeps heard at
power-up.
+5V
Ferrite Bead
470 pF
0.1 µF
10 kΩ
MOUT
0.22 µF
RESDRV
1 µF +
4
3
6
5
8
16 kΩ
the ADCs. By placing these filters at the input to
the ADCs, low-pass filters at each analog input
pin are avoided.
The REFFLT pin is used to lower the noise of
the internal voltage reference. A 1µF (must not
be greater than 1µF) and 0.1µF capacitor to analog ground should be connected with a short
wide trace to this pin. No other connection
should be made, as any coupling onto this pin
will degrade the analog performance of the
codec. Likewise, digital signals should be kept
away from REFFLT for similar reasons.
The VREF pin is typically 2.2 V and provides a
common mode signal for single-supply external
circuits. VREF only supports light DC loads and
should be buffered if AC loading is needed. For
typical use, a 0.1 µF in parallel with a 10 µF capacitor should be connected to VREF.
GROUNDING AND LAYOUT
Figure 31 is a suggested layout for motherboard
designs and Figure 32 is a suggested layout for
add-inn cards. For optimum noise performance,
the device should be located across a split analog/digital ground plane. The digital ground
plane should extend across the ISA bus pins as
well as the internal digital interface pins.
DGND1 is ground for the data bus and should
be electrically connected to the digital ground
plane which will minimize the effects of the bus
2 1 7
MC34119
or LM4861
Figure 30. Mono Output
Miscellaneous Analog Signals
The LFILT and RFILT pins must have a 1000 pF
NPO capacitor to analog ground. These capacitors, along with an internal resistor, provide a
single-pole low-pass filter used at the inputs to
92
DS213PP4
CS4237B
interface due to transient currents during bus
switching. SGND1-4 are the substrate grounds
and should also be connected to the digital
ground plane to minimize coupling into the analog section. Figure 33 shows the recommended
positioning of the decoupling capacitors. The capacitors must be on the same layer as, and close
to, the part. The vias shown go through to the
ground and power plane layers. Vias, power supply traces, and REFFLT traces should be as large
as possible to minimize the impedance.
POWER SUPPLIES
The power supply providing analog power
should be as clean as possible to minimize coupling into the analog section and degrading
analog performance.
The VD1 is isolated from the rest of the power
supply pins and provide digital power for the
asynchronous parallel ISA bus (except for
DRQA). The VD1 pin can be connected directly
Di
g it
al
Digital
Ground
to the system digital power supply. VD1 can also
be connected to a 3.3V supply providing a 3.3V
ISA interface. When connected to a 3.3V supply,
all ISA bus input pins (SA15-0, SD7-0, DACKs,
etc.) must be at 3.3V levels (not 5V), with the
exception of the DRQA pin. DRQA is internally
connected to the VDF supplies and remains a
5 Volt pin even when the ISA bus is run at
3.3 Volts. When the ISA bus is powered from
3.3 Volts, DRQA can be be used through a level
translator, or DRQA can remain used. If DRQA
is not used, all references to this pin should be
removed in the PnP Resource data. Even though
the ISA bus is at 3.3V, the peripheral port is still
at a 5V potential including XD7-0 and all chip
select and address pins.
VDF1 through VDF4 provide power to internal
digital sections of the codec and should be quieter than VD1. This can be achieved by using a
Gr
o
Analog
Ground
Crystal
Part
un
d
No
ise
1
Digital Ground Noise
G
al
gi t
i
D
ro
un
e
ois
N
d
Power
Connector
Figure 31. Suggested Motherboard Layout
DS213PP4
93
CS4237B
CD-ROM
Speaker Out
Speaker In
Analog Ground
Crystal
Part
1
Digital Ground
Figure 32. Suggested Add-In Card Layout
1µF
PIN 98
VDF3
.1µ F PIN 97
SGND3
PIN 81
VA
PIN 80
AGND
PIN 1
XD7
+
PIN 79
.1µ F REFFLT
.1µF
Analog
PIN 71
TEST
PIN 66
SGND2
.1µF
Digital
PIN 17
VDF1
PIN 65
VDF2
= vias through to
power/ground plane
.1µF
PIN 54
VDF4
PIN 18
SGND1
.1µF
PIN 53
SGND4
PIN 45
VD1
.1µ F
PIN 46
DGND1
Figure 33. Recommended Decoupling Capacitor Positions
94
DS213PP4
CS4237B
ferrite bead to the VD1 supply as shown in the
Reference Design Data Sheet. These pins must
be connected to a 5V supply.
VA provides power to the sensitive analog sections of the chip and should have a clean,
regulated supply to minimize power supply coupled noise in the analog inputs and outputs.
10
0
-10
-20
Magnitude (dB)
ADC/DAC FILTER RESPONSE PLOTS
Figures 34 through 39 show the overall frequency response, passband ripple, and transition
band for the ADCs and DACs. Figure 40 shows
the DACs’ deviation from linear phase. Since the
filter response scales based on sample frequency
selected, all frequency response plots x-axis are
shown from 0 to 1, where 1 is equivalent to Fs.
Therefore, for any given sample frequency, multiply the x-axis values by the sample frequency
selected to get the actual frequency.
-30
-40
-50
-60
-70
-80
-90
-100
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Input Frequency ( x Fs)
0.2
0
0.1
-10
0.0
-20
-0.1
-30
Magnitude (dB)
Magnitude (dB)
Figure 34. ADC Filter Response
-0.2
-0.3
-0.4
-40
-50
-60
-0.5
-70
-0.6
-80
-0.7
-90
-0.8
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
Input Frequency ( x Fs)
Figure 35. ADC Passband Ripple
DS213PP4
0.45
0.50
-100
0.40
0.45
0.50
0.55
0.60
0.65
0.70
Input Frequency ( x Fs)
Figure 36. ADC Transition Band
95
CS4237B
10
0.2
0
0.1
-10
0.0
Magnitude (dB)
Magnitude (dB)
-20
-30
-40
-50
-60
-0.1
-0.2
-0.3
-0.4
-0.5
-70
-80
-0.6
-90
-0.7
-100
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
-0.8
0.00
1.0
0.05
0.10
Input Frequency ( x Fs)
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0.45
0.50
Input Frequency ( x Fs)
Figure 37. DAC Filter Response
Figure 38. DAC Passband Ripple
2.0
0
-10
1.5
-20
1.0
∆ Phase (degrees)
Magnitude (dB)
-30
-40
-50
-60
-70
0.5
0.0
-0.5
-1.0
-80
-1.5
-90
-100
0.40
0.45
0.50
0.55
0.60
Input Frequency ( x Fs)
Figure 39. DAC Transition Band
96
0.65
0.70
-2.0
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
Input Frequency ( x Fs)
Figure 40. Deviation from Linear Phase
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AGND
REFFLT
VREF
LFILT
RFILT
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
XTALI
XTALO
VDF3
SGND3
CMAUX2
MUTE
SA12*/CDCS
SA13*/CDACK/MCS
SA14*/CDINT
SA15*/CDRQ/MIN T
RESDRV
MOUT
MIN
LLINE
RLINE
LAUX2
RAUX2
LMIC
RMIC
VA
PIN DESCRIPTIONS
CS4237B
(TOP VIEW)
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
LAUX1
RAUX1
LOUT
ROUT
TEST
JAB1
JBB1*/FSYNC
JACX
JBCX*/SDOUT
SGND2
VDF2
JBCY*/SDIN
JACY
JBB2*/SCLK
JAB2
MIDOUT
MIDIN
DACKA (DACK0*)
DACKC (DACK3*)
DACKB (DACK1*)
DRQA (DRQ0*)
VDF4
SGND4
DRQC (DRQ3*)
DRQB (DRQ1*)
AEN
IOCHRDY
SD0
SD1
SD2
SD3
VD1
DGND1
SD4
SD5
SD6
SD7
IOR
IOW
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
100-PIN
TQFP
XD7/SDATA
XD6/LRCLK
XD5/MCLK
XD4/FSYNC
XD3/SDOUT
XD2/SDIN
XD1SCLK
SDA/XD0
SCS/UP
XIOR
XIOW
XCTL0*/XA2
XA1
SCL/XA0
BRESET
XCTL1*/SINT/ACDCS/DOWN
VDF1
SGND1
(INT15*) IRQF
(INT12*) IRQE
(INT11*) IRQD
(INT9*) IRQC
(INT7*) IRQB
(INT5*) IRQA
SA0
* Defaults - See individual pin descriptions for more details
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CS4237B
ISA Bus Interface Pins
SA<11:0> - System Address Bus, Inputs
These signals are decoded during I/O cycles to determine access to the various functional
blocks within the part as defined by the configuration data written during a Plug and Play
configuration sequence.
SA<15:12> - Upper System Address Bus, Inputs
These signals are multi-function pins, shared with the CDROM and modem interface, that
default to the upper address bits SA12 through SA15. These pins are generally used for
motherboard designs that want to eliminate address decode aliasing. Using these pins as upper
address bits forces the part to only accept valid address decodes when A12-A15 = 0. If these
pins are not used for address decodes (or for CDROM support), they should be tied to SGND.
SD<7:0> - System Data Bus, Bi-directional, 24mA drive
These signals are used to transfer data to and from the part and associated peripheral devices.
Reads from peripheral devices can be disabled (the part does not drive the SD<7:0> pins) by
setting the SDD bit in the Hardware Configuration data. Reads from peripheral devices are
automatically disabled whenever the XD pins are used as serial port pins (SPS/SPE or WTEN
set to one).
AEN - Address Enable, Input
This signal indicates whether the current bus cycle is an I/O cycle or a DMA cycle. This signal
is low during an I/O cycle and high during a DMA cycle.
IOR - Read Command Strobe, Input
This active low signal defines a read cycle to the part. The cycle may be a register read or a
read from the part’s DMA registers.
IOW - Write Command Strobe, Input
This active low signal indicates a write cycle to the part. The cycle may be a write to a control
register or a DMA register.
IOCHRDY - I/O Channel Ready, Open Drain Output, 8mA drive
This signal is driven low by the part during ISA bus cycles in which the part is not able to
respond within a minimum cycle time. IOCHRDY is forced low to extend the current bus
cycle. The bus cycle is extended until IOCHRDY is brought high.
DRQ<A,B,C> - DMA Requests, Outputs, 24mA drive
These active high outputs are generated when the part is requesting a DMA transfer. This
signal remains high until all the bytes have been transferred as defined by the current transfer
data type. The DRQ<A,B,C> outputs must be connected to 8-bit DMA channel request signals
only. The defaults on the ISA bus are DRQA = DRQ0, DRQB = DRQ1, and DRQC = DRQ3.
The defaults can be changed by modifying the Hardware Resource data. Note that DRQA is a
5 Volt-only pin. When the ISA bus is run at 3.3 Volts, DRQA can either be used with the proper
level translator, or DRQA can be left unconnected and not used.
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DACK<A,B,C> - DMA Acknowledge, Inputs
The assertion of these active low signals indicate that the current DMA request is being
acknowledged and the part will respond by either latching the data present on the data bus
(write) or putting data on the bus (read). The DACK<A,B,C> inputs must be connected to 8-bit
DMA channel acknowledge lines only. The defaults on the ISA bus are DACKA = DACK0,
DACKB = DACK1, and DACKC = DACK3. The defaults can be changed by modifying the
Hardware Resource data.
IRQ <A:F>- Host Interrupt Pins, Outputs, 24mA drive
These signals are used to notify the host of events which need servicing. They are connected to
specific interrupt lines on the ISA bus. The IRQ<A:F> are individually enabled as per
configuration data that is generated during a Plug and Play configuration sequence. The defaults
on the ISA bus are IRQA = INT5, IRQB = INT7, IRQC = INT9, IRQD = INT11,
IRQE = INT12, IRQF = INT15. The defaults can be changed by modifying the Hardware
Configuration data loaded from the E2PROM.
Analog Inputs
LLINE - Left Line Input
Nominally 1 VRMS max analog input for the Left LINE channel, centered around VREF. A
programmable gain block provides volume control and is located in either I18 or X0 based on
how synthesis is mapped. LLINE is typically used for Left Channel Synthesis (FM or
Wavetable).
RLINE - Right Line Input
Nominally 1 VRMS max analog input for the Right LINE channel, centered around VREF. A
programmable gain block provides volume control and is located in either I19 or X1 based on
how synthesis is mapped. RLINE is typically used for Right Channel Synthesis (FM or
Wavetable).
LMIC - Left Mic Input
Microphone input for the Left MIC channel, centered around VREF. A programmable gain
block provides volume control and is located in X2. In MODE 3, the output mixer has an extra
selectable 20 dB of gain controlled by the LMBST bit.
RMIC - Right Mic Input
Microphone input for the Right MIC channel, centered around VREF. A programmable gain
block provides volume control and is located in X3. In MODE 3, the output mixer has an extra
selectable 20 dB of gain controlled by the RMBST bit.
LAUX1 - Left Auxiliary #1 Input
Nominally 1 VRMS max analog input for the Left AUX1 channel, centered around VREF. A
programmable gain block provides volume control and is located in I2. Typically used for an
external Left line-level input.
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CS4237B
RAUX1 - Right Auxiliary #1 Input
Nominally 1 VRMS max analog input for the Right AUX1 channel, centered around VREF. A
programmable gain block provides volume control and is located in I3. Typically used for an
external Right line-level input.
LAUX2 - Left Auxiliary #2 Input
Nominally 1 VRMS max analog input for the Left AUX2 channel, centered around VREF. A
programmable gain block provides volume control and is located in I4. Typically used for the
Left channel CDROM input.
RAUX2 - Right Auxiliary #2 Input
Nominally 1 VRMS max analog input for the Right AUX2 channel, centered around VREF. A
programmable gain block provides volume control and is located in I5. Typically used for the
Right channel CDROM input.
CMAUX2 - Common Mode Auxiliary #2 Input
Common mode ground input for the LAUX2 and RAUX2 inputs. Typically connected to the
CDROM ground input to provide common-mode noise rejection. The impedance on this pin
should be one half the impedance on the LAUX2 and RAUX2 inputs.
MIN - Mono Input
Nominally 1 VRMS max analog input, centered around VREF, that goes through a
programmable gain stage (I26) into both channels of the output mixer. This is a general purpose
mono analog input that is normally used to mix the typical "beeper" signal on most computers
into the audio system.
Analog Outputs
LOUT - Left Line Level Output
Analog output from the mixer for the left channel. Nominally 1 VRMS max centered around
VREF. This pin needs a 1000 pF NPO capacitor attached and tied to analog ground.
ROUT - Right Line Level Output
Analog output from the mixer for the Right channel. Nominally 1 VRMS max centered around
VREF. This pin needs a 1000 pF NPO capacitor attached and tied to analog ground.
MOUT - Mono Output
MOUT is nominally 1 VRMS max analog output, centered around VREF. This output is a
summed analog output from both the left and right output channels of the mixer. MOUT
typically is connected to a speaker driver that drives the internal speaker in most computers. In
MODE2, MOM in I26 mutes both channels going into MOUT. In MODE 3, MOM in I26
mutes the left channel and MOMR in X5 mutes the right channel.
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MIDI Interface
MIDOUT - MIDI Out Transmit Data, Output, 4mA drive
This output is used to send MIDI data serially out to a external MIDI device. Normally
connected to pin 12 of the joystick connector for use with breakout boxes.
MIDIN - MIDI In Receive Data, Input
This input is used to receive serial MIDI data from an external MIDI device. This pin should
have a 4.7 kΩ pullup attached and is normally connected to pin 15 of the joystick connector for
use with breakout boxes.
External FM Synthesizer Interface
SCS - Synthesizer Chip Select, Output, 4 mA drive
By default, SCS/UP is an active low output forced low when a valid address decode to an
external FM synthesizer, as defined in the Plug and Play configuration registers, has occurred.
When the internal FM synthesizer is enabled, this pin is no longer used as an FM synthesizer
chip select. This pin can be used for a hardware volume up pin by setting VCEN in the
Hardware Configuration data.
SINT - Synthesizer Interrupt, Input
This pin, XCTL1/SINT/ACDCS/DOWN, defaults to the XCTL1 output which is controlled by
the XCTL1 bit in the WSS register I10. If VCEN in the Hardware Configuration data is set, this
pin converts to the DOWN volume control function. If VCEN is zero, and ACDbase is never
programmed to a non-zero value, this pin can be changed to SINT input by connecting a 10 kΩ
resistor between the XIOW pin and SGND. The polarity of SINT can be programmed through
CTRLbase+1 register, the ISH bit, or the Hardware Configuration data. SINT defaults to an
active low input that should be driven by the external FM synthesizer interrupt output pin. This
pin can also be configured at a second CDROM Chip Select, ACDCS, to support the alternate
IDE CDROM decode. (See the CDROM section for more information.) The pin is switched to
the CDROM alternate chip select when VCEN is zero and the base address is first programmed
to non-zero through the E2PROM data or PnP commands.
External Peripheral Port
XD<7:1> - External Data Bus bits 7 through 1, Bi-directional, 4mA drive
These pins are used to transfer data between the ISA bus and external devices such as the
modem and CDROM. These pins are also multiplexed with two serial ports. A DSP serial port
can be connected through the XD4-XD1 pins. This interface is multiplexed onto these external
data bus pins OR the 2nd Joystick pins based on the SPS (Serial Port Switch) bit. The second
serial port connects to the CS9236 Single-Chip Wavetable Music Synthesizer and uses pins
XD7-XD5. This serial port is enabled via the WTEN bit. Both SPS and WTEN are located in
either C8 in the Control logical device, or the Global Configuration byte in the E2PROM
Hardware Configuration data.
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CS4237B
SDA/XD0 - External Data Bus bit 0/E2PROM Data Pin, Bi-directional, Open Drain,4mA sink
This open-drain pin must have an external pullup (3.3 kΩ) and is used to transfer data between
the ISA bus bit 0, SD0, and external devices such as a modem or CDROM. SDA/XD0 is also
used in conjunction with SCL/XA0 to access an external serial E2PROM. When an E2PROM is
used, the SDA/XD0 pin should be connected to the data pin of the E2PROM device and
provides a bi-directional data port. The E2PROM is used to set the Plug and Play resource data.
XCTL0/XA2 - XCTL0 or External Address SA2, Output, 4mA drive
This pin either outputs ISA bus address SA2 or XCTL0 depending on the Hardware
Configuration data. The default is XCTL0 which is controlled by the XCTL0 bit in the WSS
register I10. This pin changes to address bit XA2 if the Hardware Configuration data indicates
that the peripheral port requires more than four I/O addresses.
XA1 - External Address, Output, 4mA drive
This pin outputs ISA bus address SA1.
XA0/SCL - External Address, Output/Serial Clock, Output, 4mA drive
This pin outputs the ISA bus address SA0. When E2PROM access is enabled, via EEN in
CTRLbase+1, then SCL is used as a clock output to the E2PROM.
BRESET - Buffered Reset, Output, 4mA drive
This active low signal goes low whenever the RESDRV pin goes high. This pin is also software
controllable through the BRES bit in register C8 in the Control Logical Device space. BRES
provides a software power down and reset control over devices connected to the Crystal Codec
such as the CS9236 Single-Chip Wavetable Music Synthesizer.
XIOR - External Read Strobe, Output, 4mA drive (SA12-SA15/CDROM selection)
This active low signal goes low whenever (SCS, CDCS, or MCS) and IOR goes low. When
RESDRV goes low, this pin also selects either the CDROM/Modem port or SA12 - SA15 and
contains an internal pullup of approximately 100 kΩ. When XIOR is left high (default), pins
91-94 are SA15-SA12 respectively. To enable the CDROM and Modem ports, an external 10kΩ
resistor must be tied between this pin and SGND.
XIOW - External Write Strobe, Output, 4mA drive (XCTL1/SINT/ACDCS/DOWN selection)
This active low signal goes low whenever (SCS or CDCS or MCS) and IOW goes low. When
RESDRV goes low, this pin also selects either XCTL1 or SINT and contains an internal pullup
of approximately 100 kΩ. When XIOW is left high (default), pin 16 is the XCTL1 function (or
ACDCS, based on a non-zero value being programmed into the alternate CDROM address
register). To change the pin to SINT, an external 10kΩ resistor must be tied between this pin
and SGND.
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Joystick/DSP Serial Port Interface
JACX, JACY - Joystick A Coordinates, Input
These pins and are the X/Y coordinates for Joystick A. They should have a 5.6nF capacitor to
ground and a 2.2kΩ resistor to the joystick connector pins 3 and 6, respectively.
JAB1, JAB2 - Joystick A Buttons, Input
These pins are the switch inputs for Joystick A. They should be connected to joystick connector
pins 2 and 7, respectively; as well as have a 1nF capacitor to ground, and a 4.7kΩ pullup
resistor.
JBCX/SDOUT - Joystick B Coordinate X/Serial Data Output, Input/Output
When this pin is used as a second joystick, it is the X coordinates input for Joystick B; and
should have a 5.6nF capacitor to ground and a 2.2kΩ resistor to the joystick connector pin 11.
When the serial port is enabled, SPE = 1 in I16, this pin is the serial data output. The DSP
serial port SDOUT pin can be switched to XD3 via the SPS bit. This would facilitate using the
DSP serial port and the second joystick simultaneously.
JBCY/SDIN - Joystick B Coordinate Y/Serial Data Input, Input
When this pin is used as a second joystick, it is the Y coordinates input for Joystick B; and
should have a 5.6nF capacitor to ground and a 2.2kΩ resistor to the joystick connector pin 13.
When the serial port is enabled, SPE = 1 in I16, this pin is the serial data input. The DSP serial
port SDIN pin can be switched to XD2 via the SPS bit. This would facilitate using the DSP
serial port and the second joystick simultaneously.
JBB1/FSYNC - Joystick B Button 1/Frame Sync, Input/Output
When this pin is used as a second joystick, it is the switch 1 input for Joystick B; and should be
connected to joystick connector pin 10; as well as have a 1nF capacitor to ground, and a 4.7kΩ
pullup resistor. When the serial port is enabled, SPE = 1 in I16, this pin is the serial frame sync
output. The DSP serial port FSYNC pin can be switched to XD4 via the SPS bit. This would
facilitate using the DSP serial port and the second joystick simultaneously.
JBB2/SCLK - Joystick B Button 2/Serial Clock, Input/Output
When this pin is used as a second joystick, it is the switch 2 input for Joystick B; and should be
connected to joystick connector pin 14; as well as have a 1nF capacitor to ground, and a 4.7kΩ
pullup resistor. When the serial port is enabled, SPE = 1 in I16, this pin is the serial clock
output. The DSP serial port SCLK pin can be switched to XD1 via the SPS bit. This would
facilitate using the DSP serial port and the second joystick simultaneously.
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CS9236 Wavetable Serial Port Interface
A digital interface to the Crystal CS9236 Single-Chip Wavetable Music Synthesizer is provided
that allows the CS9236 PCM audio data to be summed digitally on the Crystal Codec without
the need for an external DAC. The Wavetable Serial Port interface pins are multiplexed with the
XD7-XD5 external bus pins. This serial port is enabled via the WTEN bit which is located in
the Global Configuration byte in the E2PROM Hardware Configuration data, or C8. The
interface typically consists of the three pins listed below as well as:
connecting the Crystal Codec MIDOUT pin to the CS9236 MIDI_IN pin, and
connecting the Crystal Codec BRESET pin to the CS9236 PDN and RST pins.
(The BRES bit in C8 provides a maximum software power-down mode for the
CS9236 by driving the BRESET signal low whenever BRES is set.)
SDATA - Wavetable Serial Audio Data, Input
This pin is multiplexed with the XD7 external data bus pin. When use as SDATA, this input
supplies the serial audio PCM data to be digitally mixed to the DACs of the Crystal codec. The
data consists of left and right channel 16-bit data delineated by LRCLK. This pin should be
connected to the SOUT output pin on the CS9236. This pin should also have a weak pull-down
resistor of approx. 100 kΩ to minimize power-down currents and allow for stuffing options.
LRCLK - Wavetable Serial Left/Right Clock, Input
This pin is multiplexed with the XD6 external data bus pin. When use as LRCLK, this input
supplies the serial data alignment signal that delineates left from right data. This pin should be
connected to the LRCLK output pin on the CS9236. This pin should also have a weak
pull-down resistor of approx. 100 kΩ to minimize power-down currents and allow for stuffing
options.
MCLK - Wavetable Master Clock, Output
This pin is multiplexed with the XD5 external data bus pin. When use as MCLK, this output
supplies the 16.9344 MHz master clock that controls all the timing on the CS9236. This pin
should be connected to the MCLK5I input pin on the CS9236. MCLK can be disabled in
software using the DMCLK bit in C8 in the Control logical device space. DMCLK provides a
partial software power-down mode for the CS9236.
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CDROM and Modem Interface
The four CDROM pins are multi-function and default to ISA upper address bits SA12-SA15.
To enable the CDROM port, an external 10kΩ resistor must be tied between XIOR and SGND.
XIOR is sampled on the falling edge of RESDRV. If the CDROM interface doesn’t support
DMA, the two CDROM DMA pins can be converted to support Logical Device 5, a modem
interface.
CDCS - CDROM Chip Select, Output, 4mA drive
This output goes low whenever an address is decoded that matches the value programmed into
the CDROM base address register.
ACDCS - Alternate CDROM Chip Select, Output, 4mA drive
This pin, XCTL1/SINT/ACDCS/DOWN, is multiplexed with three other functions, and defaults
to the XCTL1 output which is controlled by the XCTL1 bit in the WSS I10. This pin can also
be configured at a second CDROM Chip Select, ACDCS, to support the alternate IDE CDROM
decode. The pin is switched to the CDROM alternate chip select when the base address
ACDbase is first programmed to non-zero through the E2PROM data or PnP commands. This
output then goes low whenever an address is decoded that matches the value programmed into
the CDROM alternate base address register, ACDbase. This pin can also be used as the volume
up pin DOWN by setting VCEN in Control register C0 or the Hardware Configuration data.
VCEN has the highest precedence over the other pin functions.
CDINT - CDROM Interrupt, Input
This pin is used to input an interrupt signal from the CDROM interface. The part can be
programmed, through the plug-and-play resource data, to output this signal to the appropriate
ISA bus interrupt line. The polarity if this input can be programmed through CTRLbase+1
register, bit ICH, or the Hardware Configuration data; the default is active high.
CDRQ/MINT - CDROM DMA Request, or Modem Interrupt, Input
This pin can be used to input the DMA request signal from the CDROM interface. The part can
be programmed, through the plug-and-play resource data, to output this signal to the
appropriate ISA bus DRQ line.
This pin can also be used to input an interrupt signal from a modem. The pin is switched to
MINT when the LD5 base address, COMbase, is first programmed to non-zero through the PnP
data or a hostload. The polarity of MINT can be programmed through CTRLbase+1 register,
IMH bit, or the Hardware Configuration data; the default is active low.
CDACK/MCS - CDROM DMA Acknowledge, or Modem Chip Select, Output, 4mA drive
This pin can be used to output the ISA bus-generated DMA acknowledge signal to the CDROM
interface. Alternately, this pin can be used to output an active low Modem chip select, MCS.
The pin is switched to the modem chip select when the LD5 base address, COMbase, is first
programmed to non-zero through the PnP data or a hostload.
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CS4237B
Volume Control
The volume control pins are enabled by setting VCEN in the Hardware Configuration data,
Misc. Hardware Config. byte. The VCF1,0 bits in the Hardware Configuration data, Global
Configuration byte, set the format for the volume control pins. Each pin must have an external
pullup resistor (10kΩ) and either a momentary or toggle style switch based on format. Typically
a 100Ω series resistor and a capacitor to ground, capacitor on the switch side of the series
resistor, would be included on each pin for ESD protection and to help with EMI emissions.
UP - Volume Up
The SCS/UP pin is multiplexed with the external Synthesizer chip select. This pin is switched
to the UP function when VCEN is set. When UP is low, the master volume output for left and
right channels are incremented.
DOWN - Volume Down
The XCTL1/SINT/ACDCS/DOWN is a multiplexed pin that can be used as XCTL1, the
external FM synthesizer interrupt, the alternate CDROM chip select, or the Volume Down pin.
This pin is switched to the DOWN function when VCEN is set. When DOWN is low, the
master volume output for left and right channels are decremented.
MUTE - Volume Mute
The MUTE pin function can be toggle, momentary, or non-existent based on the VCF1,0 bits.
The MUTE function is enabled when VCEN is set.
Miscellaneous
XTALI - Crystal Input
This pin will accept either a crystal, with the other pin attached to XTALO, or an external
CMOS clock. XTAL must have a crystal or clock source attached for proper operation. The
crystal frequency must be 16.9344 MHz and designed for fundamental mode, parallel resonance
operation.
XTALO - Crystal Output
This pin is used for a crystal placed between this pin and XTALI. If an external clock is used
on XTALI, this pin must be left floating with no traces or components connected to it.
RESDRV - Reset Drive, Input
Places the part in lowest power consumption mode. All sections of the part are shut down and
consuming minimal power. The part is reset and in power down mode when this pin is logic
high. The falling edge also latches the state of XIOR and XIOW to determine the functionality
of dual mode pins. This signal is typically connected to the ISA bus signal RESDRV. RESDRV
must be asserted whenever the part is powered up to initialize the internal registers to a known
state. This pin, when high, also drives the BRESET pin low.
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VREF - Voltage Reference, Output
All analog inputs and outputs are centered around VREF which is nominally 2.1 Volts. This
pin may be used to level shift external circuitry, although any AC loads should be buffered.
REFFLT - Reference Filter, Input
Voltage reference used internal to the part. A 0.1 µF and a 1 µF (must not be bigger than 1 µF)
capacitor with short fat traces must be connected to this pin. No other connections should be
made to this pin.
LFILT - Left Channel Antialias Filter Input
This pin needs a 1000 pF NPO capacitor attached and tied to analog ground.
RFILT - Right Channel Antialias Filter Input
This pin needs a 1000 pF NPO capacitor attached and tied to analog ground.
TEST - Test
This pin must be tied to ground for proper operation.
Power Supplies
VA - Analog Supply Voltage
Supply to the analog section of the codec.
AGND - Analog Ground
Ground reference to the analog section of the codec. This pin should be placed on an analog
ground pin separate from other chip grounds.
VD1 - Digital Supply Voltage
Digital supply for the parallel data bus section of the codec.
DGND1 - Digital Ground
Digital ground reference for the parallel data bus section of the part. These pins are isolated
from the other grounds and should be connected to the digital ground section of the board (see
Figure 33).
VDF1, VDF2, VDF3, VDF4 - Digital Filtered Supply Voltage
Digital supply for the internal digital section of the codec (except for the parallel data bus).
These pins should be filtered, using a ferrite bead, from VD1.
SGND1, SGND2, SGND3, SGND4 - Substrate Ground
Substrate ground reference for the codec . These pins are connected to the substrate of the die.
Optimum layout is achieved by placing SGND1/2/3/4 on the digital ground plane with the
DGND pin as shown in Figure 33.
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CS4237B
PARAMETER DEFINITIONS
Resolution
The number of bits in the input words to the DACs, and in the output words in the ADCs.
Differential Nonlinearity
The worst case deviation from the ideal code width. Units in LSB.
Total Dynamic Range
TDR is the ratio of the RMS value of a full scale signal to the lowest obtainable noise floor. It
is measured by comparing a full scale signal to the lowest noise floor possible in the codec (i.e.
attenuation bits for the DACs at full attenuation). Units in dB.
Instantaneous Dynamic Range
IDR is the ratio of a full-scale RMS signal to the RMS noise available at any instant in time,
without changing the input gain or output attenuation settings. It is measured using S/(N+D)
with a 1 kHz, -60 dB input signal, with 60 dB added to compensate for the small input signal.
Use of a small input signal reduces the harmonic distortion components to insignificance when
compared to the noise. Units in dB.
Total Harmonic Distortion (THD)
THD is the ratio of the test signal amplitude to the RMS sum of all the in-band harmonics of
the test signal. THD is measured using an input signal which is 3dB below typical full-scale,
and referenced to typical full scale.
Interchannel Isolation
The amount of 1 kHz signal present on the output of the grounded input channel with 1 kHz
0 dB signal present on the other channel. Units in dB.
Interchannel Gain Mismatch
For the ADCs, the difference in input voltage that generates the full scale code for each
channel. For the DACs, the difference in output voltages for each channel with a full scale
digital input. Units in dB.
Offset Error
For the ADCs, the deviation in LSBs of the output from mid-scale with the selected input
grounded. For the DACs, the deviation in volts of the output from VREF with mid-scale input
code.
108
DS213PP4
CS4237B
PACKAGE PARAMETERS
D
100-pin TQFP - Package Code ’Q’
MIN
Symbol
Description
N
Lead Count
A
Overall Height
A1
0.00
Stand Off
0.14
Lead Width
b
Lead Thickness
0.077
c
Terminal Dimension 15.70
D
Package Body
D1
Terminal Dimension 15.70
E
Package Body
E1
0.40
Lead Pitch
e1
0.30
Foot Length
L1
0.0°
Lead Angle
T
D1
E1
100
E
1
L1
e1
b
c
T
A1
DS213PP4
A
NOM
100
MAX
1.66
0.20
0.127
16.00
14.0
16.00
14.0
0.50
0.50
0.26
0.177
16.30
16.30
0.60
0.70
12.0°
Notes:
1) Dimensions in millimeters.
2) Package body dimensions do not include mold protrusion,
which is 0.25 mm.
3) Coplanarity is 0.004 in.
4) Lead frame material is AL-42 or copper, and lead finish
is solder plate.
5) Pin 1 identification may be either ink dot or dimple.
6) Package top dimensions can be smaller than bottom
dimensions by 0.20 mm.
7) The "lead width with plating" dimension does not include
a total allowable dambar protrusion of 0.08 mm (at
maximum material condition).
8) Ejector pin marks in molding are present on every package.
109
CS4237B
APPENDIX A: TYPICAL MOTHERBOARD E2PROM DATA
; EEPROM Validation Bytes
DB
055H, 0BBH
DB
DB
; EEPROM Validation Bytes: CS4237B
001H
00FH
; EEPROM data length upper byte
; lower byte, Listed Size = 271
; Hardware
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
DB
Configuration Data
000H
003H
080H
080H
00BH
020H
004H
008H
010H
080H
000H
000H
;
;
;
;
;
;
;
;
;
;
;
;
ACDbase Addr. Mask Length = 1 bytes
COMbase Addr. Mask Length = 4 bytes
MCB: IHCD
GCB1: IFM
Code Base Byte
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
; Hardware
DB
DB
DB
DB
DB
DB
DB
Mapping Data
000H
048H
075H
0B9H
0FCH
010H
003H
;
;
;
;
;
;
;
00=4/08=8 peripheral
RESERVED
IRQ selection A & B
IRQ selection C & D
IRQ selection E & F
DMA selection A & B
DMA selection C
port size, XCTL0/XA2
-
B= 7,
D=11,
F=15,
B= 1,
A=5
C=9
E=12
A=0
C=3
; PnP Resource Header - PnP ID for CS4237B IC, OEM ID = 42
DB
00EH, 063H, 042H, 037H, 0FFH,0FFH,0FFH,0FFH,030H ; CSC4237 FFFFFFFF
DB
00AH, 010H, 001H
; PnP version 1.0, Vender version 0.1
DB
082H, 009H, 000H, ’CMB4237B’, 000H ; ANSI ID
; LOGICAL DEVICE 0 (Windows Sound System & SBPro)
DB
015H, 00EH, 063H, 000H, 000H, 000H ; EISA ID: CSC0000
DB
DB
DB
DB
DB
DB
DB
DB
082H,
031H,
02AH,
02AH,
022H,
047H,
047H,
047H,
007H,
000H
002H,
009H,
020H,
001H,
001H,
001H,
DB
DB
DB
DB
031H,
02AH,
02AH,
022H,
001H
00AH, 028H
00BH, 028H
0A0H, 09AH
110
000H, ’WSS/SB’, 000H ; ANSI ID
; DF Best Choice
028H
; DMA: 1 - WSS & SBPro
028H
; DMA: 0,3 - WSS & SBPro
000H
; IRQ: 5 Interrupt Select
034H, 005H, 034H, 005H, 004H, 004H ;16b
088H, 003H, 088H, 003H, 008H, 004H ;16b
020H, 002H, 020H, 002H, 020H, 010H ;16b
capture
0
WSSbase: 534
SYNbase: 388
SBbase: 220
; DF Acceptable Choice 1
; DMA: 1,3 - WSS & SBPro
; DMA: 0,1,3 - WSS & SBPro capture
; IRQ: 5,7,9,11,12,15 Interrupt Select 0
DS213PP4
CS4237B
DB
DB
DB
047H, 001H, 034H, 005H, 0FCH, 00FH, 004H, 004H ;16b WSSbase: 534-FFC
047H, 001H, 088H, 003H, 088H, 003H, 008H, 004H ;16b SYNbase: 388
047H, 001H, 020H, 002H, 060H, 002H, 020H, 010H ;16b SBbase: 220-260
DB
DB
DB
DB
DB
DB
031H,
02AH,
022H,
047H,
047H,
047H,
DB
038H
002H
00BH,
0A0H,
001H,
001H,
001H,
; DF Suboptimal Choice 1
028H
; DMA: 0,1,3 - WSS & SBPro
09AH
; IRQ: 5,7,9,11,12,15 Interrupt Select 0
034H, 005H, 0FCH, 00FH, 004H, 004H ;16b WSSbase: 534-FFC
088H, 003H, 0F8H, 003H, 008H, 004H ;16b SYNbase: 388-3F8
020H, 002H, 000H, 003H, 020H, 010H ;16b SBbase: 220-300
; End of DF for Logical Device 0
; LOGICAL DEVICE 1 (Game Port)
DB
015H, 00EH, 063H, 000H, 001H, 000H ; EISA ID: CSC0001
DB
DB
DB
082H, 005H, 000H, ’GAME’, 000H ; ANSI ID
031H, 000H
; DF Best Choice
047H, 001H, 000H, 002H, 000H, 002H, 008H, 008H ;16b GAMEbase: 200
DB
DB
031H, 001H
; DF Acceptable Choice 1
047H, 001H, 008H, 002H, 008H, 002H, 008H, 008H ;16b GAMEbase: 208
DB
038H
; End of DF for Logical Device 1
; LOGICAL DEVICE 2 (Control)
DB
015H, 00EH, 063H, 000H, 010H, 000H ; EISA ID: CSC0010
DB
DB
082H, 005H, 000H, ’CTRL’, 000H ; ANSI ID
047H, 001H, 020H, 001H, 0F8H, 00FH, 008H, 008H ;16b CTRLbase: 120-FF8
; LOGICAL DEVICE 3 (MPU-401)
DB
015H, 00EH, 063H, 000H, 003H, 000H ; EISA ID: CSC0003
DB
DB
DB
DB
082H,
031H,
022H,
047H,
DB
DB
DB
031H, 001H
; DF Acceptable Choice 1
022H, 000H, 09AH
; IRQ: 9,11,12,15 Interrupt Select 0
047H, 001H, 030H, 003H, 060H, 003H, 008H, 002H ;16b MPUbase: 330-360
DB
DB
031H, 002H
; DF Suboptimal Choice 1
047H, 001H, 030H, 003H, 0E0H, 003H, 008H, 002H ;16b MPUbase: 330-3E0
DB
038H
DB
079H, 09FH
DS213PP4
004H, 000H, ’MPU’, 000H ; ANSI ID
000H
; DF Best Choice
000H, 002H
; IRQ: 9 Interrupt Select 0
001H, 030H, 003H, 030H, 003H, 008H, 002H ;16b MPUbase: 330
; End of DF for Logical Device 3
; End of Resource Data, Checksum
111
CS4237B
APPENDIX B: DIFFERENCES BETWEEN THE CS4236 AND THE CS4237B
This part is designed to be hardware and software backwards compatible with the CS4236 and will
drop into an existing CS4236 socket without any hardware modifications. Properly written code for the
CS4236 will run on the this Codec. However, the CS4237B has enhancements over the CS4236 that
provide extra functionality.
The differences are as follows:
1. CTRLbase+3 is redefined to be an indirect address register and CTRLbase+4 is redefined to be an
indirect data register. These registers allows access to C0 through C8 indirect registers.
2. CDSDD in the Global Configuration byte of the Hardware Configuration data has been renamed
SDD and its function expanded. On this part, setting SDD disables peripheral port reads from driving the ISA data bus for ALL peripheral port devices, e.g. CDROM and MODEM. On the CS4236,
setting CDSDD disables peripheral port reads for the CDROM device ONLY.
3. The Serial Port works continuously once enabled. CEN and PEN do not have any effect on the serial port. On the CS4236, CEN and PEN disabled their respective part of the serial port when set to
zero.
4. The GAME Logical Device (Joystick) only aliases from GAMEbase+0 to GAMEbase+5. GAMEbase+6 and GAMEbase+7 are reserved. This Codec also contains support for Digital Assist of
analog joysticks to support the Microsoft Direct Input initiative.
5. I25 was defined as a Version and Chip ID register in the CS4236. This register is now redefined as
a Compatibility register and is identical to the CS4236 to allow software written to the CS4236 to
work properly on this part. The Version and Chip ID for this chip has been moved to Control indirect register C1 and WSS indirect register X25 (Revision C or greater).
6. I27 and I29 in the WSS space are reserved.
7. When IFM is enabled (and remapping is enabled) I18/I19 return the same value written when mute
is enabled. On the CS4236, I18/19 returns 0xBF when mute is enabled.
8 The OLB bit in I16 is no longer functional and internally is set as if OLB is on.
9. The MIC input impedance is now 8 kΩ minimum.
112
DS213PP4
CS4237B
The added features over the CS4236 are as follows:
10. SRS 3D Sound Technology is added and is controlled through C2 and C3 registers.
11. A Wavetable Serial Port interface is added for connection to the CS9236 Single-Chip Wavetable
Music Synthesizer. The pins are multiplexed with the XD7-XD5 pins and are controlled by the
WTEN bit in C8 or the Global Configuration byte in the Hardware Configuration data.
12. The DSP serial port can be multiplexed to the XD4-XD1 pins to allow the DSP serial port and the
second joystick to be used simultaneously. The multiplexing is controlled by the SPS bit in C8 or
the Global Configuration byte in the Hardware Configuration data.
13. Hardware volume control supports 4 formats.
14. New bits are added to the Global Configuration byte of the Hardware Configuration data:
VCF1 and VCF0 Hardware Volume Control Format bits
SLAD which disables Sound Blaster Synthesis volume changes from affecting LINE volume.
WTEN to enable the Wavetable Serial Port
SPS to switch the DSP serial port pins from the second joystick to the XD4-XD1 pins
15. The Consumer digital audio transmission format supported on the DSP serial port through the C4C6 registers is new.
16. Serial Port Format 3 (I16) is a new DSP serial port format.
17. A symmetrical mixer (the input mixer is new) is included and is supported by a new mode,
MODE 3. This mode is enabled by setting the CMS1,0 bits in WSS I12 to 11. Note that the
CS4236 MODE2 bit has been renamed CMS1 (Codec Mode Select 1). CMS1 is backwards compatible with the CS4236 MODE2 bit.
18. The MIC can be mixed directly to the output mixer with full volume control.
19. Hardware Configuration byte 9 was reserved in the CS4236 (at 0x43) and is now used as a Code
Base Byte that determines the firmware code compatibility in the E2PROM. When firmware code
for this part is loaded in the E2PROM this byte must be changed to 0x0B. This provides backwards
compatibility by ignoring CS4236-based firmware code, which has this byte set to 0x43, while still
reading the Hardware Configuration and PnP data from CS4236-programmed E2PROM.
20. 3.3 Volt ISA bus support is added. This includes all ISA pins except DRQA (which still runs at
5 Volts). When the VD1 pin is powered from a 3.3 Volt supply, the ISA bus connected to it must
also run at 3.3 Volts.
DS213PP4
113
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