88F619x Hardware Specifications

88F619x Hardware Specifications

Cover

88F6190 and 88F6192

Integrated Controller

Hardware Specifications

Marvell.

Moving Forward Faster

Doc. No. MV-S104987-U0, Rev. F

December 2, 2008, Preliminary

L

Document Classification: Proprietary Information

88F619x

Hardware Specifications

Document Conventions

Note: Provides related information or information of special importance.

Caution: Indicates potential damage to hardware or software, or loss of data.

Warning: Indicates a risk of personal injury.

Document Status

Doc Status: Preliminary Technical Publication: 0.xx

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Doc. No. MV-S104987-U0 Rev. F

Page 2 Document Classification: Proprietary Information

Copyright © 2008 Marvell

December 2, 2008, Preliminary

88F6190 and 88F6192

Integrated Controller

Hardware Specifications

PRODUCT OVERVIEW

The Marvell

®

88F6190 and 88F6192 are high-performance, highly integrated controllers. These controllers are based on the Marvell proprietary, ARMv5TE-compliant, high-speed Sheeva

CPU core. The CPU core integrates a 256 KB

L2 cache.

JTAG interface

Processor

Sheeva™

CPU Core

16 KB-I, 16 KB-D cache

Up to 600 MHz

L2 cache

256 KB

High Speed I/0

PCI Express PCI Express x1

External DDR

400 MHz

Memory

DDR

SDRAM controller

SATA

USB 2.0

SATA port

USB 2.0 port

Security Engine

AES/DES/

3DES

SHA-1/MD5

XOR Engine

4 XOR/DMA channels

Misc

Gigabit Ethernet

IEEE 1588AVB support

Gigabit Ethernet

Fast Ethernet

SPI, NAND, SDIO

UART x2

GPIO, TWSI

Flash, SDIO

88F6190 Functional Block Diagram

Copyright © 2008 Marvell

December 2, 2008, Preliminary Document Classification: Proprietary Information

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Page 3

88F619x

Hardware Specifications

JTAG interface

External DDR

400 M Hz

FXS / FXO

SPI, NAND , SDIO

Processor

Sheeva™

CPU Core

16 KB-I, 16 KB-D cache

Up to 800 M Hz

L2 cache

256 KB

High Speed I/0

PCI Express

SATA

USB 2.0

M em ory

DDR

SDR AM controller

Security Engine

AES/DES/

3DES

SHA-1/M D 5

XO R Engine

4 XO R/DM A channels

M isc

TDM

UART x2

G PIO , TW SI

Flash, SDIO

M edia interfaces

M PEG TS

Audio

G igabit Ethernet

IEEE 1588AVB support

88F6192 Functional Block Diagram

G bE

G bE

PCI Express x1

Dual SATA ports

USB 2.0 port

M PEG 2-TS

I

2

S / S/PDIF

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Copyright © 2008 Marvell

December 2, 2008, Preliminary

Features

FEATURES

88F6190 – Incorporates a single GbE port and a single

SATA port. CPU speed is up to 600 MHz.

88F6192 – Incorporates two GbE ports and two SATA ports. CPU speed is up to 800 MHz. It also supports a

Sony/Philips Digital Interconnect Format / Integrated

Interchip Sound (S/PDIF / I

2

S) Audio interface, a TDM

SLIC/SLAC Codec interface, and an MPEG Transport

Stream (TS) interface.

„

„

The 88F6190 and 88F6192 controllers include:

High-performance CPU core, running at up to

600 MHz in the 88F6190 or 800 MHz in the

88F6192, with integrated, four-way, set-associative

L1 16-KB I-cache/16-KB D-cache and unified,

256-KB, four-way, set-associative L2 cache

High-bandwidth dual-port DDR2 memory interface

(16-bit DDR2 SDRAM @ up to 400 MHz data rate)

PCI Express (x1) port with integrated PHY

Gigabit Ethernet (10/100/1000 Mbps) MAC(s)

USB 2.0 port with integrated PHY

SATA 2.0 port(s) with integrated 3 Gbps SATA II PHY

Security Cryptographic engine

S/PDIF / I

2

S Audio in/out interface (88F6192 only)

SD/SDIO/MMC interface

TDM SLIC/SLAC Codec interface (88F6192 only)

Two XOR engines, each containing two XOR/DMA channels (a total of four XOR/DMA channels)

MPEG Transport Stream (TS) interface

(88F6192 only)

SPI port with SPI flash boot support

8-bit NAND flash interface with boot support

Two 16550 compatible UART interfaces

TWSI port

36 multi-purpose pins

Internal Real Time Clock (RTC)

Interrupt controller

Timers

128-bit eFuse (one-time programmable memory)

Sheeva

CPU core

88F6190 – Up to 600 MHz

88F6192 – Up to 800 MHz

32-bit and 16-bit RISC architecture

Compliant with v5TE architecture, as published in the ARM Architect Reference Manual, Second

Edition

Includes MMU to support virtual memory features

256-KB, four-way, set-associative L2 unified cache

16-KB, four-way, set-associative I-cache

16-KB, four-way, set-associative D-cache

64-bit internal data bus

„

„

„

„

Branch Prediction unit

Supports JTAG/ARM ICE

Supports both Big and Little Endian modes

DDR2 SDRAM controller

16-bit interface

Up to 200 MHz clock frequency (400 MHz data rate)

DDR SDRAM with a clock ratio of 1:N and 2:N between the DDR SDRAM and the CPU core, respectively

SSTL 1.8V I/Os

Auto calibration of I/Os output impedance

Supports two DRAM chip selects

Supports all DDR devices densities up to1 Gb

Supports up to16 open pages (page per bank)

Up to 512 MB total address space

Supports on-board DDR designs (no DIMM support)

Supports 2T mode, to enable high-frequency operation under heavy load configuration

Supports DRAM bank interleaving

Supports up to a 128-byte burst per single memory access

PCI Express interface (x1)

PCI Express Base 1.1 compatible

Integrated low-power SERDES PHY, based on proven Marvell ® SERDES technology

Serves as a Root Complex or an Endpoint port

x1 link width

2.5 Gbps data rate

Lane polarity reversal support

Maximum payload size of 128 bytes

Single Virtual Channel (VC-0)

Replay buffer support

Extended PCI Express configuration space

Advanced Error Reporting (AER) support

Power management: L0s and software L1 support

Interrupt emulation message support

Error message support

PCI Express master specific features

Single outstanding read transaction

Maximum read request of up to 128 bytes

Maximum write request of up to 128 bytes

Up to four outstanding read transactions in

Endpoint mode

PCI Express target specific features

Supports up to eight read request transactions

Maximum read request size of 4 KB

Maximum write request of 128 bytes

Copyright © 2008 Marvell

December 2, 2008, Preliminary Document Classification: Proprietary Information

Doc. No. MV-S104987-U0 Rev. F

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88F619x

Hardware Specifications

„

„

„

„

Supports PCI Express access to all of the controller’s internal registers

Integrated GbE (10/100/1000) MAC port(s)

88F6190 – One GbE port and one Fast Ethernet port

88F6192 – Two GbE ports

Supports 10/100/1000 Mbps

Dedicated DMA for data movement between memory and port

Priority queuing on receive based on Destination

Address (DA), VLAN Tag, and IP TOS

Layer 2/3/4 frame encapsulation detection

TCP/IP checksum on receive and transmit

Supports proprietary 200 Mbps Marvell MII (MMII) interface

88F6190 supports the following modes:

-

Port 0 RGMII, Port 1 MII/MMII

-

Port 0 GMII, Port 1 N/A

88F6192 supports the following modes:

-

Port 0 RGMII, Port 1 RGMII

-

Port 0 RGMII, Port 1 MII/MMII

-

Port 0 MII/MMII, Port 1 RGMII

-

Port 0 GMII, Port 1 N/A

DA filtering

Precise Timing Protocol (PTP)

Supports precise time stamping for packets, as defined in IEEE 1588 PTP v1 and v2 and IEEE

802.1AS draft standards

Supports Flexible Time Application interface to distribute PTP clock and time to other devices in the system

Optionally accepts an external clock input for time stamping

Audio Video Bridging networks

Supports IEEE 802.1Qav draft Audio Video

Bridging networks

Supports time- and priority-aware egress pacing algorithm to prevent bunching and bursting effects—suitable for audio/video applications

Supports Egress Jitter Pacer for AVB-Class A and

AVB-Class B traffic and strict priority for legacy traffic queues

USB 2.0 port

Serves as a peripheral or host

USB 2.0 compliant

Integrated USB 2.0 PHY

Enhanced Host Controller Interface (EHCI) compatible as a host

As a host, supports direct connection to all peripheral types (LS, FS, HS)

As a peripheral, connects to all host types (HS, FS) and hubs

„

„

„

Up to four independent endpoints, supporting control, interrupt, bulk, and isochronous data transfers

Dedicated DMA for data movement between memory and port

Integrated Marvell 3 Gbps (Gen2i) SATA PHYs

88F6190 – Single SATA port

88F6192 – Two SATA ports

Compliant with SATA II Phase 1 specifications

-

Supports SATA II Native Command Queuing

(NCQ), up to 128 outstanding commands per port

-

Fully supports first party DMA (FPDMA)

-

Backwards compatible with SATA I devices

Supports SATA II Phase 2 advanced features

-

3 Gbps (Gen2i) SATA II speed

-

Port Multiplier (PM)—performs FIS-based switching, as defined in SATA working group PM definition

-

Port Selector (PS)—issues the protocol-based

Out-Of-Band (OOB) sequence, for selecting the active host port

Supports device 48-bit addressing

Supports ATA Tag Command Queuing

SATA II Host controller

Enhanced-DMA (EDMA) for the SATA ports

Automatic command execution, without host intervention

Command queuing support, for up to 32 outstanding commands

Separate SATA request/response queues

64-bit addressing support for descriptors and data buffers in system memory

Read ahead

Advanced interrupt coalescing

Target mode operation—supports attaching two

88F6190/88F6192 controllers through their

Serial-ATA ports, enabling data communication between the 88F6190/88F6192 controllers

Advanced drive diagnostics via the ATA SMART command

Cryptographic engine

Hardware implementation on encryption and authentication engines, to boost packet processing speed

Dedicated DMA to feed the hardware engines with data from the internal SRAM memory or from the

DDR memory

Implements AES, DES, and 3DES encryption algorithms

Implements SHA1 and MD5 authentication algorithms

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Copyright © 2008 Marvell

December 2, 2008, Preliminary

Features

„

S/PDIF / I

2

S Audio In/Out interface (88F6192 only)

Either S/PDIF or I

2

S inputs can be active at one time

Both S/PDIF and I

2

S outputs can be active simultaneously, transferring the same PCM data

„

„

„

„

„

„

S/PDIF-specific features (88F6192 only)

Compliant with 60958-1, 60958-3, and IEC61937 specifications

Sample rates of 44.1/48/96 kHz

16/20/24-bit depths

I

2

S-specific features (88F6192 only)

Sample rates of 44.1/48/96 kHz

I

2

S input and I

2

S output operate at the same sample rate

16/24-bit depths

I

2

S in and I

2

S out support independent bit depths

(16 bit/24 bit)

Supports plain I

2

S, right-justified and left-justified formats

SD/SDIO/MMC host interface

1-bit/4-bit SDmem, SDIO, and MMC cards

Up to 50 MHz

Hardware generate/check CRC, on all command and data transactions on the card bus

TDM SLIC/SLAC Codec interface (88F6192 only)

Generic interface to standard SLIC/SLAC codec devices

Compatible with standard PCM highway formats

TDM protocol support for two channels, up to

128 time slots

Dedicated SPI interface for codec management

Integrated DMA to transfer voice data to/from memory buffer

Two XOR engines and DMA

Two XOR/DMA channels per XOR engine (for a total of four XOR/DMA channels)

Chaining via linked-lists of descriptors

Moves data from source interface to destination interface

Supports increment or hold on both Source and

Destination Addresses

Supports XOR operation, on up to eight source blocks—useful for RAID applications

Supports iSCSI CRC-32 calculation

NAND flash controller

8-bit NAND flash interface

Glueless interface to CE Care and CE Don’t Care

NAND flash devices

Boot support

„

„

„

„

„

„

„

„

„

„

Serial Peripheral Interface (SPI) controller

Up to 41.6 MHz clock

Supports direct boot from external SPI serial flash memory

MPEG Transport Stream (TS) interface (88F6192 only)

ISO/IEC 13818-1 standard compliant

Supports any one of the following modes:

-

Parallel (8 bit) input

-

Parallel output

-

Two independent serial interfaces

Data rate up to 80 Mbps

Two UART interfaces

16550 UART compatible

Two pins for transmit and receive operations

Two pins for modem control functions

Two-Wire Serial Interface (TWSI)

General purpose TWSI master/slave port

Can also be used for serial ROM initialization

36 dedicated Multi-Purpose Pins (MPPS) for peripheral functions and general purpose I/O

Each pin can be configured independently.

GPIO inputs can be used to register interrupts from external devices, and to generate maskable interrupts.

In the 88F6192, one of the following multiplexed interfaces may be configured at a time:

-

Audio

-

TS

-

TDM

-

GbE Port 0 in GMII mode or GbE Port 1

Interrupt Controller

Maskable interrupts to CPU core

(and PCI Express for a PCI Express endpoint)

Two general purpose 32-bit timers/counters

Internal architecture

Mbus-L bus for high-performance, low-latency CPU core to DDR SDRAM connectivity

Advanced Mbus architecture

Dual port DDR SDRAM controller connectivity to both CPU and Mbus

Bootable from

SPI flash

SATA device

NAND flash

PCI Express

UART (for debug purpose)

216-pin LQFP package, 24 x 24 mm, 0.4 mm pitch

Copyright © 2008 Marvell

December 2, 2008, Preliminary Document Classification: Proprietary Information

Doc. No. MV-S104987-U0 Rev. F

Page 7

88F619x

Hardware Specifications

Hard Disk

Drive

PCI Express

Mini Card Wi-Fi

USB Host x1

88F6190 x16 On Board DDR2

SPI Flash

Gigabit

Ethernet

PHY

88F6190 Usage Model Example: Common NAS Application

SATA Port

Multiplier

Hard Disk

Drive

PCI Express

Mini Card Wi-Fi

USB Host x1

88F6192 x16

On Board DDR2

SPI Flash

Gigabit

Ethernet

PHY

88F6192 Usage Model Example: Common NAS Application

Doc. No. MV-S104987-U0 Rev. F

Page 8 Document Classification: Proprietary Information

Copyright © 2008 Marvell

December 2, 2008, Preliminary

Table of Contents

Table of Contents

3

4

5

6

6.1

6.2

6.3

1

2

2.1

2.2

2.3

7

7.1

8

8.1

8.2

8.3

8.4

8.5

8.6

8.7

Product Overview ....................................................................................................................................... 3

Features....................................................................................................................................................... 5

Preface....................................................................................................................................................... 16

About this Document .......................................................................................................................................16

Related Documentation...................................................................................................................................16

Document Conventions ...................................................................................................................................17

Overview....................................................................................................................................... 18

Pin and Signal Descriptions ....................................................................................................... 20

Pin Logic .........................................................................................................................................................21

Pin Descriptions ..............................................................................................................................................23

Internal Pull-up and Pull-down Pins ................................................................................................................55

Unused Interface Strapping........................................................................................................ 56

88F6190 Pinout ............................................................................................................................ 57

88F6192 Pinout ............................................................................................................................ 59

Pin Multiplexing ........................................................................................................................... 61

Multi-Purpose Pins Functional Summary ........................................................................................................61

Gigabit Ethernet (GbE) Pins Multiplexing on MPP ..........................................................................................68

TSMP (TS Multiplexing Pins) on MPP.............................................................................................................70

Clocking ....................................................................................................................................... 71

Spread Spectrum Clock Generator (SSCG)....................................................................................................72

System Power Up/Down and Reset Settings ............................................................................ 73

Power-Up/Down Sequence Requirements......................................................................................................73

Hardware Reset ..............................................................................................................................................74

PCI Express Reset ..........................................................................................................................................76

Sheeva

CPU TAP Controller Reset..............................................................................................................76

Pins Sample Configuration..............................................................................................................................76

Serial ROM Initialization ..................................................................................................................................80

Boot Sequence................................................................................................................................................81

Copyright © 2008 Marvell

December 2, 2008, Preliminary Document Classification: Proprietary Information

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88F619x

Hardware Specifications

10

10.1

10.2

10.3

10.4

10.5

10.6

10.7

11

12

13

13.1

13.2

A

9

9.1

9.2

9.3

9.4

9.5

JTAG Interface ............................................................................................................................. 83

TAP Controller.................................................................................................................................................83

Instruction Register .........................................................................................................................................83

Bypass Register ..............................................................................................................................................84

JTAG Scan Chain ...........................................................................................................................................84

ID Register ......................................................................................................................................................84

Electrical Specifications (Preliminary) ......................................................................................85

Absolute Maximum Ratings ............................................................................................................................85

Recommended Operating Conditions .............................................................................................................87

Thermal Power Dissipation .............................................................................................................................89

Current Consumption ......................................................................................................................................91

DC Electrical Specifications ............................................................................................................................92

AC Electrical Specifications ............................................................................................................................97

Differential Interface Electrical Characteristics..............................................................................................127

Thermal Data (Preliminary) ....................................................................................................... 138

Package ...................................................................................................................................... 139

Part Order Numbering/Package Marking ................................................................................ 141

Part Order Numbering ...................................................................................................................................141

Package Marking ..........................................................................................................................................142

Revision History ........................................................................................................................ 143

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Page 10 Document Classification: Proprietary Information

Copyright © 2008 Marvell

December 2, 2008, Preliminary

List of Tables

List of Tables

1 Overview............................................................................................................................................ 18

Table 1: 88F6190 and 88F6192 Device Differences ......................................................................................18

2 Pin and Signal Descriptions ............................................................................................................ 20

Table 2: Pin Functions and Assignments Table Key ......................................................................................23

Table 3:

Table 4:

Table 5:

Table 6:

Interface Pin Prefix Codes ................................................................................................................23

Power Pin Assignments ....................................................................................................................25

Miscellaneous Pin Assignments .......................................................................................................27

DDR SDRAM Interface Pin Assignments .........................................................................................28

Table 7:

Table 8:

PCI Express Interface Pin Assignments ...........................................................................................30

SATA Port Interface Pin Assignment ................................................................................................31

Table 9: 88F6190 Gigabit Ethernet Interface Pin Assignments .....................................................................32

Table 10: 88F6192 Gigabit Ethernet Port0/1 Interface Pin Assignments ........................................................34

Table 11: Serial Management Interface (SMI) Pin Assignments ......................................................................39

Table 12: USB 2.0 Interface Pin Assignments..................................................................................................40

Table 13: JTAG Pin Assignment.......................................................................................................................41

Table 14: RTC Interface Pin Assignments........................................................................................................42

Table 15: NAND Flash Interface Pin Assignment .............................................................................................43

Table 16: MPP Interface Pin Assignment .........................................................................................................44

Table 17: Two-Wire Serial Interface (TWSI) Interface Pin Assignment ............................................................45

Table 18: UART Port 0/1 Interface Pin Assignment .........................................................................................46

Table 19: Audio (S/PDIF / I

2

S) Interface Signal Assignment ............................................................................47

Table 20: Serial Peripheral Interface (SPI) Interface Signal Assignment .........................................................48

Table 21: Secure Digital Input/Output (SDIO) Interface Signal Assignment.....................................................49

Table 22:

Time Division Multiplexing (TDM) Interface Signal Assignment .......................................................50

Table 23:

Transport Stream (TS) Interface Signal Assignment ........................................................................52

Table 24: Precise Timing Protocol (PTP) Interface Signal Assignment............................................................54

Table 25:

Internal Pull-up and Pull-down Pins ..................................................................................................55

3 Unused Interface Strapping ............................................................................................................. 56

Table 26: Unused Interface Strapping ..............................................................................................................56

4 88F6190 Pinout ................................................................................................................................. 57

Table 27: 88F6190 Pinout Sorted by Pin Number ............................................................................................58

5 88F6192 Pinout ................................................................................................................................. 59

Table 28: 88F6192 Pinout Sorted by Pin Number ............................................................................................60

6 Pin Multiplexing ................................................................................................................................ 61

Table 29: MPP Functionality .............................................................................................................................62

Table 30:

88F6190 MPP Function Summary....................................................................................................63

Table 31:

88F6192 MPP Function Summary....................................................................................................65

Copyright © 2008 Marvell

December 2, 2008, Preliminary Document Classification: Proprietary Information

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88F619x

Hardware Specifications

Table 32: 88F6190 Ethernet Ports Pins Multiplexing........................................................................................68

Table 33: 88F6192 Ethernet Ports Pins Multiplexing........................................................................................69

Table 34: TS Port Pin Multiplexing .................................................................................................................70

7 Clocking............................................................................................................................................. 71

Table 35: 88F619x Clocks ................................................................................................................................71

Table 36:

Supported Clock Combinations ........................................................................................................72

8 System Power Up/Down and Reset Settings ................................................................................. 73

Table 37: I/O and Core Voltages ......................................................................................................................73

Table 38: Reset Configuration ..........................................................................................................................77

9 JTAG Interface .................................................................................................................................. 83

Table 39: Supported JTAG Instructions............................................................................................................83

Table 40: IDCODE Register Map .....................................................................................................................84

10 Electrical Specifications (Preliminary) ........................................................................................... 85

Table 41: Absolute Maximum Ratings ..............................................................................................................85

Table 42: Recommended Operating Conditions...............................................................................................87

Table 43: Thermal Power Dissipation ...............................................................................................................89

Table 44: Current Consumption........................................................................................................................91

Table 45: General 3.3V Interface (CMOS) DC Electrical Specifications...........................................................92

Table 46: RGMII 1.8V Interface (CMOS) DC Electrical Specifications .............................................................93

Table 47: SDRAM DDR2 Interface DC Electrical Specifications ......................................................................94

Table 48: TWSI Interface 3.3V DC Electrical Specifications.............................................................................95

Table 49: SPI Interface 3.3V DC Electrical Specifications................................................................................95

Table 50: TDM Interface 3.3V DC Electrical Specifications..............................................................................96

Table 51: Reference Clock AC Timing Specifications ......................................................................................97

Table 52: SDRAM DDR2 Interface AC Timing Table .......................................................................................99

Table 53: RGMII 10/100/1000 AC Timing Table at 1.8V ................................................................................102

Table 54: RGMII 10/100 AC Timing Table at 3.3V .........................................................................................102

Table 55: GMII AC Timing Table ....................................................................................................................104

Table 56: MII/MMII MAC Mode AC Timing Table ...........................................................................................106

Table 57: SMI Master Mode AC Timing Table................................................................................................108

Table 58: JTAG Interface AC Timing Table ....................................................................................................110

Table 59: TWSI Master AC Timing Table .......................................................................................................112

Table 60: TWSI Slave AC Timing Table .........................................................................................................112

Table 61: S/PDIF AC Timing Table ................................................................................................................114

Table 62: Inter-IC Sound (I2S) AC Timing Table ............................................................................................116

Table 63: TDM Interface AC Timing Table .....................................................................................................118

Table 64: SPI (Master Mode) AC Timing Table ..............................................................................................120

Table 65: SDIO Host in High Speed Mode AC Timing Table .........................................................................122

Table 66: Transport Stream Output Interface AC Timing Table ....................................................................124

Table 67: Transport Stream Input Interface AC Timing Table ........................................................................124

Table 68: PCI Express Interface Differential Reference Clock Characteristics ..............................................127

Table 69: PCI Express Interface Spread Spectrum Requirements.................................................................128

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Copyright © 2008 Marvell

December 2, 2008, Preliminary

List of Tables

Table 70: PCI Express Interface Driver and Receiver Characteristics ...........................................................129

Table 71: SATA-I Interface Gen1i Mode Driver and Receiver Characteristics ...............................................132

Table 72: SATA-II Interface Gen2i Mode Driver and Receiver Characteristics ..............................................133

Table 73: USB Low Speed Driver and Receiver Characteristics ....................................................................134

Table 74: USB Full Speed Driver and Receiver Characteristics.....................................................................135

Table 75: USB High Speed Driver and Receiver Characteristics ...................................................................136

11 Thermal Data (Preliminary) ............................................................................................................ 138

Table 76: Thermal Data for the 88F619x in the QFP 216-pin Package (Preliminary) ....................................138

12

Package ........................................................................................................................................... 139

Table 77: LQFP 216-pin Package Dimensions...............................................................................................140

Table 78: LQFP 216-pin Package Exposed Pad (ePAD) Size .......................................................................140

13

Part Order Numbering/Package Marking...................................................................................... 141

Table 79: Part Order Options..........................................................................................................................141

A Revision History ............................................................................................................................. 143

Table 80: Revision History ..............................................................................................................................143

Copyright © 2008 Marvell

December 2, 2008, Preliminary Document Classification: Proprietary Information

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Page 13

88F619x

Hardware Specifications

List of Figures

1 Overview........................................................................................................................................... 18

2 Pin and Signal Descriptions ........................................................................................................... 20

Figure 1:

88F6190 Pin Logic Diagram .............................................................................................................21

Figure 2: 88F6192 Pin Logic Diagram .............................................................................................................22

3 Unused Interface Strapping ............................................................................................................ 56

4 88F6190 Pinout ................................................................................................................................ 57

Figure 3: 88F6190 Pin Map Top View .............................................................................................................57

5 88F6192 Pinout ................................................................................................................................ 59

Figure 4: 88F6192 Pin Map Top View .............................................................................................................59

6 Pin Multiplexing ............................................................................................................................... 61

7 Clocking............................................................................................................................................ 71

8 System Power Up/Down and Reset Settings ................................................................................ 73

Figure 5: Power-Up Sequence Example..........................................................................................................74

Figure 6: Serial ROM Data Structure ...............................................................................................................80

Figure 7: Serial ROM Read Example...............................................................................................................81

9 JTAG Interface ................................................................................................................................. 83

10 Electrical Specifications (Preliminary) .......................................................................................... 85

Figure 8: SDRAM DDR2 Interface Test Circuit ..............................................................................................100

Figure 9: SDRAM DDR2 Interface Write AC Timing Diagram .......................................................................100

Figure 10: SDRAM DDR2 Interface Address and Control AC Timing Diagram ...............................................101

Figure 11: SDRAM DDR2 Interface Read AC Timing Diagram .......................................................................101

Figure 12: RGMII Test Circuit ..........................................................................................................................103

Figure 13: RGMII AC Timing Diagram .............................................................................................................103

Figure 14: GMII Test Circuit .............................................................................................................................104

Figure 15: GMII Output AC Timing Diagram ....................................................................................................105

Figure 16: GMII Input AC Timing Diagram.......................................................................................................105

Figure 17: MII/MMII MAC Mode Test Circuit....................................................................................................106

Figure 18: MII/MMII MAC Mode Output Delay AC Timing Diagram.................................................................106

Figure 19: MII/MMII MAC Mode Input AC Timing Diagram..............................................................................107

Figure 20: MDIO Master Mode Test Circuit .....................................................................................................108

Figure 21: MDC Master Mode Test Circuit ......................................................................................................109

Figure 22: SMI Master Mode Output AC Timing Diagram ...............................................................................109

Figure 23: SMI Master Mode Input AC Timing Diagram ..................................................................................109

Figure 24: JTAG Interface Test Circuit ............................................................................................................110

Doc. No. MV-S104987-U0 Rev. F

Page 14 Document Classification: Proprietary Information

Copyright © 2008 Marvell

December 2, 2008, Preliminary

List of Figures

Figure 25: JTAG Interface Output Delay AC Timing Diagram .........................................................................111

Figure 26: JTAG Interface Input AC Timing Diagram ......................................................................................111

Figure 27: TWSI Test Circuit............................................................................................................................113

Figure 28: TWSI Output Delay AC Timing Diagram.........................................................................................113

Figure 29: TWSI Input AC Timing Diagram .....................................................................................................113

Figure 30: S/PDIF Test Circuit .........................................................................................................................115

Figure 31: Inter-IC Sound (I2S) Test Circuit ....................................................................................................116

Figure 32: Inter-IC Sound (I2S) Output Delay AC Timing Diagram .................................................................117

Figure 33: Inter-IC Sound (I2S) Input AC Timing Diagram ..............................................................................117

Figure 34: TDM Interface Test Circuit ..............................................................................................................119

Figure 35: TDM Interface Output Delay AC Timing Diagram...........................................................................119

Figure 36: TDM Interface Input Delay AC Timing Diagram..............................................................................119

Figure 37: SPI (Master Mode) Test Circuit ......................................................................................................120

Figure 38: SPI (Master Mode) Output AC Timing Diagram .............................................................................121

Figure 39: SPI (Master Mode) Input AC Timing Diagram ................................................................................121

Figure 40: Secure Digital Input/Output (SDIO) Test Circuit .............................................................................122

Figure 41: SDIO Host in High Speed Mode Output AC Timing Diagram .........................................................123

Figure 42: SDIO Host in High Speed Mode Input AC Timing Diagram............................................................123

Figure 43: Transport Stream Interface Test Circuit..........................................................................................125

Figure 44: Transport Stream Output Interface AC Timing Diagram ................................................................125

Figure 45: Transport Stream Input Interface AC Timing Diagram ...................................................................126

Figure 46: PCI Express Interface Test Circuit..................................................................................................130

Figure 47: Low/Full Speed Data Signal Rise and Fall Time ............................................................................136

Figure 48: High Speed TX Eye Diagram Pattern Template .............................................................................137

Figure 49: High Speed RX Eye Diagram Pattern Template.............................................................................137

11 Thermal Data (Preliminary) ........................................................................................................... 138

12

Package .......................................................................................................................................... 139

Figure 50: LQFP 216-pin Package and Dimensions........................................................................................139

13

Part Order Numbering/Package Marking..................................................................................... 141

Figure 51: Sample Part Number ......................................................................................................................141

Figure 52: Package Marking and Pin 1 Location .............................................................................................142

Copyright © 2008 Marvell

December 2, 2008, Preliminary Document Classification: Proprietary Information

Doc. No. MV-S104987-U0 Rev. F

Page 15

88F619x

Hardware Specifications

Preface

About this Document

This datasheet provides the hardware specifications for the 88F6190 and 88F6192 integrated controllers. The hardware specifications include detailed pin information, configuration settings, electrical characteristics and physical specifications.

This datasheet is intended to be the basic source of information for designers of new systems.

All feature descriptions and specifications described in this document refer to both controllers, unless otherwise specified.

In this document, the 88F6190 and 88F6192 are often referred to as “88F619x“ or “the device(s)”.

Related Documentation

The following documents contain additional information related to the 88F619x:

„

„

„

88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications,

Doc No. MV-S104860-U0

Sheeva

88SV131 ARM v5TE Processor Core with MMU and L1/L2 Cache Datasheet,

Doc No. MV-S104950-U0

Unified Layer 2 (L2) Cache for Sheeva

CPU Cores Addendum, Doc No. MV-S104858-U0

„

„

„

„

„

„

„

„

„

„

„

„

„

„

„

88F6180, 88F6190, 88F6192, and 88F6281 Functional Errata, Interface Guidelines, and

Restrictions, Doc No. MV-S501157-U0

88F6180, 88F6190, 88F6192, and 88F6281 Design Guide, Doc No. MV-S301398-00

1

AN-63: Thermal Management for Marvell Technology Products Doc No. MV-S300281-00

1

AN-179: TWSI Software Guidelines for Discovery™, Horizon™, and Feroceon

®

Devices,

Doc No. MV-S300754-00

1

AN-183: 88F5181 and 88F5281 Big Endian and Little Endian Support,

Doc No. MV-S300767-00

1

AN-249: Configuring the Marvell

®

SATA PHY to Transmit Predefined Test Patterns,

Doc No. MV-S301342-00

1

AN-260 System Power-Saving Methods for 88F6180, 88F6190, 88F6192, and 88F6281,

Doc No. MV-S301454-00

1

TB-227: Differences Between the 88F6190, 88F6192, and 88F6281 Stepping Z0 and A0,

Doc No. MV-S105223-00

1

White Paper, ThetaJC, ThetaJA, and Temperature Calculations, Doc No. MV-S700019-00

ARM Architecture Reference Manual, Second Edition

PCI Express Base Specification, Revision 1.1

Universal Serial Bus Specification, Revision 2.0, April 2000, Compaq, Hewlett-Packard, Intel,

Lucent, Microsoft, NEC, Philips

Enhanced Host Controller Interface Specification for Universal Serial Bus, Revision 0.95,

November 2000, Intel Corporation

ARC USB-HS OTG High-Speed Controller Core reference V 4.0.1

Federal Information Processing Standards (FIPS) 46-2 (Data Encryption Standard)

1. This document is a Marvell proprietary, confidential document, requiring an NDA and can be downloaded from the

Marvell Extranet.

Doc. No. MV-S104987-U0 Rev. F

Page 16 Document Classification: Proprietary Information

Copyright © 2008 Marvell

December 2, 2008, Preliminary

Preface

Document Conventions

„

„

„

„

„

„

„

„

„

FIPS 81 (DES Modes of Operation)

FIPS 180-1 (Secure Hash Standard)

FIPS draft - Advanced Encryption Standard (Rijndeal)

RFC 1321 (The MD5 Message-Digest Algorithm)

RFC 1851 – The ESP Triple DES Transform

RFC 2104 (HMAC: Keyed-Hashing for Message Authentication).

RFC 2405 – The ESP DES-CBC Cipher Algorithm With Explicit IV

IEEE standard, 802.3-2000 Clause 14

ANSI standard X3.263-1995

See the Marvell Extranet website for the latest product documentation.

Document Conventions

The following conventions are used in this document:

Signal Range

Active Low Signals #

State Names

A signal name followed by a range enclosed in brackets represents a range of logically related signals. The first number in the range indicates the most significant bit (MSb) and the last number indicates the least significant bit (LSb).

Example: DB_Addr[12:0]

An n letter at the end of a signal name indicates that the signal’s active state occurs when voltage is low.

Example: INTn

State names are indicated in italic font.

Example: linkfail

Register Naming

Conventions

Register field names are indicated by angle brackets.

Example: <RegInit>

Register field bits are enclosed in brackets.

Example: Field [1:0]

Register addresses are represented in hexadecimal format.

Example: 0x0

Reserved: The contents of the register are reserved for internal use only or for future use.

A lowercase <n> in angle brackets in a register indicates that there are multiple registers with this name.

Example: Multicast Configuration Register<n>

Reset Values

Abbreviations

Reset values have the following meanings:

0 = Bit clear

1 = Bit set

Kb: kilobit

KB: kilobyte

Mb: megabit

MB: megabyte

Gb: gigabit

GB: gigabyte

Numbering Conventions Unless otherwise indicated, all numbers in this document are decimal (base 10).

An 0x prefix indicates a hexadecimal number.

An 0b prefix indicates a binary number.

Copyright © 2008 Marvell

December 2, 2008, Preliminary Document Classification: Proprietary Information

Doc. No. MV-S104987-U0 Rev. F

Page 17

88F619x

Hardware Specifications

1

Overview

The Marvell

®

88F6190 and 88F6192 devices are high-performance, highly integrated controllers.

The devices are based on the ARMv5TE-compliant, high-speed Sheeva

88SV131 CPU core with

256 KB L2 cache.

Table 1

provides a list of the differences between the 88F6190 and 88F6192 devices.

Table 1: 88F6190 and 88F6192 Device Differences

Sheeva

CPU Core

8 8 F 6 1 9 0

Running at up to 600 MHz

L2 cache at up to 300 MHz

No

Time Division

Multiplexing

(SLIC/codec) Interface

Serial ATA II (SATA II)

Interface

Gigabit Ethernet

Interface

1 port

2 Ethernet ports

• Port0 RGMII, Port1 MII/MMII

• Port0 GMII, Port1 N/A

8 8 F 6 1 9 2

Running at up to 800 MHz

L2 cache at up to 400 MHz

Yes

1

2 ports

2 Ethernet ports

1

• Port0 RGMII, Port1 RGMII

• Port0 RGMII, Port1 MII/MMII

• Port0 MII/MMII, Port1 RGMII

• Port0 GMII, Port1 N/A

Yes

1

Audio S/PDIF / I2S

Interface

MPEG Video / Transport

Stream Interface (TS)

DDR SDRAM Interface

No

No Yes

1

• Up to 200 MHz clock frequency with an 400 MHz data rate

• Supports two DRAM chip selects

• Supports all DDR devices densities up to 1Gb

• Supports up to 16 open pages (page per bank)

• Up to 512 MB total address space

Yes

Yes

Yes

PCI Express Interface

USB 2.0 Interface

Cryptographic Engine and Security

Accelerator

XOR engine and DMA

Two-Wire Serial

Interface (TWSI)

UART Interface

NAND Flash Interface

SPI Serial Flash

Interface

SDIO Interface

Yes

1 port

2 ports

Yes

Yes

Yes

Doc. No. MV-S104987-U0 Rev. F

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Copyright © 2008 Marvell

December 2, 2008, Preliminary

Table 1: 88F6190 and 88F6192 Device Differences (Continued)

General-Purpose I/O

Port

Real-Time Clock (RTC)

8 8 F 6 1 9 0 8 8 F 6 1 9 2

36-bits

Yes

1. The following interfaces are multiplexed and only one of them may be selected at a time:

- Audio

- TS

- TDM

- GbE Port 0 in GMII mode

- GbE Port 1

For further details, see Section 6, Pin Multiplexing, on page 61

.

Overview

Copyright © 2008 Marvell

December 2, 2008, Preliminary Document Classification: Proprietary Information

Doc. No. MV-S104987-U0 Rev. F

Page 19

88F619x

Hardware Specifications

2

Pin and Signal Descriptions

This section provides a detailed description of the 88F6190 and 88F6192 device pin assignments and their functionality.

Doc. No. MV-S104987-U0 Rev. F

Page 20 Document Classification: Proprietary Information

Copyright © 2008 Marvell

December 2, 2008, Preliminary

Pin and Signal Descriptions

Pin Logic

2.1

Pin Logic

Figure 1: 88F6190 Pin Logic Diagram

VDD

VDDO

VDD_GE_A

VDD_GE_B

VDD_M

VSS

CPU_PLL_AVDD

CORE_PLL_AVDD

XTAL_AVDD

XTAL_AVSS

PEX_AVDD

SATA_AVDD

USB_AVDD

RTC_AVDD

SSCG_AVDD

VHV

MPP[35:0]

Power

MPP

NF_CLE

NF_ALE

NF_CEn

NF_REn

NF_WEn

NAND

Flash

JT_CLK

JT_TDI

JT_TDO

JT_TMS_CPU

JT_TMS_CORE

JT_RSTn

SATA_T_P

SATA_T_N

SATA_R_P

SATA_R_N

RTC_XIN

RTC_XOUT

JTAG

SATA

RTC

PCI Express

USB

Gigabit Ethernet

Misc.

SDRAM

REF_CLK_XIN

XOUT

SYSRSTn

TP

ISET

NC

PEX_CLK_P

PEX_CLK_N

PEX_TX_P

PEX_TX_N

PEX_RX_P

PEX_RX_N

PEX_ISET

USB_DP

USB_DM

GE_TXCLKOUT

GE_TXD[3:0]

GE_TXCTL

GE_RXD[3:0]

GE_RXCTL

GE_RXCLK

GE_MDC

GE_MDIO

M_CLKOUT

M_CLKOUTn

M_CKE

M_RASn

M_CASn

M_WEn

M_A[13:0]

M_BA[2:0]

M_CSn[1:0]

M_DQ[15:0]

M_DQS[1:0]

M_DQSn[1:0]

M_DM[1:0]

M_ODT

M_STARTBURST

M_STARTBURST_IN

M_PCAL

M_NCAL

Copyright © 2008 Marvell

December 2, 2008, Preliminary Document Classification: Proprietary Information

Doc. No. MV-S104987-U0 Rev. F

Page 21

NF_CLE

NF_ALE

NF_CEn

NF_REn

NF_WEn

JT_CLK

JT_TDI

JT_TDO

JT_TMS_CPU

JT_TMS_CORE

JT_RSTn

SATA0_T_P

SATA0_T_N

SATA0_R_P

SATA0_R_N

SATA1_T_P

SATA1_T_N

SATA1_R_P

SATA1_R_N

RTC_XIN

RTC_XOUT

88F619x

Hardware Specifications

Figure 2: 88F6192 Pin Logic Diagram

VDD

VDDO

VDD_GE_A

VDD_GE_B

VDD_M

VSS

CPU_PLL_AVDD

CORE_PLL_AVDD

XTAL_AVDD

XTAL_AVSS

PEX_AVDD

SATA0_AVDD

SATA1_AVDD

USB_AVDD

RTC_AVDD

SSCG_AVDD

VHV

MPP[35:0]

Power

MPP

NAND

Flash

JTAG

SATA0/1

RTC

Misc.

PCI Express

USB

Gigabit Ethernet

SDRAM

REF_CLK_XIN

XOUT

SYSRSTn

TP

ISET

PEX_CLK_P

PEX_CLK_N

PEX_TX_P

PEX_TX_N

PEX_RX_P

PEX_RX_N

PEX_ISET

USB_DP

USB_DM

GE_TXCLKOUT

GE_TXD[3:0]

GE_TXCTL

GE_RXD[3:0]

GE_RXCTL

GE_RXCLK

GE_MDC

GE_MDIO

M_CLKOUT

M_CLKOUTn

M_CKE

M_RASn

M_CASn

M_WEn

M_A[13:0]

M_BA[2:0]

M_CSn[1:0]

M_DQ[15:0]

M_DQS[1:0]

M_DQSn[1:0]

M_DM[1:0]

M_ODT

M_STARTBURST

M_STARTBURST_IN

M_PCAL

M_NCAL

NOTE: The GE_TXCLKOUT pin is an input only when used as the MII/MMII Transmit Clock (88F6192 only).

Doc. No. MV-S104987-U0 Rev. F

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Copyright © 2008 Marvell

December 2, 2008, Preliminary

Pin and Signal Descriptions

Pin Descriptions

2.2

For details about MPP configuration options see

Section 6.1, Multi-Purpose Pins Functional

Summary, on page 61

.

Pin Descriptions

This section details all the pins for the different interfaces providing a functional description of each pin and pin attributes.

Table 2<Default ¬¹ Font> defines the abbreviations and acronyms used in the pin description tables.

Table 2: Pin Functions and Assignments Table Key

DDR

GND

I

HCSL

I/O

O o/d

Te r m

[n]

<n>

Analog

Calib

CML

CMOS

Power

SSTL t/s

XXXn

D e f i n i t i o n

n - Represents the SERDES pair number

Represents port number when there are more than one ports

Analog Driver/Receiver or Power Supply

Calibration pad type

Common Mode Logic

Complementary Metal-Oxide-Semiconductor

Double Data Rate

Ground Supply

High-speed Current Steering Logic

Input

Input/Output

Output

Open Drain pin

The pin allows multiple drivers simultaneously (wire-OR connection).

A pullup is required to sustain the inactive value.

VDD Power Supply

Stub Series Terminated Logic for 1.8V

Tri-State pin n - Suffix represents an Active Low Signal

Table 3: Interface Pin Prefix Codes

I n t e r f a c e

Misc

DDR SDRAM

PCI Express

SATA

Gigabit Ethernet

P r e f i x

N/A

M_

PEX_

88F6190

SATA_

88F6192 – SATA0_, SATA1_

GE_

Copyright © 2008 Marvell

December 2, 2008, Preliminary Document Classification: Proprietary Information

Doc. No. MV-S104987-U0 Rev. F

Page 23

88F619x

Hardware Specifications

Table 3: Interface Pin Prefix Codes (Continued)

I n t e r f a c e P r e f i x

USB 2.0

JTAG

USB_

JT_

RTC RTC_

NAND Flash NF_

MPP

TWSI

UART

Audio

SPI

SDIO SD_

TDM TDM_

PTP PTP_

N/A

TW_

UA0_

UA1_

AU_

SPI_

Doc. No. MV-S104987-U0 Rev. F

Page 24 Document Classification: Proprietary Information

Copyright © 2008 Marvell

December 2, 2008, Preliminary

Pin and Signal Descriptions

Pin Descriptions

2.2.1

Power Supply Pins

Table 4

provides the voltage levels for the various interface pins. These do not include the analog power supplies for the PLLs or PHYs which are explicitly mentioned in the other pin description tables.

Table 4: Power Pin Assignments

P i n N a m e

VDD

VDDO

For the 88F6190 –

VDD_GE_A

I

I

I

I / O P i n

Ty p e

Power

Power

Power

For the 88F6190 –

VDD_GE_B

For the 88F6192 –

VDD_GE_A

For the 88F6192

VDD_GE_B

VDD_M

VSS

CPU_PLL_AVDD

CORE_PLL_AVDD

SSCG_AVDD

XTAL_AVDD

I

I

I

I

I

I

I

I

I Power

Power

Power

Power

GND

Power

Power

Power

Power

D e s c r i p t i o n

1.0V Digital core and CPU voltage

3.3V I/O power for MPP[19:0] and JTAG pins

1.8 or 3.3V I/O supply voltage for RGMII and SMI interfaces

3.3V I/O supply voltage for GMII and SMI interfaces

3.3V I/O supply voltage for SMI interface when operating in MII/MMII mode.

NOTE: When configure to RGMII mode at 3.3V, only 10/100 Mbps operation is supported.

3.3V I/O supply voltage for GMII and MII/MMII interfaces.

3.3V I/O supply voltage for MPP[35:20].

1.8V or 3.3V I/O supply voltage for RGMII and SMI interfaces

3.3V I/O supply voltage for GMII, MII/MMII, and SMI interfaces

NOTE: When configure to RGMII mode at 3.3V, only 10/100 Mbps operation is supported.

I/O power for MPP[35:20]

1.8V or 3.3V I/O supply voltage for RGMII interfaces

3.3V I/O supply voltage for GMII and MII/MMII interfaces

NOTE: When configure to RGMII mode at 3.3V, only 10/100 Mbps operation is supported.

1.8V I/O supply voltage for the DDR2 SDRAM interface

VSS

1.8V analog quiet power to CPU PLL

NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design

Guide

for power supply filtering recommendations.

1.8V analog quiet power to Core PLL

NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design

Guide for power supply filtering recommendations.

1.8V quiet power supply to the internal Spread Spectrum Clock

Generator

1.8V analog quiet power to on-chip clock inverter for supporting external crystal, and on-chip current reference for SATA and USB PHYs

NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design

Guide for power supply filtering recommendations.

Copyright © 2008 Marvell

December 2, 2008, Preliminary Document Classification: Proprietary Information

Doc. No. MV-S104987-U0 Rev. F

Page 25

88F619x

Hardware Specifications

Table 4: Power Pin Assignments (Continued)

P i n N a m e D e s c r i p t i o n

VHV I

I / O P i n

Ty p e

Power

PEX_AVDD

88F6190

SATA_AVDD

88F6192

SATA0_AVDD

SATA1_AVDD

USB_AVDD

RTC_AVDD

RTC_AVSS I

I

I

I

I

I Power

Power

Power

Power

Power

GND

I/O supply voltage for eFuse:

• 2.5V for eFuse burning only

• 1.0V for eFuse reading only

PCI Express PHY quiet power supply 1.8V

NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design

Guide for power supply filtering recommendations.

SATA II port quiet 3.3V power supply

NOTE: See 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide for power supply filtering recommendation.

SATA II port0/1 quiet 3.3V power supply

NOTE: See 88F6180, 88F6190, 88F6192, and 88F6281 Design Guide for power supply filtering recommendation.

USB 2.0 PHY quiet 3.3V power supply

NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281 Design

Guide for power supply filtering recommendation.

1.5V (via battery) or 1.8V (via the board) RTC interface voltage

RTC ground

Doc. No. MV-S104987-U0 Rev. F

Page 26 Document Classification: Proprietary Information

Copyright © 2008 Marvell

December 2, 2008, Preliminary

Pin and Signal Descriptions

Pin Descriptions

2.2.2

Miscellaneous Pin Assignment

The Miscellaneous signal list contains clock and reset, test, and related signals.

Table 5: Miscellaneous Pin Assignments

P i n N a m e

REF_CLK_XIN

XOUT

SYSRSTn

SYSRST_OUTn

PEX_RST_OUTn

TP

ISET

NC (88F6190 only)

I

I

I

I / O P i n

Ty p e

Analog

O

O

O

O

Analog

CMOS

CMOS

CMOS

Analog

Analog

P o w e r

R a i l

D e s c r i p t i o n

XTAL_AVDD Reference clock input from external oscillator or input from external crystal. Used as input to core, CPU, SATA, and USB

PLLs.

XTAL_AVDD XTAL_OUT

Feedback signal to external crystal.

When not used, leave this pin floating.

VDDO System reset

Main reset signal of the device clock. Used to reset all units to their initial state.

When in the reset state, most output pins are in Tri-State.

VDDO Reset request from the device to the board reset logic.

This pin is multiplexed on the MPP pins (see

Section 6, Pin

Multiplexing, on page 61 ).

VDDO Optional PCI Express Endpoint card reset output

This pin is multiplexed on the MPP pins (see

Section 6, Pin

Multiplexing, on page 61 ).

Analog Test Point for SATA, USB, and PCI Express interfaces

For internal use. Leave this pin unconnected.

Current reference for both the USB and SATA PHYs.

Terminate this pin with a 6.04 k

Ω

resistor, pulled down.

Reserved for Marvell

®

future usage.

Leave unconnected externally.

Copyright © 2008 Marvell

December 2, 2008, Preliminary Document Classification: Proprietary Information

Doc. No. MV-S104987-U0 Rev. F

Page 27

88F619x

Hardware Specifications

2.2.3

DDR SDRAM Interface Pin Assignments

Table 6: DDR SDRAM Interface Pin Assignments

P i n N a m e I / O P i n

Ty p e

O SSTL

P o w e r

R a i l

VDD_M

D e s c r i p t i o n

SDRAM Differential Clock Pair M_CLKOUT

M_CLKOUTn

M_CKE O SSTL VDD_M

M_RASn

M_CASn

M_WEn

M_A[13:0]

M_BA[2:0]

M_CSn[1:0]

M_DQ[15:0]

M_DQS[1:0],

M_DQSn[1:0]

M_DM[1:0]

M_ODT

O

O

O

O

O

O t/s

I/O t/s

I/O

O

O

SSTL

SSTL

SSTL

SSTL

SSTL

SSTL

SSTL

SSTL

SSTL

SSTL

VDD_M

VDD_M

VDD_M

VDD_M

VDD_M

VDD_M

VDD_M

VDD_M

VDD_M

VDD_M

Driven high to enable SDRAM clock.

Driven low when setting the SDRAM to Self-refresh mode.

SDRAM Row Address Select

Asserted to indicate an active ROW address driven on the

SDRAM address lines.

SDRAM Column Address Select

Asserted to indicate an active column address driven on the

SDRAM address lines.

SDRAM Write Enable

Asserted to indicate a write command to the SDRAM.

SDRAM Address

Driven during RASn and CASn cycles to generate—together with M_BA[2:0]—the SDRAM address.

Driven during M_RASn and M_CASn cycles to select one of the eight SDRAM virtual banks.

NOTE: If an SDRAM device does not support the BA[2] pin, leave the M_BA[2] unconnected.

SDRAM Chip Selects

Asserted to select a specific SDRAM Physical bank.

SDRAM Data Bus

Driven during write.

Driven by SDRAM during reads.

SDRAM Data Strobe

Driven by the 88F619x during write.

Driven by SDRAM during reads.

SDRAM Data Mask

Asserted by the 88F619x to select the specific byte out of the

16-bit data to be written to the SDRAM.

SDRAM On Die Termination control.

Driven high to connect the SDRAM on die termination.

Driven low to disconnect the SDRAM’s termination.

NOTE: For the recommended setting, refer to the 88F6180,

88F6190, 88F6192, and 88F6281 Design Guide.

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December 2, 2008, Preliminary

Pin and Signal Descriptions

Pin Descriptions

Table 6: DDR SDRAM Interface Pin Assignments (Continued)

P i n N a m e D e s c r i p t i o n

M_STARTBURST

I / O P i n

Ty p e

O SSTL

P o w e r

R a i l

VDD_M

I SSTL VDD_M

Start Burst

88F619x indication of starting a burst read transaction.

Asserted with the first M_CASn cycle of SDRAM access.

NOTE: Must be routed on board to the SDRAM, and back to the 88F619x as M_STARTBURST_IN. For the recommended length calculation for this routing and termination requirements, see the 88F6180, 88F6190,

88F6192, and 88F6281 Design Guide.

Start Burst Input M_START

BURST_IN

M_PCAL I Calib

M_NCAL I Calib

SDRAM interface P channel output driver calibration. Connect to VSS through a resistor. The resistor value can vary between 30–70 ohm.

NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281

Design Guide for the recommended values of the calibration resistors.

SDRAM interface N channel output driver calibration. Connect to M_VDD through a resistor. The resistor value can vary between 30–70 ohm.

NOTE: See the 88F6180, 88F6190, 88F6192, and 88F6281

Design Guide for the recommended values of the calibration resistors.

Copyright © 2008 Marvell

December 2, 2008, Preliminary Document Classification: Proprietary Information

Doc. No. MV-S104987-U0 Rev. F

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88F619x

Hardware Specifications

2.2.4

PCI Express Interface Pin Assignments

Table 7: PCI Express Interface Pin Assignments

P i n N a m e

PEX_CLK_P/N

PEX_TX_P/N

PEX_RX_P/N

PEX_ISET I

I

I / O P i n

Ty p e

I/O HCSL

O CML

CML

Analog

P o w e r

R a i l

D e s c r i p t i o n

PEX_AVDD PCI Express Reference Clock

100 MHz, differential

This clock can be configured as input or output according to the reset strap (see

Table 38, Reset Configuration, on page 77

).

NOTE: For Output mode, 50-ohm, pull-down resistors are required.

PEX_AVDD Transmit Lane

Differential pair of PCI Express transmit data

PEX_AVDD Receive Lane

Differential pair of PCI Express receive data

Current reference. Pull down to VSS through a 5 k

Ω

resistor.

See the 88F6180, 88F6190, 88F6192, and 88F6281 Design

Guide for the recommended resistor value.

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December 2, 2008, Preliminary

Pin and Signal Descriptions

Pin Descriptions

2.2.5

SATA Interface Pin Assignments

Table 8:

SATA Port Interface Pin Assignment

P i n N a m e I / O P i n

Ty p e

88F6190 – Single SATA Port

SATA_T_P/N

SATA_R_P/N

SATA_PRESENTn

I

O

O

P o w e r R a i l

CML

CML

SATA_AVDD

SATA_AVDD

CMOS VDD_GE_B

SATA_ACTn O CMOS VDD_GE_B

D e s c r i p t i o n

Transmit Data: Differential analog output of SATA II port

Receive Data: Differential analog input of SATA II port

When this signal is asserted there is an active link between the SATA II port and the external device (disk).

NOTE: This signal is multiplexed on the MPP pins (see

Section 6, Pin Multiplexing, on page 61 ).

When this signal is asserted, there is an active and used link between the SATA II port and the external device

(disk).

NOTE: This signal is multiplexed on the MPP pins (see

Section 6, Pin Multiplexing, on page 61 ).

88F6192 – SATA Ports 0 and 1

SATA0_T_P/N

SATA1_T_P/N

O CML

I CML SATA0_R_P/N

SATA1_R_P/N

SATA0_PRESENTn

SATA1_PRESENTn

O CMOS

SATA0/1_AVDD Transmit Data: Differential analog output of SATA II port0/1

SATA0/1_AVDD Receive Data: Differential analog input of SATA II port0/1

VDD_GE_B

SATA0_ACTn

SATA1_ACTn

O CMOS VDD_GE_B

When this signal is asserted there is an active link between the SATA II port and the external device (disk).

NOTE: These signals are multiplexed on the MPP pins

(see

Section 6, Pin Multiplexing, on page 61

).

When this signal is asserted, there is an active and used link between the SATA II port and the external device

(disk).

NOTE: These signals are multiplexed on the MPP pins

(see

Section 6, Pin Multiplexing, on page 61

).

Copyright © 2008 Marvell

December 2, 2008, Preliminary Document Classification: Proprietary Information

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Page 31

88F619x

Hardware Specifications

2.2.6

Gigabit Ethernet Port Interface Pin Assignments

For additional information about the Gigabit Ethernet port pin functions refer to

Section 6.2, Gigabit

Ethernet (GbE) Pins Multiplexing on MPP, on page 68

.

For the 88F6190, Table 9 lists the Gigabit Ethernet port interface pin assignments.

For the 88F6192, Table 10

lists the Gigabit Ethernet port interface pin assignments.

Table 9: 88F6190 Gigabit Ethernet Interface Pin Assignments

P i n N a m e I / O P i n

Ty p e

Dedicated Ethernet Pins

GE_TXCLKOUT t/s

O

CMOS

P o w e r

R a i l

D e s c r i p t i o n

GE_TXD[3:0]

GE_TXCTL

GE_RXD[3:0]

GE_RXCTL I

I t/s

O t/s

O

CMOS

CMOS

CMOS

CMOS

VDD_GE_A RGMII Transmit Clock

RGMII transmit reference output clock for GE_TXD[3:0] and

GE_TXCTL.

Provides 125 MHz, 25 MHz or 2.5 MHz clock.

Not used in MII/MMII mode.

GMII Transmit Clock

Provides the timing reference for the transfer of the transmit enable, transmit error and transmit data signals. This clock operates at 125 MHz.

VDD_GE_A RGMII Transmit Data

Contains the transmit data nibble outputs that run at double data rate with bits [3:0] driven on the rising edge of GE_TXCLKOUT and bits [7:4] driven on the falling edge.

GMII Transmit Data

Contains the transmit data nibble outputs.

VDD_GE_A RGMII Transmit Control

Transmit control synchronous to the GE_TXCLKOUT output rising/falling edge.

GE_TXEN is driven on the rising edge of GE_TXCLKOUT.

A logical derivative of transmit enable and transmit error is driven on the falling edge of GE_TXCLKOUT.

GMII Transmit Enable

Indicates that the packet is being transmitted to the PHY.

It Is synchronous to GE_TXCLKOUT.

VDD_GE_A RGMII Receive Data

Contains the receive data nibble inputs that are synchronous to

GE_RXCLK input rising/falling edge.

GMII Receive Data

Contains the receive data nibble inputs.

VDD_GE_A RGMII Receive Control

GE_RXCTL is presented on the rising edge of GE_RXCLK.

A logical derivative of receive data valid and receive data error is presented on the falling edge of RXCLK.

GMII Receive Data Valid.

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Pin and Signal Descriptions

Pin Descriptions

Table 9: 88F6190 Gigabit Ethernet Interface Pin Assignments (Continued)

P i n N a m e

GE_RXCLK I

I / O P i n

Ty p e

CMOS

P o w e r

R a i l

D e s c r i p t i o n

VDD_GE_A RGMII Receive Clock

The receive clock provides a 125 MHz, 25 MHz, or 2.5 MHz reference clock derived from the received data stream.

GMII Receive Clock

Provides the timing reference for the reception of the GE_RXDV, receive error and receive data signals. This clock operates at

125 MHz

Multiplexed Ethernet Pins

MPP[23:20]/

GE1[3:0] t/s

O

CMOS

MPP[27:24]/

GE1[7:4]

MPP[28]/GE1[8]

MPP[29]/GE1[9]

MPP[30]/GE1[10] I

MPP[31]/GE1[11] I

I

I

I t/s

O

CMOS

CMOS

CMOS

CMOS

CMOS

VDD_GE_B MII/MMII Transmit Data

Contains the transmit data nibble outputs that are synchronous to the transmit clock input.

GMII Transmit Data

Contains the transmit data nibble outputs.

VDD_GE_B MII/MMII Receive Data

Contains the receive data nibble inputs that are synchronous to

GE_RXCLK input.

GMII Receive Data

Contains the receive data nibble inputs.

VDD_GE_B MII/MMII Collision Detect

Indicates a collision has been detected on the wire. This input is ignored in full-duplex mode. Collision detect is not synchronous to any clock.

GMII Collision Detect

VDD_GE_B MII/MMII Transmit Clock

MII/MMII transmit reference clock from PHY.

Provides the timing reference for the transmission of the GMII transmit clock, transmit enable, and GE_TXD[3:0] signals. This clock operates at 2.5 MHz or 25 MHz.

GMII Transmit Clock

Provides the timing reference for the transfer of the transmit enable, transmit error and transmit data signals. This clock operates at 125 MHz.

VDD_GE_B MII/MMII Receive Data Valid

GMII Receive Error

VDD_GE_B MII/MMII Receive Clock

Provides the timing reference for the reception of the receive data valid, receive error, and GE_RXD[3:0] signals. This clock operates at 2.5 MHz or 25 MHz.

Copyright © 2008 Marvell

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Hardware Specifications

Table 9: 88F6190 Gigabit Ethernet Interface Pin Assignments (Continued)

P i n N a m e I / O P i n

Ty p e

MPP[32]/GE1[12] I/O CMOS

MPP[33]/GE1[13] t/s

O

CMOS

MPP[34]/GE1[14] O

MPP[35]/GE1[15] I

CMOS

CMOS

P o w e r

R a i l

D e s c r i p t i o n

VDD_GE_B MII/MMII Carrier Sense

Indicates that the receive medium is non-idle. In half-duplex mode, GE_CRS is also asserted during transmission. Carrier sense is not synchronous to any clock.

GMII Carrier Sense

VDD_GE_B MII/MMII Transmit Error

It is synchronous to transmit clock.

NOTE: Multiplexed on MPP.

GMII Transmit Error

It Is synchronous to GE_TXCLKOUT.

NOTE: Multiplexed on MPP.

VDD_GE_B MII/MMII Transmit Enable

Indicates that the packet is being transmitted to the PHY. It Is synchronous to transmit clock.

VDD_GE_B MII/MMII Receive Error

Indicates that an error symbol, a false carrier, or a carrier extension symbol is detected on the cable. It is synchronous to

GE_RXCLK input.

NOTE: Multiplexed on MPP.

Table 10: 88F6192 Gigabit Ethernet Port0/1 Interface Pin Assignments

P i n N a m e I / O P i n

Ty p e

Port0—Dedicated GbE Pins

GE_TXCLKOUT t/s

O

CMOS

P o w e r

R a i l

D e s c r i p t i o n

I t/s

O

VDD_GE_A RGMII Transmit Clock

RGMII transmit reference output clock for GE_TXD[3:0] and

GE_TXCTL.

Provides 125 MHz, 25 MHz or 2.5 MHz clock.

Not used in MII/MMII mode.

MII/MMII Transmit Clock

MII/MMII transmit reference clock from PHY.

Provides the timing reference for the transmission of the MII transmit clock, transmit enable, and GE_TXD[3:0] signals. This clock operates at 2.5 MHz or 25 MHz.

GMII Transmit Clock

Provides the timing reference for the transfer of the transmit enable, transmit error and transmit data signals. This clock operates at 125 MHz.

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December 2, 2008, Preliminary

Pin and Signal Descriptions

Pin Descriptions

Table 10: 88F6192 Gigabit Ethernet Port0/1 Interface Pin Assignments (Continued)

P i n N a m e

GE_TXD[3:0]

GE_RXD[3:0]

GE_RXCTL I

I

I / O P i n

Ty p e

t/s

O

CMOS

O

CMOS

CMOS

P o w e r

R a i l

D e s c r i p t i o n

VDD_GE_A RGMII Transmit Data

Contains the transmit data nibble outputs that run at double data rate with bits [3:0] driven on the rising edge of GE_TXCLKOUT and bits [7:4] driven on the falling edge.

MII/MMII Transmit Data

Contains the transmit data nibble outputs that are synchronous to the transmit clock input.

GMII Transmit Data

Contains the transmit data nibble outputs.

VDD_GE_A RGMII Transmit Control

Transmit control synchronous to the GE_TXCLKOUT output rising/falling edge.

GE_TXEN is driven on the rising edge of GE_TXCLKOUT.

A logical derivative of transmit enable and transmit error is driven on the falling edge of GE_TXCLKOUT.

MII/MMII Transmit Enable

Indicates that the packet is being transmitted to the PHY. It Is synchronous to transmit clock.

GMII Transmit Enable

Indicates that the packet is being transmitted to the PHY.

It Is synchronous to GE_TXCLKOUT.

VDD_GE_A RGMII Receive Data (Only relevant for the 88F6192.)

Contains the receive data nibble inputs that are synchronous to

GE_RXCLK input rising/falling edge.

MII/MMII Receive Data

Contains the receive data nibble inputs that are synchronous to

GE_RXCLK input.

GMII Receive Data

Contains the receive data nibble inputs.

VDD_GE_A RGMII Receive Control

GE_RXCTL is presented on the rising edge of GE_RXCLK.

A logical derivative of receive data valid and receive data error is presented on the falling edge of RXCLK.

MII/MMII Receive Data Valid

GMII Receive Data Valid.

Copyright © 2008 Marvell

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Hardware Specifications

Table 10: 88F6192 Gigabit Ethernet Port0/1 Interface Pin Assignments (Continued)

P i n N a m e

GE_RXCLK I

I / O P i n

Ty p e

CMOS

P o w e r

R a i l

D e s c r i p t i o n

VDD_GE_A RGMII Receive Clock

The receive clock provides a 125 MHz, 25 MHz, or 2.5 MHz reference clock derived from the received data stream.

MII/MMII Receive Clock

Provides the timing reference for the reception of the receive data valid, receive error, and GE_RXD[3:0] signals. This clock operates at 2.5 MHz or 25 MHz.

GMII Receive Clock

Provides the timing reference for the reception of the GE_RXDV, receive error and receive data signals. This clock operates at

125 MHz

Port1—Multiplexed GbE Pins

MPP[23:20]/

GE1[3:0] t/s

O

CMOS

MPP[27:24]/

GE1[7:4]

I CMOS

VDD_GE_B RGMII Transmit Data

Contains the transmit data nibble outputs that run at double data rate with bits [3:0] presented on the rising edge of

GE_TXCLKOUT and bits [7:4] presented on the falling edge.

MII/MMII Transmit Data

Contains the transmit data nibble outputs that are synchronous to the transmit clock input.

GMII Transmit Data

Contains the transmit data nibble outputs.

VDD_GE_B RGMII Receive Data

Contains the receive data nibble inputs that are synchronous to

GE_RXCLK input rising/falling edge.

MII/MMII Receive Data

Contains the receive data nibble inputs that are synchronous to

GE_RXCLK input.

GMII Receive Data

Contains the receive data nibble inputs.

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Pin and Signal Descriptions

Pin Descriptions

Table 10: 88F6192 Gigabit Ethernet Port0/1 Interface Pin Assignments (Continued)

P i n N a m e

MPP[28]/GE1[8]

MPP[29]/GE1[9]

MPP[30]/GE1[10] I

MPP[31]/GE1[11] I

I

I

I / O P i n

Ty p e

CMOS t/s

O

MPP[32]/GE1[12] I/O

CMOS

CMOS

CMOS

CMOS

P o w e r

R a i l

D e s c r i p t i o n

VDD_GE_B MII/MMII Collision Detect

Indicates a collision has been detected on the wire. This input is ignored in full-duplex mode. Collision detect is not synchronous to any clock.

GMII Collision Detect

VDD_GE_B MII/MMII Transmit Clock

MII/MMII transmit reference clock from PHY.

Provides the timing reference for the transmission of the MII transmit clock, transmit enable, and GE_TXD[3:0] signals. This clock operates at 2.5 MHz or 25 MHz.

GMII Transmit Clock

Provides the timing reference for the transfer of the transmit enable, transmit error and transmit data signals. This clock operates at 125 MHz.

VDD_GE_B RGMII Receive Control

GE_RXCTL is presented on the rising edge of GE_RXCLK.

A logical derivative of receive data valid and receive data error is presented on the falling edge of RXCLK.

MII/MMII Receive Data Valid

GMII Receive Error

VDD_GE_B RGMII Receive Clock

The receive clock provides a 125 MHz, 25 MHz, or 2.5 MHz reference clock derived from the received data stream.

MII/MMII Receive Clock

Provides the timing reference for the reception of the receive data valid, receive error, and GE_RXD[3:0] signals. This clock operates at 2.5 MHz or 25 MHz.

VDD_GE_B RGMII Transmit Clock

RGMII transmit reference output clock for GE_TXD[3:0] and

GE_TXCTL Provides 125 MHz, 25 MHz or 2.5 MHz clock.

Not used in MII/MMII mode.

MII/MMII Carrier Sense

Indicates that the receive medium is non-idle. In half-duplex mode, GE_CRS is also asserted during transmission. Carrier sense is not synchronous to any clock.

GMII Carrier Sense

Copyright © 2008 Marvell

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Hardware Specifications

Table 10: 88F6192 Gigabit Ethernet Port0/1 Interface Pin Assignments (Continued)

P i n N a m e

MPP[33]/GE1[13]

MPP[34]/GE1[14] O

MPP[35]/GE1[15] I

I / O P i n

Ty p e

t/s

O

CMOS

CMOS

CMOS

P o w e r

R a i l

D e s c r i p t i o n

VDD_GE_B RGMII Transmit Control

Transmit control synchronous to the GE_TXCLKOUT output rising/falling edge.

GE_TXEN is presented on the rising edge of GE_TXCLKOUT.

A logical derivative of transmit enable transmit error is presented on the falling edge of GE_TXCLKOUT.

MII/MMII Transmit Error

It is synchronous to transmit clock.

NOTE: Multiplexed on MPP.

GMII Transmit Error

It Is synchronous to GE_TXCLKOUT.

NOTE: Multiplexed on MPP.

VDD_GE_B MII/MMII Transmit Enable

Indicates that the packet is being transmitted to the PHY. It Is synchronous to transmit clock.

VDD_GE_B MII/MMII Receive Error

Indicates that an error symbol, a false carrier, or a carrier extension symbol is detected on the cable. It is synchronous to

GE_RXCLK input.

NOTE: Multiplexed on MPP.

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December 2, 2008, Preliminary

Pin and Signal Descriptions

Pin Descriptions

2.2.7

Serial Management Interface (SMI) Interface Pin

Assignments

Table 11: Serial Management Interface (SMI) Pin Assignments

P i n N a m e

GE_MDC

GE_MDIO

I / O P i n

Ty p e

t/s

O

CMOS/ t/s

I/O

CMOS

P o w e r

R a i l

D e s c r i p t i o n

VDD_GE_A Management Data Clock

MDC is derived from TCLK divided by 128.

Provides the timing reference for the transfer of the MDIO signal.

VDD_GE_A Management Data In/Out

Used to transfer control and status information between PHY devices and the GbE controller.

NOTE: An external pull-up is required.

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Hardware Specifications

2.2.8

USB 2.0 Interface Pin Assignments

Table 12: USB 2.0 Interface Pin Assignments

P i n N a m e

USB_DP

USB_DM

I / O

I/O

P i n

Ty p e

CML

P o w e r

R a i l

D e s c r i p t i o n

USB_AVDD USB 2.0 Data Differential Pair

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December 2, 2008, Preliminary

Pin and Signal Descriptions

Pin Descriptions

2.2.9

JTAG Interface Pin Assignment

Table 13: JTAG Pin Assignment

P i n N a m e

I

I / O P i n

Ty p e

CMOS

P o w e r

R a i l

VDDO

D e s c r i p t i o n

JT_CLK

JT_RSTn

JT_TMS_CPU

JT_TMS_CORE

JT_TDO

JT_TDI I

I

I

I

O

CMOS

CMOS

CMOS

CMOS

CMOS

VDDO

VDDO

VDDO

VDDO

VDDO

JTAG Clock

Clock input for the JTAG controller.

NOTE: This pin is internally pulled down to 0.

JTAG Reset

When asserted, resets the JTAG controller.

NOTE: This pin is internally pulled down to 0.

1

CPU JTAG Mode Select

Controls CPU JTAG controller state.

Sampled with the rising edge of JT_CLK.

NOTE: This pin is internally pulled up to 1.

Core JTAG Mode Select

Controls the Core JTAG controller state.

Sampled with the rising edge of JT_CLK.

NOTE: This pin is internally pulled up to 1.

JTAG Data Out

Driven on the falling edge of JT_CLK.

JTAG Data In

JTAG serial data input. Sampled with the JT_CLK rising edge.

NOTE: This pin is internally pulled up to 1.

1. If this pull-down conflicts with other devices, the JTAG tool must not use this signal. This signal is not mandatory for the

JTAG interface, since the TAP (Test Access Port) can be reset by driving the JT_TMS signal HIGH for 5 JT_CLK cycles.

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Hardware Specifications

2.2.10

Real Time Clock (RTC) Interface Pin Assignments

Table 14: RTC Interface Pin Assignments

P i n N a m e I / O P i n

Ty p e

P o w e r

R a i l

RTC_XIN I Analog

D e s c r i p t i o n

RTC_AVDD RTC Crystal Clock Input

RTC_XOUT O Analog RTC_AVDD RTC Crystal Clock Feedback

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December 2, 2008, Preliminary

Pin and Signal Descriptions

Pin Descriptions

2.2.11

NAND Flash Interface Pin Assignment

Table 15: NAND Flash Interface Pin Assignment

P i n N a m e

NF_IO[7:0]

I / O P i n

Ty p e

I/O CMOS

P o w e r

R a i l

VDDO

D e s c r i p t i o n

NF_CLE

NF_ALE

NF_CEn

NF_REn

NF_WEn

O

O

O

O

O

CMOS

CMOS

CMOS

CMOS

CMOS

VDDO

VDDO

VDDO

VDDO

VDDO

Data Input/Output

Used to output command, address and data, and to input data during read operations.

NOTE: All of the NF_IO pins are multiplexed on the MPP pins

(see Section 6, Pin Multiplexing, on page 61

)

Command Latch Enable

Controls the activating path for commands sent to the command register.

Address Latch Enable

Controls the activating path for the address to the internal address registers.

Chip Enable

Controls the device selection.

Read Enable

Controls the serial data-in.

Write Enable

Controls writes to the NF_IO[7:0] ports.

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Hardware Specifications

2.2.12

MPP Interface Pin Assignment

Table 16: MPP Interface Pin Assignment

P i n N a m e

MPP[19:0]

MPP[35:20]

I / O P i n

Ty p e

t/s

I/O

CMOS t/s

I/O

CMOS

P o w e r

R a i l

VDDO

D e s c r i p t i o n

Multi Purpose Pin

Various functionalities

VDD_GE_B Multi Purpose Pin

Various functionalities

The various functionalities of the MPP pins are detailed in Section 6, Pin Multiplexing, on page 61

.

Note

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December 2, 2008, Preliminary

2.2.13

Pin and Signal Descriptions

Pin Descriptions

Two-Wire Serial Interface (TWSI) Interface

Note

All of the TWSI signals are multiplexed on the MPP pins (see

Section 6, Pin Multiplexing, on page 61

).

Table 17: Two-Wire Serial Interface (TWSI) Interface Pin Assignment

P i n N a m e I / O P i n

Ty p e

P o w e r

R a i l

D e s c r i p t i o n

TW_SDA o/d

I/O

CMOS VDDO TWSI Port Serial Data

Address or write data driven by the TWSI master or read response data driven by the TWSI slave.

NOTE: Requires a pull-up resistor to VDDO.

TW_SCK o/d

I/O

CMOS VDDO TWSI Port Serial Clock

Serves as output when acting as an TWSI master.

Serves as input when acting as an TWSI slave.

NOTE: Requires a pull-up resistor to VDDO.

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Page 45

2.2.14

88F619x

Hardware Specifications

UART Interface

Note

All of the UART signals are multiplexed on the MPP pins (see

Section 6, Pin Multiplexing, on page 61

).

Table 18: UART Port 0/1 Interface Pin Assignment

P i n N a m e I / O P i n

Ty p e

P o w e r

R a i l

D e s c r i p t i o n

UA0/1_RXD

UA0/1_TXD

I

O

CMOS

CMOS

VDDO

VDDO

UART Port 0/1 RX Data

UART Port 0/1 TX Data

UA0/1_CTS

UA0/1_RTS

I

O

CMOS

CMOS

VDDO

VDDO

Clear to Send

Request to Send

Doc. No. MV-S104987-U0 Rev. F

Page 46 Document Classification: Proprietary Information

Copyright © 2008 Marvell

December 2, 2008, Preliminary

Pin and Signal Descriptions

Pin Descriptions

2.2.15

Audio (S/PDIF / I

2

S) Interface

Note

„

„

„

„

The Audio interface is only relevant for the 88F6192.

All of the Audio signals are multiplexed on the MPP pins (see

Section 6, Pin

Multiplexing, on page 61

).

If the Audio interface is not used, leave all of the signals unconnected.

The Audio signals are powered on VDDO or on VDD_GE_B, based on the pin multiplexing option.

Table 19: Audio (S/PDIF / I

2

S) Interface Signal Assignment

P i n N a m e I / O P i n

Ty p e

P o w e r

R a i l

D e s c r i p t i o n

AU_SPDIFI I CMOS VDD_GE_B S/PDIF

AU_SPDIFO

AU_

SPDFRMCLK

AU_I2SBCLK

AU_I2SDO

AU_I2SLRCLK

AU_I2SMCLK

AU_I2SDI

AU_EXTCLK I

O

I

O

O

O

O

O

CMOS VDD_GE_B S/PDIF

CMOS VDD_GE_B S/PDIF Recovered Master Clock (256 x F s

)

1

For the frequency of this clock, see the Audio External

Reference Clock section of Table 51, Reference Clock AC

Timing Specifications, on page 97 .

CMOS VDD_GE_B I

2

S Bit Clock (64 x F s

)

CMOS VDD_GE_B Transmitter Data Out

CMOS VDD_GE_B I

2

S Left/Right Clock (1 x F s

)

CMOS VDD_GE_B I

2

S Master Clock (256 x F s

)

CMOS VDD_GE_B I

2

S Receiver Data In

CMOS VDD_GE_B External Audio Clock

For the frequency of this clock, see the Audio External

Reference Clock section of Table 51, Reference Clock AC

Timing Specifications, on page 97 .

1. F s

is the audio sample rate.

Copyright © 2008 Marvell

December 2, 2008, Preliminary Document Classification: Proprietary Information

Doc. No. MV-S104987-U0 Rev. F

Page 47

2.2.16

88F619x

Hardware Specifications

Serial Peripheral Interface (SPI) Interface

Note

All of the SPI signals are multiplexed on the MPP pins (see

Section 6, Pin Multiplexing, on page 61

).

Table 20: Serial Peripheral Interface (SPI) Interface Signal Assignment

I/O Description

Pin Name

SPI_MOSI

1

O

Pin Type

CMOS

Power Rail

VDDO SPI Data Output

Data is output from the master and input to the slave.

SPI_MISO

2

I CMOS VDDO SPI Data Input

Data is input to the master and output from the slave.

SPI_SCK O CMOS VDDO SPI Clock

SPI_CSn O CMOS VDDO SPI Chip Select

NOTE: This pin requires an external pull up.

1. MOSI = Master Out Slave In.

2. MISO = Master In Slave Out.

Doc. No. MV-S104987-U0 Rev. F

Page 48 Document Classification: Proprietary Information

Copyright © 2008 Marvell

December 2, 2008, Preliminary

2.2.17

Pin and Signal Descriptions

Pin Descriptions

Secure Digital Input/Output (SDIO) Interface

Note

All of the SDIO signals are multiplexed on the MPP pins (see

Section 6, Pin Multiplexing, on page 61

).

Table 21: Secure Digital Input/Output (SDIO) Interface Signal Assignment

I/O Description

Pin Name

SD_CLK O

Pin Type

CMOS

Power Rail

VDDO SDIO Clock

SD_CMD I/O CMOS VDDO SDIO Command

Used to transfer a command serially from the SDIO host to the

SDIO device. Used to transfer a command response serially from the SDIO device to the SDIO host.

NOTE: This pin requires a pull up on board.

SD_D[3:0] I/O CMOS VDDO SDIO Data Input/Output

Used to transfer data from the SDIO host to the SDIO device or vice versa.

NOTE: These pins require a pull up on board.

Copyright © 2008 Marvell

December 2, 2008, Preliminary Document Classification: Proprietary Information

Doc. No. MV-S104987-U0 Rev. F

Page 49

88F619x

Hardware Specifications

2.2.18

Time Division Multiplexing (TDM) Interface

Note

„

„

„

The TDM interface is only relevant for the 88F6192.

All of the TDM signals are multiplexed on the MPP pins (see Section 6, Pin

Multiplexing, on page 61

).

The TDM signals are powered on VDDO or on VDD_GE_B, based on the pin multiplexing option (see

Section 6, Pin Multiplexing, on page 61 ).

Table 22: Time Division Multiplexing (TDM) Interface Signal Assignment

Pin Name

TDM_CH0_TX_

QL

TDM_CH2_TX_

QL

TDM_CH0_RX_

QL

TDM_CH2_RX_

QL

TDM_CODEC_

INTn

TDM_CODEC_

RSTn

TDM_PCLK

TDM_FS

TDM_DRX

TDM_DTX

I

I/O

O

O

O

O

O

I

I/O

I/O

O

Pin Type

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

Power Rail

Description

VDD_GE_B TDM Channel0 Transmit Qualifier

VDD_GE_B TDM Channel2 Transmit Qualifier

VDD_GE_B TDM Channel0 Receive Qualifier

VDD_GE_B TDM Channel2 Receive Qualifier

VDD_GE_B Interrupt Signal FROM the SLIC/codec

VDD_GE_B SLIC/codec Reset Signal

VDD_GE_B PCM Audio Bit Clock

VDD_GE_B TDM Frame Sync Signal

VDD_GE_B PCM Audio Input Data (for recording)

VDD_GE_B PCM Audio Output Data (for playback)

TDM_SPI_CS[1:0] O

TDM_SPI_SCK O

CMOS

CMOS

VDD_GE_B Active low SPI chip selects driven by the host to the codec for register access. Always asserted for eight SCLK cycles at a time.

Only Byte-by-Byte mode codec register read/write is supported.

VDD_GE_B Serial SPI clock from the host to the codec for register access.

This is an RTO (return to one) clock. It toggles for eight cycles at a time (for 1 byte transfer) during codec register access, then it returns to high.

The host drives write data on TDM_SPI_MOSI on the negative edge of TDM_SPI_SCK, and captures read data from the codec on the positive edge of TDM_SPI_SCK.

Doc. No. MV-S104987-U0 Rev. F

Page 50 Document Classification: Proprietary Information

Copyright © 2008 Marvell

December 2, 2008, Preliminary

Pin and Signal Descriptions

Pin Descriptions

Table 22: Time Division Multiplexing (TDM) Interface Signal Assignment (Continued)

I/O

Pin Name

TDM_SPI_MOSI

TDM_SPI_MISO I

O

Pin Type

CMOS

CMOS

Power Rail

Description

VDD_GE_B Serial SPI data from the host to the codec for register access.

When TDM_SPI_CS is asserted low, the data is driven from the host on the negative edge of TDM_SPI_SCK. It is always driven for eight TDM_SPI_SCK cycles at a time.

In a byte, the data can be driven MSB or LSB first.

VDD_GE_B Serial SPI read data from the CODEC to the host for register access.

When TDM_SPI_CS is asserted low, this data is driven from

CODEC on negative edge of TDM_SPI_SCK. It is always driven for eight TDM_SPI_SCK cycles at a time. The CODEC drives data on this line only for a read operation, when it gets command and address in previous bytes from the host on TDM_SPI_MOSI

In a byte, the data can be driven MSB or LSB first.

Copyright © 2008 Marvell

December 2, 2008, Preliminary Document Classification: Proprietary Information

Doc. No. MV-S104987-U0 Rev. F

Page 51

88F619x

Hardware Specifications

2.2.19

Transport Stream (TS) Interface

Note

„

„

„

The TS interface is only relevant for the 88F6192 only.

All of the TS signals are multiplexed on the MPP pins (see Section 6, Pin

Multiplexing, on page 61

).

The TS signals are powered on VDDO or on VDD_GE_B based on the pin multiplexing option (see

Section 6, Pin Multiplexing

).

Table 23: Transport Stream (TS) Interface Signal Assignment

I/O

Pin Name

TSMP[0]

TSMP[1]

TSMP[2]

TSMP[3]

TSMP[4]

TSMP[5]

TSMP[6]

I

I/O

I/O

I/O

I/O

I/O

I/O

Pin Type

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

Power Rail

Description

VDD_GE_B EXT_CLK

External clock that can be used to drive the TS0_CLK and

TS1_CLK

VDD_GE_B TS0_CLK

Port0 TS clock.

• If TS0_VAL is used, the clock may be continuous.

• If TS0_VAL is not used, the clock may toggle only when valid data is available on TS0_DATA.

VDD_GE_B TS0_SYNC

Port0 Sync/Frame Start Indicator or Packet Clock.

The TS0_SYNC in parallel mode is a pulse that is active during the first (Sync) byte of the TS packet. In serial mode, the

TS0_SYNC pulse may be active for the entire byte or only for the first bit. The polarity is programmable to be either active high or active low.

VDD_GE_B TS0_VAL

Port0 Valid Data Indicator

When this signal is used and is valid, it indicates that valid data is present on TS0_DATA. TS0_VAL is active during the TS frame packet data and inactive when there is no TS synchronization.

In output mode, the polarity of TS0_VAL is programmable to be either active high or active low.

VDD_GE_B TS0_ERR

Port0 Uncorrectable Packet Error

When this signal is used, an error indicates that the packet contains an uncorrectable error, and therefore should not be used.

In output mode, the TS0_ERR is active during the entire TS frame.

VDD_GE_B TS0_DATA[0]

Port0 TS Data bit 0 in both parallel and serial modes.

In Serial mode TS0_DATA[0] is used as data input or output.

VDD_GE_B

• Parallel Mode:

TS0_DATA[1]: Port0 TS Data bit 1

• Serial Mode:

TS1_CLK: Port1 TS clock.

- If TS1_VAL is used, the clock may be continuous.

- If TS1_VAL is not used, the clock may toggle only when valid data is available on TS1_DATA

Doc. No. MV-S104987-U0 Rev. F

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Copyright © 2008 Marvell

December 2, 2008, Preliminary

Pin and Signal Descriptions

Pin Descriptions

Table 23: Transport Stream (TS) Interface Signal Assignment (Continued)

I/O

Pin Name

TSMP[7]

TSMP[8]

TSMP[9]

TSMP[10]

TSMP[11]

TSMP[12]

I/O

I/O

I/O

I/O

I/O

I/O

Pin Type

CMOS

CMOS

CMOS

CMOS

CMOS

CMOS

Power Rail

Description

VDD_GE_B

• Parallel Mode:

TS0_DATA[2]: Port0 TS Data bit 2

• Serial Mode:

TS1_SYNC: Port1 Sync/Frame Start Indicator or Packet

Clock.

The TS1_SYNC pulse may be active for the entire byte or only for the first bit. The polarity is programmable to be either active high or active low

VDD_GE_B

• Parallel Mode:

TS0_DATA[3]: Port0 TS Data bit 3

• Serial Mode:

TS1_VAL: Port1Valid Data Indicator

When this signal is used and is valid, it indicates that valid data is present on TS1_DATA[0].

TS1_VAL is active during the TS frame packet data and inactive when there is no TS synchronization.

In output mode, the polarity of TS1_VAL is programmable to be either active high or active low.

VDD_GE_B

• Parallel Mode:

TS0_DATA[4]: Port0 TS Data bit 4

• Serial Mode:

TS1_ERR: Port1 Uncorrectable Packet Error

When this signal is used, an error indicates that the packet contains an uncorrectable error, and, therefore, should not be used.

In output mode the TS1_ERR is active during the entire TS frame.

VDD_GE_B

• Parallel Mode:

TS0_DATA[5]: Port0 TS Data bit 5

• Serial Mode:

TS1_DATA[0]: Port1 TS Data bit 0, used as data input or output.

VDD_GE_B TS0_DATA[6]

Port0 TS Data bit 6

This pin is only valid in Parallel mode.

VDD_GE_B TS0_DATA[7]

Port0 TS Data bit 7

This pin is only valid in Parallel mode.

Copyright © 2008 Marvell

December 2, 2008, Preliminary Document Classification: Proprietary Information

Doc. No. MV-S104987-U0 Rev. F

Page 53

2.2.20

88F619x

Hardware Specifications

Precise Timing Protocol (PTP) Interface

Note

All of the PTP signals are multiplexed on the MPP pins (see

Section 6, Pin Multiplexing, on page 61

).

Table 24: Precise Timing Protocol (PTP) Interface Signal Assignment

I/O Description

Pin Name

PTP_CLK I

Pin Type

CMOS

Power Rail

VDDO PTP Clock

PTP_EVENT_REQ I CMOS VDDO Trigger generation to the PTP core.

PTP_TRIG_GEN O CMOS VDDO Trigger generated by the PTP core.

Doc. No. MV-S104987-U0 Rev. F

Page 54 Document Classification: Proprietary Information

Copyright © 2008 Marvell

December 2, 2008, Preliminary

2.3

Pin and Signal Descriptions

Internal Pull-up and Pull-down Pins

Internal Pull-up and Pull-down Pins

Some pins of the device package are connected to internal pull-up and pull-down resistors. When these pins are Not Connected (NC) on the system board, these resistors set the default value for input and sample at reset configuration pins.

The internal pull-up and pull-down resistor value is 50 k

Ω. An external resistor with a lower value can override this internal resistor.

Table 25: Internal Pull-up and Pull-down Pins

P i n N a m e

GE_TXD[0]

GE_TXD[1]

GE_TXD[2]

GE_TXD[3]

88F6190 – GE_TXEN

88F6192

GE_TXCTL

GE_MDC

JT_TMS_CORE

MPP[1]

MPP[2]

MPP[3]

MPP[4]

MPP[5]

MPP[7]

MPP[10]

MPP[11]

JT_RSTn

JT_TDI

JT_TMS_CPU

NF_ALE

NF_REn

NF_CLE

NF_CEn

NF_WEn

MPP[12]

MPP[14]

MPP[18]

MPP[19]

MPP[33]

81

80

82

85

93

92

91

94

33

114

109

115

112

90

97

99

88

89

86

75

72

74

45

20

19

23

P i n N u m b e r

22

21

P u l l u p / P u l l d o w n

Pull down

Pull down

Pull up

Pull up

Pull down

Pull up

Pull up

Pull down

Pull up

Pull up

Pull up

Pull down

Pull down

Pull up

Pull up

Pull down

Pull down

Pull down

Pull up

Pull up

Pull up

Pull down

Pull up

Pull down

Pull up

Pull up

Pull up

Pull down

Copyright © 2008 Marvell

December 2, 2008, Preliminary Document Classification: Proprietary Information

Doc. No. MV-S104987-U0 Rev. F

Page 55

88F619x

Hardware Specifications

3

Unused Interface Strapping

Table 26 lists the signal strapping to be used for systems in which some of the device interfaces are unused (not

connected).

Table 26: Unused Interface Strapping

U n u s e d I n t e r f a c e

Ethernet SMI

MPP

USB

PCI Express

88F6190 – SATA

88F6192 – SATA

RTC

SSCG eFuse

St r a p p i n g

Pull up GE_MDIO.

Configure any unused MPP pin to GPIO output.

Leave the power supply connected.

• If the related power supply is VDDO, leave it connected to 3.3V.

• If the related power supply is VDD_GE_B, leave it connected to either 3.3V or 1.8V.

Discard the power filter.

Leave USB_AVDD connected to 3.3V.

All other signals can be left unconnected.

Discard the analog power filters.

Leave PEX_AVDD connected to 1.8V.

Pull down the PEX_CLK_N signal through a 50 k

Ω

resistor to GND.

Pull up the PEX_CLK_P signal through a 16 k

Ω

resistor to 1.8V.

All other signals can be left unconnected.

Configure the PEX_CLK_P and PEX_CLK_N signals as inputs, as indicated in

Table 38,

Reset Configuration, on page 77

.

Discard the analog power filters.

SATA_AVDD can be left unconnected.

Discard the analog power filters.

SATA0_AVDD/SATA1_AVDD can be left unconnected.

Connect RTC_AVDD, RTC_AVSS, RTC_XIN, and RTC_XOUT to GND.

Discard the power filter.

Leave SSCG_AVDD connected to 1.8V.

Connect VHV to VDD

Doc. No. MV-S104987-U0 Rev. F

Page 56 Document Classification: Proprietary Information

Copyright © 2008 Marvell

December 2, 2008, Preliminary

88F6190 Pinout

4

88F6190 Pinout

This section provides the pin map and pin list for the 88F6190.

Figure 3: 88F6190 Pin Map Top View

M_A[9]

M_A[12]

M_A[5]

M_A[7]

VDD_M

M_A[1]

M_A[3]

M_BA[1]

M_A[10]

VDD_M

M_BA[2]

M_DQS[0] 185

M_DQSn[0] 186

M_DM[0]

VDD_M

187

188

M_DQ[6]

M_DQ[1]

189

190

VDD_M

M_DQ[3]

M_DQ[4]

VDD

VDD_M

191

192

193

194

195

196

197

198

199

200

201

202

203

204

205

206

M_ODT[0] 163

M_CSn[1] 164

M_RASn 165

M_CSn[0] 166

VDD_M 167

M_CASn

M_A[0]

M_A[2]

M_A[4]

VDD_M

168

169

170

171

172

M_A[6]

M_A[8]

M_A[13]

M_A[11]

VDD_M

VDD

M_DQ[5]

M_DQ[0]

VDD_M

M_DQ[2]

M_DQ[7]

VDD_M

179

180

181

182

183

184

173

174

175

176

177

178

M_WEn

M_BA[0]

M_CKE

VDD_M

207

208

209

210

VDD 211

M_DQ[12] 212

M_DQ[11] 213

VDD_M 214

M_DQ[14] 215

M_DQ[9] 216

88F6190

Top View

75

74

73

72

71

70

69

68

67

66

65

86

85

84

83

82

81

80

79

78

77

76

64

63

62

61

60

59

58

57

56

55

92

91

90

89

88

87

98

97

96

95

94

93

108 JT_CLK

107 VDD

106 VSS

105 VDD

104 CPU_PLL_AVDD

103 VDD

102 VDDO

101 MPP[17]

100 MPP[16]

99 MPP[14]

MPP[15]

MPP[12]

MPP[13]

VDDO

NF_WEn

NF_REn

NF_CLE

NF_CEn

NF_ALE

MPP[19]

MPP[18]

VSS

SATA_R_P

VDD

NC

NC

NC

NC

NC

NC

NC

VDD

MPP[5]

MPP[4]

VSS

MPP[0]

MPP[3]

MPP[1]

MPP[2]

VDDO

MPP[9]

MPP[8]

VSS

MPP[7]

MPP[11]

MPP[6]

MPP[10]

VDD

VSS

SATA_T_P

VSS

SATA_T_N

SATA_AVDD

SATA_R_N

Copyright © 2008 Marvell

December 2, 2008, Preliminary Document Classification: Proprietary Information

Doc. No. MV-S104987-U0 Rev. F

Page 57

88F619x

Hardware Specifications

Table 27: 88F6190 Pinout Sorted by Pin Number

Pin # Pin Nam e

1 VDD_M

2 M_DM[1]

3 M_DQS[1]

4 M_DQSn[1]

5 VDD_M

6 M_DQ[15]

7 M_DQ[8]

8 VDD_M

9 M_DQ[10]

10 M_DQ[13]

11 VSS

12 VDD

13 USB_AVDD

14 USB_DP

15 USB_DM

Pin # Pin Nam e

46 MPP[32]

47 VDD_GE_B

48 MPP[31]

49 MPP[30]

50 MPP[24]

51 MPP[25]

52 MPP[26]

53 MPP[27]

54 VDD

55 VDD

56 NC

57 NC

58 NC

59 NC

60 NC

Pin # Pin Nam e

91 NF_CEn

92 NF_CLE

93 NF_REn

94 NF_WEn

95 VDDO

Pin # Pin Nam e

136 VDD

137 CORE_PLL_AVDD

138 PEX_ISET

139 VSS

140 PEX_TX_N

96 MPP[13]

97 MPP[12]

98 MPP[15]

99 MPP[14]

100 MPP[16]

101 MPP[17]

102 VDDO

103 VDD

141 VSS

142 PEX_TX_P

143 PEX_AVDD

144 PEX_RX_N

145 PEX_RX_P

146 TP

147 PEX_CLK_N

148 PEX_CLK_P

104 CPU_PLL_AVDD 149 PEX_AVDD

105 VDD 150 RTC_AVDD

Pin # Pin Nam e

181 VDD_M

182 M_DQ[2]

183 M_DQ[7]

184 VDD_M

185 M_DQS[0]

186 M_DQSn[0]

187 M_DM[0]

188 VDD_M

189 M_DQ[6]

190 M_DQ[1]

191 VDD_M

192 M_DQ[3]

193 M_DQ[4]

194 VDD

195 VDD_M

16 VDD

17 VHV

18 VDD_GE_A

19 GE_TXD[3]

20 GE_TXD[2]

21 GE_TXD[1]

22 GE_TXD[0]

23 GE_TXCTL

61 NC

62 NC

63 VDD

64 SATA_R_P

65 SATA_R_N

66 SATA_AVDD

67 SATA_T_N

68 VSS

24 GE_TCLKOUT 69 SATA_T_P

25 VDD_GE_A 70 VSS

106 VSS

107 VDD

108 JT_CLK

109 JT_RSTn

110 SYSRSTn

111 VDDO

112 JT_TMS_CPU

113 JT_TDO

114 JT_TMS_CORE

115 JT_TDI

151 RTC_XIN

152 RTC_XOUT

153 VSS

154 M_PCAL

155 M_STARTBURST_IN

156 VDD

157 M_NCAL

158 M_STARTBURST

159 VDD_M

160 M_CLKOUTn

196 M_A[9]

197 M_A[12]

198 M_A[5]

199 M_A[7]

200 VDD_M

201 M_A[1]

202 M_A[3]

203 M_BA[1]

204 M_A[10]

205 VDD_M

26 GE_RXCLK

27 GE_RXCTL

28 GE_RXD[0]

29 GE_RXD[1]

30 GE_RXD[2]

31 GE_RXD[3]

32 VSS

33 GE_MDC

34 GE_MDIO

71 VDD

72 MPP[10]

73 MPP[6]

74 MPP[11]

75 MPP[7]

76 VSS

77 MPP[8]

78 MPP[9]

79 VDDO

116 SSCG_AVDD

117 VDD

118 VSS

119 VDD

120 VSS

121 VDD

122 VSS

123 VDD

124 VDD

161 M_CLKOUT

162 VDD_M

163 M_ODT[0]

164 M_CSn[1]

165 M_RASn

166 M_CSn[0]

167 VDD_M

168 M_CASn

169 M_A[0]

206 M_BA[2]

207 M_WEn

208 M_BA[0]

209 M_CKE

210 VDD_M

211 VDD

212 M_DQ[12]

213 M_DQ[11]

214 VDD_M

215 M_DQ[14]

216 M_DQ[9]

35 VSS

36 MPP[28]

37 MPP[29]

38 MPP[34]

39 MPP[35]

40 VDD_GE_B

41 MPP[23]

42 MPP[22]

43 MPP[20]

80 MPP[2]

81 MPP[1]

82 MPP[3]

83 MPP[0]

84 VSS

85 MPP[4]

86 MPP[5]

87 VSS

88 MPP[18]

125 VSS

126 VDD

127 VSS

128 VDD

129 VSS

130 VDD

131 ISET

132 XTAL_AVSS

133 XTAL_AVDD

170 M_A[2]

171 M_A[4]

172 VDD_M

173 M_A[6]

174 M_A[8]

175 M_A[13]

176 M_A[11]

177 VDD_M

178 VDD

44 MPP[21]

45 MPP[33]

89 MPP[19]

90 NF_ALE

134 REF_CLK_XIN

135 XOUT

179 M_DQ[5]

180 M_DQ[0]

Doc. No. MV-S104987-U0 Rev. F

Page 58 Document Classification: Proprietary Information

Copyright © 2008 Marvell

December 2, 2008, Preliminary

88F6192 Pinout

5

88F6192 Pinout

This section provides the pin map and pin list for the 88F6192.

Figure 4: 88F6192 Pin Map Top View

VDD_M 188

M_DQ[6] 189

M_DQ[1] 190

VDD_M 191

M_DQ[3] 192

M_DQ[4] 193

VDD

VDD_M

M_A[9]

M_A[12]

M_A[5]

M_A[7]

194

195

196

197

198

199

VDD_M

M_A[1]

200

201

M_A[3] 202

M_BA[1] 203

M_A[10]

VDD_M

204

205

M_BA[2] 206

M_WEn 207

M_BA[0] 208

M_CKE 209

VDD_M

VDD

210

211

M_DQ[12] 212

M_DQ[11] 213

VDD_M 214

M_DQ[14] 215

M_DQ[9] 216

M_ODT[0] 163

M_CSn[1] 164

M_RASn 165

M_CSn[0] 166

VDD_M 167

M_CASn 168

M_A[0] 169

M_A[2] 170

M_A[4]

VDD_M

M_A[6]

M_A[8]

171

172

173

174

M_A[13]

M_A[11]

VDD_M

175

176

177

VDD 178

M_DQ[5] 179

M_DQ[0] 180

VDD_M 181

M_DQ[2] 182

M_DQ[7] 183

VDD_M 184

M_DQS[0] 185

M_DQSn[0] 186

M_DM[0] 187

88F6192

Top View

83 MPP[0]

82 MPP[3]

81 MPP[1]

80 MPP[2]

79 VDDO

78 MPP[9]

77 MPP[8]

76 VSS

75 MPP[7]

74 MPP[11]

73 MPP[6]

72 MPP[10]

71 VDD

70 VSS

69 SATA0_T_P

68 VSS

67 SATA0_T_N

66 SATA0_AVDD

65 SATA0_R_N

64 SATA0_R_P

63 VDD

62 SATA1_T_P

61 VSS

60 SATA1_T_N

59 SATA1_AVDD

58 SATA1_R_N

57 SATA1_R_P

56 VSS

55 VDD

108 JT_CLK

107 VDD

106 VSS

105 VDD

104 CPU_PLL_AVDD

103 VDD

102 VDDO

101 MPP[17]

100 MPP[16]

99 MPP[14]

98 MPP[15]

97 MPP[12]

96 MPP[13]

95 VDDO

94 NF_WEn

93 NF_REn

92 NF_CLE

91 NF_CEn

90 NF_ALE

89 MPP[19]

88 MPP[18]

87 VSS

86 MPP[5]

85 MPP[4]

84 VSS

Copyright © 2008 Marvell

December 2, 2008, Preliminary Document Classification: Proprietary Information

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Hardware Specifications

Table 28: 88F6192 Pinout Sorted by Pin Number

Pin # Pin Nam e

1 VDD_M

2 M_DM[1]

3 M_DQS[1]

4 M_DQSn[1]

5 VDD_M

6 M_DQ[15]

7 M_DQ[8]

8 VDD_M

9 M_DQ[10]

10 M_DQ[13]

11 VSS

12 VDD

Pin # Pin Nam e

46 MPP[32]

47 VDD_GE_B

48 MPP[31]

49 MPP[30]

50 MPP[24]

51 MPP[25]

52 MPP[26]

53 MPP[27]

54 VDD

55 VDD

56 VSS

57 SATA1_R_P

Pin # Pin Nam e

91 NF_CEn

92 NF_CLE

93 NF_REn

94 NF_WEn

95 VDDO

96 MPP[13]

97 MPP[12]

98 MPP[15]

99 MPP[14]

100 MPP[16]

101 MPP[17]

102 VDDO

Pin # Pin Nam e

136 VDD

137 CORE_PLL_AVDD

138 PEX_ISET

139 VSS

140 PEX_TX_N

141 VSS

142 PEX_TX_P

143 PEX_AVDD

144 PEX_RX_N

145 PEX_RX_P

146 TP

147 PEX_CLK_N

Pin # Pin Nam e

181 VDD_M

182 M_DQ[2]

183 M_DQ[7]

184 VDD_M

185 M_DQS[0]

186 M_DQSn[0]

187 M_DM[0]

188 VDD_M

189 M_DQ[6]

190 M_DQ[1]

191 VDD_M

192 M_DQ[3]

13 USB_AVDD

14 USB_DP

15 USB_DM

16 VDD

17 VHV

18 VDD_GE_A

19 GE_TXD[3]

20 GE_TXD[2]

58 SATA1_R_N 103 VDD 148 PEX_CLK_P

59 SATA1_AVDD 104 CPU_PLL_AVDD 149 PEX_AVDD

60 SATA1_T_N

61 VSS

105 VDD

106 VSS

150 RTC_AVDD

151 RTC_XIN

62 SATA1_T_P

63 VDD

107 VDD

108 JT_CLK

64 SATA0_R_P 109 JT_RSTn

65 SATA0_R_N 110 SYSRSTn

152 RTC_XOUT

153 VSS

193 M_DQ[4]

194 VDD

195 VDD_M

196 M_A[9]

197 M_A[12]

198 M_A[5]

154 M_PCAL 199 M_A[7]

155 M_STARTBURST_IN 200 VDD_M

21 GE_TXD[1]

22 GE_TXD[0]

23 GE_TXCTL

66 SATA0_AVDD 111 VDDO

67 SATA0_T_N 112 JT_TMS_CPU

68 VSS 113 JT_TDO

24 GE_TCLKOUT 69 SATA0_T_P

25 VDD_GE_A 70 VSS

26 GE_RXCLK 71 VDD

114 JT_TMS_CORE

115 JT_TDI

116 SSCG_AVDD

156 VDD

157 M_NCAL

158 M_STARTBURST

159 VDD_M

160 M_CLKOUTn

161 M_CLKOUT

201 M_A[1]

202 M_A[3]

203 M_BA[1]

204 M_A[10]

205 VDD_M

206 M_BA[2]

27 GE_RXCTL

28 GE_RXD[0]

29 GE_RXD[1]

30 GE_RXD[2]

31 GE_RXD[3]

32 VSS

33 GE_MDC

34 GE_MDIO

35 VSS

36 MPP[28]

37 MPP[29]

38 MPP[34]

39 MPP[35]

40 VDD_GE_B

41 MPP[23]

42 MPP[22]

43 MPP[20]

72 MPP[10]

73 MPP[6]

74 MPP[11]

75 MPP[7]

76 VSS

77 MPP[8]

78 MPP[9]

79 VDDO

80 MPP[2]

81 MPP[1]

82 MPP[3]

83 MPP[0]

84 VSS

85 MPP[4]

86 MPP[5]

87 VSS

88 MPP[18]

117 VDD

118 VSS

119 VDD

120 VSS

121 VDD

122 VSS

123 VDD

124 VDD

125 VSS

126 VDD

127 VSS

128 VDD

129 VSS

130 VDD

131 ISET

132 XTAL_AVSS

133 XTAL_AVDD

162 VDD_M

163 M_ODT[0]

164 M_CSn[1]

165 M_RASn

166 M_CSn[0]

167 VDD_M

168 M_CASn

169 M_A[0]

170 M_A[2]

171 M_A[4]

172 VDD_M

173 M_A[6]

174 M_A[8]

175 M_A[13]

176 M_A[11]

177 VDD_M

178 VDD

207 M_WEn

208 M_BA[0]

209 M_CKE

210 VDD_M

211 VDD

212 M_DQ[12]

213 M_DQ[11]

214 VDD_M

215 M_DQ[14]

216 M_DQ[9]

44 MPP[21]

45 MPP[33]

89 MPP[19]

90 NF_ALE

134 REF_CLK_XIN

135 XOUT

179 M_DQ[5]

180 M_DQ[0]

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Multi-Purpose Pins Functional Summary

The 88F6190/88F6192 device contains 36 Multi-Purpose Pins (MPP). Each one can be assigned to a different functionality through the MPP Control register.

„ General Purpose pins: MPP[5:0] and MPP[35:7]:

GPIO (input/output): MPP[0], MPP[4], MPP[9:8], MPP[11], MPP[17:13], MPP[32:20], and

MPP[35:34]

GPO (output): MPP[3:1], MPP[5], MPP[7], MPP[10], MPP[12], MPP[19:18], and MPP[33]

SYSRST_OUTn: Reset request from the device to the board reset logic. This pin is an output.

SYSRST_OUTn is the default setting for MPP[6].

PEX_RST_OUTn: Optional PCI Express Endpoint card reset output.

MII/MMII/GMII/RGMII interface signals

For the 88F6190 only, SATA_ACTn/SATA_PRESENTn: SATA active and SATA present indications—see the SATA section in the 88F6180, 88F6190, 88F6192, and 88F6281

Functional Specifications.

For the 88F6192 only, SATA0/1_ACTn/SATA0/1_PRESENTn (port 0 and port 1): SATA active and SATA present indications—see the SATA section in the 88F6180, 88F6190, 88F6192, and

88F6281 Functional Specifications.

NF_IO[7:0] (NAND Flash data [7:0])

SPI interface: SPI_MOSI, SPI_MISO, SPI_SCK, SPI_CSn

UART interface (port 0 and port 1): Transmit and receive functions: UA0_TXD, UA0_RXD,

UA1_TXD, UA1_RXD, and Modem control functions: UA0_RTSn, UA0_CTSn, UA1_RTSn,

UA1_CTSn

SDIO interface: SD_CLK, SD_CMD, SD_D[3:0]

For the 88F6192 only, Audio interface signals: AU_SPDIFI, AU_SPDIFO, AU_SPDIFRMCLK,

AU_I2SBCLK, AU_I2SDO, AU_I2SLRCLK, AU_I2SMCLK, AU_I2SDI, AU_EXTCLK

TS (Transport Stream) interface signals (88F6192 only): TSMP[12:0]

TDM/SPI interface signals (88F6192 only): TDM_CH0/2_TX_QL, TDM_CH0/2_RX_QL,

TDM_SPI_CS0/1, TDM_SPI_SCK, TDM_SPI_MOSI, TDM_SPI_MISO, TDM_CODEC_INTn,

TDM_CODEC_RSTn, TDM_PCLK, TDM_FS, TDM_DRX, TDM_DTX

PTP signals: PTP_EVENT_REQ, PTP_TRIG_GEN, PTP_CLK

TWSI signals: TW_SDA, TW_SCK

Copyright © 2008 Marvell

December 2, 2008, Preliminary Document Classification: Proprietary Information

Doc. No. MV-S104987-U0 Rev. F

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88F619x

Hardware Specifications

MPP pins can be assigned to different functionalities through the MPP Control register, as shown in

Table 29 .

Table 29: MPP Functionality

M P P [ 1 9 : 0 ]

GPIO

SATA LEDs

NAND flash

TWSI

UART

SPI

PTP

SDIO

M P P [ 3 5 : 2 0 ]

GPIO

SATA LEDs

GbE

Audio (88F6192 only)

TDM (88F6192 only)

TS (88F6192 only)

PTP

Table 30

and Table 31 lists the functionality of the MPP pins, as determined by the MPP Multiplex

register, see the Pins Multiplexing Interface Registers section in the 88F6180, 88F6190, 88F6192,

and 88F6281 Functional Specifications.

Doc. No. MV-S104987-U0 Rev. F

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December 2, 2008, Preliminary

Pin Multiplexing

Multi-Purpose Pins Functional Summary

Table 30: 88F6190 MPP Function Summary

Pin name 0x0 0x1 0x2 0x3 0x4 0x5 0xC 0xD

MPP[0]

GPIO[0]

(in/out)

NF_IO[2]

(in/out)

SPI_SCn

(out)

MPP[1]

GPO[1] (out only)

NF_IO[3]

(in/out)

SPI_MOSI

(out)

MPP[2]

GPO[2] (out only)

NF_IO[4]

(in/out)

SPI_SCK

(out)

-

-

-

-

-

-

-

-

-

MPP[3]

GPO[3] (out only)

NF_IO[5]

(in/out)

SPI_MISO

(in)

MPP[4]

GPIO[4]

(in/out)

NF_IO[6]

(in/out)

UA0_RXD

(in)

-

-

-

-

-

-

MPP[5]

GPO[5] (out only)

NF_IO[7]

(in/out)

UA0_TXD

(out)

MPP[6] -

-

SYSRST_O

UTn (out)

SPI_MOSI

(out)

PTP_TRIG_

GEN (out)

PTP_TRIG_

GEN (out)

SATA_ACT n (out)

-

-

-

-

-

-

-

-

-

-

-

-

PTP_CLK

(in)

-

-

MPP[7]

GPO[7] (out only)

PEX_RST_

OUTn (out)

SPI_SCn

(out)

PTP_TRIG_

GEN (out)

-

MPP[8]

MPP[9]

MPP[10]

GPIO[8]

(in/out)

GPIO[9]

(in/out)

GPO [10]

(out only)

TW_SDA

(in/out)

TW_SCK

(in/out)

-

UA0_RTS

(out)

UA1_RTS

(out)

MII0_RXER

R (in)

UA0_CTS

(in)

UA1_CTS

(in)

-

-

PTP_CLK

(in)

MII0_COL

(in)

SATA_PRE

SE NTn

(out)

PTP_EVEN

T_REQ (in)

MII0_CRS

(in)

SPI_SCK

(out)

UA0_TXD

(out)

-

PTP_TRIG_

GEN (out)

-

MPP[11]

GPIO[11]

(in/out)

-

SPI_MISO

(in)

UA0_RXD

(in)

PTP_EVEN

T_REQ (in)

SATA_ACT n (out)

PTP_TRIG_

GEN (out)

PTP_clk

(in)

MPP[12]

GPO[12]

(out only)

SD_CLK

(out)

-

MPP[13]

GPIO[13]

(in/out)

SD_CMD

(in/out)

-

UA1_TXD

(out)

-

MPP[14]

MPP[15]

GPIO[14]

(in/out)

SD_D[0]

(in/out)

-

UA1_RXD

(in)

-

GPIO[15]

(in/out)

SD_D[1]

(in/out)

UA0_RTS

(out)

UA1_TXD

(out)

SATA_ACT n (out)

MPP[16]

GPIO[16]

(in/out)

SD_D[2]

(in/out)

UA0_CTS

(in)

UA1_RXD

(in)

-

MPP[17]

GPIO[17]

(in/out)

SD_D[3]

(in/out)

-

SATA_PRE

SE NTn

(out)

-

-

-

-

-

-

-

-

-

-

-

MII0_COL

(in)

-

MII0_CRS

(in)

-

Copyright © 2008 Marvell

December 2, 2008, Preliminary Document Classification: Proprietary Information

Doc. No. MV-S104987-U0 Rev. F

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Hardware Specifications

Table 30: 88F6190 MPP Function Summary (Continued)

Pin name 0x0 0x1 0x2 0x3 0x4

MPP[18]

GPO[18]

(out only)

NF_IO[0]

(in/out)

MPP[19]

GPO[19]

(out only)

NF_IO[1]

(in/out)

MPP[20]

GPIO[20]

(in/out)

MPP[21]

GPIO[21]

(in/out)

MPP[22]

GPIO[22]

(in/out)

MPP[23]

GPIO[23]

(in/out)

MPP[24]

GPIO[24]

(in/out)

-

-

-

-

-

MPP[25]

GPIO[25]

(in/out)

MPP[26]

GPIO[26]

(in/out)

MPP[27]

GPIO[27]

(in/out)

MPP[28]

GPIO[28]

(in/out)

MPP[29]

GPIO[29]

(in/out)

MPP[30]

GPIO[30]

(in/out)

MPP[31]

GPIO[31]

(in/out)

MPP[32]

GPIO[32]

(in/out)

MPP[33]

GPO[33]

(out only)

MPP[34]

GPIO[34]

(in/out)

MPP[35]

GPIO[35]

(in/out)

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

GE1[0]

GE1[1]

GE1[2]

GE1[3]

GE1[4]

GE1[5]

GE1[6]

GE1[7]

GE1[8]

GE1[9]

GE1[10]

GE1[11]

GE1[12]

GE1[13]

GE1[14]

GE1[15]

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

0x5

SATA_ACT n (out)

-

SATA_PRE

SE NTn

(out)

-

-

-

-

-

-

-

-

-

-

-

-

-

-

0xC

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

SATA_ACT n (out)

MII0_RXER

R (in)

0xD

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

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December 2, 2008, Preliminary

Pin Multiplexing

Multi-Purpose Pins Functional Summary

Table 31: 88F6192 MPP Function Summary

Pin name 0x0 0x1 0x2 0x3 0x4 0x5 0xC 0xD

MPP[0]

GPIO[0]

(in/out)

NF_IO[2]

(in/out)

SPI_SCn

(out)

MPP[1]

GPO[1] (out only)

NF_IO[3]

(in/out)

SPI_MOSI

(out)

MPP[2]

GPO[2] (out only)

NF_IO[4]

(in/out)

SPI_SCK

(out)

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

MPP[3]

GPO[3] (out only)

NF_IO[5]

(in/out)

SPI_MISO

(in)

-

MPP[4]

GPIO[4]

(in/out)

NF_IO[6]

(in/out)

UA0_RXD

(in)

-

MPP[5]

GPO[5] (out only)

NF_IO[7]

(in/out)

UA0_TXD

(out)

MPP[6] -

-

SYSRST_O

UTn (out)

SPI_MOSI

(out)

PTP_TRIG_

GEN (out)

-

SATA1_AC

Tn (out)

PTP_TRIG_

GEN (out)

SATA0_AC

Tn (out)

-

MPP[7]

MPP[8]

MPP[9]

MPP[10]

GPO[7] (out only)

PEX_RST_

OUTn (out)

GPIO[8]

(in/out)

GPIO[9]

(in/out)

GPO [10]

(out only)

TW_SDA

(in/out)

TW_SCK

(in/out)

-

SPI_SCn

(out)

PTP_TRIG_

GEN (out)

SPI_SCK

(out)

UA0_TXD

(out)

-

UA0_RTS

(out)

UA0_CTS

(in)

UA1_RTS

(out)

MII0_RXER

R (in)

UA1_CTS

(in)

-

SATA1_PR

ESE NTn

(out)

SATA0_PR

ESE NTn

(out)

PTP_CLK

(in)

PTP_EVEN

T_REQ (in)

MII0_COL

(in)

MII0_CRS

(in)

-

-

SATA1_AC

Tn (out)

PTP_TRIG_

GEN (out)

-

-

MPP[11]

GPIO[11]

(in/out)

-

SPI_MISO

(in)

UA0_RXD

(in)

PTP_EVEN

T_REQ (in)

SATA0_AC

Tn (out)

PTP_TRIG_

GEN (out)

PTP_clk

(in)

MPP[12]

GPO[12]

(out only)

SD_CLK

(out)

-

MPP[13]

MPP[14]

MPP[15]

GPIO[13]

(in/out)

GPIO[14]

(in/out)

GPIO[15]

(in/out)

SD_CMD

(in/out)

SD_D[0]

(in/out)

SD_D[1]

(in/out)

-

-

UA1_TXD

(out)

-

UA1_RXD

(in)

SATA1_PR

ESE NTn

(out)

UA0_RTS

(out)

UA1_TXD

(out)

SATA0_AC

Tn (out)

MPP[16]

MPP[17]

GPIO[16]

(in/out)

SD_D[2]

(in/out)

GPIO[17]

(in/out)

SD_D[3]

(in/out)

UA0_CTS

(in)

UA1_RXD

(in)

SATA1_AC

Tn (out)

-

SATA0_PR

ESE NTn

(out)

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

PTP_CLK

(in)

-

-

-

MII0_COL

(in)

-

MII0_CRS

(in)

-

Copyright © 2008 Marvell

December 2, 2008, Preliminary Document Classification: Proprietary Information

Doc. No. MV-S104987-U0 Rev. F

Page 65

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Hardware Specifications

Table 31: 88F6192 MPP Function Summary (Continued)

Pin name 0x0 0x1 0x2 0x3 0x4 0x5 0xC

MPP[18]

GPO[18]

(out only)

NF_IO[0]

(in/out)

MPP[19]

GPO[19]

(out only)

NF_IO[1]

(in/out)

-

-

-

-

-

-

-

-

MPP[20]

GPIO[20]

(in/out)

TSMP[0]

(in/out)

TDM_CH0_

TX_QL (out)

GE1[0]

AU_SPDIFI

(in)

SATA1_AC

Tn (out)

MPP[21]

MPP[22]

MPP[23]

MPP[24]

GPIO[21]

(in/out)

GPIO[22]

(in/out)

GPIO[23]

(in/out)

GPIO[24]

(in/out)

TSMP[1]

(in/out)

TDM_CH0_

RX_QL (out)

TSMP[2]

(in/out)

TSMP[3]

(in/out)

TSMP[4]

(in/out)

TDM_CH2_

TX_QL (out)

TDM_CH2_

RX_QL (out)

TDM_SPI_

CS0 (out)

GE1[1]

GE1[2]

GE1[3]

GE1[4]

AU_SPDIF

O (out)

SATA0_AC

Tn (out)

AU_SPDIF

RMCLK(out

)

AU_I2SBCL

K (out)

SATA1_PR

ESENTn

(out)

SATA0_PR

ESENTn

(out)

AU_I2SDO

(out)

-

MPP[25]

GPIO[25]

(in/out)

TSMP[5]

(in/out)

TDM_SPI_

SCK (out)

GE1[5]

AU_I2SLRC

LK (out)

-

MPP[26]

GPIO[26]

(in/out)

TSMP[6]

(in/out)

TDM_SPI_

MISO (in)

GE1[6]

AU_I2SMC

LK (out)

MPP[27]

MPP[28]

MPP[29]

MPP[30]

GPIO[27]

(in/out)

GPIO[28]

(in/out)

GPIO[29]

(in/out)

GPIO[30]

(in/out)

TSMP[7]

(in/out)

TSMP[8]

(in/out)

TSMP[9]

(in/out)

TDM_SPI_

MOSI (out)

TDM_COD

EC_INTn

(in)

TDM_COD

EC_RSTn

(out)

GE1[7]

GE1[8]

GE1[9]

TSMP[10]

(in/out)

TDM_PCLK

(in/out)

GE1[10]

AU_I2SDI

(in)

AU_EXTCL

K (in)

-

-

MPP[31]

GPIO[31]

(in/out)

TSMP[11]

(in/out)

TDM_FS

(in/out)

GE1[11] -

-

-

-

-

-

-

MPP[32]

GPIO[32]

(in/out)

TSMP[12]

(in/out)

TDM_DRX

(in)

GE1[12]

MPP[33]

MPP[34]

GPO[33]

(out only)

GPIO[34]

(in/out)

-

-

TDM_DTX

(out)

GE1[13]

TDM_SPI_

CS1 (out)

GE1[14]

MPP[35]

GPIO[35]

(in/out)

-

TDM_CH0_

TX_QL (out)

GE1[15]

-

-

-

-

-

-

SATA1_AC

Tn (out)

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

SATA0_AC

Tn (out)

MII0_RXER

R (in)

0xD

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

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December 2, 2008, Preliminary

Pin Multiplexing

Multi-Purpose Pins Functional Summary

Note

„

For MPPs assigned as NAND flash and SPI flash, wake-up mode after reset

depends on Boot mode (see the Boot Device field in Table 38, Reset

Configuration, on page 77 ):

When Boot mode is NAND Flash, MPP[5:0] and MPP[19:18] wake up after reset in NAND Flash mode.

When Boot mode is SPI Flash, either MPP[3:0] or {MPP[3:1] and MPP[7]} wake up after reset in SPI mode, (according to boot mode configured by reset strap pins).

Pin MPP[6] wakes up after reset in 0x1 mode (SYSRST_OUTn)

„

„

„

„

Pin MPP[7] wakes up after reset:

As SPI_CSn, if the boot device—selected according to boot device reset strapping—is 0x2 (boot from SPI flash, SPI_CSn on MPP[7]).

As PEX_RST_OUTn, if the boot device—selected according to boot device reset strapping—is any option other than 0x2.

When TWSI serial ROM initialization is enabled (see

TWSI Serial ROM

Initialization in Table 38, Reset Configuration, on page 77

), MPP[8] and MPP[9] wake up as TWSI data and clock pins, respectively.

All other MPP interface pins wake up after reset in 0x0 mode (GPIO/GPO) and are default set to Data Output disabled (Tri-State). Therefore, those MPPs that are

GPIO are in fact inputs, and those that are GPO are Tri-State.

The SPI interface can be configured using one of the following sets of MPP pins:

„

„

„

„

MPP[3:0]

MPP[11], MPP[10], MPP[7], and MPP[6]

MPP[3:1] and MPP[7]

Do not configure both MPP[3] and MPP[11] as SPI_MISO.

UART0 and UART1 signals are duplicated on a few MPPs. The UART0 or UART1 signals must not be configured to more than one MPP.

Some of the MPP pins are sampled during SYSRSTn de-assertion to set the device configuration. These pins must be set to the correct value during reset (see

Section 8.5, Pins Sample Configuration, on page 76 ).

„ Pins that are left as GPIO and are not connected should be set to output after

SYSRSTn de-assertion.

Copyright © 2008 Marvell

December 2, 2008, Preliminary Document Classification: Proprietary Information

Doc. No. MV-S104987-U0 Rev. F

Page 67

6.2

88F619x

Hardware Specifications

Gigabit Ethernet (GbE) Pins Multiplexing on MPP

88F6190

„

„

Contains 14 dedicated pins for its GbE port (12 GMII pins, an MDC pin, and an

MDIO pin).

Includes additional GbE interface pins that are multiplexed on the MPPs, to serve as the remaining pin interfaces to an external PHY or switch:

RGMII

„

MII/MMII

GMII

88F6192

„

„

„

Contains 14 dedicated pins for its GbE ports. (12 RGMII/GMII pins, an MDC pin, and an MDIO pin).

Includes additional GbE interface pins that are multiplexed on the MPPs, to serve as the following interfaces to an external PHY or switch:

GMII

2 x RGMII

RGMII + MII/MMII

Table 32 summarizes the GbE port pins multiplexing for the 88F6190.

Table 32: 88F6190 Ethernet Ports Pins Multiplexing

P i n N a m e

GE_TXCLKOUT

GE_TXD[3:0]

GE_TXCTL

GE_RXD[3:0]

GE_RXCTL

GE_RXCLK

MPP [23:20] / GE1[3:0]

MPP_[27:24] / GE1[7:4]

MPP_28 / GE1[8]

MPP_29 / GE1[9]

MPP_30 / GE1[10]

MPP_31 / GE1[11]

MPP_32 / GE1[12]

MPP_33 / GE1[13]

MPP_34 / GE1[14]

MPP_35 / GE1[15]

G M I I

GMII_TXCLKOUT (out)

GMII_TXD[3:0] (out)

GMII_TXEN (out)

GMII_RXD[3:0] (in)

GMII_RXDV (in)

GMII_RXCLK (in)

GMII_TXD[7:4] (out)

GMII_RXD[7:4] (in)

GMII_COL (in)

GMII_TXCLK (in)

GMII_RXERR (in)

NA

GMII_CRS (in)

GMII_TXERR (out)

NA

NA

R G M I I 0 + M I I 1 / M M I I 1

RGMII0_TXCLKOUT (out)

RGMII0_TXD[3:0] (out)

RGMII0_TXCTL (out)

RGMII0_RXD[3:0] (in)

RGMII0_RXCTL (in)

RGMII0_RXCLK (in)

MII1_TXD[3:0] (out)

MII1_RXD[3:0] (in)

MII1_COL (in)

MII1_TXCLK (in)

MII1_RXDV (in)

MII1_RXCLK (in)

MII1_CRS (in)

MII1_TXERR (out)

MII1_TXEN (out)

MII1_RXERR (in)

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December 2, 2008, Preliminary

Pin Multiplexing

Gigabit Ethernet (GbE) Pins Multiplexing on MPP

Table 33 summarizes the GbE port pins multiplexing for the 88F6192.

Table 33: 88F6192 Ethernet Ports Pins Multiplexing

P i n N a m e

GE_TXCLKOUT GMII0_TXCLKOUT

(out)

GE_TXD[3:0] GMII0_TXD[3:0] (out)

GE_TXCTL

MPP_28 /

GE1[8]

MPP_29 /

GE1[9]

MPP_30 /

GE1[10]

MPP_31 /

GE1[11]

MPP_32 /

GE1[12]

MPP_33 /

GE1[13]

MPP_34 /

GE1[14]

MPP_35 /

GE1[15]

GE_RXD[3:0]

GE_RXCTL

GE_RXCLK

MPP[8] or

MPP[35]

MPP[8] or

MPP[14]

MPP[9] or

MPP[16]

MPP [23:20] /

GE1[3:0]

MPP_[27:24] /

GE1[7:4]

1 x G M I I

GMII0_TXEN (out)

GMII0_RXD[3:0] (in)

GMII0_RXDV (in)

GMII0_RXCLK (in)

NA

NA

NA

GMII0_TXD[7:4] (out)

GMII0_RXD[7:4] (in)

GMII0_COL (in)

GMII0_TXCLK (in)

GMII0_RXERR (in)

NA

GMII0_CRS (in)

GMII0_TXERR (out)

NA

NA

R G M I I 0 + M I I 1 /

M M I I 1

2 x R G M I I

RGMII0_TXCLKOUT

(out)

RGMII0_TXD[3:0]

(out)

RGMII0_TXCTL (out)

RGMII0_TXCLKOUT

(out)

RGMII0_TXD[3:0]

(out)

RGMII0_TXCTL (out)

RGMII0_RXD[3:0] (in) RGMII0_RXD[3:0] (in)

RGMII0_RXCTL (in) RGMII0_RXCTL (in)

RGMII0_RXCLK (in)

NA

RGMII0_RXCLK (in)

NA

NA

NA

MII1_TXD[3:0] (out)

MII1_RXD[3:0] (in)

MII1_COL (in)

MII1_TXCLK (in)

MII1_RXDV (in)

MII1_RXCLK (in)

MII1_CRS (in)

MII1_TXERR (out)

MII1_TXEN (out)

MII1_RXERR (in)

NA

NA

M I I 0 / M M I I 0 +

R G M I I 1

MII0_TXCLK (in)

MII0_TXEN (out)

MII0_RXD[3:0] (in)

MII0_RXDV (in)

MII0_RXCLK (in)

MII0_RXERR (in)

RGMII1_TXD[3:0]

(out)

RGMII1_TXD[3:0]

(out)

RGMII1_RXD[3:0] (in) RGMII1_RXD[3:0] (in)

NA

NA

RGMII1_RXCTL (in)

RGMII1_RXCLK (in)

RGMII1_TXCLKOUT

(out)

RGMII1_TXCTL (out)

NA

NA

MII0_TXD[3:0] (out)

MII0_COL (in)

MII0_CRS (in)

NA

NA

RGMII1_RXCTL (in)

RGMII1_RXCLK (in)

RGMII1_TXCLKOUT

(out)

RGMII1_TXCTL (out)

NA

NA

Note

When using Gigabit Ethernet signals on MPPs, all relevant Gigabit Ethernet signals

(except those marked as NA) must be implemented. For example, if using MII, and the chosen PHY does not have an MII_RXERR out signal, the MII_RX_ERR (in) (MPP[35]) must still be configured accordingly and must have a pull-down resistor.

Copyright © 2008 Marvell

December 2, 2008, Preliminary Document Classification: Proprietary Information

Doc. No. MV-S104987-U0 Rev. F

Page 69

6.3

88F619x

Hardware Specifications

TSMP (TS Multiplexing Pins) on MPP

The TSMP multiplexing information is only relevant for the 88F6192.

Note

„

„

„

„

„

The TS interface can be configured to one of five modes:

One or two serial in interfaces

One or two serial out interfaces

Serial in and serial out interface

Parallel in interface

Parallel out interface

In parallel in or serial in mode, all TS signals are inputs.

In parallel out or serial out mode, all TS signals are outputs.

Table 34 summarizes the TS port pins multiplexing.

Table 34: TS Port Pin Multiplexing

P i n

N a m e

TSMP[0]

TSMP[1]

TSMP[2]

TSMP[3]

TSMP[4]

TSMP[5]

TSMP[6]

TSMP[7]

TSMP[8]

TSMP[9]

TSMP[10]

TSMP[11]

TSMP[12]

F u n c t i o n a l i t y i n T S s e r i a l m o d e s

2 x i n / 2 x o u t / i n + o u t

EXT_CLK (in)

TS0_CLK (in/out))

TS0_SYNC(in/out))

TS0_VAL (in/out))

TS0_ERR (in/out))

TS0_DATA[0] (in/out)

TS1_CLK (in/out))

TS1_SYNC(in/out))

TS1_VAL (in/out))

TS1_ERR (in/out))

TS1_DATA[0] (in/out)

NA

NA

F u n c t i o n a l i t y i n T S pa r a l l e l i n / o u t m o d e

EXT_CLK (in)

TS0_CLK (in/out))

TS0_SYNC(in/out))

TS0_VAL (in/out))

TS0_ERR (in/out))

TS0_DATA[0] (in/out)

TS0_DATA[1] (in/out))

TS0_DATA[2] (in/out))

TS0_DATA[3] (in/out))

TS0_DATA[4] (in/out))

TS0_DATA[5] (in/out))

TS0_DATA[6] (in/out))

TS0_DATA[7] (in/out))

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December 2, 2008, Preliminary

Clocking

7

Clocking

Table 35 lists the clocks in the 88F619x.

Table 35: 88F619x Clocks

C l o c k Ty p e

CPU PLL

D e s c r i p t i o n

• Reference clock:

REF_CLK_XIN (25 MHz)

• Derivative clocks:

- CPU clock

- L2 cache clock

- DDR Clock (the Mbus-L uses the DDR clock.)

NOTE: See Table 38, Reset Configuration, on page 77 for CPU, L2 cache and

DDR frequency configuration.

Core PLL

PEX PHY

USB PHY PLL

L2 cache clock frequency must be equal or higher then DDR clock frequency.

If the SSCG enable bit in the Sampled at Reset register is set, then the

SSCG circuit is applied for the CPU PLL reference clock (refer to the

Sampled at Reset register in the 88F6180, 88F6190, 88F6192, and

88F6281 Functional Specifications).

• Reference clock:

REF_CLK_XIN (25 MHz)

• Derivative clocks:

- TCLK (core clock, 166 MHz)

- SDIO Clock (100 MHz)

- Gigabit Ethernet Clock (125 MHz)

- TS unit Clock(100/91/83/77MHz) (88F6192 only)

- SPI clock (TCLK/30–TCLK/4 MHz)

- SMI clock (TCLK/128 MHz)

- TWSI clock (up to TCLK/1600)

NOTE: See Table 38, Reset Configuration, on page 77 for TCLK frequency

configuration.

NOTE: See the TS Interface Configuration register in the 88F6180, 88F6190,

88F6192, and 88F6281 Functional Specifications for TS clock frequency configuration (88F6192 only).

There are two options for the reference clock configuration, depending on the PCI

Express clock 100 MHz differential clock:

• The device uses an external source for PCI Express clock. The PEX_CLK_P pin is an input.

• The device uses an internal generated clock for PCI Express clock. The

PEX_CLK_P pin is an output, driving out the PCI Express differential clock.

• Reference clock:

REF_CLK_XIN (25 MHz)

Copyright © 2008 Marvell

December 2, 2008, Preliminary Document Classification: Proprietary Information

Doc. No. MV-S104987-U0 Rev. F

Page 71

88F619x

Hardware Specifications

7.1

Table 35: 88F619x Clocks (Continued)

C l o c k Ty p e

SATA PHY PLL

RTC

PTP

D e s c r i p t i o n

• Reference clock:

REF_CLK_XIN (25 MHz)

• Derivative clock:

SATA Clock (150 MHz)

• Reference clock:

RTC_XIN (32.768 kHz)

Used for real time clock functionality, see the Real Time Clock section in the

88F6180, 88F6190, 88F6192, and 88F6281 Functional Specifications.

• Reference clock:

PTP_CLK (125 MHz)

The PTP_CLK can be used for the following functions:

• PTP time stamp clock

Two options for reference clock:

- PTP_CLK

- Gigabit Ethernet Clock (125 MHz)

• TS unit clock

Two options for reference clock:

- PTP_CLK/2

- Core PLL

• Audio unit clock

Two options for reference clock:

- PTP_CLK

- REF_CLK_XIN (25 MHz)

For clocking configuration registers, see the 88F6180, 88F6190, 88F6192, and

88F6281 Functional Specifications.

The following table lists the supported combinations of the CPU_CLK Frequency select, CPU_CLK to DDR CLK ratio, and to CPU_CLK to CPU L2 clock ratio (see

Section 8.5, Pins Sample

Configuration, on page 76 ).

Table 36: Supported Clock Combinations

D e v i c e

88F6190:

88F6192:

D D R C l o c k

( M H z )

200

200

C P U t o D D R

C l o c k R a t i o

3:1

4:1

C P U C l o c k

( M H z )

600

800

C P U t o L 2

C l o c k R a t i o

2:1

2:1

L 2 C l o c k

( M H z )

300

400

Spread Spectrum Clock Generator (SSCG)

The SSCG (Spread Spectrum Clock Generator) may be used to generate the spread spectrum clock

for the PLL input. See SSCG Disable

in Table 38, Reset Configuration, on page 77

, for SSCG enable/bypass configuration settings.

The SSCG block can be configured to perform up spread, down spread and center spread.

The modulation frequency is configurable. Typical frequency is 30 kHz.

The spread percentage can also be configured up to 1%.

For additional details, see the SSCG Configuration Register description in the 88F6180, 88F6190,

88F6192, and 88F6281 Functional Specifications

.

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December 2, 2008, Preliminary

System Power Up/Down and Reset Settings

Power-Up/Down Sequence Requirements

8

System Power Up/Down and Reset

Settings

This section provides information about the device power-up/down sequence and configuration at reset.

8.1

8.1.1

Power-Up/Down Sequence Requirements

Power-Up Sequence Requirements

These guidelines must be applied to meet the 88F619x device power-up requirements:

„ The non-core voltages (I/O and Analog) as listed in

Table 37 must reach 70% of their voltage

level before the core voltages reach 70% of their voltage level.

The order of the power-up sequence between the non-core voltages is unimportant so long as the non-core voltages power up before the core voltages reach 70% of their voltage level

(shown in Figure 5 ).

„

„

The reset signal(s) must be asserted before the core voltages reach 70% of their voltage level

(shown in Figure 5 ).

The reference clock(s) inputs must toggle with their respective voltage levels before the core voltages reach 70% of their voltage level (shown in

Figure 5

).

„ If VHV is set to burning mode (2.5V), which is a higher voltage than the VDD voltage, VDD must be powered before VHV, to prevent the fuse from being accidentally burned.

Table 37: I/O and Core Voltages

I / O Vo l ta g e s

VDD_GE_A

VDD_GE_B

VDD_M

VDDO

N o n - C o r e Vo l ta g e s

A n a l o g P o w e r S u p p l i e s

CPU_PLL_AVDD

CORE_PLL_AVDD

PEX_AVDD

RTC_AVDD

88F6190

SATA_AVDD

88F6192 – SATA0_AVDD

88F6192 – SATA1_AVDD

SSCG_AVDD

XTAL_AVDD

USB_AVDD

C o r e Vo l ta g e s

VDD

Copyright © 2008 Marvell

December 2, 2008, Preliminary Document Classification: Proprietary Information

Doc. No. MV-S104987-U0 Rev. F

Page 73

88F619x

Hardware Specifications

Figure 5: Power-Up Sequence Example

Voltage

Non-Core Voltage

Core Voltage

70% of

Non-Core

Voltage

70% of Core

Voltage

8.1.2

8.2

Reset(s)

Clock(s)

Note

„

„

It is the designer's responsibility to verify that the power sequencing requirements of other components are also met.

Although the non-core voltages can be powered up any time before the core voltages, allow a reasonable time limitation (for example, 100 ms) between the

first non-core voltage power-up and the last core voltage power-up.

Power-Down Sequence Requirements

There are no special requirements for the core supply to go down before non-core power, or for reset assertion when powering down (except for VHV, as described below). However, allow a reasonable time limitation (no more than 100 ms) between the first and last voltage power-down.

When using the eFuse in Burning mode, VHV must be powered down before VDD.

Hardware Reset

„

„

„

„

„

The device has one reset input pin—SYSRSTn. When asserted, the entire chip is placed in its initial state. Most outputs are placed in high-z, except for the following output pins, that are still active during SYSRSTn assertion:

M_CLKOUT, M_CLKOUTn

M_CKE

M_ODT

M_STARTBURST

SYSRST_OUTn

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December 2, 2008, Preliminary

8.2.1

8.2.2

8.2.3

System Power Up/Down and Reset Settings

Hardware Reset

Note

Reset (SYSRSTn signal) must be active for a minimum length of 5 ms. core power, I/O power, and analog power must be stable (VDD +/- 5%) during that time and onward.

Reset Out Signal

The device has an optional SYSRST_OUTn output signal, multiplexed on an MPP pin, that is used as a reset request from the device to the board reset logic. SYSRST_OUTn is the default option for that MPP pin.

This signal is asserted low for 20 ms, when one of the following maskable events occurs:

„ Received hot reset indication from the PCI Express link (only relevant when used as a PCI

Express endpoint), and bit <PexRstOutEn> is set to 1 in the RSTOUTn Mask Register (see the

Reset register section of the 88F6180, 88F6190, 88F6192, and 88F6281 Functional

Specifications).

„ PCI Express link failure (only relevant when used as a PCI Express endpoint), and bit

<PexRstOutEn> is set to 1 in the RSTOUTn Mask Register.

„

„

Watchdog timer expiration and bit <WDRstOutEn> is set to 1 in the RSTOUTn Mask Register.

Bit <SystemSoftRst> is set to 1 in System Soft Reset Register and bit <SoftRstOutEn> is set to 1 in RSTOUTn Mask Register.

This signal is asserted low for 20 ms, when the POR (power on reset) non-maskable event occurs.—the device includes a power on reset circuit for VDD power.

Power On Reset (POR)

The SYSRST_OUTn output signal is asserted low for 20 ms, when the power-on-reset (POR) circuit is triggered.

POR is triggered when VDD power up (digital core voltage) reaches a VDD threshold (threshold maximum value 0.8V).

Hysteresis: Another trigger will only occur after the power first drops to 50 mV, and then a power up occurs.

SYSRSTn Duration Counter

„

„

„

„

When SYSRSTn is asserted low, a SYSRSTn duration counter is running.

The counter clock is the 25 MHz reference clock.

It is a 29-bit counter, yielding a maximum counting duration of 2^29/25 MHz (21.4 seconds).

The host software can read the counter value and reset the counter.

When the counter reach its maximum value, it remains at this value until counter reset is triggered by software.

Note

The SYSRSTn duration counter is useful for implementing manufacturer/factory reset.

Upon a long reset assertion, greater than a pre-configured threshold, the host software may reset all settings to the factory default values.

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Page 75

8.3

8.3.1

8.3.2

8.4

8.5

88F619x

Hardware Specifications

PCI Express Reset

PCI Express Root Complex Reset

As a Root Complex, the device may generate a Hot Reset to the PCI Express port. Upon CPU setting the PCI Express Control register’s <conf_mstr_hot_reset> bit, the PCI Express unit sends a

Hot Reset indication to the Endpoint, see the PCI Express Interface section in the 88F6180,

88F6190, 88F6192, and 88F6281 Functional Specifications.

PCI Express Endpoint Reset

„

„

When a Hot Reset packet is received:

„

A maskable interrupt is asserted.

If the <conf_dis_hot_rst_reg_rst> field in the PCI Express Debug Control register is cleared, the device also resets the PCI Express register file to its default values.

The device triggers an internal reset, if not masked by the <conf_msk_hot_reset> field in the

PCI Express Debug Control register.

„

„

Link failure is detected if the PCI Express link was up (LTTSSM L0 state) and dropped back to an inactive state (LTSSM Detect state). When Link failure is detected:

A maskable interrupt is asserted.

If the <conf_dis_link_fail_reg_rst> field in the PCI Express Debug Control register is cleared, the device also resets the PCI Express register file to its default values.

„ The device triggers an internal reset, if the <conf_msk_link_fail> field is not masked by PCI

Express Debug Control register.

„

„

Both link fail and hot reset conditions trigger a chip internal reset (if not masked in the PCI Express interface). All the chip logic is reset to the default values, except for sticky registers and the sample on reset logic. In addition, these events can trigger reset to the board, using one of the following:

PEX_RST_OUTn signal (multiplexed on MPP).

SYSRST_OUTn output (multiplexed on MPP)—if not masked by the <PexRstOutEn> bit.

The external reset logic (on the board) may assert the SYSRSTn input pin and reset the entire chip.

Sheeva

CPU TAP Controller Reset

The Sheeva

CPU Test Access Port (TAP) controller is reset when JT_RSTn is set and

JT_TMS_CPU is active.

Pins Sample Configuration

The following pins are sampled during SYSRSTn de-assertion:

„

Internal pull up/down resistors set the default mode (see

Section 2.3, Internal Pull-up and

Pull-down Pins, on page 55 ).

„

Higher value, external pull up/down resistors are required to change the default mode of operation.

These signals must remain pulled up or down until SYSRSTn de-assertion (zero hold time in respect to SYSRSTn de-assertion).

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System Power Up/Down and Reset Settings

Pins Sample Configuration

Note

„

„

„

If external logic is used instead of pull-up and pull-down resistors, the logic must drive all of these signals to the desired values during SYSRSTn assertion. To prevent bus contention on these pins, the external logic must float the bus no later than the third TCLK cycle after SYSRSTn de-assertion.

All reset sampled values are registered in the Sample at Reset register (see the

MPP Registers in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional

Specifications). This is useful for board debug purposes and identification of board and system settings for the host software.

If a signal is pulled up on the board, it must be pulled to the proper voltage level. In the devices, certain reset configuration pins are powered by VDD_GE_A and

VDD_GE_B. In the 88F6190 VDD_GE_A has multiple voltage options, and in the

88F6192, VDD_GE_A and VDD_GE_B have multiple voltage options (see

Table 42, Recommended Operating Conditions, on page 87 ).

In each row of Table 38

, the order of the pins is from MSb to LSb (e.g., for in the row CPU_CLK

Frequency Select, MPP[2] is the MSB and MPP[10] is the LSB).

Table 38: Reset Configuration

P i n

MPP[1]

MPP[2],

MPP[5]

MPP[10]

MPP[19]

MPP[33],

C o n f i g u r a t i o n F u n c t i o n

TWSI Serial ROM Initialization

0 = Disabled

1 = Enabled

NOTE: Internally pulled down to 0x0.

When this pin is set to 0x1, MPP[8] and MPP[9] wake up as TWSI data and clock pins,

respectively (see Section 6.1, Multi-Purpose Pins Functional Summary, on page 61

).

Used for internal testing

Must be 0x0 during reset.

Either leave the signal floating (internally pulled down to 0x0) or pull the signal to 0x0 during reset.

Reserved

For the 88F6190:

NOTE: Must be externally pulled down to 0x0 during reset.

For the 88F6192:

Must be 0x1 during reset.

Either leave the signal floating (internally pulled up to 0x1) or pull the signal to 0x1 during reset.

Used for internal testing

Must be 0x0 during reset.

Either leave the signal floating (internally pulled down to 0x0) or pull the signal to 0x0 during reset.

Reserved

Must be 0x1 during reset.

Either leave the signal floating (internally pulled up to 0x1) or pull the signal.

Reserved

Must be 0x0 during reset.

Either leave the signal floating (internally pulled down to 0x0) or pull the signal to 0x0 during reset.

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Hardware Specifications

Table 38: Reset Configuration (Continued)

P i n

NF_ALE

NF_REn

NF_CLE

MPP[3]

MPP[12]

NF_WEn

C o n f i g u r a t i o n F u n c t i o n

Reserved

Must be 0x1 during reset.

Either leave the signal floating (internally pulled up to 0x1) or pull the signal to 0x1 during reset.

Reserved

For the 88F6190:

Must be 0x0 during reset.

Either leave the signal floating (internally pulled down to 0x0) or pull the signal to 0x0 during reset.

For the 88F6192:

NOTE: Must be externally pulled up to 0x1 during reset.

Reserved

Must be 0x0 during reset.

Either leave the signal floating (internally pulled down to 0x0) or pull the signal to 0x0 during reset.

Reserved

Must be 0x0 during reset.

Either leave the signal floating (internally pulled down to 0x0) or pull the signal to 0x0 during reset.

Reserved

Must be 0x0 during reset.

Either leave the signal floating (internally pulled down to 0x0) or pull the signal to 0x0 during reset.

Reserved

Must be 0x1 during reset.

Either leave the signal floating (internally pulled up to 0x1) or pull the signal to 0x1 during reset.

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System Power Up/Down and Reset Settings

Pins Sample Configuration

Table 38: Reset Configuration (Continued)

P i n

GE_TXD[2:0]

C o n f i g u r a t i o n F u n c t i o n

Boot Device

0x0 = Reserved

0x1 = Reserved

0x2 = Boot from SPI flash (SPI_CSn on MPP[7])

0x3 = Reserved

0x4 = Boot from SPI flash (SPI_CSn on MPP[0])

0x5 = Boot from NAND flash

0x6 = Boot from SATA

0x7 = Boot from the PCI Express port

GE_TXD[3]

GE_MDC

88F6190 –

GE_TXEN

88F6192

GE_TXCTL

MPP[7]

NOTE:

• Internally pulled to 0x4.

• Only SPI signals configured on pins MPP[3:0] or on pins MPP[7] and MPP[3:1] can be used for booting from SPI.

SPI signals that are multiplexed on other MPPs can only be used after booting (see Section 6.1,

Multi-Purpose Pins Functional Summary, on page 61 ).

• When GE_TXD[2:0] is set to 0x4, MPP[3:0] wake up as SPI signals.

• When GE_TXD[2:0] is set to 0x2, MPP[7] and MPP[3:1] wake up as SPI signals.

• When GE_TXD[2:0] is set to 0x5, MPP[5:0] and MPP[19:18] wake up as NAND Flash signals.

• For a more detailed description of the bootROM, see the BootROM section in the 88F6180,

88F6190, 88F6192, and 88F6281 Functional Specifications.

• For a more detailed description of the boot from SPI flash or NAND flash, see the SPI Interface and NAND Flash Interface sections in the 88F6180, 88F6190, 88F6192, and 88F6281 Functional

Specifications.

• There is an option to boot from UART when GE_TXD[2:0] = 0x2–0x7. For a more detailed description of the boot from UART, see the BootROM section in the 88F6180, 88F6190,

88F6192, and 88F6281 Functional Specifications.

SSCG Disable

0 = Enable

1 = Disable

NOTE: Internally pulled to 0x1.

PCI Express Clock (100 MHz Differential Clock) Configuration

0x0 = The device use external source for PCI Express clock. Pins PEX_CLK_P/PEX_CLK_N are inputs.

0x1 = The device uses internal generated clock for PCI Express clock. Pins

PEX_CLK_P/PEX_CLK_N pins are outputs, driving out the PCI Express differential clock.

NOTE: Internally pulled to 0x1.

Used for internal testing

Must be 0x0 during reset. Either leave the signal floating (internally pulled down to 0x0) or pull the signal to

0x0 during reset.

Reserved

Must be 0x1 during reset. Either leave the signal floating (internally pulled up to 0x1) or pull the signal to 0x1 during reset.

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Hardware Specifications

Table 38: Reset Configuration (Continued)

P i n

MPP[18]

C o n f i g u r a t i o n F u n c t i o n

Reserved

Must be 0x1 during reset. Either leave the signal floating (internally pulled up to 0x1) or pull the signal to 0x1 during reset.

8.6

8.6.1

Serial ROM Initialization

The device supports initialization of ALL of its internal and configuration registers through the TWSI master interface. If serial ROM initialization is enabled, the device TWSI master starts reading initialization data from serial ROM and writes it to the appropriate registers, upon de-assertion of

SYSRSTn.

When using Serial ROM Initialization, the MPP[9:8] pins must be configured to as TW_SCK

(MPP[9]) and TW_SDA (MPP[8]).

Serial ROM Data Structure

Serial ROM data structure consists of a sequence of 32-bit address and 32-bit data pairs, as shown

in Figure 6 .

Figure 6: Serial ROM Data Structure

Start

MSB LSB address0[31:24] address0[23:16] address0[15:8] address0[7:0] data0[31:24] data0[23:16] data0[15:8] data0[7:0] address1[31:24] address1[23:16] address1[15:8] address1[7:0] data1[31:24] data1[23:16] data1[15:8] data1[7:0]

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System Power Up/Down and Reset Settings

Boot Sequence

8.6.2

The serial ROM initialization logic reads eight bytes at a time. It performs address decoding on the

32-bit address being read, and based on address decoding result, writes the next four bytes to the required target.

The Serial Initialization Last Data Register contains the expected value of last serial data item

(default value is 0xFFFFFFFF). When the device reaches last data, it stops the initialization sequence.

Serial ROM Initialization Operation

On SYSRSTn de-assertion, the device starts the initialization process. It first performs a dummy write access to the serial ROM, with data byte(s) of 0x0, to set the ROM byte offset to 0x0. Then, it performs the sequence of reads, until it reaches last data item, as shown in

Figure 7

.

Figure 7: Serial ROM Read Example

8.7

s r t t a w t e i r s 1 0 1 0 0 0 0 0

ROM

Address a c k

Upper Byte Offset

0 0 0 0 0 0 0 0 a c k

Lower Byte Offset

0 0 0 0 0 0 0 0 a c k a r s t t r e a d s 1 0 1 0 0 0 0 1 a c k

ROM

Address

Data from

ROM

A A A A A A A A a c k

A A A A

Last Data from ROM

1 1 1 1 1 1 1 1 a c k

1 1 1 1 1 1 1 1 a c k

1 1 1 1 1 1 1 1 a c k

1 1 1 1 1 1 1 1 a c k x x x x x x x x c k n a s t o p p

„

„

„

For a detailed description of TWSI implementation, see the Two-Wire Serial Interface section in the

88F6180, 88F6190, 88F6192, and 88F6281

Functional Specifications.

„

Initialization data must be programmed in the serial ROM starting at offset 0x0.

The device assumes 7-bit serial ROM address of ‘b1010000.

After receiving the last data identifier (default value is 0xFFFFFFFF), the device receives an additional byte of dummy data. It responds with no-ack and then asserts the stop bit.

The serial EEPROM must contain two address offset bytes (It must not be less than a 256 byte

ROM.).

Boot Sequence

The device requires that SYSRSTn stay asserted for at least 300

μs after power and clocks are stable. The following procedure describes the boot sequence starting with the reset assertion:

1.

While SYSRSTn is asserted, the CPU PLL and the core PLL are locked.

2.

Upon SYSRSTn de-assertion, the pad drive auto-calibration process starts. It takes 512 TCLK cycles.

3.

If Serial ROM initialization is enabled, an initialization sequence is started.

4.

If configured to boot from NAND flash (and BootROM is disabled), the device also performs a

NAND Flash boot sequence to prepare page 0 in the NAND flash device for read.

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Hardware Specifications

Upon completing the above sequence, the internal CPU reset is de-asserted, and the CPU starts executing boot code from the boot device (SPI flash, NAND flash, or internal Boot ROM), according to sample at reset setting, see

Table 38, Reset Configuration, on page 77 .

For bootROM details, see the BootROM section in the

88F6180, 88F6190, 88F6192, and 88F6281

Functional Specifications.

„

„

As part of the CPU boot code, the CPU typically performs the following:

Configures the PCI Express address map.

Configures the proper SDRAM controller parameters, and then triggers SDRAM initialization

(sets <InitEn> bit [0] to 1 in the SDRAM Initialization Control register).

„ Sets the <PEXEn> bits in the CPU Control and Status register to wake up the PCI Express link.

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December 2, 2008, Preliminary

JTAG Interface

TAP Controller

9

JTAG Interface

To enable board testing, the device supports a test mode operation through its JTAG boundary scan interface.

The JTAG interface is IEEE 1149.1 standard compliant. It supports mandatory and optional boundary scan instructions.

9.1

9.2

TAP Controller

The Test Access Port (TAP) is constructed with a 5-pin interface and a 16-state Finite State Machine

(FSM), as defined by IEEE JTAG standard 1149.1.

To place the device in a functional mode, reset the JTAG state machine to disable the JTAG interface.

„

„

According to the IEEE 1149.1 standard, the JTAG state machine is not reset when the

88F619xSYSRSTn is asserted. The JTAG state machine can only be reset by one of the following methods:

Asserting JT_RSTn.

Setting JT_TMS_CORE for at least five JT_CLK cycles.

To place the device in one of the boundary scan test mode, the JTAG state machine must be moved to its control states. JT_TMS_CORE and JT_TDI inputs control the state transitions of the JTAG state machine, as specified in the IEEE 1149.1 standard. The JTAG state machine will shift instructions into the Instruction register while in SHIFT-IR state and shift data into and from the various data registers when in SHIFT-DR state.

Instruction Register

The Instruction register (IR) is a 4-bit, two-stage register. It contains the command that is shifted in when the TAP FSM is in the Shift-IR state. When the TAP FSM is in the Capture-IR state, the IR outputs all four bits in parallel.

Table 39 lists the instructions supported by the device.

Table 39: Supported JTAG Instructions

I n s t r u c t i o n

HIGHZ

IDCODE

EXTEST

SAMPLE/PRE

LOAD

BYPASS

C o d e

0011

0010

0000

0001

1111

D e s c r i p t i o n

Select the single bit Bypass register between TDI and TDO.

Sets the device output pins to high-impedance state.

Selects the Identification register between TDI and TDO. This 32-bit register is used to identify the device.

Selects the Boundary Scan register between TDI and TDO. Outputs the boundary scan register cells to drive the output pins of the device. Inputs the boundary scan register cell to sample the input pin of the device.

Selects the Boundary Scan register between TDI and TDO. Samples input pins of the device to input boundary scan register cells.

Preloads the output boundary scan register cells with the Boundary Scan register value.

Selects the single bit Bypass register between TDI and TDO. This allows for rapid data movement through an untested device.

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9.3

9.4

9.5

88F619x

Hardware Specifications

Bypass Register

The Bypass register (BR) is a single bit serial shift register that connects TDI to TDO, when the IR holds the Bypass command, and the TAP FSM is in Shift-DR state. Data that is driven on the TDI input pin is shifted out one cycle later on the TDO output pin. The Bypass register is loaded with 0 when the TAP FSM is in the Capture-DR state.

JTAG Scan Chain

The JTAG Scan Chain is a serial shift register used to sample and drive all of the device pins during the JTAG tests. It is a 2-bit per pin shift register in the device, thereby allowing the shift register to sequentially access all of the data pins both for driving and strobing data. For further details, refer to the BSDL Description file for the device.

ID Register

The ID register is a 32-bit deep serial shift register. The ID register is loaded with vendor and device information when the TAP FSM is in the Capture-DR state. The Identification code format of the ID

register is shown in Table 40

, which describes the various ID Code fields.

Table 40: IDCODE Register Map

B i ts Va l u e

31:28 0x0

27:12 0x6192

D e s c r i p t i o n

Version (4'b0010 for version A0, 4'b0011 for A1, etc.)

11:1 0x1AB

0 1 Mandatory

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December 2, 2008, Preliminary

Electrical Specifications (Preliminary)

Absolute Maximum Ratings

10

Electrical Specifications (Preliminary)

The numbers specified in this section are PRELIMINARY and SUBJECT TO CHANGE.

Note

10.1

Absolute Maximum Ratings

Table 41: Absolute Maximum Ratings

P a r a m e t e r

VDD

CPU_PLL_AVDD

CORE_PLL_AVDD

SSCG_AVDD

M i n

-0.5

-0.5

-0.5

M a x

1.2

2.2

2.2

U n i ts

V

V

V

C o m m e n ts

Core and CPU voltage

Analog supply for the internal PLL

VDD_GE_A

VDD_GE_B

VDD_M

VDDO

VHV

PEX_AVDD

USB_AVDD

88F6190

SATA_AVDD

88F6192

SATA0_AVDD

SATA1_AVDD

-0.5

-0.5

-0.5

-0.5

-0.5

-0.5

-0.5

4.0

2.2

4.0

3.0

2.2

4.0

4.0

V

V

V

V

V

V

V

Analog supply for:

Internal Spread Spectrum Clock Generator

I/O voltage for:

RGMII/GMII/MII/MMII/SMI interface

I/O voltage for:

SDRAM interface

I/O voltage for:

MPP, TWSI, JTAG, SDIO, I

2

S, SPI, TS, and

TDM interfaces

NOTE: The I

2

S, TS, and TDM interfaces are only relevant for the 88F6192.

I/O voltage for eFuse burning

Analog supply for:

PCI Express interface

Analog supply for:

USB interface

Analog supply for:

SATA interface

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Table 41: Absolute Maximum Ratings (Continued)

P a r a m e t e r

XTAL_AVDD

M i n

-0.5

M a x

2.2

U n i ts

V

RTC_AVDD

T

C

T

STG

-0.5

-40

-40

2.2

125

125

V

° C

° C

C o m m e n ts

Analog supply for internal clock inverter for crystal support and current source for SATA and

USB PHYs

Analog supply for:

RTC interface

Case temperature

Storage temperature

Caution

„

„

Exposure to conditions at or beyond the maximum rating may damage the device.

Operation beyond the recommended operating conditions (

Table 42 ) is neither

recommended nor guaranteed.

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Electrical Specifications (Preliminary)

Recommended Operating Conditions

10.2

Recommended Operating Conditions

Table 42: Recommended Operating Conditions

P a r a m e t e r

VDD

CPU_PLL_AVDD

CORE_PLL_AVDD

SSCG_AVDD

M i n

0.95

1.7

1.7

Ty p

1.0

1.8

1.8

M a x

1.05

1.9

1.9

Units C o m m e n ts

V

V

Core and CPU voltage

Analog supply for the internal PLL

V

88F6190

VDD_GE_A

88F6192 –

VDD_GE_A

VDD_GE_B

88F6190 – VDD_GE_B

VDD_M

VDDO

3.15

1.7

3.15

1.7

3.15

3.3

1.8

3.3

1.8

3.3

3.45

1.9

3.45

1.9

3.45

V

V

V

V

V

Analog supply for:

Internal Spread Spectrum Clock

Generator

I/O voltage for:

RGMII(10/100 RGMII only)/

GMII/MII/MMII/SMI interfaces

I/O voltage for:

RGMII/SMI interfaces

I/O voltage for:

GMII/MII/MMII/SMI interfaces

I/O voltage for:

SDRAM interface

I/O voltage for:

MPP, TWSI, JTAG, SDIO, I

2

S, SPI,

TS, and TDM interfaces

NOTE: The I

2

S, TS, and TDM interfaces are only relevant for the 88F6192.

VHV (during eFuse

Burning mode)

VHV (during eFuse

Reading mode)

PEX_AVDD

USB_AVDD

2.375

0.95

1.7

3.15

2.5

1.0

1.8

3.3

2.625

1.05

1.9

3.45

V

V

V

V

I/O voltage for eFuse burning

NOTE: If the VHV voltage is higher than VDD voltage (burning mode), VDD must be powered before VHV, to prevent the fuse from being accidentally burned.

I/O voltage for eFuse reading

NOTE: It is recommended that if only a read operation is required, VHV would be connected to the device

VDD power.

Analog supply for:

PCI Express interface

Analog supply for:

USB interface

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Table 42: Recommended Operating Conditions (Continued)

P a r a m e t e r

88F6190

SATA_AVDD

88F6192 –

SATA0_AVDD

SATA1_AVDD

XTAL_AVDD

M i n

3.15

1.7

Ty p

3.3

1.8

M a x

3.45

1.9

Units C o m m e n ts

V Analog supply for:

SATA interface

V

RTC_AVDD

TJ

1.7

1.3

0

1.8

1.5

1.9

1.7

105

V

V

° C

Analog supply for:

Internal clock inverter for crystal support and current source for

SATA and USB PHYs

Analog supply for RTC in Regular mode

Analog supply for RTC in Battery

Back-up mode

Junction Temperature

Caution

Operation beyond the recommended operating conditions is neither recommended nor guaranteed.

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December 2, 2008, Preliminary

Electrical Specifications (Preliminary)

Thermal Power Dissipation

10.3

Thermal Power Dissipation

Note

Before designing a system, Marvell recommends reading application note AN-63:

Thermal Management for Marvell Technology Products. This application note presents basic concepts of thermal management for integrated circuits (ICs) and includes guidelines to ensure optimal operating conditions for Marvell Technology's products.

The purpose of the Thermal Power Dissipation table is to support system engineering in thermal

design.

.

Table 43: Thermal Power Dissipation

I n t e r f a c e

Core (including CPU)—VDD 1.0V

For the 88F6190:

S y m b o l

P

VDD

Te s t C o n d i t i o n s Ty p

930

U n i ts

mW

For the 88F6192:

CPU @ 600 MHz,

L2 @ 300 MHz,

Core @ 166 MHz

CPU @ 800 MHz,

L2 @ 400 MHz,

Core @ 166 MHz

1000 mW

RGMII 1.8V interface P

RGMII

RGMII (10/100 RGMII only) 3.3V interface P

RGMII

GMII 3.3V interface

MII/MMII 3.3V interface

P

GMII

P

MII

P

MISC

Miscellaneous interfaces

(JTAG, TWSI, UART, NAND flash, Audio,

SDIO, TDM, TS, and SPI)

NOTE: The Audio, TDM, and TS interfaces only apply to the

88F6192.

P

DDR2

DDR2 SDRAM interface (On Board,

16-bit, 200 MHz) eFuse during Burning mode

NOTE: Since the eFuse burn is performed only once, there is no thermal effect after the burn has finished.

P

FUSE eFuse during Reading mode

PCI Express interface

USB interface

SATA interface

P

FUSE

P

PEX

P

USB

P

SATA

Two on board devices, 75 ohm

ODT termination

88F6190 – A single SATA port

88F6192

Two SATA ports

180

50

25

100

120

205

410

30

50

50

10

50 mW mW mW mW mW mW mW mW mW mW mW mW

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Hardware Specifications

Notes:

1.

The values are for nominal voltage.

2.

Power in mW is calculated using the typical recommended VDDIO specification for each power rail.

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December 2, 2008, Preliminary

Electrical Specifications (Preliminary)

Current Consumption

10.4

Current Consumption

The purpose of the Current Consumption table is to support board power design and power module

selection.

.

Table 44: Current Consumption

I n t e r f a c e

Core (including CPU)—VDD 1.0V

For the 88F6190:

S y m b o l

I

VDD

Te s t C o n d i t i o n s M a x

1930

U n i ts

mA

For the 88F6192:

CPU @ 600 MHz,

L2 @ [email protected] MHz,

Core @ 166 MHz

CPU @ 800 MHz,

L2 @ [email protected] MHz,

Core @ 166 MHz

2000 mA

RGMII 1.8V or 3.3V interface

GMII 3.3V interface

MII/MMII 3.3V interface

Miscellaneous interfaces

(JTAG, TWSI, UART, NAND flash, Audio,

SDIO, TDM, TS, and SPI)

NOTE: The Audio, TDM, TS interfaces only apply to the 88F6192.

DDR2 SDRAM interface (On Board 16-bit

200 MHz) eFuse during Burning mode eFuse during Reading mode

PCI Express interface

USB interface

SATA interface

I

RGMII

I

GMII

I

MII_MMII

I

MISC

I

DDR2

I

FUSE

I

FUSE

I

PEX

I

USB

I

SATA

Two on board devices, 75 ohm

ODT termination

88F6190 – A single SATA port

88F6192

Two SATA ports

450

20

25

50

40

65

130

25

25

25

25 mA mA mA mA mA mA mA mA mA mA mA

Notes:

1.

Current in mA is calculated using maximum recommended VDDIO specification for each power rail.

2.

All output clocks toggling at their specified rate.

3.

Maximum drawn current from the power supply.

Copyright © 2008 Marvell

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Page 91

10.5

10.5.1

88F619x

Hardware Specifications

DC Electrical Specifications

Note

See Section 2.3, Internal Pull-up and Pull-down Pins, on page 55 for internal

pullup/pulldown information.

General 3.3V (CMOS) DC Electrical Specifications

The S/PDIF / I2S and Transport Stream interfaces are only relevant for the 88F6192.

Note

„

„

The DC electrical specifications in Table 45 are applicable for the following interfaces and signals:

JTAG

RGMII (10/100 Mbps)/GMII/MII/MMII

„

„

Secure Digital Input/Output (SDIO)

S/PDIF / I

2

S (Audio)

Transport Stream (TS)

„

„

„

„

NAND flash

UART

„

„

MPP

PTP

SYSRSTn

In the following table, for the JTAG, SDIO, S/PDIF / I

2

S, TS, NAND flash, UART, PTP, and MPP interfaces, VDDIO means the VDDO power rail. For the 88F6190 RGMII interface VDDIO means the

VDD_GE_A power rail, and for the GMII/MII/MMII interface, VDDIO means the VDD_GE_A and

VDD_GE_B power rails. For the 88F6192 RGMII/GMII/MII/MMII interface, VDDIO means the

VDD_GE_A and VDD_GE_B power rails.

Table 45: General 3.3V Interface (CMOS) DC Electrical Specifications

Param eter

Input low level

Input high level

Output low level

Output high level

Input leakage current

Pin capacitance

Sym bol Test Condition

VIL

VIH

VOL IOL = 2 mA

VOH IOH = -2 mA

IIL

Cpin

0 < VIN < VDDIO

Min

-0.3

2.0

-

2.4

-10

Typ

5

Max

0.8

VDDIO+0.3

0.4

-

10

Units Notes

V -

V

V

V uA pF

-

-

-

1, 2

-

Notes:

General comment: See the Pin Description section for internal pullup/pulldow n.

1. While I/O is in High-Z.

2. This current does not include the current flow ing through the pullup/pulldow n resistor.

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December 2, 2008, Preliminary

Electrical Specifications

DC Electrical Specifications

10.5.2

RGMII, SMI and REF_CLK_XIN 1.8V (CMOS) DC Electrical

Specifications

In the following table, for the RGMII interface, VDDIO means the VDD_GE_A power rail or

VDD_GE_B power rail (88F6192 only).

In the following table, for the REF_CLK_XIN pin, VDDIO means the XTAL_AVDD power rail.

Table 46: RGMII 1.8V Interface (CMOS) DC Electrical Specifications

Param eter

Input low level

Input high level

Output low level

Output high level

Input leakage current

Pin capacitance

Sym bol Test Condition

VIL

VIH

VOL IOL = 2 mA

VOH

IIL

Cpin

IOH = -2 mA

0 < VIN < VDDIO

Min

-0.3

0.65*VDDIO

-

VDDIO-0.45

-10

Typ

5

Max

0.35*VDDIO

VDDIO+0.3

0.45

-

10

Units Notes

V -

V

V

-

-

V uA pF

-

1, 2

-

Notes:

General comment: See the Pin Description section for internal pullup/pulldow n.

1. While I/O is in High-Z.

2. This current does not include the current flow ing through the pullup/pulldow n resistor.

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Hardware Specifications

10.5.3

SDRAM DDR2 Interface DC Electrical Specifications

In the following table, VREF is VDD_M/2 and VDDIO means the VDD_M power rail.

Table 47: SDRAM DDR2 Interface DC Electrical Specifications

Input low level

Parameter

Input high level

Output low level

Output high level

Rtt effective impedance value

Symbol Test Condition

VIL -

VIH -

VOL IOL = 13.4 mA

VOH IOH = -13.4 mA

RTT See note 2

Deviation of VM w ith respect to VDDQ/2 dVm See note 3

Input leakage current

Pin capacitance

IIL

Cpin -

0 < VIN < VDDIO

Min

-0.3

VREF + 0.125

Typ Max Units Notes

VREF - 0.125

V -

1.42

120

60

40

-6

-10

150

75

50

5

VDDIO + 0.3

V

0.28

V

180

90

60

6

10 ohm 1 , 2

% uA pF

3

4, 5

-

-

-

V ohm 1 , 2 ohm 1 , 2

Notes:

General comment: See the Pin Description section for internal pullup/pulldow n.

1. See SDRAM functional description section for ODT configuration.

2. Measurement definition for RTT: Apply VREF +/- 0.25 to input pin separately,

then measure current I

(VREF + 0.25)

and I

(VREF - 0.25)

respectively.

RTT

=

I

(

VREF

+

0 .

25 )

0 .

5

I

(

VREF

0 .

25 )

3. Measurement definition for VM: Measured voltage (VM) at input pin (midpoint) w ith no load.

dVM

=

2

×

Vm

VDDIO

1

×

100 %

4. While I/O is in High-Z.

5. This current does not include the current flow ing through the pullup/pulldow n resistor.

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Electrical Specifications

DC Electrical Specifications

10.5.4

Two-Wire Serial Interface (TWSI) 3.3V DC Electrical

Specifications

In the following table, VDDIO means the VDDO power rail.

Table 48: TWSI Interface 3.3V DC Electrical Specifications

Param eter

Input low level

Input high level

Output low level

Input leakage current

Pin capacitance

Sym bol Test Condition

VIL

VIH

VOL

IIL

Cpin

IOL = 3 mA

0 < VIN < VDDIO

Min

-0.5

0.7*VDDIO

-

-10

Typ

5

Max

0.3*VDDIO

VDDIO+0.5

0.4

10

Units Notes

V -

V -

V uA pF

-

1, 2

-

Notes:

General comment: See the Pin Description section for internal pullup/pulldow n.

1. While I/O is in High-Z.

2. This current does not include the current flow ing through the pullup/pulldow n resistor.

10.5.5

Serial Peripheral Interface (SPI) 3.3V DC Electrical

Specifications

In the following table VDDIO means the VDDO power rail.

Table 49: SPI Interface 3.3V DC Electrical Specifications

Typ Param eter

Input low level

Input high level

Output low level

Output high level

Input leakage current

Pin capacitance

Sym bol Test Condition

VIL

VIH

VOL

VOH

IIL

Cpin

IOL = 4 mA

IOH = -4 mA

0 < VIN < VDDIO

Min

-0.5

0.7*VDDIO

-

VDDIO-0.6

-10

5

Max

0.3*VDDIO

VDDIO+0.5

0.4

-

10

Units Notes

V -

V -

V

V uA pF

-

-

1, 2

-

Notes:

General comment: See the Pin Description section for internal pullup/pulldow n.

1. While I/O is in High-Z.

2. This current does not include the current flow ing through the pullup/pulldow n resistor.

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10.5.6

88F619x

Hardware Specifications

Time Division Multiplexing (TDM) 3.3V DC Electrical

Specifications

The TDM interface is only relevant for the 88F6192.

Note

In the following table VDDIO means the either the VDDO or the VDD_GE_B power rail, depending on which MPP pins are configured for the TDM interface.

Table 50: TDM Interface 3.3V DC Electrical Specifications

Param eter

Input low level

Input high level

Output low level

Output high level

Input leakage current

Pin capacitance

Sym bol Test Condition

VIL

VIH

VOL IOL = 4 mA

VOH

IIL

Cpin

IOH = -4 mA

0 < VIN < VDDIO

Min

-0.5

0.7*VDDIO

-

VDDIO-0.6

-10

Typ

5

Max

0.3*VDDIO

VDDIO+0.5

0.4

-

10

Units Notes

V -

V

V

-

-

V uA pF

-

1, 2

-

Notes:

General comment: See the Pin Description section for internal pullup/pulldow n.

1. While I/O is in High-Z.

2. This current does not include the current flow ing through the pullup/pulldow n resistor.

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December 2, 2008, Preliminary

Electrical Specifications

AC Electrical Specifications

10.6

AC Electrical Specifications

See

Section 10.7, Differential Interface Electrical Characteristics, on page 127

for differential interface specifications.

10.6.1

Reference Clock AC Timing Specifications

Table 51: Reference Clock AC Timing Specifications

D e s c r i p t i o n

C P U a n d C o r e R e f e r e n c e C l o c k

S y m b o l

Frequency F

REF_CLK_XIN

M i n M a x

Clock duty cycle

Slew rate

Pk-Pk jitter

E t h e r n e t R e f e r e n c e C l o c k

DC

REF_CLK_XIN

SR

JR

REF_CLK_XIN

REF_CLK_XIN

50 ppm

40

0.7

50 ppm

60

200

Frequency in MII/MMII-MAC mode F

GE_TXCLK_OUT

F

GE_RXCLK

2.5 -

100 ppm

MII/MMII-MAC mode clock duty cycle DC

GE_TXCLK_OUT

35

DC

GE_RXCLK

Slew rate SR

GE_TXCLK_OUT

0.7

SR

GE_RXCLK

A u d i o E x t e r n a l R e f e r e n c e C l o c k ( O n l y r e l e v a n t f o r t h e 8 8 F 6 1 9 2 )

Audio external reference clock F

AU_EXTCLK

S / P D I F R e c o v e r e d M a s t e r C l o c k ( O n l y r e l e v a n t f o r t h e 8 8 F 6 1 9 2 )

50 +

100 ppm

65

256 X F s

256 X F s

S/PDIF recovered master clock F

AU_SPDFRMCLK

I

2

S R e f e r e n c e C l o c k ( O n l y r e l e v a n t f o r t h e 8 8 F 6 1 9 2 )

I

2

S clock F

I2S_BCLK

S P I O u t p u t C l o c k

SPI output clock

R T C R e f e r e n c e C l o c k

F

SPI_SCK

64 X F

TCLK/30 s

TCLK/4

Units

MHz

%

V/ns ps

MHz

%

V/ns

N o t e s

1

7

7

1, 7 kHz 3 kHz 3 kHz 3

MHz 2

RTC_XIN crystal frequency F

RTC_XIN

Tr a n s p o r t St r e a m ( T S ) O u t pu t M o d e R e f e r e n c e C l o c k ( O n l y r e l e v a n t f o r t h e 8 8 F 6 1 9 2 )

TS output clock in parallel mode

TS output clock in serial mode F

TS0_CLK,

F

TS1_CLK

9.61

83

Tr a n s p o r t St r e a m I n p u t M o d e R e f e r e n c e C l o c k ( O n l y r e l e v a n t f o r t h e 8 8 F 6 1 9 2 )

TS input clock in parallel mode F

TS0_CLK,

F

TS1_CLK

13.5

TS input clock in serial mode F

TS0_CLK,

F

TS1_CLK

83

Tr a n s p o r t St r e a m E x t e r n a l R e f e r e n c e C l o c k ( O n l y r e l e v a n t f o r t h e 8 8 F 6 1 9 2 )

TS external clock in parallel mode

TS external clock in serial mode

F

TS0_CLK,

F

TS1_CLK

F

EXT_CLK

F

EXT_CLK

9.61

9.61

9.61

12.5

12.5

83

MHz

MHz

MHz

MHz

MHz

MHz

5

5

5

5

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Hardware Specifications

Table 51: Reference Clock AC Timing Specifications (Continued)

D e s c r i p t i o n S y m b o l

T D M _ S P I O u t p u t C l o c k ( O n l y r e l e v a n t f o r t h e 8 8 F 6 1 9 2 )

M i n M a x

F

TDM_SPI_SCK

8.192

TDM_SPI output clock

S M I M a s t e r M o d e R e f e r e n c e C l o c k

SMI output MDC clock

T W S I M a s t e r M o d e R e f e r e n c e C l o c k

SCK output clock

F

F

GE_MDC

TW_SCK

TCLK/128

TCLK/

1600

P T P R e f e r e n c e C l o c k

Frequency

Clock duty cycle

Slew rate

Pk-Pk jitter

F

PTP_CLK

DC

PTP_CLK

SR

PTP_CLK

JR

PTP_CLK

100 ppm

40

125 -

0.7

125 +

100 ppm

60

100

Units N o t e s

MHz

MHz kHz

MHz

%

V/ns ps

6

1

Notes:

1.

Slew rate is defined from 20% to 80% of the reference clock signal.

2.

For additional information regarding configuring this clock, see the Serial Memory Interface

Control Register in the

88F6180, 88F6190, 88F6192, and 88F6281

Functional Specifications.

3.

F s

is the audio sample rate, which can be configured to 44.1 kHz, 48 kHz, or 96 kHz (see the

Audio (I

2

S / S/PDIF) Interface section in the

88F6180, 88F6190, 88F6192, and 88F6281

Functional Specifications).

4.

The RTC design was optimized for a standard CL = 12.5 pF crystal. No passive components are provided internally. Connect the crystal and the passive network as recommended by the crystal manufacturer.

5.

The frequency can be set using the TS Interface Configuration register (see the

88F6180,

88F6190, 88F6192, and 88F6281

Functional Specifications).

6.

For the minimum value refer to the Baud Rate Register section of the

88F6180, 88F6190,

88F6192, and 88F6281

Functional Specifications.

7.

The Ethernet Reference Clock parameters refer both to the reference clock for an Ethernet port configured using the dedicated port pins and for an Ethernet port configured using the multiplexed port pins.

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Electrical Specifications

AC Electrical Specifications

10.6.2

SDRAM DDR2 Interface AC Timing

10.6.2.1

SDRAM DDR2 Interface AC Timing Table

Table 52: SDRAM DDR2 Interface AC Timing Table

Description

Clock frequency

DQ and DM valid output time before DQS transition

DQ and DM valid output time after DQS transition

DQ and DM output pulse w idth

DQS output high pulse w idth

DQS output low pulse w idth

DQS falling edge to CLK-CLKn rising edge

DQS falling edge from CLK-CLKn rising edge

CLK-CLKn rising edge to DQS output rising edge

DQS w rite preamble

DQS w rite postamble

CLK-CLKn high-level w idth

CLK-CLKn low -level w idth

DQ input setup time relative to DQS in transition

DQ input hold time relative to DQS in transition

Address and Control valid output time before CLK-CLkn rising edge

Address and Control valid output time after CLK-CLKn rising edge

Address and control output pulse w idth

Sym bol

fCK tDOVB tDOVA tDIPW tDQSH tDQSL tDSS tDSH tDQSS tWPRE tWPST tCH tCL tDSI tDHI tAOVB tAOVA tIPW

0.37

0.34

0.34

-0.11

0.35

0.42

0.45

0.45

-0.55

1.50

1.70

1.70

0.67

200 MHz @ 1.8V

Min

200.00

Max

0.50

0.50

0.37

0.37

-

-

-

-

-

-

-

0.11

-

-

0.55

0.55

-

-

-

-

-

1

1

-

-

-

1

-

-

1

-

1, 2

1, 2

-

Notes

-

-

-

-

tCK tCK tCK tCK ns tCK tCK tCK tCK ns ns ns tCK

Units

MHz ns ns tCK tCK

Notes:

General comment: All timing values w ere measured from vref to vref, unless otherw ise specified.

General comment: All input timing values assume minimum slew rate of 1 V/ns (slew rate measured from Vref +/-125 mV).

General comment: tCK = 1/fCK.

General comment: For all signals, the load is CL = 8 pF.

1. This timing value is defined on CLK / CLKn crossing point.

2. This timing value is defined w hen Address and Control signals are output w ith CLK-CLKn falling edge.

For more information, see register settings.

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88F619x

Hardware Specifications

SDRAM DDR2 Interface Test Circuit

Figure 8: SDRAM DDR2 Interface Test Circuit

Test Point

VTT

50 ohm

CL

10.6.2.3

SDRAM DDR2 Interface AC Timing Diagrams

Figure 9: SDRAM DDR2 Interface Write AC Timing Diagram

tDSH tDSS

CLK

CLKn

DQS tCH

DQSn tCL tWPRE tDQSH tDQSL tWPST tDIPW

DQ tDOVB tDOVA

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AC Electrical Specifications

Figure 10: SDRAM DDR2 Interface Address and Control AC Timing Diagram

CLK

CLKn tCH tCL

ADDRESS/

CONTROL tIPW tAOVB tAOVA

Figure 11: SDRAM DDR2 Interface Read AC Timing Diagram

DQS

DQSn

DQ tDSI tDHI

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10.6.3

10.6.3.1

88F619x

Hardware Specifications

Reduced Gigabit Media Independent Interface (RGMII)

AC Timing

RGMII AC Timing Table

Table 53: RGMII 10/100/1000 AC Timing Table at 1.8V

Description

Clock frequency

Data to Clock output skew

Data to Clock input skew

Clock cycle duration

Duty cycle for Gigabit

Duty cycle for 10/100 Megabit

Sym bol Min

fCK 125.0

Max Units Notes

MHz -

Tskew T -0.50

0.50

ns 2

Tskew R 1.00

Tcyc 7.20

Duty_G 0.45

Duty_T 0.40

2.60

8.80

0.55

0.60

ns ns tCK tCK

-

1 , 2

2

2

Notes:

General comment: All values w ere measured from vddio/2 to vddio/2, unless otherw ise specified.

General comment: tCK = 1/fCK.

General comment: If the PHY does not support internal-delay mode, the PC board design requires

routing clocks so that an additional trace delay of greater than 1.5 ns and less

than 2.0 ns is added to the associated clock signal.

For 10/100 Mbps RGMII, the Max value is unspecified.

1. For RGMII at 10 Mbps and 100 Mbps, Tcyc w ill scale to 400 ns +/-40 ns and 40 ns +/-4 ns, respectively.

2. For all signals, the load is CL = 5 pF.

Table 54: RGMII 10/100 AC Timing Table at 3.3V

Description

Clock frequency

Data to Clock output skew

Data to Clock input skew

Clock cycle duration

Duty cycle for Gigabit

Duty cycle for 10/100 Megabit

Sym bol Min

fCK 25.0

Max Units Notes

MHz -

Tskew T -0.50

Tskew R 1.00

0.50

2.60

ns ns

2

-

Tcyc 7.20

Duty_G 0.45

Duty_T 0.40

8.80

0.55

0.60

ns tCK tCK

1 , 2

2

2

Notes:

General comment: All values w ere measured from vddio/2 to vddio/2, unless otherw ise specified.

General comment: tCK = 1/fCK.

General comment: If the PHY does not support internal-delay mode, the PC board design requires

routing clocks so that an additional trace delay of greater than 1.5 ns

is added to the associated clock signal.

For 10/100 Mbps RGMII, the Max value is unspecified.

1. For RGMII at 10 Mbps and 100 Mbps, Tcyc w ill scale to 400 ns +/-40 ns and 40 ns +/-4 ns, respectively.

2. For all signals, the load is CL = 5 pF.

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10.6.3.2

RGMII Test Circuit

Figure 12: RGMII Test Circuit

Test Point

CL

Electrical Specifications

AC Electrical Specifications

10.6.3.3

RGMII AC Timing Diagram

Figure 13:

RGMII AC Timing Diagram

TX

CLOCK

(At Transmitter)

TX

DATA

RX

CLOCK

(At Receiver)

RX

DATA

TskewT

TskewR

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10.6.4

Gigabit Media Independent Interface (GMII) AC Timing

10.6.4.1

GMII AC Timing Table

Table 55: GMII AC Timing Table

Description

GTX_CLK cycle time

RX_CLK cycle time

GTX_CLK and RX_CLK high level w idth

GTX_CLK and RX_CLK low level w idth

GTX_CLK and RX_CLK rise time

GTX_CLK and RX_CLK fall time

Data input setup time relative to RX_CLK rising edge

Data input hold time relative to RX_CLK rising edge

Data output valid before GTX_CLK rising edge

Data output valid after GTX_CLK rising edge

Sym bol

tCK tCKrx tHIGH tLOW tR tF tSETUP tHOLD tOVB tOVA

-

-

2.0

0.0

2.5

0.5

125 MHz

Min

7.5

7.5

2.5

2.5

Max

8.5

-

-

-

-

-

-

1.0

1.0

ns ns ns ns ns ns

Units

ns ns ns ns

-

1

1

1, 2

1, 2

-

Notes

-

-

1

1

Notes:

General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified.

1. For all signals, the load is CL = 5 pF.

2. Rise time measured from VIL(max) to VIH(min), fall time measured from VIH(min) to VIL(max).

10.6.4.2

GMII Test Circuit

Figure 14: GMII Test Circuit

Test Point

CL

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Electrical Specifications

AC Electrical Specifications

10.6.4.3

GMII AC Timing Diagrams

Figure 15: GMII Output AC Timing Diagram

tLOW tHIGH

GTX_CLK

TXD, TX_EN, TX_ER tOVB tOVA

Figure 16: GMII Input AC Timing Diagram

tLOW tHIGH

RX_CLK

RXD, RX_EN, RX_ER tSETUP tHOLD

VIH(min)

VIL(max)

VIH(min)

VIL(max)

VIH(min)

VIL(max)

VIH(min)

VIL(max)

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Hardware Specifications

10.6.5

Media Independent Interface/Marvell Media Independent

Interface (MII/MMII) AC Timing

10.6.5.1

MII/MMII MAC Mode AC Timing Table

Table 56: MII/MMII MAC Mode AC Timing Table

Description

Data input setup relative to RX_CLK rising edge

Data input hold relative to RX_CLK rising edge

Data output delay relative to MII_TX_CLK rising edge

Sym bol

tSU tHD tOV

Min

3.5

2.0

0.0

Max

-

-

10.0

Units

ns ns ns

Notes

-

-

1

Notes:

General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified.

1. For all signals, the load is CL = 5 pF.

10.6.5.2

MII/MMII MAC Mode Test Circuit

Figure 17: MII/MMII MAC Mode Test Circuit

Test Point

CL

10.6.5.3

MII/MMII MAC Mode AC Timing Diagrams

Figure 18: MII/MMII MAC Mode Output Delay AC Timing Diagram

MII_TX_CLK

TXD, TX_EN, TX_ER

Vih(min)

Vil(max)

Vih(min)

Vil(max)

TOV

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December 2, 2008, Preliminary

Figure 19: MII/MMII MAC Mode Input AC Timing Diagram

Electrical Specifications

AC Electrical Specifications

RX_CLK

RXD, RX_EN, RX_ER

Vih(min)

Vih(min)

Vil(max) tSU tHD

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Hardware Specifications

10.6.6

Serial Management Interface (SMI) AC Timing

10.6.6.1

SMI Master Mode AC Timing Table

Table 57: SMI Master Mode AC Timing Table

Description

MDC clock frequency

MDC clock duty cycle

MDIO input setup time relative to MDC rise time

MDIO input hold time relative to MDC rise time

MDIO output valid before MDC rise time

MDIO output valid after MDC rise time

Sym bol

fCK tDC tSU tHO tOVB tOVA

Min Max

See note 2

0.4

40.0

0.0

15.0

15.0

0.6

-

-

-

-

Units Notes

MHz tCK ns

2

-

ns ns ns

-

1

1

Notes:

General comment: All timing values w ere measured from VIL(max) and VIH(min) levels, unless otherw ise specified.

General comment: tCK = 1/fCK.

1. For MDC signal, the load is CL = 390 pF, and for MDIO signal, the load is CL = 470 pF.

2. See "Reference Clocks" table for more details.

10.6.6.2

SMI Master Mode Test Circuit

Figure 20: MDIO Master Mode Test Circuit

Test Point

VDDIO

2 kilohm

MDIO

CL

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AC Electrical Specifications

Figure 21: MDC Master Mode Test Circuit

Test Point

MDC

CL

10.6.6.3

SMI Master Mode AC Timing Diagrams

Figure 22: SMI Master Mode Output AC Timing Diagram

VIH(min)

MDC

MDIO tOVB tOVA

Figure 23: SMI Master Mode Input AC Timing Diagram

MDC

VIH(min)

VIL(max)

VIH(min)

MDIO

VIH(min)

VIL(max) tSU tHO

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10.6.7

JTAG Interface AC Timing

10.6.7.1

JTAG Interface AC Timing Table

Table 58: JTAG Interface AC Timing Table

Description

JTClk frequency

JTClk minimum pulse w idth

JTClk rise/fall slew rate

JTRSTn active time

TMS, TDI input setup relative to JTClk rising edge

TMS, TDI input hold relative to JTClk rising edge

JTClk falling edge to TDO output delay

Sym bol

fCK

Tpw

Sr/Sf

Trst

Tsetup

Thold

Tprop

Min

30 MHz

Max

30.0

0.45

0.55

0.50

1.0

6.67

13.0

1.0

-

-

-

-

8.33

Units

MHz tCK

V/ns ms ns ns ns

Notes

-

-

2

-

-

-

1

Notes:

General comment: All values w ere measured from vddio/2 to vddio/2, unless otherw ise specified.

General comment: tCK = 1/fCK.

1. For TDO signal, the load is CL = 10 pF.

2. Defined from VIL to VIH for rise time, and from VIH to VIL for fall time.

10.6.7.2

JTAG Interface Test Circuit

Figure 24: JTAG Interface Test Circuit

Test Point

CL

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10.6.7.3

Electrical Specifications

AC Electrical Specifications

JTAG Interface AC Timing Diagrams

Figure 25: JTAG Interface Output Delay AC Timing Diagram

Tprop

(max)

JTCK

VIH

VIL

TDO

Tprop

(min)

Figure 26: JTAG Interface Input AC Timing Diagram

JTCK

TMS,TDI

Tsetup

Thold

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10.6.8

Two-Wire Serial Interface (TWSI) AC Timing

10.6.8.1

TWSI AC Timing Table

Table 59: TWSI Master AC Timing Table

Description

SCK clock frequency

SCK minimum low level w idth

SCK minimum high level w idth

SDA input setup time relative to SCK rising edge

SDA input hold time relative to SCK falling edge

SDA and SCK rise time

SDA and SCK fall time

SDA output delay relative to SCK falling edge

Sym bol

fCK tLOW tHIGH tSU tHD tr tf tOV

Min Max

See note 1

0.47

-

0.40

250.0

0.0

-

-

0.0

-

-

-

1000.0

300.0

0.4

Units Notes

kHz 1 tCK 2 tCK ns ns ns ns tCK

2

-

-

2, 3

2, 3

2

Notes:

General comment: All values referred to VIH(min) and VIL(max) levels, unless otherw ise specified.

General comment: tCK = 1/fCK.

1. See "Reference Clocks" table for more details.

2. For all signals, the load is CL = 100 pF, and RL value can be 500 ohm to 8 kilohm.

3. Rise time measured from VIL(max) to VIH(min), fall time measured from VIH(min) to VIL(max).

Table 60: TWSI Slave AC Timing Table

Description

SCK minimum low level w idth

SCK minimum high level w idth

SDA input setup time relative to SCK rising edge

SDA input hold time relative to SCK falling edge

SDA and SCK rise time

SDA and SCK fall time

SDA output delay relative to SCK falling edge

Sym bol

tLOW tHIGH tSU tHD tr tf tOV

100 kHz

Min

4.7

Max

-

4.0

250.0

0.0

-

-

-

-

-

0.0

1000.0

300.0

4.0

Units

us us ns ns ns ns us

Notes

1

1

-

-

1, 2

1, 2

1

Notes:

General comment: All values referred to VIH(min) and VIL(max) levels, unless otherw ise specified.

1. For all signals, the load is CL = 100 pF, and RL value can be 500 ohm to 8 kilohm.

2. Rise time measured from VIL(max) to VIH(min), fall time measured from VIH(min) to VIL(max).

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AC Electrical Specifications

10.6.8.2

TWSI Test Circuit

Figure 27:

TWSI Test Circuit

Test Point

VDDIO

RL

CL

10.6.8.3

TWSI AC Timing Diagrams

Figure 28: TWSI Output Delay AC Timing Diagram

tHIGH tLOW

SCK

SDA tOV(min) tOV(max)

Figure 29: TWSI Input AC Timing Diagram

tLOW tHIGH

SCK

SDA tSU tHD

Vih(min)

Vil(max)

Vih(min)

Vil(max)

Vih(min)

Vil(max)

Vih(min)

Vil(max)

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10.6.9

88F619x

Hardware Specifications

Sony/Philips Digital Interconnect Format (S/PDIF) AC

Timing

The S/PDIF interface is only relevant for the 88F6192.

Note

10.6.9.1

S/PDIF AC Timing Table

Table 61: S/PDIF AC Timing Table

Description

Output frequency accuracy

Input frequency accuracy

Output jitter - total peak-to-peak

Jitter transfer gain

Input jitter - total peak-to-peak

Sym bol

Ftxtol

Frxtol

Txjit

Txjitgain

Rxjit

Min

-50.0

-100.0

-

-

-

-

-

Max

50.0

100.0

0.05

3.0

10.0

0.25

0.2

Units

ppm ppm

UI dB

UI

UI

UI

Notes

1

-

1, 2

3

4

5

6

Notes:

General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified.

General comment: For more information, refer to the Digital Audio Interface - Part 3: Consumer Applications,

IEC 60958-3:2003(E), Chapter 7.3, January 2003.

1. For all signals, the load is CL = 10 pF.

2. Using inristic jitter filter.

3. Refer to Figure-8 in IEC 60958-3:2003(E), Chapter 7.3, January 2003.

4. Defined for up to 5 Hz.

5. Defined from 200 Hz to 400 kHz.

6. Defined for above 400 kHz.

Note

For additional information about working with a coax connection, see the 88F6180,

88F6190, 88F6192, and 88F6281 Design Guide.

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December 2, 2008, Preliminary

10.6.9.2

S/PDIF Test Circuit

Figure 30: S/PDIF Test Circuit

Test Point

CL

Electrical Specifications

AC Electrical Specifications

Copyright © 2008 Marvell

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Hardware Specifications

10.6.10

Inter-IC Sound Interface (I

2

S) AC Timing

The I

2

S interface is only relevant for the 88F6192.

Note

10.6.10.1

Inter-IC Sound (I

2

S) AC Timing Table

Table 62: Inter-IC Sound (I

2

S) AC Timing Table

Description

I2SBCLK clock frequency

I2SBCLK clock high/low level pulse w idth

I2SDI input setup time relative to I2SBCLK rise time

I2SDI input hold time relative to I2SBCLK rise time

I2SDO, I2SLRCLK output delay relative to I2SBCLK rise time

Sym bol

fCK tCH/tCL tSU tHO tOD

Min Max

See note 2

0.37

-

0.10

0.00

0.10

-

-

0.70

Units Notes

MHz 2 tCK 1 tCK ns tCK

-

-

1

Notes:

General comment: All timing values w ere measured from VIL(max) and VIH(min) levels, unless otherw ise specified.

General comment: tCK = 1/fCK.

1. For all signals, the load is CL = 15 pF.

2. See "Reference Clocks" table for more details.

10.6.10.2

Inter-IC Sound (I

2

S) Test Circuit

Figure 31: Inter-IC Sound (I

2

S) Test Circuit

Test Point

CL

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AC Electrical Specifications

10.6.10.3

Inter-IC Sound (I

2

S) AC Timing Diagrams

Figure 32: Inter-IC Sound (I

2

S) Output Delay AC Timing Diagram

tCL tCH

I2SBCLK

VIH(min)

VIL(max)

VIH(min)

VIL(max)

I2SDO,

I2SLRCLK tODmin tODmax

Figure 33: Inter-IC Sound (I

2

S) Input AC Timing Diagram

tCL tCH

I2SBCLK

I2SDI

VIH(min)

VIL(max)

VIH(min)

VIL(max) tSU tHO

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10.6.11

Time Division Multiplexing (TDM) Interface AC Timing

The TDM interface is only relevant for the 88F6192.

Note

10.6.11.1

TDM Interface AC Timing Table

Table 63: TDM Interface AC Timing Table

Description

PCLK cycle time

PCLK duty cycle

PCLK rise/fall time

DTX and FSYNC valid after PCLK rising edge

DRX and FSYNC setup time relative to PCLK falling edge

DRX and FSYNC hold time relative to PCLK falling edge

Sym bol

1/tC tDTY tR/tF tD tSU tHD

8.192 MHz

Min

0.256

0.4

Max

8.192

0.6

-

0.0

10.0

10.0

3.0

20.0

-

-

Units

MHz tC ns ns ns ns

Notes

1, 3

1

1, 2, 8

1, 4, 6

5, 7

5, 7

Notes:

General comment: All values w ere measured from vddio/2 to vddio/2, unless otherw ise specified.

1. For all signals, the load is CL = 20 pF.

2. Rise and Fall times are referenced to the 20% and 80% levels of the w aveform.

3. PCLK can be configured to 0.256, 0.512, 0.768, 1.024, 1.536, 2.048, 4.096, 8.192 MHz frequencies only.

4. This parameter is relevant to FSYNC signal in master-mode only.

5. This parameter is relevant to FSYNC signal in slave-mode only.

6. In negative-mode, the DTX signal is relative to PCLK falling edge.

7. In negative-mode, the DRX signal is relative to PCLK rising edge.

8. This parameter is relevant w hen the PCLK pin is output.

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AC Electrical Specifications

10.6.11.2

TDM Interface Test Circuit

Figure 34: TDM Interface Test Circuit

Test Point

CL

10.6.11.3

TDM Interface Timing Diagrams

Figure 35: TDM Interface Output Delay AC Timing Diagram

tC

PCLK

DTX tD tD

Figure 36: TDM Interface Input Delay AC Timing Diagram

tC

PCLK

DRX tSU tHD

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Hardware Specifications

10.6.12

Serial Peripheral Interface (SPI) AC Timing

10.6.12.1

SPI (Master Mode) AC Timing Table

Table 64: SPI (Master Mode) AC Timing Table

Description

SCLK clock frequency

SCLK high time

SCLK low time

SCLK slew rate

Data out valid relative to SCLK falling edge

CS active before SCLK rising edge

CS not active after SCLK rising edge

Data in setup time relative to SCLK rising edge

Data in hold time relative to SCLK rising edge

Sym bol

fCK tCH tCL tSR tDOV tCSB tCSA tSU tHD

SPI

Min Max

See Note 3

0.46

0.46

0.5

-2.5

8.0

8.0

0.2

5.0

-

-

-

-

-

-

2.5

-

Units

MHz tCK tCK

V/ns ns ns ns tCK ns

1

2

2

1

1

1

Notes

3

1

1

Notes:

General comment: All values w ere measured from 0.3*vddio to 0.7*vddio, unless otherw ise specified.

General comment: tCK = 1/fCK.

1. For all signals, the load is CL = 10 pF.

2. Defined from vddio/2 to vddio/2.

3. See "Reference Clocks" table for more details.

10.6.12.2

SPI (Master Mode) Test Circuit

Figure 37: SPI

(Master Mode)

Test Circuit

Test Point

CL

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AC Electrical Specifications

10.6.12.3

SPI (Master Mode) Timing Diagrams

Figure 38: SPI

(Master Mode)

Output AC Timing Diagram

tCH tCL

SCLK

Data

Out tDOVmin tDOVmax

CS tCSB

Figure 39: SPI

(Master Mode)

Input AC Timing Diagram

tCSA

SCLK

Data in tSU tHD

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10.6.13

Secure Digital Input/Output (SDIO) Interface AC Timing

10.6.13.1

Secure Digital Input/Output (SDIO) AC Timing Table

Table 65: SDIO Host in High Speed Mode AC Timing Table

Description

Clock frequency in Data Transfer Mode

Clock high/low level pulse w idth

Clock rise/fall time

CMD, DAT output valid before CLK rising edge

CMD, DAT output valid after CLK rising edge

CMD, DAT input setup relative to CLK rising edge

CMD, DAT input hold relative to CLK rising edge

Symbol

fCK

Min

0 tWL/tWH 0.35

tTLH/tTHL tDOVB

-

6.5

tDOVA tISU tIHD

2.5

7.0

0.0

Max

50

-

3.0

-

-

-

-

Units Notes

MHz tCK ns ns

1, 3

1, 3

2, 3 ns ns ns

2, 3

2

2

Notes:

General comment: tCK = 1/fCK.

1. Defined on VIL(max) and VIH(min) levels.

2. Defined on VDDIO/2 for Clock signal, and VIL(max) / VIH(min) for CMD & DAT signals.

3. For all signals, the load is CL = 10 pF.

10.6.13.2

Secure Digital Input/Output (SDIO) Test Circuit

Figure 40: Secure Digital Input/Output (SDIO) Test Circuit

Test Point

VDDIO

50 KOhm

CL

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AC Electrical Specifications

10.6.13.3

Secure Digital Input/Output (SDIO) AC Timing Diagrams

Figure 41: SDIO Host in High Speed Mode Output AC Timing Diagram

tWL tWH

CLK

DAT,

CMD

VIH(min)

VIL(max)

VIH(min)

VDDIO/2

VIL(max) tDOVB tDOVA

Figure 42: SDIO Host in High Speed Mode Input AC Timing Diagram

tWL tWH

CLK

DAT,

CMD

VIH(min)

VIL(max)

VIH(min)

VDDIO/2

VIL(max) tISU tIHD

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10.6.14

Transport Stream (TS) Interface AC Timing

The TS interface is only relevant for the 88F6192.

Note

10.6.14.1

Transport Stream Interface AC Timing Table

Table 66: Transport Stream Output Interface AC Timing Table

Description

Clock frequency

Clock minimum low level w idth

Clock minimum high level w idth

Data output valid after Clock rising edge

Sym bol

fCK tLOW tHIGH tOV

Min Max Units

See note 1 MHz

0.4

0.4

0.4

0.6

0.6

0.6

tCK tCK tCK

Notes

1

2

2

2, 3

Notes:

General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified.

General comment: tCK = 1/fCK.

1. See "Reference Clocks" table for more details.

2. For all signals, the load is CL = 5 pF.

3. When configured to falling edge, the tOV parameter is relative to Clock falling edge.

Table 67: Transport Stream Input Interface AC Timing Table

Description

Clock frequency

Clock minimum low level w idth

Clock minimum high level w idth

Data input setup time relative to Clock rising edge

Data input setup time relative to Clock rising edge

Sym bol

fCK tLOW tHIGH tSU tHD

Min Max Units

See note 1 MHz

0.35

0.35

0.65

0.65

tCK tCK

0.30

0.30

-

tCK tCK

Notes

1

-

-

2

2

Notes:

General comment: All values w ere measured from VIL(max) to VIH(min), unless otherw ise specified.

General comment: tCK = 1/fCK.

1. See "Reference Clocks" table for more details.

2. When configured to falling edge, the tSU/tHD parameters are relative to Clock falling edge.

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AC Electrical Specifications

10.6.14.2

Transport Stream Interface Test Circuit

Figure 43:

Transport Stream

Interface Test Circuit

Test Point

CL

10.6.14.3

Transport Stream Interface Timing Diagrams

Figure 44:

Transport Stream

Output Interface AC Timing Diagram

tHIGH tLOW

Clock

Data Out

Vih(min)

Vil(max)

Vih(min)

Vil(max) tOV(min) tOV(max)

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Hardware Specifications

Figure 45:

Transport Stream

Input Interface AC Timing Diagram

tLOW tHIGH

Clock

Data In

Vih(min)

Vil(max)

Vih(min)

Vil(max) tSU tHD

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Electrical Specifications

Differential Interface Electrical Characteristics

10.7

Differential Interface Electrical Characteristics

„

„

This section provides the reference clock, AC, and DC characteristics for the following differential interfaces:

PCI Express Interface Electrical Characteristics

„

SATA Interface Electrical Characteristics

USB Electrical Characteristics

10.7.1

Differential Interface Reference Clock Characteristics

10.7.1.1

PCI Express Interface Differential Reference Clock Characteristics

Table 68: PCI Express Interface Differential Reference Clock Characteristics

Description

Clock frequency

Clock duty cycle

Differential rising/falling slew rate

Differential high voltage

Differential low voltage

Absolute crossing point voltage

Variation of Vcross over all rising clock edges

Sym bol

fCK

DCrefclk

SRrefclk

VIHrefclk

VILrefclk

Vcross

Vcrs_dlta

Min

0.4

0.6

150.0

-

100.0

Max

0.6

4.0

-

-150.0

Average differential clock period accuracy

Absolute differential clock period

Differential clock cycle-to-cycle jitter

Tperavg

Tperabs

Tccjit

250.0

-

-300.0

9.8

-

Notes:

General Comment: The reference clock timings are based on 100 ohm test circuit.

General Comment: Refer to the PCI Express Card Electromechanical Specification, Revision 1.1,

550.0

140.0

2800.0

10.2

150.0

March 2005, section 2.1.3 for more information.

1. Defined on a single-ended signal.

2. Including jitter and spread spectrum.

3. Defined from -150 mV to +150 mV on the differential w aveform.

Units Notes

MHz tCK

V/nS

-

3 mV mV mV mV

1

1

-

ppm nS pS

-

2

-

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Hardware Specifications

PCI Express Interface Spread Spectrum Requirements

Table 69: PCI Express Interface Spread Spectrum Requirements

Fmod

Fspread

Sym bol Min

0.0

-0.5

Max

33.0

0.0

Units Notes

kHz 1

% 1

Notes:

1. Defined on linear sw eep or “Hershey’s Kiss” (US Patent 5,631,920) modulations.

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Electrical Specifications

Differential Interface Electrical Characteristics

10.7.2

PCI Express Interface Electrical Characteristics

10.7.2.1

PCI Express Interface Driver and Receiver Characteristics

Table 70: PCI Express Interface Driver and Receiver Characteristics

Description

Baud rate

Unit interval

Baud rate tolerance

Differential peak to peak output voltage

Minimum TX eye w idth

Differential return loss

Common mode return loss

DC differential TX impedance

Differential input peak to peak voltage

Minimum receiver eye w idth

Differential return loss

Common mode return loss

DC differential RX impedance

DC common input impedance

Sym bol

BR

UI

Bppm

Driver parameters

VTXpp

TTXeye

TRLdiff

TRLcm

ZTXdiff

Receiver parameters

VRXpp

TRXeye

RRLdiff

RRLcm

ZRXdiff

ZRXcm

Min Max

2.5

-300.0

400.0

300.0

0.175

0.4

10.0

6.0

80.0

40.0

0.8

0.75

10.0

6.0

80.0

-

-

1.2

-

120.0

60.0

1.2

-

-

-

120.0

Units

Gbps ps ppm

V

UI dB dB

Ohm

Ohm

V

UI dB dB

Ohm

-

-

1

1

-

Notes

-

-

2

1

1

-

-

-

-

Notes:

General Comment: For more information, refer to the PCI Express Base Specification, Revision 1.1, March, 2005.

1. Defined from 50 MHz to 1.25 GHz.

2. Does not account for SSC dictated variations.

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10.7.2.2

88F619x

Hardware Specifications

PCI Express Interface Test Circuit

Figure 46: PCI Express Interface Test Circuit

Test Points

+

D+

C_TX

D-

C_TX

50 ohm 50 ohm

When measuring Transmitter output parameters, C_TX is an optional portion of the

Test/Measurement load. When used, the value of C_TX must be in the range of 75 nF to 200 nF.

C_TX must not be used when the Test/Measurement load is placed in the Receiver package reference plane.

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December 2, 2008, Preliminary

10.7.3

Electrical Specifications

Differential Interface Electrical Characteristics

SATA Interface Electrical Characteristics

The driver and receiver characteristics for the SATA-I Interface Gen1i Mode and the SATA-II

Interface Gen2i Mode are provided in the following sections.

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Hardware Specifications

10.7.3.1

SATA-I Interface Gen1i Mode Driver and Receiver Characteristics

Table 71: SATA-I Interface Gen1i Mode Driver and Receiver Characteristics

Description

Baud Rate

Baud rate tolerance

Spread spectrum modulation frequency

Spread spectrum modulation Deviation

Unit Interval

Sym bol

BR

Bppm

Fssc

Min

-350.0

30.0

1.5

Max

350.0

33.0

SSCtol -5000.0

UI 666.67

0.0

Differential impedance

Single ended impedance

Differential return loss (75 MHz-150 MHz)

Differential return loss (150 MHz-300 MHz)

Differential return loss (300 MHz-1.2 GHz)

Differential return loss (1.2 GHz-2.4 GHz)

Differential return loss (2.4 GHz-3.0 GHz)

Output differential voltage

Total jitter at connector data-data, 5UI

Deterministic jitter at connector data-data, 5UI

Total jitter at connector data-data, 250UI

Deterministic jitter at connector data-data, 250UI

Driver Parameters

Zdifftx

Zsetx

RLOD

RLOD

RLOD

RLOD

RLOD

Vdifftx

TJ5

DJ5

TJ250

DJ250

85.0

40.0

14.0

8.0

6.0

3.0

1.0

400.0

-

-

-

-

115.0

-

-

-

-

-

-

600.0

0.355

0.175

0.470

0.220

Differential impedance

Single ended impedance

Differential return loss (75 MHz-150 MHz)

Differential return loss (150 MHz-300 MHz)

Differential return loss (300 MHz-600 MHz)

Differential return loss (600 MHz-1.2 GHz)

Differential return loss (1.2 GHz-2.4 GHz)

Differential return loss (2.4 GHz-3.0 GHz)

Input differential voltage

Total jitter at connector data-data, 5UI

Deterministic jitter at connector data-data, 5UI

Total jitter at connector data-data, 250UI

Deterministic jitter at connector data-data, 250UI

Receiver Parameters

Zdiffrx

Zsetx

RLID

RLID

RLID

RLID

RLID

RLID

Vdiffrx

TJ5

DJ5

TJ250

DJ250

85.0

40.0

18.0

14.0

10.0

8.0

3.0

1.0

325.0

-

-

-

-

115.0

-

-

-

600.0

0.430

0.250

-

-

-

-

0.600

0.350

Notes:

General Comment: For more information, refer to SATA II Revision 2.6 Specification, February, 2007.

General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified.

General Comment: To comply w ith the values presented in this table, refer to your local

Marvell representative for register settings.

1. Total jitter is defined as TJ = (14 * RJ

σ) + DJ w here Rjσ is random jitter.

2. Output Differential Amplitude and Pre-Emphasis are configurabile. See functional register description

for more details.

Ohm

Ohm dB dB mV

UI

UI dB dB dB dB

UI

UI

Units

Gbps ppm kHz ppm ps

Ohm

Ohm dB dB dB dB dB mV

UI

UI

UI

UI

Notes

-

-

-

-

-

-

2

-

-

1

-

-

-

-

-

1

-

1

-

-

-

1

-

-

-

-

-

-

-

-

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December 2, 2008, Preliminary

Electrical Specifications

Differential Interface Electrical Characteristics

10.7.3.2

SATA-II Interface Gen2i Mode Driver and Receiver Characteristics

Table 72: SATA-II Interface Gen2i Mode Driver and Receiver Characteristics

Baud Rate

Baud rate tolerance

Description

Spread spectrum modulation frequency

Spread spectrum modulation Deviation

Unit Interval

Output differential voltage

Differential return loss (150 MHz-300 MHz)

Differential return loss (300 MHz-600 MHz)

Differential return loss (600 MHz-2.4 GHz)

Differential return loss (2.4 GHz-3.0 GHz)

Differential return loss (3.0 GHz-5.0 GHz)

Total jitter at connector clock-data

Deterministic jitter at connector clock-data

Total jitter at connector clock-data

Deterministic jitter at connector clock-data

Sym bol

BR

Bppm

Min

-350.0

3.0

Max

350.0

Fssc 30.0

SSCtol -5000.0

UI 333.33

33.0

0.0

Driver Parameters

Vdifftx

RLOD

RLOD

RLOD

RLOD

RLOD

TJ10

DJ10

TJ500

DJ500

400.0

14.0

8.0

6.0

3.0

1.0

-

-

-

-

700.0

-

0.30

0.17

0.37

0.19

-

-

-

-

Input differential voltage

Differential return loss (150 MHz-300 MHz)

Differential return loss (300 MHz-600 MHz)

Differential return loss (600 MHz-1.2 GHz)

Differential return loss (1.2 GHz-2.4 GHz)

Differential return loss (2.4 GHz-3.0 GHz)

Differential return loss (3.0 GHz-5.0 GHz)

Total jitter at connector clock-data

Deterministic jitter at connector clock-data

Total jitter at connector clock-data

Deterministic jitter at connector clock-data

Receiver Parameters

Vdiffrx

RLID

RLID

RLID

RLID

RLID

RLID

TJ10

DJ10

TJ500

DJ500

275.0

18.0

14.0

10.0

8.0

3.0

1.0

-

-

-

-

750.0

-

-

-

-

-

-

0.46

0.35

0.60

0.42

Notes:

General Comment: For more information, refer to SATA II Revision 2.6 Specification, February, 2007.

General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified.

General Comment: To comply w ith the values presented in this table, refer to your local

Marvell representative for register settings.

1. 0.45-0.55 UI is the range w here the signal meets the minimum level.

2. Output Differential Amplitude and Pre-Emphasis are configurabile. See functional register description

for more details.

3. Defined for BR/10.

4. Defined for BR/500.

5. 0.5 UI is the point w here the signal meets the minimum level.

mV dB dB dB dB dB dB

UI

UI

UI

UI mV dB

UI

UI

UI

UI dB dB dB dB

Units

Gbps ppm kHz ppm ps

1 , 2

-

4

4

3

3

-

-

-

-

Notes

-

-

-

-

-

-

-

-

-

-

5

-

4

4

3

3

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Hardware Specifications

10.7.4

USB Electrical Characteristics

10.7.4.1

USB

Driver and Receiver Characteristics

Table 73: USB Low Speed Driver and Receiver Characteristics

Baud Rate

Baud rate tolerance

Ouput single ended high

Ouput single ended low

Description

Output signal crossover voltage

Data fall time

Data rise time

Rise and fall time matching

Source jitter total: to next transition

Source jitter total: for paired transitions

Low Speed

Sym bol

BR

Min

1.5

Max

Bppm -15000.0

15000.0

Driver Parameters

VOH 2.8

3.6

VOL

VCRS

TLR

TLF

0.0

1.3

75.0

75.0

0.3

2.0

300.0

300.0

TLRFM

TUDJ1

TUDJ2

Receiver Parameters

VIH

VIL

VDI

80.0

-95.0

-150.0

2.0

-

0.2

125.0

95.0

150.0

-

0.8

-

Units

Mbps ppm

Input single ended high

Input single ended low

Differential input sensitivity

V

V

V

Notes:

General Comment: For more information, refer to Universal Serial Bus Specification, Revision 2.0, April 2000.

General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified.

General Comment: To comply w ith the values presented in this table, refer to your local

Marvell representative for register settings.

1. Defined w ith 1.425 kilohm pull-up resistor to 3.6V.

2. Defined w ith 14.25 kilohm pull-dow n resistor to ground.

3. See "Data Signal Rise and Fall Time" w aveform.

ns

% ns ns

V

V

V ns

4. Defined from 10% to 90% for rise time and 90% to 10% for fall time.

5. Including frequency tolerance. Timing difference betw een the differential data signals.

Defined at crossover point of differential data signals.

Notes

-

-

-

-

-

1

2

3

3, 4

3, 4

-

5

5

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December 2, 2008, Preliminary

Electrical Specifications

Differential Interface Electrical Characteristics

Table 74: USB Full Speed Driver and Receiver Characteristics

Baud Rate

Baud rate tolerance

Ouput single ended high

Ouput single ended low

Description

Output signal crossover voltage

Output rise time

Output fall time

Source jitter total: to next transition

Sym bol

BR

Bppm

Driver Parameters

VOH

VOL

VCRS

TFR

TFL

TDJ1

Source jitter total: for paired transitions TDJ2

Source jitter for differential transition to SE0 transition TFDEOP

Receiver Parameters

Input single ended high

Input single ended low

Differential input sensitivity

Receiver jitter : to next transition

Receiver jitter: for paired transitions

VIH

VIL

VDI tJR1 tJR2

Full Speed

Min

2.8

0.0

1.3

4.0

4.0

-3.5

-4.0

-2.0

2.0

-

0.2

-18.5

-9.0

12.0

Max

-2500.0

2500.0

3.6

0.3

2.0

20.0

20.0

3.5

4.0

5.0

-

0.8

-

18.5

9.0

Units

Mbps ppm ns ns ns ns

V

V

V ns

V

V

V ns ns

Notes:

General Comment: For more information, refer to Universal Serial Bus Specification, Revision 2.0, April 2000.

General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified.

General Comment: To comply w ith the values presented in this table, refer to your local

Marvell representative for register settings.

1.. Defined w ith 1.425 kilohm pull-up resistor to 3.6V.

2.. Defined w ith 14.25 kilohm pull-dow n resistor to ground.

3. Defined from 10% to 90% for rise time and 90% to 10% for fall time.

4. See "Data Signal Rise and Fall Time" w aveform.

5. Including frequency tolerance. Timing difference betw een the differential data signals.

6. Defined at crossover point of differential data signals.

Notes

-

-

-

6

-

-

6

1

2

4

3, 4

3, 4

5, 6

5, 6

6

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Hardware Specifications

Table 75: USB High Speed Driver and Receiver Characteristics

Baud Rate

Baud rate tolerance

Data signaling high

Data signaling low

Data rise time

Data fall time

Data source jitter

Description Sym bol

BR

Bppm

Driver Parameters

VHSOH

VHSOL

THSR

THSF

High Speed

Min

-500.0

480.0

Max

500.0

360.0

-10.0

500.0

500.0

440.0

10.0

See note 2

-

-

Units

Mbps ppm mV mV ps ps

Receiver Parameters

Differential input signaling levels

Data signaling common mode voltage range

Receiver jitter tolerance

VHSCM

See note 3

-50.0

500.0

See note 3 mV

Notes:

General Comment: For more information, refer to Universal Serial Bus Specification, Revision 2.0, April 2000.

General Comment: The load is 100 ohm differential for these parameters, unless otherw ise specified.

General Comment: To comply w ith the values presented in this table, refer to your local

Marvell representative for register settings.

1. Defined from 10% to 90% for rise time and 90% to 10% for fall time.

2. Source jitter specified by the "TX eye diagram pattern template" figure.

3. Receiver jitter specified by the "RX eye diagram pattern template" figure.

Notes

-

-

1

1

-

-

2

3

-

3

10.7.4.2

USB Interface Driver Waveforms

Figure 47: Low/Full Speed Data Signal Rise and Fall Time

Rise Time

90%

Fall Time

VCRS

90%

10% 10%

Differential

Data Lines

TR TF

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December 2, 2008, Preliminary

Electrical Specifications

Differential Interface Electrical Characteristics

Figure 48: High Speed TX Eye Diagram Pattern Template

+525mV

+475mV

+300mV

+400mV

Differential

0 Volts

Differential

-300mV

-475mV

-525mV

0%

7.5% 37.5% 62.5% 92.5%

100%

Figure 49: High Speed RX Eye Diagram Pattern Template

- 400mV

Differential

+525mV

+475mV

+400mV

Differential

+175mV

0 Volts

Differential

-175mV

- 400mV

Differential

-475mV

-525mV

0%

12.5% 35

65

87.5%

100%

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Hardware Specifications

11

Thermal Data (Preliminary)

Table 76

provides the package thermal data for the device. This data is derived from simulations that were run according to the JEDEC standard.

The thermal parameters are preliminary and subject to change.

Note

TET

The documents listed below provide a basic understanding of thermal management of integrated circuits (ICs) and guidelines to ensure optimal operating conditions for Marvell products. Before designing a system it is recommended to refer to these documents:

„

„

Application Note, AN-63 Thermal Management for Selected Marvell® Products, Document

Number MV-S300281-00

White Paper, ThetaJC, ThetaJA, and Temperature Calculations, Document Number

MV-S700019-00.

Table 76: Thermal Data for the 88F619x in the QFP 216-pin Package (Preliminary)

S y m b o l D e f i n i t i o n

θ

JA

Ψ

JT

θ

JC

Ψ

JB

θ

JB

Thermal resistance: junction to ambient.

Thermal characterization parameter: junction to case center.

Thermal resistance: junction to case (not air-flow dependent)

Thermal characterization parameter: junction to the bottom of the package.

Thermal resistance: junction to the bottom of the package (not air-flow dependent)

A i r f l o w Va l u e ( C / W )

0 [ m / s ] 1 [ m / s ]

24.2

21.7

1.04

1.16

2 [ m / s ]

20.7

1.26

11.84

9.7

11.95

16.1

11.93

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December 2, 2008, Preliminary

12

Package

This section provides the 88F619x package drawing and dimensions.

Figure 50: LQFP 216-pin Package and Dimensions

Package

1.

To be determined at seating plane —C—.

2.

Dimensions D1 and E1 do not include mold protrusions.

6.

A1 is defined as the distance from the seating plane to the lowest point of the package body.

7.

Controlling dimension: millimeter.

D1 and E1 are maximum plastic body size dimensions

8.

Reference document: JEDEC MS-026 including mold mismatch.

9.

Special characteristics C class: ccc

3.

Dimension b does not include Dambar protrusions.

Dambar can not be located on the lower radius or the foot.

4.

Exact shape of each corner is optional.

5.

These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip.

Copyright © 2008 Marvell

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88F619x

Hardware Specifications

Table 77: LQFP 216-pin Package Dimensions

S y m b o l

A

D

1

E

E

1

| e |

L

A

1

A

2 b b

1 c c

1

D

L

1

R

1

R

2

S

θ

θ

1

θ

2

θ

3 ccc

0.09

0.09

25.85

23.90

25.85

23.90

M i n

0.05

1.35

0.13

0.13

0.45

0.08

0.08

0.20

0 o

0 o

11 o

11 o

D i m e n s i o n i n m m

N o m i n a l

1.40

0.18

0.16

0.14

0.12

26.00

24.00

26.00

24.00

0.40 BSC

0.60

1.00 REF

3.5

o

12 o

12 o

0.08

0.20

0.16

26.15

24.10

26.15

24.10

M a x

1.60

0.15

1.45

0.23

0.19

0.75

7 o

13 o

13 o

0.003

0.003

0.008

0 o

0 o

0 o

0 o

0.004

0.004

1.018

0.941

1.018

0.941

M i n

0.002

0.053

0.005

0.005

D i m e n s i o n i n i n c h e s

N o m i n a l

M a x

0.063

0.055

0.007

0.006

0.006

0.057

0.009

0.007

0.018

0.006

0.005

1.024

0.945

1.024

0.945

0.016 BSC

0.24

0.008

0.006

1.030

0.949

1.030

0.949

0.030

0.039 REF

3.5

o

12 o

12 o

0.003

7 o

13 o

13 o

Table 78: LQFP 216-pin Package Exposed Pad (ePAD) Size

S y m b o l

D 2

E 2

E x p o s e d P a d S i z e m m

5.715 REF

5.715 REF

I n c h e s

0.225 REF

0.225 REF

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Copyright © 2008 Marvell

December 2, 2008, Preliminary

Part Order Numbering/Package Marking

Part Order Numbering

13

Part Order Numbering/Package Marking

13.1

Part Order Numbering

Figure 51 shows the part order numbering scheme for the 88F6190 and 88F6192. Refer to Marvell

Field Application Engineers (FAEs) or representatives for further information when ordering parts.

Figure 51: Sample Part Number

88F619x–xx–LGO2Cxxx–xxxx

Custom code (optional)

Part number

88F6190

88F6192

Die revision

Custom code

Speed code

060 = 600 MHz (88F6190)

080 = 800 MHz (88F6192)

Temperature code

C = Commercial

I = Industrial

Environmental code

2 = Green (RoHS 6/6 and

Halogen-free)

Package code

LGO = 216-pin LQFP

r

Table 79: Part Order Options

P a c k a g e Ty p e

216-pin LQFP

216-pin LQFP

P a r t O r d e r N u m b e r

88F6190-xx-LGO2C060 (Green, RoHS 6/6 and Halogen-free package), 600 MHz

88F6192-xx-LGO2C080 (Green, RoHS 6/6 and Halogen-free package), 800 MHz

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88F619x

Hardware Specifications

13.2

Package Marking

Figure 52 shows a sample Commercial package marking and pin 1 location for the device.

Figure 52: Package Marking and Pin 1 Location

Country of origin

(Contained in the mold ID or marked as the last line on the package.)

Part number and die revision code

88F6190 = Part number

XX

=

Die revision

Pin 1 location

88F6-LGOe

Lot Number

YYWW [email protected]

Country of Origin

88F6190-xx

XXXX

Marvell logo

Part number prefix, package code, environmental code

88F6 = Part number prefix

LGO = Package code e = Environmental code: 2 = Green

Date code, custom code, assembly plant code

YYWW = Date code (YY = year, WW = Work Week) xx = Custom code

@ = Assembly plant code

Temperature and speed code

C060 = Commercial, 600 MHz

88F6-LGOe

Lot Number

YYWW [email protected]

Country of Origin

88F6192-xx

XXXX

Part number and die revision code

88F6192 = Part number

XX

=

Die revision

Temperature and speed code

C080 = Commercial, 800 MHz

Note:

The above drawings are not drawn to scale. Location of markings is approximate.

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Copyright © 2008 Marvell

December 2, 2008, Preliminary

Revision History

A

Revision History

Table 80: Revision History

R e v i s i o n D a t e C o m m e n ts

F December 2, 2008 Revision

1. For the 88F6190, added a Fast Ethernet port, in addition for the Gigabit Ethernet port.

2. In

Figure 2, 88F6192 Pin Logic Diagram, on page 22

:

• Changed the GE_TXCLKOUT pin to input/output and added a note under the figure, stating that the pin is an input when used the MII/MMII Transmit Clock.

• Changed the name of pins GE_TXEN to GE_TXCTL and GE_RXDV to GE_RXCTL.

• Deleted the VDD_GE pin and replaced it with pins VDD_GE_A and VDD_GE_B. Also changed the VDD_GE pin to

VDD_GE_A/VDD_GE_B throughout the document.

3. In

Table 4, Power Pin Assignments, on page 25

, changed the name of the VDD_GE pin to VDD_GE_A and

VDD_GE_B and added new descriptions for those pins.

4. In

Table 7, PCI Express Interface Pin Assignments, on page 30

, revised the description of the PEX_CLK_P/N pins to state that they can be configured as input or output according to the reset strap.

5. In

Table 9, 88F6190 Gigabit Ethernet Interface Pin Assignments, on page 32

:

• Revised most of the pin descriptions.

• Revised the I/O designations for GE_TXCLKOUT and MPP[29]/GE1[9].

• Changed the name of GE_TXEN to GE_TXCTL and GE_RXDV to GE_RXCTL.

6. In

Table 10, 88F6192 Gigabit Ethernet Port0/1 Interface Pin Assignments, on page 34 , indicated that:

• When the GE_TXCLKOUT pin is used as an MII/MMII Transmit Clock, it is an input pin.

• When the MPP[29]/GE1[9] pin is used as a GMII Transmit Clock, it is a Tri-State output pin.

7. In

Table 14, RTC Interface Pin Assignments, on page 42

, changed the type for RTC_XOUT to analog.

8. In the description of signal AU_SPDFRMCLK in

Table 19, Audio (S/PDIF / I

2

S) Interface Signal Assignment, on page 47 , added a reference to the new AU_SPDFRMCLK information in the Reference Clock AC Timing

Specifications table.

9. In

Table 26, Unused Interface Strapping, on page 56

, revise the description for configuring the:

• MPP signals.

• PCI Express clock signals.

10. In

Table 37, I/O and Core Voltages, on page 73

, for the 88F6190, revise the I/O Voltage column to remove pin

VDD_GE and replace it with pins VDD_GE_A and VDD_GE_B.

11. In

Figure 3, 88F6190 Pin Map Top View, on page 57

and

Table 27, 88F6190 Pinout Sorted by Pin Number, on page 58 :

• Changed pins 18 and 25 from VDD_GE to VDD_GE_A.

• Changed pin 23 from GE_TXEN to GE_TXCTL and changed pin 27 from GE_RXDV to GE_RXCTL.

• Changed pins 40 and 47 from VDD_GE to VDD_GE_B.

12. In

Table 32, 88F6190 Ethernet Ports Pins Multiplexing, on page 68

, revised the RGMII column.

13. Revised the configurations options described in Section 6.2, Gigabit Ethernet (GbE) Pins Multiplexing on MPP, on page 68

and added a note stating that all relevant Gigabit Ethernet signals must be implemented.

14. In

Table 36, Supported Clock Combinations, on page 72 , added a column showing the device number.

15. In

Section 8.5, Pins Sample Configuration, on page 76

, revised the note describing the pins with multiple voltage options.

16. In

Table 38, Reset Configuration, on page 77

, revised the rows relating to the following signals:

MPP[2], MPP[3], MPP[5], MPP[10], MPP[12], MPP[19], MPP[33], NF_ALE, NF_REn, NF_CLE, NF_WEn.

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Hardware Specifications

Table 80: Revision History (Continued)

R e v i s i o n D a t e C o m m e n ts

17. In

Table 42, Recommended Operating Conditions, on page 87 :

• For the 88F6190, revised the VDD_GE pin to VDD_GE_A and added a separate row for VDD_GE_B.

• For parameter RTC_AVDD Analog supply for RTC in Battery Back-up mode, revised the values for the minimum to

1.3V from 1.4V and for the maximum to 1.7V from 1.6V.

18. In

Table 43, Thermal Power Dissipation, on page 89 , for the eFuse during Burning mode parameter added a note:

The eFuse burn is done once, and there should be no thermal effect, after it has been burned.

19. Revised the introduction to Section 10.5.2, RGMII, SMI and REF_CLK_XIN 1.8V (CMOS) DC Electrical Specifications, on page 93

.

20. In

Table 51, Reference Clock AC Timing Specifications, on page 97

:

• Revised the names of the Ethernet transmit symbols to F

GE_TXCLK_OUT

, DC

GE_TXCLK_OUT

, and SR

GE_TXCLK_OUT

.

• Added the S/PDIF Recovered Master Clock.

• Added the Transport Stream External Reference Clock.

• For the PTP Reference Clock, revised the values for the Frequency, Duty Cycle, and Pk-Pk jitter parameters.

21. Revised the description of the power rails in the paragraph before Table 45, General 3.3V Interface (CMOS) DC

Electrical Specifications, on page 92 .

22. Revised the description of the power rails in the paragraph before Table 46, RGMII 1.8V Interface (CMOS) DC

Electrical Specifications, on page 93 .

E October 5, 2008 Revision

1. In

Table 38, Reset Configuration, on page 77

, for

CPU_CLK Frequency Select

, revised the description of values 0x4 and 0x6.

2. In

Table 7, PCI Express Interface Pin Assignments, on page 30 , revised the note in the description of the

PEX_CLK_P/N pins.

3. In

Table 26, Unused Interface Strapping, on page 56

, added the eFuse strapping.

4. In

Section 8.1.1, Power-Up Sequence Requirements, on page 73

and

Section 8.1.2, Power-Down Sequence

Requirements, on page 74

, added a power up/down requirements for when VHV is in eFuse Burning mode.

5. In

Table 42, Recommended Operating Conditions, on page 87 :

• For VHV, revised the two parameters to VHV (during eFuse Burning mode) and VHV (during eFuse Reading mode) and added notes in the comments column for both VHV voltages.

• For VDD_M, PEX_AVDD, and USB_AVDD, revised the comments column.

• for RTC_AVDD, revised the values for minimum to 1.4V from 1.3V and for maximum to 1.6V from 1.7V.

6. In

Table 43, Thermal Power Dissipation, on page 89 , revised the row for the SDRAM and added a row for the eFuse.

7. In

Table 44, Current Consumption, on page 91 , revised the row for the SDRAM and added a row for the eFuse.

8. In

Table 51, Reference Clock AC Timing Specifications, on page 97

:

• For the CPU and Core Reference Clock frequency, revised the values.

• For the PTP Reference Clock, added the Slew rate and Pk-Pk jitter parameters.

D August 18, 2008 Revision

1. Added the XOR engine to the block diagrams in the

Product Overview

on

page 3

.

2. In

Table 4, Power Pin Assignments, on page 25

:

• Changed the voltage for XTAL_AVDD from 2.5V to 1.8V.

• Changed the voltage for SATA_AVDD (88F6190) and SATA0_AVDD/SATA1_AVDD (88F6192) from 2.5V to 3.3V.

• Added pin VHV.

3. In

Figure 1, 88F6190 Pin Logic Diagram, on page 21 ,

Figure 2, 88F6192 Pin Logic Diagram, on page 22 , and

Table 7,

PCI Express Interface Pin Assignments, on page 30 , changed PEX_CLK_P/N for input to input/output (I/O). Also

added VHV to both pin logic diagrams.

4. In Table 6, DDR SDRAM Interface Pin Assignments, on page 28

, revised the description of M_NCASL and M_PCAL to indicate the range of the resistor.

5. Added present and active pins to

Table 8, SATA Port Interface Pin Assignment, on page 31

.

Doc. No. MV-S104987-U0 Rev. F

Page 144 Document Classification: Proprietary Information

Copyright © 2008 Marvell

December 2, 2008, Preliminary

Revision History

Table 80: Revision History (Continued)

R e v i s i o n D a t e C o m m e n ts

6. In

Section 2.2.6, Gigabit Ethernet Port Interface Pin Assignments, on page 32

, added a note: For the TXCLK, use the

GE_RXCLK pin. Also indicated which pins are for port0 and which for port1.

7. Revised Table 21, Secure Digital Input/Output (SDIO) Interface Signal Assignment, on page 49 to indicate the pins

requiring pull up.

8. Added

Table 23, Transport Stream (TS) Interface Signal Assignment, on page 52 .

9. Added

Section 2.2.20, Precise Timing Protocol (PTP) Interface, on page 54

.

10. In

Table 25, Internal Pull-up and Pull-down Pins, on page 55

, changed pins GE_MDC, MPP[7] and MPP[18] from pull down to pull up and removed MPP[13], MPP[15], and MPP[17] from the table, since they do not require a pull up/down.

11. In Table 3, Unused Interface Strapping, on page 56 , revised the description of the strapping for the SATA_AVDD pin in

the 88F6190 and the SATA0_AVDD/SATA1_AVDD pins in the 88F6192.

12. In

Section 6.1, Multi-Purpose Pins Functional Summary, on page 61 :

• Changed the MPP[6] row in the table to remove the 0x0 option.

• Revised the description of SYSRST_OUTn.

• Added a bullet: Pin MPP[6] wakes up after reset in 0x1 mode (SYSRST_OUTn)

13. In

Section 6.3, TSMP (TS Multiplexing Pins) on MPP, on page 70 , added to the description of the TSMP pins.

14. In

Table 35, 88F619x Clocks, on page 71

, added the PTP clock and changed references to the Core clock to be the

TCLK.

15. Revised Section 7.1, Spread Spectrum Clock Generator (SSCG), on page 72

.

16. Revised Table 37, I/O and Core Voltages, on page 73

.

17. In

Section 8.2, Hardware Reset, on page 74

, added SYSRST_OUTn to the list of pins that are still active during

SYSRSTn assertion.

18. Revised Section 8.2.1, Reset Out Signal, on page 75 and Section 8.2.3, SYSRSTn Duration Counter, on page 75

and added

Section 8.2.2, Power On Reset (POR), on page 75 .

19. In

Section 8.3.2, PCI Express Endpoint Reset, on page 76

revised the bulleted items.

20. Revised Section 8.5, Pins Sample Configuration, on page 76 .

21. Made major revisions to Table 38, Reset Configuration, on page 77

.

22. Revised the first two paragraphs in Section 8.6, Serial ROM Initialization, on page 80 .

23. In

Section 8.7, Boot Sequence, on page 81 revised the paragraph following step 4.

24. Revised Table 35, 88F619x Clocks, on page 71 and

Table 36, Supported Clock Combinations, on page 72 .

25. In

Table 40, IDCODE Register Map, on page 84 , revised the description of bits [31:28].

26. In

Table 41, Absolute Maximum Ratings, on page 85 , revised the voltage for the SATA and XTAL AVDD pins.

27. In the

Table 42, Recommended Operating Conditions, on page 87 :

• Revised the voltage for the SATA and XTAL AVDD pins

• Added values for VDD_CPU and for the 3.3V interfaces

• Revised the minimum value to 3.15V and the maximum value to 3.45V (+/-5%)

• Revised the values for PEX_AVDD to minimum 1.7V, typical 1.8V, and maximum 1.9V.

28. In

Section 10.3, Thermal Power Dissipation, on page 89 , revised values for Core, PCI Express, USB, and SATA

parameters and revised the notes under the table.

29. In

Section 10.4, Current Consumption, on page 91 , revised values for the Core (including CPU), PCI Express, USB,

and SATA parameters and revised the notes under the table.

30. In

Section 10.5.1, General 3.3V (CMOS) DC Electrical Specifications, on page 92

, added reference to PTP and

RGMII.

31. Deleted Section 8.5.2 REF_CLK_XIN 2.5V (CMOS) DC Electrical Specifications and added pin REF_CLK_XIN to

Section 10.5.2, RGMII, SMI and REF_CLK_XIN 1.8V (CMOS) DC Electrical Specifications, on page 93

, since the power rail for the REF_CLK_XIN pin was changed from 2.5V to 1.8V.

32. Revised Table 51, Reference Clock AC Timing Specifications, on page 97 .

Copyright © 2008 Marvell

December 2, 2008, Preliminary Document Classification: Proprietary Information

Doc. No. MV-S104987-U0 Rev. F

Page 145

88F619x

Hardware Specifications

Table 80: Revision History (Continued)

R e v i s i o n D a t e C o m m e n ts

33. Revised Table 68, PCI Express Interface Differential Reference Clock Characteristics, on page 127

and Table 69, PCI

Express Interface Spread Spectrum Requirements, on page 128 .

34. Revised Figure 28, TWSI Output Delay AC Timing Diagram, on page 113 so that it shows SDA t

OV

relative to the SCK falling edge, as shown in the two tables that proceed the figure.

35. Revised all of

Section 13, Part Order Numbering/Package Marking, on page 141

.

C June 16, 2008 Revision

1. Added information for the 88F6190 device throughout this specification. This includes the addition of two new sections:

Section 1, Overview, on page 18

and Section 4, 88F6190 Pinout, on page 57

.

2. Added AN-249: Configuring the Marvell® SATA PHY to Transmit Predefined Test Patterns to the list of Related

Documentation on page 16

.

3. In

Table 4, Power Pin Assignments, on page 25

, revised the description of VDD_GE_A and VDD_GE_B to add additional information about RGMII. Also added pin VDD_GE for the 88F6190 and revised the description of VDD to indicate that it provides the CPU voltage.

4. In

Table 10, 88F6192 Gigabit Ethernet Port0/1 Interface Pin Assignments, on page 34 , added a description for

MII/MMII to the GE_TXD[3:0], GE_TXCTL, GE_RXCTL, GE_RXCLK, GE_RXD[3:0] rows. Also for pin

MPP[30]/GE1[10] added a description for MII/MMII Receive Data Valid.

5. In

Table 11, Serial Management Interface (SMI) Pin Assignments, on page 39

and in Table 16, MPP Interface Pin

Assignment, on page 44 , revised the power rail information to indicate the power rail for each device.

6. In

Table 19, Audio (S/PDIF / I

2

S) Interface Signal Assignment, on page 47

and Table 22, Time Division Multiplexing

(TDM) Interface Signal Assignment, on page 50 , revised the power rail to VDD_GE_B.

7. In

Section 6.1, Multi-Purpose Pins Functional Summary, on page 61 :

• Changed all reference to MPP[0] and MPP[11] from GPI to GPIO.

• Added the following bullet at the end of the section, after the tables: When TWSI serial ROM initialization is enabled,

MPP[8] and MPP[9] wake up as TWSI data and clock pins, respectively.

8. Revised the supported clock combinations in Table 36, Supported Clock Combinations, on page 72

.

9. Revised Section 6.2, Gigabit Ethernet (GbE) Pins Multiplexing on MPP, on page 68 to describe the differences in the

Gigabit Ethernet multiplexing for the 88F6190 and 88F6192.

10. Revised Table 32, 88F6190 Ethernet Ports Pins Multiplexing, on page 68 and

Table 33, 88F6192 Ethernet Ports Pins

Multiplexing, on page 69 including the addition of a new configuration option for the Gigabit Ethernet ports: Port 0

MII/MMII, Port 1 RGMII.

11. In

Table 35, 88F619x Clocks, on page 71

, revised the PEX PHY and USB PHY PLL rows and added the PTP clock.

12. In

Table 38, Reset Configuration, on page 77 , revised the description of TWSI Serial ROM Initialization

to indicate that

MPP[8] and MPP[9] wake up as TWSI data and clock pins, respectively.

13. In

Table 41, Absolute Maximum Ratings, on page 85 ,

Table 42, Recommended Operating Conditions, on page 87 ,

Table 43, Thermal Power Dissipation, on page 89 , and

Table 44, Current Consumption, on page 91 , changed all

occurrences of VDD_CPU to VDD.

14. In Table 42, Recommended Operating Conditions, on page 87 , revised the description of the VDD_GE_A/VDD_GE_B

row to show that RGMII can also operate with a voltage of 3.3V.

15. In

Table 43, Thermal Power Dissipation, on page 89 , added the row RGMII 3.3V interface.

16. In

Table 44, Current Consumption, on page 91 , revised the interface RGMII 1.8V interface to RGMII 1.8V or 3.3V

interface. Also added the parameter DDR2 SDRAM interface (On Board 16-bit 200 MHz).

17. Added

Table 54, RGMII 10/100 AC Timing Table at 3.3V, on page 102 .

B April 8, 2008 Revision

1. In the features list, added the functional block diagram and the usage model diagram.

2. Throughout this specification, LVCMOS and LVTTL were changed to CMOS.

3. In

Figure 2, 88F6192 Pin Logic Diagram, on page 22

revised the power pins section, changed the MPP pins to

MPP[35:0] from MPP[34:0] and removed the interfaces that are multiplexed on the MPP pins.

Doc. No. MV-S104987-U0 Rev. F

Page 146 Document Classification: Proprietary Information

Copyright © 2008 Marvell

December 2, 2008, Preliminary

Revision History

Table 80: Revision History (Continued)

R e v i s i o n D a t e C o m m e n ts

4. Revised Table 2, Pin Functions and Assignments Table Key, on page 23

to show only terms relevant for this device.

5. In Table 4, Power Pin Assignments, on page 25

, added pin SSCG_AVDD and added the SMI interface at 1.8V and the

MII/MMII interface at 3.3V to the description of the interfaces supported by pin VDD_GE_A.

6. In

Table 10, 88F6192 Gigabit Ethernet Port0/1 Interface Pin Assignments, on page 34 , removed pins GE_MDC and

GE_MDIO.

7. Added

Section 2.2.7, Serial Management Interface (SMI) Interface Pin Assignments, on page 39

, with a description of the GE_MDC and GE_MDIO pins.

8. In

Table 14, RTC Interface Pin Assignments, on page 42

, changed the pin type for RTC_XIN to analog from CMOS.

9. In

Table 17, Two-Wire Serial Interface (TWSI) Interface Pin Assignment, on page 45

, changed the note to:

Requires a pull-up resistor to VDDO.

10. Added

Section 3, Unused Interface Strapping, on page 56

.

11. In

Figure 4, 88F6192 Pin Map Top View, on page 59

and

Table 28, 88F6192 Pinout Sorted by Pin Number, on page 60 :

• Changed pin 100 to MPP[16] from MPP[17].

• Changed pin 101 to MPP[17] from MPP[16].

• Changed pin 149 to PEX_AVDD from VSS.

12. In

Table 35, 88F619x Clocks, on page 71

, revised the description of CPU PLL to mention SSCG.

13. Added

Section 7.1, Spread Spectrum Clock Generator (SSCG), on page 72

.

14. Added

Section 8.1, Power-Up/Down Sequence Requirements, on page 73

and revised the title of

Section 8

to reflect this changed.

15. In

Section 8.4, Sheeva

CPU TAP Controller Reset, on page 76

, revised the note referring to sample at reset and added the note: If a signal is pulled up on the board, it must be pulled to the proper voltage level. Certain reset configuration pins are powered by VDD_GE_A and VDD_GE_B. Those pins have multiple voltage options (see

Table 42, Recommended Operating Conditions, on page 87

).

16. In Table 41, Absolute Maximum Ratings, on page 85

and

Table 42, Recommended Operating Conditions, on page 87

, added the parameter SSCG_VDD.

17. In

Table 43, Thermal Power Dissipation, on page 89 added the following:

The purpose of the Thermal Power Dissipation table is to support system engineering in thermal design.

18. In

Table 44, Current Consumption, on page 91 added the following:

The purpose of the Current Consumption table is to support board power design and power module selection.

19. In

Table 51, Reference Clock AC Timing Specifications, on page 97

:

• Revised the symbols for the Transport Stream (TS) output and input mode reference clocks

• Revised the symbols for the SMI master mode reference clock

• Revised the symbols for the TWSI master mode reference clock

• Revised the description for symbol F

RTC_XIN.

• Removed the RGMII, GMII, MII 100 Mbps, and MII 10 Mbps rows from this table since they are not relevant to this device.

20. In

Table 71, SATA-I Interface Gen1i Mode Driver and Receiver Characteristics, on page 132

, added driver and receiver return loss parameters, according to updated standard.

21. In Table 64, Thermal Data for the 88F6190/88F6192 in the QFP 216-pin Package, on page 102, added values for all of the parameters.

22. Replaced

Figure 50, LQFP 216-pin Package and Dimensions, on page 139

with a revised package drawing,

revised Table 77, LQFP 216-pin Package Dimensions, on page 140 , and added Table 78, LQFP 216-pin Package

Exposed Pad (ePAD) Size, on page 140 .

A January 28, 2008 Initial release

Copyright © 2008 Marvell

December 2, 2008, Preliminary Document Classification: Proprietary Information

Doc. No. MV-S104987-U0 Rev. F

Page 147

THIS PAGE IS INTENTIONALLY LEFT BLANK.

Contact I NFORMATION

Marvell Semiconductor, Inc.

5488 Marvell Lane

Santa Clara, CA 95054, USA

Tel: 1.408.222.2500

Fax: 1.408.752.9028

www.marvell.com

Marvell.

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