Stereo Class AB Audio Subsystem with a True Ground Headphone

Stereo Class AB Audio Subsystem with a True Ground Headphone
LM49200, LM49200TLEVAL
www.ti.com
LM49200
SNAS459A – MAY 2009 – REVISED APRIL 2013
Stereo Class AB Audio Subsystem with a True
Ground Headphone Amplifier
Check for Samples: LM49200, LM49200TLEVAL
FEATURES
APPLICATIONS
•
•
•
•
1
2
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•
•
•
•
•
•
•
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Differential Mono Input and Stereo SingleEnded Input
32-Step Digital Volume Control (-80 to +18dB)
Three Independent Volume Channels (Left,
Right, Mono)
Separate Headphone Volume Control
Flexible Output for Speaker and Headphone
Output
True Ground Headphone Amplifier Eliminates
Large DC Blocking Capacitors Reducing PCB
Space and Cost
Receiver Pass-Through Capability
Soft Enable Function
RF Immunity Topology
“Click and Pop” Suppression Circuitry
Thermal Shutdown Protection
Micro-Power Shutdown
I2C Control Interface
Available in Space-Saving DSBGA Package
KEY SPECIFICATIONS
•
•
•
•
•
•
Supply Voltage (VDD): 2.7V ≤ VDD ≤ 5.5V
I2C Supply Voltage: 1.7V ≤ I2CVDD ≤ 5.5V
Output power at VDD = 5V, 1% THD+N
– RL = 8Ω speaker: 1.25W (typ)
– RL = 32Ω headphone: 38mW (typ)
Output power at VDD = 3.3V, 1% THD+N
– RL = 8Ω speaker: 520W (typ)
– RL = 32Ω headphone: 38mW (typ)
PSRR:
– VDD = 3.3V, 217Hz ripple, Mono In: 95dB
(typ)
Shutdown power supply current 0.02μA (typ)
Portable Electronic Devices
Mobile Phones
PDAs
DESCRIPTION
The LM49200 is a fully integrated audio subsystem
with a stereo power amplifier capable of delivering
500mW of continuous average power per channel
into 8Ω with 1% THD+N using a 3.3V supply. The
LM49200 includes a separate stereo headphone
amplifier that can deliver 35mW per channel into
32Ω.
The LM49200 has three input channels. A pair of
single-ended inputs and a fully differential input
channel. The LM49200 features a 32-step digital
volume control on the input stage and an 8-step
digital volume control on the headphone output stage.
The digital volume control and output modes are
programmed through a two-wire I2C compatible
interface that allows flexibility in routing and mixing
audio channels.
The LM49200 is designed for cellular phone, PDA,
and other portable handheld applications. The high
level of integration minimizes external components.
The True Ground headphone amplifier eliminates the
physically large DC blocking output capacitors
reducing required board space and reducing cost.
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2013, Texas Instruments Incorporated
LM49200, LM49200TLEVAL
SNAS459A – MAY 2009 – REVISED APRIL 2013
www.ti.com
Typical Application
Figure 1. Typical Audio Application Circuit
2
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SNAS459A – MAY 2009 – REVISED APRIL 2013
Connection Diagram
Top View
1
2
3
ROUT-
VDD
MIN+
MIN-
ROUT+
I CVDD
LIN
RIN
GND
SCL
BIAS
VSSCP
D
LOUT+
SDA
C1N
C1P
E
LOUT-
HPR
HPL
CPGND
A
B
C
2
4
Figure 2. 20 Bump DSBGA Package
(Bump Side Down)
See Package Number YZR0020BBA
Bump Descriptions
Bump
Name
Pin Function
Type
A1
ROUT-
Right Loudspeaker Negative Output
Analog Output
A2
VDD
Power Supply
Power Input
A3
MIN+
Differential Mono Positive Input
Analog Input
A4
MIN-
Differential Mono Negative Input
Analog Input
B1
ROUT+
Right Loudspeaker Positive Output
Analog Output
B2
I2CVDD
I2C power supply
Power Input
B3
LIN
Single-ended Left Input
Analog Input
B4
RIN
Single-ended Right Input
Analog Input
C1
GND
Power Ground
Ground
C2
SCL
I2C Clock
Digital Input
C3
BIAS
Half-Supply Bias point, capacitor bypassed
Analog Output
C4
VSSCP
Negative Charge Pump Power Supply
Analog Output
D1
LOUT+
Left Loudspeaker Negative Output
Analog Output
D2
SDA
I2C Data
Digital Input
D3
CIN
Negative Terminal Charge Pump Flying Capacitor
Analog Output
D4
CIP
Positive Terminal Charge Pump Flying Capacitor
Analog Output
E1
LOUT-
Left Loudspeaker Positive Output
Analog Output
E2
HPR
Right Headphone Output
Analog Output
E3
HPL
Left Headphone Output
Analog Output
E4
CPGND
Charge Pump Ground
Ground
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LM49200 LM49200TLEVAL
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LM49200, LM49200TLEVAL
SNAS459A – MAY 2009 – REVISED APRIL 2013
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Absolute Maximum Ratings (1) (2) (3)
Supply Voltage (1)
6.0V
−65°C to +150°C
Storage Temperature
GND − 0.3 to VDD + 0.3V
Voltage at Any Input Pin
Power Dissipation (4)
ESD Rating
Internally Limited
(5)
2000V
ESD Rating (6)
200V
Junction Temperature (TJMAX)
Soldering Information
150°C
Vapor Phase (60sec.)
215°C
Infrared (15sec.)
220°C
See AN-1112 “Micro SMD Wafer Level Chip Scale Package” (SNVA009).
Thermal Resistance
(1)
(2)
(3)
(4)
(5)
(6)
θJA
45.1°C/W
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
The maximum power dissipation must be derated at elevated temperatures and is dictated by TJMAX, θJA, and the ambient temperature,
TA. The maximum allowable power dissipation is PDMAX = (TJMAX - TA) / θJA or the number given in Absolute Maximum Ratings,
whichever is lower.
Human body model, applicable std. JESD22-A114C.
Machine model, applicable std. JESD22-A115-A.
Operating Ratings
Temperature Range TMIN ≤ TA ≤ TMAX
−40°C ≤ TA ≤ 85°C
2.7V ≤ VDD ≤ 5.5V
Supply Voltage (VDD)
2
1.7V ≤ I2CVDD ≤ 5.5V
Supply Voltage (I CVDD)
I2CVDD ≤ VDD
4
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SNAS459A – MAY 2009 – REVISED APRIL 2013
Electrical Characteristics VDD = 3.3V (1) (2)
The following specifications apply for VDD = 3.3V, TA = 25°C, all volume controls set to 0dB, unless otherwise specified.
LS = Loudspeaker, HP = Headphone.
LM49200
Typ (3)
Limits (4)
Units
(Limits)
EP Receiver
(Output Mode Bit D4 = 1)
1.2
1.7
mA (max)
Stereo LS only (Mode 2)
4
5.5
mA (max)
Stereo HP only (Mode 8)
4.5
6.4
mA (max)
Stereo LS + Stereo HP (Mode 10)
7.0
9.8
mA (max)
0.02
1
µA (max)
VIN = 0V, Mode 10
LS output, RL = 8Ω BTL
HP output, RL = 32Ω SE
2.5
1.4
15
5
mV (max)
mV (max)
LS output, Mode 2, RL = 8Ω BTL
THD+N = 1%, f = 1kHz
520
450
mW (min)
HP output, Mode 8, RL = 32Ω SE
THD+N = 1%, f = 1kHz
38
35
mW (min)
LS output, f = 1kHz, RL = 8Ω BTL
PO = 250mW, Mode 2
0.05
%
HP output, f = 1kHz, RL = 32Ω SE
PO = 12mW, Mode 8
0.02
%
LS output, f = 1kHz,
VREF = VOUT (1%THD+N)
Gain = 0dB, A-weighted
LIN & RIN AC terminated
105
dB
HP output, f = 1kHz,
VREF = VOUT (1%THD+N)
Gain = 0dB, A-weighted
LIN & RIN AC terminated
101
dB
Parameter
Test Conditions
VIN = 0, No Loads
IDD
Quiescent Power Supply Current
ISD
Shutdown Current
VOS
Output Offset Voltage
PO
Output Power
THD+N
SNR
Total Harmonic Distortion + Noise
Signal-to-Noise Ratio
A-weighted, Inputs terminated to AC GND, Output Referred
εOUT
Output Noise
Right LS only, Mode 1
8
µV
LS: Mode 1
8
µV
LS: Mode 2
11
µV
LS: Mode 3
14
µV
HP: Mode 4
8
µV
HP: Mode 8
9
µV
HP: Mode 12
11
µV
LS: Mode 1, RL = 8Ω BTL
95
dB
LS: Mode 2, RL = 8Ω BTL
75
dB
HP: Mode 4, RL = 32Ω SE
90
dB
HP: Mode 8, RL = 32Ω SE
80
dB
VRIPPLE = 200mVPP, fRIPPLE = 217Hz, CB = 2.2μF
All inputs AC terminated to GND, output referred
PSRR
(1)
(2)
(3)
(4)
Power Supply Rejection Ratio
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
Datasheet min/max specification limits are ensured by test or statistical analysis.
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LM49200 LM49200TLEVAL
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LM49200, LM49200TLEVAL
SNAS459A – MAY 2009 – REVISED APRIL 2013
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Electrical Characteristics VDD = 3.3V(1)(2) (continued)
The following specifications apply for VDD = 3.3V, TA = 25°C, all volume controls set to 0dB, unless otherwise specified.
LS = Loudspeaker, HP = Headphone.
Parameter
CMRR
Common-Mode Rejection Ratio
XTALK
Crosstalk
ZIN
LM49200
Test Conditions
Typ (3)
Digital Volume Control Range
VOL
Volume Control Step Size Error
TWU
Wake-Up Time from Shutdown
Units
(Limits)
f = 217Hz, VCM = 1VP-P
LS: RL = 8Ω BTL, Mode 1
HP: RL = 32Ω SE, Mode 4
60
66
dB
dB
LS: PO = 400mW, f = 1kHz, Mode 2
80
dB
HP: PO = 12mW, f = 1kHz, Mode 8
70
dB
Maximum Gain setting
12.5
10
15
Maximum Attenuation setting
110
90
130
Maximum Gain
Maximum Attenuation
18
–80
MIN, LIN, and RIN Input Impedance
VOL
Limits (4)
kΩ (min)
kΩ (max)
kΩ (min)
kΩ (max)
dB
dB
0.2
dB
CB = 2.2μF, HP, Normal Turn-On Mode
29
ms
CB = 2.2μF, HP, Fast Turn-On Mode
16
ms
Electrical Characteristics VDD = 5.0V (1) (2)
The following specifications apply for VDD = 5.0V, TA = 25°C, all volume controls set to 0dB, unless otherwise specified.
LS = Loudspeaker, HP = Headphone.
Parameter
LM49200
Typ (3)
Limits (4)
Units
(Limits)
EP Receiver
(Output Mode Bit D4 = 1)
1.3
1.8
mA (max)
Stereo LS only (Mode 2)
4.2
5.9
mA (max)
Stereo HP only (Mode 8)
4.7
6.5
mA (max)
Test Conditions
VIN = 0, No Loads
IDD
Quiescent Power Supply Current
Stereo LS + Stereo HP (Mode 10)
ISD
VOS
Output Offset Voltage
PO
Output Power
THD+N
(1)
(2)
(3)
(4)
6
7.3
10.1
mA (max)
0.02
1
µA (max)
VIN = 0V, Mode 10
LS output, RL = 8Ω BTL
HP output, RL = 32Ω SE
2.5
1.4
15
5
mV (max)
mV (max)
LS output, Mode 2, RL = 8Ω BTL
THD+N = 1%, f = 1kHz
1.25
W
HP output, Mode 8, RL = 32Ω SE
THD+N = 1%, f = 1kHz
38
mW
LS output, f = 1kHz, RL = 8Ω BTL
PO = 400mW, Mode 2
0.05
%
HP output, f = 1kHz, RL = 32Ω SE
PO = 12mW, Mode 8
0.02
%
Shutdown Current
Total Harmonic Distortion + Noise
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
Datasheet min/max specification limits are ensured by test or statistical analysis.
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SNAS459A – MAY 2009 – REVISED APRIL 2013
Electrical Characteristics VDD = 5.0V(1)(2) (continued)
The following specifications apply for VDD = 5.0V, TA = 25°C, all volume controls set to 0dB, unless otherwise specified.
LS = Loudspeaker, HP = Headphone.
Parameter
SNR
LM49200
Test Conditions
Signal-to-Noise Ratio
Typ (3)
Limits (4)
Units
(Limits)
LS output, f = 1kHz,
VREF = VOUT (1%THD+N)
Gain = 0dB, A-weighted
LIN & RIN AC terminated
109
dB
HP output, f = 1kHz,
VREF = VOUT (1%THD+N)
Gain = 0dB, A-weighted
LIN & RIN AC terminated
101
dB
A-weighted, Inputs terminated to AC GND, Output Referred
εOUT
Output Noise
Right LS only, Mode 1
8
µV
LS: Mode 1
8
µV
LS: Mode 2
11
µV
LS: Mode 3
14
µV
HP: Mode 4
8
µV
HP: Mode 8
9
µV
HP: Mode 12
11
µV
LS: Mode 1, RL = 8Ω BTL
90
dB
LS: Mode 2, RL = 8Ω BTL
70
dB
HP: Mode 4, RL = 32Ω SE
87
dB
HP: Mode 8, RL = 32Ω SE
77
dB
f = 217Hz, VCM = 1VP-P
LS: RL = 8Ω BTL, Mode 1
HP: RL = 32Ω SE, Mode 4
60
66
dB
dB
LS: PO = 1W, f = 1kHz, Mode 2
80
dB
HP: PO = 12mW, f = 1kHz, Mode 8
70
dB
Maximum Gain setting
12.5
kΩ
Maximum Attenuation setting
110
kΩ
Maximum Gain
Maximum Attenuation
18
–80
dB
dB
0.2
dB
CB = 2.2μF, HP, Normal Turn-On Mode
29
ms
CB = 2.2μF, HP, Fast Turn-On Mode
16
ms
VRIPPLE = 200mVP-P, fRIPPLE = 217Hz, CB = 2.2μF
All inputs AC terminated to GND, output referred
PSRR
Power Supply Rejection Ratio
CMRR
Common-Mode Rejection Ratio
XTALK
Crosstalk
ZIN
MIN, LIN, and RIN Input Impedance
VOL
Digital Volume Control Range
VOL
Volume Control Step Size Error
TWU
Wake-Up Time from Shutdown
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I2C Interface (1) (2)
The following specifications apply for VDD = 5.0V and 3.3V, 2.2V ≤ I2C_VDD ≤ 5.5V, TA = 25°C, unless otherwise specified.
Units
(Limits)
I2C Clock Period
2.5
µs (min)
t2
I C Data Setup Time
100
ns (min)
t3
I2C Data Stable Time
0
ns (min)
t4
Start Condition Time
100
ns (min)
t5
Stop Condition Time
100
ns (min)
t6
I2C Data Hold Time
100
ns (min)
t1
(1)
(2)
(3)
(4)
(5)
LM49200
Limits (4) (5)
Parameter
Test Conditions
Typ
(3)
2
VIH
2
I C Input Voltage High
2
0.7xI CVDD
V (min)
VIL
I2C Input Voltage Low
0.3xI2CVDD
V (max)
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Human body model, applicable std. JESD22-A114C.
Datasheet min/max specification limits are ensured by test or statistical analysis.
Refer to the I2C timing diagram, Figure 32.
I2C Interface (1) (2)
The following specifications apply for VDD = 5.0V and 3.3V, 1.7V ≤ I2C_VDD ≤ 2.2V, TA = 25°C, unless otherwise specified.
Parameter
(2)
(3)
(4)
(5)
8
Typ
(3)
Limits (4)
(5)
Units
(Limits)
I2C Clock Period
2.5
µs (min)
t2
I C Data Setup Time
250
ns (min)
t3
I2C Data Stable Time
0
ns (min)
t4
Start Condition Time
250
ns (min)
t5
Stop Condition Time
250
ns (min)
t6
I2C Data Hold Time
250
ns (min)
t1
(1)
LM49200
Test Conditions
2
VIH
2
I C Input Voltage High
2
0.7xI CVDD
V (min)
VIL
I2C Input Voltage Low
0.3xI2CVDD
V (max)
“Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions. All
voltages are measured with respect to the ground pin, unless otherwise specified
The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
Typical values represent most likely parametric norms at TA = +25°C, and at the Recommended Operation Conditions at the time of
product characterization and are not ensured.
Datasheet min/max specification limits are ensured by test or statistical analysis.
Refer to the I2C timing diagram, Figure 32.
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Typical Performance Characteristics
For all performance graphs, the Output Gains are set to 0dB, unless otherwise noted.
THD+N vs Frequency
VDD = 3.3V, RL = 8Ω, PO = 250mW
Mode 1, 80kHz BW
10
10
5
5
2
2
1
1
0.5
THD+N (%)
THD+N (%)
THD+N vs Frequency
VDD = 3.3V, RL = 8Ω, PO = 250mW
Mode 2, 80kHz BW
0.5
0.2
0.2
0.1
0.05
0.02
0.1
0.01
0.05
0.005
0.02
0.002
0.01
20
100
500 1k
5k
0.001
20
20k
100
20k
Figure 4.
THD+N vs Frequency
VDD = 3.3V, RL = 32Ω, PO = 12mW/Ch
Mode 4, 80kHz BW
THD+N vs Frequency
VDD = 3.3V, RL = 32Ω, PO = 12mW/Ch
Mode 8, 80kHz BW
10
10
5
5
2
2
1
1
THD+N (%)
THD+N (%)
5k
Figure 3.
0.5
0.2
0.1
0.5
0.2
0.1
0.05
0.05
0.02
0.02
0.01
20
100
500 1k
5k
0.01
20
20k
100
10
5k
20k
Figure 5.
Figure 6.
THD+N vs Frequency
VDD = 5V, RL = 8Ω, PO = 600mW
Mode 1, 80kHz BW
THD+N vs Frequency
VDD = 5V, RL = 8Ω, PO = 600mW
Mode 2, 80kHz BW
10
5
2
1
2
1
0.5
0.5
THD+N (%)
5
0.2
0.1
0.05
0.02
0.2
0.1
0.05
0.02
0.01
0.01
0.005
0.005
0.002
0.002
0.001
20
500 1k
FREQUENCY (Hz)
FREQUENCY (Hz)
THD+N (%)
500 1k
FREQUENCY (Hz)
FREQUENCY (Hz)
100
500 1k
5k
20k
0.001
20
FREQUENCY (Hz)
Figure 7.
100
500 1k
5k
20k
FREQUENCY (Hz)
Figure 8.
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Typical Performance Characteristics (continued)
For all performance graphs, the Output Gains are set to 0dB, unless otherwise noted.
THD+N vs Frequency
VDD = 5V, RL = 32Ω, PO = 12mW/Ch
Mode 8, 80kHz BW
10
10
5
5
2
2
1
1
THD+N (%)
THD+N (%)
THD+N vs Frequency
VDD = 5V, RL = 32Ω, PO = 12mW/Ch
Mode 4, 80kHz BW
0.5
0.2
0.1
0.5
0.2
0.1
0.05
0.05
0.02
0.02
0.01
20
100
500 1k
5k
0.01
20
20k
FREQUENCY (Hz)
5k
20k
Figure 10.
THD+N vs Output Power
VDD = 3.3V & 5V, RL = 8Ω BTL, f = 1kHz
Mode 1, 80kHz BW
THD+N vs Output Power
VDD = 3.3V & 5V, RL = 8Ω BTL, f = 1kHz
Mode 2, 80kHz BW
10
10
5
5
2
2
3.3V
0.5
5.0V
0.2
0.1
0.5
0.2
0.05
0.02
0.02
10m
100m
1
5V
0.1
0.05
0.01
1m
3.3V
1
THD+N (%)
THD+N (%)
500 1k
FREQUENCY (Hz)
Figure 9.
1
0.01
1m
2
OUTPUT POWER (W)
10m
100m
1
2
OUTPUT POWER (W)
Figure 11.
Figure 12.
THD+N vs Output Power
VDD = 3.3V & 5V, RL = 32Ω, f = 1kHz
Mode 4, 80kHz BW
THD+N vs Output Power
VDD = 3.3V & 5V, RL = 8Ω, f = 1kHz
Mode 5, 80kHz BW
10
10
5
5
2
1
2
0.5
1
3.3V
0.2
0.1
THD+N (%)
THD+N (%)
100
5V
0.05
0.02
0.01
3.3V
5V
0.5
0.2
0.1
0.05
0.005
0.002
0.001
1m
0.02
2m
5m
10m
20m
50m 100m
0.01
1m
OUTPUT POWER (W)
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100m
1
2
OUTPUT POWER (W)
Figure 13.
10
10m
Figure 14.
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Typical Performance Characteristics (continued)
For all performance graphs, the Output Gains are set to 0dB, unless otherwise noted.
THD+N vs Output Power
VDD = 3.3V & 5V, RL = 8Ω BTL, f = 1kHz
Mode 10, 80kHz BW
10
10
5
5
2
1
2
0.5
1
3.3V
3.3V
0.2
0.1
THD+N (%)
THD+N (%)
THD+N vs Output Power
VDD = 3.3V & 5V, RL = 32Ω, f = 1kHz
Mode 8, 80kHz BW
5V
0.05
5V
0.5
0.2
0.02
0.1
0.01
0.05
0.005
0.002
0.001
1m
0.02
2m
5m
10m
20m
0.01
1m
50m 100m
10m
2
OUTPUT POWER (W)
Figure 16.
PSRR vs Frequency
VDD = 3.3V, VRIPPLE = 200mVP-P, RL = 8Ω
Mode 1, 80kHz BW
PSRR vs Frequency
VDD = 3.3V, VRIPPLE = 200mVP-P, RL = 8Ω
Mode 2, 80kHz BW
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
20
50 100 200 500 1k 2k
5k 10k 20k
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
20
50 100 200 500 1k 2k
FREQUENCY (Hz)
5k 10k 20k
FREQUENCY (Hz)
Figure 17.
Figure 18.
PSRR vs Frequency
VDD = 3.3V, VRIPPLE = 200mVP-P, RL =32Ω
Mode 4, 80kHz BW
PSRR vs Frequency
VDD = 3.3V, VRIPPLE = 200mVP-P, RL = 32Ω
Mode 8, 80kHz BW
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
20
50 100 200 500 1k 2k
5k 10k 20k
POWER SUPPLY REJECTION RATIO (dB)
POWER SUPPLY REJECTION RATIO (dB)
1
100m
Figure 15.
POWER SUPPLY REJECTION RATIO (dB)
POWER SUPPLY REJECTION RATIO (dB)
OUTPUT POWER (W)
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
20
50 100 200 500 1k 2k
FREQUENCY (Hz)
Figure 19.
5k 10k 20k
FREQUENCY (Hz)
Figure 20.
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Typical Performance Characteristics (continued)
For all performance graphs, the Output Gains are set to 0dB, unless otherwise noted.
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
20
50 100 200 500 1k 2k
5k 10k 20k
PSRR vs Frequency
VDD = 5V, VRIPPLE = 200mVP-P, RL = 32Ω
Mode 4, 80kHz BW
POWER SUPPLY REJECTION RATIO (dB)
POWER SUPPLY REJECTION RATIO (dB)
PSRR vs Frequency
VDD = 5V, VRIPPLE = 200mVP-P, RL = 8Ω
Mode 1, 80kHz BW
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
20
50 100 200 500 1k 2k
5k 10k 20k
FREQUENCY (Hz)
Figure 21.
Figure 22.
PSRR vs Frequency
VDD = 5V, VRIPPLE = 200mVP-P, RL = 32Ω
Mode 8, 80kHz BW
Power Dissipation vs Output Power
VDD = 3.3V & 5V, RL = 8Ω BTL
Mode 3, 80kHz BW
0
3000
-10
POWER DISSIPATION (mW)
POWER SUPPLY REJECTION RATIO (dB)
FREQUENCY (Hz)
-20
-30
-40
-50
-60
-70
-80
2500
2000
5V
1500
1000
500
3.3V
-90
-100
20
50 100 200 500 1k 2k
0
0
5k 10k 20k
200 400
FREQUENCY (Hz)
800 1000 1200 1400
OUTPUT POWER (mW)
Figure 23.
Figure 24.
Power Dissipation vs Output Power
VDD = 3.3V & 5V, RL = 32Ω SE
Mode 12, 80kHz BW
Crosstalk vs Frequency
VDD = 5.0V, VIN = 1VP-P, RL = 8Ω
Mode 2, 80kHz BW
0
350
-10
300
CHANNEL SEPERATION (dB)
POWER DISSIPATION (mW)
600
250
200
3.3V
150
100
5V
50
-20
-30
-40
-50
-60
-70
-80
-90
0
0
5
10
15
20
25
30
35 40
-100
20
50 100 200 500 1k 2k
OUTPUT POWER (mW)
FREQUENCY (Hz)
Figure 25.
12
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5k 10k 20k
Figure 26.
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Typical Performance Characteristics (continued)
For all performance graphs, the Output Gains are set to 0dB, unless otherwise noted.
Crosstalk vs Frequency
VDD = 5.0V, VIN = 1VP-P, RL = 32Ω
Mode 8, 80kHz BW
Supply Current vs Supply Voltage
No Load, Mode 3
(2 plots, output gain amps on/off)
0
6
POWER SUPPLY CURRENT (mA)
CHANNEL SEPERATION (dB)
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
20
5
4
EP_MODE = 0
3
1
0
50 100 200 500 1k 2k
EP_MODE = 1
2
5k 10k 20k
0
1
3
4
5
Figure 27.
Figure 28.
Supply Current vs Supply Voltage
No Load, Mode 12
(2 plots, output gain amps on/off)
Output Power vs Supply Voltage
f = 1kHz, RL = 8Ω BTL
Mode 2, 80kHz BW
2000
6
6
5
OUTPUT POWER (mW)
POWER SUPPLY CURRENT (mA)
2
POWER SUPPLY VOLTAGE (V)
FREQUENCY (Hz)
4
EP_MODE = 0
3
EP_MODE = 1
2
1500
THD+N = 10%
THD+N = 1%
1000
500
1
0
0
1
2
3
5
4
0
6
1
0
POWER SUPPLY VOLTAGE (V)
2
3
4
5
6
POWER SUPPLY VOLTAGE (V)
Figure 29.
Figure 30.
Output Power vs Supply Voltage
f = 1kHz, RL = 32Ω SE
Mode 8, 80kHz BW
OUTPUT POWER (mW)
60
50
THD+N = 10%
40
THD+N = 1%
30
20
10
0
0
1
2
3
4
5
6
POWER SUPPLY VOLTAGE (V)
Figure 31.
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APPLICATION INFORMATION
I2C COMPATIBLE INTERFACE
The LM49200 is controlled through an I2C compatible serial interface that consists of a serial data line (SDA) and
a serial clock (SCL). The clock line is uni-directional. The data line is bi-directional (open drain). The LM49200
and the master can communicate at clock rates up to 400kHz. Figure 32 shows the I2C interface timing diagram.
Data on the SDA line must be stable during the HIGH period of SCL. The LM49200 is a transmit/receive slaveonly device, reliant upon the master to generate the SCL signal. Each transmission sequence is framed by a
START condition and a STOP condition (Figure 33). Each data word, device address and data, transmitted over
the bus is 8 bits long and is always followed by an acknowledge pulse (Figure 34). The LM49200 device address
is 11111000.
I2C INTERFACE POWER SUPPLY PIN (I2CVDD)
The LM49200's I2C interface is powered up through the I2CVDD pin. The LM49200's I2C interface operates at a
voltage level set by the I2CVDD pin which can be set independent to that of the main power supply pin VDD. This
is ideal whenever logic levels for the I2C interface are dictated by a microcontroller or microprocessor that is
operating at a lower supply voltage than the main battery of a portable system
I2C BUS FORMAT
The I2C bus format is shown in Figure 34. The START signal, the transition of SDA from HIGH to LOW while
SCL is HIGH, is generated, alerting all devices on the bus that a device address is being written to the bus.
The 7-bit device address is written to the bus, most significant bit (MSB) first, followed by the R/W bit. R/W = 0
indicates the master is writing to the slave device, R/W = 1 indicates the master wants to read data from the
slave device. Set R/W = 0; the LM49200 is a WRITE-ONLY device and will not respond to the R/W = 1. The data
is latched in on the rising edge of the clock. Each address bit must be stable while SCL is HIGH. After the last
address bit is transmitted, the master device releases SDA, during which time, an acknowledge clock pulse is
generated by the slave device. If the LM49200 receives the correct address, the device pulls the SDA line low,
generating an acknowledge bit (ACK).
Once the master device registers the ACK bit, the 8-bit register data word is sent. Each data bit should be stable
while SCL is HIGH. After the 8-bit register data word is sent, the LM49200 sends another ACK bit. Following the
acknowledgement of the register data word, the master issues a STOP bit, allowing SDA to go high while SCL is
high.
Figure 32. I2C Timing Diagram
SDA
SCL
S
P
START condition
STOP condition
Figure 33. Start and Stop Diagram
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SCL
SDA
START
MSB
DEVICE ADDRESS
R/W
LSB
ACK
MSB
REGISTER DATA
LSB
ACK
STOP
Figure 34. Start and Stop Diagram
Table 1. Chip Address
A7
A6
A5
A4
A3
A2
A1
A0
1
1
1
1
1
0
0
0
Chip Address
Table 2. Control Registers (1)
Register
D7
D6
D5
D4
D3
D2
D1
D0
I2CVDD_SD (3)
Turn_On
_Time (4)
Power_On (5)
Shutdown Control
0
0
0
HPR_SD (2)
Output Mode Control
0
1
0
EP_Mode (6)
Headphone Output
Gain Control
1
0
0
0
Mono Input Volume
Control
1
0
1
Mono_Vol (9)
Left Input Volume
Control
1
1
0
Left_Vol (9)
Right Input Volume
Control
1
1
1
Right_Vol (9)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
0
Mode_Control (7)
HP_Gain (8)
0
Notes: All registers default to 0 on initial power-up.
HPR_SD: Right channel shutdown control. See Table 3.
I2CVDD_SD: Control Enable Function. I2CVDD can be used to act as a hardware reset input. See Table 3.
Turn_On_Time: Reduces the turn on time for faster activation. See Table 3.
Power_On: Master Power on bit. See Table 3.
EP_Mode: EP (Receiver) Mode control. Right loudspeaker channel can be used as earpiece path. See Table 4.
Mode_Control: Sets the output mode. See Table 4.
HP_Gain: Sets the headphone amplifier output gain. See Table 5
Mono_Vol/Left_Vol/Right_Vol: Sets the input volume for Mono, Left and Right inputs. See Table 6.
Table 3. Shutdown Control Register
Bit
Name
Value
Description
This bit is a master shutdown control bit and sets the device to be on or off.
0
Value
Power_On
Status
0
Master power off, device disable.
1
Master power on, device enable.
This bit sets the turn on time of the device.
1
Value
Turn_On_Time
Status
0
Normal Turn-on time
1
Fast Turn-on time
This bit allows the I2C supply voltage to be used as a reset signal.
Value
2
I CVDD_SD
Status
0
I2CVDD acts as an active low reset input. If I2CVDD drops below 1.1V,
the device resets and the I2C registers are restored to their default
state.
1
Normal Operation. I2CVDD voltage does not reset the device.
2
This bit is used when only one channel of the headphone amplifier is needed.
4
HPR_SD
0
Normal headphone operation.
1
Mono headphone output at left channel, right headphone in shutdown.
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Table 4. Output Mode Control Register (1)
Bits
Field
3:0
Mode_Control
Description
These bits determine how the input signals are mixed and routed to the outputs.
Value
4
EP Mode
Mode
Left Loudspeaker
Left Headphone
Right Headphone
0000
0
SD
SD
SD
SD
0001
1
GM x M
GM x M
Mute
Mute
0010
2
GL x L
GL x L
Mute
Mute
011
3
GL x L + GM x M
GR x R + GM x M
Mute
Mute
0100
4
SD
SD
GM x M/2
GM x M/2
0101
5
GM x M
GM x M
GM x M/2
GM x M/2
0110
6
GL x L
GR x R
GM x M/2
GM x M/2
0111
7
GL x L + GM x M
GL x L + GM x M
GM x M/2
GM x M/2
1000
8
SD
SD
GL x L
GR x R
1001
9
GM x M
GM x M
GL x L
GR x R
1010
10
GL x L
GR x R
GL x L
GR x R
1011
11
GL x L + GM x M
GR x R + GM x M
GL x L
GR x R
1100
12
SD
SD
GL x L + GM x M/2
GR x R + GM x M/2
1101
13
GM x M
GM x M
GL x L + GM x M/2
GR x R + GM x M/2
1110
14
GL x L
GR x R
GL x L + GM x M/2
GR x R + GM x M/2
1111
15
GL x L + GM x M
GR x R + GM x M
GL x L + GM x M/2
GR x R + GM x M/2
This bit sets the loudspeaker amplifiers for earpiece mode.
Value
(1)
Right
Loudspeaker
Status
0
Normal loudspeaker operation, control determined by bits 3:0.
1
Bit overrides bits 3:0. Right loudspeaker amplifier bias current reduced for low power operation. Left
loudspeaker amplifier shutdown. Mono input path active and signal routed to right loudspeaker
output. Left & right input gain amplifiers shutdown for reduced power consumption.
M : MIN, Mono differential input
L : LIN, Left single-ended input
R : RIN, Right single-ended input
SD : Shutdown
GM : Mono_Vol setting determined by the Mono Input Volume Control register, See Table 6.
GL : Left_Vol setting determined by the Left Input Volume Control register, See Table 6.
GR : Right_Vol setting determined by the Right Input Volume Control register, See Table 6.
Table 5. Output Gain Control Register
16
Bits
Field
2:0
HP_GAIN
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Description
These bits set the gain of the headphone output amplifiers.
Value
Gain (dB)
000
0
001
–1.2
010
–2.5
011
–4.0
100
–6.0
101
–8.5
110
–12
111
–18
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Table 6. Input Volume Control Registers
Bits
Fields
4:0
Mono_Vol
Right_Vol
Left_Vol
Description
These bits set the input volume for each input volume register listed.
Volume Step
Value
Gain (dB)
1
00000
–80.0
2
00001
–46.5
3
00010
–40.5
4
00011
–34.5
5
00100
–30.0
6
00101
–27.0
7
00110
–24.0
8
00111
–21.0
9
01000
–18.0
10
01001
–15.0
11
01010
–13.5
12
01011
–12.0
13
01100
–10.5
14
01101
–9.0
15
01110
–7.5
16
01111
–6.0
17
10000
–4.5
18
10001
–3.0
19
10010
–1.5
20
10011
0.0
21
10100
1.5
22
10101
3.0
23
10110
4.5
24
10111
6.0
25
11000
7.5
26
11001
9.0
27
11010
10.5
28
11011
12.0
29
11100
13.5
30
11101
15.0
31
11110
16.5
32
11111
18.0
TURN_ON_TIME BIT
The Turn_On_Time bit determines the delay time from the Power_On bit set to '1' and the internal circuits ready.
For input capacitor values up to 0.47μF the Turn_On_Time bit can be set to fast mode by setting the bit to a '1'.
When the input capacitor values are larger than 0.47μF then the Turn_On_Time bit should be set to '0' for normal
turn-on time and higher delay. This allows sufficient time to charge the input capacitors to the ½ VDDLS bias
voltage.
POWER_ON BIT
The Power_On bit is the master control bit to activate or deactivate the LM49200. All registers can be loaded
independent of the Power_On bit setting as long as the IC is powered correctly. Cycling the Power_On bit does
not change the values of any registers nor return all bits to the default power on value of zero. The Power_On bit
only determines whether the IC is on or off.
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HPR_SD BIT
The HPR_SD bit will deactivate the right headphone output amplifier. This bit is provided to reduce power
consumption when only one headphone output is needed.
MODE_CONTROL BITS
In the LM49200 OUTPUT MODE CONTROL register (Table 4), Bit B5 (EP Bypass) controls the operation of the
Earpiece Bypass path. If EP Bypass = 0, it would act under normal output mode operation set by bits B3, B2, B1,
and B0. If EP Bypass = 1, it overrides the B3, B2, B1, and B0 Bits and enables the Receiver Bypass path, a
class AB amplifier, to the speaker output.
Bit B4 (HPR_SD) of the OUPUT MODE CONTROL register controls the right headphone shutdown. If HPR_SD
= 1, the right headphone output is disabled.
The LM49200 includes a comprehensive mixer multiplexer controlled through the I2C interface. The
mixer/multiplexer allows any input combination to appear on any output of LM49200. Multiple input paths can be
selected simultaneously. Under these conditions, the selected inputs are mixed together and output on the
selected channel. Table 5 shows how the input signals are mixed together for each possible input selection.
HP_GAIN BITS
The headphone outputs have an additional, single volume control set by the three HP_Gain bits in the Output
Gain Control register. The HP_Gain volume setting controls the output level for both the left and the right
headphone outputs.
LS (EP_MODE) BIT
The LS (EP_Mode) bit selects the amount of bias current in the loudspeaker amplifier. Setting the LS (EP_Mode)
bit to a '1' will reduce the amount of current from the VDDLS supply by approximately 0.5mA. The THD
performance of the loudspeaker amplifier will be reduced as a result of lower bias current. See the performance
graphs in Typical Performance Characteristics above.
VOLUME CONTROL BITS
The LM49200 has three independent 32-step volume controls, one for each of the inputs. The five bits of the
Volume Control registers sets the volume for the specified input channel.
SHUTDOWN FUNCTION
The LM49200 features the following shutdown controls.
Bit B4 (GAMP_SD) of the SHUTDOWN CONTROL register controls the gain amplifiers. When GAMP_SD = 1, it
disables the gain amplifiers that are not in use. For example, in Modes 1, 4 and 5, the Mono inputs are in use, so
the Left and Right input gain amplifiers are disabled, causing the IDD to be minimized.
Bit B0 (PWR_On) of the SHUTDOWN CONTROL register is the global shutdown control for the entire device.
Set PWR_On = 0 for normal operation. PWR_On = 1 overrides any other shutdown control bit.
DIFFERENTIAL AMPLIFIER EXPLANATION
The LM49200 features a differential input stage, which offers improved noise rejection compared to a singleended input amplifier. Because a differential input amplifier amplifies the difference between the two input
signals, any component common to both signals is cancelled. An additional benefit of the differential input
structure is the possible elimination of the DC input blocking capacitors. Since the DC component is common to
both inputs, and thus cancelled by the amplifier, the LM49200 can be used without input coupling capacitors
when configured with a differential input signal.
BRIDGE CONFIGURATION EXPLAINED
By driving the load differentially through the MONO outputs, an amplifier configuration commonly referred to as
“bridged mode” is established. Bridged mode operation is different from the classical single-ended amplifier
configuration where one side of the load is connected to ground.
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A bridge amplifier design has a few distinct advantages over the single-ended configuration, as it provides
differential drive to the load, thus doubling output swing for a specified supply voltage. Four times the output
power is possible as compared to a single-ended amplifier under the same conditions. This increase in attainable
output power assumes that the amplifier is not current limited or clipped.
A bridge configuration, such as the one used in LM49200, also creates a second advantage over single-ended
amplifiers. Since the differential outputs are biased at half-supply, no net DC voltage exists across the load. This
eliminates the need for an output coupling capacitor which is required in a single supply, single-ended amplifier
configuration. Without an output coupling capacitor, the half-supply bias across the load would result in both
increased internal IC power dissipation and also possible loudspeaker damage.
POWER DISSIPATION
Power dissipation is a major concern when designing a successful amplifier, whether the amplifier is bridged or
single-ended. A direct consequence of the increased power delivered to the load by a bridge amplifier is an
increase in internal power dissipation. The power dissipation of the LM49200 varies with the mode selected. The
maximum power dissipation occurs in modes where all inputs and outputs are active (Modes 6, 7, 8, 9, 10, 11,
13, 14, 15). The power dissipation is dominated by the Class AB amplifier. The maximum power dissipation for a
given application can be derived from the power dissipation graphs or from Equation 1.
PDMAX = 4*(VDD)2 / (2π2RL)
(1)
It is critical that the maximum junction temperature (TJMAX) of 150°C is not exceeded. TJMAX can be determined
from the power derating curves by using PDMAX and the PC board foil area. By adding additional copper foil, the
thermal resistance of the application can be reduced from the free air value, resulting in higher PDMAX. Additional
copper foil can be added to any of the leads connected to the LM49200. It is especially effective when connected
to VDD, GND, and the output pins. Refer to the application information on the LM49200 reference design board
for an example of good heat sinking. If TJMAX still exceeds 150°C, then additional changes must be made. These
changes can include reduced supply voltage, higher load impedance, or reduced ambient temperature. Internal
power dissipation is a function of output power. Refer to the curves in Typical Performance Characteristics for
power dissipation information for different output powers and output loading.
POWER SUPPLY BYPASSING
As with any amplifier, proper supply bypassing is critical for low noise performance and high power supply
rejection. The capacitor location on both the bypass and power supply pins should be as close to the device as
possible. Typical applications employ a 5V regulator with 10µF tantalum or electrolytic capacitor and a ceramic
bypass capacitor which aid in supply stability. This does not eliminate the need for bypassing the supply nodes of
the LM49200. The selection of a bypass capacitor, especially CB, is dependent upon PSRR requirements, click
and pop performance, system cost, and size constraints.
GROUND REFERENCED HEADPHONE AMPLIFIER
The LM49200 features a low noise inverting charge pump that generates an internal negative supply voltage.
This allows the headphone outputs to be biased about GND instead of a nominal DC voltage, like traditional
headphone amplifiers. Because there is no DC component, the large DC blocking capacitors (typically 220μF)
are not necessary. The coupling capacitors are replaced by two small ceramic charge pump capacitors, saving
board space and cost. Eliminating the output coupling capacitors also improves low frequency response. In
traditional headphone amplifiers, the headphone impedance and the output capacitor from a high-pass filter that
not only blocks the DC component of the output, but also attenuates low frequencies, impacting the bass
response. Because the LM49200 does not require the output coupling capacitors, the low frequency response of
the device is not degraded by external components. In addition to eliminating the output coupling capacitors, the
ground referenced output nearly doubles the available dynamic range of the LM49200 headphone amplifiers
when compared to a traditional headphone amplifier operating from the same supply voltage.
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Product Folder Links: LM49200 LM49200TLEVAL
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LM49200, LM49200TLEVAL
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INPUT CAPACITOR SELECTION
Input capacitors may be required for some applications, or when the audio source is single-ended. Input
capacitors block the DC component of the audio signal, eliminating any conflict between the DC component of
the audio source and the bias voltage of the LM49200. The input capacitors create a high-pass filter with the
input resistors RIN. The -3dB point of the high-pass filter is found using equation below.
f = 1 / 2πRINCIN
(Hz)
where
•
the value of RIN is given in the Electrical Characteristics Table.
(2)
High-pass filtering the audio signal helps protect the speakers. When the LM49200 is using a single-ended
source, power supply noise on the ground is seen as an input signal. Setting the high-pass filter point above the
power supply noise frequencies, 217Hz in a GSM phone, for example, filters out the noise such that it is not
amplified and heard on the output. Capacitors with a tolerance of 10% or better are recommended for impedance
matching and improved CMRR and PSRR.
CHARGE PUMP FLYING CAPACITOR (C1)
The flying capacitor (C1), see Figure 1, affects the load regulation and output impedance of the charge pump. A
C1 value that is too low results in a loss of current drive, leading to a loss of amplifier headroom. A higher valued
C1 improves load regulation and lowers charge pump output impedance to an extent. Above 2.2μF, the RDS(ON)
of the charge pump switches and the ESR of C1 and Cs5 dominate the output impedance. A lower value
capacitor can be used in systems with low maximum output power requirements.
CHARGE PUMP HOLD CAPACITOR (CS3)
The value and ESR of the hold capacitor (Cs5) directly affects the ripple on CPVSS. Increasing the value of Cs5
reduces output ripple. Decreasing the ESR of Cs5 reduces both output ripple and charge pump output
impedance. A lower value capacitor can be used in systems with low maximum output power requirements.
20
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LM49200, LM49200TLEVAL
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SNAS459A – MAY 2009 – REVISED APRIL 2013
Demo Board Circuit
Figure 35. Demo Board Circuit
Demonstration Board
The demonstration board (see Figure 35) has connection and jumper options to be powered from the USB bus,
from external power supplies or a combination of both. Additional options are to power I2CVDD and VDD from a
single power supply or separate power supplies, as long as the voltage limits for each power supply are not
exceeded. See the Operating Ratings for each supply's limit range. When powered from the USB bus the I2CVDD
will be set to 3.3V and the VDD will be set to 5V. Jumper headers J13 and J12 must be set accordingly. If a single
power supply for I2CVDD and VDD is desired then header J5 should be used with a jumper added to header J11 to
connect I2CVDD to the external supply voltage connected to J5.
Connection headers J1 and J2 are provided along with the stereo headphone jack J4 for easily connection and
monitoring of the headphone outputs.
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LM49200, LM49200TLEVAL
SNAS459A – MAY 2009 – REVISED APRIL 2013
www.ti.com
LM49200 microSMD Demo Board Views
22
Figure 36. Composite View
Figure 37. Silk Screen
Figure 38. Top Layer
Figure 39. Internal Layer 1
Figure 40. Internal Layer 2
Figure 41. Bottom Layer
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SNAS459A – MAY 2009 – REVISED APRIL 2013
LM49200 Reference Demo Board Bill Of Materials
Table 7. Bill Of Materials
Designator
Vlaue
Tolerance
Part Description
R1, R2
5.1kΩ
5%
1/10W, 0603 Resistors
CIN1, CIN2
CIN3, CIN4
1μF
10%
1206, X7R Ceramic Capacitor
CS1, CB
2.2μF
10%
Size A, Tantalum Capacitor
CS2
0.1μF
10%
0805, 16V, X7R Ceramic Capacitor
CS3, C1
2.2μF
10%
0603, 10V, X7R Ceramic Capacitor
Comment
U2
LM49200TL
J1, J2, J3
J4, J5, J8
J9, J10
0.100" 1x2 header, vertical mount
Input, Output, VDD, GND
J11, J12, J13
0.100" 1x3 header, vertical mount
VDD Selects, VDD, I2CVDD, GND
J6
16 pin header
I2C Connector
U1
Headphone Jack
PCB Layout Guidelines
This section provides practical guidelines for mixed signal PCB layout that involves various digital/analog power
and ground traces. Designers should note that these are only "rule-of-thumb" recommendations and the actual
results will depend heavily on the final layout.
General Mixed Signal Layout Recommendations
SINGLE-POINT POWER AND GROUND CONNECTIONS
The analog power traces should be connected to the digital traces through a single point (link). A "Pi-filter" can
be helpful in minimizing high frequency noise coupling between the analog and digital sections. It is further
recommended to put digital and analog power traces over the corresponding digital and analog ground traces to
minimize noise coupling.
PLACEMENT OF DIGITAL AND ANALOG COMPONENTS
All digital components and high-speed digital signals traces should be located as far away as possible from
analog components and circuit traces.
AVOIDING TYPICAL DESIGN AND LAYOUT PROBLEMS
Avoid ground loops or running digital and analog traces parallel to each other (side-by-side) on the same PCB
layer. When traces must cross over each other do it at 90 degrees. Running digital and analog traces at 90
degrees to each other from the top to the bottom side as much as possible will minimize capacitive noise
coupling and cross talk.
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LM49200 LM49200TLEVAL
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LM49200, LM49200TLEVAL
SNAS459A – MAY 2009 – REVISED APRIL 2013
www.ti.com
REVISION HISTORY
24
Rev
Date
1.0
05/21/09
A
04/08/2013
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Description
Initial release.
Changed layout of National Data Sheet to TI format.
Copyright © 2009–2013, Texas Instruments Incorporated
Product Folder Links: LM49200 LM49200TLEVAL
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LM49200TL/NOPB
ACTIVE
DSBGA
YZR
20
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
GL3
LM49200TLX/NOPB
ACTIVE
DSBGA
YZR
20
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
-40 to 85
GL3
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
LM49200TL/NOPB
DSBGA
YZR
20
250
178.0
8.4
LM49200TLX/NOPB
DSBGA
YZR
20
3000
178.0
8.4
Pack Materials-Page 1
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
2.18
2.69
0.76
4.0
8.0
Q1
2.18
2.69
0.76
4.0
8.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM49200TL/NOPB
DSBGA
YZR
LM49200TLX/NOPB
DSBGA
YZR
20
250
210.0
185.0
35.0
20
3000
210.0
185.0
35.0
Pack Materials-Page 2
MECHANICAL DATA
YZR0020xxx
0.600±0.075
D
E
TLA20XXX (Rev D)
D: Max = 2.537 mm, Min =2.476 mm
E: Max = 2.051 mm, Min =1.991 mm
4215053/A
NOTES:
A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.
B. This drawing is subject to change without notice.
www.ti.com
12/12
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