On-Chip Peripherals
Chapter 6
On-Chip Peripherals
6-1
The Basic Timer
6.1 The Basic Timer
The basic timer is normally used as a time base; it is programmed to interrupt
the background program at regular time intervals. Table 6–1 shows all possible
basic timer interrupt frequencies that can be set by the control bits in byte
BTCTL (address 040h). The values shown are for MCLK = 1.048 MHz.
Table 6–1. Basic Timer Interrupt Frequencies
SSEL=0
SSEL=1
IP2
IP1
IP0
0
0
0
16348 HZ
64 Hz
[524288 Hz]
64 HZ
0
0
1
8192 HZ
32 Hz
[262144 Hz]
32 HZ
0
1
0
4096 HZ
16 Hz
[131072 Hz]
16 HZ
0
1
1
2048 HZ
8 Hz
65536 Hz
8 HZ
1
0
0
1024 HZ
4 Hz
32768 Hz
4 HZ
1
0
1
512 HZ
2 Hz
16348 Hz
2 HZ
1
1
0
256 HZ
1 Hz
8192 Hz
1 HZ
1
1
128 HZ
0.5 Hz
4096 Hz
0.5 HZ
1
Note:
DIV=0
DIV=1
DIV=0
Interrupt frequencies shown in [brackets] exceed the maximum allowable frequency and
cannot be used.
Example 6–1. Basic Timer Control
;
; DEFINITION PART FOR THE BASIC TIMER
;
BTCNT2
.EQU
047h
; Basic Timer Counter2 (0.5s)
BTCTL
.EQU
040h
; BASIC TIMER CONTROL BYTE:
SSEL
.EQU
080h
; 0: ACLK
1: MCLK
RESET
.EQU
040h
; 0: RUN
1: RESET BT
DIV
.EQU
020h
; 0: fBT1=fBT
1: fBT1=128Hz
FRFQ
.EQU
008h
; LCD FREQUENCY DIVIDER
IP
.EQU
001h
; BT FREQUENCY Selection bits
IE2
.EQU
001h
; INTERRUPT ENABLE BYTE 2:
BTIE
.EQU
080h
; BT INTERRUPT ENABLE BIT
.BSS
TIMER,4
; 0.5s COUNTER
.BSS
BTDTOL,1
; LAST READ BT VALUE
;
;
;
6-2
DIV=1
The Basic Timer
; INITIALIZATION FOR 1 SECOND TIMING: 32768:(256x128)=1
;
; Input frequency ACLK:
SSEL = 0
; Input division by 256:
DIV = 1
; Add. input division by 128:
IP = 6
; LCD frequency = 128Hz:
FRFQ = 3
;
; Initialization part
;
HLD
.EQU
040h
; 1: Disable BT
MOV.B
#(DIV+(6*IP)+(3*FRFQ)),&BTCTL ; 1s interval
BIS.B
#BTIE,&IE2
;
; ENABLE INTRPT BASIC TIMER
...
;
; INTERRUPT HANDLER BASIC TIMER
; The register BTCNT2 needs to be read twice
;
BTHAN
PUSH
R5
; SAVE USED REGISTER
L$300
MOV.B
&BTCNT2,R5
; READ ACTUAL TIMER VALUE
CMP.B
&BTCNT2,R5
; ENSURE DATA INTEGRITY
JNE
L$300
; READ AGAIN IF NOT EQUAL
;
; R5 CONTAINS ACTUAL TIMER VALUE, BTDTOL CONTAINS LAST VALUE
; READ. THE DIFFERENCE IS ADDED TO THE 1S COUNTER
;
PUSH.B
BTDTOL
; SAVE LAST TIMER VALUE
MOV.B
R5,BTDTOL
; ACTUAL VALUE –> LAST VALUE
SUB.B
@SP+,R5
; ACTUAL – LAST VALUE –> R5
ADD
R5,TIMER
; 16–BIT DIFFERENCE TO COUNTER
ADC
TIMER+2
; Carry to high word
POP
R5
; Restore R5
RETI
;
.SECT
”Int_Vect”,0FFE2h
.WORD
BTHAN
; Basic Timer Interrupt Vector
On-Chip Peripherals
6-3
The Basic Timer
6.1.1
Change of the Basic Timer Frequency
If the basic timer is used as a time base (for example as a base for a clock),
then it is necessary to compensate if the frequency is changed during the normal run. The necessary operations are different for changing from a faster frequency to a slower one than for the reverse operation. The timer register
where the interrupts are counted needs to be implemented for the highest
used basic timer frequency.
Slow to fast change: The change should be done only inside the basic timer
interrupt routine. The status is to be changed to the new time value.
Fast to slow change: The change should only be done inside the basic timer
interrupt routine. Afterward, all bits of the software timer register that represent
the higher basic timer frequencies should be reset to zero. This is the correct
time for the lower frequency.
Example 6–2. Basic Timer Interrupt Handler
A basic timer interrupt handler that works with two frequencies, 1 Hz and 8 Hz,
is shown below. All necessary status routines are shown. The handler may be
used for all other possible frequency combinations as well. The background
software changes the status according to the needs.
HIF
.EQU
8
; Hi frequency is 8Hz
LOF
.EQU
1
; Lo frequency is 1Hz
LOBIT
.EQU
HIF/LOF
; LSB position of low frequency
.BSS
TIMER,2
; 16–bit timer register
.BSS
BTSTAT,1
; Status byte
PUSH
R5
; Save R5
MOV.B
BTSTAT,R5
; R5 contains status (0, 2, 4, 6)
BR
BTTAB(R5)
; Got to appropr. routine
.WORD
BT1HZ
; ST0: 1Hz interrupt
.WORD
BT8HZ
; ST2: 8Hz interrupt
.WORD
CHGT8
; ST4: Change to 8Hz interrupt
.WORD
CHGT1
; ST6: Change to 1Hz interrupt
MOV.B
#2,BTSTAT
; Change to 8Hz interrupt
BIC.B
#IP2+IP1+IP0,&BTCTL ; Clear frequ. bits
BIS.B
#IP1+IP0,&BTCTL
;
BT_INT
BTTAB
;
CHGT8
6-4
; Set 8Hz, use BT1HZ for INCR.
The Basic Timer
BT1HZ
ADD
#LOBIT,TIMER
POP
R5
RETI
; Incr. bit 3 of the 125ms timer
; No change of status
;
BT8HZ
INC
TIMER
POP
R5
; Incr. bit 0 of the 125ms timer
RETI
; No change of status
;
CHGT1
INC
TIMER
; Incr. bit 0 (evtl. carry)
BIC
#LOBIT–1,TIMER
; Reset 8Hz bits to zero
MOV.B
#0,BTSTAT
; New status: 1Hz interrupt
BIC.B
#IP2+IP1+IP0,&BTCTL ; Clear frequ. bits
BIS.B
#DIV+IP2+IP1,&BTCTL ; Set 1Hz
POP
R5
RETI
;
6.1.2
.SECT
”Int_Vect”,0FFE2h
.WORD
BT_INT
; Basic Timer Interrupt Vector
Elimination of Crystal Tolerance Error
For normal measurement purposes, the accuracy of 32768 Hz crystals is more
than sufficient. But, if highly accurate timing has to be maintained for years,
then it is necessary to know the frequency deviation from the exact frequency
of the crystal used (together with the oscillator). An example for such an application is an electricity meter that must change the tariff at given times each
day without any possibility of synchronizing the internal timer to a reference.
The time deviations for two crystal accuracies (+1 Hz and +10 ppm) are shown
in Table 6–2. The data in the table indicates the amount of time required to accumulate a given time error.
Table 6–2. Crystal Accuracy
DEVIATION =
1S
DEVIATION =
1m
32768 Hz, 1 Hz
9.10 hours
22.75 days
3.74 years
32768 Hz, 10 ppm
27.77 hours
69.44 days
11.40 years
ACCURACY
DEVIATION =
1h
On-Chip Peripherals
6-5
The Basic Timer
If these time deviations are not acceptable, then a calibration and correction
are necessary:
1) The crystal frequency is measured and the deviation stored in the RAM
or EEPROM. All other interrupts have to be disabled during this measurement to get correct results.
2) The measured time deviation of the crystal is used for a correction that
takes place at regular time intervals.
The crystal frequency can be measured during the calibration with a timing signal of exactly 10 or 16 seconds at one of the ports with interrupt capability. The
MSP430 counts its internal oscillator frequency, ACLK, during this time with
one of the timers (8-bit timer or 16-bit timer) and gets the deviation to
32768 Hz. The deviation measured is added at appropriate time intervals
(32768 s x 10 or 32768 s x 16) to the timer register that counts the seconds.
32 kHz + –nHz
SVCC
COM
SEL
Error
C
TO
A0
Temperature
MSP430 Ox
AGND
Calibration
Unit
P0.y
CLK
EEPROM
Data
P0.x
VCC
VSS
+
10s
3 V @ 1.6 µA
Figure 6–1. Crystal Calibration
If necessary, the temperature behavior of the crystal can also be taken into account. Figure 6–2 shows the typical temperature dependence of a crystal. TO
is the nominal frequency at a particular temperature. Above and below this
temperature, the frequency is always lower (negative temperature coefficient).
The frequency deviation increases with the square of the temperature deviation (–0.035 ppm/°C2 for the example).
6-6
The Basic Timer
TO –10
0
TO
TO +10
Crystal Temperature °C
–3.5
–7
Frequency
Deviation ppm
Figure 6–2. Crystal Frequency Deviation With Temperature
The quadratic equation that describes this temperature behavior is approximately (TO = +19°C):
∆f
Where:
∆f
T
= – 0.035 × (T – 19) 2
Frequency deviation in ppm
Crystal temperature in °C
To use the equation shown above, simply measure the crystal temperature
(PC board temperature) every hour and calculate the frequency deviation.
These deviations are added up until an accumulated deviation of one second
is reached. The counter for seconds is then incremented by one and one second is subtracted from the accumulated deviation, leaving the remainder in the
accumulation register.
Example 6–3. Quadratic Crystal Temperature Deviation Compensation
The crystal temperature is measured each hour (3600 s) and calculated. The
result — with the dimension ppm/1024 — is added up in RAM location PPMS.
If PPMS reaches 1024, one second is added to seconds counter SECONDS
and PPMS is reduced by 1024. The numbers at the right margin show the digits
before and after the assumed decimal point.
On-Chip Peripherals
6-7
The Basic Timer
; Quadratic temperature compensation after each hour:
; tcorr = –|(T–19)^2 x –0.035ppm| x t
; Tmax = To+40C, Tmin = To–40C
;
To
PPM
.SET
19
; Turning point of temperature
.SET
35
; –0.035ppm/(T–To)^2
.BSS
PPMS,2
; RAM word for adding–up deviation
.BSS
SECOND,2
; RAM word for seconds counting
;
TIMCORR
CALL
#MEASTEMP
;Meas. crystal temperature
POP
IROP2L
; Result to IROP2L
SUB
#(To*10h),IROP2L
; T – To
MOV
IROP2L,IROP1
; Copy result
CALL
#MPYS
; |T–To|^2
CALL
#SHFTRS6
; Adapt |T–To|^2
ADC
IRACL
; Rounding
MOV
IRACL,IROP2L
; |T–To|^2 –> IROP2L
6.4h
6.4h
6.4h
(always pos.) 12.8
12.2
12.2
;
; tcorr = 3600 x –0.035 x 1E–6 x (T–19)^2
s/h
;
L$006
MOV
#(36*PPM),IROP1
; 36 x PPM/1E4
ms/h
CALL
#MPYS
; Signed multiplication
;
; IRAC contains: 36s x PPM x 4 (To–T)^2 x 1E–7
; = 36s x PPM x 4 (To–T)^2 x 1E–4
s/h
ms/h
;
CALL
#SHFTLS6
; to IRACM
;
; IRACM contains: tcorr = 4 x dT x 36 x PPM/1024
; Correction: 0.25 x 1E–7 x 1024 = 1/39062.5
;
L$200
6-8
ADD
IRACM,PPMS
; Add–up deviation
CMP
#39062,PPMS
; One second deviation reached?
JLO
L$200
INC
SECONDS
SUB
#39062,PPMS
RET
; Yes, add one second
; and adjust deviation counter
The Basic Timer
6.1.3
Clock Subroutines
The following two subroutines provide 24-hour clocks — one using decimal
counting (RTCLKD) and one using hexadecimal counting (RTCLK). These
subroutines are called every second by the basic timer handler.
;
SEC
.EQU
0200H
; Byte for counting of seconds
MIN
.EQU
0201H
; Byte for counting of minutes
HOURS
.EQU
0202H
; Byte for counting of hours
;
; Subroutine provides a decimal clock: 00.00.00 to 23.59.59
;
RTCLKD
RTRETD
SETC
; Entry every second
DADC.B
SEC
; Increment seconds
CMP.B
#060H,SEC
; One minute elapsed?
JLO
RTRETD
; No, return (C = 0)
CLR.B
SEC
; Yes, clear seconds (C = 1)
DADC.B
MIN
; Increment minutes with set carry
CMP.B
#060H,MIN
;
JLO
RTRETD
CLR.B
MIN
DADC.B
HOURS
CMP.B
#024H,HOURS
JLO
RTRETD
CLR.B
HOURS
RET
; 00.00.00 Return to caller
; C = 1: one day elapsed
;
; Subroutine provides a hex clock: 00.00.00 to 17.3B.3B
;
RTCLK
INC.B
SEC
; Entry point every second
CMP.B
#60,SEC
; Increment seconds
JLO
RTRET
; One minute elapsed?
CLR.B
SEC
; No, return to caller
INC.B
MIN
; Yes, clear seconds
CMP.B
#60,MIN
; Increment minutes
JLO
RTRET
On-Chip Peripherals
6-9
The Basic Timer
RTRET
CLR.B
MIN
INC.B
HOURS
CMP.B
#24,HOURS
JLO
RTRET
CLR.B
HOURS
RET
; 00.00.00
; C = 1: one day elapsed
The next subroutine increments the date with each call. The handling of leap–
years is included. The data is stored in binary format.
DAY
.EQU
0203h
; Day of month 1 – 31 (byte)
MONTH
.EQU
0204h
; Month 1 – 12 (byte)
YEAR
.EQU
0206h
; Year 1990 – 2399 (word)
PUSH
R5
; Save R5
INC.B
DAY
; To next day of month
MOV.B
MONTH,R5
; Look for length of month
MOV.B
MT–1(R5),R5
CMP.B
#2,MONTH
JNE
NOFEB
BIT
#3,YEAR
JNZ
NOFEB
INC
R5
; Yes, 29 days for February
CMP.B
R5,DAY
; One month elapsed?
JLO
DATRET
; No
MOV.B
#1,DAY
; Yes, start with 1st day
INC.B
MONTH
; of next month
CMP.B
#13,MONTH
; Year over?
JLO
DATRET
; No
MOV.B
#1,MONTH
; Yes, start with 1st month
INC
YEAR
; of next year
POP
R5
; Restore R5
;
DATE
NOFEB
DATRET
; February now?
; Yes, Leap Year?
RET
;
; Table with the length of the 12 months
;
6-10
The Basic Timer
MT
6.1.4
.BYTE
31+1,28+1,31+1,30+1,31+1,30+1 ; January to June
.BYTE
31+1,31+1,30+1,31+1,30+1,31+1 ; July to December
The Basic Timer Used as a 16-Bit Timer
The two 8-bit registers BTCNT1 and BTCNT2 may be connected together and
used as a simple 16-bit timer counting the ACLK. This 16-bit value can be used
for time measurements by calculating the difference of two readings. The
problem is that the two registers cannot be read with just one instruction, so
BTCNT1 can overflow between the two readings and deliver an incorrect result. The following software corrects this possible error. If the LSBs change
during the register read, then a second reading is made. This second register
read is likely correct because of the relatively long time interval (30.5 µs). If interrupts between the readings can occur, then the interrupt can be disabled
with the DINT instruction.
BTCTL
.equ
040h
; Basic Timer1 Control Register
DIV
.equ
020h
; Clock for BTCNT2 is ACLK/256
BTCNT1
.equ
046h
; LSBs of Basic Timer1
BTCNT2
.equ
047h
; MSBs of Basic Timer1
MOV.B
#DIV+xx,BTCTL
; Define BT as a 16–bit counter
MOV.B
&BTCNT1,R5
; Read LSBs of Basic Timer1 00yy
MOV.B
&BTCNT2,R6
; Read MSBs 00xx
CMP.B
&BTCNT1,R5
; LSBs still the same?
JNE
L$1
; No, read once more, 30.5us time
SWPB
R6
; Yes, prepare 16–bit result xx00
ADD
R5,R6
; Correct result in R6 now: xxyy
;
...
L$1
If the result of the first reading is important, then the following subroutine may
be used. The 16-bit value is read and corrected if an overflow to 0 may have
happened between the reading of the low and high bytes.
; Read–out of the Basic Timer running as a 16–bit timer
;
MOV.B
&BTCNT1,R5
; Read LSBs
00yy
MOV.B
&BTCNT2,R6
; Read MSBs
00xx
CMP.B
R5,&BTCNT1
; BTCNT1 still >= R5?
JHS
L$1
; Yes, no overflow
On-Chip Peripherals
6-11
The Basic Timer
;
; Transition from 0FFh to 0 occurred with LSBs, read actual
; MSB, it now has the value + 1.
;
L$1
6-12
MOV.B
&BTCNT2,R6
; Read actual MSBs
00xx
DEC.B
R6
; MSB – 1 is correct
SWPB
R6
; MSBs to high byte
ADD
R5,R6
; 16–bit value to R6: xxyy
xx00
The Watchdog Timer
6.2 The Watchdog Timer
The internal watchdog of the MSP430 family may be used as a simple timer
or as a watchdog that ensures system integrity. The watchdog function is enabled after power-on reset or a system reset. This means that if there are difficulties after the start-up of the MSP430, the watchdog will reset the system as
often as it is needed for it to start successfully. The watchdog mode is described in this chapter.
6.2.1
Supervision of One Task With the Watchdog
In Section 5.7.2.2 Power Fail Detection With the Watchdog, an example is given of how to use the watchdog for the supervision of a power fail task only. This
example shows the necessary hardware and the software needed to detect
an impending power failure. As long as ac line voltage is present, an interrupt
occurs for each polarity change of the ac line. These interrupts reset the watchdog, preventing it from timing out. If the line voltage falls below a certain level
or fails completely, these interrupts disappear and the watchdog is not reset.
When the watchdog times out, it initializes the MSP430 system.
6.2.2
Supervision of Multiple Tasks With the Watchdog
Normally, the watchdog can only supervise one task at a time. If this task does
not reset the watchdog, the MSP430 is initialized by the watchdog. In complex
systems, more than one function needs to be supervised to assure correct system functionality. This is possible with a small software effort — each supervised function sets a bit in a RAM byte if it runs correctly. The mainloop then
resets the watchdog only if all bits are set. This approach can be enlarged to
any number of supervised functions if more than one byte is used.
Example 6–4. Watchdog Supervision of Three Functions
A system running with MCLK = 3 MHz uses the watchdog for the supervision
of three functions.
- Power Fail — by the checking of the 60 Hz AC line (see section Battery
Check and Power Fail Detection for details)
- Function 1 — a check is made if the software reaches this background
part regularly
- Function 3 — a check is made if this interrupt handler is called regularly
On-Chip Peripherals
6-13
The Watchdog Timer
Each supervised function sets a dedicated bit in RAM byte WDB in intervals
less than 10.66 ms (power-up value of the watchdog with MCLK = 3 MHz) if
everything is functioning normally. The mainloop checks this byte (WDB) and
resets the watchdog ONLY if all three bits are set (07h). If one of the functions
fails, the watchdog is not reset and will therefore reset the system.
; HARDWARE DEFINITIONS
;
ACTL
.EQU
0114h
; ADC CONTROL REGISTER:
PD
.EQU
1000h
; 1: ADC POWERED DOWN
IFG2
.EQU
003h
; INTERRUPT FLAG REGISTER 2
.EQU
001h
; P0.0 Bit Address
IE1
.EQU
000h
; Intrpt Enable Reg. 1 Addr.
P0IE0
.EQU
004h
; P0.0 Intrpt Enable Bit
IFG1
.EQU
002h
; Intrpt Enable Reg. 1 Addr.
P0IFG0
.EQU
004h
; P0.0 Flag Bit
P0IES
.EQU
014h
; Intrpt Edge Sel. Reg. Addr.
SCFQCTL
.EQU
052h
; Sys Clk Frequ. Control Reg.
SCFI0
.EQU
050h
; Sys Clk Frequ. Integr. Reg.
WDTCTL
.EQU
0120h
; Watchdog Timer Control Reg.
WDTIFG
.EQU
01h
; Watchdog flag
CNTCL
.EQU
008h
; Watchdog Clear Bit
WDB
.EQU
0202h
; RAM byte for functional bits
;
P00
;
;
;
.TEXT 0E000h
; Software Start Address
;
; Watchdog reset and Power–up both start at label INIT. The
; reason for the reset needs to be known
;
INIT
BIT.B
#WDTIFG,&IFG1
; Reset by watchdog?
JNZ
WD_RESET
; Yes; check reason
;
; Normal reset caused by RESET pin or power–up: Init. system
;
6-14
The Watchdog Timer
INIT1
BIS.B
#8,&SCFI0
; Switch DCO to 3MHz drive
MOV.B
#96–1,&SCFQCTL
; FLL to 3MHz MCLK
MOV
#05A00h+CNTCL,&WDTCTL ; Define watchdog
BIS.B
#P0IE0,&IE1
; Enable P0.0 interrupt
BIS.B
#P00,&P0IES
; To trailing edge
BIC.B
#P0IFG0,&IFG1
; Reset flag (safety)
;
...
CLR.B
; Continue initialization
WDB
EINT
BR
; Clear Functional Bits
; Enable GIE
#MAINLOOP
; Go to MAINLOOP
;
; Reset is caused by watchdog: check reason and handle
; individually
;
WD_RESET MOV.B
TAB
WDB,R5
; Build handler address
MOV.B
TAB(R5),R5
SXT
R5
ADD
R5,PC
.BYTE
INIT1–TAB
; All functions failed: hang–up
.BYTE
PF–TAB
; power fail and function 3
.BYTE
F1F3–TAB
; Function 1 and 3 failed
.BYTE
F3–TAB
; Function 3 failed
.BYTE
PF–TAB
; Power fail and function 1
.BYTE
PF–TAB
; Power fail
.BYTE
F1–TAB
; Function 1 failed
.BYTE
INIT1–TAB
; All bits set: hang–up
; Offsets may be negative!
;
; Missing mains voltage means power fail.
; Supply current is minimized to enlarge active time
;
PF
BIC.B
#03Fh,&TPD
...
; Switch off all TP–outputs
; Switch off other loads
BIS
#PD,&ACTL
; Power down ADC
MOV.B
#32–1,&SCFQCTL
; MCLK back to 1MHz
BIC.B
#01Ch,&SCFI0
; DCO drive to 1MHz
On-Chip Peripherals
6-15
The Watchdog Timer
...
; Store values to EEPROM
;
; All tasks are done: LPM3 to bridge eventually the power fail
;
BIS
#CPUoff+GIE+SCG1+SCG0,SR
JMP
INIT1
; Continue here eventually
;
; The handlers for all failures except power fail.
; Every failure can be handled individually
;
F1
...
; Function 1 failed
F3
...
; Function 3 failed
F1F3
...
; Function 1 and 3 failed
;
; Background: Main Loop. If RAM–byte WDB contains 07h then the
; watchdog is reset: all 3 supervised functions are OK.
;
MAINLOOP CMP.B
L$1
#07h,WDB
; Test WDB
JNE
L$1
; WDB does not contain 7: continue
MOV
#05A00h+CNTCL,&WDTCTL ; All OK: reset watchdog
CLR.B
WDB
...
; Clear WDB
; Continue Mainloop
;
; Function 1: if the software reaches this address, the
; supervision bit 1 is set in WDB. This indicates normal run
;
BIS.B
#1,WDB
; Set supervision bit 1
...
;
; Function 3: if the software reaches this interrupt handler, the
; supervision bit 3 is set in WDB. This indicates normal run
;
INT_HNDLR
BIS.B
RETI
;
6-16
...
#4,WDB
; Set supervision bit 3
The Watchdog Timer
; The P00_HNDLR is called each the mains changes polarity.
; The bit 2 in WDB is set to indicate: “No Power Fail”.
;
P00_HNDLR
BIS.B #2h,WDB
; Set mains control bit
XOR.B #P00,&P0IES
; Invert edge select for P0.0
RETI
;
;
.SECT ”INT_VEC1”,0FFFAh
.WORD P00_HNDLR
; P0.0 Inrtpt Vector
.WORD 0
; NMI not used
.WORD INIT
; Reset Vector
The interrupt handler for the watchdog operation can be simplified if a strict
priority exists for the processing steps. If, for example, the priority is from power fail (highest priority), to function 3, and function 1 (lowest priority), then the
watchdog handler may look like this:
; Reset is caused by watchdog: check reason and handle with
; priority from power fail to function 1.
;
WD_RESET BIT.B
#2,WDB
; Power fail?
JZ
PF
; Yes, prepare for it
BIT.B
#4,WDB
; Function 3 failed?
JZ
F3
; Yes, handle it
BIT.B
#1,WDB
; Function 1 failed?
JZ
F1
; Yes, handle it
JMP
INIT1
; Hang–up occurred (WDB = 7)
On-Chip Peripherals
6-17
The Timer_A
6.3 The Timer_A
6.3.1
Introduction
The 16-bit Timer_A is a relatively complex timer consisting of the 16-bit timer
register and several capture/compare registers. All capture/compare registers
are identical, but one of them (CCR0) is used for additional functions. The architecture of the Timer_A shows some similarity to the MSP430 CPU — both
of them use the principle of orthogonality (equal features for all registers).
The Timer_A, whose block diagram is shown in Figure 6–3, has several registers available for different tasks. These registers are described in Section 6.3.2
The Timer_A Hardware.
Note:
The software and hardware examples shown are related to the MSP430x33x
family. Other MSP430 family members may use other I/O ports and addresses for the Timer_A registers and signals. Also, the number of capture/
compare registers may be different. The programming principle will stay unchanged; only address definitions need to be modified.
It is recommended that the data book MSP430 Family Architecture Guide
and Module Library (TI literature number SLAUE10B) be consulted. The
hardware related information given there is very valuable and complements
the information in this chapter.
The architecture of the Timer_A is not restricted to the configuration shown in
Figure 6–3. Different family members of the MSP430 family have different configurations of the Timer_A:
- The minimum configuration is the timer register block and the capture/
compare block 0. This allows one timing but no pulse width modulation
(PWM).
- The next possible configuration is the timer register block and the capture/
compare blocks 0 and 1. This allows two independent timings or one PWM
timing.
- The configuration implemented in the MSP430x33x family allows up to
five independent timings or three PWM signals and a capture input for the
speed control (for a 3-phase digital motor control, for example).
- Larger configurations are also possible — eight capture/compare blocks
for very complex applications, for example.
The upper limit for the number of capture/compare registers is only the overhead coming from the actualization of the registers and the overhead from the
interrupts, themselves.
6-18
The Timer_A
SSEL1 SSEL0
TACLK
ACLK
MCLK
INCL
K
0
1
2
3
Data
DC to MCLK
Timer Clock
15
Timer Register
Input
CLK1TAR
Divider
RC
ID1 ID0
POR/CLR
Timer Bus
ACLK
GND
VCC
0
1
2
3
Capture
Capture
Mode
0
1
2
3
Capture
VCC
0
1
2
3
0
15
Capture/Compare
Register CCR2
0
15
Output Unit 1
Capture/Compare Block 2
OM22 OM21 OM20
Output Unit 2
Out2
TA2
EQU2
0
15
Capture
Capture
Mode
Capture/Compare
Register CCR3
0
15
Capture/Compare Block 3
OM32 OM31 O320
Output Unit 3
Comparator 3
Out3
TA3
EQU3
CCM31 CCM30
0
15
Capture
Capture
Mode
Capture/Compare
Register CCR4
0
15
Capture/Compare Block 4
OM42 OM41 O340
Output Unit 4
Comparator 4
CCI4
TA1
Out1
CCM21 CCM20
CCIS41 CCIS40
ACLK
GND
VCC
0
Capture/Compare Block 1
OM12 OM11 OM10
Comparator 2
0
1
2
3
TA0
EQU1
Capture
0
1
2
3
Out0
CCM11 CCM10
Capture
Mode
CCI3
TA4 CCI4A
0
15
Capture/Compare
Register CCR1
15
CCIS31 CCIS30
ACLK
GND
Output Unit 0
Comparator 1
CCI2
TA3 CCI3A
0
Capture/Compare Block 0
OM02 OM01 OM00
EQU0
CCIS21 CCIS20
ACLK
GND
VCC
0
15
Capture/Compare
Register CCR0
CCM01 CCM00
Capture
Mode
CCI1
TA2 CCI2A
Equ0
Set_TAIFG
15
CCIS11 CCIS10
ACLK
GND
VCC
MC1
Stop
Up Mode
Continuous M
Up/Down Mode
Comparator 0
CCI0
TA1 CCI1A
MC0
Mode
Control
Carry/Zero
CCIS01 CCIS00
TA0 CCI0A
Timer Register Block
0
Out4
TA4
EQU4
CCM41 CCM40
Figure 6–3. The Hardware of the 16-Bit Timer_A (Simplified MSP430x33x Configuration)
On-Chip Peripherals
6-19
The Timer_A
Applications for the Timer_A can be:
- Generation of up to five independent timings (MSP430x33x configuration)
- Frequency generation — using the output units, the internal generated
timings can be output to the external periphery of the MSP430
- Generation of the timing for RF transmission (amplitude modulation, bi-
phase code, biphase space modulation) for the transfer of metered data
(gas meters, electric meters, heat allocation meters, etc.)
- Realization of a software SPI
- Realization of a software UART
- Digital motor control (DMC) — the MSP430x33x is able to control a
3-phase electric motor with PWM in closed loop mode
- TRIAC control for electric motors and other power applications
- Time measurement, period measurement, pulse width measurement
- Frequency measurement (using the capture mode for low frequencies)
- Analog-to-digital converter (ADC) — a single-slope ADC can be built using
the capture mode. Normal I/O ports switch the reference resistors and
sensors
- DTMF generation — the DTMF frequency pairs can be generated by soft-
ware and output by three external operational amplifiers for filtering and
mixing. See the third part of this chapter for hardware and software details
- Crystal replacement — the frequency locked loop (FLL) of the MSP430
may be locked to the ac line frequency instead of the 32-kHz frequency
of a crystal. This eliminates the need for a crystal and provides a better
adaptation to the ac line frequency (for DMC applications, for example)
- PWM generation with the output units
- Real Time Clock (RTC) — if fed by the ACLK (32 kHz), the Timer_A can
be used as an RTC with all low power modes. Time intervals of up to two
seconds in steps of 2–15 s are possible.
6-20
The Timer_A
6.3.1.1
Definitions Used with the Application Examples
; HARDWARE DEFINITIONS
;
TAIV
.equ
12Eh
; Timer_A Vector Register
TACTL
.equ
160h
; Timer_A Control Register
TAIFG
.equ
001h
; Interrupt flag
TAIE
.equ
002h
; Interrupt enable bit
CLR
.equ
004h
; Reset TAR and Input Divider
MSTOP
.equ
000h
; Stop Mode
MUP
.equ
010h
; Up Mode
MCONT
.equ
020h
; Continuous Mode
MUPD
.equ
030h
; Up/Down Mode
D1
.equ
000h
; Input Divider: Pass
D2
.equ
040h
;
/2
D4
.equ
080h
;
/4
D8
.equ
0C0h
;
/8
ISTACLK
.equ
000h
; Input Selector:TACLK
ISACLK
.equ
100h
;
ACLK
ISMCLK
.equ
200h
;
MCLK
ISINCLK
.equ
300h
;
INCLK
CCTL0
.equ
162h
; Capture/Compare Control Reg. 0
CCTL1
.equ
164h
; Capture/Compare Control Reg. 1
CCTL2
.equ
166h
; Capture/Compare Control Reg. 2
CCTL3
.equ
168h
; Capture/Compare Control Reg. 3
CCTL4
.equ
16Ah
; Capture/Compare Control Reg. 4
;
; Bits of the TACTL Register:
;
;
; Bits in the CCTLx Registers:
CCIFG
.equ
001h
; Interrupt flag
COV
.equ
002h
; Capture overflow flag
OUT
.equ
004h
; Output bit
CCI
.equ
008h
; Input signal
CCIE
.equ
010h
; Interrupt enable bit
OMOO
.equ
000h
; Output Mode:
OMSET
.equ
020h
;
set
OMTR
.equ
040h
;
toggle/reset
output only
On-Chip Peripherals
6-21
The Timer_A
OMSR
.equ
060h
;
set/reset
OMT
.equ
080h
;
toggle
OMR
.equ
0A0h
;
reset
OMTS
.equ
0C0h
;
toggle/set
OMRS
.equ
0E0h
;
reset/set
CAP
.equ
100h
; Capture/Compare switch
SCCI
.equ
400h
; Synchronized CCI
SCS
.equ
800h
; Async/sync switch
ISCCIA
.equ
000h
; Capture input:
ISCCIB
.equ
1000h
;
CCIxB
ISGND
.equ
2000h
;
GND
ISVCC
.equ
3000h
;
Vcc
CMDIS
.equ
000h
; Capture mode:
CMPE
.equ
4000h
;
rising edge
CMNE
.equ
8000h
;
falling edge
CMBE
.equ
0c000h
;
both edges
CCR0
.equ
172h
; Capture/Compare Register 0
CCR1
.equ
174h
; Capture/Compare Register 1
CCR2
.equ
176h
; Capture/Compare Register 2
CCR3
.equ
178h
; Capture/Compare Register 3
CCR4
.equ
17Ah
; Capture/Compare Register 4
TAR
.equ
0170h
; Timer Register
TA0
.equ
008h
; Bit address TA0 Port3: P3.3
TA1
.equ
010h
; Bit address TA1 Port3: P3.4
TA2
.equ
020h
; Bit address TA2 Port3: P3.5
TA3
.equ
040h
; Bit address TA3 Port3: P3.6
TA4
.equ
080h
; Bit address TA4 Port3: P3.7
P3SEL
.equ
01Bh
; Port3 Select Register
P3DIR
.equ
01Ah
; Port3 Direction Register
P3OUT
.equ
019h
; Port3 Direction Register
CCIxA
disabled
;
;
;
; Definitions of other used peripherals
;
SCFQCTL
6-22
.equ
052h
; FLL Multiplier and Mod. Bit
The Timer_A
M
.equ
080h
; Modulation Bit
SCFI0
.equ
050h
; Current Switches FN_x, FLL
FN_2
.equ
004h
; DCO Switch for 2MHz
FN_3
.equ
008h
; DCO Switch for 3MHz
SCFI1
.equ
051h
; Taps of DCO
P0FG
.equ
013h
; Port0 Flag Register Address
P0IE
.equ
015h
; Port0 Interrupt Enable Reg.
IE1
.equ
0
; Interrupt Enable Register
P0IE.0
.equ
4
; P0.0 Interrupt Enable Bit
CBCTL
.equ
053h
; Crystal Buffer Control
CBE
.equ
001h
; Enable XBUF output
CBACLK
.equ
000h
; ACLK is output at XBUF
CBMCLK
.equ
006h
; MCLK is output at XBUF
BTCTL
.equ
040h
; Basic Timer Control Register
BTCNT1
.equ
046h
; Basic Timer Counter 1
WDTCTL
.equ
120h
; Watchdog Control Register
CNCTL
.equ
008h
; Reset Watchdog Bit
HOLD
.equ
080h
;
;
;
; Stop Watchdog
; Bits in the Status Register SR
GIE
.equ
008h
; General Interrupt Enable
CPUOFF
.equ
010h
; CPU–Off bit
SCG0
.equ
040h
; Low Power Mode Bits
SCG1
.equ
080h
6.3.2
Timer_A Hardware
Timer_A has a modular structure, giving it considerable flexibility. At least one
capture/compare block is necessary for all configurations, and an almost unlimited number of capture/compare blocks may be connected to the timer register block (see Figure 6–4). The general function of these blocks is described
below. The user software controls the Timer_A with the registers that are described there.
Several registers control the function of Timer_A. Every capture/compare register (CCRx) has its own control register CCTLx and the timer register (TAR)
is also controlled by its own control register TACTL. This section describes all
registers contained in the Timer_A.
On-Chip Peripherals
6-23
The Timer_A
The Timer_A registers have two common attributes:
- All registers, with the exception of the interrupt vector register (TAIV), can
be read and written to
- All registers are word-structured and should be accessed therefore by
word instructions only. Byte addressing results in a nonpredictable operation.
Example 6–5. Timer Register Low Byte
If only the information contained in the low byte of the timer register is wanted,
then the following code sequence may be used:
MOV
&TAR,R5
; Read the complete TAR: yyxxh
MOV.B
R5,R5
; 00xxh to R5
If only the high byte information of the timer register is wanted:
MOV
&TAR,R5
; Read the complete TAR: yyxxh
SWPB
R5
; Swap bytes: yyxxh –> xxyyh
MOV.B
R5,R5
; 00yyh to R5
Table 6–3 shows the mnemonics and the hardware addresses of the Timer_A
registers.
Table 6–3. Timer_A Registers
REGISTER NAME
Timer_A control register
ABBREVIATION
REGISTER TYPE
ADDRESS
INITIAL STATE
TACTL
Read/Write
160h
POR Reset
TAR
Read/Write
170h
POR Reset
CCTL0
Read/Write
162h
POR Reset
Capture/Compare Register 0
CCR0
Read/Write
172h
POR Reset
Cap/Com Control Register 1
CCTL1
Read/Write
164h
POR Reset
Capture/Compare Register 1
CCR1
Read/Write
174h
POR Reset
Cap/Com Control Register 2
CCTL2
Read/Write
166h
POR Reset
Capture/Compare Register 2
CCR2
Read/Write
176h
POR Reset
Cap/Com Control Register 3
CCTL3
Read/Write
168h
POR Reset
Capture/Compare Register 3
CCR3
Read/Write
178h
POR Reset
Cap/Com Control Register 4
CCTL4
Read/Write
16Ah
POR Reset
Capture/Compare Register 4
CCR4
Read/Write
17Ah
POR Reset
TAIV
Read only
12Eh
(POR Reset)
Timer register
Cap/Com Control Register 0
Interrupt Vector Register
Note:
6-24
Future extensions — more capture/compare registers — will use the reserved addresses 16Ch, 16Eh, 17Ch, and 17Eh.
The Timer_A
6.3.2.1
The Timer Register Block
The timer register block is the main block of the Timer_A. Even the simplest
version contains this block, which includes the timer register (TAR). The timer
register block consists of the following parts:
- Input Multiplexer — selects the timer input signal out of four possible
sources
- Input Divider — selects the division factor for the timer input signal (1, 2,
4, 8)
- Timer Register TAR — a 16-bit counter
- Mode Control — selects one of the possible four modes (Stop, Continu-
ous, Up, Up/Down)
- Timer Control Register TACTL — contains all control bits for the timer
register Block
- Timer Vector Register TAIV — contains the vector of the interrupt with
the actual highest priority
- Interrupt Logic
SSEL1 SSEL0
0
TACLK
1
ACLK
2
MCLK
3
INCLK
Data
DC to MCLK
Timer Clock
15
Input
Divider
Data
15
Timer Register BLock
0
Timer Register (TAR)
CLK
RC
Mode
Control
Timer Control
Register
Equ0
Carry/Zero
ID1 ID0
0
0 Pass
0
1 1/2
1
0 1/4
1
1 1/8
POR/CLR
TIMOV
Set_TAIFG
Timer Bus
0
Data
MC
0
0
1
1
MC0
0
1
0
1
From CCR Blocks
0
15
Timer Vector
Register
n
Interrupt Logic
Figure 6–4. The Timer Register Block
On-Chip Peripherals
6-25
The Timer_A
6.3.2.1.1 The Timer Register (TAR)
The timer register (TAR) is the main register of the timer. The timer input frequency — selected from four different sources — is prescaled by the input divider (by a factor of 1, 2, 4, or 8) and counted with this 16-bit register. The timer
register information is distributed to all other registers via the 16-bit tmer bus.
This register contains the counted information in all three timer modes (Figure
6–4).
The timer register is incremented with the positive edge of its input signal, timer
clock. The CCIFG flags and the TAIFG flag are also set with the positive edge
if the programmed conditions are true.
The maximum resolution for the Timer_A is 1/fMCLKmax. This relates to a maximum input frequency for the timer register equal to fMCLKmax (currently 4 MHz,
250 ns resolution for the MSP430C33x).
The 16 bits of the timer register can be cleared by two methods:
CLR
&TAR
; 0 –> TAR, nothing else
BIS
#CLR,&TACTL
; Clear TAR, Inp. Div. + count dir
The second method clears not only the timer register, but also the content of
the input divider and sets the count direction of the timer register to upward.
6.3.2.1.2 The Timer_A Control Register TACTL
The timer control register (TACTL) contains all bits that control the timer register (TAR) and its operation. The control bits are reset with the power-on reset
(POR) signal but the power-up clear (PUC) signal does not affect them. This
allows a continued Timer_A operation if the watchdog times out or the watchdog security key is violated. The timer control register (Figure 6–5) is a word
register and should therefore be accessed with word instructions only.
15
0
TACTL
unused
Input
Select
Input
Divider
Mode
Control
rw–
(0)
rw–
(0)
rw–
(0)
rw–
(0)
160h
un– CLR TAIE
used
TAIFG
rw– (w)– rw– rw–
(0) (0)
(0) (0)
Figure 6–5. Timer Control Register (TACTL)
If the operation of the Timer_A needs to be modified — with the exception of
the TAIFG and TAIE bits — then the Timer_A should be halted during the modification of the control bits. After the change of the TACTL register, Timer_A is
restarted. Without this procedure, unpredictable behavior is possible.
6-26
The Timer_A
Example 6–6. The Timer_A Control Register TACTL
The timer should be restarted in continuous mode. This is accomplished with
two instructions. The first instruction defines the new state of the timer (except
the mode), and stops it (Mode Control = 00). The second instruction sets the
mode control bits to continuous mode and restarts the timer operation.
Input Selection: MCLK
Input Divider: /4, cleared
Interrupt: enabled, TAIE = 1, TAIFG = 0
MOV
#ISMCLK+D4+CLR+TAIE,&TACTL
BIS
#MCONT,&TACTL
; Define new state
; Restart Continuous Mode
The control bits of the Timer control register are explained below.
15
Timer Interrupt Flag TAIFG
0
Input
Select
unused
Input
Divider
Mode
Control
un– CLR TAIE
used
TAIFG
This flag indicates a timer overflow event: the timer register TAR reached the
value zero. The way to get the flag TAIFG set depends on the mode used:
- Continuous Mode — TAIFG is set if the timer counts from 0FFFFh to
0000h.
- Up Mode — TAIFG is set if the timer counts from the CCR0 value to 0000h.
- Up/Down Mode — TAIFG is set if the timer counts down to 0000h.
See the The Timer Vector Register TAIV section for examples how to use the
TAIFG flag.
15
Timer Overflow Interrupt Enable Bit TAIE
0
unused
Input
Select
Input
Divider
Mode
Control
un– CLR TAIE
used
TAIFG
This bit enables and disables the interrupt for the timer interrupt flag TAIFG:
TAIE = 0: Interrupt is disabled
TAIE = 1: Interrupt is enabled
An interrupt is requested only if the TAIFG bit, the TAIE bit, and the GIE (SR.3)
bit are set. The sequence of the bit setting does not matter. If two out of the
three bits (mentioned above) are 1, and the third is set afterward, an interrupt
will be requested.
On-Chip Peripherals
6-27
The Timer_A
Example 6–7. Timer Overflow Interrupt Enable Bit TAIE
Interrupt is enabled for the TAIFG flag. A pending interrupt is cleared.
BIC
#TAIFG,&TACTL
; Clear TAIFG flag
BIS
#TAIE,&TACTL
; Enable interrupt for TAIFG
15
0
Input
Select
unused
Timer Clear Bit CLR
Input
Divider
Mode
Control
un– CLR TAIE
used
TAIFG
The timer register (TAR) and the input divider are cleared, after POR or if bit
CLR is set by the software. The CLR bit is automatically reset by the hardware
and always read as 0. The Timer_A starts operation with the next positive edge
of the timer clock. The counting starts in upward direction if it is not halted by
cleared Mode Control bits.
Example 6–8. Timer Clear Bit CLR
Timer_A is restarted after the calibration process. It needs a complete reset:
up/down mode, upward count direction, interrupt enabled, MCLK passed to
the timer register, input divider cleared.
MOV
#ISMCLK+D1+CLR+TAIE,&TACTL ; Define state
BIS
#MUPD,&TACTL
; Start Up/Down Mode
Bit 3
Not used. Read as 0. To maintain software compatibility, this bit should NOT
be set.
15
0
unused
Mode Control Bits
Input
Select
Input
Divider
Mode
Control
un– CLR TAIE
used
TAIFG
The two mode control bits define the operation of the Timer_A. Table 6–4 lists
the four possible modes. See Section 6.3.3 The Timer Modes for a detailed
description of the timer modes. If the mode control bits are cleared (stop
mode), a restart of the timer operation is possible exactly at the point where
the operation was halted, including the count direction information used with
the up/down mode.
Table 6–4. Mode Control Bits
MODE CONTROL BITS
6-28
COUNT MODE
COMMENT
0
Stop Mode
Timer is halted
1
Up Mode
Count up to CCR0 and restart at 0
2
Continuous Mode
Count up to 0FFFFh and restart at 0
3
Up/Down Mode
Count up to CCR0 and back to 0, restart
The Timer_A
Example 6–9. Mode Control Bits
Timer_A is stopped and restarted in continuous mode.
BIC
#MUP+MCONT,&TACTL ; Stop Timer_A
...
BIS
#MCONT,&TACTL
; Restart in Cont. Mode
15
0
Input
Select
unused
Input Divider Control Bits
Input
Divider
Mode
Control
un– CLR TAIE
used
TAIFG
The two input divider control bits allow the use of a prescaled input frequency
(timer clock) for the timer register (TAR). A prescaler may be necessary because of any of the following:
- The MCLK frequency (up to 4 MHz) is too high for the task.
- The MCLK frequency leads to an overflow of the timer register (TAR) dur-
ing the necessary measurement periods. This makes a RAM extension of
the TAR necessary, which takes time and occupies RAM space.
- The resulting resolution is not necessary.
- The resulting timer register contents lead to numbers that are too large
during the calculations.
- Power savings is important.
If one the above reasons is true, then a prescaled input frequency should be
used. The possible prescale factors are shown in Table 6–5.
Table 6–5. Input Divider Control Bits
INPUT DIVIDER BITS
MODE
COMMENT
0
Pass
1
2
Input signal is divided by 2
2
4
Input signal is divided by 4
3
8
Input signal is divided by 8
Input signal is passed to the Timer Register
Example 6–10. Input Divider Control Bits
The input divider is changed from pass mode (0) to divide-by-4 mode (2):
BIC
#MUP+MCONT,&TACTL ; Stop Timer_A
BIS
#MUP+D4+CLR,&TACTL ; Continue in Up Mode
On-Chip Peripherals
6-29
The Timer_A
15
0
Input
Select
unused
Input Selection Bits
Input
Divider
Mode
Control
un– CLR TAIE
used
TAIFG
The three input selection bits select the input signal of the input divider. Four
different sources are provided as shown in Table 6–6. The INCLK input may
be used for a fourth input source with other family members.
Table 6–6. Input Selection Bits (MSP430x33x — Source Depends on MSP430 Type)
INPUT SELECT BITS
SIGNAL
COMMENT
0
TACLK
Signal at the external pin TACLK is used
1
ACLK
ACLK is used
2
MCLK
MCLK is used
3
INCLK
MCLK for the MSP430C33x
4–7
N/A
Reserved for future expansion
The highest timer resolution is possible with the internal MCLK signal: the full
range of the MCLK frequency may be used. If the external pin TACLK (P3.2
for the MSP430C33x) is selected, then the maximum input frequency is restricted due to the internal capacities of the signal path. See the specification
for actual limits.
Example 6–11. Input Selection Bits
Timer_A is initialized. Continuous mode, interrupt enabled, ACLK — divided
by 2 — routed to the timer register, timer register and input divider are cleared.
MOV
BIS
#ISACLK+D2+CLR+TAIE,&TACTL
#MCONT,&TACTL
; Define state
; Start timer: Cont.
Mode
Bit 11 to 15
Not used. Read as 0. To maintain software compatibility, these bits should
NOT be set to 1.
6-30
The Timer_A
6.3.2.1.3 The Timer Vector Register TAIV
This 16-bit register contains an even vector ranging from 0 (no interrupt pending) via 2 (CCR1 interrupt) to 10 (timer overflow interrupt TIMOV). See Figure
6–6 and Table 6–7 for more information.
15
0
TAIV
0
0
0
0
0
0
0
0
0
0
0
0
Interrupt vector
0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r0
r–(0) r–(0) r–(0)
r0
12Eh
Figure 6–6. Timer Vector Register (TAIV)
If more than one interrupt is pending, then the vector with the highest priority
is placed into the TAIV register. See figure 6–7. Table 6–7 illustrates the interrupt priority scheme of Timer_A:
Table 6–7. Timer Vector Register Contents
INTERRUPT
PRIORITY
Highest
g
INTERRUPT SOURCE
VECTOR
ADDRESS
VECTOR REGISTER
CONTENTS
Capture/Compare 0
CCIFG0
0FFF2h
N/A
Capture/Compare 1
CCIFG1
0FFF0h
2
Capture/Compare 2
CCIFG2
0FFF0h
4
Capture/Compare 3
CCIFG3
0FFF0h
6
Capture/Compare 4
CCIFG4
0FFF0h
8
TAIFG
0FFF0h
10
Reserved
N/A
12
No interrupt pending
N/A
0
Timer Overflow
Lowest
FLAG
The timer vector register allows a very fast response to the different timer interrupts. Its content is simply added to the program counter (PC), using a JMP
table located directly after the ADD instruction:
ADD
&TAIV,PC
RETI
HTIMOV
; INTRPT with highest priority
; 0: No INTRPT pending
JMP
HCCR1
; 2: CCIFG1 caused INTRPT
JMP
HCCR2
; 4: CCIFG2 caused INTRPT
JMP
HCCR3
; 6: CCIFG3 caused INTRPT
JMP
HCCR4
; 8: CCIFG4 caused INTRPT
...
; 10: TAIFG is reason
On-Chip Peripherals
6-31
The Timer_A
If the corresponding interrupt handlers are out of the reach of JMPs (more than
± 511 words), then a word table containing the handler start addresses may be
used:
TTAB
MOV
&TAIV,R5
; TAIV contains vector: 0 – 10
MOV
TTAB(R5),PC
; Write handler address to PC
.WORD
PRETI
; 0: No INTRPT pending, RETI
.WORD
HCCR1
; 2: CCIFG1 caused INTRPT
.WORD
HCCR2
; 4: CCIFG2 caused INTRPT
.WORD
HCCR3
; 6: CCIFG3 caused INTRPT
.WORD
HCCR4
; 8: CCIFG4 caused INTRPT
.WORD
HTIMOV
; 10: TAIFG is reason
A third (slower) method is to read the content of the register TAIV and to use
the read value for the decision of where to proceed (the interrupt flag with the
highest priority is reset by the MOV instruction):
MOV
&TAIV,R5
; Actual vector to R5. Reset flag
CMP
#2,R5
; Check for CCIFG1 interrupt
JEQ
HCCR1
; 2: CCIFG1 caused INTRPT
CMP
#4,R5
; Check for CCIFG2 interrupt
JEQ
HCCR2
...
; 4: CCIFG2 caused INTRPT
; a.s.o.
The next software example shows a method that does not use the register
TAIV. A normal skip chain is used. Only the software for blocks 0 and 1 is shown
(this example makes the advantages of using the TAIV register obvious):
BIT
#CCIFG0,&CCTL0
; Block 0: Flag set?
JNZ
MOD0
; Yes, serve it
BIT
#CCIFG1,&CCTL1
; Block 1: Flag set?
JNZ
MOD1
; Yes, serve it
...
MOD0
BIC
; Continue with skip chain
#CCIFG0,&CCTL0
...
MOD1
BIC
...
; Reset CCIFG0 flag
; Start handler for block 0
#CCIFG1,&CCTL1
; Reset CCIFG1 flag
; Start handler for block 1
The capture/compare block 0 is not included in the TAIV register; it has its own
interrupt vector located at address 0FFF2h. The shorter interrupt latency time
of register CCR0, makes it the preferred choice for the most time critical applications. The vector for the other Timer_A interrupts is located at address
0FFF0h.
6-32
The Timer_A
Note:
The timer vector register contains only the vectors of timer blocks with enabled interrupt (set CCIEx resp. TAIE bits). Blocks with disabled interrupt bits
(reset CCIEx resp. TAIE bits) can be checked by software if their CCIFG
resp. TAIFG flag is set and the flag must be reset by software too. See the
skip chain example above.
No interrupt flag (CCIFGx or TAIFG) needs to be reset if the register TAIV is
used. The act of reading of the timer vector register TAIV resets the interrupt
flag automatically that determines the actual register content. The interrupt
flag with the next lower priority level defines the timer vector register TAIV afterward.
Note:
Any access to the timer vector register (read or write) resets the interrupt flag
with the highest priority. The timer vector register should be read only and
the read data should be used to determine the interrupt handler with the highest priority, otherwise the data is lost.
On-Chip Peripherals
6-33
The Timer_A
Figure 6–7 shows the internal interrupt logic that controls the register TAIV.
The five controlling inputs are shown.
Priority Encoder
CCI1
EQU1
CAP1
Timer Clock
TAIV Access Vector Generator
CCIFG1 (Flag)
S
S
Sel
2
CCIE1 (Interrupt Enable)
R
IRACC (Interrupt Acknowledge)
CCI2
EQU2
CAP2
Timer Clock
S
S
Sel
CCIFG2
4
CCIE2
R
IRACC
CCI3
EQU3
CAP3
Timer Clock
S
S
Sel
Interrupt_Service_Request
CCIFG3
6
CCIE3
R
IRACC
CCI4
EQU4
CAP4
Timer Clock
S
S
Sel
TAIV Content (0–10)
CCIFG4
8
CCIE4
R
IRACC
Timer ’FFFF’
Timer = ’CCR0’
Mode
Timer Clock
S
S
Sel
TAIFG (Flag)
10
TAIE (Interrupt Enable)
R
IRACC (Reset Flag)
Figure 6–7. Simplified Logic of the Timer Interrupt Vector Register
6-34
The Timer_A
6.3.2.2
The Capture/Compare Register Blocks
Figure 6–8 illustrates the capture/compare register block 1. The others, with
the exception of the capture/compare register block 0, are identical The CCR0
block has additional functions. See section The Period Register CCR0, below.
Timer Bus
CCIS11 CCIS10
TA1 CCI1A
ACLK CCI1B
GND
VCC
0
1
2
3
0
15
Capture/Compare
Register CCR1
Capture
Capture
Mode
EQU0
Capture/Compare Block 1
OM12 OM11 OM10
Out1
0
15
Output Unit 1
TA1
Comparator 1
CCI1 CCM11 CCM10
0
0
Disabled
1
0
Positive Edge
0
1
Negative Edge
1
1
Both Edges
EQU1
0
15
Capture/Compare
Control Register
CCTL1
Data
To Other Capture/Compare Blocks
Figure 6–8. Capture/Compare BLock 1
6.3.2.2.1 The Capture/Compare Registers CCRx
These registers may be used individually as compare registers or as capture
registers. Any combination is possible.
15
0
CCRx
17yh
rw–(0)
rw–(0)
rw–(0)
rw–(0)
rw–(0)
rw–(0)
rw–(0)
rw–(0)
Figure 6–9. The Capture/Compare Registers CCRx
- Compare Mode With Continuous Mode — the register CCRx contains
the time information for the next interrupt. Within the interrupt handler, the
time information for the next interrupt is prepared. The number ∆n (corresponding to the time interval ∆t from the last interrupt to the next one) is
added to CCRx. The interrupt latency time does not play a role in this method. See the example in section The Continuous Mode.
The output units may be used to generate output changes at output pins
TAx with an exactly defined timing, independent of interrupt latency times.
- Compare Mode With Up Mode or Up/Down Mode — the capture/
compare register 0 is used as the period register with these two modes.
On-Chip Peripherals
6-35
The Timer_A
The register CCRx contains the time interval between interrupts respective the pulse width of the output signal at TAx. The registers CCRx are
modified depending on the result of the control calculations. If no pulse
width change is necessary, the timing is repeated without CPU intervention.
- Capture Mode With Continuous Mode — a register (CCRx) used with
the capture mode, copies the timer register at the precise moment the selected capture conditions are satisfied. This allows very accurate measurements of timings independent of the interrupt latency time. If the time
intervals to be captured are longer than 65536 timer register steps, then
a RAM extension (TIMAEXT) is necessary. This RAM extension is incremented with the TAIFG interrupt and used with the calculations as shown
below:
ncapt = 65536
next + nTAR
This means: with the continuous mode the RAM extension contains simply
the extended timer bits 17 through 31. No correction or calculation is necessary.
- Capture Mode With Up Mode — this method of capturing is exactly the
same as described above for the continuous mode. But the up mode uses
only a part of the timer register range. If the time interval to be captured
is longer than the content of the period register (CCR0), then a RAM extension (TIMAEXT) is necessary. This RAM extension is incremented with the
CCIFG0 or TAIFG interrupt and used with the calculations as shown below:
ncapt = next
(nCCR0
+ 1) + nTAR
- Capture Mode With Up/Down Mode — this method of capturing is exact-
ly the same as described above for the continuous mode. But the up/down
mode uses only a part of the timer register range and this part is counted
up and down. Therefore, the actual count direction should also be considered. If the time interval to be captured is longer than the doubled content
of the period register (CCR0), then a RAM extension (TIMAEXT) is necessary. This RAM extension is incremented with the CCIFG0 interrupt and
with the TAIFG interrupt. The LSB of the RAM extension (TIMAEXT) indicates the count direction. The RAM extension TIM32 must be initialized
to zero.
6-36
The Timer_A
LSB of TIMAEXT = 0 — Timer register counts upwards
ncapt = next
nCCR0 + n TAR
LSB of TIMAEXT = 1: Timer register counts downwards
ncapt = next
Where:
ncapt
next
nCCR0
nTAR
nCCR0 +
(nCCR0 –nTAR )
Resulting cycle value for captured signals (> 16 bits)
Content of the timer register RAM extension TIMAEXT
Content of the period register CCR0
Captured content of the timer register TAR (captured in CCRx)
Figure 6–10 illustrates the logic used for the capture/compare registers.
Overflow
Logic
CCISx1 CCISx0
CCIxA
CCIxB
GND
VCC
CAPx
0
1
2
3
0
15
Capture
Mode
CCMx1
0
0
1
1
Timer Bus
COVx
Capture/Compare Reg. CCRx
CCMx0
0 Disabled
1 Positive Edge
0 Negative Edge
1 Both Edges
0
15
Comparator X
Capture
0
CAPx
EQUx 0
Set_CCIFGx
Timer
Clock
Synchronize
Capture
1
SCSx
1
EN
Y
A
SCCIx
CCIx
Figure 6–10. Function of the Capture/Compare Registers (CCRx)
On-Chip Peripherals
6-37
The Timer_A
6.3.2.2.2 The Capture/Compare Control Registers CCTLx
Each capture/compare block has its own control word CCTLx. Figure 6–11 illustrates the organization of these control words — it is the same for all of them.
The main bit of these registers is the CAP bit (CCTLx.8), which determines if
the capture/compare block works in the capture mode or in the compare mode.
15
CCTLx
162h
to
16Ah
0
CAPTURE
MODE
INPUT
SELECT
rw–
(0)
rw–
(0)
SCS SCCI
un–
CAP
used
rw–
(0)
rw–
(0)
rw–
(0)
OUTMODx
rw–
(0)
rw–
(0)
CCIE CCI
rw–
(0)
r
OUT COV CCIFG
rw–
(0)
rw– rw–
(0) (0)
Figure 6–11.Timer Control Registers (CCTLx)
The POR signal resets all bits of the registers (CCTLx), but the PUC signal
does not affect them. This permits continuation with the same timing after a
watchdog reset, if this is necessary.
15
Capture/Compare Interrupt Flag CCIFG
CAPTURE
MODE
0
INPUT
SELECT
SCS SCCI
un–
CAP
used
OUTMODx
CCIE CCI
OUT COV
CCIFG
This flag indicates two different events depending on the mode in use:
J
Capture Mode
If set, it indicates that a timer register value was captured in the corresponding capture/compare register (CCRx).
J
Compare Mode
If set, it indicates that the timer register value was equal to the data
contained in the corresponding capture/compare register (CCRx).
The signal EQUx is also generated.
The CCIFG0 flag is reset automatically when the interrupt request is accepted.
It is a single-source interrupt flag and its interrupt vector is located at address
0FFF2h.
The reset of the CCIFG1 to CCIFGx flags depends on:
J
The timer vector register TAIV is used
The flag that determines the actual vector word (content of TAIV) is
reset automatically after the register TAIV is read.
J
The timer vector register TAIV is not used
The flags CCIFG1 to CCIFGx must be reset by the interrupt handler
6-38
The Timer_A
If the interrupt capability is not enabled for a capture/compare block then the
flag CCIFGx must be tested to check if the block x needs service. The CCIFG
flag must be reset by software for this case:
BIT
#CCIFG,&CCTLx
; Flag set?
JZ
NO_FLAG
; No continue
BIC
#CCIFG,&CCTLx
; Yes, reset flag
...
; Execute task for block x
Example 6–12. Capture/Compare Interrupt Flag CCIFG
See the examples in section The Timer Vector Register TAIV. Examples for the
treatment of the CCIFG flags are given there.
15
0
CAPTURE
MODE
Capture Overflow Flag COV
INPUT
SELECT
SCS SCCI
un–
CAP
used
OUTMODx
CCIE CCI
OUT COV
CCIFG
This flag indicates two different events depending on the mode in use:
J
Compare Mode
No function. The COV bit is always reset, independent of the state
of the capture input.
J
Capture Mode
The capture overflow flag COV is set if a second capture event occurred before the first capture sample was read out of the capture
register (CCRx). The COV flag allows the software to detect the loss
of synchronization and helps to reacquire synchronization. The COV
flag is not reset by the reading of the CCRx register and must be reset
by software.
Example 6–13. Capture Overflow Flag COV
The interrupt handler of capture/compare block 2 — running in capture mode
— checks first to see if a capture overflow occurred.
HCCR2
BIT
#COV,&CCTL2
; Capture overflow ?
JNZ
COV2
; Yes, handle it
MOV
&CCR2,CAPSTO2
; Store valid captured value
...
; Proceed with task
;
; Error handler for Capture/Compare Block 2
On-Chip Peripherals
6-39
The Timer_A
;
COV2
BIC
#COV,&CCTL2
; Reset overflow flag COV
...
; Check reason for overflow
RETI
15
0
CAPTURE
MODE
Output Bit OUT
INPUT
SELECT
SCS SCCI
un–
CAP
used
OUTMODx
CCIE CCI
OUT COV
CCIFG
The state of the output bit OUT defines the output signal (TAx) of output unit
x if the output mode 0 (output only) is selected. See section The Output Units
for details. The state of the output signal (TAx) is always indicated by this bit,
independent of the output mode in use. A modification of the output signal is
possible only if the output mode 0 is selected. The OUT bit allows the definition
of the start condition for PWM.
Example 6–14. Output Bit OUT
The output unit 3 is not used currently by Timer_A. To place TA3 in a defined
state, output mode 0 is used and output TA3 is reset.
BIC
#0E0h+OUT,&CCTL3
; Output only to OUT3: 0
If output TA3 should be set initially the following sequence is used:
BIC
#0E0h,&CCTL3
; Output only to OUT3
BIS
#OUT,&CCTL3
; Set OUT3
15
Capture/Compare Input Bit CCI
CAPTURE
MODE
0
INPUT
SELECT
SCS SCCI
un–
CAP
used
OUTMODx
CCIE CCI
OUT COV
CCIFG
The CCI bit allows to read the state of the selected capture input: the input signal (CCIxA at pin TAx, ACLK, Vcc or Vss) can be read independent of the selected mode. See figure 6–10 for details.
Example 6–15. Capture/Compare Input Bit CCI
The timer block 4 — running in capture mode — uses different software parts
for the leading and the trailing edges of the input signal. The interrupt handler
checks via the CCI4 bit which edge is the actual one.
; Initialization part: Capture both edges, TA4 input,
; synchronized capture, Capture Mode, interrupt enabled
;
6-40
The Timer_A
MOV
#CMBE+ISCCIA+SCS+CAP+CCIE,&CCTL4
; Initialize
...
HCCR4
.equ
$
; Interrupt handler Block 4
BIT
#CCI,&CCTL4
; Input signal positive?
JNZ
TA4POS
; Yes: leading edge occurred
...
; No, handle trailing edge
RETI
TA4POS
...
; Handle leading edge
RETI
15
Capture/Compare Interrupt Enable Bit CCIE
CAPTURE
MODE
0
INPUT
SELECT
SCS SCCI
un–
CAP
used
OUTMODx
CCIE CCI
OUT COV
CCIFG
This bit enables and disables the interrupt for the capture/compare interrupt
flag CCIFGx:
CCIE = 0: Interrupt is disabled
CCIE = 1: Interrupt is enabled
Interrupt is requested only if the CCIFG bit, the corresponding CCIE bit, and
the GIE bit (SR.3) are set. The sequence of the bit setting does not matter. If
two out of the above-mentioned three bits are 1 and the third is set afterward,
an interrupt will be requested.
Example 6–16. Capture/Compare Interrupt Enable Bit CCIE
The interrupt of timer block 2 is disabled. Now the interrupt should be enabled
again. But if the CCIFG2 flag is set, no interrupt should occur. All other bits in
register CCTL2 should retain their states.
BIC
#CCIE,&CCTL2
...
; Disable interrupt Block 2
; Continue
;
; The interrupt for Timer Block 2 is enabled again.
; A pending interrupt is cleared
;
BIC
#CCIFG,&CCTL2
; Reset CCIFG2 flag
BIS
#CCIE,&CCTL2
; Enable interrupt Block 2
On-Chip Peripherals
6-41
The Timer_A
15
CAPTURE
MODE
Output Mode Bits
0
INPUT
SELECT
SCS SCCI
un–
CAP
used
OUTMODx
CCIE CCI
OUT COV
CCIFG
These three bits define the behavior of the output unit x. Table 6–8 illustrates
the influence of the signals EQUx and EQU0 to the output signal TAx. The table
shows the actions when timer register TAR is equal to CCRx or CCR0. Table
6–8 is valid for all timer modes.
Table 6–8. Output Modes of the Output Units
OUTPUT MODE
NAME
TAR COUNTED UP TO CCRx
TAR COUNTED UP TO CCR0
0
Output only
TAx is set according to bit OUTx (CCTLx.2)
1
Set
Sets output
No action
2
Toggle/Reset
Toggles output
Resets output
3
Set/Reset
Sets Output
Resets output
4
Toggle
Toggles output
No action
5
Reset
Resets output
No action
6
Toggle/Set
Toggles output
Sets output
7
Reset/Set
Resets output
Sets output
See the examples given in the section The Output Units.
15
Capture/Compare Select Bit CAP
CAPTURE
MODE
0
INPUT
SELECT
SCS SCCI
un–
CAP
used
OUTMODx
CCIE CCI
OUT COV
CCIFG
The CAP bit defines if the capture/compare block works in the capture mode
or in the compare mode. This bit influences the function of nearly all other control bits located in the same capture/compare control register. See figure 6–10
for an explanation of the used logic.
CAP = 0: The compare mode is selected
CAP = 1: The capture mode is selected
Example 6–17. Capture/Compare Select Bit CAP
The use of this bit is explained with all other control bits.
Bit 9
Not used. Read as 0. To maintain software compatibility this bit should NOT
be set to 1.
6-42
The Timer_A
15
Synchronized Capture/Compare Input SCCI
J
CAPTURE
MODE
0
INPUT
SELECT
SCS SCCI
un–
CAP
used
OUTMODx
CCIE CCI
OUT COV
CCIFG
Compare Mode
The SCCI bit is the output of a transparent latch. This latch is in transparent mode as long as the timer register TAR is equal to CCRx. The
SCCI bit stores the selected capture input (ACLK, Vcc, or Vss) when
the timer register TAR becomes unequal to register CCRx.
J
Capture Mode
The state of this bit is not defined. No EQUx signal is available in capture mode.
Example 6–18. Synchronized Capture/Compare Input SCCI
The timer bock 4 — running in capture mode — uses different software parts
for the two possible states of the ACLK signal when the EQU4 signal comes
true. The interrupt handler checks via the SCCI4 bit the state of the ACLK signal when CCR4 was equal to the timer register (TAR). The read information
is shifted into a RAM word DATA.
; Initialization part: ACLK, Compare Mode, interrupt enabled
; Output Unit disabled, clear CCIFG
;
MOV
#ISCCIB+OMOO+CCIE,&CCTL4 ; Init. Timer_A
...
HCCR4
MOV
&CCR4,DATA
; Interrupt handler Block 4
BIT
#SCCI,&CCTL4
; ACLK signal –> Carry
JNZ
TA4POS
; ACLK was high during EQU4
RRC
DATA
; Shift captured info in DATA
...
; Execute task for low input
RETI
;
TA4POS
RRC
...
DATA
; Shift captured info in DATA
; Execute task for high input
RETI
15
Synchronization of Capture Signal Bit SCS
CAPTURE
MODE
0
INPUT
SELECT
SCS SCCI
un–
CAP
used
OUTMODx
CCIE CCI
OUT COV
CCIFG
The capture signal can be read in asynchronous mode or synchronized with
the selected timer clock . The SCS bit selects the mode to be used. See also
Figure 6–10 for a depiction of the internal logic.
On-Chip Peripherals
6-43
The Timer_A
J
SCS = 0
The asynchronous capture mode sets the CCIFG flag immediately
when the capture conditions are met (rising edge, falling edge, both
edges) and also immediately captures the timer register. This mode
may be used if the period of the captured data is much longer than
the period of the selected timer clock. The captured data may be incorrect for high input frequencies at terminal TAx.
J
SCS = 1
The synchronous capture mode — which is used normally — synchronizes the setting of the CCIFG flag and the capturing of the selected capture input with the selected timer clock. The captured data
is always valid.
Example 6–19. Synchronization of Capture Signal Bit SCS
See Example for Capture Compare Input bit CCI.
15
0
CAPTURE
MODE
Capture/Compare Input Selection Bits
INPUT
SELECT
SCS SCCI
un–
CAP
used
OUTMODx
CCIE CCI
OUT COV
CCIFG
These two bits select the input signal to be captured. The operation for the captured signal is different for capture mode and compare mode:
J
Compare Mode
The selected input signal is read and stored with the EQUx signal.
See the description of the SCCI bit, above.
J
Capture Mode
The selected input signal captures the timer register TAR into the
capture/compare register CCRx when the conditions defined in the
capture mode bits are met. See the description of the capture mode
bits below.
Table 6–9. Capture/Compare Input Selection Bits (MSP430x33x)
INPUT SELECTION BITS
INPUT SIGNAL
0
CCIxA
Signal at the external pin TAx is selected
1
CCIxB
ACLK is selected
2
VSS
VCC
3
COMMENT
For software capturing
For software capturing
15
Capture Mode Selection Bits
CAPTURE
MODE
0
INPUT
SELECT
SCS SCCI
un–
CAP
used
OUTMODx
CCIE CCI
OUT COV
CCIFG
These two bits select the capture operation for the input signal to be captured:
6-44
The Timer_A
J
Compare Mode
No function.
J
Capture Mode
The content of the timer register TAR is stored in the capture/
compare register CCRx when the capture condition is true for the selected input signal. The capture conditions are listed in Table 6–10.
Table 6–10. Capture Mode Selection Bits
CAPTURE MODE BITS
COMMENT
0
Capture mode is disabled
1
Capturing is done with the rising edge (0 to 1)
2
Capturing is done with the falling edge (1 to 0)
3
Capturing is done for both edges
Example 6–20. Capture Mode Selection
The capture/compare block 3 — running in capture mode — measures the period of the input signal CCI3A at terminal TA3. The measurement is made continuously between two rising edges. The calculated period is stored in the RAM
location PERIOD for the use by the background software. The actual value of
CCR3 is stored in OLDVAL for the next calculation. Timer_A uses the continuous mode.
; Initialization part: Capture rising edge, TA3 input,
; synchronous capture, Capture Mode, interrupt enabled
;
PERIOD
.equ
0200h
; Calculated period
OLDVAL
.equ
0202h
; Storage of last pos. edge time
MOV
#CMPE+ISCCIA+CAP+CCIE+SCS,&CCTL3
;
; Init.
...
HCCR3
.equ
$
; Interrupt handler Block 3
PUSH
&CCR3
; Captured TAR, rising edge
MOV
@SP,PERIOD
SUB
OLDVAL,PERIOD
; New – old = period
POP
OLDVAL
; For next calculation
RETI
On-Chip Peripherals
6-45
The Timer_A
6.3.2.2.3 The Period Register CCR0
The purpose of register CCR0 changes with the used timer mode.
- Continuous Mode — if this mode is used, CCR0 is a capture/compare
register exactly like the other four registers (CCR1 to CCR4). See section
The Timer_A Modes for details.
- Up Mode or Up/Down Mode — with one of these modes selected, the
register CCR0 works as the period register for the Timer_A, which defines
the length of the timer period. Whenever the timer register (TAR) reaches
the value of CCR0 (EQU0 = 1), the following actions occur, depending on
the mode in use:
J
Up Mode
The timer register is cleared with the next timer clock and restarts
from the value 0. This continues automatically without any software
intervention necessary. See section The Timer_A Modes.
J
Up/Down Mode
The timer register changes the count direction and starts to count
down to 0 with the next timer clock. If 0 is reached, the timer register
counts up again with the next timer clock until the value of CCR0 is
reached again. This continues automatically without any further software intervention necessary. See section The Timer_A Modes.
With the up mode or up/down mode selected, the EQU0 signal is valid if the
timer register (TAR) equals the period register (CCR0), or if it is greater than
CCR0. This is not the case for the other registers (CCRx).
The value 0 is not a valid content for the period register: the Timer_A blocks.
The content of the period register CCR0 is not modified normally. The timer
period is a constant value (50 µs for a repetition rate of 20 kHz — this means
200 cycles for a 4 MHz MCLK). But this value may also be modified if necessary.
6-46
The Timer_A
6.3.3
Timer Modes
Timer_A provides three different operating modes as well as the stop mode:
- Continuous Mode — the normal mode, except when high-speed PWM
generation is necessary
- Up Mode — used for high-speed, asymmetric PWM generation
- Up/Down Mode — used for high-speed, symmetric PWM generation
- Stop Mode — Timer_A is halted, all control bits retain their status
One of the advantages of Timer_A is the absolute synchrony of all timings and
output signals. This is due to the single timer register (TAR) that controls all
timings. This synchrony is very important for the interdependence of timings,
for example, if the MSP430 is used with a 3-phase digital motor control application (DMC).
The equations shown in the next sections use the following abbreviations:
∆t
t
tpw
∆n
n
k
fCLK
nCCR0
Time interval between two similar interrupts
Time e.g. period of a PWM signal
Pulse width of a PWM signal
Cycle value added to a CCRx register (timer clock cycles)
Number — content of a register (CCRx)
Predivider constant of the input divider (1, 2, 4 or 8)
Input frequency at the input divider input of Timer_A
Content of the period register CCR0
[s]
[s]
[s]
[Hz]
The calculation formulas and explanations for the capture mode are given in
the section Capture/Compare Blocks.
6.3.3.1
The Continuous Mode
This mode allows up to five completely independent, synchronous timings.
The capture/compare register, CCR0, works exactly the same as the other
registers (CCRx) when running in continuous mode.
Note:
The signal EQU0 has the same influence on the Mode Control Logic as it
does in the other timer modes. This means that only the Set, Reset, and
Toggle modes should be used if independent output signals are desired.
Figure 6–12 shows two independent timings generated by capture/compare
registers CCR0 and CCR1. The content of the capture/compare registers
On-Chip Peripherals
6-47
The Timer_A
(CCRx) is updated by software during each interrupt sequence by the addition
of a calculated value, ∆n. The value ∆n represents a time interval, ∆t, expressed in timer clock cycles. The software is described below. See the example for details.
The formulas for a given time interval, ∆t, respective the corresponding cycle
value ∆n are:
∆t =
∆t fCLK
∆n k
→ ∆n =
k
fCLK
The limitation for ∆n is:
∆n < 2 16
If this limitation is not given, a RAM extension for the timer register and the capture/compare registers must be used.
The number of timer steps between two equal timer register contents is 65536
(10000h). If the time interval ∆n is smaller than 65536, no checks for overflow
are necessary between two interrupts. The calculated next register content is
always correct.
FFFFh
1h
FFFEh
0h
0FFFFh
CCR1c
CCR0f
CCR1g
CCR0c
CCR0e
CCR0b
CCR1e
CCR1b
CCR1a
CCR0a
CCR1d
CCR1f
CCR0d
CCR0g
0h
CCR1h
Interrupt Events:
Example EQU0
∆ t0
Example EQU1
∆ t1
Figure 6–12. Two Different Timings Generated With the Continuous Mode
6-48
The Timer_A
Example 6–21. Continuous Mode
The software for the example illustrated in figure 6–12 is shown below. The
system clock frequency is 1.048 MHz. capture/compare Block 0 — running in
compare Mode — uses a constant interrupt repetition rate of 20971 cycles
(equivalent to ∆t0 = 20.0 ms @ 1.048 MHz), capture/compare Block 1 — running in compare mode — uses 17476 cycles (equivalent to ∆t1 = 16.67 ms).
These cycle values are added to the corresponding capture/compare registers, CCR0 and CCR1, respectively. They define the time for the next interrupt
(previous cycle count + number of cycles ∆n).
The capture/compare block 2 runs in capture mode. It checks if the time interval between two positive input edges is shorter than a given value stored in
MIN. If this is the case, the error byte ERR is set to 1.
; Initialization of the Timer_A: Cont. Mode, /1, interrupt
; enabled, MCLK = 1.048MHz. Output Units 0 and 1 not used.
;
INIT
MOV
#ISMCLK+CLR+TAIE,&TACTL ; Prepare Timer_A
MOV
#OMOO+CCIE,&CCTL0 ; CCR0: timing only
MOV
#OMOO+CCIE,&CCTL1 ; CCR1: timing only
MOV
#CMPE+SCS+CAP+CCIE,&CCTL2 ; CCR2: capt. TA2
MOV
#20971,&CCR0
; delta t0 = 20ms
MOV
#17476,&CCR1
; delta t1 = 16.6667ms
BIS.B
#TA2,&P3SEL
; P3.5 (CCI2A) Timer_A input
BIS
#MCONT,&TACTL
; Start initialized timer
....
; Continue
;
; C/C Block 0 uses a repetition rate of 20971 cycles (20ms)
;
TIMMOD0
.EQU
$
; Start of handler6
ADD
#20971,&CCR0
; Prepare next INTRPT
...
; Task0 starts here
RETI
;
;
; Interrupt handlers for Capture/Compare Blocks 1 to 4.
; (The C/C Blocks 3, 4 and timer overflow are not shown)
;
TIM_HND
.EQU
$
; Interrupt latency time
On-Chip Peripherals
6-49
The Timer_A
ADD
&TAIV,PC
RETI
TIMOVH
; Add Jump table offset
; TAIV = 0: No interrupt
JMP
TIMMOD1
; TAIV = 2: C/C Block 1
JMP
TIMMOD2
; TAIV = 4: C/C Block 2
JMP
TIMMOD3
; TAIV = 6: C/C Block 3
JMP
TIMMOD4
; TAIV = 8: C/C Block 4
...
; TAIV = 10: Timer OVFL
;
; C/C Block 1 uses a repetition rate of 17476 cycles (16.67ms)
;
TIMMOD1
.EQU
$
; Vector 2: C/C Block 1
ADD
#17476,&CCR1
; Add time interval
...
; Task1 starts here
RETI
; Back to main program
;
; C/C Block 2 checks if the time interval between two pos.
; input edges is shorter than a given value in MIN
;
TIMMOD2
COV2
RET2
.EQU
$
; Vector 4: C/C Block 2
BIT
#COV,&CCTL2
; Frequency much too high?
JNZ
COV2
; Yes, overflow!
PUSH
&CCR2
; Time of last transition
SUB
OLDC2,0(SP)
; Time difference to stack
ADD
@SP,OLDC2
; Old + difference = new
CMP
@SP+,MIN
; Time interval >= MIN
JLO
RET2
; Yes, ok
MOV.B
#1,ERR
; No, set error state 1
BIC
#COV,&CCTL2
; Reset overflow flag
RETI
; Back to main program
The tasks started by the interrupt handlers are not shown; these include:
- Incrementing software counters
- Checks after regular time intervals (keyboard, watchdog reset, etc.)
- Input tests
- Update of status bytes, etc.
- Measurement intervals
- Frequency generation with the output units
6-50
The Timer_A
6.3.3.2
The Up Mode
The up mode is mainly used for the generation of asymmetric PWM signals.
These PWM signals are absolutely synchronous due to the single timer register used for all signals. The period of the PWM repetition frequency is loaded
into the period register (CCR0) and the pulse width for each of the outputs, TA1
through TA4, is loaded into the capture/compare registers, CCR1 through
CCR4. The formula for a given timer period, t, with respect to the corresponding cycle value nCCR0 is (nCCR0 < 65536):
t =
(nCCR0 + 1) k
fCLK
! nCCR0 =
t fCLK
–1
k
The formula for a given pulse width tpw and the corresponding cycle value n
(the content of CCRx) is (n < 65536):
tpw =
tpw fCLK
n k
! n =
k
fCLK
As long as no modifications to the period register or the capture/compare registers are made, the PWM signals are repeated without any CPU intervention
necessary. The number of timer clock cycles between two equal timer register
contents is nCCR0 +1.
On-Chip Peripherals
6-51
The Timer_A
CCR0
2h
CCR0–1
1h
0h
CCR0–2
0FFFFh
CCR0
CCR1
CCR2
0h
t
CCR1:
Output Mode 2: PWM Toggle/Reset or
Output Mode 3: PWM Set/Reset
TA1 Output
tpw1
CCR2:
Output Mode 6: PWM Toggle/Set or
Output Mode 7: PWM Reset/Set
TA2 Output
tpw2
CCR0:
Output Mode 4: PWM Toggle
TA0 Output
EQU2
EQU0
TIMOV
EQU1
EQU2
EQU0
TIMOV
EQU1
EQU2
EQU0
TIMOV
Interrupts Generated
Figure 6–13. Three Different Asymmetric PWM Timings Generated With the Up Mode
If the timer register (TAR) reaches the content of capture/compare register
CCRx (EQUx = 1), with compare mode selected for capture/compare block x,
then the content of the output unit x is modified. Depending on the output mode
defined in the control register CCTLx, the output is toggled, set, reset, or not
affected. If the interrupt for the capture/compare block is enabled, an interrupt
is also generated.
If the timer register (TAR) counts up to the content of the period register CCR0
(EQU0 = 1), then the timer register (TAR) is reset to 0 with the next timer clock
and the content of the output units are toggled, set, reset, or not affected, depending on the selected output mode in control register CCTLx. The timer register continues with the counting starting at 0. If the interrupt for the reaching
of CCR0 is enabled, then an interrupt is also requested. See Figure 6–13.
6-52
The Timer_A
Notes:
The three interrupts caused by the TAIFG flag, the CCIFG0 flag, and CCIFGx
flags do not occur simultaneously if used with the up mode:
- The CCIFGx flag is set when the capture/compare register x equals the
timer register (TAR) (EQUx = 1)
- The CCIFG0 flag is prepared when the timer register equals the period
register CCR0 (EQU0 = 1). The CCIFG0 flag is delayed one timer clock cycle
and set, therefore, together with the TAIFG flag (timer register TAR contains
0)
-
The TAIFG flag is set when the timer register is reset to 0 (TIMOV = 1)
This means for the up mode: only one interrupt handler is necessary together
for the TAIFG flag and the CCIFG0 flag.
If the period register CCR0 contains 0, then the timer register TAR continues
counting until it also reaches 0. Then the counting stops until a nonzero value
is written to CCR0.
Example 6–22. Three Different Asymmetric PWM Timings Generated With the Up Mode
The software for the example illustrated in figure 6–13 is shown below. capture/compare block 1 generates a negative pulse with output unit 1, capture/
compare block 2 generates a positive pulse with the output unit 2 and capture/
compare block 0 (the period register block) outputs an evenly spaced output
pulse with its output unit 0. The initializing part of the example is also shown.
If no tasks must be executed (here tasks 0, 1, and 2), the interrupts may be
switched off; the pulse generation continues.
; Initialization of the Timer_A: Up Mode, /1, interrupt
; enabled, MCLK = 3.8MHz
;
INIT
MOV
#ISMCLK+D1+CLR+TAIE,&TACTL
MOV
#OMT+CCIE,&CCTL0
; Prepare Timer_A
MOV
#OMTR+CCIE,&CCTL1 ; CCR1: toggle/reset TA1
MOV
#OMRS+CCIE,&CCTL2 ; CCR2: reset/set TA2
MOV
#190–1,&CCR0
; fccr0 = 20kHz
MOV
#114,&CCR1
; tpw1 = 30us
MOV
#48,&CCR2
; tpw2 = 12.6us
BIS.B
#TA2+TA1+TA0,&P3SEL; Enable TA2, TA1 TA0
BIS
#MUP,&TACTL
; CCR0: toggle TA0
; Start init. timer. Up Mode
On-Chip Peripherals
6-53
The Timer_A
....
; Continue
; Interrupt handler for the Period Register CCR0
; C/C Block 0 outputs a signal with 1/2 of the frequency
; of the other C/C Blocks (50%/50%). It also increments the
; RAM extension of the Timer Register TIMAEXT. It is
; initialized to: toggle (EQU0)
;
TIMMOD0 .EQU
$
; Start of handler
INC
TIMAEXT
; Incr. timer extension
...
; Task0 starts here
RETI
;
;
; Interrupt handlers for Capture/Compare Blocks 1 to 4.
;
TIM_HND .EQU
$
; Interrupt latency time
ADD
&TAIV,PC
; Add Jump table offset
RETI
; TAIV = 0: No interrupt
JMP
TIMMOD1
; TAIV = 2: C/C Block 1
JMP
TIMMOD2
; TAIV = 4: C/C Block 2
JMP
TIMMOD3
; TAIV = 6: C/C Block 3
JMP
TIMMOD4
; TAIV = 8: C/C Block 4
TIMOVH
...
; TAIV = 10: Timer OVFL
;
; C/C Block 1 outputs a negative pulse automatically. It is
; initialized to: toggle/reset (EQU1/EQU0)
;
TIMMOD1 .EQU
$
; Vector 2: C/C Block 1
...
; Task1 starts here
RETI
; Back to main program
;
; C/C Block 2 outputs a positive pulse automatically. It is
; initialized to: reset/set (EQU2/EQU0)
;
TIMMOD2 .EQU
$
; Vector 4: C/C Block 2
...
; Task2 starts here
RETI
; Back to main program
The tasks started by the interrupt handlers are not shown; these may include:
- Pulse width modulation for control purposes with the output units
- DC generation (DAC) with the output units
- Tasks like those shown for the continuous mode, but with special treat-
ment due to the short period. The RAM extension (TIMAEXT) must therefore be taken into account for measurement.
6-54
The Timer_A
6.3.3.3
The Up/Down Mode
The up/down mode is a symmetric PWM mode. Up to four absolutely synchronous PWM outputs may be generated. The advantage of this PWM mode is
a minimum of generated harmonics due to the distributed switching of the output units. The half period of the PWM repetition frequency is loaded into the
capture/compare register (CCR0) and a calculated number for the pulse width
for each one of the used outputs (TAx) is loaded into the capture/compare registers (CCRx).
The formulas for a given time period, t, of the Timer_A frequency with respect
to the corresponding cycle value, nCCR0, are:
t fCLK
2 nCCR0 k
! nCCR0 =
2 k
fCLK
t =
The formulas for a given pulse width time, tpw, with respect to the corresponding cycle value, n, are:
tpw fCLK
2 n k
! n =
2 k
fCLK
tpw =
As long as no modifications to the period register or the capture/compare registers are made, the PWM signals are repeated indefinitely without any CPU
intervention.
CCR0
1h
CCR0–1
CCR0–1
1h
0h
0FFFFh
CCR0
CCR1
CCR3
0h
t
CCR3:
Output Mode 6: PWM Toggle/Set or
Output Mode 4: Toggle
TA3 Output
tpw3
TA1 Output
TIMOV
tpw1
EQU3
EQU0
EQU3 TIMOV EQU3
EQU1 EQU1
EQU0
EQU3
EQU1 EQU1
CCR1:
Output Mode 2: PWM Toggle/Reset or
Output Mode 4: PWM Toggle
Interrupts Generated
Figure 6–14. Two Different Symmetric PWM Timings Generated with the Up/Down Mode
On-Chip Peripherals
6-55
The Timer_A
If the timer register (TAR) reaches the content of capture/compare register,
CCRx (EQUx = 1), and the corresponding capture/compare block is switched
to the compare mode, then the content of output unit x is modified (toggled,
set, reset, or not affected) depending on the output mode of the control register
(CCTLx). If the interrupt for the capture/compare block is enabled, then an interrupt is also generated.
The timer register TAR reverses its count direction when it reaches the content
of the period register (CCR0), and the content of output unit x is modified again
(toggled, set, reset, or not affected) depending on the output mode of the control register (CCTLx). If the interrupt for the reaching of CCR0 is enabled, then
an interrupt is also requested. If the timer register reaches the value 0 again,
it starts counting upward with the next timer clock cycle. If the interrupt for the
reaching of 0 is enabled (TIMOV = 1), then an interrupt is also requested with
the TAIFG flag. See Figure 6–14.
Note:
If the period register (CCR0) contains 0, then the timer register (TAR) continues counting until it also reaches 0. Then the counting stops until a nonzero
value is written to CCR0.
Example 6–23. Two Different Symmetric PWM Timings Generated With the Up/Down
Mode
The software for the example illustrated in figure 6–14 is shown below. capture/compare block 3 generates a negative pulse with output unit 3 at the output TA3. capture/compare block 1 generates a positive pulse — symmetrically
to the zero point — with the output unit 1 at the output TA1. The initializing part
of the example is also shown. If no software tasks must be executed, the interrupts for the capture/compare blocks 0, 1, and 3 may be switched off.
TIMAEXT
.EQU
200h
; RAM extension (bits 17 – 23)
; Initialization of Timer_A: Up/Down Mode, /2, interrupt
; enabled, MCLK = 3.8MHz
;
INIT
6-56
MOV
#ISMCLK+D2+CLR+TAIE,&TACTL
; Prepare Timer_A
MOV
#OMOO+CCIE,&CCTL0 ; CCR0: normal I/O pin
MOV
#OMTR+CCIE,&CCTL1 ; CCR1: toggle/reset TA1
MOV
#OMTS+CCIE,&CCTL3 ; CCR3: toggle/set TA3
MOV
#190,&CCR0
; fccr0 = 5kHz
MOV
#114,&CCR1
; tpw1 = 120.0us
MOV
#48,&CCR3
; tpw3 = 50.5us
The Timer_A
BIS.B
#TA3+TA1,&P3SEL
; Enable TA3 and TA1 outputs
BIS
#MUPD,&TACTL
; Start initialized timer
....
; Continue
; Interrupt handler for the Period Register CCR0
; Block 0 sets the RAM extension TIMAEXT of the Timer Register
; (count down). The LSB of TIMAEXT indicates the
; count direction:
LSB = 0: count up
;
LSB = 1: count down
; This indication is necessary if the Capture Mode is used.
; The count direction indication is self–synchronizing
;
TIMMOD0
.EQU
$
; Start of handler
BIS
#1,TIMAEXT
; LSB = 1: count down now
...
; Task0 starts here
RETI
;
;
; Interrupt handlers and decision (only 3 handlers shown)
;
TIM_HND
.EQU
$
; Interrupt latency time
ADD
&TAIV,PC
; Add Jump table offset
RETI
; TAIV = 0: No interrupt
JMP
TIMMOD1
; TAIV = 2: C/C Block 1
JMP
TIMMOD2
; TAIV = 4: C/C Block 2
JMP
TIMMOD3
; TAIV = 6: C/C Block 3
JMP
TIMMOD4
; TAIV = 8: C/C Block 4
;
; Timer Register reached zero: LSB is set to 0 (count up)
;
TIMOVH
.EQU
$
; TIMOV interrupt
INC
TIMAEXT
; TAIV = 10: Block 5
RETI
;
;
; C/C Block 1 outputs a positive pulse automatically.
; Initialized to: toggle/reset (EQU1/EQU0)
;
TIMMOD1
.EQU
$
; Vector 2: C/C Block 1
On-Chip Peripherals
6-57
The Timer_A
...
; Task1 starts here
RETI
; Back to main program
;
; C/C Block 3 outputs a negative pulse automatically.
; Initialized to: toggle/set (EQU3/EQU0)
;
TIMMOD3
.EQU
$
; Vector 6: C/C Block 3
...
; Task3 starts here
RETI
; Back to main program
The tasks started by the interrupt handlers are not shown; these may be:
- Symmetric pulse width modulation for control purposes with the output
units
- DC generation (DAC) with the output units
- Tasks like those shown for the continuous mode, but with special treat-
ment due to the changing count direction and short period. The RAM extension TIMAEXT must therefore be taken into account for measurements.
6.3.3.4
The Stop Mode
The stop mode halts the timer register without the change of any control register. The timer actions can then continue on from exactly where they were
stopped.
Example 6–24. The Stop Mode
The Timer_A running in up/down mode is stopped. After a certain time, it
should continue from exactly where it was halted, including the count direction.
BIC
#MUPD,&TACTL
...
BIS
6-58
; Halt Timer_A
; Proceed without Timer_A
#MUPD,&TACTL
; Continue with Up/Down Mode
The Timer_A
6.3.3.5
Applications of the Timer Modes
Table 6–11 gives an overview of the different applications of the Timer _A
modes, together with the capture/compare registers.
Table 6–11. Combinations of Timer_A Modes
COMBINATIONS
CAPTURE/COMPARE REGISTER 0
CAPTURE/COMPARE REGISTER X
Continuous Mode
Compare
Com
are register
Capture
Ca
ture register
-
Interrupt timing
-
Slow PWM generation
-
TRIAC timing
-
SW/HW UART (transmitter)
-
SW/HW SPI
-
Capturing of internal and external events
-
SW/HW UART (receiver)
-
Revolutions measurement
Same as for capture/compare register 0
Up Mode
Compare
Com
are register
Capture
Ca
ture register
Fixed to period
eriod register
Not possible
ossible due to period
eriod register function
-
Interrupt timing
-
Asymmetric PWM generation
-
Digital motor control
-
TRIAC timing
-
SW/HW UART (transmitter)
-
Capturing of int. and ext. events
-
SW/HW UART (receiver)
-
Revolutions measurement
-
Symmetric PWM generation
-
Digital motor control
-
(Capturing of internal and external events is
difficult due to up/down counting)
Up/Down Mode
Compare register
Capture register
Fixed to period register
Not possible due to period register function
On-Chip Peripherals
6-59
The Timer_A
6.3.4
6.3.4.1
The Timer_A Interrupt Logic
Interrupt Sources
Several interrupt sources exist within the Timer_A hardware. An interrupt is requested only if the interrupt of the corresponding timer block is enabled (interrupt enable bit TAIE or CCIEx is set) and the general interrupt enable bit GIE
(SR.3) is also set. If more than one interrupt is pending, then the interrupt with
the highest priority is first in line for servicing. An interrupt is also requested
immediately if any interrupt enable bit (CCIEx or TAIE) is set and the corresponding interrupt flag and GIE (SR.3) were already set.
Timer Register Block — The timer interrupt flag TAIFG requests an interrupt
if the timer register reaches 0 and the interrupt enable bit TAIE is set. The
TAIFG flag is set, dependent on the actual mode:
- Continuous Mode — after the overflow from 0FFFFh to 0000h
- Up Mode — one timer clock after the timer period in CCR0 is reached
- Up/Down Mode — when the value 0000h is reached during the count-
down
Capture/Compare Block x — The capture/compare interrupt Flags CCIFGx
are set if one of the following conditions is met. An interrupt is requested only
if the corresponding interrupt enable bit CCIEx and GIE are also set.
- Capture Mode — an input value is captured in register CCRx (the capture
condition at the selected input came true)
- Compare Mode — the timer register counted to the value contained in
register CCRx
6.3.4.2
Interrupt Vectors
Two interrupt vectors are associated with the Timer_A module.
- The single-source vector for the capture/compare register CCR0 has the
highest priority of all Timer_A interrupts. The capture/compare register
CCR0 is used to define the timer period during the up mode and the up/
down mode. Therefore, it requires the fastest service. This interrupt vector
is located at address 0FFF2h.
- The multi-source interrupt vector for all other interrupt sources of the Tim-
er_A (capture/compare registers x and Timer Overflow). A 16-bit vector
word — the timer vector register (TAIV) — indicates the interrupt with the
6-60
The Timer_A
highest priority. The register TAIV is normally added to the Program Counter allowing a simple and fast decision without the need for a time consuming skip chain. See the section explaining the timer vector register (TAIV)
for details. The multi-source interrupt vector is located at address 0FFF0h.
All interrupt flags (CCIFGx and TAIFG) can be accessed by the CPU. The internal priorities of the Timer_A are listed in Table 6–12 (for the MSP430x33x
configuration).
Table 6–12. Timer_A Interrupt Priorities
INTERRUPT PRIORITY
Highest
Lowest
FLAG NAME
VECTOR ADDRESS
Capture/Compare Register 0
INTERRUPT SOURCE
CCIFG0
0FFF2h
Capture/Compare Register 1
CCIFG1
0FFF0h
Capture/Compare Register 2
CCIFG2
0FFF0h
Capture/Compare Register 3
CCIFG3
0FFF0h
Capture/Compare Register 4
CCIFG4
0FFF0h
TAIFG
0FFF0h
Timer Overflow
Example 6–25. Timer_A Vectors
The following software shows a possible definition for the Timer_A vectors.
; Timer_A Interrupt Vectors
;
.SECT
”TIMVEC”,0FFF0h
; Timer_A Vector Address
.WORD
TIM_HND
; Vector for all Blocks except 0
.WORD
TIMMOD0
; Vector for Timer Block 0
.SECT
”INITVEC”,0FFFEh
; RESET Vector
.WORD
INIT
; Start address
On-Chip Peripherals
6-61
The Timer_A
6.3.5
The Output Units
Each capture/compare register (CCRx) is connected to an output unit x that
controls the corresponding pulse output (TAx). Eight output modes exist and
can be selected individually for each capture/compare block by the three output mode bits (OUTMODx) located in the capture/compare control register
(CCTLx). For Table 6–13, it is assumed, that the corresponding control signal
P3SEL.y is set to 1. See Figure 6–17 for details. The rightmost column of Table
6–13 indicates the behavior of the output TAx if the EQUx and EQU0 signals
are valid simultaneously.
Table 6–13. Output Modes of the Output Units
OUTPUT MODE
MODE NAME
ACTION FOR EQUx
ACTION FOR EQU0
ACTION FOR EQUx .and. EQU0
0
Output only
TAx is set according to bit OUTx (CCTLx.2)
1
Set
Sets output TAx
No action
Sets output TAx
2
Toggle/Reset
Toggles output TAx
Resets output TAx
Sets output TAx
3
Set/Reset
Sets output TAx
Resets output TAx
Sets output TAx
4
Toggle
Toggles output TAx
No action
Toggles output TAx
5
Reset
Resets output TAx
No action
Resets output TAx
6
Toggle/Set
Toggles output TAx
Sets output TAx
Resets output TAx
7
Reset/Set
Resets output TAx
Sets output TAx
Resets output TAx
The dependence of the output units on the EQU0 signal (shown in Table 6–13)
limits the output unit 0 to the following output modes if the up mode or up/down
mode is used (the other four output modes output the static signals shown in
the rightmost column of Table 6–13).
- Output Mode 0
Output Mode — TA0 outputs content of the OUTx bit (CCTLx.2)
- Output Mode 1
Set output — TA0 is set from the EQU0 signal
- Output Mode 4
Toggle output — TA0 is toggled from the EQU0 signal
- Output Mode 5
Reset output — TA0 is reset from the EQU0 signal
If the output mode needs to be changed during the program run (from Set to
Reset, for example), then the output signal TAx will not change its state falsely
6-62
The Timer_A
if at least one of the three OUTMOD bits retains the 1 state. If this is not the
case, (with a change from output mode set to toggle, for example — mode 1
to mode 4), then for a transition time, the output mode 0 may be addressed and
will transfer the content of the bit OUTx into the output flip-flop. This may cause
glitches at the output terminal.
Figure 6–15 shows the unsafe output mode changes. It indicates that all
changes via the output mode 7 are safe.
Mode Transitions
Output Modes 0
Output only
1
2
3
4
5
6
7
Set
Toggle/Reset
Set/Reset
Toggle
Reset
Toggle/Set
Reset/Set
Figure 6–15. Unsafe Output Mode Changes
Example 6–26. Safe Output Mode Changes
The following code may be used for safe changes.
; To avoid Output Mode 0, the change is made via Output Mode 7
; Example: Output Mode x to 4
;
BIS
#OMRS,&CCTL1
; Set Output Mode 7 (OMRS)
BIC
#OMSR,&CCTL1
; Reset LSBs with Output Mode 3
If one of the safe changes is possible, then only the different bits are changed:
; Change Output Mode from Set to Reset (1 to 5)
;
BIS
;
#OMT,&CCTL1
; Set MSB (OMT) for 1 to 5
...
; Change Output Mode from Reset to Set (5 to 1)
;
BIC
#OMT,&CCTL1
; Reset MSB (OMT) for 5 to 1
If, for initialization purposes, a certain state of the output signal TAx is necessary, then the output mode 0 can be used. For the output mode toggle, the output signal OUTx is reset:
; Reset output signal TA1 and switch Output Unit 1 to toggle
; mode
On-Chip Peripherals
6-63
The Timer_A
;
BIC
#OMRS+OUT,&CCTL1
; OUT1 = 0, Output mode = 0
BIS
#OMT,&CCTL1
; Start toggle mode wit OUT1 = 0
If the input signals EQU0 and EQUx occur simultaneously, then the output signal Outx behaves as shown in the rightmost column of Table 6–13.
Figure 6–16 illustrates the simplified structure of the output units. All of the inputs that influence the behavior of the output Outx are shown. The reason that
some mode changes are safe and some are not is the NOR gate that decodes
the output mode 0.
TAx
Timer Clock
EQUx
OUTx(CCTLx.2)
Logic
Output Signal Outx
Set
EQU0
D
Output
Timer Clock
Q
To Output Logic TAx
Reset
POR
OUTx
Output Mode 0
Output Mode Bits
(CCTLx.5–7)
Figure 6–16. Simplified Logic of the Output Units
6-64
The Timer_A
6.3.5.1
Output Unit I/Os
The bits located in the selection register P3SEL (address 01Bh) and the CAPx
bits (CCTLx.8) define the function of the Port3 pins (the MSP430C/P33x configuration is shown — Other family members may use a different implementation, but the principle is the same).
Table 6–14. Timer_A I/O–Port Selection
P3SEL.y = 0
P3SEL.y = 1
CAPx = 0
P3SEL.y = 1
CAPx = 1
Port I/O P3.0
Port I/O P3.0
Port I/O P3.0
Port I/O P3.1
Port I/O P3.1
Port I/O P3.1
Port I/O P3.2
Timer Clock input TACLK
Timer clock input TACLK
Port I/O P3.3
Output TA0
Capture input CCI0A
Port I/O P3.4
Output TA1
Capture input CCI1A
Port I/O P3.5
Output TA2
Capture input CCI2A
Port I/O P3.6
Output TA3
Capture input CCI3A
Port I/O P3.7
Output TA4
Capture input CCI4A
Figure 6–17 illustrates the Timer_A interface to the external world. Six Port3
I/O terminals (MSP430C33x) may be selected individually as normal
Port3 I/Os or as Timer_A I/Os. The control bit P3SEL.y selects the function:
- P3SEL.y = 0
The I/O pin is connected to the Port3 module (input or output)
- P3SEL.y = 1
The I/O pin is connected to the Timer_A module (TAx output or
CCIxA input)
On-Chip Peripherals
6-65
The Timer_A
P3SEL.y
P3DIR.y
I/O Direction
CAP.x
Port3 I/O
PWM Output
Capture Input
P3OUT.y
P3.y / TAx / CCIxA
Outx
P3IN.y
y=x+3
En
Capture Input CCIxA
Y
D
Figure 6–17. Connection of the Port3 Terminals to the Timer_A (MSP430C33x
Configuration)
Example 6–27. Port3 Output Control
The initialization for the use of the TA2 and TA1 outputs for PWM is shown.
They are disconnected from the Port3 logic by the setting of the bits P3SEL.5
and P3SEL.4.
;
; Initialize the Timer_A: MCLK, Stop Mode, INTRPT enabled, /2
;
MOV
#ISMCLK+D2+CLR+TAIE,&TACTL ; Define Timer_A
MOV
#200–1,&CCR0
; Define period 200 cycles
;
; Initialize Control Registers CCTL2 and CCTL1: Reset/set
; mode, INTRPT enabled, Compare Mode, clear flags
;
MOV
#OMRS+CCIE,&CCTL1 ; CCIFG1 = 0,
MOV
#OMRS+CCIE,&CCTL2 ; CCIFG2 = 0
;
; Initialize Capture Compare Registers to PWM duty
;
6-66
The Timer_A
MOV
#100,&CCR1
; 50% PWM
MOV
#50,&CCR2
; 25% PWM
;
; Prepare Timer_A Output Units TA2 and TA1 (P3.5 and P3.4)
;
MOV.B
#TA2+TA1,&P3SEL
; Connect to Output Units
BIS
#MUP,&TACTL
; Start Timer_A in Up Mode
;
6.3.5.2
Pulse Width Modulation in the Continuous Mode
The continuous mode is not intended for PWM, but may be used for this purpose in two ways. The timing can be controlled from:
- One capture/compare register only
- One capture/compare register and additional capture/compare register 0
6.3.5.2.1 One Capture/Compare Register only
The same capture/control register x sets and resets the output TAx. The output
modes toggle or alternating set and reset are used. For the second method
(Set and Reset), the interrupt handler modifies the output mode in addition to
the adding of the time interval to the register CCRx. PWM values near 0% and
100% must be realized with software. See also Section 6.3.6 The Limitations
of Timer_A.
The output modes and their usability for the first method of PWM in the continuous mode are listed below:
- Set Mode — used to get the output signal into the set state. It is necessary
to alternate with the reset mode to get a PWM output signal
- Toggle/Reset — not usable due to the influence of capture/compare reg-
ister 0
- Set/Reset — not usable due to the influence of capture/compare register
0
- Toggle — usable, but a defined start position must be initialized. Other-
wise, an inverted output signal is generated
- Reset Mode — used to get the output signal into the reset state. It is nec-
essary to alternate with the set mode to get a PWM output signal
On-Chip Peripherals
6-67
The Timer_A
- Toggle/Set — not usable due to the influence of capture/compare regis-
ter 0
- Reset/Set — not usable due to the influence of capture/compare register
0
0FFFFh
0h
Interrupt Event:
EQU1
TA1 Output Signal
Toggle or Alternating
Set and Reset
Output Mode To Set
Output Mode To Reset
Change Of Pulse Width
Figure 6–18. PWM Generation in the Continuous Mode (CCR1 only controls TA1)
6.3.5.2.2 One Capture/Compare Register and Additional Capture/Compare Register 0
The capture/compare register CCR0 has the same function as with the other
two timer modes: it switches back the PWM output TAx into a defined state.
Figure 6–19 shows PWM generation using the reset/set mode. This method
allows PWM with higher repetition rates than the method described previously.
With no pulse width modifications, the time interval between two interrupts are
always identical.
The capture/compare register 0 may be used for more than one PWM output
used this method. The output frequency of capture/compare register 0 may be
chosen in such a way that also supports other purposes — an auxiliary frequency output at TA0, for example. See also Figure 6–13.
The output modes and their usability for the second method of the continuous
mode are listed below:
- Set — used to get the output signal TAx into a defined set state initially.
- Toggle/Reset — usable, self-synchronizing PWM
- Set/Reset — usable, self-synchronizing PWM
6-68
The Timer_A
- Toggle — not usable due to the missing influence of capture/compare reg-
ister 0
- Reset Mode — used to get the output signal TAx into a defined reset state
initially
- Toggle/Set — usable, self-synchronizing PWM
- Reset/Set — usable, self-synchronizing PWM
0FFFFh
0h
Interrupt Events:
EQU0 Sets TA1
EQU1 Resets TA1:
Toggle/Set or Reset/Set
TA1 Output Signal
Mode To Set by
EQU0 Handler
Change Of Pulse Width
Mode To Reset
or Toggle by
EQU1 Handler
Figure 6–19. PWM Generation in the Continuous Mode (CCR0 and CCR1 control TA1)
Example 6–28. PWM near 0% and 100%
The PWM output values near 0% and 100% must be realized with special software code. A simple way to do this is to use the timer vector register (TAIV)
once more after each completed interrupt handler to check to see if another
timer interrupt is pending. The software example below shows this solution.
It is applicable to all PWM modes. See figure 6–19. It saves 9 to 11 cycles if
an additional Timer_A interrupt is pending.
PWMper
.EQU
333
; PWM period (Timer Clock cycles)
;
; Interrupt handler for the Period Register CCR0.
; To handle PWM duties near 0% or 100% a check is made if
; other timer interrupts are pendent: return to TIM_HND
On-Chip Peripherals
6-69
The Timer_A
;
TIMMOD0
.EQU
$
; Start of handler
INC
TIMAEXT
; Incr. timer extension
ADD
#PWMper,&CCR0
; Add period length to CCR0
...
; Task0 starts here
...
; Fall through to TIM_HND
;
; Interrupt handlers for Capture/Compare Blocks
;
TIM_HND
.EQU
$
; Interrupt latency time
ADD
&TAIV,PC
; Add Jump table offset
RETI
TIMOVH
; TAIV = 0: No interrupt
JMP
TIMMOD1
; TAIV = 2: C/C Block 1
JMP
TIMMOD2
; TAIV = 4: C/C Block 2
JMP
TIMMOD3
; TAIV = 6: C/C Block 3
JMP
TIMMOD4
; TAIV = 8: C/C Block 4
...
; TAIV = 10: Block 5
;
; C/C Block 1 returns to the timer interrupt handler after
; completion to look for pendent timer interrupts
;
TIMMOD1
.EQU
$
; Vector 2: C/C Block 1
ADD
#PWMper,&CCR1
; Add period length to CCR1
...
JMP
6.3.5.3
; Task1 starts here
TIM_HND
; Pendent INTRPTs ?
Pulse Width Modulation in the Up Mode
The up mode permits all pulse widths from 0% to 100% without any special
treatment necessary. The calculation software delivers results ranging from 0
to nCCR0+1. Like Figure 6–20 illustrates, the full range of PWM output signals
is possible.
The output modes and their usability for the up mode are listed below.
- Set Mode — used to get the output signal initially into a defined set state.
- Toggle/Reset — outputs self–synchronizing negative pulses without
CPU activity.
6-70
The Timer_A
- Set/Reset — outputs self–synchronizing negative pulses without CPU ac-
tivity.
- Toggle — this mode cannot be used with the up mode. It outputs a signal
with 50% duty and doubled period for all contents of register CCRx, except
for CCRx > CCR0. These contents retain the last state of output Outx due
to the missing EQUx signal.
- Reset Mode — used to get the output signal initially into a defined reset
state.
- Toggle/Set — outputs self-synchronizing positive pulses without CPU ac-
tivity.
- Reset/Set — outputs self-synchronizing positive pulses without CPU ac-
tivity.
Figure 6–20 illustrates the four usable output modes for PWM in the up mode.
Note:
No interrupts are generated from the capture/compare blocks x for CCRx =
0 and for CCRx > CCR0. For these two cases, a special treatment is necessary. See the software examples in section Software Examples for the Up
Mode.
CCRx = 0
CCRx = 1
CCRx = 2
CCRx = CCR0
CCRx > CCR0
4
3
Output Mode
2
TAR
0
1
Toggle/Set
Reset/Set
TAx
0%
Toggle/Reset
Set/Reset
TAx
100%
EQU0
20%
80%
EQU0
No EQUx Interrupt
40%
80%
60%
EQUx
20%
0%
EQU0
EQU0
EQU0
100%
EQUx
EQUx
EQU0
No EQUx Interrupt
Figure 6–20. PWM Signals at TAx in the Up Mode (CCR0 contains 4)
On-Chip Peripherals
6-71
The Timer_A
6.3.5.4
Pulse Width Modulation in the Up/Down Mode
The output modes and their usability for the up/down mode are listed below.
- Set Mode — used to get the output signal initially into a defined set state.
- Toggle/Reset — outputs self-synchronizing positive pulses without CPU
activity. The Timer_A hardware can produce all of the theoretically possible nCCR0+1 states. But special treatment is necessary if register CCRx
contains 0. Then the output signal Outx toggles only once per period,
which means the output shows a 50% duty and not 0%. See figure 6–21.
- Set/Reset — cannot be used with up/down mode.
- Toggle — should not be used with the up/down mode.
- Reset Mode — used to get the output signal initially into a defined reset
state.
- Toggle/Set — outputs self-synchronizing negative pulses without CPU
activity. See Toggle/Reset, above, for restrictions.
- Reset/Set — cannot be used with up/down mode.
As figure 6–21 also shows, the missing PWM values of 0% for toggle/reset and
100% for toggle/set can be output if CCRx contains a greater value than
CCR0.
Example 6–29. Pulse Width Modulation in the Up/Down Mode
The checking software for output mode toggle/reset is shown. All PWM values
from 1 to nCCR0 are valid. The value 0 is emulated by a number greater than
nCCR0. R5 contains the calculated PWM value.
; PWM value in R5 is checked to be in limits 1 to nCCR0
;
CMP
R5,&CCR0
; PWM value =< nCCR0?
JHS
L$1
; Yes, proceed
MOV
&CCR0,R5
; No, upper limit (100% PWM)
;
; If 0% PWM is needed: 0FFFFh to R5
;
L$1
6-72
TST
R5
; Zero value?
JNZ
L$2
; No, proceed
The Timer_A
MOV
L$2
#0FFFFh,R5
; Use largest, unsigned number
...
; Result in R5 is in limits
The above correction limits the maximum period length nCCR0 to 0FFFEh.
Figure 6–21 illustrates the two possible PWM modes for the up/down mode.
They correct themselves after one period, max.
CCRx = 0
CCRx = 1
3
3
2
Output Mode
2
1
1
3
3
2
2
1
0
1
0
CCRx = CCR0–1
3
3
2
2
1
1
0
CCRx = CCR0
3
3
2
2
1
1
0
CCRx > CCR0
3
3
2
2
1
1
0
Toggle/Set
50%
67%
33%
0%
100%
Toggle/Reset
50%
33%
67%
100%
0%
EQU0
EQU0
EQUx
EQU0
EQUx
EQU0
EQUx
Figure 6–21. PWM Signals at Pin TAx With the Up/Down Mode (CCR0 contains 3)
6.3.6
Limitations of the Timer_A
This section details how to check to see if the limitations imposed by the architecture of the Timer_A are not exceeded. The abbreviations used in this chapter are:
tintrpt
ptask
povhd
fMCLK
frep
uCPU
tILmax
Time for a complete interrupt sequence
[s]
Executed MCLK cycles for the task itself during the interrupt
handler (e.g. incrementing of a counter). The necessary
cycle count of an instruction depends on the addressing
modes used.
[s]
Sum of MCLK cycles for the overhead of an interrupt sequence.
See software overhead.
[s]
System clock frequency MCLK
[Hz]
Repetition rate of an event (e.g. an interrupt request)
[Hz]
CPU loading by a given task. Ranges from 0 to 1 (100%)
Maximum (worst case) of the interrupt latency time due to other
enabled interrupts
[s]
On-Chip Peripherals
6-73
The Timer_A
The execution time tintrpt for a complete interrupt sequence is the same for all
three timer modes:
tintrpt =
ptask + povhd
fMCLK
The software overhead povhd differs slightly for the three possible Timer_A interrupt sources:
- Capture/Compare Block CCR0
11 cycles (6 + 0 + 5)
- Capture/Compare Blocks CCR1 to CCR4
16 cycles (6 + 5 + 5)
- Timer Overflow TAIFG
14 cycles (6 + 3 + 5)
The software overhead povhd consists of three parts:
J
Getting to the first instruction of the interrupt handler by the CPU (6
cycles)
J
Decision part: addition of timer vector register (TAIV) to the program
counter and execution of the JMP instruction (0 to 5 cycles)
J
Return from interrupt instruction RETI (5 cycles).
These software overhead cycles refer to the minimized software structure
shown in all software examples. This structure is valid for all three timer
modes.
To get the complete interrupt loading, all execution times of the enabled interrupts are summed up during one period.
To get the loading uCPU (ranging from 0 to 1) of the CPU by the interrupt activity,
the following formula is used:
uCPU = ∑( tintrpt
f rep )
EXAMPLE
Two Timer_A interrupts are active in continuous mode. The system clock frequency fMCLK is 2.097MHz.
1) CCR1: repetition rate 1.2 kHz — 16 cycles for the task, 16 cycles overhead
2) CCR3: repetition rate 2.0 kHz — 22 cycles for the task, 16 cycles overhead
uCPU = Σ
16 + 16
( 2.097E6
1.2E3 +
22 + 16
2.097E6
)
2.0E3 = 0.0545
The above result means a CPU loading of approximate 5.5% due to the Timer_A.
6-74
The Timer_A
6.3.6.1
Limitations of the Continuous Mode
Interrupt Handling — the shortest repetitive time interval, tCRmin, between
two similar timer events using a compare register CCRx is:
ptaskmax + pOVHD
fMCLK
t CRmin = t ILmax +
The shortest repetitive time interval, tCLmin, between two interrupt events using
a capture register CCRx is:
ptaskmax + pOVHD
fMCLK
tCLmin = t ILmax +
The time, ttaskmax, for the capture mode is the time to read the captured time
value and to test and reset the COV flag.
- Software Overhead — the interrupt loading ranges from one interrupt re-
quest (request from CCIFGx) up to six interrupt requests (requests from
TAIFG, CCIFG0, and all CCIFGx flags).
- Output Units — for relatively high PWM repetition rates special treatment
may be necessary for PWM duties near the limits 0% and 100%.
Maximum Resolution:
r =
k
fCLK
where: r is equivalent to the period of the timer clock
6.3.6.2
Limitations of the Up Mode
- Interrupt Handling — the worst case sum of all the execution times need-
ed by all interrupts during one timer period must be less than the timer period (defined by the period register, CCR0). Otherwise, the interrupt part will
loose the synchronization due to overload.
This means:
(nCCR0 + 1)
fCLK
k
t=
>
1
fMCLK
(nCCR0 +1)
k
fCLK
∑p
taskmax
+ povhd
t =0
- Software Overhead — the overhead ranges from zero (PWM is output
automatically after the loading of the timer registers), up to six interrupt requests per period (interrupt requests from TAIFG, CCIFG0, and from all
CCIFGx flags).
On-Chip Peripherals
6-75
The Timer_A
- Output Units — all values ranging from 0% to 100% for pulse width modu-
lation (PWM) are possible without special treatment.
- Maximum Resolution — for a given repetition rate, frep, of the timer out-
put, a maximum resolution, r, is possible:
r =
fMCLKmax
= nCCR0 + 1
frep
This means that with a maximum system clock frequency of 4 MHz and a repetition rate of 20 kHz for a PWM output — due to audibility — a resolution of 200
steps is possible (0.5%).
6.3.6.3
Limitations of the Up/Down Mode
- Interrupt Handling — the worst case sum of all the execution times need-
ed by all interrupts during one timer period must be less than the doubled
period defined by the period register CCR0. Otherwise, the interrupt part
will loose the synchronization due to overload.
2 nCCR0
fCLK
k
>
1
fMCLK
2 nCCR0 k
t=
fCLK
Σ
ptaskmax + povhd
t =0
- Software Overhead — the overhead ranges from zero (PWM is output
automatically after the loading of the timer registers) up to ten interrupt requests per full period (interrupt requests from TAIFG, CCIFG0, and 2 interrupts per CCIFGx).
- Output Units — the pulse width zero (0%) needs a special software treat-
ment. Without this, the hardware outputs a 50% pulse width instead. This
behavior will be changed in future versions.
- Maximum Resolution — for a given repetition rate, frep, of the timer out-
put, a maximum resolution, r, is possible:
r =
fMCLKmax
= nCCR0
2 frep
This means that with a maximum system clock frequency of 4 MHz and a repetition rate of 20 kHz for a PWM output — due to audibility — a resolution of 100
steps is possible (1.0%). The resolution of the up/down mode is less than it is
in the up mode. With the same timer clock, the up mode delivers (nCCR0+2)
different pulse widths and the up/down mode delivers (nCCR0+1) different
pulse widths — but with a reduced output frequency due to the up and down
counting. This means the resolution is approximately one half the resolution
of the up mode.
6-76
The Timer_A
6.3.7
Miscellaneous
The frequencies generated by the Timer_A may also be used as the timebase
for other tasks if defined appropriately:
- Serial Communication Interface (SCI) — If for an MSP430, a second
UART (RS232) is needed, then with a timer frequency of 19.2 kHz (8 × 2.4
kHz) a software UART with 2400 baud can be implemented. This software
UART uses the interrupt generated with the reaching of the content of the
period register, CCR0 (CCIFG0 = 1), for the synchronization of the UART
software.
- Timing Intervals for Control — These important control values can also
be derived from the timer frequency by an appropriate software prescaling. This timing may be used for calculations, keyboard scan, measurement starts, etc.
6.3.8
Software Examples for the Continuous Mode
This section shows several proven application examples for the Timer_A.
Whenever possible, the abbreviations used in the Architecture Guide and
Module Library are used.
All examples use the value FLLMPY — it defines the master clock frequency
fMCLK.
f MCLK = FLLMPY
f crystal
If this frequency, fMCLK, is too high for the application (for example: it causes
values for the timer registers exceeding the 16-bit range), then the input divider
of the Timer_A may be used. It allows a prescaling by 1, 2, 4, and 8. For prescaling by 2, the definitions at the start of each example are simply changed to:
FLLMPY
.equ
100
; FLL multiplier for 3.2768MHz
TCLK
;
.equ
FLLMPY*32768/2
; Timer Clock = 1.6384MHz
; The Input Divider D2 is used to get MCLK/2 for the TCLK
;
MOV
#ISMCLK+D2+TAIE+CLR,&TACTL ; Use D2 divider
Note:
The software and hardware examples shown here are specific to the
MSP430C/P33x family. Other MSP430 family members may use other I/O
ports and addresses for the Timer_A registers and signals. The programming principles are unchanged — only address definitions may need to be
modified.
On-Chip Peripherals
6-77
The Timer_A
The software examples were tested with the software simulator and an
EVK330 evaluation kit.
For all examples, the loading of the CPU is given. The terms used are defined
below:
- Overhead — the sum of necessary CPU cycles to get to the first instruc-
tion of the interrupt handler and to get back to the interrupted program sequence (wakeup cycles, storing of PC and SR, determination of the interrupt source, and RETI cycles)
- Task — the CPU cycles used for the interrupt task: incrementing of a
counter, calculations, etc.
Advantages of the Continuous Mode:
H
Five complete, independent timings and captures are possible.
Any mix is possible
H
No dominance by a period register
Disadvantages of the Continuous Mode:
6.3.8.1
H
Software update necessary for the capture/compare registers to
allow continuous run
H
Speed limit due to the necessary software update
Common Initialization Subroutine
The initialization subroutine INITSR is used by all examples. It executes the
following tasks:
- A check is made if the initialization subroutine is called after applying the
supply voltage (the RAM word INITKEY does not contain 0F05Ah) or after
an external reset or watchdog reset (INITKEY contains 0F05Ah). If the applying of the supply voltage caused the reset, then the RAM is cleared and
the INITKEY is initialized to 0F05Ah.
- The system clock oscillator is programmed with the FLL multiplier N. This
defines the MCLK frequency fMCLK. See above.
- The correct DCO switch FN_x for the chosen MCLK frequency (fMCLK) is
set. These switches allow the system clock oscillator to operate with one
of the center taps of the digitally controlled oscillator (DCO). This way the
DCO operates always in a nonsaturated condition.
6-78
The Timer_A
- A delay of 30000 clock cycles is included to give the oscillator time to settle
at the correct frequency.
; Common Initialization Subroutine
; Check the INITKEY value first:
; If value is 0F05Ah: a reset occurred, RAM is not cleared
; otherwise Vcc was switched on: complete initialization
;
INITSR
CMP
#0F05Ah,INITKEY
; PUC or POR?
JEQ
IN0
; Key is ok, continue program
CALL
#RAMCLR
; Restart completely: clear RAM
MOV
#0F05Ah,INITKEY
; Define “initialized state”
MOV.B
#FLLMPY–1,&SCFQCTL ; Define MCLK frequency
.if
FLLMPY < 48
; Use the right DCO current:
MOV.B
#0,&SCFI0
; MCLK < 1.5MHz: FN_x off
.if
FLLMPY < 80
; 1.5MHz < MCLK < 2.5MHz?
MOV.B
#FN_2,&SCFI0
; Yes, FN_2 on
;
IN0
;
.else
.else
;
.if
FLLMPY < 112
; 2.5MHz < MCLK < 3.5MHz?
MOV.B
#FN_3,&SCFI0
; Yes, FN_3 on
#FN_4,&SCFI0
; MCLK > 3.5MHz: FN_4 on
MOV
#10000,R5
; Allow the FLL to settle
DEC
R5
; at the correct DCO tap
JNZ
IN1
; during 30000 cycles
.else
MOV.B
.endif
.endif
.endif
;
IN1
RET
; Return from initialization
;
; Subroutine for the clearing of the RAM block
;
.bss
INITKEY,2,0200h
; 0F05Ah: initialized state
On-Chip Peripherals
6-79
The Timer_A
RAMSTRT
.equ
0200h
; Start of RAM
RAMEND
.equ
05FEh
; Highest RAM address (33x)
CLR
R5
; Prepare index register
;
RAMCLR
RCL
CLR
RAMSTRT(R5)
; 1st RAM address
INCD
R5
; Next word address
CMP
#RAMEND–RAMSTRT+2,R5 ; RAM cleared?
JLO
RCL
RET
6.3.8.2
; No, once more
; Yes, return
Generation of Five Independent Timings
The software example explains the use of the timer vector register (TAIV) and
the overhead of the interrupt handling. It refers to figure 6–22. The interrupt
handler of timer block x adds the appropriate time interval, ∆t, to the corresponding compare register, CCRx. The MCLK frequency (3.2768 MHz) is
used also for the timer clock. The five timings generated are defined as follows
(see also Table 6–15):
- Capture/Compare Block 0 — a positive pulse with a 10 kHz repetition
rate is generated and output at terminal TA0. The pulse is reset by the interrupt handler of timer block 0. The pulse is used for the precise triggering
of an external analog-to-digital converter. The error of the repetition rate
due to the MCLK frequency used is –0.097%
- Capture/Compare Block 1 — an internal interrupt with variable timing is
generated. The cycle count is stored in the RAM word TIM1REP. The maximum value of this cycle count is 0FFFFh, the minimum value is 1000. The
output terminal TA1 is not used.
- Capture/Compare Block 2 — a square wave with a fixed 1 kHz repetition
rate is generated and output at terminal TA2. The pulse is used as a reference for external devices. The error of the repetition rate due to the MCLK
frequency used is –244 ppm.
- Capture/Compare Block 3 — an internal interrupt with a fixed 200 Hz
repetition rate is generated. The output terminal TA3 is not used. The error
of the repetition rate due to the MCLK frequency used is –244 ppm.
- Capture/Compare Block 4 — a square wave with a variable output fre-
quency is generated and output at terminal TA4. The output frequency
starts at 409.6 Hz (4000 cycles) and increases up to 1638.4 Hz (1000
cycles). The square wave is used for the control of an external DC/DC converter.
6-80
The Timer_A
The formula for calculating the value, ∆n, that is added to the timer register
(TAR) depends on the application. For the internal interrupts (CCR1 and CCR3
in the example) and the external pulse (CCR0 in the example), ∆n is:
∆n =
∆t
fCLK
k
For the external-generated square wave signals with the frequency fext
(CCR2 and CCR4 in the example) ∆n is:
∆n =
Where:
fCLK
fext
k
∆t
k
fCLK
2 fext
Frequency at the input of the input divider
Frequency to be output with toggle mode
Input divider constant (1, 2, 4, 8)
Time interval to be generated
[Hz]
[Hz]
[s]
Table 6–15. Short Description of the five independent Timings
CAPTURE/
COMPARE BLOCK
TIME INTERVAL (TIMER
CLOCK CYCLES)
SIGNAL TYPE
COMMENT
0
328
External
Pulse: 10kHz ADC repetition rate
1
Variable
Internal
Cycle count stored in TIM1REP (min 1000)
2
1638
External
1 kHz @ 3.2768 MHz (error: –244 ppm)
3
16384
Internal
Fixed frequency 200 Hz
4
4000 to 1000
External
Increasing frequency for ext. DC/DC converter
The software example is written for an fMCLK of 3.276 MHz. If other frequencies are used, the time intervals need to be adapted. Subsequent examples
show methods of writing frequency-independent software. Figure 6–22 illustrates the five timings described above:
On-Chip Peripherals
6-81
The Timer_A
0FFFFh
Timer Register
0h
65536/Timer Clock
External Pulses
10 kHz at TA0
∆t1
Variable Internal
Interrupt CCR1
External Frequency
1 kHz at TA2
∆t3
Fixed Internal
Interrupt 200 Hz
Increasing Frequency
at TA4
Time
Figure 6–22. Five Independent Timings Generated in the Continuous Mode
The timing of the signals output at the TAx pins (the dedicated I/O pins of the
Timer_A) is independent of interrupt latency: the TAx outputs are set, reset or
toggled exactly at the programmed time (contained in the capture/compare
register x) by the output unit x. The requested interrupt when this occurs is
used to update the capture/compare register x and to execute necessary
tasks.
Example 6–30. Five independent Timings Generated in the Continuous Mode
The software example also shows how to output the MCLK frequency at the
output terminal XBUF for reference purposes. For example, an external ASIC
may be driven by this frequency.
; Software example: five independent timings using the
; Continuous Mode of the 16–bit Timer_A
;
; Hardware definitions
;
FLLMPY
.equ
100
; FLL multiplier for 3.2768MHz
TCLK
.equ
FLLMPY*32768
; TCLK: FLLMPY x fcrystal
STACK
.equ
600h
; Stack initialization address
;
; RAM definitions
6-82
The Timer_A
;
TIM1REP
.equ
202h
; Repetition rate Block 1
TIM4REP
.equ
204h
; Repetition rate Block 4
TIMAEXT
.equ
206h
; Extension for Timer Register
;
.text 0F000h
; Software start address
MOV
#STACK,SP
; Initialize Stack Pointer
CALL
#INITSR
; Init. FLL and RAM
;
INIT
;
; Initialize the Timer_A: MCLK, Cont. Mode, INTRPT on
;
MOV
#ISMCLK+TAIE+CLR,&TACTL
MOV
#OMSET+CCIE,&CCTL0 ; Set, INTRPT on
MOV
#OMOO+CCIE,&CCTL1 ; No output, INTRPT on
MOV
#OMT+CCIE,&CCTL2
MOV
#OMOO+CCIE,&CCTL3 ; No output, INTRPT on
MOV
#OMT+CCIE,&CCTL4
; Toggle, INTRPT on
MOV
#0FFFFh,TIM1REP
; Start value Block 1
MOV
#4000,TIM4REP
; Start value Block 4
MOV.B
#TA4+TA2+TA0,&P3SEL ; Define TAx outputs
MOV
#1,&CCR0
; Immediate start
MOV
#1,&CCR1
; with defined contents
MOV
#1,&CCR2
; for the Capture/Compare
MOV
#1,&CCR3
; Registers
MOV
#1,&CCR4
;
CLR
TIMAEXT
; Clear TAR extension
MOV.B
#CBMCLK+CBE,&CBCTL ; Output MCLK at XBUF pin
BIS
#MCONT,&TACTL
; Toggle, INTRPT on
;
EINT
MAINLOOP ...
; Start Timer
; Enable interrupt
; Continue in background
;
; Interrupt handler for Capture/Compare Block 0. An ext. ADC
; is started every 100us (328 cycles @ 3.2768MHz MCLK) with
; a positive pulse at TA0 (set exactly from Output Unit).
On-Chip Peripherals
6-83
The Timer_A
; The interrupt flag CCIFG0 is reset automatically.
;
TIMMOD0
.EQU
$
; Start of handler
ADD
#328,&CCR0
; Prepare next INTRPT (10kHz)
BIC
#OMRS+OUT,&CCTL0
; Reset TA0
BIS
#OMSET,&CCTL0
; Back to Set Mode
RETI
; Return from Interrupt
;
; Timer Block 3 generates an internal used 5ms interrupt
; 16384/3.2768MHz = 0.005s
;
TIMMOD3
.EQU
$
; Vector 6: Block 3
ADD
#16384,&CCR3
; Add time interval (5ms)
...
; Task3 starts here
; Fall through to TIM_HND
;
; Interrupt handlers for Capture/Compare Blocks 1 to 4.
; The interrupt flags CCIFGx are reset by the reading
; of the Timer Vector Register TAIV
;
TIM_HND
.EQU
$
ADD
&TAIV,PC
; Interrupt latency
; Add Jump table offset
RETI
; Vector 0: No interrupt
JMP
TIMMOD1
; Vector 2: Block 1
JMP
TIMMOD2
; Vector 4: Block 2
JMP
TIMMOD3
; Vector 6: Block 3
JMP
TIMMOD4
; Vector 8: Block 4
;
; Block 5. Timer Overflow Handler: the Timer Register is
; expanded into the RAM location TIMEXT (MSBs)
;
TIMOVH
.EQU
$
; Vector 10: TIMOV Flag
INC
TIMAEXT
; Incr. Timer extension
RETI
;
;
; Block 1 uses a variable repetition rate defined in TIM1REP
6-84
The Timer_A
; Repetition Rate = 3.2768MHz/(TIM1REP)
;
TIMMOD1
.EQU
$
; Vector 2: Block 1
ADD
TIM1REP,&CCR1
; Add time interval
...
; Task1 starts here
RETI
; Back to main program
;
; The used time interval delta t2 is 1638 cycles. This
; delivers an external 1kHz signal (1638/3.2768MHz = 500us)
;
TIMMOD2
.EQU
$
; Vector 4: Block 2
ADD
#1638,&CCR2
; Add time interval (1/2 period)
...
; Task2 starts here
RETI
; Back to main program
;
; Block 4 uses a variable repetition rate starting at 4000
; cycles and going down to 1000 cycles. It is used for an
; external DC/DC converter. Toggle Mode is used
;
TIMMOD4
T41
.EQU
$
; Vector 8: Block 4
ADD
TIM4REP,&CCR4
; Add time interval (1/2 period)
CMP
#1000,TIM4REP
; Final value reached?
JLO
T41
; Yes, no modification
SUB
#1,TIM4REP
; No, modify interval
RETI
; Back to main program
;
.sect
”TIMVEC”,0FFF0h
; Timer_A Interrupt Vectors
.word
TIM_HND
; Timer Blocks 1 to 4
.word
TIMMOD0
; Vector for Timer Block 0
.sect
”INITVEC”,0FFFEh
; Reset Vector
.word
INIT
The example above results in a maximum (worst case) CPU loading uCPU
(ranging from 0 to 1) by the Timer_A activities:
uCPU =
1
fMCLK
Σ( nintrpt
f rep )
On-Chip Peripherals
6-85
The Timer_A
Where:
fMCLK
nintrpt
frep
Frequency of the DCO
Number of cycles executed by the interrupt handler
Repetition rate of the interrupt handler
CCR0 — repetition rate 10 kHz
CCR1 — repetition rate 3.27 kHz
CCR2 — repetition rate 2.0 kHz
CCR3 — repetition rate 0.2 kHz
CCR4 — repetition rate 3.27 kHz
TIMOV — repetition rate 50 Hz
uCPU =
26
[Hz]
[Hz]
15 cycles for the task, 11 cycles overhead
6 cycles for the task, 16 cycles overhead
5 cycles for the task, 16 cycles overhead
5 cycles for the task, 20 cycles overhead
17 cycles for the task, 16 cycles overhead
4 cycles for the task, 14 cycles overhead
10 4 + 22 3276.8 + 21 2000 + 25 200 + 33 3276.8 + 18
3.2768 10 6
26 cycles
22 cycles
21 cycles
25 cycles
33 cycles
18 cycles
50
= 0.15
The result above means a CPU loading of approximative 15% due to the Timer_A (the tasks of the timer blocks 1, 2, and 3 are not included).
6.3.8.3
DTMF Generation
Modern telephones use dual-tone multi-frequency (DTMF) signaling for the
dialing process. A pair of frequencies defines each of the 16 possible numbers
and characters, and are selected from the matrix shown in Table 6–16. Two
Timer_A outputs (TA2 and TA1) are used to generate the frequency pair. External filters clean up the waveform and mix the two frequencies. The length of
the output signals is normally 65 ms to 100 ms.
Table 6–16. DTMF Frequency Pairs
6-86
FREQUENCY
1209 Hz
1336 Hz
1477 Hz
1633 Hz
697 Hz
1
2
3
A
770 Hz
4
5
6
B
852 Hz
7
8
9
C
941 Hz
*
0
#
D
The Timer_A
Table 6–17 shows the errors of the generated DTMF frequencies caused by
the timer clock frequency used. Rounding is used for the timer values to get
the smallest possible errors.
Table 6–17. Errors of the DTMF Frequencies Caused by the MCLK
FLL MULTIPLIER N
32
64
96
116
FREQUENCY
1.048 MHz
2.096 MHz
3.144 MHz
3.801 MHz
697 Hz
+0.027%
+0.027%
+0.027%
+0.027%
770 Hz
–0.015%
–0.016%
+0.033%
–0.016%
852 Hz
+0.059%
–0.023%
+0.005%
+0.031%
941 Hz
+0.029%
+0.029%
+0.029%
+0.035%
1209 Hz
–0.079%
+0.036%
+0.036%
–0.003%
1336 Hz
+0.109%
–0.018%
+0.025%
+0.025%
1477 Hz
–0.009%
–0.009%
–0.009%
–0.009%
1633 Hz
+0.018%
+0.018%
+0.018%
+0.018%
Figure 6–23 shows a proven hardware solution to mix the two output frequencies. A low-pass filter is used for the high output frequency and another one
for the low output frequency. The outputs of these low-pass filters are summed
by a third operational amplifier. The filter hardware was developed by Robert
Siwy/Bavaria.
Filters
Mixer
1 nF
4.7 nF
1/4 LM324
3.9 kΩ
150 kΩ
56 kΩ
+
_
TA.2
39 kΩ
33 nF R2
VCC/2
22 nF
1 nF
100 nF
MSP430
120 kΩ
47 kΩ
+
_
TA.1
DTMF
Output
27 kΩ
33 nF R1
33 nF
100 nF
5V
2.2 µF
0V
1/4 LM324
VSS
ÎÎÎ
ÎÎ
ÎÎ
ÎÎ
ÎÎÎ
ÎÎ
100 nF
10 nF
VCC
1/4 LM324
+
_
High DTMF
0V
4.7 kΩ
39 kΩ
2.2 nF
0V
Low DTMF
0V
All Components are 10% Tolerance
Figure 6–23. DTMF Filters and Mixer
On-Chip Peripherals
6-87
The Timer_A
The two low-pass filters and the mixer are shown in figure 6–23. The symmetrical output pulses at TA2 and TA1 bias the filter amplifiers with VCC/2.
The component values are valid for the specification of the German public telephone system. The positive supply voltage for the operational amplifiers is
switched by a TP output or an O output.
With the two resistors R1 and R2, the filters can be adapted to the specifications of the telephone systems in other countries. These resistors define the
high and low DTMF frequency parts of the DTMF output signal.
Example 6–31. DTMF Software
The following DTMF software routine is independent of the timer clock frequency used. During the assembly, the new timer values are calculated. The
length of the DTMF output signal is defined with the value DL — its value is
in milliseconds.
; Hardware definitions
;
FLLMPY
.equ
32
; FLL multiplier for 1.048MHz
TCLK
.equ
FLLMPY*32768
; TCLK: FLLMPY x fcrystal
DL
.equ
82
; DTMF signal length (65..100ms)
STACK
.equ
600h
; Stack initialization address
;
; RAM definitions
;
STDTMF
.equ
202h
; Status Hi and Lo frequency
TIMAEXT
.equ
204
; Timer Register Extension
LENGTH
.equ
206h
; DTMF length counter
;
.text 0F000h
; Software start address
;
; Initialize the Timer_A: MCLK, Cont. Mode, INTRPT enabled
; Prepare Timer_A Output Units, MCLK = 1.048MHz (autom.)
;
INIT
6-88
MOV
#STACK,SP
; Initialize Stack Pointer SP
CALL
#INITSR
; Init. FLL and RAM
MOV
#ISMCLK+TAIE+CLR,&TACTL ; Define Timer
MOV.B
#TA2+TA1,&P3SEL
; TA2 and TA1 at P3.5/4
The Timer_A
CLR
TIMAEXT
; Clear TAR extension
BIS
#MCONT,&TACTL
; Start Timer_A
EINT
; Enable interrupt
MAINLOOP ...
; Continue in mainloop
;
; A key was pressed: SDTMF contains the table offset of the
; two frequencies (0..6,0..6) in the high and low bytes
;
MOV
&TAR,R5
; For immediate start:
ADD
FDTMFLO,R5
; Short time offset
MOV
R5,&CCR1
; 1st change after 0.71ms
MOV
R5,&CCR2
; 1/(2x697) = 0.71ms
MOV
#OMT+CCIE,&CCTL1
; Toggle, INTRPT on
MOV
#OMT+CCIE,&CCTL2
; Toggle, INTRPT on
MOV.B
STDTMF,R5
; Counter for 82ms
RRA
R5
; # of low frequ. changes
MOV.B
DTMFL(R5),LENGTH
; for the signal length.
...
; Continue background
;
; CCR0 interrupt handler (not implemented here)
;
TIMMOD0
...
RETI
;
; Interrupt handler for Capture/Compare Registers 1 to 4
;
TIM_HND
ADD
&TAIV,PC
RETI
; Serve highest priority request
; No interrupt pending: RETI
JMP
HCCR1
; CCR1 request (low DTMF frequ.)
JMP
HCCR2
; CCR2 request (high DTMF fr.)
JMP
HCCR3
; CCR3 request
JMP
HCCR4
; CCR4 request
INC
TIMAEXT
; Extension of Timer_A 32 bit
;
TIMOVH
RETI
;
On-Chip Peripherals
6-89
The Timer_A
; Low DTMF frequencies: TA1 is toggled by Output Unit 1
; Output changes of TA1 are counted to control signal length
;
HCCR1
PUSH
R5
; Save used register
MOV.B
STDTMF,R5
; Status low DTMF frequency
ADD
FDTMFLO(R5),&CCR1 ; Add length of half period
DEC.B
LENGTH
; Signal length DL elapsed?
JNZ
TARET
; No
;
; Yes, terminate DTMF signal: disable interrupts, Output only
;
TARET
BIC
#OMRS+OUT+CCIE,&CCTL1 ; Reset TA1
BIC
#OMRS+OUT+CCIE,&CCTL2 ; Reset TA2
POP
R5
RETI
; Restore R5
; Return from interrupt
;
; High DTMF frequencies: TA2 is toggled by Output Unit 2
;
HCCR2
PUSH
R5
; Save used register
MOV.B
STDTMF+1,R5
; Status high DTMF frequency
ADD
FDTMFHI(R5),&CCR2 ; Add length of half period
POP
R5
; Restore R5
RETI
; Return from interrupt
...
; Task controlled by CCR3
;
HCCR3
RETI
HCCR4
...
; Task controlled by CCR4
RETI
;
; Table with the DTMF frequencies: the table contains the
; number of MCLK cycles for a half period. The values are
; adapted to the actual MCLK frequency during the assembly
; Rounding assures the smallest possible frequency error
;
FDTMFLO
6-90
.word
((TCLK/697)+1)/2
; Lo DTMF frequ.
.word
((TCLK/770)+1)/2
;
770Hz
697Hz
The Timer_A
FDTMFHI
.word
((TCLK/852)+1)/2
;
852Hz
.word
((TCLK/941)+1)/2
;
941Hz
.word
((TCLK/1209)+1)/2 ; Hi DTMF frequ. 1209Hz
.word
((TCLK/1336)+1)/2 ;
1336Hz
.word
((TCLK/1477)+1)/2 ;
1477Hz
.word
((TCLK/1633)+1)/2 ;
1633Hz
;
; Table contains the number of half periods for the signal
; length DL (ms). The low DTMF frequency is used for the timing
;
DTMFL
.byte
2*697*DL/1000
; Number of half periods
.byte
2*770*DL/1000
; per DL ms
.byte
2*852*DL/1000
;
.byte
2*941*DL/1000
;
.sect
”TIMVEC”,0FFF0h
; Timer_A Interrupt Vectors
.word
TIM_HND
; Timer Block 1..4 Vector
.word
TIMMOD0
; Vector for Timer Block 0
.sect
”INITVEC”,0FFFEh
; Reset Vector
.word
INIT
Example 6–32. DTMF Software — Faster
Another software solution that is faster — but needs more RAM — is shown
below. The table containing the length of the half waves is read only once for
the two DTMF frequencies and the read values are stored in RAM words
DTMFLO and DTMFHI. The Timer_A interrupt routines use these two values.
The tables are the same as with the example above.
FLLMPY
.equ
32
; FLL multiplier for 1.048MHz
TCLK
.equ
FLLMPY*32768
; TCLK: FLLMPY x fcrystal
DL
.equ
82
; DTMF time ms (65..100ms)
STDTMF
.equ
202h
; Status Hi and Lo frequency
TIMAEXT
.equ
204
; Timer Register Extension
LENGTH
.equ
206h
; DTMF length counter
DTMFLO
.equ
208h
; Half wave of low frequency
DTMFHI
.equ
20Ah
; Half wave of high frequency
On-Chip Peripherals
6-91
The Timer_A
STACK
.equ
600h
.text 0F000h
; Stack initialization address
; Software start address
; Initialize the Timer_A: MCLK, Cont. Mode, INTRPT enabled
; Prepare Timer_A Output Units, MCLK = 1.048MHz (autom.)
;
INIT
MOV
#STACK,SP
; Initialize Stack Pointer SP
CALL
#INITSR
; Init. FLL and RAM
MOV
#ISMCLK+TAIE+CLR,&TACTL ; Start Timer
MOV.B
#TA2+TA1,&P3SEL
; TA2 and TA1 at P3.5/4
CLR
TIMAEXT
; Clear TAR extension
BIS
#MCONT,&TACTL
; Start Timer_A
EINT
; Enable interrupt
MAINLOOP ...
; Continue in mainloop
;
; A key was pressed: STDTMF contains the table offset of the
; two frequencies (0..6,0..6) in the high and low bytes
;
MOV
&TAR,R5
; For immediate start:
ADD
FDTMFLO,R5
; Short time offset
MOV
R5,&CCR1
; 1st change after 0.71ms
MOV
R5,&CCR2
; 1/(2x697) = 0.71ms
;
; Fetch the two cycle counts for the DTMF frequencies
;
MOV.B
STDTMF+1,R5
; High DTMF frequency
MOV
FDTMFHI(R5),DTMFHI ; Length of half period
MOV.B
STDTMF,R5
MOV
FDTMFLO(R5),DTMFLO ; Length of half period
; Low DTMF frequency
;
; Counter for length
RRA
R5
; Prepare byte index
MOV.B
DTMFL(R5),LENGTH
; # of low frequ. changes
MOV
#OMT+CCIE,&CCTL1
; Toggle, INTRPT on
MOV
#OMT+CCIE,&CCTL2
; Toggle, INTRPT on
...
Mainloop
6-92
; to
The Timer_A
;
; CCR0 interrupt handler (not implemented here)
;
TIMMOD0
...
RETI
;
; Interrupt handler for Capture/Compare Registers 1 to 4
;
TIM_HND
ADD
&TAIV,PC
RETI
; Serve highest priority request
; No interrupt pending: RETI
JMP
HCCR1
; CCR1 request (low DTMF frequ.)
JMP
HCCR2
; CCR2 request (high DTMF fr.)
JMP
HCCR3
; CCR3 request
JMP
HCCR4
; CCR4 request
INC
TIMAEXT
; Extension of Timer_A 32 bit
;
TIMOVH
RETI
;
; Low DTMF frequencies: TA1 is toggled by Output Unit 1
;
HCCR1
ADD
DTMFLO,&CCR1
; Add length of half period
DEC.B
LENGTH
; DL ms elapsed?
JNZ
TARET
; No
;
; Terminate DTMF output: disable interrupts, Output only
;
TARET
BIC
#OMRS+OUT+CCIE,&CCTL1 ; Reset TA1
BIC
#OMRS+OUT+CCIE,&CCTL2 ; Reset TA2
RETI
; Return from interrupt
;
; High DTMF frequencies: TA2 is toggled by Output Unit 2
;
HCCR2
ADD
DTMFHI,&CCR2
; Add length of half period
RETI
; Return from interrupt
...
; Task controlled by CCR3
;
HCCR3
On-Chip Peripherals
6-93
The Timer_A
RETI
HCCR4
...
; Task controlled by CCR4
RETI
;
; Tables and interrupt vectors are identical to the previous
; example
The second example, with maximum frequencies on both channels, results in
a maximum CPU loading, uCPU (ranging from 0 to 1), by the Timer_A activities
due to DTMF generation:
uCPU =
Where:
fMCLK
nintrpt
frep
1
fMCLK
Σ (nintrpt
f rep)
Frequency of the system clock oscilator (DCO)
Number of cycles executed by the interrupt handler
Repetition rate of the interrupt handler
CCR1 — repetition rate 2×941 Hz
CCR2 — repetition rate 2×1633 Hz
uCPU =
28
12 cycles for the task, 16 cycles overhead
6 cycles for the task, 16 cycles overhead
2
[Hz]
[Hz]
28 cycles
22 cycles
941 + 22 2 1633
= 0.12
1.048 10 6
This result shows a worst case CPU loading of approximate 12% due to the
DTMF generation. This loading occurs only during the 82 ms activity.
6.3.8.4
TRIAC Control
TRIAC control for electric motors (DMC) or other loads is a simple task when
using the Timer_A. The software loads one of the capture/compare registers
(CCR4 with this example), prepares the output unit to change the TAx output
after the desired time, and continues with the background task. When the
loaded time interval elapses, the output unit fires the TRIAC gate at exactly the
programmed time and requests an interrupt. The interrupt handler can use dynamic control (several short pulses to save current) or static control (one long
gate pulse), which is used with this example. See figure 6–25 for details.
The TRIAC control software contains some security features. They ensure
that no gate triggering of the previous half wave can last into the next half wave
and cause gate triggering there also:
6-94
The Timer_A
H
The zero crossing part (P0.0 handler) immediately switches off
the gate signal by setting of the TA4 terminal to high
H
The P0.0 handler calculates a value, OFFTIME, that defines a
time for the actual half wave where the gate signal must be
switched off at the latest
H
The timer block 4 handler checks before each switch-on of the
TRIAC gate to see if the on-time of the gate exceeds the calculated value, OFFTIME, or not. If the value in OFFTIME is exceeded, then it is used for the maximum on time
The TRIAC control software is independent of the ac line frequency. For each
full wave of the line voltage, the period is measured and used for the security
features. The calculation software also uses the timer clocks value of the halfperiod stored in RAM location MAINHW.
Figure 6–24 shows the hardware for the TRIAC control in this example. The
temperature measurement, the overcurrent detection, and the revolution control are not included in the software example.
After power up, the TA4 terminal is switched to input mode. The base resistor
of the PNP transistor switches the gate of the TRIAC off and prevents the motor from running.
5V
32 kHz
0V
VCC Xin
CIN
COM
SEL
Error
kW
Xout
TP.2
RSENS2
TP.1
RSENS1
rpm
MCLK
XBUF
5V
MSP430
TA4
5V
Tacho Generator
5V
230 V AC Line
T
M
5V
0V
+
_
Comparator
_
Zero Crossing
P0.0
P0.4
3.5 V
230 V AC Line
RREF
TP.0
Revolutions
Amplifier
+
VSS
P0.5
Overcurrent
Direction
0V
Figure 6–24. TRIAC Control With Timer_A
On-Chip Peripherals
6-95
The Timer_A
Figure 6–25 shows a TRIAC control with three different conduction angles. Dynamic control and static control is included.
The software example is written for the static control only, but it is relatively
easy to add additional states to the TRIAC handler (timer block 4), which
means more than one gate pulse per half wave.
P0.0 Input
Zero Crossing
tdelay
tdelay
tdelay
Typically
5 to 8 Pulses
Dynamic Control
TA4 Output
Static Control
Motor
Voltage
Voltage
Offtime
Conduction
Angle
AC Line
Figure 6–25. Static and Dynamic TRIAC Gate Control
The software shown below works up to a timer clock frequency (fCLK) of MCLK
(in this case due to k = 1):
fCLK < 216
Where:
fCLK
k
fLINE
k
2
f LINE
Input frequency at the input divider input of Timer_A
Pre-divider constant of the input divider (1, 2, 4 or 8)
AC line frequency used
[Hz]
[Hz]
If fCLK is higher than defined above, then the input divider of Timer_A must be
used. This restriction is caused by the 16-bit structure of Timer_A and the
RAM.
6-96
The Timer_A
Example 6–33. Triac Control
The check to see if the gate pulse starts after the security time, SEC, is not included below. It must occur during the calculation.
; Definitions for the TRIAC control software
;
FLLMPY
.equ
32
; FLL multiplier for 1.048MHz
TCLK
.equ
FLLMPY*32768
; TCLK (Timer Clock) [Hz]
SEC
.equ
(500*TCLK/1000)/1000 ; Security time (500us)
Gate_On
.equ
(1200*TCLK/1000)/1000 ; TRIAC Gate on (1200us)
;
; RAM definitions
;
TIMAEXT
.equ
202h
; Timer Register Extension
OFFTIME
.equ
204h
; Time when gate MUST be off
MAINHW
.equ
206h
; Length of half wave (TCLK)
PRVTAR
.equ
208h
; Value of TAR at last pos. edge
FIRANGL
.equ
20Ah
; Half wave – conduction angle
STTRIAC
.equ
20Ch
; Control byte (0 = off)
STACK
.equ
600h
; Stack initialization address
.text
; Start of ROM code
;
; Initialize the Timer_A: MCLK, Cont. Mode, INTRPT enabled
; Prepare Timer_A Output Units
;
INIT
MOV
#STACK,SP
; Initialize Stack Pointer SP
CALL
#INITSR
; Init. FLL and RAM
MOV
#ISMCLK+TAIE+CLR,&TACTL ; Init. Timer
MOV
#OMOO+CCIE+OUT,&CCTL4 ; Set TA4 high
BIS.B
#TA4,&P3SEL
; TA4 controls gate transistor
BIS.B
#P0IE0,&IE1
; Enable P0.0 interrupt
CLR
TIMAEXT
; Clear TAR extension
CLR.B
STTRIAC
; TRIAC off status (0)
BIS
#MCONT,&TACTL
; Start Timer_A in Cont. Mode
MOV.B
#CBMCLK+CBE,&CBCTL ; MCLK at XBUF pin
EINT
; Enable interrupt
On-Chip Peripherals
6-97
The Timer_A
MAINLOOP
...
; Continue in mainloop
;
; Some control examples:
; Start electric motor: checked result (TCLK cycles) in R5.
; The result is the time difference from the zero crossing
; to the first gate pulse measured in Timer Clock cycles
;
MOV
R5,FIRANGL
; Gate delay to FIRANGL
MOV.B
#1,STTRIAC
; Activate TRIAC control
...
; Continue in background
;
; The motor is running. A new calculation result is available
; in R5. It will be used with the next mains half wave
;
MOV
R5,FIRANGL
...
; Gate delay to FIRANGL
; Continue in background
;
; Stop motor: switch off TRIAC control
;
CLR.B
STTRIAC
MOV
#OMOO+CCIE+OUT,&CCTL4 ; TRIAC gate off
...
; Disable TRIAC control
; Continue with background
;
; Interrupt handlers for Capture/Compare Blocks 1 to 4.
; The interrupt flags CCIFGx are reset when reading
; the Timer Vector Register TAIV
;
TIM_HND
EINT
ADD
; Real time environment
&TAIV,PC
RETI
; Add “Jump table” offset
; Vector 0: No interrupt
JMP
TIMMOD1
; Vector 2: Block 1
JMP
TIMMOD2
; Vector 4: Block 2
JMP
TIMMOD3
; Vector 6: Block 3
JMP
TIMMOD4
; Vector 8: Block 4
;
; Block 5. Timer Overflow Handler: the Timer Register is
6-98
The Timer_A
; expanded into the RAM location TIMAEXT (16 MSBs)
;
TIMOVH
.EQU
$
; Vector 10: TIMOV Flag
INC
TIMAEXT
; Incr. Timer extension
JMP
TIM_HND
; Another Timer_A interrupt?
;
; The interrupt handlers for the Timer Blocks 0 to 3 follow
; They are not implemented here
;
TIMMOD0
.equ
$
; Handler for Timer Block 0
TIMMOD1
.equ
$
; Handler for Timer Block 1
TIMMOD2
.equ
$
; Handler for Timer Block 2
TIMMOD3
.equ
$
; Handler for Timer Block 3
RETI
;
; Timer Block 4: interrupt handler for the TRIAC control
;
TIMMOD4
CC4TAB
PUSH
R5
; Save help register R5
MOV.B
STTRIAC,R5
; Status of TRIAC control
MOV.B
CC4TAB(R5),R5
; Fetch offset to status handler
ADD
R5,PC
; Branch to status handler
.byte
STATE0–CC4TAB
; Status 0: No TRIAC activity
.byte
STATE0–CC4TAB
; Status 1: activition made
.byte
STATE2–CC4TAB
; Status 2: 1st gate pulse
.byte
STATE3–CC4TAB
; Status 3: TRIAC gate off
.even
;
; TRIAC status 2: gate is switched on for ”Gate_ON” time
; The On time is shortened to the OFFTIME value if the
; OFFTIME is before the Gate_On time
;
STATE2
MOV
&CCR4,R5
; Copy time of interrupt
ADD
#Gate_On,&CCR4 ; Set end of ON state
INV
R5
INC
R5
ADD
OFFTIME,R5
; Negate last INTRPT time
; OFFTIME – last INTRPT time
On-Chip Peripherals
6-99
The Timer_A
CMP
#Gate_On,R5
; OFFTIME later than next INTRPT?
JHS
ST20
; Yes, ok
;
; The calculated ON time ends after OFFTIME: OFFTIME is used
;
ST20
MOV
OFFTIME,&CCR4
MOV
#OMSET+CCIE,&CCTL4 ; Prepare for gate off
INC.B
STTRIAC
; TRIAC status + 1
;
; TRIAC status 0: No activity. TRIAC is off always
;
STATE0
POP
R5
; Restore help register
RETI
; Return from interrupt
;
; TRIAC status 3: gate pulse
is output.
; No activity until next half wave.
STATE3
MOV
#OMOO+CCIE+OUT,&CCTL4 ; Gate off (TA4 high)
MOV.B
#1,STTRIAC
JMP
STATE0
; TRIAC status: wait for 0–cross.
;
; P0.0 Handler: the mains voltage causes interrupt with each
; zero crossing. The TRIAC gate is switched off first, to
; avoid the ignition of the coming half wave. Hardware debounce
; is necessary for the mains signal! See schematic
;
P00_HNDLR MOV
#OMOO+CCIE+OUT,&CCTL4 ; Switch off TRIAC
PUSH
R5
; Save used register
XOR.B
#1,&P0IES
; Change interrupt edge of P0.0
MOV
&TAR,R5
; 0–crossing time to R5
;
; The shorter positive halfwave is measured (TCLK cycles)
;
6-100
BIT.B
#1,&P0IN
; Positive edge of mains?
JZ
P01
; No,
MOV
R5,PRVTAR
; Yes, for next HW calculation
JMP
P03
; Save time of 0–crossing
The Timer_A
P01
MOV
R5,MAINHW
; Measure pos. mains half wave
SUB
PRVTAR,MAINHW
; Difference is length of pos. HW
;
; If STTRIAC is not 0 ( 0 = inactivity) then the next gate
; firing is prepared
;
P03
TST.B
STTRIAC
;
JZ
P02
; STTRIAC = 0: no activity
MOV.B
#2,STTRIAC
; STTRIAC > 0: prep. next firing
;
; The TRIAC firing time is calculated: Timer Reg. + FIRANGL
;
MOV
R5,&CCR4
; TAR to CCR4
ADD
FIRANGL,&CCR4
; TAR + delay –> CCR4
MOV
#OMR+CCIE+OUT,&CCTL4 ; TA4 is reset by INTRPT
;
; The worst case switch–off time for the TRIAC is calculated:
; Zero crossing time + half period – security time
; This calculation ensures a safe distance to the next zero
; crossing of the mains
;
P02
ADD
MAINHW,R5
; TAR + MAINHW
SUB
#SEC,R5
; Subtract security time
MOV
R5,OFFTIME
; worst case switch–off time
POP
R5
; Restore R5
.sect
”TIMVEC”,0FFF0h
; Timer_A Interrupt Vectors
.word
TIM_HND
; Timer Blocks 1..4 Vector
.word
TIMMOD0
; Vector for Timer Block 0
.sect
”P00VEC”,0FFFAh
; P0.0 Vector
.word
P00_HNDLR
.sect
”INITVEC”,0FFFEh
.word
INIT
RETI
; Reset Vector
The TRIAC control example results in a nominal CPU loading uCPU (ranging
from 0 to 1):
uCPU =
1
fMCLK
Σ (nintrpt
f rep )
On-Chip Peripherals
6-101
The Timer_A
Where:
fMCLK
nintrpt
frep
Frequency of the system clock generator (DCO)
Number of cycles executed by the interrupt handler
Repetition rate of the interrupt handler
CCR4 — repetition rate 100Hz
P0.0 — repetition rate 100Hz
u CPU =
79 cycles for the task, 16 cycles overhead
60 cycles for the task, 11 cycles overhead
[Hz]
[Hz]
95 cycles
71 cycles
95 + 100 71
= 0.016
6
1.048 10
100
This shows a CPU loading of approximately 1.6% due to the static TRIAC control.
6.3.8.5
Mixture of Capture and Compare Modes
Any mix of capture and compare mode is possible with the Timer_A. The following software example shows two timer blocks using the capture mode and
three timer blocks using the compare mode. For formulas, see Section 6.3.8.2.
- Capture/Compare Block 0 — a short negative pulse with a 1 kHz repeti-
tion rate is generated and output at the terminal TA0. The pulse is reset
to high by the interrupt handler of timer block 0. The pulse is used for the
precise triggering of an external peripheral. The error of the repetition rate
due to the MCLK frequency used is –0.055%.
- Capture/Compare Block 1 — the period of the input signal at the CCI1A
input terminal is measured in timer clock cycles. The period is measured
from leading edge to leading edge of the input signal. The last measured
value is stored in the RAM word PERIOD. The maximum period length that
can be measured this way is k × 216/fCLK.
- Capture/Compare Block 2 — a square wave with a variable repetition
rate is generated and output at the terminal TA2. The actual cycle count
for one half-wave is stored in the RAM word TIM2REP.
- Capture/Compare Block 3 — the event time of the trailing edge of the
input signal at the CCI3A input terminal is captured. The last captured value is stored in the RAM word STOR3.
- Capture/Compare Block 4 — a square wave with a variable output fre-
quency is generated and output at the TA4 terminal. The output frequency
starts at 4 kHz and decreases to 1 kHz. The square wave is used for the
control of an external peripheral.
6-102
The Timer_A
The software routine is independent of the MCLK frequency used. Only the
FLL multiplier constant, FLLMPY, needs to be redefined if another MCLK frequency is selected.
Table 6–18. Short Description of the Capture and Compare Mix
TIMER BLOCK
TIME INTERVAL
OUTPUT UNIT
COMMENT
0
1 ms
Outputs frequency
Negative pulses: 1 kHz
1
External
Not used
Measures period of signal at input CCI1A, leading edge to
leading edge. Minimum signal length: 2 ms
2
Variable
Outputs frequency
Length of a half-period stored in TIM2REP. (2 kHz max)
3
External
Not used
Captures event time of the trailing edge of the signal input
at CCI3A. Maximum signal = 500 Hz
4
250 µs to 1 ms
Outputs frequency
Decreasing frequency from 4 kHz to 1 kHz
The maximum frequencies and minimum signal length shown do not indicate
the limits of the Timer_A. They are given for the calculation of the loading of
the CPU only.
Figure 6–26 illustrates the above described five tasks:
0FFFFh
Timer Register
0h
65536/Timer Clock
External Pulses
1 kHz at TA0
Signal at CCI1A
Capture Interrupt CCR1
Variable Frequency
at TA2
Period
Signal 1
Frequency Change
Signal at CCI3A
Capture Interrupt CCR3
Captured Trailing Edge
Decreasing Frequency
at TA4
Time
Figure 6–26. Mixture of Capture Mode and Compare Mode With the Continuous Mode
On-Chip Peripherals
6-103
The Timer_A
The software example also shows how to output the ACLK frequency at output
terminal XBUF for reference purposes. An external device may be driven by
this stable and precise crystal-controlled frequency.
A special method is used for the return from interrupt. The interrupt handlers
of the five timer blocks do not return normally with a RETI instruction but jump
back to the start of the timer handler for a test to see if another Timer_A interrupt is pending. This makes it necessary to enable the interrupt at the start of
the timer handler. Otherwise, the interrupt latency time will get too long for other interrupts.
Example 6–34. Mixed Capture and Compare Modes
; Software example: three independent timings and two inputs
; with capturing. The Continuous Mode of Timer_A is used
;
FLLMPY
.equ
64
; FLL multiplier for 2.096MHz
TCLK
.equ
FLLMPY*32768
; TCLK: FLLMPY x fcrystal
OLDRE
.equ
202h
; Time of last edge at CCI1A
PERIOD
.equ
204h
; Calc. period of CCI1A event
TIM2REP
.equ
206h
; Repetition rate Block 2
STOR3
.equ
208h
; Last neg. edge at CCI3A
TIM4REP
.equ
20Ah
; Repetition rate Block 4
TIMAEXT
.equ
20Ch
; Extension for Timer Register
STACK
.equ
600h
; Stack initialization address
INIT
.text 0F000h
; Software start address
MOV
#STACK,SP
; Initialize Stack Pointer
CALL
#INITSR
; Init. FLL and RAM
;
; Initialize the Timer_A: MCLK, Cont. Mode, INTRPT on
; Inputs (CCIxA) and outputs (Tax) of Timer_A are defined
;
6-104
MOV
#ISMCLK+TAIE+CLR,&TACTL
MOV
#OMR+CCIE,&CCTL0
MOV
#CMPE+ISCCIA+SCS+CAP+CCIE,&CCTL1 ;
MOV
#OMT+CCIE,&CCTL2
MOV
#CMNE+ISCCIA+SCS+CAP+CCIE,&CCTL3 ;
MOV
#OMT+CCIE,&CCTL4
; Toggle, INTRPT on
MOV
#0FFFFh,TIM2REP
; Start value Block 2
; Reset Mode, INTRPT on
; Toggle, INTRPT on
The Timer_A
MOV
#((TCLK/4000)+1)/2,TIM4REP ; 4kHz start frequ.
MOV.B
#TA4+TA3+TA2+TA1+TA0,&P3SEL ; Define I/Os
MOV
#1,&CCR0
; Immediate start
MOV
#1,&CCR2
; for the Capture/Compare
MOV
#1,&CCR4
; Registers
CLR
TIMAEXT
; Clear TAR extension
MOV.B
#CBACLK+CBE,&CBCTL ; Output ACLK at XBUF pin
BIS
#MCONT,&TACTL
;
EINT
; Start Timer
; Enable interrupt
MAINLOOP ...
; Continue in background
; Interrupt handler for Capture/Compare Block 0. An ext.
; peripheral is started every 1ms with a negative pulse at
; TA0 (set exactly in time by Output Unit 0). The handler
; resets the negative signal.
;
TIMMOD0
.EQU
$
; Start of handler
ADD
#((2*TCLK/1000)+1)/2,&CCR0 ; For next INTRPT
MOV
#OMOO+CCIE+OUT,&CCTL0; Set TA0: pulse off
BIS
#OMR,&CCTL0
; Back to Reset Mode
; Fall through to TIM_HND
;
; Interrupt handlers for Capture/Compare Blocks 1 to 4.
; The interrupt flags CCIFGx are reset by the reading
; of the Timer Vector Register TAIV
;
TIM_HND
.EQU
$
EINT
TH0
ADD
; Start of Timer_A handler
; Allow interrupt nesting
&TAIV,PC
RETI
; Add Jump table offset
; Vector 0: No interrupt
JMP
TIMMOD1
; Vector 2: Block 1
JMP
TIMMOD2
; Vector 4: Block 2
JMP
TIMMOD3
; Vector 6: Block 3
JMP
TIMMOD4
; Vector 8: Block 4
;
; Block 5. Timer Overflow Handler: the Timer Register is
On-Chip Peripherals
6-105
The Timer_A
; expanded into the RAM location TIMEXT (MSBs)
;
TIMOVH
.EQU
$
; Vector 10: TIMOV Flag
INC
TIMAEXT
; Incr. Timer extension
JMP
TH0
; Test for other interrupts
;
; Timer Block 1 measures the period of an input signal at
; pin CCI1A. The interval between two rising edges is measured
;
TIMMOD1
.EQU
$
; Vector 2: Block 1
MOV
&CCR1,PERIOD
; Time of captured rising edge
SUB
OLDRE,PERIOD
; Calculate period (difference)
MOV
&CCR1,OLDRE
; Store actual edge time
JMP
TH0
; Test for another interrupts
;
; The used time interval delta t2 is stored in TIM2REP.
;
TIMMOD2
.EQU
$
; Vector 4: Block 2
ADD
TIM2REP,&CCR2
; Add time interval
...
JMP
; Task2 starts here
TH0
; Test for another interrupts
;
; Timer Block 3stores the time for a trailing edge at CCI3A
; STOR3 contains the time of the latest trailing edge
;
TIMMOD3
.EQU
$
; Vector 6: Block 3
MOV
&CCR3,STOR3
; Store event time
JMP
TH0
; Test for another interrupts
;
; Block 4 uses a variable repetition rate starting at 4kHz
; cycles and going down to 1kHz.
;
TIMMOD4
6-106
.EQU
$
; Vector 8: Block 4
ADD
TIM4REP,&CCR4
; Add time interval
CMP
#((TCLK/1000)+1)/2,TIM4REP ; Final value?
JHS
TH0
; Yes, no modification
The Timer_A
INC
TIM4REP
; No, modify interval
JMP
TH0
; Test for other interrupts
.sect
”TIMVEC”,0FFF0h
; Timer_A Interrupt Vectors
.word
TIM_HND
; Timer Blocks 1..4 Vector
.word
TIMMOD0
; Vector for Timer Block 0
.sect
”INITVEC”,0FFFEh
; Reset Vector
.word
INIT
;
The software example above results in a maximum (worst case) CPU loading
uCPU (ranging from 0 to 1) by the Timer_A activities:
uCPU =
Where:
fMCLK
nintrpt
frep
uCPU =
fMCLK
Σ (nintrpt
f rep )
Frequency of the system clock generator (DCO)
Number of cycles executed by the interrupt handler
Repetition rate of the interrupt handler
CCR0 — repetition rate 1 kHz
CCR1— rep. rate max. 0.5 kHz
CCR2 — repetition rate 2 kHz
CCR3 — repetition rate 0.5 kHz
CCR4 — repetition rate 8 kHz
TIMOV — rep. rate 32 Hz@2 MHz
30 10 3 + 40
1
15 cycles for the task, 15 cycles overhead
18 cycles for the task, 22 cycles overhead
6 cycles for the task, 22 cycles overhead
6 cycles for the task, 22 cycles overhead
17 cycles for the task, 22 cycles overhead
4 cycles for the task, 20 cycles overhead
500 + 28
[Hz]
[Hz]
30 cycles
40 cycles
28 cycles
28 cycles
39 cycles
24 cycles
2000 + 28 500 + 39 8000 + 24 32
= 0.21
2.096 10 6
This shows a worst case CPU loading of approximate 21% due to the Timer_A
(the task of the timer block 2 is not included). If fMCLK is chosen to be 3.8 MHz,
then the CPU loading is only 11.5%, max.
Any pending Timer_A interrupt during the return phase saves 6 cycles because of the code in this example.
On-Chip Peripherals
6-107
The Timer_A
6.3.8.6
Applications Exceeding the 16-Bit Range of the Timer_A
If the periods of the internal interrupt timings or the time intervals to be captured
are longer than one period of the timer register, then a special method is necessary to take care of the larger time periods. The same is true if a half period
of a generated output frequency is larger than the period of the Timer_A.
This special method, using extension registers for the capture/compare registers is necessary if:
t SIGNAL >
Where:
tSIGNAL
fCLK
k
2 16 k
f CLK
Time interval to be measured or generated
Input frequency at the input divider input of Timer_A
Predivider constant of the input divider (1, 2, 4 or 8)
[Hz]
[Hz]
Figure 6–27 illustrates the hardware and RAM registers used with the
compare mode if the compared values exceed the range of 16 bits (values are
greater than 65535):
15
0
15
TIMOV
TIMAEXT
Timer Register TAR
Carry
Software Compare
15
15
0
RAM or Constant MSBs
Timer
0
Comparison
Value
CCR1
Carry
Add
Timer Clock
Hardware Compare
0
TIMAEXT1
15
0
15
Add
RAM or Constant LSBs
0
∆t
Figure 6–27. Compare Mode with Timer Values Greater than 16 Bit (shown for CCR1)
Figure 6–28 illustrates the hardware and RAM registers used with the capture
mode if the captured values exceed the range of 16 bits (values are greater
than 65535):
6-108
The Timer_A
15
0
15
TIMOV
TIMAEXT
0
Timer Clock
Timer Register TAR
Carry
Capture
15
0
CCR3
Software Save
15
Software Save
0
RAM MSBs
Capture Value 16 bits
15
0
RAM LSBs
Capture Value 32 bits
Figure 6–28. Capture Mode With Timer Values Greater than 16 Bit (shown for CCR3)
Figure 6–29 illustrates five examples. The tasks are defined as follows:
- Capture/Compare Block 0 — a symmetric 1 kHz signal is generated and
output at terminal TA0. It is used for the control of external peripherals (e.g.
ADCs).
- Capture/Compare Block 1 — an internal interrupt with a period ∆t1 = 1s
(considerably longer than the timer register period) is generated.
- Capture/Compare Block 2 — the length, ∆t2, of the high part of the input
signal at the CCI2A input terminal is measured and stored in the RAM
words PP2MSB and PP2LSB. The captured time of the leading edge is
stored in the RAM words TIM2MSB and TIM2LSB.
- Capture/Compare Block 3 — the event time of the leading edge of the
signal at the CCI3A input pin is captured. The captured value is stored in
the RAM words TIM3MSB and TIM3LSB.
- Capture/Compare Block 4 — A symmetrical, external signal is output at
terminal TA4. The time interval, ∆t4, between two output signal edges is
defined in TIM4MSB and TIM4LSB.
The RAM extension of the timer register TIMAEXT is used for all applications
exceeding the 16-bit range of the Timer_A. Due to the low priority of the TIMOV
interrupt, however, checks are necessary in the application software to see if
the RAM extension is updated yet or not.
The software routine is independent of the MCLK frequency used. Only the
FLL multiplier constant, FLLMPY, needs to be redefined if another MCLK frequency is selected. For the example, 3.801 MHz is used.
The task of capture/compare block 0 shows that tasks extending the 16-bit
range of the Timer_A may be mixed with normal tasks that fit into the
16-bit range.
On-Chip Peripherals
6-109
The Timer_A
Table 6–19. Short Description of the Capture and Compare Mix
TIMER BLOCK
TIME INTERVAL
OUTPUT UNIT
COMMENT
0
1 ms
Outputs frequency
Pulses: 1 kHz @ 3.801 MHz
1
1s
Not used
Generation of an internal reference frequency: 1s for
time and date
2
External event
Input pin CCI2A is used
Measures high signal part.Stored in PP2MSB and
PP2LSB
3
External event
Input pin CCI3A is used
Captures event time of the leading edge of the input
signal — stored in TIM3 MSB and TIM3 LSB
4
Variable
Outputs frequency
Symmetric output signal — half period is defined by
TIM4 MSB and TIM4 LSB
Figure 6–29 illustrates the four tasks described above (not to scale):
Content of TIMAEXT
4h
5h
6h
7h
0FFFFh
Timer Register
0h
Frequency Generation
1 kHz at TA0
Internal
Interrupt CCR1
∆ t1 (1s)
∆ t2
Time Measurement
at CCI2A
Capturing of Leading
Edges at CCI3A
Captured Edge
∆ t4
∆ t4
Output Signal
Generation at TA4
Time
Figure 6–29. Five Different Timings Extending the Normal Timer_A Range
6-110
The Timer_A
Example 6–35. Extending the Normal Timer_A Range
The assembler definitions for T1 (V1sMSB and V1sLSB) show a way to define
times exceeding the range of one word.
FLLMPY
.equ
116
; 3.801MHz
TCLK
.equ
FLLMPY*32768
; TCLK: FLLMPY x fcrystal
T1
.equ
1
; T1 is 1 second
.equ
T1*FLLMPY*32768/65536 ; MSBs of 1s value
;
V1sMSB
V1sLSB .equ (T1*FLLMPY*32768)–((T1*FLLMPY*32768/65536)*65536)
TIM2MSB
.equ
202h
; Time of leading edge at CCI2A
TIM2LSB
.equ
204h
;
PP2MSB
.equ
206h
; Length of high signal at CCI2A
PP2LSB
.equ
208h
;
TIM3MSB
.equ
20Ah
; Time of leading edge at CCI3A
TIM3LSB
.equ
20Ch
;
TIM4MSB
.equ
20Eh
; Time interval between TA4 edges
TIM4LSB
.equ
210h
;
TIMAEXT
.equ
212h
; Extension for Timer Register
TIMAEXT1 .equ
214h
; Extension for Timer Block 1
TIMAEXT4 .equ
216h
; Extension for Timer Block 4
STACK
600h
INIT
.equ
; Stack initialization address
.text 0F000h
; Software start address
MOV
#STACK,SP
; Initialize Stack Pointer
CALL
#INITSR
; Init. FLL and RAM
;
; Initialize the Timer_A: MCLK, Cont. Mode, INTRPT on
;
MOV
#ISMCLK+TAIE+CLR,&TACTL
MOV
#OMT+CCIE,&CCTL0
MOV
#OMOO+CCIE,&CCTL1 ; No output, INTRPT on
MOV
#CMBE+ISCCIA+SCS+CAP+CCIE,&CCTL2 ; Both edges
MOV
#CMPE+ISCCIA+SCS+CAP+CCIE,&CCTL3 ; + edge
MOV
#OMT+CCIE,&CCTL4
MOV.B
#TA4+TA3+TA2+TA0,&P3SEL ; Define timer I/Os
; Toggle Mode, INTRPT on
; Toggle Mode, INTRPT on
;
On-Chip Peripherals
6-111
The Timer_A
MOV
#1,&CCR0
; Immediate start for TA0
CLR
TIMAEXT
; Clear Timer Register extension
MOV
#V1sLSB,&CCR1
; Next INTRPT time block 1
MOV
#V1sMSB,TIMAEXT1
MOV
TIM4LSB,&CCR4
MOV
TIM4MSB,TIMAEXT4
MOV.B
#CBMCLK+CBE,&CBCTL ; Output MCLK at XBUF pin
BIS
#MCONT,&TACTL
; Next INTRPT time block 4
;
EINT
; Start Timer
; Enable interrupt
MAINLOOP ...
; Continue in background
; Interrupt handler for Capture/Compare Block 0. An external
; peripheral is started every 1ms with the negative edge of
; TA0 (set exactly from Output Unit 0).
;
TIMMOD0
.EQU
$
; Start of handler
ADD
#((TCLK/1000)+1)/2,&CCR0 ; For next INTRPT
RETI
;
; Interrupt handlers for Capture/Compare Blocks 1 to 4.
; The interrupt flags CCIFGx are reset by the reading
; of the Timer Vector Register TAIV
;
TIM_HND
.EQU
$
; Start of Timer_A handler
ADD
&TAIV,PC
; Add Jump table offset
RETI
; Vector 0: No interrupt
JMP
TIMMOD1
; Vector 2: Block 1
JMP
TIMMOD2
; Vector 4: Block 2
JMP
TIMMOD3
; Vector 6: Block 3
JMP
TIMMOD4
; Vector 8: Block 4
;
; Block 5. Timer Overflow Handler: the Timer Register is
; expanded into the RAM location TIMAEXT (MSBs 16 to 31)
;
TIMOVH
6-112
.EQU
$
; Vector 10: TIMOV Flag
INC
TIMAEXT
; Incr. Timer extension
The Timer_A
RETI
;
;
; Timer Block 1 gen. the 1s reference used for date and time
;
TIMMOD1
TM12
.EQU
$
; Vector 2: Block 1
BIT
#TAIFG,&TACTL
; TIMOV pending?
JNZ
TM11
; Yes, checks necessary
CMP
TIMAEXT,TIMAEXT1
; MSBs also equal?
JEQ
T13
; Yes
TST
&CCR1
; TAIFG = 1: check CCR1
JN
TM12
; CCR1 > 7FFFh: correct values
PUSH
TIMAEXT
; TIMAEXT not yet updated
INC
0(SP)
; Updated value of TIMAEXT
CMP
@SP+,TIMAEXT1
; MSBs equal?
JNE
TM1R
; No, return
ADD
#V1sLSB,&CCR1
; Yes, prepare next INTRPT (1s)
ADDC
#V1sMSB,TIMAEXT1
; MSBs of 1 second
CALL
#RTCLK
; Increment time by 1s
JNC
TM1R
; if C = 1: incr. date
CALL
#DATE
; 00.00 o’clock: next day
RETI
;
TM11
T13
TM1R
RETI
;
; Capture Mode: the high part of the CCI2A input signal is
; measured. The result is stored in PP2MSB and PP2LSB.
;
TIMMOD2
.EQU
$
; Vector 4: Block 2
BIT
#CCI,&CCTL2
; Input signal high?
JZ
TM21
; No,calculation necessary
MOV
&CCR2,TIM2LSB
; Store LSBs of capt. time
MOV
TIMAEXT,TIM2MSB
; MSBs of capt. time
BIT
#TAIFG,&TACTL
; TIMOV pending?
JZ
TM2RET
; No, values are correct
TST
&CCR2
; Yes, check CCR2
JN
TM2RET
; CCR2 > 7FFFh: correct values
On-Chip Peripherals
6-113
The Timer_A
INC
TM2RET
TIM2MSB
;
TM21
TM22
; MSBs not yet updated
RETI
; High part is calculated
MOV
&CCR2,PP2LSB
; Store LSBs of capt. time
MOV
TIMAEXT,PP2MSB
; MSBs of capt. time
BIT
#TAIFG,&TACTL
; TIMOV pending?
JZ
TM22
; No, values are correct
TST
&CCR2
; Yes, check CCR2
JN
TM22
; CCR2 > 7FFFh: correct values
INC
TIM2MSB
; MSBs not yet updated
SUB
TIM2LSB,PP2LSB
; Build difference
SUBC
TIM2MSB,PP2MSB
;
...
; Task 2 to do
RETI
;
; Timer Block 3 captures the time of a leading edge at CCI3A
; TIM3MSB and TIM3LSB contain the time of the actual edge
;
TIMMOD3
TM31
.EQU
$
; Vector 6: Block 3
MOV
&CCR3,TIM3LSB
; Store LSBs of event time
MOV
TIMAEXT,TIM3MSB
; MSBs of event time
BIT
#TAIFG,&TACTL
; TIMOV pending?
JZ
TM31
; No, values are correct
TST
&CCR3
; Yes, check CCR3
JN
TM31
; CCR3 > 7FFFh: correct values
INC
TIM3MSB
; MSBs not yet updated
...
; Task 3 to do
RETI
;
; Timer Block 4 gen. a symmetric pulse at pin TA4
; f = 0.5 x TCLK/TIM4xSB
;
TIMMOD4
TM42
6-114
.EQU
$
; Vector 8: Block 4
BIT
#TAIFG,&TACTL
; TIMOV pending?
JNZ
TM41
; Yes, checks necessary
CMP
TIMAEXT,TIMAEXT4
; MSBs also equal?
The Timer_A
JEQ
T43
; Interval is reached
TST
&CCR4
; TAIFG = 1: check CCR4
JN
TM42
; CCR4 > 7FFFh: correct values
PUSH
TIMAEXT
; TIMAEXT not yet updated
INC
0(SP)
; Updated value of TIMAEXT
CMP
@SP+,TIMAEXT4
; MSBs equal?
JNE
TM4R
; No, return
ADD
TIM4LSB,&CCR4
; LSBs of interval
ADDC
TIM4MSB,TIMAEXT4
; MSBs of interval
XOR
#OUT,&CCTL4
; Toggle TA4 without Output Unit
RETI
;
TM41
T43
...
TM4R
; Task 4
RETI
;
.sect
”TIMVEC”,0FFF0h
; Timer_A Interrupt Vectors
.word
TIM_HND
; Timer Blocks 1..4 Vector
.word
TIMMOD0
; Vector for Timer Block 0
.sect
”INITVEC”,0FFFEh
; Reset Vector
.word
INIT
The example above results in a nominal CPU loading uCPU (ranging from 0
to 1) by the Timer_A activities:
uCPU =
Where:
fMCLK
nintrpt
frep
CCR0 — repetition rate 1 kHz
CCR1 — repetition rate 58 Hz
CCR2 — rep. rate max. 58 Hz
CCR3 — rep. rate max. 58 Hz
CCR4 — rep. rate max. 58 Hz
TIMOV — 58 Hz with 3.8 MHz
1
fMCLK
Σ (nintrpt
f rep )
Frequency of the system clock (DCO)
Number of cycles executed by the interrupt handler
Repetition rate of the interrupt handler
5 cycles for the task, 11 cycles overhead
16 cycles for the task, 16 cycles overhead
30 cycles for the task, 16 cycles overhead
25 cycles for the task, 16 cycles overhead
32 cycles for the task, 16 cycles overhead
4 cycles for the task, 14 cycles overhead
On-Chip Peripherals
[Hz]
[Hz]
16 cycles
32 cycles
46 cycles
41 cycles
48 cycles
18 cycles
6-115
The Timer_A
uCPU =
16
10 3 + 32 58 + 46 58 + 41 58 + 48
3.801 10 6
58 + 18
58
= 0.007
This results in a nominal CPU loading of approximate 0.7% due to the Timer_A
activities (the tasks of the timer blocks 2, 3, and 4 are not included). If fMCLK
is chosen to be 1 MHz, then the CPU loading is 2.6%, max.
6.3.8.7
MSP430 Operation Without a Crystal
The MSP430 may be used without a 32 kHz crystal. The FLL loop is opened
and a DCO tap with a frequency near the desired frequency is used (the dependence of the MCLK frequency on the DCO tap used is shown in the
MSP430 Architecture Guide and Module Library). If an application requires a
relatively stable MCLK frequency, DCO control by software is possible. The
MCLK frequency is compared to the AC line frequency or another external
stable reference frequency. No capture/compare register is necessary, but if
one is used, LCD operation is also possible.
5 V VCC
0V
Xin
VCC
Xout
CIN
XBUF
Software Regulated MCLK
TP.2
Temperature Measurement
TP.1
TP.0
Rref
MSP430
Reference Frequency 230 V AC Line
10 M
COM
Input Signal
SEL
Error
P0.7
kW
rpm
VSS
47 pF
3.5 V
Figure 6–30. MSP430 Operation Without Crystal
Any external reference frequency, fREF, may be used if it is in the range:
k
2 16
f CLK
6-116
< f REF <
f MCLK
100
The Timer_A
The lower limit prevents overflow of the result, the upper (arbitrary) limit prevents overloading of the CPU (the control task needs approximately 50 cycles
per reference period).
If the reference frequency is far above the main frequency (kilo Hertz range),
then it is recommended to use the P0.0 input due to its dedicated interrupt vector.
If the reference frequency disappears, then the MCLK frequency continues to
work with the actual DCO value until the reference frequency appears again.
The frequency of the system clock generator does not step down to the lowest
DCO frequency due to the open control loop.
Example 6–36. Operation Without Crystal
An ac line-powered system works without a crystal. The line frequency, fMAINS
is connected to P0.7, causing interrupt for each positive edge. The P0.7 interrupt handler calculates the cycle difference between two interrupts — which
is the number of MCLK cycles during one mains period — and compares this
difference to a maximum value, HID, and a minimum value, LOWD. If the difference is out of these limits, the DCO is corrected in small steps (22 of
nDCOmod). See Section 6.5 The System Clock Generator for an explanation
of nDCOmod. The nominal value of the frequency fMCLK is chosen to 2 MHz. The
hardware is shown in Figure 6–30.
The software example below works up to a maximum frequency fCLK:
f CLK < 2 16
Where:
fCLK
k
fMAINS
k
f MAINS
Input frequency at the input divider input of Timer_A
Predivider constant of the input divider (1, 2, 4 or 8)
AC Line frequency used
[Hz]
[Hz]
If no LCD is used, then the value LCD is set to 0:
LCD
.equ
0
; No LCD used
The value fLCD used with the example is calculated:
f LCD = f FRAME
Where:
fFRAME
MUX
2
MUX
Recommended frame frequency for the used LCD
Driving method for the used LCD (1, 2, 3, or 4 MUX)
On-Chip Peripherals
[Hz]
6-117
The Timer_A
; Hardware definitions
;
FLLMPY
.equ
64
; Only for FN_x selection
TCLK
.equ
40*50000
; Timer input clock 2.0MHz = MCLK
FMAIN
.equ
50
; Mains frequency 50Hz
FLCD
.equ
256
; 4MUX: fFRAME = 256/8 = 32Hz
LOWD
.equ
TCLK/FMAIN*99/100 ; Lower MCLK limit 99% TCLK
HID
.equ
TCLK/FMAIN*101/100 ; Upper MCLK limit 101%
TCLK LCD .equ
1
; 1: LCD drive implemented too
.equ
202h
; Last TAR content for delta
CNTMAINS .equ
204h
; Mains frequency counter
STACK
300h
; Stack address
;
; RAM definitions
;
TARSTOR
.equ
.text 0F000h
INIT
MOV
#STACK,SP
CALL
#INITSR
; Software start address
; Initialize RAM, set FN_2
;
; Prepare System Clock Generator for operation without crystal
;
BIS.B
#SCG0,SR
; FLL: loop Control off
CLR.B
&SCFQCTL
; Modulation on
MOV.B
#050h,&SCFI1
; Tap 10: 2MHz (nom. with FN_2)
;
; Initialize the Timer_A: MCLK, Cont. Mode, INTRPT on
;
MOV
#ISMCLK+MCONT+TAIE,&TACTL
MOV
#OMOO+CCIE,&CCTL4 ; TA4 not used, Intrpt on
BIS.B
#080h,&P0IE
; Enable INTRPT for P0.7 (mains)
BIC.B
#080h,&P0IES
; INTRUPT for leading edge
.if
LCD=1
; If LCD is needed too
MOV.B
#0,&BTCTL
; Prepare Basic Timer. Use fLCD
.endif
MOV.B
EINT
6-118
#CBMCLK+CBE,&CBCTL ; MCLK at XBUF pin
The Timer_A
MAINLOOP ...
;
; Interrupt handler Port0: P0.2 to P0.7. The mains input
; is at pin P0.7
;
P072_HNDL PUSH
P07T1
P07T2
R5
; Save R5
BIT.B
#080h,&P0FG
; P0.7 (mains) INTRPT?
JZ
P062
; No, check P0.6 to P0.2
MOV
&TAR,R5
; Act. Timer Register
SUB
TARSTOR,R5
; Build delta MCLK cycles
MOV
&TAR,TARSTOR
; For next MCLK measurement
CMP
#LOWD,R5
; fMCLK < lower MCLK limit?
JHS
P07T1
; No, check upper limit
INC.B
&SCFI1
; Yes, increase DCO frequency
CMP
#HID,R5
; fMCLK > upper MCLK limit?
JLO
P07T2
; No, return
DEC
&SCFI1
; Yes, decrease DCO frequency
INC
CNTMAINS
; Mains counter + 1 (time base)
MOV.B
&P0IFG,R5
; Read P0 flags
BIC.B
R5,&P0IFG
;
P062
....
P072RET
POP
; Reset read flags (P0.7 to P0.2)
; Process inputs P0.6 to P0.2
R5
; All done, return
LCD=1
; If LCD is needed too
RETI
;
.if
;
; Interrupt handlers for Capture/Compare Blocks 1 to 4.
;
TIM_HND
ADD
&TAIV,PC
RETI
; Add Jump table offset
; Vector 0: No interrupt
JMP
TIMMOD1
; Vector 2: Block 1
JMP
TIMMOD2
; Vector 4: Block 2
JMP
TIMMOD3
; Vector 6: Block 3
JMP
TIMMOD4
; Vector 8: Block 4
RETI
; TIMOV not used here
On-Chip Peripherals
6-119
The Timer_A
;
; The interrupt handlers for the Timer Blocks 0 to 3 follow
; They are not implemented here
;
TIMMOD0
.equ
$
; Handler for Timer Block 0
TIMMOD1
.equ
$
; Handler for Timer Block 1
TIMMOD2
.equ
$
; Handler for Timer Block 2
TIMMOD3
.equ
$
; Handler for Timer Block 3
RETI
;
; Timer Block 4: interrupt handler for the LCD drive. The
; BTCNT1 register – which generates fLCD – is incremented
; twice with the fLCD period to generate both edges
;
TIMMOD4
ADD.B
#010h,&BTCNT1
; Toggle BTCNT1.4
ADD
#TCLK/(2*FLCD),&CCR4 ; Add 1/(2*fLCD)
RETI
.endif
; End of LCD drive part
”TIMVEC”,0FFF0h
; Timer_A Interrupt Vectors
.word
TIM_HND
; Timer Blocks 1..4 Vector
.word
TIMMOD0
; Vector for Timer Block 0
.sect
”P072VEC”,0FFE0h ; P0.x Vector
.word
P072_HNDLR
; Handler for P0.7 to P0.2
.sect
”INITVEC”,0FFFEh
; Reset Vector
.word
INIT
;
.sect
The example results in a maximum (worst case) CPU loading uCPU (ranging
from 0 to 1) by the Timer_A activities:
uCPU =
Where:
fMCLK
nintrpt
frep
LCD timing — 2×256 Hz
MCLK frequency control 50 Hz
6-120
1
fMCLK
Σ (nintrpt
f rep )
Frequency of the system clock (DCO)
Number of cycles executed by the interrupt handler
Repetition rate of the interrupt handler
10 cycles for the task, 16 cycles overhead
49 cycles for the task, 11 cycles overhead
[Hz]
[Hz]
26 cycles
60 cycles
The Timer_A
uCPU =
26
512 + 60 50
= 0.008
2.0 10 6
This results in a CPU loading of approximate 0.8% due to the Timer_A tasks,
the LCD timing, and the MCLK control.
6.3.8.8
RF Timing Generation
Different modulation methods for RF timing generation are shown in Figure
6–32. All are used with metering devices (electric meter, water meter, gas meter, heat allocation meters, etc.) for the long-distance readout of the consumption.
For the generation of the modulated RF, normally a regulated 6-V supply voltage is used. If this voltage is not available, the step-up power supply shown
in figure 6–31 may be used. An existing supply voltage (here 3 V) is transformed by the step-up circuit to 8 V and regulated down to the desired 6 V. The
step-up frequency is delivered by the MSP430. The XBUF output, with its four
possible output frequencies, is used. The sequence starts with the ACLK frequency (32.768 kHz) and then lowers to ACLK/2 and ACLK/4. In this way, the
CPU is not loaded with the frequency generation at all. Figure 6–31 illustrates
the connection of an RF interface module to an MSP430.
32 kHz
Xin Xout
8V
3V
6V
L
VCC
MSP430
VCC
Voltage
Regulator
Step-Up Frequency
XBUF
C
VSS
RF-Antenna
RF-Module
GND
Modulation
TA0
Modulation
Figure 6–31. RF Interface Module Connection to the MSP430
Modulation modes used are:
- Amplitude Modulation — the RF oscillator is switched on for a logical 1
and switched off for a logical 0 (100% modulation).
- Biphase Code — the information is represented by a bit time consisting
of one half bit without modulation and one half bit with full modulation. A
logical 1 starts with 100% modulation, a logical 0 starts with no modulation.
On-Chip Peripherals
6-121
The Timer_A
- Biphase Space — a logical 1 (space) is represented by a constant signal
during the complete bit time. A logical 0 (mark) changes the signal in the
middle of the bit time. The signal changes after each transmitted bit.
The last two modulation modes do not have a dc part. Figure 6–32 shows all
three modulations modes. If the LSBs are transmitted first, the information
sent is 096h.
0
1
1
0
1
0
0
1
Information 096h
Amplitude
Modulation
RF On
Biphase Code
RF Off
Biphase Space
Bit Length
Time
Figure 6–32. RF Modulation Modes
The timer block 0 is used with the software examples for all three modes due
to the following two reasons:
- The fastest possible response. The decision making with the timer vector
register is not necessary for the timer block 0 — it uses its own, dedicated
interrupt vector.
- The capture/compare register 0 interrupts not only if the timer register and
CCR0 are equal (like with the other CCRs), but also if the timer register
contains a higher value. This prevents the loss of synchronity due to other
interrupts during the transmission.
The software of the other four timer blocks is not shown with the following software routines. Many examples of their use are given in the previous examples.
The software examples also show how to output the ACLK/2 frequency at output terminal XBUF. This accurate frequency may be used for the clocking of
external peripherals.
6-122
The Timer_A
6.3.8.8.1 RF Amplitude Modulation
This is the simplest method — a set data bit (1) switches on the RF, a zero data
bit switches off the RF.
0
1
1
0
1
0
0
1
Information 096h
Amplitude
Modulation
Time
Figure 6–33. Amplitude Modulation
- If the speed of the software is not sufficient, dedicated registers (R4 to
R15) may be used for RFDATA and RFCOUNT. This register method is
used with the biphase code and biphase space software. See sections
8.8.2 and 8.8.3.
- If the MSB needs to be output first, then the instruction
RRA RFDATA
(after label TM01) is simply replaced by RLA RFDATA
Example 6–37. Amplitude Modulation Methods
; Software example: Amplitude Modulation methods.
;
; Hardware definitions
;
FLLMPY
.equ
48
; FLL multiplier for 1.572MHz
TCLK
.equ
FLLMPY*32768
; TCLK: FLLMPY x fcrystal
fRF
.equ
19200
; Bit rep. frequency (Baud Rate)
Bit_Length .equ
((2*TCLK/fRF)+1)/2 ; Bit length (TCLK cycles)
STACK
600h
.equ
; Stack initialization address
;
; RAM definitions. Use dedicated CPU registers (R4 to R15)
; if the speed is not sufficient
;
RFDATA
.equ
202h
; 16 bit data to be sent
TIMAEXT
.equ
204h
; 32 bit extension Timer_A
RFCOUNT
.equ
206h
; Counter for 16 bits (byte)
On-Chip Peripherals
6-123
The Timer_A
;
.text 0F000h
; Software start address
MOV
#STACK,SP
; Initialize Stack Pointer
CALL
#INITSR
; Init. FLL and RAM
;
INIT
;
; Initialize the Timer_A: MCLK, Cont. Mode, no INTRPT
;
MOV
#ISMCLK+CLR,&TACTL
MOV
#OMOO,&CCTL0
; Reset TA0, INTRPT off
MOV.B
#TA0,&P3SEL
; Define TA0 output
CLR
TIMAEXT
; Clear TAR extension
MOV.B
#3,&CBCTL
; Output ACLK/2 at XBUF pin
BIS
#MCONT,&TACTL
; Start Timer
;
EINT
; Enable interrupt
MAINLOOP ...
; Continue in background
;
; A 16 bit value is to be output. R5 contains data
;
MOV
R5,RFDATA
; Value into data word
MOV.B
#16+2,RFCOUNT
; Bit count+2 to RFCOUNT
MOV
&TAR,&CCR0
; For fast response:
ADD
#100,&CCR0
; Time of 1st bit test
MOV
#OMOO+CCIE,&CCTL0 ; Enable interrupt for CCR0
...
; Continue in background
;
; Test in background if 16 bits are output: RFCOUNT = 0
;
TST.B
RFCOUNT
JZ
BPC_MADE
...
; Output completed?
; Yes, interrupt bit is reset
; No continue
;
; Interrupt handler for Capture/Compare Block 0.
; Data in RFDATA is output: LSB first
;
6-124
The Timer_A
TIMMOD0
.EQU
$
; Start of CCR0 handler
ADD
#Bit_Length,&CCR0 ; Time of next bit change
DEC.B
RFCOUNT
; Bit count – 1
JNZ
TM01
; Not zero: continue
MOV
#OMR,&CCTL0
; Finish output: reset TA0
RETI
; INTRPT off
;
TM01
RRA
RFDATA
; Next bit of RFDATA
JC
TM02
; Bit is one
MOV
#OMR+CCIE,&CCTL0
; Bit is 0: prepare reset
RETI
;
TM02
MOV
#OMSET+CCIE,&CCTL0 ; Bit is 1: prepare set
RETI
;
;
.sect
”TIMVEC”,0FFF2h
; Timer_A Interrupt Vector
.word
TIMMOD0
; Vector for Timer Block 0
.sect
”INITVEC”,0FFFEh
; Reset Vector
.word
INIT
The example results in a maximum (worst case) CPU loading uCPU (ranging
from 0 to 1) by the Timer_A activities:
uCPU =
Where:
fMCLK
nintrpt
frep
1
fMCLK
( nintrpt
f rep ) =
33 19200
= 0.44
1.572E6
Frequency of the system clock (DCO)
Number of cycles executed by the interrupt handler
Repetition rate of the interrupt handler
[Hz]
[Hz]
The RF amplitude modulation loads the CPU to 44% of its capacity when running with 1.572 MHz.
On-Chip Peripherals
6-125
The Timer_A
6.3.8.8.2 RF Biphase Code Modulation
The biphase code modulation represents each data bit by a change of the information in the middle of the sent data bit:
- Data bit is 0: the information starts with 0 (RF off) and in the middle of the
info bit the RF is switched on for the remaining half of the bit time.
- Data bit is 1: the information starts with 1 (RF on) and in the middle of the
info bit the RF is switched off for the remaining half of the bit time.
0
1
1
0
1
0
0
1
Information 096h
Biphase Code
Time
Figure 6–34. Biphase Code Modulation
Due to the information change in the middle of the data bit, biphase code modulation needs twice the repetition rate of amplitude modulation — 38400 bits/
second for a baud rate of 19200. Therefore, a system clock frequency of 1.048
MHz is not sufficient for this modulation. Instead, 1.606 MHz is selected for the
MCLK frequency for biphase modulation. All members of the MSP430 family
can use this frequency.
The information is not converted in real time due to the high transmission rate
of 38400 bits/second. The conversion is made before the transmission — bytes from eight arbitrary addresses (ADDRESS0 to ADDRESS7) are converted
and the bit pattern stored in a RAM block of 128 bits in length. This 128-bit buffer is output in real time.
Example 6–38. Biphase Code Modulation
; Software example: Bi–Phase Code Modulation
;
Input in R6
Output in R5
; Some examples:
096h
–>
06996h
;
000h
–>
0AAAAh
;
0FFh
–>
05555h
;
069h
–>
09669h
;
011h
–>
0A9A9h
;
6-126
Input –> Output
The Timer_A
; Hardware definitions
;
FLLMPY
.equ
49
; FLL multiplier for 1.606MHz
TCLK
.equ
FLLMPY*32768
; TCLK: FLLMPY x fcrystal
fRF
.equ
38400
; Bit rep. frequency
Bit_Length .equ
((2*TCLK/fRF)+1)/2 ; Bit length (TCLK cycles)
STACK
600h
; Stack initialization address
.equ
;
; RAM Definitions
;
RF_BLK
.equ
202h
; Converted data 16 bytes
TIMAEXT
.equ
212h
; 32 bit extension Timer_A
.text 0F000h
; Software start address
MOV
#STACK,SP
; Initialize Stack Pointer
CALL
#INITSR
; Init. FLL and RAM
;
INIT
;
; Initialize the Timer_A: MCLK, Cont. Mode, INTRPT on
;
MOV
#ISMCLK+TAIE+CLR,&TACTL
MOV
#OMOO,&CCTL0
; Reset TA0, INTRPT off
MOV.B
#TA0,&P3SEL
; Define TA0 output
CLR
TIMAEXT
; Clear TAR extension
MOV.B
#3,&CBCTL
; Output ACLK/2 at XBUF pin
BIS
#MCONT,&TACTL
; Start Timer
;
EINT
; Enable interrupt
MAINLOOP ...
; Continue in background
;
; 64 bits of data is to be output with Bi–Phase Code Modul.
; The data is converted into a 128–bit RAM block with the
; Bi–Phase Code sequence
;
CLR
R5
; For Bi–Phase Space necessary
MOV
#RF_BLK,R8
; Address 8 word send block
MOV.B
ADDRESS0,R6
; 1st data byte to R6
On-Chip Peripherals
6-127
The Timer_A
CALL
#BI_PHASE_CODE
; Convert it to 16 bits
MOV
R5,0(R8)
; Converted data to RF–Block
...
; Convert next 6 bytes same way
MOV.B
ADDRESS7,R6
; 8th data byte to convert to R6
CALL
#BI_PHASE_CODE
; Convert to 16 bits
MOV
R5,14(R8)
; Converted data to RF–Block
MOV
#RF_BLK+16,R9
; 1st word after RF_BLK
MOV
#16+1,R6
; Bit count for 1st 16 bits
MOV
@R8+,R5
; 1st 16 bits for output
;
;
; Switch off all interrupts to allow exact RF timing. This is
; not necessary if ALL OTHER interrupt handlers start with
; an EINT instruction
;
...
;
MOV
&TAR,&CCR0
; For fast response:
ADD
#100,&CCR0
; Time of 1st bit test
MOV
#OMOO+CCIE,&CCTL0 ; Enable interrupt for CCR0
...
; Continue in background
;
; Test in background if 128 bits are output: INTRPT of Timer
; Block 0 is switched off by the INTRPT handler
;
BIT
#CCIE,&CCTL0
; Output completed?
JZ
BPC_MADE
; Yes
...
; No continue
;
; Interrupt handler for Capture/Compare Block 0
; Data in RF_BLK is output: LSB first
;
TIMMOD0
6-128
.EQU
$
; Start of CCR0 handler
ADD
#Bit_Length,&CCR0 ; For next INTRPT
DEC
R6
; Bit count – 1
JNZ
TM01
; Not zero: continue
The Timer_A
MOV
@R8+,R5
; Next 16 bits for output
MOV
#16,R6
; Bit count
CMP
R9,R8
; End of buffer reached?
JHS
TM03
; Yes, finish output
RRC
R5
; Next data bit to carry
JC
TM02
; Bit is one
MOV
#OMR+CCIE,&CCTL0
; Bit is 0: prepare reset
;
TM01
RETI
;
TM02
MOV
#OMSET+CCIE,&CCTL0 ; Bit is 1: prepare set
RETI
;
TM03
MOV
#OMR,&CCTL0
RETI
; Output complete:
; Reset TA0, INTRPT off
;
; Subroutine transforms the data byte in R6 (8 bits) to
; Bi–Phase Code in R5 (16 bits). CALL + 86 cycles/byte
;
BI_PHASE_CODE .equ $
BIPL
; Conversion routine
MOV
#8,R7
; Convert 8 bits
RRA
R6
; LSB to Carry
RRC
R5
; Bit to R5 MSB
BIT
#8000h,R5
; Copy bit once more
RRC
R5
; to R5
XOR
#8000h,R5
; and invert it
DEC
R7
; Bit count – 1
JNZ
BIPL
; 8 bits not yet converted
RET
; 16 info bits in R5
;
.sect
”TIMVEC”,0FFF2h
; Timer_A Interrupt Vector
.word
TIMMOD0
; Vector for Timer Block 0
.sect
”INITVEC”,0FFFEh
; Reset Vector
.word
INIT
The example results in a CPU loading uCPU (ranging from 0 to 1) by the Timer_A activities:
On-Chip Peripherals
6-129
The Timer_A
uCPU =
1
fMCLK
Σ ( nintrpt
Where:
fMCLK
nintrpt
frep
f rep ) =
(27
15 / 16 + 34 1 / 16 ) 2 19200
1.606E6
Frequency of the system clock (DCO)
Number of cycles executed by the interrupt handler
Repetition rate of the interrupt handler
= 0.66
[Hz]
[Hz]
This results in a MSP430 CPU load of 66% when outputting Biphase Code
Modulation at 19200 baud with an MCLK frequency of 1.606 MHz.
RF Biphase Space Modulation
The realtime software — that outputs the 128-bit block — is exactly the same
as the biphase code modulation shown in Section 8.8.2. Only the subroutine
that converts the binary data to the biphase space code is different — the actual bit depends also on the previous bit. Therefore, only the different conversion
subroutine is shown below. The CPU loading is, due to the equal real time part,
is also 66%, like it is for the biphase code modulation.
0
1
1
0
1
0
0
1
Information 096h
Bi-Phase Space
Time
Figure 6–35. Biphase Space Modulation
Example 6–39. Biphase Space Modulation
The information cannot be converted in real time due to the high transmission
speed of 38400 bits/second. The conversion is made before the transmission:
bytes from eight arbitrary addresses (ADDRESS0 to ADDRESS7) are converted and the bit pattern is stored in a RAM block with 128 bits in length. This
128-bit buffer is output in real time by the timer block 0. See Section 8.8.2.
;
; Subroutine converts the data byte in R6 (8 bits) to
; Bi–Phase Space Code in R5 (16 bits). CALL + 162 cycles/byte
; R5 contains the MSB (2nd half bit) of the last conversion.
6-130
The Timer_A
;
;
Input in R6
Output in R5
; Some examples:
096h
–>
02B4Dh Prev. 2nd half bit = 0
;
000h
–>
05555h
;
0FFh
–>
03333h
;
069h
–>
04D2Bh
;
011h
–>
054abh
;
016h
–>
0AB4Dh
;
000h
–>
0AAAAh Prev. 2nd half bit = 1
;
0FFh
–>
0CCCCh
;
BI_PHASE_SPACE .equ $
BPSL
; Conversion routine
MOV
#8,R7
; Number of bits
CLR
R9
; Table Pointer
BIT
#8000h,R5
; Test last half bit (MSB R5)
RLC
R9
; Bit to LSB
RRC
R6
; Next info bit
RLC
R9
; 2 bit table address in R9
MOV.B
BPSTAB(R9),R9
; Data for 2 bits to be sent
SWPB
R9
; 00x0 –> x000
CLRC
; Free two bits for new data
RRC
R5
; in R5
RRA
R5
ADD
R9,R5
; Insert new data to MSBs
DEC
R7
; Bit count – 1
JNZ
BPSL
; 8 bits not yet converted
RET
; 16 info bits in R5
;
; Table with 2–bit info for all possible four bit combinations
;
BPSTAB
Prev Half–Bit
Curr. Bit
Info Bits
.byte
040h
;
0
0
10
.byte
0C0h
;
0
1
11
.byte
080h
;
1
0
01
.byte
000h
;
1
1
00
The example results in a constant CPU loading uCPU (ranging from 0 to 1) by
the Timer_A activities of 66%, as with the biphase code modulation due to the
equal RF part.
On-Chip Peripherals
6-131
The Timer_A
6.3.8.9
Real Time Clock
The Timer_A can also be used as a real time clock (RTC), especially in the low
power mode 3 (LPM3). The ACLK is summed up and when one of the capture/
compare registers is equal to the timer register (TAR), then an interrupt wakes
up the CPU. The interrupt handler adds the time interval to the capture/
compare register and returns to LPM3. Due to the available five capture/
compare registers, up to five independent wake up frequencies may be programmed. Their handlers have the same structure as shown here for timer
block 1.
The timer overflow delivers an additional 0.5 Hz wake up frequency
(216/32768 Hz = 2 s). If this timing is sufficient, no interrupt by a capture/
compare register is necessary.
0FFFFh
Timer Register
0h
2s
ACLK Pulses
32.768 kHz
0.25 s
Wake Up 0.25 s
Timer Block 1
Wake Up 2 s
Timer Overflow
Time
Figure 6–36. Real Time Clock Application of the Timer_A
The software example shows a real time application with a wake up every 0.25
s initiated by timer block 1 (the software for the other timer blocks is not shown).
The 0.25 s interrupt increments a RAM counter (RTC_CNT) and updates the
time and date if a full second has elapsed.
Example 6–40. Real Time Clock Application of the Timer_A
; Software example: Real Time Clock application of the
; Timer_A running in the Continuous Mode
;
; Hardware definitions
;
6-132
The Timer_A
FLLMPY
.equ
32
; FLL multiplier for 1.048MHz
TCLK
.equ
FLLMPY*32768
; TCLK: FLLMPY x fcrystal
RTC_DELTA .equ
32768/4
; ACLK delta for 4Hz wake–up
STACK
600h
; Stack initialization address
.equ
;
; RAM definitions
;
RTC_CNT
.equ
202h
; RTC counter for the 4Hz
TIMAEXT
.equ
204h
; TAR extension
;
.text 0F000h
; Software start address
MOV
#STACK,SP
; Initialize Stack Pointer
CALL
#INITSR
; Init. FLL and RAM
;
INIT
;
; Initialize the Timer_A: ACLK, Cont. Mode, INTRPT on
;
MOV
#ISACLK+TAIE+CLR,&TACTL
CLR
&CCR0
; Defined start value
CLR
TIMAEXT
; Clear TAR extension
MOV
#OMOO+CCIE,&CCTL1 ; CCR1 used for RTC
MOV.B
#CBACLK+CBE,&CBCTL ; Output ACLK at XBUF pin
BIS
#MCONT,&TACTL
EINT
MAINLOOP
; Start Timer
; Enable interrupt
...
; Continue in background
;
; Enter LPM3. The watchdog must be held (ACLK continues)
;
MOV
#05A00h+HOLD+CNTCL,&WDTCTL ; Hold watchdog
BIS
#CPUOFF+GIE+SCG1+SCG0,SR ; Enter LPM3
...
;
; Interrupt handlers for Capture/Compare Blocks 1 to 4.
; The interrupt flags CCIFGx are reset by the reading
; of the Timer Vector Register TAIV
;
On-Chip Peripherals
6-133
The Timer_A
TIM_HND
ADD
&TAIV,PC
RETI
; Add Jump table offset
; Vector 0: No interrupt
JMP
TIMMOD1
; Vector 2: Block 1
JMP
TIMMOD2
; Vector 4: Block 2
JMP
TIMMOD3
; Vector 6: Block 3
JMP
TIMMOD4
; Vector 8: Block 4
;
; Block 5. Timer Overflow Handler: the Timer Register is
; expanded into the RAM location TIMAEXT (MSBs). TIMAEXT is
; incremented every 2s
;
TIMOVH
.EQU
$
; Vector 10: TIMOV Flag
INC
TIMAEXT
; Incr. Timer extension
...
; 0.5Hz task starts here
RETI
;
;
; Timer Block 1 is used for the Real Time Clock
; Repetition Rate = 4Hz (0.25s)
;
TIMMOD1
.EQU
$
; Vector 2: Block 1
ADD
#RTC_DELTA,&CCR1
; Add time interval (0.25s)
...
; RTC Task 4Hz starts here
INC
RTC_CNT
; Increment 4Hz counter
BIT
#3,RTC_CNT
; one second elapsed?
JZ
TASK
RETI
; Yes
; No, back to LPM3
;
TASK
TM1
CALL
#RTCLK
; Time + 1s
JNC
TM1
; If carry: 00.00 o’clock
CALL
#DATE
; Next day
RETI
; Return to LPM3
;
6-134
.sect
”TIMVEC”,0FFF0h
; Timer_A Interrupt Vectors
.word
TIM_HND
; Vector for blocks 1 to 4
.word
TIMMOD0
; Vector for Timer Block 0
.sect
”INITVEC”,0FFFEh
.word
INIT
; Reset Vector
The Timer_A
The example results in a maximum (worst case) CPU loading uCPU (ranging
from 0 to 1) by the Timer_A activities:
CCR1 — repetition rate 4 Hz
TIMOV — repetition rate 0.5 Hz
uCPU =
1
fMCLK
Where:
fMCLK
nintrpt
frep
16 cycles for the task, 16 cycles overhead
4 cycles for the task, 14 cycles overhead
Σ ( nintrpt
frep ) =
32 cycles
18 cycles
32 4 + 18 0.5
= 0.00013
1.048E6
Frequency of the system clock (DCO)
Number of cycles executed by the interrupt handler
Repetition rate of the interrupt handler
[Hz]
[Hz]
This result means that the MSP430 CPU uses the low power mode 3 during
99.987% of the time when running the RTC software shown (time and date
tasks are not included).
On-Chip Peripherals
6-135
The Timer_A
6.3.8.10 Conclusion
This section demonstrated the many and versatile possibilities of the Timer_A
running in the continuous mode. Any mixture of capture and compare modes
is possible with the five capture/compare registers (CCRx). It is also possible
to change the mode of a capture/compare register during the run: a capture/
compare register used in capture mode during the calibration process may be
used as a compare register during the normal run and vice versa.
Also worth mentioning is the absolute synchronization of the generated timings. This is a result of the single timer register used for all capture/compare
registers. This feature is very important for digital motor control applications.
The read/write feature of all the Timer_A registers additionally offers possibilities beyond the scope of this discussion.
6.3.9
Software Examples for the Up Mode
This section shows several proven application examples for the Timer_A running in the up mode. The software definitions appear near the beginning of this
section. Whenever possible, the abbreviations defined in the MSP430 Architecture Guide and Module Library are used with the software examples.
The software examples are written to be independent of the MCLK frequency
in use. Only the FLL multiplier constant, FLLMPY, and the period for the period
register need to be redefined if another combination is needed. The source
lines for the definition of these important values are:
FLLMPY
.equ
122
; 1. FLL multiplier
fper
.equ
19200
; 2. PWM Repetition rate
TCLK
.equ
FLLMPY*32768/4
; 3. FLLMPY x fcrystal/4
PERIOD
.equ
((2*TCLK/fper)+1)/2
; 4. Period of the PWM
- Definition of the CPU frequency fMCLK. The multiplier FLLMPY for the
digitally controlled oscillator (DCO) is defined. The value for the actual frequency fMCLK is (FLLMPY × 215). The value 122 stands for fMCLK = 122
× 215 = 3.9977 MHz.
- Definition of the desired repetition rate. The value 19200 stands for fper
= 19.2 kHz.
- Definition of the input frequency for the Timer Register (TAR). The ex-
pression /4 indicates that the input divider is set to the Divide-by-Four
mode. The shown value stands for TCLK = 3.9977 MHz/4 = 999.424 kHz.
Only the selected predivider for the input divider (here /4) needs to be defined.
- Calculation of the TCLK cycles for the defined period. This expression
is used for the rounding of the result. No change is necessary for this line.
6-136
The Timer_A
6.3.9.1
Common Remarks
The up mode is designed primarily for pulse width modulation (PWM) or DC
generation applications. If none of these applications is needed, then the continuous mode, with its five independent timings, should be used.
Advantages of the Up Mode:
- Free run without CPU load for stable PWM values (e.g. DAC, PWM)
- High PWM frequency is possible due to the pure hardware control
- Clever selected timings are usable for more than one real time job
Disadvantages of the Up Mode:
- Dominance of the period register — it defines the time frame for all other
capture/compare blocks (C/C Blocks)
- Current switching occurs at the same time for all PWM outputs — this is
the case when the timer register (TAR) equals the period register CCR0
6.3.9.1.1 Initialization
The initialization subroutine, INITSR, is used in all examples. This subroutine
was described in Section 6.3.8.1. It includes the following tasks:
- Checks the reason for the initialization (switch on of the supply voltage,
watchdog interrupt, or activation of the RESET input)
- Clears the RAM — or not — depending on the result of the above check.
- Programs the system clock oscillator (multiplication factor N and optimum
current switch FN_2, FN_3, or FN_4)
- Allows the digitally controlled oscillator to settle at the appropriate tap, pro-
viding the correct MCLK frequency
6.3.9.1.2 Timer Clock
The information in this section is also valid for the continuous mode and the
up/down mode.
All software examples use the value FLLMPY — it defines the master clock
frequency, fMCLK.
On-Chip Peripherals
6-137
The Timer_A
f MCLK = FLLMPY
f crystal
If this frequency, fMCLK is too high for the application (it causes values for the
timer registers exceeding the range from 0 to 65535, for example), then the
input divider of the Timer_A may be used. This allows a prescaling of 1, 2, 4,
or 8 for the timer input frequencies (fMCLK, fACLK or fTACLK)
Example 6–41. Prescaling Factor of 2
For a required prescaling of 2, the definitions at the start of each example are
simply changed to:
FLLMPY
.equ
100
; FLL multiplier for 3.2768MHz
TCLK
.equ
FLLMPY*32768/2
; Timer Clock = 1.6384MHz
;
; Input Divider D2 is used to get MCLK/2 for the TCLK
;
MOV
#ISMCLK+D2+MUP+TAIE+CLR,&TACTL ; Use /2 divider
The examples normally use an internally generated timer clock — the MCLK
or the ACLK. It is also possible to use an external clock. This clock signal is
connected to the TACLK terminal and selected with the following code sequence during the initialization:
; Ext. clock, Up Mode, Interrupt enabled, Timer Reg. cleared
;
MOV
#ISTACLK+MUP+TAIE+CLR,&TACTL
BIS.B
#TACLK,&P3SEL
; External clock to Timer_A
6.3.9.1.3 Timing Considerations
The five independent timings provided by the continuous mode are not possible anymore in the noncontinuous modes because the period register
(CCR0) dictates the timing frame for all other capture/compare blocks. Therefore, the period of the timer must be chosen very carefully to allow all the necessary timings. For example, a period chosen for PWM with 19.2 kHz also allows the timing for a software UART running at 2400 baud (19200/8) or 4800
baud (19200/4).
6-138
The Timer_A
To allow comparison and capturing also with the noncontinuous modes, it is
a good practice to have not only a register that counts the overflows (period
counter) — like TIMAEXT used with the continuous mode — but also a 16-bit
or 32-bit register that counts the TCLK cycles. This allows the use of simple
additions for the calculation of a time point. Otherwise, a multiplication is necessary (period counter × period length) to get the elapsed time. The examples
given use both registers:
TIMACNT
TIMACYCx
Period counter
Cycle counter
counts the number of full periods
counts the cycles of the timing (one or more words)
See also figure 6–43; the contents of these two registers are shown there for
an example.
Frequencies used by the CPU and the Timer_A. The following software examples are (nearly) independent of the MCLK and timer clock frequency in
use. During the assembly, the new values for the period register and the timer
clock frequency are calculated. A worst case calculation is necessary if a
fMCLK that is too low is used.
Update of Extension Registers. Unlike the case with the continuous mode,
the update of these extension registers is made with the interrupt handler of
the period register (CCR0). This has three reasons:
- The interrupt of the period register occurs one cycle before the TIMOV in-
terrupt
- The period register (CCR0) has the highest interrupt priority of all Timer_A
interrupts
- A dedicated interrupt vector (address FFF2h) allows the fastest response
to interrupt requests
Real Time Environment. For all applications of the Timer_A running in one
of the noncontinuous modes and using interrupt frequencies in the kilohertz
range, it is recommended that strict real time environment programming be
used. Otherwise, interrupt handlers are delayed and information may be lost.
To achieve a real time environment, the following simple rules should be applied to all interrupt handlers:
- The first instruction after the processing of time critical data — Timer_A
related data for the Timer_A handlers, for example — should be the EINT
(Enable Interrupt) instruction. This allows nested interrupts, a feature possible due to the stack architecture of the MSP430 family.
- Interrupt handlers should be as short as possible. Only the absolutely nec-
essary tasks should be executed (incrementing of counters, update of the
On-Chip Peripherals
6-139
The Timer_A
status bytes, etc.). The time consuming main tasks should be shifted to the
background, where the software executes them according to the status
byte information.
Output Units. The PWM examples shown all use the set/reset mode or the
reset/set mode of the output units. This has the advantage — compared to the
use of toggling — that no incorrect pulse widths can be generated during the
change of the pulse width.
6.3.9.1.4 Interrupt Overhead
The calculations for the CPU loading that are appended to the software examples split the necessary cycles for each capture/compare block into two parts:
- Overhead — This part sums the cycles that are necessary for the CPU
to execute the interrupt (saving of the program counter and the status register, decision on which interrupt needs to be served, restoring of the CPU
registers).
- Update or Task — This part actually does the work that needs to be done
(incrementing of counters, changing of status bytes, etc.).
The number of overhead cycles shown with the examples are derived from the
following sequences:
J
Interrupt of the period register CCR0 (or other interrupt sources with a
dedicated vector):
Cycles from interrupt request to 1st instruction of the interrupt handler:
Return from Interrupt instruction:
RETI
Sum of overhead
J
Interrupt of capture/compare registers CCR1 to CCR4:
Cycles from interrupt request to 1st instruction of the interrupt handler:
Decision which source caused the interrupt: ADD &TAIV,PC
Addressed jump instruction:
JMP TIMMODx
Return from Interrupt instruction
RETI
Sum of overhead
J
6 cycles
5 cycles
11 cycles
6 cycles
3 cycles
2 cycles
5 cycles
16 cycles
Interrupt of the timer register TIMOV:
This interrupt needs the same number of cycles as the interrupt of
the capture/compare registers, but without the JMP TIMMODx instruction. This results in 14 cycles overhead.
6-140
The Timer_A
6.3.9.2
Update of the Capture/Compare Registers
If the capture/compare registers are updated asynchronously with the periodic
timing of the Timer_A, the output pulses may become too long or may be missing. Therefore, a synchronous update should be used, which means the PWM
value is written into a buffer, read out from this buffer at the correct time, and
then written into the capture/compare register. Three possibilities exist for the
synchronous update:
1) Frequent update by the appropriate Interrupt Handler
2) Infrequent update by the appropriate Interrupt Handler
3) Update by the interrupt handler of capture/compare block 0
The three possibilities are described in the following paragraphs. To find the
appropriate solution for a given timing problem, the following decision path
may be used:
- Is an individual interrupt task necessary for one ore more than one of the
capture/compare blocks? If yes, use solution 1, otherwise continue.
- Is a very fast update of the capture/compare registers necessary? If yes,
use solution 1, otherwise solution 2.
Frequent Update by the Appropriate Interrupt Handler
The interrupt handler of capture/compare block x updates the capture/
compare register CCRx with the repetition rate defined by the period register
(CCR0). This method is necessary if an additional task is to be executed by
the interrupt handler — medium preparation effort in the background, fast C/C
register change.
This method is used with Generation of Asymmetric Pulse Width Modulation
and RF Timing Generation. The following software examples refer to the first
application.
If the range for the PWM output values is limited from 1 cycle to (period–1)
cycles, then the following simple update sequence may be used:
; R6 contains new PWM info for CCR2. Range: 1 to (period–1).
;
MOV.B
R6,TA2PWM
; Actualize PWM buffer
If the PWM output values 0% or 100% are actually used (CCRx = 0 resp. CCRx
≥ period), then a special treatment is necessary due to the not-generated interrupt request of the capture/compare block x under these circumstances. The
On-Chip Peripherals
6-141
The Timer_A
new CCRx value is then written immediately. To determine these special
cases, the following update sequence may be used:
; R6 contains new PWM info for CCR2. Range: 0 to full period.
; Check if an immediate update is necessary:
; This is the case for CCR2 = 0 .or. CCR2 >= period
; Software is written for a constant Period Register CCR0
;
CMP
#PERIOD,&CCR2
; CCR2 actually >= period?
JHS
L$21
; Yes, update CCR2 immediately
TST
&CCR2
; No, CCR2 = 0?
JNZ
L$22
; CCR2 > 0: normal procedure
L$21
MOV
R6,&CCR2
; No interrupt: immed. update
L$22
MOV.B
R6,TA2PWM
; Actualize TA2PWM buffer
...
; Continue
Infrequent Update by the Appropriate Interrupt Handler
The interrupt handler of capture/compare block x updates the capture/
compare register (CCRx) with a repetition rate given by the calculation speed
of the background program. If a new PWM value is calculated for a capture/
compare block, then an individual flag is set and the interrupt for this capture/
compare block is enabled. The first asynchronous interrupt is rejected and the
second one (synchronous) is used for the update of the capture/compare register x. An interrupt task is possible only with the update repetition rate. This
method is used if the PWM values for the update are not available at the same
time — minimum interrupt overhead, individual C/C register change.
This method is used with Digital–to–Analog Conversion and TRIAC Control.
The following software examples refer to the first application.
If the range for the PWM output values is limited from 1 cycle to (period–1)
cycles, then the following simple update sequence may be used:
; R6 contains new PWM info for CCR2. Range: 1 to (period–1).
;
MOV
R6,DAC0OV
; Actualize DAC0 pulse length
BIS.B
#1,FLAG
; Set update flag for DAC0
BIS
#CCIE,&CCTL2
; Enable interrupt for DAC0
....
6-142
; Continue in background
The Timer_A
If the output values 0% or 100% are actually used (CCRx = 0 resp. CCRx ≥.
period), then a special treatment is necessary. The interrupt of the capture/
compare block x is not generated in these cases. To determine these special
cases, the following update sequence may be used:
; R6 contains the new PWM info for CCR2. Range: 0 to period.
; The interrupt is enabled individually for the update.
; A check is made if a special treatment is necessary:
; CCR2 = 0 .or. CCR2 >= period
; Software is written for a variable Period Register CCR0
;
L$21
L$22
L$23
MOV
R6,DAC0OV
; Actualize DAC0 pulse length
CMP
&CCR2,&CCR0
; CCR2 >= period actually?
JLO
L$21
; Yes, update CCR2 immediat.
TST
&CCR2
; No, is CCR2 = 0 actually?
JNZ
L$22
; No, proceed normally
MOV
R6,&CCR2
; Update CCR2 immediately
JMP
L$23
; Update made, no interrupt
BIS.B
#1,FLAG
; Set update flag for DAC0
BIS
#CCIE,&CCTL2
; Enable interrupt for DAC0
....
; Continue in background
For a constant period register (CCR0), the sequence is:
; Software is written for a constant period register CCR0
;
MOV
R6,DAC0OV
; Actualize DAC0 pulse length
CMP
#PERIOD,&CCR2
; CCR2 >= period actually?
JHS
L$21
; Yes, update CCR2 immediat.
TST
&CCR2
; No, is CCR2 = 0 actually?
....
; Same as above;
On-Chip Peripherals
6-143
The Timer_A
Update by the Interrupt Handler of Capture/Compare Block 0
The interrupt handler of capture/compare block 0 updates the capture/
compare registers (CCRx) with the repetition rate given by the period register
(CCR0). No additional tasks are possible for the other capture/compare blocks
— their interrupts are disabled. The output units control the TAx outputs without software overhead — minimum interrupt overhead, fastest C/C register
change. If an update is made from relatively large CCRx values to small ones
(approximately interrupt latency time), then 100% pulses may occur. Therefore, this method is only recommended for small changes of the PWM value.
This method can be used only if:
- A very fast update is necessary
- Only a minimum overhead can be tolerated (no additional handler is need-
ed, the CCR0 handler is only slightly longer due to this operation)
- Erroneous output pulses with 100% length can be tolerated
An example for this update method is given in section Capturing with the Up
Mode for capture/compare block 4.
These three possibilities may be mixed if it is advantageous. The examples of
this section apply the same solution for all capture/compare blocks.
Table 6–20 shows the overhead calculation and the percentage of the update
overhead for the three different update methods. The calculation results are
based on:
Where:
fMCLK
fupdate
fper
n
Frequency of the DCO (MCLK)
Update frequency for the capture/compare registers
Timer_A repetition rate (defined by the period register CCR0)
Number of C/C blocks used for the PWM generation
4.0 MHz
1.0kHz
19.2 kHz
3
Table 6–20. Interrupt Overhead for the three different Update Methods
UPDATE METHOD
Frequent Update with appropriate Handler
Infrequent Update with appropriate Handler
Update by Capture/Compare Block 0
OVERHEAD FORMULA (CPU CYCLES)
OVERHEAD PERCENTAGE
n × fper × 22
31.7%
n × fupdate × 44
3.3%
n × fper × 6
8.6%
Note:
No interrupts are generated — and therefore no interrupt overhead — for
capture/compare registers containing 0 or a value greater than or equal to
the period register (CCR0).
6-144
The Timer_A
6.3.9.3
Generation of Asymmetric Pulse Width Modulation (PWM)
The medium output voltage VPWM at the pin TAx resp. the necessary register
content nccrx for a given voltage VPWM is:
VPWM = Vcc ×
nCCRx
tpw
= Vcc ×
→ nCCRx
nCCR0 + 1
tper
Where:
VPWM
VCC
nCCR0
nCCRx
tpw
tper
=
VPWM
× (nCCR0 + 1)
Vcc
Medium output voltage at the TAx pin
Supply voltage of the system
Content of the period register CCR0
Content of the capture/compare register CCRx
Time generated by the capture/compare register
Period generated by the period register CCR0
[V]
[V]
[s]
[s]
Table 6–21 shows the necessary content of a capture/compare register CCRx
to get some defined unsigned output values for VPWM:
Table 6–21. Output Voltages for unsigned PWM
OUTPUT VOLTAGE (VPWM)
CONTENT OF CCRx nCCRx
0V
0
0.25 VCC
(nCCR0 + 1) 0.25
(nCCR0 + 1) 0.5
0.5 VCC
0.75 VCC
(nCCR0 + 1) 0.75
(nCCR0 + 1)
VCC
If the output voltage is seen as a signed voltage — like for 3-phase digital motor
control — then the voltage 0.5 × VCC is seen as the 0 point. The signed output
voltage VPWM gets:
(n
VPWM = Vcc )
nCCRx
– 0.5
CCR0 + 1
! nCCRx =
( Vcc + 0.5)(n
VPWM
CCR0
+ 1)
Table 6–22 shows the contents of a capture/compare register (CCRx) required
to get some defined values for a signed output voltage VPWM:
On-Chip Peripherals
6-145
The Timer_A
Table 6–22. Output Voltages for Signed PWM
OUTPUT VOLTAGE (VPWM)
CONTENT OF CCRx nCCRx
COMMENT
–0.5
VCC
0
–0.25
VCC
(nCCR0 + 1)
0.25
(nCCR0 + 1)
0.5
Half negative output voltage
(nCCR0 + 1)
0.75
nCCR0 + 1
Half positive output voltage
0V
0.25
VCC
0.5
VCC
Most negative output voltage
0 voltage
Most positive output voltage
Example 6–42. Generation of Two PWM Output Signals
The software example shows the generation of two PWM output signals at the
output terminals TA1 and TA2:
- Output Pin TA1 — a positive PWM signal. The length of the active high
part is defined in the RAM location TA1PWM (TCLK cycles).
- Output Pin TA2 — a negative PWM signal. The length of the active low
part is defined in the RAM location TA2PWM (TCLK cycles).
Additional tasks need to be executed by the interrupt handlers of the capture/
compare blocks 1 and 2, therefore an individual handler is used for both of
them.
The system clock frequency in use is 4 MHz (exactly fMCLK = 122 × 32768 =
3.9977 MHz), and the pulse repetition frequency is 19.2 kHz to allow the use
of this frequency for other timings as well (a software UART with 4800 baud
= 19.2 kHz/4, for example). For this application, bytes are sufficient for
TA1PWM and TA2PWM because the maximum possible value of its content
is 209. (4.0 MHz/19200 = 208.33).
The output unit 0 outputs 9600 Hz without any overhead. This signal may be
used for peripherals or for synchronization — the signal is always present,
even if the signals at TA1 and TA2 disappear due to an output signal with 0%
or 100% pulse width.
The example uses the Frequent Update by the Appropriate Interrupt Handler.
See Section 6.3.9.2 for details.
6-146
The Timer_A
Timer Register Content
0FFFFh
CCR0
CCR1
CCR2
0h
tper
CCR1:
Output Mode 7: PWM Reset/Set
TA1 Output
tpw1
CCR2:
Output Mode 3: PWM Set/Reset
TA2 Output
tpw2
CCR0:
Output Mode 4: PWM Toggle
TA0 Output
EQU2
EQU0
(TIMOV)
EQU1
EQU2
EQU0
(TIMOV)
EQU1
EQU2
EQU0
(TIMOV)
Interrupts Generated
Figure 6–37. Three Different Asymmetric PWM-Timings Generated With the Up Mode
; Software example:
; TA0: symmetric output signal
9.6kHz
; TA1: positive PWM signal
19.2kHz. Length in TA1PWM
; TA2: negative PWM signal
19.2kHz. Length in TA2PWM
;
; Hardware definitions
;
FLLMPY
.equ
122
; FLL multiplier for 3.9977MHz
fper
.equ
19200
; 19.2kHz repetition rate
TCLK
.equ
FLLMPY*32768
; TCLK: FLLMPY x fcrystal
PERIOD
.equ
((2*TCLK/fper)+1)/2 ; Period of output signals
STACK
.equ
600h
; Stack initialization address
;
; RAM definitions
;
TA1PWM
.equ
202h
; Pulse length Block 1 (0..209)
TA2PWM
.equ
203h
; Pulse length Block 2 (0..209)
On-Chip Peripherals
6-147
The Timer_A
TIMACYC0 .equ
204h
; Low cycle counter (bits 15..0)
TIMACYC1 .equ
206h
; High cycle counter (31..16)
TIMACNT
208h
; Counts # of periods
.equ
;
.text
; Software start address
;
INIT
MOV
#STACK,SP
; Initialize Stack Pointer
CALL
#INITSR
; Init. FLL and RAM
;
; Initialize the Timer_A: MCLK, Up Mode, INTRPTs on
;
MOV
#ISMCLK+CLR,&TACTL ; Define Timer_A
MOV
#PERIOD–1,&CCR0
; Period to Period Register
MOV
#0,&CCR1
; TA1: pulse width = 0
MOV
#0,&CCR2
; TA2: pulse width = 0
MOV
#OMT+CCIE,&CCTL0
; TA0: Toggle Mode
MOV
#OMRS+CCIE,&CCTL1 ; TA1: Reset/Set Mode
MOV
#OMSR+CCIE,&CCTL2 ; TA2: Set/Reset Mode
MOV.B
#TA2+TA1+TA0,&P3SEL ; Define Timer_A I/Os
MOV.B
#CBMCLK+CBE,&CBCTL ; Output MCLK at XBUF pin
CLR.B
TA1PWM
; Start value Block 1: 0V
CLR.B
TA2PWM
; Start value Block 2: 0V
CLR
TIMACYC0
; Clear low cycle counter
CLR
TIMACYC1
; Clear high cycle counter
CLR
TIMACNT
; Clear period counter
BIS
#MUP,&TACTL
; Start Timer in Up Mode
;
EINT
; Enable interrupts
MAINLOOP ...
; Continue in background
;
; Calculations resulted in new PWM values. The new results
; are stored in R6 (C/C Block 1) and R7.(C/C Block 2)
; Check if immediate update is necessary:
; CCRx = 0 .or. >= period.
;
CMP
6-148
#PERIOD,&CCR1
; CCR1 actually >= period?
The Timer_A
JHS
L$11
; Yes, update CCR1 immediately
TST
&CCR1
; No, is CCR1 = 0?
JNZ
L$12
; CCR1 > 0: normal procedure
L$11
MOV
R6,&CCR1
; No interrupt: immed. update
L$12
MOV.B
R6,TA1PWM
; Actualize TA1PWM buffer
CMP
#PERIOD,&CCR2
; CCR2 actually >= period?
JHS
L$21
; Yes, update CCR2 immediately
TST
&CCR2
; No, CCR2 = 0?
JNZ
L$22
; CCR2 > 0: normal procedure
L$21
MOV
R7,&CCR2
; No interrupt: immed. update
L$22
MOV.B
R7,TA2PWM
; Actualize TA2PWM buffer
;
...
; Continue in background
;
; Interrupt handler for CCR0: the Period Register. The cycle
; counters and the period counter are updated.
; A symmetric 9.6kHz signal is output by the Output Unit 0
; Return from interrupt via the handler of C/C Blocks 1 to 4.
;
TIMMOD0
ADD
#PERIOD,TIMACYC0 ; Add (fixed) period to
ADC
TIMACYC1
; cycle counters
INC
TIMACNT
; Period counter +1
...
; Task0 (if any)
; Fall through to TIM_HND
;
; Interrupt handlers for Capture/Compare Blocks 1 to 4.
; The actual interrupt flag CCIFGx is reset by the
; reading of the Timer Vector Register TAIV
;
TIM_HND
ADD
&TAIV,PC
RETI
; Add Jump table offset
; Vector 0: No interrupt pending
JMP
TIMMOD1
; Vector 2: Block 1
JMP
TIMMOD2
; Vector 4: Block 2
JMP
TIMMOD3
; Vector 6: Block 3 (not shown)
JMP
TIMMOD4
; Vector 8: Block 4 (not shown)
RETI
; Vector 10: TIMOV not used
On-Chip Peripherals
6-149
The Timer_A
;
; Capture/Compare Block 1 outputs a positive PWM signal at TA1
; The pulse width is defined in TA1PWM (0..PERIOD)
;
TIMMOD1
MOV.B
TA1PWM,&CCR1
; Pulse width to CCR1
EINT
; Allow nested interrupts
...
; Task1 starts here
RETI
; Back to main program
;
; Capture/Compare Block 2 outputs a negative PWM signal at TA2
; The pulse width is defined in TA2PWM (0..PERIOD)
;
TIMMOD2
MOV.B
TA2PWM,&CCR2
; Pulse width to CCR2
EINT
; Allow nested interrupts
...
; Task2 starts here
RETI
; Back to main program
;
; The tasks for the C/C Blocks 3 and 4 are not shown
;
TIMMOD3
...
; Handler for C/C Block 3
RETI
;
TIMMOD4
...
; Handler for C/C Block 4
RETI
;
.sect
”TIMVEC”,0FFF0h
; Timer_A Interrupt Vectors
.word
TIM_HND
; C/C Blocks 1 to 4
.word
TIMMOD0
; Capture/Compare Block 0
.sect
”INITVEC”,0FFFEh
; Reset Vector
.word
INIT
The example results in a nominal CPU loading uCPU (ranging from 0 to 1) by
the Timer_A activities:
uCPU =
Where:
fMCLK
nintrpt
frep
6-150
1
fMCLK
Σ (nintrpt
f rep )
Frequency of the system clock (DCO)
Number of cycles executed by the interrupt handler
Repetition rate of the interrupt handler
[Hz]
[Hz]
The Timer_A
Note:
The formula and the definitions given above are also valid for all subsequent
software examples. They are therefore not repeated.
CCR0 — repetition rate 19.2kHz
CCR1 — repetition rate 19.2kHz
CCR2 — repetition rate 19.2kHz
13 cycles for the task, 14 cycles overhead
6 cycles for the update, 17 cycles overhead
6 cycles for the update, 17 cycles overhead
uCPU =
27 cycles
23 cycles
23 cycles
19200 (27 + 23 + 23)
= 0.35
3.9977 10 6
This result shows a CPU loading of 35% due to the Timer_A (the tasks of the
capture/compare blocks 1 and 2 are not included).
6.3.9.4
Digital-to-Analog Conversion (DC Generation)
With the Timer_A running in the up mode, a maximum of four digital–to–analog
converters (DACs) can be created. With appropriate external filters, dc output
voltages are available.
The Figure 6–38 shows simple hardware solutions for cleaning up the output
dc voltage. The ripple shown on the dc output voltages is exaggerated for explanation purposes.
TDAC1
TA2
TA2 PWM Output
TA3 PWM Output
TA3 PWM Output
TA3
1/fCCR0
TDAC1 × fCCR0 × VCC
DAC1 Output Voltage
DAC1 Output Voltage
0V
TA4 PWM Output
TDAC2
MSP430
TA4 PWM Output
+
VCC
VSS
5V
0V
1/fCCR0
TDAC2 × fCCR0 × VCC
_
TA4
0V
DAC2 Output Voltage
0.5 VCC
DAC2 Output Voltage
Figure 6–38. Digital-to-Analog Conversion
On-Chip Peripherals
6-151
The Timer_A
Example 6–43. Digital-to-Analog Conversion
This software example creates three DACs that are updated at individual times
and relatively infrequently compared to the repetition rate defined by the period register (CCR0):
- DAC0 — output TA2, positive output signal, output value stored in
DAC0OV.
- DAC1 — output TA3, positive output signal, output value stored in
DAC1OV.
- DAC2 — output TA4, negative output signal, output value stored in
DAC2OV.
The higher the selected output frequency at the TAx outputs, the better the
suppression of the ac part of the output signal is.
The interrupt is used only after a new PWM value is calculated and needs to
be transferred to the capture/compare register. The update rate is approximately 500 Hz.
The repetition frequency for all three DAC outputs is 3.072 kHz, the system
clock frequency selected is 3.1457 MHz. This results in 1024 different steps
(10 bits resolution) for the DAC output voltages.
This example uses the Infrequent Update by the Appropriate Interrupt Handler. See Section 6.3.9.2 for details. The software is written for a variable period register.
; Software example: three independent DACs at TA2, TA3 and TA4
; Hardware definitions
;
FLLMPY
.equ
96
; FLL multiplier for 3.1457MHz
fper
.equ
3072
; 3.072kHz repetition rate
TCLK
.equ
FLLMPY*32768
; TCLK: FLLMPY x fcrystal
PERIOD
.equ
((2*TCLK/fper)+1)/2 ; Period of output signal
STACK
.equ
600h
; Stack initialization address
;
; RAM definitions
;
DAC0OV
.equ
202h
; Output value DAC0 (10 bits)
DAC1OV
.equ
204h
; Output value DAC1 (10 bits)
6-152
The Timer_A
DAC2OV
.equ
206h
; Output value DAC2 (10 bits)
TIMACYC0 .equ
208h
; Cycle counter low (bits 15..0)
TIMACYC1 .equ
20Ah
; Cycle counter high (bits 31..16)
TIMACNT
.equ
20Ch
; Period counter
FLAG
.equ
20Eh
; Flag register for DACs
;
.text
; Software start address
;
; Initialize the Timer_A: MCLK, Up Mode, CCR0 INTRPT enabled
; Prepare Timer_A Output Units, MCLK = 3.1457MHz
;
INIT
MOV
#STACK,SP
; Initialize Stack Pointer SP
CALL
#INITSR
; Init. FLL and RAM
MOV
#ISMCLK+CLR,&TACTL ; Define Timer_A
MOV
#OMOO+CCIE,&CCTL0 ; Enable INTRPT Per. Reg.
MOV
#OMRS,&CCTL2
; DAC0: Reset/Set
MOV
#OMRS,&CCTL3
; DAC1: Reset/Set
MOV
#OMSR,&CCTL4
; DAC2: Set/Reset
MOV
#PERIOD–1,&CCR0
; Load Period Register
CLR
&CCR2
; DAC0: 0% output
CLR
&CCR3
; DAC1
CLR
&CCR4
; DAC2
MOV.B
#TA4+TA3+TA2,&P3SEL ; Output Unit I/Os
CLR
TIMACNT
; Clear period counter
CLR
TIMACYC0
; Clear cycle counters
CLR
TIMACYC1
CLR.B
FLAG
; Disable update of DACs
BIS
#MUP,&TACTL
; Start Timer_A with Up Mode
EINT
MAINLOOP ...
; Enable interrupts
; Continue in background
;
; Calculations for the new DAC values start.
; The new results in R6 are written to DACxOV after completion
; The interrupt is enabled individually for the update. A check
; is made if special treatment is necessary:
; CCRx = 0 .or. >= period
On-Chip Peripherals
6-153
The Timer_A
; Software is written for a variable period register CCR0
;
...
L$21
L$22
L$23
; Calculate DAC0 value to R6
MOV
R6,DAC0OV
; Actualize DAC0 pulse length
CMP
&CCR2,&CCR0
; CCR2 >= period actually?
JLO
L$21
; Yes, update CCR2 immediat.
TST
&CCR2
; No, is CCR2 = 0 actually?
JNZ
L$22
; No, proceed normally
MOV
R6,&CCR2
; Update CCR2 immediately
JMP
L$23
; Update made, calc. CCR3 PWM
BIS.B
#1,FLAG
; Set update flag for DAC0
BIS
#CCIE,&CCTL2
; Enable interrupt for DAC0
.equ
$
;
...
L$31
L$32
L$33
; Calculate DAC1 value to R6
MOV
R6,DAC1OV
; Actualize DAC1 pulse length
CMP
&CCR3,&CCR0
; See comment for DAC0
JLO
L$31
TST
&CCR3
JNZ
L$32
MOV
R6,&CCR3
JMP
L$33
BIS.B
#2,FLAG
BIS
#CCIE,&CCTL3
.equ
$
;
...
L$41
L$42
6-154
; Calculate DAC2 value to R6
MOV
R6,DAC2OV
; Actualize DAC2 pulse length
CMP
&CCR4,&CCR0
; See comment for DAC0
JLO
L$41
TST
&CCR4
JNZ
L$42
MOV
R6,&CCR4
JMP
L$43
BIS.B
#4,FLAG
BIS
#CCIE,&CCTL4
The Timer_A
L$43
....
; Continue in background
;
; Interrupt handler of the Period Register CCR0.
; A way is shown how to update the cycle counters if the
; timer period is variable during the program flow
;
TIMMOD0
SETC
; Period = (CCR0)+1
ADDC
&CCR0,TIMACYC0
; Add actual period to
ADC
TIMACYC1
; cycle counters TIMACYCx
INC
TIMACNT
; Period counter +1
EINT
; Allow nested interrupts
...
; Task0 (if any)
RETI
;
; Interrupt handler for Capture/Compare Registers 1 to 4
;
TIM_HND
ADD
&TAIV,PC
RETI
; Serve highest priority requ.
; No interrupt pending
JMP
TIMMOD1
; CCR1 request
JMP
TIMMOD2
; DAC0 request
JMP
TIMMOD3
; DAC1
JMP
TIMMOD4
; DAC2
RETI
; Timer overflow disabled
;
; Capture/Compare Block 1 interrupt handler. May be used for
; comparison or capturing. Not implemented here.
;
TIMMOD1
...
; Handler start
RETI
;
; DACx updates. Interrupt is used only if a new result is
; calculated. Update frequency is 0.5kHz. The 1st interrupt
; is rejected, due to the always set interrupt flag CCIFGx.
; The 2nd synchronous interrupt updates the C/C Block.
;
TIMMOD2
BIT.B
#1,FLAG
; Update possible? (flag = 0)
On-Chip Peripherals
6-155
The Timer_A
JNZ
T20
; No, asynchronous interrupt
MOV
DAC0OV,&CCR2
; Yes, update DAC0
BIC
#CCIE,&CCTL2
; Disable interrupt
RETI
T20
BIC.B
#1,FLAG
; Indicate update readiness
RETI
; Return from interrupt
;
; DAC1 update. Same as above for DAC0
;
TIMMOD3
BIT.B
#2,FLAG
; Update possible? (flag = 0)
JNZ
T30
; No, asynchronous interrupt
MOV
DAC1OV,&CCR3
; Yes, update DAC1
BIC
#CCIE,&CCTL3
; Disable interrupt
RETI
T30
BIC.B
#2,FLAG
; Indicate readiness
RETI
; Return from interrupt
;
; DAC2 update. Same as above for DAC0
;
TIMMOD4
BIT.B
#4,FLAG
; Update possible? (flag = 0)
JNZ
T40
; No, asynchronous interrupt
MOV
DAC2OV,&CCR4
; Yes, update DAC2
BIC
#CCIE,&CCTL4
; Disable interrupt
RETI
T40
BIC.B
#4,FLAG
; Indicate readiness
RETI
; Return from interrupt
.sect
”TIMVEC”,0FFF0h
; Timer_A Interrupt Vectors
.word
TIM_HND
; Vector for C/C Block 1..4
.word
TIMMOD0
; Vector for C/C Block 0
.sect
”INITVEC”,0FFFEh
; Reset Vector
.word
INIT
This example results in a maximum CPU loading uCPU (ranging from 0 to 1)
by the Timer_A activities (maximum update frequencies on all three DAC
channels):
CCR0 — repetition rate 3.072 kHz
CCR2 — repetition rate 0.5 kHz
CCR3 — repetition rate 0.5 kHz
CCR4 — repetition rate 0.5 kHz
6-156
16 cycles for the task, 11 cycles overhead
27 cycles for the update, 32 cycles overhead
27 cycles for the update, 32 cycles overhead
27 cycles for the update, 32 cycles overhead
27 cycles
59 cycles
59 cycles
59 cycles
The Timer_A
uCPU =
3072 27 + 500 (59 + 59 + 59 )
= 0.055
3.1457 10 6
Note that an update for the capture/compare blocks 2 to 4 needs two interrupt
services. The above result means a worst case CPU loading of approximate
5.5% due to the three DACs.
If all three tasks are updated with a 100 Hz update rate, then the CPU is loaded
with only 3.2%.
6.3.9.5
TRIAC Control
TRIAC control for electric motors (DMC) or other loads is also possible with
the up mode of the Timer_A. But the time frame, defined by the period register,
does not allow the same resolution as with the continuous mode. The control
software now counts the number of periods and fires the TRIAC after the
reaching of the programmed number.
The medium resolution pmed is:
pmed =
Where:
fMAINS
tper
1
2 fMAINS tper
AC Line frequency
Period of the Timer_A, defined by CCR0
[Hz]
[s]
The integrated energy E of a sine half wave dependent on the time t is described by the equation:
E 1 – cos ω t = 1 – cos 2 π f t
t = 0 ...
1
2f
Due to this nonlinear energy increase, the worst case resolution pmin — near
the angle π/4 (90_) — is reduced by a factor of π/2 (1.57) compared to the medium resolution pmed:
pmin =
1
2 fMAINS tper π / 2
The TRIAC control software contains fewer security features than the version
shown for the continuous mode:
- The zero crossing part (P0.0 handler) immediately switches the gate sig-
nal off by setting terminal TA0 to high. This prevents the firing for the next
half wave.
On-Chip Peripherals
6-157
The Timer_A
This means, the background software has to check to see if the calculated time
for the firing of the TRIAC — the number of timer periods after the zero crossing
of the ac line voltage (FIRANGL) — is not too near to the next zero crossing.
No capture/compare register is needed for the TRIAC control — only the period register with its interrupt and output unit 0 is used. This frees the remaining
capture/compare blocks for other tasks.
Figure 6–39 shows the hardware for the TRIAC control of this example. After
power up, the TA0 terminal is switched to input mode — the base resistor of
the PNP transistor switches the gate of the TRIAC off and prevents a run of
the motor. The necessary hardware debounce for the zero crossing signal at
P0.0 is made with the internal capacity, Cz, of the zener diode.
230 V AC
Zero Crossing
5V
5V
M
VCC
>1 M
MSP430
P0.0
TA1 TA2 VSS
Cz
3.5 V
5V
TA0
Comparator
_
P0.7
+
Overcurrent
Detection
0V
PWM Output 2
PWM Output 1
Figure 6–39. TRIAC Control with Timer_A
Figure 6–40 illustrates the software example given below. The period of CCR0
is not shown in to scale — 160 steps make one half wave of the 50 Hz line.
6-158
The Timer_A
P0.0 Input
Zero Crossing
tdelay
tdelay
tdelay
tper
Timer Register TAR
TA0 Output to
TRIAC Gate
OP × tper
Motor
Voltage
Voltage
Conduction
Angle
AC
Figure 6–40. Signals for the TRIAC Gate Control With Up Mode
Example 6–44. Static TRIAC Control
A static TRIAC control software example is shown. The calculated number of
periods until the TRIAC gate is fired after the zero crossing of the ac line voltage, is contained in the RAM word FIRANGL.
The medium resolution pmed is 160 steps per 50 Hz line half wave
(16 kHz/100 Hz = 160). The minimum resolution, pmin, is 102 steps (160 × 2/π
= 102), which means approx. 1% resolution. See the equations above.
At the TA1 and TA2 terminals, positive PWM signals are output. The period is
defined by the Period register CCR0, the pulse length (TCLK cycles) is contained in the RAM bytes TA1PWM and TA2PWM. The update is made with
1 kHz.
The example uses the Infrequent Update by the Appropriate Interrupt Handler.
See Section 6.3.9.2 for details.
; Definitions for the TRIAC control software
;
FLLMPY
.equ
64
; FLL multiplier for 2.096MHz
fper
.equ
16000
; 16.000kHz repetition rate
TCLK
.equ
FLLMPY*32768
; TCLK (Timer Clock) [Hz]
PERIOD
.equ
((2*TCLK/fper)+1)/2 ; Period in Timer clocks
OP
.equ
2
; TRIAC gate pulse length (per.)
On-Chip Peripherals
6-159
The Timer_A
;
; RAM definitions
;
TIMACYC0 .equ
202h
; Timer Register Extensions:
TIMACYC1 .equ
204h
; Cycle counters
TIMACNT
.equ
206h
; Counter of periods
FIRANGL
.equ
208h
; Half wave – conduction angle
FIRTIM
.equ
20Ah
; Fire time rel. to TIMACNT
TA1PWM
.equ
20Ch
; PWM cycle count for Block 1
TA2PWM
.equ
20Dh
; PWM cycle count for Block 2
STTRIAC
.equ
20Eh
; Control byte (0 = off) Status
FLAG
.equ
20Fh
; 1: update for PWM necessary
STACK
.equ
600h
; Stack initialization address
.text
; Start of ROM code
;
; Initialize the Timer_A: MCLK, Up Mode, INTRPT enabled
; Prepare Timer_A Output Units
;
INIT
6-160
MOV
#STACK,SP
; Initialize Stack Pointer SP
CALL
#INITSR
; Init. FLL and RAM
MOV
#ISMCLK+CLR,&TACTL ; Init. Timer
MOV
#PERIOD–1,&CCR0
MOV
#OMOO+CCIE+OUT,&CCTL0 ; Set TA0 high
MOV
#OMRS,&CCTL1
; TA1: pos. PWM pulses
MOV
#OMRS,&CCTL2
; TA2: pos. PWM pulses
BIS.B
#TA2+TA1+TA0,&P3SEL ; Define timer outputs
BIS.B
#P0IE0,&IE1
; Enable P0.0 interrupt (mains)
CLR
TIMACYC0
; Clear low cycle counter
CLR
TIMACYC1
; Clear high cycle counter
CLR
TIMACNT
; Clear period counter
CLR.B
STTRIAC
; TRIAC off status (0)
CLR.B
FLAG
; No update
CLR.B
TA1PWM
; TA1: no output (0% duty cycle)
CLR.B
TA2PWM
; TA2: no output (0% duty cycle)
BIS
#MUP,&TACTL
; Start Timer_A in Up Mode
MOV.B
#CBMCLK+CBE,&CBCTL
; Period to CCR0
; MCLK at XBUF pin
The Timer_A
EINT
MAINLOOP
; Enable interrupts
...
; Continue in mainloop
;
; Some TRIAC control examples:
; Start electric motor: checked result (Timer_A periods) in R5
; The result is the time difference from the zero crossing
; of the mains voltage (P0.0) to the first gate pulse
; (measured in Timer_A periods)
;
MOV
R5,FIRANGL
MOV.B
#2,STTRIAC
...
; Delay (periods) to FIRANGL
; Activate TRIAC control
; Continue in background
;
; The motor is running. A new calculation result is available
; in R5. It will be used with the next mains half wave
;
MOV
R5,FIRANGL
...
; Delay (periods) to FIRANGL
; Continue in background
;
; Stop motor: switch off TRIAC control
;
CLR.B
STTRIAC
; Disable TRIAC control
BIC
#OMRS,&CCTL0
; TRIAC gate off
BIS
#CCIE+OUT,CCTL0
; TA0 high, Output only Mode
...
; Continue with background
;
; Calculations for the new PWM values start.
; The new results in R6 are written to TAxPWM after completion
; The interrupt is enabled individually for the update. A check
; is made if special treatment is necessary:
; Actual CCRx = 0 .or. >= period
; Software is written for a constant period register CCR0
;
...
; Calculate TA1PWM value to R6
MOV.B
R6,TA1PWM
; Actualize pulse length
CMP
#PERIOD,&CCR1
; CCR1 >= period actually?
On-Chip Peripherals
6-161
The Timer_A
L$11
L$12
L$13
JHS
L$11
; Yes, update CCR1 immediat.
TST
&CCR1
; No, is CCR1 = 0 actually?
JNZ
L$12
; No, proceed normally
MOV
R6,&CCR1
; Update CCR1 immediately
JMP
L$13
; Update made, calc. next PWM
BIS.B
#1,FLAG
; Set update flag for TA1PWM
BIS
#CCIE,&CCTL1
; Enable interrupt
.equ
$
;
...
L$21
L$22
L$23
; Calculate TA2PWM value to R6
MOV.B
R6,TA2PWM
; Actualize pulse length
CMP
#PERIOD,&CCR2
; CCR2 >= period actually?
JHS
L$21
; Yes, update CCR2 immediat.
TST
&CCR2
; No, is CCR2 = 0 actually?
JNZ
L$22
; No, proceed normally
MOV
R6,&CCR2
; Update CCR2 immediately
JMP
L$23
; Update made, continue
BIS.B
#2,FLAG
; Set update flag for TA2PWM
BIS
#CCIE,&CCTL2
; Enable interrupt for DAC0
....
; Continue in background
;
;
; Interrupt handler for CCR0: the Period Register:
; – The cycle counters and the period counter are updated:
; – The TRIAC control task is executed
;
TIMMOD0
ADD
#PERIOD,TIMACYC0
; Add (fixed) period to
ADC
TIMACYC1
; Cycle counters
INC
TIMACNT
; Increment period counter
;
; Interrupt handler for the TRIAC control
;
EINT
6-162
; Allow nested interrupts
PUSH
R5
; Save help register R5
MOV.B
STTRIAC,R5
; Status of TRIAC control
MOV
STTAB(R5),PC
; Branch to status handler
The Timer_A
STTAB
.word
STATE0
; Status 0: No TRIAC activity
.word
STATE0
; Status 2: activation possible
.word
STATE4
; Status 4: wait for gate pulse
.word
STATE6
; Status 6: wait for gate off
;
; TRIAC status 4: gate is switched on for OP periods after the
; value in FIRTIM is reached
;
STATE4
CMP
FIRTIM,TIMACNT
; TRIAC gate time reached?
JNE
STATE0
; No
BIS
#OMR+CCIE,&CCTL0 ; Prepare for gate on pulse
ADD.B
#2,STTRIAC
; Next TRIAC status (6)
;
; TRIAC status 0: No activity. TRIAC is off always
;
STATE0
POP
R5
RETI
; Restore help register
; Return from interrupt
;
; TRIAC status 6: gate pulse is active. Check if it’s time
; to switch the gate off.
STATE6
MOV
FIRTIM,R5
ADD
#OP,R5
; Gate–on time (periods)
CMP
R5,TIMACNT
; On–time terminated?
JLO
STATE0
; No
BIC
#OMRS,&CCTL0
; Yes, prepare TRIAC Gate off
BIS
#OMSET+CCIE,&CCTL0;
MOV.B
#2,STTRIAC
; TRIAC status:
JMP
STATE0
; Wait for next zero crossing
;
; Interrupt handler for Capture/Compare Blocks 1 to 4
;
TIM_HND
ADD
&TAIV,PC
RETI
; Serve highest priority requ.
; No interrupt pending
JMP
TIMMOD1
; PWM 1 request
JMP
TIMMOD2
; PWM 2 request
RETI
; Not used
On-Chip Peripherals
6-163
The Timer_A
RETI
; Not used
RETI
; Timer overflow disabled
;
; C/C Block updates. Interrupt is used only if a new result is
; calculated. Update frequency is 1.0kHz. The 1st interrupt
; is rejected, due to the always set interrupt flag CCIFGx.
; The 2nd synchronous interrupt updates the C/C Register.
;
TIMMOD1
BIT.B
#1,FLAG
; Update possible? (flag = 0)
JNZ
T10
; No, asynchronous interrupt
MOV.B
TA1PWM,&CCR1
; Yes, update C/C Block 1
BIC
#CCIE,&CCTL1
; Disable interrupt
#1,FLAG
; Indicate: ready for update
RETI
T10
BIC.B
RETI
TIMMOD2
; Return from interrupt
BIT.B
#2,FLAG
; Update possible? (flag = 0)
JNZ
T20
; No, asynchronous interrupt
MOV.B
TA2PWM,&CCR2
; Yes, update C/C Block 2
BIC
#CCIE,&CCTL2
; Disable interrupt
RETI
T20
BIC.B
#2,FLAG
RETI
; Indicate: ready for update
; Return from interrupt
;
; P0.0 Handler: the mains voltage causes interrupt with each
; zero crossing. The TRIAC gate is switched off first, to
; avoid the ignition for the actual half wave.
; Hardware debounce is necessary for the mains signal!
;
P00_HNDLR BIC
BIS
#OMRS,&CCTL0
#CCIE+OUT,&CCTL0
EINT
XOR.B
; Switch off TRIAC gate
; Allow nested interrupts
#1,&P0IES
; Change interrupt edge of P0.0
;
; If STTRIAC is not 0 ( 0 = inactivity) then the next gate
; firing is prepared: STTRIAC is set to 4
;
6-164
The Timer_A
TST.B
STTRIAC
JZ
P00
; STTRIAC = 0: no activity
MOV.B
#4,STTRIAC
; STTRIAC > 0: prep. next firing
;
; The TRIAC firing time is calculated: TIMACNT + FIRANGL
;
P00
MOV
TIMACNT,FIRTIM
; Period counter
ADD
FIRANGL,FIRTIM
; TIMACNT + delay –> FIRTIM
.sect
”TIMVEC”,0FFF0h
; Timer_A Interrupt Vectors
.word
TIM_HND
; C/C Blocks 1..4 Vector
.word
TIMMOD0
; Vector for C/C Block 0
.sect
”P00VEC”,0FFFAh
; P0.0 Vector
.word
P00_HNDLR
.sect
”INITVEC”,0FFFEh
.word
INIT
RETI
;
; Reset Vector
The TRIAC control example results in a nominal CPU loading uCPU (ranging
from 0 to 1) for the active TRIAC control (STTRIAC = 4):
CCR0 — repetition rate 16 kHz
CCR1 — repetition rate 1 kHz
CCR2 — repetition rate 1 kHz
P0.0 — repetition rate 100 Hz
u
=
CPU
16.0 10 3
32cycles for the task, 11 cycles overhead
27 cycles for the update, 32 cycles overhead
27 cycles for the update, 32 cycles overhead
32 cycles for the task, 11 cycles overhead
43 + 1.0 10 3
2.096
(59 + 59 ) + 100 47
10 6
43 cycles
59 cycles
59 cycles
43 cycles
= 0.39
The above result means a CPU loading of approximate 39% due to the static
TRIAC control. The necessary tasks for the update of the period counter and
the cycle counters are included. The PWM activities alone load the CPU with
less than 6% using this method (fupdate = 1 kHz).
On-Chip Peripherals
6-165
The Timer_A
6.3.9.6
RF Timing Generation
The repetition rate used in the up mode must be a multiple of the data change
frequency. The three different modulation methods and its conversion subroutines were explained in depth in the section RF generation.
The RF modulation modes described earlier were:
- Amplitude Modulation — the RF oscillator is switched on for a logical 1
and switched off for a logical 0 (100% modulation).
- Biphase Code — the information is represented by a bit time consisting
of one half bit without modulation and one half bit with full modulation. A
logical 1 starts with 100% modulation, a logical 0 starts with no modulation.
- Biphase Space — a logical 1 (space) is represented by a constant signal
(100% or 0% modulation) during the complete bit time. A logical 0 (mark)
changes the signal in the middle of the bit time. The signal changes after
each transmitted bit. This means, the previous bit influences the current
bit.
Figure 6–41 shows the three different modulation modes for an input byte containing the value 96h.
0
1
1
0
1
0
0
1
Information 096h
Amplitude
Modulation
RF On
Biphase Code
RF Off
Biphase Space
Bit Length
Figure 6–41. RF Modulation Modes
6-166
Time
The Timer_A
The capture/compare block 0 is used with the software example due to two
facts:
- The fastest possible response. Decision making with the timer vector reg-
ister is not necessary for the capture/compare block 0 — it uses its own,
dedicated interrupt vector. The vector address is 0FFF2h.
- The capture/compare block 0 delivers the necessary timing anyway. The
use of the period register therefore frees the remaining capture/compare
registers for other tasks.
Example 6–45. RF Modulation Modes
The real time task common to all three modulation modes is given below. The
background software prepares a 128-bit block starting at address RF_BLK,
containing the information to be output in the desired coding format. This
128-bit buffer is output in real time with the same handler for all three modulation modes.
The selected half-bit repetition frequency is 19200 Hz, because 38400 Hz is
too high a PWM frequency (increased switching losses, too few resolution
steps).
The capture/compare blocks 1 to 3 are used for the PWM generation. The
table processing used allows (nearly) simultaneous update of all three capture/compare blocks. The method used is the fastest one for updating. The
number range for the PWM is from 1 to (period–1), therefore, the fast update
— without range checks — is possible.
The CPU registers R5 and R8 are reserved for the RF timing. R5 contains the
data to be output currently, R8 points to the next data word. They must not be
overwritten by other tasks.
The conversion subroutines for the biphase code and biphase space modulation are described in the section RF Generation.
The example uses the Frequent Update by the Appropriate Interrupt Handler.
See Section 6.3.9.2 for details.
; Hardware definitions
;
FLLMPY
.equ
122
; FLL multiplier for 3.998MHz
fRF
.equ
19200
; Half–bit rep. frequency
TCLK
.equ
FLLMPY*32768
; TCLK: FLLMPY x fcrystal
PERIOD
.equ
((2*TCLK/fRF)+1)/2 ; Bit length (TCLK cycles)
On-Chip Peripherals
6-167
The Timer_A
STACK
.equ
600h
; Stack initialization address
;
; RAM Definitions
;
RF_BLK
.equ
202h
; Converted data 128 bits
TIMACYC
.equ
212h
; Cycle counter Timer_A
TIMACNT
.equ
214h
; Period counter Timer_A
RFSTAT
.equ
216h
; Status of RF transmission
TA1PWM
.equ
217h
; Value for C/C Block 1
TA2PWM
.equ
218h
; Value for C/C Block 2
.equ
219h
; Value for C/C Block 3
TA3PWM
.text
; Software start address
;
INIT
MOV
#STACK,SP
; Initialize Stack Pointer
CALL
#INITSR
; Init. FLL and RAM
;
; Initialize the Timer_A: MCLK, Up Mode, INTRPT on for CCRx
;
MOV
#ISMCLK+CLR,&TACTL ; MCLK, TIMOV off
MOV
#OMOO+CCIE,&CCTL0 ; Reset TA0, INTRPT on
MOV
#OMSR+CCIE,&CCTL1 ; TA1: Set/Reset
MOV
#OMSR+CCIE,&CCTL2 ; TA2: Set/Reset
MOV
#OMSR+CCIE,&CCTL3 ; TA3: Set/Reset
MOV
#PERIOD–1,&CCR0
; 19.2kHz period
MOV.B
#1,&CCR1
; Minimum PWM length
MOV.B
#1,&CCR2
MOV.B
#1,&CCR3
MOV.B
#TA3+TA2+TA1+TA0,&P3SEL ; Define timer outputs
CLR
TIMACYC
; Clear cycle counter
CLR
TIMACNT
; Clear period counter
MOV.B
#1,TA1PWM
; Minimum PWM output
MOV.B
#1,TA2PWM
;
MOV.B
#1,TA3PWM
;
MOV.B
#CBMCLK,&CBCTL
; Output MCLK at XBUF pin
CLR.B
RFSTAT
; RF status = 0
;
6-168
The Timer_A
BIS
#MUP,&TACTL
EINT
; Start Timer in Up Mode
; Enable interrupts
MAINLOOP ...
; Continue in background
;
; The data to be transmitted by RF is converted into a
; 128–bit RAM block starting at address RF_BLK with the
; appropriate conversion routine. The subroutines described
; in Part III are used. See there for explanation.
; R5 and R8 are reserved for the RF transmission!
;
MOV.B
ADDRESS0,R6
; 1st data byte to R6
CALL
#BI_PHASE_xxx
; Convert it to 16 bits
MOV
R5,0(R8)
; Converted data to RF–Block
...
; Continue with converting
;
; Initialize transmission of the converted data (128–bit)
;
MOV
#RF_BLK,R8
; Start of 128–bit block
MOV
@R8+,R5
; 1st 16 bits for output to R5
MOV.B
#16+1,RFSTAT
; Bit count for 1st 16 bits
...
; Continue in background
;
; Test in background if 128 bits are output: RFSTAT = 0
;
TST.B
RFSTAT
; Output completed?
JZ
BPC_MADE
; Yes, RFSTAT = 0
...
; No, continue
;
; New values for the three PWM channels are read from a table
;
MOV
ANGLE,R15
MOV.B
TABLE+00(R15),TA1PWM ; Update PWM channels
MOV.B
TABLE+12(R15),TA2PWM ; out of a sine table
MOV.B
TABLE+24(R15),TA3PWM ;
...
; Actual angle for DMC
; Continue in background
;
On-Chip Peripherals
6-169
The Timer_A
; A second example is given for a 64 bit block:
; Initialize transmission of only 64 bits: the start address
; differs, the end address is again RF_BLK+16
;
MOV
#RF_BLK+8,R8
; Start of 64–bit block
MOV
@R8+,R5
; 1st 16 bits for output to R5
MOV.B
#16+1,RFSTAT
; Bit count for 1st 16 bits
...
; Continue in background
;
TABLE
.byte
1,15,29,43...PERIOD–1 ; PWM table
;
; Interrupt handler for Capture/Compare Block 0 (CCR0)
; Data in RF_BLK is output: LSB first.
; The Output Unit outputs the data bit prepared during the last
; period. The data bit for the next period is prepared now.
; Output is completed, when (last word +4) is addressed by R8.
;
TIMMOD0
ADD
#PERIOD,TIMACYC ; Add period to cycle counter
INC
TIMACNT
; Increment period counter
;
EINT
; Allow nested interrupts
TST.B
RFSTAT
; RF transmission underway?
JZ
TM03
; No, return from interrupt
DEC.B
RFSTAT
; Yes, bit count – 1
JNZ
TM01
; Not zero: continue
MOV
@R8+,R5
; Next 16 bits for output
CMP
#RF_BLK+18,R8
; End of buffer+2 reached?
JHS
TM04
; Yes, finish output (RFSTAT=0)
MOV.B
#16,RFSTAT
; Bit count for next word
;
TM01
TM04
RRC
R5
; Next data bit to carry
JC
TM02
; Bit is one
MOV
#OMR+CCIE,&CCTL0
; Bit is 0: prepare reset
RETI
;
TM02
6-170
MOV
#OMSET+CCIE,&CCTL0 ; Bit is 1: prepare set
The Timer_A
TM03
RETI
;
; Interrupt handlers for Capture/Compare Blocks 1 to 4.
; The actual interrupt flag CCIFGx is reset by the
; reading of the Timer Vector Register TAIV
;
TIM_HND
ADD
&TAIV,PC
RETI
; Add Jump table offset
; Vector 0: No interrupt pending
JMP
TIMMOD1
; Vector 2: Block 1
JMP
TIMMOD2
; Vector 4: Block 2
JMP
TIMMOD3
; Vector 6: Block 3
RETI
; Vector 8: Block 4 (not used)
RETI
; Vector 10: TIMOV not used
;
; Capture/Compare Block 1 outputs a positive PWM signal at TA1
; The pulse width is defined in TA1PWM (1..PERIOD–1)
;
TIMMOD1
MOV.B
TA1PWM,&CCR1
RETI
; Pulse width to CCR1
; Back to main program
;
; Capture/Compare Block 2 outputs a positive PWM signal at TA2
; The pulse width is defined in TA2PWM (1..PERIOD–1)
;
TIMMOD2
MOV.B
TA2PWM,&CCR2
RETI
; Pulse width to CCR2
; Back to main program
;
; Capture/Compare Block 3 outputs a positive PWM signal at TA3
; The pulse width is defined in TA3PWM (1..PERIOD–1)
;
TIMMOD3
MOV.B
TA3PWM,&CCR3
RETI
; Pulse width to CCR3
; Back to main program
.sect
”TIMVEC”,0FFF0h
; Timer_A Interrupt Vector
.word
TIM_HND
; Vector C/C Blocks 1 to 3
.word
TIMMOD0
; Vector for C/C Block 0
.sect
”INITVEC”,0FFFEh
; Reset Vector
.word
INIT
On-Chip Peripherals
6-171
The Timer_A
The RF timing generation example results in a nominal CPU loading uCPU
(ranging from 0 to 1) for the active transmit (RFSTAT > 0):
CCR0 — repetition rate 19.2 kHz
CCR1 — repetition rate 19.2 kHz
CCR2 — repetition rate 19.2 kHz
CCR3 — repetition rate 19.2 kHz
30 cycles for the task, 11 cycles overhead
6 cycles for the update, 16 cycles overhead
6 cycles for the update, 16 cycles overhead
6 cycles for the update, 16 cycles overhead
41 cycles
22 cycles
22 cycles
22 cycles
The above example results in a medium CPU loading uCPU (ranging from 0 to
1) by the Timer_A activities:
uCPU =
1
fMCLK
Σ (n
intrpt
f rep
)=
(41 + 22 + 22 + 22)
19.2 10 3
3.998 10 6
= 0.51
The result means that the MSP430 CPU is loaded 20% when outputting the
RF buffer with 19200 baud and an MCLK frequency of 4 MHz. The updates of
the cycle counters and the period counter are included. The update of the
PWM registers adds 31%, if used.
6.3.9.7
Software UART
With a carefully chosen timer period, a software UART can be implemented
relatively simply. The complete software, a status-controlled handler, will be
the topic of an external application report. This report will describe a full-duplex
UART controlled by the timing of Timer_A.
6.3.9.8
Comparison With the Up Mode
Comparison with the up mode is made the same way as described in the section Applications exceeding the 16-Bit Range of the Timer_A for the continuous mode. As in that case, the timings to be created exceed the period of the
timer register and external RAM extensions are therefore necessary.
6.3.9.9
Capturing With the Up Mode
If the periods of the internal interrupt timings or the time intervals to be captured
are longer than one period of the timer register, then a special method is necessary to take care of the longer time periods. The same is true if a half period
of a generated output frequency is longer than the period of the Timer_A.
This special method, with the use of extension registers for the capture/
compare registers, is necessary if:
t SIGNAL >
6-172
(nccr0 + 1)
f CLK
k
The Timer_A
Where:
tSIGNAL
fCLK
k
nCCR0
Time interval to be captured
Input frequency at the input divider input of Timer_A
Pre–divider constant of the input divider (1, 2, 4 or 8)
Content of period register CCR0
[s]
[Hz]
Figure 6–42 illustrates the hardware and RAM registers used with the capture
mode if the captured values are greater than one period of the Timer_A.
15
0
Period Register CCR0
Add Period (Software)
Reset if equal
15
Cycle Counter
0
Compare
15
TIMACYC0
(n × Period)
Carry to TIMACYC1
Timer Clock
Capture
15
0
CCR1
Software Add
15
0
Time Register TAR
0
Captured Value
RAM Store
Timer_A Hardware
16-Bit Captured Value
Figure 6–42. Capture Mode with the Up Mode (shown for CCR1)
Figure 6–43 illustrates five examples. The tasks are defined as follows:
- Capture/Compare Block 0 — outputs a symmetrical 9.6 kHz signal. The
edges contain the information for the period generated by the period register (CCR0). This signal is always available (the PWM signals of the capture/compare blocks disappear for pulse widths of 0% and 100%).
- Capture/Compare Block 1 — generates a positive PWM signal with the
period defined by the period register. The pulse length is stored in the RAM
word TA1PWM. A dedicated interrupt handler is used.
- Capture/Compare Block 2 — the length, ∆t2, of the high part of the input
signal at the CCI2A input terminal is measured and stored in the RAM word
PP2. The captured time of the leading edge is stored in the RAM word
TIM2. The max. repetition rate used is 2 kHz.
- Capture/Compare Block 3 — the event time of the leading edge of the
signal at the CCI3A input terminal is captured. The last captured value is
stored in the RAM word TIM3. The max. repetition rate used is 3 kHz.
- Capture/Compare Block 4 — generates a negative PWM signal with the
period defined by the period register. The pulse length is stored in the RAM
On-Chip Peripherals
6-173
The Timer_A
word TA4PWM. Update is made with the interrupt handler of capture/
compare block 0.
For the example, 3.801 MHz is used. The resolution is 224 steps due to the
repetition frequency of 16.969 kHz (3.801 MHz/16.969 kHz = 224).
Table 6–23. Short Description of the Capture and PWM Mix
C/C BLOCK
TIME INTERVAL
TIMER I/Os
COMMENT
0
Doubled period
Outputs 0.5
PWM Frequency
Period register CCR0. Output of a symmetrical 8.484 kHz signal
1
Period
Outputs PWM
1 .. PERIOD–1
Generation of PWM. Pulse length stored in TA1PWM. Dedicated
interrupt handler for update.
2
External event
Input pin CCI2A
is used
Measures high signal part ∆t2. Length of positive signal part is
stored in PP2. Maximum input frequency is 2 kHz.
3
External event
Input pin CCI3A
is used
Captures event time t3 of the trailing edge of the input signal.
Event time t3 stored in TIM3. Maximum input frequency is 3 kHz.
4
Period
Outputs PWM 0
–100%
Generation of PWM. Pulse length stored in TA4PWM. Update by
capture/compare block 0.
Note:
The maximum input frequencies for capturing purposes shown above are
used for the overhead calculation only. The limits of the Timer_A hardware
allow it to capture much higher input frequencies.
Figure 6–43 illustrates the four tasks described above — they are not shown
to scale.
6-174
The Timer_A
Period Counter TIMACNT
Cycle Counter TIMACYC
n
n × Period
n+1
(n+1) × Period
n+2
(n+2) × Period
n+3
(n+3) × Period
CCR0
Timer Register TAR
CCR1
CCR4
0h
PWM Signal at TA1
PWM Signal at TA4
∆ t2
Time Measurement
at CCI2A
Captured Edge t3
Capturing of Leading
Edges at CCI3A
Doubled Period at TA0
Time
Figure 6–43. PWM Generation and Capturing With the Up Mode
Example 6–46. PWM Generation and Capturing With the Up Mode
; Timer_A used for PWM–generation and Capturing.
;
FLLMPY
.equ
116
; fMCLK = 3.801MHz
fper
.equ
16969
; 16.969kHz repetition rate
TCLK
.equ
FLLMPY*32768
; TCLK: FLLMPY x fcrystal
PERIOD
.equ
((2*TCLK/fper)+1)/2 ; frep = 19.969kHz
;
; RAM Definitions
;
TA1PWM
.equ
202h
; PWM pulse length TA1
TIM2
.equ
204h
; Time of leading edge at CCI2A
PP2
.equ
206h
; Length of high part at CCI2A
TIM3
.equ
208h
; Time of leading edge at CCI3A
TA4PWM
.equ
20Ah
; PWM pulse length for TA4
TIMACYC0 .equ
20Ch
; Cycle counter low
TIMACYC1 .equ
20Eh
; Cycle counter high
On-Chip Peripherals
6-175
The Timer_A
TIMACNT
.equ
210h
; Period counter
STACK
.equ
600h
; Stack initialization address
.text
INIT
; Software start address
MOV
#STACK,SP
; Initialize Stack Pointer
CALL
#INITSR
; Init. FLL and RAM
;
; Initialize the Timer_A: MCLK, Up Mode, INTRPTs on
;
MOV
#ISMCLK+CLR,&TACTL ; No TIMOV interrupt
MOV
#PERIOD–1,&CCR0
; Define period
MOV
#OMT+CCIE,&CCTL0
; Toggle TA0, INTRPT on
MOV
#OMRS+CCIE,&CCTL1 ; Reset/Set Mode, INTRPT on
MOV
#CMBE+ISCCIA+SCS+CAP+CCIE,&CCTL2 ; Both edges
MOV
#CMPE+ISCCIA+SCS+CAP+CCIE,&CCTL3 ; Pos. edge
MOV
#OMSR,&CCTL4
MOV.B
#TA4+TA3+TA2+TA1+TA0,&P3SEL ; Define I/Os
CLR
TIMACYC0
; Clear low cycle counter
CLR
TIMACYC1
; Clear high cycle counter
CLR
TIMACNT
; Clear period counter
MOV
#1,TA1PWM
; TA1 pulse length = 1
MOV
#0,TA4PWM
; TA4 pulse length = 0
MOV.B
#CBACLK+CBE,&CBCTL ; Output ACLK at XBUF pin
BIS
#MUP,&TACTL
; Set/Reset Mode, no INTRPT
;
EINT
; Start Timer in Up Mode
; Enable interrupts
MAINLOOP ...
; Continue in background
; Calculations for the new PWM values start.
; The new result in R6 is written to TA1PWM after completion.
; The PWM range is from 1 to PERIOD–1: no checks necessary
;
...
MOV.B
; Calculate TA1PWM value to R6
R6,TA1PWM
; Actualize pulse length
;
; The new result in R6 is written to TA4PWM after completion.
; The PWM range is from 0% to 100%: no checks necessary
;
6-176
The Timer_A
...
MOV.B
; Calculate TA4PWM value to R6
R6,TA4PWM
...
; Actualize pulse length
; Continue in background
;
; Interrupt handler for the Period Register CCR0. 8.484kHz
; are output at TA0 for synchronization.
;
TIMMOD0
MOV
TA4PWM,&CCR4
; Update CCR4
ADD
#PERIOD,TIMACYC0
; Actualize cycle counters
ADC
TIMACYC1
INC
TIMACNT
; Incr. period counter
RETI
;
; Interrupt handlers for Capture/Compare Blocks 1 to 4.
; The interrupt flags CCIFGx are reset by the reading
; of the Timer Vector Register TAIV
;
TIM_HND
ADD
&TAIV,PC
RETI
; Add Jump table offset
; Vector 0: No interrupt pending
JMP
TIMMOD1
; Vector 2: Block 1
JMP
TIMMOD2
; Vector 4: Block 2
JMP
TIMMOD3
; Vector 6: Block 3
RETI
; Update by C/C Block 0
RETI
; Vector 10: TIMOV not used
;
; Capture/Compare Block 1 generates a positive PWM signal at
; output TA1. Pulse width is defined in TA1PWM
;
TIMMOD1
MOV
TA1PWM,&CCR1
; Define pulse width
EINT
; Allow nested interrupts
...
; Task1 starts here
RETI
;
; The high part of the CCI2A input signal is measured.
; The result is stored in PP2. The complete handler is time
; critical: nested interrupts cannot be used.
On-Chip Peripherals
6-177
The Timer_A
; First a check is made if the cycle counter TIMACYC0 contains
; the value corresponding to the captured value in CCR2, or if
; TIMACYC0 is yet updated due to interrupt latency time.
;
TIMMOD2
CMP
&CCR2,&TAR
; Occurred overflow of TAR?
JHS
TM20
; No, Timer Reg. > capt. value
BIT
#CCIFG,&CCTL0
; Yes, TIMACYC0 yet updated?
JNZ
TM20
; No, value matches with CCR2
SUB
#PERIOD,&CCR2
; Yes, use CCR2 for correction
;
TM20
BIT
#CCI,&CCTL2
; Input signal high?
JZ
TM21
; No, time for calculation
MOV
TIMACYC0,TIM2
; Yes, store cycle counter
ADD
&CCR2,TIM2
; Time for leading edge in TIM2
RETI
;
TM21
; High part is calculated:
MOV
TIMACYC0,PP2
; Event time of trailing edge
ADD
&CCR2,PP2
; Add captured time
SUB
TIM2,PP2
; Subtr. time of leading edge
RETI
; Length of high part in PP2
;
; Capture/Compare Block 3 captures the time of trailing edges
; at CCI3A. TIM3 stores the time of the actual edge
;
TIMMOD3
CMP
&CCR3,&TAR
; Occurred overflow of TAR?
JHS
TM30
; No, Timer Reg. > capt. value
BIT
#CCIFG,CCTL0
; Yes, TIMACYC0 yet updated?
JNZ
TM30
; No, value matches with CCR3
SUB
#PERIOD,&CCR3
; Yes, use CCR3 for correction
;
TM30
MOV
TIMACYC0,TIM3
; Store sum of cycle counter
ADD
&CCR3,TIM3
; and captured event time
.sect
”TIMVEC”,0FFF0h
; Timer_A Interrupt Vectors
.word
TIM_HND
RETI
;
6-178
; C/C Blocks 1..4 Vector
The Timer_A
.word
TIMMOD0
; Vector for C/C Block 0
.sect
”INITVEC”,0FFFEh
; Reset Vector
.word
INIT
The above example results in a maximum (worst case) CPU loading uCPU
(ranging from 0 to 1) by the Timer_A activities:
CCR0 — repetition rate 16.969 kHz
CCR1 — repetition rate 16.969 kHz
CCR2 — repetition rate max. 2 kHz
CCR3 — repetition rate max. 3 kHz
CCR4 — repetition rate 16.969 kHz
uCPU =
16.969
10 6
19 cycles for the task, 11 cycles overhead
6 cycles for the update, 17 cycles overhead
60 cycles for the update, 32 cycles overhead
20 cycles for the update, 16 cycles overhead
6 cycles for the update, 0 cycles overhead
(30 + 23 + 6 ) + 2.0
3.801 10
10 3
6
92 + 3.0 10 3
36
30 cycles
23 cycles
92 cycles
36 cycles
6 cycles
= 0.34
The above result means a worst case CPU loading of approximate 34% due
to the Timer_A activities (the tasks of the capture/compare blocks 2, 3 and 4
are not included).
6.3.9.10 Conclusion
This section demonstrated the possibilities of the Timer_A running in the up
mode. Despite the dominance of the period register (CCR0) it is possible to
capture signals, compare time intervals, and create timings in a real-time environment — all this in parallel with the pulse width modulation generated with
the up mode.
On-Chip Peripherals
6-179
The Timer_A
6.3.10 Software Examples for the Up/Down Mode
This section shows several proven application examples for the Timer_A running in the up/down mode. Software definitions appear in the appendix. Whenever possible, the abbreviations defined in the MSP430 Architecture Guide
and Module Library are used.
The software examples are independent of the MCLK frequency in use. Only
the FLL multiplier constant, FLLMPY, and the repetition rate, fper, need to be
redefined if another combination is needed. The source lines for the definition
of these important values are:
FLLMPY
.equ
122
; 1. FLL multiplier
fper
.equ
19200
; 2. PWM Repetition rate
TCLK
.equ
FLLMPY*32768/4
; 3. FLLMPY x fcrystal/4
HLFPER
.equ
(TCLK/fper)/2
; 4. Half Period of the PWM
Note:
The definitions assume an external crystal or an external frequency at the
XIN input with a frequency of 32.768 kHz (215 Hz).
1) Definition of the CPU frequency fMCLK. The multiplier FLLMPY for the
digitally controlled oscillator (DCO) is defined. The value for the actual frequency fMCLK is (FLLMPY × 215). The value 122 stands for fMCLK = 122
× 215 = 3.9977 MHz.
2) Definition of the desired repetition rate. The value 19200 stands for a
repetition rate of 19.2 kHz, which means 19200 complete up and down
counts of the timer register TAR.
3) Definition of the input frequency for the Timer Register (TAR). The expression /4 indicates that the input divider is switched to the Divide–by–
Four mode. The value shown stands for TCLK = 3.9977 MHz /4 = 999.424
kHz. Only the predivider used for the input divider (here /4) needs to be
defined.
4) Calculation of the TCLK cycles for the defined half period. The full period consists of the half period counting up to the content of the period register CCR0 and the one counting down to 0 again. No change is necessary
for this line.
6-180
The Timer_A
6.3.10.1 Common Remarks
The up/down mode should be considered only for pulse width modulation
(PWM) or DC generation. The advantage of this special PWM mode is the contributed switching of the output signals — unlike the up mode that switches on
all output pulses at exactly the same time (when the timer register TAR is reset
to 0), the up/down mode switches on and off the output pulses symmetrical to
the 0 content of the timer register. See figure 6–44. If this feature is not needed,
then the up mode with its simpler handling or the continuous mode with its five
independent timings should be used.
Advantages of the Up/Down Mode:
- Distributed current switching (e.g. for digital motor control (DMC) applica-
tions)
- Free run without CPU loading for fixed PWM values (DAC, DMC)
- High PWM frequency possible due to pure hardware control
- Clever timings of the period register are usable for more than one real-time
job
- For a given PWM repetition rate, an equally spaced second interrupt is
available from the timer overflow interrupt, TIMOV. This doubles the available resolution for some applications
Disadvantages of the Up/Down Mode:
- Dominance of the period register — defines the time frame
- Direction change of the period register during the run needs special soft-
ware handling. Interrupt-driven count direction indication is necessary for
the software.
- Capturing has an inherent uncertainty for capturing values near the zero
point (TAR = 0) and the middle of the period (TAR = CCR0).
- RAM extension for the timer register is necessary due to the normally short
period.
- Change of the pulse width may cause an erroneous signal during one peri-
od.
On-Chip Peripherals
6-181
The Timer_A
6.3.10.1.1 Initialization
The initialization subroutine INITSR is used by all examples. This subroutine
was explained and included in section Software Examples of the Continuous
Mode. It includes the following tasks:
- Checks the reason for the initialization (switch on of the supply voltage,
watchdog interrupt, or activation of the RESET input)
- Clears the RAM — or not — depending on the result of the check above
- Programs the system clock oscillator (multiplication factor N and optimum
current switch FN_2, FN_3, or FN_4)
- Allows the digitally controlled oscillator to settle at the appropriate tap, pro-
viding the correct MCLK frequency
6.3.10.1.2 Timer Clock
For the timer clock, there is no difference between the up mode and the up/
down mode. See section Software Examples for the Up Mode for details.
6.3.10.1.3 Timing Considerations
As with the up mode, the independence of the five timings provided by the continuous mode is not possible with the up/down mode. The period register
(CCR0) dictates the timing frame for all other capture/compare blocks. With
the up/down mode, things are a little bit more complex due to the count direction change of the timer register (TAR) when it reaches the content of the period register (CCR0).
Two additional RAM registers — as with the up mode — are used for the management of the compared or captured data:
- TIMACNT — Period counter. This register counts the number of half peri-
ods. Its bit 0 (LSB) functions as the count direction bit for the timer register
TAR:
H
TIMACNT.0 = 0 — Timer register counts upward to nCCR0
H
TIMACNT.0 = 1 — Timer register counts downward to 0
- TIMACYCx — Cycle counter. Counts the TCLK cycles of the timing (one
or more words)
See also figure 6–48. The contents of these two registers, including the count
direction bit, are shown there for an example. Figure 6–52 gives an explanation of the update of these two registers.
6-182
The Timer_A
Update of Extension Registers — Unlike with the continuous mode and the
up mode, the update of these extension registers is made with the interrupt
handlers of both the period register (CCR0) and the timer overflow interrupt
(TIMOV). The reason is the count direction bit that needs to be updated each
half period (up and down count direction). The main part is executed by the
interrupt handler of the period register due to its higher interrupt priority and
faster interrupt response. The method used for the update of the extension
registers allows an automatic self synchronization:
BIS
#1,TIMACNT
; CCR0: TIMACNT always odd
TIMACNT
; Timer Overflow: increment
...
INC
Real Time Environment — See section Software Examples for the Up Mode
for details. There is no difference between the up mode and the up/down
mode.
Output Units — The shown PWM examples all use the toggle/reset mode
(positive output pulses) or the toggle/set mode (negative output pulses) of the
output units. The other output modes are not applicable for PWM generation
in the up/down mode.
6.3.10.1.4 Interrupt Overhead
The calculations for the CPU loading that are appended to the software examples split the necessary cycles for an interrupt into two parts:
- Overhead — This part sums the cycles that are necessary for the CPU
to execute the interrupt (saving of the program counter and the status register, decision as to which interrupt needs to be serviced, and restoring of
the CPU registers).
- Update or Task — This actually does the work that needs to be done (in-
crementing of counters, changing of status bytes, reading of input information, etc.).
Like it is for the up mode, the number of overhead cycles is:
Interrupt of the period register CCR0
Interrupt of capture/compare registers x:
Interrupt of the timer register overflow:
11 MCLK cycles
16 MCLK cycles
14 MCLK cycles
On-Chip Peripherals
6-183
The Timer_A
6.3.10.2 Differences Between the Timer_A Versions
Two versions of the Timer_A hardware exist. They differ only in the performance of the up/down mode:
- The version in the current MSP430C33x outputs a 50% PWM signal with
a doubled period if the capture/compare register contains 0. See Figure
6–44.
- The improved version running in the MSP430C11x, MSP430C33xA, and
all future family members outputs a fixed voltage (0% or 100% PWM) for
the capture/compare register content = 0. See Figure 6–45.
CCRx = 0
3
2
Output Mode
CCRx = 1
3
2
1
1
3
3
2
2
1
0
1
0
CCRx = CCR0–1
3
3
2
2
1
1
0
CCRx = CCR0
3
3
2
2
1
1
0
CCRx > CCR0
3
3
2
2
1
1
0
Toggle/Set
50%
67%
33%
0%
100%
Toggle/Reset
50%
33%
67%
100%
0%
EQU0
CCR0
Contains 3
EQU0
EQUx
TIMOV
EQU0
EQUx
TIMOV
EQU0
EQUx
Figure 6–44. PWM Signals at Pin TAx for the Current MSP430C33x Version
6-184
TIMOV
The Timer_A
CCRx = 0
CCRx = 1
3
3
2
Output Mode
2
1
Toggle/Reset
2
1
1
0
CCRx = CCR0–1
3
3
2
2
1
1
0
CCRx = CCR0
3
3
2
2
1
1
0
CCRx > CCR0
3
3
2
2
1
1
0
100%
67%
33%
0%
100%
0%
33%
67%
100%
0%
EQU0
CCR0
Contains 3
3
2
1
0
Toggle/Set
3
EQU0
EQUx
TIMOV
EQU0
EQUx
TIMOV
EQU0
TIMOV
EQUx
Figure 6–45. PWM Signals at Terminal TAx for the Improved MSP430C11x Version
The software examples are applicable to both versions — the distinction is
made by a software flag named TAV0:
TAV0 = 0 — the Timer_A version of the current MSP430C33x is used
TAV0 = 1 — the improved Timer_A version for the MSP430C11x is used
Both versions output the correct 0 value for CCRx > CCR0. The longest half
period that can be used is 0FFFEh, due to the value 0FFFFh necessary for 0.
6.3.10.2.1 .MACRO Definition for the PWM Range Check
Due to the behavior of the Timer_A running in the up/down mode, checks must
be made to determine if the calculated PWM values are in the acceptable
range or not.
Note:
These checks are not necessary if tables that contain valid data only are
used, — 0FFFFh for the output value 0 and the content of the period register
CCR0 as the maximum value (100%), for example.
To get a legible source, these checks are written as an assembler macro. This
macro replaces the following two checks:
- If the calculated PWM value is greater than the half period contained in the
period register CCR0
- If the calculated PWM value is 0
On-Chip Peripherals
6-185
The Timer_A
If one of these two possibilities is true, then a corrected value is used.
The macro is designed for two modes. They are distinguished by the software
flag PERIOD_VAR:
- Fixed period — period register CCR0 always contains the same value.
PERIOD_VAR = 0
- Variable period — CCR0 contains variable values. PERIOD_VAR = 1
The macro also distinguishes between the two Timer_A hardware versions
(see Section 6.3.10.2 for details):
- The current MSP430C33x hardware:
TAV0 = 0
- The improved MSP430C11x hardware:
TAV0 = 1
Example 6–47. Macro Code
; The MACRO corrects input values addressed by arg1
; (0 to 0FFFEh) to valid input values.
; The four destination addressing modes are valid for arg1.
;
CHCK_PWM_RNG
.macro
arg1
; arg1: address of PWM value
.if
PERIOD_VAR=0
; Fixed or variable period?
CMP
#HLFPER+1,arg1
; Fixed: result > HLFPER?
JLO
L$1?
; No, proceed
MOV
#HLFPER,arg1
; Yes, use HLFPER (100%)
.else
; Variable period
CMP
arg1,&CCR0
; Result > Period Register?
JHS
L$1?
; No, proceed
MOV
&CCR0,arg1
; Yes, use HLFPER (100%)
.endif
L$1?
L$2?
.equ
$
.if
TAV0=0
; MSP430x33x or x1xx?
TST
arg1
; MSP430x33x:
JNZ
L$2?
; is arg1 = 0?
MOV
#0FFFFh,arg1
; Yes, use max. value
.equ
$
.endif
6-186
The Timer_A
.endm
The call of the above macro is
; Definitions for the .MACRO
;
PERIOD_VAR .equ
0
; Fixed period
TAV0
0
; MSP430x33x version
.equ
...
CHCK_PWM_RNG
MOV
R6
R6,TA1PWM
; Check calc. PWM value in R6
; Corrected value to buffer
; or
CHCK_PWM_RNG
MOV
HELP
HELP,TA1PWM
; Check PWM value in HELP
; Update buffer
Note:
Software written for the MSP430C33x version of the Timer_A is upward compatible with the MSP430C11x version — it will also run well with the improved
Timer_A hardware (only an unnecessary check for zero is made).
6.3.10.3 Update of the Capture/Compare Registers
As with the up mode, only a synchronous update will give undisturbed output
pulses. The update with the accompanying interrupt handler is not possible for
the up/down mode — the required toggling results in unpredictable output
pulses for this kind of update. Four possibilities are shown here for the synchronous update by the Interrupt Handlers of capture/compare block 0 and the
timer overflow:
1) Frequent common update of the capture/compare registers by the CCR0
handler
2) Frequent common update of the capture/compare registers by the TIMOV
handler
3) Infrequent common update
4) Infrequent individual update
Unlike with the continuous mode and the up mode, only the interrupts of the
period register (CCR0) and the timer overflow (TIMOV) are enabled for all of
the four update modes.
The four possibilities are described in the following paragraphs. To find the appropriate solution for a given timing problem, the following decision path may
be used:
On-Chip Peripherals
6-187
The Timer_A
- Is a very fast update of the capture/compare registers necessary? If yes,
use solution 1 or 2, if no, continue.
- Are all of the new update values available at the same time? If yes, use
solution 3, otherwise use solution 4.
6.3.10.3.1 Frequent Common Update by CCR0
The interrupt handler of capture/compare block 0 updates the capture/
compare registers CCRx with the repetition rate defined by the period register
CCR0.
This update mode is used for the Digital Motor Control with Symmetric Pulse
Width Modulation.
If the range for the PWM output values is limited from 1 cycle to (CCR0) cycles,
then the following simple update sequence may be used:
; R6 contains new PWM info for CCR2. Range: 1 to (CCR0).
;
MOV
R6,TA2PWM
; Actualize PWM buffer
If the calculation results for the PWM output values can be 0% or >100%:
CCRx > CCR0 .or. CCRx = 0
for the current MSP430C330x
CCRx > CCR0
for the MSP430C110x,
then a special treatment is necessary due to the special behavior of the capture/compare logic under these circumstances. The capture/compare register
x value then needs to be modified. To determine these special cases, the following update sequence may be used (the macro CHCK_PWM_RNG is explained in Section 6.3.10.2.1 .MACRO Definition for the PWM Range Check):
; R6 contains the calculated PWM info for CCR2.
; Range: 0 to HLFPER+x. Check if a modification is necessary
; Software is written for a constant Period Register CCR0
;
PERIOD_VAR .equ
0
; Constant period
TAV0
0
; MSP430x33x version
.equ
...
CHCK_PWM_RNG
MOV
...
6-188
R6
R6,TA2PWM
; Correct R6 if out of range
; Actualize TA2PWM buffer
; Continue
The Timer_A
If a variable period is used — the content of the period register CCR0 changes
during the program flow — then the lines above change to:
; R6 contains the calculated PWM info for CCR2.
; Range: 0 to HLFPER+x. Check if a modification is necessary
; Software is written for a variable Period Register CCR0
;
PERIOD_VAR .equ
1
; Variable period
TAV0
0
; MSP430x33x version
.equ
...
CHCK_PWM_RNG
MOV
R6
R6,TA2PWM
...
; Correct R6 if out of range
; Actualize TA2PWM buffer
; Continue
The part of the code that modifies the PWM values of the Timer_A looks like
this:
; Handler of the Period Register CCR0
;
TIMMOD0
MOV
TA1PWM,&CCR1
; Modify C/C Block 1 synchr.
MOV
TA2PWM,&CCR2
; Modify C/C Block 2 synchr.
MOV
TA3PWM,&CCR3
; Modify C/C Block 3 synchr.
ADD
#2*HLFPER,TIMACYC0
...
; Other tasks of the handler
RETI
6.3.10.3.2 Frequent Common Update by the Timer Overflow TIMOV
If the interrupt handler of the period register CCR0 has to perform many tasks,
then it is advised to shift one half of these tasks to the interrupt handler of the
timer overflow (TIMOV). This handler has the lowest interrupt priority, but with
the up/down mode, this does not play a role because the interrupts of the capture/compare blocks 1 to 4 are normally disabled. The same background software is used as is shown with the update by the period register (CCR0) (the
macro CHCK_PWM_RNG is explained in Section 6.3.10.2.1 .MACRO Definition for the PWM Range Check).
;
PERIOD_VAR .equ
0
; Fixed period
TAV0
1
; MSP430x11x version
.equ
...
; Calc. PWM value in R7
On-Chip Peripherals
6-189
The Timer_A
CHCK_PWM_RNG
MOV
R7
R7,TA2PWM
...
; Correct R7 if out of range
; Actualize TA2PWM buffer
; Continue
The part of the code that modifies the PWM values of the Timer_A looks like
this:
TIM_HND
ADD
&TAIV,PC
; Serve highest Timer_A request
RETI
; No request
RETI
; C/C Block 1: INTRPT disabled
RETI
; C/C Block 2: INTRPT disabled
RETI
; C/C Block 3: INTRPT disabled
JMP
TIMMOD4
; C/C Block 4: Capturing
;
; Handler of the Timer Overflow TIMOV
;
TIMOV
MOV
TA1PWM,&CCR1
; Timer_A reached zero:
MOV
TA2PWM,&CCR2
; Modify C/C Blocks x
MOV
TA3PWM,&CCR3
INC
TIMACNT
; Actualize half period counter
RETI
6.3.10.3.3 Infrequent Common Update
The interrupt handlers of the capture/compare block 0 or the timer overflow update the capture/compare registers CCRx with a repetition rate given by the
calculation speed of the background program. If new PWM values are calculated or read for all capture/compare blocks, then a common flag is set and the
update is enabled in this way. This solution is used if the PWM values for the
update are available at (nearly) the same time — by table processing, for example.
This update mode is used with the example TRIAC Control.
If the range for the calculated PWM output values is limited from 1 cycle to
(CCR0) cycles, then the following simple update sequence may be used:
; R6 to R8 contain new PWM info for Output Units 1 to 3
; Range: 1 to (CCR0).
;
6-190
The Timer_A
MOV
R6,TA1PWM
; Actualize CCR1 pulse length
MOV
R7,TA2PWM
; CCR2
MOV
R8,TA3PWM
; CCR3
BIS.B
#1,FLAG
; Set update flag
...
; Intrpt handler resets FLAG
If the output values 0% or >100% are actually used, then a special treatment
is necessary. To correct these special cases, the following update sequence
may be used (the macro CHCK_PWM_RNG is explained in Section 6.3.10.2.1
.MACRO Definition for the PWM Range Check):
; R6 to R8 contain new PWM info for Output Units 1 to 3.
; Range: 0 to (CCR0)+x.
; Check if a correction is necessary.
;
CHK_PWM_RNG
MOV
R6
R6,TA1PWM
CHK_PWM_RNG
MOV
R7
R7,TA2PWM
CHK_PWM_RNG
R8
MOV
R8,TA3PWM
BIS.B
#1,FLAG
...
; Check the PWM range
; Write corrected R6 to buffer
; Check the PWM range
; Write corrected R7 to buffer
; Check the PWM range
; Write corrected R8 to buffer
; Start common update
; Continue in background
The update part of the code in the interrupt handlers of the period register
CCR0 or the timer overflow TIMOV looks like this:
L$1
BIT.B
#1,FLAG
; Is update flag set?
JZ
L$1
; No, continue
MOV
TA1PWM,&CCR1
; Actualize CCR1 pulse length
MOV
TA2PWM,&CCR2
; dito CCR2
MOV
TA3PWM,&CCR3
; dito CCR3
BIC.B
#1,FLAG
; Reset update flag
...
; Continue INTRPT handler
If the other seven bits of the RAM byte FLAG are not used, then a faster version
of the above update sequence may be used. The resetting of the bit is not necessary and saves 4 cycles.
RRA.B
FLAG
; Is update flag FLAG.0 set?
On-Chip Peripherals
6-191
The Timer_A
L$1
JNC
L$1
; No, continue
MOV
TA1PWM,&CCR1
; Actualize CCR1 pulse length
MOV
TA2PWM,&CCR2
; dito CCR2
MOV
TA3PWM,&CCR3
, dito CCR3
...
; Continue INTRPT handler
6.3.10.3.4 Infrequent Individual Update
The interrupt handler of the period register or the Timer Overflow update the
capture/compare register CCRx with a repetition rate given by the calculation
speed of the background program. If a new PWM value is calculated for a capture/compare block, then an individual flag is set and the update for this capture/compare block is made. This method is used if the PWM values for the
update are not available at the same time. This update mode is used with the
example Capturing with the Up/Down Mode. It is the update mode with the lowest overhead. The macro CHCK_PWM_RNG is detailed in Section 6.3.10.2.1
.MACRO Definition for the PWM Range Check.
; R6 contains new PWM info for CCR1. Range: 0 to (CCR0)+x.
; Check if a modification is necessary:
; Software is written for a variable Period Register CCR0
;
TAV0
.equ
PERIOD_VAR .equ
0
; MSP430X33x version
1
; Variable period
...
CHK_PWM_RNG
R6
; Check/correct result in R6
MOV
R6,TA1PWM
; Actualize TA1PWM buffer
BIS
#2,FLAG
; Start update of CCR1
...
; Start calculation for CCR2
;
; R6 contains new PWM info for CCR2. Range: 0 to (CCR0)+x
;
CHK_PWM_RNG
R6
MOV
R6,TA2PWM
BIS
#4,FLAG
...
; Actualize TA2PWM buffer
; Start update of CCR2
; Continue
The interrupt handler of the period register CCR0 or the timer overflow (TIMOV) decodes the necessary task as follows (4 to 20 MCLK cycles are needed):
6-192
The Timer_A
...
ADD
; TIMOV or CCR0 handler
FLAG,PC
; Flag contains 0 to 6
RETI
P2
; 0: No update necessary
JMP
P1
; 2: Update CCR1
JMP
P2
; 4: Update CCR2
MOV
TA1PWM,&CCR1
; 6: Update CCR2 and CCR1
MOV
TA2PWM,&CCR2
; 4: Update only CCR2
CLR
FLAG
RETI
;
P1
MOV
TA1PWM,&CCR1
CLR
FLAG
; 2: Update only CCR1
RETI
The above sequence may be changed easily for the update of three capture/
compare registers (like is used for three phase DMC).
6.3.10.3.5 Overhead for the Update
These four update modes may be mixed if this is an advantage.
Table 6–24 shows the overhead calculation and the percentage of the update
overhead for the four different update methods. The calculation results are
based on:
fMCLK
fupdate
fper
n
Frequency of the system clock generator (MCLK)
Update frequency for the capture/compare registers
Timer_A repetition rate defined by the period register CCR0
Number of C/C blocks used for the PWM generation
4 MHz
1 kHz
12 kHz
3
Table 6–24. Interrupt Overhead for the Four Different Update Methods
UPDATE METHOD
OVERHEAD FORMULA (CPU CYCLES)
OVERHEAD PERCENTAGE
Frequent Update with CCR0
n × fper × 6
5.4%
Frequent Update with TIMOV
n × fper × 6
5.4%
(fper × 6) + (fupdate x (n × 6 + 4))
(fper –fupdate) × 3 + (fupdate × 15)
2.3%
Infrequent Common Update
Infrequent Individual Update
1.2%
Note:
No interrupt is generated – and therefore no interrupt overhead – for capture/
compare registers containing a value greater than the content of the period
register CCR0 (output TAx = 0 for Toggle/Reset resp. TAx = 1 for Toggle/Set).
On-Chip Peripherals
6-193
The Timer_A
6.3.10.4 Digital Motor Control With Symmetric Pulse Width Modulation
The medium output voltage VPWM at the TAx terminal with respect to the necessary register content (nCCRx) for a given voltage VPWM is:
VPWM = Vcc ×
Where:
VPWM
VCC
nCCR0
nCCRx
tpw
tper
nCCRx
nCCR0
= Vcc ×
tpw
→ nCCRx
tper
=
VPWM
× nCCR0
Vcc
Medium output voltage at the TAx terminal
Supply voltage of the system
Content of the period register CCR0
Content of the capture/compare register CCRx
Time generated by the capture/compare register
Period generated by the period register CCR0
[V]
[V]
[s]
[s]
Table 6–25 shows the necessary content of a capture/compare register CCRx
to get some defined values for an unsigned output voltage VPWM:
Table 6–25. Output Voltages for Unsigned PWM
OUTPUT VOLTAGE (VPWM)
0.25
0.5
0.75
CONTENT OF CCRx nCCRx
0V
0
VCC
VCC
nCCR0
0.25
nCCR0
0.5
VCC
VCC
nCCR0
0.75
nCCR0
If the output voltage is seen as a signed voltage — like for 3-phase digital motor
control — then the voltage 0.5 × VCC is seen as the 0 point. The signed output
voltage VPWM gets:
nCCRx
(n
VPWM = Vcc ×
– 0.5
CCR0
)→
nCCRx =
(VVcc + 0.5) × n
PWM
CCR0
To calculate the value for nCCRx for the sine of a given angle, α, the formula
is (full VCC range):
nCCRx
=
1+ sina
× nCCR0
2
Table 6–26 shows the necessary contents of a capture/compare register
CCRx to get some defined values for a signed output voltage VPWM.
6-194
The Timer_A
Table 6–26. Output Voltages for Signed PWM
OUTPUT VOLTAGE (VPWM)
CONTENT OF CCRx nCCRx
COMMENT
–0.5
VCC
0
–0.25
VCC
nCCR0
0.25
nCCR0
0.5
Half negative output voltage
nCCR0
Half positive output voltage
0V
0.25
VCC
0.5
VCC
0.75
nCCR0
Most negative output voltage
0 voltage
Most positive output voltage
Figure 6–46 shows some of the output voltages listed above for a three-phase
system.
(CCRx)
Phase
Voltage
Vmotor
(CCR0)
Vmmax
0
(CCR0)/2
120°
0
–Vmmax
120°
Time
Vmotor
0
Figure 6–46. PWM Outputs for Different Phase Voltages
Note that 0 volt for a motor phase is generated by a pulse width of one half of
the length of the period.
Example 6–48. PWM Outputs for Different Phase Voltages
The software example shows the generation of PWM output signals for a
three-phase electric motor. The MSP430 delivers the PWM output signals and
controls the speed of the motor by the input signal CCI4A coming from the
tach/generator.
The capture/compare blocks 1 to 3 are used for the generation of the PWM
signals for the three phases.
The capture/compare block 4 is used for the capturing of the speed signal coming from the shaft of the motor. Up to 6000 rpm (100 rev/sec) are used with this
example, with four output pulses per revolution. The positive edge of the input
signal is captured and requests interrupt.
On-Chip Peripherals
6-195
The Timer_A
All security functions are included in the external control chip IR2130 (over current, delays for the transistors, etc.).
COM
SEL
Torque
r/m
Error
0V
Position/Speed
M
TA4
4 Pulse/Revolution
15 V
VCC
TA0
MSP430C33x
11DF4
5V
VCC
6 kHz
IR2130
74HC00
LIN1
TA1
HIN1
LIN2
TA2
HIN2
TA3
LIN3
325 V
VMOTOR
VB3
VB2
VB1
H01
HO2
HO3
10 µF
VS3
VS2
VS1
L03
30S10
HIN3
L01
FAULT
P0.x
L02
VS
VSS
VSS
5V
6 x IRGBC20S
Itrip
Overcurrent
Adjustment
0V
Shunt
0V
5 µF
15 V
Figure 6–47. PWM Motors Control for High Motor Voltages
The system clock frequency is 4 MHz (exactly fMCLK = 122 × 32768 = 3.9977
MHz). The pulse repetition frequency is 12 kHz.
The output unit 0 outputs 6 kHz without any overhead. This signal may be used
for peripherals or for synchronization. The signal is always present, even if the
signals at the TAx outputs disappear due to an output signal with 0% or 100%
pulse width.
The example uses the frequent common update of the compare/compare register. See Section 6.3.10.3.1 Frequent Common Update by CCR0 for details.
6-196
The Timer_A
Figure 6–48 shows the output signals at the times that they have phase shifts
of 0_, +120_ and –120_.
TIMACYC0
Direction Bit
TIMACNT
0FFFFh
2n × thlfper
(2n + 2) × thlfper
(2n + 4) × thlfper
0
1
0
1
0
2n
2n + 1
2n + 2
2n + 3
2n + 4
thlfper
CCR0
CCR2
CCR1
CCR3
0h
TA1 Output
0°
(0.5 × Vmotor)
tpw1
tpw2
TA2 Output
120°
(0.93 × Vmotor)
tpw3
–120°
(0.07 × Vmotor)
TA3 Output
TIMOV
EQU0
TIMOV
EQU0
TIMOV
Interrupts
Figure 6–48. Symmetric PWM Timings Generated With the Up/Down Mode
Example 6–49. Symmetric PWM Timings Generated With the Up/Down Mode
; Software example:
; TA0: symmetric output signal
6.0kHz
; TA1: positive PWM signal
12.0kHz. Length in TA1PWM
; TA2: positive PWM signal
12.0kHz. Length in TA2PWM
; TA3: positive PWM signal
12.0kHz. Length in TA3PWM
;
; Hardware definitions
;
FLLMPY
.equ
122
; FLL multiplier for 3.9977MHz
fper
.equ
12000
; 12.0kHz repetition rate
TCLK
.equ
FLLMPY*32768
; TCLK: FLLMPY x fcrystal
HLFPER
.equ
(TCLK/fper)/2
; Period of output signals
On-Chip Peripherals
6-197
The Timer_A
TAV0
0
; MSP430C33x Timer_A
PERIOD_VAR .equ
.equ
0
; Invariable period in CCR0
STACK
600h
; Stack initialization address
.equ
;
; RAM definitions
;
TA1PWM
.equ
202h
; Pulse length Block 1 (0..167)
TA2PWM
.equ
204h
; Pulse length Block 2 (0..167)
TA3PWM
.equ
206h
; Pulse length Block 3 (0..167)
CPT4
.equ
208h
; Captured motor shaft events
TIMACYC0 .equ
20Ah
; Low cycle counter (15..0)
TIMACYC1 .equ
20Ch
; High cycle counter (31..16)
TIMACNT
20Eh
; Period Counter, Bit 0 = Dir
.equ
;
.text
; Software start address
;
INIT
MOV
#STACK,SP
; Initialize Stack Pointer
CALL
#INITSR
; Init. FLL and RAM
;
; Initialize the Timer_A: MCLK, Up/Down Mode, INTRPTs on for
; TIMOV, Period Register and C/C Block 4 (Capture Mode)
;
MOV
#ISMCLK+CLR+TAIE,&TACTL ; Define Timer_A
MOV
#HLFPER,&CCR0
; Period Register
MOV
#HLFPER/2,R5
; Value for 0V to R5
MOV
R5,&CCR1
; TA1: pulse width = 0V
MOV
R5,&CCR2
; TA2: as before
MOV
R5,&CCR3
; TA3: as before
MOV
#OMT+CCIE,&CCTL0
; TA0: Toggle Mode
MOV
#OMTR,&CCTL1
; TA1: Toggle/Reset Mode
MOV
#OMTR,&CCTL2
; TA2: Toggle/Reset Mode
MOV
#OMTR,&CCTL3
; TA3: Toggle/Reset Mode
MOV
#CMPE+ISCCIA+SCS+CAP+CCIE,&CCTL4 ; +edge shaft
MOV.B
#TA4+TA3+TA2+TA1+TA0,&P3SEL ; Define I/Os
MOV
R5,TA1PWM
;
6-198
; Start value Block 1: 0V
The Timer_A
MOV
R5,TA2PWM
; Start value Block 2: 0V
MOV
R5,TA3PWM
; Start value Block 3: 0V
CLR
TIMACYC0
; Clear low cycle counter
CLR
TIMACYC1
; Clear high cycle counter
CLR
TIMACNT
; Clear period counter
MOV.B
#CBMCLK+CBE,&CBCTL ; Output MCLK at XBUF pin
BIS
#MUPD,&TACTL
EINT
; Start in Up/Down Mode
; Enable interrupts
MAINLOOP ...
; Continue in background
;
; Calculations resulted in new PWM values. The new results
; are stored in R6 (C/C Block 1), R7 (C/C Block 2) and R8
; (C/C Block 3). Check if ranges are valid:
;
CHCK_PWM_RNG
MOV
R6
; Correct R6 range
R6,TA1PWM
;
CHCK_PWM_RNG
MOV
R7
; Correct R7 range
R7,TA2PWM
;
CHCK_PWM_RNG
MOV
R8
; Correct R8 range
R8,TA3PWM
...
; Continue in background
;
; Read the last captured value of the tacho generator
;
MOV
CPT4,R6
...
; For calculations
; Control algorithm for speed
;
; Interrupt handler for CCR0: the Period Register. The cycle
; counters and the half period counter are updated.
; A symmetric 6.0kHz signal is output by the Output Unit 0
; TIMACYC0 points to next the 0–crossing of the TAR
;
TIMMOD0
MOV
TA1PWM,&CCR1
MOV
TA2PWM,&CCR2
; Update PWM registers
On-Chip Peripherals
6-199
The Timer_A
MOV
TA3PWM,&CCR3
ADD
#2*HLFPER,TIMACYC0 ; Add fixed period to
ADC
TIMACYC1
; cycle counters
BIS
#1,TIMACNT
; Half period counter +1 (Down)
RETI
;
; Interrupt handlers for Capture/Compare Blocks 1 to 4
; and Timer Overflow.
; Only the timer overflow interrupt and the C/C Block 4 are
; used. The other interrupts are disabled. The PWM generation
; is made by the timer hardware and updated by the CCR0 intrpt
;
TIM_HND
ADD
&TAIV,PC
; Add Jump table offset
RETI
; No interrupt pending
RETI
; C/C Block 1: Intrpt disabled
RETI
; C/C Block 2: Intrpt disabled
RETI
; C/C Block 3: Intrpt disabled
JMP
TIMMOD4
; C/C Block 4: Capturing used
;
; Timer overflow: the half period counter is incremented
;
TIMOV
INC
TIMACNT
RETI
; Make TIMACNT even (DIR = UP)
; Back to main program
;
; C/C Block 4 captures the revolutions of the motor. Dependent
; on the count direction of TAR, CCR4 is added or subtracted.
; The positive edge of the input signal at TA4 is captured
; and requests interrupt. Time out cannot occur due to
; low input frequency.
;
TIMMOD4
MOV
TIMACYC0,CPT4
; Cycle counter for calculation
BIT
#1,TIMACNT
; Direction UP?
JNZ
T40
; No, DOWN (1)
;
Direction is UP
ADD
RETI
6-200
&CCR4,CPT4
; Build time of captured event
; Back to main program
The Timer_A
;
T40
; Direction is DOWN
SUB
&CCR4,CPT4
; Build time of captured event
.sect
”TIMVEC”,0FFF0h
; Timer_A Interrupt Vectors
.word
TIM_HND
; C/C Blocks 1 to 4
.word
TIMMOD0
; Capture/Compare Block 0
.sect
”INITVEC”,0FFFEh
; Reset Vector
.word
INIT
RETI
;
The example results in a nominal CPU loading uCPU (ranging from 0 to 1) by
the Timer_A activities:
uCPU =
Where:
fMCLK
nintrpt
frep
1
fMCLK
Σ (nintrpt
f rep )
Frequency of the system clock (DCO)
Number of cycles executed by the interrupt handler
Repetition rate of the interrupt handler
[Hz]
[Hz]
Note:
The formula and the definitions given above are also valid for all subsequent
software examples. Therefore they are not repeated.
CCR0 — repetition rate 12 kHz
CCR4 — repetition rate 0.4 kHz
TIMOV — repetition rate 12 kHz
uCPU =
32 cycles for the task, 11 cycles overhead
18 cycles for the task, 16 cycles overhead
4 cycles for the update, 14 cycles overhead
12000 × (43 + 18 ) + 400 × 34
3.9977 × 10 6
43 cycles
34 cycles
18 cycles
= 0.186
The result means a CPU loading of 19% due to the Timer_A for the digital motor control task.
6.3.10.5 TRIAC Control
TRIAC control for electric motors (DMC) or other loads is possible using the
up/down mode as shown with the up mode of the Timer_A. But due to the secOn-Chip Peripherals
6-201
The Timer_A
ond interrupt coming from the timer overflow (TIMOV), the doubled resolution
is possible as with the up mode. The control software now counts the number
of half periods and fires the TRIAC after the reaching of the calculated value.
The medium resolution pmed is:
pmed =
Where:
fMAINS
thlfper
1
2 × fMAINS × thlfper
AC line frequency
Half period of the Timer_A, defined by CCR0
[Hz]
[s]
All considerations and formulas shown for the up mode are also valid for the
up/down mode, except the doubled resolution for the same PWM period.
Again, no capture/compare register is needed for the TRIAC control because
only the period register with its interrupt and output unit 0 is used. This frees
the remaining capture/compare blocks for other tasks.
Figure 6–49 shows the hardware for the TRIAC control of this example. The
TRIAC hardware is exactly the same hardware as used with the up mode. In
addition, a second three-phase motor is controlled by the same MSP430.
230 V AC
230 V AC
Revolutions
Zero Crossing
5V
5V
VCC
>1 M
M
TA4
5V
TA0
Comparator
_
P0.0
+
Cz
0V
MSP430
3.5 V
Overcurrent
Detection
VSS
0V
P0.7
Vmotor
TA1
TA2
Driver
M
TA3
0V
Figure 6–49. TRIAC Control and 3–Phase Control With the Timer_A
6-202
The Timer_A
Figure 6–50 illustrates the software example given below. The timer register
(TAR) is not shown to scale — 320 steps make one half wave of the 50-Hz line.
P0.0 Input
Zero Crossing
tdelay
tdelay
tdelay
tper
Timer Register TAR
TA0 Output to
TRIAC Gate
OP x thlfper
Motor
Voltage
Voltages
Conduction
Angle
AC
Figure 6–50. Signals for the TRIAC Gate Control With Up/Down Mode
Example 6–50. Static TRIAC Control Software
A static TRIAC control software example is shown. The calculated number of
half periods until the TRIAC gate is fired after the zero crossing of the AC line
voltage, is contained in the RAM word FIRANGL.
The medium resolution pmed is 320 steps per line half wave (2 × 16 kHz/100 Hz
= 320). The minimum resolution, pmin, is 204 steps (320 × 2/π = 204) which
means approximately. 0.5% resolution. See the equations above.
At the TA1, TA2, and TA3 terminals negative PWM signals for digital motor
control are output. The half period is defined by the period register (CCR0), the
actual pulse length (TCLK cycles) is contained in the RAM words TA1PWM,
TA2PWM, and TA3PWM. The common update is made with ≈1 kHz.
The speed of the TRIAC-controlled motor is measured with the input signal at
input TA4 (CCI4A). The negative edges are captured and an interrupt is requested afterward.
On-Chip Peripherals
6-203
The Timer_A
The example uses the infrequent common update executed by the timer overflow handler. See Section 6.3.10.3 Update of the Capture/Compare Registersfor details.
; Definitions for the TRIAC control software
;
FLLMPY
.equ
122
; FLL multiplier for 4.0MHz
fper
.equ
16000
; 16.000kHz repetition rate
TCLK
.equ
FLLMPY*32768
; TCLK (Timer Clock) [Hz]
HLFPER
.equ
(TCLK/fper)/2
; Half period in Timer clocks
OP
.equ
4
; TRIAC gate pulse length
TAV0
.equ
0
; MSP430C33x Timer_A
0
; Fixed half period in CCR0
TIMACYC0 .equ
202h
; Timer Register Extensions:
TIMACYC1 .equ
204h
; Cycle counters
TIMACNT
.equ
206h
; Counter for half periods
FIRANGL
.equ
208h
; Half wave – conduction angle
FIRTIM
.equ
20Ah
; Fire time rel. to TIMACNT
TA1PWM
.equ
20Ch
; PWM cycle count C/C Block 1
TA2PWM
.equ
20Eh
;
C/C Block 2
TA3PWM
.equ
210h
;
C/C Block 3
STTRIAC
.equ
212h
; Control byte (0 = off) Status
FLAG
.equ
213h
; 1: update for PWM request
CPT4
.equ
214h
; Captured shaft value
STACK
.equ
600h
; Stack initialization address
PERIOD_VAR .equ
;
; RAM definitions
;
.text
; Start of ROM code
;
; Initialize the Timer_A: MCLK, Up/Down Mode. Enable INTRPT
; for C/C Blocks 0 and 4 and Timer Overflow TIMOV.
; Prepare Timer_A Output Units
;
INIT
6-204
MOV
#STACK,SP
; Initialize Stack Pointer SP
CALL
#INITSR
; Init. FLL and RAM
The Timer_A
MOV
#ISMCLK+CLR+TAIE,&TACTL ; Init. Timer
MOV
#HLFPER,&CCR0
MOV
#OMOO+CCIE+OUT,&CCTL0 ; Set TA0 high, Output
MOV
#OMTS,&CCTL1
; TA1: neg. PWM pulses
MOV
#OMTS,&CCTL2
; TA2: neg. PWM pulses
MOV
#OMTS,&CCTL3
; TA3: neg. PWM pulses
MOV
#CMNE+ISCCIA+SCS+CAP+CCIE,&CCTL4 ; –edge shaft
BIS.B
#TA4+TA3+TA2+TA1+TA0,&P3SEL ; Define I/Os
BIS.B
#P0IE0,&IE1
MOV.B
#CBMCLK+CBE,&CBCTL ; MCLK at XBUF pin
CLR
TIMACYC0
; Clear low cycle counter
CLR
TIMACYC1
; Clear high cycle counter
CLR
TIMACNT
; Clear half period counter
CLR.B
STTRIAC
; TRIAC off status (0)
MOV
#HLFPER/2,TA1PWM
; TA1: 0V
MOV
#HLFPER/2,TA2PWM
; TA2: 0V
MOV
#HLFPER/2,TA3PWM
; TA3: 0V
MOV.B
#1,FLAG
; Update PWM registers CCRx
BIS
#MUPD,&TACTL
; Start Timer_A (Up/Down)
; Half period to CCR0
; Enable P0.0 interrupt mains
;
EINT
MAINLOOP
; Enable interrupts
...
; Continue in mainloop
;
; Some TRIAC control examples:
; Start electric motor: checked result (half periods) in R5
; The result is the time difference from the zero crossing
; of the mains voltage (P0.0) to the first gate pulse
; (measured in Timer_A half periods)
;
MOV
R5,FIRANGL
MOV.B
#2,STTRIAC
...
; Delay (half per.) to FIRANGL
; Activate TRIAC control
; Continue in background
;
; The motor is running. A new calculation result is available
; in R5. It will be used with the next mains half wave
;
On-Chip Peripherals
6-205
The Timer_A
MOV
R5,FIRANGL
...
; Delay (half per.) to FIRANGL
; Continue in background
;
; Stop motor: switch off TRIAC control, TRIAC gate off
;
CLR.B
STTRIAC
; Disable TRIAC control
BIS
#OUT,CCTL0
; TA0 high, Output only Mode
...
; Continue with background
;
; Read the captured value of the tacho generator
;
MOV
CPT4,R6
...
; Control algorithm for speed
;
; Preparation for the new PWM values start. A table with
; valid values only is used: no check is necessary
;
MOV
ANGLE,R6
; Current phase angle
MOV
TABLE(R6),TA1PWM
; Ph1: add
MOV
TABLE+120(R6),TA2PWM ; Ph2: add 120 degrees
MOV
TABLE+240(R6),TA3PWM ; Ph3: add 240 degrees
BIS.B
#1,FLAG
...
TABLE
.word
0 degrees
; Initiate common update
; Continue in background
HLFPER/2,100,...
; sin 0 to sin 600
;
; Interrupt handler for CCR0: the Period Register.
; – The cycle counters and the half period counter are updated
; – The TRIAC control task is executed
;
TIMMOD0
ADD
#2*HLFPER,TIMACYC0 ; Add (fixed) period to
ADC
TIMACYC0
; Cycle counters
BIS
#1,TIMACNT
; Half period counter +1 (Down)
;
; Interrupt handler for the TRIAC control. Entry point also
; from the Timer Overflow handler
;
6-206
The Timer_A
TRIACC
STTAB
EINT
; Allow nested interrupts
PUSH
R5
; Save help register R5
MOV.B
STTRIAC,R5
; Status of TRIAC control
MOV
STTAB(R5),PC
; Branch to status handler
.word
STATE0
; Status 0: No TRIAC activity
.word
STATE0
; Status 2: activation possible
.word
STATE4
; Status 4: wait for gate pulse
.word
STATE6
; Status 6: wait for gate off
;
; TRIAC status 4: TRIAC gate is switched on for “OP” half
; periods after the value in FIRTIM is reached
;
STATE4
CMP
FIRTIM,TIMACNT
; TRIAC gate time reached?
JNE
STATE0
; No
BIC
#OUT,&CCTL0
; Yes, TRIAC gate on
ADD.B
#2,STTRIAC
; Next TRIAC status (6)
;
; TRIAC status 0: No activity. TRIAC is off always
;
STATE0
POP
R5
RETI
; Restore help register
; Return from interrupt
;
; TRIAC status 6: gate pulse is active. Check if it’s time
; to switch off the TRIAC gate.
;
STATE6
MOV
FIRTIM,R5
; Time TRIAC firing
ADD
#OP,R5
; Gate–on time (half periods)
CMP
R5,TIMACNT
; On–time terminated?
JLO
STATE0
; No
BIS
#OUT,&CCTL0
; Yes, TRIAC gate off
MOV.B
#2,STTRIAC
; TRIAC status 2:
JMP
STATE0
; Wait for next zero crossing
;
; Interrupt handler for C/C Blocks 1 to 4 and Timer Overflow
;
TIM_HND
ADD
&TAIV,PC
; Serve highest priority requ.
On-Chip Peripherals
6-207
The Timer_A
RETI
; No interrupt pending
RETI
; C/C Block 1: INTRPT off
RETI
; C/C Block 2: INTRPT off
RETI
; C/C Block 3: INTRPT off
JMP
TIMMOD4
; C/C Block 4: Speed measurement
;
; The Timer Overflow interrupt handler:
; – Updates the PWM registers if necessary: FLAG.0 = 1
; – The TRIAC control task is executed
;
TIMOV
INC
TIMACNT
; Incr. period counter (UP)
BIT.B
#1,FLAG
; Update necessary?
JZ
TRIACC
; No, to TRIAC control task
MOV
TA1PWM,&CCR1
; Yes update C/C Blocks
MOV
TA2PWM,&CCR2
MOV
TA3PWM,&CCR3
BIC.B
#1,FLAG
; Clear update flag
JMP
TRIACC
; To TRIAC control task
;
; C/C Block 4 captures the revolutions of the motor. Dependent
; on the count direction of TAR, the captured TAR value in
; CCR4 is added or subtracted. CPT4 contains the 16–bit value
; of the captured negative edge of the signal at TA4.
;
TIMMOD4
MOV
TIMACYC0,CPT4
; Save cycle counter
BIT
#1,TIMACNT
; Direction UP?
JNZ
T40
; No, DOWN (1)
;
;
ADD
&CCR4,CPT4
RETI
; Build time of captured event
; Back to main program
;
T40
Direction is UP:
; Direction is DOWN:
SUB
&CCR4,CPT4
; Build time of captured event
RETI
;
; P0.0 Handler: the mains voltage causes interrupt with each
; zero crossing. The TRIAC gate is switched off first, to
6-208
The Timer_A
; avoid the ignition for the actual half wave.
; Hardware debounce is necessary for the mains signal!
;
P00_HNDLR BIS
#OUT,&CCTL0
EINT
XOR.B
; Switch off TRIAC gate
; Allow nested interrupts
#1,&P0IES
; Change intrpt edge of P0.0
;
; If STTRIAC is not 0 ( 0 = inactivity) then the next TRIAC
; gate firing is prepared: STTRIAC is set to 4
;
TST.B
STTRIAC
; TRIAC control active?
JZ
P00
; STTRIAC = 0: no activity
MOV.B
#4,STTRIAC
; Yes, STTRIAC > 0
;
; The TRIAC firing time is calculated: TIMACNT + FIRANGL
; (current time + angle) in half periods
;
P00
MOV
TIMACNT,FIRTIM
; Half period counter
ADD
FIRANGL,FIRTIM
; TIMACNT + delay –> FIRTIM
.sect
”TIMVEC”,0FFF0h
; Timer_A Interrupt Vectors
.word
TIM_HND
; Vector for C/C Blocks 1..4
.word
TIMMOD0
; Vector for C/C Block 0
.sect
”P00VEC”,0FFFAh
; P0.0 Vector
.word
P00_HNDLR
.sect
”INITVEC”,0FFFEh ; Reset Vector
.word
INIT
RETI
;
The TRIAC control example results in a nominal CPU loading uCPU (ranging
from 0 to 1) for the active TRIAC control (STTRIAC = 4):
CCR0 — repetition rate 16 kHz
TIMOV — repetition rate 16 kHz
CCR4 — repetition rate 0.4 kHz
P0.0 — repetition rate 100 Hz
Update — 1 kHz (TIMOV)
35cycles for the task, 11 cycles overhead
34 cycles for the update, 14 cycles overhead
18 cycles for the update, 16 cycles overhead
17 cycles for the task, 11 cycles overhead
22 cycles for the task, 0 cycles overhead
On-Chip Peripherals
46 cycles
48 cycles
34 cycles
28 cycles
22 cycles
6-209
The Timer_A
u
CPU
=
16.0 × 10 3 × (46 + 48 ) + 0.4 × 10 3 × 34 + 100 × 28 + 1.0 × 10 3 × 22
= 0.386
6
4.0 × 10
This results in a CPU loading of approximate 39% due to the static TRIAC control. The necessary tasks for the update of the half period counter and the cycle
counters are included. The PWM activities alone load the CPU with less than
1% this way (fupdate = 1 kHz).
6.3.10.6 RF Timing Generation
The repetition rate of the up/down mode in use must be a multiple of the data
change frequency. The timing is now made by the interrupts of the period register and of the timer overflow. This allows the output of biphase code modulation
and biphase space modulation with a 19.2 kHz repetition rate. The three different modulation methods and their conversion subroutines were discussed in
detail in the section Software Examples for the Continuous Mode. The software shown in this section may be used with the following, simple modifications:
1) The repetition frequency is also chosen to 19.2 kHz, but the equally
spaced TIMOV interrupt allows a 38.4 kHz time frame.
2) The output handler for the 128-bit buffer is executed by the interrupt handlers of the period register and the timer overflow (TIMOV) to get the
doubled bit rate (as shown for the TRIAC control example in Section
6.3.10.5).
3) The output unit 0 uses the output only mode (exactly as shown for the
TRIAC control example in Section 6.3.10.5). The interrupt handler of the
period register CCR0 sets and resets the output TA0 by software.
Figure 6–51 shows the biphase code modulation for an input byte containing
the value 96h. The other two modulation modes work the same way. The timing of the interrupts is shown below:
6-210
The Timer_A
0
1
1
0
1
0
0
1
Information 096h
Bi-Phase Code
RF Off
RF On
CCR0
Timer Register TAR
0
Direction Bit
(TIMACNT.0)
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Bit Length
Interrupts
Time
TIMOV
EQU0
Bit Length = 1/19200 s
EQU0
Figure 6–51. Biphase Code Modulation With the Up/Down Mode
6.3.10.7 Comparison With the Up/Down Mode
Comparison with the up/down mode is nearly impossible due to the uncertainty of the direction of the actual count. If comparison — which means precise
interrupts or switching of the corresponding output unit — is important, then
the up mode or the continuous mode should be used. With the up/down mode
— and its normally high repetition rates — only interrupt-driven software
switching is possible. The TRIAC Control example shows a method to use the
interrupts of the period register (CCR0) and the timer overflow (TIMOV) for the
control of outputs.
6.3.10.8 Capturing with the Up/Down Mode
Capturing of events is not as easy as with the continuous mode or the up mode.
The reason is the changing count direction of the timer register (TAR) in the
middle of the timer period. Due to the interrupt latency time, tIL, an uncertainty
zone exists at the two points where the timer register changes its direction.
This uncertainty zone has the length 2 × tIL. The interrupt latency time, tIL, depends on the actual software — it ranges from 6 MCLK cycles to the longest
program sequence with disabled interrupt. See also figure 6–52.
To get the time of an event with least calculation effort, the method shown in
figure 6–52 is used:
On-Chip Peripherals
6-211
The Timer_A
- The interrupt handler of the period register CCR0 adds the length of a peri-
od to the cycle counters TIMACYCx. This is done in such a way, that these
counters point forward to the next time point in which the timer register
(TAR) reaches 0 again (TIMOV interrupt).
- The interrupt handler of the period register also sets the bit 0 (LSB) of the
half period counter TIMACNT. This bit is used as the direction bit and indicates with this 1 the downward count direction.
- The interrupt handler of the timer overflow (TIMOV) increments the bit 0
(LSB) of the half period counter TIMACNT and sets it to 0 (upward count
direction).
The setting (CCR0) and incrementing (TIMOV) of the direction bit
(TIMACNT.0) results in an incrementing that is self synchronizing.
To calculate the time of an event at terminal TAx, it is only necessary to read
the actual direction bit:
- If the direction bit TIMACNT.0 is 0 (upward count), then the captured time
(0 to nCCR0) in the capture/compare register x is added to the cycle count
in TIMACYC0. The captured event occurred after the time stored in TIMACYC0.
- If the direction bit TIMACNT.0 is 1 (downward count), then the captured
time (0 to nCCR0) in the capture/compare register x is subtracted from the
cycle count in TIMACYC0. The captured event occurred before the time
stored in TIMACYC0.
The sections Digital Motor Control and TRIAC Control also contain examples
for the use of capturing with the up/down mode.
6-212
The Timer_A
TIMACYC0
2n × nCCR0
2(n + 1) × nCCR0
2(n + 2) × nCCR0
TIMACNT
2n
2n + 1
2n + 2
2n + 3
2n + 4
Direction Bit
Up
Down
Up
Down
Up
Time Register TAR
Uncertainty Zone
nCCR0
Event 1
nCCRx1
Event 2
nCCRx2
0h
Capt 1
Interrupts
thlfper
Capt 2
TIMOV
EQU0
CCR0 Handler Writes
2(n + 1) × nCCR0 to TIMACYC0;
Incr. TIMACNT (Dir = Down)
Capt 1 = 2(n + 1) × nCCR0 – nCCRx1
Capt 2 = 2(n + 1) × nCCR0 + nCCRx2
Subtract CCRx
EQU0
CCR0 Handler Writes
2(n + 2) × nCCR0 to TIMACYC0;
Incr. TIMACNT (Dir = Down)
Time
Add CCRx
TIMACYC0 Points to This Time;
Incr. TIMACNT (Dir = Up)
Figure 6–52. Capturing With the Up/Down Mode
Figure 6–53 illustrates the hardware and RAM registers used with the up/down
mode for capturing. The RAM words TIM31 and TIM30 store the time of the
last captured event. Figure 6–53 refers to the capture/compare block 3 of the
following example.
On-Chip Peripherals
6-213
The Timer_A
15
Half Period Counter
TIMACNT
0
Dir
Timer Overflow Increment
Set
15
0
Period Register CCR0
Add Period (Software)
EQU0
31
Cycle Counters
0
15
TIMACYC1/TIMACYC0
Direction Bit
Compare
0
Timer Clock
Time Register TAR
(n × Period)
0 = Add, 1 = Subtract
Capture
15
0
CCR3
Software Add/Subtract
31
0
Captured Value
TIM31/TIM30
32-Bit Captured Value
Timer_A Hardware
Figure 6–53. Capture Mode With the Up/Down Mode (Capture/Compare Block 3)
Figure 6–54 illustrates five tasks. They are exactly the same tasks that are
used for the up mode in the section Software Examples for the Up Mode (only
the capture/compare block 3 part — that captures the leading edge of an input
signal — is extended to 32 bits). This way a comparison is possible between
the up mode and the up/down mode. The tasks are defined as follows:
- Capture/Compare Block 0 — outputs a symmetrical 8.484 kHz signal.
The edges contain the information for the period generated by the period
register CCR0. This signal is always available for external peripherals (the
PWM signals of the capture/compare blocks disappear for pulse widths of
0% and 100%).
- Capture/Compare Block 1 — generates a positive PWM signal with the
half period defined by the period register CCR0. The pulse length is stored
in the RAM word TA1PWM; it ranges from 1 to HLFPER.
- Capture/Compare Block 2 — the length, ∆t2, of the high part of the input
signal at the CCI2A input terminal is measured and stored in the RAM word
PP2. The captured time of the leading edge is stored in the RAM word
TIM2. The maximum repetition rate used is 2 kHz.
- Capture/Compare Block 3 — the event time of the leading edge of the
signal at the CCI3A input terminal is captured. The last captured value
(TCLK cycles, 32 bits length) is stored in the RAM words TIM30 and
TIM31. The maximum repetition rate used is 3 kHz. See also figure 6–53.
6-214
The Timer_A
- Capture/Compare Block 4 — generates a negative PWM signal with the
period defined by the period register. The pulse length is stored in the RAM
word TA4PWM; it ranges from 0 to HLFPER.
For the example, 3.801 MHz is used. The resolution for the PWM is 224 steps
due to the repetition frequency of 16.969 kHz (3.801 MHz/16.969 kHz = 224).
The Infrequent Individual Update Mode is used. See Section 6.3.10.3 for details.
The maximum input frequencies for capturing purposes mentioned above are
used for the overhead calculation only. The limits of the Timer_A hardware allow the capture much of higher input frequencies.
Figure 6–54 illustrates the four tasks described above — they are not shown
to scale:
On-Chip Peripherals
6-215
The Timer_A
TIMACYC0
2n × nCCR0
Direction Bit
Timer Register
(2n + 2) × nCCR0
1
0
(2n + 4) × nCCR0
0
1
0
thlfper
CCR0
CCR4
CCR1
0h
TA1 Output
tpw1
tpw4
TA4 Output
∆ t2
Time Measurement
at CCI2A
Captured Edge t3
Capturing of Leading
Edges at CCI3A
Doubled Period at
TA0
Capt 20
Interrupts
TIMOV
EQU0
Capt 3
TIMOV
Capt 21
EQU0
TIMOV
Time
Figure 6–54. PWM Generation and Capturing With the Up/Down Mode
Example 6–51. Timer_A Used for PWM Generation and Capturing
; Timer_A used for PWM–generation and Capturing.
;
FLLMPY
.equ
116
; fMCLK = 3.801MHz
fper
.equ
16969
; 16.969kHz repetition rate
TCLK
.equ
FLLMPY*32768
; TCLK: FLLMPY x fcrystal
HLFPER
.equ
(TCLK/fper)/2
; fper = 16.969kHz
TAV0
.equ
0
; MSP430C33x version
0
; Fixed period
PERIOD_VAR .equ
6-216
The Timer_A
;
; RAM Definitions
;
TA1PWM
.equ
202h
; PWM pulse length TA1
TIM2
.equ
204h
; Time of leading edge at CCI2A
PP2
.equ
206h
; Length of high part at CCI2A
TIM30
.equ
208h
; Time of leading edge
LSBs
TIM31
.equ
20Ah
; at CCI3A
MSBs
TA4PWM
.equ
20Ch
; PWM pulse length for TA4
TIMACYC0 .equ
20Eh
; Cycle counter low
TIMACYC1 .equ
210h
; Cycle counter high
TIMACNT
.equ
212h
; Half period counter. Bit0 = Dir
FLAG
.equ
214h
; Update information
STACK
.equ
600h
; Stack initialization address
.text
INIT
; Software start address
MOV
#STACK,SP
; Initialize Stack Pointer
CALL
#INITSR
; Init. FLL and RAM
;
; Initialize the Timer_A: MCLK, Up/Down Mode, INTRPTs on
; for TIMOV, C/C blocks 0, 2, and 3
;
MOV
#ISMCLK+CLR+TAIE,&TACTL ; Define Timer_A
MOV
#HLFPER,&CCR0
; Define half period
MOV
#OMT+CCIE,&CCTL0
; Toggle TA0, INTRPT on
MOV
#OMTR,&CCTL1
; Toggle/Reset Mode
MOV
#CMBE+ISCCIA+SCS+CAP+CCIE,&CCTL2 ; Both edges
MOV
#CMPE+ISCCIA+SCS+CAP+CCIE,&CCTL3 ; Pos. edge
MOV
#OMTS,&CCTL4
MOV.B
#TA4+TA3+TA2+TA1+TA0,&P3SEL ; Define I/Os
MOV.B
#CBACLK+CBE,&CBCTL ; Output ACLK at XBUF pin
CLR
TIMACYC0
; Clear low cycle counter
CLR
TIMACYC1
; Clear high cycle counter
CLR
TIMACNT
; Clear half period counter
MOV
#1,TA1PWM
; TA1 pulse length = 1
MOV
#0,TA4PWM
; TA4 pulse length = 0
; Toggle/Set Mode
;
On-Chip Peripherals
6-217
The Timer_A
MOV
#6,FLAG
; Actualize PWMs immed.
BIS
#MUPD,&TACTL
; Start Timer in Up/Down Mode
EINT
; Enable interrupts
MAINLOOP ...
; Continue in background
; Calculations for the new PWM values start.
; The new result in R6 is written to TA1PWM after completion.
; The PWM range is from 1 to HLFPER–1: no checks necessary
;
...
; Calculate TA1 value to R6
MOV
R6,TA1PWM
BIS
#2,FLAG
...
; Actualize pulse length
; Initiate update
; Continue in background
;
; The new result in R6 is written to TA4PWM after completion.
; The PWM range is from 0% to 100%: check necessary
;
...
; Calculate TA4 value to R6
CHCK_PWM_RNG
R6
; Check and correct result
MOV
R6,TA4PWM
; Actualize pulse length
BIS
#4,FLAG
; Initiate update
...
; Continue in background
;
; Use the measured high part in PP2 for calculations
;
MOV
PP2,R7
...
; Read measured pulse length
; Control algorithm
;
; Use the captured 32 bit value in TIM31/TIM30 for calculations
;
MOV
TIM31,R7
MOV
TIM30,R6
...
; Captured MSBs
; Captured LSBs
; Control algorithm
;
; Interrupt handler for the Period Register CCR0. 8.484kHz
; are output at TA0 for synchronization.
;
6-218
The Timer_A
TIMMOD0
ADD
#2*HLFPER,TIMACYC0 ; Actualize cycle counters
ADC
TIMACYC1
BIS
#1,TIMACNT
RETI
; Incr. half period counter
; Dir = Down
;
; Interrupt handlers for Capture/Compare Blocks 1 to 4.
; The interrupt flags CCIFGx are reset by the reading
; of the Timer Vector Register TAIV
;
TIM_HND
ADD
&TAIV,PC
; Add Jump table offset
RETI
; Vector 0: No interrupt pending
RETI
; C/C Block 1: INTRPT disabled
JMP
TIMMOD2
; C/C Block 2: Capt. both edges
JMP
TIMMOD3
; C/C Block 3: Capt. pos. edge
RETI
; C/C Block 4: INTRPT disabled
;
; TIMOV Interrupt: dependent on FLAG the CCR1 and CCR4
; PWM registers are updated.
;
TIMOV
INC
TIMACNT
; Incr. half period cnt (Down)
ADD
FLAG,PC
; FLAG with update info
RETI
P4
; 0: Nothing to do
JMP
P1
; 2: Update CCR1
JMP
P4
; 4: Update CCR4
MOV
TA1PWM,&CCR1
; 6: Update CCR1 and CCR4
MOV
TA4PWM,&CCR4
; 4:
CLR
FLAG
RETI
P1
MOV
TA1PWM,&CCR1
CLR
FLAG
; 2: Update CCR1
RETI
;
; The high part of the CCI2A input signal is measured.
; The result is stored in PP2. The complete handler is time
; critical: nested interrupts cannot be used.
;
On-Chip Peripherals
6-219
The Timer_A
TIMMOD2
BIT
#CCI,&CCTL2
; Input signal high?
JZ
TM21
; No, time for calculation
MOV
TIMACYC0,TIM2
; Build time of event
BIT
#1,TIMACNT
; Pos. edge: count direction Up?
JNZ
T20
; No, Down (1)
;
Direction is Up
ADD
&CCR2,TIM2
; Build time of pos. edge in TIM2
RETI
;
T20
Direction is Down
SUB
&CCR2,TIM2
; Build time of pos. edge in TIM2
RETI
; Neg. edge: High part is calc.
TM21
MOV
TIMACYC0,PP2
; Event time of trailing edge
BIT
#1,TIMACNT
; Direction Up?
JNZ
T22
; No, Down (1)
;
Direction is Up
ADD
&CCR2,PP2
; Time of trailing edge in PP2
JMP
T23
; To calculation of high part
;
T22
T23
; Direction is Down
SUB
&CCR2,PP2
SUB
TIM2,PP2
RETI
; Time of trailing edge in PP2
; Subtr. time of leading edge
; Length of high part in PP2
;
; Capture/Compare Block 3 captures the time of leading edges
; at CCI3A. TIM3x stores the 32 bit time of the actual edge
;
TIMMOD3
MOV
TIMACYC0,TIM30
MOV
TIMACYC1,TIM31
BIT
#1,TIMACNT
; Count direction Up?
JNZ
T30
; No, Down (1)
ADD
&CCR3,TIM30
; Time of pos. edge in TIM3x
ADC
TIM31
;
; Store cycle counters (32 bit)
Direction is Up
RETI
;
T30
6-220
; Direction is Down
SUB
&CCR3,TIM30
; Time of pos. edge in TIM3x
The Timer_A
SBC
TIM31
RETI
;
.sect
”TIMVEC”,0FFF0h
; Timer_A Interrupt Vectors
.word
TIM_HND
; C/C Blocks 1..4 Vector
.word
TIMMOD0
; Vector for C/C Block 0
.sect
”INITVEC”,0FFFEh
; Reset Vector
.word
INIT
The above example results in a maximum (worst case) CPU loading uCPU
(ranging from 0 to 1) by the Timer_A activities:
CCR0 — repetition rate 16.969 kHz
CCR1 — update rate 1 kHz
CCR2 — rep. rate max. 2 kHz
CCR3 — rep. rate max. 3.0kHz
CCR4 — update rate 1.0kHz
TIMOV — rep. rate 16.969kHz
uCPU
13 cycles for the task, 11 cycles overhead
12 cycles for the update, 16 cycles overhead
64 cycles for the update, 32 cycles overhead
30 cycles for the update, 16 cycles overhead
12 cycles for the update, 0 cycles overhead
7 cycles for the task, 14 cycles overhead
24 cycles
28 cycles
96 cycles
46 cycles
12 cycles
21 cycles
16.969 × 10 3 × 45 + 1.0 × 10 3 × 40 + 2.0 × 10 3 × 96 + 3.0 × 10 3 × 46
=
= 0.298
3.801 × 10 6
This results in a worst case CPU loading of approximate 29% due to the Timer_A activities.
6.3.10.9 Conclusion
This section demonstrated the possibilities of the Timer_A running in the up/
down mode. Despite the dominance of the period register CCR0 and its changing direction during a period, it is possible to capture signals, compare time intervals, and create timings in a real-time environment — all this in parallel with
the pulse width modulation generated with the up/down mode.
On-Chip Peripherals
6-221
The Hardware Multiplier
6.4 The Hardware Multiplier
The 16 × 16-bit hardware multiplier of the MSP430 family is detailed in the following sections. Function and modes are discussed, and proven application
examples are given for this fast and versatile peripheral. Also shown is a comparison of the speed of solutions using this peripheral compared to pure software solutions. The hardware multiplier can also execute the Signed Multiply
and Accumulate function. The register to be used for the Operand 1 has the
address 136h. The function is the same as for the Signed Multiply function, except that the new product is added to the accumulated sum in the SumHi/SumLo registers. The SumExt register indicates the sign of the accumulated sum.
It is the user’s responsibilty to ensure that no overflow can occur (by worstcase calculation of the factors used).
6.4.1
Function of the Hardware Multiplier
The hardware multiplier allows three different multiply operations (modes):
- The multiplication for unsigned 16-bit and 8-bit operands
- The multiplication for signed 16-bit and 8-bit operands
- The multiply-and-accumulate function (MAC) for unsigned 16-bit and 8-bit
operands
Any mixture of operand lengths (16 bits and 8 bits) is possible. If assisting software is used, other operations are also possible — the signed Multiply-andAccumulate function, for example.
6-222
The Hardware Multiplier
15
rw
0
MPY 130h
Operand 1
(Address Defines Operation)
15
MPYS 132h
rw
0
15
rw
0
Operand 2 138h
Operand 1
Mode
MAC 134h
16 × 16 Multiplier
Accessible Register
0
31
Product Register
0000
32-Bit Adder
MPY
MPY, MPYS
MPYS MAC
32-Bit Multiplexer
Multiplexer
Mode
MAC
Mode
Sum Ext 13Eh
15
MPY
MPYS
MAC
r
C
0
S
15
Sum Hi 13Ch
rw
Sum Lo 013Ah
0
15
rw
0
0000h
S = 0 0000h
S = 1 FFFFh
C = 0 0000h
C = 1 0001h
Figure 6–55. Block Diagram of the MSP430 16 × 16-Bit Hardware Multiplier
Figure 6–55 shows the hardware modules of the MSP430 multiplier. The accessible registers are explained in the following sections. The hardware of Figure 6–55 does not precisely depict the actual circuitry — it illustrates how the
programmer sees the hardware multiplier.
6.4.1.1
Hardware and Register
The Hardware Multiplier is not part of the MSP430 CPU — it is a peripheral like
the Timer_A or the Basic Timer. This means its activities do not interfere with
the CPU activities. The multiplier registers are normal peripheral registers that
are loaded and read with the CPU instructions. The registers that the programmer can access are explained in this section.
The hardware multiplier registers are not affected by POR or PUC.
With the exception of the SumExt register, all other registers can be read from
and written to.
On-Chip Peripherals
6-223
The Hardware Multiplier
Definitions for the Hardware Multiplier appear in Section 6.4.3.
ROM
RAM
Hardware
MPYer
Other
16-Bit
Peripherals
Address
Bus 16-Bits
Test
MSP430
CPU
Including
16 Registers
JTAG
Data Bus
16-Bits
Figure 6–56. The Internal Connection of the MSP430 16 × 16-Bit Hardware Multiplier
6.4.1.2
The Operand1 Registers
The MSP430 hardware multiplier mode to be used is selected by the hardware
address where the Operand 1 is written:
- Address 130h — the unsigned multiplication is executed
- Address 132h — the signed multiplication is executed
- Address 134h — the unsigned Multiply–and–Accumulate function is exe-
cuted
Only the address used for the operand1 determines which operation the multiplier will execute (after the modification of the operand2). No operation is
started with the modification of the operand register 1 alone.
6-224
The Hardware Multiplier
Example 6–52. Multiply Unsigned
A MPY (multiply unsigned) operation is defined and started. The two operands
reside in R14 and R15.
MOV
R15,&130h
; Define MPY operation
MOV
R14,&138h
; Start MPY with operand 2
...
6.4.1.3
; Product in SumHi|SumLo
The Operand2 Register
The operand register 2 (at address 138h) is common for all three multiplier
modes. The modification of this register (normally with a MOV instruction)
starts the selected multiplication of the two operands contained in the operand
1 and 2 registers. The result is written immediately into the three hardware registers: SumExt, SumHi, and SumLo. The result can be accessed with the next
instruction unless the indirect addressing modes are used for the source addressing.
6.4.1.4
The SumLo Register
This 16-bit register contains the lower 16 bits of the calculated product or
summed result. All instructions may be used to access or modify the SumLo
register. The high byte cannot be accessed with byte instructions.
6.4.1.5
The SumHi Register
This 16-bit register contains — dependent on the previously executed operation — the following information:
- MPY Unsigned Multiply — the most significant word of the calculated
product.
- MPYS Signed Multiply — the most significant word including the sign of
the calculated product. Two’s complement notation is used for the product.
- MAC Unsigned Multiply-and-Accumulate — the most significant word
of the calculated sum.
All instructions may be used with the SumHi register. The high byte cannot be
accessed with byte instructions.
On-Chip Peripherals
6-225
The Hardware Multiplier
6.4.1.6
The SumExt Register
The SumExt register (sum extension) eases the use of calculations with results exceeding the range of 32 bits. This read only register contains the information that is needed for the most significant parts of the result — the information for the bits 32 and higher. The content of the Sum Extension Register is
different for the three multiplication modes:
- MPY Unsigned Multiply — SumExt always contains 0. No carry is pos-
sible and the maximum result possible is: 0FFFFh × 0FFFFh =
0FFFE0001h.
- MPYS Signed Multiply — SumExt contains the extended sign of the
32-bit result (bit 31). This means that if the result of the multiplication is
negative (MSB = 1), then SumExt contains 0FFFFh. If the result is positive
(MSB = 0), then SumExt contains 0000h.
- MAC Unsigned Multiply-and-Accumulate — SumExt contains the carry
of the accumulate operation. SumExt contains 0001 if a carry occurred
during the accumulation of the new product. SumExt contains 0 if no carry
occurred.
The sum extension register improves multiple word operations. No time wasting and ROM–space wasting conditional jumps are necessary — ordinary
adds are used instead.
The new product of a MPYS operation (multiplicands in R14 and R15) is added
to a signed 64-bit result located in the RAM words RESULT to RESULT+6:
Example 6–53. 64-Bit Result
MOV
R15,&MPYS
; First operand
MOV
R14,&OP2
; Start MPYS with operand 2
ADD
SumLo,RESULT
; Lower 16 bits of result
ADDC
SumHi,RESULT+2
; Upper 16 bits
ADDC
SumExt,RESULT+4
; Result bits 32 to 47
ADDC
SumExt,RESULT+6
; Result bits 48 to 63
Note:
It is strongly recommended the MACROs defined in section Assembler
.MACROS be used instead of the method shown above. The code above is
much less descriptive than the MACROs, using known abbreviations like
MPYU, MPYS and MACU.
With the software shown above, no checks and conditional jumps are necessary. The result always contains the signed, accumulated sum automatically.
6-226
The Hardware Multiplier
6.4.1.7
Rules for the Hardware Multiplier
- The hardware multiplier is a word module. The hardware registers can be
addressed in word mode or in byte mode, but the byte mode can address
the lower bytes only (the upper byte cannot be addressed).
- The operand registers of the hardware multiplier (addresses 0130h,
0132h, 0134h and 0138h) behave like the CPU working registers R0 to
R15 if modified in byte mode — the upper byte is cleared in this case. This
allows 8-bit and 16-bit multiplications in any mixture. See the examples in
Section 6.4.2.4.
- The foating point package (FPP) version 4 uses the hardware multiplier
if the variable HW_MPY is defined as 1:
HW_MPY
.equ
1
See chapter 5.6 for details.
- If the result of a hardware multiplier operation is addressed with indirect
mode or indirect-autoincrement mode, a NOP instruction is necessary after the multiplication to allow the completion of the multiplication. See the
examples in Section 6.4.3.1.
6.4.2
Multiplication Modes
Three different multiplication modes are available. They are explained in the
following sections.
6.4.2.1
Unsigned Multiply
The two operands written to the operand registers 1 and 2 are treated as unsigned numbers with:
H
00000h
as the smallest number
H
0FFFFh
as the largest number.
The maximum possible result is reached for the operands:
0FFFFh × 0FFFFh = 0FFFE0001h
No carry is possible, the SumExt register always contains 0. Table 6–27 shows
the products for some special multiplicands.
On-Chip Peripherals
6-227
The Hardware Multiplier
Table 6–27. Results With the Unsigned Multiply Mode
6.4.2.2
OPERANDS
SumExt
SumHi
SumLo
0000 × 0000
0000
0000
0000
0001 × 0001
0000
0000
0001
7FFF × 7FFF
0000
3FFF
0001
FFFF × FFFF
0000
FFFE
0001
7FFF × FFFF
0000
7FFE
8001
8000 × 7FFF
0000
3FFF
8000
8000 × FFFF
0000
7FFF
8000
8000 × 8000
0000
4000
0000
Signed Multiply
The two operands written to the operand registers 1 and 2 are treated as
signed two’s complement numbers with:
H
08000h
as the most negative number (–32768)
H
07FFFh
as the most positive number (+32767)
The SumExt register contains the extended sign of the calculated result:
H
SumExt = 00000h:
the result is positive
H
SumExt = 0FFFFh:
the result is negative
Table 6–28. Results With the Signed Multiply Mode
6-228
OPERANDS
SumExt
SumHi
SumLo
0000 × 0000
0000
0000
0000
0001 × 0001
0000
0000
0001
7FFF × 7FFF
0000
3FFF
0001
FFFF × FFFF
0000
0000
0001
7FFF × FFFF
FFFF
FFFF
8001
8000 × 7FFF
FFFF
C000
8000
8000 × FFFF
0000
0000
8000
8000 × 8000
0000
4000
0000
The Hardware Multiplier
6.4.2.3
Multiply-and-Accumulate (MAC)
The two operands written to the operand registers 1 and 2 are treated as unsigned numbers (0h to 0FFFFh). The maximum possible result is reached for
the input operands:
0FFFFh × 0FFFFh = 0FFFE0001h
This result is added to the previous content of the two sum registers (SumLo
and SumHi). If a carry occurs during this operation, the SumExt register contains 1, otherwise it is cleared.
H
SumExt = 00000h:
no carry occurred during the accumulation
H
SumExt = 00001h:
a carry occurred during the accumulation
For the results of Table 6–29, it is assumed that SumHi and SumLo contain the
accumulated content C000,0000 before the execution of each of the shown
examples. See Table 6–27 for the results of an unsigned multiplication without
accumulation.
Table 6–29. Results With the Unsigned Multiply-and-Accumulate Mode
6.4.2.4
OPERANDS
SumExt
SumHi
SumLo
0000 × 0000
0000
C000
0000
0001 × 0001
0000
C000
0001
7FFF × 7FFF
0000
FFFF
0001
FFFF × FFFF
0001
BFFE
0001
7FFF × FFFF
0001
3FFE
8001
8000 × 7FFF
0000
FFFF
8000
8000 × FFFF
0001
3FFF
8000
8000 × 8000
0001
0000
0000
Word Lengths for the Multiplication
The MSP430 hardware multiplier allows all combinations that are possible
with 8-bit and 16-bit operands. The examples given in Section 6.4.3 for 8-bit
and 16-bit operands may be adapted to mixed length operands.
It must be taken into account that the input operand registers operand1 and
operand2 behave like CPU registers — the high register byte is cleared if the
register is modified by a byte instruction.
This eases the use with 8-bit operands. Examples for the 8-bit operand are given for all three modes of the hardware multiplier.
On-Chip Peripherals
6-229
The Hardware Multiplier
; Use the 8–bit operand in R5 for an unsigned multiply.
;
MOV.B
R5,&MPY
; The high byte is cleared
; Use an 8–bit operand for a signed multiply.
;
MOV.B
R5,&MPYS
; The high byte is cleared
SXT
&MPYS
; Extend sign to high byte
; Use an 8–bit operand for a multiply–and–accumulate.
;
MOV.B
R5,&MAC
; The high byte is cleared
Operand2 is loaded as shown above for operand1. This allows all four possible
combinations for the input operands:
16 × 16
8 × 16
16 × 8
8×8
The MACROS that can be modified are shown in the next section.
6.4.3
Programming the Hardware Multiplier
At the beginning, the registers of the hardware multiplier are defined in accordance with the MSP430 Family Architecture Guide and Module Library. This
avoids confusion.
; MSP430 Hardware Multiplier Definitions
;
MPY
.equ
130h
; Multiply unsigned
MPYS
.equ
132h
; Multiply signed
MAC
.equ
134
; Multiply–and–Accumulate
OP2
.equ
138h
; Operand 2 Register
SumLo
.equ
013Ah
; Result Register LSBs 15..0
SumHi
.equ
013Ch
; Result Register MSBs 32..16
SumExt
.equ
013Eh
; Sum Extension Register 47..33
;
6-230
The Hardware Multiplier
6.4.3.1
Assembler .MACROS
Due to the MACRO construction of the multiply instructions for source and destination (normally two MOV instructions form the multiplication sequence), all
seven addressing modes are possible. If the register indirect or register indirect with autoincrement addressing modes are used to address the result, then
a NOP is necessary after the .MACRO call to allow the completion of the multiplication. The named addressing modes access the source operand so fast,
that they do not allow the completion of the multiplication.
Examples are given with each .MACRO definition. The execution cycles depend on the addressing modes used for the multiplier and the multiplicand.
The given MACROs can easily be changed to subroutines. An example is given for the unsigned multiplication:
; Subroutine Definition for the unsigned multiplication
; 16 x 16 bits. The two operands are contained in R4 and R5
;
MPYU_16
MPYU16
R4,R5
RET
; Unsigned MPY 16 x 16
; Result in SumHi|SumLo
;
6.4.3.2
Unsigned Multiplication 16 x 16-bits
; Macro Definition for the unsigned multiplication 16 x 16 bits
;
MPYU16
.MACRO
arg1,arg2
MOV
arg1,&0130h
MOV
arg2,&0138h
.ENDM
; Unsigned MPY 16x16
; Result in SumHi|SumLo
;
; Multiply the contents of the two registers R4 and R5
;
MPYU16
R4,R5
; MPY R4 and R5 unsigned
MOV
SumLo,R6
; LSBs of result to R6
MOV
SumHi,R7
; MSBs of result to R7
...
; Continue
;
; Multiply the contents located in a table, R6 points to
; The result is addressed in indirect mode: a NOP is necessary
On-Chip Peripherals
6-231
The Hardware Multiplier
; to allow the completion of the multiplication
;
MOV
#SumLo,R5
; Pointer to LSBs of result
MPYU16
@R6+,@R6
; MPYU the table contents
NOP
; Allow completion of MPYU16
MOV
@R5+,R7
; Fetch LSBs of result
MOV
@R5,R8
; Fetch MSBs of result
...
; Continue
;
; Macro Definition for the unsigned multiplication and
; accumulation 16 x 16 bits
;
MACU16
.MACRO
arg1,arg2
; Unsigned MAC 16x16
MOV
arg1,&0134h
; Carry in SumExt
MOV
arg2,&0138h
.ENDM
; Result in SumExt|SumHi|SumLo
;
; Multiply–and–accumulate the contents of registers R5 and R6
; to the previous content (IROP1 x IROP2L) of the Sum registers
;
MPYU16
IROP1,IROP2L
; Initialize Sum registers
MACU16
R5,R6
; Add (R5 x R6) to result
ADD
&SumExt,RAM
; Add carry to RAM extension
...
6.4.3.3
; Continue
Signed Multiplication 16 × 16-bit
The following software examples perform signed 16 × 16-bit multiplications
(MPYS16) or signed Multiplication and Accumulation (MACS16).
The SumExt register contains the extended sign of the result in SumHi and
SumLo: 0000h (positive result) or 0FFFFh (negative result).
; Macro Definition for the signed multiplication 16 x 16 bits
;
MPYS16
6-232
.MACRO
arg1,arg2
MOV
arg1,&0132h
MOV
arg2,&0138h
; Signed MPY 16x16 bits
The Hardware Multiplier
.ENDM
; Result in SumExt|SumHi|SumLo
;
; Multiply the contents of two registers R4 and R5
;
MPYS16
R4,R5
; MPY signed R4 and R5
MOV
&SumLo,R6
; LSBs of result to R6
MOV
&SumHi,R7
; MSBs of result to R7
MOV
&SumExt,R8
; Sign of result to R8
...
; Continue
;
; Multiply the contents located in a table, R6 points to
; The result is addressed in indirect mode: a NOP is necessary
; to allow the completion of the multiplication
;
MOV
#SumLo,R5
; Pointer to LSBs of result
MPYS16
@R6+,@R6
; MPY signed table contents
NOP
; Allow completion of MPYS16
MOV
@R5+,R7
; LSBs of result to R7
MOV
@R5+,R8
; MSBs of result to R8
MOV
@R5,R9
; Sign of result to R9
...
; Continue
;
; Macro Definition for the signed multiplication–and–
; accumulation 16 x 16 bits. The accumulation is made in the
; RAM: MACHi, MACmid and MAClo. If more than 48 bits are used
; for the accumulation, the SumExt register is added to all
; further extensions (RAM or registers) here shown for only
; one extension (48 bits).
;
MACS16
.MACRO
arg1,arg2
; Signed MAC 16x16 bits
MOV
arg1,&0132h
; Signed MPY is used
MOV
arg2,&0138h
ADD
&SumLo,MAClo
; Add LSBs to result
ADDC
&SumHi,MACmid
; Add MSBs to result
ADDC
&SumExt,MAChi
; Add SumExt to MSBs
.ENDM
On-Chip Peripherals
6-233
The Hardware Multiplier
;
; Multiply and accumulate signed the contents of two tables
;
MACS16
2(R6),@R5+
....
6.4.3.4
; MACS for the table contents
; Accumulation is yet made
Unsigned Multiplication 8 × 8-bits
If byte instructions are used for the loading of the hardware multiplier registers,
then the high byte of these registers is cleared like a CPU register. This behavior is used with the unsigned 8 × 8-bits multiplications.
; Macro Definition for the unsigned multiplication 8 x 8 bits
;
MPYU8
.MACRO
arg1,arg2
; Unsigned MPY 8x8
MOV.B
arg1,&0130h
; 00xx to 0130h
MOV.B
arg2,&0138h
; 00yy to 0138h
.ENDM
; Result in SumLo. SumHi = 0
;
; Multiply the contents of the low bytes of two registers
;
MPYU8
R12,R15
; MPY low bytes of R12 and R15
MOV
&SumLo,R6
; 16 bit result to R6
...
; SumExt = SumHi = 0
;
; Macro Definition for the unsigned multiplication–and–
; accumulation 8 x 8 bits
;
MACU8
.MACRO
arg1,arg2
; Unsigned MAC 8x8
MOV.B
arg1,&0134h
; 00xx
MOV.B
arg2,&0138h
; 00yy
.ENDM
; Result in SumExt|SumHi|SumLo
;
; Multiply–and–accumulate the low bytes of R14 and a table
;
MACU8
6-234
R14,@R5+
; CALL the MACU8 macro (R5+1)
The Hardware Multiplier
6.4.3.5
Signed Multiplication 8 × 8-bits
If byte instructions are used for the loading of the hardware multiplier registers,
then the high bytes of their registers are cleared like a CPU register. It therefore
needs only to be sign-extended.
; Macro Definition for the signed multiplication 8 x 8 bits
;
MPYS8
.MACRO
arg1,arg2
; Signed MPY 8x8
MOV.B
arg1,&0132h
; 00xx
SXT
&0132h
; Extend sign: 00xx or FFxx
MOV.B
arg2,&0138h
; 00yy
SXT
&0138h
; Extend sign: 00yy or FFyy
.ENDM
; Result in SumExt|SumHi|SumLo
;
; Multiply signed the low bytes of R5 and location EDE
;
MPYS8
R5,EDE
; CALL the MPYS8 macro
MOV
&SumLo,R6
; Fetch result (16 bits)
MOV
&SumHi,R7
; Sign: 0000 or FFFF
;
; Macro Definition for the signed multiplication and
; accumulation 8 x 8 bits. The accumulation is made in the
; locations MACHi, MACmid and MAClo (registers or RAM)
; If more than 48 bits are used for the accumulation, the
; SumExt register is added to all further RAM extensions
;
MACS8
.MACRO
arg1,arg2
; Signed MAC 8x8 bits
MOV.B
arg1,&0132h
; MPYS is used
SXT
&0132h
; Extend sign: 00xx or FFxx
MOV.B
arg2,&0138h
; 00yy
SXT
&0138h
; Extend sign
ADD
&SumLo,MAClo
; Accumulate LSBs 16 bits
ADDC
&SumHi,MACmid
; Accumulate MIDs
ADDC
&SumExt,MAChi
; Add SumExt to MSBs
.ENDM
;
;
; Multiply–and–accumulate signed the contents of two byte
On-Chip Peripherals
6-235
The Hardware Multiplier
; tables
;
MACS8
2(R6),@R5+
....
6.4.3.6
; CALL the MACS8 macro (R5+1)
; Accumulation is yet made
Interrupt Usage
Operating in the foreground only (interrupt handlers), the hardware multiplier
can be used freely. If the hardware multiplier is used in the foreground and the
background, or in nested interrupt handlers, however, there are additional considerations.
The hardware multiplier may be used in interrupt handlers and in the background (which is not typical real-time programming practice),if three rules are
observed:
- The loading of the two registers operand1 (MPY, MPYS and MAC) and op-
erand2 may not be separated by an interrupt using the multiplier. The input
information for operand1 cannot be restored due to the three input registers that are possible. See the example below.
- The registers operand1 and operand2 cannot be reread by the back-
ground software — they may be overwritten by the interrupt handler.
- The operand1 information cannot be used for more than one multiplication
— only the operand2 register is changed for the next multiplication. The
floating point package, FPP4, uses this method to speed up the calculation, so it must be changed. The place is indicated.
; Background: multiplication is used together with interrupt
; The interrupt latency time is increased by 9 cycles.
; The NOP is necessary: one additional instruction may
; be executed after the DINT instruction
;
DINT
; Ensure non–interrupted –
NOP
; load of the MPYer registers
MPYU16
R4,R6
; (R4) x (R6) –> Sum
EINT
; Allow interrupts again
...
; Continue with result
; The interrupt handler must save and restore the Sum registers
;
INTRPT_H PUSH
6-236
&SumLo
; Save the SumLo register
The Hardware Multiplier
PUSH
&SumHi
; Save the SumHi register
PUSH
&SumExt
; Save the SumExt register
MPYU16
#X,C1
; Call unsigned MPY: X x C1
....
; Continue with MPYer result
POP
&SumExt
; Restore SumExt register
POP
&SumHi
; SumHi register
POP
&SumLo
; SumLo register
RETI
6.4.3.7
; Return to background
Speed Comparison with Software Multiplication
Table 6–30 shows the speed increase for the different 16 × 16-bit multiplication
modes.
- The cycles given for the software loop include the subroutine call (CALL
#MULxx), the subroutine itself, and the RET instruction. Only CPU registers are used for the multiplication.
- The cycles given for the hardware multiplier include the loading of the mul-
tiplier operand registers operand1 and operand2 from CPU registers, and
— in the case of the signed MAC operation — the accumulation of the
48-bit result to three CPU registers (see Section 6.4.3.1.2).
Table 6–30. CPU Cycles Needed for the Different Multiplication Modes
OPERATION
6.4.3.8
SOFTWARE LOOP
HARDWARE MPYer
SPEED INCREASE
Unsigned Multiply MPY
139...171
8
17.4...21.4
Unsigned MAC
137...169
8
17.1...21.1
Signed Multiply MPY
145...179
8
18.1...22.4
Signed MAC
143...177
17
8.4...10.4
Software Hints
If the operand1 is used for more than one multiplication in sequence, then it
is not necessary to move it again into the operand1 register. The first example
shows two unsigned multiplications with the content of address TONI. Four bytes and six CPU cycles are saved compared to the normal procedure.
; Multiply TONI x R6 and TONI x R5. Results to diff. locations
;
MPYU16
TONI,R6
; TONI x R6 –> SumHi|SumLo
On-Chip Peripherals
6-237
The Hardware Multiplier
MOV
&SumLo,R7
MOV
&SumHi,R8
; Result to R8|R7
MOV
R5,&0138h
; TONI still in &0130h
MOV
&SumLo,RESULT
; TONI x R5 –> SumHi|SumLo
MOV
&SumHi,RESULT+2; Result to RESULT+2|RESULT
The second example shows three multiply-and-accumulate operations with
the same operand1. The three operands2 cannot be added simply and multiplied once — their sum may exceed the range of 16 bits. Eight ROM bytes and
twelve CPU cycles are saved by using this method compared to the normal
procedure.
; Multiply–and accumulate TONI x R6, TONI x R5 and TONI x EDE
; The accumulated result is moved to RESULT..RESULT+4
;
...
6.4.3.9
; Initialize SumXxx registers
MACU16
TONI,R6
; TONI x R6 + SumHi|SumLo
ADD
&SumExt,RESULT+4 ; Add carry to extension
MOV
R5,&0138h
ADD
&SumExt,RESULT+4 ; Add carry to extension
MOV
EDE,&0138h
; Add TONI x EDE to SumXxx
MOV
&SumLo,RESULT
; TONI x (R5+R6+EDE) in SumXxx
MOV
&SumHi,RESULT+2
; Result to RESULT..RESULT+4
ADD
&SumExt,RESULT+4
; Add TONI x R5 to SumXxx
Speed Increase for the Floating Point Package
The hardware multiplier only increases the speed of floating point multiplication. For the speed evaluation shown, the variables X and Y are used. They
are defined as follows:
.if
DOUBLE=0
; 32–bit format
X
.float
3.1416
; 3.1416
Y
.float
3.1416*100
; 314.16
.else
; 48–bit format
X
.double
3.1416
; 3.1416
Y
.double
3.1416*100
; 314.16
.endif
The execution cycles shown include the addressing of one operand and the
subroutine CALL, itself:
6-238
The Hardware Multiplier
MOV
#X,RPRES
; Address 1st operand
MOV
#Y,RPARG
; Address 2nd operand
CALL
#FLT_MUL
; Call the MPY subroutine
....
; Product X x Y on TOS
Table 6–31 shows the number of necessary cycles needed for the
multiplication:
Table 6–31. CPU Cycles Needed for the FPP Multiplication (FLT_MUL)
OPERATION
.FLOAT
.DOUBLE
COMMENT
Multiplication X × Y
395
692
Software loop
Multiplication X × Y
153
213
Hardware MPYer used
Speed increase
2.58
3.25
SW cycles/HW cycles
Due to the speed advantage of the hardware multiplier only for multiplication,
it is recommended that divisions be replaced by multiplications wherever possible. This is most simple for divisions by constants, like is shown in the next
example.
Example 6–54. Division by Multiplication
The division of the last result — on top of the stack — by the constant
2.7182818 is replaced by a multiplication with the constant 1/2.7182818. This
reduces the calculation time by a factor of 405/153 = 2.65. First, the original
sequence:
DOUBLE
HW_MPY
.equ
0
; Use the .FLOAT format
.equ
1
; Use the HW–MPYer
MOV
#FLTe,RPARG
; Address constant e
CALL
#FLT_DIV
; TOS/e: Division 405 cycl.
...
....
FLTe
.float
; Quotient on TOS
2.7182818
; Constant e
The above division is replaced by a multiplication using the hardware
multiplier:
HW_MPY
.equ
1
; Use the HW–MPYer
#FLTei,RPARG
; Address constant 1/e
...
MOV
On-Chip Peripherals
6-239
The Hardware Multiplier
CALL
#FLT_MUL
; TOS x 1/e. MPY 153 cycles
....
FLTei
.float
; Result on TOS
0.3678794
; Constant 1/e
If the .DOUBLE version (48 bits) of FPP4 is used, then the division execution
time is decreased by a factor of 756/213 = 3.55.
6.4.4
Software Applications
Typical proven software examples are given for the application of the hardware multiplier. The comments indicate for some examples the location of the
(think hexa–) decimal point:
± 2.13
S
Integer Bits
15
6.4.4.1
Fraction Bits
0
Multiplication Exceeding 16 Bits
The first software example shows the unsigned multiplication of two 40-bit
numbers (the MSBytes contain 0) — 48 bits of the result are used subsequently. The lower 32 bits of the product are not used. The first operand is contained
in the registers ARG1_xxx and the second operand in ARG2_xxx. The result
is placed into RESULT_xxx (CPU registers or RAM). The multiply routine is abstracted from the FPP4 package.
The execution time for CPU registers is 94 cycles.
6-240
The Hardware Multiplier
Multiplier
Multiplicand
×
ARG2_
0
39
ARG1_
0
39
0
31
ARG1_MID × ARG2_LSB
ARG1_LSB × ARG2_MID
00
ARG1_MSB × ARG2_LSB
00
ARG1_LSB × ARG2_MSB
ARG1_MID × ARG2_MID
00
ARG1_MSB × ARG2_MID
00
ARG1_MID × ARG2_MSB
Intermediate Products
ARG1_MSB × ARG2_MSB
MSB
MID
LSB
Final Product
79
32
Figure 6–57. 40 × 40-Bit Unsigned Multiplication MPYU40
; Register Definitions for the 40 x 40 unsigned MPY and MAC
;
ARG1_MSB .equ
R5
ARG1_MID .equ
R6
ARG1_LSB .equ
R7
ARG2_MSB .equ
R8
ARG2_MID .equ
R9
ARG2_LSB .equ
R10
RESULT_MSB .equ
R11
; Argument 1 (Multiplicand)
; Argument 2 (Multiplier)
; Result (Product)
On-Chip Peripherals
6-241
The Hardware Multiplier
RESULT_MID .equ
R12
RESULT_LSB .equ
R13
;
MPYU40
CLR
RESULT_MSB
; Clear Result
CLR
RESULT_MID
CLR
RESULT_LSB
MPYU16
ARG2_LSB,ARG1_MID ; Bits 16 to 47
MACU16
ARG1_LSB,ARG2_MID
ADD
&SumHi,RESULT_LSB
ADDC
&SumExt,RESULT_MID
MPYU16
ARG1_MSB,ARG2_LSB ; Bits 32 to 63
MACU16
ARG1_LSB,ARG2_MSB
MACU16
ARG1_MID,ARG2_MID
ADD
&SumLo,RESULT_LSB
ADDC
&SumHi,RESULT_MID
ADDC
&SumExt,RESULT_MSB
MPYU16
ARG1_MSB,ARG2_MID ; Bits 48 to 79
MACU16
ARG2_MSB,ARG1_MID
ADD
&SumLo,RESULT_MID
ADDC
&SumHi,RESULT_MSB
MPYU16
ARG1_MSB,ARG2_MSB ; Bits 64 to 79
ADD
&SumLo,RESULT_MSB
;
MACU40
RET
; 48 MSBs in result
The second software example shows all four possible multiplication routines
for two 32-bit numbers; the full 64-bit result may be used afterward. The signed
16 × 16-bit hardware multiplication MPYS cannot be used; it is designed for the
special case of 16 × 16 bits. So the unsigned multiplication MPY is used with
a correction of the final sum at the start of the subroutine.
Execution times (without CALL):
MACU32
MPYU32
MACS32
MPYS32
6-242
58 cycles
64 cycles
64 to 68 cycles
68 to 72 cycles
unsigned MAC
unsigned MPY
signed MAC
signed MPY
The Hardware Multiplier
Multiplier
S
OP2HI
Multiplicand
×
OP2LO
0 15
15
0
S
OP1HI
15
OP1LO
0 15
0
31
0
OP2LO × OP1LO
OP2LO × OP1HI
OP2HI× OP1LO
OP2HI× OP1HI
Product
SUM3
S
SUM2
SUM1
SUM0
63
0
Figure 6–58. 32 × 32-Bit Signed Multiplication MPYS32
Example 6–55. 32 x 32-bit Multiplication and MAC Functions
All four possible 32 × 32-bit multiplication and MAC functions are shown below.
The defined operands and result registers maybe working registers (as defined) or RAM locations.
SUM3
.equ
R15
; Result: sign and MSBs
SUM2
.equ
R14
; (registers or RAM locations)
SUM1
.equ
R13
SUM0
.equ
R12
; LSBs
OP1HI
.equ
R11
; 1st operand: sign and MSBs
OP1LO
.equ
R10
; LSBs
OP2HI
.equ
R9
; 2nd operand: sign and MSBs
OP2LO
.equ
R8
; LSBs
;
; The unsigned 32 x 32 bit multiplication
;
MPYU32
CLR
SUM3
; Clear the result registers
CLR
SUM2
; 64 cycles
CLR
SUM1
On-Chip Peripherals
6-243
The Hardware Multiplier
CLR
SUM0
JMP
MS321
; Proceed at common part
;
; The signed 32 x 32 bit multiplication
;
MPYS32
CLR
SUM3
; Clear the result registers
CLR
SUM2
; 68 to 72 cycles
CLR
SUM1
CLR
SUM0
;
; The signed 32–bit “Multiply–and–Accumulate” subroutine
; The final result is corrected. 64 to 68 cycles
;
MACS32
MS320
TST
OP1HI
; Operand1 negative?
JGE
MS320
; No
SUB
OP2LO,SUM2
; Yes, correct final sum
SUBC
OP2HI,SUM3
TST
OP2HI
; Operand2 negative?
JGE
MS321
; No
SUB
OP1LO,SUM2
; Yes, correct final sum
SUBC
OP1HI,SUM3
;
; The unsigned 32–bit “Multiply–and–Accumulate” subroutine
;
MACU32
.equ
$
; 58 cycles
;
; Main part for all multiplication subroutines
;
MS321
MPYU16
OP1LO,OP2LO
; LSBs x LSBs
ADD
&SumLo,Sum0
; Add product to result
ADDC
&SumHi,Sum1
ADC
Sum2
; Necessary only for MACx32
ADC
Sum3
;
MPYU16
OP1LO,OP2HI
; LSBs x MSBs
;
;
6-244
The Hardware Multiplier
MACU16
OP2LO,OP1HI
; LSBs x MSBs
ADD
&SumLo,Sum1
; Add accumulated products
ADDC
&SumHi,Sum2
; to result
ADDC
&SumExt,Sum3
; Necessary only for MACx32
MPYU16
OP1HI,OP2HI
; MSBs x MSBs
ADD
&SumLo,Sum2
; Add product to final result
ADDC
&SumHi,Sum3
;
;
RET
6.4.4.2
Sensor Characteristics
For many applications, the digital values delivered by analog-to-digital converters, I/O ports, or calculation results must be corrected or adapted. A common method is to use polynomials for this purpose. For example a cubic polynomial to calculate the corrected output value y from the input value x is:
y = a3 × x 3 + a2 × x 2 + a1 × x + a0
With the hardware multiplier, a common solution may look like the following
code. This subroutine is written for the highest possible speed — the coefficients a3 to a0 have decreasing numbers of bits after the (think hexa–) decimal
point. If this cannot be tolerated, then shifts and stores between the multiplications are necessary. The input value x stays in operand1 (MPYS 0132h) and
is used for all three multiplications.
Example 6–56. Value Correction
The output value of the ADC is corrected with a cubic polynomial. All values
are scaled to values less than 1 to get the maximum resolution. The coefficients an used for correction are:
a3: +0.01
a2: –0.25
a1: –0.5
a0: +0.999
The HORNER scheme is used for the computation:
y=
(((a3 × x) + a2) × x + a1)× x + a0
The numbers +–a.b in the code comments indicate the bits before and after
the decimal point of the numbers used.
Execution time (without CALL): 45 cycles
On-Chip Peripherals
6-245
The Hardware Multiplier
;
; Polynomial Calculation for y = a3x^3 +a2x^2 +a1x^1 +a0x^0
; Result in SumHi register
;
POLYNOM
MPYS16
X,A3
; +–0.15 x +–0.15 (+–1.14)
ADD
A2,&SumHi
; +–1.14 + +–1.14 –> +–1.14
MOV
&SumHi,&OP2
; +–1.14 x +–0.15 (+–2.13)
ADD
A1,&SumHi
; +–2.13 + +–2.13 –> +–2.13
MOV
&SumHi,&OP2
; +–2.13 x +–0.15 (+–3.12)
ADD
A0,&SumHi
; +–3.12 + +–3.12 –> +–3.12
RET
; SumHi: +–3.12
;
; Table of coefficients
;
A3
.word
+100*08000h/10000 ; +0.01
A2
.word
–2500*04000h/10000 ; –0.25 (+–1.14)
A1
.word
–5000*02000h/10000 ; –0.5 (+–2.13)
A0
.word
+9999*01000h/10000 ; +0.9999 (+–3.12)
6.4.4.3
(+–0.15)
Table Calculation
The .MACRO instructions used for the different multiplication possibilities (8
bits versus 16 bits, signed and unsigned, multiply and multiply-and-accumulate) have the advantage to allow all seven addressing modes of the MSP430
architecture for source and destination. Therefore, the MPY instructions are
ideal for table processing — both operands of a multiply instruction can also
be addressed indirectly. An example for the table calculation is given in Section
6.4.4.5
6.4.4.4
Wave Digital Filters
The main advantage of wave digital filters is that for fixed coefficients, no multiplication is needed. Instead, an optimized shift-and-add sequence is used for
the filter algorithm. But this optimization is not possible if Adaptive Filter Algorithms are used, which means changing coefficients. In this case, a hardware
multiplier has significant advantages — the calculation time is independent of
the coefficients used.
6-246
The Hardware Multiplier
6.4.4.5
Finite Impulse Response (FIR) Digital Filter
The formula for a simple FIR filter is:
y n = a0 × x n + a1 × x n–1 + a2 × x n–2 +... ak × x n–k
xn
a0
Z–1
Z–1
a1
Z–1
ak-1
ak
yn
yn = a0 xn + a1 xn-1 . . . . +ak xn-k
Figure 6–59. Finite Impulse Response Filter
The example below shows an algorithm that uses the last ADC result for the
input of a seventh-order FIR filter. The coefficients an are stored in ROM (fixed
coefficients) or in RAM (adaptable coefficients). The filter maybe changed easily to a higher order:
- The value k must be changed to the desired order
- (k+1) words in RAM must be allocated for the input samples xn starting at
label X
- The table with the coefficients an must be enlarged to (k+1) coefficients
Execution time: 28 CPU cycles are necessary per filter tap.
The example does not show a real filter — for example, for a linear phase response the coefficients an must be:
an = ak –n
which means: a0 = ak , a1 = ak–1 etc.
On-Chip Peripherals
6-247
The Hardware Multiplier
Input Values
Coefficients
xn
a0
xn-1
a1
Addresses
xn-k+1
R5
ak-1
X
xn–k
S
R7
ak
R8
0 15
15
R6
An
R9
0 15
Result Registers
0
yn = a0 xn + a1 xn-1 . . . . +ak xn-k
Figure 6–60. Storage for the Finite Impulse Response Filter
; The special ”Multiply–and–Accumulate” .MACRO accumulates the
; products X x An in the registers R7|R8|R9.
; Execution time: 19 cycles for the example below with the
; indirect addressing mode used for both operands.
;
MACS16
.MACRO
arg1,arg2
; Signed MAC 16x16
MOV
arg1,&0132h
; Signed MPY is used
MOV
arg2,&0138h
; Start MPYS
ADD
&SumLo,R9
; Add LSBs to result
ADDC
&SumHi,R8
; Add MSBs to result
ADDC
&SumExt,R7
; Add SumExt to result
.ENDM
; Result in R7|R8|R9
; Definitions:
; – Value k defines the order of the FIR–filter
; – OFFSET is used to get signed values (E000h..1FFFh) out of
;
the unsigned 14–bit ADC results (0...3FFFh)
; – X defines the address for the oldest input sample x(n–k)
;
in a sample buffer with (k+1) words length
;
k
.equ
7
; (k + 1)samples are used –
OFFSET
.equ
02000h
; to get signed ADC values
6-248
The Hardware Multiplier
X
.equ
0200h
; x(n–k) sample address
;
; With the Timer_A interrupt the calculation is made
;
TIMA_INT PUSH
TA00
R5
; Save R5 and R6
PUSH
R6
MOV
#X,R5
; Address xn buffer (oldest x)
MOV
#An,R6
; Address an constants (ak)
MOV
&ADAT,2*k(R5)
; New ADC sample to xn
SUB
#OFFSET, 2*k(R5) ; Create signed value for xn
CLR
R7
CLR
R8
CLR
R9
MACS16
@R5+,@R6+
; ak * xn–k added to R7|R8|R9
MOV
@R5,–2(R5)
; xn–k+1 –> xn–k
CMP
#X+2+(2*k),R5
; Through? (R5 points outside)
JNE
TA00
; No, once more
POP
R6
; Restore R5 and R6
POP
R5
BIS
#CS,&ACTL
RETI
; Clear result reg. (MSBs)
; Start next ADC conversion
; Result: +–17.30 (3 words)
;
; The constants An are fixed in ROM. Format: +–0.15
; (1 bit sign, 15 bits fraction)
; Range: –0.99996 to +0.99996
;
An
.word
+9999*8000h/10000 ; ak
+0.9999
.word
–9999*8000h/10000 ; ak–1
–0.9999
...
; ak–2 to a2
.word
+5000*8000h/10000 ; a1
+0.5
.word
–5000*8000h/10000 ; a0
–0.5
On-Chip Peripherals
6-249
The Hardware Multiplier
6.4.4.6
Fast Fourier Transform Algorithm
The buffer — located in the RAM — the pointer that pQR points to, is transformed and overwritten with the result of the fast Fourier transformation (FFT).
The formula used for each block consists of real and imaginary numbers:
PRi’
PIi’
QRi’
QIi’
=
=
=
=
(PRi + (QRi × WRi + QIi × WIi)/2
(PIi + (QIi × WRi – QRi × WIi)/2
(PRi – (QRi × WRi + QIi × WIi)/2
(PIi – (QIi × WRi – QRi × WIi)/2
Where:
WRi
WIi
ω
i
PRi
PRi’
real part of Pi
imaginary part of Pi
real part of Qi
imaginary part of Qi
cos (i × 2 π /N) = cos (ω × i)
sin (i × 2 π /N) = sin (ω × i)
2πf
Index number
Real part of PRi before FFT
Real part of PRi after FFT
Figure 6–61 shows the allocation of the three tables in the RAM and ROM of
the MSP430.
Execution time: the buffer shown, with eight complex numbers each for the P
and Q part, needs 717 cycles (without CALL) for the transformation (185 µs
@ 4 MHz).
6-250
The Hardware Multiplier
Sine/Cosine Table
P0 Real
pWI
sin 0
Pi Values
sin (1/8π)
P0 Imaginary
Addresses
Pn-1 Real
Pn-1 Imaginary
pQR
Q0 Real
Qi Values
Q0 Imaginary
Qn-1 Real
sin (4/8π)
cos 0
sin (5/8π)
cos (1/8π)
sin (6/8π)
cos (2/8π)
sin (7/8π)
cos (3/8π)
sin (10/8π)
cos (6/8π)
sin (11/8π)
cos (7/8π)
Qn-1 Imaginary
Figure 6–61. RAM and ROM Allocation for the Fast Fourier Transformation Algorithm
; Algorithm: ’FFT’ optimized butterfly radix 2 for MSP430x33x
;
; Originally developed by M.Christ/TID for TMS320C80
;
; Input data: PR0,PI0,PR1,PI1,......,QRn–1,QIn–1 (16 bit words)
;
;
Algorithm:
;
;
PR’ = (PR+(QR*WR+QI*WI))/2
WR=cos(wt)
;
PI’ = (PI+(QI*WR–QR*WI))/2
WI=sin(wt)
;
;
QR’ = (PR–(QR*WR+QI*WI))/2
;
QI’ = (PI–(QI*WR–QR*WI))/2
;
;
Procedure:
;
;
real = (QR*WR+QI*WI)/2
;
imag = (QI*WR–QR*WI)/2
On-Chip Peripherals
6-251
The Hardware Multiplier
;
;
PR’
=
PR/2 + real
;
QR’
=
PR/2 – real
;
PI’
=
PI/2 + imag
;
QI’
=
PI/2 – imag
;
N
.equ
16
; 16 point complex FFT
N2
.equ
N*2
; Byte count (QR – PR)
pQR
.equ
R5
; Pointer to QRi
pWI
.equ
R6
; Pointer to sine table tabsin
real
.equ
R7
; Storage
QR x WR + QI x WI
imag
.equ
R8
; Storage
QI x WR + QR x WI
TEMP
.equ
R9
; Temporary storage
TEMP1
.equ
R10
;
;
; The subroutine FFT is called after the loading of the
; pointer to QR0.
;
; Call:
MOV
#QR,pQR
;
CALL
#FFT
;
...
; Pointer to QR0 of block (RAM)
; Call the FFT subroutine
; Input table contains results
;
; Definition of the input table located in the RAM
;
.bss
PR,2,0200h
; PR0
Preal
.bss
PI,2
; PI0
Pimaginary
.bss
PRi,N2–4
; PR1, PI1...PRn–1, PIn–1
.bss
QR,2
; QR0
Qreal
.bss
QI,2
; QI0
Qimaginary
.bss
QRi,N2–4
; QR1, QI1 ...QRn–1, QIn–1
;
; Start of the FFT subroutine. pQR contains address of QR0
;
FFT
;
6-252
MOV
#tabsin,pWI
; Pointer to sin 0
The Hardware Multiplier
; Execution of the 4 multiplications. The halfed result is
; calculated without additional shifts due to the format 2.14
; Calculation of the real part: real = (QR x WR + QI x WI)/2
;
FFTLOP
MPYS16
@pQR+,tabcos–tabsin(pWI);
MOV
&SumHi,real
; Store (QR x WR)/2
MPYS16
@pQR,@pWI
; (QI x WI)/2
ADD
&SumHi,real
; Store real part
(2.14)
(2.14)
;
; Calculation of the imaginary part:
; imag = (QI x WR – QR x WI)/2
;
MPYS16
@pQR+,tabcos–tabsin(pWI);
MOV
&SumHi,imag
; Store (QI x WR)/2
(2.14)
MPYS16
–4(pQR),@pWI+
; (QR x WI)/2
(2.14)
SUB
&SumHi,imag
; Store imaginary part
;
; Calculation of PR’, PI’, QR’, QI’. pQR points to QRi+1
; Calculation of PR’: PR’ = (PR + (QR x WR + QI x WI))/2
;
MOV
–N2–4(pQR),TEMP ; PRi to TEMP
RRA
TEMP
; PRi/2
MOV
TEMP,TEMP1
; Copy PRi/2
ADD
real,TEMP1
; PRi/2 + (QRxWR + QIxWI)/2
MOV
TEMP1,–N2–4(pQR) ; to PR’ (1.15)
;
; Calculation of QR’: QR’ = (PR – (QR x WR + QI x WI))/2
;
SUB
real,TEMP
; PR/2 – (QRxWR + QIxWI)/2
MOV
TEMP,–4(pQR)
; to QR’ (1.15)
;
; Calculation of PI’: PI’ = (PI + (QI x WR – QR x WI))/2
;
MOV
–N2–2(pQR),TEMP
; PI
RRA
TEMP
; PI/2
MOV
TEMP,TEMP1
; Copy PI/2
On-Chip Peripherals
6-253
The Hardware Multiplier
ADD
imag,TEMP1
; PI/2 + (QIxWR – QRxWI)/2
MOV
TEMP1,–N2–2(pQR)
; to PI’ (1.15)
;
; Calculation of QI’: QI’ = (PI – (QI x WR – QR x WI))/2
;
SUB
imag,TEMP
; PI/2 – (QI*WR+QR*WI)/2
MOV
TEMP,–2(pQR)
; to QI’ (1.15)
;
; To next input data. Check if FFT is finished
;
CMP
#tabsin0,pWI
JLO
FFTLOP
; Through? (pWI = tabsin0)
; No
RET
; Yes, return
;
; Sine and cosine table. Format: s.fraction (1.15)
;
tabsin
tabcos
tabsin0
.word
+0000*8000h/10000 ; sin 0.0 =
.word
+3827*8000h/10000 ; sin
0.38268
.word
+7071*8000h/10000 ;
0.70711
.word
+9239*8000h/10000 ;
π/8 =
sin 2π/8 =
sin 3π/8 =
; sin 4π/8
sin 5π/8
sin 6π/8
sin 7π/8
.word
10000*8000h/10000–1
.word
+9239*8000h/10000 ;
.word
+7071*8000h/10000 ;
.word
+3827*8000h/10000 ;
.word
+0000*8000h/10000 ;
.word
–3827*8000h/10000 ;
cos 5π/8
.word
–7071*8000h/10000 ;
cos 6π/8
.word
–9239*8000h/10000 ;
cos 7π/8
cos 4π/8
0.00000
0.92388
cos 0.0
cos
cos
cos
π/8
2π/8
3π/8
;
; An example is given for the FFT:
; The following table contains 32 values that are the data
; for the FFT
; 16 point complex FFT radix 2 DIT
;
DataSt
6-254
.word
014abh,02e90h,0f6d4h,005d3h ; PR0,PI0..PI1
.word
004b2h,0fecdh,0f78ch,0fcb2h ; PR2,PI2..PI3
The Hardware Multiplier
.word
0093ch,004f0h,0ffb5h,0017ch
; PR4,PI4..PI5
.word
0fbebh,002a5h,0f3a3h,0fb38h
; PR6,PI6..PI7
.word
01854h,02a29h,0ffb9h,0f9beh
; QR0,QI0..QI1
.word
0fa49h,00907h,00a10h,0f99bh
; QR2,QI2..QI3
.word
0030ch,0fdadh,0fa2ah,002e3h
; QR4,QI4..QI5
.word
0fddbh,0029bh,0fdf9h,00225h
; QR6,QI6. QI7
;
; The following 32 values are output by the FFT
;
Result
6.4.4.7
.word
0167fh,02c5ch,0fa16h,00013h
; PR’0..PI’1
.word
00384h,0049ch,0fabeh,0f879h
; PR’2..PI’3
.word
00374h,000f2h,0024dh,002e2h
; PR’4..PI’5
.word
0ffa4h,00128h,0fb2ah,0fd01h
; PR’6..PI’7
.word
0fe2bh,00233h,0fcbdh,005bfh
; QR’0..QI’1
.word
0012dh,0fa30h,0fccdh,00438h
; QR’2..QI’3
.word
005c7h,003fdh,0fd67h,0fe99h
; QR’4..QI’5
.word
0fc47h,0017ch,0f879h,0fe36h
; QR’6..QI’7
Conclusion
As shown by the examples, the hardware multiplier has its biggest advantages
when used for signed and unsigned 16-bit operands. But also for other applications — like for 8-bit operands, 32-bit operands or floating point numbers
— the speed increase is valuable compared to the pure software solution.
On-Chip Peripherals
6-255
The System Clock Generator
6.5 The System Clock Generator
The system clock generator of the MSP430 family provides many features not
available with other microcomputers. To allow the full use of all the possibilities,
some basics concerning the function of the oscillator are needed. A detailed
description of the hardware is given in the MSP430 Family Architecture User’s
Guide and Module Library, chapter Oscillator and System Clock Generator.
The output frequency, MCLK, of the system clock generator is generated in a
digitally controlled oscillator (DCO), having 32 taps. Each one of these taps
represents a typical output frequency ranging from 500 kHz to 4 MHz. These
tap frequencies depend on temperature and supply voltage, and referencing
to a crystal is therefore necessary.
; Software definitions for the programming examples
;
SCG1
.equ
080h
; System Clock Generator Control Bit 1
SCG0
.equ
040h
; System Clock Generator Control Bit 0
OSCoff
.equ
020h
; If 1: Oscillator off
CPUoff
.equ
010h
; If 1: CPU off
GIE
.equ
008h
; General Interrupt Enable Bit
SCFI0
.equ
050h
; System Clock Frequency Integrator Reg.
FN_2
.equ
004h
; DCO current switch for 2 x fnom
SCFI1
.equ
051h
; DCO tap register 2^9 to 2^2
TAP
.equ
008h
; 2^5 bit in SCFI1
SCFQCTL
.equ
052h
; System Clock Frequency Control Register
M
.equ
080h
; Modulation Bit in SCFQCTL. M = 1: off
6.5.1
Initialization
After the application of the supply voltage, VCC, the system clock frequency
fsystem is initialized to 1.024 MHz, if a 32.768 kHz crystal is used. This is automatically made by setting of the multiplication factor, N, to 32 and clearing of
the FN_x bits in the control bytes SCFI0 and SCFI1. If the CPU is always on
afterward and 1.024 MHz is the desired frequency, then there is nothing else
to do.
6.5.1.1
First Setting of the DCO Taps during Initialization
The digitally controlled oscillator of the MSP430 starts at tap 0, which means
at the lowest possible frequency (≈ 500 kHz). To get from one tap to the next
6-256
The System Clock Generator
one, 210 (1024) cycles are needed. Thirty-two taps are implemented, so 32 ×
1024 cycles are needed, worst case, to get to the correct DCO tap. The initialization routine should therefore have a length of 32000 cycles. If this is not the
case, a delay routine should be added to guarantee this length. An example
is given below:
INIT
...
L$1
6.5.2
; Loop Control is on (SCG1 = SCG0 = 0)
MOV
#11000,R5
; Init delay to allow DCO setting
DEC
R5
; 11000 x 3 cycles = 33000 cycles
JNZ
L$1
;
BR
#MAINLOOP
; Start program
Entering of Low Power Mode 3
The low power mode 3 (LPM3 —crystal on, DCO and loop control off) is the
normal mode for battery-powered systems. Enabled interrupts (e.g. the basic
timer) wake up the CPU. LPM3 is entered with the following source code:
BIS
6.5.3
#CPUoff+GIE+SCG1+SCG0,SR
; Enter LPM3
Wake-Up From Interrupts in Low Power Mode 3
Wake-up from LPM3 clears only bit SCG1 (LPM1). Due to the set bit SCG0,
the loop control of the DCO is off. Normal interrupt routines are too short to allow the loop control to adjust the DCO tap — 1024 cycles are necessary to get
from one tap to the other one. It is not necessary, therefore, to switch on the
loop control. The CPU uses the DCO tap set during the last adaptation. A normal, short interrupt routine looks like this:
BT_HAND
INC
RETI
COUNTER
; LPM1: Loop Control stays off:
; DCO is on for 17 cycles only
If woken–up from LPM3, the interrupt latency time (6 cycles) is increased by
typ. 2 µs @ 1 MHz versus 1 µs @ 2 MHz (if FN_2 = 1). This means 8 cycles
are typically needed from the interrupt event to the start of the interrupt handler. The time the DCO needs to settle to the nominal frequency is typically 4
cycles. This means interrupt handlers are processed with the correct frequency.
6.5.4
Adaptation of the DCO Tap During Calculations
The DCO tap of the system clock generator should be updated during longer
on times of the CPU (e.g. during calculations). This is necessary especially if
On-Chip Peripherals
6-257
The System Clock Generator
accurate timing of the instructions is needed. During all calculations that exceed 100 cycles in length, the loop control of the DCO should be switched on.
The way to do this is to reset the SCG0 bit in the status register after the wake–
up:
; Calculations are necessary. Allow adaptation of the DCO tap
;
BIC
#SCG0,SR
; Switch on DCO loop control
...
; Calculate energy (>100 cycles)
RETI
; Return to LPM3 with adapted DCO tap
The RETI instruction restores the CPU mode from the stack as it was when
the interrupt occurred.
6.5.5
Wake–Up From Interrupts in Low Power Mode 4
The low power mode 4 normally lasts much longer than the low power mode
3 — it may last for months until a stored module is woken–up for calibration.
This means that the environment temperature may have changed seriously.
If the LPM4 was entered at a high temperature, the used DCO tap will be a relatively high one due to the negative temperature coefficient of the DCO. If then
the device is woken–up at a low temperature and the crystal turns on fast, this
high DCO tap may lead to a very high DCO frequency, a frequency the system
cannot operate with. Therefore, it is a good programming practice, to program
a low DCO tap before entering LPM4:
; Enter Low Power Mode 4: Set DCO tap to 2
;
MOV.B
#TAP*2,&SCFI1
; Set DCO tap to 2
BIS
#CPUoff+OSCoff+GIE+SCG1+SCG0,SR ; Enter LPM4
If woken–up from LPM4, it may last up to seconds until the crystal has reached
its nominal frequency. The frequency integrator counts down continuously as
long as the crystal oscillator has not started its operation. This lasts until the
lowest DCO tap (with the lowest system frequency) is reached. After the start
of the crystal oscillator, the loop control will set the system frequency to its correct value by stepping up the taps.
6-258
The System Clock Generator
6.5.6
Change of the System Frequency
The system clock frequency fsystem depends on two values:
fsystem = N × fcrystal
Where:
N
fcrystal
Multiplication factor of the DCO loop (SCFQCTL contains N–1)
Frequency of the crystal (normally 32.768 kHz)
The normal way to change the system clock frequency is to change the multiplication factor N. The system clock frequency control register SCFQCTL is
loaded with (N–1) to get the new frequency. To allow the DCO to work always
in one of the center taps (13 to 18), three switches FN_2 to FN_4 are implemented in the register SCFI0. It gives a safety not to be at the frequency limits
of the DCO. These switches increase the internal current of the DCO and allow
higher output frequencies if set. The switch nearest to the programmed DCO
output frequency should be used.
The switches FN_x typically settle within ±1 tap if the change is from the nominal frequency of one switch to the nominal frequency of the other one. For example, if in the example below, the initial system frequency is 1 MHz, then the
new tap is one of the neighboring taps. This means, to settle at 2 MHz, needs
a maximum of 1024 cycles (0.5 ms) only. If FN_2 is not used, it would take up
to 16 x 1024 cycles (8 ms) because the misalignment could be up to 16 taps.
Note:
The switches FN_2, FN_3, and FN_4 need to be set correctly in dependence
of the system clock frequency, fsystem. Otherwise, erroneous behavior of the
system will result. Only one switch may be in use at the same time — the one
that is nearest to the actual frequency should be used. FN_2 controls frequencies near 2 MHz, FN_3 controls frequencies around 3 MHz, and FN_4
controls frequencies around 4 MHz.
; Change system frequency to 2.048MHz (fcrystal = 32.768kHz)
; N = 64
: Multiply 32kHz by 64 to get 2.048MHz
; FN_2 = 1: Adjust DCO current to 2MHz output frequency
; M = 0
: Switch on modulation
;
MOV.B
#64–1,&SCFQCTL
; 64 x 32kHz = 2.048MHz, M = 0
MOV.B
#FN_2,&SCFI0
; Adjust DCO current to 2MHz
On-Chip Peripherals
6-259
The System Clock Generator
6.5.7
The Modulation Bit M
The modulation bit M (SCFQCTL.7) switches off and on the influence of the
5 LSBs (NDCOmod) of the system clock frequency integrator:
- M = 0 — the modulation is on. This means all 10 bits of the integrator influ-
ence the DCO. The used tap of the DCO may be changed with every clock
cycle to get the correct system clock frequency. This is the case if the programmed frequency lies exactly between two tap frequencies.
- M = 1 — the modulation is off. This means only the 5 MSBs (NDCO) of the
integrator influence the DCO. The used tap of the DCO is changed only
after 1024 clock cycles (for fsystem = 1 MHz) to get the correct system clock
frequency. If the programmed frequency lies exactly between two tap frequencies, then 1024 cycles are output with the lower tap frequency and
1024 cycles are output with the upper tap frequency.
In any case, independent of the modulation status, the integral error of the
DCO will be zero.
The modulation may be switched off if a series of MCLK cycles is needed with
exactly the same length (for measurements with the universal timer/port module, for example). To get this, the loop control also should be switched off.
; Ensure stable, non regulated output pulses with equal length:
;
BIS.B
#SCG0,SR
; Switch off loop control
BIS.B
#M,&SCFQCTL
; Switch off modulation
...
; Use non–regulated MCLK
;
; Return to a regulated MCLK with closed loop and modulation
;
6-260
BIC.B
#SCG0,SR
; Switch on loop control
BIC.B
#M,&SCFQCTL
; Switch on modulation
The System Clock Generator
6.5.8
Use Without Crystal
If for an application, no precise timing is necessary, then the crystal may be
omitted. If no ACLK is present (due to the missing crystal), then the DCO will
run with its lowest frequency, which is approximately 500 kHz. No special instructions are necessary to get this behavior.
If this lowest DCO frequency is too low, then a higher DCO tap (eg. 10) may
be used. This tap normally results in an MCLK frequency near 1MHz. It is important to switch off the FLL loop, otherwise the FLL control will step down to
tap 0 slowly. The software for this use of the DCO follows:
; Initialization of the DCO for non–crystal mode:
; Loop control off, tap number = 10: MCLK ≈ 1MHz
;
BIS.B
#SCG0,SR
; Switch off loop control
CLR.B
&SCFI0
; Reset FN_x bits
MOV.B
#050h,&SCFI1
; Set bits for tap number 10
If an external reference like the ac line is available, then the actual MCLK frequency can be controlled simply by the counting of the MCLK output with one
of the timers (e.g. for one ac line period). An example is given in section The
Timer_A where the control of an LCD is also shown without a crystal and missing LCD control frequency due to the missing ACLK.
6.5.9
High System Frequencies Together With the 14-bit ADC
The maximum MCLK without input division is 1.5 MHz (132 cycles are needed
for a conversion). To allow the full range of the system clock MCLK, together
with the active ADC, a clock divider is included in the ADC module. It allows
the division of the system frequency MCLK by factors of 1, 2, 3, and 4. See
section Analog-to-Digital Converters for examples.
6.5.10 Dependencies of the System Clock Generator
If the DCO runs with an open loop, its frequency depends on the temperature
and the supply voltage, VCC. Nominal values for these dependencies are:
- Temperature dependence: –5.6 kHz/(_C × MHz)
- Voltage dependence:
+60 kHz/(V × MHz)
These two dependencies are brought to zero if the DCO loop is closed (SR–
bits: SCG0 = SCG1 = OscOff = 0). See the next section for short term deviations of the system clock generator (MCLK).
On-Chip Peripherals
6-261
The System Clock Generator
6.5.11 Short Time Accuracy of the System Clock Generator
The error of the system clock generator is zero for long time periods
(compared to the system frequency fsystem). Normally, no tap of the DCO can
deliver the correct system frequency, fsystem, which is defined for the settled
state to
fsystem = N × fcrystal
Therefore, the system clock generator switches continuously between two adjacent DCO taps — the one with a lower frequency fN and the tap with a higher
frequency fN+1. This switching between the two DCO taps NDCO and NDCO+1
is interlaced in such a way that it results in a small error at any time within the
ACLK period. The resulting error for a complete ACLK period is nearly zero
and the integral error for a longer period is zero.
Figure 6–62 shows the use of the 10 bits of the registers SCFI0 and SCFI1.
The five MSBs NDCO control the DCO–taps, the five LSBs NDCOmod control the
modulation scheme of the DCO.
Bits located in the System Clock Frequency Integrator Registers SCFI0 and SCFI1
4
x
x
x
x
NDCO
DCO Tap Control (0 ..31)
0
4
x
x
0
x
x
x
x
NDCOmod
DCO Modulation Control (0 .. 31)
Figure 6–62. Control of the DCO by the System Clock Frequency Integrator
Figure 6–63 illustrates the DCO switching between the lower and the higher
DCO tap for selected values of NDCOmod.
6-262
The System Clock Generator
NDCOmod Value of the 5 LSBs of the
System Clock Frequency Integrator
∆ max
31
∆ max
24
16
15
∆ max
5
4
3
2
Upper DCO Tap Frequency fN+1 active
1
Lower DCO Tap Frequency fN active
0
0
5
10
15
20
25
30 31 0
MCLK Cycles 1MHz
One ACLK Cycle
Figure 6–63. Switching of The DCO Taps Dependent on NDCOmod
Table 6–32 lists the errors of the system clock generator. The assumptions for
Table 6–32 are:
- The frequency step from the lower tap frequency fN to the higher tap fre-
quency fN+1 is 10% (multiplication factor 1.1).
- The two frequencies, fN and fN+1, allow an error free system frequency
during one ACLK period — the two frequencies result in zero error if used
with the shown NDCOmod.
- The crystal error is not included — the crystal is considered to be errorfree.
- The system frequency is normalized to 1 MHz. For all other frequencies,
the resulting errors can be calculated simply by a relation to 1 MHz.
- The FLL has settled, which means, it has had enough time (e.g. during cal-
culation sequences) to switch to the appropriate DCO taps.
Three errors of the system clock generator are calculated in Table 6–32:
On-Chip Peripherals
6-263
The System Clock Generator
- The maximum time deviation, terr, during an ACLK period for a system
with ideal tap frequencies (assumption 2 above). This inherent time deviation is mainly due to the length of ∆max.
- The worst case time deviation, terrmax, during an ACLK period for a sys-
tem with ideal tap frequencies. To get this time deviation, the calculation
is made with the DCO frequencies for a value of NDCOmod that is one step
above the correct frequencies. This results in the maximum possible time
deviation for the FLL, independent of the tap frequencies.
- The worst case value of the integrated time deviation terrper. This is the
largest deviation seen at the end of a complete ACLK period.
Note:
The three errors named above do not accumulate — on the contrary, they
get smaller with each ACLK period and tend to reach zero. This is a very important property of the system clock generator.
Values in brackets are used for calculations only, shading indicates the frequency used (fN resp. fN+1) for the error calculation.
Table 6–32. System Clock Generator Error
NDCOmod
fN (MHz)
fN+1(MHz)
∆max
terr (ns)
0
1.000
1.1000
32
0
terrmax (ns)
89
terrper (ns)
91
1
0.9972
1.0969
31
87
177
91
2
0.9943
1.0938
15
86
129
91
3
0.9915
1.0906
15
128
172
93
4
0.9886
1.0875
7
80
101
92
92
5
0.9858
1.0844
7
101
121
(6)
0.9830
1.0813
7
121
–
–
15
0.9574
1.0531
3
134
143
96
16
0.9545
1.0500
1
48
51
0
(17)
0.9517
1.0469
1
51
–
–
98
24
0.9318
1.0250
3
–73
–64
(25)
0.9290
1.0219
4
–86
–
–
31
0.9119
1.0031
31
–97
–100
100
(0)
0.9091
1.0000
32
0
–
–
Note:
The values shown in Table 6–32 get smaller with increasing frequency. If fN
is 2 MHz, for example, the values are only one-half of the table values.
6-264
The System Clock Generator
Where:
NDCOmod
fN
fN+1
∆max
terr
terrmax
terrper
fsystem
Value of the five LSBs of the system clock frequency integrator
DCO output frequency of the DCO tap NDCO (lower frequency)
[MHz]
DCO output frequency of the DCO tap NDCO+1 (higher frequency)
[MHz]
Longest sequence with the same tap within the switching scheme for a
given value of NDCOmod measured in MCLK cycles. See figure 6–63
Maximum time deviation (time error) within an ACLK period due to
∆max. terr is the inherent error for a given value of NDCOmod.
[ns]
Worst case time deviation (time error) within an ACLK period due to ∆max.
The higher error results from the correction with the tap frequencies for
(NDCOmod +1). For a full ACLK period the error reduces to terrper
[ns]
Worst case time error for a complete ACLK period (30.5 µs).
The error results from the correction with the tap frequencies
for (NDCOmod+1).
[ns]
Nominal, errorless value of the system frequency. Here 1MHz.
[MHz]
The formulas used for the error calculations are:
( f1 – f 1 )
terr = ∆max ×
N
system
(f1
terr = ∆max ×
–
N+1
or for shaded cells
1
fsystem
)
The formulas for terrmax are the same as for terr, but tap frequencies fN and
fN+1 of (NDCOmod+1) are used.
The formula for terrper also uses the tap frequencies fN and fN+1 of
(NDCOmod+1).
terrper =
(32 – NDCOmod )×(
1
1
1
1
–
+ NDCOmod ×
–
fN + 1 fsystem
fN fsystem
)
(
)
6.5.12 The Oscillator Fault Interrupt Flag
If the value NDCO contained in the DCO tap control byte SCFI1 moves out of
its valid range:
0 < NDCO < 28
the oscillator fault interrupt flag OFIFG (located in IFG1.1) is set. If the oscillator interrupt enable bit OFIE (located in IE1.1) is also set, an interrupt is requested.
On-Chip Peripherals
6-265
The System Clock Generator
Note:
The interrupt vector of the oscillator fault interrupt flag is shared with the non
maskable interrupt (NMI). It is necessary, therefore, to test the oscillator fault
interrupt flag first to determine the cause of the interrupt.
The oscillator fault interrupt flag is set after the supply voltage is applied to the
MSP43, due to the start of the DCO at the lowest frequency (NDCO = 0). When
the interrupt is granted, the oscillator interrupt enable bit OFIE is reset automatically to disable further interrupt requests. The oscillator fault interrupt flag
OFIFG must be reset by software.
6.5.13 Conclusion
The time deviations listed in Table 6–32 demonstrate the small error
introduced by the modulation of the DCO. The largest time deviation inside of
one ACLK period is 177 ns. This is relatively small compared to the inherent
digital uncertainty, which is one MCLK cycle (1 µs @ 1 MHz). The time deviations of the system clock generator do not accumulate, but get smaller with
the next ACLK period. Therefore, the overall error tends to move toward zero
for a longer time period. The system clock generator, with its output frequency
fsystem (MCLK), is therefore usable for precise time measurements like a normal crystal oscillator.
6-266
The RESET Function
6.6 The RESET Function
The RESET functions of the MSP430 family are described in detail below.
Many problems can be avoided if the RESET functions are completely understood. Normally, the internal RESET hardware, together with the watchdog
timer, avoids these problems. Under certain circumstances, however, additional external hardware is necessary. Several methods are described.
6.6.1
Description of the MSP430 RESET Function
The MSP430 generates two different internal RESET signals:
- The power-on reset signal (POR).
- The power-up clear signal (PUC).
These two signals are not available externally — they are used only internally
(on-chip). Figure 6–64 gives a simplified overview of the RESET function. The
numbers at the gate inputs refer to the signals described in sections 6.6.1.1
and 6.6.1.2.
Vcc
1.
POR Detect
Delay
Set
Q
POR
Q
PUC
2.
Reset
Vss
RST/NMI
NMI (WDTCTL.5)
Delay
Reset
Watchdog Selected (WDTCTL.4)
Watchdog Overflow
Watchdog Flag
3.
t delay
Set
4.
Security Violation
Figure 6–64. Simplified MSP430 RESET Circuitry
Note:
The power on detection circuit is not a supply voltage supervisor. Control of
the supply voltage is normally performed by linear circuits. Stable supply
voltage to the MSP430 must be maintained at all times, including when it is
in low power mode 3 and 4.
On-Chip Peripherals
6-267
The RESET Function
6.6.1.1
The Power–On Reset Signal
The power-on reset signal, POR, is caused by two completely different external events:
- The power-on detection circuitry detects the rise of the supply voltage,
VCC (power-on signal).
- The RST/NMI terminal is reset to VSS and set to VCC afterward. This is the
case only if the reset terminal is switched to the RESET function (default
after power-on) and not to the NMI function. The RESET function is used
if WDTCTL.5 = 0.
(NMI stands for non maskable interrupt, an external interrupt input that cannot
be disabled by the interrupt enable bit (GIE) in the status register (SR). Each
interrupt event will request an interrupt. The NMI function is used if WDTCTL.5
= 1).
6.6.1.2
The Power-Up Clear Signal
The power-up clear signal, PUC, can be caused by several events:
- The power-on detection circuitry detects the rise of the supply voltage
(VCC). This event also causes the POR signal.
- The RST/NMI terminal is reset to VSS and then set to VCC afterward (see
above). This event also causes the POR signal.
- The expiring of the Watchdog Tmer if programmed to the watchdog mode
(WDTCTL.4 = 0). The watchdog function is always active after PUC and
POR.
- The use of an invalid password for the writing to the watchdog control word
WDTCTL (security violation). This reset generation is independent of the
watchdog function — it also occurs if the watchdog is used in timer mode
(WDTCTL.4 = 1)
6.6.1.3
Common Operations for Power–Up and Power–On Reset
If one of the events described above occurs, the following operations are
started:
- The digital I/O ports (Port0 to Port4) are set to the input direction.
- The I/O flags are set to 0 as discussed in the description of the peripherals.
- The address contained in the vector at address 0FFFEh is written into the
Program Counter PC (software start address).
6-268
The RESET Function
- The Status Register SR of the CPU is reset to 0. This means:
J
The CPU is set to the active mode.
J
The maskable interrupts are disabled by the reset GIE–bit (SR.4).
J
The loop control for the system clock generator is switched on (the
FLL is active).
J
The system clock generator is set to an MCLK frequency of 1 MHz @
fACLK = 32.768 kHz.
- The digitally controlled oscillator (DCO) in the system clock generator
(FLL for MCLK) is set to its lowest output frequency (DCO tap 0). The reason for this is to also include the possible malfunction of the system clock
generator. Otherwise the erroneous FLL frequency is also active during
the restoring phase of the system functionality with a fatal effect: the system cannot come up correctly.
- The RST/NMI terminal is configured to the RESET function.
- The Watchdog Timer is configured as a watchdog driven by the system
clock MCLK.
- The CPU starts operation at the address written into the Program Counter
(from address 0FFFEh) after the RST/NMI terminal is set to VCC voltage.
6.6.1.4
Differences Between Power-Up Reset and Power-On Reset
The few differences between the two reset signals are detailed below.
6.6.1.4.1 Peculiar to The Power-On Reset Signal
- The power-on reset signal (POR) also generates the PUC signal.
- The power-on reset signal sets (1) or resets (0) the peripheral bits en-
closed in round brackets (see Architecture User’s Guide). These bits (all
of the peripheral bits of the 16-Bit Timer_A, for example) are not influenced
by the PUC signal. For example, rw–(0) means a readable and writable
peripheral bit that is set to 0 by the POR signal only, but not by the PUC
signal.
The reason is that some functions may not be modified by watchdog events.
These functions are mostly controlled by software.
6.6.1.4.2 Peculiar to The Power-Up Clear Signal
- The power-up clear signal (PUC) does not also generate the POR signal.
On-Chip Peripherals
6-269
The RESET Function
- The power-up clear signal (PUC) sets or resets the peripheral bits not en-
closed in round brackets (see Architecture User’s Guide). For example,
rw–0 means a readable and writable bit that is set to 0 by the POR and
PUC signals.
6.6.1.5
The RST/NMI Terminal Hardware
Some important facts that need to be considered when using the MSP430
RST/NMI terminal:
- The RST/NMI terminal does not have a pulldown or pullup resistor. The
user must ensure a stable DVCC or VCC voltage level at the RST/NMI terminal during normal operation. Otherwise, hum or noise will generate arbitrary system resets if the terminal is left unconnected (floating).
- The RST/NMI terminal is an input pin only. No RESET signal is output if
an internal RESET occurs (by a watchdog overflow, for example). If external devices must also be reset, then two possibilities exist (see Figure
6–65, right side):
J
An O-output is used. This output is set and reset by a short software
routine during the initialization phase following the RESET signal. The
state of an O-output is not defined after the power up.
J
An I/O terminal (one of Port0 to Port4) or a TP terminal is used. This
terminal is connected to VSS (DVSS) with a resistor (≈10 kΩ). While the
RESET signal is active, the pin is switched to the input direction
(compared to the HI–Z state) and the resistor pulls down the I/O terminal. This low signal resets all external devices immediately. The subsequent initialization software switches the terminal to an active high
signal. The external RESET signal is terminated. (A positive RESET
signal can be generated in the same way. The resistor is connected to
the supply voltage VCC, the initialization software outputs an active
low signal.)
- The power-on detection circuitry is only able to detect a new, slow rise of
the supply voltage (VCC) after a power fail, if VCC falls below a defined voltage, VCCmin. If this cannot be guaranteed, external hardware is recommended. See the next section for the details of this hardware.
- To guarantee a successful RESET, the low signal at the RST/NMI terminal
needs a minimum length of time (treset). This minimum time is 2 µs.
6-270
The RESET Function
+3V
PUC–Signal
Vcc
P0.x,TP.y
Rrst
Reset by Software
P0.y,TP.z
RST/NMI
MSP430
Reset
Switch
0V
Software Signal
O.x
Vss
Figure 6–65. Generation of RESET–Signals for External Peripherals
6.6.2
RESET With the Internal Hardware, Including the Watchdog
The internal power-on detection hardware of the MSP430 allows very reliable
initializations for the complete system. If, due to special circumstances, this
normal process fails, the watchdog (which is completely different from that in
most other microcomputer systems in that it is active after power on) resets
the MSP430 once more.
6.6.2.1
Restrictions
The oscillator fault flag OFIFG is set as long as the system clock frequency
MCLK is outside of the frequency limits. The flag information is set by the FLL
hardware — if the DCO reaches its frequency limits then the flag OFIFG is set
(IFG1.1 = 1). This flag must be reset by software.
Note:
The oscillator fault interrupt uses the same interrupt vector (0FFFCh) as the
NMI interrupt. This means that the interrupt handler first has to check the
cause of the interrupt if the NMI function is also used. This is possible by testing of the OFIFG flag (IFG1.1) or by testing the NMI flag. (IFG1.4).
The frequency limits of the digitally controlled oscillator are reached if the
system clock frequency integrator register SCFI1 contains 0 or ≥ 0E0h (corresponds to DCO taps 0 or ≥ 28). See the Architecture User’s Guide.
On-Chip Peripherals
6-271
The RESET Function
6.6.2.2
Start-Up of the Crystal
The ultra low power design used for the crystal oscillator of the MSP430 results
in a relatively long time before it reaches oscillating stability. This may take up
to four seconds. Until the crystal oscillator has reached a stable ACLK frequency (32 kHz), the digitally controlled oscillator (DCO) of the system clock generator remains at its lowest frequency (see appropriate data sheet). This is not
a problem for most of the MSP430 applications. The crystal oscillator is
switched on after power on, and runs continuously with no off periods.
The tap used is defined by the five most significant bits of the FLL register
SCFI1 at address 051h. The actual value of register SCFI1 can be stored to
provide quick return to the former system clock frequency (MCLK) in case of
a RESET. The stored value needs to be checked, otherwise the value that
caused an oscillator fault is restored again and again, which results in a system
hangup.
6.6.3
Reliable RESET With Slowly Rising Power Supplies
To get reliable RESET conditions with power supplies that exhibit very slowly
increasing voltages (∆V/∆t), or with voltage dropouts that do not reach the lower threshold voltage (Vmin) of the POR detection circuitry (approximately 0.4 V,
see data sheet), some external hardware is recommended. Some possibilities
are shown in this chapter.
Note:
No call for emergency tasks is possible with all the solutions shown in this
section. The RESET signal goes low without any warning to the software. If
it is necessary to save important RAM contents in an external EEPROM and
to execute defined emergency tasks before the RESET signal goes active,
then the solutions shown in the section Battery Check and Power Fail Detection should be considered. Voltage supervision is performed at the regulator
input and signals the loss of the supply voltage via the RST/NMI terminal
switched to the NMI function. This early warning allows the execution of
emergency tasks before power fails completely.
6.6.3.1
RESET With a Switch
This is the most simple RESET hardware for the MSP430. It is normally used
if the battery is soldered into the system and the calibration constants reside
in the RAM. But this solution may also be used for all other supply systems.
If calibration constants are stored in the RAM, then a check at the start of the
initialization routine is necessary if a Warmstart (system is calibrated) or a
Coldstart (RAM is nonvalid) occurred. This distinction is normally made with
6-272
The RESET Function
special constants written to the RAM during the calibration process. These
constants use bit patterns that are relatively improbable (e.g. 05AF0h) due to
their mix of 0s and 1s. See section Software Applications for more details.
To reset the MSP430, the switch (Figure 6–66) is pressed for a moment and
then released. The VSS potential at the RST/NMI terminal initiates the POR
and the PUC signals.
+3V
Vcc
Rrst
COM
SEL
Cch
Battery
Error
RST/NMI
ms
h
MSP430C323
Reset
Switch
P0.x,TP.y
Vss
I/Os
An
0V
Analog Inputs
Figure 6–66. Battery-Powered System With RESET Switch
6.6.3.2
PNP Transistor With Zener Diode
This simple hardware (Figure 6–67) may be used if the supply voltage of the
MSP430 is delivered from a higher system voltage, Vsys, of 6 V to 15 V. The
PNP transistor, together with the 3.3-V or 4.5-V Zener diode, delivers the supply voltage and the RESET signal for the MSP430 system. The fast rise of the
supply voltage VCC provides a reliable power up.
Vsys +5V..+10V
SVcc
Vsys
Vcc
MSP430C3xx
DVcc
Power–down
Power–up
Voltage
AVcc
Vz+Vd
Vz+VBE
Vcc
Vz
RST/NMI
Vz
Dz
AVss
DVss
0V
Time
Figure 6–67. Simple RESET Circuit With a PNP Transistor
On-Chip Peripherals
6-273
The RESET Function
6.6.3.3
Operational Amplifier With Reference Diode
With an operational amplifier used as a comparator (an unused operational
amplifier in a dual or quad package, for example) a simple and reliable RESET
circuit can be built. Figure 6–68 illustrates this solution. During the start-up
phase of the supply voltage, the voltage of the nonconducting reference diode
is higher than the divided voltage at the noninverting input of the comparator.
This causes the output voltage of the comparator to be low and the MSP430
is held in the reset state. When the supply voltage reaches the minimum voltage, VCCmin, (defined by Vz, R2, and R3) then the comparator outputs a high
signal and the MSP430 starts with its program. The value of VCCmin is:
Vccmin = Vref ×
+1
(R2
R3 )
Spike
Powerfail
Vcc
VC
+
Voltage Drop–out
+5V
5V
R1
R2
+
Cch
Vcc
Vccmin
VRST
RST/NMI
–
MSP430
R3
Vref
–
VRST
0V
Supply from:
Accumulator
Mains Rectifier
Capacitor Supply
Vss
undefined
Figure 6–68. RESET Circuit With a Comparator and a Reference Diode
For reliable results, the operational amplifier used should be able to operate
with relatively small supply voltages (approximately 1 V).
For the calculation of the resistor values for R2 and R3, see the formulas below
for figure 6–69. Resistor R4 is simply set to infinite (∞) to get the values for this
solution.
Circuitry similar to above is used in Figure 6–69. The only difference is the
Schmitt trigger characteristic of the RESET circuitry — it rejects false RESET
signals caused by hum, noise, and spikes. Two independent voltage threshold
voltages, VTH+ and VTH–, can be calculated with the reference voltage Vref
and the three resistors R2, R3, and R4. The formulas follow below.
6-274
The RESET Function
Spike
Powerfail
Vcc
VC
+
Voltage Drop–out
+5V
5V
R2
Vcc
R4
Vth+
R1
Vth–
+5V
+
Cch
RST/NMI
–
MSP430
R3
Vref
–
VRST
0V
Vss
Supply from:
Accumulator
Mains Rectifier
Capacitor Supply
Figure 6–69. RESET Circuit With a Schmitt Trigger and a Reference Diode
All of the resistors (R2, R3, and R4) are relative to a calculated resistor Ri,
which is the resulting resistance of the paralleled resistors R2 and R3. The value of Ri depends on the input offset current (Ioff) of the operational amplifier
and the maximum tolerable error voltage (Ue) caused by Ioff. The maximum
value of Ri is calculated first:
Ri <
Ue
Ioff
With the calculated value of Ri, the three resistors (R2, R3, and R4) are calculated next:
R4 = Ri ×
(Vref V× (V ×V –V
TH +
TH –
TH +
(
1
R3 = Ri ×
1 –
)
)
–1
TH –
(
))
Vref
Ri
×
+1
VTH +
R4
On-Chip Peripherals
6-275
The RESET Function
(
R2 = Ri ×
1
(
))
Vref
Ri
×
+1
VTH +
R4
Example 6–57. RESET Circuit
A RESET circuit similar to that shown in Figure 6–69 is built with the following
behavior:
RST/NMI is VSS for VCC < 2.5 V
RST/NMI is VCC for VCC > 3 V
Vref = 1.25 V
Ioffmax = ± 200 nA (maximum offset current of the inverting input)
Maximum voltage error due to Ioff: ± 150 mV
150mV
→ Ri < 0.75MΩ
200nA
Ri <
(
R3 = 0.75MΩ ×
(
)
3V × 2.5V
–1
1.25V × (3V –2.5V )
R4 = 0.75MΩ ×
))
1
(
1.25V
0.75MΩ
1 –
×
+1
3V
9MΩ
R2 = 0.75MΩ ×
(
))
1
1.25V
0.75MΩ
×
+1
3V
9MΩ
(
= 9MΩ
= 1.37MΩ
= 1.67MΩ
Figure 6–70 illustrates the connection of an operational amplifier with an output voltage higher than VCC (here the unregulated voltage VC) to the MSP430
RST/NMI terminal. The diode protects the RST/NMI terminal and resistor Rrst
provides the positive voltage.
6-276
The RESET Function
LT1078CN
+VC
Non–regulated Voltage
2.4R
–
Voltage Regulator
+3V
+
Vcc
MSP430
Cch
Rrst
R
0V
Vss
–
Supply Voltage Supervisor
Reset
RST/NMI
+
Vref
A0
+VC
Figure 6–70. RESET Generation With a Comparator
6.6.3.4
Supply Voltage Supervisors
The use of a supply voltage supervisor is one of the best methods of getting
a reliable RESET signal. All necessary parts such as reference, programmable delay, output stage, and so on are integrated in a single IC. Only a few
external components are necessary. Two different solutions are explained:
- The TL770x supply voltage supervisor.
- The TP3750 supply voltage supervisor and regulator. This IC integrates
two functions: supply voltage regulation, and supply voltage supervision.
6.6.3.4.1 TL7701 Supply Voltage Supervisor
The schematic for a supervised MSP430 is shown in Figure 6–71. The
TLC7701 is programmed with the resistors R1 and R2 to reset the MSP430
when the output voltage of the 5-V regulator falls below Vccmin (2.5 V).
+5V
Vcc
5V
R1
Mains
VDD
Resin
TLC7701
Sense
Reset
Vout
RST/NMI
GND CTRL Ct
Cch
MSP430
R2
Ct
Vss
0V
Figure 6–71. Power Fail Detection With a Supply Voltage Supervisor
On-Chip Peripherals
6-277
The RESET Function
Figure 6–72 shows the different system states of the voltage supervisor solution. The voltage VCC is drawn in a simplified manner for a better understanding of the system function. The different System States (shown below in Figure
6–72) are:
- Up to a certain voltage, the output of the TLC7701 is undefined due to the
too-low supply voltage. After this voltage is reached, the TLC7701 output
is low until the voltage (Vccmin — defined by R1 and R2) is reached. The
RST/NMI input of the MSP430 is a reset input after the power up, so the
MSP430 CPU is inactive.
- After the reaching of the voltage Vccmin (and the expiration of the delay
time, trc), the MSP430 begins operation.
- If the supply voltage (VCC) drops below Vccmin due to a voltage dropout,
the RST/NMI input is pulled low, stopping the CPU.
- After the return of VCC and the expiration of the delay time trc, the RST/
NMI input is pulled high again and the CPU starts at the address contained
in the reset vector (0FFFEh).
- If a real power fail occurs, the RST/NMI input is held low until the voltage
region with undefined output is reached. This voltage is so low that CPU
operation is not possible.
Voltage Drop–out
Powerfail
RESET
Vcc
Vccmin
trc
trc
Vout
undefined
1
2
3
4
Figure 6–72. System Voltages With a Power Supply Supervisor
The threshold voltage Vccmin of the TLC7701 is:
6-278
5
The RESET Function
( )
R1
+1
R2
Vccmin = Vref ×
Where:
Vref
R2
Voltage of the internal voltage reference of the TLC7701:
+1.1 V
Resistor from SENSE input to GND. Nominal value:
100 kΩ to 200 kΩ
The delay trc after the return of VC is defined by the capacitor Ct shown in Figure 6–71. If this delay is not desired, capacitor Ct is omitted. The formula for
the delay time trc is:
trc = 21kΩ × Ct
6.6.3.4.2 TP3750 Supply Voltage Supervisor and Regulator
Figure 6–73 illustrates the use of a TPS7350 (regulator plus voltage supervisor), ensuring a highly reliable system initialization. The TPS7350 also allows
the use of the RST/NMI terminal of the MSP430 as described in section Battery
Check and Power Fail Detection. The RST/NMI terminal is used during normal
program operation as an NMI (non maskable interrupt) input. This gives the
possibility to save important data in an external EEPROM in case of power fail.
This is possible because the PG terminal outputs a negative signal starting at
VCC = 4.75 V, which allows a large number of activities until Vccmin of the
MSP430 (2.5 V) is reached.
Diode D, together with series resistor Rv and capacitor Cb allow the MSP430
system to bridge short voltage dropouts or disturbances of the supply voltage
Vsys. The diode (D) prevents the rapid discharge of Cb by the other peripherals
connected to Vsys and increases the possible active time for the MSP430 after
loss of Vsys.
Vsys (+7V to +24V)
D
TP73050
+5V
Rv
IN
OUT
SENSE
P0.6
Vcc
P0.0
VCb
PG
Clk
EEPROM
Data
RST/NMI
EN
Cb
IAM
MSP430
GND
10µF
Vss
0V
Figure 6–73. Power Supply From Other DC Voltages With a Voltage Regulator/Supervisor
On-Chip Peripherals
6-279
The RESET Function
6.6.4
Conclusion
It is an old truth that many difficulties are caused by the implementation of the
RESET sections of projects. The hardware of the MSP430 family is designed
to minimize these difficulties as much as possible without special considerations or external components. But when special circumstances exceed the
builtin capabilities of the MSP430, the solutions shown in this section may help
to significantly simplify the development phase of a project.
6-280
The Universal Timer/Port Module
6.7 The Universal Timer/Port Module
The Universal Timer/Port module consists of two independent parts that work
together for the measurement of resistors or voltages.
- Counter With Controller — two 8-bit counters, which may be connected
in series to get a 16-bit counter. In addition, there is a controller, a
comparator input CMPI, and a normal input CIN.
- Input/Output Port — five outputs (TP.0...TP.4) that can be switched to
Hi–Z and an I/O port, TP.5
Three different inputs are available with the module:
- The CIN input have a Schmitt trigger characteristic. It is normally used for
resistor measurements. The threshold voltages are the same as for the
other inputs (P0.x).
- The comparator input CMPI — which is used for the voltage measurement
— has a threshold voltage Vref(com) that is nominally 0.25 × Vcc with small
tolerances. The threshold voltage (Vref(com)) itself, is temperature independent. The input CMPI shares a terminal with an LCD select line and
must be switched by software to the input function. This input function is
valid until the next PUC.
- The I/O terminal TP.5, which may be used as a clock input or an enable
input.
Figure 6–74 shows the block diagram of the Universal Timer/Port module
On-Chip Peripherals
6-281
The Universal Timer/Port Module
2 x 8–Bit Counter or 1 x 16–BitCounter with Clock Frequency and Enable Control
ENB ENA
CIN
CMP
CMPI Vcc/4
Enable
Control
+
–
CPON
TPSSEL0
EN1
TPSSEL1 TPSSEL0
TP.0
TPD.0
TPE.0
TP.1
TPD.1
TPE.1
CMP
ACLK
MCLK
TPD.2
TPE.2
TP.3
TPD.3
TPE.3
TPIN.5
ACLK
MCLK
r/w
1
2
B16
Set_RC1FG
TPSSEL
ENA EN1 RC1FG
1
0 ENB
RC2FG EN1FG
Data Register
TPD
0
EN2
1
1
2
0
3
TPD.4
TPE.4
I/O Port
0
Control Register
TPCTL
8bit Counter
TPCNT1
TPSSEL3 TPSSEL2
TP.4
TPIN.5
CLK1
RC1
3
TP.2
TP.5
Set_EN1FG
TPIN.5
8bit Counter
CLK2 TPCNT2
r/w
RC2
Set_RC2FG
TPD.5
TPE.5
B16
TPD.5
CPON
Data Enable Register
TPE
TPSSEL
TPE.5
3
2
Counter with Controller
TPD.0
TPE.0
Control Registers
Figure 6–74. Block Diagram of the Universal Timer/Port Module
6.7.1
Universal Timer/Port Used as an Analog-to-Digital Converter
Applications of the Universal Timer/Port Module as an ADC are described in
section Analog-to-Digital Converters. This section shows other applications,
such as simple timers and similar functions.
6.7.2
Universal Timer/Port Used as a Timer
MSP430 family members that do not contain the Timer_A are equipped with
at least the Universal Timer/Port module, a combination of two 8-bit timers with
a common control unit. The Universal Timer/Port module is primarily regarded
as an ADC, but it is also able to handle timing tasks that are not excessively
complex. To get an interrupt request after a certain number of MCLK or ACLK
cycles, it is only necessary to load the negated number of clocks into the count
registers TPCNT1 and TPCNT2. When the 16-bit counter (used with the
MCLK) or one of the 8-bit counters (used with the ACLK) overflows to 0, the
RC2FG flag (or RC1FG flag) is set and an interrupt is requested. This method
allows precise timings for TRIAC control or PWM control in the range of 128 Hz
to 4000 Hz (repetition rate).
The Universal Timer/Port module can be used for:
6-282
The Universal Timer/Port Module
- Low frequency pulse width modulation: up to two independent PWM–out-
puts.
- Measurement of the MCLK frequency e.g. if used without crystal (see sec-
tion Use Without Crystal)
- Triggering: time measurement starting with the zero crossing of the mains
voltage
- Other time measurements
TPSSEL1 TPSSEL0
0
CMP
ACLK
MCLK
MCLK
7
0
15
8
1
Event Count
0
0
ACLK
0
1
MCLK
MCLK
1
0
1
1
2
Clk 8–bit Counter TPCNT1
3
EN1
RC1
Clk 8–bit Counter TPCNT2
EN2
RC2
Vcc
Carry:
Set RC2FG–Flag
LSB Data
MSB Data
Figure 6–75. Block Diagram of the Universal Timer/Port Module (16-Bit Timer Mode)
6.7.2.1
Continuous Mode
The Universal Timer/Port module can be used like the Timer_A in continuous
mode, allowing it to measure time differences. The 16-bit value is read out and
corrected if an overflow to 0 occurred between the readings of the low and high
bytes. The input frequency may be the ACLK or the MCLK.
; Read–out of the UTP/M running as a 16–bit timer
;
MOV.B
&TPCNT1,R5
; Read LSBs
00xx
MOV.B
&TPCNT2,R6
; Read MSBs
00yy
CMP.B
R5,&TPCNT1
; TPCNT1 still >= R5?
JHS
L$1
; Yes, no overflow
;
; Transition from 0FFh to 0 occured, read actual MSB;
; it now has the correct (value + 1).
;
L$1
MOV.B
&TPCNT2,R6
; Read actual MSBs
00yy
DEC.B
R6
; MSB – 1 is correct
SWPB
R6
; MSBs to high byte
ADD
R5,R6
; Build 16–bit value in R6 yyxx
yy00
On-Chip Peripherals
6-283
The Universal Timer/Port Module
6.7.2.2
Pulse Width Modulation Mode
Figure 6–76 shows the generation of low frequency PWM with the Universal
Timer/Port module. If the ACLK is used for the timing, then two PWM outputs
with up to 256 Hz are possible. The software is described in the paragraph
PWM Digital-to-Analog Converter with the Universal Timer/Port Module of
section Digital-to-Analog Converters.
0FFh
–n1
–n2
0h
∆t 2
∆ t1
∆t 2
∆t2 = n2/ACLK
∆ t1
∆t1 = n1/ACLK
Output
RC2FG
RC2FG
RC2FG
RC2FG
Interrupts
Figure 6–76. Low Frequency PWM Timing Generated With the Universal Timer/Port
Module
6-284
The Crystal Buffer Output
6.8 The Crystal Buffer Output
This is a relatively simple module, but it can be very helpful. It allows the use
of frequencies generated by the MSP430 for external modules without any influence to the accuracy of the crystal. Figure 6–77 shows an application with
two MSP430s. The right side MSP430 uses the buffered crystal output — @
32 kHz — of the left side MSP430. This allows both to be run with the accuracy
of a crystal controlled oscillator, but only one crystal is necessary. The right
side MSP430 uses the XBUF terminal for the output of the MCLK frequency
to drive an external ASIC.
32kHz
Xin
32kHz to Peripherals
Xout
XBUF
32kHz
Xin
XBUF
3.2MHz
CLK
ASIC
Xout
Voltage
A1
On
Data
16
Ports
Port2..3
MSP430C32x
Peripherals
MSP430
Current
A0
Vss
Port0
Control
Vcc
8
COM
SEL
Port0
Vss
Error
kW
kWh
Vcc
Figure 6–77. Two MSP430s Running From the Same Crystal
Only a single instruction is needed to implement the output of an internal frequency at the XBUF terminal:
; Hardware definitions for the Crystal Buffer
;
CBCTL
.equ
053h
; Crystal Buffer Control Byte
CBE
.equ
001h
; Enable XBUF output
CBACLK
.equ
000h
; ACLK is output at XBUF
CBACLK2
.equ
002h
; ACLK/2 is output at XBUF
CBACLK4
.equ
004h
; ACLK/4 is output at XBUF
CBMCLK
.equ
006h
; MCLK is output at XBUF
; Output the crystal frequency ACLK at pin XBUF
On-Chip Peripherals
6-285
The Crystal Buffer Output
;
MOV.B
#CBACLK+CBE,&CBCTL
; ACLK to XBUF pin
;
; Output the half crystal frequency ACLK/2 at pin XBUF
;
MOV.B
#CBACLK2+CBE,&CBCTL
; ACLK/2 to XBUF pin
;
; Output the crystal frequency ACLK divided by four at pin XBUF
;
MOV.B
#CBACLK4+CBE,&CBCTL
; ACLK/4 to XBUF pin
;
; Output the MCLK frequency at pin XBUF
;
MOV.B
#CBMCLK+CBE,&CBCTL
; MCLK to XBUF pin
As shown with the previous definitions, four different frequencies can be output
at terminal XBUF. With the CBE bit, these four frequencies can be enabled or
disabled. The four possible frequencies are:
- MCLK
The frequency of the system clock generator (DCO): 500 kHz
to 4MHz
- ACLK
The frequency of the crystal (normally 32768 Hz)
- ACLK/2
The halved crystal frequency (normally 16384 Hz)
- ACLK/4
The crystal frequency divided by 4 (normally 8192 Hz)
The crystal buffer control byte CBCTL is a write-only byte. This means the full
information must always be written to it. The following code sequence provides
an output of ACLK and not — as it is intended — to output the MCLK frequency:
; Switch off and on the MCLK at pin XBUF
;
MOV.B
#CBMCLK+CBE,&CBCTL ; MCLK to XBUF pin
BIC.B
#CBE,&CBCTL
; MCLK off
BIS.B
#CBE,&CBCTL
; WRONG: ACLK is output NOT MCLK
MOV.B
#CBMCLK+CBE,&CBCTL ; CORRECT: MCLK on again
;
6-286
The Crystal Buffer Output
Figure 6–78 shows an application with a DC/DC converter that is controlled
by the output frequency of the XBUF terminal. The converter is driven with the
frequency that fits best the actual status (8.192 kHz, 16.384 kHz or
32.768 kHz). The sequence starts with the high output frequency and steps
down after the buildup of the voltage to the 8 kHz frequency. No software overhead is necessary for the generation of this frequency.
32kHz
XIN XOUT
+8V
RF–Antenna
3V/1.6uA
L
Vcc
0V
+6V
Voltage
Regul.
CIN
Reference
TP.0
Room Temp.
TP.1
Heater Temp.
TP.2
Q1
C
Vss
P0.0
XBUF
Vcc
HF–
Modul
GND
Modulation (Data)
Mod.
32kHz/16kHz/8kHz
MSP430C31x
Keys
+
P0.4
+
P0.3
2
MBUS–
COM0–3
SEL
Error
Temp
P0.1/2
LCD
Figure 6–78. The Crystal Buffer Output Used for a DC/DC Converter
On-Chip Peripherals
6-287
The USART Module
6.9 The USART Module
The universal synchronous asynchronous receive/transmit communication interface (USART) — whose block diagram is shown in figure 6–79 — can work
in two different modes: the asynchronous mode and the synchronous mode.
This section describes the software routines usable for the asynchronous
mode (SCI, RS232).
Note:
It is recommended to also consult the data book MSP430 Family Architecture Guide and Module Library. The hardware-related information given
there is very valuable and complements the information given in this section.
The examples and the hardware definitions shown use the addresses of the
MSP430x33x. Future MSP430 family members may have different hardware addresses — especially for the I/O ports used.
The hardware features of the USART module substantially exceed the examples shown in this section. To get the USART running quickly, the UART mode
is recommended, with or without the interrupt capability. The most often used
features are included in the examples given.
Figure 6–79 shows the block diagram of the MSP430 USART module.
6-288
The USART Module
Receive Status
Receive Buffer URXBUF
SYNC
RXE
MM SYNC
Listen
0
1
1
0
SOMI
Receive Shift Register
SSEL1 SSEL0
0
1
2
UCLKI
ACLK
MCLK
MCLK
SYNC
SYNC
Baud Rate Generator
0
URXD
Baud Rate Register UBR
STE
3
SYNC
Baud Rate Generator
UCLKS
UTXD
WUT
1
Transmit Shift
Register
SIMO
0
TXWake
Transmit Buffer UTXBUF
CKPH
SYNC
CKPL
UCLKI
Control Registers
UCLK
Clock Phase & Polarity
UCLKS
Figure 6–79. The MSP430 Family USART Hardware
6.9.1
Introduction
This chapter gives a short overview to the use of the MSP430 universal synchronous, asynchronous receive/transmit communication interface (USART)
as an RS232 interface (also called serial controller interface, SCI). Tested software examples with and without the use of the interrupt capability are given
for the transmission and the reception of UART signals (universal asynchronous receive/transmit). Full duplex mode is used for all examples running in
the active mode and the low power mode 3 (LPM3).
If the USART is switched to the UART mode — made by setting the SYNC bit
UCTL.2 to 0 — then the hardware of figure 6–79 reduces to the parts used by
the UART as shown in figure 6–80.
On-Chip Peripherals
6-289
The USART Module
SYNC = 0
Receive Status
Receive Buffer URXBUF
RXE
Listen
0
Data
Receive Shift Register
URXD
1
SSEL1 SSEL0
Baud Rate Generator
UCLKS
0
UCLKI
ACLK
MCLK
MCLK
1
2
Baud Rate Register UBR
3
Baud Rate Generator
Data
Transmit Shift
Register
WUT
TXWake
LSB first
UTXD
Transmit Buffer UTXBUF
CKPL
UCLKI
Control Registers
UCLK
Clock Polarity
UCLKS
Figure 6–80. The USART Switched to the UART Mode
6.9.1.1
Definitions Used With the Application Examples
The abbreviations used for the hardware definitions are consistent with the
MSP430 Architecture User’s Guide, except for the stop bit definition (SP),
which is a predefined symbol of the MSP430 assembler for the system stack
pointer SP.
; HARDWARE DEFINITIONS
;
UCTL
.equ
070h
; USART Control Register
SWRST
.equ
001h
; 1: Software Reset 0: Run
SYNC
.equ
004h
; 1: UART Mode
0: SCI Mode
CHAR
.equ
010h
; 1: 8 Data Bits
0: 7 Data Bits
SP_
.equ
020h
; 1: 2 Stop Bits
0: 1 Stop Bit
6-290
The USART Module
PEV
.equ
040h
; 1: Even Parity
PENA
.equ
080h
; 1: Parity enabled 0: Parity dis.
0: Odd Parity
UTCTL
.equ
071h
; Transmit Control Register
TXEPT
.equ
001h
; 1: Transmitter empty
URXSE
.equ
008h
;
SSEL0
.equ
010h
; Clock Selection 0: Ext. Clock
SSEL1
.equ
020h
; 1: ACLK
URCTL
.equ
072h
; Receive Control Register
RXERR
.equ
001h
; 1: Receive Error 0: No Error
URXEIE
.equ
008h
; 1: all Char.
BRK
.equ
010h
; 1: Break detected 0: ok
OE
.equ
020h
; 1: Overrun Error
0: ok
PE
.equ
040h
; 1: Parity Error
0: ok
FE
.equ
080h
; 1: Frame Error
0: ok
UMCTL
.equ
073h
; Modulation Control Reg. m7..m0
UBR0
.equ
074h
; Baud Rate Register 0
UBR1
.equ
075h
; Baud Rate Register 1
URXBUF
.equ
076h
; Receive Buffer
UTXBUF
.equ
077h
; Transmit Buffer
IFG2
.equ
003h
; SFRs: Flags
URXIFG
.equ
001h
; Receive Flag IFG2.0
UTXIFG
.equ
002h
; Transmit Flag IFG2.1
IE2
.equ
001h
; SFRs: Interrupt Enable Bits
URXIE
.equ
001h
; Receive Intrpt Enable Bit IE2.0
UTXIE
.equ
002h
; Transmit Intrpt Enable Bit IE2.1
ME2
.equ
005h
; SFRs: Mode Enable Bits
URXE
.equ
001h
; Receiver Module Enable Bit ME2.0
UTXE
.equ
002h
; Transmitter Mod. Enable Bit ME2.1
.equ
01Fh
; Port4 Sel. Reg. (I/O <–> USART)
;
2,3: MCLK
;
0: only w/o Error
;
;
;
;
;
P4SEL
On-Chip Peripherals
6-291
The USART Module
URXD
.equ
080h
; Receive Input P4.7
UTXD
.equ
040h
; Transmit Output P4.6
SCG1
.equ
080h
; Low Power Mode bit 1
SCG0
.equ
040h
; Low Power Mode bit 0
CPUoff
.equ
010h
; Switches CPU off
GIE
.equ
008h
; General Interrupt Enable Bit
SCFQCTL
.equ
052h
; FLL multiplier and M bit
SCFI0
.equ
050h
; FLL current switches
FN_2
.equ
004h
; Switch for 2 MHz
FN_3
.equ
008h
; Switch for 3 MHz
FN_4
.equ
010h
; Switch for 4 MHz
;
;
6.9.1.2
MSP430 UART Attributes
A short overview to the USART running in the UART mode is given below:
- 7-bit and 8-bit data length is selectable
- Error detection for the receive path:
J
Frame error. The stop bits have space potential.
J
Parity error. Parity is enabled and the parity bit has the wrong value.
J
Overrun error. The next character is read in before the last one is read
out by the software.
J
Break detect. The URXD terminal has low potential for more than 10
bits
- Baud rate generation possible also from 32 kHz crystal due to the modula-
tion register
- Interrupt-driven transmit and receive functions
- Two independent interrupt vectors, one for transmit and one for receive
- Full functionality also during LPM3
- End-of-frame flag usable with interrupt or polling
6-292
The USART Module
6.9.1.3
Data Format
The RS232 data format is used. Figure 6–81 shows how this format is seen
at the MSP430 ports (URXD and UTXD) and Figure 6–82 how it is defined on
the transmission line. The format shown in Figures 6–81 and 6–82 is:
- Seven data bits. The least significant bit follows the start bit
- Parity enabled. The parity bit follows the most significant bit of the data
- No address bit. This is the normal case
- Two stop bits
Name
Signal Level
Data
”1”
Vcc
Mark
Start
Bit
LSB
MSB
Parity
Bit
Stop
Bits
Space
0V
”0”
Figure 6–81. The RS232 Format (Levels at the MSP430)
The signal on the transmission line has the inverted state as seen at the
MSP430 ports and different voltage potentials. Figure 6–82 shows this.
Name
Signal Level
Data
”0”
Space
>+3V
Start
Bit
LSB
Mark
MSB
Parity
Bit
Stop
Bits
<–3V
”1”
Figure 6–82. The RS232 Format (Levels on the Transmission Line)
6.9.1.4
UART Hardware Registers
The USART is controlled by seven control registers and one read-only register.
All are 8-bit registers and therefore should be accessed only with byte instrucOn-Chip Peripherals
6-293
The USART Module
tions. Figure 6–83 gives an overview to these eight registers including the
names, assembler mnemonics, hardware addresses and the initial states. The
register and bit definitions are contained in Section 6.9.1.
Register Name
Mnemonic Register Access
USART Control Register
UCTL
See below
UTCTL
Read/write
071h
See below
Receive Control Register
Modulation Control Reg.
URCTL
UMCTL
Read/write
Read/write
072h
073h
See below
unchanged
Baud Rate Register 0
Baud RateRegister 1
UBR0
UBR1
Read/write
Read/write
074h
075h
unchanged
unchanged
Receive Buffer
URXBUF
Read Only
076h
unchanged
Transmit Buffer
UTXBUF
Read/Write
077h
unchanged
7
PENA
rw–0
0
PEV
rw–0
SP
rw–0
CHAR
rw–0
Listen
rw–0
MM
SYNC
rw–0
rw–0
SWRST
rw–1
7
unused
rw–0
7
UBR0
CKPL
rw–0
SSEL SSEL0 URXSE TXWake unused TXEPT
1
rw–0
rw–0
rw–0
rw–0
rw–0 rw–1
7
074h
rw
26
rw
25
rw
24
rw
23
rw
22
rw
21
rw
20
rw
7
UBR1
0
215
075h
rw
0
URCTL
0
27
0
UTCTL
071
h
Initial State
070h
Transmit Control Register
UCTL
070h
Address
Read/write
214
rw
213
rw
212
rw
21
1
rw
210
rw
29
rw
28
rw
7
0
UMCTL
FE
072h
rw–0
PE
rw–0
OE
rw–0
BRK
rw–0
URXEIE URXWIE RXWake RXERR
rw–0
rw–0
rw–0
7
URXBUF
r
rw
0
27
076h
m7
073h
rw–0
26
r
25
r
24
r
23
r
22
r
21
r
20
m6
rw
m5
rw
m4
rw
m3
rw
m2
rw
m1
rw
m0
rw
7
UTXBUF
077h
r
0
27
rw
26
rw
25
rw
24
rw
23
rw
22
rw
21
rw
20
rw
Figure 6–83. USART Control Registers Used for the UART Mode
6.9.2
Baud Rate Generation
To generate the desired baud rate from a relatively high frequency (1 MHz to
5 MHz) is a simple task. The resulting baud rate error is small due to the large
integer part of the quotient compared to the truncated fractional part. This
changes completely if the timebase is a crystal of only 32 kHz. Then the error
due to the truncated fractional part of the quotient gets large and leads to the
loss of synchrony at the trailing bits of the frame. The MSP430 USART therefore uses a correction to keep the baud rate error small. The modulation register, UMCTL, contains 8-bit data to correct the baud rate of the received or
transmitted UART signal. The bits define how the predivider information contained in the two baud rate registers UBR0 and UBR1 is used:
- A 0 bit in the UMCTL register means that the information contained in
UBR1/UBR0 is used as is.
- A 1 bit means that the 16-bit content of UBR1/UBR0 is incremented by one
and used with this value. The content of UBR1/UBR0 is not changed.
6-294
The USART Module
0
7 0
7
UBR0
Start
UBR1
SSEL1 SSEL0
1
0
UCLK
ACLK
MCLK
MCLK
7
1 BRCLK
2
3
8
15
15bit Prescaler / Divider
Q1 ...................................... Q15
Toggle
FF
Compare 0 or 1
m
BITCLK
Shift Modulation Register Data
shift_out
shift_in
0
7
Modulation Register UMCTL
Start
H
L
BRCLK
H
L
Counter
n/2 n/2–1 n/2–2
1
1
1
0 n/2 n/2–1
n/2 n/2–1 n/2–2
n/2 n/2–1 n/2–2
2
1
1
1
0
0 n/2
n/2 n/2–1
n/2 n/2–1 n/2–2
H
BITCLK
L
Divide by
INT(n/2), m=0
INT(n/2)+m(=1)
n(even), m=0
n (odd) or n(even)+m(=1)
n(odd)+m(=1)
Figure 6–84. The Baud Rate Generator
The LSB (m0) of register UMCTL is used for the start bit, the next bit (m1) is
used for the LSB of the data, and so on. After the use of bit m7, the bit sequence m0 to m7 is used again. See figure 6–85 for an explanation.
Example 6–58. 4800 Baud from 32 kHz Crystal
The baud rate of 4800 is needed from a crystal frequency of 32,768Hz. This
is necessary because the UART also needs to run during the low power mode
3. With only the ACLK available, the theoretical division factor — the truncated
value is the content of the baud rate register UBR (UBR1/UBR0) — is:
On-Chip Peripherals
6-295
The USART Module
UBR =
32768
= 6.82667
4800
This means the baud rate register, UBR1, (MSBs) is loaded with 0 and the
UBR0 register contains 6. To get a rough value for the 8-bit modulation register,
UMCTL, the fractional part (0.826667) is multiplied by 8 (the number of bits in
the register UMCTL):
UMCTL = 0.82667 × 8 = 6.613
The rounded result, 7, is the number of 1s to be placed into the modulation register, UMCTL. The resulting, corrected baud rate with the UMCTL register containing seven 1s is:
BaudRate =
(
32768
7 ×7 + 1 × 6
8
)
= 4766.2545
This results in an average baud rate error of:
Baud Rate Error =
4766.2545–4800
× 100 = –0.703%
4800
To get the bit sequence for the modulation register, UMCTL, that fits best, the
following algorithm can be used. The fractional part of the theoretical division
factor is summed eight times and if a carry to the integer part occurs, the actual
m-bit is set. Otherwise it is cleared. An example with the above fraction
0.82667 follows:
Fraction Addition
Carry to next Integer
UMCTL
Bits
0.82667 + 0.82667 = 1.65333
Yes
m0
1
1.65333 + 0.82667 = 2.48000
Yes
m1
1
2.48000 + 0.82667 = 3.30667
Yes
m2
1
3.30667 + 0.82667 = 4.13333
Yes
m3
1
4.13333 + 0.82667 = 4.96000
No
m4
0
4.96000 + 0.82667 = 5.78667
Yes
m5
1
5.78667 + 0.82667 = 6.61333
Yes
m6
1
6.61333 + 0.82667 = 7.44000
Yes
m7
1
The result of the calculated bits m7...m0 (11101111b) is EFh with seven 1s. In
Section 6.9.3.3.2, a software macro (CALC_UMCTL) is contained that uses
the algorithm shown above. It calculates for every combination of the USART
clock and the desired baud rate, the optimum value for the modulation register,
UMCTL. For the above example, the algorithm also finds EFh with its seven
1s.
6-296
The USART Module
A second software macro (CALC_UBR) calculates the values for the two UBR
registers.
Example 6–59. 2400 Baud From 32 kHz ACLK
Figure 6–85 gives an example for a baud rate of 2400 generated with the ACLK
frequency (32,768 Hz). The data format for figure 6–85 is:
Eight data bits, parity enabled, no address bit, two stop bits. Figure 6–85
shows three different frames:
- The upper frame is the correct one with a bit length of 13.65333 ACLK
cycles (32,768/2400 = 13.65333)
- The middle frame uses a rough estimation with 14 ACLK cycles for the bit
length
- The lower frame shows a corrected frame using the best fit (6Dh) for the
modulation register.
It can be seen that the approximation with 14 ACLK cycles accumulates an error of more than 0.3 bit length after the second stop bit. The error of the corrected frame is only 0.011 bit length. The error of the crystal clock is not yet
included, but it adds to the above errors.
Vcc
Precise
Timing
Start
Bit
LSB
13.65
13.65
13.65
13.65
13.65
13.65
13.65
13.65
MSB
Parity
Bit
13.65
13.65
Stop
Bit(s)
13.65
13.65
0V
Rough
Approximation
Start
Bit
LSB
14
14
MSB
MSB
14
14
14
14
14
14
14
Parity
Bit
Stop
Bit(s)
14
14
14
Error
Corrected
Timing
UMCTL Bits (6Dh)
Start
Bit
LSB
14
13
14
14
13
14
14
13
m0
1
m1
0
m2
1
m3
1
m4
0
m5
1
m6
1
m7
0
Stop
Bit(s)
MSB Parity
Bit
14
13
m0
1
m1
0
14
m2
1
14
m3
1
Error
Figure 6–85. Baud Rate Correction Function
On-Chip Peripherals
6-297
The USART Module
Tables 6–33 and 6–34 contain the average errors (full frame) for the normally
used baud rates when produced with the described baud rate generation.
The software examples contain software MACROs that automatically insert
the correct values for the UBR registers and the modulation register, UMCTL.
The software MACROs — that do not need ROM or RAM — may be hidden
in the listing by a .mnolist assembler directive. See Section 6.9.3.3.2.
6.9.2.1
Baud Rate Generation With the MCLK
Table 6–33 shows the optimum values for the UBR and UMCTL registers. The
UART clock is the MCLK (1,048 MHz). The values for the UMCTL and
UBR1/UBR0 registers are calculated by the software MACROs in Section
6.9.3.3.2. The crystal error is not included.
Table 6–33 contains the following columns:
Baud Rate — The baud rate for the data exchange (transmit and receive use
the same baud rate)
Division Factor — The quotient UARTCLK/baud rate
UBR1/UBR0 Content — The truncated 16-bit hexadecimal result of the division factor (UARTCLK/baud rate). The value is calculated by the software
macro CALC_UBR. The high byte is the UBR1 value, the low byte is the UBR0
value
Calculated UMCTL Content — The 8-bit result that fits best for the modulation register. It is calculated by the software macro CALC_UMCTL.
Used Fraction — The number of 1s in the Modulation Register divided by
eight. It is an approximation to the truncated fractional part of the division factor.
Mean Error — The resulting error of a complete character caused by the
approximation to the division factor
6-298
The USART Module
Table 6–33. Baud Rate Register UBR Content (MCLK = 1,048 MHz)
BAUD
RATE
DIVISION
FACTOR
UBR1/UBR0
CONTENT
CALCULATED UMCTL
CONTENT
FRACTION
USED
MEAN
ERROR (%)
110
9532.51
253Ch
55h
0.5
+0.000
300
3495.25
0DA7h
44h
0.25
0.000
600
1747.63
06D3h
6Dh
0.625
+0.000
1200
873.81
0369h
EFh
0.875
–0.007
2400
436.91
01B4h
FFh
1.000
–0.002
4800
218.45
00DAh
AAh
0.50
–0.023
9600
109.23
006Dh
88h
0.25
–0.018
19200
54.61
0036h
ADh
0.625
–0.027
38400
27.31
001Bh
24h
0.25
+0.220
On-Chip Peripherals
6-299
The USART Module
6.9.2.2
Baud Rate Generation With the ACLK
With the relatively low ACLK frequency (32,768 Hz), the modulation register
UMCTL becomes much more important compared to the normally high MCLK
frequency used for the UART timing. Table 6–34 shows the optimum values
for the UBR and UMCTL registers for commonly used baud rates generated
with the ACLK (32,768 Hz). The table values are calculated by the MACROs
described in Section 6.9.3.3.2. The crystal is considered to be without frequency error. The table columns are described in Section 6.9.2.1.
Table 6–34. Baud Rate Registers UBR Content (ACLK = 32,768 Hz)
BAUD
RATE
6-300
DIVISION
FACTOR
UBR1/UBR0
CONTENT
CALCULATED UMCTL
CONTENT
FRACTION
USED
MEAN
ERROR (%)
110
297.8909
0129h
FFh
1.00
–0.04
300
109.2267
006Dh
88h
0.25
–0.02
600
54.6133
0036h
ADh
0.625
–0.02
1200
27.3067
001Bh
24h
0.25
+0.21
2400
13.6533
000Dh
6Dh
0.625
+0.21
4800
6.8267
0006h
EFh
0.875
–0.71
9600
3.4133
0003h
4Ah
0.375
+1.12
19200
1.7067
–
38400
0.8533
–
The USART Module
6.9.3
Software Routines
The following sections show proven software routines, subroutines, and software MACROs for the UART mode of the USART.
Note:
The program sequence for the initialization of the UART is important. As long
as the SWRST bit (UCTL.0) is set, the receive and transmit control registers
URCTL and UTCTL cannot be initialized. The program sequences given in
the software examples comply with this fact and are therefore recommended.
As long as the SWRST bit is set, the following control bits are held in the 0
state: TXWAKE, RXERROR, RXWAKE, BRK, OE, FE, PE, URXIFG, URXIE,
UTXIE.
The following control bits are held in the 1 state: UTXIFG, TXEPT
6.9.3.1
NonInterrupt Processing
The simplest way to use the USART is in the UART mode. The interrupt is not
enabled, the software checks if it is possible to output the next byte (UTXIFG
= 1) and it checks if a new character is received (URXIFG = 1).
Example 6–60. Full Duplex Modem
A full duplex UART software running without the use of the UART interrupt is
shown. It is designed for:
- Baud rate: 1200 baud
- The MCLK (1.048 MHz) is used for the UART clock
- Eight data bits
- Two stop bits
- Parity enabled with odd parity
- Receive of errorfree characters only
STACK
.equ
0600h
; Stack start address
;
; Definitions for the UART part: user defined
;
On-Chip Peripherals
6-301
The USART Module
Baudr
.equ
1200
; Baudrate is 1200 Baud
FLLMPY
.equ
32
; FLL multiplier for 1,048MHz
UARTCLK
.equ
FLLMPY*32768
; MCLK is used for UARTCLK
;
; The content for the UMCTL and UBR registers are calculated.
; The two software macros do not use RAM or ROM, they only
; define the variables CUMCTL, CUBR1 and CUBR0 for the
; UART registers UMCTL, UBR1 and UBR0
;
CALC_UMCTL
; Calc. Modulation Reg. content
CALC_UBR
; Calculate UBR1/UBR0 contents
.text
; Software start address
;
;
INIT
MOV
#STACK,SP
; Initialize Stack Pointer
CALL
#INITSR
; Init. FLL and RAM
...
; Proceed with initialization
;
; Initialize the UART: Odd parity, 8 data bits, 2 stop bits
; MCLK for UART clock
;
MOV.B
#CUMCTL,&UMCTL
; Modulation Register
MOV.B
#CUBR0,&UBR0
; Baud Rate Register low
MOV.B
#CUBR1,&UBR1
; Baud Rate Register high
BIS.B
#URXD+UTXD,&P4SEL ; Select RXD + TXD at Port4
BIS.B
#UTXE+URXE,&ME2
MOV.B
#PENA+SP_+CHAR,&UCTL ; USART Control Register
MOV.B
#SSEL1+SSEL0,&UTCTL ; Transmit Control Reg. MCLK
MOV.B
#0,&URCTL
...
; Enable USART Moduls
; Receive Control Register
; Continue with initialization
;
MAINLOOP ...
; Start Mainloop
;
; UART parts within the mainloop.
; The software checks these two parts regularly.
; UART Receive part:
6-302
The USART Module
; check if a new character is received
; R7 contains the received information.
BIT.B
#RXERR,&URCTL
; Error during receive?
JZ
L$3
; No
...
; Error handling
BIC.B
#FE+PE+OE+BRK+RXERR,&URCTL ; Clear error flags
JMP
L$2
; Continue in mainloop
BIT.B
#URXIFG,&IFG2
; Character received?
JZ
L$2
; No, proceed in mainloop
MOV.B
&URXBUF,R7,
; Yes, move character to R7
;
L$3
L$2
...
; Continue in mainloop
;
; UART Transmit part:
; check if the next character can be transmitted.
; R6 contains information to be transmitted.
;
L$1
BIT.B
#UTXIFG,&IFG2
; Transmit buffer empty?
JZ
L$1
; No, wait
MOV.B
R6,&UTXBUF
; Empty: move info to TX buffer
MOV.B
src,R6
; Next character to R6
...
BR
; Continue with mainloop
#MAINLOOP
; End of mainloop
;
; Interrupt Vectors
;
.sect
”INITVEC”,0FFFEh
; Reset Vector
.word
INIT
; Program Start Address
If the above software is to be used with the ACLK for the UART clock, then only
the following two source lines need to be modified:
UARTCLK
.equ
32768
; ACLK is used for UARTCLK
MOV.B
#SSEL0,&UTCTL
; Transmit Control Register ACLK
;
All other necessary modifications are made automatically by the macros
CALC_UMCTL and CALC_UBR.
On-Chip Peripherals
6-303
The USART Module
6.9.3.2
Interrupt Processing
This is the normal mode for the use of the UART. Interrupt is requested if the
general interrupt enable bit GIE (SR.3) is set and
- A character is transmitted and the transmit interrupt is enabled (IE2.1 = 1)
or
- A character is received and the receive interrupt is enabled (IE2.0 = 1)
Note:
If an error occurred during the reception of a character, then the error flags
of the Receive control register (PE, FE, BRK, and RXERR) must be reset
within the UART interrupt handler. Otherwise, the set error flags will block the
next interrupt. This is not the case for the overrun error flag OE.
6.9.3.2.1 MCLK Used for the UART Clock
The following example is for when the MCLK is used for the generation of the
UART clock or for external frequencies in the MCLK range (500 kHz to
3.8 MHz).
For high baud rates — higher than 38400 baud — dedicated CPU registers
may be necessary to lower the interrupt overhead. The time for the saving and
restoring of the register is not necessary. The software example shown in Section 6.9.3.2.2 uses dedicated registers.
Example 6–61. Full Duplex UART
Full duplex UART software using the two UART interrupts is shown. It is designed for:
- Baud rate: 19200 baud
- The MCLK (3.144 MHz) is used for the UART clock
- Seven data bits
- One stop bit
- Parity enabled with even parity
- Receive of errorfree characters only
Transmit Part — the start address xxxx is loaded into the pointer TXPOI and
the number of characters to be output is loaded into the character count
6-304
The USART Module
TXCNT. The interrupt routine outputs the programmed character sequence
starting at address xxxx.
Receive Part — the start address yyyy of a RAM buffer is loaded into the pointer RCPOI and the number of characters to be received is loaded into the character count RCCNT. The interrupt routine receives the characters and stores
them into the buffer. Only error-free characters are accepted.
STACK
.equ
0600h
; Stack start address
;
; Definitions for the UART part
;
Baudr
.equ
19200
; Baudrate is 19200 Baud
FLLMPY
.equ
96
; FLL multiplier for 3,144MHz
UARTCLK
.equ
FLLMPY*32768
; MCLK is used for UARTCLK
;
.even
; Word boundary
.bss
TXPOI,2
; Pointer to transmit buffer
.bss
RCPOI,2
; Pointer to receive buffer
.bss
TXCNT,1
; Counter/status for transmit
.bss
RCCNT,1
; Counter/status for receive
;
; The content for the UMCTL and UBR registers are calculated
; The two software macros do not use RAM or ROM
;
CALC_UMCTL
; Calculate Mod. Reg. content
CALC_UBR
; Calculate UBR1/UBR0 contents
.text
; Software start address
;
;
INIT
MOV
#STACK,SP
; Initialize Stack Pointer
CALL
#INITSR
; Init. FLL and RAM
...
; Proceed with initialization
;
; Initialize the UART: Even parity, 7 data bits, 1 stop bit
; MCLK for UART clock, only errorfree characters to URXBUF
;
MOV.B
#CUMCTL,&UMCTL
; Modulation Register
On-Chip Peripherals
6-305
The USART Module
MOV.B
#CUBR0,&UBR0
; Baud Rate Register low
MOV.B
#CUBR1,&UBR1
; Baud Rate Register high
BIS.B
#URXD+UTXD,&P4SEL ; Select RXD + TXD at Port4
BIS.B
#UTXE+URXE,&ME2
; Enable USART Moduls
MOV.B
#PENA+PEV,&UCTL
; USART Control Register
MOV.B
#SSEL1+SSEL0,&UTCTL ; Transmit Control Reg. MCLK
MOV.B
#0,&URCTL
BIS.B
#UTXIE+URXIE,&IE2 ; Enable USART interrupts
CLR.B
TXCNT
; Disable transmit
CLR.B
RCCNT
; Disable receive
; Receive Control Register
...
; Continue with initialization
EINT
; Enable interrupt
;
MAINLOOP ...
; Start of Mainloop
;
; Preparation for the reception of m bytes. The input
; buffer starts at address yyyy
;
L$1
TST.B
RCCNT
; Data input completed?
JNZ
L$1
; No, wait
MOV
#yyyy,RCPOI
; Buffer start address to RCPOI
MOV.B
#m,RCCNT
; Number of bytes to RCCNT
...
; Continue in mainloop
;
; Stop the reception of data. The currently received character
; is input completely
;
CLR.B
RCCNT
...
; Status to zero
; Continue
;
; Preparation for the transmission of n bytes starting at
; address xxxx. A check is made if the last transmit operation
; is really completed.
;
6-306
BIT.B
#TXEPT,&UTCTL
; Transmit part ready?
JZ
L$2
; No, buffers are not yet empty
The USART Module
;
L$2
MOV.B
#n–1,TXCNT
; Ready, init. byte count
MOV
#xxxx+1,TXPOI
; Init. transmit buffer pointer
MOV.B
xxxx,&UTXBUF
; First info byte to TX buffer
...
; Continue in background
;
; Stop the transmission of data. The currently sent character
; is transmitted completely
;
CLR.B
TXCNT
; Status to zero
...
;
; Interrupt Handlers
; Interrupt handler for the UART Receive part.
;
RCINT
RCRET
TST.B
RCCNT
; Reception allowed?
JZ
RCRET
; No, status is 0
BIT.B
#RXERR,&URCTL
; Error during receive?
JNZ
RCERR
; Yes
DEC.B
RCCNT
; No, Byte count –1
PUSH
R5
; Save R5
MOV
RCPOI,R5
; Pointer to buffer
MOV.B
&URXBUF,0(R5)
; Next byte to buffer
INC
R5
; To next buffer byte
MOV
R5,RCPOI
; Update pointer
POP
R5
; Restore R5
RETI
;
RCERR
...
BIC.B
; Error handling
#FE+PE+OE+BRK+RXERR,&URCTL ; Clear error flags
RETI
;
; Interrupt handler for the UART Transmit part.
;
TXINT
TST.B
TXCNT
; Something to transmit?
JZ
TXRET
; No, buffer is empty
On-Chip Peripherals
6-307
The USART Module
TXRET
DEC.B
TXCNT
PUSH
R5
; Byte count –1
MOV
TXPOI,R5
; Pointer to buffer
MOV.B
@R5+,&UTXBUF
; Next byte for output
MOV
R5,TXPOI
; Update pointer
POP
R5
RETI
; Interrupt Vectors
;
.sect
”SCIVEC”,0FFECh
; USART Interrupt Vectors
.word
TXINT
; Transmit Vector
.word
RCINT
; Receive Vector
.sect
”INITVEC”,0FFFEh
; Reset Vector
.word
INIT
; Program Start Address
6.9.3.2.2 ACLK Used for the UART Clock
The following example is for when the ACLK is used for the generation of the
UART clock or for external frequencies lower than 100 kHz. It is very similar
to that of Section 6.9.3.2.1. The ACLK can also be used as the UART clock.
See that section for details.
This section shows another approach, however. The CPU is normally off and
leaves the LPM3 only when the programmed number of received or transmitted characters is reached.
Example 6–62. Full Duplex UART With Interrupt
Full duplex UART software using the UART interrupt is shown. It is designed
for:
- Baud rate: 2400 baud
- The ACLK (32,768 Hz) is used for the UART clock
- Eight data bits
- Two stop bit
- Parity enabled with odd parity
- Receive of errorfree characters only
- The CPU normally uses the low power mode 3 (LPM3)
6-308
The USART Module
Transmit Part — the start address xxxx of the output sequence is loaded into
the pointer TXPOI and the number of characters m is loaded into the character
count TXCNT. The interrupt routine outputs the character sequence and when
TXCNT reaches 0 (output completed), it resets the CPUoff bit of the stored status register on the stack. This manipulation omits the return to LPM3 and initializes the next transmit sequence. R6 is exclusively used for the transmit part.
Receive Part — the start address yyyy of a RAM buffer is loaded into the pointer RCPOI and the number of characters n is loaded into the character count
RCCNT. The interrupt routine receives the characters and stores them in the
buffer until RCCNT reaches 0 (input completed). Then it resets the CPUoff bit
of the stored status register on the stack. This manipulation omits the return
to LPM3 and allows the processing of the received data. Only errorfree characters are accepted. R7 is exclusively used for the receive part.
STACK
.equ
0600h
; Stack start address
;
; Definitions for the UART part
;
Baudr
.equ
2400
; Baudrate is 2400 Baud
FLLMPY
.equ
64
; FLL multiplier for 2,096MHz
UARTCLK
.equ
32768
; ACLK is used for UARTCLK
.bss
TXCNT,1
; Counter/status for transmit
.bss
RCCNT,1
; Counter/status for receive
;
CALC_UMCTL
; Calculate Mod. Reg. content
CALC_UBR
; Calculate UBR1/UBR0 contents
.text
; Software start address
;
;
INIT
MOV
#STACK,SP
; Initialize Stack Pointer
CALL
#INITSR
; Init. FLL and RAM
...
; Proceed with initialization
;
; Initialize the UART: Odd parity, 8 data bits, 2 stop bits
; ACLK used for the UART clock
;
MOV.B
#CUMCTL,&UMCTL
; Modulation Register
On-Chip Peripherals
6-309
The USART Module
MOV.B
#CUBR0,&UBR0
; Baud Rate Register low
MOV.B
#CUBR1,&UBR1
; Baud Rate Register high
BIS.B
#URXD+UTXD,&P4SEL ; Select RXD + TXD at Port4
BIS.B
#UTXE+URXE,&ME2
MOV.B
#PENA+SP_+CHAR,&UCTL ; USART Control Register
MOV.B
#SSEL0,&UTCTL
; Transmit Contr. Reg. ACLK
MOV.B
#0,&URCTL
; Receive Control Register
BIS.B
#UTXIE+URXIE,&IE2 ; Enable USART interrupts
CLR.B
TXCNT
; Disable transmit
CLR.B
RCCNT
; Disable receive
; Enable USART Moduls
...
; Continue with initialization
EINT
; Enable interrupt (GIE = 1)
;
MAINLOOP ...
; Start Mainloop
;
; Preparation for the reception of m bytes. Buffer starts
; at address yyyy. R7 is a dedicated register for receive
;
L$1
TST.B
RCCNT
; Ready?
JNZ
L$1
; No, RCCNT > 0
MOV
#yyyy,R7
; Receive buffer start address
MOV.B
#m,RCCNT
; Number of bytes
...
;
; Stop the reception of data. The actually received character
; is input completely
;
CLR.B
RCCNT
; Status is zero
...
;
; Preparation for the transmission of n bytes starting at
; address xxxx. R6 is a dedicated register for transmit.
; The check for the empty TX buffer is faster, but needs more
; ROM bytes.
;
TST.B
6-310
TXCNT
; Ready for next characters?
The USART Module
JNZ
L$2
; No, TXCNT > 0
BIT.B
#UTXIFG,&IFG2
; TX part also ready?
JZ
L$2
; No, busy
MOV.B
#n–1,TXCNT
; Ready, init. byte count
MOV
#xxxx+1,R6
; Init. transmit buffer pointer
MOV.B
xxxx,&UTXBUF
; First info byte to TX buffer
;
L$2
...
; Continue in background
;
; Stop the transmission of data. The actually sent character
; is transmitted completely
;
CLR.B
TXCNT
; Status is zero
...
;
; After the completion of all tasks, the program enters LPM3
;
PLPM3
BIS
#CPUoff+GIE+SCG1+SCG0,SR
; Enter LPM3
;
; An interrupt handler cleared the CPUoff bit on the stack.
; Checks are made if activity is needed:
: Receive:
receive input buffer full
; Transmit:
transmit buffer output completely
; ...
other interrupt handlers
;
TST.B
RCCNT
; Receive completed?
JZ
PROCRC
; Yes, process received data
TST.B
TXCNT
; Transmit completed?
JZ
NXTTX
; Yes, prepare next characters
...
JMP
; Other handlers?
PLPM3
; Back to LPM3
;
; Interrupt Handlers
; Interrupt handler for the UART Receive part. R7 is used
; only for the receive part
;
On-Chip Peripherals
6-311
The USART Module
RCINT
RCRET
TST.B
RCCNT
; Reception allowed?
JZ
RCRET
; No, status is 0
BIT.B
#RXERR,&URCTL
; Error during receive?
JNZ
RCERR
; Yes
DEC.B
RCCNT
; Byte count –1
MOV.B
&URXBUF,0(R7)
; Next byte to buffer
INC
R7
; To next buffer byte
TST.B
RCCNT
; Buffer filled?
JNZ
RCRET
; No, proceed
BIC
#CPUoff+SCG1+SCG0,0(SP) ; Active Mode after RETI
RETI
;
RCERR
...
BIC.B
; Error handling
#FE+PE+OE+BRK+RXERR,&URCTL ; Clear error flags
RETI
;
; Interrupt handler for the UART Transmit part. R6 is used
; only for the transmit part
;
TXINT
TXRET
TST.B
TXCNT
; Something to transmit?
JZ
TXRET
; No, buffer is empty
DEC.B
TXCNT
; Byte count –1
MOV.B
@R6+,&UTXBUF
; Next byte for output
TST.B
TXCNT
; Buffer output?
JNZ
TXRET
; No, proceed
BIC
#CPUoff+SCG1+SCG0,0(SP) ; Active Mode after RETI
RETI
;
; Interrupt Vectors
;
6-312
.sect
”SCIVEC”,0FFECh
; USART Interrupt Vectors
.word
TXINT
; Transmit Vector
.word
RCINT
; Receive Vector
.sect
”INITVEC”,0FFFEh
; Reset Vector
.word
INIT
; Program Start Address
The USART Module
6.9.3.3
Subroutines and .MACROs
The subroutines and assembler .MACROs used with the previous examples
are contained in this section.
6.9.3.3.1 Subroutines
The initialization subroutine INITSR — which is explained in detail in the section Timer_A — checks first if a power-up clear (PUC) or a power-on reset
(POR) has occurred:
- Power-Up Clear — the supply voltage is switched on, the RAM is cleared
- Power-On Reset — a reset occurred (RST/NMI terminal or by watchdog)
the RAM is not changed
The two situations are distinguished by the content of the word INITKEY. If it
contains 0F05Ah, the power-on reset state is assumed. Otherwise the power–
up clear state is assumed.
The subroutine selects the correct current switch FN_x for the system clock
generator and waits 30000 clock cycles to ensure that it has locked at the correct oscillator tap.
; Common Initialization Subroutine
; Check the INITKEY value first:
; If value is 0F05Ah: a reset occurred, RAM is not cleared
; otherwise Vcc was switched on: complete initialization
;
INITSR
CMP
#0F05Ah,INITKEY
; PUC or POR?
JEQ
IN0
; Key is ok, continue program
CALL
#RAMCLR
; Restart completely: clear RAM
MOV
#0F05Ah,INITKEY ; Define “initialized state”
MOV.B
#FLLMPY–1,&SCFQCTL ; Define MCLK frequency
.if
FLLMPY < 48
; Use the right DCO current:
MOV.B
#0,&SCFI0
; MCLK < 1.5MHz: FN_x off
.if
FLLMPY < 80
; 1.5MHz < MCLK < 2.5MHz?
MOV.B
#FN_2,&SCFI0
; Yes, FN_2 on
;
IN0
;
.else
On-Chip Peripherals
6-313
The USART Module
.else
;
.if
FLLMPY < 112
; 2.5MHz < MCLK < 3.5MHz?
MOV.B
#FN_3,&SCFI0
; Yes, FN_3 on
#FN_4,&SCFI0
; MCLK > 3.5MHz: FN_4 on
MOV
#10000,R5
; Allow the FLL to settle
DEC
R5
; at the correct DCO tap
JNZ
IN1
; during 30000 cycles
.else
MOV.B
.endif
.endif
.endif
;
IN1
RET
; Return from initialization
;
; Subroutine for the clearing of the RAM block
;
.bss
INITKEY,2,0200h
; 0F05Ah: initialized state
RAMSTRT
.equ
0200h
; Start of RAM
RAMEND
.equ
05FEh
; Highest RAM address (33x)
RAMCLR
CLR
R5
; Prepare index register
RCL
CLR
RAMSTRT(R5)
; 1st RAM address
INCD
R5
; Next word address
CMP
#RAMEND–RAMSTRT+2,R5 ; RAM cleared?
JLO
RCL
;
RET
6-314
; No, once more
; Yes, return
The USART Module
6.9.3.3.2 .MACROs
The following two software macros calculate the values for the UART baud
rate generator that fit best. They do not use ROM or RAM — they only define
the three variables CUBR1, CUBR0, and CUMCTL that are used during the
initialization of the UART registers UBR1, UBR0, and UMCTL.
.mnolist
; Do not list macro calls
;
; The values for the Modulation Registers UBR1/UBR0 are
; calculated: CUBR1 and CUBR0 contain the truncated result
; of the division UARTCLK/Baudr
;
CALC_UBR .macro
CUBR1
.equ
UARTCLK/(Baudr*256)
; Baud Rate Reg. High
CUBR0
.equ
(UARTCLK/Baudr)–256*CUBR1 ; Baud Rate Reg. Low
.endm
The calculation for the content of the Modulation Register UMCTL follows.
Seven bits of resolution are used.
CALC_UMCTL
.macro
;
; Modulation Register content: the rounded fraction of
; CMOD = UARTCLK/Baudr
is calculated
; Binary format of CMOD: 0.xxxxxxx
; Then the 8 bits of UMCTL are built.
; Inputs:
UARTCLK, Baudr
; Frequencies [Hz]
; Output:
CUMCTL
; 8–bit UMCTL register value
;
CMOD .equ
M$00
((((256*UARTCLK)/Baudr)–256*(UARTCLK/Baudr))+1)/2
.equ
CMOD+CMOD
; Fraction x 2
.if
M$00>127
; Overflow to integer?
M$10
.equ
M$00–128+CMOD
; Yes, subtract 1.000000
C$0
.equ
1
; UMCTL.0 = 1
.else
M$10
.equ
M$00+CMOD
; No, add fraction
C$0
.equ
0
; UMCTL.0 = 0
On-Chip Peripherals
6-315
The USART Module
.endif
.if
M$10>127
; Overflow to integer?
M$20
.equ
M$10–128+CMOD
; Yes, subtract 1.000000
C$1
.equ
2
; UMCTL.1 = 1
.else
M$20
.equ
M$10+CMOD
; No, add fraction
C$1
.equ
0
; UMCTL.1 = 0
.if
M$20>127
; Overflow to integer?
.equ
M$20–128+CMOD
; Yes, subtract 1.000000
.equ
4
; UMCTL.2 = 1
.endif
M$30
C$2
.else
M$30
.equ
M$20+CMOD
; No, add fraction
C$2
.equ
0
; UMCTL.2 = 0
.if
M$30>127
; Overflow to integer?
M$40
.equ
M$30–128+CMOD
; Yes, subtract 1.000000
C$3
.equ
8
; UMCTL.3 = 1
.equ
M$30+CMOD
; No, add fraction
.equ
0
; UMCTL.3 = 0
.if
M$40>127
; Overflow to integer?
M$50
.equ
M$40–128+CMOD
; Yes, subtract 1.000000
C$4
.equ
10h
; UMCTL.4 = 1
.endif
.else
M$40
C$3
.endif
.else
M$50
.equ
M$40+CMOD
; No, add fraction
C$4
.equ
0
; UMCTL.4 = 0
.if
M$50>127
; Overflow to integer?
M$60
.equ
M$50–128+CMOD
; Yes, subtract 1.000000
C$5
.equ
20h
; UMCTL.5 = 1
.endif
.else
M$60
.equ
M$50+CMOD
; No, add fraction
C$5
.equ
0
; UMCTL.5 = 0
.endif
6-316
The USART Module
.if
M$60>127
; Overflow to integer?
M$70
.equ
M$60–128+CMOD
; Yes, subtract 1.000000
C$6
.equ
40h
; UMCTL.6 = 1
.equ
M$60+CMOD
; No, add fraction
.equ
0
; UMCTL.6 = 0
.if
M$70>127
; Overflow to integer?
.equ
80h
; UMCTL.7 = 1
0
; UMCTL.7 = 0
.else
M$70
C$6
.endif
C$7
.else
C$7
.equ
.endif
CUMCTL
.equ
C$7+C$6+C$5+C$4+C$3+C$2+C$1+C$0 ; Add bits
.endm
On-Chip Peripherals
6-317
The 8-Bit Interval Timer/Counter
6.10 The 8-Bit Interval Timer/Counter
6.10.1 Introduction
The 8-Bit Interval Timer/Counter peripheral is included in all members of the
MSP430x3xx family. This timer/counter — its block diagram is shown in Figure
6–86 — can work, like its name suggests, in two different modes: the timer
mode and the counter mode. This section describes software routines usable
for the UART mode (SCI, RS232) that use the timer mode of the 8-Bit Timer/
Counter. The software examples shown in the subsequent sections adapt
themselves to the needs defined by the user (number of data bits, number of
stop bits, baud rate, error detection and handling, clock frequency, and so on).
This self-adaptation is accomplished through the use of the conditional assembly feature of the MSP430 assembler.
The hardware of the 8-Bit Interval Timer/Counter module supports the receive
and transmit of UART data on a bit basis: one data bit is received or transmitted
between two interrupts, not a complete frame consisting of a start bit, data bits,
a parity bit and stop bits. This means that the interrupt overhead is relatively
large due to the interrupt request after each received or transmitted data bit.
On the other hand, the advantage is the complete flexibility of the data format
— only software defines the number and meaning of the transferred bits. Any
protocol is possible.
Figure 6–86 shows the block diagram of the complete MSP430 8-Bit Interval
Timer/Counter module.
The 8-Bit Interval Timer/Counter module allows only the half duplex mode.
This means that the module can receive data or it can transmit data, but not
receive and transmit data simultaneously. The user software must therefore
determine which mode should be active. In the following software examples,
this is accomplished by the initialization subroutines.
6-318
The 8-Bit Interval Timer/Counter
P0IES.1
Interrupt
request
IRQP0.1
P0IE.1
A
P0.1
Receive
1
_
1
P0IFG.1
Set
Q
Clear
_
1
1
Bus Grant
G1
ISCTL
P0.1 – 8bT/C Interrupt Logic
TCDAT
044h
TCPLD
043h
8b
8b
Carry
+
D
C
o
u
n
t
e
r
Enable
Q
Clear
Edge
detect
Load
’Write’ to TCDAT
MDB
Pre–
8
load
reg.
Clk
8
0
1
2
3
MCLK
ACLK
TCCTL
042h
SSEL1
A
P0DIR.2
ISCTL
P0OUT.2
ENCNT
EN1
EN2
P0.2
Transmit
MSB
SSEL0
B
TXE
8
RXACT
PUC
TXD
Set
RXD
Q
D
D
Q
Set
TXD_FF
RXD_FF
PUC
Data
Data
LSB
Interval/Timer
Control Register
Figure 6–86. MSP430 8-Bit Interval Timer/Counter Module Hardware
6.10.1.1 Definitions Used With the Application Examples
The abbreviations used for the hardware definitions are consistent with the
MSP430 Architecture User’s Guide.
; HARDWARE DEFINITIONS
; 8–BIT TIMER/COUNTER
;
TCCTL
.equ
042h
; T/C Control Register
RXD
.equ
001h
; Receive signal at P0.1
TXD
.equ
002h
; Next data bit for transmission
On-Chip Peripherals
6-319
The 8-Bit Interval Timer/Counter
RXACT
.equ
004h
; 1: detect start bit
ENCNT
.equ
008h
; Counter TCDAT enabled
0: off, reset FF
TXE
.equ
010h
; 1: TXD to P0.2
ISCTL
.equ
020h
; Intrpt source:
0: P0.1
SSEL0
.equ
040h
; Clock source.
0: P0.1
SSEL1
.equ
080h
; 1: MCLK
.equ
043h
; T/C 8–Bit Pre–load Register
.equ
044h
; T/C 8–Bit Counter
0: P0OUT.2 to P0.2
2: ACLK
1: Carry TCDAT
3: P0.1 .and. MCLK
;
TCPLD
;
TCDAT
;
; OTHER DEFINITIONS
;
IE1
.equ
0
; Interrupt Enable Register 1
P0IE1
.equ
8
; P0.1 Interrupt Enable Bit (RCV)
P0IES
.equ
014h
; P0 Interrupt Edge Select Register
SCG1
.equ
080h
; Low Power Mode bit 1
SCG0
.equ
040h
; Low Power Mode bit 0
CPUoff
.equ
010h
; Switches CPU off
GIE
.equ
008h
; General Interrupt Enable Bit
;
6.10.1.2 Attributes of a UART Implemented with the 8-Bit Timer/Counter
A short overview to the UART mode of the 8-Bit Timer/Counter module appears below:
- Half duplex mode — either transmit or receive mode is possible, but not
both simultaneously.
- Any data length and format is possible. This is due to the software con-
trolled data sequence.
- Error detection made by software:
6-320
J
Frame error — The stop bits have space potential or the start bit has
mark potential in its middle
J
Parity error — Parity is enabled and the parity bit has the wrong value.
J
Overrun error — The next character is read in before the last one is
read out by the software. This is not possible with the given software.
The 8-Bit Interval Timer/Counter
- Baud rate generation possible from the MCLK (500 kHz through 3.3 MHz)
and from the ACLK signal (32,768 kHz crystal).
- Interrupt-driven transmit and receive functions.
- One interrupt vector for transmit and receive mode. Mode selection is
made by software.
- Full functionality also during LPM3 (with ACLK only)
- Restricted baud rate range due to the length of the 8-Bit counter register
TCDAT
- One full bit length (1/baud rate) is available for the read out or modification
of the data. The time window for the reception and transmission of data
is significantly enlarged compared to a pure software solution.
6.10.1.3 The Data Format
The data format used with the software examples is the RS232 format. Figure
6–87 shows how this format is seen at the MSP430 ports (P0.1 for receive and
P0.2 for transmit) and Figure 6–88 shows how it is defined for the transmission
line between the transmitter and the receiver.
The data format used with the Figures 6–87 and 6–88 is:
- Seven data bits. The least significant bit follows the start bit
- Parity enabled. The parity bit follows the most significant bit of the data
- No address bit. This is the normal case
- Two stop bits
Name
Signal Level
Data
”1”
Vcc
Mark
Start
Bit
LSB
MSB
Parity
Bit
Stop
Bits
Space
0V
”0”
Figure 6–87. RS232 Format (Levels at the MSP430)
On-Chip Peripherals
6-321
The 8-Bit Interval Timer/Counter
The signal on the transmission line has the inverted state as seen at the
MSP430 ports and different voltage potentials. Figure 6–88 shows this.
Name
Signal Level
Data
”0”
Space
>+3V
Start
Bit
LSB
MSB
Mark
Parity
Bit
Stop
Bits
<–3V
”1”
Figure 6–88. The RS232 Format (Levels on the Transmission Line)
6.10.2 Function of the UART Hardware
6.10.2.1 The Hardware Registers
The 8-Bit Timer/Counter module is controlled by one control register and two
data registers. All are 8-bit registers and should therefore be accessed only
with byte instructions. Figure 6–89 and Table 6–35 show an overview of these
three registers, including the names, assembler mnemonics, hardware addresses, and the initial states. The detailed function of the control bits is described in the MSP430 Architecture Guide and Module Library.
Note:
When a write access to the Counter Register TCDAT is performed, then the
information stored in the Preload Register TCPLD is loaded to TCDAT — and
not the data addressed by the instruction.
The data contained in TCDAT can be read at address 044h.
Table 6–35. UART Hardware Registers
6-322
REGISTER NAME
MNEMONIC
ACCESS
ADDRESS
T/C Control Register
TCCTL
Read/Write
042h
INITIAL STATE
Reset
T/C Preload Register
TCPLD
Read/Write
043h
Unchanged
T/C Counter Register
TCDAT
Read Only
044h
Unchanged
The 8-Bit Interval Timer/Counter
7
TCCTL
042h
0
SSEL1
SSEL0
rw–0
rw–0
ISCTL
TXE
rw–0
rw–0
ENCNT
RXACT
rw–0
rw–0
TXD
rw–0
7
RXD
r(–1)
0
TCPLD
043h
rw
rw
rw
rw
rw
rw
rw
7
rw
0
TCDAT
044h
r(w)
r(w)
r(w)
r(w)
r(w)
r(w)
r(w)
r(w)
Figure 6–89. UART Hardware Registers
On-Chip Peripherals
6-323
The 8-Bit Interval Timer/Counter
6.10.2.2 The Transmit Mode
If the 8-Bit Timer/Counter module is switched to the transmit mode — done by
the initializing software of the module — then the hardware of figure 6–86
works as shown in Figure 6–90. Active data lines are drawn solid, nonactive
data paths are drawn in gray color. The MCLK is selected for the UART timing.
P0IES.1
P0IE.1
Interrupt
Request
IRQP0.1
A
Receive
P0.1
1
_
1
Not active: Half Duplex
P0IFG.1
Set
Q
Clear
Bus Grant
_
1
1
ISCTL
MDB
G1
P0.1 – 8bT/C Interrupt Logic
8b
Carry
+
D
Enable
Q
Clear
Edge
detect
8b
C
o
u
n
t
e
r
Load
Pre–
8
load
reg.
Clk
’Write’ to TCDAT
8
0
1
2
3
MCLK
ACLK
A
SSEL1
B
SSEL0
P0DIR.2
Transmit
Data
P0.2
EN1
EN2
ISCTL
RXACT
Q
Set
TXD
D
D
Q
RXD
Set
TXD_FF
Figure 6–90. The 8-Bit Timer/Counter Transmit Mode
6-324
1
ENCNT
PUC
RXD_FF
PUC
MSB
1
1
TXE
P0OUT.2
1
8
0 –> 1
0
Data
X
LSB
Interval/Timer
Control Register
The 8-Bit Interval Timer/Counter
Initialization for the transmit mode is done by the subroutine TXINIT. The main
steps for the transmission of a character are:
- Loading of the data word RTDATA with the character to be transmitted, in-
cluding the address bit information (if defined)
- Initializing of the 8-Bit Timer/Counter and the RAM bytes RTERR and
RTSTAT
J
Selecting of the clock frequency for the counter TCDAT (MCLK or
ACLK) (SSELx bits)
J
Activation of the interrupt request by the carry of the 8-bit counter register TCDAT (ISCTL = 1)
J
Selecting of the TXD output data instead of the P0.2 output register
data for the P0.2 pin (TXE = 1)
J
Setting of the TXD bit to mark (1) (TXD = 1). This value is transferred
to the TXD output with the first counter interrupt. It guarantees a leading mark signal of at least one bit time.
J
Enabling of the 8-Bit Timer/Counter: the counter starts with the selected clock (ENCNT = 1)
J
Loading of the counter with one half of a bit time. After this time interval, the TXD output is set to mark (1) if not yet set
J
Loading of the pre-load register TCPLD with a full bit time interval
(1/baud rate). This time interval is used for the leading mark before the
start bit
J
Loading of the transmit status byte RTSTAT with the status for the start
bit
J
Loading of the error byte RTERR with a start value (0 resp. 1) that delivers the correct parity bit of the complete character
J
Enabling of the interrupt for the 8-Bit Timer/Counter. Interrupt is requested now approximately after each time interval 1/baud rate. This
time can change from bit to bit. See Section 6.10.3 Baud Rate Generation and Correction.
- Loading of the TXD bit during the interrupt handler with the information of
the next but one bit to be output (start bit, data bits, address bit, parity bit,
stop bits)
- Sampling of the information for the parity bit, if parity is enabled.
- Output of the nondata signals (start bit, parity bit, stop bits) dependent on
the selected format
On-Chip Peripherals
6-325
The 8-Bit Interval Timer/Counter
- Turning off of the hardware after the complete output of a character, to
save energy.
Undefined
if not initialized
Start
Bit
LSB
C$0
C$1
C$0
MSB Parity
Bit
C$2
C$3
C$4
C$5
C$6
C$7
C$8
C$9
Stop
Bit(s)
C$10
C$11
Initialization
1/(2 x Baud Rate)
Used Correction Bit
Figure 6–91. Interrupt Timing for the Transmit Mode
6-326
Interrupt: Program Parity Bit
Disable UART Interrupt
The 8-Bit Interval Timer/Counter
6.10.2.3 The Receive Mode
If the 8-Bit Timer/Counter module is switched to the receive mode — done by
the initializing software of the module — then the hardware of Figure 6–86
works like shown in Figure 6–92. As with Figure 6–90, active data lines are
drawn solid, nonactive data paths are drawn in gray color. The ACLK is used
for the UART timing.
P0IES.1
Interrupt
request
IRQP0.1
P0IE.1
A
Receive
P0.1
1
_
1
Data
P0IFG.1
Set
Q
Clear
_
1
1
Bus Grant
G1
ISCTL
MDB
P0.1 – 8bT/C Interrupt Logic
8b
Carry
+
D
Enable
Q
Clear
Edge
detect
8b
C
o
u
n
t
e
r
Load
’Write’ to TCDAT
Pre–
8
load
reg.
Clk
8
0
1
2
3
MCLK
ACLK
SSEL1
A
P0DIR.2
Transmit
P0.2
SSEL0
B
ISCTL
EN1
EN2
X
ENCNT
RXACT
Not active: Half Duplex
PUC
Q
Set
TXD
D
D
Q
RXD
Set
TXD_FF
RXD_FF
PUC
MSB
1
1
TXE
P0OUT.2
1
8
0
0/1
X
Data
LSB
Interval/Timer
Control Register
Figure 6–92. The 8–Bit Timer/Counter in Receive Mode
On-Chip Peripherals
6-327
The 8-Bit Interval Timer/Counter
Initialization for the receive mode is done by the subroutine RCINIT. The main
steps for the reception of a character are:
- Initializing of the 8-Bit Timer/Counter and the RAM bytes RTERR and
RTSTAT:
J
Selecting the clock frequency for the counter (MCLK or ACLK)
(SSELx bits)
J
Activation of the interrupt request by the carry of the 8-bit counter Register TCDAT (ISCTL = 1)
J
Reset of the edge-detect flip-flop (RXACT = 0)
J
Preparing of the 8-Bit Timer/Counter to start with the next negative
transition of the P0.1 input signal from mark to space (1 to 0). The
counter starts with the selected clock signal (ACLK or MCLK) after the
next negative transition. (P0IES.1 = 1)
J
Loading of the counter with one half of a bit time. (If an input signal
change at P0.1 occurs from mark to space, then after this time interval
an interrupt is requested and the start signal is checked in its middle if
it is still low (0).)
J
Loading of the pre-load Register TCPLD with a full bit time interval
(1/baud rate). This time interval is used for the test in the middle of the
LSB
J
Loading of the receive status byte RTSTAT with the status for the start
bit
J
Loading of the error byte RTERR with a start value that delivers 0 if the
parity of the complete character is correct
J
Enabling of the interrupt for the 8-Bit Timer/Counter. Interrupt is requested now approximately after the time interval 1/baud rate. This
time changes slightly from bit to bit. See Section 6.10.3 Baud Rate
Generation and Correction.
J
Setting the data word RTDATA to 0.
J
Activation of the edge-detect flip–flop: it detects the negative edge of
the start bit and starts the counter (RXACT = 1).
J
Enabling of the UART interrupt (P0IE1 = 1).
- Reading of the RXD bit during the interrupt handler with the information
of all bits (start bit, data bits, address bit, parity bit, stop bits). The read information is shifted into the data word RTDATA.
- Sampling of the information for the parity bit, if parity is enabled.
6-328
The 8-Bit Interval Timer/Counter
- Check of the nondata signals (start bit, parity bit, stop bits), dependent on
the selected format
- Setting of the error bits TCPE and TCFE dependent on the bit check. If no
error occurred, the error byte RTERR contains 0
- Turning off of the timer/counter hardware after the complete reception of
a character: interrupt and clock are switched off.
Start
Bit
MSB Parity
Bit
LSB
Stop
Bit(s)
Initialization
C$0
C$1
C$2
C$3
C$4
C$5
C$6
C$7
C$8
C$9
C$10
C$11
ts
1/(2 x Baud Rate)
Interrupt in Middle
of the Start Bit
Disable UART Interrupt
Used Correction Bit
Interrupt: Program Time Interval ts
Figure 6–93. Interrupt Timing for the Receive Mode
On-Chip Peripherals
6-329
The 8-Bit Interval Timer/Counter
6.10.3 The Baud Rate Generation and Correction
The short counter register TCDAT of the 8-bit timer/counter allows the use of
the MCLK for only very few baud rates. For all other baud rates, the maximum
value 255 for the quotient MCLK/baud rate is exceeded. Therefore, the use of
the ACLK (32,768 Hz) is necessary for most of the usual baud rates. But the
use of the ACLK frequency causes another problem:
Generating the desired baud rate from a relatively high frequency (1 MHz to
5 MHz) is a simple task. The resulting baud rate error is small due to the large
integer part of the quotient compared to the truncated fractional part. This
changes completely if the time base is a crystal of only 32 kHz. Then the error
due to the truncated fractional part of the quotient grows large and leads to the
loss of synchrony at the trailing bits of the frame. The MSP430 UART software
therefore uses a correction to keep the baud rate error small. The baud rate
correction calculates correction information (9 to 13 bits, dependent on the
frame length) as to how to correct the baud rate of the received or transmitted
UART signal. The calculated bits C$0 to C$12 define how the predivider information contained in the baud rate registers TCPLD and TCDAT is used:
- C$x = 0 — the calculated time interval is used as is.
- C$x = 1 — the calculated time interval is prolonged by one timer period
(MCLK or ACLK) and used with this value.
The value C$0 is used for the start bit, the value C$1 for the LSB of the data,
and so on. See Figure 6–94 for an explanation.
Example 6–63. Baud Rate Generation
A baud rate of 2400 baud is needed from a crystal frequency of 32,768 Hz. The
frame length used is the minimum length: start bit, seven data bits, no address
bit, no parity, and one stop bit. This results in a frame length of nine bits. The
use of the ACLK is necessary due to two reasons:
- The UART also needs to run during the low power mode 3, when the
MCLK is not available.
- The maximum MCLK frequency would be 255 × 2400 = 612 kHz. This fre-
quency is too low for most of the applications (and cannot be guaranteed
for the system clock generator).
With only the ACLK available, the theoretical division factor UBR — the truncated value is the base for one of the two contents of the Pre–Load Register
TCPLD — is:
UBR =
6-330
32768
= 13.653333
2400
The 8-Bit Interval Timer/Counter
This means — because the register counts upward — that the pre-load register TCPLD normally contains –13 (0F3h). To get a rough value for the 9-bit
baud rate correction C$0 to C$8, the fractional part (0.653333) of the above
division is multiplied by 9 (the number of calculated bits for the baud rate
correction):
Number of Ones = 0.653333 × 9 = 5.88000
The rounded result, 6, is the number of 1s to be used with the baud rate correction. The resulting, corrected, baud rate with the 6 1s of the baud rate correction is (6 bits have a length of 14 ACLK periods, 3 have a length of 13 ACLK
periods):
BaudRate =
(
32768
6 × 14 + 3 × 13
9
)
= 2397.6585
This results in an average baud rate error of:
Baud Rate Error =
2397.6585–2400
× 100 = –0.0975%
2400
To get the bit sequence for the baud rate correction that fits best, the following
algorithm can be used. The fractional part of the theoretical division factor UBR
is summed nine times and if a carry to the integer part occurs, the current C$x
bit is set. Otherwise, it is cleared. An example for the calculation of 9 bits with
the above fraction (0.653333) follows:
Fraction Addition
0.653333 + 0.653333 = 1.306667
1.306667 + 0.653333 = 1.959999
1.959999 + 0.653333 = 2.613332
2.613332 + 0.653333 = 3.266667
3.266667 + 0.653333 = 3.919999
3.919999 + 0.653333 = 4.573331
4.573331 + 0.653333 = 5.226664
5.226664 + 0.653333 = 5.879997
5.879997 + 0.653333 = 6.533333
Carry to next Integer
Yes
No
Yes
Yes
No
Yes
Yes
No
Yes
Correction Bits
C$0
C$1
C$2
C$3
C$4
C$5
C$6
C$7
C$8
1
0
1
1
0
1
1
0
1
On-Chip Peripherals
6-331
The 8-Bit Interval Timer/Counter
The result of the calculated bits C$8...C$0 (1 0110 1101b) is 16Dh with six
ones. The software example contains a macro loop (starting at label MODTAB)
that uses the algorithm shown above and calculates, for every combination of
the UART clock and the desired baud rate, the optimum value for the baud rate
correction. For the above example (9 bit frame length), the macro also determines 16Dh with its six ones.
Example 6–64. 2400 Baud From ACLK
Figure 6–94 gives an example for a baud rate of 2400 baud generated with the
ACLK frequency (32,768 Hz). The data format for figure 6–94 is:
Eight data bits, parity enabled, no address bit, and two stop bits. Figure 6–94
shows three different frames:
- The upper frame is the correct one with a bit length of 13.65333 ACLK
cycles (32,768/2400 = 13.65333)
- The middle frame uses a rough estimation with 14 ACLK cycles for the bit
length
- The
lower frame uses a corrected frame with the best fit
(C$11...C$0 = 0B6Dh) for the baud rate correction.
It can be seen that the approximation with 14 ACLK cycles accumulates an error of more than 0.3 bit length after the second stop bit. The error of the corrected frame is only 0.001 bit length. The error of the crystal clock is not yet
included, and it adds to the above errors.
6-332
The 8-Bit Interval Timer/Counter
Vcc
Precise
Timing
Start
Bit
LSB
13.65
13.65
13.65
13.65
13.65
13.65
13.65
13.65
MSB
Parity
Bit
13.65
13.65
Stop
Bits
13.65
13.65
0V
Rough
Approximation
Start
Bit
LSB
14
14
MSB
MSB
14
14
14
14
14
14
14
Parity
Bit
Stop
Bits
14
14
14
Error
Corrected
Timing
Baud Rate
Correction Bits (B6Dh)
Start
Bit
LSB
14
13
14
14
13
14
14
13
14
14
C$0
1
C$1
0
C$2
1
C$3
1
C$4
0
C$5
1
C$6
1
C$7
0
C$8
1
C$9
1
0Dh
06h
Error
Stop
Bits
MSB Parity
Bit
13
14
C$10 C$11
0
1
0Bh
Figure 6–94. Baud Rate Correction
Tables 6–36 and 6–37 contain the average errors (full frame with maximum
length, 13 bits) for the normally used baud rates resulting from the described
baud rate generation. The software examples contain a looped macro. It calculates — dependent on the frame length used — for all the bits the optimum
length.
6.10.3.1 Baud Rate Generation With the MCLK
Table 6–36 shows the optimum values for the 8-bit counter register TCDAT.
The UART clock is the MCLK (1,048 MHz). The crystal error is not included.
The mean error is calculated for a medium frame length of eleven bits: start
bit, eight data bits, parity enabled, and one stop bit. Table 6–36 contains the
following columns:
- Baud Rate — The baud rate for the data exchange (transmit and receive
use the same baud rate)
- Division Factor — The quotient UARTCLK/baud rate. It indicates the
number of MCLK cycles for a data bit
- 8-Bit Counter Register — The truncated 8-bit hexadecimal result of the
division factor (UARTCLK/baud rate). The value that is loaded into the
hardware register TCDAT is (100h – table value). This is due to the upward
count of the 8-bit counter.
On-Chip Peripherals
6-333
The 8-Bit Interval Timer/Counter
- Baud Rate Correction — The 13-bit result that fits best for the baud rate
correction. It is calculated by the software macro starting at label MODTAB. If frames with less than 13 bits are used, then the MSBs of this number are omitted.
- Used Fraction — The number of 1s in the baud rate correction sequence
divided by eleven (the frame length used for the calculation). It is an
approximation of the truncated fractional part of the division factor.
- Mean Error — The resulting error of a complete character caused by the
approximation of the division factor
The length of the 8-bit counter register allows only a very limited range for the
baud rate. An MCLK frequency of 1.048 MHz is assumed. For other frequencies, the baud rates change accordingly (e.g. for 2.096 MHz the usable baud
rates are 9600 and 19200 baud). The reasons for this restriction are:
- From 110 baud to 2400 baud, the 8-bit counter register is too small to hold
the necessary number for the result of the division MCLK/baud rate: the
number contained in the column 8-Bit Counter Register is greater than
0FFh.
- Beginning at 9600 baud, the CPU cycles between two UART interrupts are
too few for correct handling (e.g. only 54 CPU cycles @ 1.048 MHz for
19200 baud). See Section 4.4. The maximum baud rate depends strongly
on the amount of interrupt activity due to the other peripherals.
Note:
The assembler outputs an error message if the resulting value for the TCDAT
register is greater than 255. This is an indication of a baud rate that is too low.
Note:
Baud rates that result in TCDAT register values lower than 100 make strictly
real time processing rules necessary. Interrupt handlers must be as short as
possible and interruptible. See Section 4.4 for hints how to speed-up the
UART.
6-334
The 8-Bit Interval Timer/Counter
Table 6–36. Baud Rate Register TCDAT Contents (MCLK = 1,048 MHz)
BAUD
RATE
DIVISION
FACTOR
8-BIT COUNTER
REGISTER
BAUD RATE
CORRECTION
110
9532.51
253Ch
–
300
3495.25
0DA7h
–
FRACTION
USED
MEAN
ERROR (%)
600
1747.63
06D3h
–
1200
873.81
0369h
–
2400
436.91
01B4h
–
4800
218.45
00DAh
14AAh
0.4545
–0.002
9600
109.23
006Dh
1088h
0.1818
+0.044
19200
54.61
0036h
–
38400
27.31
001Bh
–
6.10.3.2 Baud Rate Generation With the ACLK
With the relatively low ACLK frequency (32,768 Hz), the baud rate correction
becomes much more important compared to the normally high MCLK frequency used for the UART timing. Table 6–37 shows the optimum values for the
counter register TCDAT and the correction values for commonly used baud
rates generated with the ACLK (32,768 Hz). The table values are calculated
by the macro starting at the label MODTAB. The crystal is assumed to be without frequency error. The meaning of the table columns is explained in Section
6.10.3.1. As for Table 6–36, the mean error is calculated for a medium frame
length of eleven bits: start bit, eight data bits, parity enabled, and one stop bit.
Table 6–37. Baud Rate Register TCDAT Contents (ACLK = 32,768 Hz)
BAUD
RATE
DIVISION
FACTOR
8-BIT COUNTER
REGISTER
BAUD RATE
CORRECTION
FRACTION
USED
MEAN
ERROR (%)
+0.04
110
297.8909
0129h
–
300
109.2267
006Dh
1088h
0.1818
600
54.6133
0036h
15DAh
0.6363
–0.04
1200
27.3067
001Bh
1124h
0.2727
+0.12
2400
13.6533
000Dh
1B6Dh
0.6363
+0.12
4800
6.8267
0006h
1BEFh
0.8181
+0.13
9600
3.4133
0003h
094Ah
0.3636
+1.46
19200
1.7067
–
–
–
–
38400
0.8533
–
–
–
–
On-Chip Peripherals
6-335
The 8-Bit Interval Timer/Counter
6.10.4 Software Routines
The following sections show proven software routines for the UART mode of
the 8-Bit Timer/Counter.
Note:
The program sequences for the initialization of the UART software are important. The example code should not be modified. See the subroutines TXINIT
and RCINIT.
Note:
Any protocol is possible due to the software control for the data sequence.
It is only necessary to adapt the two tables RTTAB and MODTAB of the two
software examples that follow.
The software routines are shown for interrupt use only. It makes no sense to
use the noninterrupt solution (polling) because the time intervals between two
signal bits are relatively short — a 100% loading of the CPU would be the result. This is due to the bit orientation of the 8-Bit Timer/Counter hardware.
The initialization subroutine INITSR and the RAM initialization subroutine
RAMCLR are explained in detail in section The Timer_A, paragraph Common
Initialization Routine.
6.10.4.1 MCLK Used for UART Clock
The following example is for use when MCLK used for the generation of the
UART clock. For high baud rates — higher than 9600 baud @ 1 MHz — dedicated CPU registers may be necessary to lower the interrupt overhead. The
time for the saving and restoring of the register is not necessary. See Section
6.10.4.4.
Example 6–65. Half Duplex UART with Interrupt
Half duplex UART software using the interrupt of the 8-Bit Timer/Counter is
shown below. The software is designed for:
- Baud rate: 4800 baud
- The MCLK (1,048 MHz) is used for the UART clock
- The active mode of the CPU is used
- Seven data bits
6-336
The 8-Bit Interval Timer/Counter
- Parity enabled with even parity
- No address bit included
- One stop bit
- Reception of all characters (the error byte RTERR contains an error indi-
cation)
- UART signals like shown in figure 6–87 (mark = VCC, space = VSS)
The following seven software switches and the value for the UARTCLK need
to be defined for the UART operation (see also the examples in the software
part). Functions that are not enabled, do not use memory space: the adjacent
code is left out by Conditional Assembly.
UARTCLK
If the MCLK is used for the UART timing, then the MCLK frequency must be given here.
Normally the MCLK is defined by multiplication of the crystal frequency with the FLL multiplier.
Baudr
Baud rate used [Hz]. For 1.048 MHz MCLK frequency, the range is from 4800 baud to
9600 baud. With special care, 19200 baud is also possible. The range of usable baud
rates increases linearly with the MCLK frequency used.
CHARC
Number of data bits. The UART software allows 7 and 8 data bits, but the table structure
of the software eases the adaptation to other bit counts.
ADDR
Inclusion of an address bit (1) or not (0). See the MSP430 Architecture Guide for an explanation of this feature.
PAR
Enables (1) or disables (0) a parity check. A parity error sets bit TCPE (RTERR.0).
PAREV
If parity is enabled (PAR = 1), even (1) or odd (0) parity is used for the data check.
STB
Defines the number of stop bits. Possible values are 1 or 2 stop bits
TCERRT
Defines the treatment of detected errors. If the received character is correct, the byte
RTERR contains 0. The possible values for the switch TCERRT are:
TCERRT = 0:
the current, erroneous character is discarded and the receive function is initialized
for a new start bit check. This means the software tries to find a valid start bit.
TCERRT = 1:
the error is indicated in byte RTERR, the reception of the current character continues.
Possible errors are:
TCPE (RTERR.0) = 1 — parity error. The sum of 1s contained in the data bits, the address bit, and the
parity bit is not correct. It is not odd for odd parity OR even for even parity
TCFE (RTERR.1) = 1 — frame error. This means the middle of the start bit is high, or one of the stop
bits is low. This error is normally caused by a software start inside of a character frame.
On-Chip Peripherals
6-337
The 8-Bit Interval Timer/Counter
Transmit Mode: the data to be transmitted is loaded right-aligned into the
RAM word RTDATA. The address bit — if enabled by ADDR = 1 — is included.
No error is possible. Four examples for the data in RTDATA are shown in figure
6–95. The completion of the transmission is indicated by a value of
(TX6–RTTAB) in the status byte RTSTAT. A relative number (TX6–RTTAB) is
necessary due to the many possible data formats.
7
15
7–Bit Data
No Address Bit
0
0
0
7–Bit Data
7
15
7–Bit Data
Address Bit
0
ADR
8
15
8–Bit Data
0
7–Bit Data
7
0
0
8–Bit Data
No Address Bit
8
15
8–Bit Data
0
ADR
7
0
8–Bit Data
Address Bit
Figure 6–95. Transmitted Data Format
Receive Mode: the received data is loaded left-aligned into the RAM word
RTDATA (see Figure 6–96). This means that, depending on the address bit
and the number of data bits contained in the data word, a shift is necessary
to get a single byte containing the received character. The input format used
is necessary due to the address bit. The completion of the reception is indicated by a value of (RC6–RTTAB) in the status byte RTSTAT. A relative number is necessary due to the many possible data formats. If no error occurred,
then the error byte RTERR contains 0, otherwise it contains the reason of the
error in its LSBs:
- Bit TCPE (RTERR.0) is set: a parity error occurred
- Bit TCFE (RTERR.1) is set: a frame error occurred. This can be caused
by a start bit having a mark signal (1) or a stop bit having a space signal
(0).
6-338
The 8-Bit Interval Timer/Counter
7–Bit Data
No Address Bit
7–Bit Data
15
7–Bit Data
ADR
Address Bit
7
8
15
0
0
8
0
7
0
0
7–Bit Data
8
15
8–Bit Data
No Address Bit
7
0
0
8–Bit Data
15
8–Bit Data
ADR
Address Bit
8
7
0
0
8–Bit Data
Figure 6–96. Received Data Format
; Definitions for the common part
;
STACK
.equ
0300h
; Stack start address
FLLMPY
.equ
32
; FLL multiplier for 1,048MHz
;
; Definitions for the UART part
; Data format: 4800 Baud, even parity, 7 data bits, 1 stop bit
; MCLK for UART clock, also erroneous characters to input
; buffer
;
Baudr
.equ
4800
; Baud rate is 4800 Baud
UARTCLK
.equ
FLLMPY*32768
; MCLK is used for UARTCLK
CHARC
.equ
7
; Length:
ADDR
.equ
0
; Address bit: 1: yes
0: no
PAR
.equ
1
; Parity
0: disabled
1: enabled
PAREV
.equ
1
; Parity
0: odd
1: even
STB
.equ
1
; Stop bits: 1: one
TCERRT
.equ
1
; 0: error restart
7: 7 bits
8: 8 bits
2: two
1: indication
;
On-Chip Peripherals
6-339
The 8-Bit Interval Timer/Counter
TCPE
.equ
1
; Parity error: RTERR.0 = 1
TCFE
.equ
2
; Frame error:
CUBR
.equ
–(UARTCLK/Baudr)
; Content 8–Bit Counter
RTERR.1 = 1
;
.even
; Word boundary
.bss
RTDATA,2
; Data for receive/transmit
.bss
RTERR,1
; Error byte
.bss
RTSTAT,1
; Status byte
;
.text
; Software start address
;
INIT
MOV
#STACK,SP
; Initialize Stack Pointer
CALL
#INITSR
; Init. FLL and RAM
...
; Proceed with initialization
EINT
; Enable interrupts
;
MAINLOOP ...
; Mainloop starts here
...
;
; Prepare transmission of one character from RAM word RTDATA
; Info is contained right aligned in LSBs. No error possible
;
MOV
#xxx,RTDATA
; Character xxx to RTDATA
CALL
#TXINIT
; Initialize the transmit part
...
; Continue with background
; Check for completion:
CMP.B
#TX6–RTTAB,RTSTAT ; Character transmitted?
JEQ
CHARTX
...
; Yes, prepare next one
; No, continue
;
; Prepare the reception of one character to RAM word RTDATA
; Info is contained left aligned in the LSBs. Errors in RTERR
;
CALL
...
#RCINIT
; Initialize the receive part
; Continue in background
; Check for completion:
6-340
The 8-Bit Interval Timer/Counter
CMP.B
#RC6–RTTAB,RTSTAT ; One character received?
JNE
NO_CHAR
; No, continue
TST.B
RTERR
; Yes, error?
JNZ
ERRHDL
; Yes, check reason
CLRC
; No, shift a 0 in MSB
RRC
RTDATA
...
; RTDATA+1 contains 7–bit data
; Process data in RTDATA+1
BR
#MAINLOOP
; Back to mainloop
; Common interrupt handler for transmit and receive functions.
; The carry of TCDAT is switched to the P0.1 interrupt request.
; Interrupt time interval of the 8–bit timer is: 1/Baud rate
; The single status byte RTSTAT contains the actual status:
;
; Idle:
RTSTAT = 0
No UART activity
; Transmit:
RTSTAT = 1...TX6–RTTAB–1
Active
;
TX6–RTTAB
; Receive:
Character output
RTSTAT = RC–RTTAB...RC6–RTTAB–1
;
RC6–RTTAB
Active
Char. received
;
TXRCINT
RTTAB
PUSH
R5
; Save R5
MOV.B
RTSTAT,R5
; Receive/transmit status
MOV.B
RTTAB(R5),R5
; Offset to handler address
ADD
R5,PC
; RTTAB+RTSTATx–RTTAB –> PC
.BYTE
RTSTAT0–RTTAB
; Offset RTSTAT = 0 (inactive)
.BYTE
TXSTAT1–RTTAB
; TX: Start bit
.BYTE
TXSTAT2–RTTAB
; TX: LSB
.BYTE
TXSTAT2–RTTAB
; TX: LSB+1
.BYTE
TXSTAT2–RTTAB
; TX: LSB+2
.BYTE
TXSTAT2–RTTAB
; TX: LSB+3
.BYTE
TXSTAT2–RTTAB
; TX: MSB–3
.BYTE
TXSTAT2–RTTAB
; TX: MSB–2
.if
CHARC=8
; Data length 7 or 8 bits?
.BYTE
TXSTAT2–RTTAB
; TX: MSB–1
;
; Transmit states
;
TX
On-Chip Peripherals
6-341
The 8-Bit Interval Timer/Counter
.endif
.BYTE
TXSTAT2–RTTAB
; TX: MSB
.if
ADDR=1
; Address bit?
.BYTE
TXSTAT3–RTTAB
; TX: Address bit
.if
PAR=1
; Parity enabled?
.BYTE
TXSTAT4–RTTAB
; TX: Parity bit
.BYTE
TXSTAT5–RTTAB
; TX: stop bit 1
.if
STB=2
; Two stop bits?
.BYTE
TXSTAT5–RTTAB
; TX: stop bit 2
TXSTAT6–RTTAB
; TX: Frame output completed
.endif
.endif
.endif
TX6
.BYTE
;
; Receive states: interrupt occurs in the middle of the bits
;
RC
.BYTE
RCSTAT1–RTTAB
; RC: start bit
.BYTE
RCSTAT2–RTTAB
; RC: LSB
.BYTE
RCSTAT2–RTTAB
; RC: LSB+1
.BYTE
RCSTAT2–RTTAB
; RC: LSB+2
.BYTE
RCSTAT2–RTTAB
; RC: LSB+3
.BYTE
RCSTAT2–RTTAB
; RC: MSB–3
.BYTE
RCSTAT2–RTTAB
; RC: MSB–2
.if
CHARC=8
; Data length 7 or 8 bits?
.BYTE
RCSTAT2–RTTAB
; RC: MSB–1
.BYTE
RCSTAT2–RTTAB
; RC: MSB
.if
ADDR=1
; Address bit?
.BYTE
RCSTAT3–RTTAB
; RC: Address bit
.if
PAR=1
; Parity enabled?
.BYTE
RCSTAT4–RTTAB
; RC: Parity bit
.BYTE
RCSTAT5–RTTAB
; RC: stop bit 1, parity check
.if
STB=2
; Two stop bits?
.BYTE
RCSTAT6–RTTAB
; RC: stop bit 2
.endif
.endif
.endif
6-342
The 8-Bit Interval Timer/Counter
.endif
RC6
.BYTE
TXSTAT6–RTTAB
; RC: Frame received
;
; Transmit software part. Interrupt after output bit.
; The bit length and data of the next but one bit is defined
;
TXSTAT1
BIC.B
#TXD,&TCCTL
; Start bit: output space (0)
JMP
TXRET
; To common interrupt return
.equ
$
; Address bit (if defined)
;
TXSTAT3
TXSTAT2
TX0
RRA
RTDATA
; Data bit: next one to carry
JC
TX1
; Data is 1
BIC.B
#TXD,&TCCTL
; Output data 0: reset TXD
JMP
TXRET
.equ
$
; Output 1 with parity count
.if
PAR=1
; Parity enabled?
XOR.B
#1,RTERR
; Toggle LSB for parity
.equ
$
; Stop bit: output 1 w/o parity
BIS.B
#TXD,&TCCTL
; Data is 1: set TXD
;
TX1
.endif
TXSTAT5
;
; Tasks are made, the next but one bit length is loaded to the
; pre–load register TCPLD. The bit length for the current bit was
; loaded with the current interrupt.
;
TXRET
MOV.B
RTSTAT,R5
; Transmit status to R5
MOV.B
MODTAB–1(R5),&TCPLD ; Next but one bit length
JMP
RTRET
; To common RETI part
.if
PAR=1
; Parity enabled?
BIT.B
#1,RTERR
; Yes, check parity value
JNZ
TX1
; Output mark (1).
JMP
TX0
; Output space (0). TCPE = 0
;
TXSTAT4
TCPE = 0
.endif
;
On-Chip Peripherals
6-343
The 8-Bit Interval Timer/Counter
; One full character is received or transmitted. The UART
; hardware is switched off. The status for a completed
; character is:
; Receive Mode:
RC6–RTTAB
; Transmit Mode: TX6–RTTAB
;
TXSTAT6
BIC.B
#P0IE1,&IE1
; Disable TCDAT carry interrupt
BIC.B
#RXACT+ENCNT,&TCCTL ; Stop T/C, conserve power
JMP
RTSTAT0
; To RETI w/o status change
;
; Receive software part. Interrupt occurs in the middle of the
; bit. The bit length of the next but one bit is defined
;
RCSTAT1
BIT.B
#RXD,&TCCTL
; Check middle of start bit
JZ
RCRET
; Start bit is 0: ok
.if
TCERRT=1
; Error, indication wished?
BIS.B
#TCFE,RTERR
; Frame error bit TCFE set
JMP
RCERR
; Start bit is 1; error
RCSTAT4
.equ
$
; Parity bit is received normally
RCSTAT3
.equ
$
; Address bit too
RCSTAT2
BIT.B
#RXD,&TCCTL
; Data bits: info to carry
RRC
RTDATA
; Shift data into MSB
.if
PAR=1
; Parity enabled?
JN
RC1
; Data is a 1: adjust parity info
JMP
RCRET
; Data is a 0: all done
XOR.B
#1,RTERR
; Yes, adjust odd/even info
.endif
;
RC1
.endif
;
; Tasks are made, the next but one bit length is loaded to the
; pre–load register TCPLD. The bit length for the next bit was
; loaded with the current interrupt.
;
RCRET
6-344
MOV.B
RTSTAT,R5
; Transmit status to R5. Length
MOV.B
MODTAB–(RC–TX)(R5),&TCPLD ; next but one bit
The 8-Bit Interval Timer/Counter
RTRET
INC.B
RTSTAT
; To next receive status
RTSTAT0
POP
R5
; Restore R5
RETI
;
; Stop bit handling: RXD must be high. Parity is checked also:
; Parity bit RTERR.0 (TCPE) must be 0
;
RCSTAT5
.equ
$
; Parity check during stop bit 1
.if
PAR=1
; Parity enabled?
RLA
RTDATA
; Shift out parity bit
.if
TCERRT=0
; Restart for error?
BIT.B
#1,RTERR
; Yes, check parity value TCPE
JNZ
RCERR
; Not 0: error. TCPE stays 1
BIT.B
#RXD,&TCCTL
; Stop bit (1 or 2) high?
JNZ
RCRET
; Yes, Parity and stop bits ok
.if
TCERRT=1
; No, Error indication wished?
BIS.B
#TCFE,RTERR
; Yes, set frame error bit
JMP
RCRET
; Continue with frame
.endif
.endif
RCSTAT6
.endif
; No, to error handler RCERR
;
; Error handling: two different ways can be selected:
; TCERRT = 0: restart, start bit check. Current char. is discarded
; TCERRT = 1: error indication in RTERR. Reception continues.
;
RCERR
.if
TCERRT=0
; Error indication wished?
BIC.B
#P0IE1,&IE1
; No, intrpt disabled: UART off
EINT
; Allow nesting
CALL
#RCINIT
JMP
RTSTAT0
; Restart receive task
.else
RCERR
.equ
RCRET
; Yes, continue
.endif
;
; Table MODTAB contains the calculated bit lengths that fit
On-Chip Peripherals
6-345
The 8-Bit Interval Timer/Counter
; best. Sequence: start bit, LSB...MSB, (address bit),
; (parity), stop bits + one bit more for the turn–off
; Only the necessary bytes – dependent on the frame length –
; are included. All bits are calculated individually.
; Resolution of the calculation is 10 bits
;
MODTAB
.equ
$
; Calculate fraction (UARTCLK/Baudr)
CMOD
.equ
(((1024*UARTCLK)/Baudr)–1024*(UARTCLK/Baudr))
.eval
CMOD,M$00
.mnolist
.loop
9+(ADDR=1)+(PAR=1)+(CHARC=8)+(STB=2)+1 ; Bit #
.eval
CMOD+M$00,M$00
.if
M$00>1023
; Carry to integer?
.eval
M$00–1024,M$00
; Yes
CUBR–1
; C$x = 1: Bit one cycle longer
CUBR
; C$x = 0: Bit normal length
.mlist
.byte
.mnolist
.else
.mlist
.byte
.mnolist
.endif
.endloop
.even
; To word boundary
;
; Subroutines
; The subroutine prepares the 8–Bit Timer/Counter hardware to
; transmit data. Initialize control byte TCCTL:
; SSEL1/SSEL0: 1/0 for MCLK frequency
; ISCTL:
1
Carry of TCDAT register causes P0.1 intrpt
; TXE:
1
Output P0.2 to TXD, disable P0OUT.2
; TXD
1
Set TXD (P0.2) to high (mark)
; ENCNT:
1
Enable clock to the TCDAT register
;
TXINIT
6-346
MOV.B
#SSEL1+ISCTL+TXE+TXD+ENCNT,&TCCTL
MOV.B
#TX–RTTAB,RTSTAT ; Transmit status for start bit
The 8-Bit Interval Timer/Counter
JMP
RTINIT
; To common part
;
; The subroutine prepares the 8–Bit Timer/Counter hardware to
; receive data. Initialize control byte TCCTL:
; SSEL1/SSEL0: 1/0 for MCLK frequency
; ISCTL:
1
Carry of TCDAT register causes P0.1 intrpt
; TXE:
1
Enable output buffer for P0.2
; TXD:
1
Set TXD (P0.2) to high (mark)
; RXACT:
0
Reset Edge Detect Flip–Flop
;
RCINIT
MOV.B
#SSEL1+ISCTL+TXD+TXE,&TCCTL
MOV.B
#RC–RTTAB,RTSTAT
; Receive status start bit
CLR
RTDATA
; Clear data word
BIS.B
#2,&P0IES
; Neg. edge detect for P0.1
;
; Common part for transmit and receive. The parity bit RTERR.0
; is initialized in a way, that always zero is returned, if
; the parity is ok.
;
RTINIT
MOV.B
#CUBR/2,&TCPLD
; Half bit time to 1st intrpt
MOV.B
#0,&TCDAT
; Load half bit time to TCDAT
MOV.B
MODTAB,&TCPLD
; Bit time for 1st bit
.if
(PAR=1)&(PAREV=0) ; Odd Parity enabled?
MOV.B
#1,RTERR
; Odd parity: RTERR.0 = 1
#0,RTERR
; No parity .or. even parity
BIS.B
#P0IE1,&IE1
; TCDAT carry intrpt enabled
BIS.B
#RXACT,&TCCTL
; Receive: enable edge detect.
.else
MOV.B
.endif
RET
; Interrupt Vectors
;
.sect
”SCIVEC”,0FFF8h
; HW/SW UART Vectors
.word
TXRCINT
; Common TX/RC Vector
.sect
”INITVEC”,0FFFEh
; Reset Vector
.word
INIT
; Program Start Address
On-Chip Peripherals
6-347
The 8-Bit Interval Timer/Counter
6.10.4.2 ACLK Used for the UART Clock
With the ACLK used for the UART clock, two different methods are possible.
- ACLK used with the active mode — the only difference to the last section
is the use of the ACLK instead of the MCLK.
- ACLK used with the low power mode 3 — The CPU is switched off normal-
ly (LPM3) but the UART activity continues. This method is necessary for
low power applications.
The two different methods are described in the next two sections.
6.10.4.2.1 ACLK With the Active Mode
The ACLK can be used for the UART clock in very much the same way as the
MCLK (see Section 6.10.4.1 for details). The use of the ACLK may be necessary if the needed baud rate is too low for the MCLK frequency in use. For example, with an MCLK of 1.048 MHz, the lowest (usual) baud rate is 4800 baud.
To use the ACLK with the active mode, it is only necessary to change two parts
of the software example of Section 6.10.4.1:
- The definition line for the UART clock:
UARTCLK
.equ
32768
; ACLK is used for UARTCLK
- The initialization subroutines TXINIT and RCINIT. Instead of the MCLK,
the ACLK needs to be defined with the initialization subroutines (SSEL0
= 1, SSEL1 = 0). The simplest way is to use the subroutines of this Section
(6.10.4.2).
6.10.4.2.2 ACLK With the Low Power Mode 3
This section shows another approach. With this example, the CPU is normally
off and leaves the LPM3 only for the interrupt handling and after a complete
character is received or transmitted.
Example 6–66. Half duplex UART With Interrupt
Half duplex UART software using the UART interrupt is shown. It is designed
for:
- Baud rate: 2400 baud
6-348
The 8-Bit Interval Timer/Counter
- The ACLK (32,768 Hz) is used for the UART clock
- Eight data bits
- Parity enabled with odd parity
- Address bit included
- Two stop bits
- Reception of correct characters only (no error indication, restart instead)
- The CPU normally uses the low power mode 3 (LPM3)
- UART signals like shown in figure 6–87 (mark = VCC, space = VSS)
The software switches have the same function as described in Section
6.10.4.1. The UARTCLK is defined with the crystal frequency.
Also, this example uses a looped calculation for the correction of the bits. Not
only eight different bits are calculated, but all of the bits of a frame (9 to 13) are
calculated individually. See the software part starting at the label MODTAB.
Transmit Mode: the data to be transmitted is loaded right-aligned into the
RAM word RTDATA. The address bit — if enabled by ADDR = 1 — is included.
No error is possible. Four examples for the data in RTDATA are shown in figure
6–95. The completion of the transmission is indicated by the value
(TX6–RTTAB) in the status byte RTSTAT. The interrupt routine outputs the
character and resets after the completion the CPUoff bit and the SCG1 and
SCG0 bits of the stored status register on the stack. This manipulation omits
the return to LPM3 and initializes the next transmit sequence.
Receive Mode: the received data is loaded left-aligned into the RAM word
RTDATA. This means that depending on the address bit and the number of
data bits contained in the data word, a shift is necessary to get a single byte
containing the received character. Examples for the data are shown in figure
6–96. The input format used is necessary due to the address bit. The completion of the reception is indicated by the value (RC6–RTTAB) in the status byte
RTSTAT. After the reception of a complete character, the interrupt handler resets the CPUoff bit and the SCG1 and SCG0 bits of the stored status register
on the stack. This manipulation omits the return to LPM3 and allows the processing of the received data. The error handling is the same as shown for the
example in Section 6.10.4.1.
On-Chip Peripherals
6-349
The 8-Bit Interval Timer/Counter
; Definitions for the common part
;
STACK
.equ
0300h
; Stack start address
FLLMPY
.equ
32
; FLL multiplier for 1,048MHz
;
; Definitions for the UART. Data format:
; odd parity, 8 data bits, address bit, 2 stop bits
; ACLK for UART clock, only correct characters to input buffer
;
Baudr
.equ
2400
; Baud rate is 2400 Baud
UARTCLK
.equ
32768
; ACLK is used for UARTCLK
CHARC
.equ
8
; Length:
ADDR
.equ
1
; Address bit: 1 yes
0 no
PAR
.equ
1
; Parity
0: disabled
1: enabled
PAREV
.equ
0
; Parity
0: odd
1: even
STB
.equ
2
; Stop bits:
TCERRT
.equ
0
; 0: error restart
TCPE
.equ
1
; Parity error: RTERR.0 = 1
TCFE
.equ
2
; Frame error:
CUBR
.equ
–(UARTCLK/Baudr)
; Content 8–Bit Counter
7: 7 bits
8: 8 bits
1: one
2: two
1: indication
;
RTERR.1 = 1
;
.even
; Word boundary
.bss
RTDATA,2
; Data for receive/transmit
.bss
RTERR,1
; Error byte
.bss
RTSTAT,1
; Status byte
;
.text
; Software start address
;
INIT
MOV
#STACK,SP
CALL
#INITSR
; Initialize Stack Pointer
; Init. FLL and RAM
...
; Proceed with initialization
EINT
; Enable interrupts
...
;
; Prepare the transmission of one character from RAM word
6-350
The 8-Bit Interval Timer/Counter
; RTDATA. Info is contained right aligned in the LSBs. No error
; is possible
;
MOV
#xxx,RTDATA
; Character xxx to RTDATA
CALL
#TXINIT
; Initialize the transmit part
...
; Continue with background
;
; Prepare the reception of one character to RAM word RTDATA
;
CALL
#RCINIT
...
; Initialize the receive part
; Continue in background
;
; After the completion of all background tasks, enter LPM3
;
PLPM3
BIS
#CPUoff+GIE+SCG1+SCG0,SR
; Enter LPM3
;
; An interrupt handler cleared the CPUoff, SCG1 and SCG0 bits
; of the SR on the stack. Checks are made if activity is
; needed:
; Receive Mode:
one character is received
; Transmit Mode:
one character is output completely
; ...
other interrupt handlers
;
CMP.B
#RC6–RTTAB,RTSTAT ; One character received?
JEQ
CHAR_RC
CMP.B
#TX6–RTTAB,RTSTAT ; One character transmitted?
JEQ
CHAR_TX
...
JMP
; Yes, process character
; Yes, prepare next one
; Check other reasons
PLPM3
; Back to LPM3
;
; Common interrupt handler for transmit and receive functions.
; The carry of TCDAT is switched to the P0.1 interrupt request
; Interrupt time interval of the 8–bit timer is: 1/Baud rate
; The single status byte RTSTAT contains the actual status:
; Idle:
RTSTAT = 0
No activity
; Transmit:
RTSTAT = 1...TX6–RTTAB–1
Active
On-Chip Peripherals
6-351
The 8-Bit Interval Timer/Counter
;
TX6–RTTAB
; Receive:
Character output
RTSTAT = RC–RTTAB...RC6–RTTAB–1
;
RC6–RTTAB
Active
Char. received
;
TXRCINT
RTTAB
PUSH
R5
; Save R5
MOV.B
RTSTAT,R5
; Receive/transmit status
MOV.B
RTTAB(R5),R5
; Offset to handler –> R5
ADD
R5,PC
; RTTAB+RTSTATx–RTTAB –> PC
.BYTE
RTSTAT0–RTTAB
; Offset RTSTAT = 0 (inactive)
;
...
; Like shown for MCLK version
Note:
The interrupt handler for the UART when using the ACLK for the the UART
clock is the same as the handler for when the MCLK is used. Only the small
software part after the completion of a received or sent character (at label
TXSTAT6) is slightly different. It resets the CPUoff, SCG1, and also SCG0
bits (SR.4 to SR.6) to allow a software activity after the return from interrupt
RETI. Also, the first instructions of the initialization subroutines are different.
These parts are shown below.
;
; One full character is received or transmitted. The UART
; hardware is switched off, the LPM3 is terminated to wake–up
; the CPU after the RETI. The status for a completed character
; is:
; Receive Mode:
RC6 – RTTAB
; Transmit Mode: TX6 – RTTAB
;
TXSTAT6
BIC.B
#P0IE1,&IE1
; Disable TCDAT carry interrupt
BIC.B
#RXACT+ENCNT,&TCCTL ; Stop T/C, conserve power
BIC
#SCG1+SCG0+CPUoff,2(SP) ; Terminate LPM3
JMP
RTSTAT0
; To RETI
;
; Subroutines
; The subroutine prepares the 8–Bit Timer/Counter hardware to
; transmit data. Initialize control byte TCCTL:
; SSEL1/SSEL0: 0/1 for ACLK frequency
6-352
The 8-Bit Interval Timer/Counter
; ISCTL:
1
Carry of TCDAT register causes P0.1 intrpt
; TXE:
1
Enable output buffer for P0.2
; TXD
1
Set TXD (P0.2) to high (mark)
; ENCNT:
1
Enable clock to the TCDAT register
;
TXINIT
MOV.B
#SSEL0+ISCTL+TXE+TXD+ENCNT,&TCCTL
MOV.B
#TX–RTTAB,RTSTAT
; Transmit status, start bit
JMP
RTINIT
; To common part
;
; The subroutine prepares the 8–Bit Timer/Counter hardware to
; receive data. Initialize control byte TCCTL:
; SSEL1/SSEL0: 0/1 for ACLK frequency
; ISCTL:
1
Carry of TCDAT register causes P0.1 intrpt
; TXE:
1
Enable output buffer for P0.2
; TXD:
1
Set TXD (P0.2) to high (mark)
; RXACT:
0
Reset the Edge Detection Flip–Flop
;
RCINIT
MOV.B
#SSEL0+ISCTL+TXD+TXE,&TCCTL ; Control byte
MOV.B
#RC–RTTAB,RTSTAT
; Receive status, start bit
CLR
RTDATA
; Clear data word
BIS.B
#2,&P0IES
; Neg. edge detection on P0.1
;
; Common part for transmit and receive. The parity bit RTERR.0
; is initialized in a way, that always zero is returned, if the
; parity is ok.
;
RTINIT
MOV.B
#CUBR/2,&TCPLD
; Half bit time to 1st intrpt
MOV.B
#0,&TCDAT
; Load half bit time to TCDAT
MOV.B
MODTAB,&TCPLD
; Bit time for 1st bit
.if
(PAR=1)&(PAREV=0) ; Odd Parity enabled?
MOV.B
#1,RTERR
; Odd parity: RTERR.0 = 1
#0,RTERR
; No parity .or. even parity
BIS.B
#P0IE1,&IE1
; TCDAT carry intrpt enabled
BIS.B
#RXACT,&TCCTL
; Receive: enable edge detect.
.else
MOV.B
.endif
On-Chip Peripherals
6-353
The 8-Bit Interval Timer/Counter
RET
;
; Interrupt Vectors
;
.sect
”SCIVEC”,0FFF8h
; HW/SW UART Vectors
.word
TXRCINT
; Common TX/RC Vector
.sect
”INITVEC”,0FFFEh
; Reset Vector
.word
INIT
; Program Start Address
6.10.4.3 CPU Loading and Memory Space
6.10.4.3.1 CPU Loading
The CPU loading due to the UART activity can be calculated with simple formulas. The formulas are slightly different for the transmit and the receive
mode, because they have different medium cycles per bit. The numbers are
given for a frame with 8 data bits, parity enabled, no address bit, and two stop
bits. This results in 13 interrupts per frame (the turn off of the 8-Bit Timer/
Counter is included). The transmitted [resp.] received character is 0AAh with
its sequence of ones and zeros.
The cycle count includes:
6
n
5
cycles to get to the 1st instruction of the interrupt handler
cycles for the interrupt handler itself
cycles for the RETI instruction
Not included are: the initialization subroutines, the data preparation for the
transmit mode, and the data processing for the receive mode.
Transmit Mode — the sum of cycles for a complete frame is 708 cycles. The
medium cycle count per transmitted bit is 708/13 = 54.46 cycles.
Receive Mode — the sum of cycles for a complete frame is 699 cycles. The
medium cycle count per received bit is 699/13 = 53.77 cycles.
The formula to calculate the percentage for the CPU load due to the UART activity is:
CPULoad =
6-354
BaudRate × c
× 100
fMCLK
The 8-Bit Interval Timer/Counter
Where:
CPULoad
fMCLK
BaudRate
c
Loading of the MSP430 CPU by the UART
system clock used for the UART
Used baud rate of the UART
MCLK cycles per bit used by the interrupt handler
[%]
[Hz]
[Hz]
If MCLK = 1.048 MHz and the baud rate = 4800 Hz, then the CPU loading is
approximately 24.7%.
6.10.4.3.2 Memory Space
The memory space needed by the 8-Bit Timer/Counter UART depends on the
UART format used and the enabled options. The minimum version is shown
first and the additional bytes due to the enabled functions afterward. The numbers given include the interrupt handler TXRCINT and the two initialization
subroutines TXINIT and RCINIT.
Minimum Version: (7 data bits, no address bit, no parity, one stop bit, error indication).
8 data bits
Address bit included
Parity enabled
Two stop bits
Error restart enabled
202 ROM bytes, 4 RAM bytes
+ 4 bytes
+ 2 bytes
+30 bytes
+ 2 bytes
+16 bytes
Maximum Version:
256 ROM bytes, 4 RAM bytes.
6.10.4.4 UART Speed-Up Possibilities
The following ideas on how to speed up the UART come from Mark Buccini TI/Atlanta. It must be determined for each application if these possibilities can be used.
6.10.4.4.1 Dedicated CPU Register for the Status
The use of a dedicated CPU register for the status makes the saving and restoring of the needed register unnecessary. If it is incremented by two, it can
step through a word table with minimum overhead.
; Initialization for transmit
;
TXINIT
...
MOV
; Like described before
#TX–RTTAB,R5
; Initialize transmit status
...
On-Chip Peripherals
6-355
The 8-Bit Interval Timer/Counter
;
; Interrupt handler: R5 contains the status in steps of two
;
TXRCINT
MOV
RTTAB(R5),PC
; Start of handler to PC
RTTAB
.WORD
RTSTAT0
; Address for R5 = 0 (inactive)
TX
.WORD
TXSTAT1
; TX: Start bit
.WORD
TXSTAT2
; TX: LSB
; Transmit states:
...
; Return from interrupt
RTRET
INCD
RTSTAT0
RETI
R5
; To next status (steps of 2)
The autoincrement addressing mode may also be used to speed up the interrupt handler:
; Initialization for transmit
;
TXINIT
...
MOV
; Like described before
#TX,R5
; Initialize transmit status
...
;
; R5 contains the address of the current table word
;
TXRCINT
MOV
@R5+,PC
; Start of handler to PC
RTTAB
.WORD
RTSTAT0
; Address = RTTAB (inactive)
; Transmit states:
TX
.WORD
TXSTAT1
; TX: Start bit
.WORD
TXSTAT2
; TX: LSB
...
; Return from interrupt
RTRET
RETI
RTSTAT0
DECD
RETI
6-356
; Next status yet in R5
R5
; Completed: last status
The 8-Bit Interval Timer/Counter
6.10.4.4.2 No Baud Rate Correction
No baud rate correction is needed if the MCLK is used for the baud rate Generation. This allows a shorter interrupt handler with fewer cycles and less program space.
6.10.4.4.3 Word Table Instead of a Byte Table
If a word table instead of the byte table is used for the distribution at the start
of the interrupt handler, then more program space is needed, but the execution
is faster. See Section 6.10.4.4.1.
6.10.4.4.4 Mixture of the Methods
The two sources for the UART clock are detailed in sections 6.10.4.1 (MCLK)
and 6.10.4.2 (ACLK) may be mixed to get the best of both worlds:
Transmit Mode — the program normally uses the LPM3. If a character needs
to be output, then the active mode with its MCLK is used. The software is identical to the transmit mode shown in Section 6.10.4.1.
Receive Mode — the program normally uses the LPM3 with the interrupt of
the P0.1 pin activated on negative edges (start bit).
- The initialization subroutine is the same as shown in Section 6.10.4.1 with
the exception of:
J
The bit ISCTL in the control register TCCTL is reset to enable the interrupt at pin P0.1 for negative edges.
- The next start bit wakes up the MSP430, which starts the following activi-
ties:
J
The control loop of the system clock generator is closed to get a controlled MCLK frequency (SCG0 = 0)
J
The interrupt source is switched from the input pin P0.1 to the carry of
the 8-bit counter (ISCTL = 1)
- The MCLK stays active until the complete character is received. The
LPM3 is activated again after the processing of the received data.
On-Chip Peripherals
6-357
The Comparator_A
6.11 The Comparator_A
The Comparator_A module is contained in some members of the
MSP430x1xx family. It can be used for precise analog measurements. Figure
6–97 shows the versatile hardware of the module.
VCC
PCA0
CA0
0
1
0
1
CA1
CAON
CAEX
CAF
internal
module
0
1
0
1
+
0
–
1
0
CAOUT
1
τ ≈ 1.2 µs
PCA1
VCC
3 2 1 0
CAREF
CARSEL
1
0
VCAREF
0
0.5xVCC
2
1
0.25xVCC
3
Figure 6–97. Comparator_A Hardware
6-358
set
CAIFG
The Comparator_A
6.11.1 Definitions Used With the Application Examples
The abbreviations used for the hardware definitions are consistent with the
MSP430 Architecture User’s Guide.
; HARDWARE DEFINITIONS
; COMPARATOR_A
;
CACTL1
.equ
059h
; Control Register 1
CAIFG
.equ
001h
; Interrupt Flag
CAIE
.equ
002h
; Interrupt Enable Flag
CAIES
.equ
004h
; Edge Select 0: rising 1: falling
CAON
.equ
008h
; Supply
CAREF0
.equ
010h
; 00: off
01: 0.5xVcc
CAREF1
.equ
020h
; 10: 0.25xVcc
11: Vref
CARSEL
.equ
040h
; Reference to: 0: CA0
CAEX
.equ
080h
; 0: CA0 –> +
CACTL2
.equ
05Ah
; Control Register 2
CAOUT
.equ
001h
; CA Output
CAF
.equ
002h
; Output Filter 0: off
1: on
P2CA0
.equ
004h
; Switch CA0
0: off
1: CA0 on
P2CA1
.equ
008h
; Switch CA1
0: off
1: CA1 on
CACTL24
.equ
010h
; Software Bits
CACTL25
.equ
020h
CACTL26
.equ
040h
CACTL27
.equ
080h
CAPD
.equ
05Bh
; Control Register 3
CAPD0
.equ
001h
; Input Buffer Switches Port 2
CAPD1
.equ
002h
; 0: Input Buffer enabled
CAPD2
.equ
004h
; 1: Input Buffer disabled
CAPD3
.equ
008h
CAPD4
.equ
010h
; Avoid current through input buffers
CAPD5
.equ
020h
; with analog signals
CAPD6
.equ
040h
CAPD7
.equ
080h
0: off
1: off
1: CA1
1: CA1 –> +
;
;
On-Chip Peripherals
6-359
The Comparator_A
6.11.1.1 Attributes of the Comparator_A
The hardware allows all combinations of comparisons. The bit CAOUT
(CACTL.0) contains the result of the comparison:
- Comparison of two external inputs
- Comparison of each external input with 0.25 × VCC or 0.5 × VCC
- Comparison of each external input with an internal reference voltage
- An analog filter can be switched to the CAOUT output
- The module has interrupt capability for the leading and the trailing edge
of the output signal CAOUT
6-360
The Comparator_A
6.11.2 Fast Comparator Input Check
Often a very fast sampling of sequential input values is necessary. The following measurement sequence is the fastest way to do this with the Comparator_A inputs. After the n input checks, a majority test — or something equivalent — can be made for a decision. Figure 6–98 shows the hardware used for
the example. The software samples the voltage generated by the current
Imeas through resistor Rm. A voltage drop higher than 0.25 × VCC sets CAOUT, a lower voltage drop resets CAOUT. After n samples, the number of
sampled 1s is checked. Any other input combination may also be used.
VCC
VCC
PCA0
Imeas
CA1
0
CAF
0
1
1
0
Rm
CAON
CAEX
0
1
1
+
0
–
1
e.g. capture
input of
Timer_A
0
CAOUT
1
CA2
set
CAIFG
τ ≈1.2 µs
PCA1
VCC
3
2
1
0
CAREF
CARSEL
0
1
0
VCAREF
0.5xVCC
1
2
0.25xVCC
3
Figure 6–98. Fast Comparator Input Check Circuitry
On-Chip Peripherals
6-361
The Comparator_A
; Fast test for the state of the Comparator_A input
;
MOV.B
#CARSEL+CAREF1+CAON,&CACTL1 ; Define Comp_A mode
MOV.B
#PCA0,&CACTL2
MOV
#CACTL2,R15
; Prepare pointer to reg. CACTL2
MOV.B
@R15,R5
; Sample CAOUT (CAOUT = CACTL2.0)
ADD.B
@R15,R5
; Add next sample
...
...
ADD.B
; Add following samples
@R15,R5
; Add sample n
;
; Test if CAOUT showed more than n/2 times a positive result
;
SUB
#n*PCA0,R5
; Correct result
CMP.B
#1+(n/2),R5
; R5 – (1+n/2)
JHS
POS
; More samples are 1
...
; More samples are 0
or an even faster decision:
; Test if CAOUT showed more than n/2 times a positive result
;
CMP.B
#n*PCA0+1+(n/2),R5
; R5–n*PCA0+(1+n/2)
JHS
POS
; More samples are 1
...
6-362
; More samples are 0
The Comparator_A
6.11.3 Voltage Measurement
Figure 6–99 shows hardware that can be used for the measurement of external voltages. The supply voltage is used for reference. The measurement principle is the same one as shown in section Voltage Measurement with the
Universal Timer Port/Module.
0.25 × Vcc ×
R1+ R2 + R3
R1+ R2 + R3
< Vin < Vcc ×
R2+ R3
R2 + R3
Vin
R1
270k
VCC
P1.1
PCA0
R2
CAON
CAEX
CAF
270k
CA0
0
1
0
1
R3
CA1
0
1
+
0
0
–
1
1
0
1
e.g. capture
input of
Timer_A
CAOUT
set
CAIFG
τ ≈ 1.2 µs
820k
PCA1
47k
P1.5
VCC
P1.3
3
NTC
P1.2
0
1
Cm
0
Vss
1
0
CAREF
CARSEL
P1.4
10k
2
VCAREF
0.5xVCC
2
1
0.25xVCC
3
Figure 6–99. Voltage Measurement
On-Chip Peripherals
6-363
Was this manual useful for you? yes no
Thank you for your participation!

* Your assessment is very important for improving the work of artificial intelligence, which forms the content of this project

Download PDF

advertising